repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/radio_controller_v1_21_a/hdl/vhdl/radio_controller.vhd | 4 | 46158 | ------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: radio_controller.vhd
-- Version: 1.20.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Feb 06 13:11:09 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_00_a;
use plbv46_slave_single_v1_00_a.plbv46_slave_single;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
controller_logic_clk : out std_logic;
spi_clk : out std_logic;
data_out : out std_logic;
radio1_cs : out std_logic;
radio2_cs : out std_logic;
radio3_cs : out std_logic;
radio4_cs : out std_logic;
dac1_cs : out std_logic;
dac2_cs : out std_logic;
dac3_cs : out std_logic;
dac4_cs : out std_logic;
radio1_interpfiltbypass : out std_logic;
radio1_decfiltbypass : out std_logic;
radio1_SHDN : out std_logic;
radio1_TxEn : out std_logic;
radio1_RxEn : out std_logic;
radio1_RxHP : out std_logic;
radio1_LD : in std_logic;
radio1_24PA : out std_logic;
radio1_5PA : out std_logic;
radio1_ANTSW : out std_logic_vector(0 to 1);
radio1_LED : out std_logic_vector(0 to 2);
radio1_ADC_RX_DCS : out std_logic;
radio1_ADC_RX_DFS : out std_logic;
radio1_ADC_RX_OTRA : in std_logic;
radio1_ADC_RX_OTRB : in std_logic;
radio1_ADC_RX_PWDNA : out std_logic;
radio1_ADC_RX_PWDNB : out std_logic;
radio1_DIPSW : in std_logic_vector(0 to 3);
radio1_RSSI_ADC_CLAMP : out std_logic;
radio1_RSSI_ADC_HIZ : out std_logic;
radio1_RSSI_ADC_OTR : in std_logic;
radio1_RSSI_ADC_SLEEP : out std_logic;
radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio1_TX_DAC_PLL_LOCK : in std_logic;
radio1_TX_DAC_RESET : out std_logic;
radio1_SHDN_external : in std_logic;
radio1_TxEn_external : in std_logic;
radio1_RxEn_external : in std_logic;
radio1_RxHP_external : in std_logic;
radio1_TxGain : out std_logic_vector(0 to 5);
radio1_TxStart : out std_logic;
radio2_interpfiltbypass : out std_logic;
radio2_decfiltbypass : out std_logic;
radio2_SHDN : out std_logic;
radio2_TxEn : out std_logic;
radio2_RxEn : out std_logic;
radio2_RxHP : out std_logic;
radio2_LD : in std_logic;
radio2_24PA : out std_logic;
radio2_5PA : out std_logic;
radio2_ANTSW : out std_logic_vector(0 to 1);
radio2_LED : out std_logic_vector(0 to 2);
radio2_ADC_RX_DCS : out std_logic;
radio2_ADC_RX_DFS : out std_logic;
radio2_ADC_RX_OTRA : in std_logic;
radio2_ADC_RX_OTRB : in std_logic;
radio2_ADC_RX_PWDNA : out std_logic;
radio2_ADC_RX_PWDNB : out std_logic;
radio2_DIPSW : in std_logic_vector(0 to 3);
radio2_RSSI_ADC_CLAMP : out std_logic;
radio2_RSSI_ADC_HIZ : out std_logic;
radio2_RSSI_ADC_OTR : in std_logic;
radio2_RSSI_ADC_SLEEP : out std_logic;
radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio2_TX_DAC_PLL_LOCK : in std_logic;
radio2_TX_DAC_RESET : out std_logic;
radio2_SHDN_external : in std_logic;
radio2_TxEn_external : in std_logic;
radio2_RxEn_external : in std_logic;
radio2_RxHP_external : in std_logic;
radio2_TxGain : out std_logic_vector(0 to 5);
radio2_TxStart : out std_logic;
radio3_interpfiltbypass : out std_logic;
radio3_decfiltbypass : out std_logic;
radio3_SHDN : out std_logic;
radio3_TxEn : out std_logic;
radio3_RxEn : out std_logic;
radio3_RxHP : out std_logic;
radio3_LD : in std_logic;
radio3_24PA : out std_logic;
radio3_5PA : out std_logic;
radio3_ANTSW : out std_logic_vector(0 to 1);
radio3_LED : out std_logic_vector(0 to 2);
radio3_ADC_RX_DCS : out std_logic;
radio3_ADC_RX_DFS : out std_logic;
radio3_ADC_RX_OTRA : in std_logic;
radio3_ADC_RX_OTRB : in std_logic;
radio3_ADC_RX_PWDNA : out std_logic;
radio3_ADC_RX_PWDNB : out std_logic;
radio3_DIPSW : in std_logic_vector(0 to 3);
radio3_RSSI_ADC_CLAMP : out std_logic;
radio3_RSSI_ADC_HIZ : out std_logic;
radio3_RSSI_ADC_OTR : in std_logic;
radio3_RSSI_ADC_SLEEP : out std_logic;
radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio3_TX_DAC_PLL_LOCK : in std_logic;
radio3_TX_DAC_RESET : out std_logic;
radio3_SHDN_external : in std_logic;
radio3_TxEn_external : in std_logic;
radio3_RxEn_external : in std_logic;
radio3_RxHP_external : in std_logic;
radio3_TxGain : out std_logic_vector(0 to 5);
radio3_TxStart : out std_logic;
radio4_interpfiltbypass : out std_logic;
radio4_decfiltbypass : out std_logic;
radio4_SHDN : out std_logic;
radio4_TxEn : out std_logic;
radio4_RxEn : out std_logic;
radio4_RxHP : out std_logic;
radio4_LD : in std_logic;
radio4_24PA : out std_logic;
radio4_5PA : out std_logic;
radio4_ANTSW : out std_logic_vector(0 to 1);
radio4_LED : out std_logic_vector(0 to 2);
radio4_ADC_RX_DCS : out std_logic;
radio4_ADC_RX_DFS : out std_logic;
radio4_ADC_RX_OTRA : in std_logic;
radio4_ADC_RX_OTRB : in std_logic;
radio4_ADC_RX_PWDNA : out std_logic;
radio4_ADC_RX_PWDNB : out std_logic;
radio4_DIPSW : in std_logic_vector(0 to 3);
radio4_RSSI_ADC_CLAMP : out std_logic;
radio4_RSSI_ADC_HIZ : out std_logic;
radio4_RSSI_ADC_OTR : in std_logic;
radio4_RSSI_ADC_SLEEP : out std_logic;
radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio4_TX_DAC_PLL_LOCK : in std_logic;
radio4_TX_DAC_RESET : out std_logic;
radio4_SHDN_external : in std_logic;
radio4_TxEn_external : in std_logic;
radio4_RxEn_external : in std_logic;
radio4_RxHP_external : in std_logic;
radio4_TxGain : out std_logic_vector(0 to 5);
radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 17;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 17
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
controller_logic_clk : out std_logic;
spi_clk : out std_logic;
data_out : out std_logic;
Radio1_cs : out std_logic;
Radio2_cs : out std_logic;
Radio3_cs : out std_logic;
Radio4_cs : out std_logic;
Dac1_cs : out std_logic;
Dac2_cs : out std_logic;
Dac3_cs : out std_logic;
Dac4_cs : out std_logic;
Radio1_interpfiltbypass : out std_logic;
Radio1_decfiltbypass : out std_logic;
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio1_ADC_RX_DCS : out std_logic;
Radio1_ADC_RX_DFS : out std_logic;
Radio1_ADC_RX_OTRA : in std_logic;
Radio1_ADC_RX_OTRB : in std_logic;
Radio1_ADC_RX_PWDNA : out std_logic;
Radio1_ADC_RX_PWDNB : out std_logic;
Radio1_DIPSW : in std_logic_vector(0 to 3);
Radio1_RSSI_ADC_CLAMP : out std_logic;
Radio1_RSSI_ADC_HIZ : out std_logic;
Radio1_RSSI_ADC_OTR : in std_logic;
Radio1_RSSI_ADC_SLEEP : out std_logic;
Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio1_TX_DAC_PLL_LOCK : in std_logic;
Radio1_TX_DAC_RESET : out std_logic;
Radio1_SHDN_external : in std_logic;
Radio1_TxEn_external : in std_logic;
Radio1_RxEn_external : in std_logic;
Radio1_RxHP_external : in std_logic;
Radio1_TxGain : out std_logic_vector(0 to 5);
Radio1_TxStart : out std_logic;
Radio2_interpfiltbypass : out std_logic;
Radio2_decfiltbypass : out std_logic;
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio2_ADC_RX_DCS : out std_logic;
Radio2_ADC_RX_DFS : out std_logic;
Radio2_ADC_RX_OTRA : in std_logic;
Radio2_ADC_RX_OTRB : in std_logic;
Radio2_ADC_RX_PWDNA : out std_logic;
Radio2_ADC_RX_PWDNB : out std_logic;
Radio2_DIPSW : in std_logic_vector(0 to 3);
Radio2_RSSI_ADC_CLAMP : out std_logic;
Radio2_RSSI_ADC_HIZ : out std_logic;
Radio2_RSSI_ADC_OTR : in std_logic;
Radio2_RSSI_ADC_SLEEP : out std_logic;
Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio2_TX_DAC_PLL_LOCK : in std_logic;
Radio2_TX_DAC_RESET : out std_logic;
Radio2_SHDN_external : in std_logic;
Radio2_TxEn_external : in std_logic;
Radio2_RxEn_external : in std_logic;
Radio2_RxHP_external : in std_logic;
Radio2_TxGain : out std_logic_vector(0 to 5);
Radio2_TxStart : out std_logic;
Radio3_interpfiltbypass : out std_logic;
Radio3_decfiltbypass : out std_logic;
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio3_ADC_RX_DCS : out std_logic;
Radio3_ADC_RX_DFS : out std_logic;
Radio3_ADC_RX_OTRA : in std_logic;
Radio3_ADC_RX_OTRB : in std_logic;
Radio3_ADC_RX_PWDNA : out std_logic;
Radio3_ADC_RX_PWDNB : out std_logic;
Radio3_DIPSW : in std_logic_vector(0 to 3);
Radio3_RSSI_ADC_CLAMP : out std_logic;
Radio3_RSSI_ADC_HIZ : out std_logic;
Radio3_RSSI_ADC_OTR : in std_logic;
Radio3_RSSI_ADC_SLEEP : out std_logic;
Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio3_TX_DAC_PLL_LOCK : in std_logic;
Radio3_TX_DAC_RESET : out std_logic;
Radio3_SHDN_external : in std_logic;
Radio3_TxEn_external : in std_logic;
Radio3_RxEn_external : in std_logic;
Radio3_RxHP_external : in std_logic;
Radio3_TxGain : out std_logic_vector(0 to 5);
Radio3_TxStart : out std_logic;
Radio4_interpfiltbypass : out std_logic;
Radio4_decfiltbypass : out std_logic;
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
Radio4_ADC_RX_DCS : out std_logic;
Radio4_ADC_RX_DFS : out std_logic;
Radio4_ADC_RX_OTRA : in std_logic;
Radio4_ADC_RX_OTRB : in std_logic;
Radio4_ADC_RX_PWDNA : out std_logic;
Radio4_ADC_RX_PWDNB : out std_logic;
Radio4_DIPSW : in std_logic_vector(0 to 3);
Radio4_RSSI_ADC_CLAMP : out std_logic;
Radio4_RSSI_ADC_HIZ : out std_logic;
Radio4_RSSI_ADC_OTR : in std_logic;
Radio4_RSSI_ADC_SLEEP : out std_logic;
Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio4_TX_DAC_PLL_LOCK : in std_logic;
Radio4_TX_DAC_RESET : out std_logic;
Radio4_SHDN_external : in std_logic;
Radio4_TxEn_external : in std_logic;
Radio4_RxEn_external : in std_logic;
Radio4_RxHP_external : in std_logic;
Radio4_TxGain : out std_logic_vector(0 to 5);
Radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
controller_logic_clk => controller_logic_clk,
spi_clk => spi_clk,
data_out => data_out,
Radio1_cs => radio1_cs,
Radio2_cs => radio2_cs,
Radio3_cs => radio3_cs,
Radio4_cs => radio4_cs,
Dac1_cs => dac1_cs,
Dac2_cs => dac2_cs,
Dac3_cs => dac3_cs,
Dac4_cs => dac4_cs,
Radio1_interpfiltbypass => radio1_interpfiltbypass,
Radio1_decfiltbypass => radio1_decfiltbypass,
Radio1_SHDN => radio1_SHDN,
Radio1_TxEn => radio1_TxEn,
Radio1_RxEn => radio1_RxEn,
Radio1_RxHP => radio1_RxHP,
Radio1_LD => radio1_LD,
Radio1_24PA => radio1_24PA,
Radio1_5PA => radio1_5PA,
Radio1_ANTSW => radio1_ANTSW,
Radio1_LED => radio1_LED,
Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
Radio1_DIPSW => radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
Radio1_SHDN_external => radio1_SHDN_external,
Radio1_TxEn_external => radio1_TxEn_external,
Radio1_RxEn_external => radio1_RxEn_external,
Radio1_RxHP_external => radio1_RxHP_external,
Radio1_TxGain => radio1_TxGain,
Radio1_TxStart => radio1_TxStart,
Radio2_interpfiltbypass => radio2_interpfiltbypass,
Radio2_decfiltbypass => radio2_decfiltbypass,
Radio2_SHDN => radio2_SHDN,
Radio2_TxEn => radio2_TxEn,
Radio2_RxEn => radio2_RxEn,
Radio2_RxHP => radio2_RxHP,
Radio2_LD => radio2_LD,
Radio2_24PA => radio2_24PA,
Radio2_5PA => radio2_5PA,
Radio2_ANTSW => radio2_ANTSW,
Radio2_LED => radio2_LED,
Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
Radio2_DIPSW => radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
Radio2_SHDN_external => radio2_SHDN_external,
Radio2_TxEn_external => radio2_TxEn_external,
Radio2_RxEn_external => radio2_RxEn_external,
Radio2_RxHP_external => radio2_RxHP_external,
Radio2_TxGain => radio2_TxGain,
Radio2_TxStart => radio2_TxStart,
Radio3_interpfiltbypass => radio3_interpfiltbypass,
Radio3_decfiltbypass => radio3_decfiltbypass,
Radio3_SHDN => radio3_SHDN,
Radio3_TxEn => radio3_TxEn,
Radio3_RxEn => radio3_RxEn,
Radio3_RxHP => radio3_RxHP,
Radio3_LD => radio3_LD,
Radio3_24PA => radio3_24PA,
Radio3_5PA => radio3_5PA,
Radio3_ANTSW => radio3_ANTSW,
Radio3_LED => radio3_LED,
Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
Radio3_DIPSW => radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
Radio3_SHDN_external => radio3_SHDN_external,
Radio3_TxEn_external => radio3_TxEn_external,
Radio3_RxEn_external => radio3_RxEn_external,
Radio3_RxHP_external => radio3_RxHP_external,
Radio3_TxGain => radio3_TxGain,
Radio3_TxStart => radio3_TxStart,
Radio4_interpfiltbypass => radio4_interpfiltbypass,
Radio4_decfiltbypass => radio4_decfiltbypass,
Radio4_SHDN => radio4_SHDN,
Radio4_TxEn => radio4_TxEn,
Radio4_RxEn => radio4_RxEn,
Radio4_RxHP => radio4_RxHP,
Radio4_LD => radio4_LD,
Radio4_24PA => radio4_24PA,
Radio4_5PA => radio4_5PA,
Radio4_ANTSW => radio4_ANTSW,
Radio4_LED => radio4_LED,
Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
Radio4_DIPSW => radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
Radio4_SHDN_external => radio4_SHDN_external,
Radio4_TxEn_external => radio4_TxEn_external,
Radio4_RxEn_external => radio4_RxEn_external,
Radio4_RxHP_external => radio4_RxHP_external,
Radio4_TxGain => radio4_TxGain,
Radio4_TxStart => radio4_TxStart,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/edidram/simulation/edidram_synth.vhd | 3 | 8872 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: edidram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY edidram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE edidram_synth_ARCH OF edidram_synth IS
COMPONENT edidram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: edidram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/jpeg_encoder/design/DCT1D.vhd | 3 | 14044 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal ramwe_s : STD_LOGIC:='0';
signal wmemsel_reg : STD_LOGIC:='0';
signal stage2_reg : STD_LOGIC:='0';
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0):=(others=>'1');
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal even_not_odd : std_logic:='0';
signal even_not_odd_d1 : std_logic:='0';
signal even_not_odd_d2 : std_logic:='0';
signal even_not_odd_d3 : std_logic:='0';
signal ramwe_d1 : STD_LOGIC:='0';
signal ramwe_d2 : STD_LOGIC:='0';
signal ramwe_d3 : STD_LOGIC:='0';
signal ramwe_d4 : STD_LOGIC:='0';
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal wmemsel_d1 : STD_LOGIC:='0';
signal wmemsel_d2 : STD_LOGIC:='0';
signal wmemsel_d3 : STD_LOGIC:='0';
signal wmemsel_d4 : STD_LOGIC:='0';
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
begin
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif rising_edge(clk) then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/patternClk/example_design/patternClk_exdes.vhd | 3 | 5769 | -- file: patternClk_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity patternClk_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end patternClk_exdes;
architecture xilinx of patternClk_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
-- Need to buffer input clocks that aren't already buffered
signal clk_in1_buf : std_logic;
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component patternClk is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Insert BUFGs on all input clocks that don't already have them
----------------------------------------------------------------
clkin1_buf : BUFG
port map
(O => clk_in1_buf,
I => CLK_IN1);
-- Instantiation of the clocking network
----------------------------------------
clknetwork : patternClk
port map
(-- Clock in ports
CLK_IN1 => clk_in1_buf,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clkout1_buf : BUFG
port map
(O => clk,
I => clk_int);
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/rawUVCfifo/example_design/rawUVCfifo_exdes.vhd | 3 | 5723 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity rawUVCfifo_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(24-1 DOWNTO 0);
DOUT : OUT std_logic_vector(24-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end rawUVCfifo_exdes;
architecture xilinx of rawUVCfifo_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component rawUVCfifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(24-1 DOWNTO 0);
DOUT : OUT std_logic_vector(24-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : rawUVCfifo
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/cdcfifo/simulation/cdcfifo_pkg.vhd | 3 | 11447 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT cdcfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END cdcfifo_pkg;
PACKAGE BODY cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END cdcfifo_pkg;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/bytefifo/simulation/bytefifo_pkg.vhd | 3 | 11620 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE bytefifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT bytefifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT bytefifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT bytefifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT bytefifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT bytefifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT bytefifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END bytefifo_pkg;
PACKAGE BODY bytefifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END bytefifo_pkg;
| bsd-2-clause |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_00_a/hdl/vhdl/radio_controller.vhd | 2 | 23552 | ------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY **
-- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR **
-- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND **
-- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES **
-- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: radio_controller.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Fri Jun 24 10:11:25 2005 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_a;
use opb_ipif_v3_01_a.all;
library radio_controller_v1_00_a;
use radio_controller_v1_00_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
radio1shdn : out std_logic;
radio2shdn : out std_logic;
radio3shdn : out std_logic;
radio4shdn : out std_logic;
radio1txen : out std_logic;
radio2txen : out std_logic;
radio3txen : out std_logic;
radio4txen : out std_logic;
radio1rxen : out std_logic;
radio2rxen : out std_logic;
radio3rxen : out std_logic;
radio4rxen : out std_logic;
radio1ld : in std_logic;
radio2ld : in std_logic;
radio3ld : in std_logic;
radio4ld : in std_logic;
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_CE : integer := 1;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Radio1SHDN : out std_logic;
Radio2SHDN : out std_logic;
Radio3SHDN : out std_logic;
Radio4SHDN : out std_logic;
Radio1TxEn : out std_logic;
Radio2TxEn : out std_logic;
Radio3TxEn : out std_logic;
Radio4TxEn : out std_logic;
Radio1RxEn : out std_logic;
Radio2RxEn : out std_logic;
Radio3RxEn : out std_logic;
Radio4RxEn : out std_logic;
Radio1LD : in std_logic;
Radio2LD : in std_logic;
Radio3LD : in std_logic;
Radio4LD : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_a.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Radio1SHDN => radio1shdn,
Radio2SHDN => radio2shdn,
Radio3SHDN => radio3shdn,
Radio4SHDN => radio4shdn,
Radio1TxEn => radio1txen,
Radio2TxEn => radio2txen,
Radio3TxEn => radio3txen,
Radio4TxEn => radio4txen,
Radio1RxEn => radio1rxen,
Radio2RxEn => radio2rxen,
Radio3RxEn => radio3rxen,
Radio4RxEn => radio4rxen,
Radio1LD => radio1ld,
Radio2LD => radio2ld,
Radio3LD => radio3ld,
Radio4LD => radio4ld,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/bytefifoFPGA/simulation/bytefifoFPGA_synth.vhd | 3 | 11634 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifoFPGA_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.bytefifoFPGA_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bytefifoFPGA_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF bytefifoFPGA_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL overflow : STD_LOGIC;
SIGNAL underflow : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: bytefifoFPGA_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: bytefifoFPGA_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: bytefifoFPGA_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 15,
C_RD_PNTR_WIDTH => 15,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
bytefifoFPGA_inst : bytefifoFPGA_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
OVERFLOW => overflow,
UNDERFLOW => underflow,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/jpeg_encoder/design/AC_CR_ROM.vhd | 3 | 35186 | -------------------------------------------------------------------------------
-- File Name : AC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_CR_ROM
--
-- Content : AC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090329: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity AC_CR_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLC_AC_size : out unsigned(4 downto 0);
VLC_AC : out unsigned(15 downto 0)
);
end entity AC_CR_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of AC_CR_ROM is
signal rom_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rom_addr <= runlength & VLI_size;
-------------------------------------------------------------------
-- AC-ROM
-------------------------------------------------------------------
p_AC_CR_ROM : process(CLK, RST)
begin
if RST = '1' then
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
elsif CLK'event and CLK = '1' then
case runlength is
when X"0" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("00", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("01", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length);
VLC_AC <= resize("100", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1010", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110110", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110100", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"1" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11110110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110101", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110110", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110101", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001001", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001010", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001011", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"2" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"3" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111000", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"4" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"5" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"6" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"7" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"8" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111000", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111001", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111011", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111100", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111101", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111110", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111111", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"9" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110111", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000010", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000011", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"A" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001010", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001100", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001101", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001110", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001111", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010000", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010001", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"B" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010010", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010011", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010101", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010110", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010111", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011000", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011001", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011010", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"C" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011011", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011100", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011101", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011110", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011111", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100001", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100010", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100011", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"D" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100100", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100111", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101001", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101010", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101011", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101100", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"E" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(14, VLC_AC_size'length);
VLC_AC <= resize("11111111100000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101101", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"F" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111010", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when others =>
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/image_selector_fifo/example_design/image_selector_fifo_exdes.vhd | 3 | 5618 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity image_selector_fifo_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(24-1 DOWNTO 0);
DOUT : OUT std_logic_vector(24-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end image_selector_fifo_exdes;
architecture xilinx of image_selector_fifo_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component image_selector_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(24-1 DOWNTO 0);
DOUT : OUT std_logic_vector(24-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : image_selector_fifo
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-2-clause |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/linkport_v1_00_a/hdl/vhdl/global_logic.vhd | 4 | 8982 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/16 00:32:43 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: global_logic_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- GLOBAL_LOGIC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: The GLOBAL_LOGIC module handles channel bonding, channel
-- verification, channel error manangement and idle generation.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity GLOBAL_LOGIC is
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
LANE_UP : in std_logic;
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic
);
end GLOBAL_LOGIC;
architecture MAPPED of GLOBAL_LOGIC is
-- External Register Declarations --
signal EN_CHAN_SYNC_Buffer : std_logic;
signal GEN_A_Buffer : std_logic;
signal GEN_K_Buffer : std_logic_vector(0 to 1);
signal GEN_R_Buffer : std_logic_vector(0 to 1);
signal GEN_V_Buffer : std_logic_vector(0 to 1);
signal RESET_LANES_Buffer : std_logic;
signal CHANNEL_UP_Buffer : std_logic;
signal START_RX_Buffer : std_logic;
signal CHANNEL_SOFT_ERROR_Buffer : std_logic;
signal CHANNEL_HARD_ERROR_Buffer : std_logic;
-- Wire Declarations --
signal gen_ver_i : std_logic;
signal reset_channel_i : std_logic;
signal did_ver_i : std_logic;
-- Component Declarations --
component CHANNEL_INIT_SM
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
-- Idle and Verification Sequence Generator Interface
DID_VER : in std_logic;
GEN_VER : out std_logic;
-- Channel Init State Machine Interface
RESET_CHANNEL : in std_logic
);
end component;
component IDLE_AND_VER_GEN
port (
-- Channel Init SM Interface
GEN_VER : in std_logic;
DID_VER : out std_logic;
-- Aurora Lane Interface
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
-- System Interface
RESET : in std_logic;
USER_CLK : in std_logic
);
end component;
component CHANNEL_ERROR_DETECT
port (
-- Aurora Lane Interface
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
LANE_UP : in std_logic;
-- System Interface
USER_CLK : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic;
-- Channel Init SM Interface
RESET_CHANNEL : out std_logic
);
end component;
begin
EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
GEN_A <= GEN_A_Buffer;
GEN_K <= GEN_K_Buffer;
GEN_R <= GEN_R_Buffer;
GEN_V <= GEN_V_Buffer;
RESET_LANES <= RESET_LANES_Buffer;
CHANNEL_UP <= CHANNEL_UP_Buffer;
START_RX <= START_RX_Buffer;
CHANNEL_SOFT_ERROR <= CHANNEL_SOFT_ERROR_Buffer;
CHANNEL_HARD_ERROR <= CHANNEL_HARD_ERROR_Buffer;
-- Main Body of Code --
-- State Machine for channel bonding and verification.
channel_init_sm_i : CHANNEL_INIT_SM
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
CH_BOND_DONE => CH_BOND_DONE,
EN_CHAN_SYNC => EN_CHAN_SYNC_Buffer,
-- Aurora Lane Interface
CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
GOT_A => GOT_A,
GOT_V => GOT_V,
RESET_LANES => RESET_LANES_Buffer,
-- System Interface
USER_CLK => USER_CLK,
RESET => RESET,
START_RX => START_RX_Buffer,
CHANNEL_UP => CHANNEL_UP_Buffer,
-- Idle and Verification Sequence Generator Interface
DID_VER => did_ver_i,
GEN_VER => gen_ver_i,
-- Channel Error Management Module Interface
RESET_CHANNEL => reset_channel_i
);
-- Idle and verification sequence generator module.
idle_and_ver_gen_i : IDLE_AND_VER_GEN
port map (
-- Channel Init SM Interface
GEN_VER => gen_ver_i,
DID_VER => did_ver_i,
-- Aurora Lane Interface
GEN_A => GEN_A_Buffer,
GEN_K => GEN_K_Buffer,
GEN_R => GEN_R_Buffer,
GEN_V => GEN_V_Buffer,
-- System Interface
RESET => RESET,
USER_CLK => USER_CLK
);
-- Channel Error Management module.
channel_error_detect_i : CHANNEL_ERROR_DETECT
port map (
-- Aurora Lane Interface
SOFT_ERROR => SOFT_ERROR,
HARD_ERROR => HARD_ERROR,
LANE_UP => LANE_UP,
-- System Interface
USER_CLK => USER_CLK,
POWER_DOWN => POWER_DOWN,
CHANNEL_SOFT_ERROR => CHANNEL_SOFT_ERROR_Buffer,
CHANNEL_HARD_ERROR => CHANNEL_HARD_ERROR_Buffer,
-- Channel Init State Machine Interface
RESET_CHANNEL => reset_channel_i
);
end MAPPED;
| bsd-2-clause |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/warp_timer_plbw_v1_00_a/hdl/vhdl/warp_timer.vhd | 4 | 209538 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e IS
port (
A: IN std_logic_VECTOR(32 downto 0);
B: IN std_logic_VECTOR(32 downto 0);
S: OUT std_logic_VECTOR(32 downto 0));
END adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e;
ARCHITECTURE adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e_a OF adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e
port (
A: IN std_logic_VECTOR(32 downto 0);
B: IN std_logic_VECTOR(32 downto 0);
S: OUT std_logic_VECTOR(32 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 0,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 32,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 0,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 1,
c_has_aclr => 0,
c_out_width => 33,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 33,
c_a_width => 33,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_b57302a6bcbb6876.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_b57302a6bcbb6876. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_b57302a6bcbb6876 IS
port (
Q: OUT std_logic_VECTOR(31 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_b57302a6bcbb6876;
ARCHITECTURE binary_counter_virtex2p_7_0_b57302a6bcbb6876_a OF binary_counter_virtex2p_7_0_b57302a6bcbb6876 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876
port (
Q: OUT std_logic_VECTOR(31 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 32,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_b57302a6bcbb6876_a;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
package clock_pkg is
-- synopsys translate_off
signal int_clk : std_logic;
-- synopsys translate_on
end clock_pkg;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_b389f41afb is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((20 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_b389f41afb;
architecture behavior of mcode_block_b389f41afb is
signal plbrst_2_20: unsigned((1 - 1) downto 0);
signal plbabus_2_28: unsigned((32 - 1) downto 0);
signal plbpavalid_2_37: unsigned((1 - 1) downto 0);
signal plbrnw_2_49: unsigned((1 - 1) downto 0);
signal plbwrdbus_2_57: unsigned((32 - 1) downto 0);
signal rddata_2_68: unsigned((32 - 1) downto 0);
signal addrpref_2_76: unsigned((20 - 1) downto 0);
signal plbrstreg_13_24_next: boolean;
signal plbrstreg_13_24: boolean := false;
signal plbabusreg_14_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_14_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_15_28_next: boolean;
signal plbpavalidreg_15_28: boolean := false;
signal plbrnwreg_16_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_16_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_17_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_17_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_29_23_next: boolean;
signal avalidreg_29_23: boolean := false;
signal ps1reg_40_20_next: boolean;
signal ps1reg_40_20: boolean := false;
signal psreg_48_19_next: boolean;
signal psreg_48_19: boolean := false;
type array_type_rdcompdelay_59_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25: array_type_rdcompdelay_59_25 := (
"0",
"0",
"0");
signal rdcompdelay_59_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_push_front_pop_back_en: std_logic;
signal rdcompreg_63_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_63_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_67_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_67_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_71_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_71_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_85_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_85_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_21_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_22_1_slice: unsigned((8 - 1) downto 0);
signal addrpref_in_33_1_slice: unsigned((20 - 1) downto 0);
signal rel_34_4: boolean;
signal ps1_join_34_1: boolean;
signal ps_43_1_bit: boolean;
signal bitnot_50_49: boolean;
signal bitnot_50_73: boolean;
signal bit_50_49: boolean;
signal addrack_50_1_convert: unsigned((1 - 1) downto 0);
signal bit_56_43: unsigned((1 - 1) downto 0);
signal bitnot_73_35: unsigned((1 - 1) downto 0);
signal wrdackreg_73_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_77_1_bit: unsigned((1 - 1) downto 0);
signal rel_79_4: boolean;
signal rddbus1_join_79_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_98_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_13_24_next_x_000000: boolean;
signal plbpavalidreg_15_28_next_x_000000: boolean;
begin
plbrst_2_20 <= std_logic_vector_to_unsigned(plbrst);
plbabus_2_28 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_2_37 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_2_49 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_2_57 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_2_68 <= std_logic_vector_to_unsigned(rddata);
addrpref_2_76 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_13_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_13_24 <= plbrstreg_13_24_next;
end if;
end if;
end process proc_plbrstreg_13_24;
proc_plbabusreg_14_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_14_25 <= plbabusreg_14_25_next;
end if;
end if;
end process proc_plbabusreg_14_25;
proc_plbpavalidreg_15_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_15_28 <= plbpavalidreg_15_28_next;
end if;
end if;
end process proc_plbpavalidreg_15_28;
proc_plbrnwreg_16_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_16_24 <= plbrnwreg_16_24_next;
end if;
end if;
end process proc_plbrnwreg_16_24;
proc_plbwrdbusreg_17_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_17_27 <= plbwrdbusreg_17_27_next;
end if;
end if;
end process proc_plbwrdbusreg_17_27;
proc_avalidreg_29_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_29_23 <= avalidreg_29_23_next;
end if;
end if;
end process proc_avalidreg_29_23;
proc_ps1reg_40_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_40_20 <= ps1reg_40_20_next;
end if;
end if;
end process proc_ps1reg_40_20;
proc_psreg_48_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_48_19 <= psreg_48_19_next;
end if;
end if;
end process proc_psreg_48_19;
rdcompdelay_59_25_back <= rdcompdelay_59_25(2);
proc_rdcompdelay_59_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_59_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_59_25(i) <= rdcompdelay_59_25(i-1);
end loop;
rdcompdelay_59_25(0) <= rdcompdelay_59_25_front_din;
end if;
end if;
end process proc_rdcompdelay_59_25;
proc_rdcompreg_63_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_63_23 <= rdcompreg_63_23_next;
end if;
end if;
end process proc_rdcompreg_63_23;
proc_rddackreg_67_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_67_23 <= rddackreg_67_23_next;
end if;
end if;
end process proc_rddackreg_67_23;
proc_wrdackreg_71_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_71_23 <= wrdackreg_71_23_next;
end if;
end if;
end process proc_wrdackreg_71_23;
proc_rddbusreg_85_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_85_23 <= rddbusreg_85_23_next;
end if;
end if;
end process proc_rddbusreg_85_23;
bankaddr_21_1_slice <= u2u_slice(plbabusreg_14_25, 11, 10);
linearaddr_22_1_slice <= u2u_slice(plbabusreg_14_25, 9, 2);
addrpref_in_33_1_slice <= u2u_slice(plbabusreg_14_25, 31, 12);
rel_34_4 <= addrpref_in_33_1_slice = addrpref_2_76;
proc_if_34_1: process (rel_34_4)
is
begin
if rel_34_4 then
ps1_join_34_1 <= true;
else
ps1_join_34_1 <= false;
end if;
end process proc_if_34_1;
ps_43_1_bit <= ((boolean_to_vector(ps1_join_34_1) and boolean_to_vector(plbpavalidreg_15_28)) = "1");
bitnot_50_49 <= ((not boolean_to_vector(plbrstreg_13_24)) = "1");
bitnot_50_73 <= ((not boolean_to_vector(psreg_48_19)) = "1");
bit_50_49 <= ((boolean_to_vector(bitnot_50_49) and boolean_to_vector(ps_43_1_bit) and boolean_to_vector(bitnot_50_73)) = "1");
addrack_50_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_50_49)), 0, 1, 0);
bit_56_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_16_24));
bitnot_73_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_16_24));
wrdackreg_73_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(bitnot_73_35));
rdsel_77_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_59_25_back) or unsigned_to_std_logic_vector(rdcompreg_63_23));
rel_79_4 <= rdsel_77_1_bit = std_logic_vector_to_unsigned("1");
proc_if_79_1: process (rddata_2_68, rel_79_4)
is
begin
if rel_79_4 then
rddbus1_join_79_1 <= rddata_2_68;
else
rddbus1_join_79_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_79_1;
plbwrdbusreg_98_1_slice <= u2u_slice(plbwrdbus_2_57, 31, 0);
plbrstreg_13_24_next_x_000000 <= (plbrst_2_20 /= "0");
plbrstreg_13_24_next <= plbrstreg_13_24_next_x_000000;
plbabusreg_14_25_next <= plbabus_2_28;
plbpavalidreg_15_28_next_x_000000 <= (plbpavalid_2_37 /= "0");
plbpavalidreg_15_28_next <= plbpavalidreg_15_28_next_x_000000;
plbrnwreg_16_24_next <= plbrnw_2_49;
plbwrdbusreg_17_27_next <= plbwrdbusreg_98_1_slice;
avalidreg_29_23_next <= plbpavalidreg_15_28;
ps1reg_40_20_next <= ps1_join_34_1;
psreg_48_19_next <= ps_43_1_bit;
rdcompdelay_59_25_front_din <= bit_56_43;
rdcompdelay_59_25_push_front_pop_back_en <= '1';
rdcompreg_63_23_next <= rdcompdelay_59_25_back;
rddackreg_67_23_next <= rdcompreg_63_23;
wrdackreg_71_23_next <= wrdackreg_73_1_bit;
rddbusreg_85_23_next <= rddbus1_join_79_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_17_27);
addrack <= unsigned_to_std_logic_vector(addrack_50_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_63_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_71_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_21_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_16_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_67_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_85_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_22_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_b59e0d51fc is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((8 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
sm_timer0_timeleft : in std_logic_vector((32 - 1) downto 0);
sm_timer1_timeleft : in std_logic_vector((32 - 1) downto 0);
sm_timer2_timeleft : in std_logic_vector((32 - 1) downto 0);
sm_timer3_timeleft : in std_logic_vector((32 - 1) downto 0);
sm_timer_control_r : in std_logic_vector((32 - 1) downto 0);
sm_timer_status : in std_logic_vector((32 - 1) downto 0);
sm_timer0_countto : in std_logic_vector((32 - 1) downto 0);
sm_timer1_countto : in std_logic_vector((32 - 1) downto 0);
sm_timer2_countto : in std_logic_vector((32 - 1) downto 0);
sm_timer3_countto : in std_logic_vector((32 - 1) downto 0);
sm_timer_control_w : in std_logic_vector((32 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
sm_timer0_countto_din : out std_logic_vector((32 - 1) downto 0);
sm_timer0_countto_en : out std_logic_vector((1 - 1) downto 0);
sm_timer1_countto_din : out std_logic_vector((32 - 1) downto 0);
sm_timer1_countto_en : out std_logic_vector((1 - 1) downto 0);
sm_timer2_countto_din : out std_logic_vector((32 - 1) downto 0);
sm_timer2_countto_en : out std_logic_vector((1 - 1) downto 0);
sm_timer3_countto_din : out std_logic_vector((32 - 1) downto 0);
sm_timer3_countto_en : out std_logic_vector((1 - 1) downto 0);
sm_timer_control_w_din : out std_logic_vector((32 - 1) downto 0);
sm_timer_control_w_en : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_b59e0d51fc;
architecture behavior of mcode_block_b59e0d51fc is
signal wrdbus_1_273: unsigned((32 - 1) downto 0);
signal bankaddr_1_281: unsigned((2 - 1) downto 0);
signal linearaddr_1_291: unsigned((8 - 1) downto 0);
signal rnwreg_1_303: unsigned((1 - 1) downto 0);
signal addrack_1_311: unsigned((1 - 1) downto 0);
signal sm_timer0_timeleft_1_320: unsigned((32 - 1) downto 0);
signal sm_timer1_timeleft_1_340: unsigned((32 - 1) downto 0);
signal sm_timer2_timeleft_1_360: unsigned((32 - 1) downto 0);
signal sm_timer3_timeleft_1_380: unsigned((32 - 1) downto 0);
signal sm_timer_control_r_1_400: unsigned((32 - 1) downto 0);
signal sm_timer_status_1_420: unsigned((32 - 1) downto 0);
signal sm_timer0_countto_1_437: unsigned((32 - 1) downto 0);
signal sm_timer1_countto_1_456: unsigned((32 - 1) downto 0);
signal sm_timer2_countto_1_475: unsigned((32 - 1) downto 0);
signal sm_timer3_countto_1_494: unsigned((32 - 1) downto 0);
signal sm_timer_control_w_1_513: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_47_30_next: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_47_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal read_bank_out_reg_158_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_158_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_161_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_161_26: unsigned((2 - 1) downto 0) := "00";
signal rel_50_4: boolean;
signal rel_52_8: boolean;
signal rel_54_8: boolean;
signal rel_56_8: boolean;
signal rel_58_8: boolean;
signal rel_60_8: boolean;
signal rel_62_8: boolean;
signal rel_64_8: boolean;
signal rel_66_8: boolean;
signal rel_68_8: boolean;
signal rel_70_8: boolean;
signal reg_bank_out_reg_join_50_1: unsigned((32 - 1) downto 0);
signal opcode_81_1_concat: unsigned((12 - 1) downto 0);
signal rel_102_4: boolean;
signal sm_timer0_countto_en_join_102_1: boolean;
signal rel_108_4: boolean;
signal sm_timer1_countto_en_join_108_1: boolean;
signal rel_114_4: boolean;
signal sm_timer2_countto_en_join_114_1: boolean;
signal rel_120_4: boolean;
signal sm_timer3_countto_en_join_120_1: boolean;
signal rel_126_4: boolean;
signal sm_timer_control_w_en_join_126_1: boolean;
signal slice_141_42: unsigned((32 - 1) downto 0);
signal slice_144_42: unsigned((32 - 1) downto 0);
signal slice_147_42: unsigned((32 - 1) downto 0);
signal slice_150_42: unsigned((32 - 1) downto 0);
signal slice_153_43: unsigned((32 - 1) downto 0);
signal rel_163_4: boolean;
signal rel_166_8: boolean;
signal rel_169_8: boolean;
signal rel_172_8: boolean;
signal read_bank_out_reg_join_163_1: unsigned((32 - 1) downto 0);
begin
wrdbus_1_273 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_281 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_291 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_303 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_311 <= std_logic_vector_to_unsigned(addrack);
sm_timer0_timeleft_1_320 <= std_logic_vector_to_unsigned(sm_timer0_timeleft);
sm_timer1_timeleft_1_340 <= std_logic_vector_to_unsigned(sm_timer1_timeleft);
sm_timer2_timeleft_1_360 <= std_logic_vector_to_unsigned(sm_timer2_timeleft);
sm_timer3_timeleft_1_380 <= std_logic_vector_to_unsigned(sm_timer3_timeleft);
sm_timer_control_r_1_400 <= std_logic_vector_to_unsigned(sm_timer_control_r);
sm_timer_status_1_420 <= std_logic_vector_to_unsigned(sm_timer_status);
sm_timer0_countto_1_437 <= std_logic_vector_to_unsigned(sm_timer0_countto);
sm_timer1_countto_1_456 <= std_logic_vector_to_unsigned(sm_timer1_countto);
sm_timer2_countto_1_475 <= std_logic_vector_to_unsigned(sm_timer2_countto);
sm_timer3_countto_1_494 <= std_logic_vector_to_unsigned(sm_timer3_countto);
sm_timer_control_w_1_513 <= std_logic_vector_to_unsigned(sm_timer_control_w);
proc_reg_bank_out_reg_47_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
reg_bank_out_reg_47_30 <= reg_bank_out_reg_47_30_next;
end if;
end if;
end process proc_reg_bank_out_reg_47_30;
proc_read_bank_out_reg_158_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_158_31 <= read_bank_out_reg_158_31_next;
end if;
end if;
end process proc_read_bank_out_reg_158_31;
proc_bankaddr_reg_161_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_161_26 <= bankaddr_reg_161_26_next;
end if;
end if;
end process proc_bankaddr_reg_161_26;
rel_50_4 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000101");
rel_52_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000110");
rel_54_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000111");
rel_56_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001000");
rel_58_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001001");
rel_60_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001010");
rel_62_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000000");
rel_64_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000001");
rel_66_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000010");
rel_68_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000011");
rel_70_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000100");
proc_if_50_1: process (reg_bank_out_reg_47_30, rel_50_4, rel_52_8, rel_54_8, rel_56_8, rel_58_8, rel_60_8, rel_62_8, rel_64_8, rel_66_8, rel_68_8, rel_70_8, sm_timer0_countto_1_437, sm_timer0_timeleft_1_320, sm_timer1_countto_1_456, sm_timer1_timeleft_1_340, sm_timer2_countto_1_475, sm_timer2_timeleft_1_360, sm_timer3_countto_1_494, sm_timer3_timeleft_1_380, sm_timer_control_r_1_400, sm_timer_control_w_1_513, sm_timer_status_1_420)
is
begin
if rel_50_4 then
reg_bank_out_reg_join_50_1 <= sm_timer0_timeleft_1_320;
elsif rel_52_8 then
reg_bank_out_reg_join_50_1 <= sm_timer1_timeleft_1_340;
elsif rel_54_8 then
reg_bank_out_reg_join_50_1 <= sm_timer2_timeleft_1_360;
elsif rel_56_8 then
reg_bank_out_reg_join_50_1 <= sm_timer3_timeleft_1_380;
elsif rel_58_8 then
reg_bank_out_reg_join_50_1 <= sm_timer_control_r_1_400;
elsif rel_60_8 then
reg_bank_out_reg_join_50_1 <= sm_timer_status_1_420;
elsif rel_62_8 then
reg_bank_out_reg_join_50_1 <= sm_timer0_countto_1_437;
elsif rel_64_8 then
reg_bank_out_reg_join_50_1 <= sm_timer1_countto_1_456;
elsif rel_66_8 then
reg_bank_out_reg_join_50_1 <= sm_timer2_countto_1_475;
elsif rel_68_8 then
reg_bank_out_reg_join_50_1 <= sm_timer3_countto_1_494;
elsif rel_70_8 then
reg_bank_out_reg_join_50_1 <= sm_timer_control_w_1_513;
else
reg_bank_out_reg_join_50_1 <= reg_bank_out_reg_47_30;
end if;
end process proc_if_50_1;
opcode_81_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_311) & unsigned_to_std_logic_vector(rnwreg_1_303) & unsigned_to_std_logic_vector(bankaddr_1_281) & unsigned_to_std_logic_vector(linearaddr_1_291));
rel_102_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000000");
proc_if_102_1: process (rel_102_4)
is
begin
if rel_102_4 then
sm_timer0_countto_en_join_102_1 <= true;
else
sm_timer0_countto_en_join_102_1 <= false;
end if;
end process proc_if_102_1;
rel_108_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000001");
proc_if_108_1: process (rel_108_4)
is
begin
if rel_108_4 then
sm_timer1_countto_en_join_108_1 <= true;
else
sm_timer1_countto_en_join_108_1 <= false;
end if;
end process proc_if_108_1;
rel_114_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000010");
proc_if_114_1: process (rel_114_4)
is
begin
if rel_114_4 then
sm_timer2_countto_en_join_114_1 <= true;
else
sm_timer2_countto_en_join_114_1 <= false;
end if;
end process proc_if_114_1;
rel_120_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000011");
proc_if_120_1: process (rel_120_4)
is
begin
if rel_120_4 then
sm_timer3_countto_en_join_120_1 <= true;
else
sm_timer3_countto_en_join_120_1 <= false;
end if;
end process proc_if_120_1;
rel_126_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000100");
proc_if_126_1: process (rel_126_4)
is
begin
if rel_126_4 then
sm_timer_control_w_en_join_126_1 <= true;
else
sm_timer_control_w_en_join_126_1 <= false;
end if;
end process proc_if_126_1;
slice_141_42 <= u2u_slice(wrdbus_1_273, 31, 0);
slice_144_42 <= u2u_slice(wrdbus_1_273, 31, 0);
slice_147_42 <= u2u_slice(wrdbus_1_273, 31, 0);
slice_150_42 <= u2u_slice(wrdbus_1_273, 31, 0);
slice_153_43 <= u2u_slice(wrdbus_1_273, 31, 0);
rel_163_4 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("00");
rel_166_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("01");
rel_169_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("10");
rel_172_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("11");
proc_if_163_1: process (read_bank_out_reg_158_31, reg_bank_out_reg_47_30, rel_163_4, rel_166_8, rel_169_8, rel_172_8)
is
begin
if rel_163_4 then
read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_166_8 then
read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_169_8 then
read_bank_out_reg_join_163_1 <= reg_bank_out_reg_47_30;
elsif rel_172_8 then
read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_163_1 <= read_bank_out_reg_158_31;
end if;
end process proc_if_163_1;
reg_bank_out_reg_47_30_next <= reg_bank_out_reg_join_50_1;
read_bank_out_reg_158_31_next <= read_bank_out_reg_join_163_1;
bankaddr_reg_161_26_next <= bankaddr_1_281;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_158_31);
sm_timer0_countto_din <= unsigned_to_std_logic_vector(slice_141_42);
sm_timer0_countto_en <= boolean_to_vector(sm_timer0_countto_en_join_102_1);
sm_timer1_countto_din <= unsigned_to_std_logic_vector(slice_144_42);
sm_timer1_countto_en <= boolean_to_vector(sm_timer1_countto_en_join_108_1);
sm_timer2_countto_din <= unsigned_to_std_logic_vector(slice_147_42);
sm_timer2_countto_en <= boolean_to_vector(sm_timer2_countto_en_join_114_1);
sm_timer3_countto_din <= unsigned_to_std_logic_vector(slice_150_42);
sm_timer3_countto_en <= boolean_to_vector(sm_timer3_countto_en_join_120_1);
sm_timer_control_w_din <= unsigned_to_std_logic_vector(slice_153_43);
sm_timer_control_w_en <= boolean_to_vector(sm_timer_control_w_en_join_126_1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
generic(width : integer := -1;
latency : integer := -1;
reg_retiming : integer := 0);
port(d : in std_logic_vector (width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
en : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component synth_reg_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
signal internal_ce : std_logic;
begin
internal_ce <= ce and en;
srl_delay: if (reg_retiming = 0) or (latency < 1) generate
synth_reg_srl_inst : synth_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate srl_delay;
reg_delay: if (reg_retiming = 1) and (latency >= 1) generate
synth_reg_reg_inst : synth_reg_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate reg_delay;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_80f90b97d0 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_80f90b97d0;
architecture behavior of logical_80f90b97d0 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_q : integer := 1;
c_has_s : integer := 0;
c_has_c_out : integer := 0;
c_has_q_c_out : integer := 0;
c_has_b_out : integer := 0;
c_has_q_b_out : integer := 0;
c_has_q_ovfl : integer := 0;
c_has_ovfl : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub ;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e
port (
a: in std_logic_vector( 33 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(33 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process(a, b, core_s)
begin
full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e")) generate
core_instance0: adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if (c_latency = 0) or (c_latency = 1) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test : if((c_has_c_out = 1) or
(c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_q_b_out = 1)) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if ( ((latency = 0) or (extra_registers = 0)) and
((c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_c_out = 1) or
(c_has_q_b_out = 1))) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if ((c_has_c_out = 0) and
(c_has_b_out = 0) and
(c_has_q_c_out = 0) and
(c_has_q_b_out = 0)) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
signal real_din, real_dout : real;
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
begin
-- synopsys translate_off
-- synopsys translate_on
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0)
generate
reg : synth_reg
generic map ( width => dout_width,
latency => latency)
port map (i => result,
ce => ce,
clr => clr,
clk => clk,
o => dout);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_free ;
architecture behavior of xlcounter_free is
component binary_counter_virtex2p_7_0_b57302a6bcbb6876
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_b57302a6bcbb6876:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b57302a6bcbb6876:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_b57302a6bcbb6876:
component is "black_box";
-- synopsys translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_b57302a6bcbb6876")) generate
core_instance0: binary_counter_virtex2p_7_0_b57302a6bcbb6876
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_6cb8f0ce02 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_6cb8f0ce02;
architecture behavior of logical_6cb8f0ce02 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal d2_1_30: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
d2_1_30 <= d2(0);
fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_aacf6e1b0e is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_aacf6e1b0e;
architecture behavior of logical_aacf6e1b0e is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_112ed141f4 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_112ed141f4;
architecture behavior of mux_112ed141f4 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_3ffd1d0a40 is
port (
a : in std_logic_vector((32 - 1) downto 0);
b : in std_logic_vector((32 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_3ffd1d0a40;
architecture behavior of relational_3ffd1d0a40 is
signal a_1_31: unsigned((32 - 1) downto 0);
signal b_1_34: unsigned((32 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
result_12_3_rel <= a_1_31 = b_1_34;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_34fc311f5b is
port (
a : in std_logic_vector((32 - 1) downto 0);
b : in std_logic_vector((32 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_34fc311f5b;
architecture behavior of relational_34fc311f5b is
signal a_1_31: unsigned((32 - 1) downto 0);
signal b_1_34: unsigned((32 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_18_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_18_3_rel <= a_1_31 > b_1_34;
op_mem_32_22_front_din <= result_18_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_37567836aa is
port (
op : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_37567836aa;
architecture behavior of constant_37567836aa is
begin
op <= "00000000000000000000000000000000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_a1e126f11c is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
in2 : in std_logic_vector((8 - 1) downto 0);
in3 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_a1e126f11c;
architecture behavior of concat_a1e126f11c is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal in2_1_31: unsigned((8 - 1) downto 0);
signal in3_1_35: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((32 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
in3_1_35 <= std_logic_vector_to_unsigned(in3);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_09e13b86e0 is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
in2 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_09e13b86e0;
architecture behavior of concat_09e13b86e0 is
signal in0_1_23: boolean;
signal in1_1_27: boolean;
signal in2_1_31: boolean;
signal y_2_1_concat: unsigned((3 - 1) downto 0);
begin
in0_1_23 <= ((in0) = "1");
in1_1_27 <= ((in1) = "1");
in2_1_31 <= ((in2) = "1");
y_2_1_concat <= std_logic_vector_to_unsigned(boolean_to_vector(in0_1_23) & boolean_to_vector(in1_1_27) & boolean_to_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_a6d07705dd is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_a6d07705dd;
architecture behavior of logical_a6d07705dd is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal d2_1_30: std_logic;
signal d3_1_33: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
d2_1_30 <= d2(0);
d3_1_33 <= d3(0);
fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30 or d3_1_33;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/EDK Processor"
entity edk_processor_entity_cddda35d8e is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(31 downto 0);
from_register1: in std_logic_vector(31 downto 0);
from_register2: in std_logic_vector(31 downto 0);
from_register3: in std_logic_vector(31 downto 0);
from_register4: in std_logic_vector(31 downto 0);
from_register5: in std_logic_vector(31 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
to_register: in std_logic_vector(31 downto 0);
to_register1: in std_logic_vector(31 downto 0);
to_register2: in std_logic_vector(31 downto 0);
to_register3: in std_logic_vector(31 downto 0);
to_register4: in std_logic_vector(31 downto 0);
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0);
plb_memmap_x0: out std_logic_vector(31 downto 0);
plb_memmap_x1: out std_logic;
plb_memmap_x2: out std_logic_vector(31 downto 0);
plb_memmap_x3: out std_logic;
plb_memmap_x4: out std_logic_vector(31 downto 0);
plb_memmap_x5: out std_logic;
plb_memmap_x6: out std_logic_vector(31 downto 0);
plb_memmap_x7: out std_logic;
plb_memmap_x8: out std_logic_vector(31 downto 0);
plb_memmap_x9: out std_logic
);
end edk_processor_entity_cddda35d8e;
architecture structural of edk_processor_entity_cddda35d8e is
signal bankaddr: std_logic_vector(1 downto 0);
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal linearaddr: std_logic_vector(7 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal timer0_countto_din_x0: std_logic_vector(31 downto 0);
signal timer0_countto_dout_x0: std_logic_vector(31 downto 0);
signal timer0_countto_en_x0: std_logic;
signal timer0_timeleft_dout_x0: std_logic_vector(31 downto 0);
signal timer1_countto_din_x0: std_logic_vector(31 downto 0);
signal timer1_countto_dout_x0: std_logic_vector(31 downto 0);
signal timer1_countto_en_x0: std_logic;
signal timer1_timeleft_dout_x0: std_logic_vector(31 downto 0);
signal timer2_countto_din_x0: std_logic_vector(31 downto 0);
signal timer2_countto_dout_x0: std_logic_vector(31 downto 0);
signal timer2_countto_en_x0: std_logic;
signal timer2_timeleft_dout_x0: std_logic_vector(31 downto 0);
signal timer3_countto_din_x0: std_logic_vector(31 downto 0);
signal timer3_countto_dout_x0: std_logic_vector(31 downto 0);
signal timer3_countto_en_x0: std_logic;
signal timer3_timeleft_dout_x0: std_logic_vector(31 downto 0);
signal timer_control_r_dout_x0: std_logic_vector(31 downto 0);
signal timer_control_w_din_x0: std_logic_vector(31 downto 0);
signal timer_control_w_dout_x0: std_logic_vector(31 downto 0);
signal timer_control_w_en_x0: std_logic;
signal timer_status_dout_x0: std_logic_vector(31 downto 0);
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
timer0_timeleft_dout_x0 <= from_register;
timer1_timeleft_dout_x0 <= from_register1;
timer2_timeleft_dout_x0 <= from_register2;
timer3_timeleft_dout_x0 <= from_register3;
timer_control_r_dout_x0 <= from_register4;
timer_status_dout_x0 <= from_register5;
plb_abus_net_x0 <= plb_abus;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
splb_rst_net_x0 <= splb_rst;
timer0_countto_dout_x0 <= to_register;
timer1_countto_dout_x0 <= to_register1;
timer2_countto_dout_x0 <= to_register2;
timer3_countto_dout_x0 <= to_register3;
timer_control_w_dout_x0 <= to_register4;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
plb_memmap_x0 <= timer0_countto_din_x0;
plb_memmap_x1 <= timer0_countto_en_x0;
plb_memmap_x2 <= timer1_countto_din_x0;
plb_memmap_x3 <= timer1_countto_en_x0;
plb_memmap_x4 <= timer2_countto_din_x0;
plb_memmap_x5 <= timer2_countto_en_x0;
plb_memmap_x6 <= timer3_countto_din_x0;
plb_memmap_x7 <= timer3_countto_en_x0;
plb_memmap_x8 <= timer_control_w_din_x0;
plb_memmap_x9 <= timer_control_w_en_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_b389f41afb
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_b59e0d51fc
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
sm_timer0_countto => timer0_countto_dout_x0,
sm_timer0_timeleft => timer0_timeleft_dout_x0,
sm_timer1_countto => timer1_countto_dout_x0,
sm_timer1_timeleft => timer1_timeleft_dout_x0,
sm_timer2_countto => timer2_countto_dout_x0,
sm_timer2_timeleft => timer2_timeleft_dout_x0,
sm_timer3_countto => timer3_countto_dout_x0,
sm_timer3_timeleft => timer3_timeleft_dout_x0,
sm_timer_control_r => timer_control_r_dout_x0,
sm_timer_control_w => timer_control_w_dout_x0,
sm_timer_status => timer_status_dout_x0,
wrdbus => wrdbusreg,
read_bank_out => rddata,
sm_timer0_countto_din => timer0_countto_din_x0,
sm_timer0_countto_en(0) => timer0_countto_en_x0,
sm_timer1_countto_din => timer1_countto_din_x0,
sm_timer1_countto_en(0) => timer1_countto_en_x0,
sm_timer2_countto_din => timer2_countto_din_x0,
sm_timer2_countto_en(0) => timer2_countto_en_x0,
sm_timer3_countto_din => timer3_countto_din_x0,
sm_timer3_countto_en(0) => timer3_countto_en_x0,
sm_timer_control_w_din => timer_control_w_din_x0,
sm_timer_control_w_en(0) => timer_control_w_en_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/timer/S-R_Latch1"
entity s_r_latch1_entity_5f9ce35768 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
r: in std_logic;
s: in std_logic;
q: out std_logic
);
end s_r_latch1_entity_5f9ce35768;
architecture structural of s_r_latch1_entity_5f9ce35768 is
signal ce_1_sg_x1: std_logic;
signal clk_1_sg_x1: std_logic;
signal inverter_op_net: std_logic;
signal logical2_y_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
signal register_q_net_x0: std_logic;
begin
ce_1_sg_x1 <= ce_1;
clk_1_sg_x1 <= clk_1;
logical2_y_net_x0 <= r;
logical3_y_net_x0 <= s;
q <= register_q_net_x0;
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
ip(0) => register_q_net_x0,
op(0) => inverter_op_net
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
d(0) => logical3_y_net_x0,
en(0) => inverter_op_net,
rst(0) => logical2_y_net_x0,
q(0) => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/timer/posedge"
entity posedge_entity_8c50a6be04 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
in_x0: in std_logic;
out_x0: out std_logic
);
end posedge_entity_8c50a6be04;
architecture structural of posedge_entity_8c50a6be04 is
signal ce_1_sg_x3: std_logic;
signal clk_1_sg_x3: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal slice_y_net_x0: std_logic;
begin
ce_1_sg_x3 <= ce_1;
clk_1_sg_x3 <= clk_1;
slice_y_net_x0 <= in_x0;
out_x0 <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
d(0) => slice_y_net_x0,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
ip(0) => delay_q_net,
op(0) => inverter_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice_y_net_x0,
d1(0) => inverter_op_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/timer"
entity timer_entity_fee90fe8e7 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
countto: in std_logic_vector(31 downto 0);
idlefordifs_inp: in std_logic;
interruptreset: in std_logic;
mode: in std_logic;
pause: in std_logic;
resume: in std_logic;
start: in std_logic;
stop: in std_logic;
active: out std_logic;
interrupt: out std_logic;
paused: out std_logic;
timeleft: out std_logic_vector(31 downto 0)
);
end timer_entity_fee90fe8e7;
architecture structural of timer_entity_fee90fe8e7 is
signal addsub_s_net_x0: std_logic_vector(31 downto 0);
signal ce_1_sg_x5: std_logic;
signal clk_1_sg_x5: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic_vector(31 downto 0);
signal convert1_dout_net: std_logic;
signal counter_op_net: std_logic_vector(31 downto 0);
signal from_register1_data_out_net_x0: std_logic_vector(31 downto 0);
signal idlefordifs_net_x0: std_logic;
signal inverter_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical4_y_net_x0: std_logic;
signal logical_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal mux_y_net: std_logic;
signal register_q_net_x2: std_logic;
signal register_q_net_x3: std_logic;
signal relational1_op_net: std_logic;
signal relational_op_net_x0: std_logic;
signal slice1_y_net_x0: std_logic;
signal slice2_y_net_x1: std_logic;
signal slice3_y_net_x0: std_logic;
signal slice4_y_net_x0: std_logic;
signal slice5_y_net_x1: std_logic;
signal slice_y_net_x1: std_logic;
begin
ce_1_sg_x5 <= ce_1;
clk_1_sg_x5 <= clk_1;
from_register1_data_out_net_x0 <= countto;
idlefordifs_net_x0 <= idlefordifs_inp;
slice5_y_net_x1 <= interruptreset;
slice4_y_net_x0 <= mode;
slice3_y_net_x0 <= pause;
slice2_y_net_x1 <= resume;
slice_y_net_x1 <= start;
slice1_y_net_x0 <= stop;
active <= register_q_net_x2;
interrupt <= register_q_net_x3;
paused <= logical4_y_net_x0;
timeleft <= addsub_s_net_x0;
addsub: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 32,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 32,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 33,
core_name0 => "adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 33,
latency => 0,
mode => 2,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 32
)
port map (
a => from_register1_data_out_net_x0,
b => counter_op_net,
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
clr => '0',
en => "1",
s => addsub_s_net_x0
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => mux_y_net,
dout(0) => convert1_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_b57302a6bcbb6876",
op_arith => xlUnsigned,
op_width => 32
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
clr => '0',
en(0) => logical_y_net,
rst(0) => logical1_y_net,
op => counter_op_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
clr => '0',
ip(0) => register_q_net_x2,
op(0) => inverter_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => convert1_dout_net,
d1(0) => register_q_net_x2,
y(0) => logical_y_net
);
logical1: entity work.logical_6cb8f0ce02
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net_x0,
d1(0) => slice1_y_net_x0,
d2(0) => logical_y_net_x0,
y(0) => logical1_y_net
);
logical2: entity work.logical_6cb8f0ce02
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice1_y_net_x0,
d1(0) => slice3_y_net_x0,
d2(0) => relational_op_net_x0,
y(0) => logical2_y_net_x0
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical_y_net_x0,
d1(0) => logical_y_net_x1,
y(0) => logical3_y_net_x0
);
logical4: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational1_op_net,
d1(0) => inverter_op_net,
y(0) => logical4_y_net_x0
);
mux: entity work.mux_112ed141f4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => constant1_op_net,
d1(0) => idlefordifs_net_x0,
sel(0) => slice4_y_net_x0,
y(0) => mux_y_net
);
posedge1_8332b77348: entity work.posedge_entity_8c50a6be04
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
in_x0 => slice2_y_net_x1,
out_x0 => logical_y_net_x1
);
posedge_8c50a6be04: entity work.posedge_entity_8c50a6be04
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
in_x0 => slice_y_net_x1,
out_x0 => logical_y_net_x0
);
relational: entity work.relational_3ffd1d0a40
port map (
a => from_register1_data_out_net_x0,
b => counter_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational_op_net_x0
);
relational1: entity work.relational_34fc311f5b
port map (
a => counter_op_net,
b => constant_op_net,
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
clr => '0',
op(0) => relational1_op_net
);
s_r_latch1_5f9ce35768: entity work.s_r_latch1_entity_5f9ce35768
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
r => logical2_y_net_x0,
s => logical3_y_net_x0,
q => register_q_net_x2
);
s_r_latch2_722d862217: entity work.s_r_latch1_entity_5f9ce35768
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
r => slice5_y_net_x1,
s => relational_op_net_x0,
q => register_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/timer_control"
entity timer_control_entity_09b11c57d8 is
port (
constant6_x0: out std_logic
);
end timer_control_entity_09b11c57d8;
architecture structural of timer_control_entity_09b11c57d8 is
signal constant6_op_net_x0: std_logic;
begin
constant6_x0 <= constant6_op_net_x0;
constant6: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant6_op_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer"
entity warp_timer is
port (
ce_1: in std_logic;
clk_1: in std_logic;
data_out: in std_logic_vector(31 downto 0);
data_out_x0: in std_logic_vector(31 downto 0);
data_out_x1: in std_logic_vector(31 downto 0);
data_out_x2: in std_logic_vector(31 downto 0);
data_out_x3: in std_logic_vector(31 downto 0);
data_out_x4: in std_logic_vector(31 downto 0);
data_out_x5: in std_logic_vector(31 downto 0);
data_out_x6: in std_logic_vector(31 downto 0);
data_out_x7: in std_logic_vector(31 downto 0);
data_out_x8: in std_logic_vector(31 downto 0);
data_out_x9: in std_logic_vector(31 downto 0);
dout_x4: in std_logic_vector(31 downto 0);
dout_x5: in std_logic_vector(31 downto 0);
dout_x6: in std_logic_vector(31 downto 0);
dout_x7: in std_logic_vector(31 downto 0);
dout_x8: in std_logic_vector(31 downto 0);
idlefordifs: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
data_in: out std_logic_vector(31 downto 0);
data_in_x0: out std_logic_vector(31 downto 0);
data_in_x1: out std_logic_vector(31 downto 0);
data_in_x2: out std_logic_vector(31 downto 0);
data_in_x3: out std_logic_vector(31 downto 0);
data_in_x4: out std_logic_vector(31 downto 0);
data_in_x5: out std_logic_vector(31 downto 0);
data_in_x6: out std_logic_vector(31 downto 0);
data_in_x7: out std_logic_vector(31 downto 0);
data_in_x8: out std_logic_vector(31 downto 0);
data_in_x9: out std_logic_vector(31 downto 0);
en: out std_logic;
en_x0: out std_logic;
en_x1: out std_logic;
en_x2: out std_logic;
en_x3: out std_logic;
en_x4: out std_logic;
en_x5: out std_logic;
en_x6: out std_logic;
en_x7: out std_logic;
en_x8: out std_logic;
en_x9: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
timer0_active: out std_logic;
timer1_active: out std_logic;
timer2_active: out std_logic;
timer3_active: out std_logic;
timerexpire: out std_logic
);
end warp_timer;
architecture structural of warp_timer is
signal ce_1_sg_x21: std_logic;
signal clk_1_sg_x21: std_logic;
signal concat1_y_net: std_logic_vector(2 downto 0);
signal concat2_y_net: std_logic_vector(2 downto 0);
signal concat3_y_net: std_logic_vector(2 downto 0);
signal concat4_y_net: std_logic_vector(2 downto 0);
signal convert1_dout_net: std_logic_vector(7 downto 0);
signal convert2_dout_net: std_logic_vector(7 downto 0);
signal convert3_dout_net: std_logic_vector(7 downto 0);
signal convert_dout_net: std_logic_vector(7 downto 0);
signal data_in_net: std_logic_vector(31 downto 0);
signal data_in_x0_net: std_logic_vector(31 downto 0);
signal data_in_x1_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(31 downto 0);
signal data_in_x3_net: std_logic_vector(31 downto 0);
signal data_in_x4_net: std_logic_vector(31 downto 0);
signal data_in_x5_net: std_logic_vector(31 downto 0);
signal data_in_x6_net: std_logic_vector(31 downto 0);
signal data_in_x7_net: std_logic_vector(31 downto 0);
signal data_in_x8_net: std_logic_vector(31 downto 0);
signal data_out_net: std_logic_vector(31 downto 0);
signal data_out_x0_net: std_logic_vector(31 downto 0);
signal data_out_x1_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(31 downto 0);
signal data_out_x3_net: std_logic_vector(31 downto 0);
signal data_out_x4_net: std_logic_vector(31 downto 0);
signal data_out_x5_net: std_logic_vector(31 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal dout_x4_net: std_logic_vector(31 downto 0);
signal dout_x5_net: std_logic_vector(31 downto 0);
signal dout_x6_net: std_logic_vector(31 downto 0);
signal dout_x7_net: std_logic_vector(31 downto 0);
signal dout_x8_net: std_logic_vector(31 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x1_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal from_register2_data_out_net_x0: std_logic_vector(31 downto 0);
signal idlefordifs_net: std_logic;
signal logical4_y_net_x0: std_logic;
signal logical4_y_net_x1: std_logic;
signal logical4_y_net_x2: std_logic;
signal logical4_y_net_x3: std_logic;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal register_q_net_x3: std_logic;
signal register_q_net_x5: std_logic;
signal register_q_net_x7: std_logic;
signal register_q_net_x9: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal slice10_y_net_x0: std_logic;
signal slice11_y_net_x1: std_logic;
signal slice12_y_net_x1: std_logic;
signal slice13_y_net_x0: std_logic;
signal slice14_y_net_x1: std_logic;
signal slice15_y_net_x0: std_logic;
signal slice16_y_net_x0: std_logic;
signal slice17_y_net_x1: std_logic;
signal slice18_y_net_x1: std_logic;
signal slice19_y_net_x0: std_logic;
signal slice1_y_net_x0: std_logic;
signal slice20_y_net_x1: std_logic;
signal slice21_y_net_x0: std_logic;
signal slice22_y_net_x0: std_logic;
signal slice23_y_net_x1: std_logic;
signal slice2_y_net_x1: std_logic;
signal slice3_y_net_x0: std_logic;
signal slice4_y_net_x0: std_logic;
signal slice5_y_net_x1: std_logic;
signal slice6_y_net_x1: std_logic;
signal slice7_y_net_x0: std_logic;
signal slice8_y_net_x1: std_logic;
signal slice9_y_net_x0: std_logic;
signal slice_y_net_x1: std_logic;
signal splb_rst_net: std_logic;
signal timer0_active_net: std_logic;
signal timer1_active_net: std_logic;
signal timer2_active_net: std_logic;
signal timer3_active_net: std_logic;
signal timerexpire_net: std_logic;
begin
ce_1_sg_x21 <= ce_1;
clk_1_sg_x21 <= clk_1;
data_out_net <= data_out;
data_out_x0_net <= data_out_x0;
data_out_x1_net <= data_out_x1;
data_out_x2_net <= data_out_x2;
data_out_x3_net <= data_out_x3;
data_out_x4_net <= data_out_x4;
data_out_x5_net <= data_out_x5;
data_out_x6_net <= data_out_x6;
data_out_x7_net <= data_out_x7;
data_out_x8_net <= data_out_x8;
from_register2_data_out_net_x0 <= data_out_x9;
dout_x4_net <= dout_x4;
dout_x5_net <= dout_x5;
dout_x6_net <= dout_x6;
dout_x7_net <= dout_x7;
dout_x8_net <= dout_x8;
idlefordifs_net <= idlefordifs;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
data_in <= data_in_net;
data_in_x0 <= data_in_x0_net;
data_in_x1 <= data_in_x1_net;
data_in_x2 <= data_in_x2_net;
data_in_x3 <= data_in_x3_net;
data_in_x4 <= data_in_x4_net;
data_in_x5 <= data_in_x5_net;
data_in_x6 <= data_in_x6_net;
data_in_x7 <= data_in_x7_net;
data_in_x8 <= data_in_x8_net;
data_in_x9 <= from_register2_data_out_net_x0;
en <= en_net;
en_x0 <= en_x0_net;
en_x1 <= en_x1_net;
en_x2 <= en_x2_net;
en_x3 <= en_x3_net;
en_x4 <= en_x4_net;
en_x5 <= en_x5_net;
en_x6 <= en_x6_net;
en_x7 <= en_x7_net;
en_x8 <= en_x8_net;
en_x9 <= en_x9_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
timer0_active <= timer0_active_net;
timer1_active <= timer1_active_net;
timer2_active <= timer2_active_net;
timer3_active <= timer3_active_net;
timerexpire <= timerexpire_net;
concat: entity work.concat_a1e126f11c
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => convert3_dout_net,
in1 => convert2_dout_net,
in2 => convert1_dout_net,
in3 => convert_dout_net,
y => data_in_x3_net
);
concat1: entity work.concat_09e13b86e0
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => logical4_y_net_x0,
in1(0) => timer0_active_net,
in2(0) => register_q_net_x3,
y => concat1_y_net
);
concat2: entity work.concat_09e13b86e0
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => logical4_y_net_x1,
in1(0) => timer1_active_net,
in2(0) => register_q_net_x5,
y => concat2_y_net
);
concat3: entity work.concat_09e13b86e0
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => logical4_y_net_x2,
in1(0) => timer2_active_net,
in2(0) => register_q_net_x7,
y => concat3_y_net
);
concat4: entity work.concat_09e13b86e0
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => logical4_y_net_x3,
in1(0) => timer3_active_net,
in2(0) => register_q_net_x9,
y => concat4_y_net
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_net
);
constant2: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_x0_net
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_x1_net
);
constant4: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_x2_net
);
constant5: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_x3_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 3,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din => concat1_y_net,
dout => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 3,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din => concat2_y_net,
dout => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 3,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din => concat3_y_net,
dout => convert2_dout_net
);
convert3: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 3,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din => concat4_y_net,
dout => convert3_dout_net
);
edk_processor_cddda35d8e: entity work.edk_processor_entity_cddda35d8e
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_x3_net,
from_register1 => data_out_x4_net,
from_register2 => data_out_x5_net,
from_register3 => data_out_x6_net,
from_register4 => data_out_x7_net,
from_register5 => data_out_x8_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
to_register => dout_x4_net,
to_register1 => dout_x5_net,
to_register2 => dout_x6_net,
to_register3 => dout_x7_net,
to_register4 => dout_x8_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net,
plb_memmap_x0 => data_in_x4_net,
plb_memmap_x1 => en_x4_net,
plb_memmap_x2 => data_in_x5_net,
plb_memmap_x3 => en_x5_net,
plb_memmap_x4 => data_in_x6_net,
plb_memmap_x5 => en_x6_net,
plb_memmap_x6 => data_in_x7_net,
plb_memmap_x7 => en_x7_net,
plb_memmap_x8 => data_in_x8_net,
plb_memmap_x9 => en_x8_net
);
logical: entity work.logical_a6d07705dd
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register_q_net_x3,
d1(0) => register_q_net_x5,
d2(0) => register_q_net_x7,
d3(0) => register_q_net_x9,
y(0) => timerexpire_net
);
slice: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice_y_net_x1
);
slice1: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 1,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice1_y_net_x0
);
slice10: entity work.xlslice
generic map (
new_lsb => 12,
new_msb => 12,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice10_y_net_x0
);
slice11: entity work.xlslice
generic map (
new_lsb => 13,
new_msb => 13,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice11_y_net_x1
);
slice12: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 16,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice12_y_net_x1
);
slice13: entity work.xlslice
generic map (
new_lsb => 17,
new_msb => 17,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice13_y_net_x0
);
slice14: entity work.xlslice
generic map (
new_lsb => 18,
new_msb => 18,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice14_y_net_x1
);
slice15: entity work.xlslice
generic map (
new_lsb => 19,
new_msb => 19,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice15_y_net_x0
);
slice16: entity work.xlslice
generic map (
new_lsb => 20,
new_msb => 20,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice16_y_net_x0
);
slice17: entity work.xlslice
generic map (
new_lsb => 21,
new_msb => 21,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice17_y_net_x1
);
slice18: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 24,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice18_y_net_x1
);
slice19: entity work.xlslice
generic map (
new_lsb => 25,
new_msb => 25,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice19_y_net_x0
);
slice2: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice2_y_net_x1
);
slice20: entity work.xlslice
generic map (
new_lsb => 26,
new_msb => 26,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice20_y_net_x1
);
slice21: entity work.xlslice
generic map (
new_lsb => 27,
new_msb => 27,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice21_y_net_x0
);
slice22: entity work.xlslice
generic map (
new_lsb => 28,
new_msb => 28,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice22_y_net_x0
);
slice23: entity work.xlslice
generic map (
new_lsb => 29,
new_msb => 29,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice23_y_net_x1
);
slice3: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice3_y_net_x0
);
slice4: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 4,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice4_y_net_x0
);
slice5: entity work.xlslice
generic map (
new_lsb => 5,
new_msb => 5,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice5_y_net_x1
);
slice6: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice6_y_net_x1
);
slice7: entity work.xlslice
generic map (
new_lsb => 9,
new_msb => 9,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice7_y_net_x0
);
slice8: entity work.xlslice
generic map (
new_lsb => 10,
new_msb => 10,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice8_y_net_x1
);
slice9: entity work.xlslice
generic map (
new_lsb => 11,
new_msb => 11,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice9_y_net_x0
);
timer1_a9ea58dee7: entity work.timer_entity_fee90fe8e7
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
countto => data_out_x0_net,
idlefordifs_inp => idlefordifs_net,
interruptreset => slice11_y_net_x1,
mode => slice10_y_net_x0,
pause => slice9_y_net_x0,
resume => slice8_y_net_x1,
start => slice6_y_net_x1,
stop => slice7_y_net_x0,
active => timer1_active_net,
interrupt => register_q_net_x5,
paused => logical4_y_net_x1,
timeleft => data_in_x0_net
);
timer2_15928ecc3b: entity work.timer_entity_fee90fe8e7
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
countto => data_out_x1_net,
idlefordifs_inp => idlefordifs_net,
interruptreset => slice17_y_net_x1,
mode => slice16_y_net_x0,
pause => slice15_y_net_x0,
resume => slice14_y_net_x1,
start => slice12_y_net_x1,
stop => slice13_y_net_x0,
active => timer2_active_net,
interrupt => register_q_net_x7,
paused => logical4_y_net_x2,
timeleft => data_in_x1_net
);
timer3_4ea9afe7c4: entity work.timer_entity_fee90fe8e7
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
countto => data_out_x2_net,
idlefordifs_inp => idlefordifs_net,
interruptreset => slice23_y_net_x1,
mode => slice22_y_net_x0,
pause => slice21_y_net_x0,
resume => slice20_y_net_x1,
start => slice18_y_net_x1,
stop => slice19_y_net_x0,
active => timer3_active_net,
interrupt => register_q_net_x9,
paused => logical4_y_net_x3,
timeleft => data_in_x2_net
);
timer_control_09b11c57d8: entity work.timer_control_entity_09b11c57d8
port map (
constant6_x0 => en_x9_net
);
timer_fee90fe8e7: entity work.timer_entity_fee90fe8e7
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
countto => data_out_net,
idlefordifs_inp => idlefordifs_net,
interruptreset => slice5_y_net_x1,
mode => slice4_y_net_x0,
pause => slice3_y_net_x0,
resume => slice2_y_net_x1,
start => slice_y_net_x1,
stop => slice1_y_net_x0,
active => timer0_active_net,
interrupt => register_q_net_x3,
paused => logical4_y_net_x0,
timeleft => data_in_net
);
end structural;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
entity xlclkprobe is
port (clk : in std_logic;
clr : in std_logic;
ce : in std_logic;
fakeOutForXst : out std_logic);
end xlclkprobe;
architecture behavior of xlclkprobe is
begin
fakeOutForXst <= '0';
-- synopsys translate_off
work.clock_pkg.int_clk <= clk;
-- synopsys translate_on
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity warp_timer_cw is
port (
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
idlefordifs: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
timer0_active: out std_logic;
timer1_active: out std_logic;
timer2_active: out std_logic;
timer3_active: out std_logic;
timerexpire: out std_logic
);
end warp_timer_cw;
architecture structural of warp_timer_cw is
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type: string;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal ce_1_sg_x21: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x21: signal is "REDUCE";
signal clkNet: std_logic;
signal clk_1_sg_x21: std_logic;
signal data_in_net: std_logic_vector(31 downto 0);
signal data_in_x0_net: std_logic_vector(31 downto 0);
signal data_in_x1_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(31 downto 0);
signal data_in_x3_net: std_logic_vector(31 downto 0);
signal data_in_x4_net: std_logic_vector(31 downto 0);
signal data_in_x5_net: std_logic_vector(31 downto 0);
signal data_in_x6_net: std_logic_vector(31 downto 0);
signal data_in_x7_net: std_logic_vector(31 downto 0);
signal data_in_x8_net: std_logic_vector(31 downto 0);
signal data_out_net: std_logic_vector(31 downto 0);
signal data_out_x0_net: std_logic_vector(31 downto 0);
signal data_out_x1_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(31 downto 0);
signal data_out_x3_net: std_logic_vector(31 downto 0);
signal data_out_x4_net: std_logic_vector(31 downto 0);
signal data_out_x5_net: std_logic_vector(31 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x1_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal from_register2_data_out_net_x0: std_logic_vector(31 downto 0);
signal from_register2_data_out_net_x1: std_logic_vector(31 downto 0);
signal idlefordifs_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal timer0_active_net: std_logic;
signal timer0_countTo_reg_ce: std_logic;
signal timer0_timeLeft_reg_ce: std_logic;
signal timer1_active_net: std_logic;
signal timer1_countTo_reg_ce: std_logic;
signal timer1_timeLeft_reg_ce: std_logic;
signal timer2_active_net: std_logic;
signal timer2_countTo_reg_ce: std_logic;
signal timer2_timeLeft_reg_ce: std_logic;
signal timer3_active_net: std_logic;
signal timer3_countTo_reg_ce: std_logic;
signal timer3_timeLeft_reg_ce: std_logic;
signal timer_control_r_reg_ce: std_logic;
signal timer_control_w_reg_ce: std_logic;
signal timer_status_reg_ce: std_logic;
signal timerexpire_net: std_logic;
begin
clkNet <= clk;
idlefordifs_net <= idlefordifs;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
timer0_active <= timer0_active_net;
timer1_active <= timer1_active_net;
timer2_active <= timer2_active_net;
timer3_active <= timer3_active_net;
timerexpire <= timerexpire_net;
clk_probe: entity work.xlclkprobe
port map (
ce => '1',
clk => clkNet,
clr => '0'
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
timer0_countTo: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer0_countTo_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x4_net,
o => data_out_net
);
timer0_countTo_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x4_net,
dout => timer0_countTo_reg_ce
);
timer0_timeLeft: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer0_timeLeft_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_net,
o => data_out_x3_net
);
timer0_timeLeft_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_net,
dout => timer0_timeLeft_reg_ce
);
timer1_countTo: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer1_countTo_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x5_net,
o => data_out_x0_net
);
timer1_countTo_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x5_net,
dout => timer1_countTo_reg_ce
);
timer1_timeLeft: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer1_timeLeft_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x0_net,
o => data_out_x4_net
);
timer1_timeLeft_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x0_net,
dout => timer1_timeLeft_reg_ce
);
timer2_countTo: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer2_countTo_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x6_net,
o => data_out_x1_net
);
timer2_countTo_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x6_net,
dout => timer2_countTo_reg_ce
);
timer2_timeLeft: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer2_timeLeft_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x1_net,
o => data_out_x5_net
);
timer2_timeLeft_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x1_net,
dout => timer2_timeLeft_reg_ce
);
timer3_countTo: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer3_countTo_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x7_net,
o => data_out_x2_net
);
timer3_countTo_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x7_net,
dout => timer3_countTo_reg_ce
);
timer3_timeLeft: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer3_timeLeft_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x2_net,
o => data_out_x6_net
);
timer3_timeLeft_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x2_net,
dout => timer3_timeLeft_reg_ce
);
timer_control_r: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer_control_r_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => from_register2_data_out_net_x1,
o => data_out_x7_net
);
timer_control_r_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x9_net,
dout => timer_control_r_reg_ce
);
timer_control_w: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer_control_w_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x8_net,
o => from_register2_data_out_net_x0
);
timer_control_w_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x8_net,
dout => timer_control_w_reg_ce
);
timer_status: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer_status_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x3_net,
o => data_out_x8_net
);
timer_status_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x3_net,
dout => timer_status_reg_ce
);
warp_timer_x0: entity work.warp_timer
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
data_out => data_out_net,
data_out_x0 => data_out_x0_net,
data_out_x1 => data_out_x1_net,
data_out_x2 => data_out_x2_net,
data_out_x3 => data_out_x3_net,
data_out_x4 => data_out_x4_net,
data_out_x5 => data_out_x5_net,
data_out_x6 => data_out_x6_net,
data_out_x7 => data_out_x7_net,
data_out_x8 => data_out_x8_net,
data_out_x9 => from_register2_data_out_net_x0,
dout_x4 => data_out_net,
dout_x5 => data_out_x0_net,
dout_x6 => data_out_x1_net,
dout_x7 => data_out_x2_net,
dout_x8 => from_register2_data_out_net_x0,
idlefordifs => idlefordifs_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
data_in => data_in_net,
data_in_x0 => data_in_x0_net,
data_in_x1 => data_in_x1_net,
data_in_x2 => data_in_x2_net,
data_in_x3 => data_in_x3_net,
data_in_x4 => data_in_x4_net,
data_in_x5 => data_in_x5_net,
data_in_x6 => data_in_x6_net,
data_in_x7 => data_in_x7_net,
data_in_x8 => data_in_x8_net,
data_in_x9 => from_register2_data_out_net_x1,
en => en_net,
en_x0 => en_x0_net,
en_x1 => en_x1_net,
en_x2 => en_x2_net,
en_x3 => en_x3_net,
en_x4 => en_x4_net,
en_x5 => en_x5_net,
en_x6 => en_x6_net,
en_x7 => en_x7_net,
en_x8 => en_x8_net,
en_x9 => en_x9_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
timer0_active => timer0_active_net,
timer1_active => timer1_active_net,
timer2_active => timer2_active_net,
timer3_active => timer3_active_net,
timerexpire => timerexpire_net
);
end structural;
| bsd-2-clause |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_01_a/hdl/vhdl/radio_controller.vhd | 2 | 25787 | ------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY **
-- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR **
-- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND **
-- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES **
-- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: radio_controller.vhd
-- Version: 1.01.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Thu Jul 07 16:33:45 2005 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_a;
use opb_ipif_v3_01_a.all;
library radio_controller_v1_01_a;
use radio_controller_v1_01_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
radio1_shdn : out std_logic;
radio1_txen : out std_logic;
radio1_rxen : out std_logic;
radio1_rxhp : out std_logic;
radio1_ld : in std_logic;
radio1_24pa : out std_logic;
radio1_5pa : out std_logic;
radio1_antsw : out std_logic_vector(0 to 1);
radio1_led : out std_logic_vector(0 to 2);
radio2_shdn : out std_logic;
radio2_txen : out std_logic;
radio2_rxen : out std_logic;
radio2_rxhp : out std_logic;
radio2_ld : in std_logic;
radio2_24pa : out std_logic;
radio2_5pa : out std_logic;
radio2_antsw : out std_logic_vector(0 to 1);
radio2_led : out std_logic_vector(0 to 2);
radio3_shdn : out std_logic;
radio3_txen : out std_logic;
radio3_rxen : out std_logic;
radio3_rxhp : out std_logic;
radio3_ld : in std_logic;
radio3_24pa : out std_logic;
radio3_5pa : out std_logic;
radio3_antsw : out std_logic_vector(0 to 1);
radio3_led : out std_logic_vector(0 to 2);
radio4_shdn : out std_logic;
radio4_txen : out std_logic;
radio4_rxen : out std_logic;
radio4_rxhp : out std_logic;
radio4_ld : in std_logic;
radio4_24pa : out std_logic;
radio4_5pa : out std_logic;
radio4_antsw : out std_logic_vector(0 to 1);
radio4_led : out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_CE : integer := 4;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_a.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Radio1_SHDN => radio1_shdn,
Radio1_TxEn => radio1_txen,
Radio1_RxEn => radio1_rxen,
Radio1_RxHP => radio1_rxhp,
Radio1_LD => radio1_ld,
Radio1_24PA => radio1_24pa,
Radio1_5PA => radio1_5pa,
Radio1_ANTSW => radio1_antsw,
Radio1_LED => radio1_led,
Radio2_SHDN => radio2_shdn,
Radio2_TxEn => radio2_txen,
Radio2_RxEn => radio2_rxen,
Radio2_RxHP => radio2_rxhp,
Radio2_LD => radio2_ld,
Radio2_24PA => radio2_24pa,
Radio2_5PA => radio2_5pa,
Radio2_ANTSW => radio2_antsw,
Radio2_LED => radio2_led,
Radio3_SHDN => radio3_shdn,
Radio3_TxEn => radio3_txen,
Radio3_RxEn => radio3_rxen,
Radio3_RxHP => radio3_rxhp,
Radio3_LD => radio3_ld,
Radio3_24PA => radio3_24pa,
Radio3_5PA => radio3_5pa,
Radio3_ANTSW => radio3_antsw,
Radio3_LED => radio3_led,
Radio4_SHDN => radio4_shdn,
Radio4_TxEn => radio4_txen,
Radio4_RxEn => radio4_rxen,
Radio4_RxHP => radio4_rxhp,
Radio4_LD => radio4_ld,
Radio4_24PA => radio4_24pa,
Radio4_5PA => radio4_5pa,
Radio4_ANTSW => radio4_antsw,
Radio4_LED => radio4_led,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/rawUVCfifo_synth.vhd | 3 | 4394 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rawUVCfifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END rawUVCfifo;
ARCHITECTURE spartan6 OF rawUVCfifo IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/jpeg_encoder/design/OutMux.vhd | 3 | 5882 | -------------------------------------------------------------------------------
-- File Name : OutMux.vhd
--
-- Project : JPEG_ENC
--
-- Module : OutMux
--
-- Content : Output Multiplexer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090308: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity OutMux is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
out_mux_ctrl : in std_logic;
-- ByteStuffer
bs_ram_byte : in std_logic_vector(7 downto 0);
bs_ram_wren : in std_logic;
bs_ram_wraddr : in std_logic_vector(23 downto 0);
-- JFIFGen
jfif_ram_byte : in std_logic_vector(7 downto 0);
jfif_ram_wren : in std_logic;
jfif_ram_wraddr : in std_logic_vector(23 downto 0);
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity OutMux;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of OutMux is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Mux
-------------------------------------------------------------------
p_ctrl : process(CLK, RST)
begin
if RST = '1' then
ram_byte <= (others => '0');
ram_wren <= '0';
ram_wraddr <= (others => '0');
elsif CLK'event and CLK = '1' then
if out_mux_ctrl = '0' then
ram_byte <= jfif_ram_byte;
ram_wren <= jfif_ram_wren;
ram_wraddr <= std_logic_vector(jfif_ram_wraddr);
else
ram_byte <= bs_ram_byte;
ram_wren <= bs_ram_wren;
ram_wraddr <= bs_ram_wraddr;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/bytefifoFPGA/simulation/bytefifoFPGA_dgen.vhd | 3 | 4545 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifoFPGA_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.bytefifoFPGA_pkg.ALL;
ENTITY bytefifoFPGA_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF bytefifoFPGA_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:bytefifoFPGA_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| bsd-2-clause |
freecores/eco32 | fpga/src/ram/sdramcntl.vhd | 1 | 31168 | --------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS Corp
-- Tool Versions : WebPACK 6.3.03i
--
-- Description:
-- SDRAM controller
--
-- Revision:
-- n.a. (because of hacking by Hellwig Geisse)
--
-- Additional Comments:
-- 1.4.0:
-- Added generic parameter to enable/disable independent active rows in each bank.
-- 1.3.0:
-- Modified to allow independently active rows in each bank.
-- 1.2.0:
-- Modified to allow pipelining of read/write operations.
-- 1.1.0:
-- Initial release.
--
-- License:
-- This code can be freely distributed and modified as long as
-- this header is not removed.
--------------------------------------------------------------------
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity sdramCntl is
port(
-- host side
clk : in std_logic; -- master clock
clk_ok : in std_logic; -- true if clock is stable
rd : in std_logic; -- initiate read operation
wr : in std_logic; -- initiate write operation
done : out std_logic; -- read or write operation is done
hAddr : in std_logic_vector(23 downto 0); -- address from host to SDRAM
hDIn : in std_logic_vector(15 downto 0); -- data from host to SDRAM
hDOut : out std_logic_vector(15 downto 0); -- data from SDRAM to host
-- SDRAM side
cke : out std_logic; -- clock-enable to SDRAM
ce_n : out std_logic; -- chip-select to SDRAM
ras_n : out std_logic; -- SDRAM row address strobe
cas_n : out std_logic; -- SDRAM column address strobe
we_n : out std_logic; -- SDRAM write enable
ba : out std_logic_vector(1 downto 0); -- SDRAM bank address
sAddr : out std_logic_vector(12 downto 0); -- SDRAM row/column address
sDIn : in std_logic_vector(15 downto 0); -- data from SDRAM
sDOut : out std_logic_vector(15 downto 0); -- data to SDRAM
sDOutEn : out std_logic; -- true if data is output to SDRAM on sDOut
dqmh : out std_logic; -- enable upper-byte of SDRAM databus if true
dqml : out std_logic -- enable lower-byte of SDRAM databus if true
);
end sdramCntl;
architecture arch of sdramCntl is
constant YES : std_logic := '1';
constant NO : std_logic := '0';
-- select one of two integers based on a Boolean
function int_select(s : in boolean; a : in integer; b : in integer) return integer is
begin
if s then
return a;
else
return b;
end if;
return a;
end function int_select;
constant OUTPUT : std_logic := '1'; -- direction of dataflow w.r.t. this controller
constant INPUT : std_logic := '0';
constant NOP : std_logic := '0'; -- no operation
constant READ : std_logic := '1'; -- read operation
constant WRITE : std_logic := '1'; -- write operation
-- SDRAM timing parameters
constant Tinit : natural := 200; -- min initialization interval (us)
constant Tras : natural := 45; -- min interval between active to precharge commands (ns)
constant Trcd : natural := 20; -- min interval between active and R/W commands (ns)
constant Tref : natural := 64_000_000; -- maximum refresh interval (ns)
constant Trfc : natural := 66; -- duration of refresh operation (ns)
constant Trp : natural := 20; -- min precharge command duration (ns)
constant Twr : natural := 15; -- write recovery time (ns)
constant Txsr : natural := 75; -- exit self-refresh time (ns)
-- SDRAM timing parameters converted into clock cycles (based on FREQ = 50_000)
constant NORM : natural := 1_000_000; -- normalize ns * KHz
constant INIT_CYCLES : natural := 1+((Tinit*50_000)/1000); -- SDRAM power-on initialization interval
constant RAS_CYCLES : natural := 1+((Tras*50_000)/NORM); -- active-to-precharge interval
constant RCD_CYCLES : natural := 1+((Trcd*50_000)/NORM); -- active-to-R/W interval
constant REF_CYCLES : natural := 1+(((Tref/8192)*50_000)/NORM); -- interval between row refreshes
constant RFC_CYCLES : natural := 1+((Trfc*50_000)/NORM); -- refresh operation interval
constant RP_CYCLES : natural := 1+((Trp*50_000)/NORM); -- precharge operation interval
constant WR_CYCLES : natural := 1+((Twr*50_000)/NORM); -- write recovery time
constant XSR_CYCLES : natural := 1+((Txsr*50_000)/NORM); -- exit self-refresh time
constant MODE_CYCLES : natural := 2; -- mode register setup time
constant CAS_CYCLES : natural := 3; -- CAS latency
constant RFSH_OPS : natural := 8; -- number of refresh operations needed to init SDRAM
-- timer registers that count down times for various SDRAM operations
signal timer_r, timer_x : natural range 0 to INIT_CYCLES; -- current SDRAM op time
signal rasTimer_r, rasTimer_x : natural range 0 to RAS_CYCLES; -- active-to-precharge time
signal wrTimer_r, wrTimer_x : natural range 0 to WR_CYCLES; -- write-to-precharge time
signal refTimer_r, refTimer_x : natural range 0 to REF_CYCLES; -- time between row refreshes
signal rfshCntr_r, rfshCntr_x : natural range 0 to 8192; -- counts refreshes that are neede
signal nopCntr_r, nopCntr_x : natural range 0 to 10000; -- counts consecutive NOP operations
signal doSelfRfsh : std_logic; -- active when the NOP counter hits zero and self-refresh can start
-- states of the SDRAM controller state machine
type cntlState is (
INITWAIT, -- initialization - waiting for power-on initialization to complete
INITPCHG, -- initialization - initial precharge of SDRAM banks
INITSETMODE, -- initialization - set SDRAM mode
INITRFSH, -- initialization - do initial refreshes
RW, -- read/write/refresh the SDRAM
ACTIVATE, -- open a row of the SDRAM for reading/writing
REFRESHROW, -- refresh a row of the SDRAM
SELFREFRESH -- keep SDRAM in self-refresh mode with CKE low
);
signal state_r, state_x : cntlState; -- state register and next state
-- commands that are sent to the SDRAM to make it perform certain operations
-- commands use these SDRAM input pins (ce_n,ras_n,cas_n,we_n,dqmh,dqml)
subtype sdramCmd is unsigned(5 downto 0);
constant NOP_CMD : sdramCmd := "011100";
constant ACTIVE_CMD : sdramCmd := "001100";
constant READ_CMD : sdramCmd := "010100";
constant WRITE_CMD : sdramCmd := "010000";
constant PCHG_CMD : sdramCmd := "001011";
constant MODE_CMD : sdramCmd := "000011";
constant RFSH_CMD : sdramCmd := "000111";
-- SDRAM mode register
-- the SDRAM is placed in a non-burst mode (burst length = 1) with a 3-cycle CAS
subtype sdramMode is std_logic_vector(12 downto 0);
constant MODE : sdramMode := "000" & "0" & "00" & "011" & "0" & "000";
-- the host address is decomposed into these sets of SDRAM address components
constant ROW_LEN : natural := 13; -- number of row address bits
constant COL_LEN : natural := 9; -- number of column address bits
signal bank : std_logic_vector(ba'range); -- bank address bits
signal row : std_logic_vector(ROW_LEN - 1 downto 0); -- row address within bank
signal col : std_logic_vector(sAddr'range); -- column address within row
-- registers that store the currently active row in each bank of the SDRAM
constant NUM_ACTIVE_ROWS : integer := 1;
type activeRowType is array(0 to NUM_ACTIVE_ROWS-1) of std_logic_vector(row'range);
signal activeRow_r, activeRow_x : activeRowType;
signal activeFlag_r, activeFlag_x : std_logic_vector(0 to NUM_ACTIVE_ROWS-1); -- indicates that some row in a bank is active
signal bankIndex : natural range 0 to NUM_ACTIVE_ROWS-1; -- bank address bits
signal activeBank_r, activeBank_x : std_logic_vector(ba'range); -- indicates the bank with the active row
signal doActivate : std_logic; -- indicates when a new row in a bank needs to be activated
-- there is a command bit embedded within the SDRAM column address
constant CMDBIT_POS : natural := 10; -- position of command bit
constant AUTO_PCHG_ON : std_logic := '1'; -- CMDBIT value to auto-precharge the bank
constant AUTO_PCHG_OFF : std_logic := '0'; -- CMDBIT value to disable auto-precharge
constant ONE_BANK : std_logic := '0'; -- CMDBIT value to select one bank
constant ALL_BANKS : std_logic := '1'; -- CMDBIT value to select all banks
-- status signals that indicate when certain operations are in progress
signal wrInProgress : std_logic; -- write operation in progress
signal rdInProgress : std_logic; -- read operation in progress
signal activateInProgress : std_logic; -- row activation is in progress
-- these registers track the progress of read and write operations
signal rdPipeline_r, rdPipeline_x : std_logic_vector(CAS_CYCLES+1 downto 0); -- pipeline of read ops in progress
signal wrPipeline_r, wrPipeline_x : std_logic_vector(0 downto 0); -- pipeline of write ops (only need 1 cycle)
-- registered outputs to host
signal hDOut_r, hDOut_x : std_logic_vector(hDOut'range); -- holds data read from SDRAM and sent to the host
-- registered outputs to SDRAM
signal cke_r, cke_x : std_logic; -- clock enable
signal cmd_r, cmd_x : sdramCmd; -- SDRAM command bits
signal ba_r, ba_x : std_logic_vector(ba'range); -- SDRAM bank address bits
signal sAddr_r, sAddr_x : std_logic_vector(sAddr'range); -- SDRAM row/column address
signal sData_r, sData_x : std_logic_vector(sDOut'range); -- SDRAM out databus
signal sDataDir_r, sDataDir_x : std_logic; -- SDRAM databus direction control bit
begin
-----------------------------------------------------------
-- attach some internal signals to the I/O ports
-----------------------------------------------------------
-- attach registered SDRAM control signals to SDRAM input pins
(ce_n, ras_n, cas_n, we_n, dqmh, dqml) <= cmd_r; -- SDRAM operation control bits
cke <= cke_r; -- SDRAM clock enable
ba <= ba_r; -- SDRAM bank address
sAddr <= sAddr_r; -- SDRAM address
sDOut <= sData_r; -- SDRAM output data bus
sDOutEn <= YES when sDataDir_r = OUTPUT else NO; -- output databus enable
-- attach some port signals
hDOut <= hDOut_r; -- data back to host
-----------------------------------------------------------
-- compute the next state and outputs
-----------------------------------------------------------
combinatorial : process(rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r,
activeFlag_r, activeRow_r, activeBank_r,
rdPipeline_r, wrPipeline_r,
nopCntr_r, rfshCntr_r, timer_r, rasTimer_r,
wrTimer_r, refTimer_r, cmd_r, cke_r)
begin
-----------------------------------------------------------
-- setup default values for signals
-----------------------------------------------------------
cke_x <= YES; -- enable SDRAM clock
cmd_x <= NOP_CMD; -- set SDRAM command to no-operation
sDataDir_x <= INPUT; -- accept data from the SDRAM
sData_x <= hDIn(sData_x'range); -- output data from host to SDRAM
state_x <= state_r; -- reload these registers and flags
activeFlag_x <= activeFlag_r; -- with their existing values
activeRow_x <= activeRow_r;
activeBank_x <= activeBank_r;
rfshCntr_x <= rfshCntr_r;
-----------------------------------------------------------
-- setup default value for the SDRAM address
-----------------------------------------------------------
-- extract bank field from host address
ba_x <= hAddr(ba'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN);
bank <= ba_x;
bankIndex <= 0;
-- extract row, column fields from host address
row <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN);
-- extend column (if needed) until it is as large as the (SDRAM address bus - 1)
col <= (others => '0'); -- set it to all zeroes
col(COL_LEN-1 downto 0) <= hAddr(COL_LEN-1 downto 0);
-- by default, set SDRAM address to the column address with interspersed
-- command bit set to disable auto-precharge
sAddr_x <= col(col'high-1 downto CMDBIT_POS) & AUTO_PCHG_OFF
& col(CMDBIT_POS-1 downto 0);
-----------------------------------------------------------
-- manage the read and write operation pipelines
-----------------------------------------------------------
-- determine if read operations are in progress by the presence of
-- READ flags in the read pipeline
if rdPipeline_r(rdPipeline_r'high downto 1) /= 0 then
rdInProgress <= YES;
else
rdInProgress <= NO;
end if;
-- enter NOPs into the read and write pipeline shift registers by default
rdPipeline_x <= NOP & rdPipeline_r(rdPipeline_r'high downto 1);
wrPipeline_x(0) <= NOP;
-- transfer data from SDRAM to the host data register if a read flag has exited the pipeline
-- (the transfer occurs 1 cycle before we tell the host the read operation is done)
if rdPipeline_r(1) = READ then
-- get the SDRAM data for the host directly from the SDRAM if the controller and SDRAM are in-phase
hDOut_x <= sDIn(hDOut'range);
else
-- retain contents of host data registers if no data from the SDRAM has arrived yet
hDOut_x <= hDOut_r;
end if;
done <= rdPipeline_r(0) or wrPipeline_r(0); -- a read or write operation is done
-----------------------------------------------------------
-- manage row activation
-----------------------------------------------------------
-- request a row activation operation if the row of the current address
-- does not match the currently active row in the bank, or if no row
-- in the bank is currently active
if (bank /= activeBank_r) or (row /= activeRow_r(bankIndex)) or (activeFlag_r(bankIndex) = NO) then
doActivate <= YES;
else
doActivate <= NO;
end if;
-----------------------------------------------------------
-- manage self-refresh
-----------------------------------------------------------
-- enter self-refresh if neither a read or write is requested for 10000 consecutive cycles.
if (rd = YES) or (wr = YES) then
-- any read or write resets NOP counter and exits self-refresh state
nopCntr_x <= 0;
doSelfRfsh <= NO;
elsif nopCntr_r /= 10000 then
-- increment NOP counter whenever there is no read or write operation
nopCntr_x <= nopCntr_r + 1;
doSelfRfsh <= NO;
else
-- start self-refresh when counter hits maximum NOP count and leave counter unchanged
nopCntr_x <= nopCntr_r;
doSelfRfsh <= YES;
end if;
-----------------------------------------------------------
-- update the timers
-----------------------------------------------------------
-- row activation timer
if rasTimer_r /= 0 then
-- decrement a non-zero timer and set the flag
-- to indicate the row activation is still inprogress
rasTimer_x <= rasTimer_r - 1;
activateInProgress <= YES;
else
-- on timeout, keep the timer at zero and reset the flag
-- to indicate the row activation operation is done
rasTimer_x <= rasTimer_r;
activateInProgress <= NO;
end if;
-- write operation timer
if wrTimer_r /= 0 then
-- decrement a non-zero timer and set the flag
-- to indicate the write operation is still inprogress
wrTimer_x <= wrTimer_r - 1;
wrInPRogress <= YES;
else
-- on timeout, keep the timer at zero and reset the flag that
-- indicates a write operation is in progress
wrTimer_x <= wrTimer_r;
wrInPRogress <= NO;
end if;
-- refresh timer
if refTimer_r /= 0 then
refTimer_x <= refTimer_r - 1;
else
-- on timeout, reload the timer with the interval between row refreshes
-- and increment the counter for the number of row refreshes that are needed
refTimer_x <= REF_CYCLES;
rfshCntr_x <= rfshCntr_r + 1;
end if;
-- main timer for sequencing SDRAM operations
if timer_r /= 0 then
-- decrement the timer and do nothing else since the previous operation has not completed yet.
timer_x <= timer_r - 1;
else
-- the previous operation has completed once the timer hits zero
timer_x <= timer_r; -- by default, leave the timer at zero
-----------------------------------------------------------
-- compute the next state and outputs
-----------------------------------------------------------
case state_r is
-----------------------------------------------------------
-- let clock stabilize and then wait for the SDRAM to initialize
-----------------------------------------------------------
when INITWAIT =>
-- wait for SDRAM power-on initialization once the clock is stable
timer_x <= INIT_CYCLES; -- set timer for initialization duration
state_x <= INITPCHG;
-----------------------------------------------------------
-- precharge all SDRAM banks after power-on initialization
-----------------------------------------------------------
when INITPCHG =>
cmd_x <= PCHG_CMD;
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for precharge operation duration
rfshCntr_x <= RFSH_OPS; -- set counter for refresh ops needed after precharge
state_x <= INITRFSH;
-----------------------------------------------------------
-- refresh the SDRAM a number of times after initial precharge
-----------------------------------------------------------
when INITRFSH =>
cmd_x <= RFSH_CMD;
timer_x <= RFC_CYCLES; -- set timer to refresh operation duration
rfshCntr_x <= rfshCntr_r - 1; -- decrement refresh operation counter
if rfshCntr_r = 1 then
state_x <= INITSETMODE; -- set the SDRAM mode once all refresh ops are done
end if;
-----------------------------------------------------------
-- set the mode register of the SDRAM
-----------------------------------------------------------
when INITSETMODE =>
cmd_x <= MODE_CMD;
sAddr_x <= MODE; -- output mode register bits on the SDRAM address bits
timer_x <= MODE_CYCLES; -- set timer for mode setting operation duration
state_x <= RW;
-----------------------------------------------------------
-- process read/write/refresh operations after initialization is done
-----------------------------------------------------------
when RW =>
-----------------------------------------------------------
-- highest priority operation: row refresh
-- do a refresh operation if the refresh counter is non-zero
-----------------------------------------------------------
if rfshCntr_r /= 0 then
-- wait for any row activations, writes or reads to finish before doing a precharge
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation
state_x <= REFRESHROW; -- refresh the SDRAM after the precharge
end if;
-----------------------------------------------------------
-- do a host-initiated read operation
-----------------------------------------------------------
elsif rd = YES then
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
-- This gives extra time for the row activation circuitry.
if (true) then
-- activate a new row if the current read is outside the active row or bank
if doActivate = YES then
-- activate new row only if all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation
state_x <= ACTIVATE; -- activate the new row after the precharge is done
end if;
-- read from the currently active row if no previous read operation
-- is in progress or if pipeline reads are enabled
-- we can always initiate a read even if a write is already in progress
elsif (rdInProgress = NO) then
cmd_x <= READ_CMD; -- initiate a read of the SDRAM
-- insert a flag into the pipeline shift register that will exit the end
-- of the shift register when the data from the SDRAM is available
rdPipeline_x <= READ & rdPipeline_r(rdPipeline_r'high downto 1);
end if;
end if;
-----------------------------------------------------------
-- do a host-initiated write operation
-----------------------------------------------------------
elsif wr = YES then
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
-- This gives extra time for the row activation circuitry.
if (true) then
-- activate a new row if the current write is outside the active row or bank
if doActivate = YES then
-- activate new row only if all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation
state_x <= ACTIVATE; -- activate the new row after the precharge is done
end if;
-- write to the currently active row if no previous read operations are in progress
elsif rdInProgress = NO then
cmd_x <= WRITE_CMD; -- initiate the write operation
sDataDir_x <= OUTPUT; -- turn on drivers to send data to SDRAM
-- set timer so precharge doesn't occur too soon after write operation
wrTimer_x <= WR_CYCLES;
-- insert a flag into the 1-bit pipeline shift register that will exit on the
-- next cycle. The write into SDRAM is not actually done by that time, but
-- this doesn't matter to the host
wrPipeline_x(0) <= WRITE;
end if;
end if;
-----------------------------------------------------------
-- do a host-initiated self-refresh operation
-----------------------------------------------------------
elsif doSelfRfsh = YES then
-- wait until all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation
state_x <= SELFREFRESH; -- self-refresh the SDRAM after the precharge
end if;
-----------------------------------------------------------
-- no operation
-----------------------------------------------------------
else
state_x <= RW; -- continue to look for SDRAM operations to execute
end if;
-----------------------------------------------------------
-- activate a row of the SDRAM
-----------------------------------------------------------
when ACTIVATE =>
cmd_x <= ACTIVE_CMD;
sAddr_x <= (others => '0'); -- output the address for the row to be activated
sAddr_x(row'range) <= row;
activeBank_x <= bank;
activeRow_x(bankIndex) <= row; -- store the new active SDRAM row address
activeFlag_x(bankIndex) <= YES; -- the SDRAM is now active
rasTimer_x <= RAS_CYCLES; -- minimum time before another precharge can occur
timer_x <= RCD_CYCLES; -- minimum time before a read/write operation can occur
state_x <= RW; -- return to do read/write operation that initiated this activation
-----------------------------------------------------------
-- refresh a row of the SDRAM
-----------------------------------------------------------
when REFRESHROW =>
cmd_x <= RFSH_CMD;
timer_x <= RFC_CYCLES; -- refresh operation interval
rfshCntr_x <= rfshCntr_r - 1; -- decrement the number of needed row refreshes
state_x <= RW; -- process more SDRAM operations after refresh is done
-----------------------------------------------------------
-- place the SDRAM into self-refresh and keep it there until further notice
-----------------------------------------------------------
when SELFREFRESH =>
if (doSelfRfsh = YES) then
-- keep the SDRAM in self-refresh mode as long as requested and until there is a stable clock
cmd_x <= RFSH_CMD; -- output the refresh command; this is only needed on the first clock cycle
cke_x <= NO; -- disable the SDRAM clock
else
-- else exit self-refresh mode and start processing read and write operations
cke_x <= YES; -- restart the SDRAM clock
rfshCntr_x <= 0; -- no refreshes are needed immediately after leaving self-refresh
activeFlag_x <= (others => NO); -- self-refresh deactivates all rows
timer_x <= XSR_CYCLES; -- wait this long until read and write operations can resume
state_x <= RW;
end if;
-----------------------------------------------------------
-- unknown state
-----------------------------------------------------------
when others =>
state_x <= INITWAIT; -- reset state if in erroneous state
end case;
end if;
end process combinatorial;
-----------------------------------------------------------
-- update registers on the appropriate clock edge
-----------------------------------------------------------
update : process(clk_ok, clk)
begin
if clk_ok = NO then
-- asynchronous reset
state_r <= INITWAIT;
activeFlag_r <= (others => NO);
rfshCntr_r <= 0;
timer_r <= 0;
refTimer_r <= REF_CYCLES;
rasTimer_r <= 0;
wrTimer_r <= 0;
nopCntr_r <= 0;
rdPipeline_r <= (others => '0');
wrPipeline_r <= (others => '0');
cke_r <= NO;
cmd_r <= NOP_CMD;
ba_r <= (others => '0');
sAddr_r <= (others => '0');
sData_r <= (others => '0');
sDataDir_r <= INPUT;
hDOut_r <= (others => '0');
elsif rising_edge(clk) then
state_r <= state_x;
activeBank_r <= activeBank_x;
activeRow_r <= activeRow_x;
activeFlag_r <= activeFlag_x;
rfshCntr_r <= rfshCntr_x;
timer_r <= timer_x;
refTimer_r <= refTimer_x;
rasTimer_r <= rasTimer_x;
wrTimer_r <= wrTimer_x;
nopCntr_r <= nopCntr_x;
rdPipeline_r <= rdPipeline_x;
wrPipeline_r <= wrPipeline_x;
cke_r <= cke_x;
cmd_r <= cmd_x;
ba_r <= ba_x;
sAddr_r <= sAddr_x;
sData_r <= sData_x;
sDataDir_r <= sDataDir_x;
hDOut_r <= hDOut_x;
end if;
end process update;
end arch;
| bsd-2-clause |
dpolad/dlx | DLX_synth/a.f-DECODEBLOCK.vhd | 2 | 3973 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
--TODO: add some comments in signal assignment
entity jump_logic is
generic (
SIZE : integer := 32
);
port (
NPCF_i : in std_logic_vector(SIZE - 1 downto 0);
IR_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
A_o : out std_logic_vector(SIZE - 1 downto 0);
rA_o : out std_logic_vector(4 downto 0);
rB_o : out std_logic_vector(4 downto 0);
rC_o : out std_logic_vector(4 downto 0);
branch_target_o : out std_logic_vector(SIZE - 1 downto 0);
sum_addr_o : out std_logic_vector(SIZE - 1 downto 0);
extended_imm : out std_logic_vector(SIZE - 1 downto 0);
taken_o : out std_logic; --was the branch taken or not?
FW_X_i : in std_logic_vector(SIZE - 1 downto 0);
FW_W_i : in std_logic_vector(SIZE - 1 downto 0);
S_FW_Adec_i : in std_logic_vector(1 downto 0);
S_EXT_i : in std_logic;
S_EXT_SIGN_i : in std_logic;
S_MUX_LINK_i : in std_logic;
S_EQ_NEQ_i : in std_logic
);
end jump_logic;
architecture struct of jump_logic is
-- component basicadd
-- port(
-- IN1 : in unsigned(SIZE - 1 downto 0);
-- IN2 : in unsigned(SIZE - 1 downto 0);
-- OUT1 : out unsigned(SIZE - 1 downto 0)
-- );
-- end component;
component p4add
generic (
N : integer := 32;
logN : integer := 5);
Port (
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
Cin : in std_logic;
sign : In std_logic;
S : out std_logic_vector(N-1 downto 0);
Cout : out std_logic);
end component;
component mux21
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component mux41
generic (
MUX_SIZE : integer :=5
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end component;
component extender_32
port(
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0 extend on 16 bits , when 1 extend on 26 bits
SIGN : in std_logic; -- when 0 unsigned, when 1 signed
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component zerocheck
port(
IN0 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0, out 1 if not equal . when 1 out 1 if equal
OUT1 : out std_logic
);
end component;
component add4
port(
IN1 : in unsigned(SIZE - 1 downto 0);
OUT1 : out unsigned(SIZE - 1 downto 0)
);
end component;
signal ext_imm : std_logic_vector (SIZE - 1 downto 0);
signal sum_addr : std_logic_vector(SIZE - 1 downto 0);
signal branch_sel : std_logic;
signal FW_MUX_OUT : std_logic_vector(SIZE - 1 downto 0);
begin
EXTENDER: extender_32 port map(
IN1 => IR_i,
CTRL => S_EXT_i,
SIGN => S_EXT_SIGN_i,
OUT1 => ext_imm);
JUMPADDER: p4add
generic map (
N => 32,
logN => 5
)
port map (
A => NPCF_i,
B => ext_imm,
Cin => '0',
sign => '0',
S => sum_addr,
Cout => open
);
BRANCHMUX: mux21 port map(
IN0 => sum_addr,
IN1 => NPCF_i,
CTRL => branch_sel,
OUT1 => branch_target_o);
ZC: zerocheck port map(
IN0 => FW_MUX_OUT,
CTRL => S_EQ_NEQ_i,
OUT1 => branch_sel);
MUXLINK: mux21 port map(
IN0 => ext_imm,
IN1 => NPCF_i,
CTRL => S_MUX_LINK_i,
OUT1 => extended_imm);
MUX_FWA: mux41
generic map(
MUX_SIZE => 32
)
port map(
IN0 => A_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => "00000000000000000000000000000000",
CTRL => S_FW_Adec_i,
OUT1 => FW_MUX_OUT
);
rA_o <= IR_i(25 downto 21);
rB_o <= IR_i(20 downto 16);
rC_o <= IR_i(15 downto 11);
A_o <= FW_MUX_OUT;
sum_addr_o <= sum_addr;
taken_o <= not(branch_sel);
end struct;
| bsd-2-clause |
dpolad/dlx | DLX_synth/a.i.a.a.b-PISOR2.vhd | 2 | 650 | library ieee;
use ieee.std_logic_1164.all;
entity piso_r_2 is
generic(
N : natural := 8
);
port(
Clock : in std_logic;
ALOAD : in std_logic;
D : in std_logic_vector(N-1 downto 0);
SO : out std_logic_vector(N-1 downto 0)
);
end piso_r_2;
architecture archi of piso_r_2 is
signal tmp: std_logic_vector(N-1 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if (ALOAD='1') then
tmp <= D;
else
tmp <= tmp(N-3 downto 0) & "00";
end if;
end if;
end process;
SO <= tmp;
end archi;
| bsd-2-clause |
dpolad/dlx | DLX_synth/a.f.b-EXTENDER32.vhd | 2 | 890 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity extender_32 is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0 extend on 16 bits , when 1 extend on 26 bits
SIGN : in std_logic; -- when 0 unsigned, when 1 signed
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end extender_32;
architecture Bhe of extender_32 is
signal TEMP16 : std_logic_vector(15 downto 0);
signal TEMP26 : std_logic_vector(25 downto 0);
begin
TEMP16 <= IN1(15 downto 0);
TEMP26 <= IN1(25 downto 0);
OUT1 <= std_logic_vector(resize(signed(TEMP26),SIZE)) when CTRL = '1' else
std_logic_vector(resize(signed(TEMP16),SIZE)) when CTRL = '0' and SIGN = '1' else
std_logic_vector(resize(unsigned(TEMP16),SIZE)); -- CTRL = 0 SIGN = 0
end Bhe;
| bsd-2-clause |
dpolad/dlx | DLX_synth/a.i.a.d.b.a-CARRYSELGEN.vhd | 2 | 1428 | library ieee;
use ieee.std_logic_1164.all;
entity carry_sel_gen is
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end carry_sel_gen;
architecture STRUCTURAL of carry_sel_gen is
component rca
generic ( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end component;
component mux21
generic (
SIZE : integer
);
Port ( IN0: In std_logic_vector(N-1 downto 0);
IN1: In std_logic_vector(N-1 downto 0);
CTRL: In std_logic;
OUT1: Out std_logic_vector(N-1 downto 0));
end component;
constant zero : std_logic := '0';
constant one : std_logic := '1';
signal nocarry_sum_to_mux : std_logic_vector(N-1 downto 0);
signal carry_sum_to_mux : std_logic_vector(N-1 downto 0);
signal carry_carry_out : std_logic;
signal nocarry_carry_out : std_logic;
begin
rca_nocarry : rca
generic map (N => N)
port map (A,B,zero,nocarry_sum_to_mux,nocarry_carry_out);
rca_carry : rca
generic map (N => N)
port map (A,B,one,carry_sum_to_mux,carry_carry_out);
outmux : mux21
generic map (SIZE => N)
port map (nocarry_sum_to_mux,carry_sum_to_mux,Ci,S);
end STRUCTURAL;
| bsd-2-clause |
dpolad/dlx | DLX_synth/a.a-CU_HW.vhd | 1 | 13251 | -- *** a.a-CU-HW.vhd *** --
-- this block is describes the control unit.
-- This is a Hardwired control unit
-- Microcode LUT is declared directly here
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.myTypes.all;
entity dlx_cu is
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer := 6; -- Op Code Size
IR_SIZE : integer := 32; -- Instruction Register Size
CW_SIZE : integer := 13); -- Control Word Size
port (
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset: Active-High
IR_IN : in std_logic_vector(IR_SIZE - 1 downto 0); -- Instruction Register
stall_exe_i : in std_logic; -- Stall signal coming from EXE stage
mispredict_i : in std_logic;
D1_i : in std_logic_vector(4 downto 0); -- Destination register of exe stage
D2_i : in std_logic_vector(4 downto 0); -- Destination register of mem stage
S1_LATCH_EN : out std_logic; -- Latch enable of Fetch stage
S2_LATCH_EN : out std_logic; -- Latch enable of Dec stage
S3_LATCH_EN : out std_logic; -- Latch enable of Exe stage
S_MUX_PC_BUS : out std_logic_vector(1 downto 0); -- Control of mux to PC
S_EXT : out std_logic; -- Control of extender
S_EXT_SIGN : out std_logic; -- Control of extender sign
S_EQ_NEQ : out std_logic; -- Control of Comparator
S_MUX_DEST : out std_logic_vector(1 downto 0); -- Control of Destination register
S_MUX_LINK : out std_logic; -- Control of link mux
S_MUX_MEM : out std_logic; -- Control of mux to memory address
S_MEM_W_R : out std_logic; -- Control of mem W/R
S_MEM_EN : out std_logic; -- Control mem enable
S_RF_W_wb : out std_logic; -- Control WB enable
S_RF_W_mem : out std_logic; -- Current op in mem is going to write on wb?
S_RF_W_exe : out std_logic; -- Current op in exe is going to write on wb?
S_MUX_ALUIN : out std_logic; -- Control ALU input ( IMM or B )
stall_exe_o : out std_logic; -- Stall exe stage
stall_dec_o : out std_logic; -- Stall dec stage
stall_fetch_o : out std_logic; -- Stall fetch stage
stall_btb_o : out std_logic; -- Stall btb
was_branch_o : out std_logic; -- Op in decode is a branch or not?
was_jmp_o : out std_logic;
ALU_WORD_o : out std_logic_vector(12 downto 0); -- Opcode to ALU
ALU_OPCODE : out aluOp -- Opcode to ALU
);
end dlx_cu;
architecture dlx_cu_hw of dlx_cu is
-- ***************************
-- *** SIGNAL DECLARATIONS ***
-- ***************************
-- this is the microcode memory, it works as a LUT -> to decode an instruction it's opcode indexes this memory
signal IR_opcode : std_logic_vector(OP_CODE_SIZE -1 downto 0); -- OpCode part of IR
signal IR_func : std_logic_vector(FUNC_SIZE -1 downto 0); -- Func part of IR when Rtype
signal cw_d : std_logic_vector(CW_SIZE - 1 downto 0);
signal cw_from_mem : std_logic_vector(CW_SIZE - 1 downto 0); -- full control word read from cw_mem
-- control word is shifted to the correct stage
signal cw_e : std_logic_vector(CW_SIZE - 1 - 6 downto 0); -- second stage
signal cw_m : std_logic_vector(CW_SIZE - 1 - 9 downto 0); -- third stage
signal cw_w : std_logic_vector(CW_SIZE - 1 - 12 downto 0); -- fourth stage
signal aluOpcode_d : aluOp := NOP; -- ALUOP defined in package -- ! MIGHT NOT BE SYNTHESIZABLE
signal aluOpcode_e : aluOp := NOP; -- shifted ALUOP to feed execute stage -- ! MIGHT NOT BE SYNTHESIZABLE
signal S_MEM_LOAD : std_logic; -- is current op in mem stage a LOAD?
signal S_EXE_LOAD : std_logic; -- is current op in exe stage a LOAD?
-- stall signals from stall unit
signal stall_exe_o_TEMP : std_logic;
signal stall_dec_o_TEMP : std_logic;
signal stall_btb_o_TEMP : std_logic;
signal stall_fetch_o_TEMP : std_logic;
signal bubble_dec : std_logic; -- transform next op in decode into a NOP
signal next_bubble_dec : std_logic;
signal bubble_exe : std_logic; -- transform next op in exe into a NOP
signal next_bubble_exe : std_logic;
-- ********************************
-- *** COMPONENTS DECLARATION ***
-- ********************************
component cw_mem is
generic (
MICROCODE_MEM_SIZE : integer; -- Microcode Memory Size
OP_CODE_SIZE : integer; -- Op Code Size
CW_SIZE : integer -- Control Word Size
);
port (
OPCODE_IN : in std_logic_vector(OP_CODE_SIZE - 1 downto 0); -- Instruction Register
CW_OUT : out std_logic_vector(CW_SIZE - 1 downto 0)
);
end component;
component alu_ctrl is
port (
OP : in AluOp;
ALU_WORD : out std_logic_vector(12 downto 0)
);
end component;
-- instantiation of stall_logic block
component stall_logic is
generic (
FUNC_SIZE : integer; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer -- Op Code Size
);
port (
-- Instruction Register
OPCODE_i : in std_logic_vector(OP_CODE_SIZE-1 downto 0);
FUNC_i : in std_logic_vector(FUNC_SIZE-1 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
D1_i : in std_logic_vector(4 downto 0); -- taken from output of destination mux in EXE stage
D2_i : in std_logic_vector(4 downto 0);
S_mem_LOAD_i : in std_logic;
S_exe_LOAD_i : in std_logic;
S_exe_WRITE_i : in std_logic;
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
mispredict_i : in std_logic;
bubble_dec_o : out std_logic;
bubble_exe_o : out std_logic;
stall_exe_o : out std_logic;
stall_dec_o : out std_logic;
stall_btb_o : out std_logic;
stall_fetch_o : out std_logic
);
end component;
begin
-- ********************************
-- *** COMPONENTS INSTANTIATION ***
-- ********************************
STALL_L : stall_logic
generic map (
FUNC_SIZE => 11,
OP_CODE_SIZE => 6
)
port map(
-- Instruction Register
OPCODE_i => IR_opcode,
FUNC_i => IR_func,
rA_i => IR_IN(25 downto 21),
rB_i => IR_IN(20 downto 16),
D1_i => D1_i,
D2_i => D2_i,
S_mem_LOAD_i => S_MEM_LOAD,
S_exe_LOAD_i => S_EXE_LOAD,
S_exe_WRITE_i => cw_e(CW_SIZE - 13),
S_MUX_PC_BUS_i => cw_d(CW_SIZE - 1 downto CW_SIZE - 2),
mispredict_i => mispredict_i,
bubble_dec_o => next_bubble_dec,
bubble_exe_o => next_bubble_exe,
stall_exe_o => stall_exe_o_TEMP,
stall_dec_o => stall_dec_o_TEMP,
stall_btb_o => stall_btb_o_TEMP,
stall_fetch_o => stall_fetch_o_TEMP
);
CWM : cw_mem
generic map(
MICROCODE_MEM_SIZE => MICROCODE_MEM_SIZE,
OP_CODE_SIZE => OP_CODE_SIZE,
CW_SIZE => CW_SIZE
)
port map(
OPCODE_IN => IR_opcode,
CW_OUT => cw_from_mem
);
ALU_C: alu_ctrl
port map(
OP => aluopcode_d,
ALU_WORD => ALU_WORD_o
);
-- stall signals for each individual stage of the pipeline
-- an OR is needed cause a stall might come from ALU too
stall_exe_o <= stall_exe_i or stall_exe_o_TEMP;
stall_dec_o <= stall_exe_i or stall_dec_o_TEMP;
stall_fetch_o <= stall_exe_i or stall_fetch_o_TEMP;
stall_btb_o <= stall_exe_i or stall_btb_o_TEMP;
-- split function in OPCODE and FUNC
IR_opcode(5 downto 0) <= IR_IN(31 downto 26);
IR_func(10 downto 0) <= IR_IN(FUNC_SIZE - 1 downto 0);
-- control work is assigned to the word looked up in microcode memory
-- in case of bubble_dec, a NOP cw is fed instead
cw_d <= cw_from_mem when bubble_dec = '0' else "0000000000000";
-- *** ATM THE LATCH ENABLES ARE DOING NOTHING! EVERYTHING IS CONTROLLED BY STALL ***
S1_LATCH_EN <= '1';
S2_LATCH_EN <= '1';
S3_LATCH_EN <= '1';
-- DEC stage control signals
S_MUX_PC_BUS <= cw_d(CW_SIZE - 1 downto CW_SIZE - 2);
S_EXT <= cw_d(CW_SIZE - 3);
S_EXT_SIGN <= cw_d(CW_SIZE - 4);
S_EQ_NEQ <= cw_d(CW_SIZE - 5);
S_MUX_LINK <= cw_d(CW_SIZE - 6);
-- EXE stage control signals
S_MUX_ALUIN <= cw_e(CW_SIZE - 7);
S_MUX_DEST <= cw_e(CW_SIZE - 8 downto CW_SIZE - 9);
-- MEM stage control signals
S_MEM_EN <= cw_m(CW_SIZE - 10);
S_MEM_W_R <= cw_m(CW_SIZE - 11);
S_MUX_MEM <= cw_m(CW_SIZE - 12);
-- WB stage control signals
S_RF_W_wb <= cw_w(CW_SIZE - 13);
-- RF write signal is sent to other stages to compute hazards/forwarding
S_RF_W_mem <= cw_m(CW_SIZE - 13);
S_RF_W_exe <= cw_e(CW_SIZE - 13);
-- is the current op in mem stage a LOAD?
S_MEM_LOAD <= cw_m(CW_SIZE - 10) and (not cw_m(CW_SIZE - 11));
-- is the current op in exe stage a LOAD?
S_EXE_LOAD <= cw_e(CW_SIZE - 10) and (not cw_e(CW_SIZE - 11));
-- is current op in DEC stage a branch?
was_branch_o <= cw_d(CW_SIZE - 1) and cw_d(CW_SIZE - 2);
-- is current op in DEC stage an inconditional jump?
was_jmp_o <= cw_d(CW_SIZE - 1) xor cw_d(CW_SIZE - 2);
ALU_OPCODE <= aluOpcode_e;
-- ********************************
-- *** PROCESSES ***
-- ********************************
-- sequential process to manage and pipeline control words
CW_PIPE: process (Clk, Rst)
begin -- process Clk
if Rst = '1' then -- asynchronous reset (active high)
cw_e <= (others => '0');
cw_m <= (others => '0');
cw_w <= (others => '0');
aluOpcode_e <= NOP;
elsif Clk'event and Clk = '1' then -- rising clock edge
-- update of the bubbe signal
-- bubble means: cancel next operation and make it a nop ( used in case of misprediction or inconditional jumps)
bubble_dec <= next_bubble_dec;
bubble_exe <= next_bubble_exe;
-- EXE stalled
if stall_exe_i = '1' or stall_exe_o_TEMP = '1' then
cw_m <= "0000"; -- NOP instertion
cw_e <= cw_e;
aluOpcode_e <= aluOpcode_e;
-- DEC stalled
elsif stall_dec_o_TEMP = '1' then
cw_e <= "0000000"; -- NOP instertion
cw_m <= cw_e(CW_SIZE - 1 - 9 downto 0);
-- no stall
else
cw_e <= cw_d(CW_SIZE - 1 - 6 downto 0);
cw_m <= cw_e(CW_SIZE - 1 - 9 downto 0);
aluOpcode_e <= aluOpcode_d;
end if;
-- WB cannot be stalled
cw_w <= cw_m(CW_SIZE - 1 - 12 downto 0);
end if;
end process CW_PIPE;
-- combinatorial process to generate ALU OP CODES
ALU_OP_CODE_P : process (IR_opcode, IR_func)
begin
case conv_integer(unsigned(IR_opcode)) is
-- case of R type requires analysis of FUNC
when 0 =>
case conv_integer(unsigned(IR_func)) is
when 4 => aluOpcode_d <= SLLS; -- sll according to instruction set coding
when 6 => aluOpcode_d <= SRLS;
when 7 => aluOpcode_d <= SRAS;
when 32 => aluOpcode_d <= ADDS;
when 33 => aluOpcode_d <= ADDUS;
when 34 => aluOpcode_d <= SUBS;
when 35 => aluOpcode_d <= SUBUS;
when 36 => aluOpcode_d <= ANDS;
when 37 => aluOpcode_d <= ORS;
when 38 => aluOpcode_d <= XORS;
when 40 => aluOpcode_d <= SEQS;
when 41 => aluOpcode_d <= SNES;
when 42 => aluOpcode_d <= SLTS;
when 43 => aluOpcode_d <= SGTS;
when 44 => aluOpcode_d <= SLES;
when 45 => aluOpcode_d <= SGES;
when 48 => aluOpcode_d <= MOVI2SS;
when 49 => aluOpcode_d <= MOVS2IS;
when 50 => aluOpcode_d <= MOVFS;
when 51 => aluOpcode_d <= MOVDS;
when 52 => aluOpcode_d <= MOVFP2IS;
when 53 => aluOpcode_d <= MOVI2FP;
when 54 => aluOpcode_d <= MOVI2TS;
when 55 => aluOpcode_d <= MOVT2IS;
when 58 => aluOpcode_d <= SLTUS;
when 59 => aluOpcode_d <= SGTUS;
when 60 => aluOpcode_d <= SLEUS;
when 61 => aluOpcode_d <= SGEUS;
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
-- type F instruction case -- MULT only at the moment
when 1 =>
case conv_integer(unsigned(IR_func)) is
when 22 => aluOpcode_d <= MULTU;
when 14 => aluOpcode_d <= MULTS;
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
-- I-TYPE instructions
when 2 => aluOpcode_d <= NOP; -- j
when 3 => aluOpcode_d <= NOP; -- jal
when 4 => aluOpcode_d <= NOP; -- beqz
when 5 => aluOpcode_d <= NOP; -- bnez
when 8 => aluOpcode_d <= ADDS; -- addi
when 9 => aluOpcode_d <= ADDUS; -- addui
when 10 => aluOpcode_d <= SUBS; -- subi
when 11 => aluOpcode_d <= SUBUS; -- subui
when 12 => aluOpcode_d <= ANDS; -- andi
when 13 => aluOpcode_d <= ORS; -- ori
when 14 => aluOpcode_d <= XORS; -- xori
when 18 => aluOpcode_d <= NOP; -- jr
when 19 => aluOpcode_d <= NOP; -- jalr
when 20 => aluOpcode_d <= SLLS; -- slli
when 21 => aluOpcode_d <= NOP; -- nop
when 22 => aluOpcode_d <= SRLS; -- srli
when 23 => aluOpcode_d <= SRAS; -- srai
when 24 => aluOpcode_d <= SEQS; -- seqi
when 25 => aluOpcode_d <= SNES; -- snei
when 26 => aluOpcode_d <= SLTS; -- slti
when 27 => aluOpcode_d <= SGTS; -- sgti
when 28 => aluOpcode_d <= SLES; -- slei
when 29 => aluOpcode_d <= SGES; -- sgei
when 35 => aluOpcode_d <= ADDS; -- lw
when 43 => aluOpcode_d <= ADDS; -- sw
when 58 => aluOpcode_d <= SLTUS; -- sltui
when 59 => aluOpcode_d <= SGTUS; -- sgtui
when 60 => aluOpcode_d <= SLEUS; -- sleui
when 61 => aluOpcode_d <= SGEUS; -- sgeui
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
end process ALU_OP_CODE_P;
end dlx_cu_hw;
| bsd-2-clause |
dpolad/dlx | DLX_vhd/003-FF32_EN_IR.vhd | 2 | 597 |
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity ff32_en_IR is
generic (
SIZE : integer := 32
);
PORT(
D : in std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic;
Q : out std_logic_vector(SIZE - 1 downto 0)
);
end ff32_en_IR;
architecture behavioral of ff32_en_IR is
begin
process(clk,rst)
begin
if(rst='1') then
Q <= X"54000000";
else
if(clk='1' and clk'EVENT) then
if en = '1' then
Q <= D;
end if;
end if;
end if;
end process;
end behavioral;
| bsd-2-clause |
dpolad/dlx | DLX_synth/a.i.a.b.b-T2LEVEL2.vhd | 2 | 690 | library ieee;
use ieee.std_logic_1164.all;
use work.myTypes.all;
--00 mask00
--01 mask08
--10 mask16
entity shift_secondLevel is
port(sel : in std_logic_vector(1 downto 0);
mask00 : in std_logic_vector(38 downto 0);
mask08 : in std_logic_vector(38 downto 0);
mask16 : in std_logic_vector(38 downto 0);
Y : out std_logic_vector(38 downto 0));
end shift_secondLevel;
architecture behav of shift_secondLevel is
begin
process(sel, mask00, mask08, mask16)
begin
case sel is
when "00" =>
Y <= mask00;
when "01" =>
Y <= mask08;
when "10" =>
Y <= mask16;
when others => Y <= x"000000000" & "000";
end case;
end process;
end behav;
| bsd-2-clause |
dpolad/dlx | DLX_synth/postsynth/execute_block_1300.vhdl | 1 | 449069 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_execute_block is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
type aluOp is (NOP, SLLS, SRLS, SRAS, ADDS, ADDUS, SUBS, SUBUS, ANDS, ORS,
XORS, SEQS, SNES, SLTS, SGTS, SLES, SGES, MOVI2SS, MOVS2IS, MOVFS, MOVDS,
MOVFP2IS, MOVI2FP, MOVI2TS, MOVT2IS, SLTUS, SGTUS, SLEUS, SGEUS, MULTU,
MULTS);
attribute ENUM_ENCODING of aluOp : type is
"00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110";
-- Declarations for conversion functions.
function aluOp_to_std_logic_vector(arg : in aluOp) return std_logic_vector;
end CONV_PACK_execute_block;
package body CONV_PACK_execute_block is
-- enum type to std_logic_vector function
function aluOp_to_std_logic_vector(arg : in aluOp) return std_logic_vector
is
-- synopsys built_in SYN_FEED_THRU;
begin
case arg is
when NOP => return "00000";
when SLLS => return "00001";
when SRLS => return "00010";
when SRAS => return "00011";
when ADDS => return "00100";
when ADDUS => return "00101";
when SUBS => return "00110";
when SUBUS => return "00111";
when ANDS => return "01000";
when ORS => return "01001";
when XORS => return "01010";
when SEQS => return "01011";
when SNES => return "01100";
when SLTS => return "01101";
when SGTS => return "01110";
when SLES => return "01111";
when SGES => return "10000";
when MOVI2SS => return "10001";
when MOVS2IS => return "10010";
when MOVFS => return "10011";
when MOVDS => return "10100";
when MOVFP2IS => return "10101";
when MOVI2FP => return "10110";
when MOVI2TS => return "10111";
when MOVT2IS => return "11000";
when SLTUS => return "11001";
when SGTUS => return "11010";
when SLEUS => return "11011";
when SGEUS => return "11100";
when MULTU => return "11101";
when MULTS => return "11110";
when others => assert FALSE -- this should not happen.
report "un-convertible value"
severity warning;
return "00000";
end case;
end;
end CONV_PACK_execute_block;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_63 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_63;
architecture SYN_BEHAVIORAL of FA_63 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_62 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_62;
architecture SYN_BEHAVIORAL of FA_62 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_61 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_61;
architecture SYN_BEHAVIORAL of FA_61 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_60 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_60;
architecture SYN_BEHAVIORAL of FA_60 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_59 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_59;
architecture SYN_BEHAVIORAL of FA_59 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3, n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : OR2_X1 port map( A1 => B, A2 => A, ZN => n5);
U3 : NAND2_X1 port map( A1 => Ci, A2 => n5, ZN => n3);
U4 : NAND2_X1 port map( A1 => n3, A2 => n4, ZN => Co);
U5 : NAND2_X1 port map( A1 => B, A2 => A, ZN => n4);
U6 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_58 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_58;
architecture SYN_BEHAVIORAL of FA_58 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n4, A2 => n5, ZN => Co);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n5);
U4 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n4);
U5 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_57 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_57;
architecture SYN_BEHAVIORAL of FA_57 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_56 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_56;
architecture SYN_BEHAVIORAL of FA_56 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_55 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_55;
architecture SYN_BEHAVIORAL of FA_55 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_54 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_54;
architecture SYN_BEHAVIORAL of FA_54 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_53 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_53;
architecture SYN_BEHAVIORAL of FA_53 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_52 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_52;
architecture SYN_BEHAVIORAL of FA_52 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_51 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_51;
architecture SYN_BEHAVIORAL of FA_51 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_50 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_50;
architecture SYN_BEHAVIORAL of FA_50 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_49 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_49;
architecture SYN_BEHAVIORAL of FA_49 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_48 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_48;
architecture SYN_BEHAVIORAL of FA_48 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => A, B => B, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_47 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_47;
architecture SYN_BEHAVIORAL of FA_47 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n5, n6, n7 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n6, A2 => n5, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n7, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n7);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n5);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_46 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_46;
architecture SYN_BEHAVIORAL of FA_46 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_45 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_45;
architecture SYN_BEHAVIORAL of FA_45 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_44 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_44;
architecture SYN_BEHAVIORAL of FA_44 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => A, B => B, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_43 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_43;
architecture SYN_BEHAVIORAL of FA_43 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_42 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_42;
architecture SYN_BEHAVIORAL of FA_42 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_41 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_41;
architecture SYN_BEHAVIORAL of FA_41 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_40 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_40;
architecture SYN_BEHAVIORAL of FA_40 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => B, B => A, Z => S);
U2 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_39 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_39;
architecture SYN_BEHAVIORAL of FA_39 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_38 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_38;
architecture SYN_BEHAVIORAL of FA_38 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_37 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_37;
architecture SYN_BEHAVIORAL of FA_37 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n4, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_36 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_36;
architecture SYN_BEHAVIORAL of FA_36 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_35 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_35;
architecture SYN_BEHAVIORAL of FA_35 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_34 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_34;
architecture SYN_BEHAVIORAL of FA_34 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_33 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_33;
architecture SYN_BEHAVIORAL of FA_33 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n4, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_32 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_32;
architecture SYN_BEHAVIORAL of FA_32 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => B, B => A, Z => S);
U2 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_31 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_31;
architecture SYN_BEHAVIORAL of FA_31 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_30 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_30;
architecture SYN_BEHAVIORAL of FA_30 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U4 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_29 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_29;
architecture SYN_BEHAVIORAL of FA_29 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_28 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_28;
architecture SYN_BEHAVIORAL of FA_28 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_27 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_27;
architecture SYN_BEHAVIORAL of FA_27 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_26 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_26;
architecture SYN_BEHAVIORAL of FA_26 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U4 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_25 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_25;
architecture SYN_BEHAVIORAL of FA_25 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_24 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_24;
architecture SYN_BEHAVIORAL of FA_24 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_23 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_23;
architecture SYN_BEHAVIORAL of FA_23 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : OAI21_X1 port map( B1 => B, B2 => A, A => Ci, ZN => n5);
U4 : XNOR2_X1 port map( A => A, B => B, ZN => n6);
U5 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_22 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_22;
architecture SYN_BEHAVIORAL of FA_22 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_21 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_21;
architecture SYN_BEHAVIORAL of FA_21 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_20 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_20;
architecture SYN_BEHAVIORAL of FA_20 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_19 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_19;
architecture SYN_BEHAVIORAL of FA_19 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : OAI21_X1 port map( B1 => B, B2 => A, A => Ci, ZN => n5);
U2 : XNOR2_X1 port map( A => A, B => B, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_18 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_18;
architecture SYN_BEHAVIORAL of FA_18 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_17 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_17;
architecture SYN_BEHAVIORAL of FA_17 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_16 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_16;
architecture SYN_BEHAVIORAL of FA_16 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_15 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_15;
architecture SYN_BEHAVIORAL of FA_15 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_14 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_14;
architecture SYN_BEHAVIORAL of FA_14 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_13 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_13;
architecture SYN_BEHAVIORAL of FA_13 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_12 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_12;
architecture SYN_BEHAVIORAL of FA_12 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_11 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_11;
architecture SYN_BEHAVIORAL of FA_11 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_10 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_10;
architecture SYN_BEHAVIORAL of FA_10 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_9 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_9;
architecture SYN_BEHAVIORAL of FA_9 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_8 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_8;
architecture SYN_BEHAVIORAL of FA_8 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_7 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_7;
architecture SYN_BEHAVIORAL of FA_7 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_6 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_6;
architecture SYN_BEHAVIORAL of FA_6 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_5 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_5;
architecture SYN_BEHAVIORAL of FA_5 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_4 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_4;
architecture SYN_BEHAVIORAL of FA_4 is
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_3 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_3;
architecture SYN_BEHAVIORAL of FA_3 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_2 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_2;
architecture SYN_BEHAVIORAL of FA_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_1 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_1;
architecture SYN_BEHAVIORAL of FA_1 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_7 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_7;
architecture SYN_Bhe of mux21_SIZE4_7 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_6 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_6;
architecture SYN_Bhe of mux21_SIZE4_6 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_5 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_5;
architecture SYN_Bhe of mux21_SIZE4_5 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_4 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_4;
architecture SYN_Bhe of mux21_SIZE4_4 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_3 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_3;
architecture SYN_Bhe of mux21_SIZE4_3 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n1, n2, n3, n4, n5 : std_logic;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : INV_X1 port map( A => IN0(0), ZN => n2);
U4 : OR2_X1 port map( A1 => CTRL, A2 => n4, ZN => n1);
U5 : NAND2_X1 port map( A1 => n1, A2 => n5, ZN => OUT1(1));
U6 : INV_X1 port map( A => IN0(1), ZN => n4);
U7 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(0), ZN => n3);
U8 : OAI21_X1 port map( B1 => CTRL, B2 => n2, A => n3, ZN => OUT1(0));
U9 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(1), ZN => n5);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_2 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_2;
architecture SYN_Bhe of mux21_SIZE4_2 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U4 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_1 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_1;
architecture SYN_Bhe of mux21_SIZE4_1 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U2 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U3 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U4 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_15 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_15;
architecture SYN_STRUCTURAL of RCA_N4_15 is
component FA_57
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_58
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_59
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_60
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561359 : std_logic;
begin
FAI_1 : FA_60 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_59 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_58 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_57 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561359);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_14 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_14;
architecture SYN_STRUCTURAL of RCA_N4_14 is
component FA_53
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_54
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_55
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_56
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561358 : std_logic;
begin
FAI_1 : FA_56 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_55 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_54 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_53 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561358);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_13 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_13;
architecture SYN_STRUCTURAL of RCA_N4_13 is
component FA_49
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_50
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_51
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_52
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561357 : std_logic;
begin
FAI_1 : FA_52 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_51 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_50 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_49 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561357);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_12 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_12;
architecture SYN_STRUCTURAL of RCA_N4_12 is
component FA_45
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_46
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_47
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_48
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, n1, net561356 : std_logic;
begin
FAI_1 : FA_48 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co => n1)
;
FAI_2 : FA_47 port map( A => A(1), B => B(1), Ci => n1, S => S(1), Co =>
CTMP_2_port);
FAI_3 : FA_46 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_45 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561356);
n2 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_11 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_11;
architecture SYN_STRUCTURAL of RCA_N4_11 is
component FA_41
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_42
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_43
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_44
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561355 : std_logic;
begin
FAI_1 : FA_44 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_43 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_42 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_41 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561355);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_10 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_10;
architecture SYN_STRUCTURAL of RCA_N4_10 is
component FA_37
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_38
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_39
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_40
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561354 : std_logic;
begin
FAI_1 : FA_40 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_39 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_38 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_37 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561354);
n2 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_9 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_9;
architecture SYN_STRUCTURAL of RCA_N4_9 is
component FA_33
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_34
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_35
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_36
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561353 : std_logic;
begin
FAI_1 : FA_36 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_35 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_34 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_33 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561353);
n2 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_8 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_8;
architecture SYN_STRUCTURAL of RCA_N4_8 is
component FA_29
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_30
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_31
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_32
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561352 : std_logic;
begin
FAI_1 : FA_32 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_31 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_30 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_29 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561352);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_7 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_7;
architecture SYN_STRUCTURAL of RCA_N4_7 is
component FA_25
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_26
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_27
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_28
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561351 : std_logic;
begin
FAI_1 : FA_28 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_27 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_26 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_25 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561351);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_6 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_6;
architecture SYN_STRUCTURAL of RCA_N4_6 is
component FA_21
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_22
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_23
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_24
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561350 : std_logic;
begin
FAI_1 : FA_24 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_23 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_22 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_21 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561350);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_5 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_5;
architecture SYN_STRUCTURAL of RCA_N4_5 is
component FA_17
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_18
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_19
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_20
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561349 : std_logic;
begin
FAI_1 : FA_20 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_19 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_18 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_17 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561349);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_4 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_4;
architecture SYN_STRUCTURAL of RCA_N4_4 is
component FA_13
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_14
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_15
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_16
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561348 : std_logic;
begin
FAI_1 : FA_16 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_15 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_14 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_13 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561348);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_3 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_3;
architecture SYN_STRUCTURAL of RCA_N4_3 is
component FA_9
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_10
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_11
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_12
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561347 : std_logic;
begin
FAI_1 : FA_12 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_11 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_10 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_9 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561347);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_2 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_2;
architecture SYN_STRUCTURAL of RCA_N4_2 is
component FA_5
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_6
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_7
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_8
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561346 : std_logic;
begin
FAI_1 : FA_8 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_7 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_6 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_5 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561346);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_1 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_1;
architecture SYN_STRUCTURAL of RCA_N4_1 is
component FA_1
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_2
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_3
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_4
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561345 : std_logic;
begin
FAI_1 : FA_4 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_3 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_2 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_1 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561345);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_1 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_1;
architecture SYN_archi of shift_N9_1 is
component SDFF_X2
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n11);
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n10);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n9);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n8);
tmp_reg_8_inst : SDFF_X1 port map( D => n6, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n7);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n5);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n4);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n3);
tmp_reg_0_inst : SDFF_X2 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n2);
n6 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_8 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_8;
architecture SYN_bhe of booth_encoder_8 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n9, n10, n11, n12 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n9, B1 => n12,
B2 => n11, B3 => B_in(2), ZN => A_out(0));
U6 : INV_X1 port map( A => B_in(1), ZN => n11);
U3 : INV_X1 port map( A => B_in(2), ZN => n9);
U4 : INV_X1 port map( A => B_in(0), ZN => n12);
U5 : OAI221_X1 port map( B1 => B_in(1), B2 => n12, C1 => n11, C2 => B_in(2),
A => n10, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n12, ZN => n10);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n9, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_7 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_7;
architecture SYN_bhe of booth_encoder_7 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U6 : INV_X1 port map( A => B_in(1), ZN => n10);
U3 : INV_X1 port map( A => B_in(0), ZN => n11);
U4 : INV_X1 port map( A => B_in(2), ZN => n8);
U5 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_6 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_6;
architecture SYN_bhe of booth_encoder_6 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_5 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_5;
architecture SYN_bhe of booth_encoder_5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_4 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_4;
architecture SYN_bhe of booth_encoder_4 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_3 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_3;
architecture SYN_bhe of booth_encoder_3 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(1), ZN => n10);
U4 : INV_X1 port map( A => B_in(0), ZN => n11);
U5 : INV_X1 port map( A => B_in(2), ZN => n8);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_2 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_2;
architecture SYN_bhe of booth_encoder_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(1), ZN => n10);
U4 : INV_X1 port map( A => B_in(0), ZN => n11);
U5 : INV_X1 port map( A => B_in(2), ZN => n8);
U6 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_1 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_1;
architecture SYN_bhe of booth_encoder_1 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n7, n8, n9 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n9, B2
=> n8, B3 => B_in(2), ZN => A_out(0));
U4 : NAND2_X1 port map( A1 => B_in(2), A2 => n9, ZN => n7);
U3 : OAI221_X1 port map( B1 => B_in(1), B2 => n9, C1 => n8, C2 => B_in(2), A
=> n7, ZN => A_out(2));
U5 : INV_X1 port map( A => B_in(0), ZN => n9);
U6 : INV_X1 port map( A => B_in(1), ZN => n8);
U7 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_7 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_7;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_7 is
component mux21_SIZE4_7
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_13
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_14
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561343, net561344 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_14 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561344);
rca_carry : RCA_N4_13 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561343);
outmux : mux21_SIZE4_7 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_6 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_6;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_6 is
component mux21_SIZE4_6
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_11
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_12
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561341, net561342 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_12 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561342);
rca_carry : RCA_N4_11 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561341);
outmux : mux21_SIZE4_6 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_5 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_5;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_5 is
component mux21_SIZE4_5
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_9
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_10
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561339, net561340 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_10 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561340);
rca_carry : RCA_N4_9 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561339);
outmux : mux21_SIZE4_5 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_4 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_4;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_4 is
component mux21_SIZE4_4
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_7
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_8
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561337, net561338 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_8 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561338);
rca_carry : RCA_N4_7 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561337);
outmux : mux21_SIZE4_4 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_3 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_3;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_3 is
component mux21_SIZE4_3
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_5
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_6
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561335, net561336 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_6 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561336);
rca_carry : RCA_N4_5 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561335);
outmux : mux21_SIZE4_3 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_2 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_2;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_2 is
component mux21_SIZE4_2
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_3
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_4
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561333, net561334 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_4 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561334);
rca_carry : RCA_N4_3 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561333);
outmux : mux21_SIZE4_2 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_1 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_1;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_1 is
component mux21_SIZE4_1
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_1
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_2
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561331, net561332 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_2 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561332);
rca_carry : RCA_N4_1 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561331);
outmux : mux21_SIZE4_1 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_26 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_26;
architecture SYN_beh of pg_26 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U3 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_25 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_25;
architecture SYN_beh of pg_25 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_24 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_24;
architecture SYN_beh of pg_24 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n3);
U2 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_23 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_23;
architecture SYN_beh of pg_23 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_22 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_22;
architecture SYN_beh of pg_22 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_21 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_21;
architecture SYN_beh of pg_21 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_20 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_20;
architecture SYN_beh of pg_20 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
signal n3, n4 : std_logic;
begin
U1 : CLKBUF_X1 port map( A => p, Z => n3);
U2 : INV_X1 port map( A => n4, ZN => g_out);
U3 : AND2_X1 port map( A1 => n3, A2 => p_prec, ZN => p_out);
U4 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n4);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_19 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_19;
architecture SYN_beh of pg_19 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_18 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_18;
architecture SYN_beh of pg_18 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_17 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_17;
architecture SYN_beh of pg_17 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_16 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_16;
architecture SYN_beh of pg_16 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_15 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_15;
architecture SYN_beh of pg_15 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_14 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_14;
architecture SYN_beh of pg_14 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_13 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_13;
architecture SYN_beh of pg_13 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_12 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_12;
architecture SYN_beh of pg_12 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => n3, A2 => g_BAR, ZN => g_out);
U3 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_11 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_11;
architecture SYN_beh of pg_11 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_10 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_10;
architecture SYN_beh of pg_10 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_9 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_9;
architecture SYN_beh of pg_9 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_8 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_8;
architecture SYN_beh of pg_8 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_7 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_7;
architecture SYN_beh of pg_7 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_6 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_6;
architecture SYN_beh of pg_6 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_5 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_5;
architecture SYN_beh of pg_5 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n2);
U2 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
U4 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_4 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_4;
architecture SYN_beh of pg_4 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_3 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_3;
architecture SYN_beh of pg_3 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_2 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_2;
architecture SYN_beh of pg_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_1 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_1;
architecture SYN_beh of pg_1 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_9 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_9;
architecture SYN_beh of g_9 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n2);
U2 : INV_X1 port map( A => n2, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_8 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_8;
architecture SYN_beh of g_8 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_7 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_7;
architecture SYN_beh of g_7 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_6 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_6;
architecture SYN_beh of g_6 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_5 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_5;
architecture SYN_beh of g_5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_4 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_4;
architecture SYN_beh of g_4 is
component NAND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n3);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X2 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_3 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_3;
architecture SYN_beh of g_3 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n2);
U2 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_2 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_2;
architecture SYN_beh of g_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n3);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_1 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_1;
architecture SYN_beh of g_1 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_31 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_31;
architecture SYN_beh of pg_net_31 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_30 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_30;
architecture SYN_beh of pg_net_30 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : INV_X1 port map( A => a, ZN => n1);
U2 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_29 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_29;
architecture SYN_beh of pg_net_29 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_28 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_28;
architecture SYN_beh of pg_net_28 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_27 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_27;
architecture SYN_beh of pg_net_27 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_26 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_26;
architecture SYN_beh of pg_net_26 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_25 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_25;
architecture SYN_beh of pg_net_25 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => a, A2 => b, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_24 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_24;
architecture SYN_beh of pg_net_24 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_23 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_23;
architecture SYN_beh of pg_net_23 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_22 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_22;
architecture SYN_beh of pg_net_22 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_21 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_21;
architecture SYN_beh of pg_net_21 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : INV_X1 port map( A => a, ZN => n1);
U2 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_20 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_20;
architecture SYN_beh of pg_net_20 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_19 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_19;
architecture SYN_beh of pg_net_19 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_18 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_18;
architecture SYN_beh of pg_net_18 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_17 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_17;
architecture SYN_beh of pg_net_17 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_16 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_16;
architecture SYN_beh of pg_net_16 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_15 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_15;
architecture SYN_beh of pg_net_15 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_14 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_14;
architecture SYN_beh of pg_net_14 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_13 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_13;
architecture SYN_beh of pg_net_13 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_12 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_12;
architecture SYN_beh of pg_net_12 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => a, A2 => b, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_11 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_11;
architecture SYN_beh of pg_net_11 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_10 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_10;
architecture SYN_beh of pg_net_10 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_9 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_9;
architecture SYN_beh of pg_net_9 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_8 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_8;
architecture SYN_beh of pg_net_8 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_7 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_7;
architecture SYN_beh of pg_net_7 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_6 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_6;
architecture SYN_beh of pg_net_6 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_5 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_5;
architecture SYN_beh of pg_net_5 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_4 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_4;
architecture SYN_beh of pg_net_4 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_3 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_3;
architecture SYN_beh of pg_net_3 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_2 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_2;
architecture SYN_beh of pg_net_2 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_1 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_1;
architecture SYN_beh of pg_net_1 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE32_1 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end mux41_MUX_SIZE32_1;
architecture SYN_bhe of mux41_MUX_SIZE32_1 is
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X3
port( A : in std_logic; Z : out std_logic);
end component;
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component OR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n38, n39, n40, n41, n53, n54, n55, n57, n61, n63, n64, n65, n66, n68,
n69, n70, n71, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92
, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130,
n131, n132, n135, n136, n137, n138, n139, n141, n142, n143, n144, n145,
n146, n147, n148, n149 : std_logic;
begin
U21 : INV_X1 port map( A => n143, ZN => OUT1(29));
U15 : INV_X1 port map( A => n145, ZN => OUT1(31));
U1 : BUF_X2 port map( A => n148, Z => n128);
U2 : NAND2_X1 port map( A1 => n83, A2 => IN2(12), ZN => n38);
U3 : AOI21_X1 port map( B1 => n127, B2 => IN0(12), A => n96, ZN => n39);
U4 : NAND2_X1 port map( A1 => n38, A2 => n39, ZN => OUT1(12));
U5 : AOI222_X1 port map( A1 => n130, A2 => IN1(23), B1 => n127, B2 =>
IN0(23), C1 => IN2(23), C2 => n83, ZN => n40);
U6 : INV_X1 port map( A => n40, ZN => OUT1(23));
U7 : AOI222_X1 port map( A1 => n126, A2 => IN0(30), B1 => n125, B2 =>
IN2(30), C1 => IN1(30), C2 => n71, ZN => n41);
U8 : INV_X1 port map( A => n41, ZN => OUT1(30));
U9 : BUF_X1 port map( A => n148, Z => n127);
U10 : NOR2_X2 port map( A1 => n81, A2 => CTRL(0), ZN => n83);
U11 : OR3_X1 port map( A1 => n93, A2 => n94, A3 => n95, ZN => OUT1(16));
U12 : NAND3_X1 port map( A1 => n53, A2 => n54, A3 => n55, ZN => OUT1(15));
U13 : OR3_X1 port map( A1 => n112, A2 => n113, A3 => n114, ZN => OUT1(17));
U14 : OR3_X1 port map( A1 => n97, A2 => n98, A3 => n99, ZN => OUT1(26));
U16 : BUF_X2 port map( A => n61, Z => n125);
U17 : NAND2_X1 port map( A1 => n131, A2 => IN1(15), ZN => n53);
U18 : NAND2_X1 port map( A1 => n83, A2 => IN2(15), ZN => n54);
U19 : NAND2_X1 port map( A1 => n127, A2 => IN0(15), ZN => n55);
U20 : AOI222_X1 port map( A1 => n57, A2 => IN1(29), B1 => n128, B2 =>
IN0(29), C1 => n125, C2 => IN2(29), ZN => n143);
U22 : AOI222_X1 port map( A1 => n57, A2 => IN1(31), B1 => n128, B2 =>
IN0(31), C1 => n125, C2 => IN2(31), ZN => n145);
U23 : CLKBUF_X1 port map( A => n129, Z => n57);
U24 : BUF_X1 port map( A => n149, Z => n131);
U25 : NOR2_X1 port map( A1 => n64, A2 => CTRL(0), ZN => n61);
U26 : BUF_X2 port map( A => n61, Z => n63);
U27 : NAND2_X1 port map( A1 => n63, A2 => IN2(0), ZN => n68);
U28 : NAND2_X1 port map( A1 => n125, A2 => IN2(1), ZN => n70);
U29 : NAND2_X1 port map( A1 => n125, A2 => IN2(21), ZN => n90);
U30 : NAND2_X1 port map( A1 => n125, A2 => IN2(13), ZN => n124);
U31 : AND2_X1 port map( A1 => n63, A2 => IN2(16), ZN => n95);
U32 : AOI222_X1 port map( A1 => n130, A2 => IN1(4), B1 => n127, B2 => IN0(4)
, C1 => n63, C2 => IN2(4), ZN => n147);
U33 : AOI222_X1 port map( A1 => n71, A2 => IN1(19), B1 => n127, B2 =>
IN0(19), C1 => n63, C2 => IN2(19), ZN => n136);
U34 : NAND2_X1 port map( A1 => n125, A2 => IN2(8), ZN => n85);
U35 : NAND3_X1 port map( A1 => n66, A2 => n68, A3 => n65, ZN => OUT1(0));
U36 : INV_X1 port map( A => CTRL(1), ZN => n64);
U37 : NAND2_X1 port map( A1 => n131, A2 => IN1(0), ZN => n65);
U38 : NAND2_X1 port map( A1 => n128, A2 => IN0(0), ZN => n66);
U39 : AOI22_X1 port map( A1 => n131, A2 => IN1(1), B1 => n127, B2 => IN0(1),
ZN => n69);
U40 : NAND2_X1 port map( A1 => n69, A2 => n70, ZN => OUT1(1));
U41 : INV_X1 port map( A => n146, ZN => OUT1(3));
U42 : AOI222_X1 port map( A1 => n130, A2 => IN1(28), B1 => n126, B2 =>
IN0(28), C1 => n83, C2 => IN2(28), ZN => n142);
U43 : BUF_X2 port map( A => n149, Z => n71);
U44 : NOR2_X2 port map( A1 => CTRL(1), A2 => CTRL(0), ZN => n148);
U45 : CLKBUF_X3 port map( A => n148, Z => n126);
U46 : BUF_X2 port map( A => n149, Z => n130);
U47 : AND2_X2 port map( A1 => CTRL(0), A2 => n82, ZN => n149);
U48 : BUF_X2 port map( A => n149, Z => n129);
U49 : INV_X1 port map( A => n138, ZN => OUT1(24));
U50 : INV_X1 port map( A => n139, ZN => OUT1(25));
U51 : AND2_X1 port map( A1 => n83, A2 => IN2(26), ZN => n99);
U52 : AND2_X1 port map( A1 => n127, A2 => IN0(26), ZN => n98);
U53 : AND2_X1 port map( A1 => n129, A2 => IN1(26), ZN => n97);
U54 : INV_X1 port map( A => n141, ZN => OUT1(27));
U55 : INV_X1 port map( A => n142, ZN => OUT1(28));
U56 : INV_X1 port map( A => n137, ZN => OUT1(20));
U57 : AND2_X1 port map( A1 => n129, A2 => IN1(12), ZN => n96);
U58 : INV_X1 port map( A => n147, ZN => OUT1(4));
U59 : INV_X1 port map( A => n144, ZN => OUT1(2));
U60 : INV_X1 port map( A => n136, ZN => OUT1(19));
U61 : AND2_X1 port map( A1 => n127, A2 => IN0(16), ZN => n94);
U62 : AND2_X1 port map( A1 => n130, A2 => IN1(16), ZN => n93);
U63 : AND2_X1 port map( A1 => n83, A2 => IN2(17), ZN => n114);
U64 : AND2_X1 port map( A1 => n127, A2 => IN0(17), ZN => n113);
U65 : AND2_X1 port map( A1 => n129, A2 => IN1(17), ZN => n112);
U66 : INV_X1 port map( A => n135, ZN => OUT1(18));
U67 : INV_X1 port map( A => CTRL(1), ZN => n81);
U68 : INV_X1 port map( A => CTRL(1), ZN => n82);
U69 : INV_X1 port map( A => n132, ZN => OUT1(10));
U70 : NAND3_X1 port map( A1 => n106, A2 => n107, A3 => n108, ZN => OUT1(6));
U71 : NAND3_X1 port map( A1 => n109, A2 => n110, A3 => n111, ZN => OUT1(7));
U72 : NAND3_X1 port map( A1 => n119, A2 => n120, A3 => n121, ZN => OUT1(9));
U73 : NAND3_X1 port map( A1 => n115, A2 => n116, A3 => n117, ZN => OUT1(14))
;
U74 : NAND3_X1 port map( A1 => n100, A2 => n101, A3 => n102, ZN => OUT1(11))
;
U75 : NAND3_X1 port map( A1 => n122, A2 => n123, A3 => n124, ZN => OUT1(13))
;
U76 : NAND3_X1 port map( A1 => n103, A2 => n104, A3 => n105, ZN => OUT1(5));
U77 : AOI222_X1 port map( A1 => n129, A2 => IN1(25), B1 => n128, B2 =>
IN0(25), C1 => n125, C2 => IN2(25), ZN => n139);
U78 : AOI222_X1 port map( A1 => n71, A2 => IN1(3), B1 => n126, B2 => IN0(3),
C1 => n83, C2 => IN2(3), ZN => n146);
U79 : AOI222_X1 port map( A1 => n130, A2 => IN1(18), B1 => n126, B2 =>
IN0(18), C1 => n63, C2 => IN2(18), ZN => n135);
U80 : NAND3_X1 port map( A1 => n84, A2 => n85, A3 => n86, ZN => OUT1(8));
U81 : NAND2_X1 port map( A1 => n130, A2 => IN1(8), ZN => n84);
U82 : NAND2_X1 port map( A1 => n126, A2 => IN0(8), ZN => n86);
U83 : NAND3_X1 port map( A1 => n87, A2 => n88, A3 => n89, ZN => OUT1(22));
U84 : NAND2_X1 port map( A1 => n125, A2 => IN2(22), ZN => n87);
U85 : NAND2_X1 port map( A1 => n71, A2 => IN1(22), ZN => n88);
U86 : NAND2_X1 port map( A1 => n126, A2 => IN0(22), ZN => n89);
U87 : NAND3_X1 port map( A1 => n90, A2 => n91, A3 => n92, ZN => OUT1(21));
U88 : NAND2_X1 port map( A1 => n71, A2 => IN1(21), ZN => n91);
U89 : NAND2_X1 port map( A1 => n126, A2 => IN0(21), ZN => n92);
U90 : NAND2_X1 port map( A1 => n71, A2 => IN1(11), ZN => n100);
U91 : NAND2_X1 port map( A1 => n126, A2 => IN0(11), ZN => n101);
U92 : NAND2_X1 port map( A1 => n125, A2 => IN2(11), ZN => n102);
U93 : NAND2_X1 port map( A1 => n129, A2 => IN1(5), ZN => n103);
U94 : NAND2_X1 port map( A1 => n126, A2 => IN0(5), ZN => n104);
U95 : NAND2_X1 port map( A1 => n63, A2 => IN2(5), ZN => n105);
U96 : NAND2_X1 port map( A1 => n129, A2 => IN1(6), ZN => n106);
U97 : NAND2_X1 port map( A1 => n128, A2 => IN0(6), ZN => n107);
U98 : NAND2_X1 port map( A1 => n83, A2 => IN2(6), ZN => n108);
U99 : NAND2_X1 port map( A1 => n130, A2 => IN1(7), ZN => n109);
U100 : NAND2_X1 port map( A1 => n126, A2 => IN0(7), ZN => n110);
U101 : NAND2_X1 port map( A1 => n83, A2 => IN2(7), ZN => n111);
U102 : NAND2_X1 port map( A1 => n129, A2 => IN1(14), ZN => n115);
U103 : NAND2_X1 port map( A1 => n128, A2 => IN0(14), ZN => n116);
U104 : NAND2_X1 port map( A1 => n125, A2 => IN2(14), ZN => n117);
U105 : NAND2_X1 port map( A1 => n129, A2 => IN1(9), ZN => n119);
U106 : NAND2_X1 port map( A1 => n128, A2 => IN0(9), ZN => n120);
U107 : NAND2_X1 port map( A1 => n125, A2 => IN2(9), ZN => n121);
U108 : NAND2_X1 port map( A1 => n130, A2 => IN1(13), ZN => n122);
U109 : NAND2_X1 port map( A1 => n126, A2 => IN0(13), ZN => n123);
U110 : AOI222_X1 port map( A1 => n130, A2 => IN1(24), B1 => n128, B2 =>
IN0(24), C1 => n125, C2 => IN2(24), ZN => n138);
U111 : AOI222_X1 port map( A1 => n71, A2 => IN1(2), B1 => n126, B2 => IN0(2)
, C1 => n125, C2 => IN2(2), ZN => n144);
U112 : AOI222_X1 port map( A1 => n71, A2 => IN1(27), B1 => n126, B2 =>
IN0(27), C1 => n83, C2 => IN2(27), ZN => n141);
U113 : AOI222_X1 port map( A1 => n130, A2 => IN1(20), B1 => n127, B2 =>
IN0(20), C1 => n83, C2 => IN2(20), ZN => n137);
U114 : AOI222_X1 port map( A1 => n129, A2 => IN1(10), B1 => n127, B2 =>
IN0(10), C1 => n83, C2 => IN2(10), ZN => n132);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_1 is
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end mux21_1;
architecture SYN_Bhe of mux21_1 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : MUX2_X1 port map( A => IN0(9), B => IN1(9), S => CTRL, Z => OUT1(9));
U2 : MUX2_X1 port map( A => IN0(8), B => IN1(8), S => CTRL, Z => OUT1(8));
U3 : MUX2_X1 port map( A => IN0(7), B => IN1(7), S => CTRL, Z => OUT1(7));
U4 : MUX2_X1 port map( A => IN0(6), B => IN1(6), S => CTRL, Z => OUT1(6));
U5 : MUX2_X1 port map( A => IN0(5), B => IN1(5), S => CTRL, Z => OUT1(5));
U6 : MUX2_X1 port map( A => IN0(4), B => IN1(4), S => CTRL, Z => OUT1(4));
U7 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U8 : MUX2_X1 port map( A => IN0(31), B => IN1(31), S => CTRL, Z => OUT1(31))
;
U9 : MUX2_X1 port map( A => IN0(30), B => IN1(30), S => CTRL, Z => OUT1(30))
;
U10 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U12 : MUX2_X1 port map( A => IN0(28), B => IN1(28), S => CTRL, Z => OUT1(28)
);
U13 : MUX2_X1 port map( A => IN0(27), B => IN1(27), S => CTRL, Z => OUT1(27)
);
U14 : MUX2_X1 port map( A => IN0(26), B => IN1(26), S => CTRL, Z => OUT1(26)
);
U15 : MUX2_X1 port map( A => IN0(25), B => IN1(25), S => CTRL, Z => OUT1(25)
);
U16 : MUX2_X1 port map( A => IN0(24), B => IN1(24), S => CTRL, Z => OUT1(24)
);
U17 : MUX2_X1 port map( A => IN0(23), B => IN1(23), S => CTRL, Z => OUT1(23)
);
U18 : MUX2_X1 port map( A => IN0(22), B => IN1(22), S => CTRL, Z => OUT1(22)
);
U19 : MUX2_X1 port map( A => IN0(21), B => IN1(21), S => CTRL, Z => OUT1(21)
);
U20 : MUX2_X1 port map( A => IN0(20), B => IN1(20), S => CTRL, Z => OUT1(20)
);
U21 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U22 : MUX2_X1 port map( A => IN0(19), B => IN1(19), S => CTRL, Z => OUT1(19)
);
U23 : MUX2_X1 port map( A => IN0(18), B => IN1(18), S => CTRL, Z => OUT1(18)
);
U24 : MUX2_X1 port map( A => IN0(17), B => IN1(17), S => CTRL, Z => OUT1(17)
);
U25 : MUX2_X1 port map( A => IN0(16), B => IN1(16), S => CTRL, Z => OUT1(16)
);
U26 : MUX2_X1 port map( A => IN0(15), B => IN1(15), S => CTRL, Z => OUT1(15)
);
U27 : MUX2_X1 port map( A => IN0(14), B => IN1(14), S => CTRL, Z => OUT1(14)
);
U28 : MUX2_X1 port map( A => IN0(13), B => IN1(13), S => CTRL, Z => OUT1(13)
);
U29 : MUX2_X1 port map( A => IN0(12), B => IN1(12), S => CTRL, Z => OUT1(12)
);
U30 : MUX2_X1 port map( A => IN0(11), B => IN1(11), S => CTRL, Z => OUT1(11)
);
U31 : MUX2_X1 port map( A => IN0(10), B => IN1(10), S => CTRL, Z => OUT1(10)
);
U11 : MUX2_X1 port map( A => IN0(29), B => IN1(29), S => CTRL, Z => OUT1(29)
);
U32 : INV_X1 port map( A => IN0(0), ZN => n1);
U33 : NOR2_X1 port map( A1 => CTRL, A2 => n1, ZN => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_0 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_0;
architecture SYN_BEHAVIORAL of FA_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_0 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_0;
architecture SYN_Bhe of mux21_SIZE4_0 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_0 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_0;
architecture SYN_STRUCTURAL of RCA_N4_0 is
component FA_61
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_62
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_63
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_0
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561330 : std_logic;
begin
FAI_1 : FA_0 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_63 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_62 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_61 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561330);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_0 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_0;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_0 is
component mux21_SIZE4_0
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_15
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_0
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561328, net561329 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_0 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561329);
rca_carry : RCA_N4_15 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561328);
outmux : mux21_SIZE4_0 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_0 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_0;
architecture SYN_beh of pg_0 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_0 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_0;
architecture SYN_beh of g_0 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n2);
U2 : INV_X1 port map( A => n2, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_0 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_0;
architecture SYN_beh of pg_net_0 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1, n2 : std_logic;
begin
U1 : NOR2_X1 port map( A1 => n2, A2 => n1, ZN => g_out);
U2 : XNOR2_X1 port map( A => n1, B => b, ZN => p_out);
U3 : INV_X1 port map( A => a, ZN => n1);
U4 : INV_X1 port map( A => b, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_thirdLevel is
port( sel : in std_logic_vector (2 downto 0); A : in std_logic_vector (38
downto 0); Y : out std_logic_vector (31 downto 0));
end shift_thirdLevel;
architecture SYN_behav of shift_thirdLevel is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
signal n17, n18, n20, n21, n22, n23, n24, n25, n26, n28, n29, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n48, n49
, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78
, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141 :
std_logic;
begin
U144 : AOI22_X1 port map( A1 => n135, A2 => A(0), B1 => n40, B2 => A(2), ZN
=> n129);
U140 : AOI22_X1 port map( A1 => n137, A2 => A(4), B1 => n23, B2 => A(6), ZN
=> n130);
U137 : OAI22_X1 port map( A1 => A(1), A2 => n134, B1 => A(3), B2 => n26, ZN
=> n132);
U136 : AOI21_X1 port map( B1 => n23, B2 => n36, A => n132, ZN => n131);
U135 : OAI21_X1 port map( B1 => A(5), B2 => n136, A => n131, ZN => n93);
U134 : OAI222_X1 port map( A1 => n141, A2 => n129, B1 => n141, B2 => n130,
C1 => n138, C2 => n93, ZN => Y(0));
U29 : AOI22_X1 port map( A1 => n135, A2 => A(32), B1 => n40, B2 => A(34), ZN
=> n49);
U28 : AOI22_X1 port map( A1 => n137, A2 => A(36), B1 => n23, B2 => A(38), ZN
=> n50);
U33 : OAI22_X1 port map( A1 => A(33), A2 => n26, B1 => A(37), B2 => n33, ZN
=> n55);
U32 : AOI21_X1 port map( B1 => n135, B2 => n54, A => n55, ZN => n53);
U31 : OAI21_X1 port map( B1 => A(35), B2 => n136, A => n53, ZN => n51);
U27 : OAI222_X1 port map( A1 => n138, A2 => n49, B1 => n138, B2 => n50, C1
=> n51, C2 => n141, ZN => Y(31));
U93 : OAI22_X1 port map( A1 => A(19), A2 => n134, B1 => A(21), B2 => n26, ZN
=> n101);
U92 : AOI21_X1 port map( B1 => n23, B2 => n78, A => n101, ZN => n100);
U91 : OAI21_X1 port map( B1 => A(23), B2 => n136, A => n100, ZN => n96);
U89 : OAI22_X1 port map( A1 => A(20), A2 => n134, B1 => A(22), B2 => n26, ZN
=> n98);
U88 : AOI21_X1 port map( B1 => n137, B2 => n82, A => n98, ZN => n97);
U87 : OAI21_X1 port map( B1 => A(26), B2 => n33, A => n97, ZN => n90);
U86 : AOI22_X1 port map( A1 => sel(0), A2 => n96, B1 => n90, B2 => n140, ZN
=> Y(19));
U80 : OAI22_X1 port map( A1 => A(21), A2 => n134, B1 => A(23), B2 => n26, ZN
=> n92);
U79 : AOI21_X1 port map( B1 => n137, B2 => n78, A => n92, ZN => n91);
U78 : OAI21_X1 port map( B1 => A(27), B2 => n33, A => n91, ZN => n87);
U77 : AOI22_X1 port map( A1 => n139, A2 => n90, B1 => n87, B2 => n140, ZN =>
Y(20));
U76 : OAI22_X1 port map( A1 => A(22), A2 => n134, B1 => A(28), B2 => n33, ZN
=> n89);
U75 : AOI21_X1 port map( B1 => n40, B2 => n82, A => n89, ZN => n88);
U74 : OAI21_X1 port map( B1 => A(26), B2 => n21, A => n88, ZN => n84);
U73 : AOI22_X1 port map( A1 => n139, A2 => n87, B1 => n84, B2 => n140, ZN =>
Y(21));
U38 : OAI22_X1 port map( A1 => A(5), A2 => n26, B1 => A(3), B2 => n134, ZN
=> n58);
U37 : AOI21_X1 port map( B1 => n137, B2 => n36, A => n58, ZN => n57);
U36 : OAI21_X1 port map( B1 => A(9), B2 => n33, A => n57, ZN => n45);
U26 : OAI22_X1 port map( A1 => A(6), A2 => n26, B1 => A(4), B2 => n134, ZN
=> n48);
U25 : AOI21_X1 port map( B1 => n137, B2 => n31, A => n48, ZN => n46);
U24 : OAI21_X1 port map( B1 => A(10), B2 => n33, A => n46, ZN => n42);
U23 : AOI22_X1 port map( A1 => n138, A2 => n45, B1 => n42, B2 => n140, ZN =>
Y(3));
U72 : OAI22_X1 port map( A1 => A(23), A2 => n134, B1 => A(29), B2 => n33, ZN
=> n86);
U71 : AOI21_X1 port map( B1 => n40, B2 => n78, A => n86, ZN => n85);
U70 : OAI21_X1 port map( B1 => A(27), B2 => n21, A => n85, ZN => n80);
U69 : AOI22_X1 port map( A1 => n139, A2 => n84, B1 => n80, B2 => n140, ZN =>
Y(22));
U68 : OAI22_X1 port map( A1 => A(26), A2 => n26, B1 => A(30), B2 => n33, ZN
=> n83);
U67 : AOI21_X1 port map( B1 => n135, B2 => n82, A => n83, ZN => n81);
U66 : OAI21_X1 port map( B1 => A(28), B2 => n136, A => n81, ZN => n76);
U64 : OAI22_X1 port map( A1 => A(27), A2 => n26, B1 => A(31), B2 => n33, ZN
=> n79);
U63 : AOI21_X1 port map( B1 => n135, B2 => n78, A => n79, ZN => n77);
U62 : OAI21_X1 port map( B1 => A(29), B2 => n136, A => n77, ZN => n73);
U61 : AOI22_X1 port map( A1 => sel(0), A2 => n76, B1 => n73, B2 => n140, ZN
=> Y(24));
U111 : OAI22_X1 port map( A1 => A(15), A2 => n134, B1 => A(21), B2 => n33,
ZN => n115);
U110 : AOI21_X1 port map( B1 => n40, B2 => n107, A => n115, ZN => n114);
U109 : OAI21_X1 port map( B1 => A(19), B2 => n21, A => n114, ZN => n109);
U107 : OAI22_X1 port map( A1 => A(18), A2 => n26, B1 => A(22), B2 => n33, ZN
=> n112);
U106 : AOI21_X1 port map( B1 => n135, B2 => n111, A => n112, ZN => n110);
U105 : OAI21_X1 port map( B1 => A(20), B2 => n21, A => n110, ZN => n105);
U104 : AOI22_X1 port map( A1 => n139, A2 => n109, B1 => n105, B2 => n141, ZN
=> Y(15));
U10 : OAI22_X1 port map( A1 => A(14), A2 => n33, B1 => A(10), B2 => n26, ZN
=> n32);
U9 : AOI21_X1 port map( B1 => n135, B2 => n31, A => n32, ZN => n29);
U8 : OAI21_X1 port map( B1 => A(12), B2 => n136, A => n29, ZN => n20);
U5 : OAI22_X1 port map( A1 => A(11), A2 => n26, B1 => A(9), B2 => n134, ZN
=> n25);
U4 : AOI21_X1 port map( B1 => n23, B2 => n24, A => n25, ZN => n22);
U3 : OAI21_X1 port map( B1 => A(13), B2 => n136, A => n22, ZN => n17);
U2 : AOI22_X1 port map( A1 => n138, A2 => n20, B1 => n17, B2 => n140, ZN =>
Y(8));
U18 : OAI22_X1 port map( A1 => A(6), A2 => n134, B1 => A(12), B2 => n33, ZN
=> n41);
U17 : AOI21_X1 port map( B1 => n40, B2 => n31, A => n41, ZN => n39);
U16 : OAI21_X1 port map( B1 => A(10), B2 => n136, A => n39, ZN => n34);
U14 : OAI22_X1 port map( A1 => A(13), A2 => n33, B1 => A(9), B2 => n26, ZN
=> n37);
U13 : AOI21_X1 port map( B1 => n135, B2 => n36, A => n37, ZN => n35);
U12 : OAI21_X1 port map( B1 => A(11), B2 => n136, A => n35, ZN => n28);
U11 : AOI22_X1 port map( A1 => n138, A2 => n34, B1 => n28, B2 => n140, ZN =>
Y(6));
U59 : OAI22_X1 port map( A1 => A(26), A2 => n134, B1 => A(28), B2 => n26, ZN
=> n75);
U58 : AOI21_X1 port map( B1 => n23, B2 => n61, A => n75, ZN => n74);
U57 : OAI21_X1 port map( B1 => A(30), B2 => n136, A => n74, ZN => n70);
U56 : AOI22_X1 port map( A1 => sel(0), A2 => n73, B1 => n70, B2 => n140, ZN
=> Y(25));
U103 : OAI22_X1 port map( A1 => A(19), A2 => n26, B1 => A(23), B2 => n33, ZN
=> n108);
U102 : AOI21_X1 port map( B1 => n135, B2 => n107, A => n108, ZN => n106);
U101 : OAI21_X1 port map( B1 => A(21), B2 => n21, A => n106, ZN => n102);
U98 : OAI22_X1 port map( A1 => A(18), A2 => n134, B1 => A(20), B2 => n26, ZN
=> n104);
U97 : AOI21_X1 port map( B1 => n23, B2 => n82, A => n104, ZN => n103);
U96 : OAI21_X1 port map( B1 => A(22), B2 => n21, A => n103, ZN => n99);
U95 : AOI22_X1 port map( A1 => n139, A2 => n102, B1 => n99, B2 => n140, ZN
=> Y(17));
U123 : OAI22_X1 port map( A1 => A(14), A2 => n26, B1 => A(12), B2 => n134,
ZN => n124);
U122 : AOI21_X1 port map( B1 => n137, B2 => n111, A => n124, ZN => n123);
U121 : OAI21_X1 port map( B1 => A(18), B2 => n33, A => n123, ZN => n119);
U119 : OAI22_X1 port map( A1 => A(15), A2 => n26, B1 => A(13), B2 => n134,
ZN => n121);
U118 : AOI21_X1 port map( B1 => n137, B2 => n107, A => n121, ZN => n120);
U117 : OAI21_X1 port map( B1 => A(19), B2 => n33, A => n120, ZN => n116);
U116 : AOI22_X1 port map( A1 => n139, A2 => n119, B1 => n116, B2 => n141, ZN
=> Y(12));
U100 : AOI22_X1 port map( A1 => n139, A2 => n105, B1 => n102, B2 => n140, ZN
=> Y(16));
U50 : OAI22_X1 port map( A1 => A(28), A2 => n134, B1 => A(30), B2 => n26, ZN
=> n69);
U49 : AOI21_X1 port map( B1 => n137, B2 => n61, A => n69, ZN => n68);
U48 : OAI21_X1 port map( B1 => A(34), B2 => n33, A => n68, ZN => n63);
U46 : OAI22_X1 port map( A1 => A(31), A2 => n26, B1 => A(35), B2 => n33, ZN
=> n66);
U45 : AOI21_X1 port map( B1 => n135, B2 => n65, A => n66, ZN => n64);
U44 : OAI21_X1 port map( B1 => A(33), B2 => n136, A => n64, ZN => n59);
U43 : AOI22_X1 port map( A1 => n139, A2 => n63, B1 => n59, B2 => n140, ZN =>
Y(28));
U22 : OAI22_X1 port map( A1 => A(5), A2 => n134, B1 => A(11), B2 => n33, ZN
=> n44);
U21 : AOI21_X1 port map( B1 => n40, B2 => n36, A => n44, ZN => n43);
U20 : OAI21_X1 port map( B1 => A(9), B2 => n136, A => n43, ZN => n38);
U19 : AOI22_X1 port map( A1 => n138, A2 => n42, B1 => n38, B2 => n140, ZN =>
Y(4));
U54 : OAI22_X1 port map( A1 => A(27), A2 => n134, B1 => A(33), B2 => n33, ZN
=> n72);
U53 : AOI21_X1 port map( B1 => n40, B2 => n65, A => n72, ZN => n71);
U52 : OAI21_X1 port map( B1 => A(31), B2 => n136, A => n71, ZN => n67);
U47 : AOI22_X1 port map( A1 => n139, A2 => n67, B1 => n63, B2 => n140, ZN =>
Y(27));
U15 : AOI22_X1 port map( A1 => n138, A2 => n38, B1 => n34, B2 => n140, ZN =>
Y(5));
U115 : OAI22_X1 port map( A1 => A(14), A2 => n134, B1 => A(20), B2 => n33,
ZN => n118);
U114 : AOI21_X1 port map( B1 => n40, B2 => n111, A => n118, ZN => n117);
U113 : OAI21_X1 port map( B1 => A(18), B2 => n21, A => n117, ZN => n113);
U112 : AOI22_X1 port map( A1 => n139, A2 => n116, B1 => n113, B2 => n141, ZN
=> Y(13));
U132 : OAI22_X1 port map( A1 => A(12), A2 => n26, B1 => A(10), B2 => n134,
ZN => n128);
U131 : AOI21_X1 port map( B1 => n23, B2 => n111, A => n128, ZN => n127);
U130 : OAI21_X1 port map( B1 => A(14), B2 => n21, A => n127, ZN => n18);
U1 : AOI22_X1 port map( A1 => n139, A2 => n17, B1 => n18, B2 => n140, ZN =>
Y(9));
U7 : AOI22_X1 port map( A1 => n138, A2 => n28, B1 => n20, B2 => n140, ZN =>
Y(7));
U108 : AOI22_X1 port map( A1 => n139, A2 => n113, B1 => n109, B2 => n141, ZN
=> Y(14));
U90 : AOI22_X1 port map( A1 => n139, A2 => n99, B1 => n96, B2 => n140, ZN =>
Y(18));
U65 : AOI22_X1 port map( A1 => sel(0), A2 => n80, B1 => n76, B2 => n140, ZN
=> Y(23));
U51 : AOI22_X1 port map( A1 => n139, A2 => n70, B1 => n67, B2 => n140, ZN =>
Y(26));
U42 : OAI22_X1 port map( A1 => A(30), A2 => n134, B1 => A(36), B2 => n33, ZN
=> n62);
U41 : AOI21_X1 port map( B1 => n40, B2 => n61, A => n62, ZN => n60);
U40 : OAI21_X1 port map( B1 => A(34), B2 => n136, A => n60, ZN => n52);
U39 : AOI22_X1 port map( A1 => n138, A2 => n59, B1 => n52, B2 => n140, ZN =>
Y(29));
U84 : OAI22_X1 port map( A1 => A(4), A2 => n26, B1 => A(2), B2 => n134, ZN
=> n95);
U83 : AOI21_X1 port map( B1 => n23, B2 => n31, A => n95, ZN => n94);
U82 : OAI21_X1 port map( B1 => A(6), B2 => n136, A => n94, ZN => n56);
U35 : AOI22_X1 port map( A1 => n138, A2 => n56, B1 => n45, B2 => n140, ZN =>
Y(2));
U81 : AOI22_X1 port map( A1 => sel(0), A2 => n93, B1 => n56, B2 => n140, ZN
=> Y(1));
U30 : AOI22_X1 port map( A1 => n138, A2 => n52, B1 => n51, B2 => n140, ZN =>
Y(30));
U128 : OAI22_X1 port map( A1 => A(13), A2 => n26, B1 => A(11), B2 => n134,
ZN => n126);
U127 : AOI21_X1 port map( B1 => n23, B2 => n107, A => n126, ZN => n125);
U126 : OAI21_X1 port map( B1 => A(15), B2 => n21, A => n125, ZN => n122);
U120 : AOI22_X1 port map( A1 => n139, A2 => n122, B1 => n119, B2 => n141, ZN
=> Y(11));
U125 : AOI22_X1 port map( A1 => n139, A2 => n18, B1 => n122, B2 => n141, ZN
=> Y(10));
U146 : INV_X1 port map( A => sel(2), ZN => n133);
U138 : INV_X1 port map( A => n40, ZN => n26);
U34 : INV_X1 port map( A => A(31), ZN => n54);
U124 : INV_X1 port map( A => n23, ZN => n33);
U94 : INV_X1 port map( A => A(25), ZN => n78);
U99 : INV_X1 port map( A => A(24), ZN => n82);
U85 : INV_X1 port map( A => A(8), ZN => n31);
U129 : INV_X1 port map( A => A(17), ZN => n107);
U133 : INV_X1 port map( A => A(16), ZN => n111);
U6 : INV_X1 port map( A => A(15), ZN => n24);
U60 : INV_X1 port map( A => A(32), ZN => n61);
U55 : INV_X1 port map( A => A(29), ZN => n65);
U139 : INV_X1 port map( A => A(7), ZN => n36);
U141 : INV_X1 port map( A => n135, ZN => n134);
U142 : BUF_X1 port map( A => sel(0), Z => n138);
U143 : BUF_X1 port map( A => sel(0), Z => n139);
U145 : INV_X1 port map( A => n138, ZN => n140);
U147 : INV_X1 port map( A => n137, ZN => n136);
U148 : INV_X1 port map( A => n21, ZN => n137);
U149 : NAND2_X1 port map( A1 => n133, A2 => sel(1), ZN => n21);
U150 : NOR2_X1 port map( A1 => sel(1), A2 => n133, ZN => n40);
U151 : AND2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n135);
U152 : INV_X1 port map( A => n139, ZN => n141);
U153 : NOR2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n23);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_secondLevel is
port( sel : in std_logic_vector (1 downto 0); mask00, mask08, mask16 : in
std_logic_vector (38 downto 0); Y : out std_logic_vector (38 downto
0));
end shift_secondLevel;
architecture SYN_behav of shift_secondLevel is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
signal n41, n42, n43, n44, n45, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70
, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n46,
n84, n92 : std_logic;
begin
U79 : AOI222_X1 port map( A1 => n84, A2 => mask00(0), B1 => n43, B2 =>
mask16(0), C1 => n44, C2 => mask08(0), ZN => n82);
U35 : AOI222_X1 port map( A1 => n84, A2 => mask00(2), B1 => n43, B2 =>
mask16(2), C1 => n92, C2 => mask08(2), ZN => n60);
U13 : AOI222_X1 port map( A1 => n84, A2 => mask00(4), B1 => n43, B2 =>
mask16(4), C1 => n92, C2 => mask08(4), ZN => n49);
U9 : AOI222_X1 port map( A1 => n84, A2 => mask00(6), B1 => n43, B2 =>
mask16(6), C1 => n92, C2 => mask08(6), ZN => n47);
U11 : AOI222_X1 port map( A1 => n84, A2 => mask00(5), B1 => n43, B2 =>
mask16(5), C1 => n92, C2 => mask08(5), ZN => n48);
U57 : AOI222_X1 port map( A1 => n84, A2 => mask00(1), B1 => n43, B2 =>
mask16(1), C1 => n44, C2 => mask08(1), ZN => n71);
U15 : AOI222_X1 port map( A1 => n84, A2 => mask00(3), B1 => n43, B2 =>
mask16(3), C1 => n92, C2 => mask08(3), ZN => n50);
U29 : AOI222_X1 port map( A1 => n84, A2 => mask00(32), B1 => n43, B2 =>
mask16(32), C1 => n92, C2 => mask08(32), ZN => n57);
U25 : AOI222_X1 port map( A1 => n84, A2 => mask00(34), B1 => n43, B2 =>
mask16(34), C1 => n92, C2 => mask08(34), ZN => n55);
U21 : AOI222_X1 port map( A1 => n84, A2 => mask00(36), B1 => n43, B2 =>
mask16(36), C1 => n92, C2 => mask08(36), ZN => n53);
U17 : AOI222_X1 port map( A1 => n84, A2 => mask00(38), B1 => n43, B2 =>
mask16(38), C1 => n92, C2 => mask08(38), ZN => n51);
U23 : AOI222_X1 port map( A1 => n84, A2 => mask00(35), B1 => n43, B2 =>
mask16(35), C1 => n92, C2 => mask08(35), ZN => n54);
U31 : AOI222_X1 port map( A1 => n84, A2 => mask00(31), B1 => n43, B2 =>
mask16(31), C1 => n92, C2 => mask08(31), ZN => n58);
U27 : AOI222_X1 port map( A1 => n84, A2 => mask00(33), B1 => n43, B2 =>
mask16(33), C1 => n92, C2 => mask08(33), ZN => n56);
U19 : AOI222_X1 port map( A1 => n84, A2 => mask00(37), B1 => n43, B2 =>
mask16(37), C1 => n92, C2 => mask08(37), ZN => n52);
U49 : AOI222_X1 port map( A1 => n84, A2 => mask00(23), B1 => n43, B2 =>
mask16(23), C1 => n44, C2 => mask08(23), ZN => n67);
U45 : AOI222_X1 port map( A1 => n84, A2 => mask00(25), B1 => n43, B2 =>
mask16(25), C1 => n92, C2 => mask08(25), ZN => n65);
U59 : AOI222_X1 port map( A1 => n84, A2 => mask00(19), B1 => n43, B2 =>
mask16(19), C1 => n44, C2 => mask08(19), ZN => n72);
U53 : AOI222_X1 port map( A1 => n84, A2 => mask00(21), B1 => n43, B2 =>
mask16(21), C1 => n44, C2 => mask08(21), ZN => n69);
U43 : AOI222_X1 port map( A1 => n84, A2 => mask00(26), B1 => n43, B2 =>
mask16(26), C1 => n92, C2 => mask08(26), ZN => n64);
U47 : AOI222_X1 port map( A1 => n84, A2 => mask00(24), B1 => n43, B2 =>
mask16(24), C1 => n92, C2 => mask08(24), ZN => n66);
U55 : AOI222_X1 port map( A1 => n84, A2 => mask00(20), B1 => n43, B2 =>
mask16(20), C1 => n44, C2 => mask08(20), ZN => n70);
U51 : AOI222_X1 port map( A1 => n84, A2 => mask00(22), B1 => n43, B2 =>
mask16(22), C1 => n92, C2 => mask08(22), ZN => n68);
U41 : AOI222_X1 port map( A1 => n84, A2 => mask00(27), B1 => n43, B2 =>
mask16(27), C1 => n92, C2 => mask08(27), ZN => n63);
U39 : AOI222_X1 port map( A1 => n84, A2 => mask00(28), B1 => n43, B2 =>
mask16(28), C1 => n92, C2 => mask08(28), ZN => n62);
U3 : AOI222_X1 port map( A1 => n84, A2 => mask00(9), B1 => n43, B2 =>
mask16(9), C1 => n92, C2 => mask08(9), ZN => n41);
U77 : AOI222_X1 port map( A1 => n84, A2 => mask00(10), B1 => n43, B2 =>
mask16(10), C1 => n44, C2 => mask08(10), ZN => n81);
U5 : AOI222_X1 port map( A1 => n84, A2 => mask00(8), B1 => n43, B2 =>
mask16(8), C1 => n92, C2 => mask08(8), ZN => n45);
U37 : AOI222_X1 port map( A1 => n84, A2 => mask00(29), B1 => n43, B2 =>
mask16(29), C1 => n92, C2 => mask08(29), ZN => n61);
U33 : AOI222_X1 port map( A1 => n84, A2 => mask00(30), B1 => n43, B2 =>
mask16(30), C1 => n44, C2 => mask08(30), ZN => n59);
U63 : AOI222_X1 port map( A1 => n84, A2 => mask00(17), B1 => n43, B2 =>
mask16(17), C1 => n44, C2 => mask08(17), ZN => n74);
U67 : AOI222_X1 port map( A1 => n84, A2 => mask00(15), B1 => n43, B2 =>
mask16(15), C1 => n92, C2 => mask08(15), ZN => n76);
U65 : AOI222_X1 port map( A1 => n84, A2 => mask00(16), B1 => n43, B2 =>
mask16(16), C1 => n44, C2 => mask08(16), ZN => n75);
U61 : AOI222_X1 port map( A1 => n84, A2 => mask00(18), B1 => n43, B2 =>
mask16(18), C1 => n92, C2 => mask08(18), ZN => n73);
U73 : AOI222_X1 port map( A1 => n84, A2 => mask00(12), B1 => n43, B2 =>
mask16(12), C1 => n44, C2 => mask08(12), ZN => n79);
U69 : AOI222_X1 port map( A1 => n84, A2 => mask00(14), B1 => n43, B2 =>
mask16(14), C1 => n44, C2 => mask08(14), ZN => n77);
U71 : AOI222_X1 port map( A1 => n84, A2 => mask00(13), B1 => n43, B2 =>
mask16(13), C1 => n44, C2 => mask08(13), ZN => n78);
U75 : AOI222_X1 port map( A1 => n84, A2 => mask00(11), B1 => n43, B2 =>
mask16(11), C1 => n44, C2 => mask08(11), ZN => n80);
U78 : INV_X1 port map( A => n82, ZN => Y(0));
U34 : INV_X1 port map( A => n60, ZN => Y(2));
U12 : INV_X1 port map( A => n49, ZN => Y(4));
U8 : INV_X1 port map( A => n47, ZN => Y(6));
U10 : INV_X1 port map( A => n48, ZN => Y(5));
U56 : INV_X1 port map( A => n71, ZN => Y(1));
U14 : INV_X1 port map( A => n50, ZN => Y(3));
U28 : INV_X1 port map( A => n57, ZN => Y(32));
U24 : INV_X1 port map( A => n55, ZN => Y(34));
U20 : INV_X1 port map( A => n53, ZN => Y(36));
U16 : INV_X1 port map( A => n51, ZN => Y(38));
U22 : INV_X1 port map( A => n54, ZN => Y(35));
U30 : INV_X1 port map( A => n58, ZN => Y(31));
U26 : INV_X1 port map( A => n56, ZN => Y(33));
U18 : INV_X1 port map( A => n52, ZN => Y(37));
U48 : INV_X1 port map( A => n67, ZN => Y(23));
U44 : INV_X1 port map( A => n65, ZN => Y(25));
U58 : INV_X1 port map( A => n72, ZN => Y(19));
U52 : INV_X1 port map( A => n69, ZN => Y(21));
U42 : INV_X1 port map( A => n64, ZN => Y(26));
U46 : INV_X1 port map( A => n66, ZN => Y(24));
U54 : INV_X1 port map( A => n70, ZN => Y(20));
U50 : INV_X1 port map( A => n68, ZN => Y(22));
U40 : INV_X1 port map( A => n63, ZN => Y(27));
U38 : INV_X1 port map( A => n62, ZN => Y(28));
U2 : INV_X1 port map( A => n41, ZN => Y(9));
U76 : INV_X1 port map( A => n81, ZN => Y(10));
U4 : INV_X1 port map( A => n45, ZN => Y(8));
U36 : INV_X1 port map( A => n61, ZN => Y(29));
U32 : INV_X1 port map( A => n59, ZN => Y(30));
U62 : INV_X1 port map( A => n74, ZN => Y(17));
U66 : INV_X1 port map( A => n76, ZN => Y(15));
U64 : INV_X1 port map( A => n75, ZN => Y(16));
U60 : INV_X1 port map( A => n73, ZN => Y(18));
U72 : INV_X1 port map( A => n79, ZN => Y(12));
U68 : INV_X1 port map( A => n77, ZN => Y(14));
U70 : INV_X1 port map( A => n78, ZN => Y(13));
U74 : INV_X1 port map( A => n80, ZN => Y(11));
U6 : AOI222_X1 port map( A1 => n92, A2 => mask08(7), B1 => mask00(7), B2 =>
n84, C1 => mask16(7), C2 => n43, ZN => n46);
U7 : INV_X1 port map( A => n46, ZN => Y(7));
U80 : BUF_X2 port map( A => n42, Z => n84);
U81 : BUF_X1 port map( A => n44, Z => n92);
U82 : AND2_X2 port map( A1 => n83, A2 => sel(1), ZN => n43);
U83 : NOR2_X2 port map( A1 => sel(1), A2 => n83, ZN => n44);
U84 : INV_X1 port map( A => sel(0), ZN => n83);
U85 : NOR2_X1 port map( A1 => sel(1), A2 => sel(0), ZN => n42);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_firstLevel is
port( A : in std_logic_vector (31 downto 0); sel : in std_logic_vector (1
downto 0); mask00, mask08, mask16 : out std_logic_vector (38 downto
0));
end shift_firstLevel;
architecture SYN_behav of shift_firstLevel is
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal mask08_38_port, mask08_37_port, mask08_36_port, mask08_35_port,
mask08_34_port, mask08_33_port, mask08_32_port, mask08_31_port,
mask08_23_port, mask08_22_port, mask08_21_port, mask08_20_port,
mask08_19_port, mask08_18_port, mask08_17_port, mask08_16_port,
mask08_15_port, mask08_7_port, mask08_6_port, mask08_5_port,
mask08_4_port, mask08_3_port, mask08_2_port, mask08_1_port, mask08_0_port
, mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask16_31_port,
mask16_30_port, mask16_29_port, mask16_28_port, mask16_27_port,
mask16_26_port, mask16_25_port, mask16_24_port, mask16_23_port,
mask16_15_port, mask16_14_port, mask16_13_port, mask16_12_port,
mask16_11_port, mask16_10_port, mask16_9_port, mask16_8_port,
mask16_7_port, mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port
, mask16_2_port, mask16_1_port, mask16_0_port, n36, n37, n38, n39, n40,
n41, n42, n43, mask16_18_port, n45, n46, n47, n48, n49, n50, n51, n52,
n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67
, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n88, n89, n90, n91, n92, n93, n94, n95, n86, n87, n96
: std_logic;
begin
mask08 <= ( mask08_38_port, mask08_37_port, mask08_36_port, mask08_35_port,
mask08_34_port, mask08_33_port, mask08_32_port, mask08_31_port,
mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask08_23_port,
mask08_22_port, mask08_21_port, mask08_20_port, mask08_19_port,
mask08_18_port, mask08_17_port, mask08_16_port, mask08_15_port,
mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port, mask16_2_port
, mask16_1_port, mask16_0_port, mask08_7_port, mask08_6_port,
mask08_5_port, mask08_4_port, mask08_3_port, mask08_2_port, mask08_1_port
, mask08_0_port );
mask16 <= ( mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask16_31_port,
mask16_30_port, mask16_29_port, mask16_28_port, mask16_27_port,
mask16_26_port, mask16_25_port, mask16_24_port, mask16_23_port,
mask16_18_port, mask16_18_port, mask16_18_port, mask16_18_port,
mask16_18_port, mask16_18_port, mask16_18_port, mask16_15_port,
mask16_14_port, mask16_13_port, mask16_12_port, mask16_11_port,
mask16_10_port, mask16_9_port, mask16_8_port, mask16_7_port,
mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port, mask16_2_port
, mask16_1_port, mask16_0_port );
U137 : NAND2_X1 port map( A1 => sel(0), A2 => A(16), ZN => n67);
U62 : NAND2_X1 port map( A1 => sel(0), A2 => A(8), ZN => n84);
U131 : NAND2_X1 port map( A1 => sel(0), A2 => A(18), ZN => n53);
U155 : NAND2_X1 port map( A1 => sel(0), A2 => A(10), ZN => n81);
U125 : NAND2_X1 port map( A1 => sel(0), A2 => A(20), ZN => n41);
U149 : NAND2_X1 port map( A1 => sel(0), A2 => A(12), ZN => n71);
U119 : NAND2_X1 port map( A1 => sel(0), A2 => A(22), ZN => n39);
U143 : NAND2_X1 port map( A1 => sel(0), A2 => A(14), ZN => n69);
U122 : NAND2_X1 port map( A1 => sel(0), A2 => A(21), ZN => n40);
U146 : NAND2_X1 port map( A1 => sel(0), A2 => A(13), ZN => n70);
U67 : NAND2_X1 port map( A1 => n87, A2 => A(0), ZN => n60);
U116 : NAND2_X1 port map( A1 => sel(0), A2 => A(23), ZN => n38);
U140 : NAND2_X1 port map( A1 => sel(0), A2 => A(15), ZN => n68);
U134 : NAND2_X1 port map( A1 => sel(0), A2 => A(17), ZN => n61);
U59 : NAND2_X1 port map( A1 => sel(0), A2 => A(9), ZN => n83);
U129 : NAND2_X1 port map( A1 => sel(0), A2 => A(19), ZN => n42);
U152 : NAND2_X1 port map( A1 => sel(0), A2 => A(11), ZN => n72);
U91 : NAND2_X1 port map( A1 => sel(0), A2 => A(31), ZN => n82);
U85 : AOI21_X1 port map( B1 => A(25), B2 => n85, A => mask16_18_port, ZN =>
n94);
U138 : NAND2_X1 port map( A1 => n85, A2 => A(9), ZN => n50);
U15 : NAND2_X1 port map( A1 => n50, A2 => n96, ZN => mask16_32_port);
U112 : NAND2_X1 port map( A1 => n87, A2 => A(17), ZN => n79);
U44 : NAND2_X1 port map( A1 => n79, A2 => n96, ZN => mask08_32_port);
U81 : AOI21_X1 port map( B1 => A(27), B2 => n85, A => mask16_18_port, ZN =>
n92);
U132 : NAND2_X1 port map( A1 => n87, A2 => A(11), ZN => n48);
U13 : NAND2_X1 port map( A1 => n48, A2 => n96, ZN => mask16_34_port);
U106 : NAND2_X1 port map( A1 => n87, A2 => A(19), ZN => n77);
U42 : NAND2_X1 port map( A1 => n77, A2 => n96, ZN => mask08_34_port);
U77 : AOI21_X1 port map( B1 => A(29), B2 => n85, A => mask16_18_port, ZN =>
n90);
U124 : NAND2_X1 port map( A1 => n87, A2 => A(13), ZN => n46);
U11 : NAND2_X1 port map( A1 => n46, A2 => n96, ZN => mask16_36_port);
U100 : NAND2_X1 port map( A1 => n87, A2 => A(21), ZN => n75);
U40 : NAND2_X1 port map( A1 => n75, A2 => n96, ZN => mask08_36_port);
U73 : AOI21_X1 port map( B1 => A(31), B2 => n85, A => mask16_18_port, ZN =>
n88);
U118 : NAND2_X1 port map( A1 => n87, A2 => A(15), ZN => n43);
U9 : NAND2_X1 port map( A1 => n43, A2 => n96, ZN => mask16_38_port);
U93 : NAND2_X1 port map( A1 => n85, A2 => A(23), ZN => n73);
U38 : NAND2_X1 port map( A1 => n73, A2 => n96, ZN => mask08_38_port);
U79 : AOI21_X1 port map( B1 => A(28), B2 => n85, A => mask16_18_port, ZN =>
n91);
U128 : NAND2_X1 port map( A1 => n87, A2 => A(12), ZN => n47);
U12 : NAND2_X1 port map( A1 => n47, A2 => n96, ZN => mask16_35_port);
U103 : NAND2_X1 port map( A1 => n87, A2 => A(20), ZN => n76);
U41 : NAND2_X1 port map( A1 => n76, A2 => n96, ZN => mask08_35_port);
U89 : AOI21_X1 port map( B1 => A(24), B2 => n85, A => mask16_15_port, ZN =>
n95);
U141 : NAND2_X1 port map( A1 => n87, A2 => A(8), ZN => n51);
U16 : NAND2_X1 port map( A1 => n51, A2 => n96, ZN => mask16_31_port);
U115 : NAND2_X1 port map( A1 => n87, A2 => A(16), ZN => n80);
U45 : NAND2_X1 port map( A1 => n80, A2 => n96, ZN => mask08_31_port);
U83 : AOI21_X1 port map( B1 => A(26), B2 => n85, A => mask16_18_port, ZN =>
n93);
U135 : NAND2_X1 port map( A1 => n85, A2 => A(10), ZN => n49);
U14 : NAND2_X1 port map( A1 => n49, A2 => n96, ZN => mask16_33_port);
U109 : NAND2_X1 port map( A1 => n87, A2 => A(18), ZN => n78);
U43 : NAND2_X1 port map( A1 => n78, A2 => n96, ZN => mask08_33_port);
U75 : AOI21_X1 port map( B1 => A(30), B2 => n85, A => mask16_18_port, ZN =>
n89);
U121 : NAND2_X1 port map( A1 => n87, A2 => A(14), ZN => n45);
U10 : NAND2_X1 port map( A1 => n45, A2 => n96, ZN => mask16_37_port);
U97 : NAND2_X1 port map( A1 => n87, A2 => A(22), ZN => n74);
U39 : NAND2_X1 port map( A1 => n74, A2 => n96, ZN => mask08_37_port);
U114 : NAND2_X1 port map( A1 => n38, A2 => n80, ZN => mask00(23));
U25 : NAND2_X1 port map( A1 => n96, A2 => n60, ZN => mask16_23_port);
U47 : NAND2_X1 port map( A1 => n51, A2 => n82, ZN => mask08_23_port);
U110 : NAND2_X1 port map( A1 => sel(0), A2 => A(25), ZN => n36);
U108 : NAND2_X1 port map( A1 => n36, A2 => n78, ZN => mask00(25));
U60 : NAND2_X1 port map( A1 => n85, A2 => A(2), ZN => n58);
U23 : NAND2_X1 port map( A1 => n96, A2 => n58, ZN => mask16_25_port);
U127 : NAND2_X1 port map( A1 => n42, A2 => n47, ZN => mask00(19));
U153 : NAND2_X1 port map( A1 => n85, A2 => A(4), ZN => n56);
U104 : NAND2_X1 port map( A1 => sel(0), A2 => A(27), ZN => n65);
U52 : NAND2_X1 port map( A1 => n56, A2 => n65, ZN => mask08_19_port);
U120 : NAND2_X1 port map( A1 => n40, A2 => n45, ZN => mask00(21));
U147 : NAND2_X1 port map( A1 => n85, A2 => A(6), ZN => n54);
U98 : NAND2_X1 port map( A1 => sel(0), A2 => A(29), ZN => n63);
U49 : NAND2_X1 port map( A1 => n54, A2 => n63, ZN => mask08_21_port);
U107 : NAND2_X1 port map( A1 => sel(0), A2 => A(26), ZN => n66);
U105 : NAND2_X1 port map( A1 => n66, A2 => n77, ZN => mask00(26));
U156 : NAND2_X1 port map( A1 => n87, A2 => A(3), ZN => n57);
U22 : NAND2_X1 port map( A1 => n57, A2 => n96, ZN => mask16_26_port);
U113 : NAND2_X1 port map( A1 => sel(0), A2 => A(24), ZN => n37);
U111 : NAND2_X1 port map( A1 => n37, A2 => n79, ZN => mask00(24));
U63 : NAND2_X1 port map( A1 => n85, A2 => A(1), ZN => n59);
U24 : NAND2_X1 port map( A1 => n96, A2 => n59, ZN => mask16_24_port);
U123 : NAND2_X1 port map( A1 => n41, A2 => n46, ZN => mask00(20));
U150 : NAND2_X1 port map( A1 => n85, A2 => A(5), ZN => n55);
U101 : NAND2_X1 port map( A1 => sel(0), A2 => A(28), ZN => n64);
U50 : NAND2_X1 port map( A1 => n55, A2 => n64, ZN => mask08_20_port);
U117 : NAND2_X1 port map( A1 => n39, A2 => n43, ZN => mask00(22));
U144 : NAND2_X1 port map( A1 => n85, A2 => A(7), ZN => n52);
U94 : NAND2_X1 port map( A1 => sel(0), A2 => A(30), ZN => n62);
U48 : NAND2_X1 port map( A1 => n52, A2 => n62, ZN => mask08_22_port);
U102 : NAND2_X1 port map( A1 => n65, A2 => n76, ZN => mask00(27));
U21 : NAND2_X1 port map( A1 => n56, A2 => n96, ZN => mask16_27_port);
U99 : NAND2_X1 port map( A1 => n64, A2 => n75, ZN => mask00(28));
U20 : NAND2_X1 port map( A1 => n55, A2 => n96, ZN => mask16_28_port);
U58 : NAND2_X1 port map( A1 => n58, A2 => n83, ZN => mask00(9));
U154 : NAND2_X1 port map( A1 => n57, A2 => n81, ZN => mask00(10));
U61 : NAND2_X1 port map( A1 => n59, A2 => n84, ZN => mask00(8));
U96 : NAND2_X1 port map( A1 => n63, A2 => n74, ZN => mask00(29));
U19 : NAND2_X1 port map( A1 => n54, A2 => n96, ZN => mask16_29_port);
U92 : NAND2_X1 port map( A1 => n62, A2 => n73, ZN => mask00(30));
U17 : NAND2_X1 port map( A1 => n52, A2 => n96, ZN => mask16_30_port);
U133 : NAND2_X1 port map( A1 => n49, A2 => n61, ZN => mask00(17));
U54 : NAND2_X1 port map( A1 => n36, A2 => n58, ZN => mask08_17_port);
U139 : NAND2_X1 port map( A1 => n51, A2 => n68, ZN => mask00(15));
U56 : NAND2_X1 port map( A1 => n38, A2 => n60, ZN => mask08_15_port);
U136 : NAND2_X1 port map( A1 => n50, A2 => n67, ZN => mask00(16));
U55 : NAND2_X1 port map( A1 => n37, A2 => n59, ZN => mask08_16_port);
U130 : NAND2_X1 port map( A1 => n48, A2 => n53, ZN => mask00(18));
U53 : NAND2_X1 port map( A1 => n57, A2 => n66, ZN => mask08_18_port);
U148 : NAND2_X1 port map( A1 => n55, A2 => n71, ZN => mask00(12));
U142 : NAND2_X1 port map( A1 => n52, A2 => n69, ZN => mask00(14));
U145 : NAND2_X1 port map( A1 => n54, A2 => n70, ZN => mask00(13));
U151 : NAND2_X1 port map( A1 => n56, A2 => n72, ZN => mask00(11));
U158 : AND2_X1 port map( A1 => sel(0), A2 => A(0), ZN => mask00(0));
U32 : INV_X1 port map( A => n67, ZN => mask16_0_port);
U57 : INV_X1 port map( A => n84, ZN => mask08_0_port);
U95 : AND2_X1 port map( A1 => sel(0), A2 => A(2), ZN => mask00(2));
U18 : INV_X1 port map( A => n53, ZN => mask16_2_port);
U46 : INV_X1 port map( A => n81, ZN => mask08_2_port);
U70 : AND2_X1 port map( A1 => sel(0), A2 => A(4), ZN => mask00(4));
U7 : INV_X1 port map( A => n41, ZN => mask16_4_port);
U36 : INV_X1 port map( A => n71, ZN => mask08_4_port);
U68 : AND2_X1 port map( A1 => sel(0), A2 => A(6), ZN => mask00(6));
U5 : INV_X1 port map( A => n39, ZN => mask16_6_port);
U34 : INV_X1 port map( A => n69, ZN => mask08_6_port);
U69 : AND2_X1 port map( A1 => sel(0), A2 => A(5), ZN => mask00(5));
U6 : INV_X1 port map( A => n40, ZN => mask16_5_port);
U35 : INV_X1 port map( A => n70, ZN => mask08_5_port);
U126 : AND2_X1 port map( A1 => sel(0), A2 => A(1), ZN => mask00(1));
U26 : INV_X1 port map( A => n61, ZN => mask16_1_port);
U51 : INV_X1 port map( A => n83, ZN => mask08_1_port);
U71 : AND2_X1 port map( A1 => sel(0), A2 => A(3), ZN => mask00(3));
U8 : INV_X1 port map( A => n42, ZN => mask16_3_port);
U37 : INV_X1 port map( A => n72, ZN => mask08_3_port);
U90 : INV_X1 port map( A => n82, ZN => mask16_15_port);
U84 : INV_X1 port map( A => n94, ZN => mask00(32));
U80 : INV_X1 port map( A => n92, ZN => mask00(34));
U76 : INV_X1 port map( A => n90, ZN => mask00(36));
U72 : INV_X1 port map( A => n88, ZN => mask00(38));
U78 : INV_X1 port map( A => n91, ZN => mask00(35));
U88 : INV_X1 port map( A => n95, ZN => mask00(31));
U82 : INV_X1 port map( A => n93, ZN => mask00(33));
U74 : INV_X1 port map( A => n89, ZN => mask00(37));
U2 : INV_X1 port map( A => n36, ZN => mask16_9_port);
U31 : INV_X1 port map( A => n66, ZN => mask16_10_port);
U3 : INV_X1 port map( A => n37, ZN => mask16_8_port);
U29 : INV_X1 port map( A => n64, ZN => mask16_12_port);
U27 : INV_X1 port map( A => n62, ZN => mask16_14_port);
U28 : INV_X1 port map( A => n63, ZN => mask16_13_port);
U30 : INV_X1 port map( A => n65, ZN => mask16_11_port);
U4 : INV_X1 port map( A => n68, ZN => mask08_7_port);
U33 : INV_X1 port map( A => n38, ZN => mask16_7_port);
U64 : NAND2_X1 port map( A1 => sel(0), A2 => A(7), ZN => n86);
U65 : NAND2_X1 port map( A1 => n60, A2 => n86, ZN => mask00(7));
U66 : AND2_X2 port map( A1 => sel(1), A2 => mask16_15_port, ZN =>
mask16_18_port);
U86 : INV_X2 port map( A => mask16_18_port, ZN => n96);
U87 : BUF_X1 port map( A => n85, Z => n87);
U157 : NOR2_X2 port map( A1 => sel(0), A2 => sel(1), ZN => n85);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity sum_gen_N32 is
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic_vector
(8 downto 0); S : out std_logic_vector (31 downto 0));
end sum_gen_N32;
architecture SYN_STRUCTURAL of sum_gen_N32 is
component carry_sel_gen_N4_1
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_2
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_3
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_4
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_5
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_6
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_7
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_0
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal net539424, net539425, net539426, net539427, net539428, net539429,
net539430, net539431 : std_logic;
begin
csel_N_0 : carry_sel_gen_N4_0 port map( A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), Ci => Cin(0), S(3) => S(3),
S(2) => S(2), S(1) => S(1), S(0) => S(0), Co =>
net539431);
csel_N_1 : carry_sel_gen_N4_7 port map( A(3) => A(7), A(2) => A(6), A(1) =>
A(5), A(0) => A(4), B(3) => B(7), B(2) => B(6), B(1)
=> B(5), B(0) => B(4), Ci => Cin(1), S(3) => S(7),
S(2) => S(6), S(1) => S(5), S(0) => S(4), Co =>
net539430);
csel_N_2 : carry_sel_gen_N4_6 port map( A(3) => A(11), A(2) => A(10), A(1)
=> A(9), A(0) => A(8), B(3) => B(11), B(2) => B(10),
B(1) => B(9), B(0) => B(8), Ci => Cin(2), S(3) =>
S(11), S(2) => S(10), S(1) => S(9), S(0) => S(8), Co
=> net539429);
csel_N_3 : carry_sel_gen_N4_5 port map( A(3) => A(15), A(2) => A(14), A(1)
=> A(13), A(0) => A(12), B(3) => B(15), B(2) =>
B(14), B(1) => B(13), B(0) => B(12), Ci => Cin(3),
S(3) => S(15), S(2) => S(14), S(1) => S(13), S(0) =>
S(12), Co => net539428);
csel_N_4 : carry_sel_gen_N4_4 port map( A(3) => A(19), A(2) => A(18), A(1)
=> A(17), A(0) => A(16), B(3) => B(19), B(2) =>
B(18), B(1) => B(17), B(0) => B(16), Ci => Cin(4),
S(3) => S(19), S(2) => S(18), S(1) => S(17), S(0) =>
S(16), Co => net539427);
csel_N_5 : carry_sel_gen_N4_3 port map( A(3) => A(23), A(2) => A(22), A(1)
=> A(21), A(0) => A(20), B(3) => B(23), B(2) =>
B(22), B(1) => B(21), B(0) => B(20), Ci => Cin(5),
S(3) => S(23), S(2) => S(22), S(1) => S(21), S(0) =>
S(20), Co => net539426);
csel_N_6 : carry_sel_gen_N4_2 port map( A(3) => A(27), A(2) => A(26), A(1)
=> A(25), A(0) => A(24), B(3) => B(27), B(2) =>
B(26), B(1) => B(25), B(0) => B(24), Ci => Cin(6),
S(3) => S(27), S(2) => S(26), S(1) => S(25), S(0) =>
S(24), Co => net539425);
csel_N_7 : carry_sel_gen_N4_1 port map( A(3) => A(31), A(2) => A(30), A(1)
=> A(29), A(0) => A(28), B(3) => B(31), B(2) =>
B(30), B(1) => B(29), B(0) => B(28), Ci => Cin(7),
S(3) => S(31), S(2) => S(30), S(1) => S(29), S(0) =>
S(28), Co => net539424);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_tree_N32_logN5 is
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic; Cout :
out std_logic_vector (7 downto 0));
end carry_tree_N32_logN5;
architecture SYN_arch of carry_tree_N32_logN5 is
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component pg_1
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_2
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_3
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_4
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_5
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component g_1
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_2
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_3
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_4
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_5
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_6
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_7
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_6
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_7
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_8
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_9
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_10
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_11
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_12
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component g_8
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_13
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_14
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_15
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_16
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_17
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_18
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_19
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_20
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_21
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_22
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_23
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_24
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_25
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_26
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_0
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component g_9
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_0
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_net_1
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_2
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_3
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_4
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_5
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_6
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_7
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_8
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_9
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_10
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_11
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_12
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_13
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_14
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_15
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_16
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_17
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_18
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_19
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_20
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_21
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_22
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_23
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_24
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_25
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_26
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_27
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_28
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_29
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_30
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_31
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_0
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
signal Cout_7_port, Cout_6_port, Cout_5_port, Cout_4_port, n9, Cout_2_port,
n10, n11, p_net_31_port, p_net_30_port, p_net_29_port, p_net_28_port,
p_net_27_port, p_net_26_port, p_net_25_port, p_net_24_port, p_net_23_port
, p_net_22_port, p_net_21_port, p_net_20_port, p_net_19_port,
p_net_18_port, p_net_17_port, p_net_16_port, p_net_15_port, p_net_14_port
, p_net_13_port, p_net_12_port, p_net_11_port, p_net_10_port,
p_net_9_port, p_net_8_port, p_net_7_port, p_net_6_port, p_net_5_port,
p_net_4_port, p_net_3_port, p_net_2_port, p_net_1_port, g_net_31_port,
g_net_30_port, g_net_29_port, g_net_28_port, g_net_27_port, g_net_26_port
, g_net_25_port, g_net_24_port, g_net_23_port, g_net_22_port,
g_net_21_port, g_net_20_port, g_net_19_port, g_net_18_port, g_net_17_port
, g_net_16_port, g_net_15_port, g_net_14_port, g_net_13_port,
g_net_12_port, g_net_11_port, g_net_10_port, g_net_9_port, g_net_8_port,
g_net_7_port, g_net_6_port, g_net_5_port, g_net_4_port, g_net_3_port,
g_net_2_port, g_net_1_port, g_net_0_port, magic_pro_1_port,
magic_pro_0_port, pg_1_15_1_port, pg_1_15_0_port, pg_1_14_1_port,
pg_1_14_0_port, pg_1_13_1_port, pg_1_13_0_port, pg_1_12_1_port,
pg_1_12_0_port, pg_1_11_1_port, pg_1_11_0_port, pg_1_10_1_port,
pg_1_10_0_port, pg_1_9_1_port, pg_1_9_0_port, pg_1_8_1_port,
pg_1_8_0_port, pg_1_7_1_port, pg_1_7_0_port, pg_1_6_1_port, pg_1_6_0_port
, pg_1_5_1_port, pg_1_5_0_port, pg_1_4_1_port, pg_1_4_0_port,
pg_1_3_1_port, pg_1_3_0_port, pg_1_2_1_port, pg_1_2_0_port, pg_1_1_1_port
, pg_1_1_0_port, pg_1_0_0_port, pg_n_4_7_1_port, pg_n_4_7_0_port,
pg_n_4_6_1_port, pg_n_4_6_0_port, pg_n_3_7_1_port, pg_n_3_7_0_port,
pg_n_3_5_1_port, pg_n_3_5_0_port, pg_n_3_3_1_port, pg_n_3_3_0_port,
pg_n_2_7_1_port, pg_n_2_7_0_port, pg_n_2_6_1_port, pg_n_2_6_0_port,
pg_n_2_5_1_port, pg_n_2_5_0_port, pg_n_2_4_1_port, pg_n_2_4_0_port,
pg_n_2_3_1_port, pg_n_2_3_0_port, pg_n_2_2_1_port, pg_n_2_2_0_port,
pg_n_2_1_1_port, pg_n_2_1_0_port, n1, Cout_3_port, Cout_1_port, n5,
Cout_0_port, n7, n8 : std_logic;
begin
Cout <= ( Cout_7_port, Cout_6_port, Cout_5_port, Cout_4_port, Cout_3_port,
Cout_2_port, Cout_1_port, Cout_0_port );
pg_net_x_1 : pg_net_0 port map( a => A(1), b => B(1), g_out => g_net_1_port,
p_out => p_net_1_port);
pg_net_x_2 : pg_net_31 port map( a => A(2), b => B(2), g_out => g_net_2_port
, p_out => p_net_2_port);
pg_net_x_3 : pg_net_30 port map( a => A(3), b => B(3), g_out => g_net_3_port
, p_out => p_net_3_port);
pg_net_x_4 : pg_net_29 port map( a => A(4), b => B(4), g_out => g_net_4_port
, p_out => p_net_4_port);
pg_net_x_5 : pg_net_28 port map( a => A(5), b => B(5), g_out => g_net_5_port
, p_out => p_net_5_port);
pg_net_x_6 : pg_net_27 port map( a => A(6), b => B(6), g_out => g_net_6_port
, p_out => p_net_6_port);
pg_net_x_7 : pg_net_26 port map( a => A(7), b => B(7), g_out => g_net_7_port
, p_out => p_net_7_port);
pg_net_x_8 : pg_net_25 port map( a => A(8), b => B(8), g_out => g_net_8_port
, p_out => p_net_8_port);
pg_net_x_9 : pg_net_24 port map( a => A(9), b => B(9), g_out => g_net_9_port
, p_out => p_net_9_port);
pg_net_x_10 : pg_net_23 port map( a => A(10), b => B(10), g_out =>
g_net_10_port, p_out => p_net_10_port);
pg_net_x_11 : pg_net_22 port map( a => A(11), b => B(11), g_out =>
g_net_11_port, p_out => p_net_11_port);
pg_net_x_12 : pg_net_21 port map( a => A(12), b => B(12), g_out =>
g_net_12_port, p_out => p_net_12_port);
pg_net_x_13 : pg_net_20 port map( a => A(13), b => B(13), g_out =>
g_net_13_port, p_out => p_net_13_port);
pg_net_x_14 : pg_net_19 port map( a => A(14), b => B(14), g_out =>
g_net_14_port, p_out => p_net_14_port);
pg_net_x_15 : pg_net_18 port map( a => A(15), b => B(15), g_out =>
g_net_15_port, p_out => p_net_15_port);
pg_net_x_16 : pg_net_17 port map( a => A(16), b => B(16), g_out =>
g_net_16_port, p_out => p_net_16_port);
pg_net_x_17 : pg_net_16 port map( a => A(17), b => B(17), g_out =>
g_net_17_port, p_out => p_net_17_port);
pg_net_x_18 : pg_net_15 port map( a => A(18), b => B(18), g_out =>
g_net_18_port, p_out => p_net_18_port);
pg_net_x_19 : pg_net_14 port map( a => A(19), b => B(19), g_out =>
g_net_19_port, p_out => p_net_19_port);
pg_net_x_20 : pg_net_13 port map( a => A(20), b => B(20), g_out =>
g_net_20_port, p_out => p_net_20_port);
pg_net_x_21 : pg_net_12 port map( a => A(21), b => B(21), g_out =>
g_net_21_port, p_out => p_net_21_port);
pg_net_x_22 : pg_net_11 port map( a => A(22), b => B(22), g_out =>
g_net_22_port, p_out => p_net_22_port);
pg_net_x_23 : pg_net_10 port map( a => A(23), b => B(23), g_out =>
g_net_23_port, p_out => p_net_23_port);
pg_net_x_24 : pg_net_9 port map( a => A(24), b => B(24), g_out =>
g_net_24_port, p_out => p_net_24_port);
pg_net_x_25 : pg_net_8 port map( a => A(25), b => B(25), g_out =>
g_net_25_port, p_out => p_net_25_port);
pg_net_x_26 : pg_net_7 port map( a => A(26), b => B(26), g_out =>
g_net_26_port, p_out => p_net_26_port);
pg_net_x_27 : pg_net_6 port map( a => A(27), b => B(27), g_out =>
g_net_27_port, p_out => p_net_27_port);
pg_net_x_28 : pg_net_5 port map( a => A(28), b => B(28), g_out =>
g_net_28_port, p_out => p_net_28_port);
pg_net_x_29 : pg_net_4 port map( a => A(29), b => B(29), g_out =>
g_net_29_port, p_out => p_net_29_port);
pg_net_x_30 : pg_net_3 port map( a => A(30), b => B(30), g_out =>
g_net_30_port, p_out => p_net_30_port);
pg_net_x_31 : pg_net_2 port map( a => A(31), b => B(31), g_out =>
g_net_31_port, p_out => p_net_31_port);
pg_net_0_MAGIC : pg_net_1 port map( a => A(0), b => B(0), g_out =>
magic_pro_0_port, p_out => magic_pro_1_port);
xG_0_0_MAGIC : g_0 port map( g => magic_pro_0_port, p => magic_pro_1_port,
g_prec => Cin, g_out => g_net_0_port);
xG_1_0 : g_9 port map( g => g_net_1_port, p => p_net_1_port, g_prec =>
g_net_0_port, g_out => pg_1_0_0_port);
xPG_1_1 : pg_0 port map( g => g_net_3_port, p => p_net_3_port, g_prec =>
g_net_2_port, p_prec => p_net_2_port, g_out =>
pg_1_1_0_port, p_out => pg_1_1_1_port);
xPG_1_2 : pg_26 port map( g => g_net_5_port, p => p_net_5_port, g_prec =>
g_net_4_port, p_prec => p_net_4_port, g_out =>
pg_1_2_0_port, p_out => pg_1_2_1_port);
xPG_1_3 : pg_25 port map( g => g_net_7_port, p => p_net_7_port, g_prec =>
g_net_6_port, p_prec => p_net_6_port, p_out =>
pg_1_3_1_port, g_out_BAR => pg_1_3_0_port);
xPG_1_4 : pg_24 port map( g => g_net_9_port, p => p_net_9_port, g_prec =>
g_net_8_port, p_prec => p_net_8_port, g_out =>
pg_1_4_0_port, p_out => pg_1_4_1_port);
xPG_1_5 : pg_23 port map( g => g_net_11_port, p => p_net_11_port, g_prec =>
g_net_10_port, p_prec => p_net_10_port, p_out =>
pg_1_5_1_port, g_out_BAR => pg_1_5_0_port);
xPG_1_6 : pg_22 port map( g => g_net_13_port, p => p_net_13_port, g_prec =>
g_net_12_port, p_prec => p_net_12_port, g_out =>
pg_1_6_0_port, p_out => pg_1_6_1_port);
xPG_1_7 : pg_21 port map( g => g_net_15_port, p => p_net_15_port, g_prec =>
g_net_14_port, p_prec => p_net_14_port, p_out =>
pg_1_7_1_port, g_out_BAR => pg_1_7_0_port);
xPG_1_8 : pg_20 port map( g => g_net_17_port, p => p_net_17_port, g_prec =>
g_net_16_port, p_prec => p_net_16_port, g_out =>
pg_1_8_0_port, p_out => pg_1_8_1_port);
xPG_1_9 : pg_19 port map( g => g_net_19_port, p => p_net_19_port, g_prec =>
g_net_18_port, p_prec => p_net_18_port, p_out =>
pg_1_9_1_port, g_out_BAR => pg_1_9_0_port);
xPG_1_10 : pg_18 port map( g => g_net_21_port, p => p_net_21_port, g_prec =>
g_net_20_port, p_prec => p_net_20_port, g_out =>
pg_1_10_0_port, p_out => pg_1_10_1_port);
xPG_1_11 : pg_17 port map( g => g_net_23_port, p => p_net_23_port, g_prec =>
g_net_22_port, p_prec => p_net_22_port, g_out =>
pg_1_11_0_port, p_out => pg_1_11_1_port);
xPG_1_12 : pg_16 port map( g => g_net_25_port, p => p_net_25_port, g_prec =>
g_net_24_port, p_prec => p_net_24_port, g_out =>
pg_1_12_0_port, p_out => pg_1_12_1_port);
xPG_1_13 : pg_15 port map( g => g_net_27_port, p => p_net_27_port, g_prec =>
g_net_26_port, p_prec => p_net_26_port, g_out =>
pg_1_13_0_port, p_out => pg_1_13_1_port);
xPG_1_14 : pg_14 port map( g => g_net_29_port, p => p_net_29_port, g_prec =>
g_net_28_port, p_prec => p_net_28_port, g_out =>
pg_1_14_0_port, p_out => pg_1_14_1_port);
xPG_1_15 : pg_13 port map( g => g_net_31_port, p => p_net_31_port, g_prec =>
g_net_30_port, p_prec => p_net_30_port, g_out =>
pg_1_15_0_port, p_out => pg_1_15_1_port);
xG_2_0 : g_8 port map( g => pg_1_1_0_port, p => pg_1_1_1_port, g_prec =>
pg_1_0_0_port, g_out => n11);
xPG_2_1 : pg_12 port map( p => pg_1_3_1_port, g_prec => pg_1_2_0_port,
p_prec => pg_1_2_1_port, g_out => pg_n_2_1_0_port,
p_out => pg_n_2_1_1_port, g_BAR => pg_1_3_0_port);
xPG_2_2 : pg_11 port map( p => pg_1_5_1_port, g_prec => pg_1_4_0_port,
p_prec => pg_1_4_1_port, g_out => pg_n_2_2_0_port,
p_out => pg_n_2_2_1_port, g_BAR => pg_1_5_0_port);
xPG_2_3 : pg_10 port map( p => pg_1_7_1_port, g_prec => pg_1_6_0_port,
p_prec => pg_1_6_1_port, g_out => pg_n_2_3_0_port,
p_out => pg_n_2_3_1_port, g_BAR => pg_1_7_0_port);
xPG_2_4 : pg_9 port map( p => pg_1_9_1_port, g_prec => pg_1_8_0_port, p_prec
=> pg_1_8_1_port, g_out => pg_n_2_4_0_port, p_out =>
pg_n_2_4_1_port, g_BAR => pg_1_9_0_port);
xPG_2_5 : pg_8 port map( g => pg_1_11_0_port, p => pg_1_11_1_port, g_prec =>
pg_1_10_0_port, p_prec => pg_1_10_1_port, p_out =>
pg_n_2_5_1_port, g_out_BAR => pg_n_2_5_0_port);
xPG_2_6 : pg_7 port map( g => pg_1_13_0_port, p => pg_1_13_1_port, g_prec =>
pg_1_12_0_port, p_prec => pg_1_12_1_port, g_out =>
pg_n_2_6_0_port, p_out => pg_n_2_6_1_port);
xPG_2_7 : pg_6 port map( g => pg_1_15_0_port, p => pg_1_15_1_port, g_prec =>
pg_1_14_0_port, p_prec => pg_1_14_1_port, g_out =>
pg_n_2_7_0_port, p_out => pg_n_2_7_1_port);
xG_3_1 : g_7 port map( g => pg_n_2_1_0_port, p => pg_n_2_1_1_port, g_prec =>
n11, g_out => n10);
xG_4_2 : g_6 port map( g => pg_n_2_2_0_port, p => pg_n_2_2_1_port, g_prec =>
n8, g_out => Cout_2_port);
xG_4_3 : g_5 port map( g => pg_n_3_3_0_port, p => pg_n_3_3_1_port, g_prec =>
n10, g_out => n9);
xG_5_4 : g_4 port map( g => n5, p => pg_n_2_4_1_port, g_prec => n9, g_out =>
Cout_4_port);
xG_5_5 : g_3 port map( g => n7, p => pg_n_3_5_1_port, g_prec => n9, g_out =>
Cout_5_port);
xG_5_6 : g_2 port map( g => pg_n_4_6_0_port, p => pg_n_4_6_1_port, g_prec =>
n9, g_out => Cout_6_port);
xG_5_7 : g_1 port map( g => pg_n_4_7_0_port, p => pg_n_4_7_1_port, g_prec =>
n1, g_out => Cout_7_port);
xPG_3_3 : pg_5 port map( g => pg_n_2_3_0_port, p => pg_n_2_3_1_port, g_prec
=> pg_n_2_2_0_port, p_prec => pg_n_2_2_1_port, g_out
=> pg_n_3_3_0_port, p_out => pg_n_3_3_1_port);
xPG_3_5 : pg_4 port map( p => pg_n_2_5_1_port, g_prec => pg_n_2_4_0_port,
p_prec => pg_n_2_4_1_port, g_out => pg_n_3_5_0_port,
p_out => pg_n_3_5_1_port, g_BAR => pg_n_2_5_0_port);
xPG_3_7 : pg_3 port map( g => pg_n_2_7_0_port, p => pg_n_2_7_1_port, g_prec
=> pg_n_2_6_0_port, p_prec => pg_n_2_6_1_port, g_out
=> pg_n_3_7_0_port, p_out => pg_n_3_7_1_port);
xPG_4_6 : pg_2 port map( g => pg_n_2_6_0_port, p => pg_n_2_6_1_port, g_prec
=> pg_n_3_5_0_port, p_prec => pg_n_3_5_1_port, g_out
=> pg_n_4_6_0_port, p_out => pg_n_4_6_1_port);
xPG_4_7 : pg_1 port map( g => pg_n_3_7_0_port, p => pg_n_3_7_1_port, g_prec
=> n7, p_prec => pg_n_3_5_1_port, g_out =>
pg_n_4_7_0_port, p_out => pg_n_4_7_1_port);
U1 : CLKBUF_X1 port map( A => Cout_3_port, Z => n1);
U2 : BUF_X1 port map( A => n9, Z => Cout_3_port);
U3 : CLKBUF_X1 port map( A => pg_n_3_5_0_port, Z => n7);
U4 : CLKBUF_X1 port map( A => n11, Z => Cout_0_port);
U5 : CLKBUF_X1 port map( A => pg_n_2_4_0_port, Z => n5);
U6 : CLKBUF_X1 port map( A => n8, Z => Cout_1_port);
U7 : CLKBUF_X1 port map( A => n10, Z => n8);
end SYN_arch;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity xor_gen_N32 is
port( A : in std_logic_vector (31 downto 0); B : in std_logic; S : out
std_logic_vector (31 downto 0));
end xor_gen_N32;
architecture SYN_bhe of xor_gen_N32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component XNOR2_X2
port( A, B : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component XOR2_X2
port( A, B : in std_logic; Z : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n13, n1, n2, n3, n4, n6, n7, n8, n9, n10, n11 : std_logic;
begin
U8 : XOR2_X1 port map( A => B, B => A(31), Z => S(31));
U9 : XOR2_X1 port map( A => B, B => A(30), Z => S(30));
U12 : XOR2_X1 port map( A => B, B => A(28), Z => S(28));
U15 : XOR2_X1 port map( A => B, B => A(25), Z => S(25));
U17 : XOR2_X1 port map( A => B, B => A(23), Z => S(23));
U26 : XOR2_X1 port map( A => A(15), B => B, Z => S(15));
U30 : XOR2_X1 port map( A => B, B => A(11), Z => S(11));
U16 : XOR2_X1 port map( A => B, B => A(24), Z => S(24));
U1 : XOR2_X1 port map( A => A(20), B => B, Z => S(20));
U2 : XNOR2_X1 port map( A => n2, B => A(3), ZN => S(3));
U3 : MUX2_X1 port map( A => B, B => n2, S => A(7), Z => S(7));
U4 : XNOR2_X1 port map( A => A(8), B => n2, ZN => S(8));
U5 : XOR2_X1 port map( A => B, B => A(29), Z => S(29));
U6 : XOR2_X1 port map( A => B, B => A(26), Z => S(26));
U7 : XNOR2_X1 port map( A => A(27), B => n2, ZN => S(27));
U10 : XOR2_X2 port map( A => B, B => A(22), Z => S(22));
U11 : OAI21_X1 port map( B1 => A(13), B2 => n2, A => n4, ZN => S(13));
U13 : OAI21_X1 port map( B1 => n2, B2 => A(0), A => n1, ZN => S(0));
U14 : NAND2_X1 port map( A1 => A(0), A2 => n2, ZN => n1);
U18 : XNOR2_X2 port map( A => A(19), B => n2, ZN => S(19));
U19 : INV_X2 port map( A => B, ZN => n2);
U20 : XNOR2_X2 port map( A => A(12), B => n2, ZN => S(12));
U21 : XNOR2_X2 port map( A => A(21), B => n2, ZN => S(21));
U22 : XNOR2_X1 port map( A => A(17), B => n2, ZN => S(17));
U23 : XNOR2_X2 port map( A => A(16), B => n2, ZN => S(16));
U24 : XOR2_X1 port map( A => B, B => A(18), Z => S(18));
U25 : XOR2_X1 port map( A => A(2), B => B, Z => S(2));
U27 : BUF_X2 port map( A => n13, Z => S(6));
U28 : INV_X1 port map( A => A(9), ZN => n9);
U29 : INV_X1 port map( A => A(14), ZN => n6);
U31 : NAND2_X1 port map( A1 => A(1), A2 => n2, ZN => n3);
U32 : OAI21_X1 port map( B1 => A(1), B2 => n2, A => n3, ZN => S(1));
U33 : NAND2_X1 port map( A1 => A(13), A2 => n2, ZN => n4);
U34 : NAND2_X1 port map( A1 => n10, A2 => n11, ZN => S(9));
U35 : NAND2_X1 port map( A1 => n7, A2 => n8, ZN => S(14));
U36 : XOR2_X1 port map( A => B, B => A(10), Z => S(10));
U37 : XOR2_X1 port map( A => B, B => A(5), Z => S(5));
U38 : XOR2_X1 port map( A => B, B => A(6), Z => n13);
U39 : XOR2_X1 port map( A => A(4), B => B, Z => S(4));
U40 : NAND2_X1 port map( A1 => B, A2 => n6, ZN => n7);
U41 : NAND2_X1 port map( A1 => A(14), A2 => n2, ZN => n8);
U42 : NAND2_X1 port map( A1 => B, A2 => n9, ZN => n10);
U43 : NAND2_X1 port map( A1 => n2, A2 => A(9), ZN => n11);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity ff32_en_SIZE32 is
port( D : in std_logic_vector (31 downto 0); en, clk, rst : in std_logic;
Q : out std_logic_vector (31 downto 0));
end ff32_en_SIZE32;
architecture SYN_behavioral of ff32_en_SIZE32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component DFFR_X1
port( D, CK, RN : in std_logic; Q, QN : out std_logic);
end component;
signal n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93
, n94, n95, n97, net549739, net549740, net549741, net549742, net549743,
net549744, net549745, net549746, net549747, net549748, net549749,
net549750, net549751, net549752, net549753, net549754, net549755,
net549756, net549757, net549758, net549759, net549760, net549761,
net549762, net549763, net549764, net549765, net549766, net549767,
net549768, net549769, net549770, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11
, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n1, n34 : std_logic;
begin
Q_reg_31_inst : DFFR_X1 port map( D => n97, CK => clk, RN => n34, Q => Q(31)
, QN => net549770);
Q_reg_30_inst : DFFR_X1 port map( D => n95, CK => clk, RN => n34, Q => Q(30)
, QN => net549769);
Q_reg_29_inst : DFFR_X1 port map( D => n94, CK => clk, RN => n34, Q => Q(29)
, QN => net549768);
Q_reg_28_inst : DFFR_X1 port map( D => n93, CK => clk, RN => n34, Q => Q(28)
, QN => net549767);
Q_reg_27_inst : DFFR_X1 port map( D => n92, CK => clk, RN => n34, Q => Q(27)
, QN => net549766);
Q_reg_26_inst : DFFR_X1 port map( D => n91, CK => clk, RN => n34, Q => Q(26)
, QN => net549765);
Q_reg_25_inst : DFFR_X1 port map( D => n90, CK => clk, RN => n34, Q => Q(25)
, QN => net549764);
Q_reg_24_inst : DFFR_X1 port map( D => n89, CK => clk, RN => n34, Q => Q(24)
, QN => net549763);
Q_reg_23_inst : DFFR_X1 port map( D => n88, CK => clk, RN => n34, Q => Q(23)
, QN => net549762);
Q_reg_22_inst : DFFR_X1 port map( D => n87, CK => clk, RN => n34, Q => Q(22)
, QN => net549761);
Q_reg_21_inst : DFFR_X1 port map( D => n86, CK => clk, RN => n34, Q => Q(21)
, QN => net549760);
Q_reg_19_inst : DFFR_X1 port map( D => n84, CK => clk, RN => n34, Q => Q(19)
, QN => net549758);
Q_reg_18_inst : DFFR_X1 port map( D => n83, CK => clk, RN => n34, Q => Q(18)
, QN => net549757);
Q_reg_17_inst : DFFR_X1 port map( D => n82, CK => clk, RN => n34, Q => Q(17)
, QN => net549756);
Q_reg_16_inst : DFFR_X1 port map( D => n81, CK => clk, RN => n34, Q => Q(16)
, QN => net549755);
Q_reg_15_inst : DFFR_X1 port map( D => n80, CK => clk, RN => n34, Q => Q(15)
, QN => net549754);
Q_reg_14_inst : DFFR_X1 port map( D => n79, CK => clk, RN => n34, Q => Q(14)
, QN => net549753);
Q_reg_13_inst : DFFR_X1 port map( D => n78, CK => clk, RN => n34, Q => Q(13)
, QN => net549752);
Q_reg_12_inst : DFFR_X1 port map( D => n77, CK => clk, RN => n34, Q => Q(12)
, QN => net549751);
Q_reg_11_inst : DFFR_X1 port map( D => n76, CK => clk, RN => n34, Q => Q(11)
, QN => net549750);
Q_reg_10_inst : DFFR_X1 port map( D => n75, CK => clk, RN => n34, Q => Q(10)
, QN => net549749);
Q_reg_9_inst : DFFR_X1 port map( D => n74, CK => clk, RN => n34, Q => Q(9),
QN => net549748);
Q_reg_8_inst : DFFR_X1 port map( D => n73, CK => clk, RN => n34, Q => Q(8),
QN => net549747);
Q_reg_7_inst : DFFR_X1 port map( D => n72, CK => clk, RN => n34, Q => Q(7),
QN => net549746);
Q_reg_6_inst : DFFR_X1 port map( D => n71, CK => clk, RN => n34, Q => Q(6),
QN => net549745);
Q_reg_5_inst : DFFR_X1 port map( D => n70, CK => clk, RN => n34, Q => Q(5),
QN => net549744);
Q_reg_4_inst : DFFR_X1 port map( D => n69, CK => clk, RN => n34, Q => Q(4),
QN => net549743);
Q_reg_3_inst : DFFR_X1 port map( D => n68, CK => clk, RN => n34, Q => Q(3),
QN => net549742);
Q_reg_2_inst : DFFR_X1 port map( D => n67, CK => clk, RN => n34, Q => Q(2),
QN => net549741);
Q_reg_1_inst : DFFR_X1 port map( D => n66, CK => clk, RN => n34, Q => Q(1),
QN => net549740);
Q_reg_0_inst : DFFR_X1 port map( D => n65, CK => clk, RN => n34, Q => Q(0),
QN => net549739);
U9 : OAI21_X1 port map( B1 => en, B2 => net549767, A => n5, ZN => n93);
U21 : OAI21_X1 port map( B1 => en, B2 => net549761, A => n11, ZN => n87);
U7 : OAI21_X1 port map( B1 => en, B2 => net549768, A => n4, ZN => n94);
U2 : OAI21_X1 port map( B1 => en, B2 => net549770, A => n2, ZN => n97);
U17 : OAI21_X1 port map( B1 => en, B2 => net549763, A => n9, ZN => n89);
U11 : OAI21_X1 port map( B1 => en, B2 => net549766, A => n6, ZN => n92);
U19 : OAI21_X1 port map( B1 => en, B2 => net549762, A => n10, ZN => n88);
U13 : OAI21_X1 port map( B1 => en, B2 => net549765, A => n7, ZN => n91);
U40 : NAND2_X1 port map( A1 => en, A2 => D(13), ZN => n20);
U39 : OAI21_X1 port map( B1 => en, B2 => net549752, A => n20, ZN => n78);
U36 : NAND2_X1 port map( A1 => en, A2 => D(15), ZN => n18);
U35 : OAI21_X1 port map( B1 => en, B2 => net549754, A => n18, ZN => n80);
U32 : NAND2_X1 port map( A1 => en, A2 => D(17), ZN => n16);
U31 : OAI21_X1 port map( B1 => en, B2 => net549756, A => n16, ZN => n82);
U30 : NAND2_X1 port map( A1 => en, A2 => D(18), ZN => n15);
U29 : OAI21_X1 port map( B1 => en, B2 => net549757, A => n15, ZN => n83);
U34 : NAND2_X1 port map( A1 => en, A2 => D(16), ZN => n17);
U33 : OAI21_X1 port map( B1 => en, B2 => net549755, A => n17, ZN => n81);
U27 : OAI21_X1 port map( B1 => en, B2 => net549758, A => n14, ZN => n84);
U38 : NAND2_X1 port map( A1 => en, A2 => D(14), ZN => n19);
U37 : OAI21_X1 port map( B1 => en, B2 => net549753, A => n19, ZN => n79);
U42 : NAND2_X1 port map( A1 => en, A2 => D(12), ZN => n21);
U41 : OAI21_X1 port map( B1 => en, B2 => net549751, A => n21, ZN => n77);
U44 : NAND2_X1 port map( A1 => en, A2 => D(11), ZN => n22);
U43 : OAI21_X1 port map( B1 => en, B2 => net549750, A => n22, ZN => n76);
U50 : NAND2_X1 port map( A1 => en, A2 => D(8), ZN => n25);
U49 : OAI21_X1 port map( B1 => en, B2 => net549747, A => n25, ZN => n73);
U48 : NAND2_X1 port map( A1 => en, A2 => D(9), ZN => n24);
U47 : OAI21_X1 port map( B1 => en, B2 => net549748, A => n24, ZN => n74);
U46 : NAND2_X1 port map( A1 => en, A2 => D(10), ZN => n23);
U45 : OAI21_X1 port map( B1 => en, B2 => net549749, A => n23, ZN => n75);
U52 : NAND2_X1 port map( A1 => en, A2 => D(7), ZN => n26);
U51 : OAI21_X1 port map( B1 => en, B2 => net549746, A => n26, ZN => n72);
U54 : NAND2_X1 port map( A1 => en, A2 => D(6), ZN => n27);
U53 : OAI21_X1 port map( B1 => en, B2 => net549745, A => n27, ZN => n71);
U60 : NAND2_X1 port map( A1 => en, A2 => D(3), ZN => n30);
U59 : OAI21_X1 port map( B1 => en, B2 => net549742, A => n30, ZN => n68);
U56 : NAND2_X1 port map( A1 => en, A2 => D(5), ZN => n28);
U55 : OAI21_X1 port map( B1 => en, B2 => net549744, A => n28, ZN => n70);
U58 : NAND2_X1 port map( A1 => en, A2 => D(4), ZN => n29);
U57 : OAI21_X1 port map( B1 => en, B2 => net549743, A => n29, ZN => n69);
U62 : NAND2_X1 port map( A1 => en, A2 => D(2), ZN => n31);
U61 : OAI21_X1 port map( B1 => en, B2 => net549741, A => n31, ZN => n67);
U64 : NAND2_X1 port map( A1 => en, A2 => D(1), ZN => n32);
U63 : OAI21_X1 port map( B1 => en, B2 => net549740, A => n32, ZN => n66);
U66 : NAND2_X1 port map( A1 => en, A2 => D(0), ZN => n33);
U65 : OAI21_X1 port map( B1 => en, B2 => net549739, A => n33, ZN => n65);
Q_reg_20_inst : DFFR_X1 port map( D => n85, CK => clk, RN => n34, Q => Q(20)
, QN => net549759);
U3 : NAND2_X1 port map( A1 => en, A2 => D(21), ZN => n1);
U4 : OAI21_X1 port map( B1 => en, B2 => net549760, A => n1, ZN => n86);
U5 : INV_X2 port map( A => rst, ZN => n34);
U6 : OAI21_X1 port map( B1 => en, B2 => net549769, A => n3, ZN => n95);
U8 : NAND2_X1 port map( A1 => en, A2 => D(30), ZN => n3);
U10 : OAI21_X1 port map( B1 => en, B2 => net549764, A => n8, ZN => n90);
U12 : NAND2_X1 port map( A1 => en, A2 => D(25), ZN => n8);
U14 : NAND2_X1 port map( A1 => en, A2 => D(24), ZN => n9);
U15 : NAND2_X1 port map( A1 => en, A2 => D(26), ZN => n7);
U16 : OAI21_X1 port map( B1 => en, B2 => net549759, A => n13, ZN => n85);
U18 : NAND2_X1 port map( A1 => en, A2 => D(20), ZN => n13);
U20 : NAND2_X1 port map( A1 => en, A2 => D(27), ZN => n6);
U22 : NAND2_X1 port map( A1 => en, A2 => D(23), ZN => n10);
U23 : NAND2_X1 port map( A1 => en, A2 => D(19), ZN => n14);
U24 : NAND2_X1 port map( A1 => en, A2 => D(22), ZN => n11);
U25 : NAND2_X1 port map( A1 => en, A2 => D(28), ZN => n5);
U26 : NAND2_X1 port map( A1 => en, A2 => D(29), ZN => n4);
U28 : NAND2_X1 port map( A1 => en, A2 => D(31), ZN => n2);
end SYN_behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity piso_r_2_N32 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (31 downto 0);
SO : out std_logic_vector (31 downto 0));
end piso_r_2_N32;
architecture SYN_archi of piso_r_2_N32 is
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
signal SO_31_port, SO_30_port, SO_29_port, SO_28_port, SO_27_port,
SO_26_port, SO_25_port, SO_24_port, SO_23_port, SO_22_port, SO_21_port,
SO_20_port, SO_19_port, SO_18_port, SO_17_port, SO_16_port, SO_15_port,
SO_14_port, SO_13_port, SO_12_port, SO_11_port, SO_10_port, SO_9_port,
SO_8_port, SO_7_port, SO_6_port, SO_5_port, SO_4_port, SO_3_port,
SO_2_port, SO_1_port, SO_0_port, N3, N4, N5, N6, N7, N8, N9, N10, N11,
N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26
, N27, N28, N29, N30, N31, N32, net549709, net549710, net549711,
net549712, net549713, net549714, net549715, net549716, net549717,
net549718, net549719, net549720, net549721, net549722, net549723,
net549724, net549725, net549726, net549727, net549728, net549729,
net549730, net549731, net549732, net549733, net549734, net549735,
net549736, net549737, net549738, n1, n3_port, n4_port, n5_port, n6_port,
n9_port, n10_port, n11_port, n12_port, n13_port, n14_port, n15_port,
n16_port, n17_port, n19_port, n20_port, n21_port, n22_port, n23_port,
n24_port, n25_port, n26_port, n27_port, n28_port, n29_port, n30_port,
n31_port, n32_port, n2, n7_port : std_logic;
begin
SO <= ( SO_31_port, SO_30_port, SO_29_port, SO_28_port, SO_27_port,
SO_26_port, SO_25_port, SO_24_port, SO_23_port, SO_22_port, SO_21_port,
SO_20_port, SO_19_port, SO_18_port, SO_17_port, SO_16_port, SO_15_port,
SO_14_port, SO_13_port, SO_12_port, SO_11_port, SO_10_port, SO_9_port,
SO_8_port, SO_7_port, SO_6_port, SO_5_port, SO_4_port, SO_3_port,
SO_2_port, SO_1_port, SO_0_port );
tmp_reg_1_inst : DFF_X1 port map( D => N4, CK => Clock, Q => SO_1_port, QN
=> net549738);
tmp_reg_3_inst : DFF_X1 port map( D => N6, CK => Clock, Q => SO_3_port, QN
=> net549737);
tmp_reg_5_inst : DFF_X1 port map( D => N8, CK => Clock, Q => SO_5_port, QN
=> net549736);
tmp_reg_7_inst : DFF_X1 port map( D => N10, CK => Clock, Q => SO_7_port, QN
=> net549735);
tmp_reg_9_inst : DFF_X1 port map( D => N12, CK => Clock, Q => SO_9_port, QN
=> net549734);
tmp_reg_11_inst : DFF_X1 port map( D => N14, CK => Clock, Q => SO_11_port,
QN => net549733);
tmp_reg_13_inst : DFF_X1 port map( D => N16, CK => Clock, Q => SO_13_port,
QN => net549732);
tmp_reg_15_inst : DFF_X1 port map( D => N18, CK => Clock, Q => SO_15_port,
QN => net549731);
tmp_reg_17_inst : DFF_X1 port map( D => N20, CK => Clock, Q => SO_17_port,
QN => net549730);
tmp_reg_19_inst : DFF_X1 port map( D => N22, CK => Clock, Q => SO_19_port,
QN => net549729);
tmp_reg_21_inst : DFF_X1 port map( D => N24, CK => Clock, Q => SO_21_port,
QN => net549728);
tmp_reg_23_inst : DFF_X1 port map( D => N26, CK => Clock, Q => SO_23_port,
QN => net549727);
tmp_reg_25_inst : DFF_X1 port map( D => N28, CK => Clock, Q => SO_25_port,
QN => net549726);
tmp_reg_27_inst : DFF_X1 port map( D => N30, CK => Clock, Q => SO_27_port,
QN => net549725);
tmp_reg_29_inst : DFF_X1 port map( D => N32, CK => Clock, Q => SO_29_port,
QN => net549724);
tmp_reg_0_inst : DFF_X1 port map( D => N3, CK => Clock, Q => SO_0_port, QN
=> net549723);
tmp_reg_2_inst : DFF_X1 port map( D => N5, CK => Clock, Q => SO_2_port, QN
=> net549722);
tmp_reg_4_inst : DFF_X1 port map( D => N7, CK => Clock, Q => SO_4_port, QN
=> net549721);
tmp_reg_6_inst : DFF_X1 port map( D => N9, CK => Clock, Q => SO_6_port, QN
=> net549720);
tmp_reg_8_inst : DFF_X1 port map( D => N11, CK => Clock, Q => SO_8_port, QN
=> net549719);
tmp_reg_10_inst : DFF_X1 port map( D => N13, CK => Clock, Q => SO_10_port,
QN => net549718);
tmp_reg_12_inst : DFF_X1 port map( D => N15, CK => Clock, Q => SO_12_port,
QN => net549717);
tmp_reg_14_inst : DFF_X1 port map( D => N17, CK => Clock, Q => SO_14_port,
QN => net549716);
tmp_reg_16_inst : DFF_X1 port map( D => N19, CK => Clock, Q => SO_16_port,
QN => net549715);
tmp_reg_18_inst : DFF_X1 port map( D => N21, CK => Clock, Q => SO_18_port,
QN => net549714);
tmp_reg_20_inst : DFF_X1 port map( D => N23, CK => Clock, Q => SO_20_port,
QN => net549713);
tmp_reg_22_inst : DFF_X1 port map( D => N25, CK => Clock, Q => SO_22_port,
QN => net549712);
tmp_reg_24_inst : DFF_X1 port map( D => N27, CK => Clock, Q => SO_24_port,
QN => net549711);
tmp_reg_26_inst : DFF_X1 port map( D => N29, CK => Clock, Q => SO_26_port,
QN => net549710);
tmp_reg_28_inst : DFF_X1 port map( D => N31, CK => Clock, Q => SO_28_port,
QN => net549709);
U26 : NAND2_X1 port map( A1 => ALOAD, A2 => D(26), ZN => n12_port);
U25 : OAI21_X1 port map( B1 => ALOAD, B2 => net549711, A => n12_port, ZN =>
N29);
U30 : NAND2_X1 port map( A1 => ALOAD, A2 => D(24), ZN => n14_port);
U29 : OAI21_X1 port map( B1 => ALOAD, B2 => net549712, A => n14_port, ZN =>
N27);
U32 : NAND2_X1 port map( A1 => ALOAD, A2 => D(23), ZN => n15_port);
U31 : OAI21_X1 port map( B1 => ALOAD, B2 => net549728, A => n15_port, ZN =>
N26);
U36 : NAND2_X1 port map( A1 => ALOAD, A2 => D(21), ZN => n17_port);
U35 : OAI21_X1 port map( B1 => ALOAD, B2 => net549729, A => n17_port, ZN =>
N24);
U38 : NAND2_X1 port map( A1 => ALOAD, A2 => D(20), ZN => n19_port);
U37 : OAI21_X1 port map( B1 => ALOAD, B2 => net549714, A => n19_port, ZN =>
N23);
U42 : NAND2_X1 port map( A1 => ALOAD, A2 => D(18), ZN => n21_port);
U41 : OAI21_X1 port map( B1 => ALOAD, B2 => net549715, A => n21_port, ZN =>
N21);
U44 : NAND2_X1 port map( A1 => ALOAD, A2 => D(17), ZN => n22_port);
U43 : OAI21_X1 port map( B1 => ALOAD, B2 => net549731, A => n22_port, ZN =>
N20);
U34 : NAND2_X1 port map( A1 => ALOAD, A2 => D(22), ZN => n16_port);
U33 : OAI21_X1 port map( B1 => ALOAD, B2 => net549713, A => n16_port, ZN =>
N25);
U46 : NAND2_X1 port map( A1 => ALOAD, A2 => D(16), ZN => n23_port);
U45 : OAI21_X1 port map( B1 => ALOAD, B2 => net549716, A => n23_port, ZN =>
N19);
U19 : NAND2_X1 port map( A1 => ALOAD, A2 => D(29), ZN => n9_port);
U18 : OAI21_X1 port map( B1 => ALOAD, B2 => net549725, A => n9_port, ZN =>
N32);
U23 : NAND2_X1 port map( A1 => ALOAD, A2 => D(27), ZN => n11_port);
U22 : OAI21_X1 port map( B1 => ALOAD, B2 => net549726, A => n11_port, ZN =>
N30);
U28 : NAND2_X1 port map( A1 => ALOAD, A2 => D(25), ZN => n13_port);
U27 : OAI21_X1 port map( B1 => ALOAD, B2 => net549727, A => n13_port, ZN =>
N28);
U21 : NAND2_X1 port map( A1 => ALOAD, A2 => D(28), ZN => n10_port);
U20 : OAI21_X1 port map( B1 => ALOAD, B2 => net549710, A => n10_port, ZN =>
N31);
U40 : NAND2_X1 port map( A1 => ALOAD, A2 => D(19), ZN => n20_port);
U39 : OAI21_X1 port map( B1 => ALOAD, B2 => net549730, A => n20_port, ZN =>
N22);
U12 : NAND2_X1 port map( A1 => ALOAD, A2 => D(2), ZN => n6_port);
U11 : OAI21_X1 port map( B1 => ALOAD, B2 => net549723, A => n6_port, ZN =>
N5);
U50 : NAND2_X1 port map( A1 => ALOAD, A2 => D(14), ZN => n25_port);
U49 : OAI21_X1 port map( B1 => ALOAD, B2 => net549717, A => n25_port, ZN =>
N17);
U54 : NAND2_X1 port map( A1 => ALOAD, A2 => D(12), ZN => n27_port);
U53 : OAI21_X1 port map( B1 => ALOAD, B2 => net549718, A => n27_port, ZN =>
N15);
U58 : NAND2_X1 port map( A1 => ALOAD, A2 => D(10), ZN => n29_port);
U57 : OAI21_X1 port map( B1 => ALOAD, B2 => net549719, A => n29_port, ZN =>
N13);
U62 : NAND2_X1 port map( A1 => ALOAD, A2 => D(8), ZN => n31_port);
U61 : OAI21_X1 port map( B1 => ALOAD, B2 => net549720, A => n31_port, ZN =>
N11);
U4 : NAND2_X1 port map( A1 => ALOAD, A2 => D(6), ZN => n1);
U3 : OAI21_X1 port map( B1 => ALOAD, B2 => net549721, A => n1, ZN => N9);
U8 : NAND2_X1 port map( A1 => ALOAD, A2 => D(4), ZN => n4_port);
U7 : OAI21_X1 port map( B1 => ALOAD, B2 => net549722, A => n4_port, ZN => N7
);
U64 : NAND2_X1 port map( A1 => ALOAD, A2 => D(7), ZN => n32_port);
U63 : OAI21_X1 port map( B1 => ALOAD, B2 => net549736, A => n32_port, ZN =>
N10);
U48 : NAND2_X1 port map( A1 => ALOAD, A2 => D(15), ZN => n24_port);
U47 : OAI21_X1 port map( B1 => ALOAD, B2 => net549732, A => n24_port, ZN =>
N18);
U52 : NAND2_X1 port map( A1 => ALOAD, A2 => D(13), ZN => n26_port);
U51 : OAI21_X1 port map( B1 => ALOAD, B2 => net549733, A => n26_port, ZN =>
N16);
U56 : NAND2_X1 port map( A1 => ALOAD, A2 => D(11), ZN => n28_port);
U55 : OAI21_X1 port map( B1 => ALOAD, B2 => net549734, A => n28_port, ZN =>
N14);
U60 : NAND2_X1 port map( A1 => ALOAD, A2 => D(9), ZN => n30_port);
U59 : OAI21_X1 port map( B1 => ALOAD, B2 => net549735, A => n30_port, ZN =>
N12);
U10 : NAND2_X1 port map( A1 => ALOAD, A2 => D(3), ZN => n5_port);
U9 : OAI21_X1 port map( B1 => ALOAD, B2 => net549738, A => n5_port, ZN => N6
);
U6 : NAND2_X1 port map( A1 => ALOAD, A2 => D(5), ZN => n3_port);
U5 : OAI21_X1 port map( B1 => ALOAD, B2 => net549737, A => n3_port, ZN => N8
);
U24 : AND2_X1 port map( A1 => ALOAD, A2 => D(0), ZN => N3);
U13 : AND2_X1 port map( A1 => ALOAD, A2 => D(1), ZN => N4);
tmp_reg_31_inst : SDFF_X1 port map( D => SO_29_port, SI => D(31), SE =>
ALOAD, CK => Clock, Q => SO_31_port, QN => n7_port);
tmp_reg_30_inst : SDFF_X1 port map( D => SO_28_port, SI => D(30), SE =>
ALOAD, CK => Clock, Q => SO_30_port, QN => n2);
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_2 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_2;
architecture SYN_archi of shift_N9_2 is
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n11);
tmp_reg_0_inst : SDFF_X1 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n10);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n9);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n8);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n7);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n6);
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n5);
tmp_reg_8_inst : SDFF_X1 port map( D => n3, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n4);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n2);
n3 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_0 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_0;
architecture SYN_archi of shift_N9_0 is
component SDFF_X2
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n11);
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n10);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n9);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n8);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n7);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n6);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n5);
tmp_reg_8_inst : SDFF_X1 port map( D => n3, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n4);
tmp_reg_0_inst : SDFF_X2 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n2);
n3 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_0 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_0;
architecture SYN_bhe of booth_encoder_0 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal N53, N57, n5, n6 : std_logic;
begin
A_out <= ( N57, B_in(2), N53 );
U3 : INV_X1 port map( A => B_in(1), ZN => n5);
U4 : INV_X1 port map( A => B_in(2), ZN => n6);
U5 : NAND2_X1 port map( A1 => n6, A2 => n5, ZN => N57);
U6 : NOR2_X1 port map( A1 => B_in(1), A2 => n6, ZN => N53);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity logic_unit_SIZE32 is
port( IN1, IN2 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end logic_unit_SIZE32;
architecture SYN_Bhe of logic_unit_SIZE32 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31
, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60
, n61, n62, n63, n64, n166, n167, n169 : std_logic;
begin
U25 : AOI21_X1 port map( B1 => IN2(31), B2 => IN1(31), A => CTRL(0), ZN =>
n17);
U24 : OAI22_X1 port map( A1 => IN1(31), A2 => IN2(31), B1 => n2, B2 => n17,
ZN => n18);
U23 : AOI21_X1 port map( B1 => n169, B2 => n17, A => n18, ZN => OUT1(31));
U65 : AOI21_X1 port map( B1 => n2, B2 => n45, A => n46, ZN => OUT1(19));
U61 : AOI21_X1 port map( B1 => IN2(20), B2 => IN1(20), A => CTRL(0), ZN =>
n41);
U60 : OAI22_X1 port map( A1 => IN1(20), A2 => IN2(20), B1 => n169, B2 => n41
, ZN => n42);
U59 : AOI21_X1 port map( B1 => n169, B2 => n41, A => n42, ZN => OUT1(20));
U56 : AOI21_X1 port map( B1 => n2, B2 => n39, A => n40, ZN => OUT1(21));
U20 : AOI21_X1 port map( B1 => n169, B2 => n15, A => n16, ZN => OUT1(3));
U54 : OAI22_X1 port map( A1 => IN1(22), A2 => IN2(22), B1 => n169, B2 => n37
, ZN => n38);
U53 : AOI21_X1 port map( B1 => n169, B2 => n37, A => n38, ZN => OUT1(22));
U49 : AOI21_X1 port map( B1 => IN2(24), B2 => IN1(24), A => CTRL(0), ZN =>
n33);
U48 : OAI22_X1 port map( A1 => IN1(24), A2 => IN2(24), B1 => n2, B2 => n33,
ZN => n34);
U47 : AOI21_X1 port map( B1 => n169, B2 => n33, A => n34, ZN => OUT1(24));
U77 : AOI21_X1 port map( B1 => n169, B2 => n53, A => n54, ZN => OUT1(15));
U5 : AOI21_X1 port map( B1 => n2, B2 => n5, A => n6, ZN => OUT1(8));
U11 : AOI21_X1 port map( B1 => n2, B2 => n9, A => n10, ZN => OUT1(6));
U46 : AOI21_X1 port map( B1 => IN2(25), B2 => IN1(25), A => CTRL(0), ZN =>
n31);
U45 : OAI22_X1 port map( A1 => IN1(25), A2 => IN2(25), B1 => n2, B2 => n31,
ZN => n32);
U44 : AOI21_X1 port map( B1 => n169, B2 => n31, A => n32, ZN => OUT1(25));
U71 : AOI21_X1 port map( B1 => n169, B2 => n49, A => n50, ZN => OUT1(17));
U86 : AOI21_X1 port map( B1 => n2, B2 => n59, A => n60, ZN => OUT1(12));
U76 : AOI21_X1 port map( B1 => IN2(16), B2 => IN1(16), A => CTRL(0), ZN =>
n51);
U75 : OAI22_X1 port map( A1 => IN1(16), A2 => IN2(16), B1 => n2, B2 => n51,
ZN => n52);
U74 : AOI21_X1 port map( B1 => n169, B2 => n51, A => n52, ZN => OUT1(16));
U37 : AOI21_X1 port map( B1 => IN2(28), B2 => IN1(28), A => CTRL(0), ZN =>
n25);
U36 : OAI22_X1 port map( A1 => IN1(28), A2 => IN2(28), B1 => n2, B2 => n25,
ZN => n26);
U35 : AOI21_X1 port map( B1 => n169, B2 => n25, A => n26, ZN => OUT1(28));
U19 : AOI21_X1 port map( B1 => IN2(4), B2 => IN1(4), A => CTRL(0), ZN => n13
);
U18 : OAI22_X1 port map( A1 => IN1(4), A2 => IN2(4), B1 => n169, B2 => n13,
ZN => n14);
U17 : AOI21_X1 port map( B1 => n169, B2 => n13, A => n14, ZN => OUT1(4));
U40 : AOI21_X1 port map( B1 => IN2(27), B2 => IN1(27), A => CTRL(0), ZN =>
n27);
U39 : OAI22_X1 port map( A1 => IN1(27), A2 => IN2(27), B1 => n2, B2 => n27,
ZN => n28);
U38 : AOI21_X1 port map( B1 => n2, B2 => n27, A => n28, ZN => OUT1(27));
U14 : AOI21_X1 port map( B1 => n2, B2 => n11, A => n12, ZN => OUT1(5));
U83 : AOI21_X1 port map( B1 => n169, B2 => n57, A => n58, ZN => OUT1(13));
U2 : AOI21_X1 port map( B1 => n2, B2 => n3, A => n4, ZN => OUT1(9));
U8 : AOI21_X1 port map( B1 => n169, B2 => n7, A => n8, ZN => OUT1(7));
U80 : AOI21_X1 port map( B1 => n2, B2 => n55, A => n56, ZN => OUT1(14));
U68 : AOI21_X1 port map( B1 => n169, B2 => n47, A => n48, ZN => OUT1(18));
U50 : AOI21_X1 port map( B1 => n169, B2 => n35, A => n36, ZN => OUT1(23));
U41 : AOI21_X1 port map( B1 => n2, B2 => n29, A => n30, ZN => OUT1(26));
U34 : AOI21_X1 port map( B1 => IN2(29), B2 => IN1(29), A => CTRL(0), ZN =>
n23);
U33 : OAI22_X1 port map( A1 => IN1(29), A2 => IN2(29), B1 => n2, B2 => n23,
ZN => n24);
U32 : AOI21_X1 port map( B1 => n169, B2 => n23, A => n24, ZN => OUT1(29));
U31 : AOI21_X1 port map( B1 => IN2(2), B2 => IN1(2), A => CTRL(0), ZN => n21
);
U30 : OAI22_X1 port map( A1 => IN1(2), A2 => IN2(2), B1 => n2, B2 => n21, ZN
=> n22);
U29 : AOI21_X1 port map( B1 => n2, B2 => n21, A => n22, ZN => OUT1(2));
U62 : AOI21_X1 port map( B1 => n169, B2 => n43, A => n44, ZN => OUT1(1));
U28 : AOI21_X1 port map( B1 => IN2(30), B2 => IN1(30), A => CTRL(0), ZN =>
n19);
U27 : OAI22_X1 port map( A1 => IN1(30), A2 => IN2(30), B1 => n2, B2 => n19,
ZN => n20);
U26 : AOI21_X1 port map( B1 => n2, B2 => n19, A => n20, ZN => OUT1(30));
U89 : AOI21_X1 port map( B1 => n169, B2 => n61, A => n62, ZN => OUT1(11));
U92 : AOI21_X1 port map( B1 => n169, B2 => n63, A => n64, ZN => OUT1(10));
U3 : AOI21_X1 port map( B1 => IN1(0), B2 => IN2(0), A => CTRL(0), ZN => n166
);
U4 : OAI22_X1 port map( A1 => IN2(0), A2 => IN1(0), B1 => n2, B2 => n166, ZN
=> n167);
U6 : AOI21_X1 port map( B1 => n2, B2 => n166, A => n167, ZN => OUT1(0));
U7 : INV_X2 port map( A => CTRL(1), ZN => n2);
U9 : BUF_X2 port map( A => n2, Z => n169);
U10 : OAI22_X1 port map( A1 => IN1(18), A2 => IN2(18), B1 => n169, B2 => n47
, ZN => n48);
U12 : AOI21_X1 port map( B1 => IN2(18), B2 => IN1(18), A => CTRL(0), ZN =>
n47);
U13 : OAI22_X1 port map( A1 => IN1(10), A2 => IN2(10), B1 => n2, B2 => n63,
ZN => n64);
U15 : AOI21_X1 port map( B1 => IN2(10), B2 => IN1(10), A => CTRL(0), ZN =>
n63);
U16 : OAI22_X1 port map( A1 => IN1(21), A2 => IN2(21), B1 => n169, B2 => n39
, ZN => n40);
U21 : AOI21_X1 port map( B1 => IN2(21), B2 => IN1(21), A => CTRL(0), ZN =>
n39);
U22 : OAI22_X1 port map( A1 => IN1(26), A2 => IN2(26), B1 => n169, B2 => n29
, ZN => n30);
U42 : AOI21_X1 port map( B1 => IN2(26), B2 => IN1(26), A => CTRL(0), ZN =>
n29);
U43 : OAI22_X1 port map( A1 => IN1(12), A2 => IN2(12), B1 => n2, B2 => n59,
ZN => n60);
U51 : AOI21_X1 port map( B1 => IN2(12), B2 => IN1(12), A => CTRL(0), ZN =>
n59);
U52 : OAI22_X1 port map( A1 => IN1(3), A2 => IN2(3), B1 => n169, B2 => n15,
ZN => n16);
U55 : AOI21_X1 port map( B1 => IN2(3), B2 => IN1(3), A => CTRL(0), ZN => n15
);
U57 : OAI22_X1 port map( A1 => IN1(1), A2 => IN2(1), B1 => n169, B2 => n43,
ZN => n44);
U58 : AOI21_X1 port map( B1 => IN2(1), B2 => IN1(1), A => CTRL(0), ZN => n43
);
U63 : OAI22_X1 port map( A1 => IN1(17), A2 => IN2(17), B1 => n169, B2 => n49
, ZN => n50);
U64 : AOI21_X1 port map( B1 => IN2(17), B2 => IN1(17), A => CTRL(0), ZN =>
n49);
U66 : OAI22_X1 port map( A1 => IN1(14), A2 => IN2(14), B1 => n2, B2 => n55,
ZN => n56);
U67 : AOI21_X1 port map( B1 => IN2(14), B2 => IN1(14), A => CTRL(0), ZN =>
n55);
U69 : OAI22_X1 port map( A1 => IN1(23), A2 => IN2(23), B1 => n169, B2 => n35
, ZN => n36);
U70 : AOI21_X1 port map( B1 => IN2(23), B2 => IN1(23), A => CTRL(0), ZN =>
n35);
U72 : OAI22_X1 port map( A1 => IN1(13), A2 => IN2(13), B1 => n2, B2 => n57,
ZN => n58);
U73 : AOI21_X1 port map( B1 => IN2(13), B2 => IN1(13), A => CTRL(0), ZN =>
n57);
U78 : OAI22_X1 port map( A1 => IN1(8), A2 => IN2(8), B1 => n2, B2 => n5, ZN
=> n6);
U79 : AOI21_X1 port map( B1 => IN2(8), B2 => IN1(8), A => CTRL(0), ZN => n5)
;
U81 : OAI22_X1 port map( A1 => IN1(6), A2 => IN2(6), B1 => n2, B2 => n9, ZN
=> n10);
U82 : AOI21_X1 port map( B1 => IN2(6), B2 => IN1(6), A => CTRL(0), ZN => n9)
;
U84 : OAI22_X1 port map( A1 => IN1(19), A2 => IN2(19), B1 => n169, B2 => n45
, ZN => n46);
U85 : AOI21_X1 port map( B1 => IN2(19), B2 => IN1(19), A => CTRL(0), ZN =>
n45);
U87 : OAI22_X1 port map( A1 => IN1(15), A2 => IN2(15), B1 => n2, B2 => n53,
ZN => n54);
U88 : AOI21_X1 port map( B1 => IN2(15), B2 => IN1(15), A => CTRL(0), ZN =>
n53);
U90 : AOI21_X1 port map( B1 => IN2(22), B2 => IN1(22), A => CTRL(0), ZN =>
n37);
U91 : OAI22_X1 port map( A1 => IN1(11), A2 => IN2(11), B1 => n2, B2 => n61,
ZN => n62);
U93 : AOI21_X1 port map( B1 => IN2(11), B2 => IN1(11), A => CTRL(0), ZN =>
n61);
U94 : OAI22_X1 port map( A1 => IN1(7), A2 => IN2(7), B1 => n2, B2 => n7, ZN
=> n8);
U95 : AOI21_X1 port map( B1 => IN2(7), B2 => IN1(7), A => CTRL(0), ZN => n7)
;
U96 : OAI22_X1 port map( A1 => IN1(9), A2 => IN2(9), B1 => n2, B2 => n3, ZN
=> n4);
U97 : AOI21_X1 port map( B1 => IN2(9), B2 => IN1(9), A => CTRL(0), ZN => n3)
;
U98 : OAI22_X1 port map( A1 => IN1(5), A2 => IN2(5), B1 => n169, B2 => n11,
ZN => n12);
U99 : AOI21_X1 port map( B1 => IN2(5), B2 => IN1(5), A => CTRL(0), ZN => n11
);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shifter is
port( A : in std_logic_vector (31 downto 0); B : in std_logic_vector (4
downto 0); LOGIC_ARITH, LEFT_RIGHT : in std_logic; OUTPUT : out
std_logic_vector (31 downto 0));
end shifter;
architecture SYN_struct of shifter is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component shift_thirdLevel
port( sel : in std_logic_vector (2 downto 0); A : in std_logic_vector
(38 downto 0); Y : out std_logic_vector (31 downto 0));
end component;
component shift_secondLevel
port( sel : in std_logic_vector (1 downto 0); mask00, mask08, mask16 :
in std_logic_vector (38 downto 0); Y : out std_logic_vector (38
downto 0));
end component;
component shift_firstLevel
port( A : in std_logic_vector (31 downto 0); sel : in std_logic_vector
(1 downto 0); mask00, mask08, mask16 : out std_logic_vector (38
downto 0));
end component;
signal s3_2_port, s3_1_port, s3_0_port, m0_38_port, m0_37_port, m0_36_port,
m0_35_port, m0_34_port, m0_33_port, m0_32_port, m0_31_port, m0_30_port,
m0_29_port, m0_28_port, m0_27_port, m0_26_port, m0_25_port, m0_24_port,
m0_23_port, m0_22_port, m0_21_port, m0_20_port, m0_19_port, m0_18_port,
m0_17_port, m0_16_port, m0_15_port, m0_14_port, m0_13_port, m0_12_port,
m0_11_port, m0_10_port, m0_9_port, m0_8_port, m0_7_port, m0_6_port,
m0_5_port, m0_4_port, m0_3_port, m0_2_port, m0_1_port, m0_0_port,
m8_38_port, m8_37_port, m8_36_port, m8_35_port, m8_34_port, m8_33_port,
m8_32_port, m8_31_port, m8_30_port, m8_29_port, m8_28_port, m8_27_port,
m8_26_port, m8_25_port, m8_24_port, m8_23_port, m8_22_port, m8_21_port,
m8_20_port, m8_19_port, m8_18_port, m8_17_port, m8_16_port, m8_15_port,
m8_14_port, m8_13_port, m8_12_port, m8_11_port, m8_10_port, m8_9_port,
m8_8_port, m8_7_port, m8_6_port, m8_5_port, m8_4_port, m8_3_port,
m8_2_port, m8_1_port, m8_0_port, m16_38_port, m16_37_port, m16_36_port,
m16_35_port, m16_34_port, m16_33_port, m16_32_port, m16_31_port,
m16_30_port, m16_29_port, m16_28_port, m16_27_port, m16_26_port,
m16_25_port, m16_24_port, m16_23_port, m16_15_port, m16_14_port,
m16_13_port, m16_12_port, m16_11_port, m16_10_port, m16_9_port,
m16_8_port, m16_7_port, m16_6_port, m16_5_port, m16_4_port, m16_3_port,
m16_2_port, m16_1_port, m16_0_port, y_38_port, y_37_port, y_36_port,
y_35_port, y_34_port, y_33_port, y_32_port, y_31_port, y_30_port,
y_29_port, y_28_port, y_27_port, y_26_port, y_25_port, y_24_port,
y_23_port, y_22_port, y_21_port, y_20_port, y_19_port, y_18_port,
y_17_port, y_16_port, y_15_port, y_14_port, y_13_port, y_12_port,
y_11_port, y_10_port, y_9_port, y_8_port, y_7_port, y_6_port, y_5_port,
y_4_port, y_3_port, y_2_port, y_1_port, y_0_port, n5, n7, n8, n9, n2, n3,
n4, n6, n10, n11, n12, n14 : std_logic;
begin
IL : shift_firstLevel port map( A(31) => A(31), A(30) => A(30), A(29) =>
A(29), A(28) => A(28), A(27) => A(27), A(26) =>
A(26), A(25) => A(25), A(24) => A(24), A(23) =>
A(23), A(22) => A(22), A(21) => A(21), A(20) =>
A(20), A(19) => A(19), A(18) => A(18), A(17) =>
A(17), A(16) => A(16), A(15) => A(15), A(14) =>
A(14), A(13) => A(13), A(12) => A(12), A(11) =>
A(11), A(10) => A(10), A(9) => A(9), A(8) => A(8),
A(7) => A(7), A(6) => A(6), A(5) => A(5), A(4) =>
A(4), A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0)
=> A(0), sel(1) => LOGIC_ARITH, sel(0) => LEFT_RIGHT
, mask00(38) => m0_38_port, mask00(37) => m0_37_port
, mask00(36) => m0_36_port, mask00(35) => m0_35_port
, mask00(34) => m0_34_port, mask00(33) => m0_33_port
, mask00(32) => m0_32_port, mask00(31) => m0_31_port
, mask00(30) => m0_30_port, mask00(29) => m0_29_port
, mask00(28) => m0_28_port, mask00(27) => m0_27_port
, mask00(26) => m0_26_port, mask00(25) => m0_25_port
, mask00(24) => m0_24_port, mask00(23) => m0_23_port
, mask00(22) => m0_22_port, mask00(21) => m0_21_port
, mask00(20) => m0_20_port, mask00(19) => m0_19_port
, mask00(18) => m0_18_port, mask00(17) => m0_17_port
, mask00(16) => m0_16_port, mask00(15) => m0_15_port
, mask00(14) => m0_14_port, mask00(13) => m0_13_port
, mask00(12) => m0_12_port, mask00(11) => m0_11_port
, mask00(10) => m0_10_port, mask00(9) => m0_9_port,
mask00(8) => m0_8_port, mask00(7) => m0_7_port,
mask00(6) => m0_6_port, mask00(5) => m0_5_port,
mask00(4) => m0_4_port, mask00(3) => m0_3_port,
mask00(2) => m0_2_port, mask00(1) => m0_1_port,
mask00(0) => m0_0_port, mask08(38) => m8_38_port,
mask08(37) => m8_37_port, mask08(36) => m8_36_port,
mask08(35) => m8_35_port, mask08(34) => m8_34_port,
mask08(33) => m8_33_port, mask08(32) => m8_32_port,
mask08(31) => m8_31_port, mask08(30) => m8_30_port,
mask08(29) => m8_29_port, mask08(28) => m8_28_port,
mask08(27) => m8_27_port, mask08(26) => m8_26_port,
mask08(25) => m8_25_port, mask08(24) => m8_24_port,
mask08(23) => m8_23_port, mask08(22) => m8_22_port,
mask08(21) => m8_21_port, mask08(20) => m8_20_port,
mask08(19) => m8_19_port, mask08(18) => m8_18_port,
mask08(17) => m8_17_port, mask08(16) => m8_16_port,
mask08(15) => m8_15_port, mask08(14) => m8_14_port,
mask08(13) => m8_13_port, mask08(12) => m8_12_port,
mask08(11) => m8_11_port, mask08(10) => m8_10_port,
mask08(9) => m8_9_port, mask08(8) => m8_8_port,
mask08(7) => m8_7_port, mask08(6) => m8_6_port,
mask08(5) => m8_5_port, mask08(4) => m8_4_port,
mask08(3) => m8_3_port, mask08(2) => m8_2_port,
mask08(1) => m8_1_port, mask08(0) => m8_0_port,
mask16(38) => m16_38_port, mask16(37) => m16_37_port
, mask16(36) => m16_36_port, mask16(35) =>
m16_35_port, mask16(34) => m16_34_port, mask16(33)
=> m16_33_port, mask16(32) => m16_32_port,
mask16(31) => m16_31_port, mask16(30) => m16_30_port
, mask16(29) => m16_29_port, mask16(28) =>
m16_28_port, mask16(27) => m16_27_port, mask16(26)
=> m16_26_port, mask16(25) => m16_25_port,
mask16(24) => m16_24_port, mask16(23) => m16_23_port
, mask16(22) => n3, mask16(21) => n11, mask16(20) =>
n6, mask16(19) => n2, mask16(18) => n12, mask16(17)
=> n4, mask16(16) => n10, mask16(15) => m16_15_port,
mask16(14) => m16_14_port, mask16(13) => m16_13_port
, mask16(12) => m16_12_port, mask16(11) =>
m16_11_port, mask16(10) => m16_10_port, mask16(9) =>
m16_9_port, mask16(8) => m16_8_port, mask16(7) =>
m16_7_port, mask16(6) => m16_6_port, mask16(5) =>
m16_5_port, mask16(4) => m16_4_port, mask16(3) =>
m16_3_port, mask16(2) => m16_2_port, mask16(1) =>
m16_1_port, mask16(0) => m16_0_port);
IIL : shift_secondLevel port map( sel(1) => B(4), sel(0) => B(3), mask00(38)
=> m0_38_port, mask00(37) => m0_37_port, mask00(36)
=> m0_36_port, mask00(35) => m0_35_port, mask00(34)
=> m0_34_port, mask00(33) => m0_33_port, mask00(32)
=> m0_32_port, mask00(31) => m0_31_port, mask00(30)
=> m0_30_port, mask00(29) => m0_29_port, mask00(28)
=> m0_28_port, mask00(27) => m0_27_port, mask00(26)
=> m0_26_port, mask00(25) => m0_25_port, mask00(24)
=> m0_24_port, mask00(23) => m0_23_port, mask00(22)
=> m0_22_port, mask00(21) => m0_21_port, mask00(20)
=> m0_20_port, mask00(19) => m0_19_port, mask00(18)
=> m0_18_port, mask00(17) => m0_17_port, mask00(16)
=> m0_16_port, mask00(15) => m0_15_port, mask00(14)
=> m0_14_port, mask00(13) => m0_13_port, mask00(12)
=> m0_12_port, mask00(11) => m0_11_port, mask00(10)
=> m0_10_port, mask00(9) => m0_9_port, mask00(8) =>
m0_8_port, mask00(7) => m0_7_port, mask00(6) =>
m0_6_port, mask00(5) => m0_5_port, mask00(4) =>
m0_4_port, mask00(3) => m0_3_port, mask00(2) =>
m0_2_port, mask00(1) => m0_1_port, mask00(0) =>
m0_0_port, mask08(38) => m8_38_port, mask08(37) =>
m8_37_port, mask08(36) => m8_36_port, mask08(35) =>
m8_35_port, mask08(34) => m8_34_port, mask08(33) =>
m8_33_port, mask08(32) => m8_32_port, mask08(31) =>
m8_31_port, mask08(30) => m8_30_port, mask08(29) =>
m8_29_port, mask08(28) => m8_28_port, mask08(27) =>
m8_27_port, mask08(26) => m8_26_port, mask08(25) =>
m8_25_port, mask08(24) => m8_24_port, mask08(23) =>
m8_23_port, mask08(22) => m8_22_port, mask08(21) =>
m8_21_port, mask08(20) => m8_20_port, mask08(19) =>
m8_19_port, mask08(18) => m8_18_port, mask08(17) =>
m8_17_port, mask08(16) => m8_16_port, mask08(15) =>
m8_15_port, mask08(14) => m8_14_port, mask08(13) =>
m8_13_port, mask08(12) => m8_12_port, mask08(11) =>
m8_11_port, mask08(10) => m8_10_port, mask08(9) =>
m8_9_port, mask08(8) => m8_8_port, mask08(7) =>
m8_7_port, mask08(6) => m8_6_port, mask08(5) =>
m8_5_port, mask08(4) => m8_4_port, mask08(3) =>
m8_3_port, mask08(2) => m8_2_port, mask08(1) =>
m8_1_port, mask08(0) => m8_0_port, mask16(38) =>
m16_38_port, mask16(37) => m16_37_port, mask16(36)
=> m16_36_port, mask16(35) => m16_35_port,
mask16(34) => m16_34_port, mask16(33) => m16_33_port
, mask16(32) => m16_32_port, mask16(31) =>
m16_31_port, mask16(30) => m16_30_port, mask16(29)
=> m16_29_port, mask16(28) => m16_28_port,
mask16(27) => m16_27_port, mask16(26) => m16_26_port
, mask16(25) => m16_25_port, mask16(24) =>
m16_24_port, mask16(23) => m16_23_port, mask16(22)
=> n3, mask16(21) => n11, mask16(20) => n6,
mask16(19) => n2, mask16(18) => n12, mask16(17) =>
n4, mask16(16) => n10, mask16(15) => m16_15_port,
mask16(14) => m16_14_port, mask16(13) => m16_13_port
, mask16(12) => m16_12_port, mask16(11) =>
m16_11_port, mask16(10) => m16_10_port, mask16(9) =>
m16_9_port, mask16(8) => m16_8_port, mask16(7) =>
m16_7_port, mask16(6) => m16_6_port, mask16(5) =>
m16_5_port, mask16(4) => m16_4_port, mask16(3) =>
m16_3_port, mask16(2) => m16_2_port, mask16(1) =>
m16_1_port, mask16(0) => m16_0_port, Y(38) =>
y_38_port, Y(37) => y_37_port, Y(36) => y_36_port,
Y(35) => y_35_port, Y(34) => y_34_port, Y(33) =>
y_33_port, Y(32) => y_32_port, Y(31) => y_31_port,
Y(30) => y_30_port, Y(29) => y_29_port, Y(28) =>
y_28_port, Y(27) => y_27_port, Y(26) => y_26_port,
Y(25) => y_25_port, Y(24) => y_24_port, Y(23) =>
y_23_port, Y(22) => y_22_port, Y(21) => y_21_port,
Y(20) => y_20_port, Y(19) => y_19_port, Y(18) =>
y_18_port, Y(17) => y_17_port, Y(16) => y_16_port,
Y(15) => y_15_port, Y(14) => y_14_port, Y(13) =>
y_13_port, Y(12) => y_12_port, Y(11) => y_11_port,
Y(10) => y_10_port, Y(9) => y_9_port, Y(8) =>
y_8_port, Y(7) => y_7_port, Y(6) => y_6_port, Y(5)
=> y_5_port, Y(4) => y_4_port, Y(3) => y_3_port,
Y(2) => y_2_port, Y(1) => y_1_port, Y(0) => y_0_port
);
IIIL : shift_thirdLevel port map( sel(2) => s3_2_port, sel(1) => s3_1_port,
sel(0) => s3_0_port, A(38) => y_38_port, A(37) =>
y_37_port, A(36) => y_36_port, A(35) => y_35_port,
A(34) => y_34_port, A(33) => y_33_port, A(32) =>
y_32_port, A(31) => y_31_port, A(30) => y_30_port,
A(29) => y_29_port, A(28) => y_28_port, A(27) =>
y_27_port, A(26) => y_26_port, A(25) => y_25_port,
A(24) => y_24_port, A(23) => y_23_port, A(22) =>
y_22_port, A(21) => y_21_port, A(20) => y_20_port,
A(19) => y_19_port, A(18) => y_18_port, A(17) =>
y_17_port, A(16) => y_16_port, A(15) => y_15_port,
A(14) => y_14_port, A(13) => y_13_port, A(12) =>
y_12_port, A(11) => y_11_port, A(10) => y_10_port,
A(9) => y_9_port, A(8) => y_8_port, A(7) => y_7_port
, A(6) => y_6_port, A(5) => y_5_port, A(4) =>
y_4_port, A(3) => y_3_port, A(2) => y_2_port, A(1)
=> y_1_port, A(0) => y_0_port, Y(31) => OUTPUT(31),
Y(30) => OUTPUT(30), Y(29) => OUTPUT(29), Y(28) =>
OUTPUT(28), Y(27) => OUTPUT(27), Y(26) => OUTPUT(26)
, Y(25) => OUTPUT(25), Y(24) => OUTPUT(24), Y(23) =>
OUTPUT(23), Y(22) => OUTPUT(22), Y(21) => OUTPUT(21)
, Y(20) => OUTPUT(20), Y(19) => OUTPUT(19), Y(18) =>
OUTPUT(18), Y(17) => OUTPUT(17), Y(16) => OUTPUT(16)
, Y(15) => OUTPUT(15), Y(14) => OUTPUT(14), Y(13) =>
OUTPUT(13), Y(12) => OUTPUT(12), Y(11) => OUTPUT(11)
, Y(10) => OUTPUT(10), Y(9) => OUTPUT(9), Y(8) =>
OUTPUT(8), Y(7) => OUTPUT(7), Y(6) => OUTPUT(6),
Y(5) => OUTPUT(5), Y(4) => OUTPUT(4), Y(3) =>
OUTPUT(3), Y(2) => OUTPUT(2), Y(1) => OUTPUT(1),
Y(0) => OUTPUT(0));
U1 : AOI22_X1 port map( A1 => B(2), A2 => n5, B1 => n14, B2 => n7, ZN =>
s3_2_port);
U8 : OR2_X1 port map( A1 => LOGIC_ARITH, A2 => LEFT_RIGHT, ZN => n5);
U2 : INV_X1 port map( A => B(2), ZN => n7);
U3 : INV_X1 port map( A => B(1), ZN => n8);
U4 : INV_X1 port map( A => B(0), ZN => n9);
U5 : INV_X1 port map( A => LEFT_RIGHT, ZN => n14);
U6 : AOI22_X1 port map( A1 => B(0), A2 => n5, B1 => n14, B2 => n9, ZN =>
s3_0_port);
U7 : AOI22_X1 port map( A1 => B(1), A2 => n5, B1 => n14, B2 => n8, ZN =>
s3_1_port);
end SYN_struct;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity comparator_M32 is
port( C, V : in std_logic; SUM : in std_logic_vector (31 downto 0); sel :
in std_logic_vector (2 downto 0); sign : in std_logic; S : out
std_logic);
end comparator_M32;
architecture SYN_BEHAVIORAL of comparator_M32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI211_X1
port( C1, C2, A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component AND4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component AND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n3, n11, n12, n23, n22, n21, n20, n19, n18, n17, n16, n25, n26, n27,
n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41 :
std_logic;
begin
U21 : NOR2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n3);
U1 : INV_X1 port map( A => sel(2), ZN => n36);
U2 : OR2_X1 port map( A1 => sel(0), A2 => sel(2), ZN => n25);
U3 : NAND2_X1 port map( A1 => n38, A2 => n25, ZN => n34);
U4 : OR3_X1 port map( A1 => SUM(4), A2 => SUM(5), A3 => SUM(3), ZN => n29);
U5 : NOR4_X1 port map( A1 => SUM(9), A2 => SUM(8), A3 => SUM(7), A4 =>
SUM(6), ZN => n17);
U6 : NOR2_X1 port map( A1 => SUM(31), A2 => n29, ZN => n16);
U7 : NOR4_X1 port map( A1 => SUM(30), A2 => SUM(2), A3 => SUM(29), A4 =>
SUM(28), ZN => n19);
U8 : NOR4_X1 port map( A1 => SUM(27), A2 => SUM(26), A3 => SUM(25), A4 =>
SUM(24), ZN => n18);
U9 : AND2_X1 port map( A1 => n16, A2 => n17, ZN => n28);
U10 : NOR4_X1 port map( A1 => SUM(17), A2 => SUM(19), A3 => SUM(18), A4 =>
SUM(1), ZN => n20);
U11 : NOR4_X1 port map( A1 => SUM(12), A2 => SUM(11), A3 => SUM(10), A4 =>
SUM(0), ZN => n22);
U12 : NOR4_X1 port map( A1 => SUM(16), A2 => SUM(15), A3 => SUM(14), A4 =>
SUM(13), ZN => n23);
U13 : NOR4_X1 port map( A1 => SUM(23), A2 => SUM(22), A3 => SUM(20), A4 =>
SUM(21), ZN => n21);
U14 : AND3_X1 port map( A1 => n28, A2 => n18, A3 => n19, ZN => n27);
U15 : AND4_X1 port map( A1 => n21, A2 => n23, A3 => n22, A4 => n20, ZN =>
n26);
U16 : NAND2_X1 port map( A1 => n26, A2 => n27, ZN => n30);
U17 : XNOR2_X1 port map( A => n30, B => n40, ZN => n38);
U18 : OAI21_X1 port map( B1 => n31, B2 => sel(0), A => n3, ZN => n33);
U19 : CLKBUF_X1 port map( A => n30, Z => n31);
U20 : OAI22_X1 port map( A1 => n37, A2 => n3, B1 => n32, B2 => n33, ZN => S)
;
U22 : NAND2_X1 port map( A1 => n11, A2 => n41, ZN => n32);
U23 : NAND2_X1 port map( A1 => n32, A2 => n36, ZN => n35);
U24 : AND2_X1 port map( A1 => n34, A2 => n35, ZN => n37);
U25 : OR2_X1 port map( A1 => C, A2 => sign, ZN => n41);
U26 : INV_X1 port map( A => n39, ZN => n40);
U27 : OAI21_X1 port map( B1 => sel(0), B2 => sel(1), A => sel(2), ZN => n39)
;
U28 : OAI211_X1 port map( C1 => SUM(31), C2 => V, A => n12, B => sign, ZN =>
n11);
U29 : NAND2_X1 port map( A1 => SUM(31), A2 => V, ZN => n12);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity p4add_N32_logN5 is
port( A, B : in std_logic_vector (31 downto 0); Cin, sign : in std_logic;
S : out std_logic_vector (31 downto 0); Cout : out std_logic);
end p4add_N32_logN5;
architecture SYN_STRUCTURAL of p4add_N32_logN5 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component sum_gen_N32
port( A, B : in std_logic_vector (31 downto 0); Cin : in
std_logic_vector (8 downto 0); S : out std_logic_vector (31 downto
0));
end component;
component carry_tree_N32_logN5
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic;
Cout : out std_logic_vector (7 downto 0));
end component;
component xor_gen_N32
port( A : in std_logic_vector (31 downto 0); B : in std_logic; S : out
std_logic_vector (31 downto 0));
end component;
signal new_B_31_port, new_B_30_port, new_B_29_port, new_B_28_port,
new_B_27_port, new_B_26_port, new_B_25_port, new_B_24_port, new_B_23_port
, new_B_22_port, new_B_21_port, new_B_20_port, new_B_18_port,
new_B_16_port, new_B_14_port, new_B_13_port, new_B_12_port, new_B_11_port
, new_B_10_port, new_B_9_port, new_B_8_port, new_B_7_port, new_B_6_port,
new_B_5_port, new_B_4_port, new_B_3_port, new_B_2_port, new_B_1_port,
new_B_0_port, carry_pro_7_port, carry_pro_6_port, carry_pro_5_port,
carry_pro_4_port, carry_pro_3_port, carry_pro_2_port, carry_pro_1_port,
n1, n2, n3, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26 : std_logic;
begin
xor32 : xor_gen_N32 port map( A(31) => B(31), A(30) => B(30), A(29) => B(29)
, A(28) => B(28), A(27) => B(27), A(26) => B(26),
A(25) => B(25), A(24) => B(24), A(23) => B(23),
A(22) => B(22), A(21) => B(21), A(20) => B(20),
A(19) => B(19), A(18) => B(18), A(17) => B(17),
A(16) => B(16), A(15) => B(15), A(14) => B(14),
A(13) => B(13), A(12) => B(12), A(11) => B(11),
A(10) => B(10), A(9) => B(9), A(8) => B(8), A(7) =>
B(7), A(6) => B(6), A(5) => B(5), A(4) => B(4), A(3)
=> B(3), A(2) => B(2), A(1) => B(1), A(0) => B(0), B
=> sign, S(31) => new_B_31_port, S(30) =>
new_B_30_port, S(29) => new_B_29_port, S(28) =>
new_B_28_port, S(27) => new_B_27_port, S(26) =>
new_B_26_port, S(25) => new_B_25_port, S(24) =>
new_B_24_port, S(23) => new_B_23_port, S(22) =>
new_B_22_port, S(21) => new_B_21_port, S(20) =>
new_B_20_port, S(19) => n13, S(18) => new_B_18_port,
S(17) => n9, S(16) => new_B_16_port, S(15) => n3,
S(14) => new_B_14_port, S(13) => new_B_13_port,
S(12) => new_B_12_port, S(11) => new_B_11_port,
S(10) => new_B_10_port, S(9) => new_B_9_port, S(8)
=> new_B_8_port, S(7) => new_B_7_port, S(6) =>
new_B_6_port, S(5) => new_B_5_port, S(4) =>
new_B_4_port, S(3) => new_B_3_port, S(2) =>
new_B_2_port, S(1) => new_B_1_port, S(0) =>
new_B_0_port);
ct : carry_tree_N32_logN5 port map( A(31) => A(31), A(30) => A(30), A(29) =>
A(29), A(28) => A(28), A(27) => A(27), A(26) =>
A(26), A(25) => A(25), A(24) => A(24), A(23) =>
A(23), A(22) => A(22), A(21) => A(21), A(20) =>
A(20), A(19) => A(19), A(18) => A(18), A(17) =>
A(17), A(16) => A(16), A(15) => A(15), A(14) =>
A(14), A(13) => A(13), A(12) => A(12), A(11) =>
A(11), A(10) => A(10), A(9) => A(9), A(8) => A(8),
A(7) => A(7), A(6) => A(6), A(5) => A(5), A(4) =>
A(4), A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0)
=> A(0), B(31) => new_B_31_port, B(30) =>
new_B_30_port, B(29) => new_B_29_port, B(28) =>
new_B_28_port, B(27) => new_B_27_port, B(26) =>
new_B_26_port, B(25) => new_B_25_port, B(24) =>
new_B_24_port, B(23) => new_B_23_port, B(22) =>
new_B_22_port, B(21) => new_B_21_port, B(20) =>
new_B_20_port, B(19) => n13, B(18) => new_B_18_port,
B(17) => n9, B(16) => new_B_16_port, B(15) => n3,
B(14) => new_B_14_port, B(13) => new_B_13_port,
B(12) => new_B_12_port, B(11) => new_B_11_port,
B(10) => new_B_10_port, B(9) => new_B_9_port, B(8)
=> new_B_8_port, B(7) => new_B_7_port, B(6) =>
new_B_6_port, B(5) => new_B_5_port, B(4) =>
new_B_4_port, B(3) => new_B_3_port, B(2) =>
new_B_2_port, B(1) => new_B_1_port, B(0) =>
new_B_0_port, Cin => n20, Cout(7) => Cout, Cout(6)
=> carry_pro_7_port, Cout(5) => carry_pro_6_port,
Cout(4) => carry_pro_5_port, Cout(3) =>
carry_pro_4_port, Cout(2) => carry_pro_3_port,
Cout(1) => carry_pro_2_port, Cout(0) =>
carry_pro_1_port);
add : sum_gen_N32 port map( A(31) => A(31), A(30) => A(30), A(29) => A(29),
A(28) => A(28), A(27) => A(27), A(26) => A(26),
A(25) => A(25), A(24) => A(24), A(23) => A(23),
A(22) => A(22), A(21) => A(21), A(20) => A(20),
A(19) => A(19), A(18) => A(18), A(17) => A(17),
A(16) => A(16), A(15) => A(15), A(14) => A(14),
A(13) => A(13), A(12) => A(12), A(11) => A(11),
A(10) => A(10), A(9) => A(9), A(8) => A(8), A(7) =>
A(7), A(6) => A(6), A(5) => A(5), A(4) => A(4), A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(31) => new_B_31_port, B(30) => new_B_30_port,
B(29) => new_B_29_port, B(28) => new_B_28_port,
B(27) => new_B_27_port, B(26) => n1, B(25) => n14,
B(24) => new_B_24_port, B(23) => new_B_23_port,
B(22) => new_B_22_port, B(21) => new_B_21_port,
B(20) => new_B_20_port, B(19) => n13, B(18) => n8,
B(17) => n22, B(16) => new_B_16_port, B(15) => n3,
B(14) => n16, B(13) => n6, B(12) => new_B_12_port,
B(11) => n2, B(10) => n17, B(9) => n15, B(8) => n5,
B(7) => n25, B(6) => new_B_6_port, B(5) => n19, B(4)
=> n23, B(3) => n12, B(2) => n11, B(1) => n24, B(0)
=> n10, Cin(8) => n26, Cin(7) => carry_pro_7_port,
Cin(6) => carry_pro_6_port, Cin(5) =>
carry_pro_5_port, Cin(4) => carry_pro_4_port, Cin(3)
=> carry_pro_3_port, Cin(2) => carry_pro_2_port,
Cin(1) => carry_pro_1_port, Cin(0) => n20, S(31) =>
S(31), S(30) => S(30), S(29) => S(29), S(28) =>
S(28), S(27) => S(27), S(26) => S(26), S(25) =>
S(25), S(24) => S(24), S(23) => S(23), S(22) =>
S(22), S(21) => S(21), S(20) => S(20), S(19) =>
S(19), S(18) => S(18), S(17) => S(17), S(16) =>
S(16), S(15) => S(15), S(14) => S(14), S(13) =>
S(13), S(12) => S(12), S(11) => S(11), S(10) =>
S(10), S(9) => S(9), S(8) => S(8), S(7) => S(7),
S(6) => S(6), S(5) => S(5), S(4) => S(4), S(3) =>
S(3), S(2) => S(2), S(1) => S(1), S(0) => S(0));
U1 : BUF_X1 port map( A => new_B_26_port, Z => n1);
U2 : CLKBUF_X1 port map( A => new_B_11_port, Z => n2);
U3 : INV_X1 port map( A => new_B_1_port, ZN => n7);
U4 : BUF_X1 port map( A => new_B_14_port, Z => n16);
U5 : BUF_X1 port map( A => new_B_4_port, Z => n23);
U6 : BUF_X1 port map( A => sign, Z => n20);
U7 : BUF_X1 port map( A => new_B_8_port, Z => n5);
U8 : BUF_X1 port map( A => new_B_13_port, Z => n6);
U9 : CLKBUF_X1 port map( A => new_B_0_port, Z => n10);
U10 : CLKBUF_X1 port map( A => new_B_18_port, Z => n8);
U11 : BUF_X1 port map( A => new_B_2_port, Z => n11);
U12 : CLKBUF_X1 port map( A => new_B_3_port, Z => n12);
U13 : CLKBUF_X1 port map( A => new_B_25_port, Z => n14);
U14 : CLKBUF_X1 port map( A => new_B_7_port, Z => n25);
U15 : INV_X1 port map( A => n18, ZN => n19);
U16 : INV_X1 port map( A => new_B_5_port, ZN => n18);
U17 : CLKBUF_X1 port map( A => new_B_9_port, Z => n15);
U18 : CLKBUF_X1 port map( A => new_B_10_port, Z => n17);
U19 : INV_X1 port map( A => n21, ZN => n22);
U20 : INV_X1 port map( A => n9, ZN => n21);
U21 : INV_X1 port map( A => n7, ZN => n24);
n26 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity simple_booth_add_ext_N16 is
port( Clock, Reset, sign, enable : in std_logic; valid : out std_logic; A,
B : in std_logic_vector (15 downto 0); A_to_add, B_to_add : out
std_logic_vector (31 downto 0); sign_to_add : out std_logic;
final_out : out std_logic_vector (31 downto 0); ACC_from_add : in
std_logic_vector (31 downto 0));
end simple_booth_add_ext_N16;
architecture SYN_struct of simple_booth_add_ext_N16 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR2_X4
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component BUF_X8
port( A : in std_logic; Z : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component OAI211_X1
port( C1, C2, A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component DFFS_X1
port( D, CK, SN : in std_logic; Q, QN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component ff32_en_SIZE32
port( D : in std_logic_vector (31 downto 0); en, clk, rst : in std_logic
; Q : out std_logic_vector (31 downto 0));
end component;
component mux21_1
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end component;
component piso_r_2_N32
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (31 downto 0)
; SO : out std_logic_vector (31 downto 0));
end component;
component shift_N9_1
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component shift_N9_2
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component shift_N9_0
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component booth_encoder_1
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_2
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_3
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_4
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_5
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_6
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_7
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_8
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_0
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component DFFR_X1
port( D, CK, RN : in std_logic; Q, QN : out std_logic);
end component;
signal X_Logic0_port, valid_port, A_to_add_31_port, A_to_add_30_port,
A_to_add_29_port, A_to_add_28_port, A_to_add_27_port, A_to_add_26_port,
A_to_add_25_port, A_to_add_24_port, A_to_add_23_port, A_to_add_22_port,
A_to_add_21_port, A_to_add_20_port, A_to_add_19_port, A_to_add_18_port,
A_to_add_17_port, A_to_add_16_port, A_to_add_15_port, A_to_add_14_port,
A_to_add_13_port, A_to_add_12_port, A_to_add_11_port, A_to_add_10_port,
A_to_add_9_port, A_to_add_8_port, A_to_add_7_port, A_to_add_6_port,
A_to_add_5_port, A_to_add_4_port, A_to_add_3_port, A_to_add_2_port,
A_to_add_1_port, A_to_add_0_port, enc_N2_in_2_port, piso_0_in_8_port,
piso_0_in_7_port, piso_0_in_6_port, piso_0_in_5_port, piso_0_in_4_port,
piso_0_in_3_port, piso_0_in_2_port, piso_0_in_1_port, piso_0_in_0_port,
piso_1_in_8_port, piso_1_in_7_port, piso_1_in_6_port, piso_1_in_5_port,
piso_1_in_4_port, piso_1_in_3_port, piso_1_in_2_port, piso_1_in_1_port,
piso_1_in_0_port, piso_2_in_8_port, piso_2_in_7_port, piso_2_in_6_port,
piso_2_in_5_port, piso_2_in_4_port, piso_2_in_3_port, piso_2_in_2_port,
piso_2_in_1_port, piso_2_in_0_port, load, extend_vector_15_port,
A_to_mux_31_port, A_to_mux_30_port, A_to_mux_29_port, A_to_mux_28_port,
A_to_mux_27_port, A_to_mux_26_port, A_to_mux_25_port, A_to_mux_24_port,
A_to_mux_23_port, A_to_mux_22_port, A_to_mux_21_port, A_to_mux_20_port,
A_to_mux_19_port, A_to_mux_18_port, A_to_mux_17_port, A_to_mux_16_port,
A_to_mux_15_port, A_to_mux_14_port, A_to_mux_13_port, A_to_mux_12_port,
A_to_mux_11_port, A_to_mux_10_port, A_to_mux_9_port, A_to_mux_8_port,
A_to_mux_7_port, A_to_mux_6_port, A_to_mux_5_port, A_to_mux_4_port,
A_to_mux_3_port, A_to_mux_2_port, A_to_mux_1_port, A_to_mux_0_port,
input_mux_sel_2_port, input_mux_sel_0, next_accumulate_31_port,
next_accumulate_30_port, next_accumulate_29_port, next_accumulate_28_port
, next_accumulate_27_port, next_accumulate_26_port,
next_accumulate_25_port, next_accumulate_24_port, next_accumulate_23_port
, next_accumulate_22_port, next_accumulate_21_port,
next_accumulate_20_port, next_accumulate_19_port, next_accumulate_18_port
, next_accumulate_17_port, next_accumulate_16_port,
next_accumulate_15_port, next_accumulate_14_port, next_accumulate_13_port
, next_accumulate_12_port, next_accumulate_11_port,
next_accumulate_10_port, next_accumulate_9_port, next_accumulate_8_port,
next_accumulate_7_port, next_accumulate_6_port, next_accumulate_5_port,
next_accumulate_4_port, next_accumulate_3_port, next_accumulate_2_port,
next_accumulate_1_port, next_accumulate_0_port, reg_enable, count_4_port,
count_3_port, count_1_port, count_0_port, N21, N23, N24, n49, n50, n51,
n52, n54, n11, n12, n13, net549699, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n55, n56, n57, n58, n59, n60, n61, n63, n64, n65, n66
, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n79, n81, n82,
sub_213_n3, sub_213_n2, n14, n15, n16, n17, n18, n22, n23_port, net561327
: std_logic;
begin
valid <= valid_port;
A_to_add <= ( A_to_add_31_port, A_to_add_30_port, A_to_add_29_port,
A_to_add_28_port, A_to_add_27_port, A_to_add_26_port, A_to_add_25_port,
A_to_add_24_port, A_to_add_23_port, A_to_add_22_port, A_to_add_21_port,
A_to_add_20_port, A_to_add_19_port, A_to_add_18_port, A_to_add_17_port,
A_to_add_16_port, A_to_add_15_port, A_to_add_14_port, A_to_add_13_port,
A_to_add_12_port, A_to_add_11_port, A_to_add_10_port, A_to_add_9_port,
A_to_add_8_port, A_to_add_7_port, A_to_add_6_port, A_to_add_5_port,
A_to_add_4_port, A_to_add_3_port, A_to_add_2_port, A_to_add_1_port,
A_to_add_0_port );
X_Logic0_port <= '0';
count_reg_1_inst : DFFR_X1 port map( D => n51, CK => Clock, RN => n23_port,
Q => count_1_port, QN => n13);
count_reg_2_inst : DFFR_X1 port map( D => n50, CK => Clock, RN => n23_port,
Q => net561327, QN => n11);
count_reg_4_inst : DFFR_X1 port map( D => n49, CK => Clock, RN => n23_port,
Q => count_4_port, QN => n12);
U85 : MUX2_X1 port map( A => A_to_add_9_port, B => ACC_from_add(9), S =>
input_mux_sel_2_port, Z => final_out(9));
U86 : MUX2_X1 port map( A => A_to_add_8_port, B => ACC_from_add(8), S =>
input_mux_sel_2_port, Z => final_out(8));
U87 : MUX2_X1 port map( A => A_to_add_7_port, B => ACC_from_add(7), S =>
input_mux_sel_2_port, Z => final_out(7));
U88 : MUX2_X1 port map( A => A_to_add_6_port, B => ACC_from_add(6), S =>
input_mux_sel_2_port, Z => final_out(6));
U89 : MUX2_X1 port map( A => A_to_add_5_port, B => ACC_from_add(5), S =>
input_mux_sel_2_port, Z => final_out(5));
U90 : MUX2_X1 port map( A => A_to_add_4_port, B => ACC_from_add(4), S =>
input_mux_sel_2_port, Z => final_out(4));
U91 : MUX2_X1 port map( A => A_to_add_3_port, B => ACC_from_add(3), S =>
input_mux_sel_2_port, Z => final_out(3));
U92 : MUX2_X1 port map( A => A_to_add_31_port, B => ACC_from_add(31), S =>
input_mux_sel_2_port, Z => final_out(31));
U93 : MUX2_X1 port map( A => A_to_add_30_port, B => ACC_from_add(30), S =>
input_mux_sel_2_port, Z => final_out(30));
U94 : MUX2_X1 port map( A => A_to_add_2_port, B => ACC_from_add(2), S =>
input_mux_sel_2_port, Z => final_out(2));
U95 : MUX2_X1 port map( A => A_to_add_29_port, B => ACC_from_add(29), S =>
input_mux_sel_2_port, Z => final_out(29));
U96 : MUX2_X1 port map( A => A_to_add_28_port, B => ACC_from_add(28), S =>
input_mux_sel_2_port, Z => final_out(28));
U97 : MUX2_X1 port map( A => A_to_add_27_port, B => ACC_from_add(27), S =>
input_mux_sel_2_port, Z => final_out(27));
U98 : MUX2_X1 port map( A => A_to_add_26_port, B => ACC_from_add(26), S =>
input_mux_sel_2_port, Z => final_out(26));
U99 : MUX2_X1 port map( A => A_to_add_25_port, B => ACC_from_add(25), S =>
input_mux_sel_2_port, Z => final_out(25));
U100 : MUX2_X1 port map( A => A_to_add_24_port, B => ACC_from_add(24), S =>
input_mux_sel_2_port, Z => final_out(24));
U101 : MUX2_X1 port map( A => A_to_add_23_port, B => ACC_from_add(23), S =>
input_mux_sel_2_port, Z => final_out(23));
U102 : MUX2_X1 port map( A => A_to_add_22_port, B => ACC_from_add(22), S =>
input_mux_sel_2_port, Z => final_out(22));
U103 : MUX2_X1 port map( A => A_to_add_21_port, B => ACC_from_add(21), S =>
input_mux_sel_2_port, Z => final_out(21));
U104 : MUX2_X1 port map( A => A_to_add_20_port, B => ACC_from_add(20), S =>
input_mux_sel_2_port, Z => final_out(20));
U105 : MUX2_X1 port map( A => A_to_add_1_port, B => ACC_from_add(1), S =>
input_mux_sel_2_port, Z => final_out(1));
U106 : MUX2_X1 port map( A => A_to_add_19_port, B => ACC_from_add(19), S =>
input_mux_sel_2_port, Z => final_out(19));
U107 : MUX2_X1 port map( A => A_to_add_18_port, B => ACC_from_add(18), S =>
input_mux_sel_2_port, Z => final_out(18));
U108 : MUX2_X1 port map( A => A_to_add_17_port, B => ACC_from_add(17), S =>
input_mux_sel_2_port, Z => final_out(17));
U109 : MUX2_X1 port map( A => A_to_add_16_port, B => ACC_from_add(16), S =>
input_mux_sel_2_port, Z => final_out(16));
U110 : MUX2_X1 port map( A => A_to_add_15_port, B => ACC_from_add(15), S =>
input_mux_sel_2_port, Z => final_out(15));
U111 : MUX2_X1 port map( A => A_to_add_14_port, B => ACC_from_add(14), S =>
input_mux_sel_2_port, Z => final_out(14));
U112 : MUX2_X1 port map( A => A_to_add_13_port, B => ACC_from_add(13), S =>
input_mux_sel_2_port, Z => final_out(13));
U113 : MUX2_X1 port map( A => A_to_add_12_port, B => ACC_from_add(12), S =>
input_mux_sel_2_port, Z => final_out(12));
U114 : MUX2_X1 port map( A => A_to_add_11_port, B => ACC_from_add(11), S =>
input_mux_sel_2_port, Z => final_out(11));
U115 : MUX2_X1 port map( A => A_to_add_10_port, B => ACC_from_add(10), S =>
input_mux_sel_2_port, Z => final_out(10));
encod_0_0 : booth_encoder_0 port map( B_in(2) => B(1), B_in(1) => B(0),
B_in(0) => X_Logic0_port, A_out(2) =>
piso_2_in_0_port, A_out(1) => piso_1_in_0_port,
A_out(0) => piso_0_in_0_port);
encod_i_1 : booth_encoder_8 port map( B_in(2) => B(3), B_in(1) => B(2),
B_in(0) => B(1), A_out(2) => piso_2_in_1_port,
A_out(1) => piso_1_in_1_port, A_out(0) =>
piso_0_in_1_port);
encod_i_2 : booth_encoder_7 port map( B_in(2) => B(5), B_in(1) => B(4),
B_in(0) => B(3), A_out(2) => piso_2_in_2_port,
A_out(1) => piso_1_in_2_port, A_out(0) =>
piso_0_in_2_port);
encod_i_3 : booth_encoder_6 port map( B_in(2) => B(7), B_in(1) => B(6),
B_in(0) => B(5), A_out(2) => piso_2_in_3_port,
A_out(1) => piso_1_in_3_port, A_out(0) =>
piso_0_in_3_port);
encod_i_4 : booth_encoder_5 port map( B_in(2) => B(9), B_in(1) => B(8),
B_in(0) => B(7), A_out(2) => piso_2_in_4_port,
A_out(1) => piso_1_in_4_port, A_out(0) =>
piso_0_in_4_port);
encod_i_5 : booth_encoder_4 port map( B_in(2) => B(11), B_in(1) => B(10),
B_in(0) => B(9), A_out(2) => piso_2_in_5_port,
A_out(1) => piso_1_in_5_port, A_out(0) =>
piso_0_in_5_port);
encod_i_6 : booth_encoder_3 port map( B_in(2) => B(13), B_in(1) => B(12),
B_in(0) => B(11), A_out(2) => piso_2_in_6_port,
A_out(1) => piso_1_in_6_port, A_out(0) =>
piso_0_in_6_port);
encod_i_7 : booth_encoder_2 port map( B_in(2) => B(15), B_in(1) => B(14),
B_in(0) => B(13), A_out(2) => piso_2_in_7_port,
A_out(1) => piso_1_in_7_port, A_out(0) =>
piso_0_in_7_port);
encod_i_8 : booth_encoder_1 port map( B_in(2) => enc_N2_in_2_port, B_in(1)
=> enc_N2_in_2_port, B_in(0) => B(15), A_out(2) =>
piso_2_in_8_port, A_out(1) => piso_1_in_8_port,
A_out(0) => piso_0_in_8_port);
piso_0 : shift_N9_0 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_0_in_8_port, D(7) => piso_0_in_7_port, D(6) =>
piso_0_in_6_port, D(5) => piso_0_in_5_port, D(4) =>
piso_0_in_4_port, D(3) => piso_0_in_3_port, D(2) =>
piso_0_in_2_port, D(1) => piso_0_in_1_port, D(0) =>
piso_0_in_0_port, SO => input_mux_sel_0);
piso_1 : shift_N9_2 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_1_in_8_port, D(7) => piso_1_in_7_port, D(6) =>
piso_1_in_6_port, D(5) => piso_1_in_5_port, D(4) =>
piso_1_in_4_port, D(3) => piso_1_in_3_port, D(2) =>
piso_1_in_2_port, D(1) => piso_1_in_1_port, D(0) =>
piso_1_in_0_port, SO => sign_to_add);
piso_2 : shift_N9_1 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_2_in_8_port, D(7) => piso_2_in_7_port, D(6) =>
piso_2_in_6_port, D(5) => piso_2_in_5_port, D(4) =>
piso_2_in_4_port, D(3) => piso_2_in_3_port, D(2) =>
piso_2_in_2_port, D(1) => piso_2_in_1_port, D(0) =>
piso_2_in_0_port, SO => input_mux_sel_2_port);
A_reg : piso_r_2_N32 port map( Clock => Clock, ALOAD => n22, D(31) =>
extend_vector_15_port, D(30) =>
extend_vector_15_port, D(29) =>
extend_vector_15_port, D(28) =>
extend_vector_15_port, D(27) =>
extend_vector_15_port, D(26) =>
extend_vector_15_port, D(25) =>
extend_vector_15_port, D(24) =>
extend_vector_15_port, D(23) =>
extend_vector_15_port, D(22) =>
extend_vector_15_port, D(21) =>
extend_vector_15_port, D(20) =>
extend_vector_15_port, D(19) =>
extend_vector_15_port, D(18) =>
extend_vector_15_port, D(17) =>
extend_vector_15_port, D(16) =>
extend_vector_15_port, D(15) => A(15), D(14) =>
A(14), D(13) => A(13), D(12) => A(12), D(11) =>
A(11), D(10) => A(10), D(9) => A(9), D(8) => A(8),
D(7) => A(7), D(6) => A(6), D(5) => A(5), D(4) =>
A(4), D(3) => A(3), D(2) => A(2), D(1) => A(1), D(0)
=> A(0), SO(31) => A_to_mux_31_port, SO(30) =>
A_to_mux_30_port, SO(29) => A_to_mux_29_port, SO(28)
=> A_to_mux_28_port, SO(27) => A_to_mux_27_port,
SO(26) => A_to_mux_26_port, SO(25) =>
A_to_mux_25_port, SO(24) => A_to_mux_24_port, SO(23)
=> A_to_mux_23_port, SO(22) => A_to_mux_22_port,
SO(21) => A_to_mux_21_port, SO(20) =>
A_to_mux_20_port, SO(19) => A_to_mux_19_port, SO(18)
=> A_to_mux_18_port, SO(17) => A_to_mux_17_port,
SO(16) => A_to_mux_16_port, SO(15) =>
A_to_mux_15_port, SO(14) => A_to_mux_14_port, SO(13)
=> A_to_mux_13_port, SO(12) => A_to_mux_12_port,
SO(11) => A_to_mux_11_port, SO(10) =>
A_to_mux_10_port, SO(9) => A_to_mux_9_port, SO(8) =>
A_to_mux_8_port, SO(7) => A_to_mux_7_port, SO(6) =>
A_to_mux_6_port, SO(5) => A_to_mux_5_port, SO(4) =>
A_to_mux_4_port, SO(3) => A_to_mux_3_port, SO(2) =>
A_to_mux_2_port, SO(1) => A_to_mux_1_port, SO(0) =>
A_to_mux_0_port);
INPUTMUX : mux21_1 port map( IN0(31) => A_to_mux_31_port, IN0(30) =>
A_to_mux_30_port, IN0(29) => A_to_mux_29_port,
IN0(28) => A_to_mux_28_port, IN0(27) =>
A_to_mux_27_port, IN0(26) => A_to_mux_26_port,
IN0(25) => A_to_mux_25_port, IN0(24) =>
A_to_mux_24_port, IN0(23) => A_to_mux_23_port,
IN0(22) => A_to_mux_22_port, IN0(21) =>
A_to_mux_21_port, IN0(20) => A_to_mux_20_port,
IN0(19) => A_to_mux_19_port, IN0(18) =>
A_to_mux_18_port, IN0(17) => A_to_mux_17_port,
IN0(16) => A_to_mux_16_port, IN0(15) =>
A_to_mux_15_port, IN0(14) => A_to_mux_14_port,
IN0(13) => A_to_mux_13_port, IN0(12) =>
A_to_mux_12_port, IN0(11) => A_to_mux_11_port,
IN0(10) => A_to_mux_10_port, IN0(9) =>
A_to_mux_9_port, IN0(8) => A_to_mux_8_port, IN0(7)
=> A_to_mux_7_port, IN0(6) => A_to_mux_6_port,
IN0(5) => A_to_mux_5_port, IN0(4) => A_to_mux_4_port
, IN0(3) => A_to_mux_3_port, IN0(2) =>
A_to_mux_2_port, IN0(1) => A_to_mux_1_port, IN0(0)
=> A_to_mux_0_port, IN1(31) => A_to_mux_30_port,
IN1(30) => A_to_mux_29_port, IN1(29) =>
A_to_mux_28_port, IN1(28) => A_to_mux_27_port,
IN1(27) => A_to_mux_26_port, IN1(26) =>
A_to_mux_25_port, IN1(25) => A_to_mux_24_port,
IN1(24) => A_to_mux_23_port, IN1(23) =>
A_to_mux_22_port, IN1(22) => A_to_mux_21_port,
IN1(21) => A_to_mux_20_port, IN1(20) =>
A_to_mux_19_port, IN1(19) => A_to_mux_18_port,
IN1(18) => A_to_mux_17_port, IN1(17) =>
A_to_mux_16_port, IN1(16) => A_to_mux_15_port,
IN1(15) => A_to_mux_14_port, IN1(14) =>
A_to_mux_13_port, IN1(13) => A_to_mux_12_port,
IN1(12) => A_to_mux_11_port, IN1(11) =>
A_to_mux_10_port, IN1(10) => A_to_mux_9_port, IN1(9)
=> A_to_mux_8_port, IN1(8) => A_to_mux_7_port,
IN1(7) => A_to_mux_6_port, IN1(6) => A_to_mux_5_port
, IN1(5) => A_to_mux_4_port, IN1(4) =>
A_to_mux_3_port, IN1(3) => A_to_mux_2_port, IN1(2)
=> A_to_mux_1_port, IN1(1) => A_to_mux_0_port,
IN1(0) => X_Logic0_port, CTRL => input_mux_sel_0,
OUT1(31) => B_to_add(31), OUT1(30) => B_to_add(30),
OUT1(29) => B_to_add(29), OUT1(28) => B_to_add(28),
OUT1(27) => B_to_add(27), OUT1(26) => B_to_add(26),
OUT1(25) => B_to_add(25), OUT1(24) => B_to_add(24),
OUT1(23) => B_to_add(23), OUT1(22) => B_to_add(22),
OUT1(21) => B_to_add(21), OUT1(20) => B_to_add(20),
OUT1(19) => B_to_add(19), OUT1(18) => B_to_add(18),
OUT1(17) => B_to_add(17), OUT1(16) => B_to_add(16),
OUT1(15) => B_to_add(15), OUT1(14) => B_to_add(14),
OUT1(13) => B_to_add(13), OUT1(12) => B_to_add(12),
OUT1(11) => B_to_add(11), OUT1(10) => B_to_add(10),
OUT1(9) => B_to_add(9), OUT1(8) => B_to_add(8),
OUT1(7) => B_to_add(7), OUT1(6) => B_to_add(6),
OUT1(5) => B_to_add(5), OUT1(4) => B_to_add(4),
OUT1(3) => B_to_add(3), OUT1(2) => B_to_add(2),
OUT1(1) => B_to_add(1), OUT1(0) => B_to_add(0));
ACCUMULATOR : ff32_en_SIZE32 port map( D(31) => next_accumulate_31_port,
D(30) => next_accumulate_30_port, D(29) =>
next_accumulate_29_port, D(28) =>
next_accumulate_28_port, D(27) =>
next_accumulate_27_port, D(26) =>
next_accumulate_26_port, D(25) =>
next_accumulate_25_port, D(24) =>
next_accumulate_24_port, D(23) =>
next_accumulate_23_port, D(22) =>
next_accumulate_22_port, D(21) =>
next_accumulate_21_port, D(20) =>
next_accumulate_20_port, D(19) =>
next_accumulate_19_port, D(18) =>
next_accumulate_18_port, D(17) =>
next_accumulate_17_port, D(16) =>
next_accumulate_16_port, D(15) =>
next_accumulate_15_port, D(14) =>
next_accumulate_14_port, D(13) =>
next_accumulate_13_port, D(12) =>
next_accumulate_12_port, D(11) =>
next_accumulate_11_port, D(10) =>
next_accumulate_10_port, D(9) =>
next_accumulate_9_port, D(8) =>
next_accumulate_8_port, D(7) =>
next_accumulate_7_port, D(6) =>
next_accumulate_6_port, D(5) =>
next_accumulate_5_port, D(4) =>
next_accumulate_4_port, D(3) =>
next_accumulate_3_port, D(2) =>
next_accumulate_2_port, D(1) =>
next_accumulate_1_port, D(0) =>
next_accumulate_0_port, en => reg_enable, clk =>
Clock, rst => Reset, Q(31) => A_to_add_31_port,
Q(30) => A_to_add_30_port, Q(29) => A_to_add_29_port
, Q(28) => A_to_add_28_port, Q(27) =>
A_to_add_27_port, Q(26) => A_to_add_26_port, Q(25)
=> A_to_add_25_port, Q(24) => A_to_add_24_port,
Q(23) => A_to_add_23_port, Q(22) => A_to_add_22_port
, Q(21) => A_to_add_21_port, Q(20) =>
A_to_add_20_port, Q(19) => A_to_add_19_port, Q(18)
=> A_to_add_18_port, Q(17) => A_to_add_17_port,
Q(16) => A_to_add_16_port, Q(15) => A_to_add_15_port
, Q(14) => A_to_add_14_port, Q(13) =>
A_to_add_13_port, Q(12) => A_to_add_12_port, Q(11)
=> A_to_add_11_port, Q(10) => A_to_add_10_port, Q(9)
=> A_to_add_9_port, Q(8) => A_to_add_8_port, Q(7) =>
A_to_add_7_port, Q(6) => A_to_add_6_port, Q(5) =>
A_to_add_5_port, Q(4) => A_to_add_4_port, Q(3) =>
A_to_add_3_port, Q(2) => A_to_add_2_port, Q(1) =>
A_to_add_1_port, Q(0) => A_to_add_0_port);
U34 : NOR2_X1 port map( A1 => n22, A2 => n59, ZN => next_accumulate_24_port)
;
U36 : NOR2_X1 port map( A1 => n22, A2 => n60, ZN => next_accumulate_23_port)
;
U58 : NOR2_X1 port map( A1 => n22, A2 => n71, ZN => next_accumulate_13_port)
;
U54 : NOR2_X1 port map( A1 => n22, A2 => n69, ZN => next_accumulate_15_port)
;
U48 : NOR2_X1 port map( A1 => n22, A2 => n66, ZN => next_accumulate_18_port)
;
U46 : NOR2_X1 port map( A1 => n22, A2 => n65, ZN => next_accumulate_19_port)
;
U60 : NOR2_X1 port map( A1 => n22, A2 => n72, ZN => next_accumulate_12_port)
;
U62 : NOR2_X1 port map( A1 => n22, A2 => n73, ZN => next_accumulate_11_port)
;
U6 : NOR2_X1 port map( A1 => n22, A2 => n39, ZN => next_accumulate_8_port);
U4 : NOR2_X1 port map( A1 => n22, A2 => n38, ZN => next_accumulate_9_port);
U64 : NOR2_X1 port map( A1 => n22, A2 => n74, ZN => next_accumulate_10_port)
;
U8 : NOR2_X1 port map( A1 => n22, A2 => n40, ZN => next_accumulate_7_port);
U10 : NOR2_X1 port map( A1 => n22, A2 => n41, ZN => next_accumulate_6_port);
U16 : NOR2_X1 port map( A1 => n22, A2 => n44, ZN => next_accumulate_3_port);
U12 : NOR2_X1 port map( A1 => n22, A2 => n42, ZN => next_accumulate_5_port);
U14 : NOR2_X1 port map( A1 => n22, A2 => n43, ZN => next_accumulate_4_port);
U22 : NOR2_X1 port map( A1 => n22, A2 => n47, ZN => next_accumulate_2_port);
U44 : NOR2_X1 port map( A1 => n22, A2 => n64, ZN => next_accumulate_1_port);
U66 : NOR2_X1 port map( A1 => n22, A2 => n75, ZN => next_accumulate_0_port);
U78 : AND3_X1 port map( A1 => n81, A2 => N21, A3 => net549699, ZN =>
valid_port);
U72 : AOI21_X1 port map( B1 => enable, B2 => N24, A => valid_port, ZN => n77
);
U71 : OAI21_X1 port map( B1 => net549699, B2 => enable, A => n77, ZN => n52)
;
U76 : NAND2_X1 port map( A1 => enable, A2 => N23, ZN => n79);
U75 : OAI22_X1 port map( A1 => n79, A2 => valid_port, B1 => enable, B2 =>
n11, ZN => n50);
U69 : AOI21_X1 port map( B1 => enable, B2 => N21, A => valid_port, ZN => n76
);
U68 : OAI21_X1 port map( B1 => N21, B2 => enable, A => n76, ZN => n54);
U59 : INV_X1 port map( A => ACC_from_add(13), ZN => n71);
U55 : INV_X1 port map( A => ACC_from_add(15), ZN => n69);
U63 : INV_X1 port map( A => ACC_from_add(11), ZN => n73);
U7 : INV_X1 port map( A => ACC_from_add(8), ZN => n39);
U5 : INV_X1 port map( A => ACC_from_add(9), ZN => n38);
U65 : INV_X1 port map( A => ACC_from_add(10), ZN => n74);
U9 : INV_X1 port map( A => ACC_from_add(7), ZN => n40);
U11 : INV_X1 port map( A => ACC_from_add(6), ZN => n41);
U17 : INV_X1 port map( A => ACC_from_add(3), ZN => n44);
U13 : INV_X1 port map( A => ACC_from_add(5), ZN => n42);
U15 : INV_X1 port map( A => ACC_from_add(4), ZN => n43);
U23 : INV_X1 port map( A => ACC_from_add(2), ZN => n47);
U45 : INV_X1 port map( A => ACC_from_add(1), ZN => n64);
U67 : INV_X1 port map( A => ACC_from_add(0), ZN => n75);
U79 : INV_X1 port map( A => n82, ZN => n81);
sub_213_U4 : OAI21_X1 port map( B1 => sub_213_n3, B2 => n11, A => sub_213_n2
, ZN => N23);
sub_213_U3 : XNOR2_X1 port map( A => count_3_port, B => sub_213_n2, ZN =>
N24);
sub_213_U5 : NAND2_X1 port map( A1 => sub_213_n3, A2 => n11, ZN =>
sub_213_n2);
sub_213_U9 : NOR2_X1 port map( A1 => count_1_port, A2 => count_0_port, ZN =>
sub_213_n3);
U84 : NAND3_X1 port map( A1 => n13, A2 => n11, A3 => n12, ZN => n82);
count_reg_0_inst : DFFS_X1 port map( D => n54, CK => Clock, SN => n23_port,
Q => count_0_port, QN => N21);
count_reg_3_inst : DFFS_X1 port map( D => n52, CK => Clock, SN => n23_port,
Q => count_3_port, QN => net549699);
U3 : NOR2_X1 port map( A1 => sub_213_n2, A2 => count_3_port, ZN => n14);
U18 : NAND2_X1 port map( A1 => n14, A2 => count_4_port, ZN => n15);
U19 : OAI211_X1 port map( C1 => n14, C2 => count_4_port, A => n15, B =>
enable, ZN => n16);
U20 : OAI22_X1 port map( A1 => enable, A2 => n12, B1 => valid_port, B2 =>
n16, ZN => n49);
U21 : MUX2_X1 port map( A => A_to_add_0_port, B => ACC_from_add(0), S =>
input_mux_sel_2_port, Z => final_out(0));
U24 : INV_X1 port map( A => ACC_from_add(21), ZN => n17);
U25 : NOR2_X1 port map( A1 => n22, A2 => n17, ZN => next_accumulate_21_port)
;
U26 : OAI221_X1 port map( B1 => sub_213_n3, B2 => count_1_port, C1 =>
sub_213_n3, C2 => count_0_port, A => enable, ZN =>
n18);
U27 : OAI22_X1 port map( A1 => enable, A2 => n13, B1 => valid_port, B2 =>
n18, ZN => n51);
U28 : BUF_X8 port map( A => load, Z => n22);
U29 : NOR3_X1 port map( A1 => N21, A2 => net549699, A3 => n82, ZN => load);
U30 : INV_X1 port map( A => Reset, ZN => n23_port);
U31 : AND2_X1 port map( A1 => sign, A2 => A(15), ZN => extend_vector_15_port
);
U32 : AND2_X1 port map( A1 => sign, A2 => B(15), ZN => enc_N2_in_2_port);
U33 : INV_X1 port map( A => ACC_from_add(12), ZN => n72);
U35 : NOR2_X1 port map( A1 => n22, A2 => n46, ZN => next_accumulate_30_port)
;
U37 : INV_X1 port map( A => ACC_from_add(30), ZN => n46);
U38 : INV_X1 port map( A => ACC_from_add(14), ZN => n70);
U39 : INV_X1 port map( A => ACC_from_add(19), ZN => n65);
U40 : INV_X1 port map( A => ACC_from_add(16), ZN => n68);
U41 : INV_X1 port map( A => ACC_from_add(25), ZN => n58);
U42 : INV_X1 port map( A => ACC_from_add(18), ZN => n66);
U43 : INV_X1 port map( A => ACC_from_add(17), ZN => n67);
U47 : INV_X1 port map( A => ACC_from_add(26), ZN => n57);
U49 : INV_X1 port map( A => ACC_from_add(23), ZN => n60);
U50 : INV_X1 port map( A => ACC_from_add(27), ZN => n56);
U51 : INV_X1 port map( A => ACC_from_add(24), ZN => n59);
U52 : INV_X1 port map( A => ACC_from_add(31), ZN => n45);
U53 : INV_X1 port map( A => ACC_from_add(20), ZN => n63);
U56 : INV_X1 port map( A => ACC_from_add(29), ZN => n48);
U57 : INV_X1 port map( A => ACC_from_add(22), ZN => n61);
U61 : INV_X1 port map( A => ACC_from_add(28), ZN => n55);
U70 : OR2_X4 port map( A1 => n22, A2 => input_mux_sel_2_port, ZN =>
reg_enable);
U73 : NOR2_X1 port map( A1 => n22, A2 => n70, ZN => next_accumulate_14_port)
;
U74 : NOR2_X1 port map( A1 => n22, A2 => n68, ZN => next_accumulate_16_port)
;
U77 : NOR2_X1 port map( A1 => n22, A2 => n58, ZN => next_accumulate_25_port)
;
U80 : NOR2_X1 port map( A1 => n22, A2 => n67, ZN => next_accumulate_17_port)
;
U81 : NOR2_X1 port map( A1 => n22, A2 => n57, ZN => next_accumulate_26_port)
;
U82 : NOR2_X1 port map( A1 => n22, A2 => n56, ZN => next_accumulate_27_port)
;
U83 : NOR2_X1 port map( A1 => n22, A2 => n61, ZN => next_accumulate_22_port)
;
U116 : NOR2_X1 port map( A1 => n22, A2 => n48, ZN => next_accumulate_29_port
);
U117 : NOR2_X1 port map( A1 => n22, A2 => n55, ZN => next_accumulate_28_port
);
U118 : NOR2_X1 port map( A1 => n22, A2 => n63, ZN => next_accumulate_20_port
);
U119 : NOR2_X1 port map( A1 => n22, A2 => n45, ZN => next_accumulate_31_port
);
end SYN_struct;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE32_0 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end mux41_MUX_SIZE32_0;
architecture SYN_bhe of mux41_MUX_SIZE32_0 is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62
, n63, n64, n65, n66, n67, n69, n68, n70, n71, n72, n73, n74, n75, n76,
n77 : std_logic;
begin
U42 : AOI222_X1 port map( A1 => n77, A2 => IN1(1), B1 => n76, B2 => IN0(1),
C1 => n73, C2 => IN2(1), ZN => n57);
U46 : AOI222_X1 port map( A1 => n77, A2 => IN1(18), B1 => n76, B2 => IN0(18)
, C1 => n73, C2 => IN2(18), ZN => n59);
U48 : AOI222_X1 port map( A1 => n77, A2 => IN1(17), B1 => n76, B2 => IN0(17)
, C1 => n73, C2 => IN2(17), ZN => n60);
U50 : AOI222_X1 port map( A1 => n77, A2 => IN1(16), B1 => n76, B2 => IN0(16)
, C1 => n73, C2 => IN2(16), ZN => n61);
U44 : AOI222_X1 port map( A1 => n77, A2 => IN1(19), B1 => n76, B2 => IN0(19)
, C1 => n73, C2 => IN2(19), ZN => n58);
U20 : AOI222_X1 port map( A1 => n68, A2 => IN1(2), B1 => n70, B2 => IN0(2),
C1 => n74, C2 => IN2(2), ZN => n46);
U14 : AOI222_X1 port map( A1 => n68, A2 => IN1(3), B1 => n70, B2 => IN0(3),
C1 => n75, C2 => IN2(3), ZN => n43);
U6 : AOI222_X1 port map( A1 => n68, A2 => IN1(7), B1 => n70, B2 => IN0(7),
C1 => n75, C2 => IN2(7), ZN => n39);
U10 : AOI222_X1 port map( A1 => n68, A2 => IN1(5), B1 => n70, B2 => IN0(5),
C1 => n75, C2 => IN2(5), ZN => n41);
U12 : AOI222_X1 port map( A1 => n68, A2 => IN1(4), B1 => n70, B2 => IN0(4),
C1 => n75, C2 => IN2(4), ZN => n42);
U58 : AOI222_X1 port map( A1 => n77, A2 => IN1(12), B1 => n76, B2 => IN0(12)
, C1 => n73, C2 => IN2(12), ZN => n65);
U56 : AOI222_X1 port map( A1 => n77, A2 => IN1(13), B1 => n76, B2 => IN0(13)
, C1 => n73, C2 => IN2(13), ZN => n64);
U52 : AOI222_X1 port map( A1 => n77, A2 => IN1(15), B1 => n76, B2 => IN0(15)
, C1 => n73, C2 => IN2(15), ZN => n62);
U54 : AOI222_X1 port map( A1 => n77, A2 => IN1(14), B1 => n76, B2 => IN0(14)
, C1 => n73, C2 => IN2(14), ZN => n63);
U62 : AOI222_X1 port map( A1 => n77, A2 => IN1(10), B1 => n76, B2 => IN0(10)
, C1 => n73, C2 => IN2(10), ZN => n67);
U60 : AOI222_X1 port map( A1 => n77, A2 => IN1(11), B1 => n76, B2 => IN0(11)
, C1 => n73, C2 => IN2(11), ZN => n66);
U4 : AOI222_X1 port map( A1 => n68, A2 => IN1(8), B1 => n70, B2 => IN0(8),
C1 => n75, C2 => IN2(8), ZN => n38);
U2 : AOI222_X1 port map( A1 => n68, A2 => IN1(9), B1 => n70, B2 => IN0(9),
C1 => n75, C2 => IN2(9), ZN => n34);
U36 : AOI222_X1 port map( A1 => n68, A2 => IN1(22), B1 => n70, B2 => IN0(22)
, C1 => n74, C2 => IN2(22), ZN => n54);
U38 : AOI222_X1 port map( A1 => n68, A2 => IN1(21), B1 => n70, B2 => IN0(21)
, C1 => n74, C2 => IN2(21), ZN => n55);
U40 : AOI222_X1 port map( A1 => n68, A2 => IN1(20), B1 => n70, B2 => IN0(20)
, C1 => n74, C2 => IN2(20), ZN => n56);
U34 : AOI222_X1 port map( A1 => n68, A2 => IN1(23), B1 => n70, B2 => IN0(23)
, C1 => n74, C2 => IN2(23), ZN => n53);
U18 : AOI222_X1 port map( A1 => n68, A2 => IN1(30), B1 => n70, B2 => IN0(30)
, C1 => n74, C2 => IN2(30), ZN => n45);
U22 : AOI222_X1 port map( A1 => n68, A2 => IN1(29), B1 => n70, B2 => IN0(29)
, C1 => n74, C2 => IN2(29), ZN => n47);
U24 : AOI222_X1 port map( A1 => n68, A2 => IN1(28), B1 => n70, B2 => IN0(28)
, C1 => n74, C2 => IN2(28), ZN => n48);
U16 : AOI222_X1 port map( A1 => n68, A2 => IN1(31), B1 => n70, B2 => IN0(31)
, C1 => n75, C2 => IN2(31), ZN => n44);
U26 : AOI222_X1 port map( A1 => n68, A2 => IN1(27), B1 => n70, B2 => IN0(27)
, C1 => n74, C2 => IN2(27), ZN => n49);
U28 : AOI222_X1 port map( A1 => n68, A2 => IN1(26), B1 => n70, B2 => IN0(26)
, C1 => n74, C2 => IN2(26), ZN => n50);
U30 : AOI222_X1 port map( A1 => n68, A2 => IN1(25), B1 => n70, B2 => IN0(25)
, C1 => n74, C2 => IN2(25), ZN => n51);
U32 : AOI222_X1 port map( A1 => n68, A2 => IN1(24), B1 => n70, B2 => IN0(24)
, C1 => n74, C2 => IN2(24), ZN => n52);
U66 : NOR2_X1 port map( A1 => CTRL(1), A2 => CTRL(0), ZN => n36);
U68 : INV_X1 port map( A => CTRL(1), ZN => n69);
U67 : AND2_X1 port map( A1 => n69, A2 => CTRL(0), ZN => n35);
U41 : INV_X1 port map( A => n57, ZN => OUT1(1));
U45 : INV_X1 port map( A => n59, ZN => OUT1(18));
U47 : INV_X1 port map( A => n60, ZN => OUT1(17));
U49 : INV_X1 port map( A => n61, ZN => OUT1(16));
U43 : INV_X1 port map( A => n58, ZN => OUT1(19));
U19 : INV_X1 port map( A => n46, ZN => OUT1(2));
U13 : INV_X1 port map( A => n43, ZN => OUT1(3));
U7 : INV_X1 port map( A => n40, ZN => OUT1(6));
U5 : INV_X1 port map( A => n39, ZN => OUT1(7));
U9 : INV_X1 port map( A => n41, ZN => OUT1(5));
U11 : INV_X1 port map( A => n42, ZN => OUT1(4));
U57 : INV_X1 port map( A => n65, ZN => OUT1(12));
U55 : INV_X1 port map( A => n64, ZN => OUT1(13));
U51 : INV_X1 port map( A => n62, ZN => OUT1(15));
U53 : INV_X1 port map( A => n63, ZN => OUT1(14));
U61 : INV_X1 port map( A => n67, ZN => OUT1(10));
U59 : INV_X1 port map( A => n66, ZN => OUT1(11));
U3 : INV_X1 port map( A => n38, ZN => OUT1(8));
U1 : INV_X1 port map( A => n34, ZN => OUT1(9));
U35 : INV_X1 port map( A => n54, ZN => OUT1(22));
U37 : INV_X1 port map( A => n55, ZN => OUT1(21));
U39 : INV_X1 port map( A => n56, ZN => OUT1(20));
U33 : INV_X1 port map( A => n53, ZN => OUT1(23));
U17 : INV_X1 port map( A => n45, ZN => OUT1(30));
U21 : INV_X1 port map( A => n47, ZN => OUT1(29));
U23 : INV_X1 port map( A => n48, ZN => OUT1(28));
U15 : INV_X1 port map( A => n44, ZN => OUT1(31));
U25 : INV_X1 port map( A => n49, ZN => OUT1(27));
U27 : INV_X1 port map( A => n50, ZN => OUT1(26));
U29 : INV_X1 port map( A => n51, ZN => OUT1(25));
U31 : INV_X1 port map( A => n52, ZN => OUT1(24));
U8 : BUF_X2 port map( A => n35, Z => n68);
U63 : BUF_X1 port map( A => n36, Z => n76);
U64 : BUF_X2 port map( A => n36, Z => n70);
U65 : BUF_X2 port map( A => n35, Z => n77);
U69 : AOI222_X1 port map( A1 => n68, A2 => IN1(6), B1 => n70, B2 => IN0(6),
C1 => n75, C2 => IN2(6), ZN => n40);
U70 : BUF_X2 port map( A => n37, Z => n75);
U71 : BUF_X2 port map( A => n37, Z => n74);
U72 : BUF_X2 port map( A => n37, Z => n73);
U73 : NOR2_X1 port map( A1 => CTRL(0), A2 => n69, ZN => n37);
U74 : NAND2_X1 port map( A1 => n73, A2 => IN2(0), ZN => n71);
U75 : NAND2_X1 port map( A1 => n71, A2 => n72, ZN => OUT1(0));
U76 : AOI22_X1 port map( A1 => n77, A2 => IN1(0), B1 => n76, B2 => IN0(0),
ZN => n72);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE5 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (4 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (4 downto
0));
end mux41_MUX_SIZE5;
architecture SYN_bhe of mux41_MUX_SIZE5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3, n4, n5, n6, n8, n9, n10, n11, n12, n13, n14, n15, n16 :
std_logic;
begin
U1 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => OUT1(4));
U4 : NAND2_X1 port map( A1 => n8, A2 => n9, ZN => OUT1(3));
U7 : NAND2_X1 port map( A1 => n10, A2 => n11, ZN => OUT1(2));
U10 : NAND2_X1 port map( A1 => n12, A2 => n13, ZN => OUT1(1));
U17 : AOI22_X1 port map( A1 => n5, A2 => IN2(0), B1 => n6, B2 => IN1(0), ZN
=> n14);
U13 : NAND2_X1 port map( A1 => n14, A2 => n15, ZN => OUT1(0));
U19 : NOR2_X1 port map( A1 => CTRL(0), A2 => n16, ZN => n5);
U20 : INV_X1 port map( A => CTRL(1), ZN => n16);
U18 : AND2_X1 port map( A1 => n16, A2 => CTRL(0), ZN => n6);
U16 : AND2_X1 port map( A1 => CTRL(0), A2 => CTRL(1), ZN => n4);
U2 : INV_X1 port map( A => n4, ZN => n15);
U3 : AOI21_X1 port map( B1 => n5, B2 => IN2(1), A => n4, ZN => n13);
U5 : NAND2_X1 port map( A1 => n6, A2 => IN1(1), ZN => n12);
U6 : AOI21_X1 port map( B1 => n5, B2 => IN2(2), A => n4, ZN => n11);
U8 : NAND2_X1 port map( A1 => n6, A2 => IN1(2), ZN => n10);
U9 : AOI21_X1 port map( B1 => n5, B2 => IN2(3), A => n4, ZN => n9);
U11 : NAND2_X1 port map( A1 => n6, A2 => IN1(3), ZN => n8);
U12 : AOI21_X1 port map( B1 => n5, B2 => IN2(4), A => n4, ZN => n3);
U14 : NAND2_X1 port map( A1 => n6, A2 => IN1(4), ZN => n2);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity real_alu_DATA_SIZE32 is
port( IN1, IN2 : in std_logic_vector (31 downto 0); ALUW_i : in
std_logic_vector (12 downto 0); DOUT : out std_logic_vector (31
downto 0); stall_o : out std_logic; Clock, Reset : in std_logic);
end real_alu_DATA_SIZE32;
architecture SYN_Bhe of real_alu_DATA_SIZE32 is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component NAND2_X4
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component logic_unit_SIZE32
port( IN1, IN2 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component shifter
port( A : in std_logic_vector (31 downto 0); B : in std_logic_vector (4
downto 0); LOGIC_ARITH, LEFT_RIGHT : in std_logic; OUTPUT : out
std_logic_vector (31 downto 0));
end component;
component comparator_M32
port( C, V : in std_logic; SUM : in std_logic_vector (31 downto 0); sel
: in std_logic_vector (2 downto 0); sign : in std_logic; S : out
std_logic);
end component;
component p4add_N32_logN5
port( A, B : in std_logic_vector (31 downto 0); Cin, sign : in std_logic
; S : out std_logic_vector (31 downto 0); Cout : out std_logic);
end component;
component simple_booth_add_ext_N16
port( Clock, Reset, sign, enable : in std_logic; valid : out std_logic;
A, B : in std_logic_vector (15 downto 0); A_to_add, B_to_add : out
std_logic_vector (31 downto 0); sign_to_add : out std_logic;
final_out : out std_logic_vector (31 downto 0); ACC_from_add : in
std_logic_vector (31 downto 0));
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal X_Logic0_port, mux_A_31_port, mux_A_30_port, mux_A_29_port,
mux_A_28_port, mux_A_27_port, mux_A_26_port, mux_A_25_port, mux_A_24_port
, mux_A_23_port, mux_A_22_port, mux_A_21_port, mux_A_20_port,
mux_A_19_port, mux_A_18_port, mux_A_17_port, mux_A_16_port, mux_A_15_port
, mux_A_14_port, mux_A_13_port, mux_A_12_port, mux_A_11_port,
mux_A_10_port, mux_A_9_port, mux_A_8_port, mux_A_7_port, mux_A_6_port,
mux_A_5_port, mux_A_4_port, mux_A_3_port, mux_A_2_port, mux_A_1_port,
mux_A_0_port, A_booth_to_add_31_port, A_booth_to_add_30_port,
A_booth_to_add_29_port, A_booth_to_add_28_port, A_booth_to_add_27_port,
A_booth_to_add_26_port, A_booth_to_add_25_port, A_booth_to_add_24_port,
A_booth_to_add_23_port, A_booth_to_add_22_port, A_booth_to_add_21_port,
A_booth_to_add_20_port, A_booth_to_add_19_port, A_booth_to_add_18_port,
A_booth_to_add_17_port, A_booth_to_add_16_port, A_booth_to_add_15_port,
A_booth_to_add_14_port, A_booth_to_add_13_port, A_booth_to_add_12_port,
A_booth_to_add_11_port, A_booth_to_add_10_port, A_booth_to_add_9_port,
A_booth_to_add_8_port, A_booth_to_add_7_port, A_booth_to_add_6_port,
A_booth_to_add_5_port, A_booth_to_add_4_port, A_booth_to_add_3_port,
A_booth_to_add_2_port, A_booth_to_add_1_port, A_booth_to_add_0_port,
mux_B_31_port, mux_B_30_port, mux_B_29_port, mux_B_28_port, mux_B_27_port
, mux_B_26_port, mux_B_25_port, mux_B_24_port, mux_B_23_port,
mux_B_22_port, mux_B_21_port, mux_B_20_port, mux_B_19_port, mux_B_18_port
, mux_B_17_port, mux_B_16_port, mux_B_15_port, mux_B_14_port,
mux_B_13_port, mux_B_12_port, mux_B_11_port, mux_B_10_port, mux_B_9_port,
mux_B_8_port, mux_B_7_port, mux_B_6_port, mux_B_5_port, mux_B_4_port,
mux_B_3_port, mux_B_2_port, mux_B_1_port, mux_B_0_port,
B_booth_to_add_31_port, B_booth_to_add_30_port, B_booth_to_add_29_port,
B_booth_to_add_28_port, B_booth_to_add_27_port, B_booth_to_add_26_port,
B_booth_to_add_25_port, B_booth_to_add_24_port, B_booth_to_add_23_port,
B_booth_to_add_22_port, B_booth_to_add_21_port, B_booth_to_add_20_port,
B_booth_to_add_19_port, B_booth_to_add_18_port, B_booth_to_add_17_port,
B_booth_to_add_16_port, B_booth_to_add_15_port, B_booth_to_add_14_port,
B_booth_to_add_13_port, B_booth_to_add_12_port, B_booth_to_add_11_port,
B_booth_to_add_10_port, B_booth_to_add_9_port, B_booth_to_add_8_port,
B_booth_to_add_7_port, B_booth_to_add_6_port, B_booth_to_add_5_port,
B_booth_to_add_4_port, B_booth_to_add_3_port, B_booth_to_add_2_port,
B_booth_to_add_1_port, B_booth_to_add_0_port, mux_sign, sign_booth_to_add
, valid_from_booth, mult_out_31_port, mult_out_30_port, mult_out_29_port,
mult_out_28_port, mult_out_27_port, mult_out_26_port, mult_out_25_port,
mult_out_24_port, mult_out_23_port, mult_out_22_port, mult_out_21_port,
mult_out_20_port, mult_out_19_port, mult_out_18_port, mult_out_17_port,
mult_out_16_port, mult_out_15_port, mult_out_14_port, mult_out_13_port,
mult_out_12_port, mult_out_11_port, mult_out_10_port, mult_out_9_port,
mult_out_8_port, mult_out_7_port, mult_out_6_port, mult_out_5_port,
mult_out_4_port, mult_out_3_port, mult_out_2_port, mult_out_1_port,
mult_out_0_port, sum_out_31_port, sum_out_30_port, sum_out_29_port,
sum_out_28_port, sum_out_27_port, sum_out_26_port, sum_out_25_port,
sum_out_24_port, sum_out_23_port, sum_out_22_port, sum_out_21_port,
sum_out_20_port, sum_out_18_port, sum_out_17_port, sum_out_16_port,
sum_out_15_port, sum_out_14_port, sum_out_13_port, sum_out_12_port,
sum_out_11_port, sum_out_10_port, sum_out_9_port, sum_out_8_port,
sum_out_7_port, sum_out_6_port, sum_out_5_port, sum_out_4_port,
sum_out_3_port, sum_out_2_port, sum_out_1_port, sum_out_0_port,
carry_from_adder, overflow, comp_out, shift_out_31_port,
shift_out_30_port, shift_out_29_port, shift_out_28_port,
shift_out_27_port, shift_out_26_port, shift_out_25_port,
shift_out_24_port, shift_out_23_port, shift_out_22_port,
shift_out_21_port, shift_out_20_port, shift_out_19_port,
shift_out_18_port, shift_out_17_port, shift_out_16_port,
shift_out_15_port, shift_out_14_port, shift_out_13_port,
shift_out_12_port, shift_out_11_port, shift_out_10_port, shift_out_9_port
, shift_out_8_port, shift_out_7_port, shift_out_6_port, shift_out_5_port,
shift_out_4_port, shift_out_3_port, shift_out_2_port, shift_out_1_port,
shift_out_0_port, lu_out_31_port, lu_out_30_port, lu_out_29_port,
lu_out_28_port, lu_out_27_port, lu_out_26_port, lu_out_25_port,
lu_out_24_port, lu_out_23_port, lu_out_22_port, lu_out_21_port,
lu_out_20_port, lu_out_19_port, lu_out_18_port, lu_out_17_port,
lu_out_16_port, lu_out_15_port, lu_out_14_port, lu_out_13_port,
lu_out_12_port, lu_out_11_port, lu_out_10_port, lu_out_9_port,
lu_out_8_port, lu_out_7_port, lu_out_6_port, lu_out_5_port, lu_out_4_port
, lu_out_3_port, lu_out_2_port, lu_out_1_port, lu_out_0_port, n9, n10,
n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25
, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54
, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83
, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n112,
n113, n115, n109, n110, n111, n114, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187 : std_logic;
begin
X_Logic0_port <= '0';
U112 : OAI33_X1 port map( A1 => n9, A2 => n10, A3 => IN1(31), B1 =>
sum_out_31_port, B2 => n11, B3 => IN2(31), ZN =>
overflow);
U140 : MUX2_X1 port map( A => IN2(14), B => B_booth_to_add_14_port, S =>
ALUW_i(1), Z => mux_B_14_port);
U143 : MUX2_X1 port map( A => IN2(11), B => B_booth_to_add_11_port, S =>
ALUW_i(1), Z => mux_B_11_port);
U146 : MUX2_X1 port map( A => IN1(9), B => A_booth_to_add_9_port, S =>
ALUW_i(1), Z => mux_A_9_port);
U147 : MUX2_X1 port map( A => IN1(8), B => A_booth_to_add_8_port, S =>
ALUW_i(1), Z => mux_A_8_port);
U148 : MUX2_X1 port map( A => IN1(7), B => A_booth_to_add_7_port, S =>
ALUW_i(1), Z => mux_A_7_port);
U151 : MUX2_X1 port map( A => IN1(4), B => A_booth_to_add_4_port, S =>
ALUW_i(1), Z => mux_A_4_port);
U152 : MUX2_X1 port map( A => IN1(3), B => A_booth_to_add_3_port, S =>
ALUW_i(1), Z => mux_A_3_port);
U153 : MUX2_X1 port map( A => IN1(31), B => A_booth_to_add_31_port, S =>
ALUW_i(1), Z => mux_A_31_port);
U154 : MUX2_X1 port map( A => IN1(30), B => A_booth_to_add_30_port, S =>
ALUW_i(1), Z => mux_A_30_port);
U156 : MUX2_X1 port map( A => IN1(29), B => A_booth_to_add_29_port, S =>
ALUW_i(1), Z => mux_A_29_port);
U157 : MUX2_X1 port map( A => IN1(28), B => A_booth_to_add_28_port, S =>
ALUW_i(1), Z => mux_A_28_port);
U158 : MUX2_X1 port map( A => IN1(27), B => A_booth_to_add_27_port, S =>
ALUW_i(1), Z => mux_A_27_port);
U159 : MUX2_X1 port map( A => IN1(26), B => A_booth_to_add_26_port, S =>
ALUW_i(1), Z => mux_A_26_port);
U160 : MUX2_X1 port map( A => IN1(25), B => A_booth_to_add_25_port, S =>
ALUW_i(1), Z => mux_A_25_port);
U161 : MUX2_X1 port map( A => IN1(24), B => A_booth_to_add_24_port, S =>
ALUW_i(1), Z => mux_A_24_port);
U162 : MUX2_X1 port map( A => IN1(23), B => A_booth_to_add_23_port, S =>
ALUW_i(1), Z => mux_A_23_port);
U163 : MUX2_X1 port map( A => IN1(22), B => A_booth_to_add_22_port, S =>
ALUW_i(1), Z => mux_A_22_port);
U164 : MUX2_X1 port map( A => IN1(21), B => A_booth_to_add_21_port, S =>
ALUW_i(1), Z => mux_A_21_port);
U165 : MUX2_X1 port map( A => IN1(20), B => A_booth_to_add_20_port, S =>
ALUW_i(1), Z => mux_A_20_port);
U167 : MUX2_X1 port map( A => IN1(19), B => A_booth_to_add_19_port, S =>
ALUW_i(1), Z => mux_A_19_port);
U169 : MUX2_X1 port map( A => IN1(17), B => A_booth_to_add_17_port, S =>
ALUW_i(1), Z => mux_A_17_port);
U170 : MUX2_X1 port map( A => IN1(16), B => A_booth_to_add_16_port, S =>
ALUW_i(1), Z => mux_A_16_port);
U171 : MUX2_X1 port map( A => IN1(15), B => A_booth_to_add_15_port, S =>
ALUW_i(1), Z => mux_A_15_port);
U172 : MUX2_X1 port map( A => IN1(14), B => A_booth_to_add_14_port, S =>
ALUW_i(1), Z => mux_A_14_port);
U174 : MUX2_X1 port map( A => IN1(12), B => A_booth_to_add_12_port, S =>
ALUW_i(1), Z => mux_A_12_port);
U175 : MUX2_X1 port map( A => IN1(11), B => A_booth_to_add_11_port, S =>
ALUW_i(1), Z => mux_A_11_port);
U178 : NAND3_X1 port map( A1 => n12, A2 => n13, A3 => n14, ZN => DOUT(9));
U179 : NAND3_X1 port map( A1 => n20, A2 => n21, A3 => n22, ZN => DOUT(8));
U180 : NAND3_X1 port map( A1 => n23, A2 => n24, A3 => n25, ZN => DOUT(7));
U181 : NAND3_X1 port map( A1 => n26, A2 => n27, A3 => n28, ZN => DOUT(6));
U182 : NAND3_X1 port map( A1 => n29, A2 => n30, A3 => n31, ZN => DOUT(5));
U183 : NAND3_X1 port map( A1 => n32, A2 => n33, A3 => n34, ZN => DOUT(4));
U184 : NAND3_X1 port map( A1 => n35, A2 => n36, A3 => n37, ZN => DOUT(3));
U185 : NAND3_X1 port map( A1 => n40, A2 => n41, A3 => n42, ZN => DOUT(30));
U186 : NAND3_X1 port map( A1 => n43, A2 => n44, A3 => n45, ZN => DOUT(2));
U187 : NAND3_X1 port map( A1 => n46, A2 => n47, A3 => n48, ZN => DOUT(29));
U188 : NAND3_X1 port map( A1 => n49, A2 => n50, A3 => n51, ZN => DOUT(28));
U189 : NAND3_X1 port map( A1 => n52, A2 => n53, A3 => n54, ZN => DOUT(27));
U190 : NAND3_X1 port map( A1 => n55, A2 => n56, A3 => n57, ZN => DOUT(26));
U191 : NAND3_X1 port map( A1 => n58, A2 => n59, A3 => n60, ZN => DOUT(25));
U192 : NAND3_X1 port map( A1 => n61, A2 => n62, A3 => n63, ZN => DOUT(24));
U193 : NAND3_X1 port map( A1 => n64, A2 => n65, A3 => n66, ZN => DOUT(23));
U194 : NAND3_X1 port map( A1 => n67, A2 => n68, A3 => n69, ZN => DOUT(22));
U195 : NAND3_X1 port map( A1 => n70, A2 => n71, A3 => n72, ZN => DOUT(21));
U196 : NAND3_X1 port map( A1 => n73, A2 => n74, A3 => n75, ZN => DOUT(20));
U197 : NAND3_X1 port map( A1 => n76, A2 => n77, A3 => n78, ZN => DOUT(1));
U198 : NAND3_X1 port map( A1 => n79, A2 => n80, A3 => n81, ZN => DOUT(19));
U199 : NAND3_X1 port map( A1 => n82, A2 => n83, A3 => n84, ZN => DOUT(18));
U200 : NAND3_X1 port map( A1 => n85, A2 => n86, A3 => n87, ZN => DOUT(17));
U201 : NAND3_X1 port map( A1 => n88, A2 => n89, A3 => n90, ZN => DOUT(16));
U202 : NAND3_X1 port map( A1 => n91, A2 => n92, A3 => n93, ZN => DOUT(15));
U203 : NAND3_X1 port map( A1 => n94, A2 => n95, A3 => n96, ZN => DOUT(14));
U204 : NAND3_X1 port map( A1 => n97, A2 => n98, A3 => n99, ZN => DOUT(13));
U205 : NAND3_X1 port map( A1 => n100, A2 => n101, A3 => n102, ZN => DOUT(12)
);
U206 : NAND3_X1 port map( A1 => n103, A2 => n104, A3 => n105, ZN => DOUT(11)
);
U207 : NAND3_X1 port map( A1 => n106, A2 => n107, A3 => n108, ZN => DOUT(10)
);
MULT : simple_booth_add_ext_N16 port map( Clock => Clock, Reset => Reset,
sign => ALUW_i(0), enable => ALUW_i(1), valid =>
valid_from_booth, A(15) => IN1(15), A(14) => IN1(14)
, A(13) => IN1(13), A(12) => IN1(12), A(11) =>
IN1(11), A(10) => IN1(10), A(9) => IN1(9), A(8) =>
IN1(8), A(7) => IN1(7), A(6) => IN1(6), A(5) =>
IN1(5), A(4) => IN1(4), A(3) => IN1(3), A(2) =>
IN1(2), A(1) => IN1(1), A(0) => IN1(0), B(15) =>
n177, B(14) => IN2(14), B(13) => IN2(13), B(12) =>
n170, B(11) => n175, B(10) => n147, B(9) => n176,
B(8) => IN2(8), B(7) => n171, B(6) => n173, B(5) =>
n183, B(4) => n178, B(3) => n180, B(2) => n186, B(1)
=> n181, B(0) => n184, A_to_add(31) =>
A_booth_to_add_31_port, A_to_add(30) =>
A_booth_to_add_30_port, A_to_add(29) =>
A_booth_to_add_29_port, A_to_add(28) =>
A_booth_to_add_28_port, A_to_add(27) =>
A_booth_to_add_27_port, A_to_add(26) =>
A_booth_to_add_26_port, A_to_add(25) =>
A_booth_to_add_25_port, A_to_add(24) =>
A_booth_to_add_24_port, A_to_add(23) =>
A_booth_to_add_23_port, A_to_add(22) =>
A_booth_to_add_22_port, A_to_add(21) =>
A_booth_to_add_21_port, A_to_add(20) =>
A_booth_to_add_20_port, A_to_add(19) =>
A_booth_to_add_19_port, A_to_add(18) =>
A_booth_to_add_18_port, A_to_add(17) =>
A_booth_to_add_17_port, A_to_add(16) =>
A_booth_to_add_16_port, A_to_add(15) =>
A_booth_to_add_15_port, A_to_add(14) =>
A_booth_to_add_14_port, A_to_add(13) =>
A_booth_to_add_13_port, A_to_add(12) =>
A_booth_to_add_12_port, A_to_add(11) =>
A_booth_to_add_11_port, A_to_add(10) =>
A_booth_to_add_10_port, A_to_add(9) =>
A_booth_to_add_9_port, A_to_add(8) =>
A_booth_to_add_8_port, A_to_add(7) =>
A_booth_to_add_7_port, A_to_add(6) =>
A_booth_to_add_6_port, A_to_add(5) =>
A_booth_to_add_5_port, A_to_add(4) =>
A_booth_to_add_4_port, A_to_add(3) =>
A_booth_to_add_3_port, A_to_add(2) =>
A_booth_to_add_2_port, A_to_add(1) =>
A_booth_to_add_1_port, A_to_add(0) =>
A_booth_to_add_0_port, B_to_add(31) =>
B_booth_to_add_31_port, B_to_add(30) =>
B_booth_to_add_30_port, B_to_add(29) =>
B_booth_to_add_29_port, B_to_add(28) =>
B_booth_to_add_28_port, B_to_add(27) =>
B_booth_to_add_27_port, B_to_add(26) =>
B_booth_to_add_26_port, B_to_add(25) =>
B_booth_to_add_25_port, B_to_add(24) =>
B_booth_to_add_24_port, B_to_add(23) =>
B_booth_to_add_23_port, B_to_add(22) =>
B_booth_to_add_22_port, B_to_add(21) =>
B_booth_to_add_21_port, B_to_add(20) =>
B_booth_to_add_20_port, B_to_add(19) =>
B_booth_to_add_19_port, B_to_add(18) =>
B_booth_to_add_18_port, B_to_add(17) =>
B_booth_to_add_17_port, B_to_add(16) =>
B_booth_to_add_16_port, B_to_add(15) =>
B_booth_to_add_15_port, B_to_add(14) =>
B_booth_to_add_14_port, B_to_add(13) =>
B_booth_to_add_13_port, B_to_add(12) =>
B_booth_to_add_12_port, B_to_add(11) =>
B_booth_to_add_11_port, B_to_add(10) =>
B_booth_to_add_10_port, B_to_add(9) =>
B_booth_to_add_9_port, B_to_add(8) =>
B_booth_to_add_8_port, B_to_add(7) =>
B_booth_to_add_7_port, B_to_add(6) =>
B_booth_to_add_6_port, B_to_add(5) =>
B_booth_to_add_5_port, B_to_add(4) =>
B_booth_to_add_4_port, B_to_add(3) =>
B_booth_to_add_3_port, B_to_add(2) =>
B_booth_to_add_2_port, B_to_add(1) =>
B_booth_to_add_1_port, B_to_add(0) =>
B_booth_to_add_0_port, sign_to_add =>
sign_booth_to_add, final_out(31) => mult_out_31_port
, final_out(30) => mult_out_30_port, final_out(29)
=> mult_out_29_port, final_out(28) =>
mult_out_28_port, final_out(27) => mult_out_27_port,
final_out(26) => mult_out_26_port, final_out(25) =>
mult_out_25_port, final_out(24) => mult_out_24_port,
final_out(23) => mult_out_23_port, final_out(22) =>
mult_out_22_port, final_out(21) => mult_out_21_port,
final_out(20) => mult_out_20_port, final_out(19) =>
mult_out_19_port, final_out(18) => mult_out_18_port,
final_out(17) => mult_out_17_port, final_out(16) =>
mult_out_16_port, final_out(15) => mult_out_15_port,
final_out(14) => mult_out_14_port, final_out(13) =>
mult_out_13_port, final_out(12) => mult_out_12_port,
final_out(11) => mult_out_11_port, final_out(10) =>
mult_out_10_port, final_out(9) => mult_out_9_port,
final_out(8) => mult_out_8_port, final_out(7) =>
mult_out_7_port, final_out(6) => mult_out_6_port,
final_out(5) => mult_out_5_port, final_out(4) =>
mult_out_4_port, final_out(3) => mult_out_3_port,
final_out(2) => mult_out_2_port, final_out(1) =>
mult_out_1_port, final_out(0) => mult_out_0_port,
ACC_from_add(31) => n185, ACC_from_add(30) =>
sum_out_30_port, ACC_from_add(29) => n168,
ACC_from_add(28) => n172, ACC_from_add(27) =>
sum_out_27_port, ACC_from_add(26) => sum_out_26_port
, ACC_from_add(25) => n149, ACC_from_add(24) => n150
, ACC_from_add(23) => sum_out_23_port,
ACC_from_add(22) => n169, ACC_from_add(21) => n174,
ACC_from_add(20) => n179, ACC_from_add(19) => n120,
ACC_from_add(18) => sum_out_18_port,
ACC_from_add(17) => sum_out_17_port,
ACC_from_add(16) => sum_out_16_port,
ACC_from_add(15) => sum_out_15_port,
ACC_from_add(14) => sum_out_14_port,
ACC_from_add(13) => sum_out_13_port,
ACC_from_add(12) => sum_out_12_port,
ACC_from_add(11) => sum_out_11_port,
ACC_from_add(10) => sum_out_10_port, ACC_from_add(9)
=> sum_out_9_port, ACC_from_add(8) => sum_out_8_port
, ACC_from_add(7) => sum_out_7_port, ACC_from_add(6)
=> sum_out_6_port, ACC_from_add(5) => sum_out_5_port
, ACC_from_add(4) => sum_out_4_port, ACC_from_add(3)
=> sum_out_3_port, ACC_from_add(2) => sum_out_2_port
, ACC_from_add(1) => sum_out_1_port, ACC_from_add(0)
=> sum_out_0_port);
ADDER : p4add_N32_logN5 port map( A(31) => mux_A_31_port, A(30) =>
mux_A_30_port, A(29) => mux_A_29_port, A(28) =>
mux_A_28_port, A(27) => mux_A_27_port, A(26) =>
mux_A_26_port, A(25) => mux_A_25_port, A(24) =>
mux_A_24_port, A(23) => mux_A_23_port, A(22) =>
mux_A_22_port, A(21) => mux_A_21_port, A(20) =>
mux_A_20_port, A(19) => mux_A_19_port, A(18) =>
mux_A_18_port, A(17) => mux_A_17_port, A(16) =>
mux_A_16_port, A(15) => mux_A_15_port, A(14) =>
mux_A_14_port, A(13) => mux_A_13_port, A(12) =>
mux_A_12_port, A(11) => mux_A_11_port, A(10) =>
mux_A_10_port, A(9) => mux_A_9_port, A(8) =>
mux_A_8_port, A(7) => mux_A_7_port, A(6) =>
mux_A_6_port, A(5) => mux_A_5_port, A(4) =>
mux_A_4_port, A(3) => mux_A_3_port, A(2) =>
mux_A_2_port, A(1) => mux_A_1_port, A(0) =>
mux_A_0_port, B(31) => mux_B_31_port, B(30) =>
mux_B_30_port, B(29) => mux_B_29_port, B(28) =>
mux_B_28_port, B(27) => mux_B_27_port, B(26) =>
mux_B_26_port, B(25) => mux_B_25_port, B(24) =>
mux_B_24_port, B(23) => mux_B_23_port, B(22) =>
mux_B_22_port, B(21) => mux_B_21_port, B(20) =>
mux_B_20_port, B(19) => mux_B_19_port, B(18) =>
mux_B_18_port, B(17) => mux_B_17_port, B(16) =>
mux_B_16_port, B(15) => mux_B_15_port, B(14) =>
mux_B_14_port, B(13) => mux_B_13_port, B(12) =>
mux_B_12_port, B(11) => mux_B_11_port, B(10) =>
mux_B_10_port, B(9) => mux_B_9_port, B(8) =>
mux_B_8_port, B(7) => mux_B_7_port, B(6) =>
mux_B_6_port, B(5) => mux_B_5_port, B(4) =>
mux_B_4_port, B(3) => mux_B_3_port, B(2) =>
mux_B_2_port, B(1) => mux_B_1_port, B(0) =>
mux_B_0_port, Cin => X_Logic0_port, sign => mux_sign
, S(31) => sum_out_31_port, S(30) => sum_out_30_port
, S(29) => sum_out_29_port, S(28) => sum_out_28_port
, S(27) => sum_out_27_port, S(26) => sum_out_26_port
, S(25) => sum_out_25_port, S(24) => sum_out_24_port
, S(23) => sum_out_23_port, S(22) => sum_out_22_port
, S(21) => sum_out_21_port, S(20) => sum_out_20_port
, S(19) => n120, S(18) => sum_out_18_port, S(17) =>
sum_out_17_port, S(16) => sum_out_16_port, S(15) =>
sum_out_15_port, S(14) => sum_out_14_port, S(13) =>
sum_out_13_port, S(12) => sum_out_12_port, S(11) =>
sum_out_11_port, S(10) => sum_out_10_port, S(9) =>
sum_out_9_port, S(8) => sum_out_8_port, S(7) =>
sum_out_7_port, S(6) => sum_out_6_port, S(5) =>
sum_out_5_port, S(4) => sum_out_4_port, S(3) =>
sum_out_3_port, S(2) => sum_out_2_port, S(1) =>
sum_out_1_port, S(0) => sum_out_0_port, Cout =>
carry_from_adder);
COMP : comparator_M32 port map( C => carry_from_adder, V => overflow,
SUM(31) => sum_out_31_port, SUM(30) =>
sum_out_30_port, SUM(29) => sum_out_29_port, SUM(28)
=> sum_out_28_port, SUM(27) => sum_out_27_port,
SUM(26) => sum_out_26_port, SUM(25) =>
sum_out_25_port, SUM(24) => sum_out_24_port, SUM(23)
=> sum_out_23_port, SUM(22) => sum_out_22_port,
SUM(21) => sum_out_21_port, SUM(20) =>
sum_out_20_port, SUM(19) => n120, SUM(18) =>
sum_out_18_port, SUM(17) => sum_out_17_port, SUM(16)
=> sum_out_16_port, SUM(15) => sum_out_15_port,
SUM(14) => sum_out_14_port, SUM(13) =>
sum_out_13_port, SUM(12) => sum_out_12_port, SUM(11)
=> sum_out_11_port, SUM(10) => sum_out_10_port,
SUM(9) => sum_out_9_port, SUM(8) => sum_out_8_port,
SUM(7) => sum_out_7_port, SUM(6) => sum_out_6_port,
SUM(5) => sum_out_5_port, SUM(4) => sum_out_4_port,
SUM(3) => sum_out_3_port, SUM(2) => sum_out_2_port,
SUM(1) => sum_out_1_port, SUM(0) => sum_out_0_port,
sel(2) => ALUW_i(4), sel(1) => ALUW_i(3), sel(0) =>
ALUW_i(2), sign => ALUW_i(0), S => comp_out);
SHIFT : shifter port map( A(31) => IN1(31), A(30) => IN1(30), A(29) =>
IN1(29), A(28) => IN1(28), A(27) => IN1(27), A(26)
=> IN1(26), A(25) => IN1(25), A(24) => IN1(24),
A(23) => IN1(23), A(22) => IN1(22), A(21) => IN1(21)
, A(20) => IN1(20), A(19) => IN1(19), A(18) =>
IN1(18), A(17) => IN1(17), A(16) => IN1(16), A(15)
=> IN1(15), A(14) => IN1(14), A(13) => IN1(13),
A(12) => IN1(12), A(11) => IN1(11), A(10) => IN1(10)
, A(9) => IN1(9), A(8) => IN1(8), A(7) => IN1(7),
A(6) => IN1(6), A(5) => IN1(5), A(4) => IN1(4), A(3)
=> IN1(3), A(2) => IN1(2), A(1) => IN1(1), A(0) =>
IN1(0), B(4) => n178, B(3) => n180, B(2) => n186,
B(1) => n181, B(0) => n184, LOGIC_ARITH => ALUW_i(8)
, LEFT_RIGHT => ALUW_i(9), OUTPUT(31) =>
shift_out_31_port, OUTPUT(30) => shift_out_30_port,
OUTPUT(29) => shift_out_29_port, OUTPUT(28) =>
shift_out_28_port, OUTPUT(27) => shift_out_27_port,
OUTPUT(26) => shift_out_26_port, OUTPUT(25) =>
shift_out_25_port, OUTPUT(24) => shift_out_24_port,
OUTPUT(23) => shift_out_23_port, OUTPUT(22) =>
shift_out_22_port, OUTPUT(21) => shift_out_21_port,
OUTPUT(20) => shift_out_20_port, OUTPUT(19) =>
shift_out_19_port, OUTPUT(18) => shift_out_18_port,
OUTPUT(17) => shift_out_17_port, OUTPUT(16) =>
shift_out_16_port, OUTPUT(15) => shift_out_15_port,
OUTPUT(14) => shift_out_14_port, OUTPUT(13) =>
shift_out_13_port, OUTPUT(12) => shift_out_12_port,
OUTPUT(11) => shift_out_11_port, OUTPUT(10) =>
shift_out_10_port, OUTPUT(9) => shift_out_9_port,
OUTPUT(8) => shift_out_8_port, OUTPUT(7) =>
shift_out_7_port, OUTPUT(6) => shift_out_6_port,
OUTPUT(5) => shift_out_5_port, OUTPUT(4) =>
shift_out_4_port, OUTPUT(3) => shift_out_3_port,
OUTPUT(2) => shift_out_2_port, OUTPUT(1) =>
shift_out_1_port, OUTPUT(0) => shift_out_0_port);
LU : logic_unit_SIZE32 port map( IN1(31) => IN1(31), IN1(30) => IN1(30),
IN1(29) => IN1(29), IN1(28) => IN1(28), IN1(27) =>
IN1(27), IN1(26) => IN1(26), IN1(25) => IN1(25),
IN1(24) => IN1(24), IN1(23) => IN1(23), IN1(22) =>
IN1(22), IN1(21) => IN1(21), IN1(20) => IN1(20),
IN1(19) => IN1(19), IN1(18) => IN1(18), IN1(17) =>
IN1(17), IN1(16) => IN1(16), IN1(15) => IN1(15),
IN1(14) => IN1(14), IN1(13) => IN1(13), IN1(12) =>
IN1(12), IN1(11) => IN1(11), IN1(10) => IN1(10),
IN1(9) => IN1(9), IN1(8) => IN1(8), IN1(7) => IN1(7)
, IN1(6) => IN1(6), IN1(5) => IN1(5), IN1(4) =>
IN1(4), IN1(3) => IN1(3), IN1(2) => IN1(2), IN1(1)
=> IN1(1), IN1(0) => IN1(0), IN2(31) => IN2(31),
IN2(30) => IN2(30), IN2(29) => IN2(29), IN2(28) =>
IN2(28), IN2(27) => IN2(27), IN2(26) => IN2(26),
IN2(25) => IN2(25), IN2(24) => IN2(24), IN2(23) =>
IN2(23), IN2(22) => IN2(22), IN2(21) => IN2(21),
IN2(20) => IN2(20), IN2(19) => n148, IN2(18) =>
IN2(18), IN2(17) => n146, IN2(16) => IN2(16),
IN2(15) => n177, IN2(14) => IN2(14), IN2(13) =>
IN2(13), IN2(12) => n170, IN2(11) => n175, IN2(10)
=> n147, IN2(9) => n176, IN2(8) => IN2(8), IN2(7) =>
n171, IN2(6) => n173, IN2(5) => n183, IN2(4) => n178
, IN2(3) => n180, IN2(2) => n186, IN2(1) => n181,
IN2(0) => n184, CTRL(1) => ALUW_i(6), CTRL(0) =>
ALUW_i(5), OUT1(31) => lu_out_31_port, OUT1(30) =>
lu_out_30_port, OUT1(29) => lu_out_29_port, OUT1(28)
=> lu_out_28_port, OUT1(27) => lu_out_27_port,
OUT1(26) => lu_out_26_port, OUT1(25) =>
lu_out_25_port, OUT1(24) => lu_out_24_port, OUT1(23)
=> lu_out_23_port, OUT1(22) => lu_out_22_port,
OUT1(21) => lu_out_21_port, OUT1(20) =>
lu_out_20_port, OUT1(19) => lu_out_19_port, OUT1(18)
=> lu_out_18_port, OUT1(17) => lu_out_17_port,
OUT1(16) => lu_out_16_port, OUT1(15) =>
lu_out_15_port, OUT1(14) => lu_out_14_port, OUT1(13)
=> lu_out_13_port, OUT1(12) => lu_out_12_port,
OUT1(11) => lu_out_11_port, OUT1(10) =>
lu_out_10_port, OUT1(9) => lu_out_9_port, OUT1(8) =>
lu_out_8_port, OUT1(7) => lu_out_7_port, OUT1(6) =>
lu_out_6_port, OUT1(5) => lu_out_5_port, OUT1(4) =>
lu_out_4_port, OUT1(3) => lu_out_3_port, OUT1(2) =>
lu_out_2_port, OUT1(1) => lu_out_1_port, OUT1(0) =>
lu_out_0_port);
U141 : MUX2_X1 port map( A => IN2(13), B => B_booth_to_add_13_port, S =>
ALUW_i(1), Z => mux_B_13_port);
U137 : MUX2_X1 port map( A => IN2(17), B => B_booth_to_add_17_port, S =>
ALUW_i(1), Z => mux_B_17_port);
U129 : MUX2_X1 port map( A => IN2(24), B => B_booth_to_add_24_port, S =>
ALUW_i(1), Z => mux_B_24_port);
U128 : MUX2_X1 port map( A => IN2(25), B => B_booth_to_add_25_port, S =>
ALUW_i(1), Z => mux_B_25_port);
U127 : MUX2_X1 port map( A => IN2(26), B => B_booth_to_add_26_port, S =>
ALUW_i(1), Z => mux_B_26_port);
U126 : MUX2_X1 port map( A => IN2(27), B => B_booth_to_add_27_port, S =>
ALUW_i(1), Z => mux_B_27_port);
U125 : MUX2_X1 port map( A => IN2(28), B => B_booth_to_add_28_port, S =>
ALUW_i(1), Z => mux_B_28_port);
U122 : MUX2_X1 port map( A => IN2(30), B => B_booth_to_add_30_port, S =>
ALUW_i(1), Z => mux_B_30_port);
U121 : MUX2_X1 port map( A => IN2(31), B => B_booth_to_add_31_port, S =>
ALUW_i(1), Z => mux_B_31_port);
U118 : MUX2_X1 port map( A => IN2(5), B => B_booth_to_add_5_port, S =>
ALUW_i(1), Z => mux_B_5_port);
U117 : MUX2_X1 port map( A => IN2(6), B => B_booth_to_add_6_port, S =>
ALUW_i(1), Z => mux_B_6_port);
U135 : MUX2_X1 port map( A => IN2(19), B => B_booth_to_add_19_port, S =>
ALUW_i(1), Z => mux_B_19_port);
U131 : MUX2_X1 port map( A => IN2(22), B => B_booth_to_add_22_port, S =>
ALUW_i(1), Z => mux_B_22_port);
U29 : AOI22_X1 port map( A1 => n187, A2 => lu_out_31_port, B1 => n123, B2 =>
IN2(31), ZN => n39);
U28 : NAND2_X1 port map( A1 => n38, A2 => n39, ZN => DOUT(31));
U70 : AOI22_X1 port map( A1 => n122, A2 => shift_out_19_port, B1 => n121, B2
=> mult_out_19_port, ZN => n81);
U65 : AOI22_X1 port map( A1 => n187, A2 => lu_out_20_port, B1 => n123, B2 =>
IN2(20), ZN => n74);
U64 : AOI22_X1 port map( A1 => n122, A2 => shift_out_20_port, B1 => n121, B2
=> mult_out_20_port, ZN => n75);
U61 : AOI22_X1 port map( A1 => n122, A2 => shift_out_21_port, B1 => n121, B2
=> mult_out_21_port, ZN => n72);
U27 : NAND2_X1 port map( A1 => sum_out_3_port, A2 => n124, ZN => n35);
U25 : AOI22_X1 port map( A1 => n15, A2 => shift_out_3_port, B1 => n121, B2
=> mult_out_3_port, ZN => n37);
U59 : AOI22_X1 port map( A1 => n187, A2 => lu_out_22_port, B1 => n123, B2 =>
IN2(22), ZN => n68);
U58 : AOI22_X1 port map( A1 => n122, A2 => shift_out_22_port, B1 => n121, B2
=> mult_out_22_port, ZN => n69);
U53 : AOI22_X1 port map( A1 => n187, A2 => lu_out_24_port, B1 => n123, B2 =>
IN2(24), ZN => n62);
U52 : AOI22_X1 port map( A1 => n122, A2 => shift_out_24_port, B1 => n121, B2
=> mult_out_24_port, ZN => n63);
U84 : NAND2_X1 port map( A1 => sum_out_15_port, A2 => n124, ZN => n91);
U82 : AOI22_X1 port map( A1 => n122, A2 => shift_out_15_port, B1 => n121, B2
=> mult_out_15_port, ZN => n93);
U12 : NAND2_X1 port map( A1 => sum_out_8_port, A2 => n124, ZN => n20);
U10 : AOI22_X1 port map( A1 => n122, A2 => shift_out_8_port, B1 => n121, B2
=> mult_out_8_port, ZN => n22);
U18 : NAND2_X1 port map( A1 => sum_out_6_port, A2 => n124, ZN => n26);
U16 : AOI22_X1 port map( A1 => n15, A2 => shift_out_6_port, B1 => n121, B2
=> mult_out_6_port, ZN => n28);
U50 : AOI22_X1 port map( A1 => n187, A2 => lu_out_25_port, B1 => n123, B2 =>
IN2(25), ZN => n59);
U49 : AOI22_X1 port map( A1 => n122, A2 => shift_out_25_port, B1 => n121, B2
=> mult_out_25_port, ZN => n60);
U78 : NAND2_X1 port map( A1 => sum_out_17_port, A2 => n124, ZN => n85);
U76 : AOI22_X1 port map( A1 => n122, A2 => shift_out_17_port, B1 => n16, B2
=> mult_out_17_port, ZN => n87);
U91 : AOI22_X1 port map( A1 => n122, A2 => shift_out_12_port, B1 => n121, B2
=> mult_out_12_port, ZN => n102);
U80 : AOI22_X1 port map( A1 => n187, A2 => lu_out_16_port, B1 => n123, B2 =>
IN2(16), ZN => n89);
U79 : AOI22_X1 port map( A1 => n122, A2 => shift_out_16_port, B1 => n121, B2
=> mult_out_16_port, ZN => n90);
U42 : NAND2_X1 port map( A1 => n172, A2 => n124, ZN => n49);
U41 : AOI22_X1 port map( A1 => n187, A2 => lu_out_28_port, B1 => n123, B2 =>
IN2(28), ZN => n50);
U40 : AOI22_X1 port map( A1 => n15, A2 => shift_out_28_port, B1 => n121, B2
=> mult_out_28_port, ZN => n51);
U24 : NAND2_X1 port map( A1 => sum_out_4_port, A2 => n124, ZN => n32);
U23 : AOI22_X1 port map( A1 => n187, A2 => lu_out_4_port, B1 => n123, B2 =>
n178, ZN => n33);
U22 : AOI22_X1 port map( A1 => n122, A2 => shift_out_4_port, B1 => n121, B2
=> mult_out_4_port, ZN => n34);
U45 : NAND2_X1 port map( A1 => sum_out_27_port, A2 => n124, ZN => n52);
U44 : AOI22_X1 port map( A1 => n187, A2 => lu_out_27_port, B1 => n123, B2 =>
IN2(27), ZN => n53);
U43 : AOI22_X1 port map( A1 => n122, A2 => shift_out_27_port, B1 => n121, B2
=> mult_out_27_port, ZN => n54);
U21 : NAND2_X1 port map( A1 => sum_out_5_port, A2 => n124, ZN => n29);
U19 : AOI22_X1 port map( A1 => n122, A2 => shift_out_5_port, B1 => n121, B2
=> mult_out_5_port, ZN => n31);
U90 : NAND2_X1 port map( A1 => sum_out_13_port, A2 => n124, ZN => n97);
U88 : AOI22_X1 port map( A1 => n122, A2 => shift_out_13_port, B1 => n121, B2
=> mult_out_13_port, ZN => n99);
U9 : NAND2_X1 port map( A1 => sum_out_9_port, A2 => n124, ZN => n12);
U7 : AOI22_X1 port map( A1 => n122, A2 => shift_out_9_port, B1 => n121, B2
=> mult_out_9_port, ZN => n14);
U15 : NAND2_X1 port map( A1 => sum_out_7_port, A2 => n124, ZN => n23);
U13 : AOI22_X1 port map( A1 => n122, A2 => shift_out_7_port, B1 => n121, B2
=> mult_out_7_port, ZN => n25);
U87 : NAND2_X1 port map( A1 => sum_out_14_port, A2 => n124, ZN => n94);
U85 : AOI22_X1 port map( A1 => n122, A2 => shift_out_14_port, B1 => n121, B2
=> mult_out_14_port, ZN => n96);
U73 : AOI22_X1 port map( A1 => n122, A2 => shift_out_18_port, B1 => n16, B2
=> mult_out_18_port, ZN => n84);
U55 : AOI22_X1 port map( A1 => n122, A2 => shift_out_23_port, B1 => n121, B2
=> mult_out_23_port, ZN => n66);
U46 : AOI22_X1 port map( A1 => n122, A2 => shift_out_26_port, B1 => n16, B2
=> mult_out_26_port, ZN => n57);
U38 : AOI22_X1 port map( A1 => n187, A2 => lu_out_29_port, B1 => n123, B2 =>
IN2(29), ZN => n47);
U37 : AOI22_X1 port map( A1 => n122, A2 => shift_out_29_port, B1 => n121, B2
=> mult_out_29_port, ZN => n48);
U36 : NAND2_X1 port map( A1 => sum_out_2_port, A2 => n124, ZN => n43);
U35 : AOI22_X1 port map( A1 => n187, A2 => lu_out_2_port, B1 => n123, B2 =>
n186, ZN => n44);
U34 : AOI22_X1 port map( A1 => n122, A2 => shift_out_2_port, B1 => n121, B2
=> mult_out_2_port, ZN => n45);
U69 : NAND2_X1 port map( A1 => sum_out_1_port, A2 => n124, ZN => n76);
U67 : AOI22_X1 port map( A1 => n122, A2 => shift_out_1_port, B1 => n121, B2
=> mult_out_1_port, ZN => n78);
U32 : AOI22_X1 port map( A1 => n187, A2 => lu_out_30_port, B1 => n123, B2 =>
IN2(30), ZN => n41);
U31 : AOI22_X1 port map( A1 => n122, A2 => shift_out_30_port, B1 => n121, B2
=> mult_out_30_port, ZN => n42);
U96 : NAND2_X1 port map( A1 => sum_out_11_port, A2 => n124, ZN => n103);
U94 : AOI22_X1 port map( A1 => n122, A2 => shift_out_11_port, B1 => n121, B2
=> mult_out_11_port, ZN => n105);
U99 : NAND2_X1 port map( A1 => sum_out_10_port, A2 => n124, ZN => n106);
U97 : AOI22_X1 port map( A1 => n122, A2 => shift_out_10_port, B1 => n121, B2
=> mult_out_10_port, ZN => n108);
U108 : NOR3_X1 port map( A1 => ALUW_i(12), A2 => ALUW_i(11), A3 => n115, ZN
=> n17);
U166 : MUX2_X1 port map( A => IN1(1), B => A_booth_to_add_1_port, S =>
ALUW_i(1), Z => mux_A_1_port);
U168 : MUX2_X1 port map( A => IN1(18), B => A_booth_to_add_18_port, S =>
ALUW_i(1), Z => mux_A_18_port);
U173 : MUX2_X1 port map( A => IN1(13), B => A_booth_to_add_13_port, S =>
ALUW_i(1), Z => mux_A_13_port);
U176 : MUX2_X1 port map( A => IN1(10), B => A_booth_to_add_10_port, S =>
ALUW_i(1), Z => mux_A_10_port);
U149 : MUX2_X1 port map( A => IN1(6), B => A_booth_to_add_6_port, S =>
ALUW_i(1), Z => mux_A_6_port);
U5 : INV_X1 port map( A => IN2(31), ZN => n10);
U4 : INV_X1 port map( A => IN1(31), ZN => n11);
U111 : INV_X1 port map( A => ALUW_i(10), ZN => n115);
U105 : INV_X1 port map( A => ALUW_i(12), ZN => n112);
U2 : NAND2_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_3_port, ZN =>
n109);
U3 : NAND2_X1 port map( A1 => n132, A2 => n109, ZN => mux_B_3_port);
U6 : AOI22_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_8_port, B1 =>
n127, B2 => IN2(8), ZN => n110);
U8 : INV_X1 port map( A => n110, ZN => mux_B_8_port);
U11 : INV_X1 port map( A => ALUW_i(1), ZN => n111);
U14 : NOR2_X1 port map( A1 => valid_from_booth, A2 => n111, ZN => stall_o);
U17 : AOI22_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_29_port, B1
=> n127, B2 => IN2(29), ZN => n114);
U20 : INV_X1 port map( A => n114, ZN => mux_B_29_port);
U26 : INV_X1 port map( A => ALUW_i(11), ZN => n116);
U30 : NOR3_X1 port map( A1 => ALUW_i(12), A2 => n115, A3 => n116, ZN => n143
);
U33 : AOI22_X1 port map( A1 => A_booth_to_add_2_port, A2 => ALUW_i(1), B1 =>
n127, B2 => IN1(2), ZN => n117);
U39 : INV_X1 port map( A => n117, ZN => mux_A_2_port);
U47 : AOI222_X1 port map( A1 => sum_out_0_port, A2 => n124, B1 => n184, B2
=> n123, C1 => n17, C2 => lu_out_0_port, ZN => n118)
;
U48 : INV_X1 port map( A => n118, ZN => n119);
U51 : AOI21_X1 port map( B1 => n121, B2 => mult_out_0_port, A => n119, ZN =>
n141);
U54 : CLKBUF_X1 port map( A => sum_out_20_port, Z => n179);
U56 : INV_X2 port map( A => ALUW_i(1), ZN => n127);
U57 : BUF_X1 port map( A => sum_out_21_port, Z => n174);
U60 : BUF_X1 port map( A => IN2(1), Z => n181);
U62 : MUX2_X1 port map( A => IN1(0), B => A_booth_to_add_0_port, S =>
ALUW_i(1), Z => mux_A_0_port);
U63 : BUF_X2 port map( A => n16, Z => n121);
U66 : BUF_X2 port map( A => n18, Z => n123);
U68 : BUF_X2 port map( A => n19, Z => n124);
U71 : BUF_X1 port map( A => IN2(2), Z => n186);
U72 : BUF_X1 port map( A => IN2(15), Z => n177);
U74 : MUX2_X1 port map( A => IN1(5), B => A_booth_to_add_5_port, S =>
ALUW_i(1), Z => mux_A_5_port);
U75 : BUF_X2 port map( A => n17, Z => n187);
U77 : BUF_X2 port map( A => n15, Z => n122);
U81 : BUF_X1 port map( A => IN2(4), Z => n178);
U83 : NAND2_X1 port map( A1 => n139, A2 => n140, ZN => mux_B_0_port);
U86 : NAND2_X1 port map( A1 => n144, A2 => n145, ZN => DOUT(0));
U89 : NAND2_X1 port map( A1 => IN2(4), A2 => n127, ZN => n125);
U92 : NAND2_X1 port map( A1 => n125, A2 => n126, ZN => mux_B_4_port);
U93 : NAND2_X1 port map( A1 => B_booth_to_add_4_port, A2 => ALUW_i(1), ZN =>
n126);
U95 : NAND2_X1 port map( A1 => B_booth_to_add_20_port, A2 => ALUW_i(1), ZN
=> n129);
U98 : NAND2_X1 port map( A1 => IN2(20), A2 => n127, ZN => n128);
U100 : NAND2_X1 port map( A1 => n128, A2 => n129, ZN => mux_B_20_port);
U101 : NAND2_X1 port map( A1 => B_booth_to_add_7_port, A2 => ALUW_i(1), ZN
=> n130);
U102 : NAND2_X1 port map( A1 => n131, A2 => n130, ZN => mux_B_7_port);
U103 : NAND2_X1 port map( A1 => IN2(7), A2 => n127, ZN => n131);
U104 : NAND2_X1 port map( A1 => IN2(3), A2 => n127, ZN => n132);
U106 : NAND2_X1 port map( A1 => B_booth_to_add_9_port, A2 => ALUW_i(1), ZN
=> n133);
U107 : NAND2_X1 port map( A1 => n134, A2 => n133, ZN => mux_B_9_port);
U109 : NAND2_X1 port map( A1 => IN2(9), A2 => n127, ZN => n134);
U110 : NAND2_X1 port map( A1 => B_booth_to_add_12_port, A2 => ALUW_i(1), ZN
=> n136);
U113 : NAND2_X1 port map( A1 => IN2(12), A2 => n127, ZN => n135);
U114 : NAND2_X1 port map( A1 => n135, A2 => n136, ZN => mux_B_12_port);
U115 : NAND2_X1 port map( A1 => B_booth_to_add_23_port, A2 => ALUW_i(1), ZN
=> n138);
U116 : NAND2_X1 port map( A1 => IN2(23), A2 => n127, ZN => n137);
U119 : NAND2_X1 port map( A1 => n137, A2 => n138, ZN => mux_B_23_port);
U120 : NAND2_X1 port map( A1 => B_booth_to_add_0_port, A2 => ALUW_i(1), ZN
=> n140);
U123 : NAND2_X1 port map( A1 => IN2(0), A2 => n127, ZN => n139);
U124 : NAND2_X1 port map( A1 => shift_out_0_port, A2 => n15, ZN => n142);
U130 : AND2_X1 port map( A1 => n142, A2 => n141, ZN => n145);
U132 : NAND2_X1 port map( A1 => comp_out, A2 => n143, ZN => n144);
U133 : NAND2_X4 port map( A1 => n156, A2 => n157, ZN => mux_sign);
U134 : CLKBUF_X1 port map( A => IN2(17), Z => n146);
U136 : CLKBUF_X1 port map( A => IN2(10), Z => n147);
U138 : CLKBUF_X1 port map( A => IN2(19), Z => n148);
U139 : BUF_X1 port map( A => sum_out_25_port, Z => n149);
U142 : BUF_X1 port map( A => sum_out_24_port, Z => n150);
U144 : CLKBUF_X1 port map( A => IN2(11), Z => n175);
U145 : CLKBUF_X1 port map( A => IN2(7), Z => n171);
U150 : CLKBUF_X1 port map( A => IN2(9), Z => n176);
U155 : CLKBUF_X1 port map( A => IN2(5), Z => n183);
U177 : CLKBUF_X1 port map( A => IN2(12), Z => n170);
U208 : CLKBUF_X1 port map( A => IN2(6), Z => n173);
U209 : INV_X1 port map( A => n182, ZN => n185);
U210 : CLKBUF_X1 port map( A => n9, Z => n182);
U211 : CLKBUF_X1 port map( A => sum_out_29_port, Z => n168);
U212 : CLKBUF_X1 port map( A => sum_out_22_port, Z => n169);
U213 : CLKBUF_X1 port map( A => sum_out_28_port, Z => n172);
U214 : INV_X1 port map( A => ALUW_i(11), ZN => n113);
U215 : CLKBUF_X1 port map( A => IN2(3), Z => n180);
U216 : CLKBUF_X1 port map( A => IN2(0), Z => n184);
U217 : INV_X1 port map( A => sum_out_31_port, ZN => n9);
U218 : OR2_X1 port map( A1 => ALUW_i(1), A2 => n155, ZN => n157);
U219 : INV_X1 port map( A => ALUW_i(7), ZN => n155);
U220 : NOR2_X1 port map( A1 => n123, A2 => n112, ZN => n16);
U221 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(12), A3 => n113, ZN
=> n15);
U222 : NAND2_X1 port map( A1 => ALUW_i(1), A2 => sign_booth_to_add, ZN =>
n156);
U223 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(12), A3 =>
ALUW_i(11), ZN => n19);
U224 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(11), A3 => n112, ZN
=> n18);
U225 : NAND2_X1 port map( A1 => IN2(16), A2 => n127, ZN => n151);
U226 : NAND2_X1 port map( A1 => n151, A2 => n152, ZN => mux_B_16_port);
U227 : NAND2_X1 port map( A1 => B_booth_to_add_16_port, A2 => ALUW_i(1), ZN
=> n152);
U228 : NAND2_X1 port map( A1 => IN2(18), A2 => n127, ZN => n153);
U229 : NAND2_X1 port map( A1 => n153, A2 => n154, ZN => mux_B_18_port);
U230 : NAND2_X1 port map( A1 => B_booth_to_add_18_port, A2 => ALUW_i(1), ZN
=> n154);
U231 : NAND2_X1 port map( A1 => B_booth_to_add_1_port, A2 => ALUW_i(1), ZN
=> n159);
U232 : NAND2_X1 port map( A1 => B_booth_to_add_2_port, A2 => ALUW_i(1), ZN
=> n161);
U233 : NAND2_X1 port map( A1 => B_booth_to_add_21_port, A2 => ALUW_i(1), ZN
=> n165);
U234 : NAND2_X1 port map( A1 => B_booth_to_add_15_port, A2 => ALUW_i(1), ZN
=> n167);
U235 : NAND2_X1 port map( A1 => IN2(1), A2 => n127, ZN => n158);
U236 : NAND2_X1 port map( A1 => n158, A2 => n159, ZN => mux_B_1_port);
U237 : NAND2_X1 port map( A1 => IN2(2), A2 => n127, ZN => n160);
U238 : NAND2_X1 port map( A1 => n160, A2 => n161, ZN => mux_B_2_port);
U239 : NAND2_X1 port map( A1 => IN2(10), A2 => n127, ZN => n162);
U240 : NAND2_X1 port map( A1 => n162, A2 => n163, ZN => mux_B_10_port);
U241 : NAND2_X1 port map( A1 => B_booth_to_add_10_port, A2 => ALUW_i(1), ZN
=> n163);
U242 : NAND2_X1 port map( A1 => IN2(21), A2 => n127, ZN => n164);
U243 : NAND2_X1 port map( A1 => n164, A2 => n165, ZN => mux_B_21_port);
U244 : NAND2_X1 port map( A1 => IN2(15), A2 => n127, ZN => n166);
U245 : NAND2_X1 port map( A1 => n166, A2 => n167, ZN => mux_B_15_port);
U246 : AOI22_X1 port map( A1 => n187, A2 => lu_out_18_port, B1 => n123, B2
=> IN2(18), ZN => n83);
U247 : NAND2_X1 port map( A1 => n169, A2 => n124, ZN => n67);
U248 : AOI22_X1 port map( A1 => n17, A2 => lu_out_10_port, B1 => n123, B2 =>
n147, ZN => n107);
U249 : NAND2_X1 port map( A1 => sum_out_26_port, A2 => n124, ZN => n55);
U250 : AOI22_X1 port map( A1 => n187, A2 => lu_out_21_port, B1 => n123, B2
=> IN2(21), ZN => n71);
U251 : AOI22_X1 port map( A1 => n187, A2 => lu_out_26_port, B1 => n123, B2
=> IN2(26), ZN => n56);
U252 : NAND2_X1 port map( A1 => n168, A2 => n124, ZN => n46);
U253 : AOI22_X1 port map( A1 => n187, A2 => lu_out_12_port, B1 => n123, B2
=> n170, ZN => n101);
U254 : NAND2_X1 port map( A1 => n179, A2 => n124, ZN => n73);
U255 : NAND2_X1 port map( A1 => n174, A2 => n124, ZN => n70);
U256 : NAND2_X1 port map( A1 => sum_out_12_port, A2 => n124, ZN => n100);
U257 : AOI22_X1 port map( A1 => n187, A2 => lu_out_3_port, B1 => n123, B2 =>
n180, ZN => n36);
U258 : AOI22_X1 port map( A1 => n187, A2 => lu_out_1_port, B1 => n123, B2 =>
n181, ZN => n77);
U259 : AOI22_X1 port map( A1 => n187, A2 => lu_out_17_port, B1 => n123, B2
=> n146, ZN => n86);
U260 : AOI22_X1 port map( A1 => n17, A2 => lu_out_14_port, B1 => n123, B2 =>
IN2(14), ZN => n95);
U261 : AOI22_X1 port map( A1 => n187, A2 => lu_out_23_port, B1 => n123, B2
=> IN2(23), ZN => n65);
U262 : AOI22_X1 port map( A1 => n187, A2 => lu_out_13_port, B1 => n123, B2
=> IN2(13), ZN => n98);
U263 : NAND2_X1 port map( A1 => n120, A2 => n124, ZN => n79);
U264 : AOI22_X1 port map( A1 => n187, A2 => lu_out_8_port, B1 => n123, B2 =>
IN2(8), ZN => n21);
U265 : AOI22_X1 port map( A1 => n187, A2 => lu_out_6_port, B1 => n123, B2 =>
n173, ZN => n27);
U266 : AOI22_X1 port map( A1 => n187, A2 => lu_out_19_port, B1 => n123, B2
=> n148, ZN => n80);
U267 : NAND2_X1 port map( A1 => sum_out_16_port, A2 => n124, ZN => n88);
U268 : NAND2_X1 port map( A1 => sum_out_18_port, A2 => n124, ZN => n82);
U269 : AOI22_X1 port map( A1 => n187, A2 => lu_out_15_port, B1 => n123, B2
=> n177, ZN => n92);
U270 : AOI22_X1 port map( A1 => n187, A2 => lu_out_11_port, B1 => n123, B2
=> n175, ZN => n104);
U271 : AOI22_X1 port map( A1 => n187, A2 => lu_out_7_port, B1 => n123, B2 =>
n171, ZN => n24);
U272 : NAND2_X1 port map( A1 => n149, A2 => n124, ZN => n58);
U273 : NAND2_X1 port map( A1 => sum_out_23_port, A2 => n124, ZN => n64);
U274 : NAND2_X1 port map( A1 => sum_out_30_port, A2 => n124, ZN => n40);
U275 : AOI222_X1 port map( A1 => n185, A2 => n124, B1 => n122, B2 =>
shift_out_31_port, C1 => n121, C2 =>
mult_out_31_port, ZN => n38);
U276 : AOI22_X1 port map( A1 => n187, A2 => lu_out_9_port, B1 => n123, B2 =>
n176, ZN => n13);
U277 : NAND2_X1 port map( A1 => n150, A2 => n124, ZN => n61);
U278 : AOI22_X1 port map( A1 => n187, A2 => lu_out_5_port, B1 => n123, B2 =>
n183, ZN => n30);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_0 is
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end mux21_0;
architecture SYN_Bhe of mux21_0 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X2
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n4, n5, n6, n7, n8, n9, n10, n11, n12 : std_logic;
begin
U5 : MUX2_X1 port map( A => IN0(5), B => IN1(5), S => CTRL, Z => OUT1(5));
U6 : MUX2_X1 port map( A => IN0(4), B => IN1(4), S => CTRL, Z => OUT1(4));
U8 : MUX2_X1 port map( A => IN0(31), B => IN1(31), S => CTRL, Z => OUT1(31))
;
U9 : MUX2_X1 port map( A => IN0(30), B => IN1(30), S => CTRL, Z => OUT1(30))
;
U11 : MUX2_X1 port map( A => IN0(29), B => IN1(29), S => CTRL, Z => OUT1(29)
);
U13 : MUX2_X1 port map( A => IN0(27), B => IN1(27), S => CTRL, Z => OUT1(27)
);
U14 : MUX2_X1 port map( A => IN0(26), B => IN1(26), S => CTRL, Z => OUT1(26)
);
U15 : MUX2_X1 port map( A => IN0(25), B => IN1(25), S => CTRL, Z => OUT1(25)
);
U16 : MUX2_X1 port map( A => IN0(24), B => IN1(24), S => CTRL, Z => OUT1(24)
);
U20 : MUX2_X1 port map( A => IN0(20), B => IN1(20), S => CTRL, Z => OUT1(20)
);
U23 : MUX2_X1 port map( A => IN0(18), B => IN1(18), S => CTRL, Z => OUT1(18)
);
U1 : MUX2_X1 port map( A => IN0(16), B => IN1(16), S => CTRL, Z => OUT1(16))
;
U2 : MUX2_X1 port map( A => IN0(22), B => IN1(22), S => CTRL, Z => OUT1(22))
;
U3 : MUX2_X2 port map( A => IN0(23), B => IN1(23), S => CTRL, Z => OUT1(23))
;
U4 : MUX2_X2 port map( A => IN0(13), B => IN1(13), S => CTRL, Z => OUT1(13))
;
U7 : MUX2_X2 port map( A => IN0(14), B => IN1(14), S => CTRL, Z => OUT1(14))
;
U10 : MUX2_X1 port map( A => IN0(17), B => IN1(17), S => CTRL, Z => OUT1(17)
);
U12 : MUX2_X1 port map( A => IN0(15), B => IN1(15), S => CTRL, Z => OUT1(15)
);
U17 : MUX2_X1 port map( A => IN0(10), B => IN1(10), S => CTRL, Z => OUT1(10)
);
U18 : MUX2_X1 port map( A => IN0(8), B => IN1(8), S => CTRL, Z => OUT1(8));
U19 : MUX2_X1 port map( A => IN0(19), B => IN1(19), S => CTRL, Z => OUT1(19)
);
U21 : INV_X1 port map( A => CTRL, ZN => n4);
U22 : NAND2_X1 port map( A1 => n5, A2 => n6, ZN => OUT1(0));
U24 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(0), ZN => n6);
U25 : NAND2_X1 port map( A1 => IN0(0), A2 => n4, ZN => n5);
U26 : NAND2_X1 port map( A1 => IN0(3), A2 => n4, ZN => n7);
U27 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(3), ZN => n8);
U28 : NAND2_X1 port map( A1 => n7, A2 => n8, ZN => OUT1(3));
U29 : NAND2_X1 port map( A1 => n9, A2 => n10, ZN => OUT1(2));
U30 : MUX2_X1 port map( A => IN0(28), B => IN1(28), S => CTRL, Z => OUT1(28)
);
U31 : MUX2_X1 port map( A => IN0(21), B => IN1(21), S => CTRL, Z => OUT1(21)
);
U32 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(2), ZN => n10);
U33 : NAND2_X1 port map( A1 => IN0(2), A2 => n4, ZN => n9);
U34 : MUX2_X1 port map( A => IN0(12), B => IN1(12), S => CTRL, Z => OUT1(12)
);
U35 : MUX2_X1 port map( A => IN0(7), B => IN1(7), S => CTRL, Z => OUT1(7));
U36 : NAND2_X1 port map( A1 => n11, A2 => n12, ZN => OUT1(6));
U37 : MUX2_X1 port map( A => IN0(11), B => IN1(11), S => CTRL, Z => OUT1(11)
);
U38 : MUX2_X1 port map( A => IN0(9), B => IN1(9), S => CTRL, Z => OUT1(9));
U39 : NAND2_X1 port map( A1 => IN0(6), A2 => n4, ZN => n11);
U40 : NAND2_X1 port map( A1 => IN1(6), A2 => CTRL, ZN => n12);
U41 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity execute_block is
port( IMM_i, A_i : in std_logic_vector (31 downto 0); rB_i, rC_i : in
std_logic_vector (4 downto 0); MUXED_B_i : in std_logic_vector (31
downto 0); S_MUX_ALUIN_i : in std_logic; FW_X_i, FW_W_i : in
std_logic_vector (31 downto 0); S_FW_A_i, S_FW_B_i : in
std_logic_vector (1 downto 0); muxed_dest : out std_logic_vector (4
downto 0); muxed_B : out std_logic_vector (31 downto 0);
S_MUX_DEST_i : in std_logic_vector (1 downto 0); OP : in aluOp;
ALUW_i : in std_logic_vector (12 downto 0); DOUT : out
std_logic_vector (31 downto 0); stall_o : out std_logic; Clock,
Reset : in std_logic);
end execute_block;
architecture SYN_struct of execute_block is
component mux41_MUX_SIZE32_1
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component mux41_MUX_SIZE32_0
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component mux41_MUX_SIZE5
port( IN0, IN1, IN2, IN3 : in std_logic_vector (4 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (4
downto 0));
end component;
component real_alu_DATA_SIZE32
port( IN1, IN2 : in std_logic_vector (31 downto 0); ALUW_i : in
std_logic_vector (12 downto 0); DOUT : out std_logic_vector (31
downto 0); stall_o : out std_logic; Clock, Reset : in std_logic);
end component;
component mux21_0
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end component;
signal X_Logic1_port, X_Logic0_port, muxed_B_31_port, muxed_B_30_port,
muxed_B_29_port, muxed_B_28_port, muxed_B_27_port, muxed_B_25_port,
muxed_B_24_port, muxed_B_23_port, muxed_B_22_port, muxed_B_21_port,
muxed_B_20_port, muxed_B_19_port, muxed_B_18_port, muxed_B_16_port,
muxed_B_14_port, muxed_B_13_port, muxed_B_12_port, muxed_B_11_port,
muxed_B_10_port, muxed_B_9_port, muxed_B_8_port, muxed_B_7_port,
muxed_B_6_port, muxed_B_5_port, muxed_B_4_port, muxed_B_3_port,
muxed_B_2_port, muxed_B_1_port, muxed_B_0_port, FWB2alu_31_port,
FWB2alu_30_port, FWB2alu_29_port, FWB2alu_28_port, FWB2alu_27_port,
FWB2alu_26_port, FWB2alu_25_port, FWB2alu_24_port, FWB2alu_23_port,
FWB2alu_22_port, FWB2alu_21_port, FWB2alu_20_port, FWB2alu_19_port,
FWB2alu_18_port, FWB2alu_17_port, FWB2alu_16_port, FWB2alu_15_port,
FWB2alu_14_port, FWB2alu_13_port, FWB2alu_12_port, FWB2alu_11_port,
FWB2alu_10_port, FWB2alu_9_port, FWB2alu_8_port, FWB2alu_7_port,
FWB2alu_6_port, FWB2alu_5_port, FWB2alu_4_port, FWB2alu_3_port,
FWB2alu_2_port, FWB2alu_1_port, FWB2alu_0_port, FWA2alu_31_port,
FWA2alu_30_port, FWA2alu_29_port, FWA2alu_28_port, FWA2alu_27_port,
FWA2alu_26_port, FWA2alu_25_port, FWA2alu_24_port, FWA2alu_23_port,
FWA2alu_22_port, FWA2alu_21_port, FWA2alu_20_port, FWA2alu_19_port,
FWA2alu_18_port, FWA2alu_17_port, FWA2alu_16_port, FWA2alu_15_port,
FWA2alu_14_port, FWA2alu_13_port, FWA2alu_12_port, FWA2alu_11_port,
FWA2alu_10_port, FWA2alu_9_port, FWA2alu_8_port, FWA2alu_7_port,
FWA2alu_6_port, FWA2alu_5_port, FWA2alu_4_port, FWA2alu_3_port,
FWA2alu_2_port, FWA2alu_1_port, FWA2alu_0_port, net536481, net536482,
net536483, net536484, net536485, n1, muxed_B_15_port, muxed_B_17_port,
muxed_B_26_port : std_logic;
begin
muxed_B <= ( muxed_B_31_port, muxed_B_30_port, muxed_B_29_port,
muxed_B_28_port, muxed_B_27_port, muxed_B_26_port, muxed_B_25_port,
muxed_B_24_port, muxed_B_23_port, muxed_B_22_port, muxed_B_21_port,
muxed_B_20_port, muxed_B_19_port, muxed_B_18_port, muxed_B_17_port,
muxed_B_16_port, muxed_B_15_port, muxed_B_14_port, muxed_B_13_port,
muxed_B_12_port, muxed_B_11_port, muxed_B_10_port, muxed_B_9_port,
muxed_B_8_port, muxed_B_7_port, muxed_B_6_port, muxed_B_5_port,
muxed_B_4_port, muxed_B_3_port, muxed_B_2_port, muxed_B_1_port,
muxed_B_0_port );
(net536481, net536482, net536483, net536484, net536485) <=
aluOp_to_std_logic_vector(OP);
X_Logic1_port <= '1';
X_Logic0_port <= '0';
n1 <= '0';
ALUIN_MUX : mux21_0 port map( IN0(31) => muxed_B_31_port, IN0(30) =>
muxed_B_30_port, IN0(29) => muxed_B_29_port, IN0(28)
=> muxed_B_28_port, IN0(27) => muxed_B_27_port,
IN0(26) => muxed_B_26_port, IN0(25) =>
muxed_B_25_port, IN0(24) => muxed_B_24_port, IN0(23)
=> muxed_B_23_port, IN0(22) => muxed_B_22_port,
IN0(21) => muxed_B_21_port, IN0(20) =>
muxed_B_20_port, IN0(19) => muxed_B_19_port, IN0(18)
=> muxed_B_18_port, IN0(17) => muxed_B_17_port,
IN0(16) => muxed_B_16_port, IN0(15) =>
muxed_B_15_port, IN0(14) => muxed_B_14_port, IN0(13)
=> muxed_B_13_port, IN0(12) => muxed_B_12_port,
IN0(11) => muxed_B_11_port, IN0(10) =>
muxed_B_10_port, IN0(9) => muxed_B_9_port, IN0(8) =>
muxed_B_8_port, IN0(7) => muxed_B_7_port, IN0(6) =>
muxed_B_6_port, IN0(5) => muxed_B_5_port, IN0(4) =>
muxed_B_4_port, IN0(3) => muxed_B_3_port, IN0(2) =>
muxed_B_2_port, IN0(1) => muxed_B_1_port, IN0(0) =>
muxed_B_0_port, IN1(31) => IMM_i(31), IN1(30) =>
IMM_i(30), IN1(29) => IMM_i(29), IN1(28) =>
IMM_i(28), IN1(27) => IMM_i(27), IN1(26) =>
IMM_i(26), IN1(25) => IMM_i(25), IN1(24) =>
IMM_i(24), IN1(23) => IMM_i(23), IN1(22) =>
IMM_i(22), IN1(21) => IMM_i(21), IN1(20) =>
IMM_i(20), IN1(19) => IMM_i(19), IN1(18) =>
IMM_i(18), IN1(17) => IMM_i(17), IN1(16) =>
IMM_i(16), IN1(15) => IMM_i(15), IN1(14) =>
IMM_i(14), IN1(13) => IMM_i(13), IN1(12) =>
IMM_i(12), IN1(11) => IMM_i(11), IN1(10) =>
IMM_i(10), IN1(9) => IMM_i(9), IN1(8) => IMM_i(8),
IN1(7) => IMM_i(7), IN1(6) => IMM_i(6), IN1(5) =>
IMM_i(5), IN1(4) => IMM_i(4), IN1(3) => IMM_i(3),
IN1(2) => IMM_i(2), IN1(1) => IMM_i(1), IN1(0) =>
IMM_i(0), CTRL => S_MUX_ALUIN_i, OUT1(31) =>
FWB2alu_31_port, OUT1(30) => FWB2alu_30_port,
OUT1(29) => FWB2alu_29_port, OUT1(28) =>
FWB2alu_28_port, OUT1(27) => FWB2alu_27_port,
OUT1(26) => FWB2alu_26_port, OUT1(25) =>
FWB2alu_25_port, OUT1(24) => FWB2alu_24_port,
OUT1(23) => FWB2alu_23_port, OUT1(22) =>
FWB2alu_22_port, OUT1(21) => FWB2alu_21_port,
OUT1(20) => FWB2alu_20_port, OUT1(19) =>
FWB2alu_19_port, OUT1(18) => FWB2alu_18_port,
OUT1(17) => FWB2alu_17_port, OUT1(16) =>
FWB2alu_16_port, OUT1(15) => FWB2alu_15_port,
OUT1(14) => FWB2alu_14_port, OUT1(13) =>
FWB2alu_13_port, OUT1(12) => FWB2alu_12_port,
OUT1(11) => FWB2alu_11_port, OUT1(10) =>
FWB2alu_10_port, OUT1(9) => FWB2alu_9_port, OUT1(8)
=> FWB2alu_8_port, OUT1(7) => FWB2alu_7_port,
OUT1(6) => FWB2alu_6_port, OUT1(5) => FWB2alu_5_port
, OUT1(4) => FWB2alu_4_port, OUT1(3) =>
FWB2alu_3_port, OUT1(2) => FWB2alu_2_port, OUT1(1)
=> FWB2alu_1_port, OUT1(0) => FWB2alu_0_port);
ALU : real_alu_DATA_SIZE32 port map( IN1(31) => FWA2alu_31_port, IN1(30) =>
FWA2alu_30_port, IN1(29) => FWA2alu_29_port, IN1(28)
=> FWA2alu_28_port, IN1(27) => FWA2alu_27_port,
IN1(26) => FWA2alu_26_port, IN1(25) =>
FWA2alu_25_port, IN1(24) => FWA2alu_24_port, IN1(23)
=> FWA2alu_23_port, IN1(22) => FWA2alu_22_port,
IN1(21) => FWA2alu_21_port, IN1(20) =>
FWA2alu_20_port, IN1(19) => FWA2alu_19_port, IN1(18)
=> FWA2alu_18_port, IN1(17) => FWA2alu_17_port,
IN1(16) => FWA2alu_16_port, IN1(15) =>
FWA2alu_15_port, IN1(14) => FWA2alu_14_port, IN1(13)
=> FWA2alu_13_port, IN1(12) => FWA2alu_12_port,
IN1(11) => FWA2alu_11_port, IN1(10) =>
FWA2alu_10_port, IN1(9) => FWA2alu_9_port, IN1(8) =>
FWA2alu_8_port, IN1(7) => FWA2alu_7_port, IN1(6) =>
FWA2alu_6_port, IN1(5) => FWA2alu_5_port, IN1(4) =>
FWA2alu_4_port, IN1(3) => FWA2alu_3_port, IN1(2) =>
FWA2alu_2_port, IN1(1) => FWA2alu_1_port, IN1(0) =>
FWA2alu_0_port, IN2(31) => FWB2alu_31_port, IN2(30)
=> FWB2alu_30_port, IN2(29) => FWB2alu_29_port,
IN2(28) => FWB2alu_28_port, IN2(27) =>
FWB2alu_27_port, IN2(26) => FWB2alu_26_port, IN2(25)
=> FWB2alu_25_port, IN2(24) => FWB2alu_24_port,
IN2(23) => FWB2alu_23_port, IN2(22) =>
FWB2alu_22_port, IN2(21) => FWB2alu_21_port, IN2(20)
=> FWB2alu_20_port, IN2(19) => FWB2alu_19_port,
IN2(18) => FWB2alu_18_port, IN2(17) =>
FWB2alu_17_port, IN2(16) => FWB2alu_16_port, IN2(15)
=> FWB2alu_15_port, IN2(14) => FWB2alu_14_port,
IN2(13) => FWB2alu_13_port, IN2(12) =>
FWB2alu_12_port, IN2(11) => FWB2alu_11_port, IN2(10)
=> FWB2alu_10_port, IN2(9) => FWB2alu_9_port, IN2(8)
=> FWB2alu_8_port, IN2(7) => FWB2alu_7_port, IN2(6)
=> FWB2alu_6_port, IN2(5) => FWB2alu_5_port, IN2(4)
=> FWB2alu_4_port, IN2(3) => FWB2alu_3_port, IN2(2)
=> FWB2alu_2_port, IN2(1) => FWB2alu_1_port, IN2(0)
=> FWB2alu_0_port, ALUW_i(12) => ALUW_i(12),
ALUW_i(11) => ALUW_i(11), ALUW_i(10) => ALUW_i(10),
ALUW_i(9) => ALUW_i(9), ALUW_i(8) => ALUW_i(8),
ALUW_i(7) => ALUW_i(7), ALUW_i(6) => ALUW_i(6),
ALUW_i(5) => ALUW_i(5), ALUW_i(4) => ALUW_i(4),
ALUW_i(3) => ALUW_i(3), ALUW_i(2) => ALUW_i(2),
ALUW_i(1) => ALUW_i(1), ALUW_i(0) => ALUW_i(0),
DOUT(31) => DOUT(31), DOUT(30) => DOUT(30), DOUT(29)
=> DOUT(29), DOUT(28) => DOUT(28), DOUT(27) =>
DOUT(27), DOUT(26) => DOUT(26), DOUT(25) => DOUT(25)
, DOUT(24) => DOUT(24), DOUT(23) => DOUT(23),
DOUT(22) => DOUT(22), DOUT(21) => DOUT(21), DOUT(20)
=> DOUT(20), DOUT(19) => DOUT(19), DOUT(18) =>
DOUT(18), DOUT(17) => DOUT(17), DOUT(16) => DOUT(16)
, DOUT(15) => DOUT(15), DOUT(14) => DOUT(14),
DOUT(13) => DOUT(13), DOUT(12) => DOUT(12), DOUT(11)
=> DOUT(11), DOUT(10) => DOUT(10), DOUT(9) =>
DOUT(9), DOUT(8) => DOUT(8), DOUT(7) => DOUT(7),
DOUT(6) => DOUT(6), DOUT(5) => DOUT(5), DOUT(4) =>
DOUT(4), DOUT(3) => DOUT(3), DOUT(2) => DOUT(2),
DOUT(1) => DOUT(1), DOUT(0) => DOUT(0), stall_o =>
stall_o, Clock => Clock, Reset => Reset);
MUXDEST : mux41_MUX_SIZE5 port map( IN0(4) => X_Logic0_port, IN0(3) =>
X_Logic0_port, IN0(2) => X_Logic0_port, IN0(1) =>
X_Logic0_port, IN0(0) => X_Logic0_port, IN1(4) =>
rC_i(4), IN1(3) => rC_i(3), IN1(2) => rC_i(2),
IN1(1) => rC_i(1), IN1(0) => rC_i(0), IN2(4) =>
rB_i(4), IN2(3) => rB_i(3), IN2(2) => rB_i(2),
IN2(1) => rB_i(1), IN2(0) => rB_i(0), IN3(4) =>
X_Logic1_port, IN3(3) => X_Logic1_port, IN3(2) =>
X_Logic1_port, IN3(1) => X_Logic1_port, IN3(0) =>
X_Logic1_port, CTRL(1) => S_MUX_DEST_i(1), CTRL(0)
=> S_MUX_DEST_i(0), OUT1(4) => muxed_dest(4),
OUT1(3) => muxed_dest(3), OUT1(2) => muxed_dest(2),
OUT1(1) => muxed_dest(1), OUT1(0) => muxed_dest(0));
MUX_FWA : mux41_MUX_SIZE32_0 port map( IN0(31) => A_i(31), IN0(30) =>
A_i(30), IN0(29) => A_i(29), IN0(28) => A_i(28),
IN0(27) => A_i(27), IN0(26) => A_i(26), IN0(25) =>
A_i(25), IN0(24) => A_i(24), IN0(23) => A_i(23),
IN0(22) => A_i(22), IN0(21) => A_i(21), IN0(20) =>
A_i(20), IN0(19) => A_i(19), IN0(18) => A_i(18),
IN0(17) => A_i(17), IN0(16) => A_i(16), IN0(15) =>
A_i(15), IN0(14) => A_i(14), IN0(13) => A_i(13),
IN0(12) => A_i(12), IN0(11) => A_i(11), IN0(10) =>
A_i(10), IN0(9) => A_i(9), IN0(8) => A_i(8), IN0(7)
=> A_i(7), IN0(6) => A_i(6), IN0(5) => A_i(5),
IN0(4) => A_i(4), IN0(3) => A_i(3), IN0(2) => A_i(2)
, IN0(1) => A_i(1), IN0(0) => A_i(0), IN1(31) =>
FW_X_i(31), IN1(30) => FW_X_i(30), IN1(29) =>
FW_X_i(29), IN1(28) => FW_X_i(28), IN1(27) =>
FW_X_i(27), IN1(26) => FW_X_i(26), IN1(25) =>
FW_X_i(25), IN1(24) => FW_X_i(24), IN1(23) =>
FW_X_i(23), IN1(22) => FW_X_i(22), IN1(21) =>
FW_X_i(21), IN1(20) => FW_X_i(20), IN1(19) =>
FW_X_i(19), IN1(18) => FW_X_i(18), IN1(17) =>
FW_X_i(17), IN1(16) => FW_X_i(16), IN1(15) =>
FW_X_i(15), IN1(14) => FW_X_i(14), IN1(13) =>
FW_X_i(13), IN1(12) => FW_X_i(12), IN1(11) =>
FW_X_i(11), IN1(10) => FW_X_i(10), IN1(9) =>
FW_X_i(9), IN1(8) => FW_X_i(8), IN1(7) => FW_X_i(7),
IN1(6) => FW_X_i(6), IN1(5) => FW_X_i(5), IN1(4) =>
FW_X_i(4), IN1(3) => FW_X_i(3), IN1(2) => FW_X_i(2),
IN1(1) => FW_X_i(1), IN1(0) => FW_X_i(0), IN2(31) =>
FW_W_i(31), IN2(30) => FW_W_i(30), IN2(29) =>
FW_W_i(29), IN2(28) => FW_W_i(28), IN2(27) =>
FW_W_i(27), IN2(26) => FW_W_i(26), IN2(25) =>
FW_W_i(25), IN2(24) => FW_W_i(24), IN2(23) =>
FW_W_i(23), IN2(22) => FW_W_i(22), IN2(21) =>
FW_W_i(21), IN2(20) => FW_W_i(20), IN2(19) =>
FW_W_i(19), IN2(18) => FW_W_i(18), IN2(17) =>
FW_W_i(17), IN2(16) => FW_W_i(16), IN2(15) =>
FW_W_i(15), IN2(14) => FW_W_i(14), IN2(13) =>
FW_W_i(13), IN2(12) => FW_W_i(12), IN2(11) =>
FW_W_i(11), IN2(10) => FW_W_i(10), IN2(9) =>
FW_W_i(9), IN2(8) => FW_W_i(8), IN2(7) => FW_W_i(7),
IN2(6) => FW_W_i(6), IN2(5) => FW_W_i(5), IN2(4) =>
FW_W_i(4), IN2(3) => FW_W_i(3), IN2(2) => FW_W_i(2),
IN2(1) => FW_W_i(1), IN2(0) => FW_W_i(0), IN3(31) =>
n1, IN3(30) => n1, IN3(29) => n1, IN3(28) => n1,
IN3(27) => n1, IN3(26) => n1, IN3(25) => n1, IN3(24)
=> n1, IN3(23) => n1, IN3(22) => n1, IN3(21) => n1,
IN3(20) => n1, IN3(19) => n1, IN3(18) => n1, IN3(17)
=> n1, IN3(16) => n1, IN3(15) => n1, IN3(14) => n1,
IN3(13) => n1, IN3(12) => n1, IN3(11) => n1, IN3(10)
=> n1, IN3(9) => n1, IN3(8) => n1, IN3(7) => n1,
IN3(6) => n1, IN3(5) => n1, IN3(4) => n1, IN3(3) =>
n1, IN3(2) => n1, IN3(1) => n1, IN3(0) => n1,
CTRL(1) => S_FW_A_i(1), CTRL(0) => S_FW_A_i(0),
OUT1(31) => FWA2alu_31_port, OUT1(30) =>
FWA2alu_30_port, OUT1(29) => FWA2alu_29_port,
OUT1(28) => FWA2alu_28_port, OUT1(27) =>
FWA2alu_27_port, OUT1(26) => FWA2alu_26_port,
OUT1(25) => FWA2alu_25_port, OUT1(24) =>
FWA2alu_24_port, OUT1(23) => FWA2alu_23_port,
OUT1(22) => FWA2alu_22_port, OUT1(21) =>
FWA2alu_21_port, OUT1(20) => FWA2alu_20_port,
OUT1(19) => FWA2alu_19_port, OUT1(18) =>
FWA2alu_18_port, OUT1(17) => FWA2alu_17_port,
OUT1(16) => FWA2alu_16_port, OUT1(15) =>
FWA2alu_15_port, OUT1(14) => FWA2alu_14_port,
OUT1(13) => FWA2alu_13_port, OUT1(12) =>
FWA2alu_12_port, OUT1(11) => FWA2alu_11_port,
OUT1(10) => FWA2alu_10_port, OUT1(9) =>
FWA2alu_9_port, OUT1(8) => FWA2alu_8_port, OUT1(7)
=> FWA2alu_7_port, OUT1(6) => FWA2alu_6_port,
OUT1(5) => FWA2alu_5_port, OUT1(4) => FWA2alu_4_port
, OUT1(3) => FWA2alu_3_port, OUT1(2) =>
FWA2alu_2_port, OUT1(1) => FWA2alu_1_port, OUT1(0)
=> FWA2alu_0_port);
MUX_FWB : mux41_MUX_SIZE32_1 port map( IN0(31) => MUXED_B_i(31), IN0(30) =>
MUXED_B_i(30), IN0(29) => MUXED_B_i(29), IN0(28) =>
MUXED_B_i(28), IN0(27) => MUXED_B_i(27), IN0(26) =>
MUXED_B_i(26), IN0(25) => MUXED_B_i(25), IN0(24) =>
MUXED_B_i(24), IN0(23) => MUXED_B_i(23), IN0(22) =>
MUXED_B_i(22), IN0(21) => MUXED_B_i(21), IN0(20) =>
MUXED_B_i(20), IN0(19) => MUXED_B_i(19), IN0(18) =>
MUXED_B_i(18), IN0(17) => MUXED_B_i(17), IN0(16) =>
MUXED_B_i(16), IN0(15) => MUXED_B_i(15), IN0(14) =>
MUXED_B_i(14), IN0(13) => MUXED_B_i(13), IN0(12) =>
MUXED_B_i(12), IN0(11) => MUXED_B_i(11), IN0(10) =>
MUXED_B_i(10), IN0(9) => MUXED_B_i(9), IN0(8) =>
MUXED_B_i(8), IN0(7) => MUXED_B_i(7), IN0(6) =>
MUXED_B_i(6), IN0(5) => MUXED_B_i(5), IN0(4) =>
MUXED_B_i(4), IN0(3) => MUXED_B_i(3), IN0(2) =>
MUXED_B_i(2), IN0(1) => MUXED_B_i(1), IN0(0) =>
MUXED_B_i(0), IN1(31) => FW_X_i(31), IN1(30) =>
FW_X_i(30), IN1(29) => FW_X_i(29), IN1(28) =>
FW_X_i(28), IN1(27) => FW_X_i(27), IN1(26) =>
FW_X_i(26), IN1(25) => FW_X_i(25), IN1(24) =>
FW_X_i(24), IN1(23) => FW_X_i(23), IN1(22) =>
FW_X_i(22), IN1(21) => FW_X_i(21), IN1(20) =>
FW_X_i(20), IN1(19) => FW_X_i(19), IN1(18) =>
FW_X_i(18), IN1(17) => FW_X_i(17), IN1(16) =>
FW_X_i(16), IN1(15) => FW_X_i(15), IN1(14) =>
FW_X_i(14), IN1(13) => FW_X_i(13), IN1(12) =>
FW_X_i(12), IN1(11) => FW_X_i(11), IN1(10) =>
FW_X_i(10), IN1(9) => FW_X_i(9), IN1(8) => FW_X_i(8)
, IN1(7) => FW_X_i(7), IN1(6) => FW_X_i(6), IN1(5)
=> FW_X_i(5), IN1(4) => FW_X_i(4), IN1(3) =>
FW_X_i(3), IN1(2) => FW_X_i(2), IN1(1) => FW_X_i(1),
IN1(0) => FW_X_i(0), IN2(31) => FW_W_i(31), IN2(30)
=> FW_W_i(30), IN2(29) => FW_W_i(29), IN2(28) =>
FW_W_i(28), IN2(27) => FW_W_i(27), IN2(26) =>
FW_W_i(26), IN2(25) => FW_W_i(25), IN2(24) =>
FW_W_i(24), IN2(23) => FW_W_i(23), IN2(22) =>
FW_W_i(22), IN2(21) => FW_W_i(21), IN2(20) =>
FW_W_i(20), IN2(19) => FW_W_i(19), IN2(18) =>
FW_W_i(18), IN2(17) => FW_W_i(17), IN2(16) =>
FW_W_i(16), IN2(15) => FW_W_i(15), IN2(14) =>
FW_W_i(14), IN2(13) => FW_W_i(13), IN2(12) =>
FW_W_i(12), IN2(11) => FW_W_i(11), IN2(10) =>
FW_W_i(10), IN2(9) => FW_W_i(9), IN2(8) => FW_W_i(8)
, IN2(7) => FW_W_i(7), IN2(6) => FW_W_i(6), IN2(5)
=> FW_W_i(5), IN2(4) => FW_W_i(4), IN2(3) =>
FW_W_i(3), IN2(2) => FW_W_i(2), IN2(1) => FW_W_i(1),
IN2(0) => FW_W_i(0), IN3(31) => n1, IN3(30) => n1,
IN3(29) => n1, IN3(28) => n1, IN3(27) => n1, IN3(26)
=> n1, IN3(25) => n1, IN3(24) => n1, IN3(23) => n1,
IN3(22) => n1, IN3(21) => n1, IN3(20) => n1, IN3(19)
=> n1, IN3(18) => n1, IN3(17) => n1, IN3(16) => n1,
IN3(15) => n1, IN3(14) => n1, IN3(13) => n1, IN3(12)
=> n1, IN3(11) => n1, IN3(10) => n1, IN3(9) => n1,
IN3(8) => n1, IN3(7) => n1, IN3(6) => n1, IN3(5) =>
n1, IN3(4) => n1, IN3(3) => n1, IN3(2) => n1, IN3(1)
=> n1, IN3(0) => n1, CTRL(1) => S_FW_B_i(1), CTRL(0)
=> S_FW_B_i(0), OUT1(31) => muxed_B_31_port,
OUT1(30) => muxed_B_30_port, OUT1(29) =>
muxed_B_29_port, OUT1(28) => muxed_B_28_port,
OUT1(27) => muxed_B_27_port, OUT1(26) =>
muxed_B_26_port, OUT1(25) => muxed_B_25_port,
OUT1(24) => muxed_B_24_port, OUT1(23) =>
muxed_B_23_port, OUT1(22) => muxed_B_22_port,
OUT1(21) => muxed_B_21_port, OUT1(20) =>
muxed_B_20_port, OUT1(19) => muxed_B_19_port,
OUT1(18) => muxed_B_18_port, OUT1(17) =>
muxed_B_17_port, OUT1(16) => muxed_B_16_port,
OUT1(15) => muxed_B_15_port, OUT1(14) =>
muxed_B_14_port, OUT1(13) => muxed_B_13_port,
OUT1(12) => muxed_B_12_port, OUT1(11) =>
muxed_B_11_port, OUT1(10) => muxed_B_10_port,
OUT1(9) => muxed_B_9_port, OUT1(8) => muxed_B_8_port
, OUT1(7) => muxed_B_7_port, OUT1(6) =>
muxed_B_6_port, OUT1(5) => muxed_B_5_port, OUT1(4)
=> muxed_B_4_port, OUT1(3) => muxed_B_3_port,
OUT1(2) => muxed_B_2_port, OUT1(1) => muxed_B_1_port
, OUT1(0) => muxed_B_0_port);
end SYN_struct;
| bsd-2-clause |
rqou/yavhdl | parser_tests/subtype_indication20.vhd | 1 | 69 | entity test is
subtype t is foo(bar (open)(baz (quz'xxx)));
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/name_ext8.vhd | 1 | 77 | entity test is
constant a : b :=
<<constant foo(bar).baz : t>>;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/const_decl3.vhd | 1 | 78 | architecture test of test2 is
constant foo, foo2 : bar := baz;
begin end;
| bsd-2-clause |
rqou/yavhdl | analyser_json_tests/entity_dup.vhd | 1 | 52 | entity test is begin end;
entity test is begin end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/type_decl5.vhd | 1 | 56 | entity test is
type t is (foo, bar, 'b', 'q');
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/lit_dec7.vhd | 1 | 56 | entity test is
type t is range 0 to 1.0.E+2e3;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/subtype_indication2.vhd | 1 | 46 | entity test is
subtype t is foo'bar;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/file_decl1.vhd | 1 | 40 | entity test is
file foo : bar;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/name_ext5.vhd | 1 | 68 | entity test is
constant a : b :=
<<constant foo : t>>;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/subtype_indication24.vhd | 1 | 53 | entity test is
subtype t is foo(bar)(open);
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/subtype_indication23.vhd | 1 | 47 | entity test is
subtype t is foo(bar);
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/type_decl1.vhd | 1 | 32 | entity test is
type t;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/type_decl8.vhd | 1 | 47 | entity test is
type t is file of foo;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/subtype_indication15.vhd | 1 | 54 | entity test is
subtype t is foo(open, open);
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/subtype_indication_generic_map_arrow5.vhd | 1 | 80 | entity test is
package a is new b generic map(c => foo range bar'baz);
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/subtype_indication21.vhd | 1 | 75 | entity test is
subtype t is foo(bar (open)(open)(baz (quz'xxx)));
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/expr10.vhd | 1 | 59 | entity test is
constant a : b :=
(a + b) * c;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/lit_based5.vhd | 1 | 57 | entity test is
type t is range 0 to 16#f.f#e+2;
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/assoc_list3.vhd | 1 | 72 | entity test is
package a is new b generic map(foo, open, bar);
end;
| bsd-2-clause |
rqou/yavhdl | parser_tests/bit_string_lit6.vhd | 1 | 80 | architecture test of test2 is
constant foo : bar := 32sO"12345";
begin end;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/fifo_generator_v11_0/ramfifo/axi_reg_slice.vhd | 2 | 17286 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
X2w3bNHrWxpELMMAkXSeXNYBysxurI1EFYGFMc/tvlkGvpkqXhMB2jFMicYCIDIbaRrYlwxNMKpK
2w4UQS8BGA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MEHiQ9/JFTDDxLjJhRdjTorlFm8hSOuYMkB6b1YnTi0kSQ/LxduZFsvQEV+NKtVqY2lDnpuzFV9T
SCizKS74yA8ZjycdXKEwAmPgrGV7aGnent/c/rT77TNJojn4ep+UIfKit7OOAQmhL11j6OXUL5yc
e9R733OHdfdqGkOArks=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
2RUNZ3R0+4aa0Ta2ab74Bqu51OQJPED3AA9PHCvYb1aBVNPVqfABMXKTLZdwA1aboqr0IMwRHddg
BuQrDzV3Kn/Ep1s9S5Zm7vcAq+OkOgx1vrMoKMesAqtXz8JN7OvCPtiibdQfMxccpDTijLOoVIu/
171/8Y1HdQKreRGmMplA5Hm+htcCGasrijqImBuUWwAEc6181Q/8HynTiZLy2vNW0z6vZ1sLdOz/
Xx17dEjSfIl1PSRXwCOF0jch7KCNqhqqzFtLTyvw0F31mb8YqZm2PVTRClUawNNhqdpVcAlepwRU
iipRtrZSq9DtSRwPMQud3/LlaS+xtGvy2fklZg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UeXO2O4fkNDidtzEqPdhkaeHbuONYwQUTSi3T7Dxd12zbAji3DNkcf22qa6uk57NQDSsZZ763yCA
pIlr2Owo8LBDkbsm/g5HCdHOUlPdLFuS5LV/en6CjsKdRinXCTf7q9Pup/INiNamCNKRszwGEa61
CrOTpuE3hioZnFocDqg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gQFlwpBvk3lBMh9GLwkhMF1BV2PrUTD1H6YWrY+HlRsP8HRu2+yXLqVQGoONih9Kj4tAipZXffeq
nO4d2Jl04Lf+IMOnf+vqD3Y/X/gFOlcpjX57qMteiI+8kkgapYoYdsPvS6NMukeyyn0y1nPiEYAp
4sRvIziJOTnduVphQ6a4KEkqyY5u/K2DMxisyCzIgKIC6B6hRTbeGGe04Z2iaIOc4vAqXfwifCWY
+lTQol/ERvRQEPHy06X6zaRiYF+UKDRMopAesPCwnXrE8rC0BM8l3amFCsK9DFuJ4p+s5SRdjX95
zvLexoN9C3XI8uvCokQE/2/gaJq9F6WH7H4VUA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11056)
`protect data_block
hqnvkUa8JUdZ+G0rH27DZmTMEgKlM27+iNEeM1enbuxeJ6YkLAmBtbX8SYwOpBUVybD4rUNQMn2k
hE2yI3PPuOWTkANKQHG4o7pRZY1cxEkR1cCp+2dnDuKX3KxrHaOo/NgNR0ggpIrCsPRTkDiLdoAp
ue9MP0nkjt5kOGTUZkRBMy7fgqo+HNx97mEswu6B3Y3B+zjh5CsLpzr+RkHJByQJqcz1nMFN1XeH
DjqTl97GyMcrg2oB47L15m/jTxUXrdEf8haOEn0zUF6KnN0QJyzYbjp0opJE1dl1izx0g7EYHLMV
wJN4RAh1qwSO7UWp4HJdiB68/hFRk67twuFLzNQboBYGwUhkwe2FOzaYg9ClHXDkYRRuwTheV0oa
YZiE4gPenxp0h9AOx9mZO1KvmXV1k56GuebqipQjfM+fwYsMw1LgczivsfOV0EtrmjXhm6WX64zA
kMsqOsRjaKcGfa6D+ZZ3mxhGbHSneyXBKf03qoaXo7u9Uxlbo8sjbec1maujdp3ECcU+FRRD2ND3
TH0Nt1hnVpm2JVlYsyqW17mfTzpKCwgAt380G21R3cQK/6E4dhmBK3I6gTyxtaA25Vx5D3Z1Zjqk
Yk9UUdw7EQlaSkhHMyR04b7mR/nSMrdaEs0OGCDvZVcuzWzZmLFEe8EZpgaF5iK4knRUQp9zg0Rs
FPaXMzZehc6zBVxmLSM0rY8o39UwONlAfqimcjFZ0NJbuEv9n218cwxexrQYcFh1v1kgRL7ZMUpz
84gOTp3SimS5GrLMphgWObbRZ546h+jFYFye2gQ+sBQ/0RKJ7JFN05O4gklNUkrH7i+NIRTAavRc
llgn+r5WRqXtj85ZQX2Wtkxt0iTV4j64BzNSzyaDFVeeIsSQzHIGvmtBAk1FZAGQuOg9UUHKsA91
af/cJcox2cCGshWrkibHyVK/HKHaZd6dEy46m7rYpUumWtUwY/joxB3+H/h4DL87UkK80x+xk+UQ
ITRRLEmM3benNOxpjojArmaSHYnx2iBbgEJaZiGRMj70eDAgqFIz8g+tXXA8Z5XtVo2o9O+knZBf
LSfHGqT3UQfbhGYTrlxKr0PdGKggpq31CRCu933szz0pHOZj6EcLybEa36K/0i+zq8YOU47HQIaj
7naZhDmQ4jsXZckk52lpT1BRXrMEbjqnifGpD3UvBXI6HERb8EaUj6EPGWqVap9IQ+8tKAgiS7Yz
I7vNQxvbB+9B3HUnCOf04QBYr7SDOskAxJmJBajDM3AhcAmIG2R64UbDUSmxIDkQz7lu2VjegB7u
WIAiGHMLgA1gKuhTYW2TYhzEe29HrrOdWy+Nl1TV2fKr3KDmM6rjd9KqLrCMbANS4a3cNTmVwZSU
OZogHhczJHk1uYA6zkP/m2XFYDWnHcYjb/pCf2rw3oSD4vXLaDVYdIdG2JzTBYkoJhYH0wPe5NNl
AAf5VG4V3fSFV+Jom6QE5yK1hF1s9kc/8S3Vl0eHGytXa0Eh/Oles/FY3dDE+vF8xsJ8ko7sQUKl
2m3ybue+U03yIcikONSa4mX6KDeI2ZW83zmkrCcs5BLXQgArk5KGFk5QXI2m7i8yBZtHsq19Yx4a
oaKCTTKCEpCATjivttUxJhx8Mmms+OdkzLQ9+U2zi7X4tkiTRCdJa3DIKQYFU547XWHezwmg+jDq
le9KxNi3PjfmGTd7ytFx+wN9dJEEh1f8F3lsVkHvoxmwDAi0zzfoX3IiiQ0l9SyJ7iNZSuer+kti
loBUIXq2uLrF51+h98Iukg6DUgrFl+qxqQEDf9mlHYYj9gyw6C2zXizKVAtIWUeS4Pei/JOmXmzQ
ousAbh3+QdQv3D2PVwiLdXbHS33xQvGyym1NyAceWwQqAxC1kuSLhRgYUNqyR10YSQA0X/8NSH/M
bgOx40hGxQ2krvbbyW6e9u6vi89qM0RbJYwEhY9ToJ2I9tbDnjPbny9G+NHET4tVhnI2mydbPHlS
QgiBYywcroGiNjwN/axWM8Ai1DHNZuWvxIaqdOQ0sGNBsi4RRmoL2QiIasjhyR/CGrMTkgK4zusC
Wu3e6XvGKu9I0VtZq4LUHwPU9x3BWxZuivGtFLiuqP1fpSc6QFpSnkZ4y987JNj8BKwex9cXOYbT
5hTwu6wXC/yMgb7a11t+Hhc+cdHqNfxJ1/Q0qG72Xc8wBrDdxjMuZPDtB//EYoAZ0cy1UzbSPVRk
PyzjsYNcPrVhllNPZstPvOao3RyrRxeFUm10YeXTAF8e8gjvBLWMtHfk0mtg9beCfMfHh2h+zAtc
WM+3IuXhVnMrzMnLrMAkneiUyQ+mB91tlcqf24fGIql6et4g+UEfNKvh8TWObxLC1MRdEvNciEVr
Plp3JGNwzUOLV0rXogChkbl1LL9P4RBRxwsF3Val/rvpGeDK46z5Y8s1+OTb7oVgaiH4XP3BLMCJ
9gMlJiHkvDsfRtPdyMJDXlFkU84bBNRlfwGKStoeBxhosO51gOv1/WPlvRJQe/vLWvxEIKGm7oAP
8ujnHRVBT31xF4fCSgNXWyulHaGmZZlmQ1EDmuVyTbekyBqQVvmxWzSvnshW+kyMIDfDpw2I4Olg
GqqncByB2fObuwxBaYoaKlj/aIQp/5ViO6usHI+Wn9uwN2oLTkyndyJWZTx7Dz2UOqoY9G3O41Ng
6DVtfUa4z4ybhdRI9XptceS1chu3KOYLABX3QLNu4vKYKK29/uk1p2LkH5v+KNggM6ezhhsGacv4
KwMhkGY1WooQEj1XUNeFPMKItPieAazJ5GrSInPBOGewKr3saKAsmc23rR18GNr127SV/m0pOJKn
YOTlIJGL0aacHpffWXcMO9kyGVjpbhlMEjewEPmGnDHjyC/D52OemFOOKz4ooo8KgG5D5UoCscVM
jKdu/GQ/yWm2MbC+fAhLGttR6l5BC7meYxAcNuZVlXNUwXiKBTsQgyjFgss6DW0t7PSEo1FSnwnO
0h/IjmJr51hOYocX/lrJP37PKOB8y+CsokglccVk1VT2qxkhQC6NkZC8uCHdFXHJShww0kDsrEFb
Q/MX2heNr4g+o53TVf5rW/nuML/thaaxJS+YZBs5WO0VQs+57Ib6q08TEb4lBt0L9EokxsQjlD8Z
JONXzzLo64gjgfaVZ+quSA67qrk5y3way2cWZzfCtOZlfoAM8CN1pxq89Yuae85GW5pXfpt8vn0s
VsYs5zyTgBJMfk52A50oaQPenlNhargcUDKC6Msn9Pqs/6PEyE9HLyvVS6Z6OvqC5Sh/SuRlOoy+
YGwN3gTYd4yKfSendAQXLbnBAXhT84B4Q6MO6zMlEd80ga3muEqlrpFXC6PQz3tDdogb4QXXRWX4
WbIWy4mQzqtyFYhYbj5mpYQATyoxX3PJhCQfekechhfO9P8OsVskgAQmn98aaBynCq7eVSI9IL1C
4yRkCBF+28HIyJqhveFsfexqleBCeQ8z1RcgZLmfPkAdQ3fOlwHt6/iJR+9IkfW3JD9v9iHQJDL1
qxJxe1zNW1GhtC/G6aLjrX9gYXkHWDXWMB7KuPDFqnqiDCZWEjTzcJhWduGSTUFAXRQrz5z3NFex
uwj5X09zb2ZMnVLHKbTiI+KUGePFXZwFTQz5bH8KY/RMCQyeR/ly0YgXAENlgmFfw/3qTXorBOhh
ZY6GieR39U2QsGXMxaS1dmMzy/L9pWvZQbNTGkztla0SM+mpa1gaxpjChZTYi23kdlrgRPKc8ZET
VVRn8SloyBoCkhCVE1RCZzOQS3ak8QfcLiMpXN0jVgbwlYS0TYjUCt91scE5g8qhSMJkLIxJ9LL0
3Xaja4X5O1/q13zM7CGxzzoSaIcUbF4V9Ff2YxP7kCdgdOiTl2MYfn4uApdQt2X2PAFhW3R72pLb
eM4hf4kyLpDG5iBhBJgWNX3t+Dqr9Ni/gyc4lhsfJPqCreDjCIrUNlqZAsys870oNpBkHDHdb3zj
LyQwjp7QDXm0hdQ/TrwYOXIhrMQBve3RZAbPCdYZ/iY6sMaN6dpKe0oG/6+LtElfUf8/+1C4ILTC
ECVGBreH2tvS4q+9Ztmq/OEJN0T//mguh+dJ2Qa9Q9B0RA0If7swtGiJTFVU95yc0gE8NDyJcVMv
hQ9QeY5HP8KRYoIYrp5z8UwtjDq5DLaEAXIkgcmE5UVgn6jSvbumghTW3qYFSRMtmh/URACoVS0V
L5du7ZPCiaNXapTb2nW65S76TyLrbKVNCxtCjG4yOCkKpxQ3dZpU1Pm244TLBfVck/mPCV3dBVbB
1LtW0QjVxPuypiBcyDVSI3RYJHStoWvpPqLzHCvdn3V/UWZO4ssCixWsCtPpzIIaCvi5qhf2LU6u
nqynBUGrUmXH/Jw9nVsm/wbCW3LxWu8WxCseKI5eL8y5iS/V8aoF3mYhJiNvJNvXVGICRVOkOyAI
NGsHIHZZJ0baAWTCo4TBN0kXuRQ5xzWR193TBHnWNe8kzJCYxsh7qRoq3wHJTCjER0FDHiGJLiwG
U0z+fri7FjCNJYVA+4Dhs5QJfFTeFKWL7wvrH8kf9sFTwwQdgZC+fYgM9NoDTvUya11+vfCUmLa4
v35OHLU5PPwEr9GuyvcD7Bq3OYVx1a9at++sGvsoVkILqq3r5GKMCVT4sS45y9XKjbF8Akc/KvRP
Isep+/qxvE3wY+FJ//FjdMSnI1HKs63d2hdrqlLSUoyD8d5kHCzhMm9SboMKt5T4CafrE4fDhBxo
eprkUv/Zvj0ZDntuJWqHtdBcR4il+geoKQxExOfcNBli6Dt5N0CJLh+hMJPNYXatFjy5C3iRalAi
NBxu7FraTD3I8oeYwBGz1AL2dm4ZCcWGiAfIqF+hufGh72bH94E5K03euROhnMt+1f8Po/j8UMd0
46771rKGniMVeN5BO1TR1V/7ZQZm4WF1yZmXTza0lA9rKLZLpbv+fwhXvVteTMjEcrnaKWlylph4
gGMtaJms5MQZGqxSP4DWyeoUq3MCwJlK8BDPGe9Ufe6W2J8Vg9yu1q0lCbOCh/K5UeOdl/xdRbbX
Ahv3kC1578ha4cuaojOJ9EiRROzX7X/z+qD95zQ5rLhoRiPUXY4F6D6zkG13GMzqYAUsDF+t/LzB
vTYfQPQaGbFLdFUa8CHt/5mrBCyU2WbkDD+7w1YHoMsCkbpWXm9p1jkfNsykTsZ8hQ9JcxW1fgKY
1hT36u6YOaFdd9TiCJSPuzfW5WIHoi1RktricweWaDn1FC2RDb+MBkPXlPj2euJbJ6Z2q7Mp5k+8
rrvSYDQ7ZwXMFsjrw61QENdvDpxokJ7pvfZc9WkHkWl3cD99JnQXdZ0OU/6S6izaqaq75FIAzcIk
ZJzKmgbmxipGefs/QJcGFOBbOb2XBk0+cQPSjIc9/h4d9RPJIQ712V9Aga+a3AD0v0JaN2ewtQMT
idDcwUnQlOgZhRJljF4Ig1h7AWpzqwBAIGTzmDlAyIRyW2lZQiCLGlszn4fxhM8OY/mhAwCm2iul
JDXqXuAXK3KHFSE8SQukPrBbgiybuao716Pn/MA+hrIu0OJuE7NT9y39U7Is+8SWF4E22o7TdFLX
HoBVzdHPsZBsEep6stqF5UHcazT2f9yGzQDcfDRTiwZap2jofbRD/90I3rxJn6L6sZTFEkcDkX5i
W87TNNVYYifp62K/c7NAXCxExhocmYMMW6oTE5g7SmMwXfDf8veNmLISAhy7dmvXtMYvQBa4T8Kj
cz4oRozscWrgI7jzYrllS8b8h8UmKVi5dMG8IVkd2bmQV96R3o9S4j98yE2AiccqkbuCOA0OemDa
CIZX5ltKuNvUd9VQyWUOnHFeBbjMViJEGrqGPIdbxqbsrCj6bmiPXCcQx2ASLrjKfidLBNy7dLfN
wuPceewZwH46AD6M6TgmEmLDFfpZrNv238zIBqqD/jqckkaPsOHFGYQ4hjtriXYFRJeJIGgfnMb3
GTG5n5Zo1+0JTs2T+zIAjIXplBqJFcjoHv+/5R6qaAL69O7cJzome9tPxpHx0kw/rHL98P6lw6EM
XeZw9iDye2wmz2u4zuO9+7REi2uRc8IGJdbNIEKMpBgChoT2+b1c1zAFm6lGFs+M5wLBlbiblke5
+COB6R0KDo/VnPN6gz2hr0Nqc2smwF8TuQd6NV9KtwXizOoyfHk1QgREZypbFQzElD/S6bUE/Lzq
qi3MEKYtc6vbGP+OkKhW9xb3dlai7mjBMAFC7/pgaQ24p3fqkagquKY5DyvuAQM2kOOr7WnyURHm
HH1jrCM7a7ShJ/VDlSnGjaH9wvIqF14N3aDOiXP3nMQ7rRqPuC2u4nfkn12K7js+IIh6lLrRVlwu
G5Nglz275sD1PoIcQ8iMm9EPFwPhPtnga7adGwnDdnx5/+RnbbL2SHMIBBrqet3px/8gTY1a9/05
3rQ2xu7cQixc6MeMNfQc8OcYgRNvXOGTxSisn0PUQtQFXXGk7lui1UnWvZ/Rz6lSRh28d3QWP+6D
izfaEQ1ABg6RDUvPUChH6vy73BJY/Gd069dKiRExkuaLwFnZmFp7J8yynID1VQplTCBmih+LTSO9
B+PjAusmAorlhh7X7QJqVAMhy0DErNL8mcsxPK3QecRCEILVeQt5g1RBq+9laQkgF8LL8DsoaMTG
a6zhZImZiqEvtAY8vgm0Qw9b34geR1A+fjXd3OVG1gyF2KVkeiLuufvD8+WnN7MJCMAxteFI6Jnu
jI7kQyEskpj85XeGWSrlD2/bdsdLMZqPw3saJBNU9cVZNXQRxmGk9tGHsu4iFhXaage7aR2q0CfB
7xrB5zJX0qM0nqPVz6xip9rDnDOR7BLmpi4teDQ5I+RISFU+jAFZSr9pBiha1Hsfd+SpHPtlas3C
4+WwvsfDkBxp226QBZfK+6tp+CPiMX724cXWIDIm657TpCHi+8MjqD5VjLsRA2BCc27dyAU0HnBc
2ljJV+Abr48YaceKv9KemdODBQXgCMe4xaZtLyET/G0jF+dCWr/0sTMyD4BDpbiQOQBWMy2f8NQV
q53CQpVec0I8S49tLg6ynHU57T1tQw28dzzoMqnDgvaxdtKe60XEiqewhwpbNNxyRkPZMKV4d/b5
5TThkoRlCOrF7frcjUdrYvjJUlWfWCVgWO6LI6LvYnCK2gIYkFoOpg+KWXhL0iFMs5D95cxJu3/O
U7q0v1zpln/JLjsScJfFAnXGxYPhLCdSSmoKyvbnqFOTGN/+pRieS2IETw1ZyZN1LtSiKm4aysLc
mK4i37CWh2g1E6TU95yUW3aA0+3siyKUgI5e9cY2TEWUPSTml4lYW79OShfXT9rp3hdNyjcfBo4e
+TyuYwF72ZFM+AMOKvjX758plAFEwAcF5jVWRzTZBCMbVcxO3QgVnFRrpTSygmBJakX6niaLiyLq
huFGVVz4EoIU09VwFwGNnHH7LFLla3RTiVens/pCX9w9Jy0eCEQqTN+wUEO/5mlITwSE4Ziclz6V
al4GY4zdEs/Mec++HlpBTeOw5+c6rM1B+9yQ698qjXZsCzE1lTzZxUoAg1sCgGhH7DadDSYe9thF
GMrr2vdIBqooVwqcLCMXJS0wspBsZ0On/6+smVDzV/cA6DhfMONGNIlf8aw/WFt03vKcYgXAiCiC
5Xkd0CTuJ2qoNQwxQX/L5IgU1qKm0m0/1H7WBmACeVt0/0io5tL+Nd77+IjYj+KoRCwkCp1lHF0F
AulomSbd2p1qru9GtbKe2VQ3HQOzx6GFpko6itIi6nuU6NSpuVO2r5s+U7hvxBw4UcHNxPfANn4Y
bRdDglerA5Qexy2PtETR2QsWNdWyKbYmJSPjvwBXHl2BTc84MTj6hJ0c5W1SE2FEedakG+Y8FNzE
NXjwNgAZx/Zi/vRrSYMbWyu1IVSZyFESbKtNvCd2EU/fq1QTEfQXCjZUpdlPqc7XpdXEigCY7nD0
kF1TK4H2Xgo1Yb4N0KNj0DGXGVF4igxABQTvrd/1Nxe2NhCRZ3yzPLpGkechp60orV1P+uEw9u4S
cV1SB/G/gngseBO1Rzjexn/t4ZHSHQi5MJMGtYmkYfMVDYWCvscwomY9gei0QgTkL2DVn4ehXMkW
gwqxx3GLCoKeR6kiRL1zugQGjtCU3bnlldYwObkarYIRS0MiGGorSClappMHXG/mjc0PYi7CVxP9
Tt2X6y6oCK21+pz8vXrPzdApqfMhhBAb3T1FEaIKULZIa8Bi3umM5heLcU3BGPjHob9ObN/HVjiE
80mlHihUyE+vh1WPWkJJUr/nL2i/Seb0xxQ7S4sq6nfaiq6vGL5bevmV5GTp/F8aZVnhIjx/t4Ci
w+dfAu+Xqv3Icp7UdxfNG1954R3klVbmUfM9gQtMMbL2M35Vop5wj+wcd0g+uRV89EXPRvugjLBs
LbTstB2GYOPnq9BqNRTxId8MRuVRRaaIb5G7fAK3bzZgPUG//B9F6vReT+gmxZJu2+BZ13jW2fjD
EQdAgY1T/zsblcUVjccyAKoGt2LejcXhUBy3GNoutpH/xacDAd7sXwjyXDFM7zcqiI3PMvremwFZ
k/m4lHSdPs9vmLoh6ArerH1i/+KezgA3xciknExBERpz9dn2Bl2VU7PMf4MqaGsY/XR1TCuK2VKI
QTpyKFHhb0bzhmsVy/vF4NlIo8G14os/4VfvfjPSILL5nUug6GrRpLOZragw2AaSoIAXcgM7Kje6
C2X8gCMpUbeGN1gLaLiiOhH1wBAdWhn0aeAKe+xrceXXBfsxIXVzDeCmypCmLTZU9p3hxWlJhFgd
+/E3DWVXcQfQD4CbOJX3FBKTlXVYoPFuUy4JxPA/mVXczQZI+DSNeJV91/9fLhV6slaHIr86SXDo
xwq6jOJzRU6YjvXzBhSpbfnBoNereCQB6QsY7jycLsS6aOEFbZVaPciJbHCQ0/QzwlABOy90rgq5
YCw7HP+67vrBgnJC1PeshEy9pxQjdQjC5VK0mY0faROAFJAifXFkyLeVm2LXgV0/j9ijC5IwzmHS
YT3ywqKbn127OE/509++TVcrmv2c1YItg+zVQS5ZUJE8qu0fOs3SkNlxUknTKQHFx6P19IYSWC4T
mcwQ4qBKG/JUya4qTGLv/N63kFcx5E0JSUhL3TOBgqmQX1gbYrhQEDFPaSN3Sr+zVk/I9rVlzcZr
HVYy6QlL3kDFko0spUNCLEQOaZL+aoxVQEyYvrnqpTgmF+RW+14inTbqewrVx7Scx/PFHs7kpb5j
4VzyL9BgBdgTB+vJ8jOiWaauUVaJBI0XAZf6uPad4xKCXM+oul8SsAbCHNUCekpUKj1tzLkKmokI
b9Slm7rL+CnOhtoSaN6TVhgUHhBNdOZ2ZQyYWmZUF8CO8uog78fA4Tj2f+Bvj1DfCLAgKJtOd+zn
SD8DahhWT1RMaV8itrVhA88gmt/KB63ps0azWyIHEIqfc8FyHQ7LV7w83FqzaBml66Wemc5IYeuK
qKP+99fp5l1Ic3a0FTU1J5glHt38d/kF4cwlpaTaLTXCxzXZqq1sq/qcmzIvaoU0eBZBze1j3gk9
ZWDTLCLaegxHONBErTiFvgyghzOt2BKUQ2FapB/krfnmS2CAu1bsys5w6af1rPHdhjYAsOg7YdO/
Xj81e7Z05ADwtJQ+OC+LEkAo4hsNsjD6ylNq4jkYMNScTsGJH6TrQXtnmFq+SRM8GBt0tOZlrU/z
8SqYZFynev7elUTUOwJpkUPOY2w+JzzII+yh3cJth5DfHCBi8Z+fpxGzlxu9Gwn1T4UJJuCo/fUe
hIKLtM31PFDJhlsQC1i3O2Y/xZZlJoENts0TKpVWpGCTWvjnuJdPEATqnunNxzhfxSyuhbArcdQ9
emE5Q80LHGBgRzCxTwh8NkS3rzNFa19452Ggm7Mca6Ofq9QOyW2BL9rYndPRcuAvfiF3ee2CFzkq
H0Qhz08SWIhcKQP4hROOCZRQov0mnP7Tkdova7P85I12SwdfIKScQw3pizCKcn+R800Fdc3hc/yo
jNe/k6Zh4pCKEnyV2TXuGax0LKONmPWs15j8+UjymWHkgXsSo355wb9xaD07VFWaIEQhC5nT95Eg
Y+k0bu7/asiW5zgsMLPZ8RPmemlui3M3ke7sipOMEFL7ggQtT63DiFdyfFkMuq/rJk6mSqRMdApV
HrDuh38+CU8xU3/nCJM26mLxC/xlQF4/0DDQfFPg9SK8+GOs7oEfIstTkGFx76ZuAkezOpMYfgdt
52BKvtWFogjI4F9UNTeC7fSFA24Byrynx0cckNMaMrEBG1smp54nHdHtvyZI8x8fs1id789W24pf
HbtdMQucJXufqjw/h7pQ2D0fXMrXFNQU0W2PDJl5KiPnzPUKgOBRXzqkcV6IN4nAusitk7bL7esK
fheUxQNINn5WjXH4Cf92VInDnWGu8Zf7mPN8us9j3odXHgISHQstBPdnWb/8zqxo377qlOr9q4/W
Vsd94gEk6+J1vPXh1V2mNCKasUCfSlER5WaHiizWCHbLxCvoBvMVyvs/GWs/qjG7g80Ac/k5n3i/
N+OHMeTVfRGMfcpjO+a2t9/fabCe93nM+QLff4TMSyM5uaEL4fG6TJ4iza2eURwNSgsu+qhyYOz/
Hx2RYwE1oaSx3QiFTAi4TyUO/qat8KhaPy9LCGxFFRCFAS/CYub6UY+ckJzL84+GVpulJf15TKCF
jXc3CNrn7x9tJq4cXERDOOXPoySHVSOkbOco87xKABOxdsF2eIBEy6w7u06DiN4VlrmG2IykDaVU
yn3UWrVxmQ0smokBQANg7m8US5zHVtSj+FvqrZ896Hnj4yUD4AGAs7aD8sF/klcP2B5VEfy+McJd
jZb7bN457JlJTZPuvvbp9rO5H1UqBjaFksnP5NaxGrsGZgKR4RCKDRytdrt/xncRthaiPuhbZisO
V0i5D8yqSPvlBOVnsUSOEJWXV/jL9FSk86RQHUSQqzLQXb0qL1kBnxuzjjRLSwa4uQ2Wz5SJs4vX
tCsCr1/kBJmVPgHANsztHRXyZO8yJaXuBkuNH6YslQA3FDWL+nP+Hcbyy24FlC+oknVkfjKd9InK
zmMEjul7+kdmx3Zc4APOco2q8cFNikvdYQawFPZTb84KDMMk3cS28gMbiyVKEKKG5bk+kil5GBdS
qWrKkrYdIhkR2VhL+CHIX5ruhhnYhBfUuQyHSKT38reBqvxJHcZbWPvoPFYrahRPn2Yfx62hSATe
REkw1i5iCgbkxzUfAW5d65sH5UtAIW2HCR0lnpNMzSmsOw93CHn7OkXeGbn1BbzzzjFcVhy4wOdd
lu7qo7Z/3r7DU0+OkZIEl79IX1HMJT+KL6f7Vjb7yHAtxINpoPiafWsmUnKnF7IEGERlIDPb0662
Q87DDWUEuRp1f6ujvTfmeA2vCoYdUWRPqKp1BJHuj8p/9uDrweJLXSFtNBDE4ttnp/T7oUEYXd/d
mZZI+ErQJ5I0H0ZEGKX5kfokq4rol9LvR1d2a7bGpkuWHp6hyd4mek+Pnd2YG8rdN1VdAuJXOfuK
B+3aNGaHoPAPvfY16vMJpa2DyRiCzwJBpXTYSLxxgGF9h1CpAplZ3lKbHjWtPk+b4W/E+LN2LVWF
VBzWnKF3fR05j1o08V76L6cou2biCN/rgvyTbFbvs8DbfTXwF7wNsm58HBvl64e+naiZ/Acg6tl3
jNpY6Ouu+/zlrfZmW1h0EGucBzqV20KHEGkqtcYvfOxM6S3ZcsAYAOCtcr+8/3w8RaC8HDd410Fl
6ICviDEmvOhEthh0AguEmO6s65BHxONn1qUs3SQPO6mL6oOe+HzMMu2ohZlpXH0NawwEwi7R1JnV
T8xw97S3Mho5W0g7YmVSym+AYXO6F7zsUndG3ijx//2crO3UXWJtqo35nVBLjn1gOlVBINajuIfE
MMXI4dTQi9kMeLREd2ARlWJYeDdaCS6MueeQnte27vXcYSh9CRB+QBpxsFAuae2StWkwrjWIGhdK
AHk5K8Zboev1gTNtZf2fZjXp5QBfWh7Gse5J1ymrxTF0OfPzgRNPhGAoHZCkrghIBx0/iHI8yWhR
MzBd7xW98jGZb57fhantzUfKfEWdA/0I2rArxrd9+/u3C2/Xqjbd2TtNP98Ezc4p0MeLWBlovkpQ
CgyLqhwXFBDH9cC1uQ06pCQNzTH0BuBPpDWNTFgVguNemV3FffAL4ST5BgBpV1amFTeL96TI2818
BNwWPQtlcyzy8XJ3CZOjYPYxZ9YrjhnEMXHvIgSk85Ny8UORBA2SLzSWmkeTEpF8uCHwzQ5TRFhA
7p8cM+/v9KzNnI9ZBgVWpB2qcE3CgzkKjZiOMhvkCrxiZ5/q8VOA0ERlMpcMwvvK5MiSuzPmLmD3
zPRzBh/cptbdtRXvBLO8XrAoYbHcDQo8giq4RTfeJNj4ArCmQ9+5T0GTCp5nveA2n1BO7zKWRwTA
IPbTQTj1QHMiB8TpnCoJakfGJnY276rsiODkNS5u9n0HyNabQLDGZhnTGqG1Yquw2oyPhDPKcqbY
lQGsHmEFfSxLCHZ8AJjijMdJJByWGrjuznTcN7tw0Rzxe5yogY7RyR9P4rbkwDDjtdCpJEUPABe3
Xu+hVV9AmYCw/Gknf6EOHYvQgv/XwxIslD0tUFti9TGgsqZX5NCmbCZPupG9Bdtfa2vVHeWlHvik
OQ/3EoBW38nUNxGxjkoZTnE0z6ChFeyUFtKdH+TeeUdzvy/0D0f3CMjIR/nO6NGlMULHTbSpnz0S
AyK+D5iHb8ntBxI45vD6u/hw/UNjQW94DophG6JLzHWuoUsqm63KZKTbl7YO2QlEUNn0L5II/knK
R9vGC54iAZZXDI2T77eXnx0wD6GFIUmgD0MZSeB8a/Yz6Q5JMeR6wTUtSSkOjRlzxbm3OKowjUwn
mXEVpQDbCjeciSqpZBY+sxPNBixBvN/zDbAqEM8YGewQ71pskiAoV58iQkc2EVfhuSSpGaje5n9J
BRM+tpFtK/ig/5OIKWQV7efeeedpwVg5A7mHDkTKPG7QlBynOkvYxNFyvvYmZIG/udyzEklEAuT7
/a2KXkg8hLTmz+phbKsc4WR6tvgxU/wT5Y+0yACKBmsRIDQyF3ffs1RhcwDS0mSrvGXkNkNwCPkf
Jg1fQ+AxGfbXdsnGMVb9BIKBHHW+DtBY+2Pbd0qc++aNJaNErKO5y7QfGwtripHwkteNTXE7oWPJ
k6yrrYOt+C1Bxj7EJcd9nnUyXUFdEHL6Z8Jwkm4FosOcp4crZPTtFGtmsSCidCmsTN+MyldcjrPs
3hxsWkdZ5jnPBHRIjct4FaldVt0/yKSsmgrgar3g3aheHNaScoSWHeo6/X0HwPgxyyD3BBgtB81F
uFHQOqqoo5Dr1SmmEy/09vvvjIelQXnECDFW+sFcj6dE69o9YfyvYzjz9K82HFccxdRYzp2hEtOp
OIgoITLNeYQGvBNk5rgQ0y4rtxQ7Nr5ADvZtbgqDtsINmQQbcMtC+a7ha/XIF03oZ/BILzQbHhda
s9QtONPAo021zY+zTj5RrVsaCu1DHiefPDRrASYVNWtxr/YKFhLUIxoA5LYVd05G55UoxsFnNKav
fwKTfedUmKdVGlbKQYt4hYFVT5Q37DZ6QQHvgY0gQPsdR+IxK7VxffjPRzwrCaTZyMworbnykjLW
A8Yg5pvNUgzCtk1z5C+ST1635mrofkahsIKWJFwbjdSZfW+pRxx/rY41Ew78koDRq8VRZqCzA8UQ
xxnmOAML3WBGvRQ76OxtQxycDDZprhoN9806KRowNnDL1qdJ32lm/LHeF2wgMckMxQHDmpOuvYxD
CFTWir9oVbJPbqM+6m4PpGO0Ai8PGAshCa0y1Vo4zgwvdmJFAn6J1KY3kUBYiTZHxMmC0etmDepA
0uM4K5vNfGEvOG19bQdkvXaBTlyGG+TUg4zu+WfJ0vADfa+AHIcSE3fH0oriIe1OEi+gy85uNeEY
1m1GQD1lPbtxlgwFp39r2evDpy9dc4mplOp15CIYDZ7v/jBmEItqe2SVl8TbwcXC2HM/JPXle2yF
X+k+w6V99c1XzakYamWSBfvviRTWMcpj5bWLRTcrtxWpCikpiuTwp+8WT0ixTWlWhpBA5fa8Qxg2
02/2kgHnkxgWzyfXxi/Id9miVZp3eFH4Ji8nVRicQIcIztz0atifzL7hkawCaQxBIVyQPFccCNoo
Yg/oXyOE3Neq1/BFu8WlcDmdKILX3SC/ccV6cE8Vi8QsFtHW0t/LtZsihPQxSmAMBw2rnFfLZwyv
zwxLSBaBfURyZQrzuIsNNX7mQybENnnIIlrbtzTUmlwFZW4Jjz8BaoXRQoEXF0fhY3E3dWfqaTd9
5VvjVdKYpBUJQNv3Quin8rXUAKaYjud07992GD99bl5RWtaC2trQn75e/C0Iz7ja5L4WJj/jCoNM
k/nrM54wbzGF7ZH/+YRe0/7YMWdN1g8GYr0R9xP26Iaebs1hLAIIc+V/lndx+epCcBT9l+eNz8Sn
tZM6GxIW7CM5s6IxMAvQcSGCEOxmVBnPISGY2oBjTe3+3v198Dv/UUc/i07M7Ft1npFE9M0lOQNt
5pf+qrean0uFgOKZMacmZPTMJ/Wbne4ELXOp9b2J7VmHlSEylkSeM/1OLRZgNGdr23KIqYS/V+fE
wj7Kuk95LND83Y6ROPSTLC2ExpsE9PBeEHAATFeG8af6I6QOKhwgFl5N6kHo9hZhMd4LmyUaS9B8
VDgK6hK/ACb5RAK5XPfIkbfCmmZKVNPfeIwgmlDiKYXvaGyDMIaWS4rQ3GeaF03G/hSGzCswpQ==
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/memory.vhd | 2 | 114679 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
XMWpQ/ZiY32/Ly6F+y1CnyWzbgKcQX1mQQVgNoCwyPMGR2bEuX4NYXm+p+Iv3PIhaldxjepF2RNp
Jc3C4BBZbw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SA0D+WTT3om8muP6KFaCvEKsAK2d8kJ7c/1+WkPjg+oNHtqxPAgev5CH3pGtfJnfCDtVW30bVydn
iVo2IVoNwsVVu9Q9AjhRo0zA6Kfu31BXlt5yPr8PvVt1k2vwJrcw3lPPOtbVMgg/pl1ewe63cMvG
2YwxeElh6VHnz+YEqEs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RIC0A6wLjhgVuryPDLTwQMfUWKLIOPUQFBk2N0w6fSq0EKwDEZaSs8NUZpA0M+lt3OIjShTjgzs7
VsriaJmqA0Mh7loJmEudaSWNxT1M5kZQA8wfHeFra4gZ7zlrUF3xScr2ww0f1pZ8kSV+Kh+lmViG
d0DW6FltgxKQrOXUdiRkKVbLnxyOGhzi49QIkIdCMLfD+KkaM0H1lageNhOLPIwXTKwPur06x0wb
lLd8KaaUefT5hYJu3X7Vn26o3MJxsOhbmeKaCnrY0snpT+rUwS3typF9zyCeFOO32JFRItyUMEeH
hCmSJL2+/F21Gy+cPuI8zppRWTdR69c/xv/VvA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fdu4AemMw8f1gIptkydQOd/hkwvxqBaLUBoD/OP2tpU5Pf8MBe5bNwExhla0VJT7hkqKAHfByjoZ
4NirY9xerEzIaGvi/OtJxBUDtVXRE9EHua/mBS5naTrasFRiVMqnGOgGWm4Mcf1Mq1qsizZw804z
ojBzkNMO6M+q9E68PCw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
awMhpk+acHYAH4FU7PBCGUmsQ/JayVyiUpNYAmv06/0+PF8ioPme04zYCLkz1OtbgNemuykfRgC3
Y32RiNAmCAwxscVS7MV8Q8zPk7hV/o1oBT9LIFyEA3BSTlgsNZ6gxniIs/bA8ftJSAJUyctISFGJ
C4QATTRRj6H9GQZcVuVu23DvJWvHpsAEwzDohsGnqUcayE4VyTuuS9WIILlH10HxbkRzbZ1sLrKl
Qh8kddevYhVaLigS4BoRMYRxY6fxC3adNu5EStvb4btA82772bRkFu75YNI/+sOBDFpkgyMzL8uk
0lODSBH56yYXZ4M/FhnpUUSAgWZD7owfRaUekA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 83152)
`protect data_block
n17aYW9pRBh2VHU/RAQBmV/+Tpt2lbNCtzp+8WeFaU7a2IV0W7nIaW05ZpqYI+a7qcevLsA11XM7
lIjTPsU8MqiYK0uK6rUu+s9w6xbl74oKzU6xw3HVAqPoViF8nBG68AsVVauooTYWI9V5IGzqeIgb
tDEFbfkp30e8eK7VqgD8pk4U+k/n/ugQHibNyyK3Y1OH26Xe3BSDf6IfI35FMok0iIdbUsPWsP/B
GZr6pL59PIciwZy7B8dlkV4GIOXXyDPVAz6ZlAwwcmdA1qjHboE67v5nA3oeAELJlgAq+5kqidHr
cXxlj1u3/PTi6leXPiXJl5ZDHZqHpigx1mxx9NQPHeMOVcAGXDyy/txm3WwGDBTpt95OltJBzxWX
HDo3Bv3zwzV7Azt//HVjSDFmdIKsDtAN6TQgOwGdLtPwzmA22igK0We/W03AqA2xektHpMIKEDXp
KSAo7gpoOMSrMiKVSbm5UVEhuGH4wR3u8bX1OkXQBSvtrgQuKC2WTc2H8jKWyEMMJy/s8y8wKq9A
nBd8HnD7QnaRVuVM8nqzr1LeEMwuQ2INeqslTVLw/MXrb9HJKashOCAmV8ABoBoaMKOzIKHWNOCp
PbiYJACVs54ED0wbdPGVxx+4iYMXnP4nPh0xCiBdXHodDXCENLa4A9zG7vqYtBpS+d6BzxQhsbvj
nFzW+F8etSazopiRHmdwrZiTD+tk4XKGSNt00TRoUjM9KLoZ8RJCsBz4LUctVuo46LSHZeNhDak9
pyz+pN4WLW0M2Zdx+vkj//Y5WRjrs79WEjL6FORjnLD3W/ZabxcfNqfjkXAkNeqozm00gugvRR0O
i8zx0a00lUdnSKwQm+JJ0R/kh7FdAYMIS1Cd7zoLbbz/kDZ3Fy/L1bh/u1icieyUdJH+0QwzAI9q
L2P/qQIpc4LT4bvrlWh6NeGzpGgwtklot5AnJyG5FbLTkjNKn9aJdtS6RqzNg07i7RVYJ8+NISDF
XGi8vz0IkvPn3rpz1Xko4EZatTuRVYIaTXF9GHRs2/Ty9iLKYPeUc1wxCClh47mfrB47KhfTDhJ2
f5NyjT1GQ4DZcUvgDjwDCJHSdAi0jYJVeOSMmz18cdKxgSNTvUcA/4u+UTkfghRI7anx7Xn06Qrt
atnqB4zn8yfwDBVzxgBc+Y3nL9bu5ANbhQgoaqleomaRVsPHD214NRFNaWw7zwnWxfVXSmcF4yHn
Wcj8eoCFse8u64mPI1UPRoqDqzdMyuZVhmUuyBATzvsTPeh2ehYZwv7NndQ166m6Xzv1Mq58giDI
2B41i8pbeKJOjv9BiOI7oCrpBimKcRzLuOAzCB+vW+oD+rZjoP33GwHvCXOm3JDpstR9EpFudy5R
PvQh4st91+peMbessk4+h4o2OQrR2sGxQOCWSmqZFzV4jojpWdrDNTVJ74suZ71gwHqFm4GjhLqs
9FLGzxXgYz42CoAeiGQE++P31FYErB3r6t0k9xUsVHPTKc4SgNKd8dTzh3rg/pB5wKuRjgYzWjFE
cey/76uIUeFYqZD945uHBaAeaOY5ltiP/n9916jOg5yYrfOK4MSTA1Z2HzzUmSKd+eqYNDsu1Iez
7ubRcw5JR3GsaSXVwd/cVEflrFFmcSY0LnF48/uu6egOKGwLf41NUFBghGGHm+ulLZySbl6K67Sw
N2/scp7AS6yZ4uhibcoXZhJOpJycNDkkf9jhvnkrPEIu+xYinhVKBS79+mMrpJ2Mx1RuiCPqr37E
BdVBAEu+B8ARBTg6JtiDxRHWBIVs8wVA2UIheM5rVXlqIe8xlXMksfnW1fET0bGsGq8TSuouorx7
jNksacAKfZv055qsbUPFPzfFq6TVBSMK9twog3F6U/TUmPbbOxYXDJIFiEO6WsTn2hLcLFRo4fSn
ztKBqd0VkBcYDxEmMwtoyXAFUm4l1Tw/f5jKFnlxU6Rr4b3HQ5SxPsA28R5ch3rzZysRuWpFb1Im
GXbg8ytx/iUOdzsDQVO+BSU/qPUpnOyqzY8knhd50OJ83whwI3Fqmhzy1sdgrnLZDJYhw2/iHUR4
6TIDgjgx92KucCy7/SZ4AfMdoY53rQjtnIMmX9/D6D14Mqcql5SKSz1AoYmF8NbW8VRXTAsnpi5A
RxKk5w9Q2ABDiPCqVjJGsDdUNOm/E/r60ayXmZAvPYFp8/DnPfBmg0UYYTdktasMIRq2yqX/1BCb
9dx4n0pii3wMH1gBNUJzpNH8VHQAry3BgzjyTpwrP0tgm+lAO1nBVnvCTUT79U86qrlBHaR8l88Y
+sg8UPaRDvdtqhILBJyr7GLBghW4zMb6oMctkBOwoicawtrVf2975M0zZa2J29mI31W68oR4HTtT
Cbl6ONkFs9Abfl27gY2HWspjPeOmR225NJPyicEIsziInl/HPCk3g9q5PBv8/hfhyjd1tgaMZXUk
7RPh2y3FpJIxbx1tJRiNUTlELaKTHhzlocp77bPHAkPYez8v1d8q9On3JRVV9DXvqWxHDVL2DzoV
xApSyY5betku1imEJJ5lnS5WZ7inMtcq5V7wJrcd/KzJfWhtDPqDW8x8clBbCncj0ihHmUvM/Qrg
UF6/rLBRwYigkONKxvSyxuz96n+ZdEI/fKOK6bjFiTqtr+rvCYvF3PuW58Ih9uWCuCrvPZcX0gDs
YRQDcyVmYsb/BRPoLQLbA/wQnIAvD9YxQmDMPwCjZ1AkgvLobmC9EBIGD6HCJRerCfVfqe5PkJk8
3UFNgqej4ZWYWMwiX53TSmC+WqMe7KGSR64WyzjSe3RHZQ4vkFUudRJ7usklhdGp80yEzJqi80QT
I3sfbz5Fi+rJSVBk7vRDsGPQ1e8o3O/QuqiWBJNkfSx4/VvntnyAIxCB+o4m8Rjp2xgoecpnF0qL
+eywoJXE6+ztzav2KRFaHrNivFJSfdElggD9O9+6LkGLHBHIKmaBGg80gm3e+rdUddNXK7pNpY5A
rctVU2CkA5blw/IhpZTpTW9GquyoAyivM5H8j0mKltOBXsp7CW5TfuDLJtanTJ9iQOtyk4eBJX2H
ni0V2bw1koTCrhGXPUx3TzXNTSJKFZptCY1/ISNsAN4RxxSju/TKiIWLOY2p+c7npqxlgbam3bXK
Ppuid98kjFY62UqI+pExARPtLC7qPaU+mkohnXjyhQHltblsfz/wrdQOZVoqsSYlQJL9MaKA/l0M
QqFpGMPKC8g1lMdAWB1eKaW3D3EUS6p5DVE5tpceVtbZCU99Yqf5Z46ntSC9MQbUxrsZvuktP6eU
6HLsAlO839VRUPBqgddATnvq7TSAYgznTEcNzA+1m4to/dECzTMG7Ab7TK2ETY63eHV9hysl0gVB
Bkuay+7ZlmaufGx7XdLDB1k1isQ0Jo8njdhG+EJTuE1MOH0O1U+Of+CwBxc0YrPdqWnt88Lj1SlS
rRtk/7pdgwV6mdM6BmIkO2NQIfrS0C1MInOlkgHPi02XKljAtPW8wEKDO46oKGvMvn2os0bjmJgs
oaeFpc83zCa2CSV0VW1hmT+De2qeadX5o+L0BoJAGXkhURJgCSj7n5YMfJLECzbqCCznqQO/vAAt
aCKsJRbRINcVrUrfTDgSzydJiAzPrLVDX8ggFA/VkdeP/LyLSiByacfCTKu7Uj56nfpycGV6a5LP
eZpMnfTBPE9SvVgi5qr2XTOJwc0IKcn4spxupVI770Ql7EuWPrIYiqDRK/bdpa9T4BzD42G5nwHx
N6iHSbIx+uwQpvhxLXovhW9xgj45tWyZ3O0cDqgnc4yuGs+gQEVtzLOrI9PBi+ICK5B3Wtyp4ohF
Lwh2++wSQ4W45KMXmbEvaC6k1yZeq9Sz1/u/aJWMHgPCbNhUk7o/AHW4bYAebynUARg65ISuGPHZ
MoufdIoLR9sP43/WFqdYscX4i1cwgZn2viiNWOKaPpUSd3pAZwZLnOGkDjXgw9sBUUzLI+dTcuTs
vRfdVFej5QXcLa1O+1JojYVpR1YkgguSdQ3ja8BOhxUHaWYs1uFnVrjflka6epVrl4b+GF/FXQVT
l8BWcYuXbo2bslVoZdV2zg4DvyFYDaMCIV+r/K6Vefycuxhm4biaSzTXrVma6Lg2mmwIluPDIkM6
rrMP5CDWxGRMoiNrL7PpWl9s8Rz4PIDoBEW3zA6HF0OSEf8vQNkhOIJvU19xlYCwvSRvZiayIwKm
BZF/l3E8jsHvBNW1lOE3H5svialocibkeCwRGvyMgqhxnWawBDancW13A7XUvwyYKlGhopgkQvUV
9NK+Qwt4cprq/xpxfBWVeYn3d/nCqoTqE2kKQhAp3qFkprX6kqADsFhp474RFCMWKg+46IGuz6fU
SNItXoLBrHm1eFrX3UImWZBSEQgsWGELIokCL8bX4ZPGZupKLmhV4OGYkRLuplSbcAgQpzY1Ys2z
UuZXZoIn5+VdmpLK+QFGpNaJbhB+0OhHA2AbtQlb/+3qOMLekNqppmLsQ6RECv4zsD0VXqvmKpbp
fX4+9W7UhcOH1RyVikaIJ8hQglgHMHmTD7o/oI3fIumlx+yY60E3+WC7tGyYr529oz6O4TY0G9Cf
A6NsMHPzbOlIOtKLcQrLmgi05tZ1wpj/KzEypuoo0TIDNdLNquxShRD0x6/c4bz4HjFSUQ7g3C8F
pHn8eFszj5tP51Tveyl96yRgjsSaU+9ojgE420UBPknpDkcrqF1w1xKhtzvy7Fa150ohDkfKiRMV
bXDJ96LUTxkxa6ExN6thuCrMkSeX8g+yXC4rwhMU56dBORKpLZk9SkAFx6biZTGgpG/M5dESmeUF
sOEfKArWFCoLCFb3uocgZzb63Iyf/Mmx01ModSLLwPqfYcsUaAlxXoSkTQ3yn83KGEtQuUgpYxrl
soqe0TnOJ/t6lLN35ZVTYIwsfmg7TmpQR/gfzlyh32afioUx3O9NyD9asMZKai1wWNGC0j8f5wpc
3zrLJB/2XUJTElVO/BrfXX+UZg+cwuF2srpLBbu5TrAaQd86kNGPhYe3HXqgsZozv+x100TqGgUv
1NMX6ohz/M2JbkWZG6XqETLDHtCycmQoGp4zTlp72izYP7E3c4xNsKGMy++Kwwmnq3RDMmMVonNx
pdC7NY7b8Y3IymVJWQo2jefw/A3MZLWxbhs4aiwSK72P+EaJ7J0yjzrOkPd7C0fN/Vwadwa4Sz7p
QRJsZ4p7Ekx/emUfj/ygtTetTBOz1fSYcKnhGKpLBshLXuojcKBBie43fHPTOCGNLtx7Fdh94hkr
g+ltpdelIL0jVzwRm18yZeQaDrhvkf3vomKXF0v/N2MNEzJH4xlfYF/szHKkE2IMUyhrC225XBKn
FNeAGHhUZEtPne9hKPOQa4qagpbrptjZrriSSvyGv9T95cH21Yf8c6jhb+SMvhYTiuldQwDzhXYh
Fu7KgcxwO/XMn8aHNT1+jrQx9sGQWNT5XoNWyIZZgefLQ2zB+CUTDKw/EIB/9KdJ/s/rmWqOjmd/
di0GlesIi4ZQL/sSWC+lJKDNazVNB69zD0/xl1YhmLTb0ukEV27qEAaFmQITnb+KWodvgholiOrJ
uB9WdJTWyQMSoKe8Ca+NqpwXC0k+RDscN0RLiZJ9Nq5dcm5sNxVjMeKKNuG1A1SpZoXCknWz8cKq
Vo7dJ/zh3voo4PMkQtfwub2sTa4kA9qe2B5K6BymxbFqkxCqvuQWS2LZidZjKcY2Hx5pThfErPdN
8d+JyiU3mm9kaoMYH4lQ40t9NciN09BzK5cz5AZY+0bbcCO5Wa5JrqhxPOpeK70L4T+PciBcSLPX
I1j0lGv+kpxgM6LWnXXxChio0/YKq3zdYCo+CTcyxSyH5Dpa+va52vdaN/x+RZs7ZftVe64teXnO
gJfhCdGUvGHNn6RbeFwRSdzXLAHJTJBTFo/9PjArjwfbbRLeK0dPhCS1U6R3dRytD3+NRPQ6dKYy
zgTaNRCbSBY3B+/CLK6h+YNOuznl7EQ00zoG6xZDhFaebKMZbKPxH/I1d4aLTrQl2ulZp0Jwhv0b
Kai7IfE0LkyJ/fCFuaY8BBKVfjsJlY7T/nIjC9IfuouptsdkOpc9g3GkwKIDNz4ABcBW6c283oSz
yvK0e2Z6OL4ttz08JcuVyPZDxnr3sGWX8JC0flh7OUrULEgosr79YxYFupskrYmslii8PJvF6+HB
3ryxKunDndGDOOGzl3FeiKaRe/4SMN199b6F19nAYUtED7WB2r8PQeTDmtc5mxtqPHyGpdI87uJ/
pKOM7nTtJWJEQ8xE/OtHrmsf1sbpIVgbb4rRUMCelpOuVPer3/FlKpi687Fi8FOUIkZsiI7/CHzI
DgwAs7UvSBQyz6MjlTclcqzns3cB42ur7Bmrxu6NweIVKMmmQcvfs/SnySX0PtDZ6KbwLuLOKe83
V4+rP1XsY3SKRwuKJfUy0UAgAU52htkhjKt+TGF2Wfqk4lvGJDLNZSSaPXv3bunkWibzrlyxDtmk
114fAy2vAAHh3fO8M1ove07g0mTHSZB0z4ELJMp0LFiC5u4tqcO0P9MTDzXyJ/cFXGqnhpXoVwib
+qmLaTs36FjeutoEmZq9H+yi3Uatanh/mNjsIEXqYlwKAnhzAJ0R2sYie113itRQ03a8Zm5KP/Ud
V+jhZH+Ob9myAiM1kM0XprHokJ7Wda+wuCfGgk6wIMJoLIGDPiUxKonYLsu9kZWkFsCniH8j8Fbj
JmN424vHBfbBX2M0NW1Nweg/NHGkmxtE7D/oFbgm5Ps2CB6kAUeI9+j3eEJh75UJ8bTJeI57fmqm
WZBD3DvjN2RZBMmYsTTqyUdEFzUK7xMyK8znF8iZGsdPgDNYlccEsFlMOyeqxOLu1dtoBlkYEdtj
uCPvATyddKr4c1Tcz/n/SFE8lBFrH/KgzdH2MyWL672S4VlNEwhVqstedQK5c4l8T1mJ/5T4Soqs
1HYHpHfmD5qrmFbIKYfKCJeVyDQdapxhETdxmHOgGrTw3S3hynr1VYtqY28MKHzd7NxSQPzeDJie
ZtAP2bS6x6NSCd0WuCcDAA0VwaevBsn8jkdxEy+wt5cllkxU7MHYKVIsYUbohFinK6w/ZmzYUdDS
DYdqkHWGaAQo01dvszTsQObfjBufY9kXMUFOKAHyC2rTizw+rNYfomUzL+73dCVvcYjbJ40qM3+x
2t8G1IyPI5AodtMWRHx05dTEiLT1/idT4/f2sp216qBcPs4Ub76nVJKOgJfayWXSG4mLYofAyp5e
EZWflfAwWvchbSS4rOoZ2BtCV4pEt5PBuzNIPStvjtMwF5J/fn7vLQGAp7iZrUnOjri4EXQnQYne
0GoMH7ZfqckCsnLHMV3tdeK/kKYb32oOtckKh2kTrs1XtJG9UsG3qb0zWfj2Q6iIiS5gtxa2YPL3
ic9G3Ih8DuZR3MoZyfwkeLDY0tbZuxdqV2yOEPzJdbIuJCtWAEXpPcGe+Ox8w4kRYdIVZ34Q9lHk
Tk5bQwS7lMwz/B1dFz2tbKpbtxKiPJ0gwUquSsvUSiG7nEzuIup+UCtsAJ1tzmqH9T1lkAcZu+28
a5g1gNWYXiiwlsFCzQB3sQOO9oHteXEhKL1P/6xUoQd7Y6wh5r+gG65/3tzGQMmOgrksGJ4ig7og
g5dV7xfJDyfSkMZarl6CG+Bg2QDg6uAP0h6VPHcUAgrsDHbES3ORwUFJslCc7d2F26G0ScEjTOZV
PK5ORkAPspDcujENYI5J93WQuhVgWHVXtXUQgFNrWElmsq9FudTAA67IlcZ48Pi8JYr/AFm0jWhY
6OS8WiiWG5eX5IVjuAAC809K0flsHM0FA4/0ZOURneTqbQoQXeObllZKPge2zoIrXah0eiUysvaD
qQNGPODo9311jGS6TIbcsX+re3IOq4p+L+kUfqqaOSs9xbQjXY+nIPf9SoaV0tvX8SWz2c22YMRy
9B9xRWYvH71z3Nn9eLw6QV3/OE5FB0CsdDai0QB8QHRa1MaXDADqJqy1/WtLAq0fT5WTM0zQjVwi
ddLcgssUCdRZE7kX43rqAMxtiSjoNLGk/EDTcvCW/Wu4YVKBqKPOOTfmD87rRPGYHLnpWtkjpvWB
l4TLEGpt1A8CdfJg8icSXb1RdZxkyl+H1vQTj9vkqdKbbaYKA222QP6/6/FkYoxFQiTkZb82GYai
XSku6BeyF8rrWLNn938owu+WLbhGe1n2UCNT4v7Zq4qupSz8Yu12EVp45bmrMysqV1+gxN577uzK
c+aeMZLbCHLm4L86cAPPh/HwQI7160pvlfqOcvOne8zf1t5T3mYAf7MTmEGxOdX3A5J040Qy6SKK
+NoBVIWYbEgvLF+DZDHI5CCzRNEQ6XYnlp2/gvhaL6Cmp5V/d8qK7jdxZRz8/t8kjnTHOnfvWaT8
j7kYAmQFC0ZYbcZey1z4opnkfyK2KwGKS3Y4KnAyZZRP0ww9uTja1/pno/M8iEzQ1Cp5u8SDQ+ko
w5c9JGy8VLIEAK9d7xuBh787hjkICu0dazA1XNLWWWbtg8KBqcQg3vykVh0UTuMPr6gyzLDHhQyC
wzwuJP9Sd7A7pz9aj3/fytVVb9Tz6NzakQNHBrhopTYQrL37q6saXNo0HzPMowgnvHlT5dvdDMTo
BExKOU1hpQtj/9MgY+AVzZk9/R5tVkcWj0JVhhsmdNlPIxpMD0JHbkLPDfG3hV7+AvFB/E9vM2xQ
Phq8Ak2r2agrla57PovWOH+Yx5YZXTgLPICjWxNss8w+6IY5ZMMZWpV7vurJ2ThW/9Pa3LyEMiUY
HJypaHU6RUqZu0L75RG8yDZ6nspQw1tSQdGBkyVozHT6nkZY3D7KFEopb5iDURQHFBoE7m3Y0VeL
M8qwYmlxTx7bBfGGRVH5WUGwAyBiNvgnw3bxHPWnZ+gtPPT++MofTX4vIsSTquXPD1QGzSk3RCeK
guPj1htw5kQDOwd88VGWmul4ddgOxZdwZJlVCR9Qi07qHInRe1TWdcW6JI0bosTPk5mFh9YLFI2y
HfeVlvkuYA5qxJWKBdyP7fhyhdEJERMiOltB+dSTCgc1kfv3kZcEd/GtwjnO77U6kndfMpPQcy6x
WUEs0ZSuPswWcWrFTue7XpZnXliTujLHdV7kmiBepwggOMD80bKrsf7zL3ucP8oeHMyBWftmju1C
6kLOY9Eedm/MPaukvkJtTk8XtMd76cPwzdsv75zfHtDivX63zqaQ5HoJyt039FDWtd507ZKItBrE
VP/dnf6u/zoAKj1tei/kYGXVS0oP1KnMS/ljybEFM2Yo5RSTF5GKSXHJBVJwxeGuyP1dvcREMsmy
aIeeZ/7CJ5uL53DOUJAxFLMANTA5eSzMwfbrybsh6lSsJbTfv6I/23JRVIm4D16XwEaQbxlX9iZz
5m/dJ7INrrjDjHJ/l9Ji8ObJpi+nfOumV+myMQ2pSZhX3q/TgZfMHHzL2+7OOkBS67rssamLDaxN
xFyHrb0S0EmzWnDUjzuqTQ4R9hLszJIf2DDWwuV5cLJDedSliCqM7jQ8LYANCqLz9n78bBDoR6y2
H5olSGZ++V1q9HD7FBOA4ovocwjTMvka1cvBHU578xzZq0+Za3OXIQg0fjLTuULgK1j8c/CrAzLN
RnhVdMXIcA0NfGyQnvWqah2hOAxyOZ5fNTOUNDJJfuhkVH0ba+5Bodx4HYlA3y2AESlnJMGXDBNM
HhAw/z/DPsevj4FfE4VcihxILCZwBhCYkZKCDBJYJH8qi61ZM67DbN0gJTiExHlGp4gqmeKt1qlJ
+hbamngZWsqVd4Y2kkV4KeLJaMUID5jAIwuwLAj0DKcH7xq7qaUgeuyy0yEUvMnZVrBq7bzTwJuB
X+jZEcDOQF57qMD1UlddYkxkZB1LgN0JJHjZsJaPccimHCXrsk7KrpCm4Wi+T12o+vhWXouIYkLU
KHHkB17OOwqFGMSNSZcARjffmKBnA+26RhkQF84wX+yeaFME/3MZccCITzUEO0D6TarzwrPGONBS
amsbDdw/tVZgStVHkuG29MklwucbfP55e+8WJ19CKvuPe3X1cg8Kwk0KQ/u6jcVnp4LQAvHEvt7t
/VHFfwPYexBvWBvrOqXoM7hMVDW4fyvFNMxNn5HOTIiwGqmNaIK56a7zeVrU4sGKauEcfSFXGxc3
OfUsspBFg87eQAdmGxceqZQu2QcF072aWoX03xU+2FGLfpTx9kBss/ZikHeKa3CnDxL/dARMxfXh
lHyJl1GHKOo/+TfTh2WuU0LUJRyAvL+7gMx0XATC18pool8I40Vir6REwhmdy0rYZu8JDLChT+Vs
iaPDuB9UCVV9/EMyDLcZ+Zhmf6hXYs8WTinsJloYFtVFYnK18e6gxhO52R+3xfY+mYOifuZmk6sa
wN3u5fK0Vs7uhFrPHJNoEtuvi0KN8vTbABS8YKS/6AUljedWL9tUwi1mV9BtZWLcVatS5kISozX/
JAbD7teT63FjuMztTq8rpi4xnXCZdUChJm04ShStJj1zkFc9sKGXdmMDQ1FCvNP2Y7vj+x/ZqfUj
KPLXhzktbAqT0rSIsNeD1um3Q5vSkc+PLCsWSDiflWdmSw7MVUt4PKrY9At37E6BZq/HIV15m+pF
NNdLsX7yNDHL/LPAX9xm4aMRK9AULvEErCiU+uI22PriCqeBezy6lLC8/mbgJatyyoPyrhW6XOmf
MzgCltVZ0VVx0V74vPUegIzAEzzgnYC1EkCT4entNBBYbUDTohfqSBxparIRO8oKCOI2MlRHOhRg
t5h6V1PSoM4HDhGuGJof1ikI7DX4A4eFlfrWxa7rOqXRpFCrr2GSN8vDjhAva1xyyqBOSyy62U0O
g0LHTeYZBx72XlS+7+UHc+6G7vbJVXau4AMCvUMhlg6rK84OHUax/uBUAZNYGptpbqzb8AFOqx5R
Z8GHW02Z0YdWxWpZ600hLV+wdF2ywIkIN+XHemF9gnpYb54tr+9+LpX88/oKKlLKu+JrcPd4LJZ7
1NlP5iXYkzIJjaJQZbcDtmlFoatjFY2Ifabz/rW21Z0R+sBgmwzWhjGunCM6rIWIPvVb7HlQsabY
+wxJWHvRpsAB436AR0W15BXhPqagZbSbpxNtdHIiOvFG2d2/jVEle+si8+P2eM7hIvharXWOEfND
Z46T/lnXAXBeAaIlMr/OrjVXzpafDHZOUxvfyWsaRVMZ8U6DxbUJB7/cNPRpcJ4meeXDy9v6MIAu
7JyY8zS0KPrdjO28xEtqo5tB5lkx+BDd9tFdfOCdIr4dPqSJDNDVyAVIDJ0zTeXOTf/G2sccdcxI
X655SB0SC1dDJo4YbNOxLIAWXf9mDHmzQpHRIsDDlIOz7D6Kz+XcLPHl3deb/QUPwNuYCQWvgdCo
eVmB/k71o4wOs9Fda71VtalU6VIQE7MiQ0JP2nmnCpmAhvTqejNdc1ThITAff85wV4shiqcr+BGT
h5howlhNoJRiFIQfjlcK8paGRafJJhLhvQZru1GLKjeAZ7X5KeB+reMZOPEHbq9zRKGq3bWKIwEn
xZ5DCaTRnyBs3lgBltVrQ/VUR4nnRAtAMa/b0E0ASPJLzVb+FGKZ9kUU8h4Qfark22u0k6kTG28N
X6PIpwPN/+PxsNjeXJOiuRi6kb8wixd4rxwBfQdjNUoz4blWZelSrgQ+LnC+rNcNr/MtQscRZC7q
AwabC5pXnDJTnwuN1o4MPMepHzga6A70qXMcv0g0PAZlxuT4Jt5f/ISJLiyOodkRMnJRL5Ghol0V
mXukdW7pBnsz8o8pNetfXlQeS6f1sh0lP5em5L1H8FVz8td1kco6gdQ0VunY17Tfp7n5Kwc9FN1q
5N1dob4jDf1TqPtEsSQ2u/wsbDtgdBfOrKx4YxSBijFqu+YxUK7fTWpvOHM3nT7ltnIUK69mIGhG
X9soqMaMNcni8x8+xXyw6rmxGvdeWuxn3aejt+lNl1i6vg5qZ3H7QqIbFbAt4yaxqX/TqRt2TuIf
1t9hT093I3H+j8iMz8aNFqJQbk+ycWia1VVeo6wnqdinvyInapcIOS0BVCDXmJ6naDPNVX/Ow4Ab
WIPj/pQDqnD8QsyVPUDZyreUv79jMvK6ZENySGUWHx5MmFtVta2AKsMp+pekHvyGmPPgkG5cMrbr
vTdaWFx5hi4bXqPmbnskofxzk6TMt3hEI2QV6r2q44VWKEue6WEcOe/EOlwxY7nKnKHXocNs/w66
Z90oDAwrZBWAFKpPqWBxGafToZzb6k9CShXsIpkTUK86EO66yOkO32+zuN61uihvFW8YjV9Hd9U2
sWQVNBJbMtCCWbIi0gF6u3ay8qSdzPWvjrVsbH/zHwL0caPuVWl1afFDguZv2/xgAcvyRYgroFaW
BmDhtgMjNiHhtnfRf7+Vh/VKi1+mxOrz4BxqrfE1/B4vOypkGmxIBPnRK3uK9/2E1Hzzzj//1ipd
mtdmfWThXsISFOh1++AgbrkSWpshc+dCeHKV7ETnRUcM57tSqa0Ij85aSBulmGkyxiQJOu1kq71k
CzIP0adSRSN/elqWSUGmvSRe8zWQNujN3PA9Np0OaPW6wgVU8CktMeYvk5D1EDZjy3gjeL+Erh4m
GusUXMc3vevf8A5k0i1IUXCCZW9fUqtane/KgvG8c9vuP6XoxvQRQLHMtDdcFwb+F1IGHeZ1xNi4
20kR3XnUil0lHhLUA5c370+H6MfoyrknbMEgOKUrUxmtr8oVKS5R6DV/bZVRGNZ8H+vQm/3GFRok
/NqsIT4StFpOr36G/77W4PZG+d+997HUsokl+FqgSB37aHXX0RndtM++849kCvEKf6IduUvPtR+f
EppxnIndEgoSoFP3sslLRItA3bfWtrkUXcUkN2WqWfFMlK+pwQfx0kRfHvCgIUKHnGXHYk/Z1+Vl
NF/57hFDR8PxJvpX4RCDfl8P7UyN68HDvRR/rVMCKq/MltRenvE6k/V+6Cx41FDEyXVMhvSbovSS
zdipQkLznMHfK+rCB+OkVx7eLdwZybvtpirZHgaRNxzLXtIMa71CqbggSLsFunJsGQD5ww3U+nFo
l+w0gxH7TxwRwHZGzRFs0NYLHC5NPy9xwZA3u72dnshgSWVU6iAE5J0L+/k11frF/VRUSkD7nGbc
EF/Z5MMl2wb7nWjbdo3VyLud7xwOw/Oc4oPc1xjsXF9bqX98H/HivcnotGN7LiNyXq5uxW5gr2JD
RroCfZwizE9LQQs+4G+4RP3Dhosmkp6wL8/JQpkUQX6WlWlyuTjDMq5MgQv5dn13smEfjRJ0uawI
WLw1/NIL1Ygxg76RYYqWgd98K+muB/MSBf5kzmHBJVPfNof9y/0qWLlzIbrAhI0rnogqq997SV9r
iO1mom1W/OEJWxDCWhcf1/ikiUEEZ5IEgGWnEcsqwAYg4DOunXbJjFzOc2cr0BBq1dR429bbSpYw
RpmFegDomg0jGNatXC0WnhW0bX4e4+u5IOyE3DRXmaixntXoa3GWXre78RYJvKORKBvb2LRQ1Ipk
n9UclKrWIEAW7JFG7M51m3gKSK2e0vtUucyRnvXY/mfPkaPyTGZC437dmfD2FwQudQ+rqVwo8Yzp
cpmCKlr26PhAVHaxWbxPIEuHaP/bItnqucx+Fk7MedwEc5xr+RmDsJcZmz/pCXaLYHyTDOdy2NWi
jHEQ+cJKnyXYxyWDOpNFD5QuJZuJabkBrXZkhS5u7OkDwfB+fZPvnzx65iX7I5BKCaM1r5xGW/of
rojDnZ887+XQaJuKk98VlJQQgyObnwelI/3/hpstCi7HPpMPNjiJ4z8FXAop9jq3hrZIDy33Z8vU
EnDvW++DhZNI3u23u0kmzBsZzCxG/3VHKTDs+0j+ZGcO+UOeVjySOaDCNX4UoQx/BGSlqe0QLM3X
UQYKAhquSqopLvKrJG1nuUPe1LBgYfgYQKlx0eGEMxumMqi26FZXWl8BirXhacGz0rHZWzOPWYji
E/IlcmkwTwnkLoUh/bJ4px9cfi76Li6z+Pl9bqVgkUdCUZZCJeKQj+n7UuzQSbDk5rHH9VgbrTEc
HBFoM1ZXiijBgcjBwky/4iZWmrCgKnQ72GsrR8ad26XcqMskYsB9UeCEJF+2OoOLrP/+T0XAYi1e
YcHFxc1HQX4S9rkeNe/O5hXXOZs7bOJWaS1c4qujIXzbu8pexwk7i2qDsTJcbcrCDex8KiqZaa5V
HBEse3Q5FLOh3FZ2I0DgSfXGwLf5Cx5wvVnyFBpWuzTt1u3D/ywBpk/kQ5wayeNCa5fytqPWx4y6
6i06SkVTpreP/m/f1ooqPA6z7NH+vfKaHDFMZFV/P5z6YOiHlVaynXeZqmVTcAO2RBkrSbsZxmTy
QzCQqfsyFnG7raQzQkJLzYwA7YNi1rJnnDBpHD/AVKm3INiwA9x5VD3O4bRt5HKKk2scDReZLnvw
cRjpfLG4DDsr8NevVjW9xpeDFkYasIU8+BtwolBn5qnm1GcSDmEyShjRGQS41gPBet7N0qa0M8Ru
99JZ+4TEOCl/crrATzAl+dg+Ds6K14uTcvFzyFyjxVaie/POSH1maZGLrA80CxjPm2aUJz/ueSmv
rn55UxXUwj1KqrpOW9TL0VTfB9Gl+5qJZJn7y9fRuSldUOBX19LhqD7BUd35vjsXnajs5S5Wkskt
oICu6KRnrLsurzzbUqEvkXXXCVpeqOb5psensd+QCLl5EufuHfLUnCOd/kZ2sq22D2o9mhfKbBPv
qo8wHtdUKHF+/NCMDVmw629lRot//JAJYth0Vn/3o/Wd7pcO9IYasfy2af+Ry7YsissXia87hAAY
yIU/ia3d+GAh+LajMjaOx3cyIfECEsw0eeqy2J3TN8uWp8BN0H3n2b5TomUQxqRia5Hg4TzKqNig
xwfG4+rm18BqCXgOCtx3sShYxvXxAJm3Asswr2ogbytT18mvAkOFfiYuGND1oXjeahZstfyvWpmG
je+ri/1LfsQYyuSg0vUiKrHo+LFf5LI+Ayz/Ezpd6OYI92yglzSlfPg6tnvtvepET9aGNhCl7lvN
9AIgalIpo08SC7QC8gYkrL/pPYBYNQ125S+dA4fUDHF3buGvVHPWTdItC1t0OBvJdP/nFDhEFgwT
alUY7jtbWH+kYR8GVgi0VHkm2nhCK401drIv8HrZkzcBXo4vnaJNwYC/iepyEfatDU1LK8ext6E7
I/PsHYzrIAhB3Sb0DuFwOPJPnyZKl6GeM38dnoXDSITAyXun1YiLqBM6I8pRfBmLafewX9f3R+yU
2oap66ElA1TQQtVxUpfiBbmznN2Oum0zsfwcngHZvSuks4tmRTdpk+4Evh4STRTO4A6QDB7yztWT
4fgxfEYRZx0FcjiFlwelN/0n5YTNHvrmT32K5sXTpK3OHjls4/zCaSm3lvbT/pZdsQtriTCFnvSn
+SDz3jhYeTfqq037qA2AfvWg8Uy7Xgz9YR21yeQeMnnfEGP0OZAPXArteZ84PvuR4MqhrMQnZEEJ
VGwhpU5ZJoueM7VjpVVdYf/TGjQlcKXmm//xlom/mkPQ4OmjHM4SBTkVftaj/TCquntpJG4EOf16
Vgo1UfrT1COHnKPzmgmAyDNmrZ4YY4i815O79aFVn96+JNZFwPlHzsu6m5T48gM794EOLlotCQad
qUtI2pcX8wwm69GuWqBjsuXqJy6qXXq5uLyfNyLvZLRGxMjlpdX2Y2iRQdhsD8DsM/b1eGDjrul3
PdBSzj31vH1onKipJ3f9heEEutkTez6ogt7/Lew26W8Ix7x5iGZO50te63+NVwnP6DGocQvO9Y2P
sLiWZSwBYS9E/IeZE0vAboR3x33OldXjs+uvqBtDa9RGa0aoGKukySmNQIj1GetsKuH9Ld1VfNQb
nD+CI587ei47YjCSxlQoRF3pt8b/l9yw0q012c6S2PuhoulZholQmnOfFFqgemM/SZbDXrywkRKy
VA9VhFaiST13EZzw4rm75dQNUthy7tYxH/9nCBAOQHFf2XjIt1peyIdSaA0/08u+OFFyKfl0suuo
+4WsuPfeio4xQQrp1Guqhlz18Tt1MW/kZwnMIZngYSIfn/2td8uLEk8MD7npv69V2kK6qrYvcmwo
CbgVNCwf+8T0lCp7jDgUZEkTDCI6Wh9Kf0YPNecIaaBGHU3xRkqXavlhXjS3BlH8WoJQkTyPU7ns
5Nv0JOsAfe49XZvprr0FqTYGaCX9kV7+m6nZ5ZNK5D4GZVmfpAM7uNvXJ80xTSUBdpbVMSiCYKnx
ULBs796a494ldDa7rwTaK38xTd3UNfcbou4onwMDI1Fk30fNpjyhegmv2TZWMmPfjcF+pzzBybi1
yNk7sgXvWIghtTHQxIcO9R3ZuwJFKDjRWXz0Ixnn1mPqalFKMyyTmNBWqgDhBG01e6c45q23E4/5
RBqw6L09316ZQrNwpGM93wSPgXXBDzv2sQ8p5mJvrmG6xtKOZ5kmUfsenKyzQfY4HIPq5pmR5vEo
RfN1XdgZQ8/3tyXlWYWZsb7RNya1wYEV0kCTXom8bWlcQ7mVDcuwHSBw87mMb8Ac1lDge/3wITsQ
kn1EyRHsJPELJB2KUTqo4VFWYDuh8dZ9ymqY/xRaRe8R2LYBypRhxh03hsPGS2+UK7IkXaERCjwU
oshWqK90hEAAND6qfvG9tKlkgn+S0P8hSxsiu+R9+V2Jve48YsefdAJZ3gtZvQ7NcCp8qXtW021v
fjoX2ZfAoewTngKLNpCa7POjBpax8FLJDRCkmmQDhj/qVM3tN8W8IsbYBD1CJBhQPt8sg/dZwZbF
ISyfCXO5UNcGavCJpxmUaAPcYKz+2NwRosA1e2UPyostO3pcvZyu99M/bQsWi2R0GiwZhvbHg4l0
AmGpI0uCuyxlQOFjpWBFBR8A5g9LS5+xmSHLngxNbP8b7dhnkMhbS9zQFQGNTQdVwodpbdWzp/Nh
wQXjuzAe7Wbgad3BB+VyGct8ThwQBFCjA3iR4v66U/WYuIGJebCvHXsWxvJv0i5VJnkaGWzkw8Un
TGJbg8FBo/WRBmb0um3nYKY6aOw3HfYWallmE7zPGrJ2nrAHdLODYY6HAp/6oOmKiIl8OW2RbD+9
weorR4AHA7m8XjDnLngittWiBwXU+m750d/SbL5KllvnJo0nMKKJMU8qk+bEC3saq54UG9M7Ak7A
avaGN0/ngs4lHarZ6Kw4cUMZG9DhW1hnhqSARXjsnV2S5/BXLvELyn4BIlFOE08/sBWgKAS/+LvB
BmIXiLk0ZaZWpKqXM/zZOQvcb7wAWcd+bLCcWRVNwY0AKyeJjvDiADF/tW2RH4dewMBqKIG2+MRa
4KksSBnww62ZSl2ignaYF2m/DfSvhMql7xntMXRXv+Y2b7i0OyEbDx7rhJ9iHTBKYLCDwkWPh0IK
b4+pqNT6u2NG1wqPXQu5SCvwIFCtpOYXraJuN0skucheC9uLfLBD7WVYbxthYSRTdTIspslOwtoA
qfm6qcoq2ttaRX14sZ8V470+Q7JBdzg4jQ+N1pKTKOSWBfhffBD7kWnB7rw/EpfZvopdyzKk/ltt
AN04+Rj+gy8QaoLqUFc7bJGtIXqMyIVpfU1ODZUuJPXz5+yv+9xLlUYQ8OgUmuFYyHbRwl29OrHK
7B9oxpnHT2D2e9RawoozrTvRqn7Oorybnv4YSHqKgEgMhDO4IUCmDpQBk7PXEN/i512g0T02QusW
35iiLHEd5iFobH33G4GUeIvuxiXIE0C2r3KJkSCMRF5ZOL9cqMkcHgPdiSTdsdLl0nkwojVpadUZ
0TyKpPpyXrip+B5jYFHep9nSed4XPSqFoNzyDV8wXHTToVEKm1+RDBv8I0Z+8L060+TOisJNY9bT
+HBvswIukjcKBs6EEJcKApAfmnJ9ZQ6egSaAG783M53w9f54VKD4H8Z9kAdlJlQa6d7T63GvVRay
FS3K8csgSphbaTz7M2KVtLrrh3qAyVy5dgTPToQ38td7tdhC9Mx+xl5HVOI9kxFHoPuGYTt78veq
NrS+cJz6uZRdApNqPx9nJMT1JrgvaEeJ4UAhNbOWKDaxbmkzMb8UN8uahJBjiTG63XH5u9N/CwCl
hbHdxUccW2aj2UGxNxDLDyML/FdpBwpv0Jzh8MnOGO8I0N5N3xUKsS6c8MXx39CtieK6ibFhxrIo
A4b6WTeCOJ5t3v/djTIBhZb9tsMD/dRt/dNllUo3bWWTwpouqSGaEadK5gBObQ6OVU0WbeTt1JOG
iMo8HzsLppLp56ZRcMB5co8NJV1ZEn/gTM06Hrdi0CvuQ1VJk5V0Sr72LE9qRJFjKLanDGq49Jsh
zZXYILo4zTAk51xPvUDqsOBc90MA/L0ljjf9kckMxcJomeiqpJ2t9SusM3nAYdgbLP6cQfQBSp29
DFmyPF5kzfwg36xZNJDkOPlw85C6qqtIC1r+Swe/7wVlIUAebEEXtT2y+Sg8QEMvZe1zX10biG7f
CoER0uMHNNmvvJ+Wo2//ZXYi7AFAooo0T6oxACyea6buUPjiLgz2wUOtZUH4E4RkP5BkCPvcFdcx
jQt8Uok/YJ2O53jMh37NpKFWsVB1p4eTTBdIQWMfvJKom5YE/lI9RMve4TFh/No+2KyisqPW5Rm1
ztC/Fj1OUDk/YvpceaPj0HFr+d88HM848fUg18QOjYDlJHBS02jAv5dnTq/MCtZtjQngwz3xw15U
rouwIhvoiXKHZfmazcqoRduXodCYMcW7EIa1EgAm/Jvnn1UEkfWk3tfmEflGjEDOR27cmOJKnduv
7X2Tsj0hsVJSHPUzC1wLI7bnUi88Yg8JfTjW0odeO5RCVFcOlIyc07CvryjOKHDzsfC7Xjjz5KEn
MZ+dHWcj0pp5Zc3M/vc5Z33jPbCoxd+LjlBenlEPCaEJa5FsQ3N1E29jJV/rnvm5w1nesCbf8DPG
Q28iK7REeuoG21Wt7IBEDp6CjNPy51+5sP3yPbMbO7aegVqw91zIqaEhj7mwTyG9Qtpp1n3rKDdx
B9OJRPIC9Vl3tBZm899avqbfxr5uQdw/yTkKpksPMiYV34DLh6wqVfLD0SMuoa+S+r0eJwmL3g/1
bbQJHF/2Klh6TQyitfIV1MnJhPLcE83j8TpD3YbFPtMwyitbMMnY9CABQ+drw04MNBtFg4DCWRMr
TmARdTLFfQ6n8Eo8Yt7B/fd4OGK7Xd+6J+DY+LCCaZF5lmYgwPyid0LTwvqkjoJFAZjfhrkBJxQg
1MTvxOc3JAfaruLnd4SElXcPnwRkZfDMYX+kKIW3gHTKSfFIl3IKDEEtOTrsfDoiu8oyOjK/fYV1
t5SWA5pbGdA/OTz8baLD6vhMOgFx3ilpRQO1ok1ByF0dEPh+DggaLvKO6t/rSrOofKrGNvo5ZU2B
2PclgX/J6p+RP/hgMBSzD+4/2eDq0v08+lf1eq9xwQdNNMpmvgCFguIKNafqCPaEN1OFSXHgN6H6
OpUm/X7r4He0ZPgUgg2KiMLRxp3LsO4ZMvRx5dJrZG2VIamiFx8v6OST7kz7DXunE3dBrc/mq1Fa
6jn3H3XkHf+qmMs24XsSgAF3YdkQHhCl1fTuwB8agl25ZPOAjLqwhme4boRpuhhvuNOVDZQ5s3Jj
XBtpjgVbeiJ+XIZkcelIcOq3AdjWKA586MgTxVkMwcfbe3AnAHHpItX++4eKOXgdmgqnrWxi0j+y
8GTIJ5sZnhvZaI+1emCy/JBm0QpvN9N5LR4a1BpdhcVWVnswuIwvwLft41utBtoQq1YCXyMsEQfb
TAdbLrn2T0KZbpqyQQmziyXsOUkBL4fTHX1Bru4f5qT0Yt/0iY/KfeStlnPfAW33xiUAjOeZr4oI
K2iUT4VUNwCRjFwyEKTDvIgbXx4OFVSAZv5XNF++p4ZKAEinkA+B9zZeJslMYL0vRPsjtZuDtZN0
P8MYd3dZivL4qAKSlD4vTfquBhRi+3goepHj9ORvWAJ6YeAzHgZ5JspbgrGy3cadXOAdW7gbcCFe
IKrDba4cgEkc2eyANuEnqYuNqeQtmoFlVmSp5s8JTYXLpb2vJOHO6dvV+k7eDlzJ0aFCTfrFXB5I
oJK1P0IkmULXEWrqiSwnrBiKBfbkSdSh0UF8llrjniWEKROTk96FSmWgr9s4TB5iRLs3TyZGwPy9
SJYKoYo0ibwZaEu9+2UAbFRpHIpM045YywP2y1RZWG4+BnORA01xa+036TbJASFcK6hfJxpAbqmj
axFDhU86D/+vqZUe+4DY2xwHjkd5GWE9IHLP1s9H7j0ttCjyw787JNpFb1NPvzP7qAb7+eEwkVeU
mdX6JJD6gxNGiORVbfffGD37HITnxzjJrRoHiROpf57F0LikGAg10/0Dv0s2ufIEwyzdIyt/Z09T
TgZeeitLz+VftYmdjeIit1lAhj8poHVMwvi2Nh7XgWPPfCS21yyCVqSRdfNRiBu1m/neP06/zAob
dDGdbWmdbMQw7yigXeEa65pSoG0soeLBCWI9Ifd8VnrXbG/SJDS9p9OiWwzF6DDmO/HL31a/YvHX
F2SRyLRLdTaB7kitHeZtCk/kSwJ0ssWRQRaF+aOoQgVQvz6GAzdergzilHjwQZ736t6nZ+X6oAlk
izBtpCK/6EKLVgEq79ZUyX0gSLxmD34nuF0ztAboIb8lddMdr6JS/PDLjB8254ZgJCgsdYBTZRUT
mQUY/MYrk9L22m3Awj7ypI/mZqDfBZ+Xbwn4WfN2oP7eDyVg6oaU3NLvu91YKUnxgEidNNAchpKh
fqOdXWvFbTOvr2hbskqTurkE8KWaLfhPe9d5+glgdcIYIGxf7LrqhiYq4kPQLuHhZfYLaOYt0T7m
QbswrwV1j+V/Xup78bzBBs1CsVkX7GQFIXVoitTRJWxVYXHYx8d7RW/PkZyzhNlagbvCmHgm04+B
RpmzPlwWlNgF+XyPs4CwqZYYFx6ydRGJh1fGtzz8Twdj4crQChrnHjdd936MOKcABEWusNf03R9J
rHzrDoevGOxvcd/xgCAtqbmTOvJtz2SYIV5RTl+kZElte68oJkMFy/X36ZJuYXN8R8PA0rlwD2z7
eM32teG+tdYQVstn3TAS8r143cMF8l3qQz7fuQ69Pt2mAms0h7AKyCUxRyhvzmWPoExr+QIQe88H
Se2cI563iurGfB6dfgVCoWUgsKTbDLBE3w/V8jd5eGm0Xj/NtNixYj3GqlFaEAGwtpTTl2Yjt5C5
d0eJ5Amzfyj8oxw9umTNHESzM35bZlHWSquVFgd7p7QvHeJ9JfM8hoKJtktuuN3rb7L1znHJmnA8
NBktZOEsrGSJjXRfMek80i3bWb3Nbif3CVU4pM163C6sd7KbaGQLj9vFUo8PaYnfTeY45rdu+nn0
9gaEgEeioQZX+R7urF0Ss0i1rFodER2aXmLoQ675sjPPOJbio63nQ4nICN3r0xL2wvDvSYBS8MzD
7LLtXlcXWOzTIBTOHLrplz10FcfNpUltaez7DQ4C93+Q8FxJUtm8YbZtLqNNfj44bmDv7dcBFTfT
B7MAhyDl5eC4AR13sD+KBqREDGnIrdnONa3isuupGTo4A64B2AhxTguRU8nuPyd0A5466rRB6Lyy
Uz96eR6uGAW+uoa+chTdXAe/j5CB+kf+GDnMvSHVKsJ0bnTJZOPjTTkIQjoJuGS6BFO8Iptnyt7/
/K0ypyv21L5T7t8904yIbR5aiq/sh5d9MVt0I5GbLOJto+4kLwLmGFxZ8nB+wEF/7ENZ/R5mn3B9
YSTR8W1Wh7INGWgZWQgLTbjfFz2RX0ArLTZV1Ip5quWKMwSnsf+Y/jxtydYQAQ8ikojWjCghB8fR
UJZUvYVzq21DFm0a8v/AAX0whnz3FT2uWAdG5YFjp/E3IJDI4bOIyqLVyYHiNPzt1Ka/jsdPbogj
XIANE9euM2LQMkcOOUyFnlhmUgq1JBR+2t2JGboN7d/CBJQ9VfzC03j4XJdiV1yV0voRkj0XOIEl
RrA65EeSwDiU2gubMJRKfod5nMLqLHp357OJ1hcZJ3nGzTI593hwg8tUCUwTb2dhnsX5xN968wXq
C8LslemgTqQYAuYwlQaUa3VqBTpaX3yjC7/+8jCtxHJ5U/96zeMhxG7N9fCQpmGIjCFTsrwfNdX6
omUPd+rNa1VubSpHu28TbSjT5qTJzPKeT1xmPavfqBtJ1+wEpffy3w7Fi21gqP3xcGV6YO+C/KVv
lwofgZ9okbeYc2pRLs23eZlYW/uQ/MVJ6OY/zd7iCGU9wYaeSLQKieB0WV/7goPbfOWOhLriah4I
0r7lwqYsIt3CvUSnfeSy6S+oCW6ujNhqv63YXlXQhuP9RZxlRVvvcYF463YvejvnSXv/8gC6AOXt
vxH2qcZTqiE5ffs0kOz37PmsmRVs9a7mjtRKue19azh5chJ0DVreISMAr4DphWlEXvlNkuhbuIgP
cGFHOKLH0zNhsIG8B4SOJwf4SEpuZ1481uL5352FsdO7rRJl0wCcRPUXXll03lpCceb4CbwNjIQo
77pWbaE0pv2Tc8oJW8n798ldUuGQ0TBE2gzVnBidNo/+q2d4hkCZgvNy33tmVunC1hF33q6jVInY
JwsexXgtKJVKzb4JRh8klO26tWYJZVWUtsUJVmwFYmotgM0+1lcH4EiFvfAqsAPgB2wYJCz0nHpf
LnCEOVVmmBNxSG+NU8qktMjONJ5IUe3igykH249CHH52wugyHD2P8n9UDF55C3GVHieT3TbciAt2
uIsVsFpdW0ETzcHpF+Aic+pwAQ1FwXhGhhEDjYyyG9QzZEP5SQ61zgYRjTrhC0LpilEBd+T5Gn6V
lGPZNDOyjy+dyzqEubmL7YOwZWO9ywO0rXajlueh8S9jFaJhE6CBopDAWfWASjtct3qHF7V+2XuI
PCXDuVsnS+Ft6VneDswpAt/sCqVqpmatLrvqguOxPwnuv1dMp2wSmnOEV9r3gRF6OsjbrJD9AJWi
zDoiMU+0dduVrFZjVvtOHYkDKqPj6gd7rd9QxPPnR4+F1ZCDeJPAnDgYxNgLVK+kpdFmLGbN0hMM
WjWPRcA2DlCWtJxMVAeVbw0L8MsgfhvN7BJjaiF3xTGUXyRE6sJMkbK3lR6p3URxb+s8Ch8dNXdK
ir8mhB48atLA9+WYsoufe4Bd35r2knxp5d4u40XJ75HF8FCMZtO2Egi2uv7ua85jxjmToLcISIOz
hxhxYIUvuEXpUDACPwAJl5voPCyL0REcRgW/CZnYogBni+sPiYYnIZK+8VYN7b4ePxXyoCOIeV08
/q5wqg2TQNUl2xAC90Ym6oBUVVMgTuNnIVaINMY7nvZdApg4ZD/F6wAPIj+2Ps9qTPFN9ILa6SLk
w5o+iulrDgmB0+crAn+FlxZ1csqZR5U7Ob/9vEJEMPeoe0MGDhRYmfdQcnEGSWQde0DzvjUK7i5J
74YK8tFRLB6+T5/leE7aGm78JLJDNh1cHbLcYTSCgVp+cA6byKLKb9b8+wm7ah93H38osBSanCE1
aHUjf2Ebb80hkBWa7M9QRheDc3BmRha4STCUb4z447G20mWmzO0kilwWk/jIDTJDR0bebgW9jVwu
PFsPbxbkD5Dm5iuf8alU8Socgsudonr8+xbnYgbFOPim8CXMmtZykYsrh4bQR1l3/cFi9KZU7ArC
vWQtgWaQ0wQbu2v0J5g/XrgsLcaNSuTvdObWTEtGEFYgKQ2VmwaQFAvrxP+9qhcdA/ZPoEoq2LSS
66s8J4juzwAfauVfoq8FonPg4rSBjiF4U4SREmYx5rXMRmlMhU11cHhBYixHosm2G+Min3G0hduK
jClay+Pw+WWaNBnsxkz8PuujW8ItRTAt/YCTG6S/JfcETJWu5fkipr68Zrg/r2IXj82nBakPcCFl
YDwFbxf6TNQH2UcGSAuJCjl1OZhIBLM6mqCtet3YZ/jr67Hn6YRD3JYa41CFdecPYC/i0Oh3/Qiq
J64cBFPWwEbPFzrRxO/O3WVVoEXjy/cf6UMhQBySOPZ0T9m7btVuwFqeB/EQTVOmfkaS56mvo0cM
9TSypff3NlhtnZ3lNxoXji2Wa+FeB5o3GkqKAwAx4a+BRb/DwPgiCkVlPTAa9vCQkPyvRyHktgEd
Zh6KTaq3FT88ONRo/rD6gmU8Kk+zofpQVJFkm210oGndA6g+kStcqCUwM0ExA/D8vy8n8cFcZsAc
JEVvb7XkgDFBhx7cblgVTzljE3QMhCeIWqVlj8ueiWmtfR4krl2GVZ9sPharigflLCD14wTgycn+
dQxZiIqeTnKG0aybX0tEvamDGzSXuHTbP//R9C72PU3AKKIjMK6MY9YYfKpcBxFVAT6PLmcJLhpj
EhDXjiGPIrhMys/BNhyRYkLXLFasUobOAsOM1wdbShq82rIDk8nYkqyu9/XADaQRLPjfmbfo6L3a
Tte5SlGUtNfuOEPdpd2BPsejfzkvtwMZe5r/a208F4l29G9lMbWMx7Ou9hjZgoPRJ9FcxL958NY9
AAF43E0CtsePLUCmyINS4VQCVlTOhW2W1IACfHFrxkKq4w3293EmCCmQn35H2Rx6WcNPqOzhIXOu
5hB2YFHA4lvajJRqb9Ois2FbL57Mzq5YtAXZpeweB9jkrYL4pSLfJh3UQSn1hpbE8C7er2JaOBQp
jaQDBJHGk3akf4gyoSe/z8FUAoblGQ4ENfcI70CoUZXwE9IUUPM38+Bs2iwLCejOhNCPVd+cjtnj
B7tSKbuGp82Cc+YHC8Dt5+JUPT++ErEPKGgEp44zRNsMPigqDwKKGTjoR6HZqoSf5L2IYGrBfgOc
Uth2iL5QJodIEPrhwyAlg+ApcnE0sY6g0rKWx65BBAbwIpyYGpK7FGmzdI29vG+ITSpiiJv4cTLc
XF0JOS9lahiHt4rrBk8dcxwXk7APymxwgU8PYtJ3YseDCxbPhYuxCuyGz0bwxDV9uT4MeR2olp46
f69DUhAiuD/8Djkx3uVl2VL+wv7qYbqtNM/L48EL1ve/ENh50A4bQ/Vv1BMoauhQKKA+zfM68R8r
cYG5gc3kKU+A7tuNQ06j7MdTraI0QOXS6mF0CPRp1SaF9sJ416ZuItBN4OIY4PM1Ib5BphGQqj73
KULX1+vPM4ODg3DpWQoep9Cqd7bPG859UlEz6lPpvoCdevgWUYOuNHySsJRlwaqN4/uwTlBj30cU
b9xoESv3/2Qfph10arvrMnZYSUzTs3KhcSDZklELGFYMxE31VC9x83YV/gnne9NzaH5hnjkNL6FQ
6lvGVpwLL5D2CrcAYBrQS/N8ml/CBA6or9f8tR8DbGsnazptlFT8i5cQ8vPauL2zGAO10bLC0HBn
WsMghcyvyg9MLqWN+Wvt9Hz3qbIRVaZ+TcZn9c+aibJtMufvYSr+9ChHnZ3vfBg53G4zRqyHP0Gs
GytMmVpkEQBcXr9zH0aND6sExUq8ml8GD8Yx7MPNFo18v9HLLhi/2qqY6p33HxQ88oNECKiQU0i3
4tgmMSrB4onZ0qRmKNjW77UIjDpD1VBLVQEI4mkhHkDIQfjFqT5xGGD8McMHhK6nM5a98cnUBsen
1oGHLgATJJBEoI+N4GX7IaENKqgKB/bO87/+qVwoJK3qGr6jQ+pv4+6fAFFoSWOM1/kXNGk/2s5Y
oBBhXYtEv+ejrgEVq1Zp+NLRLurZiltH31saQB8vVSVHAi02YaA6OtH68igMJPKtpOo3iz4o2BpR
v2ASkvJiXg0AE6QH4vhmuDnc6eQe+IKApaj4aQXn939JCZ+ZZ1FYiPUibfz3WfKn/7wctfPmoorv
VBlHtqj7HaHgQyCXNaxLo/A6T/nHnveyTkfXZvyuZ5oK4tbrbKWouLaZ0MCk7EVHdAXkUyMJQoWt
EeCn1kBJUw+NbhypwGes5jD6aC6WX63n/0MTBNoBh9GktHZAunXpZAgE0I+c/8KGIAOInWbE73ea
iL1fKbdN41rBjf6LzvX6Vn9oOPehhdXl8Oi7OhZ0o4xM6PiuowXC+cUUGHd74zTd3P1fu0HiEN/F
DhmdmQcF/abHmzDJLSmSJC8BApbcDDpX9FaBGe9Gq9WKxT/ApST9OoVHT8QuTRQpqrm4jjCzuYJp
KIFgUDiPrm5Y69PNfYLvqwZN3pT6CJkUJQnaBwWjyzTQQ4ZJ85M9BsaExaFNcXoyxH29S+G6V1NC
4NQ5dHp4l1LQ+rWzpbdhajclqTwl5cXW2rrpKaQSbpN/6UY9teNK7Qd7jaL1z1xBwb3BV+cYSLWU
sHrgobfNoehiuE6I+kX3cALrEqvSoBpbquuyEOZTQmF7TbxE79xe/oMafCWe0Sj9qLBa85F9OAdB
5Q84JgubCmDt5zEHiGyTA/WblZytyUzJniwfq0VjMmnedyXlJwtsa/Lh1sa++dxxHfrkHRGZt4aH
RChv6Icta1K2d8vCryZewpuX5rlbScDbz+1lyPri2kbCL62duzfxfp/+GhLU8oToOfr5b6ttKIOB
8mHtyWGexorKnRxPkEyDPK7PT+Y9HEkPqmWL5Jycg9p190zPBqXpObn1kOEUc7sMR6R22ANTRvQN
+HSk8f0cYpivvK+9vg/AaYZSL7Ko1+VJkq0Ldycn1VsIltyhCmCVrT5a+EpJF3xaBbzk2fq/8K3+
rLQQhYj+noyaisssTvFlfA5aP2E2GY6yg8KwIUalRFyhjK05HSvSxA0DahjWK0YjHDuj7yDtHJIq
Hksf5E/M1BjjWUrBWmORtCt5Om9k6zjXP9y8wun7ebkdLdDBMglXfkklKHTF20YstI7/Lu27j0Mc
i1PPNDBk8pYLMYDE3xI1nyzWIOsVuAZ8H5apmSP4TokLIy9sVhXkadKAGX6LYRUE9EG8rvJmBF9+
md+deFXREUSzneWNsEN/TOXlR6J0vdotLFSjGUduGnz64cdXnrJ7HhCI5y2ZvRv3AhRl/7WIQL/1
fSI9gLy+A0JErzjz7UYYNaoyf9l74NN0QrgDaKGiX172ELdzA4MLhxh8GaoQsuKOfABG7eulDwPL
z+XMGUWgeIovWQY3GMEgnzFVGOqg8mLGXb84L3FxKPMPrfMkzo8Mphkx7RW9MkLZvFmFbdAm0SNY
OfGc7JyLlN58EA5hN6IzuoLB7Ndshi7ow7grFrE9fPn8DjH4/gTGyTtnyQRM0PdaSvHBRFTUgCFP
pTVXyY8lFuQtNcM5uonu/FjUk/9pj43fkqW+/k+sMMRM/AkEj5+fYUaa7VSTDQeZ47qrg9XVXfce
BUcc52Roge9+O/q0GOcol9YF1g1kJRhjeVEKxBeXxAerYV12NArL1ylI+4lmxXskGzm3N75VzQaW
aeD0BOLk5WGCaI5o1lnPSJepTj0x7gZp+SRvY3BQ076sQlVzuFP06MGQGkdU7tDf4VJhcm45obLa
TY03NZ4YDbzVyN6U8D2vyKqMkkhJfoxFN1pQWN/Zp6cTazyZNHAoZfkRaOE13Nx95Nb1wW74LtGS
rrYXVaXeZOK6n8maf4ZEBPjjhoUyvsshytQWtsbC78JI5uPzagpc3AGTNyXlX2FjBMoGuuwAW1E0
qJTI1rK/FvlvcrWpAPEIG5ys5t6GGH0V6jC197JOeu9ZWeaMMLChmQe6xt8K46oZweAH4Alztxfk
HRGOkqLo3Pek5D+fCTYlWzxm4t0AjYaPx34EXWfKgcFoub8H55ZNJFEX+PMsDndPJ+p+6qg4+O61
rkjiGhBdGGWagtTR893EGQGughjhchlAE6LGDpJMaU38IoCmk7/EUrJaD5avnOTd4diqTNPOAZJ5
3A5HlkdVwywIbId6yUYwrz7qp+PagjNIAqJQzjWlHwj1+Swk0E8vAnCivvMaYrkZ8SGHyy8CH3Hk
TNvZohKfoELdQ1suL94hNuVVPQMD2jDUbk5OAKyQLEzy7N0ro9SWIPvgw4IzluudOUHUAr5w3iDp
q45cShOvp46favemQQf/K6ANH8OV50BUDKq7paKxH5o/BdMR1XBxuHMhuWG6PC90C5WjOoAcwR+P
ZPlf18alKu+30qzjy79fb2kz6RP/KMbn0/WrO8S3fbDfiBxPLxdJSSrpPuKhPUhBHQBLCjPK7+Dn
T96qfZkrPf5HsagFY2+4nctpK+G8JZDOBls6R8R8IkmDcmeEQF/IjX+f4wKAYk/wdgBCgeQUC9nz
UTZ3Xf6Q06BRRMd4wJcqWunF3palDN7q96TmfXokGcGRG7d0m07Nu64bMpsrDGj9oARMP0yMTgu9
TEE19EURrJi5tVvb9YwQa2W56m4jQ+H0NIvaL6n1krUq99CVN6G/b8FwmweM+ifxSytyzCweAdpX
hNZFIWeAUOA0ZaZBWm0l0T6U4fZJH52vsboByyPFEThNFhpptIuLyZtBhjtsN375IN4X/xUnmtos
F9sGh6U41AHP6gp0UK8unMyW5kV0D65q5GjQ0FYYNAvmtUMlUBn7a8EbDGxN0w2G3LCv19u0oc1p
wiUmX3XfstrzClAFfyDBpLgDQaGEnzAf6qIedxVv2lC7MFT/kpLQj8UycNskLDNUUl8uK1Q4o6BF
Ccc9qsZHKaMTIiOsLO6jdObgzBF+vhKZNKd1ZYSlxEZMjPxuDZ+/Z6m5BfuqDGlBt+JAtC/Wz6oV
RdrJqptBif1vFw1P+B9rdvo5yJMj5IPoDeX6ZFgr86KrYUXNPGS6aWMOFmAIQxGQi7LXL3fX1/No
KButJnfFUzN6sa7lRBQ8F9diLW634kSjhfDiw95MvFUe/END5haoIBOHYq4a1jZQ6qoepdYRoeJB
lfeY6zqto0Kg0osvjBmdf3wqjTPal4MKv/QXmHd0KUigabsiAoYqjDcOxMWp2D8hiBNy61yqrFs9
Yco/GgeCQSTzhXKyMWPFO9f9BlW7s8y3PeO3Gnn3zRevgq5Vhp9/fkajxHOul916+psxXfcGMWwk
ujumvwRmQtZJob6ibV4xusNDvHndDuHlpKSJHA91WJ4pKy0hqVWsOOLy/uSA7is2WjXl8BrQujZo
Ru2XxD/5Mg6roTq2ADwsG5SE7eaVW7iJD7KhHJvPT1gNAPKSlhqytWfZa1/cvraIOhYwFry1Sl4l
mqLLYmGXe6KJa+10GsuIP9qQwtVxkWxAU19l0IjUWEpAmmRFDvq0LmghnAxjzkyKQoiXj94PVEXi
rj9ttDtQK5XiQz/DQQa+4cs89JkFRbPk5IQMmleXJniji1FrznKnho5bv12Y29NaV45dlvya3zUx
LFWZ2eiVXXDthYitZOwu9rHVTaSk5ovgwZFBLXWpYNez0FOYXK8+7KoExcmRtDdb0PBxAQ2dkxNA
dOvdpFNqt2zXQTvd2BSgLq87d9IF7jcexIRkv30UOoNMR52q1hkW/4mCg3yNu8ULHbg7vO/f3g4V
vR9ReRIUbFF02YpAsO/omKH6zu9t25pkczTFsCOWpB/6XAXS+3V0xhf9UtTQlNTOtzVufJDRiC+e
TWeTV9dOt5Srgw7MjR9Zx9XPzLVCbt9jFJ7123+sP/fkM1nKq6POCKeHQ1GS4/zL+WgFiUvpsdkP
xcVDdT3YK+sB3WgE3d3V03JH/+0FKZhsTjCCweaBnCE5J1pJF0N3RvFwemNeoIgtrsYQHAYn8h/P
3I7tNXQ/M0zUoF3MvLBJfVArbMMnLn2+6xlnKZn+HKqglQ/2it4jhsGAXZMf8R0tblCWF1hFXGaC
o1S3ZQhPgo7hXsGke0L0Pjtn+RUByYV3qn2JSc8/oaKjPtWUW+nGJimFKARALkjXjzq5O4g0J0cm
zAOb8gk7JXmZlDSCQF5acqIgDWgEMsqoXOu3Rp52yUAPIx2RgYlvbvt1dm/l6qtzOt+KRAANhTGA
qfi0Y5R32vvWu42rwyGu/lH3BwXO8KT/mrJKA6dzJdKWgz9s/ph77zjPQsxPWUU3QDeElJy0NAjw
tCo001RlN5DLYTOT5RQVkH1KY+ChwLGUi8isOve6NMAYNyz6tlytbOE3XWygxRSpLH66UWYwyPaY
FkjdjhRVs2CYq2u5dA03BfLXmtTmHAdQLSq4HBDEUOH7SXEhJW9SyaSxUJCSi+cIHuAJKMwCv/gl
yrXUtKB8a67WwfT7WfNAJlklyqQ6lTUDF/cx30MaS+WQH65OeBd530ZYcFyDrOA7Xu8CaAGRGwFv
+LNND5laVc+bvNKz1YgZgQ8lpJjD1Mv0iF1Uy7tKQ+tzt9G3Nbo79r4vG1oEmRMfsWdCnLx3lvnY
RW+gUBw9VcwkA/e5F81fajmUqEJbIQVplAhmFIyT0BSWPcjPOgA7eQErJbudLZPjHjiFHhStCZP1
KNnk2F2CAl1GT0tq48DrMlJfB1b+mkwiGqVy5K6yUM/Pjgdkog/AQSUXi/tsu4FcURu+6yiH4gGo
A3NqqYkhLq/PnB2/7ZbCStnaGx/qVYiP/wpyOw4y9z9kWaDY7Q8RkCCNHhiV2LN7MIFk/p7/UPzF
TE2vMxSI5jowvr1f4nFIya/ZPiblCIRY78ZHRSRIPi3m4E86o0KGp03zQs4p10CJZ70p8EAvM7BI
H4BzNvTPvorR6q3rCO1Iv+6Md940iQodiEORwF9IHRbL4QI5T3xpxaVcFxAaxUq3d4FzyY16ozAI
C8UlYN/u1veXKC4g20/y/7B6aTTz2DEwPpOoeIis9+M7rDkeK4FK/W1pj1cIcguLbv3bMQo4vkUK
uJO7xJwyQGvwJzKb2qPxhM+53+SnHVq657CvmRhoqjLuyKqjYfpt+990JwYmKTcvrZa1nldKfn5r
x5px9NQgsIA4uPP9Qgk58VX4bj4VwSRWRr9ahrJwCUQWPqVAXPUOcZZm8Fw3VbPh94MROW6uPRtB
zaWo2das6ZrK2sHd/ho/TCwzhmFjc7AgtfWAQEifY5EyjCJKXbzrOR0XebUaSx5J4YdJ8WQAbq2D
QoTcfTQUC9/vqC+QJ4+cfjyWXaHajUbp/w9sT2uFWLpC17bHxQVKTxGQdrcCwhs0p7l7tHcL5PbF
OFz20nAy8NeUAo05HFdLo1Sl+cXjtEl5R/Iwc48eZUn3he4Lzni8In/HEQgjtCCP0eif8w2oFBzV
/GJfPuqhvpsFCWUUg6piqOa1chhv2CrHJYPkqfhAL3+gcF3yQ6xXKCUPbKVzjD+c6kXjxDQVhrFq
kaCZFOghM2X6Yt8tZdNzdLqkj0OBNle6iTsEWaVQU1Gw/EinN2zksSZmWdfx5qJ3quOF5oCCLYYp
4LYMkuAo8IGtg5j/+IPx2CS2uIjqpNhyeKK9nk1ZRqv+GsNaXZEmKk7N2tgHha6MOe0JqkyyzQ/x
ULocMCrREnhOlk+MbnlhwmKaOsmDgl5RkyBtO/r/BH8srEzlcHEB4nOsR1iPmIBWm7MWRDYGC8zW
7lCHFPiKNOKxpC62l4gxWfSJJMe6SDJ3gZFbqf17TPY2dGQqy1iOsE9zcH2aKYpSAAtGQ1c8v+il
naU87ZLOYaHwH0aaWJXhQfmD9nNro0o/atGRVvWM0t6ZR/dwKOcKdSf+raKcJARFI+31PhDZnYmR
/x0Y0JNrbVFqDmZi54wkRtw0MZvlUDRDiChbqAGIGAFjl/bAs1RMCKZHz4w57In7C2laOLAn9hY9
MVMUOZsg2IxZBZOLPZYG78Mg/eCbPHD0B57xyh8NogonjKiBdfRfSJ0G6GA/HtYl5AX1BcZ9rvgb
+/DUvtF0PS8emrSQU5xbU2NK9jd9pHPPqad3lxZ+c/WGA2bYG8/ZjuFZ/2oipZODbux8tVS4lmW8
X/F9X5gksZgmNYx+7ymstT3A1qgbPR5Mr5bJfVifVINz15uCV1X4shxS8uxmhLbfA/UJ/eV9vCEZ
WDSwlvjD16eBuJ6LgolVXW8O+qhH/eRBHTswG9SUJQ/BsS4YvNSQfIPB/J49ynqabl9yCJ/EAzH1
WENNxOiGQZgj2dQDUm6hmAx7cHf1g2RVbSoDHxTmp1/OrgzbYSdoyoCmZU60HYNVpdK1hoMjjR4q
ukSNOEd7bs+KJHdLD+tvFcZaJA9eUwl/axWVySOSAfTwLNplbYrWvdGSV220bBho+xALJ9pE2vBp
OqsliTTkA1ydes60ICaqDvqV/eVsP8im6UCUM6Vd1xbFk1LSipQbyHSvrp+wcN2hDhwS3Kco+Gyx
zpbPbvz+yo5cH1Xll4ouHcckvrVn0YJVS6ZFsxp4WMBFOd7Lhlmjz+QmdBrYgVqnUza9WIQWccXb
/FKeXPamQYnNc6mxGa6aeX5AUxqYW5M6SpOPduVnpxhEi2eDvDkZg5AuTjsrypo+z7dTHcOaqJNf
GTWELQbz4BMr0KK/nYtZOtxPXsIstVc7KFGd6Myg9Tm0hMPF0s0g5D2S6mzIrGgD08pPU2/pOrVw
4N4J71o3L7hHzaKIgGcID9EZ7Ttx5tUVIN86Mhd0UIyLWSRL8rItSIfIeYPKB0pGr22Iwfe1SfcW
0Hd8YIAJVO4AJrl5SJgoN59RsYocfllty3ON1flPbsHdA0bhuILzhIB2p0AoPKVzFVy3oyrBygsH
/5yUswYAgy3VsWpCoKELC12EuTN3VDnAR/lyrTwm1XoDSRF4Cnhublj5lEWl4oxW6wjoorqH9ahp
17stYpHb/KUOrvCTWkc/OwFLifv3wGVVyvrrDB+vz+ev3UUzKVGwvU9wKwN3gIp3YiAZ/Cz5Ihjo
oB9Y+oWNX3p/kGXmFXAaHEjIa8c05oog1R8kDYBr1aTzObFduJ3CTG606A10JBqvE0WXh0WzMqfJ
6ySzVyO6NJ68ays6Q/tvydYSayh8Ck70Uvp47yQIGO1pDM8JXKNZVfQpXmzayupo3oL602wGXtia
Yeqz9FAhvwQeP/R3IixCzhhEwg1qh3oTumHNoFutQL3oCkOcELWBOQOPWlQBN08qDLxsdY0a4x8V
bHVrYl3eCHDk93PnbdeVGaC8d5cdlkRuE647ktqEPC6mYh5l6SHOKA0oIAcZrkyLBHJz/lJo2Geg
ipNw41hXbxU0/o2K2N4dYbbDEFvHA+ZxexCGlt8RLZ65zEdMF/rFu56zNTsK+4Ar8hCdX8TbvTUm
tgA4ntaTDIOwNwom821ZiXT4wvpQDkXo16CzCJo/xIYM9NRgdu23EYHaG1buCIYT+xSCfpZJErbt
0ZskzPdrquBBtBwt8kaDG170xxC8t54z1zdYQeNPNjIFuo6mQvoIRJqqP23thDt1OtfruMsY753o
ZpIep2j3LwNb/XS8U6O7wUC2n6Jk0kqxxb2OUqs8CWB3I9RwaOL0J1l1LiP8Zb2iQ2avGbNDbReX
xeiYz+NsxSz8hVsgI1GvwYUk7bpWhVtTtePvlJtxSzJb3zuBtz6allzyAenwO+co4fmbMQN3/P3L
ZQBv49O5LrXgGdEdoIaJdHjwCRDYxQerh+N63sEFI0QyT8hYrtT95JGfOBokWHkdjt4muKravLQP
aNLMlo1qI8LfJ9iZh6NE3y9CpXrHc+HtSWtWMXCfqSk2Iy41kkiE1CXliuCk9Jvh/Mi0XQbCoRXW
OATF/H8LR+6txNPPdj8ifNDehjknXbLdQyDeUwNFY8ywdRFJ3rcvMMOmnBOVVh8SppZo7v0vGxux
4FFZW219xLRttk3k4yt5lU1b1Gn4MqUGmDINcCdPegHyennrv3eg+9nclBlPtigWwO5tyJhcFLre
LKnk158CU+NbugiyYcy0wfFDk8/L20RHScZ39Ua2tEyO9tIEUVUmub0yK7kjqoMY8mt1lI6aDUXU
5Ynz9qFnL/mIY9PHBwPN8/XY0UG4JqLeGxAzRh34hYsBINKk1GmJk9oQWfOwqEzr/ht9yCzYG16K
L5xgw0XcNlyBxC0/VExS/HGFkqCkDIFTT6w29mhAAEMXO3d4mIDP0LYnzpbN9u+MCI1b1q/OcPZN
dcTXd35soyztqYusjC/Rfe95UGVNifrEuyLQjcQmRckMgBgsB1zsXujtHDary/A69YZPqLEtAlTL
mPIJC3wQm6ZhzEGn3iXOBQhCJ+IXAdqC6GwjvVrUrAjup/HXhHfr7+lutp+tOPXXeaoJvwwCiBMa
tel8746kPz9tMV2r696AKivm6wdKbfW4XLpvYUXRwmMU/Ivx0FH4IMI6IT6JDIYpRWm94+KpgyAX
ktseYrZPxDqNEv5UYhie3KuqOMCmwKEdtGEx/Nz8e3/jC/d6x0zjU9OsrkJUwxUXvGFZWu46Z5Sz
hmTsQm2ZjBm5/EhJeSGRZANWngdLwin/tIFicjkobFvfMzPdxCL00f4nAJysH4F+k9BmOejquBjG
TS/6Btr9Si8lSawb1btkr/tHu18VJDo88gziaxrWfVPBNKVXltt1zQy5WeIIlgd2a4owTgWc5oFG
vrYVMUhWYVJgcNHAcLOxdlxPHQl2NCm7czLAk/Rh2BMxqOz+KWG9PW5NIZmpNXKH+xgDqR6NKpp2
ordgued04WnNr+bb7H5XoLfvZQ6npO0wOSS8I8zhtKaVi3YQe3DbpoTr0EbDNAigvn8VeJ45e6mB
hSQts/EhTsfgFEKE7e8CMCnhRo0RK4P0ezao5ZaN/oYZxJO4odxPVMwBuyfwHqiQ/SCwrxNSbJWD
xZnMhyNHSnUXdz7zAwa5auN2hKXn/i0Df74eWP5ZL2mlNtC36dQ0u+yxFIYZ2zEN7zdRuJZMntmW
w5lohOQVkyzcRiliKg8u1boIAkwEBjhy6hKP7c7WHV5kuQtXxgqa0y7XtQEYcV0ypHztbriboUzk
6Ti00GvrBg2VnG967TQHXVScz6TFYMMLWXCTIFDt1XYopPbMhxT35lzGBHJ9U668CsEK8CzUdb4S
N+4KjOoHm9+slJboTBx0tynEVB8OOGBuXN/COYHQdzRZP3+vFftDeqhsrdMaisrBlmIlQXNPa2cJ
/iChmromCya5kXUqUCStnPVO0yfbJ3yeVxLoOu3T8ynCE8NIrVtdWFNzFsAQCucC459pTcbVnocF
zOoMFh0aJpoTPTBtI5nQ7M+IevawaFjoJxWf8w55VkLdTtdyvkfFH07amIMUnhahUBEAxfi2x1MA
g00ApgZvbtnxJr3xuyxzPbk4jcbmRXWMxz7TYrKdX3nq160oldqQ5ezaA0ubLoxZ2AMYhs41h1gx
xgl3PWprwZZNjbhThz4JJdPPMLoaCFyxYH8VVQHBg6R0w3e8Vxr1vKvCvIBOq2Y5ZOBXr0/xELwO
x9hIVN9IhFXqCKghVxq0rUW0ffy6bj6bZ4+/JHCGWMAbtBvPv7eD4KCG8pBvLQ7bJ3WXFbj0ALGe
aqnT9tUGc7ODmIoyUv4mC4ML86jI8kqSx45USw2rq+nXQiwLQuP/gkH8VpcaiUaba2WOEQd4cG3+
qnliSrVKRavH4A1LPwsNNqti8NLOmZj1ZUQ8Xp7krXvonif3Okc1YwLFGSkZkSb4XYdaGzosXF6B
gfYxxkbnEk5Srku7hfM6Ze4VM+P218cZZJfTiAiYbNJM99trSE4LEP/7ok0fBsG67STgw1XIgI+P
Abnj5VcaZ8//BsvuL9r1XPWHXb5j4LC3Qa8IizgZjXM8VDgFNKcKwmqXHl6xcxNM0Vendwqg9msY
MwbOwpm7pjQVrAr5qOkQSrtjpNBsHtu6KZWvShjVzbU4LMujuMPelEYzLskTR/AumULhqjYm/0WS
owffd8I7kNP0w+rarqQYAuzDufeNi7/in8tb9MTxDHO8WntEIVu6GoSPcWvBn4a0e5HITKLLpoIq
iDyeCp3C8bL5q3V9O9ToCcS51BtUCQlll0WCyNldBnBJtOZvrG4+HsIzxYSiqzXD9krPk3ldvp3a
tPgvZt/MeyYFnQYe2hOHd4oRTBZrtIz5jsW5HqXPTQUVbtZ/f7qupapDZTuMEW9n4+ZIQclA4/25
/sJ/m6UA0/qV+hJn/9EVIdZXzixT2yAVAaaFdq5Hnsa3nlKM7Prefe/PTMNjGCvUEXk/CjM0SN4e
NbWqC1525SpK1Y0NcNP710tvq6g8DIvfLFyaZM9aHL0psXGzNMRvTMoBc3cjglRmyZQ4U3jOVCSN
2dt/wwcJx6+np0aN4UkvNojSto2mY0WmIJYyq1iUwXs13bZwhWfBKn7SvkVRfLA5LycNLk8iTNsc
ueprGZYXJgGTT0px/vR8YKRlMK02Si5FinFgfnzVdfbPBvcXxJk1X/Yaha6Q4kvrxMwb8rwUv5kb
51HALuzGr7oKWdwKOe1J5lYI6kQ7ujfTGA1U2DHlgH7qKMYCwKLzSEnuV72Yujmba5Ss7mlpszTs
IBmd4Gu9FkOdpXhhJ/t645aqgyQRsskdq41RCQEbZs6M5B6aLsoRk6jV0JU23DLg0TBuSEVq9Z8d
g7T0TzHwCxWLiAhafeTIVBn8VZLZVxceHKqrpR76aQXpi+Jt/4uLgJrrIOpNUkC/GeKpWkFEgeK0
8qT/ZQ+bUzoU5/hbvLfCSV4dyFRFRI6B4VhCqG8BBAdvkjMMtlXTpftkgdP2sWTqIYH9wCOdvlJI
1BvU/kWPy3c7Bcsxh/gL5g+mjRUXm6wubosqFTgHXl+kPAoJ7+Z5iE21wJZcYdMzmGGjAhhVF2V7
3AD6O6qnd6wMacpQMNuwKGllf5sXklR9CQ18jBMGF+XvJoGE50YwbgnCplW2Ur/XvIyKkNRetcGE
W0xKepHU0RRI0dxKTB7EAAk/6fEAO145D1ZUUQfNcXM/BuS/RWEf35W+4BQcdfcKu0fZUTM4WRrU
YUkBJxhnJFPCzLZJ21vp5cZ7xSIcf+ePIuMyfVxCNGahRn7ZvheziyMlrEtt7U1KL7LVPriOnJak
zZa7rx4lvCqFj8culvJaA4gdkqXLhRZEqSBO/+TXT7nTB7KCqXl5Cvuwag6+H/0lkLxtFiNGtNGG
s4XfTALtz9jzxyYzJq8XgxPEKGXdOQg4z2TFUt4WgODtRl/a0irmt+R+pwGgURYf+oXdrkFwpHzt
Wz61ahiRbcAP04cMjLJ+AIO+S+kdd8w9CQPWHK34thKV1m4fXJlhsHQDzBfU0AsVg4Apua9fuHJE
cMBa2YvlK8/C1LtdVR+hL726FqdoR+BNCzCg9QZ0VpHoJmlmmnd9xEd8sRh0sHh5xtsESSQDgt+G
wEdBSDJdyZE128QJ0rZccYRnZ2yzNxmoy+y5p/gIVTvWEr5x93cYzCrUpX6rsVYI57SgwewyDNQC
DZH6nvPEEC//gio0TYQ8RfaYa1GZDeD3/1pPFtm1t8PJTArcbA06vJiIRcCfrw5i2nfpEE8rQhEV
ktkgSG5490l8IyVp10XAHTcYGNvn5LoeBs5wLh2yWgDt085nn+vKrJuIo55Q6GUpXm+7ZkqpJY/r
HBckQ/q7qQj4K7y+zKedme0HXVbO6zSlEWqnI3k4vfROrPWEsqnAD2cqIaepebn0sFQEvZjJlr/d
2Lb51jNexmbC19sosXndEWjRawKLZba7vQJEFfb0XA3s1tF9QhG/II3nyihgtVB5Kvjvo/hp00cL
iCuZop16vvQmrF6Afg4swkI0RizpqiZKzOG6uiITcaUXrdwNl5JZMRmiKVIwX7l76d6FD9xdaIAG
vxldMTNd/o1WDTK1668Uq2T9r5Sofqw9Wwyxnl2cI/ushxKBWzKkTBKUSoBAIg4Eq3DL2J0yKq21
fIH0WczSnLu/4CUjJSY51tDEIwU2zJP/CrTpDqBAvTBu0w0tPk5JDzKE4OYqcHxVtI3XUKHscd1b
Bgtq7o2uCD6y9FkRJM+6cc7YQkC6lvDZm/lKD1TpA1PhlDPI7hLOCJ9vdVQvbvrqGY8aaeu1wzGd
tmF3aBowI0PChVQMO5xStPwDQmAlJAIQ5rh5vEtAzSP08aMav0ZT6uvCdp2z6zSu9O0JE8SqDrDy
XdD2IOHIFxN4pOXWUY77oH9I0pm3bn+wKKzUyJq2sVpYpXtV5wdMezSuNI0YEMSpqat0GsDy5vjO
gwEGT1XBE35On1TGKDcdg7Ej5qbREaYn8Q8fPLqbQRlbL5AMkTtfsFHkNy/wQBMp09/CNpSVHGg0
U/np9+tRwlTzp9kQ7QFMJF3rrbmb7Fq1+C88GRLRPspFQ0gxmVqcujgBy9beJ3wgul8vFuyLYx09
3jBAq0e09oT1E0awa8EF6wFzr7gvrOCsb9LDixZTMRWIYJUkiRAKbVO8Uk7mG1x1JF2qhWT3qG1G
gstx3guR5Cio9aEhutNtoGdB34CQWetDIM/EMu++vYxByQ63zeb+CN+B1xbSQ+JrSWim6cdwX+7y
p2Xp7TpTuMH5z65IkhyaVRkxIM8Odph6j1ij1N4+tCdZ/hpmBp4yq4veO1U1hsD1eQdjIplIqhKN
rvdumAYZpwiKg/OjKoAAqeZyXtMZ9HEU6RZW6Z8qoqsFRmczfOoKZ6pJfvYzUlL44D8BkOfQBkfc
E+oiFlcXX6PB1t/5Fd/R8cd867lgzWGOMOZnoW2PDtQz6oJldpPqn8HyA8YOgzxkeB1QUwahc0fL
EQXcYlOl1g+d2MuqCXfJs6IylF8xBvRskqvTuvHsTqrngijYSGy2G02kkB+mOjtWq0PHo0/N61DE
hVxHNsTknk4GOl89qAd0fSoLkd3v9OJKuDrcDhr31MygJoGqw6WCKdne/9ZCPVw9IGCDnHpJIgc3
t0Xj3BCr9SKRE8b91pN4ugfHOMDkcGYRkIvRnszNTNBFYFudwOQXx6mN3FxH4VcM7RBmAigAUFcK
tNn969KPAz9+eC/7pA/wmRP5ClJHkXhn1gMtAQ9ZphXUVroH9xP60WDUgpcQPpEmleUptwL+Z8BV
IjGdqWBh1uP/ASB4TFBL5tyAvoMi0sgmVwWILO8CJGxKdzVHrOvAMHfI0FI446zQt16LrrRa26Ej
t2XvUWi1pr4n58wD27hzMev85a3fgQwZA4Nj1aV7APmADx917S5f8JRXsR+WTTJQkQaQ1GMyask5
NcGRhhz7zF66Hc72we7QoKd1rbsnXzOS+Kua1EFbqELeKxITd7h9r95kZZbMkzr+nFK+WPx+PU2C
6/oxSJ42OxsCxhGsaw4I8lkbXONlEO4my6ECNizXUlR5i8yVe8joBzj1G4wpIyt0DhjZr2OX20az
+ITBwbSrlbqJeencXHWL6eNfEvmZqyAtsZ3ORbKrzLxDn1ZT8H/njmrCXgHFZo4Djt8/ldnCv9iP
dW7NZKn6nCJqaGlrpIiOz1Zq49QZK1UeRvLCv7d8gtGLWoKW12aiGzIOG2p2mtLBAp1vvVKAUzeZ
G9cvof9eOQfnIXfcG2igukoi6f+0fPISiCPf7MgTob3dHIbRAgbIIVqxGuigyJATRSlynR0d38Hq
JT0gKyHap8eiR6XGp17eD0pWXLg3TJ+3otc5wjwoxwOYLTeu9Pn+yvHITrVLqCEUjRh3Xi5EcBIt
BHE4h37SezrVUMKxRITX9Q1BExuc+cUHzs+KctijfovtF7jIJ4Q7J2IWsHzFeTgJTpk+GgNCKVyG
f8zd6FQwxtoa0+Et1ut3JXQhxWWTvLsBGNe5UAKcXSvRiA5hu5wSVYONeaFqcO291sBuyCikUcGv
fOQ2L572fVfQV1o0k+Sa7ElVpD05Xr9CbSbf5Sw7exQQzQAX6uahNmCYG29p0uLk5MHtn6Cstrrk
9k2Gr6rE8CDcB9QgzqSxJqBLU3o4zAHAQ+ioust3Sze2FKCgmYpDiVpRFhNaOtpyUZ+dU8XNgON6
VNaUk/RpidvknEckxH8sPbBgIdntg/t7JViGrCmgvcM+rAG1AkOZXAOyEtLfaGtjxepPdauKMDb7
EwrvY22+k5a38rwQnMBHHv6J34CajSmxWbP1oH0NzUjKSfWrdySvAOmhiQJqjUBB7UyMstdP3wS6
v8Ls5Jt7EMl7GXXJzNRs/b6FmG4u+jNA61s0i6Fe6nIZflD3Y9TvZNDaDmunyBv0IhFZ1JxjiwW0
UAsveY3FNLu7m/+ejhWclePFzPCOTZM+VjWXtMrojiaECxG/AJkRpJokRT+jzyLN+9V/vnvY8QDW
2nkYnf7fjWNOJid3R2VC/pqljvBIa9lcaRO27o2lrFrwHYmNMZ9IeyQ0DFONE6FPVo5s0Gg8iDwz
8+2ogZ8DQzrkpdWN6GcyT9fBVb/F5r4bO/t+Zf/QZLnTQiWre8yh5aKrtur/6O35avVWvscbGfNf
BBWEMDyavfWTDx9LbCvJjvvYkAosAKzNZbQtCsoOYjuUoa3Y7oAd4VLM8kXYM7wG1FTMBMbg6MgU
/QvZYce2zlnK66JgrXwi3I1Nl1XD1pCkG+BXnLKQyASnO9DqT113/0x2ujl1BgWoXmZjoeQGSe02
7SZmp0hxLu7KaouMCITPgkT5eMPUSMGJLT9nyJcQ2kWEwrkKjWHsnJxfKeCFbPHQnSRvc88+f1Se
sRXQZE0mKkl6xpa+GIVIs3+d8gB507ThG8U/JY5DdBtB/0Mq4vpOFbv3xHdW5RFbqZpOrxVAmAPf
kGWivDKiKxG0K+MUYiKZAVCpTw7dbtoJttgA8RYxzv7H73rqKMQzhNddpEIFL4hYK2wTeqz4d+lP
oVdGzRkZJ2RR9aeeEo9qdr3/Lyy8rAEEz77y/8GB6EHYQvNNm/slYMSrILIvLYvTIekbyTbQVRr7
3dyAmp0DDDvpcnlq/Mzrr6u9lBwjMrdYzeBxMdooDD1FTKUNinAFldNalNuxdKvX+LZuNkncKe22
MY3An/G6dQExu2Tb+XLyKVg337+x0PnKWJmVG/0yN8uQPL0PbXxUoN6k6PRKE3oHPJUU62SV8x8x
Y6//hpJh0NdJxaJAVFbX1Fi0hIUIi7QeMb3DKw7nafQ3yUsNJ0npvrrh0ppyLZNEvJWXkE/piXRk
6I4MzYGAQ2XHn+KCoDo1O7RUNq6ZSH+ccdXXFBki1ekLZuVdatcy/7Ev7tdo6NX0ntYTYFEkMJ+Q
M+5YHvBCXCsvUdN+x785GP2wRxpdLUJm4RFQ/xeopTkUZaCD5PHbLK5V1x70GI8rOVHr02x5RALp
Hi1Gl/euL3/kvGwEiVe3p5m/+SL+uJCo7+Q+lGkbe6SxAZsJMCLY1fYqnn/tw02VA13dBZ/JatCq
k6p8WvrvU/OL+v8vjBGSHsL/Qkw9kbkNde4LKWi8IRIOe5Q6ToTszyEJ2gPFmN631+ZWNeATphck
Jf+j00dDC0zXz3oX5CssaGS3LtzTGQE78hLR5eUr6St0AXJYprxQiYO23+PWYj375J+l829X4SWl
9WKnKXqPm+a76x5LE+3V7pPaDpX89+qW3KQom47cWQdWssW+VnoakbO25GACrjfsgaDEdb21/gDH
8pqkRLa2f4TsVFnYHdQV51AXPeCWl6n0euTQQPPopGeSfO8D6STJvhVL3z9N+Erh1llwOjq3DSY4
Pm3wEYcVB4S+4VGExbNsi6zBVzbNSud10S3SXLScoUOsPrDbymeBtNs6n7kc5X7o1NSQ+4c4f5Z8
bh0KqM8yomm/ai6M2CTq4D+B30wZhBsbXNVoA9kdQKfaM/isG3EP6Xk29LP4+lg/GGAaQFeKvaUO
JDM8/R7xQhffSR8UYAK1Lx4RAWY4wqdpG9GoVA3VMUJmoMHliFDtoXuKsYIeETY/RE78427wkmgd
pSVAHads7DmI+Jb3oVJyEDkJS/UePdm2THUxpruwynUdiatFuykXQKG1s6EKL5P5rKOP3hG1aBtz
0Lz/kTQ2L2XKYLjZ4KC5Yn0iWjpHnBHX7zaUpR6Af0rYGZhFq21pAWj/xH9KwENTHgURvRNY+j3z
HEvwtUIsw0QUAKuLvp63w34GjjdQmrnhdnfg5WLFQO0rd6o2XSNpdPV85KNnDg13SEf+S0wj2tHS
7iqHNOZVvBTXnWTxGNmGJkzvAABzwkV+YOK5l+MqFB1YfeGDcSOM4V7ksS4VLETV5PlCmaTeEVkP
kcBKElQ+mPRU1tEn4qJK2ckxEucFW5yN4qhUZPtzgC5M2EhQX9IMecUy/5EAzOD3ha+ARAkgrBbY
gVYW1e58Pv9QFzF3AJuAAUQ6B2VDeDEi78WG7yh4M+G0pGFo6UDoLDR2uVQ3QACaU1Mtqy1JsrwG
mXlG7hXLYD2c64lCqoihPX9HA5g9PzCysZVT9N4M0Qm1/7R6c6gKOAO859mHjlRWpDBUmpHxuCCy
hwSLcX+W/DH82d8Q8kXoGqmWoeb6AzSusEFzuQEj2P1BttqMuWAwbpMmdu5WTx18AkOoI4kbKw0F
qCeZAoEhAwSOXZk6tStXy/JLos87/XxXeRCGJ9FRUhdELvKcnKVgMgw6HwE88BJwFNb41feGcusV
I28FFZGqan/ZxCUpz9PPo1JfxXAE09g+hJ6rRFuHw5UHM4EHEIG86iOLiMgbJvaRyDQ4ciCVuWGm
lDYjzt4aTdyyho5JqIhM66tYuXn84MGMxZ9s87uM0fqujW+OhvS0FPpLeQykQEoD6+cB4y8p23I9
Ku2URFvvC3HjuQjLspRUOTH/h1y9OA9cMc4RE14IzeAON14fC6jLFx//J0j2PVYIFKS05BPD0Lrx
c8JpiHPVVo9kql8D633czpdhq9uOYDvIZi+l0nyVvPOSvrCydPeh6MYIdTU5hihLbw/Z7ChqvSFM
VOm4/4nEObVeiJh5aVlWS9LTpO5/1levtenUYUwU3pjgqzXw+7QmTNLUrsGEkN5955yzR2vN7/W2
ZNNCu2W/zSt2DGD3G1URdOazq5ScDLDDMpevCBHqOLz/7OG4CH/pcCHssX1FXEPDFO2LyPWfs64/
px9O92vhwg5GmW4Ety6G1AKUe2ZVIUbLqb8okc5wn0IYTHS00EQzdNt1LAReBVI9Cl3etRYEcFji
ynZ09c81HTN1zTq48VQTMSCXYVshv8sRCIMylRd7uzWXyv9MTNHobJTVXlBIPc3V2+wjFQU6bMB+
Qc1TL33iEZu1nA9A3jZnDKPlgBDsSvj+qYyximRFa5LoO4XH6pvqkoGOpfMrAoh1XXZ5q3a1cE3d
VsoHem56b3tE2T4C8+BeI6rXD2QJHrlDvRA+vz2oGWGte6r9eaRY7iwUqP5X7tLoMw7R51QcNQYr
nMt//3K5JyuLU0zA1+N1uXBuOYMOkQje5p/KcP3Kj2ktmIXoQhXhpPWVYTnBXDTmZQ5Lu0xosnp9
fRehD1eiroHayZR0k53k8rY/xWgBj9BsdsZE4MA9IKzY6eqfhsr70TDIFexq+2DJSrr1SLW2Vgng
8CGYQOACGvldkr1L7EvPTSenxaiJazXQ93835q+JyP9kKXuNrfKT7StCFk8pWWCueNYK26/TK8BU
ntFJS/Oh1Btw5ZYXASA4MsGb2vhdLX1qSUyNg7xuqigJWv6/EkwRpqNk2uY+4iOBV3e/FOAwMvjQ
VSW9QpQ6h8/K1vxmrWvwSscdhGVswhOvIyJa8ILDxoyh3rOJif+Je4M+49dB2F/QOrffnPdrPLn8
xIl1fVUSB6g80C2m/WXnYfXS52i+fCcBonSNrBHKA5W+H9wfGsaFIH1Ep0di5M/f+quIfFMyAwZ6
DBNG9OdnjqR/ZQtQKdN36Idx+5B0/0g7LjPtntGZvAiVtlmniRJ8RFDKNm6vg5uIj50+84oMD5mh
ImFxWI+EhGyuDkBSEoSlQ8nJ13/Z0MGMKVdf1g/9ViqWf9P7Rl/5/CVczNY10P4f/S1Ytw1V/H5v
ozMHCWdEkUQsgrm7rJ2UYskQusG/cwv1OiwOySC0vqwKWaEjwFR0T4ohpkvef2x3vCRCTJpGwpjy
ALiCgPgA9eluH8mh48evnFzI7dqbuZegXy09IZX3i2cht/gKvEE2BMrC+UOBLRtF7i3iTW16ru1v
eVK5+9MR0ZmvmNAwqmzA0qDtTfzgOLe2HAjgKvgI3PD8eTgnR9zkgeOA563DB93ZKXeFe3YmHd6Z
z8rq/0UhbC/ZoiZWD5bGYZ41QweBKU7r9fhvC/vyi3gL1eDYGdB1Bp/D76BWWoPrjgb+Rf7kRy26
lZCKQ93g3lWkp8av/iKgauhzbxDWzZGb22yxfy9nJV+OTmsOSecoeWNWCjJe18tFn4coP0gDxtDk
P0XScnDWqOgc93s4pDbaSyVTAsPrytltFa5bV16rdYXtjVfGbViTj6wWDoS1/2xSaYYTYSoHP0jP
eVejuwzZkbJi4g8QVrtlIruDtXz4xQfKGW3FseHRB5VmM4Dn4c0R/J387ITpyPer0HgO9AI8he+f
T04eC9yzUwqFQn76f42Uo5rXVbshuIv3DKh3PB5GNMzkAsXFzoBFez2wV1ETYSaJVsJrysHjhvuw
vo8JfGnHVpfBT5upTbq5MlQubSzfMRs0yWMA79WHye1q2ven5FCkLyP43yL/A5Il3x3MGOcsJ2r3
5N2MrGDRscxmJGZE4LWJCmIOc/g6DR4dzotAJMs3G2nbixMcAeOC4xvInPiGpu6FU+kL8BAu+wmO
iayOXoghB1EhZDXIxi0Cy3NB74kWTqbpaFZxu2JXe/YGQG8i11lgrngeOlFa3xn54h7lgNAWxMSp
peJBlhTxSY4Uplq1PUnW6Be5XpAfokHCM6qfrHUS0yTO9/CYfP3RFJrBfBV2cv7DVv6dJtk1ly0N
EiEaU23jI2FPvZE5qbPZ9PIfe/daykwvSc+yPnPczWembIbsMob4C6dT9E/0n5AmFY5i7DtLW6GT
TKvxYctPrSP13EgY2a3IOS08Bs12nwzBQyvAMxbHPlu3chT8HxzmC1KN58mTVtfFbAfR0W3vfIBu
VW4oVKsOW3GBAXaA7lFxekXXQvAHSm2oIv7TsDjBFEX1m4R2cGcSj0162SM+66XWRWHWKgvvdSEE
+pM+m4XzxUIYve4mZlrbTlei77lk4X4LDINaYX9AQsaVP/q8ViNVL4m8/tnAkUis2RUyIzOnPHF4
paiT55ANM5Rs0ZPqgqfCU2gatUWOxotKglnarAP+IlzzsJup2fAYna7998r1o/5X3iON5B8mkQyQ
2w2Ef4L9ZBLP2sWMAssDlkNfWooX7+f8/5EfEYPc8n6oPZTb/YvafOs3RofLbRhRD3QGGFy8ZJ7Z
+ojpcTKWWJwmmklAFUfFvVb1kl9WeaUmhw4Pzmp+xhXBNn2oOJCcNL/PQCCnjDU7qU/IC4TxI/Kf
HQHxwtKPR7w2jXyh+oUWYmYwSJF0BEE4/CsIMHk9HWRk1LKltGBEGpPWFsFCRMdgNasuyU+b8GAT
UEOFkha3kLkbWj0to5iS4pJN1xKHMDBsP67vofMHeFHNcmOcx6OlC7Yk3SoYKSNADPbrsHpCIpaE
7EEi6hjW+VZAFdqjvGZQ34NkEpOsiUNzWkQhIe6Xlgm+Dh5jsGdBs+P60bQSrCPdxiB2Wi7pwiwO
m0Mx+PIQMKA5ZYXa4xbhx739bBMAjyPHRcpukvvbTo+Bzs0bhisvf5Y6ncMbt3bdRlv8kWfSWyAb
1oVvCx0pQ0BN+DZRC2DZ3zgvbJJ4ZvKTxpILl2RS/0qxKnPRDlGexUNvnGb8rzegrPXeL3n7uVJF
/ypUSR94Q0D2bi5mdAE3lbKci16td+spUDiIH2G7sZWdTKUFUlyDKu+rn0WDXG7U3xt2uFmEwRnZ
AdSJF8Xp0XkBYicz5oT9F1yAfXikaSx/R6oDM3GlCRAhQxp7KSBwfVjVY3SDAfZojZXL6yMjG4+Y
9vg/MS8olWcuNQEk89kdyPjDoCpMzFV3Wnh4d+1PCDBOe1AXOisiHiuOF0CNj9Fr6VPs0mDDAdPI
iLXE00dqqT5UxZOoVBEdPAmiLr8uf/oKp6r9m7mjwZ3OgoXSXjKbfLcAqkaVtyWSzVbPYGnneVLW
JHM+t5YFMxXg4sbK0RLpJXkKwwEfmRJ6/w3Fwj1RSvZR+b+LqEZxcWKIodt7rmXbCZE+qdJh0lfE
LZNkT+QZ+UreSLjDeaDTVOqHRMk+X3w0YLfuErCIrwSU1sSzg4DBUwkOIKrjRrz+3eDeEvbSv+Nt
Xcje34rn2FB36tQecJFAxcItcDWuNadoFUaRNXLUjGvH8nZ+MsTS7fbRkixOYYwWjlLtMzsKi67T
lkKZ1t+tS0n5bvo3fu+BKnAACqiMjkbEM6YiIm3Ho/bC8rBSEOjl7DCosiQeflihbnCBrSN+nyie
CPnhXYKbyJRxsxzdV0oKqJfbmsQ5K9QbHNz2DBmulNkdXAv5BsUuLSWfFMzSlsxORYy4+4ZZm7va
sLHFGtOJfUP805QUe19zBkBGDEjfBACZ258YHGOUqFpjffGMu96aFyNdzI41qC+ItXLg9hbLXe0o
HgEKO7b4fm2eOKEBK74SNwxN3xhzOWcaH96SEHCQInY2/nADNlqjN8mGiCXquJL4p3pzaK9shSCq
D+dSkGVaIEx013lTNemnub2cZR2ZsKNY+zWYb4bZDTjxgDBR7M+/201MCbxkAz+RQa6szmpivLor
wRuDSt/mtfK2ipfq5L85Io8ZdlZX+QIj/2NGYrpEAaC5kcam9mhFsugK9ZgwX6URO6ZCJc6hA8ob
tr8JSN01sJUp6r/axAzBw+Ma1vl/Sp0PlV6gtEvHDTYAIUXbJr9UqrxwGhGHecGSIchH9va8ZqYr
R87fJs0bnciX4jv1i56VON3CgujOPaZcbrlLZphwgWLoU1w0FNj2j4x7yKvHqIKx5SPsv9sMZNZc
Cg3kS1dA0hucK2c/8XKUG6IB94jioAt1/OUdZF6CMLzOsVTL+mC5AVs0r6wqPDNFZ4965Iw1NfXy
N4msuV5ozXpxj8Oxrh+/8vvJMfCfNlr2HmVb8zyqlDBcrPZL4eBbqEBFCAHHJgpAo9+/4d9BgG7I
IBqoXh/wS4Dj7+G3lJEB49nn7JELF5mjPQ/801ClF/fp3HfHJcUBNbh3fH7ri/EhMBDmk+nNcULk
M1Q3TBT3mAI5HUcWc0yGRf+wnM863IVTRokbhkLc0Ng4pdB3pmsjInXvVIqSyCw3slW9GlVNr/49
+7wAU6TZPp0LCbZJp9xkBn93Nh03M1tcFD+DpQEi/wWztNMIhCZDytajNvQDfWbIR1OBbSTJiA23
Jz/dvPfEXKCcrBcKAzVnwc7wQ+b9CFraFMA42OYz1u6C4pxVAj34KYntojr5i8lx+P2yj2zxLjRg
fnL4zlOWm5NslPoDt7EqLo6+buodR/116WYfVz6Zgd/T+Lo4yX/2LYZhKdGmd1phcnk2635RwOVX
bPgGWrbwql93yuukgB3tTV1ZGAQK6gewaJR/Asuk/67XBolOdpYzZKTc3cNtZSalSYhp3ubnXewI
9Zjj1b2tFc2LY+Z4/6gGxkEckbGYrCAPwStBU4SJDVbBiQiG8uKLhPSUciH8BY/PxbFXLMAW5pvN
sU2qRGcpLmLGsbL59HNnVPC0o6I6yAubIZxAzkED8tpMfgxJpwf/OznY/W3YYYF99F/NBpQh2P+8
S3v0orXiL1Mo64wAKqfgJ/YzpIC45AeU9BwRI1s3x2lJ7GYh9zHt67YJhYZKFSJlSupLsRAvbESy
Ek+kMOyRo11o5Utff0TS0XdM1bX3e40c9Sn7GXBZ+8IkE/0zD8bf6qEIRFNXHbhY16CkwMUS+UVD
5oH7lHsOQLEKsIvwJKwkUhfoLdQkpbHF3SmGcFUCBSOBhumWK/sUbOKCOc7LiggXiZ2xM78nr2N2
sqve62j1nsbJ28eHroIseBXziWLJ6SyyyzxfalHPfT7tn734zHA4XHrAm311VjMZiNKF9Q45qN2I
aVk5v+RZNp1qTt+mWi1FJaW2RWJIWsCkTdvHNOMB2jfBWGzj01CKtjnTQ3pR03Kg2ZYno6uR4nBw
Rq+rw4SsgBG9szKjszwhlKexH9xywRKK6By8yDP4IhicPUa8ADZKy8LFXLUxkhT3f7iCf9mkmhn+
0+RmsUTWIXWJiB7tpGVndhSfvlHxTYtO+CEhaSGrlFfz++WzzCDq50xUH7WT/CG7Oy9cJjMOEsxY
njY3T0mnG0gWyq3bSKVdHUAjJSNzXomS5KzW50FgN33dsSB1vQQhJ9P4piE+ZuoWWnWIF9miB0/M
PntD8GTKfh8O0q1CxEMPe9u/LZvcmnOfdHOeSqA3dDK5ps7Mq5pIS5+Z0FRrufwRkcHt2lxyQxr+
sgPWJrHuMSCSeDxIRfkAVklcGRIcZRGOvmCAAt2uGTSJk7cUS3fXO2XGAti2NZpyOlfhc5Ff/3n1
Ud8BdHuedRGjFfgnWmxyOOJtBiJRmgQ5aYdI31Qilj9F6ZwrNDaWPJx7zsp6Wdak4ReNkbsT9dWc
LpJ8XiTG/j8rJ7R4UGfgZ966+TOV+rSmucEaFUAq8PhnxlqEiLO7mKGVT0NbjbvSWcwLhraQ+U/g
xtkd/txCcWotJ+mu6gnnAWcb1OVQTcg47lsMh+KRs/u4+EZE45YVFpdC3Yc96p4MVJ9bHR2mWqh2
v6Rg0gg1JjE8zIWNjmJpjcymxQGJmk6iJTxd4HctijDGu9X3/UjsRHJz8axyUhrh9XOhkpgQQt1u
lphQLT7+AExfMT2lUW0Gu6w0iJljZmP4Vh91FBKSYulmg6eqZu5sKCyd7lInLZzrg4hR09s5WKSb
H5gl7X3+Hejbuow1dKPgfMFe9LCBKQfNtJuwTMOPlBKiAjv/ci8beF2po5F0aSbapQIyS4p77XqC
8NffAmHU/WJxa6Ud8DX5SDixATZWtvn29LsVxdOQyMm8KsuWP3nNbynZ/JB+JZDwsDXidNsXc1MM
cqF1WmBCR2iJJG6MUKfRsSokf6SbCow5lb22y7iuTyqUTUFHl0vtWurH+BL1BjXyR8X77+Q/Tbfv
rhmuHUGnjTKRkw4n4bo7fM19y0M61BMGuSuUL27oapzfRbw916tvcMjjJW2ze2eE+FqoYfzaU090
uGmKxzGigSgg6BY7QXPTiWacPH+xl++Hya/lLj7baO3xq6w38zBSY46Adj8GhInRa3RHDfrzbgW0
EhcRcnbYCaXM7H0c1y1w/yIhLvcAh7mOoYrL3tDb7mcuSF4/H3ZRATuxMlUvdMG1dtywNww4E5hC
2wlkBnw1LUQl3PIBXs8f3kGE8GquHOiTSZoPL0b0UomAw6CZcbRzGz5T/1TWCV7b1iE1mSRusv4I
Ctsq8dXjR1y27eDRAzhGeXEb9XGwY3CaKoL50n9Rfqq6XI6vF35OWQQN0b8KqqvuImVTP3VmxmO8
DWFbmLSU/8hg9QngCjLTwWxP2CJj9LPRbtBDsRA2la3QcxVLf9P+ELm3WBTK/09VhefAwr9qkamC
fGG9CmnlNj+ToFvkKa8OLA17pWTcpaOyIX0GTvMGz+sNGwZuzp3iyjv11f4I45bJSiX0ABWp/IQ0
EzgtalXJen7sPeXQ8SgXnyHV76vLCQjypLb5aaH2ZIV2nD5xFDMUZWPf37o9zEOvLqfV3jfonlL5
46Oqb0ffKRRiboMbzDiBvCOdZkY/UmxxU3zckYsRrWfLB+VEok3IYJVDJTRcsiKdp95Bv4vFvyhv
9yeQB4TXV9M8/9Hc7JrCwTyt4kH3Ff7JZzgO3A32HH5abiwJgTdDgW0Tme1XQymdfV9uo0wc/38Q
k0/5WHBzVvu0S60F1BwIM2Qx6DIY7xwE3aDXUQkgzav6DyMUBHWNXMwRozf7bCQEI3sgSgkgPHyw
0m2z95frYMkW2W54Xvh5cfNsJtAkt3AoI/iDxtHSYERzLzRuL9RIRjRpisDmwhT0Csc40prMon4a
UahejxPga4dDLaq5/P+F3UAFwlKk7HvTDZ0viL0Rfu3i4mGjgmqi/C93hCtSunrfRXekNnEadv1f
VtsrKlwvEVLzmgyklSkdlZVyvjwtvn4/QI0+bHvEwvs/p/E0iXPSgIZYkftR1AIdVfO5KgKIVZAX
nxNQwB1I6aM/eYEaF3Sri90tMnyAq4a4bA4clW7AQjA5FyTtA/YURZ73rCGw4ljmGaZ+8hCXR1TL
9yzpU3MXU+V7Wq7AE21aOxVMFVnFPemst1HsS0Cp79zZqasKmOOLkLNVePgsfjI8eRM/n3lt3YIg
F5aWZ50icfTzHyWMAkUQO7R3xQcFlDuMM3Z/meoZNWCM5ais76zSZ5ZV3NgmJ2jzKApFlcKatNV3
0gCe53cTOkDN+bjun9XXfWFtZweBkUzcUEu3b5ni3Agm16ZSbhue2+hDkCLvTkD1RtcHcZoZadPT
2I4vFuzKOL0WRe/3wjhZCwHI2e8SiHokgPkxe+hcPu2Vl35tf+L3qguEn4U8yyDTutyKMUzFv+BD
K2p66IzCWKxebimOw+gfLgphSHTAjqAywkOclIS++RW4NqidSwwFXAxQO02uZDoZgLiUctMtAgND
ip9QxbHzmGdIiAYiNtoDLYNqXl1da26UAqDpYGWyTgwhN8vk/aMxCsCJES4p8qCKKWm5I54D/FlR
hulq47LUHPdAWxEuzODlfZu3HweENDXa8dYX5D4evXbHl+kd4z9DwfST+niae6XMdPIPpO/o2TMO
W4odJ2fN4FIa1wbkRsECsSYXYF4hHgGKxHZJUVETIpDJCdNlKMp+hwFw5Kh23gCphJnH3SPOdNGj
ms1BrDz13vWm5/HIku05L+KKQtKtIAEUJcoPIR5sJhJk4tbC1iDpzhLb7Ul8hxD5XDS6go0eoPxJ
qUeb2RRsZrDfoA6iGHWlmm0IuAW01Ai6GGsHPZrsrxwqjEC68tGjTx8WPfH2pQLPJ2kgaolj+LLC
BFmiR78vYu5pvyagw94v6WeipM29N7rYV8hIOewIGKn152tkQSX/egTS9MLGWzZs35x9gR8ju90+
yIK2eZ6BAsoHpCKRunYbwI1B6RWQ6+SnDX1lqJnXhcisYrMc83TI9AoulUoDqH8l4srs9kD6rw7z
EuZVxXPYpBu8JJLLMk+wdNOICofKpCpWz0wiXEdsDUBgoEnO6pCPVC/H4ZaWaeoha+Rgn/D4ga9c
/DDHoDVK/2iRa37aFesb1qarq3/DuBYlIWegYFwm7+kUzT+kwee/5YNph2NTNDMB6dOYQZ+5E4cY
LL1ERPVm3Ru6JUkGyXK+UtBEdSGbaMlARBi+aDoxzxh8LAMrqaJpVfUWphbgDg5Jd+kdPd7nfsnz
OG/1cQtN0sGGHQ94eSwSXfGyPZPGKXd6jTydYeSH7gGUPwEJXuv/oHXxjQ5qXEMzDHo06Hpl2eP9
GSTamGT4T0QwDgDKHiNK622piOB5K0yB2FB/Zsz9t4um3FPJdUB8qU3R0tBGXWuywpAhKMTjNTnr
Vn67pBggLf8VqBEl2w/LAGJF29at4IwYumMt7JMR3S5RyKHlDAyU/JwzYuJpopFEDwc62n70d9rS
MnmTjGcEjIeX3vO+mu1ZmfuOd/D3GdQmAE8SqvkoWX4l8zK/ZopIqA8Cxd+oHQNlUczw3S/1ij4u
jDiAOudX0/+4H3WGkKMflNnr3PvcN5dCegdSD7c23LebSzaSm+U+wr4wSnZyQgi5j3AdNJ1ydtq0
23CaEk71NsF2xShuh0Ov57MROm/RerBNnzm9SMxHsI4+Z3UfZudlaPFnQIygU/fIYPrmA+qwya/D
gx/TWB1XMOsC+BsEMZ1EzdTrvJnk28MkOH9Q6A+nGsmcpCzdPEnwwLgT9Ob16oROmPP7Naxoqs34
HHKiVm6yntGGaiqelnH8TAwlzXaE1Flmmagy/kHL5hOxa/tPxrt+mVfrOtRI9dD5NZ+oszOxGnPF
0RvToNXmRadv8zQ06+pX7QlWaFGxGzxKZs8Bh0Gc5a3plZp3oYlwf4viFxEqn1Iklh/sBRRTsd8U
7d1FEHenOl9dDXzcy3OUa2+j3c9N8EFbWw9ryhaO4IdlexQ4EDotsBYAUssuwaA/jqSiPDCIaDG+
LQkfIKZbg/eruYEq9jiI381Xlxi7IbsIUNFopAWs4CjUNnnmHAaAIBCehpeBbP8uqmfVzr5qnpaZ
y1E4O6sL+lremTIk7gyaH1lWQsEQxVQ3MnAFTh3HvLm7Om3kicfYnGt9JhkfCQvqlplRDkRrRG3U
aOr2ODgdShexr19ATszRXOC5O5Y2q1pQHrGtaHUJ54J6LsIVHKDk9ECnlt+CtKoD9Kno0ZSQhtSo
O+aeO9GgrRfNx0bJ3yg4B+eMSd1m7tG4+vTj2DsogkB1JQIzSFtHFuEQv/eV+kD2zLmK3zebMbRV
4NYYzjyucd7jG5iomeoa4/oPcLoF1BT8QzD+Vz+pWZyMRgS04oq8E1KH8KP2K7OF8RkLElzioJbZ
HGJF9pq+IWJD3v4i8l4y1xPAQ7N6PdlP2ZJhxnhIKOHT2Qd7n1RnfEEFHcZEeqLFwO/2PkajVTPl
dt6L/gVi7bje7RWp+9pEeQC16PU6nfuNBNUmcX8AUPX5xChIIWLP0y/N5ZhsxgzQM1/aiU1244yH
3/gB1EP9kq1lzBB0AtMn5y7n9QrKtBBtWSU4XXkycKOvLkxO09623PjRSG0fAOh/NqssTLtIw9pO
iyU6tVs7zJVjJRUCald4JItBZPMTP2QShDBEIfYWIMjyWXfFyck1S2zo7ZN9rBUAiwTcn4zs2NTv
/TKxGu5/AAY4uT8ragaC+aC5phueO6hBvOLPFxvjwHe6EV9rEXADxP6f3rr8kPd3c3t0Nyu8SGiB
agqAuJo2GQGMaTyUmhbA5x76sPvqugK3kd2Yrqxxcs5F62rW5b6m/ExcWjdQufpRPi27DtLou1w2
+/0NyfSF9wdEeQdMpIyzmpD1PD2dg8i5O8nCTRiSk5beyNYFCrpX394rOq7xC002s3mXVTadgsLw
hqhhKmcr+f1JvVp/xwqx/kRMXv40D5WhNt9MMK7jy4buc7QFj6WSgIpJZrP7DUpDDxEgOtuuUK9g
jz0v7kxRJ62TMlcwut8H9EjKZit+FMciwmaMUOwJCfb6i38MqzEgThVVX9k9o/GuaiBkWs5j5YDE
0IHWCvlaieKNIr9vHc/Q5LaIlwfMK4s4hpVJrwMeVfOKWUP+7/WBHjf0dsFisZwwicfEV/RkPHhV
taGjWy6WY/YM5jN4x0wxx3E/gzjF3rh36ShrNang9HsTujzRb14nqcuGNmNnkCAyvRFfnMCKAzhF
eWqyMsw/uhqUlmXDGcWH3P1V5gRC38wT/lHeszmkHmt0NzPDb+G4MscopHyhvR5pjCTYhcTn7+Ie
qSC4QpEb5hdFKZPJoJrkGA1zBHRxBiO2qXCrXgkZhvjKFjCRB8Vv94hOHbCj92c4p27vNZrvJtDQ
xRmSu6puFNSzyOnTcDxxukn4yg00O62SPBa6md1b2ne4x3cVX5o5hPhQbj/LbDJbyhg5WbBlY/w8
pEZGwjozPqw6l7LJ0w5H9E2rdY7n9WH3WoX95ZHZg9v2i6Ul8THpfdEzPEoukZ84EoU15pWOJDr7
xyvC+g7GG0FTIdsYt3DkCgtAyILU4QA4sJYaiwcFkCD5fD0DLrE0A2QdyZfEy6gO4udt0M+Mq+kg
uNEikrbxIBAMpirT4NFhsAOHbuALBzUkWo6gxYByXM23oP6M5gGFOCkqG8D2qXcoIHJcM1D4u7nu
kcImCrsv8ma/DeIFW2eP6BlY6UMfV+4+GWiSCxdS6Nani9ek3mKT8nIL1o54R0zhr/ZTmpDzq/vl
0zZUsP7F0BKLGbq44o1Whw/CqbsOOZ8piO7F4RMz1XgQYoADIhYRAkB7oDoEuBXIWS/5KHhY2qn5
qRtjqaz7ely824QIpIJ8Uu5DKBdC9W6fiCnwTHM7+aejxcQvg+1xV0tw50cYTlJ9J8GEx8ljkFae
SvWM1mE7ZB+RSQWRzSQOehDk5AhYy9/1rVlpGEte3gk0gPBbRi/2I8Rfqz1aIKn1dk11Ys39Pm9D
/rQgCBkHH2SEcPsXWBcfbzvAZU/eJGPOVpAt9WgqzwSbzVepRJH+iDLUeoBVK3Lw9Pclnz40gOEk
ASf3658pEhFa0/oqfeyrbyczmW01G/Rqnegtdhtl/PtgQ1cUAQ/GUz1oL2PbMUSq8KzxZFj4Kzmv
yOCaTIsJ9wJJr/svs29DJ2WKu/TW9xbyVxzlUkMSQixIEXP3l7ZuobMeJ9CnrUvFXUWqqT/JHbYD
Lx3HZaT+bu4sssG8FnphghZ4UXlX8EMK+WHWrDdyJh0iEg8CAikBimVOMRd0ydzvrHhNz07qADrx
GYDiw67kAUTdb9WwjSXIAt4c4RYmV/y+Jdwebatd6iluIfOoJZDuIujnGkCfpWstTNj8cI7Enxlp
XoRRaHzgGk7aDQTP5c99NtguQSl9b0TzerDnHZ3n5LTeyeSa4X27I2i6co3CAHndf9S5nIrgbqDS
QqoX0OWbCcAU8Aw5Kd6W/pNBxhmuI1mdFw/2MaC9RgG9dF3FJt4kNW1d1uBbeSK8rDVwk4B9dYRv
Wn4hX1OijwgNRiLwwi9VUiE3Ou5ygyXfIA6vBbIIf5z+D+OtLgHLZYeDgIbtmO2zZJiltjNEJbsS
u+zGPsQ0vFSlAzxDKn3O0m6IfS7+OFDj4c8woTBW5C1rLd686IOgvY5UZsnJmQdPMmkbRBYFN30b
7/m+fWB2AuVOBdrNebBiNSuxtNzctniKejTnm8UJXmaDUv+7Kmmkf7JpqAt76H9Wa+u6RAErFxFP
Kds0r3OXPFdv0IwF2zSEuUdJQLCtiSDDDicb9fZaabDhfsDMzGqS+UlgKqxTWPykLq0DOFJZUKy2
GsOH/KDMrq9AZdHBLOdd/3/ZSXgJ8kuGsY72nnCyrdwaWvCtM62WwSEPF+EHFUIh8FgEXoW59fMY
F/76KEGLBlMnNogoiayEy/kXUGYvZaOsdqr46TvV8xQ1ln8dhQob/bGTSqBcbf3hm2tLXC8L1zvj
f2UegnS8FWaNu9vG2W5QndXovqt5sy3T5pTbE/g3JgPcFJYYj5B9h/uwBZEKg2oJ3UQ7HuJhWnvt
4BRAnzcyhwmoWUoGgbfS2OPlmyuNeuCWDn0DmJKCp9SlPKa7Y+WpGP82/LubTwMTn/dbKAjIaq64
rZDsz67BYzScSGaUJGfXndyu7iqb8fK6iAxd56ffJs9fkA57h445QdxwZBhtYwFwVKxDNycZ/BZ3
mcThtIEH1CsMJxmXhq0bYZqY+UxroaommcpAD87cntDbEnWsDl9tdjBBroMdv5rlktvi0qrKiP2y
2DUlDTIuU8WviQH/QJ4uqfX2usPhIPqcFAzuEQiQKisBRotLbOO5si0C4loK75K9ZzLf4X6jE8wE
q9B1JsW3hi9sdGaH2PbJOE89SjCiWPJZorL+jMBczo1ktRHKQA0jvIcduVJNdzK1odWI6vNmDBqi
a3HZH537MEqHuNqEo3+aT/QtO8QvLHW+R+MKLtqjU4IYSnsU7nd2BEDSLjcZ6NHIkfjnVpSI/bWk
9g83B7B6VFT6omb8VJn6607lA2gmpt2VM7gjwpbJX2P+i9tRlZIhSf+93ab/ZlZOj7SabNh8/ktM
8sDJVJMq/c3/DL8bKxg9h5NwlI85j7YCpZSyfV9IoyF6R+Me0Ze6X87Op1+VwKSV6+bO+yiEB4is
7PzbxcvpHKJtl/9rT2xtQN23nSuWolxOKE7Pj1NXW0lo7d9RHQzb+hT6j+bkD8sRPjbkj/8nNzaU
mgMTFB0n8X+xfBZFqXJYIKOzmKEPXHtfBer+1ZbyAzkCHI/UiudDXca6Y+27EV4bcRY1lEGH0D35
U4xXbH+nj9X3JHeHbAypfI6opiOcEeeff51mzEs+TtJ97IvbVh7FRQ1VTx/VbtEne1Pa8WYihyoj
WqTFIJbaBVbPnfhhlxIFMsbvAOaWnSizOY3gM/eQvQwXLpQjN4WjGYrafafqnNiEFZddVShyErVt
NMWOECT0+siRQUnaJZve6SewzCKfa74gH2bdusNEJoZoLjabZr0dYKC9cKa17T+JUtMGi78mZcQ7
IpDEOm1y00yQsRs1pPKxdk59Na/c/dftT42B58zSD6I6jqbZ7E6SfYNxdRcAhB5p/8nsRHY4Jdv5
uhf7C5X/LJqgbOQ+QdZZntOjHulV5UQLLbkhoI0bFXI79Y6oEtTwnkRNo5SRqfqzyvXbjP6nQice
2ii1iT2TwzDf7rXo+4TH9WjjlBvFty+vlY/3AJ69XfDPpvfVO9jwc57jtAYSCZ0WMKJYad/fDnsN
VBc0lWb4HCk/QsjTjJnsJgbv2wqz6/7d4ShNXzlaGBM++G+c7OVZMTZL7kyGNs3a0qv9afl/9Qxz
IbsCy5mK3kX/4Weq3/YevbUVU2kakxvroNN7aRt1LxGKHFy+CHfdFpcGNNNq4LmUOYWT4T5Wl1ME
yfapa2ld6p4ZNBB1/HuNgLKJfLBFCBJWLST/+8vJPjM3BsAMz3sILWp7sIaCYPogjZpDJ4WESx9z
+fX/15Kpa9mC7DlPbHQvPoO12wONCkZP2V4hNbRkUmkksFO4QoRlAxYTZG0ywljJBXmd0OKxMDGZ
JA8kc1MOzOORYrfG/mRkOfnSFlKeXTNI0xpknT/vgFXwy+YbZavVfo/MQk/MhSxdlotEr3t668jC
bmhP09DI7qOsnRzxZWRKvBVxgFRU5MDM2gvX7aJmiLgWqhpcRd1lePT2Z4kfxYo5fxsSk99SHZFr
ojIHZV5RFjQAEtIKS5WgByvVcNj63EroTwCASXwinOtghlbGAUfieyiahAviJfZVD42Z3+qfrh6N
yLGVwKiCcpAM49vLHeEptOyfylQzFMb9i4f+/XcGkYS5bJDjIwPYlBZKn1FPfN/j6XQRFokoopvZ
WMyk49nj3CCGZ5uZp2QlttBWFdjBbXlcihAlE/DxKPkMTo+TtRPvikeui78rzO2iaK+rngXEMRNy
Aj/Vgde1UDZ0Vq6q1ToFzelPejHKXzm+tZW1gXKFlboVbyXstiZbO4/eH2rxy03XgP4VnlT06UcS
jnUOppNYS+vHhOPELio0ouIU1yytjaAYsWebFNrDM3i+Y5zMVC5k394P9i1a5TH14dDqpLJDHRWo
AN3ubNPRYZeR1ubrgiPIixR/lhM+plzDaHDW0zHd2kkzzcqHevbcrdtGzQf+2eL4uGrHvHCHPqVY
RlGEjPdy/Kw7xniWxvw71WnsiSnbLNbMI+ykOawl1W+nDsbyNHOnIzD4I9ctXbwOyqrkX0JLBxis
60JCTtoV+nUP0u+RresvdrwQqDZsRqocgT9p5i8E3lRTaf5xsLaRwivg4fSZe2UvCNsTVa+Dr8EM
YG+6LjEOOcGhCZJJB84qiuBGBOKAOoUhDJ7cEwC3C0P+cFe/a/1OXwIYRm30sI7fQdCEv2zqwkRz
mMz3Jlk3SkxvT3tjxjCIh/ParPfs3vYejARnu33JI3GLKsZR91fzMnzYi6zTZasVEFrOgV4q+X1t
fiUohc+cUh2IzJWKyyoGI+rye9B80Q7UyP/y7rDbBYO6IM4lQhBYqwTVyE7telBnaAvyESKpBKdy
xq2CawsdpZPGgPRFElQr35aKtNnfe89GuhYDFFqqEWgJCd/2u5EHRgtK9V0tDVEP+UntgIkrjVbM
OnlfBpfvG8Ja4Y9+NTMgRzOblX/ZD1AX7vQtL3ZoNKp28XB2huh8aCUqcw59CCx2R9iV3vBEov9L
PhMdeV1mZnlvgnslBniUA3svBFBL8zG+vFa7WB3hFNWOEWONv8HDktb+xpc4yQGddT3W9TyylYlu
mAwg+1g72iGfZL3w9v7d2MWwq4oLBGURrVy016kpIvtmvmzxMTKOOmYVQtT9Szl4d6WlIUFCtfj7
vnKiX+jaxziGqi1/rNY180Sh/HMbXy60/4E1m5BE3wxt6CCZwANFe+XrFzF6yLalitasSB+fMWZr
wgk2b3C4BTv0SgQ+tPmkgwzeIuh2Z1iNG/MgQoC5Mb31+NfXEBn9hDgubj8+0sbmSzDTogxKcMCY
GpVH5Lu2jU7nx7TpxGcxPnYL0p0mKSZ4ThWVriiwSCoLWZuJC3xZMSwDd0TcOMBvdrvSpf0kv10L
BeaqXI4UG/Q2gTg3hsgvXVxNGi5aQjhLDJ6sUBXcK6mhDLpKIMnlsVrhCICaNXRdQIaV26XIarZA
TvOuY+hAF8Az97dTMf556s9hcA9uv0yDVPTP2hrbPxjFm3t/4pRPe6Jo4Na6YoxURTce0ypP7JsM
qmqYa199yn43zoZxybuzb+YbTOC4E9ZCbyEXAF9L6H/7OUu5xX/e66e8V9dDu6EQJLTigxwdc4vE
MkeGBdIcZKK+yC15RQnXCZRLYY/KWBHx/sc6S5S4oME+d3n8soGkpCqEsFgVkOLHqDvDSZcFMYeo
vv1oLeercCvYpWp0l1ksdwG17VWom1q94KzipPb18wPdsLBwI6KD3chsMITy0PtYzefehEPrl11c
+eQsNrEtr87kCRTJkek6hu3a3gCYDI5hokZiDLGF5Af7qsk1h/HGDjaa5fKqZDjJymPtq7TJ1bNE
Yte6Dkt2fdXCRNAfsMSkhBBJmR98fDAiiRy9unVEdwadfqvmsc36JuKbS/1Gf7TnFnVGljtNylvV
0812e9ritJgv9YsK7KIUVzLIlpJZTNU/9LieJu9sBjHZXObHCByoOGHsFA7oLd5Y7+sTPfTkoRxw
xoo5EQI6T5WlWc6xPv6WTvrYlFjc4rvKE+74zqhNMWHCUjH0rejWMEtXoY1aaOhmNqXZMg6mVgAr
oDUErUsa/G56sHQRVEgGt/7tLO2oBydKdF8oYLc6uuv6DYReAlpEk/8JlFwLKdgmE1848PzJ5hUA
MBHAPsb9WdMxoecsoS+F7D2Q4BQ4YYKMuvt/yhO8DlzANfGJB3EbCs6q+lt5VEpKdCXzksSpLF4U
YO1alSRirFgdQQHB/hVA72uXZDwhf3UvLZGmdfK6DNqIIWR/ouLPrJ6pr/vW/hcB5NWDW/tHxwKd
RMRdMnOUkqnqAg6l/OUhXYRH/IxAmBAOgpdUFxPWTwqMTwKSmkHoDSeyAUnR2hJfH6deQ1PW/qFK
kQIToxR437u6e8m/Bw6tE2YElKoBUcWoOHru+i2+orF6MgQR6FfHvP29vm+SAEzsOoHSmV5htP4G
lebXBNzvQNoxfTeRiLZ96K6u+ljSg7daRT50aEDI5Aunhw4U3YLKusEvYrppjMWojxDm5GAFnokS
GThFUHepFCnGGA9vs9re/J4V4yQcP0LE9AcpzuC9xl8i3SvyVf/EEQLftXmxlQrzaPGcbuimcZFP
rPJ66yWAiblJJAiGWwXFFEa+0SRtG0U8VzFzpV9t1gICtj44d+4jYdOc1Mw7nVZOLunuDBqGk0f5
4LHZ3+Pn9W8RYJju15R1BW29wuqzfnJjwYuy+xrKqNFqzmpqOGLHtxb9S+7EFZlTNGipIxBuRO2v
lEFM4BaOjNBnYItnuWSZPG4NnIw76j+UUycfe5pJFNyKYtcXzU86sEtISPHOF1w+HSo2+kd0/ZVk
62rlbNxyGq0tQN4yThYZmAwyyTzjH2jalE6WMbSqwPWHfC5/bWDPBnQNe+suj4KZwWcc2qDT1r8h
oYYxPiJhpuxRDJ/f0l47JnLNg7/nBq4TUJKtP9VtA2uWj8BV9qh8fGy58K+etAyt5ICjeVS/U8ob
uKSmQ/rEHCAKacjWncnO3U/v+weA1qIndPOfZm2DYprov9yh+ZbegOfk6d8oGywsKPwE+abjQQ5W
/crqnaq64rcoEJfCko9Na1Owd9u/DmYZHZ6DhBbtRXKuGDQJzQN82XQJq9uC7NISrps/8/eqi0yO
Oy5BJwGntNmRcweQhIvoV3o37m4Ew4A9d2q5gXJqqquW4m6raBrDWEJgbpU+VTiIBVCxPASg7EZB
lBDTWF8uzcXL8lRpSZtS0fBG1fT2/u2k2+9ByzGmstf4sTULgh5zogf/+EUR3lwgWuRi8ddg/brL
fAEIW/CzbaJlTZb+hE+nMN6phvJEwU6idePGsJacKVnpmge5fQW6ZbjiPQ3FHIhNfjIpted6c4ho
P3SVVwA58f5nzyDLZr1M4u2lNydyKBBvxIjwKM6LJpsMw4YA43eQG71Tvvaee0L5jeLx+bMQtDWs
pvkvP/2ykH5prd1fn2F0OXplU2JguRTx4DYjaF6Cq579HyuD8EkVWCZ3s0f35Aa4QYTrlqqaU2v9
1+7Nuh2TzHWqFJcldM+FBtzQYnUsBbAqvvWbI4WEP44aU4DAxjqkWLDBP7VWtOR5WR+RknD2MHsX
oyLsikb7hj31RZEjUXgLy3mIpBGP3DFOTyDF0TsAhK29UKEXAMJgYBpTsed7DBJkp48DALdQF0Vp
Ge9Rg1Ue6tnGulAwtHj7zxeWHdMsBriHMDAWh2ixsKKW1U2EtmNQj69UNxsPDCaFyKun8w0M+ZJ8
IqPmCT/KJE27h709AIa9j53x91vycIEJFOK7lzNTGav1GStPfkUngezDIXQnkXUAIDToHQh7GRnw
Hvhz3t+voyI5JZLJZomjPWSpM/8/DP5pIdEzM3dtEdG4lPMbCGLaQPOv/q5NXr8qYgQi7CIsfV1y
Yp1wSH1onDVLnxebCirC57BbHbCT7JFZ3Gt2dbfIhAcsi3+RTYxZ1l3kulYqsCwLtr7Rkig+EImU
UsLUG+emidj1VBV/LgSUMt8OI7WMCJlm+73zAsmbe2BntStK60fKK5xCNNK+uyPT0nFnStfrfjPZ
kGlwWQBlETMisi0KR5IkTrtD+mCOfOoIaNAS5+oWRxZIZ9tEcKFqevWOqQ3IbFcx/DFCBGwCD4T4
6/eZ4cJfdM6+Df4JV/76YeE9ZF1G7cq9Z64F4OCELanNDLXLjL7/316yzg+3JD0Z4Gw8xMd/0Axn
By4Ju0XsouNAOebaSiF+LTgf6LqksCRUS5cHCuyY+3TF4ZzjVfosPGkNwb+LxSW3xlo1fEeiR9a1
UvFdSFY9csx45jnVbLmZEaggWlZJFZcyMm+x/nxZAn0sK120jaHlEPDlwgxV6O3eUqShb7f8gUps
TPs87zU6fACbb4sU42FgEZceiKPhsF5fnPh+nkaNhWQky5RScaAERxvDCdu+4vPcqSfb+s9i0CEn
2RLUzWnd7x87Ac5FqBIyXlPvlpSGpMSJjDBJ35NrXg4jw5ysk6hoM28UEBuG9TAtWv+upm2tDMkY
afzPS59YJcw0CXoBfgl1LP1qlo+faFCPA9ReufIykiFZr2Q03PN5DvC8dhj4AEOL+jY2Qrk0Rj+S
tQ3BpMGxGafj60spCzuP52DuAJ6/s9eL1wfU3GHEhkT6fhpEA30Ez5BdaeBGsurBtGkLoIkKB1Hs
ZILq90iyHk6C3BnQ35lf7xZL0VoQLsd/ect/B5UyU2ACtv1Z7bdh1+4wcbDhfO8eLYbPRmBDbRF7
ZS8kVtLmvHYGvee3h7sW9vq+p8M5x5r9LQTCdumYyhIw7/srDi87nu6lWhn6N+m9vANZCRddBPfR
Xv5eX5gJIUkYK635XlDGUuJzaD9+ZCZ86mxPt65Liq/TimzVhFjM9iPeCuuWrW0CoIKQ1qRvRlkq
NBMWt0+PQlzIteKPdRzihSsSQgjv696AahjCSgh/KM2DNEEHE4SXrXYs1gL3nKmsMxtGZZ11QZXi
GGyK3YHz11ImJBKYfHuOJPoC59vrLmGrPrYbIXGr4cLfkEyQjjNWTrMbDIqWl8BJXTArJ+vymElx
ohHLsJH3WzPj+2TSdvIu7v3lNmnQS2yDzNCUY2xtL4fotCJzRSKSNjyruAsoJ81aQTLFvooPOTyy
WVchApVUlhaEQk3Gs1nWRcovqB/yUbXSg3YK5hAKkXtPq21zVNUzI9A//nxMnDOXmGPQ2e2rHXP/
Cye0owpFYUsWYVsseR1MI5/8TUq3pUOaKNEhlQx9k7h3VcekRFOHixZiIuqPkmydVIYtQCevVWAx
sBSGDSUL1FU9BQQi/A/azsjMBNJ0MQkigai00qCt2DfwKjj2WeOpML2Xh9v4f3Q8PwqDB9fvbEal
HKnduYDXu0CV5v+0h9IzsIqyrucWOu+bBJsYdM6WZ5o/cjLIDHlVMfTu7YCMw4yNnKSuUsRgIhvM
b5B1lInc2R9CMbnljjkxJyMumlax6a2FdqLGSw4cbjTnjYnTXLJ68wKxEcZjqXe4gxIKibD93pFJ
Q2O3YqRQ53JixYAmwKTtP0TganOULobDpEwRkecXKn52WRcRHDN484GoZg3kyeWdQ+UAB0o6Mn3b
nWH3QbtEJ2DnHioljmPZCcbyD/DJg2JQbt9S0nJlC2LjioHO1yW0PNGFTpBl0kwTeM+7vxy0GAOx
r2M66fwf10WQwgTH3Bw2V59dgCN6SJiF5y3ytDxUEhLlTlLU6MxrWlFwWU+WHKNWeC/27TNRZkkX
YoPJbbhtHO6Et0R4hAv70VU138jlD8d2zRkgQq/ypp8/RSl+Vz2tJinIGRwL5IFIlxxNQXV1BNe7
wyUqIwlbQaZoUWPzPjCc+cD0q08N3mg0+ArrzWakauKmjZCfohUTvgRqTdJ0eKkQS8kRbigxovQK
rN2jVG1K09lq47xJlIV61VgFTuXuItC3igFPPTOOh1hbgzYjgzTJjbJKQ/qCaa8p+iFie24wuXes
5TU5tzfkX9Nz6iev/Bt5+2QBq4kca2Wk/807v61gTkX6R3xU6se/WsMLsfSCtO1uHxCMf9KvLNcV
09rSjuL8Ouz4V0j999Xxrefm1qKGvzJ03OEFAjaq16nXfD8bqR41/88dNsOVmKWrpkqxTnL1J5I0
54gKue8jH1ZHjOSZFzmLyhtEBKj7JIUhhVBY9xY7R/MiKLffPUUUuxtlgNoYzcbjMDjeUE9LWlkI
Tg7Srp/hX8yngv6+oFWdDKlQvE/2NyYNsy2xN+QjhIQ+5DVVAeFC5qXRaSgc86x3x9ovYm0rXY8T
NOVRYmPyTctxHmELnGMLd1/OIKse58DP5btbgQrF/w5xKjmjMoGxcVZjaDHhC+/+OHaeGGzN7Bw5
2B3tNlLjkULV2S9R1XrUhzucUn/l4uXfZ5NVWc4ePZr35MnW3ZabiQviIR5GD5D9LK8hMNYCWsvE
UJsBYhVeU4CwTH44nCL+uH/lDFzWbSfUgPmZmZDHp2i6o+vZwi0U+JqKximnNM3rsg22f9Rc3x2H
In+TLAEGwruDkUD0YnO78sjXixPw/YWMBvuWWZGL8ThpjitPlpte+p130x/3GYQikmCuokLYdGpj
ZJyAAljxjSg0RCymID97fKpL/5yMPdvNpomZvBiWn67r/wY1YyZCw1WaNUinq5trN4lmw1FGiDqb
s5vuRaULJ/YdCt0n2JHWZFHg6nPbeNqZ5/d3BaW0z4mPhYrZEtgX2JGVOsfxcJy/FYzgVJhJXy11
6p1LB4bamKJ6ytbKT4KLMoIXb7WIft2s4qCheDbWYGS+D1UzSBA8VEV6LfW+8UmT4lQFtqKSBwlT
u0LPUyZNQVIxp5nS7QKJNJHKxlnRaKDibdmi7sD3I0xyok68nW+6+CMQctCw+favm6KElKBmXXCs
oOeZwgoDtnul9wzJcr/c/mFyQsuoZiLqh9NipQQX8IWMcYCOP+8fDZyURMlsCnDStqUsIVHsT18N
F62nlVyKWYq9O+5v3MS8mMyQbZBVkfQ/50MDfORLOLDYIvntc3wb+Db9hOQSywOs3X8LTS17+nSe
od+ITWC9P6g/FGYO1y45YaFCrcVr0eUlNcXK2TggTxSMYKjY1mkqh/g16A21X7sneLRMacwl6HvG
znMHBKmSIUpcqzwzL3HCeMAs5m/IaUc+WTr3NBGIaD+Y1b9TczVgHPe8fdOykRDxB4fuOhSx0uSK
X3m6T2oP/5no5RDZ/LxAH/djnow8RDT7km03luob+jMmwBdvck7tf6VyPrDdzVATkNFa6Uktcvt5
6Qro20ZH04dABx2nS0PmhAzkko3TqBbtO2aTwm+R+BW6/RJHU6eDkFI+VH4XF99cSUaX405hP17J
x0IpHCiQZ9CIqKQYVdC5oLOYtxVzSHuNnc2tGK5DywKdXzcOOQhdA8vKelATnwpT7AuRcOESaoRm
hIP5zO/HTj2d8GZ5WlUFsabZ9yjDvp6nWCA5sCN8pTTXGniVfsynrRPPMXbH/gMI/NAOQ42rvELM
zK0WYmYysG6d0sNuKdYvPowe6/yK9sI5LBr6OQiIIRTr/JfYhsBxIF1dzmP+hcK/erfnC4W/fa1X
17JaYKRqdXG+SS/IdSTu6lRlxPz8miR45nOH0u8Kea549J1qXf/Br0HtnqcLpLbx2sW3RimmCgMp
8LS2GxnL6nKYxb9mzvwc71Yt0L2H7tA1vHNUDpOtZfbnGjiKxKzdvedS6j2WCxDnxFRnQWxAceA0
BgAaZJs3iJQnnIpyKmPfRX3t+yeFTjgsw3KwDlxGZ3ZIDwUtuHsYmpEZCLravqjweZ8/DeIyGXfj
SeXeoo8cNNFZGncN5cRF3MjecaNjtQtkwATeZYFSMKVCEsKFQqjSSzRkehsQzSk+zBeLLXs1Mnm3
TCg300tDiNEiMFcGuCotb7HnUwAn/g1KjVSHZnCICvZGt+G7KQQP92TI9U8zG/5ARGZnEC+vsWJB
8GIrW33HQguhpP+jpWUWHOSWZ9Iq9y33ylB24o/jf+RnuyHV7TbwZyy2r2tecluseKoSnEHgcgTB
5ZDqaOnL08aPuNd5SkrXtkibX4p05FZjdPl2OeHRNOVDQrhGrErKQCzbPfNoMje9mmAa59cA6ZE7
KkmfHy14ji5xqsjPCFMOT33+tDWw+xxEsFhd8inLMaBdV2e9gjd6aPd/Zd310kGfL0HAP4wrNlou
b8m5YYbSH1HFQeYqGNd+56D15XZoYy+dgNn46fhOxVgs7v45wh4u6cSnTtfvANGhfytKoYlyjtEq
lhYhmaVQEgd18xcjI4LBJX9wA6RberBBMgJv4gXneFL3fy9MeO/+iDpgi4E2eQh9CS4wEZx9QBz+
XM02q7CFpKmgPbxWREjz7h/lQp08HEald03eIPjXyGSztma4sdTb2vgdhurihF4p8WApmWvXZ5jR
eHnCn2LTA39TBIUNdGI1DR6suKEzx/kj2N6iNCagJj0LENn1klI2R+nAU+F1Bm/V2goJDPA62sSl
J5T7HpowGdE+6UOKMvLwUMukJT0zmTU/JgoTwFAL6dVZbJYKPl92Xd3T9tlZDakXb0e14/EFCW6Z
tGRXeMS571GnisLFvv65aozMgJesTo1L+8ZNJLi8t4Ri7bmOi+5QklUybnD53n0MAELqpD3De4zc
StnV2SvIqr+QXiY31SuPR4nSKRSh0APwBXhx3KCoMNAJCgGzTwWm9fpphYmqw33N3HRjIyTsZ55m
2Q0SlusCwlTnbSK61IEWtGifi6pD4O3MhPor10ar7LBzs1ELWWh7sEM8Djx2e9NW+Xml5o5D/Atl
D+EpbHzQkmHuvczwNCN5JzvHCbMvoeMsqOwAQueTRXlFZ6WTFwRDl4pt2ss+r5xMT2IEblDk9sRN
Z46PBa53/458OGUp4T4iHf2PZyHb5T1dgollSZ0MWjnl4ZX2sPkkR1mmTZ9FeqPwcXlho6AOlfWd
D7RhO/O61hoDBDWdTVyno7QhNi56WidafCHpNEfHJZlatv/dA7oHPYpsWLSlxCdc25+4dTMfPnNb
7QfcS/AzjGHihHyV1spQ27/wTRhqRHAtkA7SJMzCnT6LL1s7qwva2fZiSwiMFZZ7A/xeB+ScqxbI
982BJJI1vV2tj/ypAD0+oDv+UL87JxNTssm+DvIAKScz+ABfNcGUMO4HD1ASKI573nQ/wfgNz2jm
DD3m2RnaV9/RwUudWqiL+rAfUqQbIk0BsSBx5cVwui3R+fZtfhYRsFEVjZvu5177MbRGzyNQsVbi
JKOM6ys4mIEgFX8h+Zugt5yLfPPdkQkBhzUm7o3w6gxvQLcJc6FFU2f1edvVWTcSEORRnCAiIL2R
yHKMALDITapO9QRbLlHopbCPGBS6JHz/QN3qLwyXgw8kT93R1IoJKlBL7SHt9V6bUsBFyv7aBbKY
4sHiqy2sXLiFdbwITFlpGUKCV4JHAAauFzbTnJSfEyiPDYRjVsaRlwZrImxE2HlzPaILc+RyWr0u
NbNgC0U5A9AsODQfkzbpog5SqTAhUfXJe44JUrdcNxu0IE6VT4N8IiKSuyFjTAleWtAOywLenKEE
Ibv+yLxWn8xnaPHvCzgtvk+ifdwun8gNtw6oHligszgx0II85k6o/yty3ekgKq5HdV44XbJvvMxz
LXBudCbjZegqkxSw8a6MlABwFyUG0ZtvEaBTtQ3jZ+ZYszPepbNUAV3UVg05p38oOyyLDG1xY92a
Blu7kX19tS/+b/6hOG71sXLg1gTqi/T5pMddsCZj4NyLdKYOY7XZjAfmKFnm0GxJ5HP7/n2KkTm6
CCbX3xz9k5lRDg91Mt9NmbiaQIBvFbWbwqwphrtbjMPoP+fPdznLV9O9JCtnnfNCiG7GMY0M1RjK
EQMDpi6T3FU8dRz/T35b3TZhR/roiRl0Uajmk3dHl0+kZQxcghgWVFdHEaL5oF/ebtTDXjnjUIr1
h0hT/BP2GYc8KnFoGtSYs1OFC7uQvUfcWImwuJS4+O3lXC6fXRcHyN91Jr68AxxFyUXL4LEAjtY0
3T49IA9sZVNIfY1bi8wWjgFpuOYMstHPMI2UBpAVI/lRxTFc/I60M08WhgMaf2TTqiYk+EZYTGOd
llKX9xFdndvAtKytafW3WGiOkSUQskCM0QBUu4WpYyTrmACW9LTpYzFsynNyPIP5TzMFjaX6D4mc
0M8LE+54o3G6vx4iXSg7/szCPtK5QiSXTH8uyv/ppNQQWEfJOaibBDxxLR86fAJSInGDYhqWczgx
NEL2svrHJnkZsw5/KiFZykw3Z8OiPxUtdpLGnFKyOYchcZgabstX2QqpN6merrDCvksKixbSWeA/
EOB+cM+danDsaNTAgsHdQZndj4B0JaPshY9vMbakCL5mQ3e7tGec3ps88sTED3GQeo7pXqCBzt68
xWMwVw6H4VLpKCA10wLYMC1If3tzczbgWLRadq5mEZOeVTnTUFs8O15GXKYOW+jyM6xMFgZgYn60
YtfY+UFg/uHSeLeR/9GcVH7myPbE7xgo4J7N45Ec0HCSRbXSVhqt3cs63Zp86sgqRNB0zaWKu6u+
n6z8D7RLUp8O3pRrbwtQbqhursDrgVBLk3p1xVPoZo9weF0jyip/lNdVB6Jmxy0FCJbB8iSI33wg
tHqxATTGSmO8avvflX+EIEETCrnDVaQsvzbD87VpTq9kSuE6O9SkU6gEsJ7BDZpHmRU1IElnuGsF
tjCpzrkYi3wuUPbABpubWDTTgromVXbFt9UWG6SammbLdITXTTrnGjXej3WU1UJWGEPMXrn0O9Fk
kggn7XVMrtzY7p1QLJPTkxguK2eie254er3wNexjBJE5nzQ+RzsgfNUHbJlKFcEju0bNkEKf737T
JCcPvT3GHRLFNNHLt5y96LJv5Slvoz7ZHRBNLSq6nuzJ9ng8yeWY8gOq3P9NLFQrHQS6hclvQqnT
VP7mr2Fzj30vITb3iPU+0Jxu+mqMThXzoB+vXWYJxyz+awsluyhGP+OwH8xwM9TSSOCaEXhW0IPg
mjdlw/gJTlSnFNXmFPzvo+NESC3FuHGXzUL8GV08txTQ/IhDVgBnJdnHENYNTC9kRfjdwUkPIEFI
hgIVJysITEtDOcaasx1LJu11wpukbolJBiVqII7Z5oePc/qGCEueKP1Ud+DCiO3uTP6r7ZSyxjNf
mW1l7+qsDAdMocWDQrI7rIvvfeAu10wlsm+gPNvZCpu1VPr7C84ur2Lic9CFTO5ax8CpgeGCqDiw
G0+dBLzQDwkJ9BQWgbT038MG5IDIZtBPdqBIrHuVnWN+i43iYTB5Ii3MLoO+c/RX+hIphZJxvgHr
thtKiVa/qCwOt86uxrF/tdFDWer2qdSRWOkuJ0PtT7UH78siu5BPVr06j3EfeMHnasrLKDAsbsGP
5eLY8Ik15E5e76mr40oSPwpHtpHZ1lOiZl5HEy4rmrY4uCi3ITqvlsB9xJp+evfWN3Bil2aJZZ2b
Tqley89EMF6pb7zHRx4JQ09cf1QVEMZJcxDLpNy+E8BxM6xtE4L/zEyDpM1RFBtTviUJC7W73d5W
vaBFN29nMY7JiwS/16YPXr/ncppCPiB5qf2NezF5o/8UIpDdbzpe8nvi3jxkxUvaQPV+Ml14dYDw
iIRj7pozWsp0Tuf9qFKVI/jqgPQ71EQOW7lC3ZQus9k4RZTLZpVKn3cDeIjkh6WH9HMUrBp+mUcG
AeQzG9vUqvUvTWIUgSfTLGiGRUvV3fsIQ22gXzqEtBO2oM3sub4ogS74ltdJq99QBCISR1adc4Zl
eJbqfODR6QxokIUhvnDif4bE6rW6gdnsacHX1O4AI696EpZur57E9kn1r0tld300TqUwCXLw+5+a
jOZeZE0iSM/9hlntVvfzR8uAuPBBy+q/9BeaL8wWfybYg33rZzChAtDiEDbmdam5LH4RoG1zI6Ur
9vSmCJ2i01YKa8Q4lzlow17pbUdmO84M1kUKAKwhAi125NgfUuoVzO9iuXKRwYKjYvo0cKlxV7hU
ibtq/9NBrVU0sYM1YFqqVMmLKXZToBwX9bP0pgvs0pISiibJoQa7u0fbmYCfr3YqcaW9drTUTckc
IH0qNcEmr7KYI5xgQlmZzMKIR3nxh0/oGD9h+opW1UCjVJrN/zRsg2kIRjh7C7MAwS2uXLESbIgm
3JWn3Cyc3hrOdMW64vVvOCx5YkD4PxWavv+sJ6EBtzwDY+ZPBWKjnIKG/4a+EQTLmTWco0F6KxOK
m9EwC7b4EgLgPa4rvdQ+W75gwU2Yv43GsUny/4Li3iqbwAUeOZ9nASIo5F7J7T2nyVD/FORD7w/q
rqAkbQx7RROLuSAlvNQNBL8izocqy+H9RFNaDNuG2usRnKx1aT2O1dFoaMhtpzdUAvDPW3lSGNHu
6D4g5UwLNnvMZ3pMQbE5wqU5I42Vf9YKqg4/jH/EWEuukVlalVtvS0mgqm56A7G9zNILgFBxur7h
UHxHE55DxbSVFa9VswARcIoYfIKjTwvSIEKSNBYECfSXQCpeMNMRRJV5Ay9aVLXz1jDpl6z+aFEI
6xwJwfyNrpixW/eh/QZC0pUFMuSRgVyQkQ2/2/2O69vLiDyNSVKWnutWyudP2X2AWlrawiLmSk+K
RdiExEb9S3RYFPqGAtDRpHol5oeWrUNWEUDcHQPHXSFtppWOZJsFN6AuaaAkZo3xONRSJrGDGKne
78J7jIgQvsrhwIFFwVmEp5pIBcL4VzX9xEEVnHIWcq6ywaDr26H5dyiviJlDvDIo4zdUsBP7Xlbh
4x/gg059o4C/Rrxe6Q2jIWo3C3h/BssfqS0M7n0Q0281jcD9+1srtemPLWLeJDZU0AMBIM5+9glS
zgW89K0ANTC+CRLKlWDPwEypxkZc/VfdSe3S5XQEgJHLxcQ9MprztmNzpIgPGZz9eYVX7kspZVRE
zf2Se2fuXnHeSeEip6tGvVgHFTv2ON60oVzuJS3qr/weYafGuxuocZy+sOwFcwdQ2Zgqzif+ehU1
XyFbXjge1yAsBJ+e6YKWgeDE1YaZ+gQPs4RdOve3c2WFSyKBN6nwNUwsTZNxzmdaOGet3hMq/uuT
JW4/oMrFyLNaRCsj6YHXX2nKgUxLbldIAyoEgXYvI7bd50piyjdJrnlLqxUeuubiMo6mlWGt8a4a
rOuQwizH5bfP/jXctPU09zCzBlVZVW1hIeh3ZcUO3LxKSfiDhG8xtYsHIa5K+Gzj32eqd4ZGkJAV
adw4f/GWQOFbZW195l3W0RQBgtt8tKlahrc0p2RXAFO2vvMQw73JoPdJa0MWIY9w5o435SQwdTHq
PeJTdNrP/CbsXHrWrDJw2hWlwWImuoarn7+x6/Kg1u4iqRbZHkeUTaNkIG+gOQ2xw62Y5fl14hEc
1A+UNbOh4qVZK0NK2LwLcDEByP8I7cFgkrFiTHggrMfwI/tBSDpl/J/MM2WU65yym0+kwWBRM/3V
uvjVgEbJeRIWSZHeoncM0WMnAVxQt7yRHDwsZURsjex3oaHuCYBHPmwuMraCbB2iy0YNu25M+hNI
KvcpqZasp9h4A6sExuPF4GM6OYx0r0yiLFbaqwsDtJS3OGYyBeGww79lApZGS1jfkVffsJPIvicL
WDaG/E3cihYaslsXMKNpA0914TsKWNRHM4ye3zgzeTE5EXrPWxEVueqXLnFCxvCT9oxhIWO4lft9
KM6pVWP8ST0ncSuI6rsk68RR2R/MkHn/alCul7r218yWLyXt90w/dgFgaTnP9S8PpyHcS9ORKf8f
FciYFlr1rILZE29o4Ttnxr6r8H32bmEcYFvWmq5hxszrVf/q1qSjo6OtW/LNAEDQQ2aU20FI5Bp5
B8UMTM6LrIIICaiPZq7Zv2gICAQmol2q36Nh0flKJU5HuAUzDe4Xu3B1hciJDo6urKVviBW4glJK
2Mpwb1YZOU7SjiQr9BwMyaOmRUucEpg2KMS9+uyPFd3ctVL38DSFXZWSQS7vwx5PXf8DxlVhiLJ7
s49SFOmYL4mPtW92tWv+TLMS1VQ/G9CafDSWmVGzkOYC940a2bLUFNrDBaRyLYZ4tqy3j+ExqvU7
bk2IHZMdvEZEG56HpUJzn7N/itKozRAopxII4CUbBQ8UsjothsczmbbhoTsu96MOVH3dRWZKP0qn
uMva6x4810hVwhNgcU4VNJFa6kzmVYEe/tSaEHUQvuzgrhkDzlfYsANpqW7HcYrx/pPEts5I7oCR
efNY5DmQp0lUFoe1WWUDOgpScHBuROAQY+CIDNNupghBRyRht4I/JdK2WcPxJ05FsC619lFWRY2U
1kGE7SX9RkcagrufYbTKqUg59heVLdohgy80IzYP6T0rK8xyPemt6n+yecNj/hdhMOiKQ2Thy3m0
7whxjYEcc4GMPYAtJaxXVrR1Y3yWMuJ+9tGP0rtSHX8BCz/g5Sh1bazfJ2DtJUQ78YjUyrJNtjuz
BXbjUytTliKwl+cwup8uimgKim/0ajbPrC32P3MIQ2YxdWO5fV2H1yulr6tkhwcCYCZN3Gpw4IwI
Q2RRJU/8M1ijj8J37y0Aai3huSCpL4hWmTrW15YAhaGIEd05IaSLMx72X4lWeWGluT2RyDcBJS8G
UBUMFUzhW3IzA6eUo6qwrpSsDUN1BNqkUx9zq6Mdag1RRzDaSmW5YCWkm9Fn4TtfgfoRhaMFlq/P
JbWykC706i4olFWsL5tMnpOYGcqGlXEb+3o0cfY8UAaoonXUQmP3O67HfxgdUOFmVgC8/FwU9+S+
WJJAhFsR9+J2GIxpr8II+EQfxvPhtB146mMV3m4qq9Au/SuOXMWaK7tMm92y+uP7UqnO8r7FdOB6
f9Ek0pVdsYhEPlemzbUQQNVKPDw4Ntc4nIIR1ecMiqw5PeYaRt1KrK797n8Lo7gevjxextfNA5w4
IMJ/Ib1N9u0+fthJ9gVA4+NlKnGlZTxjzkfBmCvGD3f8G+u62N6eR2wd8+B2/9SotPCRc/+PEWF7
HjCkMeh+6MjS6wHiYbQM5y2PZAt5nuiOnxQlk46MctPStMs3tTRrdzCn8i2klFkWZKM+R0RC3HMt
hAQYSv1Wn8xFWR63kAwO848cmx0hjdsqyIe9mPMocwy1QUCG/pjjiBDg499U+MQxKkuBs9lfU7Db
lGtnzIkwHuw7q8Z4Gz524+MrPMXHYyR3ey46zGs9AU6oySrmR1fchdCuPo++Ixpq6k5Ga3pDP8tQ
4oGQdLkR7UHa6hDSLxguAY+JdCqf6eIB/kVm+zC7Tt0vYysk6e0b6adn9qgr5Ii5hXLtcgFaMnL1
8jI547v3bwSWAHE5hAnAGAPD/MmadkT6UDOqX7i7cQi29cZjKFG3Bvf8bJmaFjK+kAcloKZO1c5B
gSP1MHbBQLj9OzkLRHgJoUZenTekzgW3+DRT6uGggeJ+uxKINSzR6Jv2kmo/VmtHDLbs+Szzvfqb
Jjjy9j83lEiEHbdusuUXtowlcJJsWsGDrhQR6SBxKiHH/hDd5qMvJXr/SBnm1qjcqu3fJ+7vlk4/
q9+SdyZlD9IUoQS2l1vw/6BtYUm6UrQDeHAxH/cDA1pVZcjG7VQAqphZ6qUCd2o6XsdLiKQo3bno
9aJK/uXpeT5oz0BI/Ky4xT5XibnLpG751pcqB6B2jEMRUGd7ZcxLYBiyeag8nl5PVUd1zNEgf3Kt
eAWR8saIhxnCHm6zF2tqwVczGp87tS8Cd/ECeyNQ286bpNFgmpnzEZ05UZiEDwQZd3x5lfubgtqe
aCwfswYfdhTgzQsS9bhqzsim9BNUzI2T6A0tLwmuzMwiYfPXex1qUM8vbj3Y6JHYbRgBfOaJFY1o
F5DSi+VqrgFv4qL6CRXSgx6MseKPYaJUaPEfucN2GDuivIAn1LBzGjwEJeyLfXZWvJOBBDVwD39/
r8TAFmFv1P+Pb8UvLCK3yl+BeTHimzSBLMkdfBj/Mo94BGXuanfMtmY7F4EVoBYABYs6ZMBEPTGO
UH2xNbib+WnIT6lSMH4h1bAmYFoGvWvBg3bwTv0Gq81D1zGSnq3dpdOV8jvXVmKPEDdHb0LzW12D
Cu94eHjLAhUPHxmn9vwfYwFR+Fi1h/XzQv/geYwn02ka5Wydhl3joB5bCl1zx76dNoTjfqLjRpf6
QGY6Cx1ySaDzQadVReK68FRiqMtrerXKFt45IaEznhMnOqvNI0tPrdAw0ulKy5CMS59ZgL31+1Mh
34epMq0WN0Nlif9QEHo/JRbNx2RKhYGgcUo04ThXDWZfFBs1a3SMUDPZlka2+ViHol2NG56HcmDX
XWoqorqxNuwhFFpUqkzIrViLtPopJ50/yeAOENR/4wIYGKlxYnHyf5Z3bMbI0LwFrLiLbFelp2Ry
uWltAuRolrBVUJmHwLVqc4W+eFquVKEwrEcWk20tIdptfyNQ2GlBkZY2FRlfH8L+TGEfDhdG7k9t
f0eAOVjFM9p6/ionN1jWb8ICHGe5bGd9qbfWVx4bBjhYiDgGhTD1W5Stn7jsmSgCD6870jzFRXUl
WyRhff+6xtWCe4fbKkEsCjG5hiFsAhh+JOBx/WqDpK8gv5l49ywVJ46dnLMgnUj7fjuNIAnZO0/N
d3BoJhnASRpnNgl4Z823eH2v47D8DkMMiubdZKOqLj5AVP/E5OQTw87HfHLl9Kt+B4SO6pwQOGPr
ug9MtJUeW4ac2hyvpyp5/FY1mwD8vajt847Jwun4frOU4wtjmKPrLKqu/qpwqUcXTYsIDxTgikh/
9kxlRND0WXkUPbW49VpxHU19nAMV1IwUryZBxZHCYH8AQyrCrlhlP+o/E5H4oraecjcLI9+JdouS
sBPxuPxMGa7/zvKpkTtCotqdTI9q2xFmcVsSGCOBj0fJgNakdopau+PHTaPrPfLEjAiRwpvmZzqc
QCRWP+72Y4srFd0otCgbR0ofhT5zTPQ4aah+3WmcapYGEsDKVy2PMAPIqfA2y3EKKssZd8SmjG05
HYBOEKZ985WmiPEfxl/msaiDyubZGggh+/hva6ns+7j9RMeEFok/LYkTaRoosmXhPiQNsr57ilwz
CK1uWLrFl37ord312kbwZdqU6kNrgkQT1SYlVDWlF7yKXT5jdosjiB/Ut2BDLwVDRYOAKkqNU2rp
1EjSyQynsmvgApb4xdeRlu3EsKJebNMZNvHECoBlpwp5MciFUJkA6emNKLVgPZbkEujplvcaNYXD
dHq4GOu5NtDu1l+dmH+YxAaPK08t4kzcpo3ARerGrESaq0Lu+7jEgmQREXTlQ5WphYCWuZxD94LL
E+AobS5PBMI2MAOAGZo40a7C0lKJy87U92Hh4ZZKmB6JEuZni/KWlWpLoVXBmCyhVXGUJM9r1+6d
HkdtWOLN8Ht3jAAv7cxKIcZo2jp+pF/GVQ3G/fobDkuMBVG4SyO80LL9S450ArdhNmNAu83yvw9T
zGDPBDfjQFVuJ/ljOkY9e3199AfSqFhOwcuz8nGcIJtcFtSqloKznQYcq3/ztripC9fHCXIMLIXB
PvpZJ7hStp8Rler04yjoogO5nB06VFoWVq/i7OqXebhbB4KPSkkjn+Kwth/+SDIDaUcXb8/GaL7Y
vGdmnyT0lU75FMUrjZbahz3bMAj+BEHhKHiSwnbGrqc/sLFtxFFsOerG4TVfE3ph9kbbbzLp6nxN
ko68Lvfgh0U1DvKM9vJKfs3WcLwXC40/QsDGTP2T190iomlOJOSfKU7fXRaeskq8N6VcCpMoS6EK
5swMbBrqV/jVOBfcgWIcnZ+d/mTUUSGot89pcpX2RBEcfiHV9j0m4UbuWOb/neMSFcnwDoddo2UO
7SOXYfQdbwQOOKzlDjnQRXgkiDlS7VngQgcbuyHIO3GxOStk53e/JqPTDQiXn/iU3d6JzvGU0T0H
3Nv7A9ar1I9F2+O+37m6MJIlJjHcHDkijaqmOAXyyZ9mitDG7ifLkDDuulg8mMNtuQHp4l4ehEwY
XxFupHUuz/R5m7p77KWShHIeZW9pitYiriLZko92tlq/mGCZj0gKkTagLRONdWo0Vf4XJLvtLqiT
JlMYEj/PtegHt4kl6iyOF9pFp6GHwmFDmjcJ+9ZYOzYxaLaq0LsgoqPI2BLtO6cb2fcHdLG6/kK1
VOCc5jgyCYpA+jj1QbJ0PHazK8RVo6h1QSbyXHV8VEtqaEDJVDeymL/Q3zsT4yViHlZwkTnencC3
cK4u+d8Z1UvWu85RnPP/5AKPGYw0z8gBEEnTmPuwOOMUVkKRhB97CwxnHlCRUXe6tDT4KWcjqTnr
gI6DND8HnHgzPjF6RPI8f+0mfQNGZ6HAtqTOAr8et4qOyc7YawfjUOUMQ2anJfJKp0yRWdba108k
CMjMqdHCzYG+j+jqwg6SUEDXoKV6Ea2K/kw/KFKlQpzN0fnB6vB8wZxj6IdBAmJjdFwJvAIhc3/T
Npl1/OZkgX7cBPz9K//W01+/G4130miCI5+lU9Bxlmdmp/Hcq4ZqxqSV016NNQw6t5GvC1hs492g
wfz3Dr1oEXj2WctbXpmAJ9VApZRNWDzhtle4Wqyv2BR73xb7rh7/MGFwC54GxjuYZHIco/IfcNdG
lP1wUDDx0EgmdBMO4+ORdts6Jud1jUobuQDlpsGnTKRMCx7hdRFiEdGpMABcGjIsWq5f36D+Vyxn
FNsOY/kB30JVg1TETuhcN+B7Zpte9BNLIZ6QHOYvKKVre9QWXt2OXykbwYwZfthXbNfdbGv6xTEy
iKZwGipcUkb2onixtLEY1L51Vuaba7b6UW/Z57VQKdwsRqeSdKRWheYjl7xPQRc1tOzwshF2vMaw
DF3PfEPPMC61rBfDW1B1xWp1KVentyX6F1n7ZeFtE3x+3OS1XiXBXRGLJS/2MOKoyDhNtYulPlFI
vrTGhh9CN9FNSP0GW16ywqBGWLt7Rrowlpg6/tTkzDYwBIy++NZUrRge/wkHnrORT+fLCM3sOB3Z
NzlQHwCIAUBhZzBh3UcZwqkwvGZHVYG1SZ/wk+bopru0YYw3E5z0Gr/FH65rOPU99jLDxJLqFe+w
CwOERFE94mMDt1QK99qzqX1m1BZcECS4TU32H1+Do3gyasj4Zp2IAYrvcEulyRAU9sbDWw1mdKqh
7NcVZL3zXvA1p3/FdEa1ue849E46sLFO7j/o+G71r881JD9pEbuM0nnNVVjhVPUnlHUG/U6dQ/dq
K5WiLMu0CxVu/BliVPoFxXuXgtTqx+sSZ8atvGCElncJmWntxUXxQiMKPEhiWmW9GnQAWCc1WBCn
OZB/nfsosmEOguoo9gAUsFROjBdvo5N96+NpJ81a1GqrZ3YZ55PkU3JPHaChcBrK6i/r3l4O20xk
gnNsj/vkmibrgVFcbV9wYGSKGoJqkldDDWDdBKcREJQt+h/rJawPEi/VjLwPh/fgsT1c0sCvM9wB
M2IxAYGUq1Wn/x2JDwxTCVhT+nLF+D0H5kVVecnkyfhOLdmMWmy0tnkDtT7abXl9AttLrdrXHK7M
JYuzfMrm3t26iJAv8zuKAYJu9n4piy92lzhwa7C3C8XpRrBcuVn60Fa2ldfEnPs05AVjvFRX3vhc
SyWfm8C6APRRedyZTLwolj/jEA9r1E7xCWSg1cQyPxy8VQZI6RoVKRhp45RWaGyW3teWEowd8uIu
ZwaI1ZAF9d6MxY6ZzGIo1gU26/9WUwA3uJ+phYoVMDE8MPpHrb06vKeHcGFFQ1aae70ybzCmpFLB
EkzE4BxI/u4IkIVuR8+5N6IrGAypCiGwChgdI47mnSjM/NbepWN7OP4HrkNu/+cJgOKwYmJjdnaT
ARmfLpTUD1mj7wiPecIVb6vHaM8q7dPdrF4OPF3067zspkMRYOKM4F0DTTWlL3lqSBmvpLk4UFuY
Fn8zImjXeutkf7XlwbwEywEzBT9wG/7Kr7NCnl0PQzXc9O2RVQ6Br0Aw8NPMJUJ+T24YcB7g6Ar8
Rjy22N9Yjdg6t3lRZ42YNxbgMcorLSz2Qy5YxoErfeACN0CcHPkE+6KYkHXK2dhVH+phkmoXZIXi
mNgAP2+B78oDPHytKgFqlsRj7tf+U4ko2qlGnn1jP6TwN725Gyqn63SzEiAua14pCoc+NHakObSU
TzP2ggj5yflGT2gX3ku2dx8YDA/iLEjU8DPDzOHOR1yX9YFLtl4Buhf0l1/rEJVgqxPqkZyEqr+i
Nfucm/EYYYMtjr3L5HVhjY7mwAHie2RscMO7YA/x3eNJNCcKBg3eJP6zaxDLzfiUCre6aETovFZY
GQVN1JmEEufhrydKCeAtHbrzROKXsixu7kOsziukMh/L3WfJgS17fg5DfdM1grMDhWwjSdB6YmvF
M+LiL0fxg1s4kkwAunsgkyOMdLs40QnL5ZApXMm3sZapp3584PIHFKJYPfQsF4gPociUSfrUw/uy
F3FDj1HQkvcNxfQ5npFNNDEJCdpu/nKTf3F5jQrWvU6h1EVB7gUItYZ1fNhwgroc2hEEB0iZj30g
pd4uF8SjolLuX+x+J0qMRkOOFRfFajKRC7Mky2/EjaDtiZnYWIqytCJLZ2rbZsBMuPIanJqwA/0p
Km1azQpIPDTHvVk/tFTjW+PTDkIM9KUEHH8NUQNISTbTYeiJ0IIRZZSXeM8ij2STPu3FKVvhmGR3
vXX5XkUuHemgzblpArbGIIbzwJHooQ4rfWfwkiiLXfylto+FZ4GLpgONkGPuRbHqmY4pImyhWQSR
fAMs9L6QG0J2ICW7X8hLlSg4HmxTg0SK9AZYbjlUp0e3UVbUIUifv2fYtmAhLcNPGOPyXQbXRmVN
+AEQvmuphtYbLSdrYkHtLX2TAzwoZPzolg1k8GY9G9BILidZ/fVrP60g07VZVnbvh+d8kG5Uc/If
/nk9XZaL9XY0SVcrbAEL05gdYgw3W8sCp27T4r2xhJbhtMtZBEOL4RfW/hu5mzF6mu5MRdAoWSam
6F0Q76mgftX8a3Fddyxpor6Da2YmnTprYeCCGy4+RnGusX1BEaJw6uda89WQqDfEsVaY2u6PAspd
b9qulHXIY2eiMtSpn4wjS67L5pxNbTcXBDk5qSU9NK9k3x//YdusTAxADKaT3+ePUngSfuAIxd4o
uY1nK2rqUL0coHtwtu74kOo8D2PlmdU/k9Xplylb6ivmmEMIH62mFxvkOfgm4aFhzgyLSXp2lBFK
F2mFiV1Jzzg/CSTsnRnNjG67zbE4HSc9xPhkZF+R39Aiq0+tFDvWQsr9VP99TdiCFFGo9HuFa/uA
K/1/o2PMZ/RfgR/8PcdlWok6S84lhSawL78obhAcbZLX7hWkf/fd7ovjl0dttViy4/gkYvyOw/Ed
Cj6gDZ4/HOfMq4ppqyPZ8rQWXqv1nm6BlUjWBgJWTyEc85roHG9teiRTnainSaSVgP+27boRSOqy
t4OvOjvb1TmdftKH67nxQOIYA2OJPOt956IC2raBBp78lvsPnC/a7XBr/cEr5/pXaQN9W77oCe0T
QDqduiGt3xWsxqLeqBlfMXYxv9B6njIVkSs5N3oO8pHdRPkdshbVmzI/hqHjYqq7cfrWk3oVTNVV
ghgoEY+aofHI6Vxvu3ru8oCJQ9ELeWp/QYWLGFgsldhngj01VpmAQf4+KKbco8kp/d4WR05Ju89h
8sKYHDV5nL1esCfQhub3BVGcjkIIK9mgbl2uY7cYwJTl8zXlLCjlZ7tfx2Us7KfAr+SArNqXEWTe
goStnhzVGf/+ZM7qCGa2giR6tTmhU3xfl8oSotQqy9erGy36MYXo+ifezSng0JSEOskOGkktV0LI
IQPQpJkR+byYSBOJUmCqjxHpMkrs7oyKc2TAqtrCC0ryYf2URqzDBZeKuHcXnBeTD0YlsSpV18lW
dit7AvzFeexE0VjlMBpLzJi48ZJe1CPWAsm2EtObfRFiPrFwVTB54okQ0iyd4leuHwBleOIlrOQa
6EAIUgKgSt5HEWWrMb9ce66CMVu8f/S7of71td8pCjEkQA8MsOU7iLfj940PlqF7ydVr7nKyeTg+
wQglFffl9vj3dcX02gdIuZtX+4H4VDLcoExhYMm+XddUF25o59iYGdxM9GPZ7KRybRJYG9wR8Iji
T2ZCRSkkgqlRkxEjCmhIkfsbfqJ9MYKlDSxPw5yLOpsPGSXoH8EEFHg/BdXdchyapC7Iluykb9t4
GYAGGpe0uZeWGeLfmPK04MZO+wDVWRR4sHHJlxe5COufaRedBqVb4ZDGO9ddbhQ56NJnAtBWzxo4
jMmWPkAo9CWxysuXKESlYAvHMuUMvdcSHpYnk3b9pujqmAa8/vbNVEK5LWWy8ao5BM9yyDbyrk4O
un90pE1voyqiQvgcNkPodJuo+FR6tWt/bvQzep0OPBiZIy85hmiAWb6WEe+AV0f1esig9k8mkuQd
E+p2aaGcrzZgZudIZEGJm103xl69MfVjh69k5jf3GtC7QAh9hn8lEBPOt0s4ZGcMFKZqoBCjI6cv
QZ3az6hDxkiRRlU34b2MOY8d57Yq+OVhW363g6R7EdTVc4GRm919uDnFdkdFllAaXdgR7ncXIRPu
aEd+U+ZwrxjIW1mlvxNfkqH2rma+AvF065zOXw4KxKjyrFefQgG4TGSrN4A6Qhr05JbEad6DUGh6
WdLzlQXzx9wMX47MCRnPMu+WMPlppoQXKEw/+wFLqh1H/oXBfewKb1D6R31jODfTteX9BoY9oB7R
2q4k4JrNfxraXXRx0Ifv7JxrtCWxUabdJisHAapN6DkR3J6uYhvOmsaFHtICG5RVijiDm7VHmOHT
W8gG4ubIqDPdjy/Bq9+I+3nxIzRJizc7ho4MM+SRztjqBk56XpzCWQzxewe8TPpr2+6o+5fKNSTa
yzvO6CSzSTroA7ZIO23XUsSTUQSu6sN0ayggYuzwd43L1MZ1qMvJfyZ9+omd1V+OkX0RSh7ZwTOn
jwoOmJUsbIQYHwLRNSntMPpnCacO3x2koVQjMszxXBQ5AKroJwBgrdE4CkfE35BGrM1mPv7wgTpG
sCQsIqilkPmpklatiPtVjDz8l5HOZRWV8/CFGC25ksWHXAuApJX+y/RHeh1DC6w68i3p7XywleML
Ty7K+Nttnd+cUPBfzpX5kzkcz1joJMi2ii03UDEBerZ2HiuiFY9KWuUA7EkKkg0l7R34IhD13uAZ
vApPHg+vrAc/Y98h2WeWITMa0Z6y/5zz9Bh6gC0Sq/FMAF4EP/cstma9qRxdfEnFU8NN+VErZ+HW
Ou4QhxEHm05wV+5zmSOP9k3hshXvvmLLrHzbd2w3bdxqb+/UnQbaAUsN5MUE1gMbA3IAxttuH5DC
4mbbvPMm5kONAw3UtZdfc0pKu3wNulQnjfnLloGIICLySgXivZ7eKRqgNWG4t1Svaf85QSoMqvGS
BRJX8SH976hRO+IhIymPkKM72G1cAe5uXv4pTVfeoylHt5VZfav0JLgGfFRtPMDcAlmtE8X/izwA
CXtDhC+C1SfetlTzlwKmOHuw0JgZv7L/NmBV8uSc7oa/XtwhY8eJY8d7XcLXEJD2Ju/hvxngHl/S
0EDvdC09S/wC4wWQf3AQoVcwUGxaLyh9kxHpE5d09sdSRrIKDdfziPhPW4NyQ40AWSlEoodrntgH
Rh6twN/umLVruT6EFFGTPTEVFHMtLt+s+CtRzvLVq3BHrjxcuFQdndcbJQIbH0yxvMuGXcppaO6X
oXC5umvTrl26llVmI4IL1H8E1TXF/FleSqrmtluLd4sP1j78SR6bkQwQFcb3kXPmVyecd0whucr5
HbXRiUQB4fW54nH5VzJIQrPqMbzXf6tkO1GgTgHSczzP/M7m2C1hhDmpVqK/izKldjdW2eDYB0yq
YiFHcUJF+/3MFe/3pfQ0CbWRIk4+LceY/mGmwoksdqujoF/xVbtLilzRgRjtayCNzY5e4g0OFd50
1vUpxRKQaMaGPzhNXMp7TNhLzRRb2apNau/dJVCewTRPWQZIpepAxTx1F7rp/Xf3MGlBE1cvu5FG
L1CxXjWPcypAswVMi/diwX/+G6d1KstrSuUg+m3NDASLx5R4PURrbSaEkLoPpu7vHJM5dNJeOH0S
jvA7Euc5YslSlaVagEshnI2leBgwvSVYFyXPibk586bQV4w0rMV0a+K/Gnk4KF/wni2y11Ib0PQJ
aiPbNgww28wr0j9ZI8LM+f9iyE0QvxEsorwJcOe31lXFJBywC0mVFEmZRBNP8K5X+aXNb7bobS7s
BJqzBZMDdg/2KBkRTSlniyI8acDWHI5xNbzWOm/EGx8xi4uqEdiTURu0bMMXCdM2xLZMOgznEl8S
WuOS4skRTYKzCBi6CHpJoZdZrSmt3jr6s27TF6eO/LZgdZEYFMZAr4FLph4aptP3wZqCsrwHaTfY
VlpmmKyGFuAdjSz6+Guoz5zZzP+kNmu8S5HVS5yC49AbKh/vq3b5CB/TkjYwqxdU4dQt+lmCNb43
8n1ZFv51H2TjEZS5te14/uMxK9b4/NbFVO2Tjq8NTuuYFaOFDwhCCYx2XMcpoyoWEliO+yL+dmez
5KLrSkLJWxQpsFl/p73yX/p+Dx972cRJEp+ip1403aevuuTDi9C15pquUHMc+Wh/oH5fTtpHN8ag
xye9PqdR/oI+wWVWANPaESQlNpFw+2ljGSX+2ealbRKsNv5EVSlpA5ftfcBTHEL2f5OeJOP8iXWS
pTNyxd346/aCUnvDr+c/ET/TfwoQ5Cn3WJpwwyE2bqKGO6DyjgMCXYe+Cgfcf4WOFEZSHZKNMBq5
b7KS8xJgOwg/pKI793jPrklFFvDSdAuhSZ9RRzFuDrG2qjgep8kFRcEyXjkjcMDmvv7pWSGZn814
Otdavu5Dt+ma67q0Qx86JEvb0kFKyo9xbDXow34ZtCMA8jxmngdq6m/ocjMzMm+XgsELGjK2BrqD
Otvq0auaHyK84PoeC5Vt5YbvRSbQF+kO+qa+3eKyfnH33AzasAjV40ZVtAnzORroQkoBs3tlLrT/
hiYY5eoOlCtI6gOhAPxxJvY53Bj/FZnS3JV25eGZlDIYYJEEQUrofYtb0YHuM1lijoCJUqp+cLVA
8/JnaY6H4LgomYxzR6M190mmIyuHBFs9yMNQChw1RxwD7kpuNg7gJWxliCrjRIGaH7JXTUGy2Yv4
gV2Pf+M2WplecPDRvHjvXuEYiENc1thFkJCVkTJDdQq7qtERGdNStXzPLnvWM2SJoaLg4NBZNXFK
phUPAjw+MtwX/J9ApxsbpCDip49vR7aoZ84a+GfKgsPUDc8eztyvsPR2kjClBMO0sOeVdMO0KgsB
7Zmd1XVBLgjaHx1L9nfc5uJ6g7y9Npf+bPGYgzuVZluR0grQHZSYAEU+qeh91HRDn3Ty9xKZTMIz
3jHUbE35TTt1L78w6G1Z9OGxrS8nIjhFQsKqb1hJhzbCaTrvxjmtG/AcEHlbVPUUMNsC0n7htrtN
cPrWCmul8sdRDXMzejGXhWZXvOVkbWC+ecgOYAFW/20fVKav/A0cwtMOfJuDVFFYOWGS/BX5DxRL
XWiURvQPP1fUVQUXdci47KsWVpXiup7/c2uaUJLDo28xByJ/yu4FN4u4VqoI5OWmub20ZIpm0kP+
eAtsHwZpf1LvdTuEKRuqVPUHF+vejfAu6dV8vZ3vikecSlYG92BpbHc4X/yASH9CeT5aykPgcXjq
dHupee1QDMNXtnrQkXh7UUd8bH+eGYRTUvFVWsbpliih54pJVTxVjfeqfu8kppLqwTCpcPh7FTZT
Tb9FuLKdAAqsvyu0GxwCjTw5Yw92E0z5oonmocAZXB1UFXjIx4FgZgqUn1i8+qI7DrCFSSpG74pu
AiiaVUML+2H8PifzLBu3qi89W0o3/07e0apcCg432eBGj/4Nm5oUIub0IsiuYQwvr6gqgjDjp2sg
joeO6wfO+sG3qN2ZWoz3UQMU6OuAZijbFHiMmSn65BcgIhEDh2+xwbBMV7i1qEVSKJt4oigoShLo
T+Npu6+PmA2tZH0pVr6HEX+ik5LgfTpMHXlSsZonn2Am7lqh2Eet/6SFJPJB/xXAJt6gnUMXL5cM
UWlA+XRden5ipnWnGsg2PpUktVDwG9bWo1Dl+pdF4J7UUHFFEPzdCF/MYSE4h0yBJt/ZkaqUD4CW
XhvPaAL9K3chXZtpO50ZgF6EWtJl/uT39gqDjjW/upfAkT7YG1A9Q88zBGDzGolUNXd1SV6vL/8o
/ns/JvH58nRhRE5WUPJya0fizblMtaoH1SpEiU7IHu3G5SP7EGyBh0AU6NIKwmHnGpv0aSvbFKE+
w5GS1P1kqdPH7nYyT/2p/TYYzt3zObbRFvnByqhTXV+qATzlSfK6G0RqX/oYb7DcR2sT0hlaGvBs
/HAhRbHJ2tsl9EjF0Ygwj+ZODqDBJbxW3yHPQs3/CehXrXs/lGFhrAo88bpvVlQzexI8BWNPkROZ
cLAeCYuSuGXjNp4SB9LQirWRjx0Tue4YBIjwV2ffWlk8J0MikH0WUNLQmtPQCLB4IpxIwnRcfJtQ
fD0zpJb7p+HW0hLTqZR0u+gbpC/Ar09DhqOO6aetQJoTdtQoUMlu7vrBtoyvsc+kMOesqsOGYYDV
JnU2hPClnVxARDkESiYZBlWO5na13V6GaMc7RMVr2PN/F0+BlthJW3Vs0zj8RxloYRQ+M4plfsM5
ZM2jztXxG36/ZRYKkLbatJ+27B+FW3GHNk9VwS4h/UI4xKeay8utENpAkrexnfw+MI1MUNgSZv5q
JerzQNGid9zHjAC0aGz9v+IZwT7lHtrqjOHUumZkBVU5T9leCSm1NqPcxdiFPXXxLtoKZ+NBkXya
LBeSSjTnPlAGK/22ZgI4vZRbOXrZWwk96mlhmVLua/MIMR0/LAzW4EHdDfg8TlGMIehaWdN7ab8+
Zb+E1HKlLXW3LpebsoNKtXQNgNXzzOG/OJe4zKlHgANtx08guiT2ClwcQZaleGL9sJp35aMriD6C
wu1/MfN9317nVu3/1PNOt8gPV5UT5clPlsDsM/6Hd9Ms1ST6ZXzFHsmP8MBkeVWC106ubioI0zJk
jwjdJN//1YR9quOYooAvgHti1x0YmPmhyXieZEfHtn3iHiKHMbUUEeFtno3XQo/kVXI+srfxdFy+
zRQa7yvnNxiPDkOF1mpHHATDPDy+sT5jL5S5mTIMtDzaap40mOzW4VV/PSGD0zBfstY/l127NzMU
oM4RpfTuOw+xyvW6Wb0ltpZyTX/dz2kvaqJqTgMLGcaIn0ty6gFKXVmINooI5rUhbYGf5VQn4tJw
CqIJvF0Ri3YrQi/sU0fjEE4SQsCEpTZ6nKnFtwIM5KWqMvXu0B7GNUWfjT9Rhwx/6YQN2MHF/tEw
tQ8KzJhRuhOSiYCat2+1uIHSEF8G1w+2tWWnqD5UUXz7+b4YvvPn0gG2flCrrhOVgbP9ocIXoDv9
C4I6INGcF9KTX5i9hgpIe8lj2xaAigkomVgIFHnxdWICa3uwLRcj2ZD/C+hfbCtnJmg6dTOiDvG7
P+3HUuj/7QlnJ0zMlSK159F1fbnecN3KUJ8cbMxgR8wug037jyJAYLQaIl2b0abMIdjlLwfrShnP
Nw7xUm3rjULqUqEcNfhGN+75YKNxyMgZF9x6o14lerJTPackrElyFX/lHn2JlJWIlGhj45JwyK59
1ND7Rb5V9JircMzVPR51BlrkYa06mpbwGuRD40jgItd+5NNaZkRU9GygMj522gm6yKVQjQKYPsae
qTxP96QdVKVa9Fhhie+kYo3q84eqq4oDIhVyicoHUKkVVrnlY8wzhn5eCMuO6wg02eA31TcVc63g
V37wNHlNNlZFDE7k6e0I8g94mZCEBSOhONt5Zc/FHrPpCaDZa433fWAFCcPChm2LpHmveUtBKxc5
dNNnUDAxs1ttOTzaIBwpI1zzjg0DYudM/c/XFE3hfExXDYR3WvTAoJFrsW/zIvGk4WmLTuXIsBG3
kweT3MlyM/Kaas3nOTq1MwwsJAKjt/h63TMd7yS1mKMmmDurh2HpUG1yVYTilaCaXOsZAyvakiYm
gQCTBWGlR7dhyAbKSvYgx0lnYTcBQNncKpCZiB4kF3+MoecCZ1TqWG9aVDG7rB8g2XutbZiNpEhe
+WM3JSwbnY9NTc+zPD4f+95njkBMOpBJHpnc/dvrP9kl9MvOeEWPccXH9Mww8z4o4bGqPuuCwJAz
7hSh+gBJTIdzFmAZgUmaOa3yV/ugjTU0r35gzXJcwFSD/ZTJLXTSEna8ZXkVDV8TFNPeN0ixfPyG
NhS/NBpEpym5tww05I31QRSw0rd/xnrNWKc9pgyDBl2hCFbGV5fMa2VBTdL4PU4zhbs7dgwEslIe
1fwNKlNfNXOtPsL24Z3zAhlzWW9/KPrt20/BaEnySyceBzQP7w9Xdt/cRBI7XRfJ16fni0zjixYE
Xp22Ejdy6PLJoz10akKGLGRyVE4zFeXDu1yDLgKWqi4VMnrJiVEIEy/7OVupC/xwgE7ltQtpG0Ax
7FeHxSqIv+g6mz22rLXodCRntsurksnPMdz/m0V2F8ipchVNeAmAlY4GtZ9PvBdDA1wwf2pjrPAF
TAD1MbGlFRhPxo9xkdnFiG1GmvuTRFuolXrUaDdrxSltCey2ZLHKPrxgaGQjnqPolzIaWO89RERN
pZp5nwBdlfuN1haA4yVjovwwyCSJUUVBGpj91UrysoZfucWmO3uFqyoe6wmYzDVuqKnea/h90TJp
jxVzhZc5ebQwlw5QP4gKKrk+OELbGNnRxtrI3swJW+fGhwKpiYwI/2jMbT1qAcbgHW9toW5baCye
UHFRDQFpg2LThoSfL6M7eLnczVt7gTvRkRH36XUvbiSaKBCcXXTmjFSiQfaS+c94E/oRBKOvGjZA
qKZ998i70Dv7H5B8GdnFfOaTVqxQXi0HG1Zk7m4n4s1BJsBwq60jVf73UxAYo4OudXelOYP1NOnH
rtNLOtP6mAnKHjc+9M2+r2uH3zyi06NWDqLCZdjqPHC4YOLr5qFzqMd0r4WV8hLkD3C4jYRPj5fi
N5RZfSz9GZPUfdFS3ztqBLqs9tlle8Q91hqbR1Zcsi/rvlYu/X9hnAumv3NiaDe7Q/dOcaviaTmj
1rkak2xhokoIl7PMXZr+AsBOmoXMUL0WbLifFVZTanTH2dpItsUQsKsHz3YiCcWMs/JSBpetgseJ
yn6/RoXRtgTZ7F3zOewb3xZmJG9MiZaLQCzPDETf6cyy1e1EKGSbNOQ/gKNiEQDuGZSZHR3eL6iv
ASIXuNNcPtaEBqPGXLZ04AvwZ7bieOFixi3J0Pe8yOuIMG/YXrXEgCwL9awKOGjUrOzW029PKl3b
E1/MlpVEgufsy7KcwhgAkIHs4pfaUgq75BVOC1Ue64Qpq8AUQ6Z12qRCZSt/X61LzOixXPihvmmo
PZdFIpE7rA8f+1LNHk63/RLdv3IKaa9REUJHsQ1zHFK2EP6KfkMKjFwOrRk1PfBDnuSQ599KkuHd
PR4UcMuTHMlOVkDRs8vVoHQN9mcc0dWbcETmJgvzPzZaN+TLUXJyL3njH2xov69kwjSXH2WM9NmG
Nwo4EVDmdXxpgApTBB2tjMxPVYYFSACsuA10wyIe3EE/8bKyYXMrIzkprRWPisQNOn5W6fC0F271
xA2IF5FFFtGNwjJZHn12dLcmbeWPoBPX6BvGRSpcxx2gqNxTcmtCIUDP6338JCPUt0zFg45+cpG2
sYJ7q8B0i+Tr7KPZD8auHhJmrHDiN5QOPIOvUSVdF/Kb0jD+7+W1BQ+sLzzC85Qv0VHqVc5HCKDw
A+clhuqijRGY9LtDoNOrnVJio4Sce0PLG6J2kExJcKVACpYH2yZXDXvXQFh9NCSUavQ3aL1QwY9G
N3YkLTbkptsfq114FGPSJH1t/B44MgSTA8ob06p12MRh7ewzkOAyjcdbtFZDjP48P81u2VBbqsSa
8SADxq7mBDuAWmSfO6aXDuv9gmMBLCrQBMDK32ZUG3dkHAf4efAPNE+Vfiy2OpjKeIHDBTSthpvD
YmUaj4oSvFibbNG5RAPLpoDoJ44QlSdCJXtUoAitoQdNlvHFhfJS33Uy90rHHBsCJJ+Bwm+VY/+6
03i7gpxqkH/1nsH31CcM1Mxa5iZ+wSTnUHCRuum0YWPOKtonnmY3SgP1oM7DyyYz/m7kjMcJOyu2
elqX/lyTl02NqHa1xDc72YPt87ObHMH7j1r6VUZvqoJiFyq7D1ubmHL42792Ga/D5Hv7MwszBnqi
1r+ZG8vjcMJqDtEdMu4dUax0C7TNQCCnHOiOjBDEJ8dCg2aUz0RIuVu38rwnU4xgUPWmRie2D7Hp
MHpGv6dvDn+Y1BfkicGbIm0k1Jt6qr3YuyAgjGCvNM2I8HMk6k3fI0NSDY9sCbUboklu27BP/VnU
K6Jgjp3nvJxxYargxmb25LeXAg/Cr7EKTD828rHgK4kzJJOMiAJXCmh+wx5NOwy5E+2yz0U4mkLX
lt/gCvfujKAPPU8f8ZGt10/Jffw4g5GOqvE43Z3Zpx74aB/H5s1NGrmuWt65wyOFJWsYbmZkFoRR
+jeUnl6xDbFmxGY9dHRbJ2d43ahuXkyv/E1gPPNYQnPWrl9cPbD7lJdzUqwC0Yj3tFaz8okE3BA3
Dq4EuoleX072TwJZNlSa8trOEvHZ9hBziVzP7/02Tv1tLcdiKH1V4NGjkMOpmJUpWsKU1kHkFtsT
8SVFcuBiG1+CVkNem9wKRj2msFj/zef1+KCjsDxjWFYE53Y1B25D6lXA4KBf5xE/kJ4mMfWzSy8T
bzvwxYoiC9pkvFLlvorA7TCPZqq7s51NY3HwVH0HDps01vVBNbEK9+q1x9sTdX9pwqe1SdDvBu1O
xSaNIaSHaE9Raqd2qUGZk9IKFWNaAwW4vGNS3NwS0S8YQC6vLyErYsX4JHHjz/+H0x7/3zOHrTZV
l/XxxGmLlur/bG3hJvfJSvNurp7X5xUFmbuXYoUIDbD5POnmtvUOQDsIcNp29AIt7o1qovCuCEt1
tYcX8dWFTR4ps9JWRjE97DFsO8iqxEOo6Eh1SwvXAq6Rjq8U5x8oHPZSBfGtmItSrtFEt/F+G/aK
X/VZ/gkTppvDtLniJHOI8P8Qflz5OcjJ1DrwmkeoykPmPJQfZ7rlsgrhz0gHK7VGxKW09JA/ROKt
JwS3p4ZOW+zERz+uJTuDgd5uTn2vHB1HqoZbZPbpkXis8JcWOmCyfl7Ybozb7jQWlmTqyMqADXUo
Q6P7Bt/8fhYGZd31dN2S8ms8dVW0UGsh+7tby3KDXGRpwRAQx7ZVHXbd+1DkuOzEho7+7lSumf5/
TSxmKZGBmUCxXri8ZUggwmuvc3oyYQ7KOqLIvVv7O6eejSMYVFl/8FEQdI7NQ9edZd2qKCAzRGW6
dslgzlEn+sLSkGrZTeJDfy1joj4ZLtjBnidN1kYi4si96WfXmG7jHbvOrSomhln6jcF5voN16fQb
IqRNa6z9S0/YjprKlHiJdKcf/QXF99IHK1b/ueoCFYk00I/8xLQ8P0py4DcTJIBDQ3kGq4xnK7sa
xbnIzQvHOXQc6WUiElE0cEwIVotr/f7L9co7II8gIMGTIfSi5D871B4YYjVNDkpLfelPnTkNZX+N
bIHI1yBNOctsalTZXMvv+zNp8SSmttMuNWptMwN0x4ys87WnqSnX4DIcZmW5YEWagwLr/hySkIeH
i8Rj6WkuUxQupzDMND99UAcgn65+wZ81uEQyhxfkOufRkij5Htc2CxdVPhIixAS9xGX36oPi6xpY
aLIuPxhSfz0QM85CXLb1ChU725s5RbSq53gyHGQ1NNHc72BEA4LhImMZr5tjY4Yq3xldl1Rmc5kW
oxfSB044ah/08gsjd0CAHiiLGQhoj1sxg3GKx5doQlHJUa+raQPF5Vb02ecDlZa8AN5q1bzFwcLT
mq8owxtXx8VahGaIZ4ZzBWPLb14t2gjtDUOEGFydoSHiMdbxhaNA80NAiCVrOTOLC/pdtQ+t7U0x
ATXSAaIfSfsMbMH7pIt6cJcG5oOQkN4BwGwUkrxBg6xbgqpXX7nTj4P83fWHUqdcOuHoUHJ7HPCT
T74w6ebZFlVyY6JZaFy5JHWX1qfnKR9aRznZTOD5Od09PTByaA4SD5n+3RxBGnhBlSNt4NpSEQc7
s0mWyiekYqvr4Gt9kjV/bnp3ufFJjB+ccDWu50nr4TkIoC6oo3gpA9GB2PKm0qzDfIVIV1Q3rgi7
Z3GMvwCmeJEp6e2FGMdVdt3WHlPgCIscURGPxRXM6Fwq0Mk1bkDNVH5MEuqKZBY/1KUkT2/Rf+Q8
XQsu0mgyd3/Dx3ini33rP7p5pY0lJyMRfaW8HmwknPjXkwxSAyH/yYZeTBsnaC5Ch5XW+zG/gQHG
W4mcaJczZEK5YnZ7YN5H961c+G35qP+gDxHlcY2dtZAONWuKIsDDJ4+i6VVk9IcDE7IX5OW4sirX
AJUSEXOKCArE89VBh95zaSFxy1NQe2y/ag+fJdlrNg2CUKgsIIPN5zJ/Zl7nttZ/vuVMWd0kplqk
po0DrGEPlvZzlr4fjXejF5frNA7Ur8et2rlfPqqL8N2zX+iXpMR/f/u/uNDtCph2I03fKJOUR2SK
fbKQVjYOBy4zMrLOokM01N+/F3nowTJBTd7y4R+j33BbH+H79dY5fJ9idVCLMfQJgCgwAJYiDZaK
WMvOgoJ68bHFA7sy7outKlJrFcg1sHoTqogoA2ahpIBHKT0f6KQTdnhpGSaqKhvxVMAHq2kRZW7T
lDtexLHhX46wxZCzxTdP+hC0AI9KfC3MPsoiYSitgwubyL0F2IA4kvhiY9KhSD9q8CFxt4iSucoo
64URPfqQBn4F2Rrrgys68QWvm4iPqRpayYnHswVw/OoJZI+hbVSoJgpPVGpQCiaF0UTjTTTcj6Jy
Dcs7/EkvQ+jIgSh81AanlqfQ2PgU2kG1nSG0rkOsfjeJ0f8EyxoQMP3cqgZ3Vi3tXmThN3TBceQd
rNt6CEttoc5/t+oWEY08RXHTHuY61y+JIe6/8DfIfuvXgmaKTTOX5lhhH0dGoGsccNqOtcJ917nF
qkLRr9s4FeDj+jwWPqe+j3xs3W9K1TsQ5TFmZJ4XSdYWmb2ACKRggbUxoB6PoevC/UJtbo9ZOTbP
pwD2bDn2I5dPYPJvO5hvx262DAGHm4XSkSbKIUl2VKWGUxUfiQ+bbkAy3IcXU1kJlHewKQbuiLdt
ulNr3HhYLNrfFeCVeXhK9fUYZiUot7SVLHmLn6FtvGl6BhhZ46ii7QCtOiGszsO0G20F+yUwSYAV
nPhRNge6aLjQyH1ZiJymlryfZQNdvfoYYezaw7q6TAhUvB1afjrSOfnR6BemeJ+AtoglWxvwbivc
PTvb+/1doYnhhgCSwqKqw6bzUpqli/Ds68vCd0wvEvQYDMK4KMXUVBpqy1O21hfqbTfEorQkIC1g
koUcCzU+QLPcMOpzFxtgG9qLgtrcr/991A4aicLsMAHiRzl8cL/IANV1ROeGVvT1v+BA9gobkTz3
VDEUglJS6wx78HIh6vj8ApYELADzmJW5rDEZqjPOro79qv8THZbg4iV7NFxL8AL7ytFlmUYrdsFX
53zNqSc1mKb3uaaBgp96deTMWVzmSq0/IjWjUPjx7944V8RL9NnVY/+S6x3R4gWQvCUZaMTxTW+h
/e7PIG4PBaZCd3znqjwC+MohYwiU59j0XJ4+Nl9tsVhN+o/iCLRHbpzJczRb1EAWp52rnyGlu/3n
A6sGqSK2XBg2iuKqgmDCOy6wqKmYXjGGFqYGBTVPncdl5uwJeiYvQo09R39Y/Py8FcOGgmeB9bqT
rSKVx2Zo9JoT0YGofcv56V5E4Jo1I3Tj6Sts6tDckPzzpEoyyUq9XLByS5KCUcZF7j4JkPyWLa0H
o8/ne3ynmQZlhTRRtkbsauIApWJT4FZiDrzEwMvvCkts0OQfmIIKX0N1OCxjc6UQXNXReMOqn+dC
PHmnv6vRVfmXvInDJ4smvyCxKkPM5jl7308QV33zN2rCqFLWumEJgpNgykuEuIh+GubD52G70R/P
31kShs2XWws8W+GYz7iIwptCCkaIq9eHuCK2KTEUsDv8DeRBOCWVFd/dtyoqHy+Qk4RXHFffaO4R
UeTZic+ghMUTw4T3dh23BCtbJQYTOKc331Z7gw3AO85jadrE5fngrDL+F2mvLOnlZ+OIqYgvgONy
cD5eUEJh23EFk97XbZW49zmCswgGD4Qkz0NoAchIHwGM500x+eephCurEbyf4KyqIugWi8v/CYDI
BW8JmBJh2QHm8vcBhr5E2ZcOAwFxxUNqX8XK0PxQd6iyGjVUc4GNpx3V5zMIj58gfoZoMExRCTTy
mLLgB7m0XW9611kxKN+R38CO/uVc7M10lvXEafwYgOIt+K/IkXqR1gWytKqF558SOntvFccnQExn
Tk2YH4uWY8F1ImWmtmCvh/byZM85i2jGju4HEOhMlAf0WbaUoTp2XwNywq8FP1NMZAX2MEqBJUzT
dzx4j57x6mBv1/udviGRqyzAEC1Ocz4lFPIHHz0aPPf5QgEvn8yxqpcqHPnoyJ0SyNU6v0vLfe06
XTS+FKlE9Z18uoqlADA0uSnb5PCLoNoJS935cCwdQ1Ut843hJEEBdq1xlFR2fJdkvuLDLBZ5bA8Z
VloSWpoUBEELcOXcKCca2bA+TRDXf3gj1/xX5jyIpUb3wp0Gh60U+LQp6lawpFiXbr5hBiTn6+yH
jG5ivoVg50xr3zoWzpHBsPpchKoBA79pRwBCu/aHzx9ozCDqXN/VSKcsRv7M7rY46c8sloz/fGES
n670gBJV7+QGQvmTEN403I7+oRSZqFMkbCX3XnDsZhkDOcGnAwaL1Q1JyVntqXuyadPMCb9dX8zl
bsCJxlGiJB7hwcD2MYP3eOS0/+lVMuEDFpbDd1T1XN0dPqb7UU75T3rE26XI+KivyD+NvTiPWWTi
Uh6QvNJQUJ3kbe4lIKXCvCrzi5jxG+zVnJdB8VnIZlhwoh45Vzshrq3rB2+ZS27ExIck/8snuVzz
Lv3M2h6uCOlgNfVcVkqamjJTaTvgdTMsKuZd5HMSrTAk98UcYRQs3C1+C1xdUkZyS6uljKFlc0w2
xcNO441f5gP8BR5WlOHHGIV/5Y3DOk97o/jKOh3Ju3HihfhSDy7fe2RSAIAO2919f6tKfCwynXno
pMKpZjb9QZ23LsHOC5jAmKv1q9OQx2tcIdxmZP/7jFDieP0RzcnyUv6okwvs3q+zqDAQvIneEWsf
8i5UyUIVhZ3ijeSOiIRbxis0ACh5KQ7ChCuXm/MLufOvyPC0b5NreeGAKAUrlsxJMj2VHb97ZB72
GsTnyJxRK0O69XgaY+HzvxsDgQ94ohXFe4LKiZEbkHSNYrALdRqSCBsoKygTclbZ2C67TtBkh7G4
dx+qiV7MZ1yEZ/h2yjIVb5BQUfX1UyDFDwIeCovCmbCjkkfUq1BMc7IhugUtTXr3DM7j0fT9VRI1
vOYo36YaSNgb0r50lcJxmiNw88oh+KYDjBpTME1uDOrrVvRPFIAnFeHB3BsixYA8fvlDBSEiREAY
j+LWQlGnu7qllgYGQ9dJhzIoV1scoddbJuUBTYptHAPq/XbhGGuPb9i/zJWWUr3BExQv0lXlqjZX
TyRjPCjP8ihbWUa5hupKxqZFp+zaaU6+llgyMaGQQ2UmWskCtI4Xzakxnj4A8qdPgHj5QLYTVpvk
f8XNM39ywkdkSwWxKqfewg3tk2MNn7xrAc1I6moq7RHffst9qf3YvjVn8AfwmmjewlKoiN1GA/wA
ht//352GTmwZHePtTTOu8VrQQlRL2f+izLJdpKGsAQ59MM9Iifs/iWPLjR6zW1FzPc+DWNdpfRWV
fRCtvl7Q6ji6lAIXzAI09rFxfbEXnX+SIy0TERWTi/uZ2WKFZZtl0SZCmnsHGKFhOtPgLbpCSFRQ
/mp/w5hQlhvq0LgR0Y/xgCOdNkBvYp7BxTq9avs+xZ4YhasDFbLSQOLEtP28een8GfgVnZOpHsHc
B0hQKHN7fsXPxrP+W0X/wB5K5wbb6ZOO/jZr8weg4PeCSbyn6LnZgfc1PEZggKfOtN+5Vo868nIc
65RvriD9XZqVyk25+vCWCOmJaOF9/i3PgtBlp75gp7QQnhcwruGP3gxb+Kk9cgkZ1I+anKMJIPJe
t3HUh9FBnaK5FgVGaCGSCIERCgNVrEscaOK6j/DWLzQkpjkkustSY0RjAABhDA/8G+i29+vIsI8L
HeaMiq2uGFi0UbPFwxSLMrguLAsBgqcKuZadYIheD/y2VwSZ1/+++1w6c2Guk8rx39gQXXkSkzHN
yLPEZipofk0PX1+Cnqhjwb0+s3ocV3JFBdFxcemp81o8+uk2vZysYPdBhBRMVI+5WkkijICt8vCC
nHt+ZyB8XuKa7yWL7k78SzXdlMpg1pRncpndnSdgnKWeUcgFbd8HEbtMz5erfCMwB5WAVBZ1Qrfx
6QFvtxonJvxi4hMChNvczUvQNeCpSC+un8AIoXa4tW5xCoZaKE5qYl/fUVOPqXzFvYTahzLdFwsX
qOG+RsPi1FofuH77Tv3HuhKxW51iUP//bcmCWrYaweWdvvtuTQl1lo/jsSpSmcRJLLoYnI3/0STx
9FQw1/nTR018/x2W15Q+LR0b1TjrmxIVoMa+GlLIZpPLMR9r90E/6/Kv7qCqyzi4Ml4IFd/N1N9g
8l0QfxJ+dfYAm4cS9YwnKNGmTDCcu79KLcyJpLNDZqXNS8FHTMhOltu8nuoAKZXK4bwBYpYtVDsU
pNmd7nhE9tl2SyPyNTV8w/Y2nNcP0LFXet9veBC2amwzawr+wxH9U6WKexAJbb/hGAqsy/rToOcL
E1LPF4W038913dX04maFx9JFyuXmvQvLkznfcylGjK2tig4yl02pdnBO6aED+cbG2HCSpSX95l0F
pcyFx2yqirdqrvG6agSenfSe8GGNM2w6/8bSiDevwMBx5r5I6OQ2AqePUS10Fve4NTylBlQnKRZC
9DPQYEPtjjdm8CrzuI05fxMf21Yvme7CFf+ru+QgnpHuMkBGPNfPovFTXVxwFEfnruzno3lvO6dm
LgNuaAOz/tNkX/26VH6p7X9BOLQCk8OrFjn4PANHRN4KVLT+S3WZKiCkr9PexSxmplE8CGSsT7YY
c5XPPfRtoFRhUe0x4RYxmbwwBp7FVZFwXC6RJLVs8AjrpCyaOn5ugTUEe1YwmYWaqQWsdxm5HvtN
DjP2Z/mhCL6jktPbx5wksVkmT852wy+nMHjGq6q7HNGhnGK3atWVESOy1qFNSr8tSL3oljJSPoO0
r52rlCDWBC5gTI/q48oTFUHbDBaSiPohq6K5xsH6sGC9yYteGASW0cMccGzr9KoCP1ptc03olh+G
ayiMry2/uzhsPv/lsEHz19DRRS6RrxAygk3hd4H5b+iUA1yD1HkGDGCMDtDILkigP0XiyCJvtCea
guZPnZJgTm8iWat3yKwP89RsmXt4KLG1zYU4hH+MVwI7r/snIomIpGqnyQyECqY0a5YeMBaXPNrh
6KCfuv2YGC13ZaRGHBiatOZGlYjdK4jaC36Xz2n0E/nbLyj4gKXSlS/GF0oHi0cqVfFobJtMoJUS
WAj3g0ZCtKARs9OKKR8NdHGLvBLcPdwIiVWa7nCpjwQljHLqNzlWdA5d+YR/1gIhVBDDz2cdHreU
A8XQIRCLY/KpiUhPQQsdaNbzcQdGNCIql8Yl1s/9UxhzNLpltv84wNA7CpQ2fJ8Bc20pRpU9OwB6
udvcTThV4pKvLd7OF/WO9+Tw6GCschvkfOfLKEA43eTJ8mm1hyVIuR/3p40pyBPX/KF4Dm6aCYwp
fm6aHwzxmMlkvI1AgQoqwzO/X4uU06K/yVNWtfL0H1nCsl+44kERKsskYTZIlxdpvUnnwpb70cT6
ItgvsRB4+0SyMGp541Wm9y+au8Lb8nzKIE5X/fVaDAFfLRmh7OIAheTcF5SNJYcpP0XBsI+sLeKD
T+3EnRcaWYKaSyRn+oJk0YCB1eQFyqmZHNGG9oHNGh++p90p+JdW6OMM/ZVTlj5UiyN83ORxZEz4
HcQmqWdcnBip0U3B5Dk6sBaKf8ekgdTa9QurSyAPXuVwAyQzoqNhtikuw5LhwQ9Aq9W00Yy/2+rd
PbTAhcD0VBBX2smU/NvaaZR7x7yhfFDuqEk7kKVPgAxKYZsyU6q3gc3q+cuXZ6aIxONRYcmfynWe
o6J0GEDRaDKvDmAwPR5cX0o3QP/KcfpxIicf3d9jmaGvYMY2+YXq4+fWcAkFhtySR1vnPa4ccnan
VCCfZSO43T7csID+XVdRtNy6iO82u9TtsrRgXhHk6IqOb7Lws8OGIcU6cgY8gPhD0ugRd9Yk5q+r
zh7nlpn3DhEpZYiLtyhatK/5O7Yk/E3PefIoOVlQqaSYki6LMewE3GlP2qwhNGLhrTl/xoxjJyJ4
bJjWCi7enmG7OlF2ZoASMRa59N/2ZLLnggy6Ag3B7x8aI3N0A4xYFzxDPBtcde6+XjDXcJbn+A35
2UdugvzHebViyp45LcQiHuj/DkTu9VMvMeNB3a8v5Oud7sPej0i+mGq5pPPCC/iV2DT42+yom7Ga
hnNWPZxYcE6d24UXm+kFZ5ZCPR5ZGqIU/g27F6ufFUJnrXYPoyrN7vdi3iN/DxPNXV2yQerYTBjW
240iFHFLoMi1LAWRvTdgUmyzRfJv3CLfPwJzC/6Jmy0a5zJ6nnYPwW59biwDwjJPAmZ25vuyQYME
w+ehiH/UxsvGpgHoNetvZyAEBO4bt/GGhxk+ozJcsFHbUsBveI/dik2DK9pIkKjq3yl63w5+8bW0
Tog6BlgyTXVzpG+qR7gthL7rIbCB7E6jXldwQYa/l/qQIrAtOzc0AvwRMXnomyHahYyqG5retRS3
fP/JvOouogcb5Hzwr0qrUHBjT51Suw5khgILs49GAmzXgSsmjDeYVJGpVnCB5msl3krMzQLmxXhJ
0M91u58pT7NLAmgEuhnG8J6hpHBqkpSMQyX7Thgb627HhYh9Qko5ueDpKR01R14ZeCCBCoTdLdkS
tJG7YsemgdxF3QtrNlIJUu7/m50NVeVavKuJFit73npEcvFDFDsFnVgpS/4eM9z0YYQxHCWcsDUO
Aml1xarqDyRBoNOKAe8hyHMswcC8I6WpN/uyZaNQkDqlgTFvPZ0yZFQNZiS/tfOAfeJKB2thrgbX
5BedyUEaoGfO8YzKV8B27LR0DyRf5pwOuPcr7b2YT+TMLgst/8VpWES/6pp18d30ZNiOrmh6qvwC
geTFpBbPBTCl5RvCquYite41Oj/JNnhT/6CCngIwInFGAsRA4XpmaFNZz30RLTPjjvv6hcMniU0l
BCpdcGvmd3Ti4uWbmvWxMFzGH421HLl14awUt4jU0WtR5yfTbXiJrzCQYd07X0IhOWaL+giV2IGF
J2HYA+Ik6UlyjGc7+MGFYvrKYAQh5IWJy1MPg8BeYDNphVT3lEpXIKaiuKQRGghsGkpRMOvQYXBF
MRxkXY8aWXeRRixWKg9e+gs20RzDcyGEPu+cl29j3wtYM5YRS7A6urvFc+V6yvGWv5gvoJGgdvwg
EY+ZgztSAfV4loRv5k1O7YW7jHFtFMxm69NohDqIRzpOUEWvlXoRODlbgJVvt3RqNjeuf4l5hjfQ
YVSM1fIo6u093ZvBLH5w18HlzyUQT4bqJ1LLUmUq18B7MW9atZfu/zPyPIHzsSTd4Zxo81gEHvSg
QmtaCvB6vbgrpF2wTaozhhgoE6B1DsOdYdQB6qYKChFvDathEXb4CzO18RTB3zJmHqS31ApQf67t
k8RzHtQCdTmZEwQu7snWx8YV5xJX/GXZl4CK4WftPda3LAdJrzqT2Ux185OvL/RzFRWE5gg3jQIH
TA6/zJelBZRXWlmI9XnQEVTo9uGzgjyNFtj9o6rR1yUER4jIYRfC9Z/v7aPiG3sjMXofi1WaJaVA
RYC52g6YkSlqGCyx3b7Yb0Niume10MYY5c/mWeiIt0W9ASDI3v+Es7RgcFmruT3tEhMkTLrAX4DW
gGjrtFxHJmR9b5cJ5oE4Bz/ug2CVT4EgwGFvSUfCbTVbcl2teHfiJGyC/icuIsOf1Rz29GccTF7F
X8asrqWFCu5bs7QQoqvsVEkzgiW/VoGXw9RBLOyAIsG+B5BTLL5VHraQBa4s8ZuC1KpljeiGap1/
Jl8qvtrtR+OjsIc8+p5/2yzNFIQeBhiiAHbhAo/DBZOAupvN68kY+VsqTjzy+tPLz7oTMSlet37f
R1R4930jARePfWoNAVyuD/R/Ka5s1oLWRp0pnvp5pGsI1r0Xp1uLmuWWXA++O8X+Bq2lpoGUrFgk
eYHD+d6ze1HYU4ZdiGz5dDq/JOtJ6dw96eWzOkZKjaRnhhu90BMaYRxgG3iHhZqKQT25iGx523d2
Swm/+R2YgSvkAHiLyUK4Klvg2aMvqHlAkdTaDuwocPodDPgJk8R+Xd7DG9+Vdnz/fxB2OgMoS8Kz
ykzNriw01VvB67JnBiOHz5cRZ1WlZeZ4KpQiKxQbox6gyeKZmUHYxf5Udwu+GOQZqyW1iWbO+8eT
vqyh6w1l3qUTA7anJCOKYvOrWK/f+Njkar2eH5za3srK0qjO1rFlrt5qhrdsv+Cr7dBic4NG6iWX
yKNkmGQFOzN23o1HwQEOpL6AIcCA2vN7D7rOhBfWHwy1hQ0dbPs9JElzgGBjLCD9pS9yV60NtPhJ
RAoifOROcc45E82JUR3mbt49WhRL6wzB1FVE8M2Cl8K5KN9r+AwpIy12QRoIFfwG3wV0ZzZajvqo
z1rFfA/TqSpjC1eKujHtEWC3Bfn/dfheYIJ8UaJnGn0U2evFJ6S1QHqyfX6P7ddfmaTH7dHgfeq/
KFOpNPQG54SMSx0K0HWXKRO/WLG0nyRP8+q7vZ8RI8TZVvUXdP1fEbWymo277cBP862B7PumcX5/
7XF6qReaGD43o9nYtUlv8mjsBgsqtvnVYC+GCMWC78g2S5MgzmzA9upOPaBkPvIuMfaJWUk1cQjY
n6QvpUBC4EZdDk/p6kR6sl/n3wDxLBhV8tzeeFJJQJwXIA1Tmi+R44KcQazN0qBo6XoyYEvQ179c
HcYAlvA0Xf58M7Fzo4R7vU9C5OgAhZ2DSA+td1h9WoamQsQ07HEc1lKFEmUd0c1UlNFcAesl1tCQ
4MM+wltapi26B2/kdOBsCZVV4bqO6z/TPysN8BtVRgYqeghA53G11GMFRKVBFEevXR7Y8GSSlP6a
DU1H/hI2kM2wuCyFUQgP2ZBsf7TAzjMLGDclycPa92GVJDtIHFJDwg5hZ7yaG7T94J4Z75ESPzEw
TWual69wf8X5Jwco9w8qqfnY8vyTkYnwK3nnRVPMXYtT69lqxn2DP7VB+2GOC8buKa5U2RQzorDD
jLEh1MdgCfTvZEhdR+475D+To54LzmzOwP34QsVxjD0io8gdguH43XxKsDj+2tn9aWVER3QACuDJ
Gnstfs9GZChd63MBwtAp85AwORGhI9NMxBSTYlv8nn7gnZiWY5kQ95+Cyw4a3W4ycsXKdaHuRBAu
xDQqxB8tZzVj/L4n2zbnvZUZdLYAlIWaPwTqGWQwig0lWgpbrrc0kufyGgs0Z0VQwD5RdhdasR2U
GNkg/n8QoCKmg0ajBNAiI87fQDqRRid4y08pguFG3s0ZDnGTbwUKl0lF7EdzsAoHcIrj4bifrro5
CgSps3fVLaMCUqjnuJPCfaJaJwHuTJU72gR6WvQ0dhuabcTqYyIDLEOSuyTqcINAWsL0OC6Fmf5y
tNw9man0SAAFNCmTBjXIdBQOWMNHfStWMkKX9phy2X/x6gfVi2i3lmjCJVmLwqvlb8dPjCltIbb7
NMTXAJBaM5Yy3rnQuO3tK/kbYhIGpyxHRPRlYarubmRKZnBAb7359dUOc2YbBLZk5u4tfKaCeeul
+ebKQicgLWZ88bXIw0G/ntMD0jfEnI/SCeMCCWI8n4rHaSCRi15vUNsWHeER8KLGa5yFr+S4JlU4
m7wmQqOb4Jeo+UGKkGbduYK4UBM9Z4M6DHfa1X22kQk3XsbZV9VzBk4nvYcDjFyjawGmX02qfJRk
uBGOt72sQ8Sp9y+JAJH/22ogXzMzcWtUccsVwoMvxjhEPU+PN0OhH0cSRJaFOJr4ukOBwHQ6o8uq
q+AUgpehgi4hj4eJdSe/J0mjUy8TxDOogbSyrbtaWYBz7aPvwPsnHrZZSEn/n4h+D0WluMFPN0ff
B9IY4A/twSEUkYEwM8rO1weqk0xQ8590+9ojp600TU3liDBY1OSwGlSvrsts9k5uJKxRrX4MX1l/
pJ3gdpUCLaobTlVuSVM8card8dxJw3FbTrlurDhk+kCx+9TIEhgXSsT8P76JQGTaiG2LCY3F3CLr
ObK4GV6zLAVUTDqWdBmDa0cC8GrzXxGgoZqLnFWSU/OiJVZTMDCp1QvzDl5Wnu3CXsVcPM3y20hH
APIO6iECth6yzC3iGcdwzwsmo+vd60GAeqicCZqzCQ1z9tsMkWGrGEpoXtgJ/UH7PBCSej4zJgbe
8KZJCBCmHoTSNTAXzBC8pP4e7HeBk+dPwTBsz6YFRk6y5K8t3XSEKQUuiLU2y6GAdmjGEgRPf+c1
BH3ovwHae7MF5iniYWGSEKtvynbbt3vG4d01WZ+2cmt7OrvisUmizKAoNy7e7ZIN8jV9hiXSeMas
pbyEgqVcwO6TVBYXbe0CYNUAVaDjJ2I46PMCPgELGWQXbyLVF0JqPpvCIRtiQZ5AygNJmM2J3xMP
v5njYOf8KlOnOrh2qsdAaRNGvSzbwk7Mm9muhD7wAnj63PRd3Cbs41sJAKKLAzm903geliBO8UdW
dCXlYdCX7XKT+1TW1+LljkwFuhivsEKjiTo4vBi9hIWggAWJ8vPYBekSkC8LRU40r3SsXWBVAI7K
kFpe64Oq2veHRzADr8OIDMKvTZMN8c49qYdYUHqGimfxAi1eBWofApi/iBKIZIXR6eIMOpsbkRYP
21bGlKgw+u2Vi5b6n5waRsj01TzMyr+9T2R1psximWd3aHv7ZQh7Z8wXW1vMiKImcdC87x1ePEHp
Z/97tec9WwCo6pwuAtICQPnQRwL82QAMjWe9wKQR4YC+RfCxK9cO1EL/RCTWdvwPQDWpeh676uYt
iOnJS+7ETMjz/hpPSUlXAhmA0D0y/b88FVPN6v+Ql1xWvKHLhfTSAAsSsShscKaEIou34WlE6c2k
dWo5f4gqwDLQY5xm7ViN2oDqd0PqP7QHhOzlQVHKvvLVE/jg69iEs+MwJwvCsulXQUeZW7hkzIFP
numoiVz6V4ETgdRSdX74XS1v2l+ECOejOo3MkJFUoVXpzxme5rbLuE21zq//c5OEe2SFrsOOxQ+h
+ucnY7MRPaKnaJ9zXq0cqCILa5I743Z6R/aX+IMhVLyONHRyLM0I2I++zBXWbM2rHmDMPNVPF2+U
SBpsmCeZifYksYniAqu1ai1mZ0sXcvOgNY7kbBomZNigbRCxfMTs8jQm+cfePFEqYkEb0/S3gGuI
/BD/Any8XRyf0CQpyLh20dhxyLUSi955aEKDlJqIlf6zMGGPJGC2XMqPR1ElPtwwpoVJ2la1PfTA
aQvBxrPZv7KhSkTVwdpba8o9yBknP3MCO1Nq9PGMhCVOtxLjAvVrjOTvsEPuRosw9mRDE43GNRBN
FdZug6pHpOBvBdIsbhkgf2yxO3vGQu0JmMtgqEma3LLa/muzWn7Isp0vrdUHznTrAWGR45Z35uB8
kcEnK6EA/8DPaJtzjVoavkWx+nMmMb+015IDtBiLZwiV1Np75QKzuKit5ibvofsN5GP23DueCwvt
hxv0faY7Udia/KlG7+/nzjlMT8kw80BgDWn9HRq1KxDdZleCIBLNOqDSqXhwQA1HEtqiopTKkM1R
x7lgMDHTyldl0X7MQeDFPh7A5Fogj2TzYB44t9WkPSisl3ca5W1S8Rn/nq28UCP9jn3F121/XGKz
HCV8bmYkeIUBmazPHgJzCNAzipCa2dkLEIefzNCLLmDTI7AMTTbGQPeEvmEPJYPxOmCa7O81f+w6
dej/PN7R//Tt2w/1nmVow45ptOtujDgfQYV3F3mhmE3g5JvcfGRsHrXZz14S01cAHiL/36ZonOci
Z71EAGe/eukF5XIlv9vEze57AOtr29FBuHbEafkaKtd5WPP3VvIljHeqR4Z5HDfQiVSFQbZoWamo
QlPUqoSNlDApdDYTvRcEpQrrmc67cbVPRCeSCOwGMmTbrYUMLsZB+S4/J5+n9jooYveXM8j3Fw3U
bHa4N9S11iqVoptwhLMov9PKCLSTP27m6CGQQ6UB/PE/sXES9KcWWIkbD7BhsvVbL9XOqIPb927O
Xi+1gSdVYtDdbUFN4g6dZnU9TizqJ36IRcl0r9f6bsiFwupGWbTlhjhnyD4aek7jeA/I0SXSLjyQ
I4/2kU/DyD0Xn65WbpIUEVEn9YUiC1pxSK7vgVP1+Vg16xYrFnzBVHc/ifvL2kPliYc80gcUcoaE
qRqwCrGwAufO9PBDk1mC2Hyd5AqlJb0Jg8AWVvFPyrQC7pvV2+NwkZSI2glW0FbBAz9k7lidnb1W
23mEAk4+YLA1hTkAaycRKHPVtjx+U0Luq5QkiN8FP00HlooRCRa7PXwLaPXJmfdEOTVgYtCGxpLG
N43PgkP/9yPyVR2yDcknehNn/4z0lKflVDBSjwgEuGuJvrNwKJNEl/g0E/w1pOL5X/pqL8FqQhA4
lpRDRlav5Hoov32AL7nv2fFE7wTrXy97lu/ySExedorc4OEOU+88wX69RVpIhP9OXDFkqzk2o6E6
CimmYIq9HTgannMOc01bhi53QBhMiSrPKGjxhNr/KN18zRUdxqGZGOGx0+2j1WbObfdfejeNHSIu
8AN/4zoIKEMmVmEhLqJFXlaM5IpbtH2wiGGEfY5RmpxzyLXpSqXTFJqJDDRJ/ojgUXtR2A8bBHvG
AXUWye7Uyk0OVmbfCN0z8Q9B62KF96nMWMsOJjHBP8dj2kXSpItVLSHU9VXk0LUxVOGyaJccry4L
RWJUiWP6SjC09jqch8i1gAqzo130rcmkteCXT21GBZz6revg/94NJT4XAbS8ioX3nNP2+X+5PYIy
8kSiSI75yllVbtqr+8YNuq/ZS5T3ryhyWcViIdnwyYHJdKLD91zjh3bsQMqOOsBwvYhoNceizQ3p
WT7Gf2EPnGs/Zgi4k/jSxBNNqT/H2ItuZOA+ZRw2rbOdeUGjpiUqNbcFvOxEL/O/AnmrBaNM1uUA
nkI2UszTXhh6i8W0wZHLrH4CNUm0UUnqg24S8ADfll9OOn5xKBdVClkZfwpnf4vgN/bzwBpPVvJA
XkIAMJQvlWkAe4zOwdvXuwd9HDX50XQaTrmb6SOK2dyA61iCuG8Q3uLM9yVZd96XsqpDiooN3GGs
WFD9lzwTnunN39NbPEKYK8RxgJFz9CKdYaDYp2O4Eo5BorqiZh7iJly5+JrgU4A6NsjgBZAn3faO
Tj5s+oI/UtJS2QbDtOfui8rh3LNrfIWe3yYnmEcL0Tt1u9+rNClxj4xOG9BmwnA4aguAb6VhG1Io
9rPeoSZvcy8KjeLdSMw3Sg5w6zSNStDc2v5XsawQgO3qfnRP+eyXlnLmgDf17rjEFYK/KZOhWP6E
274nkBsFgoEa5nSe/yKMrfElfxDGLCHq4BhsWq4Ogxjje/CSGVvgTzRIDR8r+3BNmxUOrCJ8xkNx
bUD9CI1jT2LFj1nLLmRXW6/B9APZEFFUdIVh4/wUIhuCa+MNVyr5/XKLZb31KJtQz1jMRcAlujVu
gjDCdpoxKMao98XxfZK9i2d3rAWRlMmQRHW61GlGz2GKQw0cnal2/7BkrTFEwfmEWHeW0qS0V5ZY
dz41tvYfiBA+unM/B8hXzf6d3BhROzyzyvmz+9HDlUMpADH1dbkx6q/Am/BCSR6HO+MJg4wj3+cH
G/wXNFjiRdO0c3mMZ43Tp9/FuS9ALIIXS5t6NFUW5wh1HOo9+j4I8+8dFJlMMAAoQy5DOiCqqb97
7WVL7p+4HrMwlvwf8P1Zs/JMJ58PpbNr1E09PI2xIFYP8wBuFbeR5N7xeJi8cqGrKcEaUvbaU4iM
Uc2WRnnB+tBeiW2f6Dpd8Vo9hhDwhpQ3jfI94qvOaS5JREwOvc2D/fBFhV1RIXsYbFni6yrn4ZMA
0FBuozFcql72FdAlEajfrtszQoKqUH6t06NonphYj36dQWu4L/HKf2t2t+6Q0IFLQ7+Y9D9NrXQw
tWW4uvjTyCkAlukTXVdL98aS1SJCyuf21A+rkuJ3Spt/0WmvVjTfUlSd8RTzBk9DRKNFcFzFV/qj
PStzhXjt1fbMHTZ443hx2YyrQhoTqW08uwPh8Q76ZB8SLpUvLm32ZAx3BDUpNhqZVH9XX86sGYUY
5xlH7BgejNiAGbxbuPTzMKEYgdaHDCCUgHHmsu02uUzjZHEnPmz7gXBbIoMFcjALLAyo/vrGP41b
wLgD6G1adoCkpJL73juGphYcv4IhmOdOG7qSE+iYjFmU7KWPLtCau07UC70XeJOtrNoJZr/v6BBs
85xVln5dOt1r6ni+lw2269r3+Jk4NYH3nGClkHJUr0B5lJJzFOnKkKCS8xG71lTDINnO/KP05Biv
1xiap0hD22y9QqhCD+IwxCd1O81qOOAoLhQoBovJtCJ7FIdCnXeaDUmNOA951yh0OOa0sNt3skSy
b3PlMGXgP3ad+PqdcDsk54R4XsMt78CpPdQoUceNXDR6Ghg8NuL4IV1LYlnedvM8UjE3vtKX4s8Q
9JMx981O44aEphvC3+ufVjQgjyE/akrI5W7YCTP4Z7aT0oPe7MThfwsI5wKv7ljlT2UOz59/mLam
V1dHbC5f3UjGf3my7E53Vrapd9FBvhCWcbdkQN/mo1JQONzqZbfWX4h51imCYnYkRISnapFdRz3X
NZr/KF8R4o3kGHs3JuyuvVUNBiDgETiFeV+sXa+p97s2ZfmMa8LdQVaQzIzyz5b797qyITGWZE3F
CZBtMc9zKQEXwIXp+R73Vjbj3qiWdTPTtT4scK/jwqzNV00T5nFvdvob7ZEmgQ1xvqlbVe5UgiVM
/VfCPEp8kY2J6oe3roz3QHtZZRBKmrfONfGLVZWwPuL/UxBG+lkhfw4oLgDd0mXtN+DZcNBlGjC9
IvRnDZ1GPVCuurmw9MtjYlfjTHSAv8tIqd7lGF5vcAN+BxwWOE0gMXdPZFkFRe3guFikBw83qK9q
DRjypiC+fkVharxGDvHXfKXK/Tykkz4lyKA4tL5we5224GKr3NFGkkd5uum1Pfe+yPJw5sjglGqB
KATpZRgPv086M//cRMmvd32ea9H++k2PzqlxaAwX0HlxSYH+Iusau5cFtDXQrGocDWv4Cc6V9IGT
GJb3J5cGrDq6M76OK6jGygFYo7/cRo563ijk3EuvuKT0n2jiMYoLedBTOAWFs6dYa9xRDGdE/r5c
WPyVMli/JLothfllMs64pP30oApYt82TcTsbGoSlxVHjYAc2S2C66kJjtmdio7+yGni7JeN25Wt7
Jiqxw5zNa0YDapEtmwp4liTx8Gu7T/RVp3cZJqdvDea7J4xe1OGa7/2aTNyqIJIjqL1qfTQkpgK5
3+Dg1i4tiR4CNSkfZdWEPLWwuzK/wsz0fRJ/qdV4L3lGHYRn7yXL45IEfCmf4OhE0n39PQhZ255+
loU7h4LoLNQtpZLz49i5wbk/UoLAhHFDBnohTSIykpHVXJRkAsglFWqb8Z7z7y3OlUEVBATwyPpI
LwyJ+QPElM6k4dIYi3qY9ioJFE0ynLL6/1Lco0MOGIK57rlGg8zko0EEH9F6CPvIkpNJxPnNR7SS
YwhXETdxZBCgrLRtrmHqCFW4u9EfZlelRl3ZanFEVLVZpIq0QzJtQ246W3DaMnU9XeDBRA53xErz
0Z4XjiAp6XcSq+3msI/NNujYuJaCfpcq+v2wGMFXPsS0k2/XirqT1fAtI3ps3LHcyMy2p7COzn/b
KpqnD43DYjAHiBpCZJ/NtMbOsj0swoD+zjWk9FPKyR1Czs9AloSbG0A4HeyFHPdMWiPY5D0ZCzHC
Ul/GHz5QYIurya82nDlIwm1la7xzW9mOHgj+X9Syb2BJq7GMKhGS4HKaQ/tQTKxGQARRLPlOfRe6
og0Rn8RPOqlxfVrU7npjPohyG2DO5aXdqtzHVHYrieFffgi7dXhjPg9Hz1H7dOTfU9/DtpO6v8g1
3CJru/wkWflcCRG6HcTCNGfUZBlITvVJDPlW2+HATY3cYrO93rKwj23lW/8Lcs2le+sO6NES5YPg
JCiRFsmBCGZD228ARGxhG7gLFyY0fDLxfryp2wVnvbeGfF436ssTCg0BxJ2/BiA0OueLLaUMe3Jj
6foEm9o3mLPcfctkrVe9oSTbckQBfRArjmD7PzsCWinwcahouE59ab5Oo67lNWbnwzVKy6eM5uNu
znQ++aYAPBYT2Kcaxl7cq1u5W+35fvxZeulOt+a/efqoU6ZeXNPMYNuvuJPJ3G9V2ol8+68SiqjQ
WVNvnjLGe5htYT/J16UMmCDUHOt+neWoQoQ9YtICqFSUrTYLOeCm7EKyuuVGnMGJF4HokdNHL4/9
EBUA0693Tk6qLizOkH3k+tPsll/QEsMqzVE8/b375t+1lW1gg6R7bkluK73YwoLAI+o8ejVvSVHK
dYBfA1QaCkPaH1OVoFFDc8p0eN40FpwoVA4z3J1qvTf9IrMgzhGU1UDJzFDKybLXjp/1SheHh+a2
QxaJ1bn9Lh3TJdYP3Ju8dKvs0kKz0pAfePARmxQgDVd6E4XqwU8lGfzxCJfy1nhjE64czP5jecaB
hDpwUDGLuMCM5ohsr05/qTIweaM2zD3MT7e9azcakh8ald44R5jJQwq5DNDX7dW0R4Jx8M7DCHfv
AtS+gctwi07oTUY80PSSzKPjAyRZDMxhNEe56wi3lG0hkK+Uiq3FY83omKum3evo1/XUVrXVlIsJ
9XkG66Jd3ACfZHW6/4XB7nuHB8CegxGU9ncWg7yoTXQbc49pi2IKKuLhm+n15s2CRcztOdNuqxjk
1lUwQSsfutIq4KAo1g594HWcXtEqJXnfJUtUO0Es6noM6kFSk0/Px/FYiOU3Gyv9uAG9A0Nk0RtE
BUXd6oEPJViVxo1y90VmU4vAXhX1tLo25eX8mQtr5ONLBnmpaZh6nVMzTn7yR9/GADgyycA+RNmy
t3YuDlqGWM3FtZqDwazVO29F/DA4F9zDNlNaNXDva4r491WxGzuaJZiVxzG2hDDu4Uj7i0J55avN
Q7QSEaN6pSfTCN3TIL9/7swbWdUyebbRf5C9krn4O8YOTDHc315cgBcru/6jMb5NtAbPxEpRN3Kz
5BvY0dCada7qvW+dU6VrUbXS4DLMpMufQ7JoK5IFdzeqRyFdZwxtwz8YkkWehG0pyTmQs27Z0AgW
8lzQkgE5/PUjt+o/xAV0y2N+DXHex6hYtWnXBlPZShct/kJtsgEEtjqzsHFu0SIoANakQX1HQ8PP
yP1vaSnZzj+jIPd/UIlkqyKFQj3ddJfjFYoxfGomsGfPTqJnUJLKzkeeIj430aV/xlD6L0D+iRnB
ymGOQMxAvqDjBeUjlrAPrKypAjtQvARLoWOa9NyDnxbr0bDBHcfBfKeJLDenzjuZAbI671gNtFo3
ikDO1oPcPz3nhJVo7iyvl8DFZ2neTpa5dTgXcVja1X7hVId5UuBGTHn18loe5+wYWG75ur78JX3S
6wvknc/4RKTlF3iqQtjLQGkiQUCrRNgT6EETirFSaZLUVrSK1o3OzJc+nnS8VwLYYzKFSH/sCnBZ
SmZRTn3k9u4stysCXpgoA9Bnj0IJb+jAfXPPWSvA3SqHjm68e5aND5NIp/8E9rJXU36R40u7ADCg
F/bPBZVfMMS94nSf/oZ/h+TRqNm41dyoo1Zrv52orjg34iC0SEQ0BPJ+XXfsQTZkb930CQq7IBH4
hvmEdtzHo2Ss6FIy59XDhWHlJ8lZOteszJO67f9WyLXfSTUoHzOrErmLopiVqTHKGf6vTt6eZRu1
ceYUD6u2hfgXSNaHzOKD8q0ZH+BpFhg+ET5u51IsNv65uDPAwAuy8ezLDzkhk73z9CDe/psFjB0U
jAhLTQTsasfbjF4ch93MaSi3DTlRBpli4Tmj0bl8AIovkFaWO6jm7hozoEFZhdFJKVdKmjD6xLzw
R8TvS6XJH7OdKBu7NmflqcPZNLhuh0IJBI6D5IebPo8e7p9Zd9YerSJWAkS/RY0CHyLrx3Xixi0C
lwnA/1ureyGMXwZOumLRaNLo41ZXdI8GbgtwDk8IyBDPMsrnlnbgxbi6nSM+5jckOG18nE3xJ6ix
aSEB+zsmmUnE2UJqdGz8ehtGzkcb/kmXttKnyjV1hKA8C8UvxH4RqJ1O7az2eOp4mEqlzireFszx
/zCoqs7gxgQYMBrEM2PLPHYGqP67tG1GJ/KUeWdfpoNx6WVlR8FZiIwyew2yYWYeb6LZXh/8eD3i
8tuFvEeQrxv/dWLN5lrU9wFfxC8nAAwafBZC1EKur4BSIb7TWfB5b2ueKoTTLDHZXvNmcoJwtoop
wYgwkSwMoAP9O5uq0lY+IXwdVlbkJVb6L6dntH1LerqCVGGjv3MTKf0lEEd+lBRoSpAQBIwfikA9
kBeB6vVCR+xP3X+AKQtecRj6/ZadqTCHDe47+4MqO1cjyeS+uE9RI11e7z1oMq3gDntMSp7LC6nl
NoGC/5YOxoDp2pFvMfDBfQIrlCaJ3uRiB4MbfXtEfNcCDKax1payDDAebrCQY3B8jKFw6vii9MqH
R29VcQjEt6+WSn+/VKCpoaDXxrVseYv+hQ0t3f026UeRDcv8SiXCXLEwGgLQJeYxQhXACw7Poqsl
ezN7XacbRifNmKo3DAzfAIUxtV4qrnyVJycysSOcM7DGS2NjV7dEf1BNzcUZVANGUi4SQpjHy203
h9iTtvoD93cAxfZpAB+vReQKpNJSFdyoFlLabkeBuon9Iomp/2iVRoz1rgSuAiVRY8xbfI3PMiZD
QVKfUU8kUgaPurUVOJZ6ABk2WOmA3IBUNIAXthuHnIO8G8C9pwDV4L/TgwP3T3vVnmgEuB2aNEcI
Pz4JOCeCWGFWrlMcfJjdEtGoNmB3sx2dPNmG60sGZN6Rgown/bFtBu6EKifrJi4JN/17PT9cjLy8
r2+m6/8v1RII9knRNCuAITt6fR4l9w1IUK80SZF55O7C852lVha/IdhHDbV9A1SqWndy1PaCo+2f
0LQ4DuvjTHLuPV396wCks/XDYWD8G8BF2YrXBgeGCemy2ZdWZCHNTfultdQQTaGFcUbO3l6hH/Px
AWglC7k1k17wK723+T3u346l0K9tjl6k2q8yQkWiuT6LaEvpRNc5bXzGvflLn86dH2Vwg+sIqXmC
6pDj1JLStcYuivE2FPqOc1Jc36MxJkZ/ZSu9oyKUNilvtk/z1qbFghctR9fdz9eG0Q50aycJWejm
XUwJGaYVtNtYv6MScZtil0EdDtWgpv6hxzpNG3WtX8+mAfz7eCg7XyLzwsmvUHKUNSDZOSWWgAIC
b1RwzdzpXju4oW+u+QiElkDX4UOIldFqFVmMxk17xKj6IOETzfxxk6xygSGT2a8Q2Qrr1cNeGnD6
kdDD+yjJ7iG1i76fX0/+wlV52hDE3/BhRgF5n78LjufrcrlspHBBEuGfxObvhdqbRpczSAf8MZ6y
WdBuFyxkOCbmobkB211PsckXUSlu/1I8+a+nw7V7NyCeMA8af7yhd/X9043jNcUlAAOqdhaBO+lN
Q8uiXBFEKGsVeVsl4gAySBbUtKyWXy4PVRCQFgOHsz3dS4Z93HKAk5d2p5eIbWk3IfhRgbrGT4Qk
C7JqFH8sIDS78RQc1e3LWX4M5KL2MoCL95IUIKsvOjHzi/k86/pkvUccyD7j+3Up/AqC+A7Vj+1n
1dui7orKDdktidZRNt8fSRf1yUFHRMbRC41f02yXctnvjLsBA3iiakwVwDyyG4l4NrBk9pK1+fiW
3xWejYcjwWhMm6UU6IXk/ASgXWFEx8+T3n/R9AWgPyZU3AgnsCK7zj4T7PpP9jXr6Xh262x7lLwA
n9dQk5DKxAtwhxAx32DG4kAm2lA723coI3mgymDUoiNbsB0uHlsfoJ0kgVWzkk0wX1q7Wq8yIYeV
GxMZoQGWQ8BbovYIEy/Iz9itupZCyHXjhjnjP9JZz/lr2tJef8tok2k9RkFaPOJ/wjllYcSpkg0U
oTBfzugqNgHEHaPQRtUY9gbNnaYtW5X1AntgJhQ9oKegWDW0vJohJ5RjxqO2Mu4tKlRe2RgrAZaP
XnJSYv+ryUHYTHOG3uS9ob2JyqnJY0Au/KoBYeoga4T4h9lVBOg443PQr0z9eHHf0K4KBremI/oL
tsxpwt7yH0t5K/62N+fbVNCyw9CoaAewheH5I5wLuSsFe/HOspLnkby4AbhSUr+g0KwTzY9eb6vV
4E77OYFpVwTtvyEJcUZVP7qwKGv2lbcuJCHIybeSBSl+AXd3e4e3T779/13tSsC6SkC++Bwt1rpn
+rgSo/VZWtpirsvKCfMqOwpcto+KeBGrO1w1hE1QoCw4XQV/iylfKJxTj+l5pX88swzz/tndTXw2
OWhleQS1wPOrFhoVLPO9owD24VcFf4F1jEn22AQWP16sN/zk8GT5dogHu032/mME5M1GcESGox1P
8vNszDq6HCGA/te+4IT0oSs9RZee4btU7g3bTNyd2f349X56TfzhTiUg2LrFlDeWfeqBF3zNDycD
/xT3HmN36qNmNih300TJk+mW4dTilPDF6yFVTAebUzSQVttI4GzrjdUAF3K0GYOCrW+z9xxKGjj+
x3i/mCkuL3/2Y7wKTnEydULeDXQaBM3TTN/owUCl7V1VkjK4YHZhjXY+CB/xmL3ODEVIKEtrPh25
Hk3A4Td06wvkslwjM2K3PCdg/NmFvV5JEG0qb1ffRXIGJCOFRDAg67EwKLTBie/dja4+o7idp4bp
py1Wr0O15+JZ6SjnwbIMYCmOidWirBw1LFIre85qIllj7ZNRNsbZQXZqsqVTX3EzEkWckFAACW3G
WtrwE44NFKe1o4CRt0QsAnEF0BqqkqoJbyCFscwyNoYyJuUAC7yv7wT+ImhM7ua+HoSbAsmgk4WQ
E7wcV2Ir6x3vi0GOdySjUgJaBnMLXjSejkrUgzeMkID/1j5yto2oUwC3XMixJdIGL3AE75dqlsXv
aiAj/QE1AbP3Cwq06b2JSI/+aSDIVcNJPJjVt1mAardWN5gAPI5nS1QCVf20Pgy0xoIHISj8vRgl
NnGNytAbcF9ROLIwjcpQzYGQRgYlpZzolqMnBL946U/0ndQfIg2RdEawIR1vgrh5uu8McM7niine
XHvVOlY2oqlfuLTidFEK5xBQH1l/bvasJwjKjvZQ1lerRa6aEoaMxKx8HYePOwiB++KiUFKgtqQw
ALzmWmpRYufrlsV2If00QovehFcIVX66J3QW7fj9Jjpk4sDcbEuHOszfMlMTM8OY7+Ns+4LHdQYI
TuDKWSusi9EXRT4nF7nhmgZJBcVafmGcAd+nQUFHj22ifVZV33gApG/6mt0QPNWpnD4hNFf9f8C7
j6nEL3ayuT/YxS8zAIxJkd+F9eGjySTCLL7I8pO5bd4qPEn6jKHiZCPkZEjlPu1kUrf4fJlxQSIJ
gyG1F5WipPTWUWtSM5ZBIG8fkv8KDOtHK1p1AquLuaiqNNbMk7yaUJf+njqJxnAxFreFcoaBNd/t
YjzvrBSyjtXa3LXWTlVqDKUx35LFeQzHqDtDVhG7WCqouW4Bz0QTmGwFgL55fT5nRxEQf2cqDHLA
etIODnWU4bvppxi5+8pIKw61E0VVAkDLZAg1Nev/4X9KSrfLZH8KN+WO6HtMfRnMF6S8dkBirUuW
ZVJTS+TPGQxz96KSDF1OGlRH02ChvSjHqfXoi7QuMhvMxAEZRA4Lxh8X4FfTBLSoWSU+sk/LeYVW
uwgZ4kwwHYOElvaiShcH+Maj2++rTWTgLbXqt/I4jyB+3oX+pL3k/swlxGO0DA4nZ1LQLc30kMGu
b5bIcZ3EdpZOdoapdsPrM/TD2nQGMGaf0apzuPO33lc6jDYJVruIBGk+DATgYDbPyL0FCXUHz83V
idbb5PmA/wAv1TY17hGG3sEmpFmspRWwvfperjulK2fOiqACgfxQw/GBQ67voWVlfMa+pHOdLoYQ
6uqI+EXkHD+dTDzn9oGWGAyLbN/gOMQdU9lUnoN1LEUfY4ngFJxf8XUAN1SVGebEFGgKl007OuN/
EN5bk5PyOHa7C70l95huHLrIbsFh0dBEkS6eefwm6HcXRc6f4MxUfCLEuGMjbJEsiYx2w+nFiuKp
duPowQVjQSPKMBCRwsB4WQ9OKd197wRrip3tOD5zXigMGG92jR3CwN+PgDROicvECliwE8Ov0qWi
hmymHTAbgizTmmVwx40AxCaHSDFsfN7rIuT/VFRnJWYqKSZp/ZdTyaJk43rFsSlaqTP1UlwBzHVS
mDc23H24vYVowLSbP0yIzdFjLrr6HQeuL3mzPxDSPn/lKaL5zpXK3PsaJmfeRwIUtTaYEmEZDFTE
tnJVIW+SiJ/41ykZT6ePm1s3S1/zsuthZu7n6JD5j8qzyDPQfZcGbzVDIJqrPw==
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/mux_onehot_f.vhd | 15 | 12692 | -------------------------------------------------------------------------------
-- $Id: mux_onehot_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
library proc_common_v4_0;
use proc_common_v4_0.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/blk_mem_gen_v8_0/blk_mem_axi_read_fsm.vhd | 2 | 83879 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
iQhNoP8QJ1+kTr3K1ulFnGXGJShy5Jff0AwqOXh+IFE5P69Uc53qVphYu8R52BLkC7tEaLSbbNWk
YC1DFRJLXA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
QJGPslOZ4HGlcIUvdMcabcmjWYtY06vuMx1zfz9OpVbYgdasGwK6H4xSN59LFRI6qJyNoznQWgYO
DL7eXZ4TuI5mAw0176hgjDTCgN2Ia0eTGF0Sl7jqVGmeZs2MramdL0pnQrxW0TCcY2DnzWIU58ur
Oc0G3Q/a1VYyFtXGry0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
U3kitcmcD1cUojLRHAQSoNQir/nzHHrSZ2ONNLcQ5d/XF7uI8St/l4g646YZhE0PwD6TRNd1w1fl
RfpD0cELDyvb3Wj/MxobRgDyH7CMgdX402Q2Urf5xhmwq+OVjV4MGf0wZXo+stSs8CXicOPqBEkU
/YuRTep0Hju7WtwT3+uKbIZRyIRA1Vk/wmPK8UFzNbGFfMlcd5zF8yxIFQqlrXW0MU2wZaVPnYT1
LURH/oLcGqBNfssnwqgZvsvLD0dWFA0OKDExhGjnDQZhxjO7cxk7u6NkBv6cMuA7+VbyaoX3jbsF
ad6euhoCmFJfeMQ8aYjwZWorT8osWFzS3sMrZw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gp94y45P5qlkd4FNgUCfw30qEi7KhxpQlkcG6WN0qDS4BWSKePenFr4cPG8I/43fIPS0MZnG0vAQ
F9p2z4F0tp8yWRRZ+PwTT8ASQfEYXf8L92bx6Svol9sZRFGHhvJDzOeUBqT9I/SJt2LKdszemTmG
+yTQv1F3ve2JERd4sMI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
PgP2cQog1+8yNsUwxS/UnNLSmW7LcV9lfZyOw1zAqnjpCYcxtPWuA7DaCeJN/qFK9MHFmIMJiA/R
NY+U4tyeTdjl2mTqZR4VX11LTGKSehX48rrehB0tv+LKkYv/Aj9aLKWVOo5p/EdGkEYSXuwf0m5V
0d+VYCC+jToXhmfiPStDoK6RsFnC4rL7WtmD7RHlNSDxhXIOjLJeGFzCekXnt/OaCzo2wZpiCeLL
Auy1zvoJlPqUqzMm/dP57ymuI72a4UsiCbwKUAZGr9YPFD3Go8pgJ0OeWEmey66Nxx6E9+34UQeh
IrkyG3nd2nlVF7ADZZJVIbjiImxoAVV9P447Rg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 60352)
`protect data_block
ZVJAOQicKQTcsIQAAkotfXAHb7AtSN26XX+rCp+U97b+mmWqlxJRuZzykXizFE+E6PGD4FcKCL0a
quhSS8tQSWPi4CsGvGZCL8tyR2BPmDpUo2faIPyZPpAn7u8WncfxFmHtFZtrNDqbswiuOUY9rU4q
ajKPpS9ghF4dC5I2RQe4v7u5E6pA7BUNRFbKAOTvPSRwwPoSmtizBSIZKI9YI1eG+AsIpe2GM/jk
LlIdpcr+KfB8BFbw5O44YOY62LdOJTdDYDNTBdHcuoXMVgSGlh/xvr6aR8RSb/EyxWqGjUXV7oqc
sQZ4l7yJ1zyq4/E/q7LxN+JxZtGt6Uu124SInvsOAJt3KbxWbzyylx4uqlw1N2Fm4FI0nJVuhOxw
6CkGc5TJx8X3XQpLtOBuSrfFBnIkLckiCqtdlNwKujggv2C8m/0z2SuY/sMqmEKacaZ48SEJqEln
gN7wmHGxbj1h8zl1L6Bm3eKSub7YZ4/o3T6ZD8csJGFSzyYAO3x/WcnEw/tblen2jCu59deh7K2I
A/kNKm2lgk2s+muPwvFy3xmpYLxJ5VQyLYwqAji/lhJKmiHxF1R8zBqhSM5JTuZQ0kzvjTHeF8Ft
X9GHH7Htzv8KPJolUSefR5zBJmgVlyxfqbuwQ0eCO3tWlG8ZpJV8HOqq5uhe523oxIjJ4/87DVnr
wkjKl0rOIJlPGgDDh9/GCplJLWRIw60CNkQPmYwSS1FIOcNQIlI14MgR+/c1pRIbZ+wRsf4Zs076
o/AMsevrRrxpWikUpZcm7SYciWN3s638K8gBpIh1SwJBSBMtCHr199LTcZdr6rmS42G0svP2RH9M
Zzwg1JqoT5Z3GIJGUJQf4GbRQombtasUINSW1XYSnhEMx380xiGaqdNfqumuSjT9vS6/QwSEyWp/
5Rnl83DH+GatRm5hZsvZsTg8CyRw3YhwF32MP1jkqMYQywQURz40TdYJCEFsWpmJtqsaPxhnQXre
Iir+h1jR3TZvPf3K9lkdD6UrvI41vBm3rOy113p9K91eD2H7IwHM0wCrP4WuI2s51xRa0XAk7CgP
pws7cVKH1wiYvsh4mXewwN8FAau1ZQniv2jJ+Id00tyipBZIkAytoXbhQfctFF265XqLSEAkJpd4
Es8WX95bqZH2h65diVSTEhGPUEg+cetvRbEVDk43VBRQAQqp6Rce+zomrzrMzOxEeTJqcvBSeROG
Lq0+ElmmHEn6IkU4o68+Z3QaDlXCDJfj8nG1bW7o49du2ZnTDr5M9ZsGAAorE/zRNxsxPyuAhaPu
vCmdPz/ZEmOxe7bJuq7QmBD+uVMPkn/Q3gDKQPN4jjVSRBz8MTQV8a4i4wa4ihev+rm2HBK5RchU
54oVTjWnsWsEgA2WiSBHgeSaz/j5V8a+POlzSF/AjLckZ2om5wCmGaMrtDLzS9ph/bamkWsjOB2P
IFGef2eDjiZgX7Sl5FjTYNco9QD7HWkxJ9+mTTISWq53k0V7JK/fUs8KKmgskp1BN0Z2sen/px+b
V6tSZ3lWQEmznF1B+MyTZNFmkhgCnxsB2D7sn3JfftMMmwUr2DecSmIXbeGekv9H4loH0yEKvnnr
46FtRs+NLGHOGGsmKBUhTtvyljSEOqWARF8PKYq6z/4XwSNHCSAeAi+zlraugktQ3CnSL6jYItw1
IJJzG/sXfkZ8eivKf/xvuCxWH9QecWv2egIjdylg2Fc4gS6jYH1tLyZvAUIfCsx/9j8GBDVEoekS
BRDaD2hbb/3X9R6TvGsxS+oNDuV9GXbDqzx2CbFYZ016TB3VznIU9WSZNPzOjz14Sgwq9vdGBW4B
b9WkMRBkIwtUhj9dZQ7LKe7HOUjmiVewDx3AY3gVTFA2MVayHwgX9Q3t+Rp3ENIKUkAF9nkjDTXM
2kepjcsYnVWOLi8LTxrtlYoRKTYcEqN+WBPrcn9qudipEzBBKWHrOlt/s2J3tFP3BSO2AAWyZyim
7v8//Y+RyYdo/dmqhi68sNjZrcJ6beAMmsYGFpVW+Zno/NvG0k6G6ld6Ye5xsS+soaYVosNV9K4c
jw/FZH21H+pDfVB455PDJldZK0t6IXigERHZtg89PI2s8opOGoTCTqz9T1ujer5jg9p6DDby3I40
AsUHAn8vVrkSlLIcbOIyF2izuOpe9x1FYZwv0WHTUqUOvPJDDqoDttXnoGa65eqYTqEPoD0Cd7Um
Yeu0w4RFHPOmHnjdpoZs9wWsrCD4JX1jSwIAEBUoT9otIaDnHdYbDmrig3TR18G1y1IC08l4AI0A
UuwWOf43jrMMHUCP58V8SoyG5flYlzAxfEPCirz09kOUcFUigORVcdt18Xn5V4QUfz/U7hi4ZVRq
dF9qkIm2bJmiVxWzKUmTEebBPies0ngy9l/l5tSBBMpIH5uem4xGrpllJBQiB8PyM2uezdDteh8O
WREq6DhQFz6zguHiLDV4POkfHnivZ4gJXFNTHy0yym7urdNNIyJp3XjSQO2BxN9AKL54ZTPEZv6C
3qaoEpimDzTV4MYAWU3wFfp1YBKRH6c3Etv6I5i1WWKbF8lXv2cNlfj9UcQGEPNXzLS0UBGZyKBv
1YzkVF9/MNjiYapXs2ZNOuK95v+t28tKsBxXl4fQIxaPeL1BX0aDExeBSo0+r8+lahUGiQwZnVz5
pbkUeXvTEdBB3zlhYLEMdlsakDWlYjhGnA4Jf9exMWoMr8U7jucetkhUpUDHzA0dBH7n+Ib5ddhY
A6xSBZwhygDYSkOHuVXA1MvLLDkjzZ4JpmyVCvmWJ/bIdgayPlmZnOaQEhub20f1vToFC60YCO9d
DE0Tl6DfSG1HYbPGTDuSdtxDuZSxeWXIy+otXvw/pXg2/7htd5BGghk9cl0uZqLhy9Nt4K27+jJ+
LN2RSAUpfA0zFHWnB4A0/ZZ4BgOcdijd5jcVxeUHaXJjIxJHW6tKQtmsz+OJsb55TpSpcjqsWn/o
FbxdGQw64OzP4ALmpXU+VfPjecVSwFsNrMebkeWO4jm3xzlYL/bte8Wp5nSLwJq/Mnf/8U7EkpOJ
m2TUmc9OYRwfkqDIlAieZWy5p7Z2SvwEavNwtt1DDwkRl3c9Hm8+ySCi1nL2eHsVvEmWwll4drWe
UgqUEKc6rEJRYN9No1z540dx7iR4osVzzwAijhM6lh02A2fMuhx1qcOsVgWECRjzJ3LF8P/9zxvK
Gmx+pSBQPfLlF6lIM40Vja/OMc0Dr+gQzkEF9iZLza7rGf3Eg/rSxzHXM+t18kyguV+zBscrdGhe
ZM+7S2DbpKqKsGAwfXy1U11/eR5nANPFSUoxs8DpJSjXGi/SATJ1VeY1r+x9FC/CSJ0lwPlVwbQw
r/xgzMbzAwCngIl4zUb6y1rXel7dSjTI8bzLKfKE4lwNhVGOoGMoc1ri88LaQBrQW+eqCx5hVRua
8sGUcqNqh+CDOyomynp8b77Je8tfN9azUmAhDN9/z7QeYWE0JWBKBZ1sTgGHUTMCcM4FGTGZ0EpT
gQQoSHnaHdIZvPt3z9WiM1G1uPXkvboZXjrnx3zoVyjMjGJhYulsXFQ/LGuOgGs78HmJ75SqRUUN
fhFvtTPViaCvVeANVCXCBFc/bJKawCOLB7gjYX1niGXo3c0n9OU3dE2KCyDbt7bjLv5boFfVHDAf
lsfmzk8DweFuj47qAkh8/MdazsGrTlaMb8MfVA3bFThuPrS5m8RWNboOavrxqLShkTX68IRJdhlj
f2SCikP72OHqegu3n+ZtbN/cnafcsBIxi/AH9VHNI82W99hvQy1ldy2WO7NIElvW1CuWB56fQNRj
3kRhyA81x3+a9Lsxr8OCrmr9fCnAWuluY7Tb4AZUeAt6xw/dd2bjqTlxFXKBN7Rfk6pbFkCJ0qxX
AR8niqBZZfsmoRfl+KGPk6oCqODkUgvDkrUMVY8FMgzl62qdsVvW+hFR58Rv+mepGZjAkE/56M0k
XCNMpJgPfxGEwXK58SYxLBKFyv10oM4SZeZhNq4u5oKlvkfwSU4PVh3E52W/cRqLCIyhlAOtRKew
AomJLl6Y7LHvhxuQC/i3cDCBsWJ9/0ETh8B2QqpYh8GJykIhGZNXVtYKVQdGx+owctGjmj/OtUtG
7yjRyCH73/SrLvEof/0ZDyAjXghoSH7QLlaC311vuqIN6/9tvyX/GAGO2KSRJJrt5hYptXnYD6rn
8h/MlEDentzBMoTJpubfo5Ua2qNEpFLBVzQVufK4pucm7c6nxaOtId4XS6jTB/Gw1ujGW0C2VWQy
Rv0vGxHFK9McVz21nohlpCeOTpHdNgoV8Y9s3Yb2YGK3zAQYs+jWfrdWdLh/dHSDZFoEO/vgO4ea
8YiTPXAQEsvyq/gzR2QGrHrLl/wVzLURGh0EKtNoWAMQaGry29XUHJvo+wDxkx4g9WbkwaD3kaic
2icoc1OK/l7fhjnUnZmy5dk4DPSLsMac8SkjCuI/3a1dUICixmN9GOB/LLnQtFu/fQMpKt3XImn4
l2zfcm1qku1KavU+d4jLIoV4K/cDQurExQXfIUCQlP9AZ/2i4w98rNdWje0Gc7BGxd3n6IX+oLKJ
QBTvuQgER9+nuW2HFiNFpnChOhWYnDjBGeVShUrec1MgNO/Bx+JfhVyxdERu7AyMCE1AdZxynLzx
NpOCUc5mlbfZymatWRvvcqy94zO1K1/0Fq+diT8G7aScWJzsoHiy0ui2bohbBlzKdbdfBLTAIsCN
iil0/Xyp2vQ4bxt2eXZHy5P1o9f9Fue9rfwPJUYm3WRP1beuiXXI/GLOLUzndtNwD254ZWtDiYJo
KQHh23ZPJO2WvaXYL6hnIVWAcoGTnB+wLS3ZjDn6oaQmTi0qKwVsRhw62KzZmvk+tNZfI4a3ZefT
i8ZWnl4C5/G7OdjQdmHMlX93pvxeGQhkWqwmqUJJCPRnZ8eLH6ruTQ8NgwQ1X6c4Q2qsYKbfMJFz
5VZ4QiHW5mN9M2Wvrqat485FF5Ev5xdNeQmRRaFPN/LtH5Nt0vd2c9qwkMNI6LujLXw1WCuudDja
UzkFC+bol4G4CBMbvrmJmKSpteubxkd+OXX4JJSDwRxULJovnNRG+uSMVll8tYJXNumdhsCOjjDQ
0hZIQmdjTjCvFJ2MrxE2XUqNi6+LGC2mjlqkq47MjlL8k01LIHiGGZfKRFPXp0d/e/synDdCyCbl
+3RmsV8YGec74cy9/AUyjjUOSXTQ+K70XPq829NuEyQTq87v1xu1eKsiwMSjvkAou2Q8P9Udo7VQ
9wNYYMJy/+d5Y5/6O1qcg78hBBK3DSwcFeuh9xtK+OsOZW4oBvCu/h/rDFbUvyKz5vPs+F5PtKDd
UtIqg5ndp+wRVYySZYGSIL4Bv3oiavR1/DtmhOEZIUKdwIBF0J5BDx7g5jp+xZZubLY99RKnrQ7a
3WSnJFnP4U0h8jBDLTwRz2MLBzcD4g9zJ9XYvOARRVk8wLcuZ90WPaaSrd+WfbjvOaNF+EKnRQPo
dSrN1HUeL/70TIwY18EVMOsuPYo48dow1A1o4lpF1ErfTfgwfhCOgnd/LIKbKXFJegx+SHPKmXRc
xtbU/+PBxxC9YEu2Nzm97keEgofyBk8GOz2gm/YlPllzYvnwVBBAfAWlBfopAiSDT0DUTFjjtZYG
niLaoeZXxycPuoKxhNTp7clQLaxjAK134i27la/T9bDZ8CzvQi4/A/BtUA47txew43kYojVZV3/E
oQ0NLj5rZffcrf2KAKFQ/ud3Lc/iWCZR9n+adsNRkiXl73V0sFaJ22AX0EMC9IiGjPE3flwDsAcL
/h9mLtQemo+WyAO2GnQXS/pudCnKH9Jyh20dKKOhKzORKtMoI9szEh+XnilUW/IeWPKvRbIY6G2k
ESRpvTolFJCmzyAyPnpyl5+/4gQayR1+ktwUfHmgbsdq38tfXwvGjKt3AjIXvpqEg9E/OgqQOOto
3adnGvJjvj3QxkXxAO7KCkCgtP6bKmDsD/AAbRO2RKyiepN6A3qpIr6w06fGqOuxtRdPxyVoM0bL
TDqAGb06csGsur4ZVtI1NsxMXQYHusl/1jD+4UXRcDc/rM/ozpSRGyRiLmFjZEPpkHB6Bfn5VofO
zD9+c+YFqF1js/IifXkfKK8MceaBAa+7B5oZYHvDbDowzp7Fyh5Aue4lei2EaDoMiaW/YThPNU53
7Nrean0uXyp4OH72cZNmHWsHRsC1thC7p16tV6WH/C2FXMa0fTMAcagle3Q7b5ahfnhKr1KMfHhC
0mfCHzqRoWvK6Ec9zjIMPXrhFuSwg2YGYuKYSB2LzjkH1fZoDGrnOPVrl1CtE7gOOxKsfAma7hoM
+E9sYG3S1pTz9bc2XINLiZjEBAClsb9JJdiuIS8MwJBoQKhcIfiKNAAz0bztB0AaZKuMlv4C/jOA
phtoeIKjeCii26dM4dUimNjbusfqIHCpN2JU4okt4FhOX64ML1P7wqI2l4Sx2ObaJfG3paFFeTxR
rW+oE4cgqmyVobsBkH4L8upaGakSpy6ILlktEqvejMJyVk2TTCpW4cLQJEKDQdTf/1YMq4p4MvQP
7UEr4l0UHf0Hxtsr4c0o/95O728VOPn3awzMlP4uEe9mjcd6deAHxlY0EZZGvgFdVIaQmn/Zfrgd
l3oMijsJue2HQFpSvGs27b4KmFpIyFR464W+Yw2BU5PcTGhSF2YoElyuV1PCiQbn/+HX32iFYFp4
VaikM3NkJf66Lw2edA12Xx0LUXRiL5NpwBU4nbBPLUbUMC2VBlXgW+rtkV8CR7bF5H7lmBTe/hfy
PaQiZhJs+g8H5sDGGYlCFV7zuwMo52PmrayVULIZEeaKNHyO+fvDSBgW0gysPyCQgUsTM8mKEy5Z
f6pSOLvdP3UEigUKxIrVTlv8iuptD6alaz4qHQC9b9V+Cgm/0lssZTYuWmilRy4j7uVeh8fuU2FK
Q/OzBe9ad7/yX2q5fWG8Z9wQ2fW+H21BBZYO+GRAWDAHo7crE8a7SUQ5//70DkZKPv7bLK2rrao9
eAlfz8kKDIlXN/4VUaMfK1oxUEwLKsRiBQ82yjXO0/NEwnOWoqQZ1MRIimlhHf+4y+V2PcGAyz+L
FBafmkIDV4PurSqn6azDcG4qca4P5dBVOsTXM9FSKLftUnWc1qlnaqsqv5PbHPNEOlrDu1m8br75
wotQkrCCdptbl9dnlUir79+mw3d+UrJ7CyWME7612v+6mClkhzZFr3H86zlVAwJQqVd3/9nvrY49
wzxtlXS+0nwlv4WBRQRzVXgPlQq9LAqCFN1NxrwUNfXTqwVvm7aOPeBCiAMSbvB+2uEvNwstkdL9
Mw9NONyz5xZHZJdyPO8a5i/kIyy8kjb0kRTZgU1ZgflaJOJlHLvbTOU4SdU+Kl+Fl7o4rZaAzrT7
elVgdShrxawbcJ5VHeZPNbmxYmKoEn8pdtbrCCZVPgxq2yIJzvWMQqQWqhEF4whaH1gyk1hTMoMa
sKhJRgzuk5i/96iX2Mgx48Gp7cJfPYLYgNlCBpnMzNI1DZ5e6LBW1b1OrdtAXxX5j8IH+H6JmnB5
hmKtwMaKfMW3jvGNE3w953uMOa3GyEkKnO7oRTdT13BEICbaWl5gXgnKJPobXJ0lc1meDCZhj94q
9/LupxQBtzOLpf1PhJMS8nOapnIVqjB1EE+RPGkWWuCQFFJmxyujrnpcZ4mYGqn0ARjmoEhNQkv5
4nn98g/lSTWQOkdQNjZ8GvFswFjms/hcQ0+g1QTU/LDEuSYGeHfBrcR3g4CVjErsCgUY03pKZ1dL
p/RODExJhnsa791vEwzMCKeaycLAbi301OQJXowwVEA1+RbSdToSiqLbMvltgV8VyfBxpOoR3YmC
1dm/8WMcd04lWd/glNkSbZ1DPWIdwacLChqkFm9s+F6FgN+nXvaGCjqJa1X0qLykfgC31OuMXtvl
vvRUfgp2ZPPFxetx4VplEbkQUtMlJs/npEFxN1QOZ3/Mw3Fqa85updaKTOEK4zODyHwWw2+qxmzB
OUXO46o26M8GWwVY+dPc3A7cKV8q4ZJB9k+ZN3c8dLLmBa2QxvBCGGUg/lK6MVLkcHN+O7SFyFca
Xo33MOc7Dz2S6ivD+xHMm9pfXzYNSHVpPcNC3x3SjgCOe7le+hX1zpEW43JMCENyRtGxCCRYjEA4
r+8mDEHkWdcyLes6ttyVSs8uZMG406CXBPHsYFUnmiSq0K/H4Wz31k6P/RJHExGaVMjA2kVH94kS
GFtQfcQJI+qpasJd8s6E7Akqt3Im6KD2fUaPsIF5q9zU9kRdCQHWDIc2MJX0BNjCUeoxU4znpoZr
RLBtfBuD6O2FgxaeQzoAZ+dYkqL5Y17MEaz1iqBlrD3+YsxaACWdkoBUnl2M06ARY6ECg97vYceO
2h7hs3hKs4+WNrWetSb/kiwpk2NNU8Q/4KaSR0p73bLZoEbzOp0e21HcUW4KalC/DvZiZw7eMViz
bl342ivDhKSfep+TChqfVYizaaSbgzpIpGImOOMUMEym1tntbRsc/91hhOPMscbQSRGKbSRnddyU
kVbMfSd7etIWNJtQAmWmnFMhY8ts4c7HZ3TFbO2Qlch09AL34Yd5o+U6RRQlU88mHVDF4nsTSubk
bJM3JHzViIfNiTZpBf34vrFYuuxgTsoOemGRaEvF9zOOp2fFTDo03ZB7w/rZ5fBoitoiIFzzyfvF
g/cimjz0jbpgtiR2w9MRAB6pFMzq+dmiA4GJfs+v++TnoiUsPw6Frxn3busX47KUf0DrYOb/kzVu
1gVPoxgbHx4+/XgljDLHnWJ++wqeX9+O8ielUa7set2g6FhAWyTb7LVWrBZ0eG7z/p8oc5GTNsTg
F+zeZqB65VlAZdozarImufyzFLLW/mofuekUoKixXLWOu6ozh+Vpv/sD6ZW8Ta5zaN8XxG2AG8dd
v01Fn/f/EILLmTtGPrUNeLOCY+52gE4278L5BUc3rqpKvG1ZvC0Y1iPbUmUqWYy1TLCS4xrA0iXy
6716PtnZ8U3CTSd8a2XT+mRj0JZL1MDQAL0xrWlLkJ12ifzy1C/Eal2UYM/bs6S1p1KsHbxP2gQB
ZdDflwJgIr5/280ozBTCGIswO5CB5nCxQLmUelgpApr3Gghqt7Azm6CKFAj0iq8eqXWeh8fA9WD8
DRKP3DcCto318dZnT+W6idBMVASvueSMHSEkEnt2CULfGy1Fl+B1sPzsUtAZWi00wtEJRxMc/VSl
2ZRUQJzoRmTA7bzxBXBLqIFD9Fx720ckrUX+n0xJQmh1bMSbEkxAqPU1VGVjXS8QfGQpY/xp7Aw7
SFmxvHQTmb/R1cqJw9pUqmGA/l+PUqxJajKCJ3ft898ZDnItM3VjLbAaQ+I24RHdX8oXL3VuhTcB
gpzhW4tBAeKeRwfkmnSESykHzvNGHx0v6bOb1BDM2gqXvSq0BNUiUJGwq6aWxX2mQmTEUDdUo6KF
rttP6jazrJx7SOOjydvozs1GvI1/vSuLoMofcF1B1EGs3N0u1aswL0rwHuX/FkMWzkUK1aqiSLrd
vLn/u88FWWa+1P+GLXNFfDDORCEuVvody9LMPQhm7YgWcnJaR/zZAjsyZxLBZhmtd7GNbJErnzWu
oxi3XMS0TCJprOH0dA8kyxA7/YuWAMybDj/9Jat7Zjk7gmBdMzmYykYNGkYrubMcpTpvqqgT3zUA
NEXvIPJPaQnVaSfYDsib38LtLxJ4SQAEp7kBPRFZO7ZHdypeO4Biy2RUKEQ890cUQThTfdL8SAa6
+mj09zjpJXsmZxmR13gjW/Qbk4P6Ney1mrRayhMYiH//fds/vycvsdmbxANnYm7g0U4C5abVfrrP
8/oEmEMnnt4qwrh0LElFBs2jyt9ggTHuIKZ2jdKPjLtrvHgad9qw4GCaw04jewPuOA9ETgTtmzCn
mefhummtJtg4mgEl0X3ZSRJIeen3x59YTf8qhidwiVq4TnpmzHtbvVp6n5CET3A1V8SUWQ9W7ZmQ
Lx64y1zlfmwPBoapS9Ke/GdFcnvwcJT9y219UAxqPK8kW+Mj5rtGJR1VTdKmlo0vTdOF03ntDwKQ
UNWESDGuq/Z/GNUE3ldizran6WUumq5AVovyMq3DeiZQbzDp1pt5+m+zjB0yPaqY9rof10IU8PQX
v6LrPA3wuvDlwzp3Hyg2MbAQ5lMxktxnmZZIVHncpT+EXWJURav5zr1jHpgHY+eX6Y+/LhgHRKlf
I9y3OoS4vIlf4LgPKTicMJ4h8LKQKusMVxOBxHfdxN8Z1og3vuvgsYo5Vt1HFOLqw0qfSgt+QcnH
PrJ9dyYuIyPFnDpGynHIJ7vQsZVRyDf1hdsbNdoyUnJI8NqxF0QHv/F+gbk2qnpPh/6Kq8AKAgQe
rwSJOVurJ8cfpnPTRBcjaDeMJsGdJT3XzWuBSbY/pXie7S14D1rPT43Jgy7PgecOUD1tjNDQR07s
Iii2DqZO6+hi0CsOBNQOJQ/vmvoOTOD6cYGQkcDlvaY7EPtQFr7FFeEqxw+PHEMKBEl2IBAy7fL9
rMYqSro3Rb1sp+hgPj/OBlhCX3tO0m8fWQN0w97up6Hhbb+x/VGhENaTvo3ezzZ5yY3/ZdVPo4p7
PABVChS6murfjMdjIoPIrsD8/Fopxi1Ix3zwU+xtovkeTH6TX4d0OvEKnCoQKDELiTFaZbsbgRJ5
cbsfb5i+CjP8Waza6nJ3AiieHCXxvFKPa1UarGn7PmuN75Sj6DE/tKC5OBcGSBFPUg0z3LQjneBl
kYh++ShjfwpYMMIiTP+NdPe82FEsVwPhjWCIhEMvNVpy3l7ivb0MBN+foidP+IXhHvpjS7bDMMdc
m4Jg8joVWcNVWy0vAC1oMVf3qEejNNzx7KOc1j3z4P49NF/cK7IquXIIAycmPqqBogP8AfVxNoHS
Rv1i/2styNdgY+hZf+SqOdMhocpmr+J6IJ95/d+yZXRCGZwvaKinUCZUIWsy/wMhlwzjgoU2qM+9
EvtN9Po/rLLyJ6m/DjT7NC0+Fw2sd3Foq3+uRrXYJ9myjMLLD3X6kq3TXh8avxxq1+Jnn3lYoZk2
oJU7fMSNBFNM53NOeeiEiDp1DsA7cvBih5DRCz+PRwlXYaEGDGg8BmMirsR88y7NoQxOr3zDn94O
JavxcoC6bD1D/Gxon4pdzpYAPYUIUyJzQi0qODoY/gYgFyF89Q1x6HotT4c3AAmlUVCmtoYKp9UW
FA9IaLcSfJ+aNXenAC4yrEow6zfna7rjPNaByzWNMxCW4pJx1qxfYvv5Uo2HlS+yKhjRO22cQlNy
Q17BhRY+l7zfCNp9TRdywDJSjIXaIyyaGlqPRl7FRUIBPvVXRllGF3sfWHS3pOMcAM09OzicgHCJ
8aP+3VaGcg7HgNVGqxE3wETQG0r4L8LHXpI8YS7Q1V9RY9mvqRq0Iw5Tr7ucYNBS4x32dlX0iYPH
m4YwmjbUzokaLdr/eB+A6q0GSfwzCfAm93MKoMdugnhFWm0VF6z8AhVcd8+LlaKca5I+ERaxHQNT
R5Tq9YfY3R3GN7hCTpl4uHBpKn8IJ0yfbQecbsBPoqY9JFBu9OZTRYzSmu7aSmIUYt8sEQyS9x0h
ybz3me2G51kXdsrcZoxVl/ltRb+bIBkSDDblXAzU/7MIGjzb0cYdPT2Z3XS4bLOgglkJUGBpsH5h
3YhMtFbLSzPUnvIgSxXGK0m/3iuTZ1A6BPo10t4T9ln5Rv/Mt0akiaoX8T2nPF2Q0xwmIxRCRvhW
vX3guu5WYf24pj5lEEmRvywKMQ8Qxa4aYb4AWTe5SyKioyFWZbZR4jbgoGAyHw1QtSfHw8c85FAU
vEEEVDKLHvYqY4OpZI1u8RRM2dn/D1RZMrYzZa8QvnXT0LVBtY0xmhYSI9Qcs0AxZeCOfgtZM69j
IX+Ah6cFMEBSAujRZZnRtyO1zEj9DxpzWzx8OyUydT5uK4JM5IXmJGy97Uqwa3mHO1Iv2BWOoka9
hQULQsVHejG1iRIJKUu1Cpr06fYLDBeE2YIq0uU00x6F8g81960htt0wxEIfSHFdkXb4bMN/sODA
iDctuU6/QwVA/12vRXxCRrQePMN3AdHkVwtqFlpI63cnqhwLmSjgOk6+oYrBu7waz+/W+Tn3paeK
Pg2wGSUYK+OjjKfSjEVTt5n21nONTpPaDcdaWwJHDOqPG/DjaCo+KRiH6ZqU+14K+f3tqb9dRdJl
FRTTNArjd0qYAUTNH5V15Auu4WvfPuVot8uqmvSW2X0ky5ClnHzPZGJAe9UGNbVcFvJXoS+LWAlb
RDzEO85XR8OH/HAh+QSQ6L1ZARnRE62qTwypNprg5MWbRmYgXDKoqrlxNAR3AMysFIEEKNuVu2aO
LAt/MZr6ZrtLLcT06dZqMVfCWUm74XsknXhdEvaUTipmpgD/k6IhNCnSffFgV6VCyAYhj/jWd1Zb
xim2Vl3MLI1jEy4xq0/GvakFdaw/UcIpuP5JBN+sHVcGBxOcQLzwG5cfclzmW/fAp72hRfEf3r17
6qnpNA0Ed/LxLsl2nWzIOkJQXC8AbWoFlgydx4CelWCqo75g5k/jeeB4e/8uYZbbIvHryEht1HA7
y40Mh66N0ErwBMkACsbuyqBjtLt8cmGj5kFry13BhXkrSD2S1cJFs/+f24LFlATLayYVBzmI5VWa
PkPTokOgzzFXV/B4it8KcITzgFhEA+Xy+XO1f9v3sOTBDKVE3XN4kv3o9FFG3EtVHdPk0kWd4qW9
WKjunkoi+1B7j0Ry87oeNJltgAOJ1bu7viV8mtZcDKxViubCXdqwJNgSvFANW7EJ1yJFUL47bEsq
iBfgSdxIni3ee9qphTPrzX/Myteg+0pKJ/9l8qzysRgKbJmJR2L7AoPcDsg0X7VtMVvFOUdv9HUO
8YAgCSEvizAsniAYxJP0OaNEvYP5VShI2lBX5hFThYxyxCYtQGyOKyhlrP8xA+u7w0WZYoIh0o9r
MN2VsF8X8kBpjFbmgwApPYsAYVQUbl88E8htFMKqOppx6sy027q7KFBdnuYEr8C0qhwqcmi7YrwB
o9zaoEFZx6AEeYfMI15079Cruy5IYOjwus8s1/fJb0u7mCkKWU3Bp3uM3Tl8bDHh2hlEyfk4hjfw
Jbn+6oCXYCQw9f64AVCChzI4jOYT3udxkershGe9uKSOiVQHUng5BeIsW1vE0yRuvhe7FSGTl+Dy
3dLLXpYiynyMipRiWrbA9PkynIikghDmi2+0lsaKW9xUxEtB8wIFNZVvhBndYrIQzW7y5/BPvRFM
RVDInmjt0JJr3nVDY86/UM7zy3nhLmx0rH1nmCL/n59LWSU6aRN/8eY5XJmA5+Xaoa1KBheRfNiU
GXaK1t8Hdu/jqCm4Jme1r2Q2JPc5Hh6Z3xB8WEenzgYh/T7wPTtiaJIvAtafwYipdP+YFpYdIotE
+gLkqG3ynqVgMUh2B/qQj5PzJLq/oif+9A3cNIjKLI8PUtr5XN3kxfnweTaoR7ZFiSjbFkrS0jha
sDGZaHHn7gHlB7i2XO3v6TdJAz6iFwaJh2o5zB4+uy/POFFwjvayKdx9FjPRHA75S622PkDl6874
Xzuqe9iAkQgua2wfceqLK09lgNGKD4jyNa/+0+xZJKsRSAruC3lAQf6KcL4daxK6+RS7juk1yoQb
OGk0ZjRlv3XV1+YYzBMCZcudzg+9NMxMTmrp/QiMZyymb/uIbmwEOBVq68vb/26/Cv813IWwRwUE
Zna7HZiedSzwnRNeq1uu+kuXftAa9WTxremoOzG0wFoN6VvrrCNI/ETSIlVu3DelYYk4L5XpYAaJ
RA+SDOt+Qx1bryqsk5PGIwuS51Kau3XLXF5P1EHuZaTvTffwyW/t6lgP1uQHa32C4eY4IlDcBqLv
xBYj9coiGOKx8YcjHFuEI2wJPs6m7iat0D7njeVnJxcgSAbpmrq7HiS7wE+UUG9tpm66juChrYxf
DuG/QtwJ6pA0M8Aonwi/rnZKsY0z7WejVFRsfPCzVUciBtXMEJHUOh1+KBkqmlfJCcjecLpoHJRY
J9ougKgG0dY9J+E8LkszrfUfd28jMvvcqWrMZ5i6NN/wvlZVkkrgHuAW7m4dUqE62FXCvq6rC/Rp
maIGg7Z1lev04sRAt088iIgGI38JNNy/Irh2qkFeFUJeGGkW3F98Q7+NYB7C4KQwguycNKUzW2Pg
pvdW6ciPU2J113cVjGd8O7Z5MryHcq5np+07yMNOpLpCYm7I4SsFfbmrHyV7s0HvHyL6xEh5o9iq
YeWF6S71M0ALSNVE6QqpihtilhrR4N1KsKVivnyHSOBgLLSIHi1SN7M5pAcGz2PHdDhYj3UyO9k1
/SldyJ7IuYiUpf47hEbQxeYQhlwIwyeMC4FNGj3cBl4fvWN4HS5QmiK3kBEJIAcBkeLPTI7FSX5D
T3xAcomAj5KthI+aBZCbSe5ePr6jbQdvui35AJcjqt+9S7RQG5rrVbzoJy9hSgdz773EsfoXnbww
/vjErGzPagygTExLCRFxVbMBNvAmBAv9/tBTmNlTGPaqMXnMD34lgxJZtms1egEsc/loHJcPSNOv
AWJniGFFuZxplDC43i3BlTl7gC4msiCHqpj7W9XbbZucmUc9hpmm7Rx68IkuUhZHQ+m/POxeFKF0
arBP5XVo7j3L/VIBB+IiMikjVnnNZHjXuxGWG6oyoyP4rB+VehJf+Sp3Vkt4jFzjhUvnX/lF4C4t
+/Vpzu5oY/zoLTk+tr22ZECel6EwlP9DTXlYqY7/vaEZou6rUvE3LlEBJXdz3WaGI5uED4bLzz6N
6/W3WuG+SJPs9qZxjeKUQ9AW1ljEwSzB2Ew8Yzd08kyJN8NNr4S6yVBUotxqpBBJcIk3Ev3yJhcM
Uh16IgHjv0GmoqQVQxaOQ2FpcUQdGoSTgD2AOTk1GJsQrSmLo58K+jIHR62EMbgbZXW88ixydV9y
Vr3c5aVgby0W+KgskmSHEFdL5q9/oJKcbPhnFNiu/IAJGb+EiuyJ1kBaxKS+lv6LDEnqRRxRpnDv
ZzVZxu09ry6goEhMcfmXasQdZ/pdZjJlJzbwPpIGAVZwsQW5AD2mZ1UFgmZ9Juqi9dm0CsrZ5z3+
QxUOUbMOkjC1VnC9mxfQKB0aYoQkrGIbnf4q2qZgLicHWMVHSWI50ckwcHcTPZF/9OYlCQM80v1n
VWWLa8uc9dk87Fb3HyqT0MYauxcY4XJ5raayh9b0mS2FX3Y+45E1Xa/0BiY4X9tehMhF9TMkP8ig
bTXRJR8bubYngSbG4t3XdYsV/AUyrVVmp+IxxGWo3BfOQlUcTeJfMOOff33I/M/uQdxav8QUuz5t
I9AXuhFmF+RUzxSCiU6RH6MfCcr1vWk1UzSka/dE4hNxO2RJ5iedGC5e9rk6iZLOI8G8WpiZkRgw
Wqc1dku4+LuzeP9tlvGIKOVh4o/80NTnK0TkAIs40RP6Y/VM/TcbPjSjSVG76XCtzbuIErvOsxJQ
cz4RvGurDI7o0Lz/TSVypN7gd8ZkIH4kPgcD09dJTJpt/fh5gbLmtNZ+Vq/UsENeIYgBNZeggsUP
bKO0fwKOzJtPsWUadEokK4abeR6vXFW19fTlIxjo3a0YJq9koLsO4X600uXlN0GWfD0aSBToqQaE
fkS4i335VbNdpimK6cb7jyYu+OujMXB7W9JwRzBua4M8Ze+FnXQyqdOt3jQGHvyY/Bv+Ccy6OuG7
pcZRoZyvEKws/DQb8ofzmp2O6qTIDfxnZMGUVwAR3czR8zhWJGuu0dRiTeMrHMKQZeUBWQeTEKuw
2Q2+HSDoZFWIgZDSNZmZaJ+QxtDkeTeBwL2yhzf4VIoAcpJZQhfVM2XjE9S7ApXon6GSAEFEfy6f
gy+n2t9IT7cXMBgXNuc74FecCS/W5jQxfXTk/tN9Zt6F1lpKW2lQnodn0alnuIOREPjuQ4xTPGrd
7GU/yVPlgTdSinT5LkLYLDzAGLRiHHvuZWR1iw1Ocg9GG+Qi30AV08RUauzUbPp39EFy0zXIE++g
Rtd3sGqzcQuYKdehX0K9frInDr5xDbaGEmHlwqY7X+boYKps9zpHmGSFKRt4GhHSAbWRvZd1MEw9
gV2vXIFa5fO2CKFztB4rkn5ztixyP2GXa5tc19ne1rh0y5Uu6AsHvxIw1Q/c4Z/PhDOIdmqLbN0q
7lCY4FFIEHUw2S3v6ZXmaO2qDxHhC4ohBaogirw5tlCkvXY5V/4+90XXA+U1SRPD/0Y7KjLhOfQI
IfB1y3WeUV5lmTPAmMFsjf8fhpQ6Ru7Qtb7hmJxiMhmpGTa3hSSqG6BQgP46GXbpM/A3pMGANbCl
zkZJX8LWnG/x4l0P0ZexFAIdCh08JG1Df6AF5ZZf4qgPQVQkhW0Zm35ubTLi7Xf6Oqaobdwk30dK
cF6eQpR6IXptBIyjdaM/x/SvCs9JOu9fgYFZILXipDs8fi+mOxG53tu/80x6dtDjuOWUoVdierpS
K61VwrqURL2MFU1UbGav8Pxod3vY1+ocyvJ0wvNwtQF9kSI59F+8nSf+2cyBCEsXEw4xRSpRMRMN
zm145lmuDSO6sGwyG49nqUFkXm3osS2TLVWNPoUzs4Tu631d1oxfP3gjQMBWPzKbB8dOPn1BQHWA
SRfm5SVd9XlPqb0jA4b792Gb/ENCra17t3AqdJ5hOsCZWbIbBABnBtU0DgUt4mEs5ix4JmDfRyxv
gGOWk9/AsQSYfmlct+mdvkzyT89+d8eG8co92zKmo3yBODD9EdeXKrDC+SGYAtUwFBdwpG7ObHFz
0DT/XlK1hebBC10BY3Eb5+YwK2/ZbmU/anq4vvObwq7lgc5IAN05QIX8B3nSdCUOaseTIe64JCes
0j5JFAbynzCyyYUYARClfiobuzEpX5oEwBxJDu4kSQ+zKQO6LB5JYPu4BR1XbkvcOAqXVDFZLyWW
7C2+Df5n3t4S6is6zfIGLGTmC81i7Ck4BS9peLjne6VJIsXhbkhvRAmi6pZW8+Le+OPN4xZJFNh7
1UKW1IvDHmn7Y3m0zfFE43EB+jY8qxl5Mljy4LqHexOr1YFnCsQ2DEucd0smTWnIexABNY/eJlLU
RZhNLFttgy9tnQoL60/QeyA65nYSJkQtlLZEzcuMNpGnLVjyMW4EgTSe2M+GiuuUWqySOXUaHKXX
QzR8YMGqUf5uEO8GMAMFnQUigT27odBSOhYWRYVRv+vwHQtbU1RBwyVNZMoby7Z9jus4a9fcYAxD
qlf5bTsW2F0+Zp4mhOHUg8fEMyVWaZ756tX6uR+mGCKpQ9Kk0CpSIkvuEwanHzZlurEKqTMpIw/h
4NGEitkGNbfpWfFxjvpbDA2ZfjbHlqgKKaeAlXyWhgodMWqE8xF9SAPmKmuEEXVTfanooOWnM1Em
dRauJ0mpudc+wITIkc14drFi6Dzx/n3q/2VmKTj/CBSKHAkQB4JaQTK5vk53/WJvL+TXH7mUSKD+
cuyItMNEShQHrXka/oTOvm4uPkL6dTfgN45WqqaCyebHfqfRLfkxm17MIj1xpmN7yAo4+AKG6BRr
MS9OIOmW36l/+zr7TcVW9dbVmPkan4+HcFx+6amugbH24JzFuFYRKTl1m/5XPxalD2tKT72dy1ay
vDP4T/e1XAQW4p5lOHMSr63TdMmYFxrAN9mL5LqJjH2qIJbG+6I+EDqQvFXe3GfaepeO+zwGWRDs
xM73Y41oTvU/28mshhNnlNK4DWnvdjoTOTK7KKyurXwl9dy7NwxB+9uBeBKHSYNbKeVUhVeUPdRX
lKXLJGnGTSq+6+EShoQYRkcXIaHOzheP77t/3fs+FI1Zv5HjydXTBNwLK+5PaxHyg7627OwiUNvD
j6DFEYO4anCGcWWCiu5RAzlvT6wKyWqiaAquxRCAUI9LrKRa6521T4UEVk9muXmZ28xcsIw9SQ0M
kFHuD+yvOS3UyRoSmR/NG9XTrrGrZbfGaGzO1Aj+sUQIL8VnEjlLa85oZTob7lkUlI59t7bhDPOV
27hgh2Y3XJzUnliRFa6NFaN6gGMPYfz1GZq6dUfesOjF9EEB0jF688B5YL46KP4rpWBWIKRclmc+
zwObdWRjrC27HFN0besHPWaH/v7MxNtwACGrr2V03t+94ERz9rABv3aBuyeNOUcSois38H7WlYgX
yfCsMk/mcn7Ff6mNdnEkXc4984Y1POkYR86CqSkISctpB6llmpCTi1c04e/qTa0qKpjXjuMmnU2J
iXwTjmT7N2Xn5yjO6fMiZuMP8k3gdr3uEkg3ZNjPUsrLMRTvoI0p2bSXfML8UtUzdeuhsAxsn7VT
LKOMe2yaimfuFX9cc93Bry4rS20QwUdX3fnbLSuNcbgp7ujTeILoEiHzWkuqSA/xEmiH97P1IKgi
3tTKLtS+LeUn3h5caB2hFPUIlVMM12SaRnM+TIe2h5+QtQeFG36iEljz9WbfzLXMV8YT7ZAVgNp6
LxrGiel6vq5F0NdKuhIHCyDVa4ngL4v68hAU8pGUkTvkQdxD7wm8UGnDZ2cl1aeAe9hjcxtD8gmT
03QtnmhasjArP06Yw4D8DtnNxw8e2gnx5Ve0a8B49ZNPPiprI+haY4GW+XLfCKnIOkdQZI5Dr/IX
C0XhnAndnhEtiR/FMQyutm3AJdU3WzSnpdMJOZWoD+Qn0KM8rpFQH3OTlypeb+iOEopcCF241YyF
c//FFti/pv+2Zn2aFHityHYN+EEhSHljFbbFIlEDKfR//Rx95qNJXiSHc5ZZc707sBi0Ln8ZhD6e
p784/nNjhbGHyFHc7BajNqyTX7YkbQ/CWEpsiuQ0Mh4O24ZXVLBMitENhKW7olnGKT1SetnWtRqC
B2ptfwxB1BnTjNCTYS8Q/y1aXCWHwbIL3xl8T1kQqq1JYvluXY/KskCXK9h1idatTEwNTaiSaC94
K1qgYw74kXfyUaKpjrqdVI/vPWrX+jv1Q3jUGSUSKbodgCa9SZs6t9+vQbS3TvYL0Uy/GgjOcqCK
alC575N7i+XGIpEwFM4i8or/GYiX26O3nQShyNKZ3+n/uutLiKURP+vEJWJ4Hf5+2LHPUHHG2jBm
2xmfE5M2m/sG7JpLJTDulEC/i9zeFMnsrFvqu4uArJ9IXY4UQRf7TwIeO+EjgRCOgEmUVzzbLJbV
JVH4TdWQDIKd3I+IPgbB5tSWbAwgTEAp0K89nVgtfUSNnUQ99uh2U5ZlId8mkGoETte7nzI4SeB6
uzuDMINEMCbZnMX2rvIo4zod53BQmx5J3YhNdDj1pQrgLEmKvZvpUe9MG52mifzu3J2WdsbYqzgP
iFHgq6y3Gv8xfAY/UZDzT4YqVjDCzAWyw++DBCt9NLKaqv3/baH3UKzOSQkEWUOKfpJ77cmukLMH
f72jNHl73LxWS67AhzwXYXJRh0V9VRbZgEvVbU0vnaxb6lGqlC2wlrRzwFFl+6DQ+Urzz+QWupwy
5i85/1ZDnI5ITcG5+BTVoGXTtG3XTJBN9UZqss1gJcQaOfGZmWAeTLDqcp/Zav0KOoeH/HQk2x5j
5OgY7+0yIzYqt3oAOZ5nl0pwpLOAuQGbgeaPwnshgLC+XNf7R7eyjyQptFoJsxkfGfVKgfqDgf7X
Shb56RLZik7pxxFcErsfsZoN7oV1qKxRp2NJYdntCbq5sIWRfOHlg16LtKcgi1JcB2+xWArnYgbk
HZqRMJViQa8C5G6P3Oleg4SAMWVpZQ0tNRY763QV1Ngj1nWpZvWsp2y2rj8xqFeQHkg26xHt8jAg
e2P9cJHRRb7K+AyhVJYYfuwVA2J8egWR654byvObibdpt2zFRpaFWE7zs+NID/3jagJ/iSmgugVC
wJDOrdFmqHd1MjXKP67g6MXQbSY7NAxO3dSmDKbcdRjNSe1z0lY2HnuGGFjst9RxoMk9DoJdAHfh
GaQxPvJbix3AXfdro0jsbd/sLuXoB5SPo/gVTvuTnpWJL5i1LHz+kWk8Gy4MMejkYukO4pi3Kjxm
H4MndgKpCScEChg+OEH2fYDQVXqhnRhm+KyJWq+iRVhxsAaqLWpjXi1DklEYI84ZL23EdiL9n4qY
wjQor5hbhKMxw1pXA9DvN6EdnkUvU923Rh/nAb2iqhyduoFFm7BNlUtNwi7GTkTGIWPUGI4PBrvP
jB2SCICtB6FeYpPicB1wMbHdhal6HAdAwICyhcP2U/k7FTopo52jp393VuY+VmNvPS6cSJEdurbU
fwypAVbSt+fl1QWocpZYuyTefcbz4OzTz2/axphVaauIX99sjUH4GPSoYt2lEu53d6kurGSrTyEk
Y+YWUP13+pobyaa9+iLj+H1M7NXsSLByA46nXyc4o001UwG8qpMTjz9QWaPAw9qfQVa5tGT9279+
AbWG6ARUUXQY3kg+CTuNJF/Rm1gCJ3ffwGO5FmPqnQ5aTzDn5X7SWe+Jf4A7NUtx3oS+gwoWKJs9
zVrx/qBJqm/0NpmE89VQVYw0cg/rWXdfmKzzYZutS/um9V1rz5wLuGPAIv3MNWn4o16MBnsQUX/q
iPFd4CKYz/yk8eK0TJWAJU1KhlhJ/JdVi2Aw+BtftFuhYq+Y+PKUXOTMam4O6Yg6Pvb1ISqcxhU5
SfVkxYd4m7xDwx7BrEraInZUVlCYWSzkMEBVuJyWikFUdtk4rTNZBklVrPln1dHmrWEN2IXmJWas
57PzWxDG9o45OrqOqE3HBmwNWMh0UzdRdMVX1ZR10qR6O9PkXgrV2BphRdpThzkgIGHBctt/r+YW
faxH+dAv1wdX6xzZVgFlgcDQZd4fmB3F3VFT8/v1aK2bsV/+nnPG34OfANt7446cfyfb5A8o7Hbl
aueuo8GdL036Y1wYgQzF+/uFHVckklB8GNCXg90bU1vL2EMQ22E08MZPhk/55RmWssiTWQtvqPqT
QA6K0MO9M/lwYYq3GXOkLyBincYJj6fd+QFWQ82bZBnU9Z5p2VbETjcgBRqglg+EeoHPQmB0GjGy
/9vNKehk5aJgG/HeKne9f6jzJ+GgC7GT8yx8x5vMi3R40cXXHp6HN02l8/WB6KRI/9Bwt0W2Iph1
u250UvaTvRcQVa0ylKET8SmBx/DDUy58MRDBMkIGyYSej65mdjq9douFqLNZilekeUplbWzINIpx
K1zHkZwWETM+9sx77zEiOdkNQtzjBCN56De0ertB+ysz4IiXdjx6tMKNI7RqXiuRCl/cSxMSAasg
KhvPpACJRsIqhvK4DyQnC4hpCqscdvFHptA3o9aC5iJNOAKiZP9XOgBxFtL6VIqAQjSUKkf3cdes
fHcVoDatq/LrECYhQPbqWxVcF/szhB9EQ0dSMa4VPDwIepH6IptY6lzinK17lysLPD8ZPOJNNmAt
sFff8BF+xh/dkH87cey0mcbYdXtOdidZhDqMfGvVdLl/I8eMG4Mxo3sI4GDHwd6CtTraabYyq+qb
c6euzLT+AlSZBX7cv1rS6q261CaOjy2nfW+tO2EVxX6cMUZH8tJhR1wv58UEFgw8kE4dR8dwcLnZ
ujOLbwHh6SrtChos/1kd0vcHDRC7K2WpsE9AO8gMEZOKQsDSwuIrcOJjG2HrzDajw9xxCJUUntJ6
7bQpTzv0NbV07hyk2Zcw2ovOKij2LIy9y1EjRIYCg7N8jp481P+P9HjNaI4IBHNGZoAegoGutbBx
m5xOFy86dy1gRz+okRYAbCc81qpLWuVsIhF2u9uDJictYO/07jMXUI1WZVBBHjDISia10Qe1D98y
nEqt1KVIgpX7oEzEA0b7LAzxwrrCX4GuWv0zVqXMHffeGJNweORCgmEqcmf21C7Xozwf9LAdkGh1
YdLIhgljv4KbSk3IJoz41rY18FQ0tjXjouyYGz6DCyXc3PkFYZEWLaS0AY9EOM4r4exybZJVZHkN
6wYiuDUfvBAFD2sIQi6RPnIt1PX4dv0ZrHdEXL3CjY2Cv2wpMDpmE2Hk/M1khR0wOS+9EpyE+6+s
Ij22B5q6B+jgcgC6SwlS4nsTI1w4lrrmbtYdzM86sacchHvkN7YCxfwoYx5Bb6daVqBtOkn40cgs
Jv+IweVzJyjm6pRtxOO+eKhxa43y2eq+O2Gq9eaHpp+5OCN5rbXF6EVX1y6ycC04vkoExN7nD0J0
5IurcvzyOIMR8LNZcFuaV8gKCB+Bf9ElaBQDqHConWUFf9u9bMaHZryIxCfYaqJ1jUWd3LIs1lZC
jb4BgkVJoug7d7OglM2M3DdR/2k874xEfENQbC1o7IgBP3zNSATIXoIXXuTrvArbb0K3099GFx+6
+gZRiv/0djhRtTyvGOc4qS6dX26A+0gw/gra0T9G7nFcJ9cXTPEeauiL3DpQogZH/FC1Sz6wlD3T
0ESyy1uvZjzVSaI4O9ZxVt2sFHslKmC5T4ezutM/VrrDIe4XFSpSUWc7tUdna8ytB/2PSJ5PFGd7
xTp4ULsVsyLFWEjXn26UjdpNI4lzcFivciiqbowtGro9rYfd9C9KUxJdFn0d/zpZpy+CdSE2UY/u
TDtYd8eC0s2i4l6cVQW99+8c/jkxCvT5NYXyJSQC58c7Xcd6UHasrvcAGujdIla5tnu5Io3Uinbi
xyLEAkmCPYYLwjGaFjCW+QobxjNvwd6vBMRYKIQKr5xu2DiXTIhzwIgXWJ/kT0RyEUikEU65Wl0e
7yau/J8p2gPvTRsBeEe3zWDJSBNJ21Vp7NYGcMnsQ0MpvjshSxJ4/M9Jo0Y/1lN92UfcpB5ao3Y6
lZ9l8qJAGkjKt+h2TDWjHbmajYpNH0ZYKmRcUqEC0jYmVSZNAzS/cQ/yeydYA4g/NX708+YKpYCG
q9OfhDmjIdgEe+sg4b0vJG9HG4b7fU1A+qoF+ue+H3D5TCyzx9loFyFuFZ7iUyiAcPI8oZf4rd1/
NJ282eb1zMcGEa4sUWFh7m6hqwYcq2mZxihb71XzgwPvtJfmv0g05GYX2JwRJtSOsofhQEfyaejk
ZbZni7yIGu6cwgt9cK31ldgg9O8floQt0WGo/67BVLrmb9wdw10PVgPEQ5ux5rpIsXDhbff8jzWl
R9lIfb3aOFs1MSeJhzzRaS7GRL25SnkON7/uNmu6kO8xQfSCM4ilENpuMaL34FuOIDQU/i1LHsrc
4Kk0hO+AZWmyT1wEdb+mLHpKVOPEYOoDvFlPEz5ASiFT4qyrf7p4ezvX6lxSJ/LHozHCWj+6nxHN
YVvbg3pOpAok7JrUDQ9bLyAjEIKaFnLoUPhEOavzmZmN2niSVc7K2Pb80+OQNTLBLpsWDtsd117e
Efzqm9XtYuChkdMe6mcDPEnMG1J0qO5ZZyBqU0+7Fr6Ddnk6rdGpXbps8eWSU1eEEWq9cdevdxEz
ZNoGkSP1xx5FD1dss+5PAcwGjK8oKa3rD7wQh5PQG+gs82uIJYex8cNIfyo9kz9XDCAH+LUKdUm+
J81mqq0RZK22uC+Fnq1zEROKHa1untOIqecnuxjdI5GSQAh98uEN1KqtANOYXLEvw+JYJ3/wWEkt
8ZPLq0AxMirbcnjzaklqQQPA752TM6fSboqlk/7Gp8x0Kg7pPokkB9p0bh6BwH0LPNLKdTuAUaR7
t3LDNtGgARZ4QAyIBy8JanOvxFrT/RbY237MHbJt7wCGhvvKWwypR9m96o3Xru+zhn1mFjD9ElTr
PPyJ4wTC7gJO0h8Evnz7isqatXC26Cx6e3zRRl/G7aaU9XKZpe/gjqiESegB9NNxN9GrOvPc4KgR
M1N0lrL1h6OsIupaXZQuIDq4sn62e4otIFj3qynBPHLI20lWB+QsIEl54Nepxyqi5h7XD0pi82NT
HtFdMFhqHpsz9elJhBDnX4b5163bRJk35LP6ZaVhTghU+Hq7EMaobJxV16LneDAkQ8iDbee5Ix3+
mTBBXwRt3EGe/OhVsVH45cfetT+eUaeFlhvUjfwyqPRtdOJODvZQ6WJQX9e7IIGN6kRFVngfw+XI
gRxjSvd3Va+AvVt3qbgUofmJl2dXKnjbwpp63/kycX41riLWLeihXR4btXHrw0tFnKCFeMPBS7kP
lv87ezgqeIn+zuN+mG4jCEryhUZb9u1RVmSAreY2Ww5AqpsGS9YvF+EYNKr+zqSYFC+eHSdyHYZ+
IJ/JAxTk9GgEMNfze4u/Ut6uD5Dzr72OkBxGP0GpPQnTFpRbLsO3JJQTZq7k8duLh/0Oe1RpoGdG
hS9jwmpmo5Uv6DLafdVx9Yne2AaLI2nUb25jOyzld9roj5TieOxbVHlC6lucH0lcP5wcyC/kClel
RQJlrjgvO1gwSnRnEw0KIm3sdzOlRAmDQilT4rLL5nbMGA6Mvy1SDZAitfMHRWuiPbVnWA56fXS1
eJOkml0IKRhdhHkQQWMCQd+rGXEPHnVSTH9IiK/x7aRb7tf/r1i15ajlKqVMUTfMvIpSLJsmJAV6
wt61esPpVPVeurxtMO8IDzswKd4OUbk7CxHJwoSw68+8q2ouAhQEeEtjk0rcckW+5ahEylwLo7uo
gm5frU5dJ/bRVjiSWpMsAIr63diJ58Wa46EfS2A/iiDrSxwxtn/Te3sSnecdlwZGMgsZ3p3JJ1KL
6Tu+NRsIdyLTd9F0SMMq0RLNgHV1EoTc9w0Pv+DfIhqyrPH0dJlpD5OOkXYDhCveizYLLLRH+N0E
9DXuouRc70cTrnMTCtojelynl2pybs6TWd0XHt9uZKxmogt3emt3euiDZ4fQ03Y4oWEqxUj1ZuwN
PKipbcD925V6hZNB1BBvmb5eSWCb762+qo6dve11NH/UIAVz6YmCVfpHRqS+3u8M4NL0yKTmjf3+
b7TSG3QEno+t+lc7Y13edX9hjzViYTzkEX5lpVKzA4ExpZOBlfuClOPyOBOcZ2HmiS5nhAY3fYwa
KjmwNpJM1tPRmXcXeUDWSOihwF/LZBkpT4d/vJz1fb/lA6Cy4AQ0SP7vy4idhYzCHMqDiNRJpE8Q
LeYbif1vSdlwY6BdBB7MjfSCRagy1K2pwuMGQ9Dw+2sFydRDfTcpUyzK9GmH8cdFWyQJNJ7hra5g
f8trJ+wxjFzSsbt/TGFcUz44ecCJQZibneT2IZm8zIqCn7wSDV2Yw1zUPPq6Z226SRyfEETHEuFl
bOvsWZU0mIbLoCL+Rf4u1UdA8iVQC1rz4QC7i3Koajw2dn6FuxLasPu6c/aufQsLrKvHq4xGwSFt
HrIKPDYkk3LGb4LQbN1cHf9fImfFTKL5Cu0moL+aN8R5fBK35vstVJqza7nxXlLNmx6PuQUJYdvW
l/wrAkqNJXffxr6x4CRdmpGoBQLk45jGbpDYxeTjtea6mfEf3Z4+ChCXRh46Cc4UTp/k4Uo5UBoO
YtjLm1kURMA1TxpFfHYUuKxuqmqxlHj8UERtq2gyEbeIhhqL+qpR1gGxD57ctRimUcuqa0V11f0/
Bw6uS4jdIc7TIrca6Vmz/U3BOYrXP8OcfR07pySfo4JatBZlzgo3JZigGSTg1Tno6gmBZYwhVFTP
ZUWXvVunzh3rrDIrFhB0AMKogeP/1UDjVaMifd5D/aOmFxPzYFNUFyskX+A8HdJQ4tSjDBk5gTlV
YPshp5raKbn4JnTKzPzCjVjlkk1c/cDhW77rzcSybvP5c9h84nOj68V6d+NuZ3lYyCQDylrTWyIB
qp2Jt5FCQ/cSwxNtrzq2FirGFyLdHxQRmDWYRTrmEQ0GK4U1UcATjmIJFwrSlA1uskMNxiXU44H6
T6a5HGCl+3ASNByZhejXg/Ug4HDLk9QAZ68ghTt8ndOZQZwMKLDQoi9yfItp/YIICY9jGifyIcZu
xLNXJtiLc1pGrexNHuj27dfzg7qUKOkkRcqvlmKOAAGmEFZQkJGQcMx//eC5b9xDbk6D/ziaSIjY
o0ZUSaRVOno8kVdA5AEfP/Wt521GyC4Bw9F72bwHf7nyhEulIID7IoIj+aQU4c/wY24/3tDRLyDJ
lcOn4agmrUYG7h20puvOzsg1onhxcdRx2sZgQk2ZqJs4mNyZwo1MZ/v/CctW41nkNsq8zWguuPDs
9l3eNw0BVLdI+YJUhrFr+Xd0QSMNIBSKgWOZN7wIi7ID6xcPaRNxje7fSwjhiJQfTCP+nD90JOYZ
IZX4Gb7mvy3RKm5kUsh5W6JATxtEbnM9TPsKTwghkJbPQS9Z8BCJZsuiCVHO+H9RoLXZF9R8Ju0/
rR6X6l/xf0zvlSM6itCxTAzyQhx8VeK4B26lmsS1L6kwuVq2HcyHpnm+BKohSOlGcvs6FI1XSfn/
kWxUDNhMC0MDZ43wyjI7T9ax/a26wiHQbkYIKFfOsP+IG4CZyNTeuX3dylUFN66totYDaxwlhtiv
VUnYSV9Q/UbdIXMVqTKKJza0LdJP31DWAoAgwR6P75oqOknDg3xGP+8PN/Hqvk/XtG1YtewkJBWt
EpkpfTIMU11w9RZRCbvknJPL4YR3jTMHVFbXQ+XvLHhWXf5c03lr8Jl1iVQ5vDjY20G4UijaOUXk
3yDti0BIRx9lb3pJWb4ua/J+f2yXReO2nygLBg7XbAfDS5JiNKY/nJNMr+ADGUMC/HfICpshTcML
ERPsnHGxlLxka45JUZO0zLLL9ERs2QWhQJyad1DbI1/hEPvRRfgCvxDuCyAfpvPP98dtTjF88CPD
hsH7qwiL9kmw8OBa2R/2/OWFpZL+fk3YontHoT3K6pi+mmS3LJYyQPnAW6BnY2jKsngEWDMM+FZQ
S71gIi9/PCrMRqGgr2JrrhxzJIGS0+cj2HTMPRu4q+QA0a6FF8tvHLpxpGoF9WXYW98MtiR+69BN
2ojLab3hhVEEgXNKs+VgjbI5552MpNsrcVDpbFsKM9zcVuL0RBH3Xa6fIcTBER7uuvT9GNFI0gW/
VoXUxGtl9EZmxnaXNIRC9nrj8Rl7F4B2zkWQlKgOJcQJhFm7/3fucKVcWRKCau8bmFDcbJRJSg3y
laFysptkt9MTGJOP9JEw4jpZVegReG5edZe1RybvFhCjlVXaSpuIK8b0BxlLHrnueS6zUO7RlPy3
cabVCmd2Ds5ZWFwBP/qJDf5F3EdvOMuMgHG5cH3BezI2FPtBJuDXm0O1BWOND1lSUmS49rVIUony
3JeL128AAPInM+0K+4/krM16ma0KU+ElLu3LGq62NzKhskVA22tgr2ZCvp5sYqzhe0kn2EAwOfGS
Z4jbImicj1KDxvMluZZCfLwj5+Nwvg50+fEjEReeuVz2pArtDBZvOvmGFdmfRKjKuMre9eBasEvR
h5+S6TKSoJbSvLgcO+Zlrb/f+t2tyi4H8AgcIyu39gwrx086TtQeZZ9Pnc/3JRtT+9fFuwlvDpZZ
R654Z5YG0HfcbGTA24qMFQQYhhynhdOiseGSfKBVco/KXRJ1TdVr+J1urDxqYOpOmnzUC0pXcWM7
PMjcnoGgtRojD0Ni7hU+rPdBq7+O2uOnhpQT5W2MWON7dow8xfzGUzmEwniZ96BeEHTbPZxSNDSS
WWoLJiY2PUAlL/t+ax2RURmDE+2u7/ZbxPT1NTdDB85NUGO7KRi3Ee6WI+uo8+HxeTLr3SEsLqNK
Z6coyeJOkR7MmGW0OT0a3iaoQwI/eixs9Nrq9wMAISXPzukp47MksP6gdaKlcXLgCxDiCOPGDIaJ
TC0YtyfpjR/yWbMtDqnKblahikEz64Sf3Ha2XpGUMH/8AM1VUgEAVFk0ENuSfEpMzG0oe9t+/w3L
yhKV4gHrfNyU//szDYeVp7U2WpBXpp2WgXfr66DCN1lpE2aVv8W4emIF08sWfwbW3ioPq0mSWjo6
4v9DenHiL6Mn31MT2uwlHh0JBDU1+eZYcI8+ieZ6gKoCwwJwx10PINaZXvV8nVwAuvVTMrRAmJ7x
VQzjTsNzQClGAcKobbJGha/GuJ5dZhn5+z65KhnEFJ2WLwa0nDO/Cdck5/gWdFugSMkemHsdG8Ex
M/1jFDHciZLP6WjHlZaEnjJx5nN3DMRRTsh+UcMG9Svch3v3Z5gfHunf56IYpyOGiu39vaEPAhuC
8kztjY3DP3+rOfE98zgijLvnek7Z6G7w71H+GiTMcT3DaqxQb64TU2h5U3/R5DA9IBrR50bGWZGR
v+AEufY1rORTF4tktEc1coYYvNTtgPbWMXQWhScWqovG42e0HulWFQUtDxd4pIcowBFtG2F81p+r
Cq5jSeMWP7Y0lI4qNJ4dkh7ziJp8vf8h8T6bR2IHVVt1J+y3CK4L1LisQkJuiC8wViBGseLSGQEm
JD8Bltw/q9VnA3cQXyg+61709iLCRCZ2fHhYUfYM1B3Bh3TCO4aw/0VRk3KUwVGH88jWhyzyP2mp
EpG0moA6H+SNkbwcwWmbxZaFlbeTWvy9owowObHBdeDvG3GRn0g1mAXprxhbbgczIJi6biFyp6VT
uhckB2YWmdYUObpAwx88H2qpZyynke3OL5cIB0423iycFSub7HoXCzuDR/3PoAAn954JLeoEc+4C
+Cymq/dnyT6dqkHvgA9+d39leDIMLckR2buHbu2/bhP123wJ7uBxZiPmLgcuRSZKLL+4/29LC/Wf
yoLHUpU4QuK8vZu7kCZED9/++hLs6XVz5t9jF+7DCZ3B1kFQSG3iLctcfJOHK+1AdUAP1467MMvH
yV5ooxZJguH2UZBJz/LId8ofmLr3uVLYh83I+hPWnkVOQR4KP94VbZwt3I46/1k6NrrA1zIiCPZs
7K/M1DkiTtZqPGYPwpC/qVRjj7hSaowxJbr4ykeff25RycRAkuv7K05VgwbcDcQOAY/OEhpGq3RM
rMZopBoq/s2T+uiRsNSfsN0SXG3NdcbfOgL/xo0XFJSkTInwIi9fJusL+L2N4hRkS2IELWY20S59
1KvHjFseyaO3p8RO2De5n5Tg0w/u+RGkiMzwHjmz3OP7zJfcDU4QY/XRDFdRUvVWqN3kyw3QvNvC
0k8k51jyTdqS62Oh6i2OC6qpNMLEqo4TzjAqH7JLRjCTsQ1hzEqUEzxMBWDyXUmQawoql79D2//b
pLPfmQDwll5uLmiv19obyhuEPQYU/aGZsD3qGFKNr8JE8DbmijjI8SqZcBsODqe+2tvw6Kij+bci
oxW/KJ+u4SXRi4bxFKLw9r1MUfu43Urqv5naSBS2amAjJHGYpouo4ozyKlSnt3+Vlf7cOvYWWPUj
apxeb9+5QEPgEQTA82XCXeFt059yKlalcz/PlFRERR3Tcv2kDHZHGBfsFdbJsAxA0xU5nmSGtHL3
QXJ/yq6H8cRqb0/ere0OttEvpO9uUZMJLu76K0UPss1KbYfOjtFq8e73vuIwOl0b3yqu4obb2IF1
PJsE617VycWxe+Xc0svdsjbtXn+wsFRx8TNl1xy9B9empZDy5xJwvdmUBNlEd/W0Scx8aEwmOBt6
Ya/8PW3iaflz7HUdnyQ+u1DDJ8Yy80caJ0XiabP9QTblcTRqiETdZ6YEkd5JXDy9YpcTqqkr4u2y
WG9ZKdMTEyEbYzPkibMqCnfqDOt991WZsFlslDDY/b25PTpOClOZlRE265lTEVCopUu0ISuCyYKZ
hR1cC3cXbVJYUSAsv8h/Clq01tElg8zw74xc6xHJg5LDXrmhbLQAbtXK/rJl9P0n7zRrH0bKkzmK
CR3rOTp37q0fw2eBNmY3wTH5HNnTIbAt1lgxyDTIJXtWSbKNA21Bsh1moubJ0IdFF0O8VpJqaJh0
D8xfnxaqJ21sMxK+tZUJgOdKZhK7Ot2vqCyBxV7Kuvm1H0FtljTD4uANtqaLpW2beJvzG3FAa4F1
8JBcw4z9uEEKiDHtxMZXVZ5XYHs7iuWY3Va3oVMEtES/acwnVyHpi7hMo5QOxfcRQL6oklQGkQJl
McNmNRdbEYvqhsTDdLJZ8L1T9ocn3ErxauUkDZLMBqRD+02ZCsCYryqgBQSICpSBHI5rsasL9WFx
eGRiGge2zn82MEs0OpSF/PI3IEBMVqFXXrJ3e/L0y0Oev0afYHJcab5rFV/pxmATJNPHXZB+VTft
NUzXaLfKY9SBxl76xve4f+p5SjBtC4gQgLX+XPW9UMOCoUR2ucYNEcR13CiAKECQIEU2zb32qXLP
VisRARVlAF8MUJTuNsEQbCRZ/z6j+Xog6zBtOeYKVRKljhYUsE0VCOM4RKlseF13h04asPi7DmTO
VnfmrENiWO0Gqivz4v4WhKL8i5MmkHTdbd986ugd1xKKnhf16gSAutXLgf4RcVOuBkmE9euwrl0u
c2XIwOX+DS4PQPCvshJJL8BlV5Kyr2akInk0GXTRPfzF2I8jjJqqbmVJl7Fz5560HmcLru3VAM6O
x6/qaR4dZ3GldWcUvMy0RRJtYdNuvyRKoVbHIY/2+6Flrd7Cx2QMRngQkXtrLRK0AnF1YPXbazIq
NtZJS3SD6NqHTSmB/Swnab5h1dZffDOTfJnvQTEk3R8bHWSy93rYUmpKmZ6kgrnf0Hx8zWGhS0rq
vjkdJ8VEOrqdxsCYsrOPAfmr6uGf8joQQYUpogMUF5k1/Zl8u1XcPbHto0rjSd2fusa7ImWwl9GP
psKIJh69YKuPEw4cxQfOdC5XemYl4igq8S7s0HuKxdGWhups2E8WjzeoDCeFZPLnOuS+dzZiTkN2
tJIpEEWcWSOLrAQ0EXqnhSMupKjVgI6xEOEvlhx/pPC4sJfAitxZxHw6fQRwaU1Fy0JS4B/siZEx
6GSQIalOZ6/1uAGJOmuwC3hGXGzB05xwU9sUZOf6uh9ntOvTeJscmm6RHI0vimu1w/3iWFhrNMap
nN9uISQP/QzZThkC/02MqcNNJquNxUvynh9QWSSY6Py5yDymkF72M4itbyFzsgEH+/wmRC+vqoYX
X1mfbs+UKO/zTUoXklBVx3WTseJ0yKBpl9fiSyI2A7xlKszFBZO8Ka83NCN6CnFfbCE8z+Zcxynh
5YYhM08c4LNSOlyc0XZLrVKGy9xJmZoF+EmrwIs8V4a1B0T+X3vD1gmmGJZ3KSEs2uFonvCy7oJR
FcJkwouoIx/7/kB/kFlmb5S1vcknnslWH8vHVRk+8+43xdt6b5lYR04+1pfU6nUGNxs2wT0ww4dz
CWmyNJbcO/hpyhlVlfjNh5IW7BlP1E5FXbqu7zep1Q5suSsQPqxR73cUF0KqFkjtC4XeGAVTWyqy
fmW4Tvusxd17IPL42W/ZadMh1XcKwlF4V0mYV9te3VFsbczkyh5En1XqXpyXIPe4a45sBaAeM1bf
rgdOVqpbRI26nOsd2l0x1//v92/JbL0WqF3p6ujNIMBZitnXGV3bj+dbVGKSV6KHa/IvjPS8gx7+
udSpAjkVRQnOaVAe998ZlkJyl2nfEDItyAgtB8u12r8VjhGQf2zozw59C2KtxMP+VXlVELMy/q+p
5CYUEk+kZPTAXmZHtqRNd2lKnCjIf2YC8VL/2ZYd0n4HFR0uFBL97d5SBeaGvLD2gZDD8F2WZtBP
AHv88T20pjSfDSB53tR47EMOHhYUCFRQqDuBwOodgJQHl9lx9Esjyxb096Z6mwNaCf5+px8CLJvJ
gDIQRFQBYLtc0eXCaWvca/11i85hn8DikX9HHI/lXQlN4zc4CuP/yYfsSUfDuYNzJiIxuHdPVUn0
sjxP6+WWHH6szexyVPve4DxUzjJtHe/D7lWy7nfBaVpK1D1ioFs6hUQ/hB/Wo9fkNv/diwSbIw21
edKeVOW/oVNT6u8LTQLDdha9q52crzKcnTuZU8XJxa/XHqexU+iENnkFul4eYbRU7quSnYLyu2/q
QqwhYekX1KJwsCMf4nAvDl0VYxgKHD9wQ3m9j/kspYlyAPyHJNSG3lMWIJnJUO3xvQnvVhie+/YG
aw1D1/CjPB2nJB6AihfffEBDHB5JiPXc4xjMKlkLVENlVc3cxu4oALYiL4CUmgXSHRj4oyqreEDD
jPU/ykoBInsSXl9dyi4nJWILpNy4a2FzsN80MaVRgRNGsgwIvx1RpL+eAcIKksTvzfmaGBC8UxFb
rtMrwJkOpfCOgaDnTM6k26GZRZiXInoSWZDMaWmpOD31tp4LRrTXY5f7RfiEICy5NSN/kUyxZ/Lk
Wx9UQED9brYf5w3QDBEtWw1bIFE9zbUWAo7bY70cGC+xfSpOAWT3wSfdQ0gnBo/zZyVLFiiOrBu2
JP3yafRVfYTnvl9q+eYgdHwkwvx6g71FyX7MWDIryMtZ6tjeY7la+D7/IQ7mB47gJWQAdVKXdzOh
tmdSAoWfvKeVLdzlzFd6e0qfE86y1iNxrgiViZQ7JF+N8C2S0QG0F3/vbD/zB2BRhT0ZZB5LvSXT
LQfpPACgfmNy02m2W5d/zJ8QbOykMFdCdSy1Jo70heG2KVgGPffE1MaFmgmbm1uQB7xUPv+aJr/B
aVtLbG9bjR6Gdo7S1POzXKzikYZ9ltYzaQ8mqomQv4I6PzQgChga76/UbRJakLg2ZvI0ZXA3//dc
uOmxVNc3/gcQihOOT3qTAix6M9YGHvCsWPlqNKVx2h+UJvM48j1TyuBRPR0U+k1PtLYLEJ2R2Zx+
yaoHkQs0OgF2mJjrM3Mz0L1iToF8g+LuL1jNCeftcjDB6IQthdX2U+O3kKRuTZcZi/H4Pm6MYy9W
Rw9TgHWztq8ioEDgNq856MgZRX+39RNSoNROfGTttNDZzS4Yx5YDtds4qLWJyo5KF7CoS6A5qok+
9LICF6WMKqIZzvCWXBn1VLpSpB1yfzfv6hK29Pl/MieWNhltOT72NrD2tufkS+iyM95BirOofRbW
zGIqWVMMPlA8iyFuL0a/0nYD1Kck3iDp3WjBs8IkYU9LseWbREEiTqHE1w0056ZMeKmCXjzqphdG
kfO7+LYcY9YaM2KRUjXHBVw1nYk2gtXOz0hcaLbVva8/mmx0YloFOSEDNDtz6gzTjmxx1iiiMN10
KogHto/CmUHSR4HmG52XwKoofbR5q+40RqdlfWi5KSN6gUqSAyY7Q7OxU0I9tozoi8I2aKu4Ytzv
fdqUnQeEMubVTuveJf6NPLcmaxGbco3cUrLtQJSFHti2bdjRS0PZAFUnNawsuYpxkmo1GTTkFEuA
uRjCmc3NHBjxOH0eF/CMK9hKj4ghUQOzcWUNEOjZNsP1rDKGgOd9+i9OPaqkSfd5B4w7IZU5GTWU
SSupVxNlk5LNmsdgCQVCStP1m205jwUHnJQ6q/Km+oD3nnb3A0ij9KagLtQetWPj6e9QVFx9qwL1
S3UWJowwWn2Z/FkWi8muK0/M1Nae7IRBR/OvnpFkto1NSJoc6NgBlBaeje0KqcaOLsGdgogVQ9bk
bO22BWs/hFLC3Iy2EWaqe3NbB8JLI1YH3vttswibmQiegBJY9YsR8F1AkEOjAUaHz23+29gBNFLA
VLPpJj3FfBEaVZ9cXqaRaEYFI4+VcvcKAHtd1NKGzyAr5XUFoX9V+kTrY7m0Phogpb5wJW7AVZhp
eMu8qzmbfFG/PITNo4ThSw5lGm/YApzv7hK1mjXQQg6qzaMkuXy1N09JKEN4565awMqKCZu0sWPo
Fq1AyhH/p0rsBli25ti+HJrhC0uEXpZ8jCBZ2lkYGfozK0XTqMp7iX+Rpq+F2aYWt/0pR6yNeECy
ff2zPMIvtKIlPFF0u0wEXAXx9GKRqpWWetn9QzEZzjZnAWy1Sx7ZmuMvVQEKpZaH8j48R3eMtB7b
Jj53+MZFJu+XJGcCKitIjU9BmXcIZ0XLeSdL2F+IRhtcEUBuqx8Gky0JNmyjJOpDVReKUZtJLwib
81gWop7YM1OTOKHgTOpeDmDFJ2dpKPA5dJr9JNdkkdLq/+Mgba9a2wYYb+TuEQQP3nrAcoUZzt66
HkrZ97xPNbzQqA7M55cLHDKEYtC3S+odYJUZph7gdelFT50NRD2qlR+Zc3/yyww/fRJd1L0kmWJt
wOeeE3bVp0QBvrUeyqtdjCCKLMWYJp6TXLOp0Y3YWzbrGjR+HxETe87NwxKEElja12ZrHFPjzpcV
bDX/Z6XrtHhyiL9xoizSTHmb7PPYcRsOLGl8YzfHzZVN5MZaYwTTNTcsUUkPFry8vZRoWMOlGCRn
PGA/qT5UVKAHEukPoNNXxOSAifuyYUJq9Lfx1zmZ3FdqJuO61O1vIyejHh4CnfujNDSOD7gGwl2n
gUSkBPz0cKxdefqced4bsBRTDQNjTpvVXn2EAS/I3zvwQgM+VglSggczJ6aMBBgRPGA/7pKQ98Xw
CZk6TTSNDOZpqPpAwIgm43+afQirNltNegbZ21CqPb6rXVtUTd4f0GWRUWpSXdpcyB+6g27z06xf
18l09n8/XE7ss1uPbAeVfAGm8sPQHMe9vhkFe7aIe2tzWMRxgWtPVY+Dy7OKwbpHkEhxfIMGmfiZ
WBVCjlA4e15myWel+isSa49z7ro+pQ6UZFdqVbtT12T26RMQhl6YEZqrK0bktoPJiO4CqM2SaALk
EN6KIF+AbhLqLhJ//VQOepBsgBbj75DR1wOj4NhkRJG7Kkzj/mK0JOx9ZzmV/UFjMkhmaNbuZTcN
2sTV/OWG0VMjmEEKq5ozr3t+D5CWa6B+Yb5B/W7JTJLyKyO6/bljFlRqO5wYz/mqP938Lt7E6ImQ
9XxtjU2pj8RNaqyOUjC6OlFxFKsKRPtKxyXwRNUaNw2KPPEHbVNNM8olRwAeegvrTKHZGFzKqYaS
vQQxvm3MmvtulfCnPbAukpG96PbajsJWrA9tHkAicOu6iT8httX4M06ZEOZjRPYq31eMNt9mw6HJ
RfLZq+8xS4XnGGrdTcHprTR2Z7HClTcKukniMGFndqU6adVGtM8Xs7ygon758s8+Dp8ZWCp31pcy
EPiQzUhM571984RmebOyDcxMn2GeF+2j/kCcK0kHPZPLRHoXquffOEVk1246otpyrRveJoe5AmJr
ExIBPGpbiGpCIqKNmEF0QLWr5Kju38Y8ZSsj5+Q1f0tLRslc5/5JfgM6lNbTCnC9eIENWOoK6RGe
70SxiqbS3q4YsrArVRCHSJvO6gt2CJrHToMGdxlJVGVH75t8RJfsx90y6kJQGBgBCbQcimt2YOSK
dfGnMsbEwS+A4Z+UDuFKigHdZf9yROTgXsRPrFjfdwnw4EmAuaslZBBJehopieo/d7uBci8GoYKX
j2HD/tSeSwm0wmBAQ4nuU9oDZSOrmNULS76wokNPPFCGb0mDxkXdjpgrRSzHzAtHflb1MyOYMkE9
Ti9NIjrnUDROK0foZUEQVCQ2ZdkWkAnCFIm4/4dhEOLigeJkCGklW4N4zYKWd+5Z7FCOLG2xLws7
qND/D6osXnNzITgnTiGsoF2IMDgr9bNyStrm0dyCSG1ps2izBFtpPig2cfi7n8pC9fBDWrUQNo+Q
R4pTA15tj6ZavfURfwVnWQ171e2Hf9LuN2daKOWzVUfc/K+xrmZ1KMtdtB8fXElI2yVqcNTzSygK
xKcC9mgc4+8qXQOl3Z+802q87MIoFK3Bmuoyxc68YE5vdBYC0UOERGXc1a+kuVdowXZrikzu6UPp
kn4L1zJi9O373MPXBxBUEp1OL7+0M34FwVybyKiWG+c4nYFrdUsb44foWBtik7Iqus+hfy4PVYSs
SQjiVqeStpiJlM9jl9ctS6ygjsSTI9ygWUVJQxEh0t1F94y7UWfi8ncaFPJN495FVYf3H+oyuTEw
hKQawo2XMWvWMn+/6xm7YqfoqEOW6nudc29kg3c3eok7qjtnEKSFWFUCSCxkI5xlp2+TOIlkgO19
sBFPaieclsH3vvdVkeElQ3F/8IJcnfhbzaaf91hSyRTGoaJGMeRLENJzR9bjPZDAvq/MWtkx1iQK
NATONmnRNUOhhETIHnlnNiqkg/1T3qLGXMJaHRD1HY5vG+o7UqEZ91hw2u+8blQ30fZsu3Ab57qi
ZwzPQyFJmfyGpmEGZBQGVV1HeSmdEifblchaN/8eba3gC3SPkoEswlepkVUINvhPS+9qXDmcPIWh
jvJSsUyBH1cDdRQt00WfY9Exh19aU9Rt7bQOSSzQVhRORisIvB0AgpRQqdCfjomFnypllE1jC4gm
BvvHKsw9vkhzbmRqF5fI/tXBrxlhhbaIQb1bJsVvsJZpYBItnd6O0ok2Kwl6ZFm4pAma3LkDHQz1
OmrgnKLc6+KAYpianfe4fgnirDH91RKKfWKha8zUmfG6RJRM2+YHiiRy4w+JBVBaXGlIZQp4E+hz
rq8m3k4VmLyPI2UMZ3Aq2MAm/q3XCa858c6RbfXHPlts0brLr1DyVp/NARn3SCQyi9+k/4bdobS7
lDJVHo+5067RLKw9tnYxv20vpWAFTORxJM285DS5gwFhWTwA4rLgPFde4NLFuXr9f55ozQtmIneF
470iLyuzE6tDFjHcyoXX9oOhRFShS2oI/jzueFvhEyKmX6l9gE8tMMs+XCUFxjRnDJur40jU+GjQ
Nh4eXAgJlR1miUv9zjZJBqYyejMsznea664fapojU5u9jaL7gcyLrwYz0ibOOXEBdb/69IQeYvZi
/H4Enu5H/sm3Ww/kgXn2hs2L6CIHlFzpUbxBkWfuB2CGfg3+YEgwFzzZHY/JcSi2Rkg1TGDM/E9r
qqRbRTL+LSzc9BbTaZK7tQx+WVZMrS0FoyOtQGozf0JOre+VczAY0psZiN++9cLsbBGdNo4sHu2/
t0T9fNCkXDrk+B6Vz3jdMhS888RFMKvJ3jsbtYAZF2Y0MQqN7K0kADE+2vjKxCwDkhJA6yFQEqQa
2l6RnwTmME3NdYzPPIl5PFaOfA8OnERIX0KNd/iLPl7S4CVVAubKuLBxC8A++HkrnQUXNmaNlJpW
buufTebGs1rW/eWb3yL8kXnf4uF1Vn1m2sc16qqmhgRKqPLZYgYs97lQGmXh+ihJHSQu5bPqiVlf
RcklAu+9IXiiwrCU2uV3ClAW0UqIIPMwkr3e7IFZEd8aOn3czjvROosk0gVmT3TTmPHlQcow62a2
QpG2hJVrwccO8Px8/zPBMkHfbR1S3C6nA4JFoRfLbQbWQ0i82OwR3rGyMKKTkh+DWHmKXqdYzNnN
27yyBiX3d18BWsrcaH9si5w2QnJj+BcLi/do7vf5tCn64HMjkSALy4AKal5Coqqb8rhKiCVZ6IeN
DhnsKZ1xKQIKRgnFhVqytPy7lt+uQ+umPwhTUdWCtiMfsnKDkCQY2h5soBHFdHXzEeY8LpAWR2BR
QmoEDiXHwpkNKf+7DesskxHx1XCkh+MyvslEppwNszZ9m6eW9JPmoyTvIvIzbywOGPXQLnINYa4i
hE2O3rpqQAUTZqVx1MIaofFXhXV8CBja+0iktbdDNSTBQ+e4PCjUQHqfUiUBj+WGBdIu6bos++Ee
gzCwkZWOXSY+xdXUoVAZpMta3sj4kP/P25+ch7y3KrKuEL/N2JHuvNYVnFIi7xRBRLO8O79wqve0
LIUrQujg7I3NVPAqzKpXZeDk6e7kbhweykk2jrkb1QfT79e/LjVd3NA4YC3PrYuRpXlAF7mGNd3A
9tgmAV5TpxeNtW6UaM3rdzF2nV81WeQc1zmx3JxGsSrDZM6JZ1DNzoU3F/SRgAPjPmd74QlYHai3
o4ZvjSGfulyjed0R2cz9bdB4D6PmtG56U22i67ORjPoL47WCpRVOYw7hnsuwLeNGYTAhote7taba
zqBgf+J6FJAf3k96HJyiRDRRx8O37pLOohC3iTIzM7UzIGRMn4UWGebdEQ8b1JXf1xDRXZvg/OxA
Ce/wdRwReNiY3Rf2qCu7ckBBcc/zQ/w/kwGJUC0gL8l8K03EWqHJgwM0+SSkXdFGbnPa7tTphydJ
yGWIN3YWCH8ZLN3rCuIeaE9Mqb+LVsqar5Wv/HnodiBHnD2lPrfps5UnPyd9QfGjSdKKk47Tj/HP
WYyJ/3KdAnHMDmqWP9LFe11IDc2PetGINBjixRFJL/QfYkImaS/pmaVYmc1IgK1AOld2NBXnO0dM
5gYC+baKSJTQUw+12n5a+NMb94vZ8qOrIuIIPi2rDOTTmDhN/xEhzORg1IbipW8q6K1bXCNsItpQ
FRvuZ8X3uxZqqHPRjvIjfiUIySdl5OBSDfKpoe8GkYR6IJOTjkx22PvIwhzOhhggf4vKM/znTBjp
B+XPXFnJqAmDGtjU400tCIOf5HU5OZHUCkxLTGnPMIkTP8GtI+ooGsG5V61OIq3qoP9vdB2hmTUo
VMVYgbzvbVzJhC+ip2hW2wt5Zoh+s+XSZ6Qvp4uBjm0heI7pR3JPR/ALUWuFQNVTjTBIHCxbyKrw
Ay5LdLwusbzBoQsVrF6360r3/DGXYetziGE29zHdOevUl3X8HBZR2KpO8F+Z692XBLgaHuqdkZkv
Ww2D2jQCaAQSSKa2fY9t3QwsFhfgCFa5QXHUiXDaKtdTaBwJ/Wt6lTlyTOo53rXpJavkLfqUw8hk
GrKmjPTCoZtNMU8TrDR12ydiWticb+ov03cCpDqyq5h++Jdzkiz/QhbsHcxVNg/NllU7/luxF0MK
n1sC5himamnm/Peo0uW3itGtXehQBUDD+UnKD+lP8atMzWuI0TyppmbKXnVO+3RSlPUgzJpCow61
qSUU+WER6CaBcUwVPkCo7mgIqi1gUktjiRmfhaxOUp+ifaAr49q2d+VfO44XkPL6DZx7EyTu6Jvb
sS7FLw+C3YaarFe8+B14JH3KOj5lj41oHi+Wwx+izJaT35tkpdNr1V5SKz/LOlmjLrhPnvlCYlpB
kQMDtm6XN6AqKLLBcwma3kVUO47hHEDLjBBGPH5YBydM9cT2QawDWZxMMED5m/6xbfjl6ZfwGy0R
NKfeZXgRn3cWFZt7/Tq3VAdGS2c2Hp4IQVhko59GpygM4b6hv7z5kkwRmA6LUKAykwH5z3ULFC0l
s1QLyQSa8pFkAL9zDj5C92UH6/iUhoxrHkgPLef38k84Lvf+oAcpziPjnujP9QTn2qs6OIdGUUBm
XCFAh6F3mr74Uvu4NHIf+4y47hZd9HxORYLnwRa/dpGH1rNfNB6cuF5J7uvlkwx3vKxenAz1NJ21
RIHl08u4S80drMsEq78w1AcbKKzeB0/eieZQnn753//F8pgxRpxOR9GHtCiR9FCWtSNdgzNu6BXn
+exHRaxExWMZGKsoJH+0LRF2IpPvmvWhqf9jcWPhxPLK9tRrzGyOEcs0clBI/W5DICQtjCW8ecCe
RqitHzIreDpjAemw5uyO2O89sldSGXI61P5Gmk3BBNP8Mfnw6BVCshXAuMk9NDR9zh07pz7urMnX
p+rdxXmdLQZysv/Awg6+Kr0fNW8WP0RhrjQpLZlV3DC17kFJ2QUu4b9e9SILNqAUJzbfUVDxt2Na
X8+VE3hwOFrvHkkz4HiPDay7937HIEoUlfTLVWP9B7j9rtUuis8nCvI9qKpnungnWcifLv+p+hi1
SutUxBEDFN/ed8CoYpo97nDYASYSLhnZlzeJIZzghhlYwR+T38nBRZeMCQL5u1p3vy+WpZQvuq8B
1ohC793WTh6HZKYaqzylT/oaHwJGLflqlMFpbpJxNOoKHf4DU80IRd2/deGhFuJBEoGr2LXgkZbv
79Q4nTKbaIlk0M4k1xZkZd9ofrM442fsWKj8HebAgwq5Wzp6cHFzHpfPyfAgYzSS2rykBeRgAx5S
Uu9feCelaMjYsYse/W2nQZp2FPwJix4eTRE4XEuqCHTVO1Qm0EnJkZc49gZIJrcDasximm8JWA9D
Kb/oCsPGY3ZoBJjhpX9RQyhHf0C+hxtif9mxa4ydHE3NHnHbPWxf41GYntRcZygDCbCBuop57kbw
xKlLK/UUkHoYogL9GWd97A1dSJq/KfueDtXxLyLk2wvmBWWGk8EiJQmrJCrPUVKwA+LTj3u9JC8U
5xWajbi59jsqDRmspKg/1DXN/Qqw1S0S0SaI41Rnoi30EqeSqaIPsHW4AWDvPo7y8fq+7JBipMBm
JrTfpOitj28G6JVD9xGnr+b4cDxp69JqedcbjYyD+a9RUNTFGhiiUJar/H9n9Y3FcofTQ5+KfX0S
av1PS0p/JYO0YtFjkyDDZrS1jpo78H++B9QrGIh3s2qQdl17eDnIbYmDwFo5nChD3dK59j527Wmq
s31M/ihvkNLNUsHk69Kszs3/+jG8PEEqCHABVeio7aWFUyZYvZjYGEnOVdXLHsRdYfV5ZfRyBkhO
MTJRtYNa88TLZvexTgu7kN+Y7KpFadBPXpfUVsKitgdmEnOkymx9xKHb93HRbC4JtXfOFb7VSIri
u+uFLp+mlAfj1sziTpcJloL1W+9hjOyQ4rK6v9CS/WvbjDctdQJip0BZ9tRDWR1rPeSRj7peoxVp
0gB4Im+BNHapgxyaMwtLChMK0zkJeIwvcXJVvBTUcDXZ5PCaD0kvhPqKCXh4FctU1m+7rPEEFGtN
P8HdmgyNpi6sU4qVH82q7UGz+S7VaAkZSVBEEJxEl7ZPm4nJqhk1ouDOHNhc/6ixeqnNIOu9QCC0
16kV0M71dJP0u8YN8+JRy6KbmLzij+6/Ka35HK+Xzsd1qAPt2xkJMuRlNOz0i6kS4Z/Q06cY8nR/
6hAVRR3ayyEQsrPzPJYQGZN3XjV1UAgjZKDZEHJWNmoVJDF319urYIjerYtQSNKAfg8cAReAWQ80
NugQ4J65AzYoV2Eoxw58jRF6xYEQtXmiNtozOg0FI42ssB626yAft44gANM4g2SYsVMVoWKTY8q4
/IO+533R45a5I93GVGKM+md+vbgijmsJ8P+xYcWvryG3yC4OjpBIQqgQiZjVaR3HSEbndQAckfd4
QDltDMXca7jKwmYbajRZ6x93wXtcE30H+NakmA8NfTUXRCNGf6FyeT2TnJUIrwmMVJmnbrJ3h3Z0
eDOTB+nhyfxyEwT1vtuFgIVfvZb80hn33gl9z+I4m6aISMkF8PS48B/eq06AAdU8gtiqKS1eQqL2
VOUA/aXNzfSHYMzwxVXwcWHZA2851ySTyiZiSuESuqslkegOc5DcVfIH307FQEsUJfjGeG8JXiCh
GU7j4AhTrX+d96fTp5MGcQqh84DesGKlrKnKG0rqDDl9jo3NPTtmV6CCqOjlPna52yQ0lbHPkojC
sSQKLK70Yd6sAzmdLcXNpaDlpf+z3xLu76gUnDafgWiOcu8nZwnmCDuWoqwpYZ1kz/ytAleuzHbb
ipo92wgSN0DW4VeA3s9O2IgGlvVieDak3++pINakS6aHmZRWcR60PiaBw0gVKp7J5kLzwcf9d0x6
ViAs2W4TTgqY+yTCRThgh5+pNPtSOQdXgLqQRLinqut1ZvbI/yqz+iP3jgL4K1r50Q2ZRA8N1wKY
P3ZOpbCMODi63Ys9k6k4BH1hw8PI8jdXGEOYGX5cmDEkMRNY60q5sGPDlG1SUn3dlLUn++dOg+tG
8ktIqZiSAEkn832JotIKXrburItFk2I9uaVU7COCcCpYi+txieCOjYYHs1czHMUJXy6RxVNBvoJp
sdqm0pHlijfldo2maV+QHqVBpk/O9HwC4L5rkwugmOJEAEjAsDokXcDa3wutsO+i3Us2zsZ4Aw94
6q0lOa00eCfbcqNMrXyXrcp76jmDdfm+8/kjhFgW6rXxLs0+/M52I6xed0MkkCRWeeab4DzsXeoI
GaTgM8EeyGKO3L4tKeTj4oCExWkFONNCbClbtxAzLZzwbhR2XgisZ3KWZmXM0vXq4MeOUUwsKFDN
LBp/T4VLMSs1PxNWnv84VGVYWq760CRNrZEkGHSrno322MIufP1H0A4YOhcZJqy84eTM36Q/Xr4v
OUAOgTGUOnnv7ERwVrjqn9chzQ70mp/LA64mMc3QVVIkCW1tMbFJQkuypamhT0vsoc5Rc3rAPoH0
neeGngN24jS6FObIzqLt8F13i9BAQUyt6bzUeHHO32S1/AmQhxKib2f8KnKUJouplVa77Q7EXePE
Dywl1M4dDzXGqn3nsTgMNR69G7dpQ1vN4gbMVCP2PNz1Pckd/PY6SpL2r+GqvBeh8XTxnah8zTZ3
onI6OWWWyRgphD8OOaE/Xu1AR1Lcu2MPipkEU7T2rWWVV0Xx3/cEKbO2vLhyZQODCQLqDa0kSOsR
Jnl2DkOW3rGN5LYvA092O8Az/xu2ly75S7lKjoOijO3ANTfjBllUfbOzH2BxyQ0trjfUfqHnI99V
3xyj5ApvfwfmePDPHjGvl/WpLcpLCNSJP2FyuNTPCkDVgfW9B+dmEk6u+kdQiJLq9/+wve8jFpqC
aOlc9nei786slHCfg973anADzBJLFY8tDdlbQn+YbgTgLVLtIqk0yZFN3inseaU8/7qixuybMA4+
xBZBLxxZm5KvJlkmoNq7dN6iP0XCsZb3yUcBm4Dy+WN87fvdhl4EZcuzTtBC0UjqpQSetRIvSZwi
24sn78hb0AC8IOoGZBO3d0yCAnB7ognhS/+1X94fSs1GZrgZbZWHotxfJjcPkN6QYtAdOWV1/CW0
Hi5rqH822l+650/P/evDSs5tGtpZGDTjsrQl9Aqz+sb/x64J63PuQ69m2myQc2CfmocWQhqcLoAI
0G3emcDk86bWCPywjg4KEx6cI6IkwMNNjzRBrdz+VNCpAHzmO0Q2AT5QdSacc7B8tCK7NXs3FJuA
mWGHuD67+LhC9h5bkR7EoPRvXV5gliUD+zspCNrA3QFAkgT7n5y4//Doy7nhvNuJECWQlmYeZMns
/ZrOsjQUPDhrBV018ZahzemC3zriCsxfWbIyTJ24MJaNkX/SuXS8SzVxIqUnn9vSJYoAuylHBEgj
pLxcwoH7nkeXKBLWm27/8xyiKuTq0nAlbbaW/Wx3+CSWhCWyZvzwEhpMRUEWJuxbssMmr/FKSksv
GqL8n58ouwcNJSKnuP0+N5d7L+tXaRwvH+fhGvj1yY1upcYzuMvnKY1XKxWXYbGHZKwpRUkkqlsZ
C6QEPfsOUGfYsI37mtXGdlKX4LlIcnCX4FzRZu7GrNS5fIlTkd0W7fmX+4LXpzBRsjoCejMNV85q
0K1qHdajA8MrhcqsqjXdZJ+uX9zTtuk8qTSxuSYdTqBhuJB5q/QA7sxU7s09x+IGiM7wLjVwFP5G
FiWbFKuABXoXPBfFLJfQ+5bKalssdVogU7I4LFDRk4kVWGy+Pq+Y8K6ATDkKc0Oyz33X+XzaTgSM
CBXmDJcjUW0b9bjX4UDWdFnd8i9J9lL+s6YWSMN3dI8l6RfSOjxfWfR5KwDlY/IJa1UaYWP+tpgC
G6V4Y9M4dHwDd20SiI9L7tlaSzQNladXBsrvF7Aw17k5ECouGoceQLoQe/2Cv0dEjex9pqExypLQ
972bgiipfbzumwnKxo/VrbyfK/pJcd3SpU3QNLYT9m+us7vRd22FBmoFcQISsaTQPQ8x3tXXnc4C
UpyI/JzYhAjfzeF77kHDySgAKnhcc41+ccZIEoZbu9f0UWW+FM/9dtl09cw5ZUSeTjHKBe35AL1S
BO9g/0cqqvy7B19XHhPHIYSs3PpzysTv6XWQWQ7m8B46kf5h7mEhi4ewj039rj+gpFH0bAPntGX6
Atng9Uo7aVrjCY8YCoIZCyGYPfbniIflMWcVrZP7wW+xVZNvrNm5Md/2yF1dcvz7mrR+dGT3q3nn
3fV7QEHcQjDMUa1pY0xEDNTswllrs5mCyslK8IoVkF30F83I37m2cvYpiQGAEijgRyaLaFmSjEqM
MA73LV3Zx5T6u6H1DxD/+ohkRtXIgA3yZH3QOxP+QyIhC8sHow4xRaXVSMmU/04KBpwwdTmST4pO
RJe409z4bC0uiPiA/Nuh3JkQh01sg3rEVDCPyreyDNK/e4zNJo3aqytfW+VuuipBT6o6CDHfv+/d
OK48n7NWDEs8PXmDT0wzdlZu9PgoXMaeH2Aa0cwZ+mlD+j6rtpMHUG9Ak7vhIyrl3Hgv1l4TB5TZ
Tzz9rFqDA6l9Stki+qqZ1gfx/F25e1o51x7118yHFevyXX+gg0FTT+oU7dH60GlDZkLv9/WmQhm6
lJG9mbZWPPL5Q4aqfbA8lQI5x6NDDR/SZelEveUz8aoDnMJsW+NSwMLD8k5jyBOW4SPNuyfwOKMU
/2FYN8Axch7S3rXhsMVW6zCLcNtvRBiOFITRXWBg87izCtb6NVUiWSMRq+YSq0G7UXISdc6BE8H2
n0rBu2Ytklz12X3WSwzjK/J+EcZX73VW+NFXO4Hp36XmKsxcwCXJRXJKJbL9YZpGzr2gRuQbQKlP
x9TDTPVO1pVzkbkxGbwfshBDbew5/yY+5Di7tSbWyEr636LjYrAotF/LWnxe6wnDKx6ldW8MlnnV
wlrU2jdQET2T3r1jvnlSSJuzUkEKPqB5KxGlbqGZMoVkHqWeajnfae6INYsnBk4WSfLsFJtzVi7O
6Ddg5lQHgFyMT1qxXPMQOS3Bk13/QhCPIsm/ZbEXh2SXzl420EaJFMxidGpGyYR3pBBhBGeEIcvg
b11SXnVLvgK14kaqlsRWlATwlBAzAzEAFcUCTblFZg8bFtHEz3TSnwzqK9gBvcEahnvjXkoIDwcX
QYgAkNXVFST3nLzsTgrnAcFoMZQz0LGPBhT63g2kfTGSbGUWFoLbn3dVoJavcvrzZ+KeBYhHtVMp
7igrfBPqUKzlidh4lG4W2eaShsDkcOSgO2+pwbtiZdEemfQ0uSPt4x2kA4RMllMdcMDbpmem9MJC
wPk5BDpY4lqrvrWJEnhdg6YgXvrANrqqbn6mzTeucygM7hnPW8ASijEWwM+BszCD/nMCy9X9m0MC
0EEmGFGrK2NwtW/J6NOogfUdNDXg5/+KdGISJR96gnrLu8iAfy4jTlh4Md6MX8X3Narusy9F8kA0
R/FmJOYBuz1w8lhJ2k464EYYaNiuu0iXPtUfw/SJzXGT9F94gBiP5BHXjNk4tpokGIuWmT/3bB43
VPaO6BAAE6NWq6C/TA3013HEsKecEgt/uxwSirRj7iPNcmeWY/WU0EIYrdv7x14G1ER3bkDzC6y9
UJzGne/zkvvMQbopTpJWbKBf2Zdv+EQNVKcf6/TRK2QkgjlDfBixgBukBSQAxbfostjxsGK2Hi2N
3OtQ42EmX3JZzuSuEA/ewqqsyLmxQJDzG3BWOjqmF7lyLOIXA8KRp1s4tpAoymVvcIy9FZ2IlosV
s+PERpa538ZsYAJIXn6MBHWAIZ53AXXT4p1IIsiDo0j/f6IfOO3nwqJ4eCfJVdsOx9HptMU52EnE
0sY6VsbifcC2Uoebd1RV0P7nvlcyZ5fnXR6OVReFVm2KnvrVrJmbZxwlw0ADbfXwwFOjMew3ddRY
LM2++7foiMKUTvFL60xEwQujm4QjfjEnA7nrghAQ79Jayq6I/Rk8DsDwMeQBufS05KT0BAIutZqH
w3d13+Wkfl7u+wHiTMTPO+W/jJhNn+BB9kYD0VmrT7ikuGhaW+1mWHsARl1QIE2o39IzErJOOyKd
HTQVrYueDOuJVKY1lacTAiRR3nLaoBbOE62eZH+a9cvD0TDQDdqpcUKw4hBl2O9dg154zao2IPWR
yL1+3+8lNsPlSgvORq6uL5z5u6Nudv3iBRPWF47R+7qe1Pq5yZ2QCJzVjVsjYuDukV7IH7EAcS8I
4mUubxEyqyq63dHrSU9geXV9Pglrz8GYG7KYV9mM6g0vUTxyw68+v3bP6YHwR5eWr9FByIEIBvZm
PK2OIIrgM2EqTsAsyd5sAHmKU9z13AS6e0qPQgS1r/sxblUceqxZkBeqszAaFHA/Mxwry67NsElf
iEGOrsOZFqltGbOTPSGCFwjXxSzvD8m6czw4od7VvE2zrzTNAeJffqgox14l+7WCObCMTd7H0aea
kS0/SPMft3W8fTWFXr11/o6Xpao0zhuCOhIoJvm0R7rhhN9xkl7PF4STXt1WRwNZphZkXNbJV3+j
L5asDZ0uXe/k3ksAMU35RnrDjCHsXk7zDwMS6MwdjFZdicT+syh6hZoxPj4LzCWOCzkSTZlOwJIv
TnHBwsw0HX6XvRBDGro/sICyLgpK+0xYxWU08PkDCFylNyjUCJKu8IDggN3B24wuPM+mtgPaJv8l
iIJrrj81h3xhBl3ATn/DbU/c8NRz+hcd78aloLznlJF9rdfw4Gpy5jKecDpqh+wwibiTSUiPPB43
EBXXw0zTlX2ag3Rm5P53Qi4axwRevfqaWhQyb+tSlKyTFuWtwPPPfQ+RnRCZy/Ol4ReFlnXmy1sI
ADyBl5a2OWquJeW3wwlnHiTtZfm6GzCk0IF/VQZYb3v7jsMcP1eva0b9luHq5J+CKDwGPCFFHn7/
Fkm4h5b8bh2CBmfUqAhTQioJilqoEwB1NSiTiRIo3VBimBFKuspiHr9tP9SS2kTlPkJkTGvrsilI
04w8iWyMsVn8PgX9umJLYxj3rkai7vmFAfcXH/8IRVBr5gncnpyKSxTx1JVxaRDIoQlCK7rK9LLi
BOwy/7oHKLTCaXqMBuCvJK0DkI2npTc7phf2H5UKBgSEM0WKlnGc5cMLU0p5NufgJ4omA+i6UGtB
egC3JdvVHpYNk0Y8qi8Q22jL9Ko2qlfrMnpeW58MedbfKRR2zQcXPd5Q3nSASPR6/p0+CACI6IMU
0XAwHdCNiTPxpQWgSXyKUwxccnAWDOHbtkB0eS3ckGL7aQOWxwQQP1/hG8mdj+jugkoG74sKEP+P
l8vtQ3lfHvn7UinUpVbRncNmu+EdNfhg2A0gByyAovcpdC/GnY93fUps9UkGkJ2DmIBrlvKFikWx
XvGv118MRioqHpOFeKztFsh8hEmQbnhyU1IryYxZSYqVH7gZRhOv0rNY9mLSEW337VVEXrkn7wuB
dC+ph0J2iH0m642z46XKdIphATNwIJEdAayr1dkFQLTKSj2igRNVEa8pmaNGmqLbZXLdp0ap/YQZ
s4UH7huifKwn4s6FHzClImO5QWWbo3YEhmgfWKIxDxX1dEr3fhJlpPucNtjKgtde+jfD++AxKOlJ
HhSDUJCJWDhcpGFNUk2pLdnojjXBxk46dDlqUfuOjBPOLn3a0qNlFMawirbeTGSwY1kf7Ev4wTzp
C2EZdqLrLRfWlW1qORGzvSKYyvxwUsjwZGMJGSayYEiyYw+xpHeqvLD4GHzksAj5AVgtQqXwl7Tb
ELpKAhSKk9SBO2vCYEQH3oI27Yw+VNa4ck6Y03V9onZ62Vih8Ar1N77eRZKJ7N+IaJFhT0JkRtjo
ALevM7Gq8UpxV36dOrI4dHthicFOLrbrhcB6xfZzMcMo3icGewKLoeTj753wZRtgKgBAY/FEc4Bd
5QL0zvazSzmAkckCSliLkSVdRzT6HTZgp3Or9GYcjOHhvEayNyqfKLK7fvzbTx/yup1zQN143CRF
PdI9BQN1wF6Pdw9hcKTRf3QupyrWuBRrrd/6G/lN/KKW+kUNSLGfTh2rnlP+wlUqMJELuVUMM+ky
oqx4eEyOT6xIVo4+PM2C5+Cpm0eGmLcX7c2BZiqnDLqx7Z1frQNFgQMM9fakCDZO/+s94aSDPbs/
PnIZhlRKRU4U7xcTQ5qsmjaA8jwQuHS/WUj+HVn2hTeP7LzONS4obGu7ipABZsngaUaOnQgt7bNp
KnoOxpwigRaM/jiNfsCJFKN3ZGVFD5gSHr9oHccUILHY61UFkTTlcx7rXqSSWBZvr30c2MyEw+rF
g9SkJTGqh5BVGuClHHWYyqrHeQi8/dKG391LsFYk5B2GR7EOKG+An6lvih53AMTk0QmJRd6ly4Wc
zat7vGpm/WSC2s71r1Q6ZffCLFkfeiyJ8EbeVCyNqvmMUjU5QcEDMz9oGexH3U5a6htFlcyILlPb
Ng3iPkTmaUqbHxYYDAlJ2d7Bo9tzXuPMgKJ24iFV8k7dzCtmvk5/vP0xApB1GmxXeY3vaCiDV+nx
7Pu8lnXsJjJmUg2NfmhbW7l1nU8MVzo72dTxi0R8wgDG0QriTL7b0pmxkilPUjJhxV6O5Us1yhxN
RR2WaUWqghCJZZWYDL33dFHYAT/4toFgGbegppwJMdvV+h29EO+MALtAxhNdOwup8I5KixqHVTp8
FYQJcIgm8XkxdQltydDf5ChUob9rfcj1RX4xGoMNlbB0SJpJz86HSZbKdgWh1evsjW2TLLP9Pk/F
nKow3W76WN6W5B4duirtuKHmexkxTIBab2FjiF4sWgAWu6swcmZ2Y3roirQ0NCyaWst1bbXegTJY
PBotgZb+v8rALicTO0EukLVyPCV5Uxh424GMZmsN2TskpItiraeO5R78Hy1H7A/rWNVC/r/pXqjx
EhfKqBfEy9/B4uo7DwFajbDpQBikQ+Rr5QcQn65+lMzigbLbP2m2/sHwnIsHhwAIXoukoFbzyL+X
MkF4UJ4e3O2ub2sSxLpIEEUtFiXAyamM1Rphn31dC51pVUHRk6Pjf6YBOo6R48oDyCz5zipAYs+5
1Hhllc6ni0Y2KaQNLS3pe0lqkXo7DvivHaSJGeYE38lp72xM7pSMhYmAljtTm+ifhTC7uim/9DKr
3oJ2kfyZ+AiH3dGDvUFX2sAuF+pr6eMcnd6DZeCki/Qsooz9Owu3ENHo5I7vqyfX82gRijBY0eYe
bkmawi27Sukz/A7vxwGD2frF6C2voVdZCExHB99ZcT2baNiD5DW1Uwqh8ULY0oBKVHcQazcR4P9H
Z8q9Xf36b0AwB1ZU+H/coRttOvjMhq8bYsnLzoa6PK8lyVKtIlg8sy+MRx89YVyTGRNv+uMQwN7T
bRHVYG2AM1vbBMF3hccwNH0lgUQH97V4w4OCWxzJYBo3NzPanNz1/Qzq6hzSsaXEq6JmWrJqbFvs
/uE/yISStkj0y+ZbwGQhm0dFf2Nau+YzxL76EOA4mPJdU2JVyMYX4Z6EKDk/SdFBi6pBhmRMYB0n
8/lKpHg+GKc0OrD5s5YiJFn9GJWgGddJfQdxYfw2+0MMONwFTovZGMhc98VQt3RLzVCz2JVzMIcP
lmKxc4xwCEqWq16mRmPgILSisn89KZL9/03YN4vBDIBunE26lmpNXkRACF5xYGUcHYE/MItSBzpk
k1SV/gpjbB2jH0qfC5SAs8Xe6oqzVdZ880bbBLkTtkX+GP+LFmnDRS0FgMKX82j1JZ48y1A9IOWs
7nieZCMfgFyWvX/mEVy3jkFV6yd9ULyPfNoR0U/LRVM3mXeymZveXjRxgjJxGfiMEk+LF2Y+DZSz
67sDq+UAJsXPVgjgPxTweUsb60BUSpSuSyZKEKkPBpC7R2GNpau6ai/XYAaIm42mHg132fKJ/PL9
vobNxXt5GUwgZyTHTJ15MNWZj9uuKTmXKrBw6BZ/gd6rbMbwgO8oM2bAaa1RHXLdmOE0Kzkdpwfn
4xn8nWh4/xT9bgRFioHT3Nw5s9HYbPAaO3g9JZMn4kbY8BHI44meQsZ5gkJIvfuOF9qV94ezaUf1
vqS+v7nPZ/CHIGRe1c1eT+BkOdw2OiPQAXmqvbshTkjNQT8KMh8yV5rloDzSFeUTqlxs3bAkAA8t
KgPgAL4YSZvdZXYiE6bItYUucMS50TG/wuBlUdKZCuudnc8ifAKQ30uzZVctTZdjQqIvsRkNDmAb
a7R93weHQGJdEnRyTJ3LJ/Mp4N+egxFlRYqb2uiN3WsJ8gK6qWgpMNZRRmetp0Aby7647m/tKwyx
QAJREk791vq4CZZ4Xk6CMyXHuXSoAtN7rhFYZ5fIlfMBUFIXlN3yI2BeYbGsExKZn7avj5IBRpp1
1kmQxd3rVlj0tQScoH5kgY9t52r2AAO9onJqX+KbL2Klw3gPLfVXRqT6QTcWUDdGYcZ4BeEWphfH
H+dq1/nsiC7QxisAb7EKKaMScBSWXuQOWhYSQuUoZ/BfsEuoejLZpOA0FSGCp7OcdsuCm1tkJWff
N6RH3d94RdtGfAqnrX68VW66wKOGDH9E3sx/HQaRSoDB7n+vTsf21sY4/0RpSOqmM6BAklOl/1AP
wN0j0GZwSlb1Efd8CXju+eB4nLWd5U/Lnk4UenGlNCG9XqgVR5z9sKhYHU92vaIpylQZNr0Z96HG
ZoPYudQWFQoPy2GE1NtiolD8DmAqmbxNDAEF98YMgJE4SWq/sLDs/PcRVipov/i6JlEv6YWUImj1
qcB07h6Yu0Uly46Io+Z+lf7RKzcaUC6MnRg6u9dJ1S/zKQ1l2LHnpoG752ypNFNoWkvO+knPimx7
UzU99BL3sudmKGVdHx+uCyyfpbRqHny7lRDGkrBu9rnbFxGyUAcnCu2nFO9NL+2aNZK0XQidXiWG
/nhU9BbRR2xR2cGTwrAsNs0CtsqENVtNVsAMSvhdqws/25/FjxGdMWT4W1wDahIoURXOM0W5UcBo
0wqDFhxCvm99NEzebfyqLltV4fhPfhFMiGybRp5qFRdp5z9jX9R3gvPHkuiyHlu4sD+kZY38jK6C
Ybda6x96iB56vJoiyX6PCF1NcwH4BhMmN3YiFVWka0fOk+iZDzrfYUI0dxtEHOTrMZ/a2w0DRPS8
c8zL2GqE7ILyt9nKql8HkebQHUWIGWU0scrWp6aWkSSiJrUcyvTe3h+vEtfPg/+jSvlTYfcLr1eN
hB/LA7jse9BbK9apwW2d2+lRtG+HCLgPBCCuoV8oFvC8LgGq6EOf93+m+fRbdZPXlWoXI3XJ7RHM
9K7d4b4zyogym5RwhpuUU4IgLg3tsmVg3pq1l9eJ8ndC9UQEkraUDjzAHCweT4nwB8XDBVnaKUvv
uAh4PuA98U6zsvMMVTozwHnfhRP5CY0tXVnw8POykBWtmOijHGt/mpjHvZ4Dp9F3yVXC/sNPv5Gr
GOM0R6EUwQSrjIBnR71198SbUN9NYKGGB+6rUS04Gl2TuUQAXWMludc9ockDA2RQ96IWLfiAVrKI
a9ruLZ8Wm8FUgci7Ij9gp9els3Hx4yxjwGXzMI4VkXhwmgC/LZpsGlcusFS04ZbtXpOvBadQ9M4s
MZ3nt1t0F/3dKVliXw8FVsx60RuxI70ZWSMOe54D9db+Z0xPW+x0adLZ7Sg5bCvmIgdDFv732sSY
9Dy5kqpDMLMK0gFF1Iz2CbyflDhLQtzNbhl6I+EWo0mtpvJiI/Lgb3mHYSS1jzHJHug8dClJGJsU
YNxgY9ieiAyv+GtIFKOX2fKMlAf3ZbbKj80TTax6aOenC32kwmlcL6DPmcius6Mhwqc5Ee1fn8S0
RzzezTekJCSRDK+Zk+4h3/U/asaGGJHZufjQA7Otko6uGFvaJUSMyFTsTDM8j4va+VW/Wox3SRET
DuVESVbxZ4hyQB5s7+Wal6iuJpDyyanC09GX18i7BC7J9JfdBcDLnSkmltPRdah8UHzQrbKIP7uq
QBhjON6a4jyHSbAGN5/HzWgL6rSXgMC8+p6N7THscJqMt+AFDfJOb6Qz/8ruZRWbkni/MIFvSTGx
6lRsP3KvybE92rByyPi8SBGx1jaG2rWDIg0tk07aPw/q4wPkqUDGSM2AgxxCM//z4q5SE5Zv/39H
0CAVGUlNfco+3tWNUvx1//PskmVDAB7BYlgRqRSKMhK6Kuk2Q2HRZOtEXYaFumlo1HoI4llKL4bg
GHlALPN845R5qq9AjT/+GGlkMq5EScuy6hcKaGi0IpVez1CrvXRgyl7YUk2/2RBdHYaG1AzPAe/d
UbJLERwSUSUV8pY6XiGK8ZxEqbtKE2FlbrfaNobzEixSnIQjsJKyNCJciIqerzd4L4s2V1nuRFNe
Ev0LT58I0L+FWA16/Tg6e68HYQpVBQshD+uHwofGMabzVTCmWA//5dVBEssyHakVJV+A1mShqBVJ
o6MAAxsshjykKC5xjBEIAl6ZdoWLejRwHyy59sTEmge3xJ0R+5t8Ia+ZgQGQ+0lJGHdw614T8Wdf
tUlIGExwxGJT5zMzGapeRdA7HiKyPaGAUMJcsj/f49B5871zj3cL1j4qEts6iCZLOj0gMuupPDI5
RBxUy8nLFJZHWY/U6T+ZafGdw9xEkuVDc3Q2ZCj1IurWFjqgapJ0AZ7WGgZQWUX258PdfN67vTrl
wTmOzN7FYH7cE2wfFkiL4uSDZ2JyUETwINyxVw6g1BFcyW9LzuFPETbvSPYGHyno+aAxxuJ+4odk
9SARqsYJYZ4eyItTOuf3wGj7l6b6gzumm1A+jk5FzvTb+hNZ93pqbuz1hvEfk6d5lP6rJlDQV3LG
yHuOil4JJwH97OoCp0ObByE2LejJwt3YCw16iop06oEFkLLPPcGjRYRHg1idNmCKczc76TpGx5ZQ
WVNlVPAbcXzAPqyGoOog0L74Y+FL2Az8GzU5LZOnswanASTD5nWjudP0bqbp6aInRPWW+Zxb9tLw
A87t/39Ef+d2Y3qUP95JkYWBQm6R3cx4WmQxNvr1rSjK0DFrZCswXreEQusANQ9iYAvLYMV811Zh
GhrPR3+I6TLBUviLA9N/n51zZaGbeN+qprwaTfdWFIEAf6kOn3ILtxUpXEptLsxrnwaXQb4exPWY
iuVjxVBAO1IbD8dThi/LPWoVq0gD1idywUr0Wa+d2LPzP4fe5tju7hh+NxFQgDam52Dx6lPIgbze
rv6qQGGL8StkQETe36LxV5kTVy9JJ/MqalkJJIciQK1Ys7j+XmjxaqwdnXAWKhT9FhWxCfVOsUw0
T+pkg08lS3eXpIa6mB4HUBzO8weuFNSqdmVoVR/BR2PS+xRpBGFYvjLpFjZ9psPuyosuQZsW0JJl
W59GG41BvyCWfNkAQGbCJprsL2dVv1DFEeGaZOrbyfnYLKhttR1OiDX72gdzbkwOAjDJr+0srfqo
EZZAasvi1e4h4Mg0Oaj+6jxpOnMkV4fbNusuKs9kO1wb2qlb8XfTV9m6paa5qCTG2r/SZpcpX6gU
sGXi7+o9gCrLG70gGxALEWUlWFX7La7+z+8w0DniPDta2EE88CVPp7DK4PXuatYD0/pXEYGTAEX0
ouI91w9hLEybM1n259OCCmQPMlbBwp2NWVuQU6CGQu5C65Q4ilItgSF7MdQFUluvOcyPbrUgYbxg
0eSyDrhiyulKR6i7sO3mqsfzQlf0vc9xNYU2BItByq4kET7bAPo/1wV64mdbXHiApKgryyWOL4KH
SVtCMLlN9Nrh4Dd7gNlysGMCiQuWRrvEZGF+gvReONIAS0Mvm2s7UeUQ0W49KoE3KZPUHHOxO+69
E/uqZH24iPQef9FPOEvwiqK3v3PXGq1jYwH+HJeXsCDK428Q/aw9sgSy5Ct7XAdbhApamY/IuBAz
OInBWlXxQuGIZA28zu9rSFa7oVIBT0MNssXARAUmZBcu0QKQmtiKscFQN2mxvoudxMXfPJnaFRae
uUF5lqaFozMS6DuM+ImQpFtNW+iKzsJRGqY/V7tEdgvTLcX4gyK4lEL8oLMhUrw4nr0O5MqzXsiN
aVdZ3lTAr14PYQxU8VzGubid0M8rWWcwTqI1663v30Jgc9ssMiGqsHldi/WUQ7jUppPi8XCtBGZS
j6fDH1AArMqU8iZkaiz9ZYYriUV9/sPfiY+1eTwR9Bh3iG4vC9aWxOkqbjkeDFrdoVe8ySJpxLLt
Nfs38ueVn0eay9532fnJ+TqW+zfxFfW+wvI2XGzLjcoDBFl40eGkc5ZzPit6LGecnFJ6uCSFRWcg
Qs94KJJfm5s7iUd51NiamxWgmktud2sPq9xLPiYQJ0cKwRE5HW9Rt3CaeA6oOjOwBJK6wA4PxJ0m
GlOY8m7vM1hJ0GKqrFHgzJONgRk/B35WyM6PKyFqqBm7ma6GRsmwyQt7oNpCwAItRd/4K2+6qUCz
CxwZyh20aN85a4OggWqgQWWo00AeBiSQJrVvorwUqbB7FxqZ6Tg9czGdIakQxPm2PQ44v8sdZ7ig
S3ghdRMymYbsHZ04xsCsjtC99W+R2skU8//g2eroGyj237VpIGOR/lY+UdpCHyPLaFTuKbsYV7VC
AJey5POqCQqErn8Mfmue0rYl7YbQEyGQZ9IerYPGMvlZAcb2QT1RbkxByjNWQwUCV28UuKmWPOVW
T63y7wbvoO12nYR+r/dRPQr35CwSVIIbbJaXZI+ekEcnidICkVoocL5SqO+vgMre5wLHmf8Zi+sA
Gwoyr6q9zDge5GeqXeT8vHE3zbb3bGputwRwSn69jgcw/dRMIu2K0qJEFX4RO0dQxGLPRIMBMQOM
bVhm2iwZ1Jrth8zMPDR8vK5giyco3CSJlxWyN2WkXldt0qpDDFZLQEXVPhetHPXaG7qJLcthX0Jh
Xd1JUnyUcmFzjv+l4VmjoSYW8SP9S7ldvYHmx9jeqnFnGABMqtOigVDrBwRfstw4LBWxfCZF/fNN
dG+2rSmNDeyXkei+NNXl81KyVIEgVIBiYkNMKWNeUj/rBopemQtCs+mrHToFZmpDQ8kE7a3i7FoL
0AIllKD+5hGoK7G1SAbPnPLQfT7PpL9LzuJEEH15cLoa77Aaj3KfqugF7nQ6/xMnYzm48JnKBu6A
fR9h4sFd8GNlBnJIucXdQOwGPW68YL3dIOAr3LB/IJKDBG5qedcH7kews/q8jmaDJ3Zg8G5lij/H
kjpEUtiRsFUAixzv2J+6hUt1hoY0uAO8luOF0FvFhIQP7h0SeSsSs4WNbyf/BsZwfM0ujjNxopQ7
VhvvcHRiiPPpS70SIVdE2hPxTG2qWsezGB5KUWPlofFLG/xuPpebHOAr1tr/K6Fw2whOq3IWhVSr
V0UPWpd1+eK1wBrQRkgN62DFGR4fVcSTomJAP7b6ks+2rew6OWURn2ik4yp9RrDG12oeybE39OeZ
u4EgBzq68xPmmuGknx0wqFt5S/BkO4JpJk8dpvjPIO5kByVdfixQqlMhvXaZr0MNmfZ2I72ogyRg
N2UbTNUIMfMajnC834mFW38+AZlbkFc4orFrB8+OsoKrMppk+dE+OMJVJLBNr+MLo905J2tKYrSY
ZMoZpK8cStEDhCbOKCe2hipl/cQcsno6R1GvwIwq2FXyXk4mlofb3dhKx4GJIwWW9gNJQTGzmqo1
nk/NDv0jXTUX55yXa2T4XzJ5cG9Z1FVwzATkOQawc0tdzXeDgwkmOv7ec5kzzcNOPPPGmrkJp6zc
vGi+sQecm4Bq5KppfYgxL0G3cZRo4Vl6CPJVyLBegur7vvX7rsL5+z53zj4PgcslN/s9HTLOKOJK
i8ZF4WySWpFBo6nbuW34G0Uk+IZIupCLDoY312Ka2zdiRUR8JdFCNnR/48McCpnbC6/+dLndZW7o
sMm0smDFpj71PUhXu+YU2LGf2zAk6RkLS2HuRCBpduE+XfokA+wA/FHsfaK20wbfwksBKThWUfGS
E9qAXNaNn4JPzpBHBM5NSHR7QCD5VuO3RGWM0Q+fUUK6HqkfB9enp39JRbXXspNCtnyEzDyVZC1A
ZHt/BBsh/AsXFpl16ddQ1O4URkqr46MNEj16bwoM0+pq469nPTTfcwSw2QZfoarLKPcQl4l1uvC1
8yP2qQM0h8xTLd7pLvLyWecMfMeA81qZeD/Fjii0PIE+GQTPaMjGMJ+zanONmbQZsJBwQ9FkHVh7
h8ZaoSPBExQx+l3sPgFlq+WTLjKeOHD93Rgvuaw+2vmuEQMQJKgSIByZU+fACllkUzVEGm+aJpch
lgAIkKMDQZqykpxInaGWWuULInHs0zYapoGAEh57MW2HB+bLdwuiommWZzdGm8si58oFPIb6NgET
LhHF0dqsJ4wIvNTG+wfaEHWcWZXM5Ed59o0z8mhfhrYMcMb+hzhuL10rFOe7gpBgfImJ/F0+xHsC
bA0WBcQCgcIlsa5X5uM51s7Df1TZngzP3I0X6baxFVmTSyermdloCHVYfcJ/4qCTJEC9C6D8SPVu
z6I9Csb75RmzqikBISnR6i3wp6bR6kINdzSfw8YFEa08kmj5RB57H6kvRdtuH7MfAI0HkrsMkRyD
rrk4NUSLPSv3sWEKNaUqa0SZGqlCSVy/4cTf9qjEclPlfrq3l19YJGK7e3LNdk8/nFNhx7SnQUHt
C9uLDl1ppZ2dQc9XXTBbSoufdTlz19B3Ky4T58bM07BcsKHdn1hlDXLjbbZpA9KIIjAjkCkr7gi+
U7qJ8sbeBDC29wsekSc+RVpZH49l98S/9mri/n7ghXX64wriMjdAnFsjzIqaFcg687ubaRVJLhJf
+iC3az6KZet6ngrj5nkCgdY0WfRnPyAoZa9viIH6S2VWVlIM9hgKUx81BN5E+vAaSTo+Y/SMydm2
Fgz1iYfB0iOox5KgQTlpI9BNHhy28aj3Kdj00ouMp/hDYkRb4M8Pw6whRaNItGUvtWYgjWw9MbFI
YD9dznkFUkFWG4fmv4BZYI352pF5Y4Ch7DftPByvB/vMqnZXHxMVVv1D8TXhhVYH2LV1dJrA1etH
npbWrpyR6Bd8xZJfHQm7Fa2qNpp9B4djYhloFrRoEDj3Cx6JjfGahA0ZBbjEJFMpQMsgV3qM88Zb
7LglskIO0cBdXaKHk/0JuRyTRb5M4QBuWu4LLnFbRYqReRwu7UDQjyRDJRTLg/Z4YiMGHfaBerge
6nGxtxny2ArnkGAuY82x9alDv5plb1sLT5j7OvZDjse3NCceb5rpapUhFMgVN3ANsO7BciXm+M/+
nHzDgq0zg7mfPE7LzEUn3f6nH1FXLQoya1kFeAzlNE6M5yEqbgBZsmMTbyft8V7G57yuW43mAGRC
NgGS1rqpZs/fP5DGrhzq0CaGptXsKa0CBPRKoncxhVZAflyBjlDMVppUP2kiWZbSF2O+cOkUdQHU
ceb8wyno3KKoHzkUAoAaxu0ISjijVcrBuopmLtFsM51eEt56TGUksS13fz9FSBB6eixlzGwCD78v
fKsdGHdSGgZHVcIE8poSmTsiT5tPwzfwZBNTs1+tfogqrVfqNi8ucjAt4aCeu/HKMt+kdytM++48
x5L3Mghih3Jr4cM26HrBZfxO6E7ygSs532GwFT/4oymI1pNIGt25cLMpdDULrIHQoSSs4l0AcQJJ
jVG3aEKjYT6YP5d/+ZOYU/PCZOQogG0m9N7gOePWtCTaT0cA1tnucbv/50xRaSVMKCMwMlHg+AIG
9SB0WDOjrNsg5rE5iKtj2Q3gu9f/MmBLj9LfcJbarRbYIUrhNl6e8JX2peuHTm0CwlV6hJ2BlIOD
ILhRS4kRiavbCBo29Ypt+nfm9xxfJzeX/sauQiklWo0oIggjisByJeymoGy4biVCPTVbvyThrSmY
g3PGqu6zQEUXUvnXiK9aEq46rKt7dIkH+dbXmaPbcWKC2ZEPmtIFm6hqvaErzUzZt64XaBq3UNzz
Bc1KosljrKmm+4nGq2gldu3WRNpRhOdOzpQpeITm+RjSXtxVMis+USv2xx9gShL50bqqMjICxx4w
gVF4excF8iNGXenb7zMeODMphMvjBMvJZ8etSneNGcnPIl+HYCq53SDlJdWvaN/7wxlbgaqL3M8u
XhsJJeH0WpoyMtQ91FClngdGHhx8zdqezM+FUzNA0pUfyWjaymTvibL8GDjGDeTvqbRgxXKvTNWb
rbLoKPhiHLiRfd3fq3oc4td4iOV6ACY+BN0+1264nq8uApjjcf5k4wApFbLEixM2T+jAuwKfWdPd
reIzsz6gSJ4WTCHwmZoW9KWswfFLLzHtK4d8q9s/xKQR/Kgc/LsxS9wzTtPISF8CvnkSXk/Ecnob
MKEIFD6mrNEqjqbnfFk2nGm6t1r0C0hcnUKWJpOFrlJJ8OWGEGL8W9jF2wiFCvKF6GcSVtyNWjZu
yF+ecLfdh8HXVtDR4LWbNblYpRIeUCL9sFTDLP9Bsb6B+WReuGa6iYEMhemKqaio+EaLYXhl/a8+
U18Jn+VRys71tZbRXEqVqxOAyFsjfqh9HuUKVZg+/HmQh8M0igk+HHAaJ62tD5rFD5ohvytcfuDv
FNTNNVKgWBYYB50ANRE1A9X40czGyKGAaLbsYvDfrXS2yjR4m5G2y5Rl9wNLETq3kuSFRIs+yPrJ
6tcsKgRyWBERri9vbW1kRxpjEmtTpCWyaob2CKxuPmbkEuUXdMsD1QwnfkcugbAZORBwkX6vOKyH
07BXSQFgtOPwskMbz8sFlthWYfuoffoD/wA/xvXUVE+OgIkeP+2AVvCmKnUgMUggNGwLEwIvGxqs
yaw/u0gjWa4wijfTbU1V1Nb/CvnPvp/x8nM1FQTN8/nIqB1Wq2g/w9UQyR5Cn/7ZSij42yCqTRtk
qX6N2cOWftfwLBXcivWrWj3URqBaIQhX8l46u06uo73wCXToNGzSyojLhNLrgJL5uN2GkdNq3ox6
BTd5PZ7X8l6KQgCH1A33Wm8Yl3g7ba4lwgHpe6hPLp0OVF8Vnc0B8wM7u7lHU3OUwcHFzofODZV2
/T9sv2Wq1huBGauiumC1FOFaaPHXu+11nlwRh+dmBOKuYdGysex/aXaHpm3kLxP6aimede3q47I6
ZbWzJBz9mmDuLL6U34AStpO7QqRv6Fhs8j5OJdwvdhVSe55hb8CHbsFytUGJ2elxHb3A9VgGYpG+
3vtmj8rBubu9cDX4PSPGO5Q0nIR2+aquzE/ka9nuhk0dBFUT4wpVvG41He7VA49+FJjREafP28m+
lYm5dHmQS7V5Lpvy8pI8AaIRBqlZoapTUrAtifKODc4EmevsVrCVbpTSi+knJXqvND47XRzsZ1Y1
pASlWLSstrcLbPbrJmExyXedHN4YXduJv7yz5XzLXnK6ooYch/dCXPDI4/cfTeKJUfsaRQpRlUJt
sX1nj/v4RzqWDObv7s4unaxxC8N/YX+7Flqjwzw3w9boZLXhOwDXQE3b0pil0OxfQlBn+Q/HHLcR
o8+EBiI2Q2o5HC5V4QQUK2FqA4rEX8Y1WcSPYFuhzr5bbMCUW1cQuvpXnO4wn7qZE4+LJjJmRWl8
rR2w+zu0DQO0UE6KTydEzZDyyQoA214U9ggKeAuFfIi0gOzNpdhfNl3S92kLKYUYQL0BmGTexC/z
a9l7XHCSE9bIa3xPQkXmmgV0BFyKfz3kCt3HBPJphcsl6lVaG2usugowUrwbY6d2x7AF0r8MFQiN
MRw61itaXk37iBbeFYvqWgUI4iSqWFP05Xfp6Kxj3bVIUF4f+NnLc8MoWXh5TuzhVlOSybABMHuK
rRWMiWkVKcjgf7h4/mMBSbDEACQgYAV4bNNkf2M4gcTaH1K4Ho3X8bSrcaarxv01J1RgjOQf8SA+
kEK9MsaMedDqpWQ8vBymmrB7qH//JsPlyGTha9h3r/HPhrKAoa+kbbaCJrB0OIZlXKLAXOQQzpdL
aMcoGhGylpc4/jICH+6L3gJGtakw4dVS9tkODdV+ibelNxHgeP1Xflf/rwbFwRKQejQxM9nZzyOT
APLW1YiD8uEe43WhYdxc0mjapOBMbk57EvlsXTJG/wFgW6Q8yJs/jLxA65nW+RDio9GzqNntVw6y
tM3I1ZoiVtwSpYl+cav+96hD+ZuPM4zj/zgk485GhaWyRgmPUUIxSCgYTC6nzhsH10I3UnOesv0R
0Nt5GZfh0JufDNFZBhP3DoWCrqoshc6nW5FkOoAo7osId4fBP7Nf6G+u7xCS3l1ajoJngzk7I137
weUVJxoSdEnMOyDQPX+e+dHJKAMAbjEDqRSxm0jHX6UNjcd1IwkI06x6ZTxuX/CNUpB/61hFFrD5
qI2X/sxh+Pmxo+kimVCyIc2npsIWqHhcQxoMrynl0A8VlzGKPQ/XVqTNubLgVGHwF9jwsKzJbw+A
UDqzc+WxaMv44FcwskF4lRzpxZsO15L1Q0HL+wq3Wm9x800I5pLqJvYHZqOiQODhZ/qkc0jS0zkS
l8kuADpgMc36Yu5I4izBGPJNjWdMSzyE6/z5SSTbIEVgd8xTCNBTdeQsuLAXntidVdHwoFIZnzTq
WbyqLreaIUVQJ3/Qr4MpdUq7mNPgXg8FkJhRdS/NxSdoV5Zcg8HlS6r+fO6jMuSdUTN8qEfydKru
73i9e9NdR7BlnxgsjfaXNn9/U/Xjz9UHvxIri2Vetp8XdMqbmC5+doyjtWc2I6rpEVTutzM4kmHg
NdA1NMBZEtrKht6hrqlniORrAam9If6C0VCm3/46YJkNUJ0SsVAv/dERbN8ss4p0tWc/ZmTveTpQ
n0fswc7sifc5Axc5AWVFBfXNmv92MbRpq5jIrZ52nv9EZzUpUTbSII31WuxChy3a8lKO+eVsu8BA
GLZ27MSPB4hm1SrPUUinZWDef/toPvzr488+c54LSwl0+EDlIY5w9D53JL9eXJyBY3wgNbxEnu/u
Tu6H4fH7dwSpYvM9E/9fBFdTYs0Lnxv8oOFX2VDGdFJEwJb/nTNL8GEjfLBWz90VZ7jngZ9jjfhj
tbazt9ImrKuHLkoThXgTEy4sn0oBO4ffgXvzn5XBQf+iJ8Z40D85tnfq3ThmEB3ANEpkrJBrhDQC
Rl6gxlwnERanmakQ+9DT43BPnzoOMXFUq8NyWZBKZOlTovMMW3yGQHe0+AaNq17x01a3YvKfqdRQ
s8EXEJ9XefsMavtqkW8fzguzEyqDaDWqbQ4OEyQUpcxjlBF/7rmDcPRKnjQZIWHNAKuhrh++qcf/
lEhnzNmy2sIS/6xEKMhoXyi5/+1dEswXzpcM/vRGTYl7+nIWJq1oakj0yNk9ZcqYXlg8KdsS4M9e
nVP9O3OxRR1QUyApslLq5Jzehzj5pm6Euqqsc1HECZSVZ+0TPy5Tj6EF5YtgmFcJY7/RlKWUEE19
zmIc1gGIXoO/wzHIA/rLbmjVUqMJhnihWgnQOvb2D5kX8lLdE8hKPQRiY55MN9CZN50qkaKRnzrG
6XU6mFobQ0Ei9TDrbum7COaKsXv6NB38b+63MjQjBDAikqsYepiD2jVaqZaWcob7he2Xjs2bC9Tk
g7/zTNYbpLkvvbDfTo6RZ9EYBX0AYImKH8zkBkAeCgzFtMCgy5yFmY7AyMGEF0AVUYpzz2F+5/zH
fUepEmyecjJKC4nndiIIfvNqSgseTUtiSJq88qi0+RXuhOdFm9Xfi2aj8jx7qEPIgPJDjattgVnx
+mFI7fTKpCEpMIhVK/cE4BnAIT7kAj4VEnE9ey6vW1M3vZ05idG2n08m41B36ZvscE8yNrRFi/ph
yJVU/Y5dFXkD76VD4kST7ahGwX02QTQkudxWW1drAnn/FwKj9Bf7//luZT4bQOLBG7wjei7MmJCg
Z/8Yq3XJbZU5T8M3A4oAJq/6IXfyewz6aDo3Cp3sc/chQbV4A8cUTKhfTVj+fkkLUt0WPE+UPIJa
luk9NZyEJ455/6QWnS2mslY8O5ZVqaGuWNBAgLpa8R7NS04G2iwIzjFmv9Iu0fnzTydBUSGRF90G
ZlbHVSPUJiNIjoaK9Plr9hcP6uxU7Kd6xT8hqc3xQMw5YCJmm7gT/h1VrsZHh4I4R4a6Hq5nGhlm
X0QIKfk9QzpDvyHDVbV8B6YsL0BrvWxGcCH9qa6t7E9ZzToMyGkdfDtfDINpZw3KZc8R1SV5R/RS
dvrvv5PdPjmKrVVjQqN/MoCbGI+8DfPbUan8VbCaxKMBzZJoYN3ZvINuEd7+0Up0v8aPBmdXaVz+
edXV5B31lLSSOqnFGF4pUVGbXBsY1TIsWLUlbf13wa8tTcVjP409AKX9HLxA6Nhb8C4aNEn6c49Z
eMmAqLGNxVOJSTlVxYdCV+ywZLsxXpOgD9lGRYmp75U0qAze7w+EaRd4PFSR4hBxq2pLYScMMWki
sJsCcaE+vtQTvKlzX+a9c8kIVuyDniKul+2rM8gcdfsNcfu19d/g3sE1BAA4KtIERHI2el4TiwyX
/uuXk/KvFJghVK7WxceCscxtN4TGWyIcgEtR4ZV0kWOgMXBVH/I8dDWSePajaBSGYRbEPVakCoLe
dYl8PGpRJ7+YscHPlV6/iOZuy58ldLaW3kz7+1scuXfvOBnKpbqNZ1SwKKK/D8S+pafjdQ+6Ew5M
5M1ewBBp29FSau9S1JYuzvB+IeL6+NVp87IK0c3HLc9k7xWhDR8GXYUSs2uN05S8H7BDqyMLaOeV
3UsR8ad07OCqV/WzaKLIq7LNwBuVQF3fXvvUV8NoacEYtEXOTFzIQjjwLqYuMpPnrFnSPxl2EM1h
Ge2ZHKrIBVRkhL57OjycxCl1VX9nzKbtnGu++HGPnEWss7i4RAojLzqc41USURAaQnkMWlpFq4YA
gcAIDGmELE5qzCe6CXy4CV2PyeIkngLMxHommAGP9MoGEF+wKQPcjiK+r61kiGriR69dqmIAObO4
VBRYqNAysjITaiPzAFCJ/BpA/zLxJ7rWL1huhZg42/l96hN35lNdLgsmN4ZvX72r1wuTQkVfvRp/
wij7WRXFwZ31wRBH7KcjOktoY0NxrW1flw8QbzY60rAdwCNBaOwtnMtyjSDiMomNqN1+lNaGUo9u
T3HobkmSEYVA973HaTh6gZ1yHZ1RtcM9t5wedX0bDD7R5n1J30go3pHDd5937b/FiOT2xxXT5ppX
6w8TD3vvz/6/JErDYpii8KpUHutvbM2M/KunTnYgDcz43b7GSUl9TzBzL66wq0IV3i15B+T8t2PC
yAP5hDDofmsovwu/tR5q71Dfre6r69+bEsuAIFpSc5heADX/TfJFoLaCUyFIybZlWmXoueGIapWg
THXxh3JKfAj6mIIeeuEjvhxMyWcAWwfVLqCDvTyqdIbHk2//zCjphjUldolbxOxXhFt0PoRvPFbr
i621SPaIb566jjpNIQvoJDNUKiwMTrzRTHtf0AbikRdPLaKFTZcUK+HjNf9iaCzATEtiD7T4gA1r
IopqAL41gvO6xEz4DsEqu1IFkIHsJhXNmtLivrJIgORmBhqk72wNDXRpBX3TV8QgKZ+BDD9/3T3d
aLwXWSsJeDc06IfPLigB6qd7G/bOxHB9yAjsklG0/AhIFuUHgWjn2k/+nthzG7ZPtuF70FtAtXZi
knzVqCN43og2BmfrK25nFhT4tdD9gBzwRr424/eLa1hdL+99ywiq9IoK//mSPra4gma1q15VyjgH
iP1Bwer8oorrqek5M2Et5wr4JmvmzsNlXEJ5KqvMiC+cfZsW9rjRSS467jtDZ7Mcl8Gd3ZVB/rz0
aHlNvSoQIhxXw8d936SvtkGmBHp+PHdd+WFjgbp9WYXg1K89GyC3A5rLgWRGg/Fep95xUyNweFqx
XoCvVxMVq9W2O2QC2z0aC+JjKIKB53HWUOt6pFk3qUS1eYxmQOn46DBGyvJxtgkjcSK5CeI4UdXf
BNFF3Zwd2CssvDN5bYwkyUtXswDrIxl+kT+sACJV+OM7hwYuHTbACzpiwOy3QDcplCxrtEJtEz+1
r0aaBMXkO9iuE76X1frXBVKT0uy2LLvbxHDFMdsj1VYLiumA5XP3a2MWNdW5jtrL1KfHEz5+ziUx
jg3zH6cq5avZr8K3ak2sj7C5e5KqOCO2zfnxQ+uWIW6fUiY3fxF+3BTLP1z76cpd275BdQ56y0ZK
2D0XOke5xtUtv3Xwc0dnyp89Gkn/1I5SYUPjGNmQtjXikjUZYwn90dc7U310CNmKzE7PyutjZSee
W8V99Vg2G+RLAN2dh+5GjmEp7pDN5734c+nNwVh35eNMAGgzZYolYfbSamGqTVQDrRzeFUS1djNM
Cbq7C9QXHLiW7zBDkXmbv0OzSugT9p4zOSAFDbvm6vaEGRnkrBwUL+tL6N7+cN0kMpu2tYXG9c6p
pvsi0mRBiOgFahfT0d0PkEYZP0yk3nts5v62VUXO1vuSWAoF2LwIDFw1Vkpqjus2QpTY/r0WYpSo
yQPH6LjbmulvRA1Gg9olONziHFkH/W9hapsxa5J+DdFFUeewWbhkqkUeG7sdrFARYOqLU3IZ+BWN
cbRTS82ZLSwxp3umS6ierflFGycplPiNhUnb05YA3wRTwGxrt0+8KjIjMQd6/uiLO4RmNHTJB8Iq
iure9pIExvQ2yAV/o2aJOMTtH8xUlmp5YfzPhQS4cwqWmMU3CMntpPO12jFW1giKlLl3ZmteHrZ0
7KDCMeLKVbt8jwDo1HzdImS5w+KmK+y4ZMxHsS2RTbdWLSKr9sdY7CTr4qKbpGFd4Vf21o5YVYAy
6l7NMvKM1XwFs90E8aBBYERhD2LUUv3ttT1SiHNKBbN6a/MkGIK2H9/CYNnD6wg3W7tKoJJp41Hw
9O/CGqr+jmROkqaP60SWnXbVzjFdDtmbO9scXC942empHvfe0hm2vVN3l8gUY01HdnuxREhBwkpU
O8Q9q7O31I5UMJ7Xzdf8IH94s3DzlLxlSgEWHBwP0tV+ycMoQCaDxt1WmBhQSZ/5keoYy8rLDHj7
IujeHheBNnbl9Yj58c/QEDVeodMVcK+kb9mN2xCF6htdbvFqk3wE5vR4wLUntWvOZSrIyxkIg0jv
lfk7YtvkSTwwqXccfuoH2XDwIceer4dznTaYl6aBrht5shmqyYNoRbQTloriGDyGQ7yDN+HPZ1v8
BiEhtGvTdj4jkngXbz9bMlza81pzY9iNzmIE6r2oUBXb2tG80g2N+JbgmB8lGTFuxWdkYsTEPxbJ
Z33ZdYNSpKM1acTFZbTqgo6hoRTHlwyY6HjPqMAZM9fiUz+W+un8XVAPACf7KnUOVQZ91Q/hsf/7
FwWsRaaayWA/247uPlKIvLMT9oV2+DOXV5fvqmtzGcTBWQRLXn5bj1ADNp0PbAIMyTkHlRwdY65T
QUIwxpa+bB4gwDaPliMVHj1VRHOgrq07kwewPAG6SgAaA1QQuAfxIcpwFfuEVklZeCMh+CqWQftU
vqCQDRRX/qKgwO0M41wrF8xzD17jRpNkRrtcCMuX3ttwi+H4DFNWBsGxAH9PjQGK57YPaHxVgBiN
wLGdgXMSME0hd69o46aVzML9poUoXVoGxamv54UuEase7flpswlS3mJ/Naz7DMHnk3vCPbHw6xD8
PBxc3CTVC6xhayrgb3Wru7zCezquWzOZXwkdBj3Gup3D4Uun2p3vA8x9H2IgjTB58WtjL4mpyy6F
gE1tL8Epr0sN6akQ/Rmd6qKohnC32+RDlpiw92F/aehaBcpXb7D+4njPWMY3IWWxsUqK7nBo03ht
p60frPt093W+jWnWMp8uY0iHHcwzmHHk8GO4msZVo16k768shsG8P5y/dzwZmhgGoZrd5F/Q91/N
UU4CTrr3tjHplhLZdDPKReXtpoW+7ho57GLpBzPluThpDF4ROD63hwMK1TdkDGEj5XZjbdRxEQJS
BZ94IodLyDJLVG+ZBEd2I268MBxSH19UQpSg7N8IxNojVaBKFkfGa6LXSsxBZ7HP269Eba+QdZgi
wm04/xG8MjpH6ufbqFrRgDTaG/AOOxVl7uz2dch3ZUrhIdrN9OPJJj5wGlOEdMWdX4WBPvSts1mh
E5vb3e/+KRNaqpq30/F/TsY8lQB/jUijY0wyPLc+ww+0gjv9Jay0+4KOB+Z2b7eBRPKS2+uhX/jp
i1dNsfncxEfv/OWoj7UgjZDRRQs0BI4y0HCqd54vUGtPT6Lh9KH91S/y2oU8okAXhWGF17kBx8Sl
HJCVKPhtb2W5JSWJBgNq2+jtfysTkhDCmsRDcuOjGzTjzyumF8hDKtVFlK+G+OKrg8JBV6tfwpQf
KCMSZxo3F+9X4Lx937mgiAEVk4NI2gbHtPEt1XiAMv4aBnJBxu1twVctNRiRWqGP+eM3DnZNx7Jv
ViU+2vViGRVejdP+YoflL3ZqSJBuRr62a638CDRFQ7REHccKB/OJTV25oO2kTAlbf/EvSuSDltNV
vqvKWGzH5VSKTjLXtWu3928XbIe5LNsBgOBameTyBkfM3Sh2m1o+n0Zd3vpFPna9THSncgO6MKUT
/sOP4XIN8LDH4cIMTrbeQeoCniTd9dgSTUGEqURR756UFu/vggF1vhQQYpi3LUe7moXRTxR0jOUW
QqOfU28D2uf6Edad24mOaMfeFfEnQwvp/TEObPPY4oEp8Y7lDrf4H82D5CSIWdJFUrqFD+GRfSkE
loJBQGVxIO44VhCRYwWefkZgt13bUF5P3P/tnVdYRxsivia1si0NLRYV555v0QgC0S0RVvJyFNLQ
bxcggHIHt6kXX/FyfVUvBf/zMwyZMunMpKTD7SdTpgDymCvfYCB9OEaGYA+EeAWZNdQWl4lZl00i
yC2oIE6mjshuw3Bnk9UXGiT3/XCCMTxxSnF3/ch5N0mb8D26+EGU0N0waneQfBZVf5JG9dxLe4DT
rV6nY/dzB7xCuyOJ7lSvJ9sfezhNc0+fYQThBuickR9VR5Kcgxdl4Pqh+8JVTLkAMmQuwvrslUwO
d4PwvFTpJ6pyEDX+hD4l0CTKFdbtgLLKFHxpavXTp+XcyPPb+FzdOe129sv6E0Iydg3Ptm4DuHfU
faXetN/BrvhfQqFgCoEXFkJj0iUussODS4l8nuWMlbiKPHMyZJKioAejd/djgKGrbKc7uy3QOBuT
VkFuKjQn+6EC5B1/UzlKl7CyK9JYxS3caxvtmy8CF1JLdQ5NHZtsTx6Sw1kiRpZmOzFAkr68vxEg
Om/PciDb18Di/qBg8r36tR7Sqs5Fe13sZLtAtYU1qYdqMPIMDqIPqtrFgakWTM/vvIcCRNJbJUZj
+RPZMt4f006mvMu9NfJxgiti0fvEAHONkutNTCy1l/2PzlYU02iksmu9CwqmUGGGtjSZjuDH3yqO
3JSW45aoGtaGnJYUsMXoniDVd1Xy/JcOfCXFkp1hs2YnEXUDIZjwUxBmibWVFvmM53HVc0VO6rUa
SmZ49TVOf8SBjVJVFzsx2pPWnm1StbNWC2xg/269tMPFtp83cM7V30U6Iej+I8a5c3isgpF8HPfn
JLli0yZ6efCbAMzb1d9EuTMSfn15lNLcV2c6I+P7bd3uqjGhDTFsADFEYG919JXwDswEHAyBBiam
VBKK4u9khJQVpM2SyQPDx0Tq5XGWI8MkBBLWpqb+ET5610VCJ6aN8kqJTkR3nNcQ7mPz3Za7yt+m
5U5ysl3/AF/3fvMY4ESTZC6kHe5sRDV2l0hRA7FbkgsAzTUslaJtTjZhaqapZabeaiEjnu7UVy5i
9YBgGrsDxgD1eERky5a1rKoeYj+94EUEaCUSWu+6uYlFs1DF7o7mMjMxSUYJDBrz76CfySdgKLGi
E0sZ0Ldkccg+ADHdB9i/vEKRDuc9J/N8eSOmLOlyq7FuIgB/KGElzlrQfu9XJtlnwvENxNbIZODS
jLOZzDesxqyVeBXT6R7cR9nIzfjnsbjV1V5rDHUHXsoWY13BN3VumOXl4x/YyciaUSATDJhCBFvD
Rh4I/j3ETC+lzlhfqxSUIAsY34UzvENtXhHagCMJXFiQ++MZVhYH06q8/iGI3qLv39D2XBHX93oe
c9h9gjvoD6iXs/Y+96Qufzm1Djfjp77lMkWPDJFTzRHiE/1pktgYEFlUKGwH695Qu5OrCmpswjB5
hZnhUkDOfI5THj6kEWzpN2kQfztUM4RzttdbVJvWmqO3TRih84V6vyTmmm4McKFl4aIkm5b9yC4t
iHRcCfnpV+DqL9CDes7aER0RUwtN/TvMs7ukIBNJEGI126BjTFOgo8gkvWMYp+DcsTYXupp9BXV1
ykAKGcJKn3stMXhmDHo2CC8vMUfORBa2leDDVqfSch2bJC1iJl3m9xOssklvhGuSsjV32uYhchMR
GPbrfdMmleZwM53qTXpZAACzhyxHFI/RiV8voO4dbilT4idwTAo+aoScLd9ZG+yBe6BbBo8lo8wP
vLU7Ln/qN5ybzH7O92szS9qcWP5qVRaaFrQIRHizzBW9meLFNtGZ+rSEd6Cih0SpiPupYcztHJju
R7bJRWrBXZgw0+sjpJ89OovpOCbJTa62KYuGsf9oqdhSxlQqd6882NCi83K8KJ6nVeWD/E1bRS0C
Zz4yTY6vvbZlppPZZ2fBabJhFRPzH55f/HHCC1jjgVBefqGXWKscOG/I+sA2+uKUoMPFm9Rn92q9
SsF8tZQOvep4QPG3a0yIvUMUZ3y0qY1MlHXIcb8fDdJr9BzzbJgMSt/mbawuDzfE1Qliu3Pgbewq
5DfdC5ZFyY3cisCjQXMH+q4YoF1bU29vvc8AWFGZJ5gAJHiw+UIhsvfmIdE/VLy0ewcc8G7TffmZ
ku1+7zbhM9i3WCmvbWwqI3wkhBwrnHBNESZ/xIsdO1jqx5lWCa6jUK/NRE5xXPSJhrETCwLY5M9J
ALJJ/MglivYugi02KVZHtXgFjJFrXME9e8CoAnc/DjkgYQvUQNfbp9ZmyVLqsGOT3gH3e77+K1Hw
KF0bs1/8UipLdsiuRnnfRcxWYSsW+3woWswGiZsFjSomymILE/qEDFa+q5ApjF1zQv65r91yDT9e
lW034d1g77WGUZ05QL5V1AUcUOaJhIq9QYgUJORVIlsu/DBkgfi1RxS1/kTu7oQl072gYScdn6G1
ixtHbKUtnvuWdqeJPHx49Li84sAmIk3HVegPPQlt/wAlBeQ0BQisVI6ZEV+Ab0oQ1k66YVd/tY2i
/r/l0RrPJRcCzYLYcMBX+PVQg+h+EPVwVIomUbzl4MfYvhOmGk465WNRMLdu0GblJNZ0+yPxZn1A
XILro1X8v5lqgcRu8pKNLPg7Gn50maoI9FNRPXyg+vbHsVoZaKEVZD3KJHLdq+pQIKXZuU1l54EQ
27paTa5j91YDg3sZQjvX45laAwyXJOpFkNBsMsSCiND52v2kq40lub1cyD8aGTiG4/HgB9u5TN0E
mbwEtTzHAuISPDCOHBfAx7HI8jIhgkH+A6OpszEMB0IOivTWAYZl1U8COj8Cqy1QuEy8PovFguM8
aDwgWkk8ob1zmrA74aWqMy3aH/hXxdoDjhq9RZ7xTK33BEaz1gRqkEc0verMtZ9dNcHnkOTzvLPN
/d3xW47FW2/ZSt5M3rESRuYjpgjhxoO+xkESA3nTZ8FZRl3KTd09GQIs3jLhG7dEUwNuiZ7Ftvy3
Mdmh0GK7iOpY4Z7CP1I+S79dLBDMT9VJD1UxCi59Cel7P0I2Zv1qk4sy/ouVR+EnvSgqqS69KsV6
gId8uo9CVIV9EshLWwzOtYcNjOGVqDAiJG/w/FRuymUTmtRnxM00iAxMo4vEAQtPp7SqV5U+uXxv
YtwiD/mOx1AoEcj4M/S6LICU4hRfvBYydOvPIlBg+99+wwpdhmJaHodxzPtgjNJ+LelXXYpGPFcc
4PVVvhJpSvP3i8EfOurAZ53IbEtla9q1HbqUcKaSVt7HzUSwmnMsYne5TxHaffECMfBH+3K0CA9T
hBiqlF6P2c521OK3HR1dfxBaOUM3KOfEmfVhB1+9hhKNCZlcxX+nfrQfam6cvH0T9OgQAIXllMm+
Wz4/djv6Pk7/86viAQKSuHjctYQ3fBhlypmuUPyOY0m2J953t6AJmgDBBq9cTw8Bct5bqyKaHlY1
4/kfTYMTY+2NJfyXhRs7AnWtbaVBHE1I+rVAGKWrz+ruK/1dKrvsq4PwZ5J5o8G9rsHChIYQcvOg
82yg46h5vh5ScE9oFvWu2zO1LegFrsy34euUejOQVeL/K6jnme1vvC+Tt91xlLRY7fYxP5ns8BJs
59oNMGOcdUVjCgpW/p7x3h936ppbDXnlFTFIRivhXKzA1Cf5j4p10iaHeciZgyeCopt7epA+xJtU
Zinzvw/7bFYRpMSbhPwGYzXl9DU2w5mjkJvaLjvcyztPFJBDv1Vze/fODXrMHZGvz2AbiKt5KS6g
X9hdwjzRlFEHiIKXVTUrY+tHhgla8holR2Ansz8VtnWPWGfsMtxn57z1C2o6xh0tZ5MpfnviU0Xm
jEFZ2AkG8iQr8eLkLdLQr+smtuuSySkqkswdte4pzoJHgMWEeDDtGwZCekY6e+wzyfP64rAhTZ5i
WjKCg3iDb3OVzvsB+WW0JdZi4EdyqI9DLEFVJ8nlPNuaDDoJnlYA6ri7dRpgHAMBosxztBInou5D
UV0BeQ4iVVjA+s4wUFda5Ge2mP1v88/EwFAJOwd988XNG1aDX9L/pgdDk/aToi9WplBl2ksNNXyN
kRASH8MDVNg9uq7VLX65rifCKMZqoWrnRciA3uuPw/ki30OXoTUzwAZKIzEgiRoJJYrhfkDnk8eb
PiIJwLSBPdP4BGSgKViOHcJHbgr+fwpboReAm9FPy/3cPzvO+FK2h7rJGu5+/LlA4Byd+a08CuCN
b2QW8QBGQoSqhp6B29iwfB2dYr1GQhh6hbQwdbLZh1HvSQwjmIWuCXYLGCaT0l+qBYypGrF2QW0d
jygI3uS8KcqmniYmgl/UONlZ2iSsUN0XhVbmPfKZIBl2zB0wYOvRFwCFVKMRHEgX+GePVcj2qw1w
4fuNmh1PdcbZwvpps6hAUiaZxYmFtzBPY+R5iHqy54ZNZOgvOA7JnHSAGsrqJ5pGlvyNqhi7cYis
LHhmhOXGZjRhwlVqhKUG+liRADkWB/kl2gpBR1qgqlmsy1ELeWTrj+40LTR8l86EROMJ1zkNEt1n
6VL5JUhttXQ56nRIO/thehhGXX54+YqdxwQvGHUi3J3ObCMgzkmyY+UGahYdSWGYlqqTb8OSQCbc
gJ3cUqzb7qqliCZKwfePgq2mouGHt109RjkNM+FEKEl6sZSMhjP6VQESHJK+cmoerFP/6U8975YZ
u7Qstdu8h/nRyMwxi9//I+ft3Q+3qCqojcnSIL0aaNloAk/MEK3pf4TRaKu2WnGkkcJNqVmklzZK
qSwqGIGAyVrD4vMEXFWsLWTl0h1e8JRe9ogVFSPIHxaVuST37ixE07SkSk1mqiiIJFcd4tH6nwHn
lMzs5QDEcndUHBo3l1D2EJ9nYdE02AkO8Wtc/SpbP1/W0iVzYNm9ddJ6m0Xp9rKjoiA/k2KsOycL
9o0utoSVj1T5pyUv5wdSDI3UGENRwmLI+ewm52hw/QAufPyCZ7+Iiimc1NIQCsAXxb2+NJkC+B0Y
2XIuWgghHAK68jnrbWLn9u1sZGS3lx8Vxpq8d6SUm59f/cYTaIVgvtizgMHnkfUHB3FAEgSS6LNf
Vnwt3DTvQOdawySk/7Cg/f5ERfskhugmDvPNycNkqVYH2LEqrW6umeQiLIMrsFIlULm8eRkFersx
7htbt+KwnSNWTmzk6ZzJQGTYoHtFl/fIPV5HNa7ORU/9DhKza+QuPeGPG9dPRh/r2MqzSTxzeftg
4EP+RQkiDVWi2wv/9WZ42Sq/3xyzhzDjc0ogJ2/ruG16TOc6btzSqPyGJDenx260q4G3LBTLnm5i
zCj0Dlb3wK1ZBJBZKPVv8Bg/5aliFd6F5X2x2nW9xDwjt0KIkVbXTiBy7enEuqSDWPw3T4/1E9fT
9reEu28aofJJrLSXdy+emaD8uYUW88rmXO8E3wp6uK+BFOgwVamBzCC304aWKVRAUoLdzaR+qlEG
jt3d515h7tRyJapvbhy2rjSsa0VYmATS6y9m5u4eVUDfKmc3M5UhzAs4/qUW/npF3kPUinzGayBV
XMzHiqMOi1Vm43RO2aberTSUxaF/FkkmMTveDhbaNg8Vk0+uzbXC7Ovh+P1S9YrgOUKqACh0M6h7
RNQzXD4cXjaufPMUDpfbejnjpwqfDoea87lRuWoPJ0IkzGvpyboCT1Ue4Hy8gKa7omE/SaFZcpbm
2OpbwTKaeHhUJQw/ebXzSpoD7JIpIURZne+d5gcDcGar18xExx0yWarYZCT4agx6FcQesGRlRwWr
5VKQHBDV84N9gD9a7ndwBVrTSQsg2gm32qjO3aLpWlzqcOJwpz9hvrdfJid5VTeHx8lpHNGL8o6+
reVnSFSSY7Ic3HzMlMjbR16Whmo7vzxHMKI9gjLM3M03z9aTDj3UI88lNToovyv8iQVqUb5RccJb
iRR8LmtSMYwLMZMjVULv/Zkpssb1Z0aWZasMN1+B/aFhXJUHEL1eqctM/PAvBc+/MeVtleC7Hn6K
j5eXtAABT27o3v68wGAExeWkPSOZ58mNMDK6pDmQKywl0bcz+RWP42fF43/XembmMGEWVncxk84w
NiJbfAY8V+PmzTts1PXyDsPmCVj7FbngCwCVyONKPqAf22HpBd/6XeXJOf05PG1MJhGT5FhN0wh6
jj8hwzb3oNLnBQVHhx8y2061Xb4ovhFSb011mH6hOya52GkiYonL+/FKC2HmxRB2dcrN9c4V1oW2
kZZocWYNyoXAzlkZeEClxLiwGzT4HTh6FJQZQYpl71YcIYgjJRA/Hlbg1WmF7yvXpxi7BnoDuPIR
9OqXq1FmxgnqdPNvu/Mt3owzhuA8AuRSdGnk8EVxRN1ea+hLd1XLUu7AStNHYotknaAissj/5JTn
wsZ47VE4AemR2A+VYHqIMLoy/nGKaNiaUlId5kW86MkQ/vUu8rDj74cElgab3L6sehSsiQmfC1rx
ORbjpPsdhWDbrQE9vFKQapHymbJLoT8Az13+UfBlBWLlvRZ7K5n5/AuTx+y5GJWo3fTsoTwf3mvx
a1IEpDA9Ahy1N1qQAdhJaIN5jU3S3X0nNIqePn+BqjYtTgMFZMtS0C4BFl7KGLe/ObUzwHsj7DGc
EyGhvh/aC9l2elv/K2KQdTKppeUCnyeAP1FRMrNJgsAvAZmiCPi1mtIo92cf+vgJevxX3xwV/eHn
RaJ0XAbqFZbjwuiEGoJe57zhYs+Tt+LeRB1rIxOb95e4uyWNAFnagrl3smytEpCHB1ZcflDwutqD
DLVGaQDFAXSgjLcXHso4vU9yDbjdk/f1Y9AJxAU5uBdOw5vnvR5ulgbZubGI3kxmMsYrB69Kr0ZM
Vx7aMz5+AEO+oQDjb5alf9IyaXN7lDeoHMjHIL4WM6CUgiq4OkTC6hohpoxr9p6xMBNaGzZYIeDj
/FffDTqwq6lCnXQs0uo/m58GAUq/CGL836fExZeip4U2PDvmE2Z4vk3g3UL6m2gJz25f0Qin+KhJ
SNe+rTH5TWQdvRgyJVIE4AeuFOGllsL+rKPSFhzEz//ANK/K+X8nz15TE091ZQcPvj3aLaP6WPL7
inm4bjRfCpFOROK41G3bqP+JQWc56TqJO4RwOd3GUI7jhmwIjRvbzpLjmwlsL7WygRF7PgzTnVpj
eMV/5Elg5KjUh8KlaLOc3GEpHkXSqVPj6mRi8zZDaLMyGPTY0RUwvaKI/JLnB1JizIzvnwbSxdB7
ZPPcaF7oSZSSb6NY9XwOHTA0mk9ddIZFTrWXfibxC1rYxLUZKJCI2AgPuNpYG62M801TJL6DsvuA
MWaPkDCw6YvzCsrPb+BPAgM41Djfr6WNKfkUdfSTZu7vZgRVzXAlqXNi866Yd64rXXQkBQTU/sxK
74iXuUthyqkTpbMEY+1TORLb8WlkDIUhK886iVDJOUE0Wp1I3CEOHR9GOMzC/CzBTB/oqP/GysQc
p/lFO7ZAZ18RFm9p57HARwO5SY9NKu82QQ7NQXBT3eKKnJ5ZWkxfzSWKpZEIcQlOn+DdmCWabD42
zmXJhWDkckRml6NK2ntjtIZ35TpW5wnGh8UYazWnQo4jTKErz8pilDJJVdPOZLpCPi8d5eALLyU9
fn4kaYEuQMAY27Cl/Ki19pvZCuDx9Aj4m9c6JwXH5wkG3ITLP5PZuJDXYhS2ci6ceVVAZOryBZKD
rvnxTJihpyM/v4+4xwZIydk+EOQBhLNlmwuVAherJokaraDimHZgs/7RfWs8E2JM1LxA27MlwuXC
6eAWvogRpLVFOw9XbsSYVUO5Lmkk2+WrXdhhFRq3g6G68OZodw3gJxSN8DXSw2m9Y1L5wpjz3fhd
uhQMsK7PnNKezhRn7vzyHD3DYYccp/Bo5SaJw+fY69C2fMtRBKe6GA0YPfbKBa/yzV7zAjjst84/
rZqfCUKLPP1jxBNdmhydnJAvRaU2dPlQ7BQ7Oj9xQyUgh1SZSw9IMUqxM3XupSqOWngpfUJ63p+2
gyOmMEYgcdmaqkPSQPksLQ7YblWbSWv90MFN0RQU8FIbW12GZuNtcmXRhgmrLWmMVhAVj76B47uJ
lc8/YYZg/iFnhWYsgRQ8ZgcGPp37ZPCMHOGVp+AhGNpwcujCZ16vXSAWZZzjmSs4PRRr/GRlvzyq
dBjLZ8T1tc5xag+0rYbLyHS5YSrZynME3k8eC64ZbkFoJlrf1XZGCTlZc6uzPQ/5lEwcS0uJCJaz
KSxnVAiIzdfXn66eKLZkbsEApaRnNu5C/L8hoqDnhlVoKbAPNqPjs7W2EZHFLATvYnW9IZlYn0/S
IF9o/l9KHFsuK8mO+9aOkLGF3/xF6hbQyqWOCaDoyddo9M6GATKPsw5Y9mdsKUTeUHePdSz1ATek
mbYD95gvg8cTA235lFyUUcRwP9InDyXautp+aJ7cU32Lwh7GN1CxFu7wbESn/2NtEzQ0uneucYpm
uutlX7Vm4D8DJ4LbK6CBbSzjiDtPxns0ZK1LtUEL3ovcwxZIT4Wz2Yov3LZqenVmdJ+5/Fd+ZP//
Uho91xrZOMB4LGylUJFKhBtwImBR+iRonXcbUSh7OXoInUuIZ6O2mcrTIv/jqMhPKgzJ6S1SKZbJ
eWocmGu1an/0UZimG6wbfJyDhsmlECg/RqfQRPIF0P/WdPIcdHBSCosDNlXX+U2DXFwVBbW92uBs
4D03MKmkwl16umEShQbyi3W+XzFJ6J+Mk9wbD1KAhCXMrx+Nh87mJwbw0pKwMYFqcNgnaXzcn7qj
kQ9HFJB6LGHSI994USCIC3e3BF4PEzejWflAKHXwgt2HF54D8ohx+j+O2b4psB6TFRQYw5FHdq6K
Z1cFDtuPbA7jk6kWbtgNwSpUMpfIn/+91CUkIjYr0fN5pvgX4QhtCP/ZjFJHxdKB0OfcpVP/3/j6
/9dnPEjQOyAnHsJcIPkQfop4PYYutpudeI2RucgYAJiHPJ+BhUZ1sYA7bt78Drv/KPMLUR6QFf7h
0l0jTt0Zmb7bL8B0ux9O+PbBprQIVPrirWZ16pi2sroN5UfjJaFL7jD8jmdIDee7Pf5ZZT3hjtWP
+8jcvY3oeEvn8/SH74C3xqwo3RFGsoO6XRxcntT5+K5W9ofw0Qg45aCrBjmR+q6R9zgpf8FW5N1U
9qDqsZHE7FVBLjQlHEIkgz+JuX6XHwaLsUxtdQhg7PR3/ENAXMWk+kvjln0xVgwI86RYEPYfAdsx
4z/MfIQUvbrz759Z4gYLt3okqXWjjiU2jwibfdgbGNxqGW3VpAC2+8YNGHDJgjeiOKY+r2bqKtRH
b39NBett6X6tZ8xYcUa6Qs5hDV+2mWSTo5DSyT99issL/fgthaWWix26hVVF3btfMSCNA0dfa/26
/lBWv5jGB3w2V5kaDydiqqq8wEZbYiwJlTGhoWQXHBerK19zsHuC82RAYoI76EmJfhJuMAp+5+y/
OmEL/CoCyMeq9iYGcVbsLVkp5Pf5GthWfj7LrL2N0rwToZ0zSooGxjSgZC14fCz1VH+qW3i9eT6i
P6Kh04jhRh85rQNMgg8kB5CpUBhUzPcQcUN+2K4QAwH/pPI+o5unof68ARH/JFvTUq5AUR1IVaxt
fYu6o1fV67DOr1NfEYC4FkKfPhjlils3inD/XXsLKTcuSCvDoUAW4LBZZJrGeRyDUJ3WtM3Bujgs
kJ0Dhm7JeF/oIlI1MhMT+S9zmFLuOCAT5BUOE2BivLyv2anHyQ02vOEJwUlqQyWZlJEAb1ySniBq
K7EyGc9QSywGbMtahAf+nCwaHcjZD0ltqGeUApwp3gTyS4+lnVvJZ0XHJpy8fyRQTDdss9DusgwL
YxUv2WeLNNKBQKfKMTIGwUGkuteVjTYmWmWcaIu+MvNME4L+oFz7iX4fPe3WfXai80zH9/2heQFb
zbn3zU8lacF+XnhLf4YgkNsBuJu57mcqM/0+QuIb6NXG+LB9cOaYKZ6+9ns32fJ0Cc+Shj+0JJyq
KcXcyh4WiKugol7qmduPWMwY2i9zjDFloZgsceBYDs/T6Y9vAlJle2XDIE3gdHjvr0r8+uF5/TJG
ulntHctx2fJvpLw5nN64rTroz5BlGuDE9KQ6oZmhNgK4z0VBED+E9D8a939inE0cqDcuKYrIZBkT
FUqovsSQs9K5tR43tX9x5zXvZB8HASJBQIZfxOMp4GKybn4vPGz9P/CBEjSGZvcgLKwfFFdM6Zmo
zz/CedYJKFCkaB2Sh9Yr0t7cGdVYS1YAMmdpV9XQVf97TOJBKgRpSW1Ub3zNIMKYgV8KN1cusNSe
aaYaNUq2QMGFPFXEmizjXR7reGR/suZmixP3Ye6LsFvL2ZoYNiLsDVgOOdMOnlMN+j24D0fzGFgk
yX4RVDSt202gTjwrKnp49baoOJScW2nuwUZFiIBUAH+01CJ2dUl2SXXkDO6hmtdqQ52vjRY3jt1R
aOAq16HlDYAv2gWt1Jd8r1BGWXOP7hCT4vpK9tMr1E5ild5K2Sfx5OcI00XuWLPZ2YKX+YSNRTOW
iHfzWsvqRVBmaxYTsU9+Ttc2MY+QHCb2cysZ7UT4qKUWh3PZdlRuLdQ/aAd7DgYg62FA3rDAB7Rd
syk0x0EHTXOe1D+rTcybpXeWUSE8yJyxs067fhcnbdJeKEkkivajMVHzEezaUk7CiFh/NfT+KVle
c2CFEqWsjVDZnf1oduYOeVUMLYq/jKneB6HQU0oIyHSdOH+vuSbxTRU8acPdA9mV0zl7knowI7IH
r1vbAaG0LZ3mr9Zxg4yufHNGYprnIrow+q2c1nI3a5Kj4VH3xd/gSVc9xPaYjEXVHsN5zsOEjlcz
eab3bG+ycaiCDLwcm6J/XOA6XMyf9T+kFXGGNedu+hbG2zUkbChuUV5EOgqpGt5Yv3QZulopW33S
Z7i/BAOgF74cPQ+uBjc0na6L9CG7RWRiU2L813homYiBXN7CfrEE4c2fMYrfQkAGlDK5M+m9aBnu
XBSUPBEuUGGZKYjaFR6sin1z6UXrR15C5cVQVqMZZ3+iPAOcucrYJO4IHzRV9pDoZq+VO6TDJCFQ
XYmvMAa/UazZQk6yH6X6nFdnzQAb7+Q8Fh7M7Y7T4R7FmMV2Ft+1TiYolHCXj25T3FLCLmyf1vB5
iyJjfAt0ivqAVEuAZpjMOHsTW6+e/X6QRBzCVtjCOQqSvs5qy/McLT2P8ipPC5mvIjjFk/wllker
Q8y/uet9lCFloRdiPhB89ewbQ7xvZQPVGX1YhLnmzk7isz3Nsrx7l/34xRxfds2m6Ablb6eYTg09
jxxONU5k/MNkhwh6Tr4p+fDPmICujjxM6+8hixik9zHS+rxvaPF60l+RjBBPhynZAadhl/TbA0T7
5FTl967GKqRb7v/v5tGs/siPiPA1vtvLOI8r1BcHBRsvvfP3cUpZit3UZUjuUvGlteCyGAyvAlve
DhCAHhQLHkkOGaBSoSqK7jjAuZjHKvb2gn4EZlK9iHOxsbaO/wiSFPJDctDnT31zMC5V1dwzZ4Z9
/uc9poe4nHTDorrh0h34E6EgspvGWiYkGY5U4lwFUXPAFKM13FKujLjpujkvHDREzGmOXlMSPHPj
jZ5d+WOST9S0tyT8i9hKJwFsVV/U1D1E77d+FLuqj2zSnHi/l74ZaYSkvu0ZNhrhJdCm374Qb3H8
yx7MjFXYlMjWJhyP7yKQQteL7dm6uAYmzWZFj4dj6LjehuNoxXT0xI7voriUW/NKgcCLwaCowq0f
gl8Cu/A+wYnnCrufT/kbBFFhwotz9JjRS8iPbPpIc8cbGGdXLOGa/u9qmT+58H4SFXP7p3Mb4RbS
ogazyiRcPKw4cgtVh8TawpLw/g2D/JAQm04oQvIEVuUxBYUVlenHzQJ/bMB6CllxbuqBE8ZvB510
S6jbAUpGWIOmzr+tV/DWIa11bZbI9b0UjIxSwpsRULGXkZq6uN8G8d97lsZtaUOQzTLu6BnGReRa
955m1H7R8+G2wR1irmzh+HRXPbYtO0uD0SYiX2Ci/r/P7/j3srq/DrmPTQ1aBIrPHrc9S+80E8kN
pY9kInSqXQ6kuPMbVf/nlLWnMToq5A0jSBp3uz9jxEb4YkZlZX3eJoepvGItpYk6ww2YF9QojjGS
okovXBa+GbiF1vPVimyw5QzsGaRMKzQD9rG31F1/W22+lwXDDLrt71B+GPuhFLo5pHupG2kZ95Ua
5h1Hj5ITja+ArUaJQQvh7iGwwWG7zXITDuFjfpKQrvHNW4FCxW0XxtwHH/bSGX9K9WYvHDTt7/Ty
XGjuhOW1A8VwOskA2AV8jQuS9Ywdm6rxps2Sz8INDEIXoKvGBIiWMUNcuTZ37kZD17xXQhaK7bFD
lg1BdJehVuPvCC360zdGIhejzWzdLt1/ewoJMW1BZ+agyw6/BlsR60UlhcJ8pbCS8ePGnTcKjZUN
xZoftxsKY/d6mRNyJIPIZxopVYy2xy2FEgtM1m4pBw3soFm+izcuYvForjVbQLfAeXEF495JQcYW
AbWuaHc2FjBbu1snwHpgopI7voWn9s1mfj1aPJlkBEIHw9E2z+qgJxJpYKSaAAaUbDOzPOgzDE5D
tn8LMfzRcKIaQAfZnUlzHQRQFd2N/nRFf+PJIuKcU2/wMMQyvWipBQzolafZgEnPiHkC5HpsFPgr
rqFUNG4US+xivT9Vk7a1ZKvJJO43JtlcVg7oFlrMLdpABZyziHYJy23B7/hX8x2+Ul584ElDNjm2
dHAc36fl8SD1j7OtZ22Xmib8C7gfzj6hxfoxzxuYJ1MVQBq9Abc39PwDPMMhwzsYBiR3aXBcYg7J
DbUTWmtYRACbHE+riq9Zv1f4qNYtuZ0oB3ae9eWPathylYZi9pmU8E5ltczltrhdGwQWkGUnjLab
uJ8u/YTGJa71PoT0+at2IGmb2ozfMwoOiVslZyLaWBYkpkncTiZ3cm8wbrXv5NSK1NvNFhfYc/Fb
nAcfFGPtovRz7mTPWVJEhe8v6NhSraVidQ9ixRitAEDcFhKCG/sayPb4N/GaZ+EVDlRXiBrQJaxf
+T91mi4EDDOjR9zWyGk6sV6HqfRYewWdm5sFD/r0kmOIvcakBHwiHqwvN9ltLhciGzKl9RvMqC4m
1s2pLzUPYD8F5jicthvLIgAAMGIsCohWszCTnV8AVdHygkrV+gbbyOWGogPp0m0SmZzjKkJLRfe1
Xu4FqfOOSS9AE/RORcPZQo3w6701QKHcUWPJra2wPD3DWt+uzBbFVsSWRMsAapdYys9dB2pMVIUf
OHBAzjQnyv408akIdNowq4Cq1fCbn+XL9BfnHbsOwb8HchuY6PE1mxzZYFSfJyLTGNwfCZqey10W
Q+44SuyAusYSBSTwBrjrnkjUeL4HUtBf8+8b4KIHuNRp1C3PiqqKmzlrfl/gvdVv7YhroMSo3m1U
+jSxuLW3M5u73Lz+P745+qYgjjMZ67PEbSyBJ85AlIHYlUmVTtWf0bLRlXw6JPy6ivFh7XT9uD4q
B1u/XkmjctpwEIU483udM+yH0zWEht+HrtHMSZ2tytcpuJJpBMKuGExG+1496Ybbx1iRfe0BC8YJ
7Pt/UFoGx9x/t0NRr+3pDVL+jOdUsyfrdgzzieDgFj0gXJW4Sk6f9P2wUxEO0LphMNO5idECsGil
pDYFmpJLQAW2Gn/gSH+KNvY88ZEzAjRUzZEwW4SZ4ymlPNDHBZrAcAHiko+i5Gd0mem9rYdI9C8s
zzCw/yOCFO1NAKQO2ft747yB6068+j1jWZQ5dW8gx3XzWWUONYSM3V/iTsUGMW2qy6tudK+9XogZ
0EKYBRspnVo+4lsDinSsmscV4GqWvuvsQbupxp/NWruJxU5181/kV2ensDQmGMvhjKhy9aa8RJZD
JojuCFDjJSBxK8nUgy+xoAQgLryQGJ1a8vx6zbRzityiWNikBTemFRHKQUxzKKpOGo6jHfQYAO2P
r+/ZlFxpgA4MA0Qsxp3uJMBUuhQC2A4gUgn6Uq+MxBLmXc7RFq++n5fAEaJ4g0R+Yx7LG3ZU/dQ0
kjI63E61fFZRxicEdeH34B1uuEz4i7gzY+QRhU5XhyUNbazMQlyzL0j7E7SyuKTIuMLYSqK+ckl8
2xc615vRL+TdUwYFzons1xPllDDB5FIICRPm2iQaNJUo3fEZEJvEFU047XuuOAmF8Mc29RDHFy7F
Mx1VeTQimUnmcRLpbD7uA6+RXgRPlC0mUOBgPZPY+Lj0f8sM4Z4eIH6LRHlEH8UaowGJX23pzw7+
RBLKbcwATGTJu2UROel5mMKRoLxmrqJfUoIOgj4An4IhcPSfELTppzzGYV4bzx0khMrBTFMIYhmF
banKDzFbCWbEp/OHD+eRg/RmBCRtqHgkZN+Gx7jARyXBvEuAAwQVP4K2C9KxKndKFdlO5OzkbqWX
CuQS3kv2AXzhFR2bWdAyQXhfcPGSqq3KXTg6br+9D0ZZE8cp7fGHPO8QUFuj4h3d87rac46L85eZ
2SVdCE2eOBx/OYhyLDkvQ7H/DvY/M94GPjkEHC+uGe5BkdF2Mzr96ei4wvmTIC/CzNcW7e3onl4W
cLNV5atcjqkBsRX8SVilaaF6FKwtWE+hprif1LhM7dodHtwEU8RAMFaWIOotOuMEuDnEuTFR8Aok
bbUr6of3mwKDm7deRivJDyH10KCaUtnJIZiixO5DckWdzJdAssNgTJEW/R+ceC3I4RKADqhjAPJG
1FfyfHzunJbNzjL6zCCNepgrgT6njTUgrEqjobV+aAa4HaVJbN5YBSC1wl55oEZp7dQas3T720DQ
QRQiSwTQhlSclp+3rQvzABKuU3A9sGlQhDnBMkhWUHwiBcD/3a3vubgArGNBnr5+aueAwf0lWhBv
8F43Ch+wwsos+nlVXjtDTTwwhTJuvh9Zvvh7316LmJRVZEVoQzVPoMkY4v667w==
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/sim/daala_zynq_axi_bram_ctrl_0_0.vhd | 1 | 16729 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:3.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v3_0;
USE axi_bram_ctrl_v3_0.axi_bram_ctrl;
ENTITY daala_zynq_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END daala_zynq_axi_bram_ctrl_0_0;
ARCHITECTURE daala_zynq_axi_bram_ctrl_0_0_arch OF daala_zynq_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF daala_zynq_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_MEMORY_DEPTH : INTEGER;
C_BRAM_INST_MODE : STRING;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_MEMORY_DEPTH => 1024,
C_BRAM_INST_MODE => "EXTERNAL",
C_BRAM_ADDR_WIDTH => 10,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 64,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END daala_zynq_axi_bram_ctrl_0_0_arch;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_sm.vhd | 5 | 41952 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
-- Always set to INCR type
constant UPDATE_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
attribute mark_debug of ch1_active_i: signal is "true";
attribute mark_debug of ch2_active_i: signal is "true";
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal update_tag : std_logic_vector (3 downto 0);
signal updt_ioc_irq_set : std_logic := '0';
signal ch1_interr_catch : std_logic := '0';
signal ch2_interr_catch : std_logic := '0';
signal ch1_decerr_catch : std_logic := '0';
signal ch2_decerr_catch : std_logic := '0';
signal ch1_slverr_catch : std_logic := '0';
signal ch2_slverr_catch : std_logic := '0';
signal updt_cmnd_data_int : std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
-- ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-- if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
-- updt_ns <= UPDATE_DESCRIPTOR;
-- else
-- updt_ns <= GET_UPDATE_PNTR;
-- end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
-- coverage off
updt_ns <= IDLE;
-- coverage on
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
updt_ns <= IDLE;
-- coverage on
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
-- coverage off
ch1_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
-- coverage off
ch2_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
+ 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
end if;
end if;
end process REG_UPDATE_ADDRESS;
update_tag <= "0000" when ch2_active_i = '1' else
"0001";
--REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- -- Channel 1 descriptor update pointer
-- elsif(ch1_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
-- end if;
-- end if;
-- end process REG_UPDATE_ADDRESS;
update_address (3 downto 0) <= "1100";
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
updt_cmnd_data <= updt_cmnd_data_int;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- updt_cmnd_wr <= '0';
-- updt_cmnd_data_int <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= write_cmnd_cmb; --'1';
updt_cmnd_data_int <= UPDATE_CMD_RSVD
& update_tag --UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
-- else
-- updt_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
updt_error_addr (5 downto 0) <= "000000";
end implementation;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_scc.vhd | 1 | 48409 | -------------------------------------------------------------------------------
-- axi_datamover_scc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_scc.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
--
-- PVK 9/16/2011
-- ~~~~~
-- -- Removed unused signals from the sensitivity list and added missing
-- signals to sensitivity list in SCC_SM_COMB process.
-- ^^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4
-- Sets the width of the Tag field in the input command
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_scc;
architecture implementation of axi_datamover_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when 16 =>
temp_slice_width := 5;
when 8 =>
temp_slice_width := 4;
when 4 =>
temp_slice_width := 3;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 2;
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
when 64 =>
temp_btt_ls_unused := 3;
when 32 =>
temp_btt_ls_unused := 2;
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_input_eof_reg : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= sig_input_eof_reg; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty and
sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_input_eof_reg <= '0';
sig_cmd_burst_reg <= "00";
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
if (C_MICRO_DMA = 1) then
sig_input_eof_reg <= cmd2mstr_command(CMD_EOF_INDEX);
else
sig_input_eof_reg <= '1';
end if;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SCC_SM_COMB
--
-- Process Description:
-- Implements combinational portion of state machine
--
-------------------------------------------------------------
SCC_SM_COMB : process (sm_scc_state,
cmd2mstr_cmd_valid,
sig_addr_data_rdy_pending,
sig_cmd_reg_full,
sig_btt_is_zero_reg
)
begin
-- Set default State machine outputs
sm_pop_input_cmd_ns <= '0';
sm_set_push2axi_ns <= '0';
sm_scc_state_ns <= sm_scc_state;
sm_set_error_ns <= '0';
sm_scc_sm_ready_ns <= '1';
case sm_scc_state is
----------------------------------------------------
when INIT =>
-- if (sig_addr_data_rdy4cmd = '1') then
if (cmd2mstr_cmd_valid = '1') then -- wait for first cmd valid after reset
sm_scc_state_ns <= GET_NXT_CMD; -- jump to get command
else
sm_scc_sm_ready_ns <= '0';
sm_scc_state_ns <= INIT; -- Stay in Init
End if;
----------------------------------------------------
when POP_RECOVER =>
sm_scc_state_ns <= GET_NXT_CMD; -- jump to next state
----------------------------------------------------
when GET_NXT_CMD =>
if (sig_cmd_reg_full = '1') then
sm_scc_state_ns <= CHK_AND_CALC; -- jump to next state
else
sm_scc_state_ns <= GET_NXT_CMD; -- stay in this state
end if;
----------------------------------------------------
when CHK_AND_CALC =>
sm_set_push2axi_ns <= '1'; -- Push the command to ADDR and DATA
if (sig_btt_is_zero_reg = '1') then
sm_scc_state_ns <= ERROR_TRAP; -- jump to error trap
sm_set_error_ns <= '1'; -- Set internal error flag
else
sm_scc_state_ns <= PUSH_TO_AXI;
end if;
----------------------------------------------------
when PUSH_TO_AXI =>
if (sig_addr_data_rdy_pending = '1') then
sm_scc_state_ns <= PUSH_TO_AXI; -- stay in this state
-- until both Addr and Data have taken commands
else
sm_pop_input_cmd_ns <= '1';
sm_scc_state_ns <= POP_RECOVER; -- jump back to fetch new cmd input
end if;
----------------------------------------------------
when ERROR_TRAP =>
sm_scc_state_ns <= ERROR_TRAP; -- stay in this state
sm_set_error_ns <= '1';
----------------------------------------------------
when others =>
sm_scc_state_ns <= INIT; -- error so always jump to init state
end case;
end process SCC_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sm_scc_state <= INIT;
sm_pop_input_cmd <= '0' ;
sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
sm_scc_sm_ready <= '0' ;
else
sm_scc_state <= sm_scc_state_ns ;
sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= sm_set_error_ns ;
sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_handshaking_flags.vhd | 2 | 12552 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
VbXNNz2sQNIe/Uo+l5M5dRWBWUjRxBAHVt2719Iw7IockhvUVOKInZo/KKcqFELSp5Ob7y+/U9LZ
G4tRrz3aWA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oEwJH+5spLyqbfmL33IyNNEWZbFnR3m1JM8YHVRYKyJBeGddca8IxSWU4ZOT6J4tFpvqc2uxjlWX
WZ916ejUE/4AzabGdGyyeFXme8uds+yKAAmhhr3ralVuZsXCphuzGFLti0dswL7O5NrFjjKdI//w
qBOt4tpjdrNYByXpN/w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nXB3ZSLnX4toO1TQNmQa5ihUNqsbZsBHPp58HdewczmWOt+6cnTENVFUahi3qyatrXVV8Iper8no
1kD/mBH3VfOaxKqGGfLfHNyuFw96l81ID6J98Q5fcJy+MJWMrRlmJTm8O9KAk3RuwLNo1TkQ/8bF
eQQ09VKMXsWRGR1HsgEPl7AFHy1S+Q++DeE1v2vkvkR2wM4161QOVlZjNL8bNF7QLzIyq1SBgA27
zlZDXvMin81LV0R7azOAx4PbEa5sE256fECSDuTlN2p+P4Oguy+SJjcEs8HDSln1dxufpSqL5+qB
M1HEsTgjAYxC9YtKQBVU17SY7FvG4EhwqYDUhA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
dM05GYqkaf1hWdBujxvJjJeCs5vWzaUiXDqJIjwDYgcDiWnIAGcWhCWiNUUfJhxS9VQt9ouOsVca
CsrS+Salpy84W68e0ohsGkhTvRgV5C5gMkqpFK1HGqmZHHRcXYj7kaeF3LqMu9+wY97Z3/GEw9zu
vpcCLGozCAkH1qALmic=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRMLTaZSmu/MEQhbUFNmojY091MsbTh3NThpC1c+CSF8rgGfRS4EwCE0/hlSTbpHYryBUqfMWbQY
CmNHx74Q6IPrvP+kJC6gEQojgB7XDFh7+T4mW388Y/guba05dlIQVCTrqvlK5oh+IZ05u4aqCC59
fU1Fle6FiVXsVNbdHsFxBhXzPJ4AEMB3pJwnQwCp5wKQAcyDYW9yhpsaBpnQJ8dwYnYxJj9ziozY
Ood4WHEc4+EljuAQ50SJaK8pXCci6THdWUFmXpwBqwGe4a8fdc2VD8j6x67HpWESv64oNAm01zcC
VEquQo8nnlNsfVFgO7OP26y1ElEDxALISX90rQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7552)
`protect data_block
dUFdgSRqPrbhaAcBFL9erV1feZNA/NNl5EPDZrTpV2a4nONFdB6yz85odS7HOMC+mYog6NpUr2Tn
1YrYPWC2/ukYZ9EWBNwn8jGEbEyT9lvF3Vlj+Z2+E4kEy5CAvDH++y7Qkc384XYWj7U+2qy1jwNt
IcLr6NeoQ0dQ8RtaKbJ078sg0vOC65Q/f2ox+TsPWrqR1UASCthqRtWEApbWr0y4ziC+LPYGInsT
QLzBK61vJBTP0IKZWHE1oD/UMbeK8pWFvlmPxuqM4ntQbcMDvefxbP9qi8NXq3/ZptAzrLu1Zl7U
0Ty0GlFqo2sZjBKZPHfUMBuz4leF1gnfoTzBC1F9K/XkxHS44sliZWZqVN1R9YpqYGiFZBDt8nq9
6SyT1Ec8arg5CeG+Bcr2ZT5snGqwyZKvpAqt9ZXl2Ld86X2FOGx00HT50ihIsRr0FoH8B7ZlgS14
cwmvIHP3MQt1G/eE0IjRrQDEWudmGXaaDIBFkYPWdxHpwavh4StCupLK+Bp9KvJUoZFaSrzsAlg6
MEkhsyNCqd/6cjPnbWeDA7Wn34ln4Pui649LXvkcBOP0eZrkmR0AUYUFZuiG+3rOxdiMrz+FrA7U
4QS0htV0++PH/G0UV83nBCcwHBhLV+gML1I0U4smhTF7V6euMt8v6C6+OkNkSRvHn1Fbe37x9Dr3
YYLCXMFQZ7DBWT0bFOcAwzxZU/MwT6elAufiO+krSw+nBK5ffGEotJmdCddI3Gd/NCulaSmfjVCd
1COLz4KQwuUBHw3TxBlAZGsglAblBDatOnEbre1olqp+o7Oh20s1d2MQBT79TwA7j+zvSVkrU+vS
BHf/Ajfhx132vri7Eyzjmp2zVW7Cx3dELO/uyd/+7WLxSQFNS3KCwDJphD05BjE1i5pnTZyV39N/
VDrCEFE9ylJdhaiWHKVv+B1/qbwFcA0EZhzQ3u71lwhd1Ratd0NhTd/ylS+96b/hl3Oz9wjw9UJ+
bFtkIAahOoQGHBTNATv8BeV59ss+yRvUYWQIdSPydzPc5iXCRLJKi5NUOmC3K25XRsp57Bva9+iJ
m2FFQAJcFyuaTk2RL4MySHV7u4NV4jTFVhZIbVP+mXd1OcMgJk7YW6KaFGN2YL91Ph+owdf1zWVT
LXSusjHNfF31yIspfK7PRoH20ML8xNIbd/CzvdPijHvnYdo4dn6b5u1YweMuocPjYpc6mpc8cIXL
s9RIw3nJ4W924/i/FN/HzOGiINr16PsrLzihbsWu89GwoZgMqauOvUEYI/CZlvOi/uVtS75Ce4LG
cj6t4mCt5Yb0yP51r74O5rG+c9s5pzawLCt71CEWRZ9uoSi7MvSVk4qMngB7+NwJqwWODEKtc0tv
I6SIjPfK0yKID1DSyhUV4KpgIQupIvGRWUQ4sR7Rwj5uf60/naYXJTfPIpTNotczMvzQvyW54vTC
Q+YQ/y+R2WbRhY7f2KsrFnHhWrx8UNJF1a4O5xfNMoQht2SUAXPUsYVX4pkZpRQ1UBRCDvEZaXcl
mhM8l9Ke8BZBlFo5tmZ4bummXShy6wyRprZdKCx+XpeIzl9qohp74DDHkiHLKqN5pIaKLwsLmyQM
u9n5TmshyNYr6ExnLsCzHLkQ/HkMaVIz5Mlbkvz9hi3sjUG9A6R61Ct3wnBXTiOmROOo4vnYwIoH
XkPOwRlqnropYx+7y+Pc3ajedvgACztaW+Q4JsvIgxu10VSmbLOKS1fEu3Q/8drgPzl0N4DNqtNz
hkML/Bh6uaeFQ2QIWheC46lG9UUBIPU6HM/gb0CTdYOl6xTHZOnHkHHNpGmfsw/UgxHoP9tbATt0
+/LUDs1bCJnB0SWxkNDVPQvR2dvRlQDNZWqymUOoUXlsTv1PD3mgkxfAYvbVePi0Q60MHcZcflPA
S12s0xPkdYq1aNUnzyHAsNDZJxt2FMHJl+WxlolnjgDyTBPIG6jdp/kIUsyAXkTXghveiMgQj6nf
u/hijG5EnHmUJjgAcd+tkMmkuB9+M7D8Fqtgb5PuDDOiWPnofunv0mQ2ngTkr7aZ0WpCfv0B6/HT
IViwHFwsMlsISTi58RnqZaDSE/3ZjQ3oDvdxXRLsRcxSYeMbQIzT8j32y+wiSnqAuMGKWwXcwwfP
9hXUydlZ3FVpzLSRHHp5A8eNIu3XeBSbsXF8QHKMBfOysLJMhnZMZBdp8LB5nfCs+/wlkx0qTFHb
IFyeUosJeNpye0IHfW+vnW77/Dvgc+PWnrBVO5dAgO88YyFNN6FrOe4Rlw4daSHD01yeAsQHUCSD
NsxipLB3aObyeMYA4bSSB5ygpWbYfJD41bcnwOMmlNQ3owzH7M7l53xmBOQGb1sCqEgjcJ7zOWBu
poCdGljVRMt+xR+q4UC/IGNCpg3Tk8NW0k+OHn+6/H6VY+/TspLga/Vfx2jUo5vklDz8tQSnsiG+
iYyX6RfH+LqgFlXJ+IK8RHcFchIvxDu6zLyLmUbxeekOc6ecCq/CZD7YZvfRhGcbO6HFv207gilv
stENAlrBcKsT5pVYgTUGv9hJB5u8+tugvT8pLXQbX/QIPkOTGvNzHn0fcXfuwt9MVwqWw3rhGhGF
NOnO7dU8GmBDSAuQgDphtX9eBuhzG4CbocP+cUkHA1i3AKU5FmIPvjDYo/4Q2et6sQTdqiitMPEr
KOouolC8OQ6gAj6afuU/BWLWfEXtoxdARjKe1pqmIlfhcazSnaEyRQAuGJGqxpoIiWRlR9miXBIp
mvEEzGjDiiuMTgauCvKsk/pKms6BOIJh0BwUkGZDLxnaw0kOjEdSVHKVvpvuHQ3+GuSwsWQpZiJb
W83QAUF51l0hoMEle3uCYuweSfa938jPBIZ9iJYey7CVkqyBEGbQ+reiGXRlJhqa2lGTWFP6W5jC
O7JqnBDi6D6n/P62jfDFRoc/F4AyZh3Mdwhp56bpnRywCkDpbpnaT0flitmiunlWQnz2Jfbw0Qg/
27vHmRSWVz69fIkRJUYqavTI72wxbWlbJOtoeU86on1Wc0eguFQsO4AXmVPQ/+piA907pbZ7J517
hXztVt4DDANvXwTh9npb2HVhIs1BifkUE8PE6S+HAcUU7ZOHcccXmJDCJ31hHRV6bTPY9l9W1LA/
ds2KNJ0nRRSXWLz2li6QDxyhwhPr5aiROK0cHPbOBWrVniTLfgbb92d6iZnBkSNCFnLPz+qz2TP4
HBJ2j/AuLK5AY2r3v+KQ1QMBYtU1XKcvlAl8Y3O2lBp0hly39WDOMae5q2rR+sxwNR3RnYtk2Prt
0F/43UiW5pPQ6ZFtNCMKvskQ4tsaHra2QwZdaJsFRUDDAs1n7OD/JSppB3CvzB2ZdTn1uzeVs1NO
KdfK89Ir5ikhvwpfwGEV9WF+wWD2wXnFVPIat9FFPHX1T+x8Fr/B4Q6ikWbthu/z4HQN/axOd+mo
YcLxPwCM6ANtXIiJGsBaS94IhIdzvAdrAjJ+gp5hku2sjALp1XdJumBAWKir+aXMi+/yuqVJHzF1
KMRPc8HAJxBJD6JP+wfQUoTfDFctrxtl5zIn3ElEoKXhbUw5kMzYwOVHiPU+hjVNu41yahWXB1wm
lRPJ3fJok6KBwlzl5qAIRcwkVHXIZ3ZbiSijYxo7wATJBsQUKk9AF+9RvSo1KN8i78YWw/h8vQle
nEXhfDDN9nPlOYEd5JtDdWjt7S6jeWavn3VLnhXFBu8nV8SrTTabrGxJ3+LU3mcfv+suxArlTRBP
O2ZsrgFkiRGJQq6VZdXGIVEq/8bxeeG8QQvlJSJeBHGLtMlcIZeBAFY/yjE60gr4UeIzQmPSj8I5
wqJ8xI8pHJJeF8mnIpCvT0O1ltPJaj47kuGAIHcsAOLIVsInS/gabvthUZBSfoVBDWB2VLG26cHN
RWbrLCcTZCzh7bVFDe3+T6PUcPypC28gwUpzv+moh6AKOhG+gyNhu+kkA5BDouoSLtkFDNDHIGPi
QCfpVjlMh138U+aDNZttoADYaXSVF6v+NixxmJLj0kQOQLBkwnX6AvvIwM7oJg3263BnMyzgGOnX
nGXVdJnU+PxCrAxSa7zeGN5bgEwpYwRYX/MvC81M/wqDmdUX30f5OnhaCyyrfthRzrnWBuVaan7N
3W64GDM90luHTau3lsYFc9qHGYuHgefUCeRqoYJORcLZWNGKrUWDbkAoLzIcvgLkstyEQLSe/cWG
p3f9GObH+8R3IRKirTUakmGU3XlJRNnPHe3VpJYpvn42CN/16Lbz6x/jtB6Wb8Bv9ReC8AFoO9fF
SWgFYrGX+UmyOlC5T86wi6oTpFXlk+Ddx+z9AjV5H9ZPlc2B2mRoBvqZ5iy+/igWGoM0PKfQgaQ+
MhX9XW0Jm/UYtvnOSGb4o8qzNRVb/7qE8Try2Zb8xIPD77lzQ7tx1JOSY3yuLLNMVfVQ5tQdELID
3l41aSnojVSqObPjgrbI6Z7AYEPtiz4TZtFGtXKO8xAdegk8J09+CHOE6VCn9zAd8ZYz1bl9KqGD
msbAMI0i/b8N8HrxkdIR6ni7jpnkLZRU7Tlh6Dr+X7xoCtEWxKpomySCzS8CNkeo7jFOe7EPnuH0
MHr+cC23YFluRMI6qNJndSJhP5yhwn+mcj46UekTSvATCApQbIqZpexoXoYT3Xd+Ifp9iGB6WOlz
Tm2ZEJnWMlDjyvfXbaQW6Lu7jE5476rznROFitN33ar/jcKhTuG5hbMCDMqcQUIRw/RGbItYqDEC
sfXB1bGWT7+z5XrNsI5Qrq5j4Dj/I5Z7DdycozZrHsCvdAGn2uih9vxBcnp0cOCO6eDdVHXsrPgl
NzZIE+44vZx8OpiMqqAs026cmomYk21m4iGxet/ShI1jN3/3zBSeQD4J2RvNbYyW6GSn/zCsZ6Mk
KYCVqun+hAFDs5o1H0RJC+MdTZ7b73RQpJRu922vp/cHWbbhpI0R4QnGrcuBVzbfuxkAEWfiv9LI
172Z5dyQox0KzOSSVf2vwGNAvoeISZpFP5MSusrxlw1Y76tT0E//MDO4JJdtEpdCE7XqutSI65st
eSkcc8tVEuGt+D+olsTOY3mkEJdfMwhYCZDmbkhYGcYTAINcUCVu10A6lB6XqcgGc85+IHm/ve6+
nDyh4qIkZ2JhUqTfm0/OUV2+UaFHXOXu6OPjkQO0hi9Oh85JvQyBUvlpq+z/BlCpoIAzO60z8k3b
w7qC4a/AabQWcivN+MbxsM0rAKYfeSsFDlbiaeD7B3RA3jzJW7uioqur3znKM8Td9kVWpKoi9tD4
ZgHJGxycaG9Beeo265vtYCvNHnsStGmvR1WtPWw32zhtORNyUYuDtNWpVWMANaFdvs8KpQ2/N68h
h7UBmi8+SQEjzY3Y7bSkLGhkQ9J67rAfg9qgWByfXy0wZQk1wrdbhE2mqrlZ+UgxLzplzw1/FRIj
Xaq7Sq21yiwZf6uDswzm2TPqRAyNjNJok7GZkcw5jQTqdkiJ5ip1WyYxg15ASTE7h8aq5zUvfObn
6BsWg8z3XXvNcGbKAfwM5qJeHap2kHpfaolPnwOufyKce9V+z8rLhJMcCu7hRt9HMAjrBU+o2fXx
8kt8s5E+jBnJ8vevKe3czfNQz7sIUwDZL5OcMGwTXNRxvniWOBYH6rrpRQbpIWsCVasDAS8QluQx
KgBr99JepgDpBE5wcVGbG96TGMmC4SeeumkmbZb5KYiYUfPhuN8mnJaewVZe0KFBNISxeUYW4UBN
g+Lt/4hsqmzIWjgYBTgflAWoBKVDHDsa6DPi/K2k5/ixrACHq/SMelK2n7BUIhe8S426/dhMmbIA
G5yrVtjeZCkDR6uK4W1Fr1R7zhAbh9EeQrWpXyxzDjUuEk42tjrP6TxBJPALuXuu9V6l+H2dxM2G
nW5hdYHzMjnioRY6sBXdmzXIJ4Ige/RxVVgaRd+ITMuIcEhBBr2RrebKxXrTR4tVWjtc//MipIxQ
1sNgS3akaPizbhLrVj2FITBoNkP0uAaqpd0x2gdKC9MxX8pnwoYpvi6q9sEfNKVuBkQbznd3vHEB
x3Mqc9nFmrGNHtP5xlNaNNEH69yYzHLs+lvLSiE2S5hLis83uVfZcSPa8ARCALyOfb5X645AIMWJ
XNRIheYw+SHJD6KPz+e09sQ7reM0hHJ3giHeschKj3RbCbD4DR3SLWnYaycHpyfEtb0UNQitrtkr
1ux0cVazTNrApl7F9/xHt3ALkBHq/f3FsDNwrjEFbMrGjp/tze/LW33PbWLLKDVz3xlEKRTg3LCU
UmWGR7KBiK2nuL7EbYgtHjRlxj+1omaduF9DHVi66SgkFmBJu4unCbbhRBZQmmQe12NBdJNREtIa
D8rjZB3lyG+ZwF1UH1WtK6DXeKHqUY8h8eGnija9+/YGHYQsizAfJpCay1HV43zg2N2acXuNwQuu
FIgqBAw1l15vwK7eqm2TKNu5Fwo1fYsaYHto1oXtOEWfo3WeMOakYqcLLhmkXLDX3fOvitBiE3j5
L7uO+GKs6+4PlU2GqBlCcaI3w6lAULCiymBxKZiDwPvVCtM1NpnoLFaRe7AGRy6Je6n70ygk2Qvm
FCjQLqpTotlgagGzQ1r1xMW10kFBx7L+/1XWQn/63hJHZj6kG8/96lS+w1rvBm+JSXss7yVtpKHe
ciwuXHe+p/g24H51Ghdqhyk/S2h4iz4nGYXd+sLpqpSOc1GdKCj/4DzVmlte01o8VGOAaMtGxy8V
FnTdGNJGw2WDQJ2oK71NyiJ0beot8TR7qPJ0jokm5G2zOzD6QXbtELq9z68jhYekQwfzkITiVqk1
YXbnuW2MlJiinuzY1bzXZ9SS6Pm6nFbUHYD4C7+SzUl/wG/4BwXfUZfg9t3po4Vf6Njes2bTsaGI
OWYAlLfdb/0TJKqfKIu3YIiY51I+GVjmqq097+IdOAMYLDw6q446/fCmHjvDfQHG5tiC086AVElD
mPvCSVdgaOGzlDI2M76cl1CHUJqOYseGssVzduNVo5BxVNkdrSWRHIWVUpsZkR2jnlPBZp1ceJja
oyVCkXoBweTsAAwkehGaTT1U0Y7Kvdohrs6g6ZRPsB67m9DnBsl2qxIsJk/pvbnOfDtjbHJbRoX7
8iSaVGbTZxQmb2BE9oMvC11KZBhvDuksZzjhZXX/RHq1tJdHEARvzPQ4DgGNshnLJNTR1tZoDSF5
Ddu5cdF944IQbNqxLjAtjwK8k0RHkf/6CuC2BZbPddY64kldB5XMaRmuhDUDRVS97EeDK73Iktf4
8HL29TnT5sKfHTeSMZu3mxD1wzoHu7MbNZbwGz6TGA4cVoTpkbKs6Z6mewo754I3bnVFdqVLmX/r
tcNMYL3uJLeLkrVnkPqi3QJo7fzXHIxlXc83MauGkr0DOQnvwAC0i6zX1fvQ+T4v7UJokl2YPEOY
WhTXXCf6UsDVUcUINDdMykgpsr2hHo5jNm8FKaySXCxQMJg9JvSZi/tk1hb6sZmxa6SL0TT1mAck
IBBkPM14FT/vzaaph7DZ0tWAovTb5DgQtnKvBxbGdhCTlpUo/FoHJZVIesovyvruqgo7xw+GRHkr
FwcZ/JWRXbKm9a+BMXwvApUSZzJA4s2qUL3KqaieJ8AKG4hp+D6rigtGnDmocPUSLGqJOh2Wa16z
7WV7LoSAP+j9pzJxykqyYC9Qu0kv2yCXIc1pYO5fX+pxSUqlsEXirLeX2tRmBveSGNhM64flu6sx
1a70l9wyTf+O/abNBendcwikO9d5iBPR2l8N1wZpB+7mDRtLw12fBi/EYciDKoTFVlerRlM3Hcxu
7oqOEWgOgmBq6oSCrEI4AcuoOj30BdmLjpIcyMe+w4Y81Z/pHNk9LKf+7r1ZNXB9T1N+9sX76gj/
mPQjhXgD/OTDyP1WeSGps6GaSrt+sjc6eFO9YT+ojH7HWj3xWcCa7XDcRahbQ/nus2oiNM7i9ndS
GSYuqwhTqnLzwn10Mg7Agd8rZTy+2WZhQHVAKiNolLGX3SxWldiZs1/Zf2wNCjP4Mx14QDFsEtMZ
CVARiXhmr4P1gLcDW0rwjod5NR8ppOofi1ZEV/0WaRf5eiUUlm/okZnaxJO4uJPenvPjgvAlGsyo
5gcU0SJ+xfqpbVD8NA2ShixSYAA1YLoyj9pHuL0EJFMI1IA12B9pfsW/VA27HMz0G58eIOgGfegP
iEBzM4rffX+WFhTlIiKy0npKjUdlsOoL++Dp6gt9KVu62Q7QJU+lhAZNlhZkSX9j5p0uVxX4Sl7+
UzubmagGnh+kJeSPaMSQ/0wKVGxFGja1sqHJrq29OUesp5EXiCVaMbJ6NnnCfHhNFKq2yn+1qMOs
paI0Q0dPqrHutP/K2aNKzH5cggMInVYa0h8FQcG2KzlwD5TOfUd6CpFQqK9PPOtmXUwOxP5nl0yo
RDeAfAuByf2waOGFwBpKIf+r4U5pWUpaIvxYnpuWfn6hUWXlBHYwGeedNaLzv+OvDocbl93NtfGL
/UBUaDC01k/xNzx5j2gf69A0GuL+9O3zrlOPP3MGzR3/MvRhoOSqHSUEl+fxf9SAqXIKmE723D1Z
18K36zuLqcTDDBzHcjwWEXxRzJNLI5LpXGzLYjNkqq/z43zevedcwdBm/7YJZ3n0Ew7avbCUZX7c
oOrmz2EdaN4V2Qizq+TFQR7Pbu/gBkufC0/CUDWwQKV/4D6DMHLLAIz0L9j/SRQAxNvIhQJ4jcV4
oHTJAWSPTo6vIxuYldFEHPQLq0OGwRaMIKjLq2hr0W47/B5eLLFpFCwDDVN8C5bbi3LpVrLKt5V8
1rSP3xX97BAYIkNcAn9uifKtUIaweU1fiKL++XIKVJiJSueZ5A8YlRgNGtwK7P/BQdNn9yltZUe0
CHwLLToZJsgZWYCANzDWbt+RWYSakzH9sF9KNphuI2iUeiPY9yWLEUUHGUjYQuW84YQ26s5gL/qF
RrdOBzZ9Awtb8zza+h+J3CFU7L8Db2dbDGJ2uF5jnRSs/w7OsDPHaM9lcGkD91gskd7nIBufVZ9B
W9fXCB0xdhDTxAzHAE2uMHR1zozKN3jupNzRBCOvJiW25ec5+gi3kzNF0AZA/rsVwIITW32HqcFX
iCfiEs3WeXJL7Y60tV/iSlvvkJiVfCk2QwDKCblHYeNJZPTTeJbbXjygDMwK0xRCsENcV7MtRsFw
jVaScYb9ZfWq9NmLiP635VSBfGXfN40BmggDqtRawmJA+11PRz5Ut4BGEgS/aAU7SmBN1+frxVZJ
R0/YSjSvN7u6nh726alsZlN8G1Zo+0kKjNMCbY+JGyKC+kTnfAIFs0lv/xFpqVHbXWfZXgJpysgq
Hc26e7UwXrqnPISiY+6lgBI6zpHW/ptsGj5SnCiN12F6pOTeQmb4/zGow6uY6L3GS9K+pZ3lty4R
G6VMd7rR4bKqZtiQv0OP9Z4dcs288gSK7G7aerSEzcvwzuKoSULrtCGNqRaCrUfqNCXp9yISVYKk
jUgs4d+ogGx5qDrDt4v8BCnytarjyTWJ7QTePz7HJ2NycjePv5ato8wDkoJkZNwzrwUTHQeqqXMA
jl8PBFSx2dd4VFil2uL0TMi/gkHwltQymnpCNvR2FN4CmRibpsruucAXq4OSqp5H34ZfUgzxgmSB
wGSJEUwDrtkIZ10sZc5hSTyj8W7F6yyL7NzXADYcsJ51yNLpgxsn5T/yVz2aYemn3ueA/TxLONrL
mTKFHQoyq4W8m9zbmzTTzad8ZHHxUHsCphLXy9IxFIARVujA0ZX0y7pnsT7kV2e1X7VokzSXVbF7
nyXADje5tIR23u5PFZiIwxVSewoLIMCE5l9Qe4ggnKOes12V/uXaI6a9hOZIBvxuKcoacglHzR5K
8xIda3o6On0kdCPQK2BsKraJP/2IOXW/e8d67c+rzrYNSwF16aAsVZA0hHvLZ00rVODj/lqw5UF2
11l3WHtNpQonChn5DqJ5nlYStc1AjpHBOWDWOXt9bEcE5q6zLQEK3FZqvPyWqZmvkr6HCTEt9CRs
8TuCl/Xc56IqtO0rPiunRL169wMtjFY2a+gPNZvEJJzuIaMdZgvqfUbjalLKQ2TvF5MoHtT97/FQ
Hm6TXd7y+nxv6S40eOWTgg+f+45N1QOp/Q1zLQ==
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo.vhd | 15 | 11841 | -------------------------------------------------------------------------------
-- $Id: srl_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_logic.vhd | 2 | 48062 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
VJSHZrrSAJGQxWILJepTEgNHz61nOVxBoENFY7pzILOyJpa29NYOt0NLBtRGNV9iDyJYlCuKx5VE
w32dH4iuBg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cD6ywyY+8FI3EXf6CpzYjkc9lkkGW9gitD3NI1dsE/zgr2GPMgGIMkZYo+kVjDZOtO6Q0wJhEhay
mN0plsuFJ4j2oO0vtGC7l6HDuUPlOt1qjgD2Hksd7SlYP/y4LT4pNO2jCi9RsFRrS7nZyQh4SQZv
DGhpRnjBoP/gaIrmiSw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
v4aFhasWn5h4+qHZADv8o4DXx5p5DYwfQsk2h8mlzobInUoAIgx5TX5b/J73y9Xf7oHPnPYenlOA
2tH3zpTcTNCm2kZdHHrp6z49zX4Sh+H1L/cGEvGSym3A4R88mDC6isp9BHu6wDDa2tmxkWdwoLNs
QxWsNNjKReUDhMia7B09b9djUAUtaIJhTXOa/Sd/N0rCk5I2NtlRD6eycfQ55Mehlm73netgsJSo
ZFry2NYB2bs2VANbZvvVbA42fbrMQQTEFbbGSeb4LK4NPL2jMpj65UhV8bzGK4z8g8EPmedDGvKn
BmwrsM06cY2EYM2rJP0V64tMI9Y/CQVr0uMv7w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
FBy0KRMX6Kgl7tIihOS+jt3nJcO8k1ylS/kF6+D9AI9EsiKyp4BBMplgsKiJL9dTgEavT3Bxkjeg
Rq8C8QxWlTjdeeLAk+/PiddHd5+5fOm3aqjzICh6FSYmkmpdV1L9heNNh2BpqNFF09e2iJflyupW
hCo4RTnGHJR1I2zNdUQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
oO8MS8J5XnYUCEEHZnK1A6DPbDKYPPqk1NOfK/9Gc//rn4CfpdjX8likPsiD1KID/EpnkvEX9oAQ
5P9wtpukip5HEylT9XcSfX/0K0R5EeOSsHMBN32Z/OR3dDjPiGmr97KGvyYqawiNn25oUM1H3oPQ
/N2TTT760diEV0M71xLzN52C4aPISnbNcMBNsP/90yYjYoEILQR3hNajPo2Lx6rjVZHfRsHcxZvD
CfE028lAL6N4MjAVTZrUQ/UoNwy/JwDHT8EMQl7FJrArLHxQkEMUaQzdi2CF/KR+xvUnxdPKXafy
uQEx/SWi+zrU1Hz4NbGAK9RLoE77aIwHaxiw0Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33840)
`protect data_block
unpKTw6/orWNWpshpLQJCNUGv5cpiltgLYYVZNdQZv2SMBeXYdD2MV4wsjo/lpINc1J/weEBtng4
FLjFWg2fPQRSOumClAL1Iuu9urGKzLbm07kZdTPmLR1Ty4SJsXSz8siDfT3bz7Fi/qoAzA0vlJF0
F5/lpCVQQOCZMqL/rFrkjeqvxId+dnD9cLYWjwKQ5DtyxjQW5mIHd5fe7KPl/KUxa2w7MSpNmNeY
EZzurUZt/1dFguWdMvo9oEU18vIjLyVuCLbY5bYF8ae4O5taTcdkh85vNqOBFVoRi9hE1sdha8AA
9eLKTQJuW4rMaXMrK7drny/GcNiG204GTWX/EByf9i1ZU9RelG+CHOjpriCyh0riwk727jplvLfd
QvgIJNhm7vsC89DtAEoR7Q3gpF4xjayBz/uuIzQzTEIC8jLj+SGOgHocBPsFFeTypfmLBg0MjtA1
mPunxVN0+k9UawN2cnYv03WwR4CjNh5MVOPLb5ii0BHnMU7ImOVFcGgOB1aHlXhTOLtrAsMlzOmX
8suCTlmMW7C5qLjd2ccEeETahPdKzGYMl6AR2wJvfR6wzMEYGsiMMWoGa2WJM/PzFNO7uV3gnbfq
QJJvSVQ3uQTI4P9aS+emwH8+98KO2hUokv1E2Ecx466pDgjm4AM+yD23SzhuaiavlK2rJM8q/0P2
iQgqC9rvRXSoderHH0ibFnJEMQuphRJxcbkI0QppmBtHlYuPODzkW5vPoxOIRYZit4DBFOhduwd2
jQyJKFa9V4pJaNsgF/YfIwLB8JsnuXepb3CD66c76PHfxuhi4pAwCgDAaKmQ9/HpyHCmJ1bpYgI6
FSYHjY0UgjkidLXp01aRXWWpo52hwWyDq759QMsXlrC+vIk0O6q82MDVpgqUdYHbkUbA0arEZD9u
QqzPS4DgkpjIpwqiHNe3f4ptvzo1m729pEd72j2d6PQZk9KX2Z5OsmjgE4YpOeObRbPW8dKcZsNB
zJHL/8tDIosAssbgO/Frp2QSnaSWH04aIE/7nSybSt1Wv53d5G1+2N4bWznt9eDbWeylNRiylAb8
qbG2PR/WB4mdV2WKh/NhuhP1qi3yJj/oPZBlihZxQlIjNRLZgnFFS/W9jgytY7jBAy+AjM/QqyNY
nMegtGP+wB7NTNsVkw+Td3PyUcUzHbtyySLqE5sblJPhiWlUvLE9ZCb6Rg99FLepygtyI5gtv5yM
DC0RCcBOGr8PK61rusaB+aYic7RS14frv39NI6mAtzG5muP6v+61zBtaQa8bY2oYrpWPpPDRX47g
OBWL5nMoJCFzhNrRJ7iqVjvAWHuhTSiQSqSkOS/kc9h3IrgwXYC1T1q1vBG9aJEUfBe+QvQF/y1O
/1oUK+fsH/2PeZHUvkbYl5dpN+yauXvuhAYuH/JhH9THLEVY9PkWCSv9hfyrDnOWH6D9mKtQt3Oo
uqAHOynydKasCWVDX4QeXFpPg7uDElD3TccV9ON4L97q8G8e/ey7CFem9YnkyxO3WjP1TlpML7zG
6uM10GXRUt20rPXyMPlmbAAtwBv+xpeNDM9B/2MF2bK5BAByWelUuvENkuKSAY/Pv4nPbTMLoj1L
pIqie/9nVu49ZMunUm8hi+LpBphmoNQrLtkTCvQu9GO2PQfGKrDYZhG45Kcbzhkv+JClY3eZg7M3
akdPzsrCDA2GNnuDZd/SqIJJT4J7IGWTl5UfYnLGPd9W3A6x1Ur5UBZRdAmYlV4ViYMIemwiIATQ
gt6Ght+xbsJd7Gwe9V6Q+Kpi2x03s3++qqxeoY1erL0nxnQ3TxqD19W+qbFXfcrf3ZnMo7F17r7l
88hS8tlzZCtcm+H+703hCJuJ+kXjeslP/6+y9V6iWik1FcGvHsVgj8BBl8eHzlzFjkLhArC8i5Pi
ubaX0640Zm6y2BWK/yRFaGfpj+tMowDiO5zN9gR31tX+1oobSbgQ0z5Hg0NC5sK/oiPl5vKjAVty
rZFSKFvfwOLAHpMUuEcSWQkLjesCsn4/Sx3hUs5dTsfasQzgTzvTy2usfObkw9p3d7wZBuW3UKB9
vrUQ54jc0RwHkYSB9cHkcbKE+qX6KBz2s8jEgbcwMMB/0/ZM3bSPh/nsbZdU5XcVLDWh5K6e6S+B
4MismVRL8+dgesutTjVd/Qs7IP0v7Zle7P3HR+XfCOzL+NWDQI/aibf5xEhVLUb2mVr/t/Q0b2u/
255A2qoS9cVsvqkLcX1s7euSZU/8/4rqklNK9FHJ4D9z4PBvEw2YiOVtFL/Uup/YOqFatveYbjhj
dQcmGOi70YnKPh+Ylmq+mANznkQ85IFcc1bKl3anQbWh8P2TMDCik/Y1WZ1QMRYjicvrVh8W08IO
6+nnnfFDrJxCcjSeCbRE3JEx8Wg3P51/uvxyXz9I9gvy6ZUcaQm5smqqTvohBjgj5CkhBgelpB8/
u0GwGijVwEBFKRPiHozQCFFaSH6brYYxDMTXSRBsuikG+N7oAPEkSZN+mjJxG2IQ7zrxyRIeE23e
rezVtP99bW0ZN8+n8jLdyEqOxd8KY/mzM02TEYcqFJl6CjDGqoY2sn6H3rqUnj5YyTcZCno1ixgX
APdhR5rLOH2w6H7ipyy6ptyLkR/B0Vnxr2WbWH6HMUTWk9toh1xrXivpx6RgE2a+3UmH+V6abDa8
thSU+wQ6hYGQ/1Kx0gjdZLk+xWTZixEC2gKd9IMfC14BmEsxidwTOmwNC7Xje/oCx9N8hBmfRtGG
7hYxnhYE9Rlu8poCi/ftj6GeO/8TtxDDifOA5ITYtU802JO7mgKxCVzbvTlUawMJ8MmYi83b7LoG
sw16IFgeq7IS5kHfUxnYbtvX2qjo+ZFVABLf6F57xefbQtjPnCOVPwbHYTSxv3LNZ/oNsK6jFTPs
S1w1saLuflqAtsEUpCFJfePp6o/f2XVFEidXJOb3T2d6U8geOfLuyyybZXOZsdx6BEMBVcFLTso/
VhRhE7EdjHBbe8zCbTblJA+uyn0wM/ss5yPmeWDnaLmVp7XZOulKlAxDYwEZmHzF2J/e1JzcsVxC
xMP3BQbTh+nFuLqJqgvRSEVr48xiA4BSoSb20J09uapHWnzLwDkqqH+UNm+ie6hwHwRr7paNmfKL
qPPTMuCsl3gFSSJbRjg29MmQ2o7H8LTCqIgTWcjk+jFxKccw/w7p0EZuF21s6h+zHDUtAykjCEsS
HpMd96vBuBomi2QAaTR2FYHF4wbHPAw2HLjV5K1aKB9m4uKf8yeP6Yma0+jLZeajBb7a60Ae4c6c
OHxiIH5BHAuJ3Gfd//qFPnQd5SEJ5xEyFNIbnDg/VO8IqGh5mtiYnFBo5X1krOb+Iz8kyCpzSVvv
EE7nG9KSR2EdW3ul5pvuLFf78kKPMEyoTjFLYG1VpNnDrayivdqBsK6Vp81DFP5wXmf5OFhehZVX
eXFyiIY6ZdBIPTGHuMLIhCZLfrsjk35zQsFhfkxY1wwJdrOgf0jUU1ENTHm0BH6E7QN/LW0CRhg/
/e/vTUgNPXnDq96EG6l/FfpKZCgeYHZuVC52yDhLNQQC4Trl55lyBsPUbTVXSCT42vxAjSyBT3yt
0C4CBTbB+X2qGnpeQpE0Bc7OYcwCTY4IWVt/OGaGU2JmqJdllra+2q+OiVuGvDSO+kq9MHi3QO+M
ZlIyhtmlqgwYBg+wSLFdgQefATPt4pI3/2MPh4HKnfpJBmtlpUrwirVfSH83JpOWPe4XmH//9b8q
cPsX1+zAv9Ffh1LPxbJXtU/gpVJpvAVmx6ZMJwjiQmsjLrlb3pvrJt/gXubg5pEpfi7Pybnu3Pha
Bydu8oY3/Ux3ruOD0SBR1xzSvPPqMMbJ7oGvGnZVtgdT6Mw5lAkSZwSsjJgJOptqxqzExgM+ZTTv
1vIW5Y095sgfv9j2jwiRAx81e8w3DvglT3+Pv2hsela4njPwS13B38WKpFlTDcvqd0JFGho1vBBv
oO7s4D+VfO60A/CZiq6UJnuTtjVVeplwqsOMr45ahem9OwhJP05u5dMtx/pBitF/HT1gCGcoM4GY
EaYnTAH8zB3gVtKDXKNDmoMYuXnslBYDRn494F0yVOzGdgWksjZvG/iqIHICU13TzuP6OJ98qmeY
qZGQNFmBD/+Iy7qZQUlMAGVjiggeY8PuzKR50m0OdmTwWJVBLSl6XrswtK7hbgt0IDqe6F3xQXsZ
Kl6Vdvn8En7yPun8/WL+REkgvTkz475x/Q5ao5KuUoubEyg3/U4XXMlan7jdp5ywuvaLFxKVbTyH
nterfcUOyFf8zRhk2uHe9j7iGIPp5ig1uc3TPmU/sUEkXRSPlHw/dzBYRRuypAOOoc1LGb4GhuoP
Jj2kFmJMApyrbf5OBWwVZXy5j0DGIsc7uGrIL4O5T8e0uACnxmqD/j4yZViAkjZlAi+j1R4oXJ6/
3AXUTfgX5SfGiw2txN2T2jRFog8qVgDbtqatZ70fpoWN/dlzJd9a6PM2yluK4Oh/p4RoIxI+VfMB
MonC+AjjdJus69Sgxbx57NyXSjQN0fruEchMpCldn0Yv/oazvdKMV2VIqfLQCVVdWV/AHob67yqp
P1RzkkAuCMojB1CyktQ+g9hanuDb/iRlMk+SxDf8CWetwWU6mfyLpCzxfP07GUurQDZPm9mL5cU8
IZ+o7hUZ8L8oYqNMu+XID6adu0vWpIOT1YM6aKNi//t5coSqpKmP6JJR4gTFLrNdjHPLSDhwKd3N
iVFrM+6LUv8/Xg00kEA0dP1Kff+GZ9h+kn05GOQZovLJtUgb8UnbxT740M0BgEe00tymSp0N7VHT
rg/Emcm+337I01pUTv4+TucLN735P0TGw1vsNhn+TBKRw6JQD8dmBmX+NoIEfFah/uNW983Ytlaw
X+RLU/lu3Apk8Sr92RxUZD1LDoiFfE0xVl253/1MgmpOavYVOKAvRbIKZbevaEh6tS5gPlKIdOTd
da/xdVYDGCKpq9bO553shSystjkvJQbUK+9Dk/LJyfHkvutaI7T6SchZ//ALRKdk/z/itlpmuPU7
kfBWuowk1ubljckYzg6sm5SbmmK12h18MO0L4HzWyRTWni0iQU5UEqgxhYXk1jTF/s7/jFwJ0H7D
kGO8Kynab+c8tB3WfL9mzu9jNbVN6yoci2TdmZc31t7wk5ocfIX5WOXKHFnzCowgvNt2T8AYoXsj
Y2suvzwOee08iy54N3+fBchJFzdHfrss5C3KxQApfT4iPkELRVLMfIcl4raUeG6AywXKQFSP43KD
kO1jp1nb0F1Vn54NPlHJDgHmJlEMEwsEWdn8B+05oChmFuzZJHZTaqHDe/+lKVRiWrOWdPusOccY
IohZQKqDxHG8SAFimMeAbLAbeoxRNxaBgb9XAZJ+vAnyB/kotiblLiU4xSNRpXEhEoRO/6tPi+ol
pbMfS3V3f/mD5QisoLqXZFfZBkZYX84VGeDbH8sI7MDbfk/jSuHLZ5RptPWGwXdwIPv123cSku4D
N+eAYrWkIJvp14On285XaLp6sGldj2vlcQNOSg5UVUk9kv2rlHk2q/ZmE9sOmDbeiWgL+RkXIYme
G5MddQPqd7LA9aMsSmk2iVUZai8fAj4Vm3YmklqBS3mQIGdIXhDo1V3REK1ttz0+W8yARBGIVdnT
28Khjs64YBtCq5Fvk7EqCfJOlLdiChie27QoNHcFw3b/VvolHOWOW1SjEb4zkTD/6HZWHej04Kr+
K/zM6a0JmkLawepv75WHN9iU5jO4iwAS0mXS44T8HMuFokO2AjDbwgZoRnSwSiCp1dtWp1eHxH7s
yw9Rl6MrfTEk4VZd74ZK2HYT4+OCBdLWstFw6u1+KRPeyp3V0jc0EhijvlBbapdtEgLy49dluEFD
B8HeBVFHZERN5NQw+dPmSipLPyrfX0qf01Nkbip/nr/IVi9pyXvmoaBMLnTL2qJ0w1hP5xMDcMfN
Nwbc3TW3/+h08jxS7s8G2FTQBNFuu4wcdKvacYZVnFdXBu3SHqDnIHVybps8OFbLqndKRBSS+sR6
+zeHIeNYZYxwAjAAPJ/vwSpeZuCwvhYsw/3qj7uxEwcgIOBG7THaLl0AQ9X+/t2jHrCnc9Csk2bY
MaitF55iNdvJVUKdk+sO5jwPZtulqCplnRMCAclc48yOL5feYtTi6UVTiI1KZww+gTncDeAVCZpl
z1BkLlDR9HtKSRaLJz0vgJDSmXZV/4snfXmsSRTT/Lm/HKFyLUR7ubHROJnvM2C1tt4Qgt0UU3D+
bf1jIkHUDTNXyQIk2lAMuPknzDmKghZk5pO2WTZlHYRwGsLFDRlzUeIu+yu3vHt1Id/hRI75rboF
Pl3PHZxPGmfe8OoEXy4yVd/gZYXJfOavldRFn5BjDr9QZ+ImKJwE46yRF/N9Ut4yIfKnMxTF2gZ4
8MMkUGE+LRYwsLF1Fvg/iTeLtRie8zdypcOeamVkfXRz0YHWUJ7IIlTOIbeCLkXEmVfpxTpycjCz
tngDj8xZPMWhtU2K98yJUzdm+1nWj3E/asBKae8SNZFpYQ69gDVJltQVapNzY7Z2Pjs8gJuzkagP
LZEdnKVfSgvHEsp+3jcZlmFdZvizwU+/AgVws6i5V+JAOFTw0DZgSYFi1zUOYgU2DrCFyDFZMsM2
gS/J0cFO5vWLLA7fUZK3qt4JPWEX+sBA2hN0DSStb+9K0HNTcLI4TDsIZDFPc/2xCtMrJrjFU7vp
7y/+bHrdqdJpFYKc1QWwU6mMzKaRnf1WWLTyssTmKMK7n18CCWRBucUlsQsBpI+3q6Zs46bk7FUQ
OSl8TnC/ZMSPyq2YGuBPlhMOq+QN8u3fCMR3ynJd24DL4zoMgC6hQk3e4EBNvrkyDRyyxg30Bino
hmdCN9rlEjdDmWrlz9v7RJK0XPNOlc18Wl/Zkyc2rldHm/bIU5nnsbwCYAXuGKVa6BZKsOutSTSy
P1OVHm6bXaBlTdCVd3vxqxF9geJPa3QGsEn7jNz5evZniI6i7EVVTZlN1o64dcRUOGP1C2l6f4UZ
LDdMiR07HvVFhBvR+2qpvo8oNYHiVz8ePudyk+eJeFZexeQjrCx8uEzwzhRZZvxD5NCWgslvRggJ
5sC5San/Te9KTTR1k1McwaVa3YPNqeKHghYYlHDlyF2h/ohH7+1NvwNIIas28cwpVfXiDkJwdvEw
wY1A3kjDF41f4pIxAEjS0T+bpPN5vfnHEmLkNOfLopjNda/o79joa3PXy4O3Syc/6yPuTqAiuLgf
HtAHmJLwiIIy4B/0bJVP+U4myOI4aIHLd79EqztqBZgQ3JLRq2bSr0Gx0VXB2Npm8rNYB075hu+Y
8kH4uTrtlcnXhzay8by/B6/afn8XyHAnp/oLanx6dwmtlI8rHxHE5clMaist55weyH3uHLspxVl4
tcYyRDUgbe8ZSptLlPVpYeIp/TwMA8vMCJP+PM+rYnHrdgtACa6z1aJIZU/HhZk/qxWPwe91OoJE
Py14gHSNOK639oW6XCc8v5+fS/nBpPyxbRTJEIDYnP6ckheEzggwhB34aDFOtSE6/Bkd4JFWnRkD
gpOyXBT0GzSAQ7vxOlsSKhJvnB52JMnFY2NNe1gPumLW0stZq4NXhcg5z0yNBIxBXquGBsidv7LK
kqhPB4ZfroUcGIQdsj5gi77PeUkGdqI22v6sE7V8i1V6tDOv8jWcLKYzEGXzk2pZ96Y6/YUC6oUR
1gRA5zOlBKmUsG5QM69DvQcBkLVYyRDT5d1+nErxtTAi19W8E5GWLejARb2xaMTLcNgTA5d0p4d8
HMNiPPZF3h4HVQPbqjcki0svRWHH3LH3LFZ/wUNPbyso4WFet4OK58whJ1ruag+LcDMeg4Nbq/Jt
34jD9HjJv4Fkmm9JsfbtVrsah3fmRQ9DjimvF34X6HTvWCwjhkJCGb0/kNuvG1tVYOv46r63eECw
PZso5y9iSZnXSOAp6bQiVGKALkTRe+RkB8THKxETQU+XiVZskxuy1UQSlSr8F5FjRPaQa6L9FWYm
1t+GKWqMVfOAQOPTJ8LpQUP7rSwynHbymNcDKFQ26Wmp9OCgLOMcFv8M4c/SIo8OovnXG6+iaQ79
viZW0jTcB5n1dAAKYDfOl/Sr0G2klqvlZ/b0uxBcjD5awJuGO8L6UA7BhuGVAc99ZCmQweJ+XEL3
7hbDVMV0+HBAoi2IKkvMiBKw4K8C99H70dLmLBZuHxpulBOVaRTY0Kn+U0Wk5s7vErd5b7JYy3D/
TIblzUO1sJzW48f/NLvN6/dPMORro9useYNFu+vSj9oN7uy/KDZF57z4TD8kz/8fMQCerocbzw9+
IZbyDKhDkE+LPU4eALgQ6eDIVm+ET45TjjZGmUoaq8J+AFJ0sR6QS2oBGzgG+SZI1GMhm7qURbr2
RVXysmurhpB0uvb2/6qNEbgzKfrOGH7DxbxtkKZw3iWGb0+ZxGBgraV+/rHfuBz90tRriGRbfbJe
4h/dAIiLuXWhcGctuzGOSAfVOj6nDbLwC6Yq8oUPoqjiHEVfo7eep3fxeK5I38Fz6JURc4D1u0az
FB9tFu13vLxc62rZ7muaURwG9Nq8EUyaOdwdYTUCAw1US0g4V7d8lpj0EMjyZpL/i5PP75fBPJ+m
xr7eT2FGEl0fCq0XIxuxrX/Av8KT0L3Xfnd8+9YU4gsehcPdyjKAAFRXHrZ8bDJ8eggO2WVIweNp
ggTYWWZn336sLiQ4KEzE1ztFsAOsEuzZg0xWO9vHWUz9V9IOvn3s7Yg9EuA9OcP6C5jwuWhFgyFv
crCfori5HYNTyJVnjg4Z2g8ubFi1Z3jX+wJ6Lf2o05W0CXhcE15mta4QqrDJx9+/H/ueuGDP5u8S
l+k5/NFFmUzZimPONS/1hY6Jzx4AAh5KBGlBeRWarA5q+QyaqZlEAyhObc3ZTaVlV4d6KU8YtQxI
58JMAfun66xk4JBFYU22I+PqXOwvO0F7N7Z74dWQK+d0dn4h1FLue8h2duuOXEmdRYZCrtcgg6i4
+HxQd6SgvMNZW6KG2KcJ03j1S1aLEV68eB5Xj2ogGfkw1hq/ZeVOka2vHDyxRBkcZJ0H0UpSdVaV
TPGaHbK9dpzbyatNUJDVX9hkXc072VmOw9kCff4aruz37ZThb+Dn5rRmIGhFuedYqTQ8nPkVvESG
aorISDgmU4w0Ljcact1mgurLa2ahCXk0u0vdTW91pL7yKXvscWseaJLfS5upXAigpPDOh1VHv5oJ
X3TINMwWixFdrC2+N2MkSNBmrz7GB/OMwMzECPH9N0FPRIxMFZfyioEMGB2dJAYBRkA9c/akr7AL
/+nDW828tptAi4ys5IvyUiEbxu40zgxbkU2ped5osbktg1jfzJ8CL0LBPGNXabf7YA4kP80TafXU
Zof6VReHmpFcIZALLjp8kEENga4GyGtkECrbmqJR/ku/rV8TFdk5YllU8GjJ6YxP1DLVHUSKJZwu
wZU9Hur8xbKHVdp2lB/Xg5hQuJFLcUio0Ma+tHmLxDEQEkCWQUCMXMRfks6Qq7oycjYLRdqafulw
U0gVBIZgCSC5RIIXHKlmmSHTwcilFIZHFrHj2bjK/JLien1tUg+J7VlWc8xGTm0BVxF2WLDoYCt1
mYMmXQhrGYMDnIdUUHIN4OoVhVtZNm+CoK/HTZDaxtYuToGWMrZmE2Z/gbL9vwRP9RzvLwWbbamL
/EZNTZkkVDUlVXCbTdEGay1u9bMl/nI3vvkQWNwgnTr6AgK7qR5Bs0dZqJx2kVp1YAjhU59TyDEc
ffTjZvUPal6d1NPpgM6cVBRSQuPA8rhC44RWTEZmlDVoXBIt1jcTSXysPhISnAe3prLVzOIlnCj1
p58YvnXDF/ZZ4rrDE/bIx5Pwgb2wnzq4n6iH6lIul0H4LoYySwbN9DFVDIJOj+9n0Aaif8hoSQPL
91qNyRfYc0B/G5T1ad3IFzSm56rLoK+6atpHYF6ynlWLg9M2AeL9FuoeT0uG2KCo7I1R5GHD9AK2
gp90OQiLiRbtbkv1l83Plfi3bDaCPKTpW8PWp6SrwvBvKrPwatVPmhUaGBr3GVrSZFW3EXALBSgN
MP0eh27n0hPYx9DVLaeukj387m6WQc8u0eBy0VWQ+GNVUd76R1clWAVfc1FmB3/ZNjUzUswUNeMs
7Br3bNHPlnV88bZaYtIJJHPLhrrrMHI6BGKpgwGu3zBsbAWV6VUFXo/tEBsat5+78W3nja37JE+r
dPeDWDYkvlFpobyaPXJ380drEakQm7y4HK0ryUOOvywlyt6dSy+bYQeqpxVPllSy/vQhOwgFoUpC
jGoYtTQjt0mJ321guapBJI8kLkiNKf0dYDsnuZTOa22skp/9qXzSCtJtRDuXOM7tjsZnNEZrjtLx
v2VyvV4iIVRA2VZk4ckaC5gNDRlsfq8fKP0SbcIB0K87nko58p80qSHnqMKLVmaEZaMfLhza86HY
2FUDksD/DGwhIscqdOhjrvhnWg32UeWhHtlOpXeAYm/iHnUdNK2SwpbRoJ5KaDFmpWjB9dD9GMYf
8UwSlWmpu3G/bZmLyNTNfqnrcrHPndXV3IgLHMfnGYqjtVwjABXCzgmRi07SmnGG6lXhAzblsBZT
mZuN4J5fCbuDklS50sV1wlpUTOK0UYZA8KU3IhRjddvyKR9sjpKtxP0Z71nzJUs7SBMRrisbMi5x
INBUO0uirhLZxl2jJS4IMuMF0M+xo4yrfgOzwFCHKxMvkQUCBs5EL/TXWp/Yi/kGtZqDmkFjrTfJ
5SLoApTCbG8pZW4x2zmyxsv6UBwTskj1FUNrGWTqIK/qUeTaF0ufMzYYejTrgw+ArxC9ApTbOblI
djWTQXtoS9/4AcI+pHsOb8gVtT4XD7z46IRXw3zDF3W0g8AGpmySAjgYT+Hj8Y7D/kd1eiBrQKg2
5WKliP50uQYOUVDtH3f0F/mm4TSaDEcnjxayHSxqK4vMKeyudMp2Tk6rMMj5+XC/FyAGCCWA/uSK
ZcAMBy4n9bh2H31M6H74dhXJCKnjmMSXl0veG/RpQklaoGhotQyJucumic85DmevWTq3usqm2VHx
u5uLFT/MRur3nl4yjE1yrlaZgBdBzViAwEy0nzy9DHfBYJYZB4UCgDV8DG6n4K+E2lUglGrTQK0o
9bONbT2XXP6wVJgeSr/JK4slm8gbYAAdvUkk5y/Ne9pL97Qy5XVCMwSPYM+uLU3S7iJnc+u61r7V
7+w5pSDq66M2hxn3zP4mIZUrWqQPT+08LQNA7t67h4veDxkl83mwQCK0kZykrxpJsODzMalG10Mw
PpuLcwtDxflHyzCBMr3EC7Swy8yhs/NqCf+mk/qktvs5v6AEx8e/98fkqLeUTDTZBvz1PyfW4/uK
+fw/m1Rdni5r0X/6/1cPs4YDiHebSfbgu5skIAwYmImf8NK8sCHMLn1dPV+D6PwRPc/2bSv+9E7b
QQ4WeP25g4J+5lkizxxm3ODKr/UAQ2w4m7LWR/0uB7TzH8lBHe+4hpJ4GVJbHZv5zxn+azsopPfd
n3gHumZCgUonb1q/8q1LkjqioClPBOod8u0LnmGC1PS5lO2ZxrUNtimq0c9vhTvyBc7VuRJ+StEI
Cz5PRdJvMLh4rZhjy+WAsbva0goocOSbkBpSKAwbTB9gAfWLiCaPaKv8C94w7d8CpyaI90V8uHEI
VbuhY4Fea9xzyseHVH7RJ4iUunEV/roqazYl6ZwZuGsS5kBGJ34P2pJkIAujH7N2KrtzaNbL3iVe
Nal9GjonL4aFKPHEvmaQhLF0OhNUO1BEk5jGw/kaDWAwT8BYauNGaMCC6a7HWwmqNYyBl80BrPE/
9o5LZ9bldRs/wxIfO+/pSIi/eilk3Hc64p/g/YgaTidxrTsaXI95+WzL4G2pwB80NDOnb0kXNLye
q2V7n/mfK3Wrqt8ep0/B1MxvCJKOjqwtun8gl3LN2DhLZKvsU7zpeDQMBBypAsNDYYT1trPjc9UB
J+zY7vXESFJ29ykRuLsNJRpGBirpgJuaOCRb0r/FD5nPQS95U8siTVZlLkN3u+IiNgALv5N3xbYg
n2EKNe9DlKwlswY6YKXs9p71Bo0bjWenK1W4pOupXlxwIaNzhhvRGmctZt6PBtzvL51xu1kGKxFG
J+MHvd02Xs4ghECl0deGaIYBgCBevbfbBM99oxjtYTUB8GGPP4Rki21K1hf2jbT5FSYV5OYO9V8V
3gm7Vpw/iE3XMMWkb23njkRSMpD0eXSGbar2tJrJeBZXu0aU5Wi41ah4pJhg6neeFt1TlbVokm9n
qvncyiIhMezTVUABdKKICzoytQQ1+7iD4Vk8/TQHlLLcqABj/CksqmYGf7CGlXilucaW7DSvkdSX
B3y2FaGp7ikNMyoX7tNAJlCW59Xpp3600FLDMjplsCVLL4gyNFHpGGTPyZUb0SiL9HeLnbyINxKj
tHfKBJ47E+VXiy+NVTXXbIjKa4UikxfOlmseE1sFj7959Ti7ZgfNNiikwWcxcfhKRYMJyfMlKPco
jkBgwrLa+Qvx9Bhb8YhPhb5fqcsDYSxWnSTX17mlJoeByEhG+gTkKfB1tULZol1ucSf9a36tsHtz
eOf4TgHWos/Cffvduye+nJ0HNQVNza8ClNctaIdx04wLWuy7drwmbPHPo0EJwB8Udnzz6Ip5Hbu+
VNK5xTjPUTsPsPO90Kw0m8yuCVmgStdu2PSU/cd5i4S+ZUmGV6FSYfDSvPbteOblCDYXhfGeIvNB
kAlz7TRevAinLsEjkbJm30JqehcAA+aS609EJyvoauRE1e4xhej7CuDJnee+x8FHVvJd/QlkO6RE
zmW0UEnmH6/lo5fQnVVyxW34YUOhjbspjG3m9uAkLc8maDiNCdLnqluRqA3Dh/A4uAjCJbXwn72G
EAOTMZ/N91wUr5ccdlRlu9U/gt1/ruVEadl9gENKYaTx0KeuEMtLpbwfbTU1x9U7LdW/vFbiTICp
6oDsZQYU46rNu/J/8TI2h/tu4n9N/qqK6jaVLcxlVsIU28j+lEnT4O1U1b+PY+9rhcPoiY2QgZ7+
zEJOZSX0H47MiFDeq3ImayFRrYovxDR6BuoYBsRmbN9WZhSWj8kANI4+fcTQ4a0xrtts42WBpzac
PikvjW7XwgOPmp6fLeAbLSREncYk74p1JgHN0FSC/a2y4CMN89UWBWUTDCoUJFht+4JvzLKGj3Dl
e4AeM30TPeAwo2dhlg3DKe+EkCtOepZgrFTh/hjhyO1IPDAgTeySYDAM7nYNnim4GFTuTiQ1UcJ5
/+VT+XTggmcFom02jWSDJzV3UrUDq6FyxkZQLYV3HLo7axPcbID5mvowgyCAump4QRdAAaBLvf5W
Jo13tCDqj5S++Z2XbhilydDmJ2D6tDxGCigQsizTTCjktvq2fk8TwOQgCdDG9KtbB7lp/hdYuFl/
vUCCbCRpAvko2IvZc9gsPuXCjjuXztLvSxm3vXIEJrgCt064pJFPqmui4STyhnJo9Z5BtRrpy9x4
eKNe+D0pS4uiS8p5CFW34sBWbmlpsMTfBT2dtd/Es7ZOWnq10FNwS7hxRugXBMkWlZQTk9eA484m
W4JRVLGAXOh0Di84wP3tsePVc837sgoYfGOQNt6wRi0laD+cLlqbooW96y60KN7oZVn5gG4SFsVf
/2ltAy00n+mYjwRM7xTDwEEOtOoBVvHvIPkWo9g6Z+M404WC7Ahy2fGk6qY0MCOrsAbY4zy9aZHo
RxwknAmAZEXraLRBrK0GhhwyNLiOpCX+Haj5CdoHJ2uwB8MZ06zq7J3SgFm+DeBrq6uom6SZVfQS
dVkf52mmggPBWt+Ul3/gdeQaNXw/bNjC5OMZEp3hA2hYBFlpGm28txqxtk8dqIYEJp2cSluha5sQ
++RWYKsSUf/zsK6wNm4Fql4Jl5aCkRZ965TmoFx6anjtQ/xScl/Nct47oO+TKHGnMToGwwD9AipW
KWWB4Yu9YNXFHltyUsEpvYA4wTszNR8cgqkTEAHs4sDdFou2EA9Q8fclrPFj7NP033U1mYz+Uqu7
77oUi/+OwnVYvIlva77TqXCWUmfZzIaDU58mHEVUW3uGaj7ncbF6RPKivP6akhDY6iFeY83MvDZY
qDdC82fpCmyUH+W28v7iUvTgX86fA4jJYz5a/3TYLNu9zYjkUKaPL0Y6xVZpCSKrokjJvq6XlOJu
uJGObJQVnZiEaSuzy0Bmy56OfsQs7E+UTUuZ05CiKT7kNaOY33AfIUtVZAYOcipRdTKwjl7oIkt6
YzUJQJPuYTQcy9v3N3chjU9zisAjZ60uhNdHl+9v4PmevQbCmutKIE93pUlDm1qTKuwpQvTBzxSV
M/XWZeZ55N32Fo4HAzBMrTAlOODGv15PTn0FXjej2rXQwrD6MLKJmscGOsPvhAsKfnKz0SwgXLQE
ynSU+/0Bpcn5zU2tIM6sdfKgt1PzLUiFp/6vbm9SdRsmd/pZ+WXHdV5dnWpdajGRdxPzyjCF6cIH
0c4psGCUrTdx8dMZ8gZyPHzQCJbekizjWQu672FRoHc2Ed0YhwWg2nqrJGRxg1BE1iijle5sFDUS
kgi0s3/us3iBV3+GwwwyrJP1wsCcjiMCyRiULB1oy+nPACRBr8ZWAxfydAr9boPPkUakRwf22iuH
1UvYWFDZFMjhNSLy6gE10Jlvkf9zRNVFdZZtKQKKIY7nUGP8V8wbbebehyG53F6sdRdMFbMokZdM
pTQCQg/U1mBqqZjIbrMWFpqFPZFEKorkgrc7r+ZCxSi5lZRgaSQXdPfNofZtm7bsCmhg+y0XAeQV
TiwV9iHorigGKPKLomOngWj5yecUyKKDJ0cys38VYxjj8O4Jac7wnEs/VNnJc6cmbRFc+l1O5pz9
1m6rtbIS3Al8Ptc4Pigc4dkyNYoFwWIinkInnyOcXWFle4O2kEYDBk9akxNuCAI+0ss98FEeUgr/
djFaCE0lwixW4RsJ1s6raDfiYSsTYm/vH2G3N7X0EMtIf3T+rucMYOJgvs+CQvzuZLO5afyNpBeM
JrRpZlYKc8kn+s3oP9JtSum2fDUlwzke6fERFS0Gvhq7wFZnh9oDI4tPSG61G41gre3UnmL9nvMk
TOrbFKWBhdauvNdK/JwnEZyc6M3keO0vpTD9YzKYIw4dfdeFsk2q7Wlvr/kwaa45SgV70uZhnCtO
Iwe5ue+0cm6CJrrHijB6uI8r+OBKVet5nEVK+bppAl2aNO2p/UPTdDmEZYCPz//o4F7k853Gf+LG
8+N/r713xccuk2ufbyyomVSWAlT2KS/drax9MSGJSSKYuwlTUn1y2Nx46A8bZL+Jp+Yk5EkcotaF
egHA81bQO+CEAe6KCeF8d6yAEtk+7qXWa6FQ9ucxqKHifERTiIgWNWZeesrrB8k0dmbNh8u2VLzP
J7nEA8AKSfTcYsiZLP7Qpozoa3O1DjrZ0llNWOALYiuUYV1GSfeFPOO4NgC6CQqRxrUesTb4PofB
qaldxppd4UchymtL0ZCC+ilOrJLJwEhOWEJbOSFzbZmfnGaFpVY9BIypX51KDslTYGXa+kXqOrkw
scVFlKeQE8pMKv99FejdXRnboOY3b691HRzF4bPNqnrm02dFeM89MA5fP7Vy2y+w4TbBrjoOSf0s
DtbWDGj2aJe7VfscI8AxtIxOxPIf8E3kL3+goJsZhoyjyhE0IhE3LY3zs8xjkYxa2DKQtvkLF/HI
xkrw5CPKX1+G4y0d/VksZtcLILUe/vbfGXuItHoPnFPtZpzT4HMTxWnqrtlY+JKftQSOcq7Q8enh
igQ81Guk2X3el+JcfwCkwxaLjOYY+kI+tvxnGaKrFU682pA5+pjQieRLfUtsYl6FWzR5S1MiZpL9
RjCWElbCeI5dejNZ64KGbQdlE5IBbGxdR0JZKy12j+AArQmvF+UFmTB9YXm7suvcgtB63ui2hk8J
xjiO9i7Crk/jl42xgnRWxF4vGLnRmmeP9VnoxufAOJa2JKGSEOlWR5XRZtzrhcP0kaJKZZCudYV5
DlhzKpwsr3m9zL445Df+OoVBVMJSL208ai4sNC0z4x2Pevby6VUiIWC7Wx/K8lrPl3XMf/Dd5N5a
6GlCOYFx9VD+B6owm2Gct4Za2fagZBjyPelD1dzfzjpH83m20/cPlKHHy2F/kUSPMs0/6CvqHQYS
mosWwLj/9+THY18teB0h/CdwcFrTPRYdMwM0VPb1z8BgfO60xIwfGniAEW6QI0CAd8BrVoAMOv9L
wSQz6yIkydE+mhtvjWBnmcBrY0Fg222arYsVtANGUvNRepq3veZKblOchVjmbPH/bt+34cb2iQqD
bl2ZncH95+80ZHbluR6i2Ht6F/cMRvryOaiaOhYieUdOF9PiFOPohyJfGe3YjqDLshKrQoWpJrmm
SlypdxAUgMf9KmhlO/+kMFdAmQgY6/4e8e2RzREx8l4BA/Y/Jt5aOoxqSWp2CjZF1Y9Qbf6Rdsla
vdfdy5gFjWVjtkWwcI2Vq+l4G7VmWPwPduey6PrUqMp7w8I0PKBuzWGugJCtceVurrRA/W/QaK5m
eaPDRE2wvkGxmdiyWI/QAS6x6lzH83Vfzp9/3YXrfB7tPVCM3XML2OhLG1yRtdWotUWe/R5YgHrE
XUfDIse2EZ4VOM9aNARgXwujCltMOKdSR6Kn4a2y7j9aoKhWRP9f00lpykVKb5SQ2tbVsK2ofhsl
V7jws71/BZBz/cnRVNHd/J0ORbyyjprSw/VJiSTYFHG8cSiFSP4OxL3/yTiqoQSJe98shabelp0p
G/BDvOrpYjXnnT2/6iDN1sv9O8TDz4Eh8P2Ojjt0T/4ckZurojYfMP9LQ4tJl/yqg3Ug/csHjnd3
PQXv4mUKsyf5pIWyaQTGpS3k+MXQZZgJ1y3W1Z9cw1CppHwe31ByZw53Pl8TPBTarcWjkQu/ECQe
rvCG5qfLY288IyoSBbNUWaiHrcvsXWY4D9jettvXrRy4zULxA6SGFxDHPU4syPFla2NOadWwUduc
NdSh0GMGIQFOZdffBbxg2aQYdPLYFdvZX5xEERlDwGlQVTB2Qg3x535nCuTp4aAP+8cCNHbS071n
bR6eXjF0SRiYKBRVdXBdRbgeW8B7yoQIl6EoNeFdm1hERWauwFVI+VddGte8UoIi9SmHyOK9pHeD
2t0YIpHIYvCA3z33bRryLEfYppGNjv2wmYY6KOgU86UkQJwPnh+HUOFmm/c+4Uuj5gXpBDkBtZLV
fcDss6DJhX2GPSUIdViY+5adGWONihj0gZlCnmqwt+B7/511FREbMiK5tKMxWPCxNDuvH0kh3rJy
DnXeQT4lyjPJJuxaxUybJWmUwn/gBE2/XZ+ZQ5/DBQy4lkWvfhuPgJvvTRj9h9aXl1ajEQ99y1KU
Puh+MBnuluWyShpIGu0l7n7e/NBEeoR0gyeRsutP/DOd0jACmabbu4c3gpBTL0FSryKV6E1BwGnC
3rblI33zTfAbPUetqvLbo3+TVjslz35DFeqLQFHkiKzstvaZerJyTGfmgRTgleshZeIJGOXUSW/a
C7+toYdSpQHTkos1DMo5L27KB0g3z/jREuUhMNxoxjXRzJGtgSvUlKXnVYM9v/CPzWP99TA2bEc1
MvNH4RccYKfwE8eYJLgY3PzmEynAoJStR2VoqrC1sUA3MEs0Rx67qU1VfYrB/dVBi7sewv1i52IA
oC70A6O8+aiYhVA37cer8QEvHKapoOpaCKrcPbB6kTZTdfHuEV1euAn9CIjpkFfSwgTlaWlsi77W
q/MtNH0poEBUCYxddy6egoEbSlFGubcEzyGXpk9NMRfatBg7Y54aRvnIeo1fpTQTMFT1W7akb26k
BAAyVbe7pnIP+WOECVTybk9jPNEy9gVHRKmb71VSswfIdWNgtgjmp5yu5pm/ESLkcDe5NpPhpDTt
z9sFxmWTLJVluxTxqUOyTnt6/4VjVPqIulOL+rrcszOnnit5KS8pcmdLBCEky3ef8zNcNs4oMdjR
0PHNqQvv1L0C0PiNecbdDUTjCIOSdP3zaxRj7lzilpupovy/wj2Y+HPR3mgC4cmp0UUGlGgyINGG
bEbYR22t0CROw/b79GzX8YXh7J8lIyLGz7VYrdCotpoH5VeT/8yRqvE2qZCIp3nwvs6bQKGwjzLq
xJAJHtGZRWZPmh3ri5YySNROdEpB+FUNli1wQvjE6vZsqdcIGdUxDaQoISGuaxlyfwFWiWxnxYoh
42UrgB+nkTYAtFH2VzsDElj+jzZXEMkEYHtQ0e1Dons9nJkjwZO5ZNCLSOFrSbHVTfIbL8omq/D/
/0S8Ci8zCiPB1en9LJhPfpCkwrqkrqBxnKXyQuEUx1Ho1/ftow43lz7AWS2lExy3RLpqaQc/uXIT
rI7fJcFSkm848TnoL6D2BoqAQJttC0VKTPHBHyEAh/1tSZFsXhDIK6gbx1p+Tk34MQWMCIGgkuPt
WctfG1fVb81L50sfUqQ7uLS0IqgOgW1ILb+RnFuOq/vDwPrABHXuh1sXeM+cJTiNfdxRTwgP0H8m
TYDD3qDdWY2oEJbdeaipBdkUeAf/UzX33zjSXwTzA/XhYKbnMxatgTe2vEMXZKmhg3eX1oAINhT4
7kpMZcyR+VvYndTbMap+6YE9m10tQqYSo7UDPOju02QQctK349oQs0uzULXifG0uVltRypNoM4R3
/HgZwOrQgqoNJe2PXx3HXG5z2i9RCH3SoLuXBGKpJ6V6zrojZUql8Qgmxh2DtbIHnwUu+xFNSq92
5LxLV7ewXT1SgR9AEecOUVnmhxxZaz/jZKQe4cYj1bFMI5Vt5Jtyhe+ZRmYaROXE+RgxtHsGvdP9
2LaDr0I19ltHhNHHKkadzKKVSFthipL/d+4+0OP9+pWRBF8sCpHoV/f/JMfk/8S9KsZoXW5pH/G4
eN9X/1s5J6YPUBzUnpz2hnvTokDBZUG+cogt3cPjzHKT63BmDAGKEyqnKcyVbgq0XT/ijvwi5qkr
cXqiPc9IzCyVCRrO0tXZ0Rg+fhnSatYZeRiy36qCiHKb64+Ipe8dicUTtwXpG3WqXagQbho/poLw
KXiYF7oq3BtgwOdatEs9iOZEmJkcvJP6kwhfsUSv27dL+TocYoXbWittwoz0Eg/u7kpFX9weIeg2
i6oSyeeg7NZxqV/zR2epqpa7D/AiB10LXdfBhgCs6Ke1mSEsF/0VNZpejj1YWsxEtY7YfEoxnMG3
5PqdPSWhvLPfevWqPYYuVLKtxSvBiSPzJ529aoZkymONp3AxNiWSqNSZwNMwYAoZXQ7mS5W9Ks46
BbEQ+k3HTGZdEBjvB5654vpAzDkJj3ybG+VDyNuQh8Kq8HRjY8v1xNcsWDVdZ2dyldBCOcU4GoCC
9HmhJhP3HUoyopp5Srl3aVmHzt5FTdyVdTVtP0vkIkbwfd/5HVcl7GK+a7uJMIUTNx81bTROGDM8
51uRwrc7XRjj7q1e2VU79KS9oxRJgZIDxO7JBieGxk92dZ4HY19eEhAnvrNEVDfsAPoKnaOEBpQi
aY0VZZg13wlYoZUm8uFxwC8mlLhU2Pqn1K7GZNV4QgeaSJ+UZemwUkE66rBLjffKM9TWDhO3dXoF
CvKjA5OK8pw80oiqzDWuBB634zjMZsPyLwTq7FN+tBH807S8lC159wPecf08VyBbg+0ezuJZFpGF
+reaRq7E+UOEOfDIpnIksu9HrMKG9VreHmvTrudl54fJz1FP8czsBFRGhCacCcovG4+CJE10u1Td
2n0jybVLK74RLtE/VG2v0cQvTRAi0NW53qEExSnuGFbXFgdF364TvbqQdXmo7oMt0b+ZfGC0h8uV
SzrRAg+gqFs+Cva5rIDGt3NHmqOeEW7iFeEggipF6om3xE3HW3X+f7pGu+NNq1oJ/XHX2eEKK4a+
kYR1yTG96POI82qvdT2Jofr3AZm6gtQZhH60JDiKnMzb4kYmKmXiwpexoohIfisPp3Gqgu5WAvqD
VsN9tlfw9+c0ueXfCdme6HqRflP2agyIxdqbWZBeRe0Nfle51dZKkdpoRy5LNbGo6Fur1LZM63vk
xWdyCwSShYYEWpXb46HisezytgVxa/3NWgNqFV9+7sSp5goGCadRKVv2/HmnYgYG00/6W0v7TfHd
TPcVGVHa1cxgHwfGLmUbwK3cMOnMhqEsQ/mfReKu9t7QSkd5mDssdjwJKN/Zc1TnukLeW8CU8Z5o
X/PBSBt1jvJ2XwzfQQ542iXlHj8ZzVumiGVxnzZmEi5/0uyi0QaMvF+OKlxiPb8z7QZmv9K/dOY1
m+bgWCF2TXZ0L9nIHpS+NHmi3AUiy9WIBsZpTU4MGx9SYckGf0UlRIbzRGIIawO6YtwDfzOuVN0V
2QL8s9ikCIrXE4OSqeenqOcY0UdFXGZ3msm2iXkkj2P6qcHCtwDhaOj9rU1sDkh4muA7SK4uUbak
vGPTZgfKko8aFbTELG7fN3lwrYKo9LaIYW9yTTcHZukMOskkVGHzcGfBp2AgRHDTzWdIDVuet3hO
vfzSSFDYvdvSQpQ1Jxgx1n1oYe0jrps6WGTJnAngg5Es8BOCavBrb5TarusEWsbiORgQQOYE+ZEK
E7kO0lJXdaD0LCepdfXGHYGmW/YfX6Fz0Hlm6I88m0yPvNQKAza1zSC2/gjoiT0pavIUnP0oQHyn
vQr+EFX05laj9hQ4z45HedEb2Q3k1wfjC0VJSHMVuPn9v4yoJpZdYA3DdV4AIGSPN4boLQ9OeHlm
EHLKN9GyHKQd0RgVQMz42cR4xrtWpjapp0fRbWH3wj3UXM/JW2QEAmMJePohst2RuGgY4n5WKlrK
qm3u/9o1/Y1ZECsuukrnPyO/diUYh7F0JWsCVPmfsl5K/4xedT9SuRYx3MDaNSCSr8JuOPNa5FLT
ZmGdCY77GpOOQcCBApIKYluK01rNS9tI1Hx5QPd0cAeDxt6U5grd8eg1uJZKcdvEKpkgF4asb3Ri
Rkx6cZi96+cmw24GRZwWCtudy4G3lj2NVV0dm6dtCZWnKHFB4QrfhZXY+vXG1v6n1ic6YJL+UB4n
mKW1h7CAvRTjBmLPk4o8AXDcON7hQJ/T0zu5Xm9VV36xdzlXvJ0gQHJnqXpn6B6NQzXPpiOBC+1e
zGl28AskRaKRTOUj27Zaf+yWqoISJDGvC9fUqSyO1dw8vqerZoo0bpUBcOiNzSd0DxIhJ/kp8NRM
B2rWBI0eF8gf06Ga6baQtPJyS2RptgBbm50qwDqBGkhg5oFnd+I2UVYJ7lux8euGnwlR0FT2v64i
R2MvMG/3PSLyTr1hVD1OAdxXOMwF0k32rNWim1yuGEBLV6Fyy14G90+zXuhGdRaXG1Ugb+kQzrWn
A+8QzSn0UvC1HuV9ZKw8ukw5iq2dMk7GbeHf0oVzbriIjO/62rRW+gSScNjDXkyEE8TkAPm9ro1i
7C62vXQixwsH/aI6iRKVWlBhSaWnw+gfvR/9sFjgb+sLfFuyfUlN8RQckF3kM/GHPLzXeB4uM/gw
jd0POmu2wHlpq+qNMLRxvF51tx6yN79MdJ9d6mkWMYO6N0KMKd3Q6P2hhBQwB3RoBdMJkgbCd/KD
a7EDmzXu5Xz0pRRirTEixLqAztCVr/49P9xGc/zRoMTI4/Qp7/slPI7H4yad4imHCqDyXdTo5Ib0
qnI4xL9tb/tjoun92dJLtugUNxXj34bNopPpegZasOArlpPHW6eII7Y/kxGWS/Lb0lFHgHXJBET0
yfpgf95lV9xXd4kDQ+INkrsNYW+WFtJyla72YRgzjYHOUAqzeMGy8Km6CVy20h/TTZVpsMmDBwyE
SmQ21n1mdMGbfBGXZmrALWVFSoVzl/CXqydYvB8Ecs6WFzu8wRKuAlqXrGqIGiZpYJyum56I0Lsl
arpeHB+dWRJZEXe6U+6l3Alt95WaaS7D1ZbbWTZuB/mehITN17Y8+WLJpdGhY4PLwPRntq/sCBxS
rZmPJXkPPkPzW7gBvshGcmLceAfcz0oHcP2ZUWNZ3Vl6rMW08mUUOEhWQsWlpaP8MKwstsJ6tHdX
mvo/BEf0td3cwbFyGb0r1aWK4rljf50CUpBkYtKpaujPO/8hVbQLMhbHdwqTbp0NW7f3O52yOe4/
ZAn+d+xXvYu1yqmnosFqVKHvQZ6rh+GOyt423RgAGRK6TCTtcM48XAMA62zeVQsC0hylhfII4H5Z
/Y6AQXhIOJQE8fW50iv/qqFq2Jl0Aczvh8aYwCi+aPKGa4edY5IjhQjnbV8MNkTsueUQlrNA7K23
dGkj063cuHwhz93OOXtBKhD3DTkmFryshDlQa7Hs4RtzuiuUtKP5NPzjypQAf29Oq3Wg0bwOHW+w
9i8Yf8zG6BMVV9wlUc+BG5drja+kxb8neVkAo4fMDlVIxbi6EH+IYKcobL5xfkydoMmLap1G6qw5
lc2BacZKe8ORqXrJA3oucbPWZTI/RwP0mtuK6UvRtQUwYXCxzDqE1xJFAo0A/nrqyvcK8Mpjab14
1MUL2F8BwRMob2qKzBP9ZdxN4SKxx2312V8T75XpAn2oyy7rq37qkkOz1L+IlsldG7yGseBiaALI
GMi3fuqKZD8zxr/ScttIHyc/uaQd8NzK3zKyMd+xv4jQ/qx8zSRms1zPHVao3Z9mjHgzvO3cEMuH
kC3+NTfHfPg5gthWaBf2eYnEd234ocT0k9f69z9rEsps2GT8NaUOQ68fWlzS4NJplGKvaYvbH1xY
YXK0DMXanfTHxKasFJgLmtY5OaUDbk5VnooUDIxRz1Xj3Io6vmSg9DAYjEma6tFYE0fBVemHZGPl
FP/ovHSRVmCsAcEdDuCLC+h5nlcsVS5yzGjRh/z6breZGyyJ31u7sO6X7sGHyCJYAZqMTda85Wpa
H3etZ3rFq6wb4uITjUd+B6WLlFVWQsGNFbSACobVNsBDenKv9/4aCiJQS3cN7+M6KO87Ny1tn12B
M9IS9N+COqBibgQaAzBVE8/BBxKaFMCPdikFVS84kezqnsdBiw7xkqQ1FQUKfFwvQoHXVnskxsBY
QObU7L0Xq2EZ9Mqjb4wDdFUvN5AFYhgNZwBIhwnuCfsnFdFa/7Zurpt15iAaaPECFzcDBQdw6Sa9
RgqszLk5yz6QTYQi1HGTb2/VWyhNtGY9LHnLDuxQCG9wvn6/p3cuZiM2Z2nufPR3z6zvmQ7JyyRM
dJbwa1Fi3b3dfxU6E+7U5OTN3k8rsoURzik95nJubJSuU9JQOQbh8tyq1dKlfWG7XzG3gyx0gtVx
Onv6JpzFb2kZh34P7SJAlrij0exsR4ir+cBcL5q2XoatxxuWXXBVMHIdak50tWhwvg2haRViu8ox
3fSVDj9r56hSDoNtU/sFf9bco9Y66F8iY6Zcd6vSy8lu8sS9gjqR24xn9vnkCIsmM1WGes5vUBKg
8OWABQ9PTeXWtt+DbLJ770ehFyTRK6Q233/HNLSNg/YYGhGPonkY25ZSFY1j/gYbKqiSChacgh0Q
FGjcacrSNroPDxN533fu9o59jZdoj4vSNgJxkw6LF9hU/aZFpGu/fABc1eiKm7CFXcipubqnl0EG
jTRRgYGnPdVj1yEoPDj5/2wL1y+TEws1aCof87q2jPi/qjr6qTLv7fFcDQXsD5gaqlr6RwJVitqg
N2c2+bq7xx5/u4Gt8z3QPUZou4xVEdl5v8CgRG8TcGF/J7bgDpvxuy2MGB16X7H5g1JZxIRrI6RU
j+82+hratNCAwAJiSX0O7GEKu9IXNlb2AOYoMmfsUynuz4eXQ3Efn6Q82uatqe+GQNKxHlX3iq8+
5COrsrAsfTpSm44b6WZn0ZWyuzgJc8X8LHuSSpaI92gAPHZ8uA6sCNBgNromqJO50dtl8nzMth3s
3QnRy2S3jU/XVfTO3zYAqZ46ectatcookFfDUYOw+KsJ6zDRqdADb49QZuh6FzRGrqJRxxf2igRw
klNlFJcstwbfhkDWLFSqsOsplG3k2gjklbT6lfEDI4+m9qNM2nJQOROBszJE1PjIBc2RmLSpzwl9
Cb+wmn5imMOK+cLKDNB5viKl84Zbk3yN1w5jXYDrocXLYZhqIF0w70OqNwaIMWropp56+GUhByAN
jDUV1aZT5BgYelcjFFYJZthagc2KviG6dMfsXU65luVVVkECWe2BT0xFMwyPUoQkiB2b+t+Zl7WH
deyPW9aYIaag//GiBv2KVfu6lrMnmZiJntTm9yAR24pTRU0zfFcsSEGHJM0DR6n13vMRKiOtKJQj
1tks6+oXOJfVZfouuCZmAyImPNmVCG57xP5cVeuBZuOgJHe7lK1jT3aFv/AZjkBR8Bjyi+Aekxdh
SfzPvEvTCHbCVzw4ne3JK4sf93tmqiogywygQj9GTzNAAIFWr4gRg4ywS6gvTnzfb0zsR6g66S9I
F4m81xLQuRe57YY6xPRBsmoj+BEQlJUPtz/rL4PhSEFMMUxp8M3VD1f2+wUoMlTczIG982D7MXor
3a+NttKpIAveqexKi/5vb9nF9R5MXYaGjgrwUJX914jLxzBnvAL0MTBnfVZ7K+bWLhPL1PvSBiE8
Y1wFzq4vMvmSbDVi64Pj7EoHlCsCAVj2UF6nKlDboxo2cNvQ+UxE/ttrjrUvUehGETpWXLiTLFD8
n4l7KuJTaGZeIt5Wap74tU6rifVGjgyhiyGtYX/FD2Hd81Dit3ON2TRlFmdnrllmmd9DQhk+oMNo
GSVEv/oOkzq+4y8m6sXgyXLph4zhW6B/r5yIJnlDH2CT5LpAkuvel55DmygcEOS+sDBUyAwRXQJL
c34HTvFpcrIQjnllfj9R/uuxzE6VtHqzcYSrNpkSjPBfAGc9nCa/vruXirlfN8xKA4q5noLWlE4P
xUXu1KzJt3mlTUyLJJB47fdmw7+v2CcNJJLF5dhc9qzrLS5goTUD7URxbmtInTdpi3WSD7n8oytd
9LfwM9gMXIIs67NtGfuFigDbn9VZSvhnHcTwzTfbQQ9+U9OUobbtAy5+bdnokOSdy5z3XmWMtGBp
Gv2wSs43JNY8ocSa2LWsCuhmxB5ijhGpVSLTtTkOt1HiCdys+1ykXNQTnCVEpicaOlsjziuNg+IK
d7/DKhgMSL8v0jpq/1+QUzW+EgPToCgHPhzZbUnv5Ziv2O6IPjXDfeHbVx2TSQ1hrcj4kgZB0U55
awLrXf7tFtIinTlG+JXJq1TAw0d71og7gySZiQ3YjzAGVIJ9Vi9cCdG34v/M0dwiV9rCCWaO1zky
WoS7Y8Fe+BffU9KgGY9mrKYGxDAQQPfSXSaonfubkAKezPRkpu94ylR98HGI2WhhmRko7vd8BLqV
/6It+zE9pEYVjRSlT8Lz1PAuSDi4e89FK1tK9q8Vv1Q3iKlPE85hH4BSxLcckK4qzz0TiqB1iAeZ
2TSk06m5WJYqXXxyzPPNdUXNtoLuGu0pG2rUK/VFKDmnmNv06/D4g7U09e0N8ldNGvnyZ1W5GxRr
danMTu179T+jMXTWMrzgLhStwUjZcyguAkA/ki8d/7lullQKhkBvBdi+iu+MxFIvBrEZCZrG1TjV
hn1hk5BizBpNPMFmGcHovhid4x5dtDS1n4ZBz1iXC4Gy/dc6FUqVYVAlrNj2cKoG+ZOpowmIQHot
akr7Ld4uX6GbUfODx/saZTBpnuwda2eWEV84yKUwUWNjMybLN+fltp0nIjeIreVX+SLUAn47gTcq
wSbWOBdCVDSAsjN1Asy/1DVKDQ61VvegBzjTzM6up3+27yYG6jEe0s64ezxWfBKWT2C0NCvkZ/9E
LiyVCJbUchXcicLauRxA6qqgG1G6LsrKspqBQto70PRVZQgkgzajsxqV0/XWCuR6f41pjyvOGioV
S6lHjF/ay0hJofChmdCIpeKn5L8NiVcVuUF8K+ApkLhVW3s59k1P1QwXk+0MMYWqknaPmqpicuuP
7oPrBBG57dDWi41SSAk+w8ToBzhvhC60wge3ti7/F/cy7MpkiBz62SW0dllqouVvwNvMLLVb9e41
zJ06AzbSbEuzYpZiqFyXhj4zdk3SEBkeOsHTIZWfnUPAO3s47nv77/ntGFrnVh9KGrb/C5peotqQ
jLekNDO8KfFiUz8qp0Jy0K8MfwEb+jWdcu4JEZlvfYhc6mOLKi7EhnUYm0qzm77q42IQFhsDzDCE
/s7p6Urpj2UNmzkvYMcq6kCbZWZPdDGPYWiHtAmREkaTuBZgzMdVGx7KEcFRIzJeSOhu43JP0jZH
Fngw8rk8VFSzGUfHISO5FbUdJzT1J1oK2n7cLUVcaHKpwDnNZuicU2J++dyTEvMnFvIzfTibhFew
9u/DkTht3RDGgaFiYnhUsQ54t9JrruNgdcHNwMEtf+lygdgrelyjuDNERCZ2QfV2vNyCJlUb3+dg
sB1FLdw8ArMtKLsT6YS/bxLThGG6Z8xeITP6ipOmBx21bcu+PJFxz6fJAxIagVHgdtqatiGStuAt
zx6QpvW6HNGAhx7mMxQ/3N03Ed/OhYV55269DKUK5LXjvkpLnHHrKaIekJ/ytYVcKNunmmXZfziY
gitjOoEmrymQfeOqiH+6sRcgrxD3SLi/MIqpQKX+y8PLoTNASRZRlJ/JsCnN+bAKv5J8zUkG/iUd
CH5vfmLOMZbGWTc5evuYviJuX7Ec1hKdJjfqbSdzEpwIwuQSN7KWWulHuRd2nsYHl2Tgwy7WM34P
kLomabX4cT1FdjgoSOOAogOAX05jeAQJGaQjNvwjNhnfxywD/ZnqLsd//KkiBeXjcdS1aHqYQYMk
JHpVAUckiaw6k/l7s+6RmRJsQIKmmsltB8PFmqUvr6A/uHtqZm6BEMJBmHdDy4++KmtmeIycCLIK
wjGVBeJM/mDpsUzxdWs6S6GtgXAr0X9sDY+o8hX9XgcYf28VuFngyhGS0tFm0qcVfG8pAbo1iZlz
Rplq1AY3afMFzgB0Q57U6PHsP35IYiqS4u4V1mHJDpeaPA30q6q8MBwTdQi45Gv5GBHtz44sjJx3
nKYt4d9fwSxp0E6A5lEr57d7Ywaodd+JS4Kam1kpdSsN44g/Vi0udJNCEjSKjeW9YuiXP/Fu7e14
jyS1xtO4kbV3XgncIgUmFm6n8+5yraM6ouQBxf0hDx3JWAMiO5CJJMY+hgyjjB5Wcxig4B1Ic1B7
p4SJYYMt50ZXTWEnzLwoLYWGZMMyE4mhkVQ6FrhB5N/6QDjvhRQFUWwqNkUUW68bAkXf3MqbbhBc
RpXJGru1KIbpWIf2TmuHumYrcp3DFiGeX228KXlQl7mHGEenMvMbR2fjRIbWcFmjO0AWUMBqRdaF
SpTAklkkQlxxyLBAlmKqJ1lmw1tvn3RQarmyETdI/sllPvuy3IQB7ulCqymJSAt1G7BOJ3VDen/r
5zawOv1NRNNPmZTqQ1pwvHZAFsTffIXOh8V5yaaSzdYsBlgRYM0ADmhR88FYHpCb9VY2VOzRrQEK
hmwuReBxvxfyrPZhghq9+UECbC65nX8vUMMk+s/3yMg2E8zr90aZ0jS0KgkmfEtQNvC2QPL9kQCG
APF+n0xHJIdIHgNNw1E+WjRDdYhU0v09XdDhjBOBOXMvf4j+nViiw0kQv6Nl6Zw9vCgFvwO8v0Cp
ZzW1EQ0ZUTaiIcd4FcyldKpJSQtL3dqXnRxpp/mnWe3YkQVFRXffhm6tuFjlSllPwjxW6rFowbUT
L0weQu+PhDHvssQZBJg/HNWEuZDwSQcGUYT3r+Op6ZQBjaiEB/tTf3KzMHkj8DTOoQde2RsLp52J
7KhlRv7pnPsR1jc3gRDeEpr2nWRWTqnUer7CrOU+fZYOSThS46mQjVN7womZ+qxxWcmxw4ttTsRW
zPTwfJ2XQhkSwoabMJVpI8szFZ1qYGRkcjI20j/q/15OytIFAcyUaghcTfwimZ9Gt9PNUgnxZTjb
wUDYLXRNjybIEn3mwnMYVnzRmjYC9cCjFpnV4EP4VemFuLH3KcjCv/+RTBp7TIYDj3U3wiGxKzC7
eYEpyCMdPQCRF1GDKvUk1UK0XRayUDwMeBMbqRn9gUDO9IRq4EoysEmXxM4dnV3ucoaBTNTaeV/8
wLaEVjClWhozIj7lsIxicQNfVHsI3cPmZIyyGhxg2oIRs7wv3H4QBnncZN/Cw5Q2aJbaGszO/+Ji
gw7jWo0Is6kWYk2TzQEwksQEn4BGXh7wbarfGNKxA+691PWNmuAxtHlRvB2Nnu/aS5xGIQygDkMD
1yJcSdYXvSCWFZ3U3uvsn2wDGn7aXZ2whnaKumdakqLFBAz3fvchvy2g835Fw5vRGSAsF/evyKWd
K8/tC77o1QAdAmIXH7wshRdMIZswAi5Hq1BJPiE/H9Jyxfs01mMGr/rgZTp8yfOIGJ44FVtwx0lT
Q2wage9xZzWkbXX2eQMzIu6TbSO9ufmtYehDwWjSPldoUUnfVk034dcBUFKKA5B4fXPxAf9L7QRO
MBpdpUQHlRNkMzl8ZeZkfVTX2PU61bHVoTr5KAN7TAyvoin1fDEH3rAKfB7bLakG0HVqPzsSaoTs
AUWEjkO9lDW6cu8w2bopCFXWSyl7rPsCJN9tirs0uc647eTp0xiVXDo2gS2vj+RHzyiIH/SaRXwz
m/iouV2Kezrz+9vHqiFoYJegfft5zkS6MYJTZ6McvaFkjDrGzUPwwySfaTZb/bQnPQO6OB/oYTKE
hpjpO+GkVikSVhOg8TKDggRF+l9imr4/YQw9L2eB4n9Y0rMwBDjuARdyqeboPIkoqDP0PXMIx46B
TxD7mRUTHPAAZ83TM2J8IwDkRM4kje/uI6KofHrmkbkR6FlAnfVkfff+nKF5bjeu81cXsBdiCs9j
ONs3T9IN8PkPeOyXfxRvS+s6A/4/vjwaMLGoXir/08tbm+w9R+AgYoehjiO3cw/iTPd0ZqeAnu2Q
4nk1XCPncsAFUKe+U+m9vpaLXbgo7HhmmE/ysX6DXE2tijELyJKExPYm0mgyZVpj5Nrdu+72nWCa
xvpZlL4WQIXK/+S82IdAahVn8AyJ9e5k1KAAcDwcnuPXS9pLkbgeFQpz3jcPkXNGqsmXzLXRkY+N
yFzm1AnYm787bo4cd9nZCHQo/egn40+I1AGYJpEerRA+kDmQgPO2zn8yZlYEyjtSWNeKhlG+uIQr
PVz9eNLfI9FaUyNjjd52o7f5VKXdrE5Qa+e6YhVl5Iupvhp8aQf3F6cqoKT7ghyuPaoyO4SEOoLk
oJ59KK709lmOK6+PQt/yL09zt2ryhQUWH3s7W6x/K9wFHMVuzhIBVukeBCrxncEOqFj6PX7Lmu4E
wsU8qUQ7TCa0Iv8v4lDHXnG5vgPC3Xmk2pL7P6SHte3eO2NyHrK+NT586aF42BJZ/AfU7NlfZzSS
DTJoY5hskiEDpK0mZcCZLdeaudtVW/vX8MIgYJQcQzFidi+Q+84QfLvcWNfYWkB9VYuBaZ0TqQEN
oozs2Nxn3ouND1hbAHgw37MFoGnRQrK7MN6AdLyEqTjSIoLx/0FCSvSkJsJAzvOmuZn0AsHRQ63L
1+K1FLlh6uQ71mADRcNuMeSo3QKARXYtAvIfJa+G3Rz7/17Had9J9oUE8+yDFHpJs2FZagBfqqQG
p7vTZZX29qPBg9DRvovi1Q0DkruPNhyhuYgfSyTiwRYygYBV3ac0ngpJsXTHXRXZJsyqSdsA8Ueu
FJiMMIBrbgMYdLvxNixxw3Yt07tMQ18bL8SyTTCGd7zMEMuUAhhUifv84mWDbjmD5frx5m5GeasF
/Unt+zwgCzA+SCXdDeAFk9NpnEJP0oLpHq4ed+QH2Qm9xZkbCigOSWqgTW1lT/5dkNEiRNtu2KTY
T08KxpXcOShSFr9TmHMWuVNF4/cD+avQaDkl4mGhw45nyTwWMy1CjSYKWdwDbmxpJvKhTmjH3i4h
BmvXZY81HaRKY9HJ86ja1R1GmmjLUtJfBiOgEiP6ngabVfCzNoiJTmfi8EF4omqxn5Mj+9AvCya4
KIFWm8dvMbJQNvTbn6vtWmHc0RKfuyUsfyi7z0v57d85WyFyFNyBrG0r9oV0aJ7cJcbswWy6/HSi
O+RSh8GqFENyMtd3y/hGyVw1a/Vtpy95SwYQGHuurRxMBPbzUOLnB8Eh4LVe98MOYDWNiFuQSO+D
/if4wi4d5mCkOR7tOf/wO+wOdcDrzVOLhJBZWnrCor5ddFnqpAQAt6vy2vrQV9RxTdqi22Tf5ae5
fQO2oSMED3o8p/rHyql0X0njuMRI0ME3gqO4Sj7lU9OrckME1/3cHiF7Oi0n9PAYyGxnAgKNsR/l
v7l5lbmzLFFCd0XDm7c3C3i9wmsCpnfVTqTMxHuYBzJTe0LiC5frEg1UUqqz8IONRj0iiTuB6gtN
uniFshcQ9k+ZmKtHmkVXfvMROz+IuGM3LA64BR4C1suuCrgHTZC0tAIfUgbyRvoTnZsOpwesqHvq
dhzKZHBw443c91+aNENrSCZISLeEBpma/q2KTU42b9PJNru5NmhqNUQq/KZ2HqhnRTLH4DBOzsp/
BUJKwGICIbPFni/oLN84EwsTMvSl9nngK813OVONnXQe8g9VjmohEvZF/fDoB6xg11dvopS73Q+b
HJwUahswVMpeMndpplY0KvdrNjnuVsuh+NcCUi/s1t15+J+Q7EiONTsxg1UYnenPOySk60t8o1Gb
zi9K0MpHWbOpnkwbAfqYAJW1QRhnelsMvtGrO+V42MxsGzV5qQDTIR6Z99X6pZiVnKA70WEurZkW
3AgeNIBtacfuu8zSZGT1G9TUalWJZ0fYYXQB0vHxFPtz83RGmMEJsysX9CNVZvDcEzjkoo0AJvm7
mNEL6gfeyGNuihoF2YAE2OQH/V0EWLXdFDbJq2s3Kr3KjGTa9KZE3fEcBQDRV/nM1ugMuWBcp6Fp
YH/0K0TgNIorvB6T9FZxZt0TALViaOSABQBPFJFRw2xhiokjCf+dk3IOFl942WMV0ibvF/3MPv9h
ci0agJAJkB+rZmx3y5t1zyJrPv2t40C0lw86m8MV0/1FSY2g8T/o2dwFOGUbP2pChnexp9boGr04
c4Y8f0J7ot6AJQNDI+iwBHU0gPxHhYmZmA+3A6pFphJVvFx3YrO4dKTN3pWa+Bx6smhxwzWI/Nsh
YYx6+CjGFBUpDHGzCC5K7C3mSL0yn6ySObzRuEfXjmwMsw3w9W3BoYchF16b0YnqcD29scSP9M+N
wem+azZLTQ1z1+PqS3KUD7YxgQ0Z5WSRlPCMdWDrTKwW/NqmRt9i9g0A/K0X0cNXKUppSzvbu2G/
3ls/udhZ6QYlWvP5IJJCNYqnhx7U6HYfHKmOgditS8txY4BHw3XiJG6vZIozLXRqLr8a1IS4PJlO
952wPYAmRS73ENnDe2Dsti9HeR6oqZ7DVuyTs+DspYqmb+neJKldPnD/JiBvrKTrqsBZ7evl0mmB
Mr6fgaSHwQ0tYjO+jgQmC+i/TDK7Y7sASMzAX3cuspfQqzd5lGt5KzQ2T9WguUCkVooRsTZATK51
VeeNwVPz8rUBwGAp9vXfJ4I6M3oM0oxGNm+ciEUlHu0svb/1WVwsZTV2tWGBMv9CEILLglY2Q6jS
kuQwfva8wL+6TArlkwVvTG6DeBOZNIqZ1w59TrGGaBqeflSJFSjan49kFsfVJ8upl/rkK7FmLdU7
8IlmZyIph+cIz2IriYlFc1BQvZ84MbwJnj5wpWRWWJPcxuA0hi1PyQS1Y6b9ADJWwmrHEfMU2IqP
RytDpTIYDfyE1jIY5sH83BvqW7CGbwGHgcFnmiTHN2qPefhY5sVXDd/oUJWKWM8EjhmqUblB1nO2
y+JA0XDw7DeTBZHOGZJTMsgfocRE6ffKt/V6ogKPiQ3hOxIr9ww7NTe0CzLP3bWuv/4DNhfRRkLn
ETGjjo6zbCLYk2aY4sNDWNygcHP6XfkzufzKvEGsLpwt8Pr4gP2SJu86jqLs8aug6bYAt0sv74KQ
TZ7Kj/9kEsMSmEh6xN7ZTFM323Zv1RhGSJpp71znbU7Sja8qJBkLjr5Z5G6KatjDF50sRAjCsJ1y
wg1JBJFQx/qKXRQlAYhj3yMutQ43UqSvqbuMzPvCy+oUCcBiR0C8E+VdNWa2mRpL5BJUYOZ38e1/
GQl3dqqKR4VJ8FAUhK9DedaL96L+D9QTkKVcG/+CApv6+/V6Q2B+dDIqEXOdpTSXisk+qB0YBvfC
GfmD8ZOutft1rkvXfwBbbIuOLNyablkllvm/Rh9B9gsR4yCjyoYz++hAkO2laA8sU9yAdoNKdnC3
qkkn0I1Hp6FrUipYpfp1UsSmYCg1XaXhbIoJS+omEhTTzGo+zH6xmhbfzuFpC4Z13BOV/vqYZbRO
OdtjNOLPu1qI8p5+2WO8gg+DVPltUIn/aKjiw78cndN/B8FsWD3BmmTdwrhjzTZZ01rDBjwkCIfK
67XDN4jKa/nKrkd5h28TnjBvbxghVzssMOjeJSuTxud9JIyKgg8IOYU/SaB89nBdZYgVt2cRVyq5
KFgkyVIWO/oiTW0bysbqlGs3g+0Xo40zp9a6wHUrG9LMTXI2JkzGFffwBL3oNXGhxas9K9aZzR0t
tNXovMB4xrQNNGkaXH1qBr8D8pVd0gjIRcqr56IDmOOakVUwTnShzSatlpWW4vnBsZCfYHJSbYqx
mPYtkVHGSPzR5khv7e01fB0xBn4f3egHkMBoBerORYL51oN4AuFnBWXmSUSCMrgdGm/fVngwX4tu
4tuR65EtKQKEGKsZOwdwinHMOUcsegcjWk2flhWOowuSDu+vdps57NUu6UGqjbZV8EMANPZfe0rP
Bs1Vlsx+6V1oygwQfBF00b8Ix9uHaso10yZtF+79AN+EED1Y0cAkeoGlS/hXZ3s+rJ/bL9XhHZj+
oVZAlIwq/XEMu07ohv1GcoKakQdxAipFCij8QKFmYPVRmqslfosABAsUKs7sCi+SQakbIkoKoakm
39K8VGC0/myfBrxF/vY1p9BxLZQrvlkzZ1tqsKyP3h24i/2TY8gyxdn32JkNWNWaymaRrejLSlm+
4q3g5ycfystBqfHOSQ1qbwN+eDDqRlFbDRVNQhW0Q8ahQY4W74mNvIDtO/Kgtl1wYIEFtxUKmjJe
1WFwf0vt3whG96FHgGnxRxyt1uHMcyCnipr0XZuRya+CLC0BZkXz7IJHctugcT124ucquQNSyXzF
5hBkwg6NoyVOBvWYCoCAD0njkt+pmvCrwM3bwrcT5lW2pS+9aoQCMXhPrxSYdpFzzDOUOKQQU/Rk
Y1bh9c23DrsX8slk4GVLN51wPvHQVzvBBnk3xtsaI0FUy0ea+aIo9MbbI+mSWDaHTn18kRgMfFFB
iI5Zu2FqD4fp4I6ATt8NlG/Xt09TSMswttvbVAK8DBzz9+bzNJI3ptPZh4QSPenOejnMZ9lIHHPz
jsyjxV/roBmMqZeyER1/cn+asqJK2IeT8vu7+vWnPOYXY3lhBO1BU4KT+s0Ftjl06CdhMwomeTCJ
3x+PpSy2xTj9wjHny3OkrDBf1P6q6VX6wLCyuvi2zXLa6aUTZY6UnLR2/fIJLcXz+0n8NxqCCDP4
0ljQAIN2HjEo0tFe+EWkJyAKv+DaVEIGc7/5TCznYIwemnSzLx1VFfAuI07mJdwxXP0DW663Ftkq
MD2KHLIIv7Dsx5YrltmNwp1mrJveOzYCc4eEeeAfgxgjGZfD2D1q9ksaJa/F2M+aiZV+U8r3BJ2U
mQgPlk5GvtybkF6+PiFFLNrauJBkDQygYg6VMN7o9ftKB7GY/Il6ZQUvE+hK86Ee7Oo41v6gt7M3
B9qXEIrC0zfUI8Yts+av/pyH4KQ8Ca7rVUdvCHq1U4N207yB4IkF4lUupeRbSOh5gq3tXXc8sBHW
cWs9n0Igw5THe0wUKGHWiFsU7IOOEqIgoSQ6o8yaRV3Nc6G/Me5ASMudyKAztDsdv0EIT4fGW2rX
aYvwEtdcophahhZToD+C+xx8jhRx05b+bALmPJPbmaxHLEfwdBImzdErPVTeVVOT7x5N9xVAoScL
0jIRq+scuDe+FSOY5FL0aML1fLX1e1s/BHKUlPEg3OQuimPcC7h6EM9vRxGvVYO74sRRYAeyXXEe
BRXO5ShbKwQZF2rUhmmb7aXviVfUyF7RvK/xee28zyq+PmTX5s1PJfsy0QnykRoNeS3Ol6p+W02H
ercXMjdQwAHJaQAqeFK+KFvAB8CnLvz0sLu6HQ/Bc16OST7IL7h9H6r/RMIJK2FzyxVohM935kl0
9Cq+3hWaJ1XTuxCO+rFe5XtiTd8s+jnww6sA7vu4sOxsWx1GqV7a4+bNQMxAKyUK1KB51zuqFf6V
3rlmO0F6ciquB/b9qwA2BRdq5gqrkjYQKlqh02OtgyorGKfsUO7HtUxAVOZMzFS2uQO53bHTAYso
ISKjtg5XWFwXzGJSC3/9n5BJaSKcYVIE2PmMhlL2H6lSPUWv+sYPJfcTOvu/hp1fY8PE1lUtpVR5
pXaOv6KyUyCIXfumQvctCsTmwqHeClp/k7aH5u2384sEzv/fH20I14sC8QUSV4M3SxNiaol6cftk
lDD51kQ4ir6078qeE+tkL4L6MOzgmBaXSsDRz4Az7oc4kfyQaoxun3E5eqULjak9dTDcHaL+2O2A
LiR/JtFESBnP+qjCCZhosSYeD5kctYOBwBDQl4tI2w1ZWAABfZsMxx48qD1YbJLVuHxVzaVpSq6N
GQ/D1IMIRCiLXiury1VJdCkYt6KdGccFW/C6dOp8j6WB1CYVm1iSaGPq11Feuti3HUVb+/JF1DYp
vx6YL+HtSz7R2N8RupkPJejoWuKs9duNJtbNMiGwA1CMiPhjLauJ2o5NFmJ2NzldzK9oz+WZClfU
iYibY1xIGd7ihK8UqXiWZpAiFBF6OKoQjVSt7/epA4pJd3EDaaeh+B+wuumia0YBAoXH1DJgk7T/
NsfkmKAMaoxGdtNQEYHZX+aP6FIrYuKfsxyTG3XEFXVFG7oGk7bXDyTbTvJo98M9QgNerjQ00jTN
NJsjxTzgt0g0OOVOLnplf/4T3bi+eaDjULw7QGe2acKKbbUxSVuLfRo0k2CZpPKDTdEW/tNB152I
w4JnJlyEkFxpMm4Ah6L1kMIOvGGdanThPDp3uk/6gHlQ6KK9nWk83yYb/FRd+nYuaje0VCYbto3p
nO+VnnHDIrJIAKeauZwvs2R66sDrIl6x3CEfWJLnzDUW4MYWn55zePhLt0SoVpVAN2oJIk6EFdGZ
/fszQnclaAL0u3q7jlNuxcLMK8TCj6LgHg7V1cYzUAeXPuksmIa2gVcUVckCCgeskqW8Vs6E1Chz
nSX7GvPSMqpMRPT4XgIXDnB50LHGfldRLQIvFr/UYZbqK07Hg8c1m7kK6QBfx5N8cBzJc8oIDp5T
fGNVGpPhX3OZM3F+ktS5lAMgPJH5QbEc7bZUGF/E8jD/oStYeFgLtsIjpm1pIyba5hS0HKJTnfqM
OZnWNloBbNIt4XRKoTsyK4f3ifMvMknIYuGLPXH0oNUUkMJq1XMBgoHaxIFyesPrMs3gvKZ2172n
Ao3GXQCCwYZTFGmeTNPgYJuVoqCILLCCE6wnVgaansiUAGJmamzPpTaDdjbRyJ/FrBphIM+f1G1u
P1/K0L6QJfjwDwM5upNgeZ/PLKlSCnKAxu3kiEeqTMrA+F6//o3lR9Uc0mkhOP3v7eAHb+9Zu8NG
8PAnFmVBr5CBnQq3NspxMjqd3yf1ScQiUx/Po3Gwydn/mZz1SWe6gOCmKVKaL7A7vxlu8JLoho8f
xo0ABmd99xlplHuwvEnF6yJkgFdKgB7cDeGL9pscq5cSHNx3kUtXq5SmtQEvRtgtIJf8Ihf8dzBb
xeOl7FHtrcBJ584OqCZ3lG6lM/komr33mQltBcQnrmF5RAIPrl6HbOCfKmSK1VfwizDOZ6qgaiTp
HeWC738v/PY8PHCEZ8/f7AkGvGOR1d24q5anX0uPJ1bqIf/ZD7GobFI9rkXHvAGe/EU7YfHbTcs3
eDsOHfkF0kBLEje7O2gQWri1Wv8lNmLY8ywMtXm4OWJ6NvstPQefUbzCId3/EZhy+pV7IGerXXOM
irguo8vtKocjTf7vlhOE9vVJX/FH/3l4OS2hFJTtHrgJnFzo8m4589sviMeSzpWV/Jk9Ae8JOCMP
TGXc+8KD4iWsfEiRNX/1zeLEuBM6tx2Aa2oMTz0gDwcfg4g/Cd2eMhhCpQmjfIrIUZt6yQ/ElGMq
khzWwekThMtPqjufAFuUOzTVWJe+b/yn9E3FoeLFHzJgUVVjkRLd7FOXLC2XrU9B/yBUoUQXDLa+
MlHUKGdPA52hS1NJLbXfjXHM0VGfkPCsOUTi1ucQ5/34cJYU7NxNj60XxZLMKqJ10W3c15Ie1jLV
cUg6RGPaVgR3qA0oivy/OvP6tGbuL89+BNGppbhgOQUaMo/weAAfeHzVRL/4zmeDCKdhNPsmhSZD
cjOAiBOtJJCuzleW/cbTgc1+TNRyHdDxpD2rLA+qxEkKXp3IziDBUdPVRXxTqLDxKFnmtWP/98M7
hMANDXrJ+guDt/mRD2AsF4VUAjGK/KtnGWFfM4SMM3DhD4ulkZhkuLzTohMuD/D+LBPxLkI7FfhW
/kE78ti/e0buE6CYwZbMTV2I2bJpCYmklXbjY+4ZkobYJaBejkjFOJMjh2KhCA+7b7MEmU6CDFqu
/1cU2DrrXv0OSGqNloWdR8RS1yHmRsi64+ztR7bUZrn9hLaGq98iN3QRnDj3X6cbJb5r8G6G+gtM
XnwdXKm/m+fBoHkDgmlN7xr9C7eX1L8ZV6UqyzyiH/yMDXjuId0gHL6jIApwvyJNtCdpD5PkVxJ4
/lM84RGB2fQy5KgFKhYhU94tLOJyAovDt+p1eH4JzFP8fDeotRKy41cCl8i+2SkHLRSgPgZBaDWW
WzGb9LJmA9JqG3S4mkSNGSuCDeb5ttUbHL2q0oY3X/GXWiEV+zhLkjWthcoSFOO1pd5+qAnc9vCt
3LWWITzTDNTKwgMSF83TfMTe+EIp5q0BEcAmXfMe/a5nU0MpNSp8dX71825lAJm/y5WbzMxg1NY7
qzW6y/zb8txGpkeZuzymyfiVRPEcnvckzRTZmziv8mlG+rCoY8D4awXupRAl9RTAUIHvy4wuaa1y
3N41Jh6JCM26b75SjpVmEGnl5HCKQIMscubw0rvT742tNZReXgI//epCH2d5pV7iyFuNyJbi2zsn
QmOf9D52v2j/tYydJROHHfCf6DgyeXJCe3B9FIyfFTOoyYIdJpX74sYsTYPPYxoGMevaieMjWYus
tYhBx/OiXQPWrgbX4yB4x/UJEx8qEFwLXv7yau833iV5jrBu3/1BZy5Xc10Hy/wa77v6DGwaQJfe
2Q/rOGGZlBPr6kvIYYkyDXYlXRS4QMyitjNwDLOamn2bx1oeIlwkgwfw1rj9V5NIDO1n1w/oKDmk
wdReHo9duLwrAFNP28e3UqexrthWNhJYlMhwFaFm/OSg8OP2xgV0RrXgTipYDlY1/fVPMQQf3F+H
fFsTnNUI7r44sXVnWBAW5JdtxKplnzyRORmCrzEBK6UO+n1H2GM8uAKzt2KpkrQFl2k6ZrUAtTgC
Y+B59HLwwzVqDM8F98d6sN7madXboO8nIgznxRrxQ+Pq/cSUqM0csq562y0y0rYiKsv8M3O4WJDa
pHGfJ+4ZZnOFfU6xmSLWf2UzNaBdcExdSyaSZY9MLJXlqlDPJNuw8QjSrt7eMzA2ktyme9WMuSQ8
Jg6qmPrq5mKgiAfBazHG6nLJI36MXBE326dpLB4OgasTMpuJ+DTADlmcQYdPJg5KXZzj1hGY91zz
suNqvarwLRd+pSEs0z2IIU++idcvGBgoGZ4qzyYi/rYZSCAc7/XSRncQMTYJvQjP838AtN9CeqK5
vMT5gIJMfwXUvQchZ8qKof+gLNNPcMlVh9ihbryLn47osUsObCDrdCjGwJnyJNlA/CjCLA0zvpOz
LBWZqmuLvNrgLdRQoPP8lOPJkKNStFutCD2B0dzkF5d8NDRcYzQKHZG3ns+XKw81/KkuUASwkah+
cI3QfdGfSK6oMFcg3e7jpxIE4cebBAjPEnQ1Wdh9kMp1vNKbbFDthmE4E29nZ2od4fGl+C940sfN
NKKkNIiyDprdfbhLe1uiX30oqmPHNYLN0l/D85kkMP37hI+WA036sjG4JFJhJ/h2gDq6QSFcR5A/
1jhpS5UOg8bOxWwuPSeGrLZons5txmbZswwEkfIFMiz6dcayGI+1KLAVw9Ae8noXHv36wm+gj2nO
EOYjhEaeEIQwfPlQCUm3XNc0oqzb2jkDsViNe6vVSLTMzj8ocZZUJy2bXDT0ySxoquVuuKuwLqfd
SONyWmsSUNt2VUx8LPzDH+DGYRDuldVuMpBL9ojgLvuh+ttJGin/t0ek0CjvlBeIFQkjxh/d2nMI
T/eow2ul/tpUCqVGGgsy7g8epOQWuE0wJ66oi1G6hbiyZmDGGrz1ldVW0tIi0g2jAOm5aDkVsr04
rDle/weqPGVfaVrJoJ1HxGPPSklPpsvSE79gpv57Lkkha14Ya0kZ//cyKMjdxuE5XbDkzbVLIRMl
IXcco1ZE5TdQs1UwoKsBKVf63agCp15LRrP+2sCSAWT1pPpZjT8eRgTLejMq8qemkAIA0gAx+Zob
BcZEOSnbWCUG9lNU/N0jJxkTOLGlcy+FeOnIe8pgiElbhawtS/fQyWumXrt0qTGqVjWdrLPkwhX7
uL9PWmyJFlQk2lwOOHzKdxtSD+9yin0DqVTUGGntva0ezs/HiqXDZyxAVGDfdedmsM0ErGe9oitm
Pf58JHTbqjfnxFE3jYSXet7xZTyQwCH8ezSZSBknIfeZnrhm/1GPjYoMWDPlKXx+ALqkwbO9scKf
MPdbxY4fGiiSsiPq4qdUMEq9/gloEg3vVv69gFubx+p8+gEk18YjoxJwUgyPIKlat/Vd0M8ARcTI
eiWS/Dbzr1WmmwgH8zInY+np0sOGtxxvUMWQ+S21rDqRJbkO4+qF+7voqgRpUZjc+kU4AgzdiIsz
ZegayMSEN790XDj0/v5V1bjU0RGvgWEk9/WFlQohQq2hSDdjnpD7NPEeieZld9f+KlCmVAJdzLhv
R+uPd4jFlA8PUlQJAUnsIPCu00/UlcJOZbuNJ1Dwz6r3sUWrRsTXoNpeN6Ns5sF6p/CrOm4EoQSr
WgGBBCz/DOabyVeGnn6zfIOi3WyTbk88pHpZUiSm7rzUEBOLnVg4vlSjSylYdKTg78RUYcV9r4Hf
+YuhbMmz73iN9pqltVsc5Do6I9KXEMzdU45uGnhKAzyGVenQ23y/K1JFO0Shl65bZkQDlMgTom1I
PwpncWavGcB67NKKN/5uiRMpNSnJbU5VYHj8B6WRAL3N4Xp71Wu6lcWar3OekPCEnlBbdRh1c95I
LN4Q6D8KtviuogWw6Li8TUFL2PuyUjLehnxMfUD7KKuasHdR4iuo/NTmRLStHj8D6F+U1JEifh1S
3TGLwQWlpGX2NHADk+pmPD8LBN69XX82GK3mXZ/bgmXOj1Kpkvg48VplUYXE/rTNokq1LTiXjgU6
6AfV0vaz03efBshPuxlBxfXdcvqcikkVb4sbBGqrDv1Wx0W6O9iGCprFxN7Nft9RdDeKFKp4Dg6q
mHOj0Y7FphyMQ9ScZPh1fx2vP5aMmUprdU0WE3TdPV3Wm6o9HijehNXT5yNTtEgeUzugaGxYiwoX
72AWPtXQlEz79M7H7QFaYPogEKb++qHSuB6CnBjqpvaTVqnqByl+zf8lB0K3+VB0UkG/13ISUn37
WawDpAr7zjRehDPzu3ubULtX0DcgnimIShM/S0o/KTOVxAlMrmS7JuCEZ56/wqNKHy2BHjSeSWs7
MFwXZndkc/9iIT9GOBE0ZTc4w1dS7r2hgC3qX49cTy2RySLYxs/gmvCe3riQ1p/vh2JY3llXaZ8/
5PWJwj2MDKCweId2OfYcsgyaZjomGU1kavzUMaRyi6L25rPUEqH/nuw5ZUaMFu7CEOJWnzFiw5Kw
O0GGVznWhuUAgKvLSAf2yzF8NQy7Ke3k38Tu/bhQY+uouL3KAPjICkvuTeGqDT9QWpXeS9OMfQ5G
20IA8otn/wbi9PJNx4XreSHWwYlZHpRUase2WCMorhz7bomlTTiFRmDxI0s11dPDRqoyBQpuhiAa
yeLBBldxFwyPZlMSpbjckxX4B8v5TU4GV+SpSqSeID1J/QPoaDGoEFn051zyes/YtZAGSvLwvmRO
Kk9liFy/xqlnLnBONEXxQbQNLb3pu1YnyGbkzvO6RR1xA/Qrsh2E/JPFlaa2ztyd45ZKD1prPp74
ferx+97uLlHg3zpLbFLfyCzbRU/HdtzdT8VGjomv6LNpg6kmASqHyGtYUIzpoW/l2UVm3pMnopeY
7fE8CwE6uhQRoUsdxGKZIWdWoAczNy5Ws4FQ7gF+fpF3EnIObVN3Y8+FrRzXIfOdh63ncrAIENrK
cTeMbARBPpDlVZlZB8YjA6mryrukZOc8xa+9Usu3VQziyZ2IHAi5W/oODdXvrf6y6nSrd5BBJO0z
+Ihx1RusNnRkr8GbSl0lvtK1wsRvxY2SBf37typdCVqgF1Lu7BZDcysNiycZZup1nImnEuptkCLl
C7zU0muaOpW/zRmQfelkqYU5ePwFPIzExaxVo5Q4ne/uOOdjRC9xdJsCfH/fRoaOb26v6cSIaMOb
ex/RV1rHyCqxEGq+XETFsmp/aCTw7Cq/LBCnaza0QkAkwlfili+QhYXTYZ+WatvtcGUWMsvWw34C
Y4D+vm1XqnlHsSOWazE9y1QLi0ZA1upyHQdmU8+ck034TX33NOGb2kRN9+CTy7Yx6MVimghFTpDZ
WBMdB8UnlwN579Auky3pZkuOf5Nxx/WzhLRVi79TKpOfEjYpx9aSrkosy5ZnkM7/424Dx1sMcnh4
RTwmggtrA3lVxuiB31If3CE8AqDOMPgJkb3qCuKa7S7plr8mNXg3Yx02VJYR+12fq2KdPZs3ssuj
fbrgr3ost2/Oj39YHr4TVJpHL6tIebpysg759o0KUgosDMDiEhVuMuBqLkUpgC4ccFKeeUzD5Ilx
SFN+O6DqElUrWGFZ9NBE+W0UxfzOtOqpLDY/W0fEeBvvgZ88dLqOiQ7UO4mSIiz4mDLSlg2+a6+w
1ShoYkFDCyd87g+8C04T8CO7qlwXGu4HIJ0OLQmB0KHeuU7z5AF14109Rcas1HiZb9g6CnZKqvhY
KwDeTtM7I04tkHESfhh8IDSPmqMU0tyAxzm7am9kVlH3ANxM1sySCSu8e1jzn+HtOPOFYH3F0DMe
MRYm9G9QD6uN+VZtXw2NEhTzZMj5vzkYRiXy5kCxkKdS8odXVOrAzUJFNnuAT+0VvDyjEuX7K49+
3Zl/jFU7EeohKN4fSGuuqHD6UGN2sc4HIIt3VfTDhJ9MAtQZg+VNijcRrxBmXfi2jTyeim64Gc3H
0uNhDJqKEyJyNXIQxkTckqja8LnowgMsbL3vHAsppWOg0SJwwksoZFgvsEE7y44DJjcjYien9Cdh
KhHBIcEjXv3z60ywMdY8eu1TvLHTvKOI9E6OlZ7dbATuml02JZwkii/rhPFZ2bGN3NE9JSsbiZzg
YOoUBBhVbF4bHtkB4J4XlNzvc8mddbGWJ/BqVl2Xax808XV9l/QSR5AVHaY7lj/pDvYbkTbMmr+Q
NQhG+tJ74IeMrTEiTHLeMsxWMENnYLcpPm9SlHjPuO5gApCUEUJBzd7zklYxqQa74rGpt5clkvkg
BfdmDcOSIX4w7A99KIh7U60d4opDHAxlFog5pyevtYLy1wiAlTej7kVazWcGniCyB6A8vK4+g8uj
N55LcwhRs+o4QOwG/TW9tDxSjVg1hNnCEdc6PwIkZ/P3t7MOhp7vpANbah/R7vceqQZyvK1d+cst
4Sh1NyZTLyzQ8pK21YYJWsr9cLLX8ldA1uEUaq8qtaTedx3+VmEE0/tYhrBOMWo7bJHZEGskH5Rv
9tfMSFerA8H+Mr7GYWwQqhUZqnIYT19+iiCAOIgkGG9P7OfO8n50t3u+rOPqGmnYKbahLlm5MaiJ
bQf1jFzIJmWeY94QGHYTMUyJ+dTmjmwkIMhgci/SWT4f0C3As0XZpxN/kVHMxZaKUY0bR4zlSXg+
c08o6joHybl4eYFBtDe2lBwG8wiYCUJ/YnU7w3WjIPNy0zlhN8CMUbwwDo+IOkII4A8uuCXun96P
E/43eE7ztorZdRnlCTfandUxdtPwyVrH39HfgiycHHfYQRHWqcw6kd/PwIVY/kRD/s4t39LcfCQF
kJ6Xju0WM5IRWRNd3XHfTdBxoZZM3JJENE/s4oqyfjB+QRzjcycOrvIai9WBmgUi17gLvi/DEf+a
8AYjYGbf2kecK4cBlX/epHErsVE48LFn5rKe9GmIUW8wy4SLV80ImRLmnYCDQ1c8vRRSxd59WBk0
6YxoWQ3SjGISwEKgTI3Gux847vfq9AzJXABaujWT7z1xvbAuzmKui0oXFhLL3pCLMQRWjKgERIkb
7meReZmKWNSJFApBVAmOJZSsAk/+Alli4CtAY9YpAMzr/OJDy6otiU9tCQUiORbUf3igaMiam6PJ
hTF7dPVHBM8D/ZflxN11KUtsg3IgCGEr9Eclcp6/bjv2CFRbEm2y+lTyjDTupBJRMEHC5DFKpsEi
Z7G9R7rSsRf9fQMj3/q17pbTrJfhhwA3yP3XbvKDVFaV3Ikl0N8MDP7seT9JNrpdvxE8BGVt10bv
gDnY3tmAgazahqPjzREu1qACh4jW7XgLWiH7UIOtMxWKODmsqNmKEUTOnqt1SDFkNpJCGJgknJPw
rZWwGDmC0ncXS4pdOHBLnrAkC7qaX3MwfbuLFeaNEx65eSz9J1YrahjeAzvmVMt7iWNirKe4yYtj
xZD2DSgxUejtUcQnGvLulI2YYnn6vcmowfWvxq/CYnPD7QOReNhtthe9kQJhGjWGO5dzQMyExN0a
u1bvMPmPUbR9FwACMMoxSkNK1T39woe1Y3NN4TNSjAhO2yKtHWiRPBikBR8vECSIFaqFCzaVvwK+
OX4OvaSiDzyo0AHVV6Cs+/f6sXJlIkG+j/OxY6a4vGpYuBTvMr3yn7w38rus6DtsEVVe2hBdvO1Y
h5APPdSbTzBsTHE9yjC99rKHLVNytqSV9tXHbNPNkBjpSCq8EAdqor/s78N4ZIIGOsqSJNPhz5I5
X8h+bN65J1XF3E9FbiAK8bB0h6gcdEIzFCfrcxRAKHxSaM7E/CLIZ/PKPC04tX3JfeFq2Ok3QNiD
SFi9r3450tD/J7fhdJYlKUBBFIG1vhaiqmEnhE3VyhI5u1Co0cW02b6AIB0dORXmyV1K4w4Y4ri+
6Z2qbsAMbYyQK5MwcCJ7Ltw5NdZ3OG7NJ66YpO4zXKbQlSWgjgxVNppf5lqhQGK9yz3iH2ToAMXf
E6KXo5LP0tNw88YuzoYStuimNCZmkxVZZj34rqAOzQiyFnyLzNF1ftoL4wC3eAlcStfiRq5FX/IX
wji8iTW2PFX5TrU2jxyn3PJ6Rnc7ztKuhjsf2rxp3rCpjdFqNXYv2mbMgGhhIKMUD+2g0NiHcuTt
c8vn3njTP2kMEhddKvTqPrcDqNMT31LIId/h+6N/qRtDM3SYrvjxS/43JDB6MAbTMAIBCH1ofE1g
KQ4yRzMfPzYKys2iRmKCRoo2wFn5cRuKm3U05jbiRunSblDaX/NzuApEvfsad4szm4w7NYWoFdps
BdR/6A91BmzzH6fnsaeL5Bfk+koZglqOrNUUpBTi/ROVKLaY3fwLUe4DR/vkBSoaLvn8RrOqHHTF
Uk/xr1ov7k+g05m2f8dSGoFroCFV0WlQp0d2LLK0w6W1I24/N9St78eWNrBpP1IbgrebTSmHmdxD
9ExY2NED1QLxkuFWiDRU5tS+JMl8rYqC+kri2Ts1mMJ8uyy3+RTMXDTRll6VwbCXR7oH82cOp9kC
0sI3x/3Zc3kArI/GEcT5oQTVoTn3QGxcd4Uhj06xYn27Vq8nJkz5VBQ8qFRMhcZ+0jmq7i27OfnF
4iOEjbrLq6/oSO4cwrxe13qaKJuCtwKBOUDR6DvNsO5XcZztgNPEOKbUQvtcTlD3ILCHLAJC+M3M
yIsZngjKQF+ImpDzAlC0hUU+WP5U3m5VK43bVlnxbySLxEXZMKWhPJTmWk43H3GzD3iPePTGgpk9
Y1WKUDeoHsWJP8A9tlDVFG91MZLKE4TImG8jEcgRfGJehJTQGiI2/jnSVojrAx8ZyKikUIPSNzZq
wK50m+1spaiH2CpPAD8aNccvQBKtEICYkHCF8UJjxhs0i93Gp8RAdbwIMRDWyfMFdUUOKPzq8qXn
GvfSpzwcEHArrVx/SiWjpOehnGmwY9n0OgSfpzJQlOkKtdhxmCobikq7HrGGGmyWjQMlpd32/jDu
WSEaIHyHmLxIT2Yn+wEdkbwDVbrg7eNNUmJP4V5geslSuDYlBhYDUGd5BLyGybEHpi/e2wdzMKO3
IRImAQHq5TXClEjaSHq5yziZH7P1O3qNJueIMzmNSz30cMdJetz4YeDLYl3IU9b4wkwUnQIQjurq
f4dIfo+GpgJ85VfVqx564ZDm5RETIDplGWEjhcWGiRtY13j/1g6Zbj6B36y+474vUCPIe1DNpoNt
t5tszFGPebsQ7DNb/JNSMjc8s/kjvUcY13EtfM+1FK95Q4dDcp1ajq6o17ZjwS0zy3ninPcVrlnx
Y46ot0qacE14ihpf4VrFVdiwTD2sLgxnOGASd/Zhi3a/UPXhJ0Q5Xn43HjHLwEGJowPocNuM1W16
jX6oljLKnFanzX00qlBmUNA/fEnZgrfoEKkFaFsyKcTj0dXNDLtOK8a0cQVwSgCRQOMG59rlLrHm
2F9pWadxL5Wk2ULFFduQuKGUI09JCd94d2OfIvPzsMvUOL3IfGpgUUN+r8Xb3uiWJWmMZeWlkiWG
3BQ5Cwvwo+283rUTiixUaZ+Ztv/vJEMQDMo+/UkFesABZbxT66Jh0ppRHjEZIK87lh5PugOMA0Ij
LwHO6vSv7mmFg42rReRp+g3eYTImJ5Wu2+390H/2SJ7jcNwfZpsgWVhI4uCihO8YSMHcMa7lBU/1
ajiZmsaV9fft3kJJq41tR3I2pLBIuSeC1KpebX2eOZm3ah0Wv0ZbQ4VVcnX4yvQSqK9TFMiAVB3u
HyhJ1HolwWEgbpJzC+uWBkjJqa3FzBAiYxQ4ZeIod0OPg5t/DF6V
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/output_blk.vhd | 2 | 27142 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RdT3NHqn9crEVoGlVr/u5ifJrhZxCKMuq2cHsTARQRG6jVMPRhnzggQLQXUT46IUMAW9jvMJWPX+
qzSQ7DlaGA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
l9TkRhWuYPTmqesd6suV9XTZ3VPfFaaViocpyDrxYTu6WhcA8LTA87s6O1fxFWBaEe8ejVSh+dTA
fBTywaIzD6Pvwo3SIGqcoQWG1G8b/htFi3vTrcGzHFADrN6npxmURYicoBu7Nysaz2rVS+kDvvX/
6SMxBDGJxHNluTNfOfs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
EYceV5QU4O0db9jGqBW6Zcxisvt12NgTmxxrS1V5Q7j/IhW6/quWxSq+g7EI/XdNj9QPE2IdcmH8
bVya8/qTjy0A1QX35nSxt7vTYedqNu465tC31d1gSZv/kTgwsiyLuwqEcX2XuPWtCtU9zZUhL7Il
2Kq2+W4nCCLCCcSveJad3fvCE0PHRxk26bWkXFVplZnodSz+o7HsyhlK+Dw9uZTzUAGDTcQexyg/
VwoE33FFwg3xrLtrFC3Yc+3Ci12lIOk6ox+EPKylAG3O6vdvhh/wk8fHyecQH+6mWOiDaL6mxNMD
p3c6FL9knpouY9hrFEFnkws/CVeEi955aL7iIA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
3P75IPAwFXq454ffDtSQEIRGo8/c1f61zDZVhqmKoQIPM+JnMNBWMJMtPhUFK8B/KMinqWmjw1FL
ujZLDJkbxQr6L3chtq241i3WX0GZZqzPlPtq6NgqtQc1dZYQ/6plKFwo1kFI0G0+aaXXA/Rg0my4
yCUW2cdGH1FiPkrfTTk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
U4A9VXASlEerYBMwLLMRq0uqBbuc5L+YMSRJVGgWzFToJIpoFNrOwRzqQ/AO3+K4R2EXLYMNSBSP
TdIkdh3GVx/DOJPGABU+jakJcGrmbxCsdTRe36ySkMAGm2PEBhWN5d0rJ1+mMJyR9fUAt4PqJgDT
geENJYB9LMuhHISLxMsPfmR4lwsP5W/mhqo1gOUBVrUg2ZhKO7le4N2V++ce3O1PFfF8e2ud2jGz
Kjy4RN9oYsttt1uvpKVvgY4hHqfYh3YOP284g5YDCjhAhGfLmTOjl9XXOb4fI6D0/XqL4aNNVhRE
1EOYYgYjpK7fQX3V0Yh9HmUHi+Jp2BWIjI5uyw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18352)
`protect data_block
OfMEHIw2C6kHzUz2JuaPPgsgi7BVcTnNyP5GYjhbGsmlBAGTEte9kmxdZW+Mu61HLpiiTJ43ulSL
aEAOHqO16BXbUe8CnCetzl2iOBbDTOxu5W6G2mDyY33bp5MfzSTIRKhNpslJ67RKzxFo+as/OI0r
SQofrrMl+ndXhCbCkxXGQgHwZC/CfUp0iJmmfN50KY1R+4jcwsbccLCgqlQRxssP1YdNX8H7C9u0
mL5MIv/tVpBb36m91dbeA9akm5Ls+mo30UYHQ/1p9gaJiMqkEw+ttpvq8fE2fHI4qZPfCrq0xSzS
TxODbVYfsSb571GIB+xKw5/UocYcJkBiUzYxgWK8yBpbmz+9E/v2gRGZUojG98lo22tJjazqkBJV
mRf3UqKcwcuIXaRVBkQAFXmb1tqSG5LLc7ocQ3p9I9ayPoyFPlKXlfHYczW9EvnBViaogv3Fbb1U
0aB6thXqRhCbLkSqGQ82u+5jyLzca2nmBgSw8ZKglsVCV8RBlwFTl0lHGNv9Spd6JHl32ffTJCnv
wUBSDMM8ZJuBjNzXxx8hfkmoXyNiUPs9iXTqJZe3VIMktwvCaIhzxBFXeC9k8mEIo7u3kcvO6vmH
MtYypa+loHTMvDcwzM79OlGv3W5E5DcvM0dfrvG3uefsRiTMAJEh9Mc4N0X8WdmamFPKaWrFJovX
pHMTEKfZ7w6BesNqsWTh9NTfGyiwgmmg1sc+efk2KlCgfsexm0OA2NEA8KLtSia7pk0GWEjwgpLx
TmWcG1GvwMHUPmNlltU2d4Sp75JRh2BirNMMIoxzDg97ctzxFrsKaETalgAIKD2RhbVfR5t99Gcz
JNMlFbScP20fX+/82cWisK245VAnz+fuiEd7dToNa9C5BhjJ8GSrlOgdwh+cJopwZba8bxm6V5ZN
spfYGdTkHyHAOIG32YqmMLQkF0+s/M26Kg/e8WEgSRaO5uo4f7nt4BTfGX1roR4i+wIO1KBK5+BN
RlaX1ySKt9RIKjB13KDUTmLMWkGQD9imG0DGOawlZIjNt1j2wHjx2Nf95hFgBePrwn/lMUGqdXU5
HB3YxE3mOPNigKvJ/ZU8RyPtGpAwBcwWK1dnUkMpKsvfRzmw6f0jU6HpKsT1kSkVABTmNkBSmHSO
GjV74CdBE+HzGud8jUToZVGyvU/Y0/ALAZLgeQALECLp+57NnC/fmKbHkgOrjthnfRTYYkVk0Pg5
wDcM1VhF2slH6Lax7IizTAlkvKhOEpi45AtfxT1ifINkxYNaGw41wIxhlOykvSRBO3RCVFM4v9G2
gT6wv4Ywc8POW8YNF4oFD5L5UCHrpIGFSDWRy4MybAknhL/B69ULGI/D1a+RopAozLsBrkIvf7vj
5dozf9/5mK1NJC+KY+s8goXoQPi7sew/T8l7izCgdTE6bMZMEz0mgIYzI+rcIdj/Ie2FVZmeMlJD
VNUGC6LaypE0ZygPPNjWCnRC8M1vdRwjUZK1RkQmBMMwvXMfIF1eQU6sdDs13/VuVTz1ilIGiQZA
p3l3A5H7MfMCXy7VrY5iNEBckRGqjbn4eSr/DxnAQL7Ej8+Ypun4DiVesv6sEm16vI1yOEucXlne
iC5o82rF8DW/rinfZZzT2iljQ2aB4mk77ZsDXtZh6m7XK1vFbLgey08n51Dk9b/btseeu9dENvFj
+SCKR4J0Uf/bLjn4GoGqz2kynDWcYvD+sTJtRZKtVFYLE3pJYSg7b+b9aUWtEjY4r5lXEoUd7Br/
ghLTYXi2HQZaL0UMMT9A5Rxk6/kzvTU6ymDNq6DsGHwUzQPCabVIL+aH/u2ZGvsgWejcKJ7EH8Yk
op9YOtNfcXcNxs7WypRvkukyX/Qcx5JBZoJ/pfxR6KkIL1eySdjD4Wc1YPP4hGpWxMHiCaWCJN0d
1NTyldbQfY7meAOSpDT1CDMv7oBqRVQlD/Wz1epfZbsJ9936SO1bhf7tuYKd4TFkNSN+YngnASiZ
oeEU+ZXEQmZTKwHaZ3XhsZxwYd+SmoyJ2F5hei72R/xfLbY/AzXuNbI5rHBo09XCG2YbP0enyMY7
MQUDB33lZcYsoEet+8YhdeT4U120N0LoThWHreEldex3DZAMjltW0vlTp03HURkg5Cg2t9nNK9aN
fR88rFwxeiCrG2mIcC4RS50CHm/wW+LuD+slBeSCUNb/0xtDleOxgH31jBgw4XRR/mG8w3o2pbs9
MokdAmrlHM1bu4hoCTrqaiMlkGagPTz/pR6mOd9O3ewVC3DrAGGMxuDUafFDicDBxCJBptIv0cWA
LV71llgl84ukQKJT7QsPRpVg5DsZaigDdhnLbF9ttSaZ9/7BYS74LWFTS2nrS5lQqUeQGJbSVel9
0F2q0tUbtJOqKzx25Slt9jFffJUyaWTxyQHaIui6Qie5e8ycOGIPY76gfFSdWcdTNyr9hj98YcHI
goZ83cHRaEHZ6iTQaA/YNFnCS7yoL9dbkv2mk4NJ8/rr41hMbPooaVT406sQ7OBVHcHgth3+/Fxx
UkTsZqo4d1DCIBzLLe5WHyI7k9k0CnnWAWfQ9Mw7gJJCT+7BL50fbEXaUURW5PtmW61d68p/pzAf
tcHcSP9ZTKs+vM20SdT/2Kq2UF82wMzDZa7DF3GEOhdeG84rWoppPhPIF4I3l2uQLR2xDbC9892q
9HrBQB6Gk2j1GQCZVz7lkWb69v6XQG+Giw+7iSAhaliIvquDj5o2gteYy31y3qSY1fvYoAjvnFSp
BuxtFRLXsd8EwdZE5JtgpY7em6FSyL3N4/uFXjSDWvXrFc65Be9h3uk9Rd/1lZjXCJQgNdSyKO6D
Hc3xJ98+YarsqCRpcfwzSvVyca3NjW/ly47bGWry0hB+/7VbmFMBxG+J3RZIOkO60zQKO9pJBtUJ
tjBAJZ8Lr+E+uPQQRbNupYEQljnTFhY6T1Uu2MsmNN7bJ13QGq15jFxfnFtvd6e90/JfeVGF0ICZ
xDCxzvlIRrj/fjdAZyoKsdX2abhompr+Fn6xNqIgPE/GDXb8IlwB22v62coiZVKIOcY1PStQ+C5f
Dm/6kgyTvV/t+BtsfnlIeMFdmLUWlZgzPn7E/k0Go5mYo6IQa6ILuCsVrb0qbd4841OxHLV4M6RP
/Ii0vrN+Kphb4G0j6gqwZig7EmOwJ6T7wJzArXjmEguFxi/kxfsJ6NuiJ00Ib3Eu5CuI75ghKb1o
xcw5SrBL2JvUF6UbNemoKKI+fKZvTbzFFevunhU+TmaElFfaCxiUJ1Q16WKZHuWfh8gF4J9vjJMW
dmP8Popgev2+gAuVQTjKOFx43POqWxICCMdPFmMw2tTF+TfKfbg//vArIbRTlOPEcZwvydKtci8b
mrDScqj/SX3VoV6z1yyq+a8KIoS+RYrDnIn5lvJ6m1ZkgFqzUR+Qe0fbFCwK7li8d9x31vOLTZe6
hQT2HIWrg3+lvFkZJcMwhB4PgkzHGwCjcPntoL/+9kOXhiIWggGwuLfXlkYVBgRuFrqvlC4esl5x
MGyUgjSmNF67lIDz1WZczqeAuxBgmLEFjfoibeqd9Gs3wNCnaIzQ3u5wi3DwI+G5osaC1utJeJ14
PFSAFkARpombTtWLY3IH5Guq4Fh25UtV+1JLLbXOf+wvOvxyxl05oFn5b/5VFfOGdVNdGdJ/Z9P0
WJJbX6A4wfURqqYGQgENe7gQ8DXwcbH829PhRF2BQmRK1P0PsO3qz9Z21Gn1zQgUSDW5Qb/fH5Xj
YxEpxJ4OMFublZrLw7nqI17fHKAtlDc8XJqttvq99vLMp9UYgq1cmy1AvbdKK0e/nmFfYBiQnlNJ
LZBFWB9cW94Bf7la7ReGLOCvLVQmEObsI15PcOO9kQ8J5+4y5EhBqtmkMRQpRmjmoP4A/V2ikJBE
uObhrObMWL0mCx1pMJO6TfxQkzC5UPF0W4XypdMRVbFmPG9BamuhBpKr2Jxqc7G4OpvLfKPhtqt/
BKrczvGmbgw5T4m0AUCOyqCBxQktmQo0RvZrPNTJ1Yk/9foI9+mIondHyy4oGe6S7eVPieFAA7bY
ALedNqOL9Nl6EBqKVT/XRDJ1eee76Z61HKc4ot4Ay1IQW1Sr7b4xjXiiiAKZfd85RJ6SSKCtmklj
RD6ibZjecR2FdcWUcH56iAbvWXKF92Voo+sSHXYD5GoxGs8Oy8epfJPIpFqFTJtNnt5G8/wngsor
w7dc/AmIsBaZsFN95lJTByf19n+He9NYYAXJz2sn+90sJmcSlEnoMnXu9z5+9sJAvcFFJY1ifk8i
1xzDspnsaq1CWkX1UN1qCo+i7OW02FLPywgD7sxaNhxgRrLO5wpvbG7h4eU3q3Aimn9dedL9oFvU
F2sqbsZEY2sZcuQ9eyG/4N8ZvPYt102HTwUMJbWSudTtbK75eaHZm4O249gC3A+872QYhs9UsZTP
opRPF2dMEzHBdwVOjaLoT2sHp/RPJsjgSQY+c2MrWLJHKHlCYUesEFQQN7E437xEwlLRo8lSjw+f
4QEwwxDDjM1pQ5cyY+WyM/egAwNJoyFwcDGAQ2ZI6bXlnPz0TOkYOIb9JQD5JvyFrZ4Acdn6n+qu
KBqw0uWKxPxKlUnXVwB9miRnRKxVbzCHOL/bpyWfQTW8pudmZzBiauO6OOb4eLMQUNQGcTnExHG8
Ksm5Kp206mCdLorsgzQmjyph6i0ApPvxBotSi1cSze8jmJCO7VFLBk39C8qK3ncSjbyfQXb81jef
gpCoOPZPnG6UOEJoUgh544etbIAbRJzuO0YZhHybrNGWpTY1clhmwmplXD4Vjf37isYoJOTW/2Rm
c+rlOA6RJ8DASiE9cf39iMbJTw+KISZ2foC2ZYWDr3qIY0pOiX17AY2cT+IbWKcl4fa6kVoWkdMy
xCgnoTx+KLpKVdPlTPeH5OoBv4XvqZqCwPkUJgyDiqVAdK/Fhyuk1nnsZKH0rFA23VndDKwWclBl
6/S7xddYYoNdRcogwvDAH2PD4tMBXS+ZU4+sd2/4BdRu5YXuwNZG05xCK2cIcvexgLNX0saXQTs5
3CpIS+gHRorwxX7+CsjKCaUsAqKahxV/iH7qPAMEYf/RNMTZJVmYXShLl8paoJPAJmKiJKRyXHRp
zuxbdrYlFr/SyaXYV1R7W32wMqWlQJKhdByHbvm9go3VaipPjnl0OIaWM6uL+sMg9klRxA6rRiWl
Cw0HErldMDFANLBp45LVwRqM2v+vOPy1xw0bs9KMVUgeNF+qH/ztMBVFjXfllcy74uHQDnJiSiU+
tZIEUFjbACeCfik4jiNyed+Ouf4wyLhRHz9LFXaTNAHqt0EJGyO3t9hgFIOWxsITTwtpGuvntRs8
AFVWYEgSCI3Bfwi9TWfiz1c9pokSqyUotoEmCll9mzUr9Icw2oUBkWVSMNI1sEjoDQbbgP6B3lxz
dViDAMFg5mstRdvhvufGBaFxQoQL13RIhi+ywRVH/Sc3RBnaDB0mvtl5YGChSykjBoEGCAlVNUH5
fKFEt+tlbs+IHSr/Gj6zc5fXlb10FkDONxY0HhM36fD/9J3ic0/vWiKu4a+npLegbuNRPFr+NMT7
za+tB7eivNj5cEVa3DvZpe939/Q1luBuWrlLH+RlI+T3pcVLvqnco49saX9aWWfXmVYzjJueUaGM
vHaUgvGFYk0lLIMBmHIgLdc/n05f780L7/LbP0eonmt92GmbgyurvHAZ6glHqJHeKo0oYqagVfOJ
l/p4xsNh+WTJM/FJeskdMc/t/xFzYcIXBmnBnvMSe6bFVuiKqKCGc/3fC2D5x8+7cBaMzkCnOcdv
tbmATFRZCjPmgKiLPJaKMh77ptUD9TEkc1hv6y4sktL1bdNqoYDDpFFa4fSoAYRcL06RNBLEZKss
PFIkeyaPc8eyOiXE6wWneJdfEeB/MSVHP9FFeuy5hxix3slpVXXyne9PJ3aoNKgpypr9SiVCZgQf
e96Y455PtwQrGPtCdXTRgqNUHkMdCPGyRAiLysoEQEQkWGb0t19KG9+oIbCgbxLPHnkpi+rNfECr
OZLZl7aKa4ASsurJ86QXiCMtqFBxylhaJQtLA5VLiQgEd3YvQHnZixPoGHYT6NXj0Qyk1uLr9cjP
tOJO7za2cscfoaWwPA+xsMHX3rb8cs6PiYc7CWi0sT6dlwbkZPavCg3CwLGLYnSZoKNNvIly1XgL
3wMPJqbOAUfCEWuWCBf/5g6wVtK9h7w5pU/zZAPDwm1iRf3SnL/znMs5Rhq+IIZQ7cB4239881H6
imsustX8zsOuewSA1D3rq8rBBhmf5pEHPzzEKoHuqpbKsugSRehywackhGDulFNhHBwLhKf6LUPV
7cXo45yUmPLYfAp/gmrDY4CPpXxcw4rM57Nnz/E5inp/jN3/QfOY75/xHRiNufcdt10sBL+3WYkt
fhNwEJpGS20leMm4+cU7jGkKv8kCh/cVJ0tEKWbBMKXpqiMLv6r6z0CExkfuDt5d6HtG6xRgwDYz
U6ndKA//A4ilaAuFOyJNX8QcgQlKcxwHgeNRnrzAf24TZWbnvkinF0Zs9VtfMbnfM1OAWlPCOlaQ
wTfkO1t8tSA/AEMBXjaVkRUs8Zqe/yIM9yT+Jxqp9DxHvj96ULZeNhOXJbu5gZzPXl3EWRS1FTLg
3HooNJsrJH413/3UEiXZosbuGPevLufM7fy5bFaovPLaGwwrYq9n4FEeHfu/pskjiLW2/GCgcwnc
wgo1c0apN7FnjDBDyo+BuIIOWQ/KPwKMXsr1E1ZSC4lqyMqpHkME6EXSsmDFDhrf7GBGFBnDhHb3
JvyeU77EI2fqbv9SlT/iUGkPXEKvkfnpUOihISk8jVyXF07OYv1/OUwIXwYodKztNXD8UXMYn7ue
fdwiGbIEiFL70SA7gdx4XaoNO2l5A4ESpwKhopKTOGrMkd7gkvMknmqp0yJgDFbloXIVGzDZBhSK
d5wfP9jTDe5mnKc3FyKhrM4fvxlLXIsHghebq0/p+zxXrpZ7+N54A6+jEG/bRxI4rXQeblg1sPQJ
lqeJ0rO7lRjUUqdht4O6IbXozXcTPKG/1KWXjlAwpLEmFYRtmvQui2iVE/8LtlbJ+irjEgI/RBkK
1SLX2ezohcGEyh1pAN0CZYg6FGSpwOb0nRADs0czypDfFnX2e9ETHZqUUZcFrmOehUbwJPXgn7YW
DCC6CeiOXJPt6n7IOUFmEqacaGWc4h+mzuRLo93AfBaKg0Id0AY59FghR4ij4iBn323nu2P4c41q
VtWkiMh8WdALpIgKK5inp38rrJjVUTDn8Za+9SUeWqmAT7/xdNvtpCSXwdPkdNxM8p8B9+N38tgG
3FZFGKZATTD+6cz/RjyONHtG5y8Rt+CfK3HRS7i/qPJJFmXdA/1CKWLGLyXBPT6/jXbuA+5Waowq
CY76+7C+Dc3EamwODSfZXK6AWM1ONLPwISe3/r53DlZG6NuaeewfWBlCeBCi4MQLB76m5POn/jnt
7U0REhe2+yiE6/Ns7iG5fY1Bl5Vkn2JJ5qkdOQR0UF8UYCUWBpJXPbAoMLf4wirWTHoJBBTOwmjq
6CEBoQOV9OQ/ky5MViV7xHYaZ++Ng7YBgoQmzGMJhAOZ58h5cN62oq/fozsoH2e52gZPN/qlPz0Y
4FJXP6c/NGVyThv3najn/+m5S7Uyjl/qtEKPu9YLM/FKv2kLm1EcOKG5vSoX+ZN3LqYuFJeuW6jn
8Nzg/njm69zLZIMGuMgbuRp4ZN1Udaeg7S4H8H3QkzEkU1IHnMmnesDKfuzP2jNNeUSCdPbiPDo6
a2lpw+0FLcsWzEi/oHp50T4g9uyypdmjn3RTynb/8xqQbFKTG1QHZV51aaRUpJ6BsDr1qVpD4wy2
amzaiAwF/K/D2l4ucZdCmRHr0axKpEHo+yCYl3Lt6IHePXfLMnW1Sy6zz0wSS3AOd2L2H9trs4vI
ufE+QVOt+Ni7dY9YKEWD28dlafSWfBJQuXDsSu38vz5HEXFpeEstf8VvAvX9wwFJS2q3zqRk6iMe
B6BtbEi0APjkfq53W80boGGIUW3Ey4I/tN5YbWX1s32h8i3SldAgKrb+6TwtVBIt66gomS/0VJix
MPwa4cIBwUJVRf0C2jSwY6UYzCxfbA7kduotKa4+X6CPl7gZCowzXxr7nj+9LsS8LMThRzDg8aaf
xLkIihfhBxiIzOOX+DF0rI4U+1AwFnW2pI0XcwJGweIBWRri8jG8yBoVJsSoyQo7ouK0zBp6fEcP
CCuejcRFAC46cmUPSEPCUXh49rG+70JAq0q5+ZIK13PUi2BsemopN7aldjt00VcF36urfX0nduMD
ySicSW3K9YLL361uC4cRX3O59oOKCSZVgCPIq2lUDapsiVBh4/2csZrW2pRlY7yOuGzvIZJbA0JL
u4Y5iEsHmjo2mEH5RPOsAdcpYauwaBKj0sWD7m+Xuo5BMVkMnFl0DvLHdxaOg9q3eqkmJYRs1E/K
h9+XyqjXP3234ZVZb4Vr0Hr4yFCgwyjQQHURHGNWe0zxwjO50jM7BqyY78sQOtnckAjCut6YoO2p
J1YhQwhMKitX1PDe0SLXiXcB98TxzGq1HBgiBW3vQg5JsotUfck0kh7C1iiTjjXvPmIBw4F2ehRc
Bs7rPj5U2mD6qWZ3PSgymuldNTXw/j1UA4kj3EKnSpigL5zZk2WHX2m3IWRNKi25Re4wty2HcdyL
7lS4KM4hPePebQwAN3r8K2+r+jrrpWovY70jFB2NWDfz9l9x9NdcaHqnl7Zo47h5MulLvp8P/QWO
QiNl6bX7GH1LUcVVpF1ZunvoU+kUxz78cmU2OMCHR+myOJzb2VHssw2FPMAnq86f0tbKWtNeT35p
R9WqPwIoZdL3tLQzIaxe3cYiIfdhwr9uhb3u1sVlnbZGlHZSLX8MDzXkaUKYYj7txxQfBO4p7cCj
80AdSOZNO1+R77E7ZEu2Bt3ZqzlHv5iu0KUF0umGYl/EszoTXx1z5c9mnjbJ+qP99qfn9G8qxaoB
iryYfVpCzpKSopGbsvVoOLtDJvE8wNF4tAqg6hwcKfN3BBF+JzD+WaLZnQByN69mmo5SsN6j4hbU
ZS7bbrQKej5OpOGErpN4PJYuNvONFjSiAQl2sL65JgxW/3Rc8V5VNi9s0XZJ69zfsCZyKaBH2pHO
auyvze13S2+2LK/rCgkdrzvZZzCfh6GX1z56lKGh3v8e/tv769y8QSG1gF9kUCYcTnaZmR/vK9F+
1kJb27ZrhXYFyvX0BJRXZMqSVaRj7RtsP1jlBDJJLK+tU2sFCX+kda8b9fKyHLIEluKs/xWgTpx9
bonWnF93Z+i6Uydz7gNbbku4FWBPEP2HcGRANrUC6eNHuUlWa2PXZlZ4QQgbWi8d5itmyi30U6Qn
DClqazY6nhB+rFvmbmWQZhi1889rsWoMozwLB9GxhXfGu20H8u17bxmaJbNJ+fCxrp5pMetzrU4J
MvdrSXkQ5FJVlA1CNZfPLkgPCk9ZSG7XdBfDZszwPDPlP5yL06QUEQOAHIArQDc0aA6Q9TLo7TRt
sBhI0WpcNo0fqicE2GJNIYsLNKiBVl6j/PSrGWF+8eaDayQyqzkZXyt45uCKuq8EqmvRmwfDuUYF
Pq3EwRnxxbG6DMvX2Qf85tWxmG7dZvmd40CHJsvRkfzUu5sZu2CJ+uyL9DWWncLYAy53m4n4ydB2
qo0hbT0HcdhhVkEpsTcDcra69vB9MeRauYsAUHU9kloEcRiYOwCpbvzMfNA1KezTwp1QMpACHBtI
wlEWKUmC7zLc8uXyHdpbgebGbMZz7fLD1f1RrDD2CWnBp4WuDHpPO4Qu5ySrcyVWArqyDMIB0Mf8
uXYcrPzJxZ0UtHWZ/mMBEu4Pkcdr3BohuXhqwmR8ThE0rDa+9YiegsTyDJBrXGBcXzqJWj8PWK5Q
MsfNVDOMjZftGkIl5IFfhnrPKdjE3T+XhJswf6eT08LyTMAyjq+GxRqrNfRL3smh6664+C7rQ/m1
3TcbaTojAg97Scm6NPVC1l0U13a1KLu8Q6HyIdZV7wCpUKop/eVAzDt6mskLVZJhfKYlJVQEfLPU
nlOsDkb5GKLnklokmVzoVvJjizIbxKxzx7OlfbhmX/pxnQqMZX/ndqtAyKk3XM1eIVuFWkLWjE26
P8eUntNybiyFJ6t3sLn+2RuPSkETax9t0kzZfI1Uv9xOnoclmoJadJtKn/YtpeCGNTpsx8gMs1cN
996P3jCMuamftXtOECYbC/izfbhMPSywrauKdo7ILDg2zoLOkusLxfd1FOWrJ10s98mI1DfVhQxM
L4YcSySNtigAwp7+cWGI+HIJGkg6FfpA984vEeTqYFXh0ZhNHzr048AAuObecgSkPQ0+25rdmZsl
JDxa9h7Q8JCPke4wQ3OR7KCTY2fdKEwkHztpi3x32wq1oCkQz+0DLgKLi9sPn0/PMtt5Gn6/sDKk
CSMVimwpe9TzXBaSsoDgtWBsxpiDS1J5eEE2+4qG9XPE4/ZIx5lS45eeKTJ2SjatkXQNnIK8eLNg
ZEgqmbzUKjg4ciW1csqjDqK9TCt9bi/HIcLpuuRZf27cVPUJB+ZY4b2t7u0BT3m5R8a+sres0cMB
PHX4xtvlHnzwOa2T9LwrsogZIevDfm/2yFSmKPCKn671pRLpfuY4pChKqrbrj66L8I5RgKgD4t9k
7VFGLG9Y7fu2OUTPxb603XDXyWvA3tS3FfuHDCcA1s4I4qShxG6j5ZfLZCWDHq9EZMO7dULw3Typ
bjD+jqps0p+SpUyY+aUy55z6o0Q5S9jtOISPjZy7uRY14n7EsCpGHxQ4uGY8yZJwFD+9CYuGnopZ
eL1bEoHvC9ZhME3IW7gvEgUk9d+bJgZ/ECerDBV0Cb6BG0kqYK3WGi35ch2wnC8R5Xi0tTvL2ope
mkDmuPjrUYq0IorBvd/OypTBd09mtNKi+wx9OLqi3lmPqIMnynWFy/dbv2r7w5RX9WoHhWj9cNqv
OC8q1jKndQlRZT+/w2A3n/n9nxQha+IOtOBzzwvLBDIABcy5bsFSJVdz1XDi1c09GPKE5VNFxWZ6
DgY0xv/aMxF3Wup7p5rSjlRVw0IMcsS19lFiPi2Bc9+TXBMS2czu/s8hlQ4UaAVn/KgvQbx1MDIQ
LbWI0dpBQOEbEGocrdgu5QJQh6HimneXCHECOdPlbS42g7Dw8/o10Bx/mr1LwqCjtGsGzhrR89Ze
VWh2EIWPkMcHWm5SalzkMBVcuNMaoaidX2PoGD4Qw0a7b/auyHOzwFpQqw3+rOMV7P01fgNffJkT
lztzloxYXS3FRUfAZLg7m6Ra+8EW8xLu/4IAeYI4KT6IeuFLJ9osk/h8EO+aFVR+wO3MMyP68d4W
fMZbdGoiOCwhE59WELDb/ZxSwvw1dMkVPNozVX10uB0yJLbz8PhzqARmIQ+ourxUByoTUB8fX1qm
+1StAehfl8Dv1aH7Rc1iYj7/twFbbzN2oHD8TYLQThOMpFliubpRZCognS2hY1cd/0MPSEqOOWRc
KOO2UCJJsOIcUKdKd4MlX0swX6AmiTsvCKXeixZvhXQL3+6hFFPacXWkw15ZkDUNfrTZO57ahEzG
UvLqQpEXa6zqYP1kNyMWQbzLc1ifzXWLWpCP5LvNtoMJO0syUVanub3NVnFGUjZfrs1zb07/Wi5A
RCrkWKYL5+TP+ULlJU1nEangUDjg+ZaasU8oljcqmJi/fvQlxutD54ZnY2lOeh92geJnXEcbS0tC
Zy2fjGx1WrK5TxRm3TOwpP2Hyx8ZZEJylKCd2oh0Q9rGRt7fJM70NcFNPNXmt6bPJy/vcBpOA7/Z
zvbI0zyTTfsYTlmJhszeTR3hK6S3SHMRlx24ZqItPk0FF9oWw5zXsPxj36XwEZcja+HLiWuSjd0/
R8ZjiYvKuFeAqQ2rU/wZuF8Tinwd/V5fUG5WQVdlNOWGhGc0Fjs0huWQaZoWiTsNQML6OBP7Qo/X
pukZwH7dvbLdvUEWH0Wwf3AK7TYR83ITqiHCuCe5vElZ4FCZQv/MVxqrNninD95EktsLvD3VKJR2
uxM6wHLRawJH0T58vnHI/NO8daQnM+2eRu3BlGgWTAAn7S+oh534xo4uZ2Ugb9248AA2eKR3fpd+
+Rl8+kUVj/cK21bo1psdRkuojLjXEGGPJrpp5Ysi+d+mF/yombt4bTlwPk+vSfY7bKHzuMtMRqRU
u+z4KwvC96rn01zNbIh4O0zh5y11knkKrEZ64TFpvBzCSCYUaMCSKx06982OrnwGejd6ay7tuQcr
H//n0te/1ZO/XYMaORmDInYH/yqMEnQsyCWRB36JBpW2OhmsJAWbVYimRgf7Ne6+0ejEfRKnPT8+
laGEsuA0an7lU75zNeFDhNefk1qTHhlcOls+JGkjKbYLRNNPa6gFiukecjS7/iwoobcezTczGwJu
GoGBdNN3ZZEAdgUo278pD+BYyi4hbQ6zW13sjc5axFDevu68xDuO13M0burUjcdN3S6SAoG2m4r0
oY+4kWZx663Riam1/Libh1B26FyFGhU0GHt0sKRHEr8HqD3UJsAzy3HpJghgfOnP86Oz/G6Cj6UP
jcrhScRlmGiYTnlszF+1gqo2URRYV7mLP/+Uc/EuUdgmHFIVnUU1IvXhgPn53DUgPJzXgOIaIqDA
Kmww7auU/0yKsayZghipDjo5BDlF784G/Wx9Wafo+aKS8xPowP9bYB0FS3LYN4WDrDvGHT9IE9N6
wIZazLr8gVys7VQkp1FruAULmVIvlA1x42AJo92FC06vB30focIAq6yCYHiZXQ69JNu3LhpWUOZl
EwswNNK327Z8A9rsOqloyBv6R7OFSV9KqmBGS8+n/XTA3D5Xm1AsiIvAgGj2q71M9A90UzWjfnaF
RZndGDsn5hs2wTa5s1EMoS1Ny/33MRqDdYywfHcre12GkS3GrmulufbGvDDPegtIlGHizeiIBP7i
+kIxyfAzI8LYpTJuuNBzFpn25DjscxWihy3UgB3SuNvo10Mx0rpOTQrPLa5ZTrQtw4athi1dDzR+
0nhNVEZ6d4AefpQJ9FY2vVKGgsIcNjTyvcBrF3/XeJV8lceAhwin1Za4YfmQul3GSr9XH0AfoJTD
CDHVUzePL0BA/22AzbD7Yr7XyyPbfd0JilWmkZsz97eKY+SoQLeZ4CLxao4q2Tqa3fsh0GAg2BSm
9d1yfZsnZEXJ5eLCQmWXnkVpehE94eZ9yit34uWzljHTiVuLycp0ht06ASaZwETnvDbz5r4xwErP
Jed8pVtFDM7TZ2d7nlXj7mZS4wb7+9fB6V1B9Vx3FSZ71vdDBJWXTwuGcSfcRtHVA1BVAbBq0ZHN
XNQGvFhFUTWVtr0rOVHUWGqGMMWmRaJyzujELOMfcU1BhSMp8y19oQkVP5CR6cfOZUVaCiEpbcRS
H0r0+XlzCudX6701vXF+JZVjMSyIZ06oWjANs/JGFRMaOF3uBJSETENWCDWJibkdc6jloVj6A7Ve
JP7e7ID4t6H7clyWUwapiavcflmW/DLB7p/yenIkyWv569lFL0byaHkitg4gMObtnSLcDJLOOoqP
Jy+Mv30NL/tNGtWBZdyTMk88HZZZ2i2Z82mlONIHf5v0QoMDS/NVJhCO8ReXrSCrYKaYtr0KFTL+
S08zNFbiWHlH4fYUwM9PRUeI+LAnoT1hR3+4y60djB89L9EfXF36ZDYTkB90wj07ocVVp1q+BxOt
1Yni5dPVsWMEv7x8L4Ke/vKoRSevsAPOccdkNbJh+yK+VzFa69c32qdsZMycX5NizkyJNko+eo6v
4I7eA3O+f6MuxEtrB/kUxDoRVMNqT3NGAJhF2axFeoLDkF0ZxQ9Tk7H6OBbvmbTd954GY9kI9UDz
TWLREQb6aVxafz6vKkKm4rOeOCd8oE4mwXRujWQGMs8DxXp2xIfx3Q0IajyCOZ4RFDlKlKCcX3jR
2E582PaDki+hpknumVp2MhVIReG/V8uqNAebkWRX9YPSdsEdMjhNpR/7EOSiVpK/7c1Lh6BtwZ+/
cjz8PDoZWE2qvmvQbn2QBYn7jQdlteiTg4Y/f0+Mkkw8EqvrUaBqpBoMu6wYf4XhtRSPIIRQmwEh
9Mb6zHyxr7MfFYmq5j+N0nsJbK2UD5QXexr281v3ZBaL6E5gHD9PcJOgzoqu2jMtyZPMttI1zWDF
KMVg9DO9oz7zPToarPzrcOydqlTsGc72uZtx+2Vssg9DQC3giMLqNqo29dNibC2nIk8nW4r1f/zt
0GuEbTLb4+gDl7w4JldHHYixngfQ+vhXKZk/Cwi4S4fyFYckV75bvzRF8snRFAbNQJNWVoQkKRmi
/Osp4AqPomTN+vcKH00ZhgWga2ppZ8wsB1pCruf/PyHR084IMi+ZA6EgXSaSQdshiZFUm0W1dUE0
UufWyEaL0DsI+kJ7d26to7DQ9bunSuM+6jcEViG8potXDItIbd94NiUZdQsqfopSUWKYvTDlq3nv
13YI+F3SW/9gvDl6zVOKdQok5hKSLaujTSBf3chylSzntpay20wgUzJu5NbHHFufdKhwxqQ+ZQwb
Su/qRKwD/9bzTSs3ADxydQTzf9x9BYMnmGUT80+DINwfC2DsHXLRM6aukg8cOP3Oq6+y2IAnx4jd
WZyN8BPTV0F8NRrTxjcvnntAsiRbL6trHo+nnn6UIPha2/9QTbrkVyuORrL4mEjkKf9FfQzFz5dH
cSTUPMSm3WEJydfaZzxrK0KiK9d2UlNDcmh2SJa57s7GG4wb0W2BJRkSootM1nSVkE7omaJTXudG
EDTwTsJDaG14Zu7RY+HV1JLDVmjc+TUVAsIvtRC5XJUQLbFTadAkzEl8/j5u50VcoNoGKiiRhE+w
qYC8P1mJwgiG7MJh91y3Br81HcAoJhjSMgZk0HkbOCbhmXhbEUZEUWtWtoWZjTMRGPOsG4eAAGwX
jITxxuOMbEdr1JtGJ+4WQhLwwkyUPoTLMp3tfmU8zg47b4AibJhB+4VBYw6pj9u5eZBt+ewuzo65
y5ZfwC4HstR8R5Cj0NQS+orG7/SI9GH7DDqulertAWFIn3NNDD2ZMEqMt67jv1bQE6cAObHWjoZp
sgaDWPI1Fx9X308HbUho4CtN0c5ILVi8tIvTTb89EfbO7X1NdRJJcD3WA4IhjYtEaVbKJ0N9LKyS
s5Qk/IxeyyK7tMIjRAjQo1mV/0Ylb3+aacYE4YjTt4LCf+hOs+rYFoR0nyhGkFdUSQWevJCjdhbP
Qt2nwntHc0LO3rnsMa2pmka3eSKVmDM7PUc0uao+ACz07iVlsEf4hDrySQZEVmrFarJkQZxuTaUQ
CxgSYU+zr5zkx2LLEdLTUwp1NpCouSvZ4sPOLMaoxFhgUkn+K/fCiLqk7X72VsOjIRwUe63lIUUq
I+tJQo1P7krUBSwC5au9YcUQzokQuvwmVOKHJrC/oFveIEgws4t/cQUew2x5/jEZWIBAxAKXpqbF
AbbMHICRuWIsTM8Qvn+DbnHci43oC8iYk7VUqpeMwIo6NeKdTghY9dqL/UNLX5Ni5+r3zxrzldgn
11BDiJiEK8SXNu0o8T8dNgNTwJ+3VuZ4ilYq946aebY2FUWjXTS0CN3mmjFfqplyLR5xmVnvuQnl
UiZan88yR2Mv2T3EhAdS6zRP59gQLFYRsQOGIU8tp5G3qqtBRvJbsp5bHRLHh7a8kz4c3vTBC1fL
AzooPnyl7YQZF1oqV4oCyprS+qHakGvKJ65mf7TF/2IUosN+8j5n3qfx0+Qb5iS+SYsfID3dRs+A
YfUo+Cj7ZBkmKGu+HZJ5HY7C0Qx0ZjtkR0WF4B1F8LoptikBRo8pX4Ph+qFHUTb/CMlu3CRQsOyI
zqvJa0+APkshBnQW57ClYoI+2onevmNyZXoBv5Q81V8dlQkewEkHxHgBevGLkeo6DR4SYgpbxzQl
KUNNQG8CzSCK2bpuoP/OnpUYRaL1BiQJ/EOc5WQu3TVmzVf3efALoQZ/RjHW1Y8liu/Spzrqa/9+
ua2GfCjSOiA8RFSDt+eJzpOFdxFahuSTuAfvkuPSOOD4ZW6uI61evM2+XJjfiLT+piI6imt4fKBI
gLvGxAErSpTz+dQ/ZsdEpWXkTIEcPQtMm9owZplKmS/F9FaKCxQAPftYk5ot1YHakaEjiPaLECKH
+HMCS0NSkJPaoc8FSIh3HgOTXO7Vw7LeTxd+tt7LJYHcokhlcaGdX8YJ9l8f2N0kPaR4ClFUBST6
43fXskreX27DUUvkTpf0sbkEazth2j2teyK32RZPfq8Hn5BM2zwpUWd/7YFIW0u8EzdnUKd0HI6C
5lfWvb3jnpDD8hf/RdhLw49wN+a67H1ME9HmK6yjlPaMLgsO5fvDcPPcMN966Izf2vCK6akFRjlv
qNNpt1XEe13pDbW0BqrZoia+Q+c62pavbIohqLgB1vrfvvbRgSUs3LKt7DcIwi42x6ldVvWqgkWt
8cJzWZla7MQJTbTDzSoQXmDfSpxIkrP7ZGKaasE3+tNTCUAJvoHMiZsrae36PUnyvtp5L4+0+iJP
i07i0OFlrNjj2jVi7Tyh35BL0soBEkxwPTYDm4vuXVpMPPwvH/xlRK7zwbqXfgB1WGIeEu/IWx4g
KCqSyBzz+2OEW2QFsoilN5HkKw+KTNeB6jRObhyQR40x0IVo3WOxUe9WgtEkVrBrAfg4U0E7S4nD
mcq8w2857gOrSIhkqnVyT/QtJil+iGTWbtza21ngBqdVebAZId2GYGafttI8xz4ecMubBM4IHfdJ
Uv6YbZl7jucnD5QUQIhl/yNs5k3xhPkpgJD09Cq+dg0bpLn22ZUlhCoszYTv8k4WsliT1jKSiIjJ
Qky4j6Suct7wwCvfLTn1PdvK8K9Jysl1GwYZoVPmFZoA4oBcbu/eno5LL+1yAk/4J/Sw3Qy2Njky
aenyEhNjUBDgW9vCvHPFKIpdEk9RcIQFIdGp6svNBiJCSz0CtA9XOzmA1IT0XEJmcgqNDXpR3eEj
vRmCbMi4KcRiPCCyTgPxBuqQjyRithLDmZk268U5wVDWXlerQjLhFStR2klKwuYRGTngysUA5smM
X/Z0D+2xXiZp/zXm9VdBLmxLKNon8e++8mfvWiNjWHCtgW4o8QQblGYTUQN80Y02TLQChWXIRdag
Fzv8RWY4S87K9L26YNUXCJ8JgN/UxqIJHB7v55MPyEDQ9db+ABrOeJtYpeg51POOesdl5MLymmTw
6ruz7E8s0OWO7lfbTPDJW96y9tICPTMt7d1D/n0pnp0MUGQUOJ+CUoeH+E6sa1IboAeHNWcX7p8X
4OLBMV8hC82A9mPS59P9A6OpFlnfUU7puIAO1IStjzD2M6ROgpysU4t4U5hjRs5sGNr3PKBTs6rk
vQkJNeLaBYc+D7m3wAta3JvCnLAn2AazLjkiCrrB7ZlkPlj/YuhdoXjx1ode6o8vqxHNbBINKAQG
SWjUtIhxgE/lMRAJMtrtvqq71XjHKlr0fbIkQa3gkqyibwDd+iQa4Vdgy+0FTMj19kbsod9c24Z7
kgk9k7LfrWErD7vlMPZSR0UTdqpS7tUApK1ro/42tIrR7b2b8oInQdLekzm7M3eEZKAtKbtvaDtX
yh1rehAKKN8Acc+NEoY5YhU+NbW4dnt5Xw5fxX2zECUcZ83sG+uPscWuMUjPwyt+SbJmK70BJka0
HJSu8BR5MQBJ0hqbG1Dl1pHWavP3U5/vnT50N8wzBxc1qYM+1LA4PzdAjnlIGptsgqLMmQiJSjGr
SuQ0cgOloQrEfNCvmJCx8hLaQIfs6gZASjnRtNqSGsrsu54/wOGTVPFaDI99GSLwW1tepUEgum1y
u9k8CFc+EilkcrPL0exWX54my2zyz2z2+hgXgnSRoSQR7JKsLEg1hOO5O86p4ECxg0tuEK37jZc0
8id4+BeUz9Bsu3lmMwU4ga4TDbY4sUHm7VVfoVpOXYMsSBoIha+OiaIWJRfbBpaD6UvO494RkhMu
/vhhOZZmBmCTerX/VqozQJM8YqSh1fryEFysdEP8GjiBD885njFDZyAp+q6f/cgRl/v7dNuSxF3g
3RbAb23+CE/j8skU1Pg2TfZCQ1flJ17ayYaMjuoJTcjVAyLOtEyfHb4eZeZ9tRrfsr/TglR5nWNo
dEWrkq88JCeJikc/bA250nNbvXElmlrrG7VIMG5LYE0rOi0bNXvV++cm2DPO9xSY6aPhCaoYrx7A
bQZMYTpOZ7JRNP91BjfPNn8P5RAQnU+PZpNvyVSAuu7MlzfGEcmpXGstJqkLejAEw29Isyiw3tDe
JfzLrDjD6UXbBAUPMSCNKq3TZIrWr8t9S1GO1bURNMNndXtqm64zBpkuclxu1aVUPILfQ4gCud/7
2v/h4bw1GoEm3SrZIA4LgqGV5NZIKOwv3HWxXA68XPvLjczQsw6K1xZWhvxwsXULLnpnbCe7qfbZ
vIRd8CZOfCr7J5sFgEPx+hu6WuwH0bSJiqyme19wb2gvThU24T1kJRKH1kMi74QmPkkt/jn74dE+
Bnj3sxl64xGcRsLBSH8xit1ZqVUttyD+JZGzySnprPczPJs0231sNaAkJ9Lpd8QMdddwAFrYG1B4
hKuBe4tydIRcdCVaZTGeNaF8AcfxoLNen7pNNoC/HFznSB7hkqlLTLRC7iDHSylvQ/mPbECh04eU
t8258OJ+tEXMw3pDjac266RDFU7hDCUGtT+27iDzWaY1RHjeVZEVO7W3YtfnrTsQ6BjxOQVZc6Sv
oIgxy/VDf4hUmOxJyE30sR9jaU6ij/eBu8qHtZAun/esi84shKQGwD+8xyscuU7O0yBP0JXLaS6a
6QnTzChy89TwvkHsqoxZi8/Wsn2sbWpJVq/yoJt6OhowDY936sxMpVuYDHQhL0bhl5NpGS7G46tf
qTP+V58jz0P7unq47wSHgDpjahjy5R13/2AorbYEYfZq9TWkOSwft8MABl+YCan/IBHHT5yRH7tt
TUyVIY+e22014ObvI+Iy8ESedba9krgo5aqDj+WCbnoPPtTxjiIZ40w3f5ybVS9XFnOb+yqLj8zz
KK79WG5PR4tb+rPdMDaWI8OAxL/avJ8je3/hdBEcmsGfbWER/vO7RGo5HAR+5O3lasQoX34qzOgg
bdEwlcJdWr9AQcCgtfYkSo+TLLegiFF6//OTq7DCVXv6Yv6OtZ94OYwL+bLnPsjgfLZ3lgdtwE57
p4maJTKXrZkHgEtoxBFVCLWNjsjspPqfR27WjOUpRKrSYgJXeiOClVFf4fzS7H7cg+dMSQUeUI03
/0lb/9lbve8JItRbfkhOlN5KjZdGZWcoIvwYtDrA1rw1vZi8m3L+QOhW4n4ovdhh4UP+xSSaKShu
2vPpvdeMa124a6bOfwmsDX6w4D5u+2c9tJqrpZU18XaE2VrGvd4ROl5Fg6Rel4xOUnDSmyjy1poG
BRyj1dfKtl7cNcpl5ku+UVDr8iRikL0l35w3taQsgtN616KA/Lr276KTi81AoV0mQJATF5HJ2797
1sT7sng5j/jvzrVeqo4E2/T09yZ1O6DK5+TH+gS/3CGg8+EGDFtZvBj3GRCPzlsbc+2cZiM6CNJJ
fTJgkA1FXUDZ1cqqsqSGvjdSfgejH6pTnn++1J2wDx1Mg7lnihUmgjJA/8iLmeaVOSguEXZARw8S
eakCASqbSz678pJJTaSFQx1QXht4LjcMp5MuV1wEc6X1EuywXC/f1YU617WRsodX3dT8xQSkoGJZ
P1D+hTTUZkKy5DU7cUaL+xH6JRjAA3g9ZpMiIXnU2b/haFSSN2SkM/wh31IW/7DhfWEY7qYZtc3K
oHjogXAHzQistfuYbs2mj0/w9xpMbvrKoqX33qyOX/F+dkPmLSlIvGiYhsF03ga5BaX70DcdWdw5
MQHShilc7AVqWgT3fEYAbwXILDdfyelDBXHKVzkk2xoqneSe+Px2d3Wm8ScJDeDqpmzgo4Fti6zX
zrpiJusRhzBzxd1KvnKdm8jRrZtqsTukejFq7Njh4D4aptYpQhVIywBQ+ZSTz663wJgRAJ3Ib5Af
IWWu2+bQEB66O32iBIvBYLEI6YcN9H2LNmmaMnmotSa+8nfFPnK2Q++2axoMgSU1Vpn7Txoup642
QqrAmzH/BRbz3IFH51cw268eBTnokqyG36LxgduhiMcFgXK1LY+7M95zND6aOcomNgqYtxrWdiRI
8lqtGC6daKi7xJZvxC/JvFw+r10HdAw1iNiprFoIRU7vpCU5zne5g77ta+IlMOIhGVMH88+Aec18
4XwB/aRHL4KiBDxqFAcugHUDzfvms9LX3VnJ8BCi9vR9w/F7YMLU7Xsp9ENp2H/mOpP1kyO9uPKR
X7L3pQaRQ5z+jBpb47eBLMBBBqNbtPFQoz0aJ3PHTL/7hvmHaJGaRRiVVLoAPdSQAdAh318nqbAF
nDxG8pfrMd2+38KU7IJQbxlxnXBVTP8+FU4l6pauO2e+pFzJQdUegD2DjRyb7vL198VeIFunOyeI
ENTpRSXrDTiHrJRhddEvYY8NCUd90xhj6kzouerEZptK6sRppC+oPTbmJ2EczqMWSVAsDF/Oe7sh
rzGr9vdQvSKyetq4+ACJT6CakuwFIVR/HvFaC/tKVH7sfLG+Umqk/KGdOQ5beYsl5PLekJMMrg9j
nuO3EQPDgvcjzROfTc3ECE1nmv38+oldgiJTCbvj19dvh/DPUVrJ8+o7X4dVQugfat7ktu5+FrRb
xGidno5/FvEB7M9juxHODybVXJ33JeAXdo/2M41qZXG0U5JgHz3nwgRFIugrPEVa9QB+5RabwDst
vLCRh1KFBt7O+ZBb7aBv3/5QnUXA9hT5Tn9BHO5/H4Ym0IodcnflPurVQmAw9VGM7g1wpX9MgcNc
/H2XTPlZlI0FD8xLWMu11Lqadh7gYCE4c+lWv+FkJ88nWjD10YlQqNs0djFVPIdHMIfzR4yFdzYP
N0JcXfzUM7tyY6vWgb4356vvjJJbi7jGmeZ2sxd7tmuErs+1A1dF8h+NjMu1KnMWfi3XjpRJL5he
ZGdzFBsWx487VS3I+a0XR7tRM72NQGC3rptIFW4q9cgaNcjEzCpMdStLZBNeSpSJfp7C1yt9qeYO
OY+/d4AC6h5F6vayLv4mpwIfvAuuBGCot4M1B5/UQQcgGIxr/SvBD+tB+5tr9S5ygNIUeG60nFlN
rzzEEx7qLx2sTH+v5F1KyFVxmNK1GCI6/1mgAdt3SpDc/F97NcByDVBbUp1CM564/UyPYc578HKu
YCxKE1GMCz1hVGmGVv3CV/q5UFaa8xOrKmOIyKtruSjyOw5b9e0XDkd16/i02YLPNxEYPG/HN1hp
RNCdgG79umWT1A6rhzs1M7JqAFm5LWakTiIKPCoOLU4SNc6ppQkHmfzCoelPLg03OjGrBN55//uz
LL931PhBrOM0iNJzaqzPN3GRzWy4YS+2YnxcO3h1tVO11kWUvcOmDUuBJCYE6qNBxes51EK6L6sy
FvRyKq5UcQ8d4xOiIdglGBB/KnDHvXpBJ4gZ979bhv190Nlxg5gdJFeSV6/sSh3D/UcQUgZGn7Ra
TtbEdE02H/EkF0hR+cBI3WSxC11R5iD9nAjeLqYMJY9q62BNAO8JLDOP9hI8djl7ok+xM7dHQB0x
u43CmtlYyEjmnAYJIE0VjVVR6YjYT52C6GrI2KKZaCpPVhTCpkT+jAirFfoXaJLgchL7j9xORRGY
TqnFqrccEFl0nPJyQ5zC6X7qu5yKDECUps3oPnICmDH1OaDtmjw5SCooxH0EpT17KkBSlxuR17c0
9lhcOLt6wAAAEqM9U+usVkouP6dTqWQBRLgrvemiYWyBK81P4U5FkxGJiELt5d7lN2YZ3AyPFkxP
aZ3VQ8Yv3LTKhBGaG0VdhQ22ru5trK9etg7w/YG/57gwKM4SOHgjGxuoHcq5PwjOYCOuBPTwsA2D
PV4g6a/JSVXUKnNgqJ764EkwM3txB7GsC+XLJ/gxTf8RFQCWSMeTcamdRqz3TkuGNVWNOImr0pit
ORwCHbOy28HrWbf3scW2MO38pI2ymbo4xe+DLEdpVWYeaFyCB9A6igwUU26r9MresrDwS9vPaw1k
z4F9ALDLsyGAdQWMU4DspZvF1NAPaoRbYFBHUrCeSEDicBJqTH6sjDIzflNKeWw1ohDpZa9Z4wbp
qS9TKjso6BLJeyAfR3ogsmZ4L2jDv6aB+S2J409WaaxfuWofxuqEs12uWeQf0RvsuQfwqA7lXHAO
cXenF68bMQ453+73YSTYFGJuxtgrLBkFhCgq8XSd9FHVP8D0DhEHl8OrXMjFlFQMgbiWWLjvjpxM
L3NRtJx4Gzq419UvpQDqlfoNSlXlrE9AweJyzy3RrR1UJaz+Po7txNVCKJhJZds94fgNSjbKAhRT
GzkbjRqz057MzwvBw5qtA94nfJI+FmLgd8lM3ynO9L2Ff8nGwKcvEOneAl2adYRKnXs1GxzrSqnS
lmczy+yr30DNOIdSOZcVCIloWY/5iDcEZPU0SnsGRWkqKZtufhOfkd79DpnvY2OL7RQqFUptWpUm
0oxlRdTJWP8n2hRZIacIZKiOpb2HRqwvINDzzemYP0yUld8+pfqJJroi3q9DuYojLORQLKJaGNdM
VlliHzrxT/mRQ3vVYeCcGER7MZ2fjpYM+De3grKbRskbU0Xnvvog+Iqgd+/xClqoY+ClqD4WvmnJ
Kjh6ASCbYOIYXpCi1Z+x6K9zhtD9n8KzhboRkXWxrA0wDsCizwpk0GN9j7iJKqup4lgca92eTaL+
wXZLuTBZ4iX0VIG/JFlqB+IFqUjNTq6QA8tcGcnBqjqkA61otp9oRkmgdwBENE8YnP7gfx7+9i8K
4FKEh+pJZnfyNq2Zpd6fsB3y1ASbV0S9dah7MVeM7cyy2T8bC+mQm+CGRv3WmLnJg1X1SzvAplno
W96DNBfFPFTfmtOLOEld8y875xFcubiuK4Rz9XCo0EzDxJn6Km8ASsyh8JfEcYNgFPPIBxYOi2vL
2dhb1lTiWCM14LqqQucPBKnTPlzeVV0fwBILBJn9NNbU/q/158xGSgt5dqBCKmEpdhqsLjF1k1fy
TrfY71YtmGUGJakFMT1xJlbbqCTvM87l9XgNgUIDQl1muKItCE5ZOoI4XCVK94Nh84jo9gMZ542f
0USfy33/zW6vUSnr7e+BJgT56FqJ/UHt9ez29WXxqNzAg57DmHS55HpKmx2XQdalvmUaBDTFIhmo
tPwkLbbkOC4jUjLCBOTPYoRwuyCq7qmUR+RPKntRH1ZNqw4KawLiFX/s2Gh8aKLcuCO0rIfLBybz
H0QCfAHGbTZQvIyxxqKtESS1Ka2Vv+ZHle8dbda6L1UUJO3ga1jgYRb5mqVawV3VRREUBcp1yKuk
jjIFvhVjbHDIqoS86JAOhSqXqfjl5cFbyxQEDGy75EGLG410/b+Ipe3YHMOjQTW74t7pxA0AKZee
HKk3HUspWjm6rXzU3WdOlrEvLyUWrk3oPMxsBX4wMKkN48zVxizXWQ+u61s0SVIotpm5ali3aIDP
Rg/vsTOon8SlaxYIOY3WUKyl1Jl8zbU3WKV+zP3v8StZQ6JAi+IPjDOJoRIXFLUQTiYPocRVsJ0c
Z3bmDvFTY3gft5T6QUGmTpgQVjmjiv5MBG4uqthzn+7Re7oSMDmLgQ+a7W0idTJBZkC8T7XJJrV7
M9iY6Mi2t2z9p97fH3g2Q0ONKMcPqPSCcXcdou2xr2RUD+h3paZOOKxb5zbLffzMvpvpvP/LVP6D
qyYGwImvX354hZFgQjip2tvmR97Lyh81gMD1GK8ST651vaRpQzLVE4OSyTRheVOwRFIcsqdg2nfq
s8g596wKQmHGQb0uHjFL3hJsDOm+PlNyuUjEZC+DqUOzurAyhm0mXR76kbYfGYtijaNsgNWJaDB6
8GEjfFz1QALeB50CZzR+jL7hwxSRaLOWLUmTshYIzyaiDBTMq9g3rOPswR1OpOXwXXfp/e+a4dDa
vDMwPZr7APNPkHDoq4kxMiPESoLD/AtuKjsXSvacv5aD4iQ7eV+ddnGezOKsP1/huMHtQl7iQpyQ
wipIy1q3gEhim53msEs/NQDbQU7YBBbJEyo793FHrokZCG8WJM/LnpGcinBogaO3Sa/NLJ6ata/F
sBNmfpq5pW5TjUFfNx2j8iJiXDg5QQMUif/mGLeumwfrZIP8+bwrGCHs45smoKVS7DsHcGuZxJjw
lCXadtgBvyQc3NuWzunmKeiXtEY2ljey1UpqlavQO6CoCvUvXqGmRQuzBwcCDNNyyKFVo/kBjGCa
gc81763AfkE+DKkUHEB2tWnEQKpgD1HHOpTQMz/MKrnS1+GKVls3LeLlFPrlyX75y1Nm8Fo14Hj3
avfP8TCR3RsWPTxNqBQzOY6wseqzDVT83hsvF9OxxX8IK/dD0WWTdqCTTRktHK7CLpkpp019M45J
QsVxvZMhzE2n5Hu0jMimBcUlHTmyWTSv8PMVG+vz//WZye7Bmsv+5UraNYtJRTYQJGpdqypPOQ==
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_pf_sshft.vhd | 2 | 20160 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
F9G6dpNubZOdcFjJsPg4yGA/lxMn90z+RAo6UnWnrcihwIxe5JWhi9q8L+/4/oREa75Ngvk7DQVE
g6seKWp+JQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Hb6FKCBzWQ4rBnYqb+vORxcIRgAfgPQbSN8Lj4sDZnZBaq8G4IMUME3iyIwZHkyV5R3ZUWNIHIu8
ksP2467Ea/TPnHKYBC/F3fuB9s6dVI0r9GzKDYvaX0DxXKppmjgeyySUYcUVoHxg0gIoMsV1inqP
TgEoCyv2Sr4TUsG57mg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dja7spovDKtAWBakQxz/0HG5ecXk+zKMJA+UKr9YFT19EqOhAPEWiV0tXQWh49QbUjFyCZjkAOeM
k34qRJ9x3w/sWyFssAGNHH9WoWerts4MDiFELf8NjsYwP2rALzgiv+0xY2dVCdow0InUA394Sazd
oIw9KqGCd76ynjgRALS4j1rp68O9orO9MPT8ykPXge2efg1i653lnA/5B/m7zpbcHB33yT60fuRY
3JY7odS1n0K1GM79/8QACNu4kcVQcWeexjB/ORpZeVAGmOCmERaUKwsPA1Mr77N6im6ErLeCj/Kj
OeQYszXN9eQhUYtGG2MNZzU/Z3sAYQK2Y+3Dxw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
092wbQAUa+agI2J3y2F6rmVudzHXyIDhH7KN0gCknwG7HRiIQIwXopzJgIiccVKXNeFivr5Bpj9U
HEZ9UA9IfNCPs4KbBUl4qczOUByImW9Fg/k0nvBDORYj0Avxl0N8j9OVZTsBddkdhEOAk/fV3D5i
2DWzzFcBB27esjY+SsQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
m56rCjBT0e8mkwtg+YvzZgfnsjkP7faUa77D0Senvq56+SYRcybQPdbj4QVKjz5fbXy8y0qINc+I
Yd1z4Y3/YGMBlgL8uBe1Nb2Yea49J/Q6TB/EKhBTTahZpbrnOcHnA56SUw6H7mremtAYwq7RaY7c
0FqIfo4BnIagEv+zdsrOomp3r2Hl3kLHBCOebFCY2DtxEUrk+oQ/tXhBhUTOUTP4JwcvKI2gkhkL
8hBEWM6wHOjk9vJmHClvvaPKPhZxguxiUad0uEFsxPlYzJqp6DcckvqSQYglJX2oB4OmOJ5mMfRy
dOniK41V1CMNVIi43Z/wgYyPJQbdahdxsejGeg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13184)
`protect data_block
u/GmWeDZqKz5KQvAKaqE9N9QKxvEfj0yIqhMgVXrpfXnTe/NvoYCsNw/hr9FKKZ3ipdB2jBJLy2o
fKhOrGog+cqwT8quchYiayixd6pmzpmqo3Wl4tPou/gpfwU+auo5qza5U+1k0HzLRH7vI4WIEe6a
kiCygVSQq86ij0YwyYV53aiNqFCodKUxnjAaCjQOwKa30L5oh/OG/q3/md0qLf3BqOLGCIFzSS3D
uK/HKYfUgMjd04YAJtBbU7pnf+hNvYQTDZj1zo+2OcDAqaOxEBEmMW7lmIfFodkXx7cG6020t9su
fJZSazJx7rD37rNxmsLGLIoCM0WB+siZv8E7+KMtRedfvFhML/RxgC+G5Z79paA84UOQVF5q4zqb
9PB5uNQmOD0w3pfodMP17o0WWZ/ulwI3KTMXipYUll+yAVobBuYY5ekoFQgSeJnVKOAPawdmpr+p
K2b+mIZFrR3drXHKR6rJAHU5pNSKjGujx8NYMj2TagfZhKLTtVIBSsZE1FD8QpeNTk2OHznrtOJ1
458O69tUm6+Kz7l4zqOf7B/7jD+7saC15G+bGGowG+l5bOgI8HR+H9eHIrbIHS34dbG4X3O+fXHi
9+NB1Ofgs5/OuJmXHGaxAr6iQ5gA6+Rg4G2L1sYnWy4ZH7jsjS3c8dzTa0ytNG3K2mqr5HaxrANI
RzrVt5Yn+T2kLmXmt/ctwlJZic5j2hI0wayHJTXSpi4e8lnXgDfpDqZSIt2f7gSr1BJYYQMPrgPm
rx2GFaz0YezHEixsv/PeJK1LFwFF7t3TIKIRcMNNXoWbxDQCEh5fc71WAKmDd0lfzQh7NoxOyAbZ
Xpa/gWaCb/VtDXnMnAcFg3odyLi5JZNpvyCV1i6TiSOuACWX9lvR6VLzjiZXXfqXASX8M1lnt2p8
2yGmRjL2aQE+KjOgNRbE/J6P8/yafr7MW2F9XeKVmvZqWNCJDGvrorZRj5/Z+RjHSXP6AQ2srGBr
m6rnZfQkWXoVLM1j0D1cPvTTwOsqR6rcuzrZ/foM0guDaCpIDy8nGA+6XX9cRYYxf3Cd2Ftf6/MF
b+D8Cragh+rvpsvj4EZoA8/zPsngDu2Zz2b2kTNZiurzwsCkoWI4D43l+LoU/9YsthGgYTIvSnw6
DWN8x4sWLaWLkp72nLIvWn5B+3wvWsV9pLURjF+XN8Bfuz4vG+Q07zOhnOmk6OyZJugvb1dSWSeN
SxgbYZS+Q/Awrc82tKbnBoqmSToChfWRvN3zcaHABD5mTxiEYFpg45DrWGJsSIOHn1kAFmkGNPgQ
kRLHpDLjn3A5xPrfOovzxJY6NO0b4/e1TXjvw0jfkwWAHCPw8d/YysSuO9EIDPV1y86w8qODBK7H
UXkHuNPgT9lUxu+vXZ02Proj9RqamfYQXNFkCAotP163TtOvrBH5JX4MkjnVcWllmfcE3UvyzsqP
2MTFKyKkDj8L230KdKZtuv+bdFsBqNYFZ507bzhRmdtTW1IRl+nry4LmLIbT2mWsVOAZYPWx8qDR
hITlz+f8JdqufltR8NBzTtp0y76HNshbUl1vWc3edIRYwkGSBDz2kjJw4lP8u3VcKOv70V6rL8cC
TI6XfiP/pVvFAb5a4U7pRCGZ5A0G3F5ojqudJNOHW+PDwZbL27f5PJ0nCndMryE+53yGRP2gfLl6
OlGWl9fajHfHJbbsGzGkXpq3GaXYsVJcoYZr1ZXZ9D5z1SCamXLHAYs3ky6GZLDP3Z2Tn6S2qQgk
Mtu/B/X4WAfDgU1bm0Wo4VbDjYY0/QxqUgwi30aYLyfkxlZ6xIc4/4UD+efq5EoWvPiIFD8fHO0z
Oiy0XgHgTO9dvaXMh5+jlkjiKL3L/Pbnpfajr1OeaMYSa9jJ4bZaWEs0Ol2rc6Yo469vxGZLhJAG
br1crS9xU8hJxwiesQHOhftctW6Yp9hLWu3NMnz3FVvYX/Z6XNGU0rI2N22jApsnGszNeFHZrvB0
a2PAsfOZd6oDn12dvktpvM1B/cHLz9rkmfZJtE312izxmETkUTjen9lw2IPWBLaznUCt7QFy5Xfd
FH5RN2OZMPBwXhDsoncnXv3SOx2keHSokxsocQmmbEQInvGOLaiaE7yW+NPJTWVK1esDIixlHxr6
MTVPfnGI7vI7S6Q1iYjloEUw8783n1xC46R1RlBCk2X5M5g7M1SlZepTOWQqkbPOCDulm1MuGJcf
dv+M9ef+ReqK20JOYSZfxmgWN/Cc0PjIgj+yjeGx4vnI3edxBixr8qoobEjxfUWvJf3aRfhfKpWQ
sySgPjY3w/+24QnD4qEjxChKreGi3jyyLeuoJXShlAA3Jq4BoWLe2JlRepu4m16Ya26rmQ71Hgv0
O3NTssQzTrRFyxTmu28eF5QxJgudwJcLcErbkDuxdiLgR5p/u7cRumpC1+d+Ry4eNZ1mlJK0PTr4
zuH86v2a/ogCNQm5pA7hcNORHNA6p5kJoKYlYb+V1oHMKbOrPvhIKKLversoEp8Zs0y5Ul/e4k9/
f/APwpDvaKSGNNCDqznJMk88BpMzuME/S+UwE21W1AIwY+2N8u6tyuCsE0kaXIuY9Ho4ZUgVdLi3
Sn8s3KybUX4ciou5N4qXEc4SeYFI11yzyqpXAfkjxPCwUkOdONI9fX6lBucI9mFKSr54vFTCwm+B
KOJgJPGw09v0hwqlXWPegP1LtfrLY8mvyT38ZkH44HQUxJhSO5vaWLdA+6wthgmRvaVA6KNtMObq
cxY4q52whnIeMrxpjf5uZeW87TCgo/11J7yqaUFqg45cFLEDuz3+ZbpeTN0xJmwUF55CHO4Apo/u
7N+a+NCm1YXM+/IicaeoA1q5KVgoALuoeAcCYhmtrm56CeCkSLbzt9X81bkSwJF92nBJD1cacMtA
Pt4Co6Ad04eBLpSMCrSLEB939JqhmWzcNZugEXLKAAWNav5aPN8SbyTQ/mwczftNp1nnqzWDMIhh
fsL0eB4CRUug+lUmBFup+Lbpjk9VnRJGlqaleGb5qqG+u/rhMBZ1qM2NLxI8+VEkZuSZ+B6AkMPv
Ibt+Fg+PXZOT97Rg4+mky9tXxYamSoO/I3rgxA/e5b5sb6mXJzTqF/Nr6N+7AAtXw8es4aIsj0Eg
q0u65u+FAcJhCZkZKghooPFS44iwEQxCnBT/gNSBMRHuKSHQhLIBcdxoqS97Ur9lI+MzsORQLkUU
hjN7nLxjnMzbnt2VsFClmsR1+Hkk5sFQJ9a3uGONalTqzblVWY5Co+Owp7Du4V0JZd4FYoWoTVxY
uf7n7dqogsMLXSNztusG/y+2w7pHL2GDqvJKFTLJYjU5cKD+rn1UJQ4SObxCzE81crma90nBKVi6
aeDduOa/1ggcoYyns9MVXxnGHXCqbbtZKIZ3Qwmu0rCFsTKH2h/kcLaLXE5yJTXIoogV7g5r5Nuu
CKnR6kL2ZrzQOBnGfvFIKxTGJaeYsvrAqRUDWxB/HwaOjdmps27t7zoAw8q3k/l3faoCNA9fbTpU
yDgBfoC1Ovtym6JK0DCkvJotPORZxR91RZceL5ZW1giyjHImwJzkGcXStXp2w8ViXNgGM+x5Ggpo
nS3SvpA2hrv494KlcxjwrPLIDWsc/oog4G+UA/iAx9HpjkfMb3yOlsRrgDdSFEykKJqu/0fpVKRK
G8BXMVWbuinThYwwT3FOvkAuM/AaEjSt3E+P1xISXLussy992ezlemR7z1yQeWEwmpOYuODA+wyV
HQK6ZrX6V4xrlzOTRBujSci8mpIBmUwbsxXVENHHUXtqV2ZJZy63aftKeSbpMDP/+Om5CNkcyG+N
KhF5rAtmgJImJ/6+9FpMTmYkOMlcgxFOTx03Pm7moJSrXgqrgsQy9SBQ6qC56lYKceW+D2BHtoZs
kuDA1+ib5jNz3FmGhrakJQrFbUeu9dP4/PocIrjpdsqpu8LCj9W3bmu0l1XC7yriRhO5awSeFZno
ijDAh+8yXsd0TiyW+wfnCaGVC4PRgtfuAZuTuldamfp+wD3yqL+M0ci/rwmvbsjai10U12ErlyA6
oJ9lAQ9UBsfIhOYHPhq5mQyRfruxn97/s3abIz/259dl+/4r4z++28FtfreXCKDj8DSfrs6wD6Ak
iDXBuHcvDLqYdSzRaIqb052nb1yVScO+2m71LJ2yjm973qysP0Q47hdLG1qBTD5eM2r64MxOLKsq
GXuKROO/m5u/FYY2fxqsMxrA3coX+N603N3MLse1p/CXONaboT+Y2bE1ZHPXOt/vXJd0fyrnuYNL
pRICV2wWAhPtbfa5h5w+hMZW4ImRw2ZLXQnWB2Thh9kJqkFxYNL5nP7NtesIyLmCOvUXmmuDxE04
viUvwsLdpJKHGYbVBxQVjVzxkegkTA+joIjDK/6jBc93byL0CDmcmE2f+FI3A1jfxcy0bpGqy3v+
PBppXYREYz3Tps9TZL7I2JJbp0Hy+//yPD8K5DRfhXpQuoAH/CMyK9nGeQ/6gzNyZRsccAqlMU2l
jmlMt6GyXcbMOiF9BTXpzhuzHo/VTACxfS6u2t0BsPSbtr4a3gpbivJLOroGhS9RtVwpe19KLgYU
Q1o6Rx/2zNWa8woUqNJNsAs8DBLLPHRtTJwTH+lBc/f4Rm0GRNziPwJ93R6bB7Qji1WUvtR6uw7+
+wHjE9i4NnIdMM+CZG37V7hTTbRH4uxmaa9zCKi2xFmzRQG/RxSjCsY9bejcBwln5WZW+8gtrXfc
pita5wSEyElkdRaARY5OLlBrfSaaA7/V6MpoGbSNHZ9FkfM7BR7c7Drye8Ig6N+ZWUtE4L5OD4mI
NK5XvzoKecE8gg/v/PehZLYDDUKXUu0uX0E7Qq886TA0qxOhPJWSK/aWX/RLfDr5XHreko64hLd3
SQiqPLO1AhJ5b/uXQHc8qRIaSAWsjZgdS+juAb9YxGwCETZNe166G8MtaQCGzqWdXcKz8ZPZuy5N
9cEkuo255LuKjdG+9iJA+DYzRq4pwq2HQJ+9vO8qvt7INWr7jgRubagMvOGCH9zWBT7Fqk76HzQC
7QgKdypbNl3xTC2x0pptnWJFiYEGV5JvHyusovIrBknWuD3MNCsmJnepiRlrcdbt2rs6b+4dU2lm
E0mHWfhbY7j2QChhTyg0PZkVjsJXz4clTLTgtnufJ7AmEubabyGEsV63kDO6n/Vh1ZF5LBhAAgPP
tzkOlGau+3lIVhHWcbet2CKA0lknla48W78EjM8kZCNffCvpPk7T20NzaJ8xp5OVHn662j5r9ErS
3mp4mqTHqHY7k/QJwQBQM9+QKWX4uWBS8cxvDc7wdtQdhrD48FfMrHOoM998YhpG0MvH2341dPT6
LHwmF3ez62JtVl1wsqauX1Ob3PqafFKOf/J+Wg6y98o7w2ZsLaeNXOnHtmq+YZBmq3Db1J49OXMF
VF+wIRxpZ9zQncsRsTMsCPJFL9PgR3zYueitWv3jq5eAGqiCA7qPPAB9MxB16NfRy7pf67JrS5K9
TnCSJDYhLe7NKM7RPyq7hm4lxnnefqexp7LbNpVgMKO2XJkxU5hJv8wvPyF5+qefQQYJzYXdRX9t
DDcDowpqtSWbruwGcEqcWZ3uFwJpFYGI0OmsSpl9XOWktA5T5Cf5Gjsdbt7iu5B+vE6AoRRsW0ro
XnLjvnz9rvRVNlUSp0zbSNZaepxYmnyaovc8ZRfrhxLIsN+SA8uvY6hI7Qyze2asO3wxAYbNls2y
+X8TJnLFT31azHexDc8r4n14wZX0jxmZn9RIe6EYKg2TmZODTMspAjrMsXrby4drXLNrSF22sD9W
VzNeeywXkHFa3EPA2llcAeJjwxVw3KgyU6ErcSDTZTw8eroa0ErIXZ0emyey+1OQfnntmcqexf8l
yzMTMPsxI0GeH25FzNEx4RWx/xZCAZJWfjiCnz5us1egrD/JOzoKsWwQU9kq8ii66OPGQyH5o5lr
taH/Q7AUyWICoTMSfy7/7BNSXCzzdnrNJ8UmpQH3RnjNydvinEgdcnR9ctq7rwNg42G+WULJGgNv
9q56Hy+otdJ1sGGIMTE+cDbSBCo9lqTnDPwStk3zhkUaEAbyEuDf3eeP5oG5kqBTl10bsPALfBRA
7czuLGVOEcB0knEgBj/prGYfzyEsxhMmt6FLDACajtw1WReK/OBeE3sIipdIgrSIZFTMczMAD/Qp
MjlezmWc65gmWP4Gi/Ofnp0uYIsR5VrhgO+hMhkEg5420Qm5DHIdfw+cxASythoZLJrMpgwnmpPh
G3k0F29Kg7XeHK+8Ln/hHS0wN+fVYUEtqOzTMwCWZDo5/4Q9IZ+y0chCC2wWKa1cSUo3GUcz0K2t
BDZQe8ZW4WYKKpXoeNT4763wGdGrfikVOVkRKAPlY06Qw0yXVXTB2hbsvzu0SitLLNdcp7gaASAN
KGeaD7Fq1QgsoBwVoLeQdIRZX1nFwEKAv9PYnQ1MBHMwslOuhSgh7C/3X5kVWuBQ8D3i+XRIPA5c
4nsU0TlZFI10Ew04dOzE6bdJwERPFtDOt9t72q3/z86gTM2UvcqXO1TPliqVEP3dNlTptCYIjcSF
cVcWxpCPVBTfYm4LqsZal+BuRCV8LaBPbYSIbEMzcIBGaFY3hB3yDQMbPfiOY0u6zpQOe05QZBkl
IA4psfmjgSchg45Wpb+G/oQpFh0nwdXIykD5oKxbl5TuiADLJ445OLg0k9Cp89vdZefIzBf3Yd09
0CidL743JqsDjSli+7tAwoHZxMnzXzMC7qV/9/lTCYztXwz2sHvJc8pdO7Mms5vcv7rpSg8W73uh
3L73D1UUqjlkRGjX9SgFBz8Q/RGAXgUs5DbonOjM46JZgzrA/V9pxpoQtU7dSJ/gqTTDFxWUzqTz
9O70lUKbWWZ9WW9qkcYV0NrG0rwA4LbedS1TAlHehsj1agzi26ioe6mHcFqXB93EcytRvqmRaJYu
shbEIcnc9Qf36CwiHJK0Dyy9Tl3zy8LPmozOR0zwsZFVUI44SWnj+u0JEi7pi7SQa5q4c8j4IRns
70Npu3zBags2y6SEqaJpXgshOuXujaHU+GYZIydKf7qzLaPcPMLM5vy0ShKQRHcRrzl12IuxgeDS
MC34mVzQHNNCMJCmF+uJyrnnwqjDzbivvlquCIWjC/Qwyc355SZiveU8syqmz7ccZNeJsV8tgAt4
UiAywgoy6JBJnZ8SRF1cDVHExWrqcpE/5m4aU6lTsWWGK7zUEFYzmqmmkiNCjJEgDT1youaeXhX6
+X7j3zf8GbvoPvNLHRAOLhJf0eLp/QPeJhz66/QJ5rVEOg3N6ssbN6gexK62x1euxEOSiq+Ewhzb
myywpgNBDeSspBLQhUahz/EKBG9GHoCWyStkMiEnIN/b4xKfE0Ryszm+tF6Bt09h7DU54yGUXYV8
+AKEU40Db6fnzoaWKpCcmEPI7KkOoDrfq/MzfwHF7jLGVhGC1nGBLyyEAeayztJE/vnRW78kgVFe
pHsPVEThLTqdODZ5vgwlBWEoqRA9emwApJYJ5s4v2Zjf5+ggB9aVZEecoSbXlSrGoLh7ef8zqXo8
z9f26uPFJVRIyZtVr1uWWxQA1i53ah8n6orjyn0fZ3JbABmDKKGzMXBcZQqiQJH0hojxed8RwhXG
FQ9PrBaJp4o1OBOW1Yafw1FE4xwWrH+vPdd+eJEl2xsuRXVm6hDTQ4wth+P8Bi864KQsDrs6YlrR
3tIKgyQtGyifXqGYH+7mKiorrj25qKixWMvEYVK05rUIjnSOjpkyeiLrrtYgy1U4ACog+qgFXVk/
ZSZ/uLSIL4zwS4bKwfR+KSVJ76h4nAfvCcEVuxeADR373X98io5CjMUrSs45pI6kwlQVZaTj7kZe
Bma6xtDQ73cgRMoQ2PgJ9Rw7pqNA9kUa6AmIMkUo01yN94LJw/f2I6fxxl+vjbsX0jv3sdPQwWAD
vmEl4DGRpaPs7izAbkSk/453f54A7vmI1pccff/sx+mGirGpeEQyx9XZf2mOJxI9hrg4zsrDgSZ7
UPxziiAvM+5PxuvH7Pag8OsizGAKnMODzQVyUnbiwGRDJ0KeBYZDO0UWvcu9XVd1o7Pstyer0IFs
3b95z1Qr2gLD90mIPDm0174wmz/fLHD7adFkJrzIbShVMlJjgXpCHd6WKUtO/ySkIMJJ7u2SNNR1
JifadZ0UDCIsIjuhL6GWKwmNqQEiHSe+1nU8NGQibPacskYLgS2vf1fwioMCWU6a8aIeAM84oMrj
kZlpGC0JFXyTbOx405SX3YLGzELXU1VpRgLLPLTWLfnTwziNgSQAa1fSrh6Li786qYM7iv+B7f0J
dQ1HXgeBnlKYjAtQB5MNpnVf0qrig7a1wFKI+aReHPVBHTXnIlzVo3VYzXqtp9FNwKsN/H8k7GWc
x4+UfkL92h/2ip4m6jDJWUlcytO+HECr4xqzI0hTBa1ReAyjP/BTWcPgDLXFPIDl0fWW38b9rXOR
c4KObHJG/Zj85SLfpO9aZDOCVVdCiCcPvNFkW79O/pdFk7ee0s8ijySdFPWdRycJKUZRmx36HFax
NYqOULENvIF8+UW3ESdmUv7CmCieP/VKBgRTX0YOyd+YMClCcLFRhBjqmM5FMeQDPvxql/s8+h40
Dt1uZlD1pQMvNwjSM+P02b3AopoRIX1EQ6tpCEdPqopvxJTSHHqHo26iP6jO064ohbows8y3T3he
FarT+kHbitzikAEhiz1zSSsjSUWsY6vlwa3MPMLwPRN64gDVFJLrbI9fLrNy2o2q0sPg52kURns9
AGYOPZevIqCOV3q1x3UbLsoH0S7RsETPJgjMZDvf0W8gmdiuOdBk04AkiW4YwVjdFMfuklVGBriv
h0zcaLSBew7wUaDaKdMuDOo6vGnBauGQF4Bpa7KWx4EX+JvDjyALFT+W6Lc6WbAbEPxL+lNIUZC3
U0ADQOG4FeJEUzX7v0UfufomH9skn14NpGRlcYJHyIDzEsyB3qaxPJHTmtPWlBEUftW3zDdz8dBn
7TadTdpDVRnhHVbnz1gL0bO7+VaPLF5hiUTs6lm0NgU+cBkPk/l3taAX35DWiRw9mbjcFLYFCZup
0K3J8BwQgNnLtF0tNaMl6BFtsycLe9G8qMRbqBE0wzrM8JYjA+gNJSgz7PFF2K+rnUdPiQyOgD1m
Gp400QXkul+rD9yJ7/6pwJksJEw0xqoKeb/X564yShplrMbFwp6KkPVcYbUwGJMJ6PchSCuFOBO2
cZNWJuE0ZoTBRKgN5pVfsyBYsZOvSnD4LSVyPCDkF0A+ELW/Z/SH6IGCX6EDoV8YYlcbuTM4xk/q
FG6WlzKBNvYjexv7JpArDy6qiNk5Unidkl684OzqvGg3JHVA+GU6kAY+V8W5vtx9TdZFn95+N9GZ
aI4fmbOfialgrGPuTd22Z7m7v5Zjqy3tnUYPvj08KZS+vKV8xE6b+LPH8KRWvF4TrFCQLU759uXP
6rqime0AoHHYmcfoYFXX2JNcLBae2lKTjurzXiTqIeQIG9TLQsw6tfVwnlC3v+FdYXm+LUVdJL8h
5cC/sueK5ECxFjoQE4WK+VXNSlrTjyPeCZ+/kZ8WBsxO9/yPS8anHnS+QoTl8kj/Q9AMBLZ25Qi2
4zE7pBWQHQIxKEj2jh7yfi/i/5oYhQk6xm/DICSIngmJzJTRV1YJJevrcUQDyjY70bvAaVI7vUtP
g8iNBY8+KCzOwDEidNYwA+Fe3E3qSwV56hzOlm/8yQezksArvk2yoO3vBwb0xD2972HW/87vy6YS
He6UicsSvg1s90Mk0NN7vpyOQAIQZ3Z8Yz091w6K4Z0R5d95rtXqLqeLExudWJtDng0j2kje4ok6
0c7dGERw2vJJ3tVKtwycuR80erRgjiiAnwXalhO6tzNMs0TZhJOONO5Tx66d6a+aAgSsGLV1/bzm
Lmwk4fwiFOImKXizY8hHI9n87YYEbj0OCmL8pKYI51nzN8Tw5A38d4D1CDrw70cuICxX5I3LezW0
j1vtyEysHQcR1DE2SrOqKiOO9IWT26ANYak48AuB56XwpiJU0USW84PSG9KVg8/sEMX2YKejT+tp
1Hs9EqIUKxApmkIezBxYFd9ZarfevpOBNbv4TwiwRaGwAyNSjoZMvIGgUgFpyy+yR3cSX0UMcL4g
o6xWKT/vvagMLObWX2iU4gbHtkh0PpXT5rdsNyiTRMXIbfVcLluCwjS2V1ALVOjOudH2QJDe6VL5
NWuC+Mt9Eo6hFIiSkyb7FBbOYzKYVIfAsSCoJqlSrKP7o7rDM+5DO+1f21LEUG2BBMJzajUBNspT
2N5p0vRiD8B2rCc0IpCLEAJhaQekU6MmRp6dTnf8BYowb34Mqw0SY8IuQYn/4o9yaJZHBWH3baQZ
w3SeJaay/MvwKxHkNF8bONDk7fGtmgeF7hyq0Abb8U1MH6RUbCiqtCM1UEu0vNWIb1V9IAGoAYQ3
o5o4kgT+Qw2xooxN2z1m/IFrLo6qm8gKo4D5a77Zx1c5mxo9RldYheXnHdOJ8qZbgY3du/FK4HQX
h6/aD/9hMmOklQW52AbKPmFmRgPF8c+RPZLsHy8fr65d9kJi4j0sj353IHZMod/x1j9jxBUukxbz
V3kmFQjRxlDIlcOqY6wJAfgrUpK54S+0Hubfa6ZXMicjy5WPMVuZAaqyVa8YJaDcjU3d/rn8Y96W
JF/MAKx34bdvGy4In/C1iHQOILhNWNw3r2hC8oUmU/c4qzCUgmfRK/W2THkPB2WpSGbKbmAS1luH
Yz5cZYyTEmqwGx2e36GyCpmF/6igrTEFM9rxnQzknm2X3y0/WLLamIJFy0ceF4nk0y0BHSDMLMrm
1bOm+9itwPzkgkc+fPZFacpHnMdGecko9O/tiK16M1kezTCJbdSpJLC72CPqhhVLMQROpk0EobDY
hSYeSz2k7johAEsAoG8Le4t/aQ6PV4cxUL/MJflDleCuJYx/Wyu9o0UqvJqUG4moOiHsQcYc35qm
0OMWvW0WL4sTNRWfbyFwG5h/84pzANgCwiBEw/lgtzzA8p8P/Wo6gBgC4iPafe2fwa3FKi8W9Bgv
w12oIuBvLDFsapyZ0UU9+hqACCkbooJFKgr1C6q+UhTpSRIPMc6eWZ50rO/8Rd4PQzFqTQtKfC7E
UiAyaOIok3EGaV6sLt/tXoiqjee0cVP29SPhebloiWtHhPrPgsvJhj+G3hBZLqqjD5ctH0O0Wtx7
09rtRZfGu5LZ08XMh8BxENnD64by1xrak42lCXJtPZaQk4WvKGfpSmwUKABh0jvcyDQcRH/hLAmn
R5hCVU2uDmwzuOsnJSK8U89cUUJ2kURpv9u/UCzHtBwcR1wIx3V0sDgxhAJomZX0Y0xkYO6Uzd9k
7gfU4Eci68wXe1QkaxXBFTuD7dXu61FR6Bid+YYHi5qk6BiHpKfosyz3kVzZFMKK5rOdFCikL19N
cFLoVBgwg+YaVUf3CWtDSnDpVdZuWh4WqXlsNiJoGmP4CWbhaXwmvF046FABLLv3jRWhTlsfeDf4
9SJ4FeFCSYwQk3KaaDBLAWVGFw/Q0g0LweEw2qn1KXKSiHWYrWNOzOcVl2fNHIU9uDquh34uDJnS
8GYslg1tr98NcpalIPfgpg6zw/69IKOXBrx8HVqkN6lNa0RvYdTquEY3oLEGxs4xZPU6oWM/Egqd
VDvZ0Wg9vPCdeXyHeg+WFEw+hZd04w0+wLWKdDOF09IhfMkAYG28/IoaRFFLJ3YPpNwjFMAH0st5
8f4jCfb3cLBqyCoyELAbo/eD5GJ8cZJZwEU7jz6A0BFwugn0k2701xQYz+Rma2HMKE0moUAu4O7m
poXyFjqI6x8YtWu22NRt13uI6H5r4SlexMIaveuv04p7/uofdVDcmdXDbdFDISldaK+jxgxvlmpL
BZVQJhoMLS5o7DY8M1lPjzVXwGicN9nHJkz/DOrlxzz60s2oNT1CfSWeaFHhct4F1Wtx8E7hdazB
Hmg6LaDhTahGIkypeYZHvkQbB8QuwQvj4KHIJxxqxhlui6LJcKYRT0uOlYNrQn7Nc/0vjLicplp0
Buej9Nw5ubfxeO6XZ3eS7BjtdqbpsuGmYeV3cD2DiAvSsMCQhYctAaCF28rYWUpi1wUpICYN6m/Z
8iRWwIROMVk5m8/8Yv7wHsCPnEmEb4IwFdIFa/QFZDpsIS+WSk8eq6aNTsq+cnM30nOiX3ITBgj2
VAZ+GlwNHzUieDbb6GkIlUPnwPjevbbm2cgR+msW4mNXVrSdoMQT5jx/adjc5798Gelxk81laNO1
QF+CVebCEcbe9giWseWidBkrCLK3qqdhrAVJ8lYW6fc/lY+O3IjNRVxbFaBXComBK59rDC6S/3WT
direBeqqGJc3ZtvlMvBqzJj5uAOGksnxuJnBGrOpE+IbiUwo0p3fq6hPUgQ17VBAYC1mLwpP+Hce
kdaifkuHtJ8St8dgjtAiMvAmZv6RRByKf5mv+Hp0/tz8G5hZ8hCOsyCiDoTZWPcmvTBxz49q+zEb
tYpY1LdJSA1w2nkVbUm8/ecf4GQYUYqzpdEp2VtFxwMyaqHZcXiQxxI8JKdOCU3YeuBeQyzwkYXf
FQR4l19XOIXQLEv1xpgJPwvba+o6YYJd/Cka38/BL2dQWOIV4vRWZWT8hiiCGw8gStoJz0sICz8t
kO5ZUlIrpCecdW5ocufG6ak7ne+BG9jYQ0nfbRpO4eaT9UKCMqQzML2rtrKmWm+/6dh4B5jBB6zV
4mblsKtkq4XP9imaaFxTLdkqXl8v+4Z9O1FpuHrHfbXFn/nrFKnQuqunQLmEgCYB4xdX2VEJPrdw
yGQ0Jn1qEZNqhxh7dsJFdm5rWAPB0fX545CCxwDW59lmwoOWYv07CIRmtAqFiO26r+4dMXVoz02L
dSrdti06Rn1kvbQaoZNaqWMpzewm6BLHB9L8Wr4pBtO1GG+3xMGT3u0MjfFTfhYWzMkUOEAtgk7s
35CNBquFX3vScharPSUYpzyO8rsv1muQGdjJoPRhup7cG2zJV1BMyf1cmCBNTKE70Y6HTaNPsrLb
S9J38gU1d9nqq2tmii3prcBOn6Rvf++9fZVKV9UwUxKSKiU7U1UCLnuNm+gwBzICzjltmlu/kqTg
8T8sTtMZZdAXrSgsd9O2YZGDDtLdacuFs7pzlJ+kUT6QPn6IcC3+xUQagB0XiltdZyXA7wnvfO4u
ICRybXJvJKaGSruTxhsSe3DSBQh6WmK3EwmO8RcLRMmQOJLbLR8+LUVgyjg+OlhNXzwwnqwcRCov
4phqnWok0vtXeh8PT4NGUbpceEbWuuJdsZPUUV5RjawNP53lVHOSwG14195ckFWMEC/zsG2fMAEc
hLCwPqSPzht18zWLKCaasfoDkmBF67nPQ6HNUmg8I8aXYmcKSNVuwYzBrLA3NTMbo1mz7xOSu7QD
wQ1XCD+m12aigD3Zg4zrgxf31mzWgwfuR/LKsYlT/2ukiQm1I2+XV6fC3ypZR2MNBHpPBeLUVSuB
OzpkDC2Vv1E+UdQ79ggtAvemyochjwgW+6VdXTelAmrx2vAUaIfNXzaJTJt4JVSMgZ8+I/0Ho2Hz
3TKUH/DU6Hmtbw5GD+COYazRDVu+YcAEHzlmkQJcWh2PDMkMdSTsb7ui96aV1lo54SLWy6hs3E1p
a3LJDwSfoSSK0YU8lUk/PBMkDVKoT9QUvbEB1Fav19gMxgCQLOB0p3ArExGBKQb3xQxcRF2k3zKr
gECa7Ja6OmTcFwLugVb4KvUv2z4IMeNc/ZtFAjajtVZWLXOI4ELG4SQyfGqWPsWcu6PM8U+Q84NL
+nowp+ALrtk7+DXD4A97S3+C2v9xVoJdUNWR84qs6hYYsIygJBShSHTZDypdCrNAY9RfHgC8gDQg
dw7WvApC2+ykqlEYI8xvrkHkQ5aRg6zSq/4GmgWZIRWhTkNgJ/CtRDumvfL8tAG66Z7zSGJNqf0S
sgT8bzuKHIzjeOnQJ0nDl/lefs0XUcYxr9ZycVFjgLOEngsMtViHMrzZgxXR9AiTqM9yxZ0q9Lc2
IFwvrowCHWPPptqAltmfwi++6j1IiYqUnpGzX/QKnh5L9JGCDZaUHbFwovX8OglYI8iRm2oJIV8+
w53Oj4+xiSyVNVK6+1uK7LFB6s/59AktF1QxxMxddZurI+a+bEpNX9W7sfndst2iyMJzwcbUWT/u
Hi6C6oPiRNXm3hYqGWGnWyfARdxeRnE5J9m9m2fwg7QxPvrTnAk0CDGTCmIZTs2GekrQ2WuOlf1/
L1OmvW0TD9Si5Qn/TX6oB905YaCkVJzcTS54pnf3AeqBuVEVBe8FvlJJwEv8hKLX8HJ2xRbEXjRo
4Ng7Upr2bJPG/SXtpwCbHO7iPqr5OwyHZtUgt+Fw/0DUIPjC2DKNkmiUOOzwsF0YHNpOqFwScuKr
N2LU6eXWPejgNO4yIF2w8fF2CugjKoDeIGySQXcwK9FsM5hxZ8yVyMNIk98Jhrhlprg39pxh8Lxf
QUE4AJ9/3ZUwxBHlMVMHfw+pw2ya0ntIauzyrhEnffD4uEV3vhuONnZEG8XXfe08SVw4aQs4b13h
NFHbUJItj3CTFyfMVG/9mym8w590l76Feyz6x8qEWBolZsCqmKaT9T0rvnjdijCUvbqkgsI8tP68
JPwv54+Zjp1OIVKHT5dW0KS29fjoiUMP3n75sWUtWzBcmbEY1ATU2XOB3wvv935saUZeWbUDUI93
7AMd6bHBS74qVP9rSLzGSWOESw6HJb+FEbcx8/0juAgBIPFffozdfkDrydYq6EK9S0+lgrCzu0Vi
KuxQ226jIl9bC22pRddn6Y+v8EH2sbjB4ioYkWtwtSaZBSQ5w8wbc7SOZ4fcftSaFVyf9H2/HVq8
YmiRcHo1sBW7KTr9fFMlqOmdpPfBjvB5cBvaNKxcUSR7iXzYmYSyulvSYylthBNITTdmD/O+wREK
N2rZt0Mu9cuo0ZE8EQFxdeqm3ghDLj7so7x4xdHSJ0nUn3CuO7h9ebHUeOymm+UHUCIS1Y//+2p6
ylFrt4HP9wCnHHvRUKFiwfTDd3yLsXH9UVoyxBPR/aKFw8RLpFZeLXvzTLlu7NtJJK88AldP8mF6
PUIW85stpJ94cBljEstOglYMwSLHGYveX/GyaHM/7UO/Pcy3sVb08ELqUnyzJVaA3LmmRQCpsYXP
HzdVlP5xMHco0gHDdAQbkfch6/MoRk5n3a4m19JfE8uyAcNeD97QLMu4HpFcDaqhvAC/w5A6xl2D
Hn2uwNzTz0E/MVBjo+4I5v2QJFzVFSkefKtJiz1NUHEKwEDu6fxUfCpybQUMQivpg9hPPIw/XX/B
zxA9Z5hdtdehspw2ovO+6kXJwdJd/6urOKeGpiINz0/QFiTGv5XHoP7QlD4ankSxzChjMeUgNY6p
u2UiLgg3f3DYWUX14Sj4ejfOhWsCxbNSVPGZcNI+NIMo4YyRZaUs4hakUm7IkSzhal38/zXpxGrb
/jZ8DrSKL0EONe//sZhOut424R5TKSAXLrulMCApE7x3gN8wRT8NhLHGF3i7tUQkalHtPglzFd8y
HGys55Bt5bpBBJfP/RAUnvL2ZYKwEzWcpPOdgnDL0ZXDMFaZd5z9LfmiLkPETN1Ql/xfJlpB7wm9
9Z1EqsIBvwhB25jG9T7DFXLhlrJTrD134ExoArwGua5AQiJFyhySH1O1u6ZbpJfgw9p1iv5Qjk6Z
RYoqnne9kFhHyP7/Aorx0lHkwvHBFpYY0/cpny3fkZr9U5OCV5k38kx46NNTfgijyfjesJPESVJv
dH2dBCNBUoGQSg0ngy0rg2B7+esGfspDQ0LHsSQ+v0i+MNXNrgmYxI1QhYYAOS7aL8+/9LlbgQ29
hsZfhJR2umHysypKqfZyhC8vG39jOwr7Q8vHrgPkieiY5Nja+13vXnmppSM03L1L3rlC1uWSnGN1
vqpiFap5vyFZWnhrLOeBCilR2bjVGXDHaY9pmvTV00hoT2AKg+2jtV/9e15VlZrl+/dmy5EBDtWm
1npbajuwivjsScKngya0FxeLL1XOUtctE9o8LrRhezuplysQJehlVLTTZBZxaY580e1n7Jmduhw9
snIP8ZWgyRUCBsk/76xnDZf0clV10dsQb2r92FK/ldmLx2nhexD0iteekRsVXDDm5hHwzrp4Ksij
8tFwwB36t6luKRwlKmnknSOazLy/c+pN5I6DZFZrv/dmDd1OaWBgB8ZNOdCP2VznxqEoXCCvLGzL
FqLcaj7MF9viWIZ9EHDKexGG901D2X0LHYPKA3gwpOKk7oymNdCuUNfrQXUE8Z10Hnvq4urOwyJX
3uX3qdGPSieEtZ0Pbi3WCYh4jbP/4/I9KVRO2ndQlF49c7PEa1XPDbUlPWbIQaDFAsgZB8xY45L7
+agevoIBb6pGanLs7+Sn6uVbCpgv32DsC/wFw7KL76Yyt+nf0IWiCz89GsYlztQlK3tWRGDp5bGX
0Rv+9kfueBk/dGPqSLjnnIGYgmHUscUAusY/OGBkf1vLcFqNjH8bjw+pICbt2At5RiTkXIScU95j
cLoSIpdULJ5mNZB+YXEm3AaXsVutJgkmfyBR204ID1xpkiofyP0aux/UMsy2xc0SPHo2EjKVZxof
sacGGf8OYmnOdLxPTyijBkHwdDeMRTxzo9gpVEjU8t1lUyscd2OBMdMuIvZnFtvooTzeuyDW9/ya
7JsOxnr9Fw1FfjY1JoNXyl+XFCY3OOAd+n1I/Q5nWIm1oPj2m6B/c9cQhEt4lL096dPwZ5aN9cBw
urVfSvUl2ZFiTwi1K69ky0QS82Tjw3kqmMKcDZJ2wLbGVPD8BQkUMqjMV5X6Kx+9n8uh/Yw/BwDj
IZV/y9zSWKXlzu+s535bxmjRLpgEG1YWRPb+gpn14/vmQ4Q/t/bM8a600UkZ8kNwtSxIWNwEzRnR
lKyoTSi4iO8qkg1k5hLvkJSkR+h992dwUfzblZkcWh/pV2Wvpo9KVEG1gduuzVrGzDIHJmbXUX8R
E0qGCYh2BrHgruvxCgbREFuHr9R76ZJAivvUAZBrdigWJxEjewWo4vv0U1FAr8mANRc0t/9s+k1k
CArhDoqyifDhtQx43qoCT0lnDxYjti3fg0THMPw/urnuyIhsNuELpu8yejALvAbi+s2J2AW7y+xg
BDk4qiheuKdcuk9F2XMbaOaLmv7RNvH5lnSzg4A6xckF/bV/F/OSjvh589/t6gyxYbMno9ovwcT0
cj4CttFGkk3hHTKLsKFG8/mG/I8UatvKWAraOx0FWvjsNXNFoCvwVK7kD+usJu6wXevfdEQOBWlk
gbE/pw86mvoMkkLP8sJU2NB5yl2xYQI5V9KVWVm77r9rUfpWrFRlnXm99lbZNmR3J8lG81sf5Rtj
ruik0oUQUQXhyS8jP2PUCH7scv0UYOunZAArgRpu5snHZ9Mns3umECqKDuBQdTX/NHW2kpY7i/2d
Y2I41ZhP/9as5ojauoFxhR82J5beKS4JxmYaU5uDKQFRWi8ltdQLtg9Ion3Gi4S7sXOkOmMGod2y
yfdpM3OqS9ikaAKDMbNXxP2a/VxAo+/UKOr6503oSExYoHFOa5j8nMNJV2aBiuXVbO42YmLelTNv
AnYQzN7vAoGMGo6rznuw+Xw=
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/srl16_fifo.vhd | 15 | 13201 | -------------------------------------------------------------------------------
-- $Id: srl16_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl16_fifo.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
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-- ** done at the users sole risk and will be unsupported. **
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-- ** code and therefore cannot answer specific questions related **
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-- ** code IP shall only address issues and questions related **
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-- ** indirectly, the original core source). **
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-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl16_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl16_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 First Version adapted from Goran B. srl_fifo.vhd
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_adder;
use proc_common_v4_0.pf_counter_top;
use proc_common_v4_0.pf_occ_counter_top;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity srl16_fifo is
generic (
C_FIFO_WIDTH : integer range 1 to 128 := 8;
-- Width of FIFO Data Bus
C_FIFO_DEPTH_LOG2X : integer range 2 to 4 := 4;
-- Depth of FIFO in address bit width
-- ie 4 = 16 locations deep
-- 3 = 8 locations deep
-- 2 = 4 ocations deep
C_INCLUDE_VACANCY : Boolean := true
-- Command to include vacancy calculation
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
Wr_Req : in std_logic;
Wr_Data : in std_logic_vector(0 to C_FIFO_WIDTH-1);
Rd_Req : in std_logic;
Rd_Data : out std_logic_vector(0 to C_FIFO_WIDTH-1);
Full : out std_logic;
Almostfull : Out std_logic;
Empty : Out std_logic;
Almostempty : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X)
);
end entity srl16_fifo;
-------------------------------------------------------------------------------
architecture implementation of srl16_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Signal sig_occupancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_occ_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_addr_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
Signal sig_logic_low : std_logic;
signal sig_almost_full : std_logic;
signal sig_full : std_logic;
signal sig_almost_empty : std_logic;
signal sig_empty : std_logic;
signal sig_valid_write : std_logic;
signal sig_inc_addr : std_logic;
signal sig_dec_addr : std_logic;
signal sig_valid_read : std_logic;
signal sig_addr : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_srl_addr : std_logic_vector(0 to 3);
signal sig_addr_is_nonzero : std_logic;
signal sig_addr_is_zero : std_logic;
begin -- architecture implementation
-- Misc I/O
Full <= sig_full;
Almostfull <= sig_almost_full;
Empty <= sig_empty;
Almostempty <= sig_almost_empty;
Occupancy <= sig_occupancy;
----------------------------------------------------------------------------
-- Occupancy Counter Function
----------------------------------------------------------------------------
sig_occ_load_value <= (others => '0');
sig_logic_low <= '0';
I_OCCUPANCY_CNTR : entity proc_common_v4_0.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X+1
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_occ_load_value,
Count_Down => sig_valid_read,
Count_Up => sig_valid_write,
By_2 => sig_logic_low,
Count_Out => sig_occupancy,
almost_full => sig_almost_full,
full => sig_full,
almost_empty => sig_almost_empty,
empty => sig_empty
);
----------------------------------------------------------------------------
-- Address Counter Function
----------------------------------------------------------------------------
sig_addr_load_value <= (others => '0');
sig_addr_is_nonzero <= (sig_srl_addr(0)
or sig_srl_addr(1)
or sig_srl_addr(2)
or sig_srl_addr(3));
sig_addr_is_zero <= not(sig_addr_is_nonzero);
sig_valid_write <= Wr_Req and not(sig_full);
sig_valid_read <= Rd_Req and not(sig_empty);
sig_inc_addr <= (sig_valid_write and not(sig_empty))
and not(sig_valid_read and sig_addr_is_zero);
sig_dec_addr <= sig_valid_read and sig_addr_is_nonzero;
I_ADDR_CNTR : entity proc_common_v4_0.pf_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_addr_load_value,
Count_Down => sig_dec_addr,
Count_Up => sig_inc_addr,
Count_Out => sig_addr
);
ASSIGN_ADDRESS : process(sig_addr)
Begin
sig_srl_addr <= (others => '0'); -- assign default values
for i in 0 to C_FIFO_DEPTH_LOG2X-1 loop
sig_srl_addr((4-C_FIFO_DEPTH_LOG2X)+i) <= sig_addr(i);
end loop;
end process ASSIGN_ADDRESS;
----------------------------------------------------------------------------
-- SRL memory function
----------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_FIFO_WIDTH-1 generate
I_SRL16E : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => sig_valid_write,
D => Wr_Data(i),
Clk => Bus_clk,
A0 => sig_srl_addr(3),
A1 => sig_srl_addr(2),
A2 => sig_srl_addr(1),
A3 => sig_srl_addr(0),
Q => Rd_Data(i)
);
end generate FIFO_RAM;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Constant OCC_CNTR_WIDTH : integer := C_FIFO_DEPTH_LOG2X+1;
Constant MAX_OCCUPANCY : integer := 2**C_FIFO_DEPTH_LOG2X;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity proc_common_v4_0.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => sig_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end architecture implementation;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/fifo_generator_v11_0/ramfifo/clk_x_pntrs.vhd | 2 | 35009 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IrjIZbr1S1N1qgvIxYDsixzCc5qnOgw1tPsIUfo+bkK4+Pn5pxQgdxIiL+nlNtX2zhL4HQdT2q8k
ichHS5hu8w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
n4REzcEcI7waL6YMU+Jqw1OIgXG2xAs1+wW70R+YUUwDWIL5gZNH2KP2nTjGhx8POsaPtgLJ7/eW
T9bNIE9XMSUtEKR+R090I16+RXOXOv8ya+kMk3fcXdYgg4QEgPLta58UsRux4DEGWCSKaO6oCPID
JdLnQj0BoMuw8xkQ+7A=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rjHLJ4MY+XP3nzOvpDJJx6AsycP1k1fV1c2wJLRdiN3S08N5MPAxBWoZ7/zsCr0QF2lI+DxV4o/T
cp3XfjtATNMv1ysV5GZJzQLmpa7f7aJvZ3DcaULlEDmHbNWh83GDTaVfNTCA9p9H7fRY3js9Qhwf
puEkeziQo3U8LdxZ+lPsOwgOtLF7Gnqrx7YUjj5kSqrTrON5Bmooj1b2vm0Vo+uKfoVUMjPRPfOr
CiphqTlwyqXDHka5rTiK31G3fLErV3/4F91+oNwpO8e2JjdSx50gcIHVsu4ZRDyhQalRxeSHlcx1
4uE8HNeKDV1jkRcEl54hRC4ZEOJm1QHrzMP58g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
R2UlSYmtowWZ1Tyalxq9V9OKROKkgdgGjq/mnRJwRQqtayPcuUMahK57b6Rel3wdc19OMrrVuorm
CMNV86TbU37KCojVeb4lOzIgEd6p2UVxbYplTHid1Ix3YKM6Px4RabN3HUKcqBIKXrcaWZDF3Y9k
9mBGyQ/vw6GRU4St/1A=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WvWSJ75Tab3Z7jMZq+QXzz4SvVE3m/fcB3YJ19lFi0kavKlgraH0t2JPO5XL8qd1vsoZTYkLm6iq
RkczMMArZdrPIwWmpWm7dmiDeLtZ1YvGod8mzaPHqWDY7XT1vsgN+YP1mrzVgJIVXlP3XE4GxZCa
JyPP1mFgKWp6XgiGZvV4D/ujqC/FJoyM9pEZJN+KfiZc1t/vkGRx0qE2pb/VYHbb3aF+ez5Bmmsc
mLDLi2v6QJw/1RZtXPJ7X2/NGYzO0lVZpU3uJLrkrgPTboBIq6jFEcIGUVqrWiRUUMYM5MOmj22g
C+P/dJGREeOGINbmEW1nZL8QJB1NgNw1eiA9Dw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24176)
`protect data_block
JZgdZ+lC0NMiiFf1CfcXp1HJD2QRxby4ws+ybLA8ATap1S52imq6JyH12Bb9wcLpO1WYVYEUABEr
qZr1oXLCEjsCMZxgWhlUyWXt6+N06M8VwsntFgO11m+cmUevaiAEt06uXb7aLFrBwpq9bVsizQ+4
IxynUDKwFpkuSRFHKOLCLwBCLfn1n2uPcdhnCr5pwjDmBhKON26mgpSbrK+UD/qTNX9zaZe5no/s
rbxIa/5GlUv/Z9C5RUaGqVNlsQPhtgXAJjr8mjds9sHU6Q9RcV1UMdxS2W+3sXCVjWmQ2YCxFEiv
nA0dv7olOyEDKhwBTp2+ALt8aPaei2CpFO48DyWJbUXnFw9L04qHt79l0jMv9aW7bO7ys5DSZ7ck
56qtOCECu+NdzcZAkEL3Fw3BnshJzp2JO5BTDIhsJP5n4+s4VyAUKwV5TsqvW9u8pkc3LdOBSOeI
eB/uYHeixyyWotooOL1oNnv9+0B15ICSf31xs4eF+hnVHF7OvlVqEZtixlh5CdzCjhKkjCSiSxyW
YZ4QC4wpC4+Sa1WZ0aI2kd7nqjsFN0WoVnTnKQrkUIdQ4nl1wDSkJkW4dYMjXScCceOdnCPB2gHv
LKc1hqe51Qd/hAnzZHyUPHiMSvXsUMQR2ONzvRBnyf9wq4jLbT44/JlYqkgxAGpcLpkhUrontltC
Ytb4g+dtndr07sYQTWXklD+X9ZoRf5cNb7/z1WpyAHA2KPT2tVUUAlnKzuKrF7Qk74SJSHTowS1Q
JNHO1HVyugp3G2g0p9HcKlCftXny4E0vw3c4QV78YWliF/wRsfGrxy8jkx2kNkl6vnY4r/OL8ysu
4E+uOULFIpXp+NhaKDPizD4WskASKZY+0mqzFCVV7UQtTp6APuRq5P0LLmGQh/LrbXDRWZthrN7b
rxUOxz1QHj7vJ1Fs4KE7BYL4nvwA8gf5gZMb55VMkMMe48k86QlwNix5LVIH84KNHjR0qpDCiYUD
vAnzR4oi662CwL+RYOvVQCPS4tSn7OtotNvKn9ROvhTRRJRtT1tVeSukzOyMyhz+t4lWdk1ey+3U
M8+9ObJzdShX5TSltyQdrWvuf8T2OLfdHC+k/F4qsDkan3CRP7NyDumr7Inil+aLz2xDpuwFDEAv
73OB0eRJhVDeZMO0qMjH49VF0KNyApUsvtzRfoFETU1AwTSTq6cSYi4Ye2kxQxw3uJZ3kBSO/1/H
3wWKHzHGWC1+mxBeunjoof5B8JASZusI7J48S67em7pXC4OxVsk+z3NgBiVFveAmef6+5sRJUeae
vAqvnUZI1f4dFrUR7mEAKpoQQYFzXaPiSuBbDbjj7fALkoxhKib+yrdriPsXNtGZ1hFSetkcUzJS
AubquVE472kjBKVRpjEbUoeuzpcGF+9cU41xP49iLVpzgOkk+AgdeaRBuEW1HhbYHl/v2GPvwG4H
/jc/NrICSB28hOjJtuY/AnLEjvwIJWu/jj+TlKbggC4ZNuiPkwv58XUleGQpgYO46WMzO4tGSjd4
p7kb17m3qDm62MMVi8kUgDRpoCNcE7GUE4rEofWVhy2+XrzFCHJmS9hZtmqrqEyNHwU/FJ7uR2bG
Dr1YajkrfP+flZGYy43/hA/1unJyjY81cq+My+YGIQEUCZgkJGSCUCGhEUNt4oi2dPLBbiAG7lXp
XUvGaLGDrTsfP4+pUfEiQz/10OKZ+KIIM+UihMJevisbFsP+7gr9j+cqogWbd9K64EUkeq9gzV14
mIKTBwTvLqWpUR8GFWgmdyH5BBq3MJhenty1ItVaeKljBUf5kjgg6qKbuYZrKYpE8BYygXH14zOe
Es3N9VZAasxsP1IB8qa3Jqao5W+lEPwsjFJifXM4Y3jtJM/K6YhZPfwFkir4V9QzFUu+OTDlJcIg
dVAHPwTxoSWMkd0cCK659KNOhxorSpNLpwIYQvUIpwpycpPwlV+BuSQs11j1wUptKfWSWeHDE2o1
W73XB+jIhpYyRuuU06fdnFgcbqWrrTTMV2jP21G45pisdsN6yPRh8abFHc8aSaJycdswSdj7r5wG
xgnXuietKxdueYCGtAMxYEPrBRgAuJUNboEg8kd5eHFJrWJ7Z2FjvyXLLLBYYkak0sCm/+lIs9Zo
ME8w6nCWA66a0vOLOeqpgAJ7rRssuyW5qoFNOxJ+x+X6vwDYjMs/P/wRTQU2fmaPrDJuII/KTVJf
83scJi//ykPrzxG7vHrwIyVVqThsrTF4Rkh161GD923ROITte4fk0aE95IyIapKD24wBCSY4LEge
HREnXBS2d2tkhKoJZ7YGUyU9d9s09yVC4eSRpOVvirkxugt1ldvGjwB/C1QOUpQWXRTjFrurPpPr
pnF19liKOK/EVwcJ0YosOwu7FAsm8XpEyAtItlUtmsfuUUOlslsho3d8G6Gymosr20uusteNLpRB
ed97JhkOCszcbCT/eEDQz5quZ/YrbPgUtq3EsOd1a/9o6HLB4E7zaaW8gbQ+1SzhpQxzlxmAUvV9
I3T2WO2W8i2wQgLK4Ox9Jg2x1QEqKgISVnp5VMj2oLMVuYwo9KTWaE1bnPC0YTGmvfQzigKXaOSi
T22BCRri1+iG9VbQHWJ8x5/iA4g1z8Sb0RPOCs34ES31P1B9ujh/ZVJEDk9QEz4XdySRj9ICIcsY
vdcXWfrIBoHrrInzwVsEgzHR2L9rBHZVdkbgoVZuvzD14lJkKB/WyHGtzNILiG+5aOWGCcACJusw
1rAlKN6UxKMdP4sgGHGPf9oxeE6NFbqvDuIMcYZjpBYdx3bVBRMfrZPfJ2TqT2b9g+k58jVxJygH
0PI6cCttQC0u04zzf1a1Q0i7CpsQoRTHmsDdQ7X1yekfriDxVvZdoj50Drl3k4dUgFoAw6vEt513
560NLIP9xNqeFaW0w5DVTIVpz3JUheJBXAtSCWILMR2KbVpy0lPX2LHqRmjUzAOCYGSqIZjaaDql
XJ02/28kS1YQ1TZb/nTkwBo7M3SUQprw2+pzIYmkMM6yu/T9rk7h0+B3mRV1CgUtOC+uuq0pxrTX
b4tIkLJ4xp4v2UPVv9N9ELozD8qTlKedWzMGhjuvA9hgieG92fD5ritrAPJ4MMgpSp2f8xqyK62K
o92kK/UrFOchUt+Otz5NBBb6FiQa9sWqYkPsEYWL05jZxVT2PIQT2xaFwsPCz/rhp+uZ3VJexTma
/FqnLxieysRxqjPUlp4x6g100ZdHtECh+qeAtNtTnE6a7uJiw+9/bvnKi7W5VuQKx2dTXGHufqzy
A5SCamNl13535RbBGqRexd9evu0UIKcsd44jOpIa/AYgjvBcYlkv5SoCxQhBE9/2iKTwronij/69
8R8GZpSqON5PG4TBMSAC0vIux9pAMh4yokqB+9aXjPT5SsetQzgfcFGwhE2427SV+69EOJ9DLjKT
ajkocivx2KcH4uDf2Zwjq0AzplkLhr0vsdXf3yn10r/HizNq+NkG1fGIxeFx44q5zoPUI+Oexo2A
EFSezA8AYYKi9cKWMVGzlf+yfjp605A5B/dq/88o0cEkwhBmidYKxUJ/kdJ7c3wvKAWkiOkQfnkt
8gvk69kTK4hXSsTCRFlnc1NyjFQLm4mvw7hd8wkWvK2DCkiD1scq4KCW3jaDjcwGHeqrVTSpJemB
CU7Qw0eoLW2wNpZ+SPeZqV1yMmyAI6Q7c2RIQya/5QYfYuYlBEuZEvGexX4kH2MS9H4GZPChrRGP
yvfPMqzk2pEdbAtTGoCO9zHNJcYPtFTMSHSU37+4TZ55VWxuFGhxWgzrtCg9MHc+gthNVhVcl0yh
gY3wpI7HX4K+GO4QH89vQPpld0/6v9kpQxfk4a6F+squ1HqR39Zy8qktErU6WKpWktCXy5WvgJ5c
STVrtPpRwPXZQu0ttP8Z/UE8p7we+A4F27a1/MuwaulU3vynyp9XVuq4ztFk98JXeZwQian23L+g
gM0AuItXAGF3OqnknkddGPL8Z9HcYfLj5sQBBBFVltZHpxHQjBCsTOny6tEUznpsK0s54O4CDmrq
QagwQkVFL0riDoJbl8iqgxVwHlbFoF4lqhX9mCS5O+eQ43EyBsqs4MAAOLY00xtBal5WgXCTJDQm
M3OWZF8Lj25ZTao2eew0JuN8vyt+K3xseGx3aE4E1Ei0J3tHWJi7SkTIKfkSwc5xRX//cBAm+jMH
G3cxvpqyi5lj3c7fVCALlNptB/RGBpasReU7m/dYRjqR40tA0g5cef6PVL8sGqqohwor/6dyM8wz
MbESUWnnwGjopX2pT/P0ev8HAp91g2Zsu12XcSWhD85A9q9vyCo4T66efkhe+bsIYt50RAkqPJ6R
t4mbWb9JK/0HxMv7sQ4HpshdVgVOYhqP4IPj1KSZbbGS66W0zVBk9HsRfXMOJJfECsHW0XdxevV/
FJsaOG2HhqkHbXCuvaiz+SvbriXIGUqGJK1MUsyTlkWpNAHv0C264AphzJA9sbch0ZPUFBAmt4Ut
67PKJNIhYE9VI0rd7N8GFSMPCG/xglENWIwbB/xezGbS8Es96ivV0g7bRHMAa1ASarPLyOzjWsAU
ZQMICXS+4TBj3CdgX62epRwIdLrADaJ2p/X1JdEN5qkhHFMZVJURIxLahmRANfEjNTYGBaiKXJcE
42Bjuo24CztV3XfzQgIhSLkjjnAWYCWwP7BunPc37qvlbFzv3rXbPyV5PdAqNxLTQghpQKlLKi++
RFvBTPzn46sNxzrqryF9ucklvDFeHWgRJASqUYex8Qd2U/zENnFo4BteR7jC9OkkdR/vh7SLnwEL
4bAkVKQPoYwYWKjG4JLdvN6T2Q8oYhcWORdhDGj0/cRGCBPxj/wY2DcTX2J+Ek1rqcAtJwqmy7Sj
x7GJL15GzNF42UsdtTBqfuMJxV3rxo5fvA549h9FU66L/n37PWjgsWvvhrgIcZ92M8nvPNBc2o4T
6i4CFJb1edbSz913c99ApYL7ML0y48a/QMNTG0X5sA+kbIajF5NE0OoQEzZ7yBD1MtlHfUS9yCSz
1TbvlqGzdttF2IgyV74B9DF6Q8dD+PRy8+Mun+V2X8keLQzWSWagkh/kf9MkxNfo+TbVX0JqsLYu
vRpMk8SPWN36KPUK+WGZhlvh2FkkgdPI8T6VVNzIPxvYpoTu8k7AAJHWjUEEhQu2yJNzvhSZQhMf
0H55g9itwRbpqYcD/Obaz796KP0bfo0Yyib6vVARgADALUXXmnLORVLlxj7GsjUW9HwNs7P6iec2
dj1pCu+rCHyS+FVf/b0mS15tVHwhuXwAPp88EHrLQB9N5qX/eC4lgwJd5kjDmCAgs9PJCqjVHdKQ
99aDWE/mIBe4PCn42IG4mbZ4ENZ06oo0J4RGuInoRKbJ8EmUxbS4yiw8N764OTWSwJDeSQ+OQjgF
OTuo0/1hoBUiJPnBDIy/B/Jh89L2DtB200spbQ8KWzxBvJjywXub7jtDJjzCx83nvXR5x7pEp2ND
GiRdWiDjmj4F8hNJhxrYmW3NtRKrsAF8DK6DCuiFVGSnhvbAssBp/iav7IdP8DLFLBCXTcmBgjoc
bjZ2ZONA6qqoZWHAoswNvFminmttKQu/MedRwtDV/+8kvSJ/f+39rdvk1UiG2rNaK05+xQdvoyoi
wVNaq0MpRwDs5bHGE2ddLNbs3QPWrje6kin41rnoBXEsN14P51BnbTYQ7zY0VovgBmHhi8RduBsR
iGv8axSzjI13WfqWCDSCSpx7fQJtuDCvigqsa/p1WzUh5Vf1a66JQvw5eHK32zTw0eagr2VXaz9C
gbfJ26LOuLgM/IMJgn8ohSk31zFHO7zEqtns3/XvzsVSiTbGCstLfdeALvxSJpSL8fiEv4vcJQit
jP7+K+X5ptsVwz4rtVrBSP6GNRBtp/6fyO/FNr1MPnwRxAHymhBTAkgeRb043s71cEb8xDBc0tOF
6KZvyHR7LOo0u540fe6Mq2259gBq8uJpdPjbCl5G32OBGimJDiiRwsTlILFwfUjCMAW8v1tWRWmb
wPr5WDGajV4TOjN2VE+F+nKx+a/ayuvxKtbN7iFgz9ogiL1EhkRwhs5+UG2PnP8KgUTDvcsnJ3et
UV8pxdbKPkwwNSU4uXfAWMFMH/WnNLblrEtJ2EdMJK1sKVvE5dFJF1ZeIR6fuDUXYvfeBwlu8X4H
Rr8H4WoDnYCywsCQmxaSJjBMS+ZsOeVV6Jw5FOttP5g1ijompqPro9S6S+7P1N2URd9cTgUgfVWB
Bp9yWynS8qFjpDZBLw3KpOf1ati7FbELHs/x73N1juvwTSi+xFglpLPAx0C73rDY7antHLI0flid
637ml+0BqexF50nsnPDLULxYFC56sMDMlBZdak2E993vc9tX+F4ral+qPg6H4AISrggVryM/6Wxa
4EXHKxjxpKYWOXSiyoIb5bmZtF/ySRRdr50aEWF1MLQMPg91GKkxd5qEoE1Yz+m733HmY5Cfw/tP
iL/SBjj4/v4RNVfVsKjO7EeFI79Vi7ilL4Nr+cIPiQrpadU4KAr0Z92Ylmg+MhBur1tuXqXMyWQg
KIipcLl9RoQsVSorRgGCKf8UAbeBFEcMQCCTCR20ksX6b7xsF7i/zZMiBqh2FvArySYbV6l7SgwK
x+VlY0J+LEyMRbqUIzKcX2CpsJdoaFxlqLDKvfyfnnSiCX9XnYdpkf+3nlf6o0u4+Jl383llvYJt
4bnTfsii6vAyde5gtrStHJLvLoQJCGdOSqJikuC+vIfapmat6WB2/pxsUC7Jnd+Jv+ua5khySk/O
Ir+fwV0CsyO24Pw1ffTNkZxazafxGhbFWvNF0SQ3QqePntYLi01UN+C+fProdQJayNXP/ujDpPEd
87/CKIGiRXsEJvevMBjkoYfU8fVophW1YIgl0lWx20bs4Uba/ceY3E4Mt8lHz2UCZKyXzqkk46VK
dL+HtRdW7/T2Q/+gJUXOVPAFtNB0imSKVUCnvNYtti1CwbKINuMgCJILefo5bWNkgLSurVNyOQWi
oewrUg4DrYbzPTNKtz1XmQImrsW9VT6t10Ok+sb7VCB113Uus1r/FpFhy1CKbEIP534U9zfAknFI
Qqgbws5gGZ5thl+v43ZEMGptQN1zPXiqpZIGdvYMQOZTucbEdt24AxyVdad14x9qs2isWJG+n+qG
6Y1DYIMnmv8Yq2y5xPrEUu8XVFNDehMoVCtEaF8Sm7WqK0+18XdQnCOWXGlSGA40Amn2tj9SON1V
3kVPXdYo+nLgR6DHmYMIGtfgLv6QeGQK0UTciCtjWTnjGIycFvTVg+HQuNpQmPAOd2P5gCHFGgAT
DHiiikfGbI8yZlVJDCToEkyjxcnrXftUydjbTd4AA2oJHLHqN0iLm+98qji16IO+5xBcR+wLSa1J
aEGqRTO7ha3W25MMktHHQ2mOqr8CCLpc5Ze0KV9SUN2S5QasXvTUEGFWeP1AuyLDh+xrifWF8Igq
3n711n1menznck8Nogn0QyFCpztF5AcG8TFXG36moA1pKxw/nlsx1EYPhOOJYw3mb0ULnnxw20g0
dcNfgM6zR4OO5Ac0JVhhvrgjro5R+fecOK/nBrgrxRmhpQ9Rxk6NsEveFrEggth9hRDY3Dg9kWY3
UEmpC8E9jBbDHUzuoXC15GGgG3c4zZ/QQ6n6Ou3cTiJMm2W2TEDcz2IFFmth+yKmZCexVoMpJM5A
nD7G5+YUq9UUmI06T2dMszSeZcSDD/o1zFrR21n7nzENwggneQMgtjWuYJo2PM+YFuemfS/oyRJe
YXXcV/X91zSL5OgOAopWkkzEw29x+Jdpusk60ev+b8qQUhqRWjO75xNhI+UKv2+C+j561XR1w/ID
TTc6xU0tZJsc4g3Mzi8UQcdvGx8EBP/E0VRuIKod1cSXdkUwX1cWeW4y0Apcc5s8me0+S/yo6NWm
h8m/Ej2JLxKPy8BFngKPUua6KACl+6Y7H2fS7w1rT29/zYn3P5wiVimwCNw0tUX7huRd1Yli2sQY
xheDanEhV5tjV3aBt1dB9gka/1ER0n14m2ApLljjvY7Ootz2u3pR1+qnv7CLRkR0wjXTzGTL7F0k
ogrNLejt+T9Iq6ibGhqGZXX1vjA167Cm8QcKDSFnSZrGp/8m6EfndDh6FPGFuejwGxb5eq2hQZGJ
paRPJ/TIpMaXx/6KWpc3smDOZjSs624CGJEE6K5gvuURLg4ANHAAOekAKa7/VaLedJfpuBzHW1hX
3A3sDHSWZgAt/Fh168A9pCtuv5TFvF0DSXXagmfAnEXEPqkB1KAQhgdvf96PUEOA0PTy2G8MEfEU
/xPsR3IQ0/pHiruPqGo1mHVFO/M8jtCmwUVk3hVu5PY50/JdgK6xvlTH3Xfr/qH8mP3CLSeX4QHR
Sb2k+9bE6Zb8aGODWF0j+gWdkItRpMwGweQZ4m/BBbjie/gpRD9CCAcozyw0Q5XpVYF9twGMEdG4
b7j1/qaZgt9rAJGCnu+3nn38u0Cn7WSjeexg/CPHuBExZcu4LX7seIfUJNB9r7DwbqAlEJQijEt1
pXOnylY5Xlk4c/+sJ1AQakHppv2g4N4hOQFmh3loJhbSp8cfLpcKLm1Wk73QpK8ZG45WfowEuhrE
/nubOqoZD0/C+tZowDNhBc6KQtBVnfPqF4rXNRqMl1yBbLzLZn7d+dV3cRaq9tFUv7D5U1f4sXUS
CIUARhQQ9H2n6skmn0xiCgTiCzygyCal+159Ix+onwBp52zCz2bkMv0HCVgF3vQFe9VhnUzhfn66
yDuyjG4DlxP+9O3IqLpZa3jZ3yEDYUqxfLi5BSD/ePsy+s/1QWS3vyiW+NM6PyXXqcBbVHFgzj6O
d6FI0NigrWGsq4q0ZFXNvJHjvxSvJbmQ9vHfvL5gn9pQ1gRRfUQxnNZv1HwzLQzgO68pRQntTg6c
8amglIlA5P62fuTMPD5Yw5N5NMAWiEyLOzoXoyfTQBVulwEoz35Ca0hDtccF9ATnt1kjHhV72F6y
8VHrOJ0EPnrln8MDWTX+pv0DWQ2uWh12Qjq2dlAklE4WswvIYXRGV8Vzhv0vit4jSnGSFQPv1J4Y
7eob9JxeStsooyE3/zmKrJIaPKVxdoiAqgQK7Msq+gmrM7VI874BwxCagOjeP+IAXq3EcMqmH6cL
rlw4pS4CmJgMZWc+1GqvVuelJNg2Kiz8GO+CU+GzG5wGjpTdAX+gjdylL+hCWVAoUjFcQ5Bcn81v
z4CLEsZl/NTLCqZh+4Hckvp3926f9eeJ/F4JUHLwWVmIPAbPAQvAK4GJOin3RlIa29Hmr7Kmsg7G
1QiBy9OADMLVT7A3YM4kI8spbvbWMrwbkOH/Olb+sbVm+LfVDinqnx+NWeAg0nITCrCzw6duM9fc
VfvFb9IqmASj/sp5nCV+I1XQvWU9RQqEhuu9FUDu19WtkV9YwRMm/8Kuo4tktZjWSe9YeH0ZXP/x
Zk8hjm7cLkXuS4iQ/THr6p+PD08JkfsOiaVP/ky5sSCfygbwAVYurdG9uT01qx8XgTSzAz8Hlc8f
DZXk/z5TsCk8Pu/81BJLRTE47SI43k+HsHga/Afwdb6UBPDLEI7RQrhrZogYLC5DGGYy9EHBDNEJ
oyPqVI4dN9uMssTyOqJX/+WCzuA4STgg4lacDvos6q5i3OAu5AgK/LS8gucpaV0cOnPr5K0jFQHk
XAjDU9ElVHH/pYvedhjcKdXzOs4WSDHEFkKrfxTMRl86munHiytEGWg5Frnde32k2Dl0vVjs4cmB
1fVi2zZaypBozGaVJ6xut7g2zhWg5AzgUPukZFvwHDqlPT2qXkMuiXDfn9EJei1CAhVeFRnS5WA5
jySNK2+DDrdpBaTgwzQZDltwN0FU/diUqldLSdnmNHTA6UndFBHK9WRlwEIs+G5CGiPti2rUFx0W
dhW8s5GhFD7Fw97tFg5zccdjVfvE8+fqvhSXR4s+hHIQ1sJfHFok3wi4Ig/+6lZEMqOq/5naBm6S
3oo5fQKvVIn31M3hygSp48teFdc22jU1yy4YKiAjp5lxjPMXnpL527ZCWu8wqIw3Uc4+OGGcDJly
PTr61CMtFIsLINu5xSMIiTKOxsEUqekIhVdTwTCGwgo7Uotu0+XudHr0uTkXLWnj92NUlMhrf46q
wGU7wO9DyEqCQRFUHa9cBldl3YO+Swh44TBfDkq37VIl125ZWcNsV/FwiSzlgCUdmj6cOmnKjY3S
HpSx1zwGi+jbOY4/UUSVfatV3cRBCL4X50a/hfR7DfCvpJGBZv42lFN/RwwKRlerfa7G16tt+7CZ
+IdoKAT/DYILlhWDK6GxlGhzVckExXlYN9gekkKhaoCMyEpyRWvUopSvqGAaK12Iiwp3amWkCYaN
kMFRJ4be9WroCPqZfTYLjwfBXplEv1TvD2tvdRAmaSFv84y5DBznqibSzylxkQCef0rUKxGd1Gtn
kuPdmaD4zXU/oz9EnSNb0xSgt1uY+eBN/hwdlWfjJZGBxEI/XJx9h7UlMuAp859hiiKtqAv7cWh4
nKBeJebgf5gnpfUbf3jNy3yuI6yDnqizrsxscE+uN31/uC0cjrCm/y/byD7guhbXDZ5nHHK/laDO
B1TbQmBGhoAyu+4Bx6URl0lvKmwHeD37JbOwg27Gj+SZLp54j51IjjjoRCZxlg8Dw4e9T9yq6VZk
ePmOwZmGS6agkgJwogBpi83uO7CJmDd6naLANXccNyDePkFuyhEjNe7XeyvX5ecPvcnMsR0ySqpI
TiLKL1ly4KGJvzzfzzgDh/j4YDQPrtsct6ICBnWpYiPyENht9KgeFN8ndNblxA9gicTNWQYB97Oh
JjRgG+xKW6fkTh66isQs/3gljWNUyyMiZIOAHpRTgmQJUA2cZsYUr9z7xSw1iyF/MINEc2i4o8V4
yTB/oHSSl5/iM4jwiSNFQYzl2MlspF56A9MtuelwWbL6NGR35CerOTt6J/Suba2YH/EW2nQziaaB
01APzZn8MaDwjR4Ph0TGoL4tweMxQMaJ4q8s04DC/Qc565HPbjsG5teT2qY2cD0+PnEkQqIzhy+8
OwGb/CRf1c6l5O6qCcvUfckNhE27UPLLfbGP65H7oA449oj7O8t7jTQa7FW/EeMtUfL6W/IRJkAX
l5tYv4j6N0K0ssKAR8HF+iJDOUH//cTzsUSwtKwBTIu+N0xaiLjZcDF1m+Nxn/HYz4u0qDljnl6J
aZAIw9SeweRmVEN4ovXwdPaNAW1NxiaLaewzYYLMa4kIkT4U6pRZkERzHo7MqFYtNic0C0PQw95/
UA67kAn7DaxTGcGe84x5A9MyuK+IvmLAlap3fDeKvpuN1MFL7bPQ9YgsstrWecLuIVfGjZOjeES/
GQcIWhh67LxLrEoAvH1Eilu+iiXEUW22x6vO8uSxbbt9+C8H7FUw/PePyeTJNNKu9OqfrlktI/rT
gnFNKH+lvAYsKomXbIgAyFfpjkPnI0Okt9yny4BFAB36r3xytqB5quEWGneSoDE9ORg7FzGu2BCO
MsvsF2ifD+3uPII3dpMAggZ/JfBjiz+JuX9siIlM2oZyQh0H6gPRc4787gakjxq/kK6htQDnmzZQ
jy+xL+EF4cEoG8yWp+eL/A0xy9navuSPnNLoQtGVLng8SA/VPc+BI1nR8RmvIoSWRrga6f3/93Jp
qSU1NskM/JKsCd8vgJWtyJzJfCUt8rvWuzRY+fVG0WwTNB7O78ID7mYPE0jJKAnCKYJhh+gVKfVr
FqJSsY/RjDupCW1LOipXJ0SXHXWZaub6RYtvTUC0+egBU9LW8VcyE5XwbaPiTIuzcBNzFkJqYsDh
2UC/6XQJGeFH79XEdaswn6Rnkm4Ha0WZZB2+NaZtpdKsS+sKBvzPIU14C9rkLGzx/AYu0GU9F5m7
exqse/hONfMKyA2JSlXpL1o9SbhsKveuZ2vtOE7NhloAbnHJy4tgHqyMdMbdlA5jSYGR+Uxjas90
zyCxezyRZW5ZibWyJWHLOVMeALvSqd7hIaJLtSvWxJIWiE6X2MfmOVTyhA2E5IL/d9pVCoXja6Uw
d1kegiJMUs4SASuqo5QVjCE/K29Mm3pn+hgfTnHKDNE5/PXNCOyJphwLGceUSJQ85gxokZhlmFKJ
W+Ygs5Or4MpKdsL+U6vFABv/hZJCvSEK7MOJnM3YWYG9gfZLX+oI+XbofZujU4Y7Jtmz28l1u+aP
piwEobYPc/gVrGoHvB2pCE02MMiM+LhS5DkfjUMWZBcx07S7IpJyNY6LNQLDg8QoiHtjcBRAJBhw
S+3ixFfwqbnwyzHCM9fnZNhiN30X0c29LX/xs39KS66bWHwgc0CA6DfSviSVXAmecArrsrKbinZ+
HjuoXbDIoufupDKAfCfvrfheB6AbHaRVEFLwjpCGF10fTPJqq8t3kyajNvQWl5dB6iNTcGttOyS2
WDrGML98fFRK0X0401y6uqxX0ol+boCmW40I2wnWMFhChAr4tud3WQ/lgon46PKkGNdHdhLr8ALE
hwGIfuJk9t0NcaA30POdEh7E9yCG4fM4hxFwUGTvL7jqwKSa92A9pSc1VeRN5wgeYUc5XpCaEvNF
1k9p9q0myyns84AONqxve438rz/jcnvFLG+LuuTqFx6aFzNtMtXy9npme+ag1A0LuN6w62wGg/wG
rj8S1s2D6OLqhtrpAzPk7iB0TLth8YZ9RDeb934yVKDwYxz0Tvz7scMJxaveoThHHM9yQifEcecx
U/t4rCaqs+sGHurb6c4jQGritT6vYeIbDCUt6Mh4Oho2UP8DqosbK5Nee6CDRdGnALvOHyG3zTfc
Tr119MlxJJfd4ftLyeHZAeLh8YwGb8iWqnsLSOc0Kgxmo1m4+aVdWSMlk1XOg6qDTWYSlOp5AH8L
ovXo9jSSzhpH/a46KXcKbaA6Gr79ESZdChsONY371x2tg5Ltmtv6zp5DuJPjk2/WOf8HsjGno5ul
zcdbryPslg0yWm59WXMOnZQhsX4FXD4vL+QTi6oJCCO+2ZLjuJDyq2Mo7ONtktnmXTCf0rbxAXnM
UK7I/VDEMcWXxhJy3OXMt7nGs8CF+6ho7uxGeL+k/axwtSdOi2s5U5A3EevmlXpjVt1XICyEIt29
EtBaCDztE/aA0J56enLWjP/6mqG5BCm9QRmjJbzIKiKa8Ol9XqM/0nuzi00tASgBni8guEr/UBhF
Rq+4pBrTiLeaWjlMkmEMHwryuNpFpVM2ga+wKApc6eixxzvH947tAyDS9/cX8d852qsXjkBxi7lF
zmgxuhwM/UwSrRkZ+yUd2NtquQZqxshES73oME6RR19n7DYbc7XpMFtoYx0pqgfVVL01rhyvRc/+
8GhXq4YZoAkg0QNy54vwl9Td92TrJIsFBWrJXqQdQBx731h8Th+OEQoRQF123BdnGwyXhbgHeXIX
mtT9vla9c8CA03KHQWbonAe0OJR00Ms0GId5AKw558FXeB/sN6E/LWDxG7LQ1CKo0WnFe5i0Me2g
o8MlH4mmmkgA8e/e+He3i8ZFOtxDUH7P9yp/erJHBg7WxV0TbMm23y2lJME89pwAsDtTWr2p83gf
v3afOetK6QmY0P3k/IvE0b/T9kn+yYIR5MSov8v7e+4pMSCJrrFjGgIZz/61I6IATwU7vobUUddD
iQofo9iyZ5sSV0ezYSJIq7Dii1tVsg6lt8oZqaC27KlJErKMqO6wt02S2wtpvtFNhBc5kfAhctyM
6ADf8YxvBM8J7enkLOTEMTs3EgpDo3pQhMWpYm/0AiEjszzbjqfKqATVXK4M+0QThiaR0AvZQdRO
y8sHxyuLSr/L5rOF3YcEdjwh9eXFLH+WW+gxp/Qb1NFAOiVAviZp5+bpSNOh9UtIdL/jkp5pKPQw
HE2lXyIWl41r97re30od3WWExajilD8KVuGEuRTVkq0AwjTMpgJppSc92Wr6xsaemTeXHBjBUrTk
QsOMHZ541rFrlJAki8vcSXOy1J/QaBSnmG4Pd7h/mWrgafubgDUC4ZDTIymnKD5wvOjXiucf+bqk
9kyHsh+zO4gzdoPn3yr8SkofxH0lj94mbpqUotvttK/gbmZLiiaokzfC/Wx8jzI16V/fWeNpyEm3
1JSnzBet/i2IqaKttsBcVSAq+fgu7EjmO2tfEX3Wbyq0EWxE6morKVDtHOwiTQrP8MaORIr0cHSb
SpaR8/1bgZMqepXBSCtTZl02f8XmKt/NRpADm9DlUOgeXeXDbEwGNBJzku93Mof5kEOllpxX5Jpd
WSXa0/2fvneelsjyxOVK/qkZWvaOPSu2kgvGqNF+hWdIXgm/ewpF7bxWqE8GEOrVpcHFz0xdgyj7
AKKcETKSh5P5SF4rqCywsxBrnMVSWNGnr1jUbejSSz9RBDyVxu5yDvV47sahRGJ78mhNVAIbtlH+
lo+Xmj0KjQPqKHm8sACAjx7Pwsz607jU3Cj+Ep7l7/LYIFvw/WVu/vkyeNkzzVvedRbcfa9bb5Fj
Um1mBquOKGiK+eL866YJ8DEW7m2JDLHALLLkkslzjDh8cQIDsBRjSEa81QVF6qonlLp1yFnHJYNM
Uh1p9ogM0cLyur6rt7FnN0tOZtt/iv4TX2RW0qwhS6tuKKyzhx/F708bYCZJuWTLjF1+v8pMTLuf
hre65eFkMBXtuFYMuKqePK7I1WoV5yHuJanRuyPtTQktFUNGuMDjJBq0/zGolCuDCWrFomBj+J0o
aQr4mnbDrC6I2Wjd3q3FrVSU0idZqoopeptdcTZ9l4MVztQz5g2FP4rdxKM3xo5K0EAIpLSa/sYd
AE2BRN1RbYmbljgMYmDP9wBUtbwqGOS3e44BGfpmOA5ylQngoWDYz5Uzi/BpyvC1EytdADM6QmyW
zrrRWBdNCvgg7dr5KzWweofuBHHRuovt7O3w3xFR5DtA5kBy87TCgxRtLjgpA/KflnWGM897GALI
4W8bHZInqqfJihERQLodkxyDWWXYEw7c3+pjvJpjsWpVLvdSTooyw/zlPhXFhOQfsRimt9Ax/Ima
svni9fqzSG+/JUNrN4KadzKobGoMxiPsNAKw1xPDuz9Kn4diMJtIfPIQgQ5+k8sQQEd3eT9LXnsY
gf6+GtYPvTlBkn+jwMmEoTiyanvA0REc8HgO2z7c0whO9Yqla7wTu12C1WmulRmxr7EM0qdWKlsj
1zo1Zc5sYM2c0KpT8TJCv1IpE+sTquIAOwDD1ZB7Vi+zKdJm2aT9fk/yb/k6N5A6d9i9vYQxQO0e
bJHIK2+cVApf0ol6MARKJyjUbpLIxKGrWBNh5itRPFTtquFT+eaNNFf7wDmhRzutBMTXZnpsfetH
HUY7JivuiaD09+xxloPZzjZ/D7MvybPDBjPnudGmTMLqz0TjV3cZbyc9ngEHriWfGervmwJaiDKZ
w7+WvAi2wCc0abqwdXo8UNqXAGbgdljQvdCKWBfKR0ycCa+rFgTEjhp00paiMvS6CilZCltWXx4e
JqhIKCmh3+4pscnXYJXWSO6xBjjBiMlgeQAjR5Hh+k/junUUTkVcWFBIJN2WsvUrl16weVj7D8cQ
K+Iks18Rix0PE+ElUlI1PV42H4D4MkevD9jePhANZKzyHUeTJFJ73JOMYsrZWYIvHOfhQSVFxllm
yoxX+katQN4AImAm4qgiiBi+pp3bYROscevAZmnnD0om4h+Xz3vgkB20CbWv+1x2s/ZXC63ztj3H
t2o7Iti0Mf6781NK7cg22OVotEUYhoomQxHjTuMh8OpXMs/a2u4Dy0NZHtTkaGh3ioaz9tsPa3sO
HvCgpvSFqK74a3zwOLVAxDvZUMVF17v2v5quY8fFCsVG2RUzJzuNEocds68kC6LqHsP4fSBb99lW
M4cFU5p+bhRY3I24fVL7FaeJAUTldzmTZz6cDt9kcuLM1pHxiVS+MPuAO+jdhtwCoepKErhLa6di
HoHPFmXVty5hiUHTAdVL1MzjJGyksN0vvQHB4JNCT4VBdniMxAPV2iV+hssoJeC19QarmXcHSAiI
GdNtn/8HnRgiuCENIK1WoHUQ61ng7HZ6F/LSWR2x02g+4rlcEe9l9UzrMq8HCRDRPOXLKt4jCa50
5TtpbhbmMh5G99iZhPHXpoukfxGBkHUCWKsCcG4rnhPbbZUJ3Jopbmszf7zwCt84RC5HCqBu0cDG
/qD4LExyPj0ls7fm5x9HP3lqwCCsH5sAc/fiFo2W2MwiUm4RUTMI6x2lZOefMiHajHtyEtMz3xGB
f7Oy540bzAOAZkPFWijG6MeftL8n5xKZrKGyQZVtxfrE8jGI3QyFkJeNY//vO9I6S23018d+meJQ
VB0Tg4bJGCbyTD1309DqHR8UXs5sCw3skyuWXIDNhehRut+h0MaVYPmME1MLYbySRCFsCnt/Snur
x8kDDiBXd8SxBSZ+9Ol0gVo5VMifBPLaBBz7HIlEAmaG8Z7W8nYDMiupckEqBvQJDAjvYliKHQf/
NvdzpA1MjKNKF6hHOBmYqcoEWzDZWLCDzFM7AHcmGJ9fMUX424/S+1Q6EFuHrME0XlHoLvVmnEn8
GvH1GOcKxFz/+c29mNlNjq0yOik26q3vnwT+ooVGPzEZGd3e3DTykJpehZqLDQTPTyyEO0KqN3MV
Rl0gg1kiEXh4WS5ZLAibBCHey+/YYwtJ+VKqVcyqAajD0FUDchAgJeeWw6TDd19xwSeMRjytYlBk
Ce5Xkw8N8cDUMjBPhYIPQqjIUDxPnNQx0VObH5+DckPyL8z64WU+sS7MSOH/0UoYeuHk3U82ugya
A2lcVU6bKF+uSq2XSbSZALZZ584+vZdVh2/kSSBLOcJmXE4r5La2h9kTqeszirwff1rl38CsDkhN
NUXhrZZauqCPL2AJP8V7IMJ8KwccXxSg3N6gMSc5d+diT7dxUsZUKdN66xFHtiCMpzYqtn/aHmf5
U3w+jfdo0ILsDquyc6tSziR0J3mnE9flLeS0gDOP6sIRhZelq4LkkjDeIYMkmFhRyTid8kSuEUSt
jsRMfEMsitpgKyaoT0iDjfblrpNXtLDaRGyWIfgwU14nWsdHQeKjv1wFDosYjDivtkI4PCUFdGFR
Y2weGWX0B/z1HfjyPGDTQXrjWR3sdZCoFY+dfNbAajBKlfalY7+S2AXtwTs8My3BjkxN/1PCZRNM
E4SMPLtwJvun+e4jU+VpDtqWQOP80bDoJ0BiNPWvUr709vMA1feas2M0h0mpv8fVH5uAJ+l4Rwyp
/zWefcVLtk2rgPQ+7gCGqsTfs3kVW7HRdYOcIkkQ/Lwro6+RSgEgn2gg4zctvTynH9Yh/4hL5sqT
YZMvwq+hYJko8eeZLFvrAmjRSYWhpiLh9clZP3+URFAUU9nr2Bm3RXlGXA3bAo9rxVG1bgKojc5T
cT1nAfCTR3QTzUuGGMl/wAkNL369t3XfOzj80Y3eIn2H0DYMl/q3w+YofvmNsmqQ3Rss/p/NQ+U8
W3oOnf0KGt/eSYmWpgsINvphADZvQLrgLGGUzoOuAipflimpDejoUgd6ra7uJ0BGblw0WIO/cAjl
ridYAnWGnPO9Md6UbVk/wnox7o+NQ4g1X6yE04G5z7NEtjAqt5v+RELH2ESglriWlDUfg53Kguo9
a64UFgjkCsAlCgjnTkl4b9TTmmDnlb2uR54k33MOCYw5VZR+6rVYxvzY0cDs8WLhFQu19seIQhxT
+RG/XsBJ9wtwpVzI23IPCDqY2ZAE4gUHVBwl5iyql7T9AtkaLBcCrnQ+GeIqoXzRdmrO/T9Rha6/
HVMUmG1BHLFye/2rvS1iuLNZ0NAz5JFRGCVu5FW8OXNpe1sLCk9S4xc5cmjw2VQJQ1QdiM/q89Zr
zbGX74zMrC9ae3ppvvbXVU9q8Qg40rfy6smkM7enrOjmS/g2+1ce95cr3iurts+E/e5z1//YjtM5
HdQjvIg6OaQCw46W0bJBsPwvVf8IhnI72pXRz1OaqLeAsWKlA21jPJsHkEb+31bakO7ww3h9cWeO
kPUfvegXFMiUWaziAR5hqQsukFsDUTKenKkQxd9UfRukvJXlyR4gnSlTvhKQPwJEDsSdJiAk+nOD
KrjS1l+awu+yconxpaqAjrgO1d5KD4/ELN9M5h8ZwMbi42a0aDeQYOTjNJ7uo88XnSD1unwSSEim
Wa2wnXBo30fMAil7WfaC+5Dhou/TjtYf6LP5SgC2h7d6kIvMBJWeAFBgGNvzsQSrZsVlYUBlnYvr
KQuaCjDR8UyNfWz2C5acNI/26/6hMkdCA75LO9lXBZ3D0jE+Ywh7tJDAL28P9Ynhfs8rwG4qcUqX
VQDeZ7aR11d4sPgDhAqdguchGC/j1igD81IjTGnkitpSERcUTIEhUOHdCiDIBDlH31x0zS5lBsZD
hcAfQJ78/dcvAw3s1H6BwRbhvoHhdQCKYjJAq8cy5vaQbnMKgqpBDTSYC8iuapAJQKcuJnEn0tpG
tRyIz2chFvQbJ+7KdBOMQ498X5eiggOpcPLvmdq/IFFz8MRAi0vMWgPcU5JwPZAlnUN3Oqcq3zh0
SPkL0q9ByBRRmWevOAsMLBTK+94c4MU4j9BYzyGvmwnmRU0Ze17k9N7QQoEFjP/jk1cTOkpHwULm
oAlWektNcpSXC+sQj3QWnVznV/31nHEN0XPovXTIOgwXvY+soYyhSbdBEajHiODqFNuWvlllZ6w0
LX+XkmMrCGozp0gnme2y74tT7Nxhzop6rSUauEMDFEt/eAPZQnSmCtePK1iTNnxPHAxE8SMyKj5p
hpd0jRjOF9gN6FudLnKV4NllaB59+TcWy+Apazu2Yld5nWFnjPDRyQ8v2IW3Mrky1liOk4fMiVdQ
8gOXRoBOsBeB0bWd3Q5Xv7WBOdqONe0gK8YaUCg4njKCKwIAXgH79zJ9qbDZzbQxkpZS/x4WGJrO
zAwgxWYmUo9pAcZy6yKtEh2rFBzsAnYUBGeT291FTHTQN01FfSmW28CEpi14Txrxl9Bl3gQqLQwz
UBak+sv865GhFojuT8InLRME8Dr5BjjFz5iKDFGn59yVffUWDh7Ih+Oxe0y9/j9g5uLLkzBb9p9z
+GuoPi7EPIeDBOsdnHiKAxcG72NICKybm5G/KzN5bBEVM7/6DQopmsK1K91fa38BdrVnTZbak2bS
nt3B8uNJgWBbBheZOZOxCKnpzLMm//OE2gg+84Kou4o1bAfPV9OyeExREP8bSd74VRZrAarAM5mi
5Aicaa4nt0hJ0dFOLq5Hf1bUt31qnO5fXnUEL+2fgS6srhZUNAi4S0B/Piln9sfVhY/b2DrOElcO
wZXlcmDT4BC6tFC4gOH2cQRVNiOxqlR95BAExf44E/WcXo5zKQP1tLUaJyZK5YsQWkdnp+HQiuQ3
tTqSUIgMzmRQg8KQN8nHaQxJZO0JApcIVcX4Fdh4PXhgbUtzeKkkydXTZQIeDrAF8lbJqvPk/Ppy
tE00Ujk9yl5Iijb/budGtSipLjQV9L9eBgPn60qwxCt17+HPvirV2w1xspjy6HoOjUfyDAlg4dQA
tCgULAqm2b25LIu9CgWfViG3ZD9/1lnQDGKffBxkguvWsHV4b8VVyWhAhtp8ZVMtJU7AcyE1Sz8r
VgRYMijgiIBNttdVGqI0heKmXZpcT2td1FsdAktEWVBdfIW59rBTqvHl+VdS+LXIzL1slORJV5As
pxwuIfoOf6JzXJXYm6VOR8Z4yCzKwtYoL8Y6lqwS/qyQ9VSoHyXeEtSnz+1emFfteUEOgGdcMcE3
eEwFhnE6awUPWWSTO5WCO7KTBJPOp8KHsFzcvsYQD6IjGskUKTIbbBebEaqpGQXOu+baOjmFtl28
R6BFYps6OdUPsR3YVcnY9grrAAYSW43FrqKESjHMEDrBbJYug41oRGlfzsYOzJG9Spmx7Ak0Q7s9
2R2fFVkAhFnuvjD4EoFpcsm07CH3hY1JJPbraEO/v2it9e/OA37y8pkl1+mFi4b8kJmExHq+zsEF
nRR2q5rDs6c0Pl5yfa2Xf9sk0QrfgPJBAOd6zPT9c07uKyKxHtSmVvFMDp/Zq751KlE/rSLkh+IF
j97kFJkc0iMzZcKDKYnQMLMgCRT8czp9Hv0eZjUxDD1A/0o8vGSXAACIIY+EomTmgGpyjPOL3Nqe
QrPEL2QTThqWOiC3QwFhjj2njlqf77h0KtKKDHRiBTnrGGYCl1CiGm0UiQhnwc1lfucXubIik3ZU
GIVz1pv1byMMLaCuYywXOqcutHXNXiUzLoDzqkZ7+BUGasX4tSZVKnTNBR78EhQcaqPcveTP3CtD
AxM0p/qqw0iOIi4M8734vL156n2iFZxfXJO/y1uiabxCVBVm3AOa8TjZqKVivQVtInLjYhJyncZE
gCXMhySpSC9COYyGXI5AI8zdoAbs3Idr6+CxNTtjHGj1owtizr4fI+AOFPF0Bh8MzvQfZNLI+m0C
RYQOhMoWxbTos6Tidl63b5k9ZWTu1r1rZVXzQFUJjL4V1bMev1xIOXIMQyA+6RYNGqCMlxGKQ75V
Z1VuAmzECdt5d9ELCj1BoEzGO4O0IAz5J9kWYwhdUEciC/h+gPrP1WmXib9pJIQhF5ZrjJcVt/i9
vNm/cWgoaAYceev2SAM44+Y3DwY2LQ0ccASRibJ96kNXEowI5MYbWT2rpbPRdPunUv1meibS1dU6
Suz4TnE8zmj33351PSGgB4qrmMMq7PWZ8OJLy0NO2CX2Ar0JJqCifBCL99sfErgGmwy78emGMmNl
MsaUg+InEjpxe3f/FiorH+LYfYZkM5NHWDsrc7TJEIDjqfioerbzaDP0G4j/TYzsmhPm99y8SG5k
5PK50cyh/tT7wXOWJHX17oFW6cSyv/NhvCyZVra53GcDywPn7kMF/s5pKr1x2Krz6hMzZWGFiGuE
26arQkvginB/asaz9dD8jSB+RoZEnu1X9w643zB88g+7Y3NppRiplMaIUX+A9QFdJ7wlTqWHk0au
pC1BCd1J8mjZYa6BYF6o3IGzAY0ApQW+stF80X1IUrBJfM28r3zFQWPl7Fc+MVVW6KDa4lh7tvF8
u8UIg7iJhkhTW8ZJGL4Kc4S6y6fP/pElaOHpRIyhQtxe7oRyTA4qYOd7zHugmzj4Fj9MBbQ0uo7E
h11GuQV316dRKJ9Yp4wl7ZkC51b5gTPNaNBjhSxc910WX6NnwIv54fe9NuRQvphIAY3VLI/icUca
3/Nl7Eb5b6BRiL998lfyeZ15kAQQCFprr5IukCE3QDGuXWcWoVleaxbBInzldjUMrgsmyTOxljv5
N464g9nwPytHFQMkk616rkGOPBgnnqBpHQD0jQnZHvNAQ3Q6kXNFqeXYjAmycEsDpx2DoPqTb9dr
qcj4kFQ6JowTwVXvVLUnI7IfeV4T+4iWZ34yi+V2pk+PdiuZ85UQ1W8VXEkaYvpygFN7hxX3K5iW
L94attF9KH0aON8ZlPbnQvos8PnsRFxlbDFKoMN1w9Q9YFbaMHVOYife89iBOLyqawy5mgwAdvIb
UU8/MDsd+M7nKqSbSkG1rmadceGuNbz/7yYvN2zJvz/s1ewJ5xW3/2G+2FUa2YV2k88E/iW2isWD
T5dszX+zTDMGevJiX/7foAK2ZLvWGPCdXfnO0xTDpkR9FhaLWF18+D6vY2ux4/CP1h+QZkjo8HqU
6TbPJkkwOjBsc+/GP+P4yJvyxAuvn9mnOAS0i1JY6J8BAdENBGlc4TmDCJaMeNCAmHRQGBeKjT+T
pgjsHhd6DSWPvt81vQP4l9Sis6yQey5rWREW+jSn8eJ7e94xodCDAc6cT176Ysq0lOMXNCv2LI1X
BQIYzjp2Il6OnQEggY/+KRmunVAPs+8NLfDZ3LBKxVrh27NmoEEtjpJ121xKElvVQDWk3W07r9cs
I++6RZuhzeQQBygnCD0g/kHoMAWCXlmWuFn9y6S6w08ZsFvlZdNJFcXOQX7I/MqO1t7u03xJyFg9
jhYRhfwqFE5+kbJ6HYu3pmPa0CgZd730XDsofAfpNXjemKahrAVcojSBCVoc/rosXh0OqUNrDAT6
lLE3jRpDjs2C5wK23uHtJkZRq91iSGgB1Fa9ko/HnWiwFdIsJ/C6ZgqE+k/D3m6ZW2rbMIwsNivC
Nc2QKRaYllWDXp1jHNzoJVs7BQxXDHVxgXjQ+VixArR/4LAqWYKB3rNICUM8ZvFPSPKLQ+5QzbKA
dbflD31xgITp55AGB/n1BfOJzAQJXIN7gNqPjYKy4OE4Kcvu+t0iqgCESqURdsVaMKiHVHmvaw9c
GHIMzTBY+rJY9j4mnD9u3Q28yJBKLztzURDs9FYNhGmt7i+V1DRABzdhhAecLpZOn2OuJddKC7oq
xLtUbOZwhTa1GKr878qt/WyooEfuz5d/1oRSJb3f5VpzhW9CWAl2ogE14uGo7jb9rba4ZArjN29d
MmKnMAnsAcZUvkbNunvhcRtUyYqqXF2VsbHOSd3mPLqt9KHnBY1JZnbCtIAVFZBpzhUb4QU9hAAj
m9KY1u5C4pLK2mT3waveMDDEEkvQ1KSOOzZ+snci16YYjQ0RzMsMs0hwuHX7HE39jZs1Kz25U4Ol
6Iz/rWWbyxxgoIplzMSKAaifre5SzssrslP5U6sj8+x2pihiN9IKAqQedHhtEvp50y5cvaI3Y/8C
C4K4FQ4BJVg23weqBX3PmDUiXsNvJ3te/8x4zyZzTE2aBkMdodZw2QwgnTk1tfBOCIXXh7eIPye+
FAlAok/94EbK1MPBHlfT4/fQFQkOq7oiDuIcKeBe/PMOUrgJryu6WD7RhT9kD6YFmuPtjhjIM9/K
ela3Hux8p+TecmtnG+HrhD/lNBagGPOTCcb7SvUEnhxBhbQBjabzopip0gdrFAVtXgOmzxyYm4N2
rJB560JL5ipDYYeI6XojpxASUoIenqlMniQAkt6p1DP54+VAsWlpPkHtP90Hx/+LWS+LIYi0UZ6P
q80G9UbAcCXs5ACGLsLy6infOa4o4wlbKLYr3Zq6Y+2nzwRqYasV56IoWwBhfE5Ll7Ad554l3tla
EGOd/As5ByBmRdTWsDKPumgZRygyi+ziCWVwIoyFloWhU2fyQaQOwm9beh0TelEfZz6Ay0RtWTMK
GDDKGO84c9OTZSWoBzmvlcK+LOGpCMc59lYqNJYxxSNKuqzO02FcMEja+gBSMCzw2V9Qus0Qm0xe
1AThWuPXNbkpK1Cba0MgVfVi5cyZEbzwNrXZQIUMaPaKtagYRkkGNwDy/EzTQtTg0SL/GVZAfkFv
ZdhtvR40Nd62bwuDwzOGJtevS6AB2LK5GQ0Bs3nYY2w3Z9ZtrND0C7GJv149K2JesMC+3SWF+xcG
PQRueM9q8QT27ON5qP7fasZV6duYH82y/XhkYSHYIUUQLeQq1l7prk9SIdNYlCH5FBQrvC2beooy
FfiMpvAGkBfvnrPP8OD8zqsj9nYkzKz/pMTBTGI/dnvoMB9v6U2+JKvr3vV6Xhav6bGVyrjzLc9l
TOxozlFw96ReOX2r7f+gaCfdlC3ZD4vDlh5QbybfEeGhWIm59E2jYubb2OC/A+eix7hYnZNIapSY
3eBGVMjDpNr96Dt5v/6DCR9j7L6KEcZEX+oWsC82lRX36LGTv202nzPUFU2L5nEvn7GxrdPpmR8i
NO5K2IUTAjLt3h8MPYsMNPtakExF4RWUwxRb/OEYAb99oFz6gMS2g8xHpzuj9btkUK75dthQcFcj
YV6GMzeeVPEDz4oxCZs+mpa6z4+6ssXR+OFUQMjC4CFth9Y3NtLbglWD8gjaWWZw9lI1VN+fn9cy
urarld/xolvXws4r3MDIHlqaHxdCO3630bvfb8tRCUEz0ptDKl8LWjBbU/SbejQEsz8ivkY+qQIG
sbE+TCM6CrHsQ76k0sbYLfS47GnIqVxbrdTYYmcekOvqhwplVAkLgFZa/Wn68ZKMDsuSjFx1DUZv
Ab6mXpzYa5Q7vlo0chFro3JD9FRGzthWXHYCK7zBbWf0riMIhQ6L2Akb4YURT1qq6pvuXydBIIdl
mBiuJlqmBB8HxxPlYMzAMgKQpjWimBeYkoboJsnPU4yxTTNuDAiOGflAI7u8gKNga7VlYRjyVIxg
Ysb1AZcVGK6Y/aSeLLhAJppcSxQbgoeYl0bE7PvJe3JLWGTqkSBQEWDeJEm111oxnGKvwn9yAl1E
bmNcLeg5DJUzVPv51IlrJbsZlqU+cSE769GOzJEv5Bpd0ETDFoxrukqaCj01YJ3L8iy81afJvsIh
MrH+vFkTiS3tbUDSBk8mnx26KABrXDoHOI3VsvfyES+HEo4fYw94zG354GbTJiFcqYuHZ1+t1Kei
3kPn4iWeiAGAkAKkkNHOG62qXPALPb0VoXAFax+Jn+HheasYOwlKPkQEevJJJN3HZCG2rbVUlTBX
VX5cZZYyaOlLdHDSkGBhAIyGnKmoGKlQqyOdpnNSA/u1vBm7m2y3x0hpoFdcYbsbGxIewqDrAE93
d3qvwa3k9kKKmW7eh6HnER+jlcWUFDREmnd2txwd6dalDNZZS0HkurojaTkqWOmdxwojeSE9biWw
XUI96KxTyeaVkEZMVGh/FdZrfLQnZGQfSET7dXKBae0IPSxR46GFVBAIMRzSt9HaJueouFoFnf64
1yA35kj5laAetTOmsb895m+GFtOKvVks13Ij9Oe9N6DZkH0yQKfmhcevCi5XONnh9MiltgLnfv5N
HOZZ7fcN282mAZCk2+ztBF2I4mRuXXGTNcRwKu9QpSrQqIgDmF9bmMON1VQox+LHTt3Sq0q9Lc7V
StRA6oqAIN/2WvP6Ynz09Tj/0CTBAYwpbBjjX3n0O6/9dwZa9zTOlcbOHFYyQ0a8b0BDQPpes3zG
H7/wyPZUf5HKU98N2U/krMbMSCdnnL9suWhHiMTWO7pXkmEV0w3zDQlWFMeg+bcn7dUjSyCNLz2q
Vm+2iFm8tfg76DkoYR6ny0RwZ1Qm7xbOheJL4LpYTdOZVrMJVYhQxT+v07dLkxZPn+1/AkWdIGcI
r4ix0V/2ibk/5Z3jWFf1ufB6F3mHaAZDHPBfm+uykKKKS/8DTlLVlGJQ4TUGHz+ekD1ANQHopjcJ
d07HIQLRm7c4hIRX7zSVMGC+gADQiU23gcbfcQaAb668FgmoOnEH2x8QdNGR0KCEMx5YRGc8dDsy
iTsIQ+Qwr81Zu6p9qBuB3GkJAeQRryMgmv75rQWQpMVeIZjsjEzpFEtOOcde2ZF4YdVSZkeR1HRy
wnwyYzpao5T9ejZUZ8suqpPrha81WYMI//kZMw9Q9vdcKAU4++gbGZwQKxL7p8kgm2ZZnj1gxkgL
7hmIkffgMSqKSJKdxdm0RLWffhDNBj2v9Z8Md8+VmEdVezB46xq8wuU8ZzDugHtkdbnJHAtcz9Gj
/FDCplO8w4d5O+viR36Ob2fT9q22FFURenF/XTq3Ij1tZAj4BgxS7PHOtDjzkaslHJjaApH6rBb0
/VAcak4SsX+Utu+hJbMPUmigB/AyKSBuHmfQ0qqEe+kcsl4QSLC43hL8SQkYTp9ZcUllkhFKxJ3M
KId9oXfj0AwIJYT6jcfaBsEeIWgMd1Qf1Um5rx6AZK0W7Ux35wosHeeq5y+ZrNubUpntIXCzy473
ov/2uyL4jzq6YwiXD0IrYQmMS8eU6b6lhGSKEdW8Yze/OVTDI0JJCZeNKqEAeZoGeDONXmIaZBSJ
t5sMLB7AUwVLVpccZgW79aKqpFPm1wQn5x1Jb5iSsXrT9K/fzTYI7dd2ByTlqgXY7HUFo2vZjJvP
tdm2rjP3SlYMQa0u69fha3zCcj//Us/ha5h7zZde1Vt4Z8iIfKNzlvh8V4VK/7TtYnGIakvXQUCM
9WcTLec5qHIhZWJ/3xsqxkxiU3r1+0pF2sMW1JisPSOlCu3+wmL9+tTD2SiOytphSNPq2yZgA+q4
a9zH5tptfQg5OO++SWUY3MaRnHbVQYv27JOIQdVHXy+nrQjESzdDRH5/rC2T2OnlOKN5jcQfcfer
gY8fMgIsROo5Fto7+kDY5SOb4EgMzFVRrOXVe/MTHoWaGlHVAuTw1Wv7WvFyf68WVD49FsVPCage
q+Uct3y3yP7XhlVDtxREGATcC4/PafrMtkN5aGrnzLJI71eg3lkRrThG5TKVBFrvvHhobLBSXP3/
L77FK0DMP4HMROeAzAZQWoULyWGKBDQR69tB6kYhwvuHnQGYGiZZ7FLDjoGAtzqzoShDi2QkMJZ8
IimaLwzP385WPcPSNBx1XMwcnU3/Cv4YvOzW7eKcSfInb7sIFDhT4/ufyCFIprHMqt8R8BZRyZZk
++FSmaTH7QhId05DMWsx5pH7/heuMDtyXUIKr+3+Yw3Aurt+Gs9tc5stKCrRVCWIdxCGofLiTyAm
iHemUXmSTamSntbhiMr6h9rBpzUDc+FzaHL+FYy2CAb0LgNfYdMhXDQP0Nh4PCnfDJHJzGZkvrJr
BMUoev1tLQ4OQohgbJn/6l/lYr2RYaE3UhevMJfsG136Q1v2EFkqDzUHW6oGfmbgfCkiFYGVczq2
oeLbW0rx5V8rbYGUNqaEru42RcRp1U7hrelkyvAJJUj4BxTYDhKTkUda8YTHH1S6eR5FI8jzg+z4
dFYS/2+cVpqzgLE109iq6H9OD3z9FP1NnrCEA/oriQd5gTGw+yjn9Eg8n/rzpSFWRfMDOZG/lIsi
FJU3aaZv+iZ26L5XLYHB2WIjAvqwhU4SKKLnRyc+YzRvx7TwgzYcQE1S6swe3OH1X7K/4Ox1RuL6
mY5/xuUnUQrsI0cI+MSYKQBQjMHqblEPDUZqgzjKlO1L+lSYzmahBHnAGOCizIlobAalQ9w+c5Xr
AKmLSAPiM1TpSxBftBqJPtPEzkmHbA+qtBqRGH9xLB4UUk21gIwviT42Ekp5ZwqEmEMWRH6BB3is
z53tAZsxoC3zid/LrTQ5/mUwsGHOK9pjYy5PgpayFydHlOFUHij4fpTVJ3X3+tnQxn8LRa4K8bko
bSlslvFChWOe6FdY8+Rfbz8Sy+OSIUJyrWLX+zbrf/u/+RJLtP+ILSVg3xUlYwKIi5EHTXqxzT+i
EosOIWmm/AOroWWeEZqrDdf8a1ikK0jiyUvemL9FqRe+2glabLekcr1atsToWzyhBoBByyb1gNNj
yI12HJWMocksJr+Uj53KbdaN8KvycbtjpWz4CSCY4tYWkOpoBEe4Dtp78Sy+uuPr8gxVbtvJvzZ2
bxq/Xwd6AP4W6o0t/gp8RQYuWq+rTb77wyck1GfGvruJ9Fqni3JmwmOxqCE/pUJ0x/1bZBs/LAeH
M+VRDDmJl5o4HRMjam0lTVa0QLfM+onzLAJIYHoUDnLhSQEgJgZOWzV+d3ZvvfrskmVN2IjnTxOi
LoFnj7XexnQR89D7W4Cr8j+8FHYABLPvAORe+zt7nsgaD0o8UxZWcQ+eQTxEtmbjJ2vrXeItwcP2
tFssN3QdfUnt+Wy9M+4JeegYe9AFJRfk5l38ZyXV+A6e1Fgq+DH/jJd7luOa41Za5OYSmyhYbxiw
1R8hnakN46WByBXHjA3SqjQ0Hw9Dq0yXc+ZMt8nt4Tixiw8o6l6c240mUI0QubzQVDRqyIobwrAF
HcL0zNuW+7QliJrq/0dOTFyRG2W02bAu7SpIaPdppRsRx30q3fnJbz1fvAFmxxfYr7+DodpHUWM8
1QUHEChBN04NirJERAgksgCrgo/VZ1Zhx90Fz+xi1wQf6a/hfiD0ITH53xy1sLiJs8nHm+pPhwFk
ef/DqdgOzB4eWsGtbA/05aZRq0Qw+dQ0l83gr724qDBsc1OIgaNIQCFdFHUvUn0RVflPIC5PTWdR
DfT0SvcCsHu8RhqxT5jpbYZtoilFBY8Lsj8uPtp7L/UyBxI2sohtNOJEMtRMZfXuyhga9wjXeNl7
VMB6eYF0UAGQLLdnVyNyBJGpYt/HbbOH8IzApWz3fRZqwjV0lRiuzHzUpmZL7CEk1utMeJwB7ogd
A5jnY9YEQDTiiG7S/YhnBxG0EVwawNMhRJCeS8AeKGas1fWcWDljjui/vc1WCLeyVw3QpAoJ9Aq0
RWt67Q6L+SyHs5uMw5mDm7aRr0445RnB6AdKRxCZvfSu7PGiPGOJsDgzhbn+PlOelL50E+Y4RIjM
BPM0TP8HuqySbuynHlCDDrKz+P8sAc3pcOx+WmVHoe7TkdkOMnE+HHyll3TtJmBQ3ZNxGhRQmrRn
5vJdVbHIUl5GNFjZDgqXz61l+g0HPZU1l8Do7n4PLdKBCvvjOs1ZGLs41HdL6LJHFi9zGSTRrwna
836cHAXohbNJO4/HL+cYiv8x13uTJDVkGAoPdA76ThmL91QYprRV8QyFJhPMvEI1VJSLZSsfKgbw
UlVXqV28LYvlwXWqhq/5qwKftP8bFbxcUtaYvFbgfYRuA6ScJw9aUaw91Avia39p90uBAkAzm6gN
aKc8gkYnKSUQ3jh98OzYg+VU22lYYTDd56GC0uqTfPUNGCUiafLUjK8W9KoORP7e/2WW9AINsNK7
9hxE5ma3pLJmYZkVS6GLlpSm1Q8jpRwsASxxb1eevuS4F4CglG9VhZs/8J5oN6RkEbqN1VcEZlMG
RGIgIgEQ4OU9aB1/qo/v0ipTwjClMHL+KHycrJzkhKOs0TW/4fzxoFWKCjhHEFsqv7i9Po/B6Pmu
LDHsxdG44NVxZB3WYicC3zpYdNQqZU4L69lV8py4g/JdFI0uLhdXov+4Pboauj+Gt8ymg4wYxTZA
QqVbLeaLvwNOnW6YtL+hRhJa1q4Ewso9OO+X3IEzZCnzdzmA4LPr/DENrmFX9ne2Hi2ELI99RKRF
3JstgwoAh0qkHdgLXGDoxS3Pc/hOPIjMz9cNpguVgMVqFsx+gobEBa06V8iMYGADX72vrbALgEKd
usvYpjschqagZvaJ04PATlUhnbTa4hE5NnkJI+lKD3hZxgEId20S8uzKEWRP46JELkGBP7onG0Al
vc959v1a6jxdalRJQyllbfUiTii4g+P07gDcazrAUZjlR+/3zWDDsXtAxZkExQkeJuiKEUz2K4Mo
XudK7ZWVk9+SL7wLuz9n2Fqqkk7Z2JIKiio7718jhaQMSgYUWwE9sv+RPCc8yKfwLC848nej/bAg
hpunyylhBqWwoht8wN2O1wytj7jfVs4l+QwjYW0y6Kh6F9sUR6M0tBsKAp85p1ckzciEfkllxhCm
Oxmqd+P6pEvAysevOrT60XRtH7ZGFU1U15wBSCSmbEUIym7FsyPfwJwB3EOawVBM2tSN1fCamY7G
SHcuTFP+BTZPeF9OMgGVC6o23ltKMdAlSs2lAdxfrHscQexWt+C2r5gtNITZdAZZs2+FRhE6Pr77
eIx6CXituJvYAvsGy0L/sZfl4CZ1ZMAiVPmpGxIUUxcTWFJkCvSC8CCycvsszS0g/XAvowTpOYyN
Ta/Yan+SkyZMOXvX8RS92/hf93KsGK2k7jRKhZ+ncdVb4waeE2xHck27coaaDCAuOiQBTxKm4vvh
/mOzuOkZP2l6Sr9ksdPtw6WCzV56+NoDa3Z5wEb5ylQBlUwxdk79MqLEzgOqtJSchgsYulHPbtx8
ajXEZtu/Pi6poAvOz0aTONeYEHZP8PBlP861lcXuMoCw2hoQxvhmFZpmRmYzufZg2LbPYVAKT+fe
GZBvpbgtvG63BqsrSHPkNl3jfTbIxeY8CJg1gnHyK57vQZY3yXh7cR3uphUKXNajKqh1cIY3GQG0
3NVxvH5cv1LmOTlp66DhuW4+7eBOLdEu8DGrwJBEDyHXvBo/42kIGD+Ku/u9F8cLdSn4xRbymAyf
Nq+vTXA/attnqjjj18duF8vbJr6a1/PtmwoF6M7erISVjjZyPrqBu0GSG5YscUcCTlIhf0VaWdaX
2YA7nk5MjnAjeP7l/Qcd8JYVRyaFc62lujXcwFN+Oec8rVpdDNdIuuwDsPMMxs2IukxTCuwpgAuL
aTCJuByXlK9KIN/rtgT9dxDze7TNAvGhaxhEDkRjSy06i8fOcmybaq25e4V+rXyhCVRny847fBmG
p9N5sfzMVSA0+XfiYH1G6s9xWrKyE2EBzNt1uSOguKJNHrjFAGcYvooiHvD4S2YTTiYfq1UmNB5t
oDkQuDropzjJO1ACzngHaJtdGa5bsyUYsdac/4S3Ny0CUMXF/OSvz5t93StVH9XGRcwKwmslL744
xXTlXHP9ZH3d5psqO3wsKV1v7j4sYz+IhuqbxSjcQrvDnglM/jDRrR68NprjKzq6CmNzy9zJREgd
qXiItP1IiaO8KzvfIg0++QC5cjNcXRBEDV/QymSxaFzjgLvGONLufic60WSrxfBA/yvwQDASOaXs
qsjgsQxGnSo9XXNsuyvGUxBP6RL9e+daLgiZH9sAh9xuDFlWIR+K185d3Lix6FiuoJdXjp1JBx6M
rkoDRm8VMgi2ww2FycNaDwUw+tGfef+1bLxQhmYfJSbF7JvJUkIvSjkQ8GF6xkRVh7BLCY6L/9Y7
459dyT8U4tzV019ktEI1ndQ4q5iW0yLp3ReTNMwb0femmdB6mB+wicN0uWhrOKDXhOEYhn0aMeFH
xTqD5+WmcEgwvffOu4DhD5IXOUN5uNQtX5yyf8waWagr6s0Ss/Z8C8R/TDsSC1XJ9mOWct2eLEoQ
phFSqgFiiHF3cAsH3oNSGMOEZ1W8RoMAJ4Ec9NKcbATicXXIjM6jffTZ3UCTBnrR0v+x3vqDV9zd
wt9ddE0+0Y6DmhM1CqtSRHe+lE9ZYGOcTihRi3d0OudIeMcXItpG8lIHb11gS2ozSujuG8/XC7Aq
iP1+T9/vCFn9HdzfsSTt78zOYWaqc0XXa27G/2ZxCJHmB59JF7C8nxSa5baACakL3w0wVkGX4wWG
+8KOh/NvivhheW0wCVstuG+1Q5x3Uk4Q6F4XGNa+iU4eFjv3lSsD73Nw6dC28YM0govhf/VavCBE
nHlKYOs+CIn22LBgpUgPzHr7F/RKuXeGYDVH2KLHYkKxvoRURpZtk4kPmxdqiGkv+wpPzQ7dCjo3
AWraoVLEefzzsq82lc+dHuBDNECtlSkCVbdoZe8VwkHZrmWfpFQY3U1Yagx9qLfQv36wSbSOU1ch
I9bEPDqnOqvBtjo3A5JKVQtQM1muMBioGbWwJ6NWba67eYk2Xb5Ibem6I9wnU0PZ3BckcVGTsOUL
ebD+OWbjQp6It4WGiNbbR+fpIoC3yd0CdZ0M052i+YIs9zQwMSihevpZyu8HLELa7OcBJwTa3IB+
RuSUcK6OUHAQhV58SF4rwh84SPctoODUjRomOVWASz/sRruyJP4w+Nr71fWuG7KuJLNdjunYmoBL
hm7t676S49B1heYNmDDW87g5/uXQofXeEv2dnfUUkhLC3Z6Tsk4HY4Z9lIilGmdvB8MG08rMJ2yo
Rlw60jD1B6s32FNpAMZhAHEEnsGeBcXQ6NUoQkV6zy52oa32uf8OXZpvnx3OHhEKDwe05TV7jYZA
q2S/IaHaUNqknKwJP7ht1xBeB0TCXbiNHh/YQbwaF5ycrNUoq6DjW55NDw8jtrcQbluphpAA4upr
Z/YUXeh6rBep3UkZtpICny8s/9ZvE2XhR7FyKLj3/bkLbURbMgRDNub8ixcyW/X21gfYl1z1ooX2
IvCh0e5k9iKzzRdNCuzT6XArIMfJUw2kkKR31TpC1GepsGMqakOLKewdbYMqr8+Xkm6eWYr7HdMY
ekW57rEGMFrytJDSxN6bJF+HX8yUX5GP3rlIx1uhCA8Xq0sQfgTpDgB7tGyBrLRptQSShdzP+p7j
wEbGDfz0rWS5OExHSo+5qTvQivbAhVGspAffcZxBX2ZDpUvJ2RDf0dTi+DqH0CWTBsHmazHnKbqX
6N92ETmwBnoZVSkszI3MwAlFDmyXQWfife++G3kBeQW6sB6//mFWSjjnguFPiSCfCzqKybPi+Toi
2biJH+W6hfJF4zSuWbprLfIh3Y3ORiST3wCCu+JQTgCNxc6tGUFVltEzWo8x9CL0KQ0gOSHrZMzz
0TuyQelSbQp0Z0b7hnlTNhDYu/jaeRmiLPhC2fZUB7O2MU6LqGKiei/Ivd05P/4K0vKhp/OV7RVu
+wZZVVT8Qe+onYdRdCMoAXirTfh+KyVXwYkuTZHm6GRlglr0YOkPuZ/rNCdonLRgDEuWp30+1lCF
JOnbq7KxOCYgFC3+WFnVbSbPjBHaTp1RjwO1XgMPLbruk6rLTSCMLFYyFCd8mwOQW5wsl+nbSqwn
UDbr8RCPYwV7FltD291E2w95kGnNmnARGI8zLhyeqe2rkkK+wN5fPNma/puO4ilLA9Ks/YzHvg53
fT+NQpLlEiY=
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd | 3 | 50534 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA S2MM
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
-- MM2S Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ;
s2mm_halted : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_ftch_err_early : in std_logic ; --
s2mm_ftch_stale_desc : in std_logic ; --
s2mm_halt : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_packet_eof_out : out std_logic ;
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic ; --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
s2mm_stop : out std_logic ; --
s2mm_desc_flush : out std_logic ; --
s2mm_all_idle : out std_logic ; --
s2mm_error : out std_logic ; --
mm2s_error : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
-- Simple DMA Mode Signals
s2mm_da : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : in std_logic ; --
s2mm_smple_done : out std_logic ; --
s2mm_interr_set : out std_logic ; --
s2mm_slverr_set : out std_logic ; --
s2mm_decerr_set : out std_logic ; --
s2mm_bytes_rcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : out std_logic ; --
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(31 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); --
s2mm_err : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : in std_logic ; --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal s2mm_cmnd_wr : std_logic := '0';
signal s2mm_cmnd_data : std_logic_vector
((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s2mm_cmnd_pending : std_logic := '0';
attribute mark_debug of s2mm_cmnd_wr : signal is "true";
attribute mark_debug of s2mm_cmnd_data : signal is "true";
-- Primary DataMover Status signals
signal s2mm_done : std_logic := '0';
signal s2mm_stop_i : std_logic := '0';
signal s2mm_interr : std_logic := '0';
signal s2mm_slverr : std_logic := '0';
signal s2mm_decerr : std_logic := '0';
attribute mark_debug of s2mm_interr : signal is "true";
attribute mark_debug of s2mm_slverr : signal is "true";
attribute mark_debug of s2mm_decerr : signal is "true";
signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0');
signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal dma_s2mm_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal s2mm_error_i : std_logic := '0';
signal sts_strm_stop : std_logic := '0';
signal s2mm_halted_set_i : std_logic := '0';
signal s2mm_sts_received_clr : std_logic := '0';
signal s2mm_sts_received : std_logic := '0';
signal s2mm_cmnd_idle : std_logic := '0';
signal s2mm_sts_idle : std_logic := '0';
signal s2mm_eof_set : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_info : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_cmplt : std_logic := '0';
signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
-- S2MM Status Stream Signals
signal s2mm_rxlength_valid : std_logic := '0';
signal s2mm_rxlength_clr : std_logic := '0';
signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal stsstrm_fifo_rden : std_logic := '0';
signal stsstrm_fifo_empty : std_logic := '0';
signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal s2mm_desc_flush_i : std_logic := '0';
signal updt_pending : std_logic := '0';
signal s2mm_cmnd_wr_1 : std_logic := '0';
signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include S2MM (Received) Channel
-------------------------------------------------------------------------------
GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate
begin
-- pass out to register module
s2mm_halted_set <= s2mm_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM
or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down mm2s
s2mm_error <= s2mm_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- s2mm_stop_i <= s2mm_error -- Error
-- or soft_reset; -- Soft Reset issued
s2mm_stop_i <= s2mm_error_i -- Error on s2mm
or mm2s_error -- Error on mm2s
or soft_reset; -- Soft Reset issued
-- Register signals out
REG_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop <= '0';
s2mm_desc_flush_i <= '0';
else
s2mm_stop <= s2mm_stop_i;
-- Flush any fetch descriptors if error or if run stop cleared
s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop;
end if;
end if;
end process REG_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not used in Scatter Gather mode
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
-- Flush descriptors
s2mm_desc_flush <= s2mm_desc_flush_i;
OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_cmnd_wr <= s2mm_cmnd_wr_1;
end generate OLD_CMD_WR;
NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
begin
s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new;
end generate NEW_CMD_WR;
---------------------------------------------------------------------------
-- S2MM Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_S2MM_SM : entity axi_dma_v7_1.axi_dma_s2mm_sm
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_stop => s2mm_stop_i ,
-- Channel 1 Control and Status
s2mm_run_stop => s2mm_run_stop ,
s2mm_keyhole => s2mm_keyhole ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_desc_flush => s2mm_desc_flush_i ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Status Stream RX Length
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
desc_available => desc_available ,
-- DataMover Command
s2mm_cmnd_wr => s2mm_cmnd_wr_1 ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
-- Descriptor Fields
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_blength => s2mm_desc_blength,
s2mm_desc_blength_v => s2mm_desc_blength_v,
s2mm_desc_blength_s => s2mm_desc_blength_s
);
---------------------------------------------------------------------------
-- S2MM Scatter Gather State Machine
---------------------------------------------------------------------------
I_S2MM_SG_IF : entity axi_dma_v7_1.axi_dma_s2mm_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
-- S2MM Status Stream Interface
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data (
((1+C_ENABLE_MULTI_CHANNEL)*
C_M_AXI_S2MM_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- S2MM Descriptor Update Request (from s2mm_sm)
desc_update_done => desc_update_done ,
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
s2mm_done => s2mm_done ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag ,
s2mm_brcvd => s2mm_brcvd ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_packet_eof => s2mm_packet_eof ,
s2mm_halt => s2mm_halt ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Descriptor Field Output
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_blength => s2mm_desc_blength ,
s2mm_desc_blength_v => s2mm_desc_blength_v ,
s2mm_desc_blength_s => s2mm_desc_blength_s ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_app0 => s2mm_desc_app0 ,
s2mm_desc_app1 => s2mm_desc_app1 ,
s2mm_desc_app2 => s2mm_desc_app2 ,
s2mm_desc_app3 => s2mm_desc_app3 ,
s2mm_desc_app4 => s2mm_desc_app4
);
end generate GEN_SCATTER_GATHER_MODE;
s2mm_packet_eof_out <= s2mm_packet_eof;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
s2mm_desc_flush <= '0';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others => '0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others => '0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
desc_fetch_req <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
desc_update_done <= '0';
s2mm_rxlength_clr <= '0';
stsstrm_fifo_rden <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_desc_baddress <= (others => '0');
s2mm_desc_info <= (others => '0');
s2mm_desc_blength <= (others => '0');
s2mm_desc_blength_v <= (others => '0');
s2mm_desc_blength_s <= (others => '0');
s2mm_desc_cmplt <= '0';
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-- Simple DMA State Machine
I_S2MM_SMPL_SM : entity axi_dma_v7_1.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => s2mm_run_stop ,
keyhole => s2mm_keyhole ,
stop => s2mm_stop_i ,
cmnd_idle => s2mm_cmnd_idle ,
sts_idle => s2mm_sts_idle ,
-- DataMover Status
sts_received => s2mm_sts_received ,
sts_received_clr => s2mm_sts_received_clr ,
-- DataMover Command
cmnd_wr => s2mm_cmnd_wr ,
cmnd_data => s2mm_cmnd_data ,
cmnd_pending => s2mm_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => s2mm_length_wren ,
xfer_address => s2mm_da ,
xfer_length => s2mm_length
);
-- Pass Done/Error Status out to DMASR
s2mm_interr_set <= s2mm_interr;
s2mm_slverr_set <= s2mm_slverr;
s2mm_decerr_set <= s2mm_decerr;
s2mm_bytes_rcvd <= s2mm_brcvd;
s2mm_bytes_rcvd_wren <= s2mm_done;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0'
-- Else halt set prior to halted being set
else s2mm_halted_set_i when s2mm_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- S2MM DataMover Command / Status Interface
-------------------------------------------------------------------------------
I_S2MM_CMDSTS : entity axi_dma_v7_1.axi_dma_s2mm_cmdsts_if
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_tailpntr_enble => s2mm_tailpntr_enble ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
-- S2MM Primary DataMover Status
s2mm_brcvd => s2mm_brcvd ,
s2mm_err => s2mm_err ,
s2mm_done => s2mm_done ,
s2mm_error => dma_s2mm_error ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_S2MM_STS_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
s2mm_run_stop => s2mm_run_stop ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
-- stop and halt control/status
s2mm_stop => s2mm_stop_i ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-- system state and control
s2mm_all_idle => s2mm_all_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set_i ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr
);
-- S2MM Status Stream Included
GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Status Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to sts strm
-- skid buffer.
sts_strm_stop <= s2mm_error_i -- Error
or soft_reset_re; -- Soft Reset issued
I_S2MM_STS_STREAM : entity axi_dma_v7_1.axi_dma_s2mm_sts_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
axi_prmry_aclk => axi_prmry_aclk ,
p_reset_n => p_reset_n ,
s2mm_stop => sts_strm_stop ,
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Stream to Memory Map Status Stream Interface ,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
end generate GEN_STS_STREAM;
-- S2MM Status Stream Not Included
GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
stsstrm_fifo_empty <= '1';
stsstrm_fifo_dout <= (others => '0');
s_axis_s2mm_sts_tready <= '0';
end generate GEN_NO_STS_STREAM;
end generate GEN_S2MM_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Do Not Include S2MM Channel
-------------------------------------------------------------------------------
GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate
begin
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others =>'0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others =>'0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
s2mm_new_curdesc <= (others =>'0');
s2mm_new_curdesc_wren <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others =>'0');
m_axis_s2mm_sts_tready <= '0';
s2mm_halted_clr <= '0';
s2mm_halted_set <= '0';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s_axis_s2mm_sts_tready <= '0';
s2mm_stop <= '0';
s2mm_desc_flush <= '0';
s2mm_all_idle <= '1';
s2mm_error <= '0'; -- CR#570587
s2mm_packet_eof_out <= '0';
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
end generate GEN_NO_S2MM_DMA_CONTROL;
end implementation;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wrdata_cntl.vhd | 1 | 91898 | -------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_wrdata_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
-- DET 7/8/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- -- Per CR616212
-- - Added special case status push on TLAST error and no addresses have
-- been posted to the AXI Address Channel.
-- ^^^^^^
--
-- DET 8/19/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- -- Per CR616409
-- - The function funct_get_dbeat_residue_width was updated to support
-- 512 and 1024 bit transfer widths.
-- ^^^^^^
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for line 1558.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/dc_ss.vhd | 2 | 8726 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
CQfQuP2Vn0fVR/euDVNik1h/3tRifR3CceOPQ+YpUdgbrk2D99jxZBBiDIC1WCbxbICuTMnSOkxs
tl6DZGvUcQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
YGuCIWMtB67MkBDYpgFXoAAKUu4hfOKbs5bs1+ef2Ug1/Rl+pwffP7EKUItX5BCuzRhBGpl+JqgA
77NtTpH10Crmquu+f9QevyNBxEF9TpoOL43c2pwjXMRdiSudl3dC8AXZOm+5obMh5OtSHFPjYDpP
yNWQ4292/idiVxLUtB0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
2aHoySse40a/bZE6BifyqNy/KcIhm2NQKRBhKBgyjxX2mkmpb9mcNariDBBoGgvH38NSHWySwiJd
i+GSKkH7dxYflTLCfuyTnP8ZsiYFcHA//9FFx2QbYwBFeqBI7DOznGBerHrc4Hzvfijuzv3c0B0R
okpQrfozDo4JTHZ02lJD0d+Mk8xb2VctbK501Mj1l83aT5SCCNBzccJN5ZHUAYlOYt31Xi9fDW+7
3hbdKMvLai1A6zFGc7o9jDqLLsNWUlavTrUcWpQoLBg2lPSuCX2vKtD5d+vUCGt6WVtoT/uVfWTM
C2u3zzu44fgm2tAy7omdt8/ZnbP+WQH+lOXEpw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fw3n275XbefQcdbu5POSbgQLcozakyeBmMV6+h5ErECHWWOvDHlhCf7UinwPb1INiaOD2FEexoSz
ZleTc+DTFxwf07DTZBBp3zGdGzioWWx3xk+KJd8SA4USD9Bn56phg7gAp4ayKOjRWoeXOpHyEQgC
FoVkkysuOkpc+fbv96o=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M2FTHOLS/7bv/XVJi4IN6E5NOcRefsKFmeHh3B+hewN0ufjIq5J9thxbfHrhQ/qY0jtP9yCKiZC/
m4+cTi9uzqhOs5BszEuWzhJ4W0JLRe+bo9OddgTlPFLURMUM/10v4+DhBFRwn3hXW9Tl3kcRN39b
lDpTaZPJuPDsM3xPKGlv7Jiip26BO+dWpRoBbDCHdIT2N02VE1lryhUMjC63PD70dSg4iympvsMD
0lK9oisDo1y5mzYJNadvDSzNwUrP5Ag0S05l6gl8czSXhojoat0xUHcdlxL3c12WdmM12oMeap2D
YyQ7FmgPvyvvo/wJHaLORhy3uTiJLUSheN3tRQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
8SrUVsGkf1GdHn0ifnyi2Jy4NM9wxXxHdP61gzVJflibqUrMJKJRByJeYw/qQ/9ZL3XkTjMWNWhs
ioUg+j87MEqJGdSUPD+jdTGAsEw6m8/CgoIukoD+SwJxfHU53J1uHaadYKz3nIvT5IUFsVoU2hOn
I/N2lGRwKPcmr/1KxOXmeUSx+HZbS/TAeQX6tvTmJdTecoMtPzn0yFeh2sz6dddbSji3J4D2f1um
BBSvWpJHWqrfqtwp+BSygcc2oFzlNRLck3VNpNTQgrG6p89vIf3QySwygjNn3CIospMs3blHp8Ax
bk87N16aN3Xh4BzGL9BDZ7rp2ceXyNnVbYLcTC3ppaSeJ7sO1rs/E9H9nHmMvT7rdUcjPZKBnwaJ
YT18ZO0uxkJPRzhu7OA98t63Aqh2pZNTsCAOdHA/AkFOdcExw4XuOV57ho6OCifThKLS8pOvMUOT
hkNG0G3WHNjAKSbn5Z8VNBTGoW9avvSfgmMjRr4M1Rd6bz5WutumSMMcyverZeJZXrSSgICtPzlE
/y0ZdmojXhf9MwQRtfRXssYyW7xw5ItulpcRCCDIjDO7PHVgf4W0PrsolRVTLJUDAlyLwxM7SKJm
HwojUwPKqoh5y6nwC0U6gBhWZsD+/cKo/pICV9rF5ktqev3bkh5EHAzQGA9QetbcQjoNTsy2ADgp
GaAxOtOO0EB5KSPqc0iWLdE0TCgal46twk7x5xplYEmmGA7nOi698Hg9DnmSel2Zxijb/R+1L1zA
kSP8s/lLTbEMv3qLM3WhAsbKOrY8CCmo640F5PGUNLQREowyISrxbFz2e+1rCJZVh+TfcPRO01gC
l0mMozoT28EiOByh61v6nGSzr1EuRCZtbE35Xv8jEpB3VvcER5igHpnGrAT3q+H9vQnO77w32qe7
Qii2Yffd8Hu+0mjE09pJj1XnQUmVsF3nOlDBg54oVTrDRobmwmPlos58g3f8YB4T29nPFG5Wk8MM
GkkIrp7QcPf1MNK1r7SLY4VcDd5W8f8uQKwkDr/NzjMNHaeLwsOEtIfjHcaz/59OzJCTzkRlIIwz
wIu5pkWll6Krg3jY6fSOxy397ZnJyLaxxyWCQOM19HaAmfWBuGYQ5ussXm1b1+umV6ynaZ9KtFrE
rz6OV+eY4RaQuCpnz42oSehFdwqM5/uUAYBvxhKxfsanG6j9xA+bzPnoLiLcvrHAnQObKgrW79SL
WNTMiSt09yWQwXkqLKjrj2scX0sgm1/pcPxaJXLT50L7swEJtGjEm+fW6+LFIh5NmBeP447MlqTY
5ox9B5kUqg+9BfC+Qr4BcqKpUveskqttYzFVR3eAA9M1B9bHGUSNClML6lgLh9kEfAOm4uLJAtJa
vk9LZcMUXoEhwcdgMKQLkY4fLcyfRUJDPqKiaEMSF1QF6MQP0AZDbEcNE5e9j9B3/dVkuBKoYwEI
HA2r9FxJMtFtnjSBz9rXuDjyCaecGZ7oaZqRY6/FK3Vbm/NqvlBbA1/xD/dQi+Eyaq8k+ru8LiJK
42PlZV8XVmeIeddygla+npNjIvWc7endt8Sil8DsFGdxayawVvNHaUaJ/W0gLqFyc0W4Cip7dKRj
sStrJPxuljbwLxHCYPiERh0b3ncdwEBLSDcPiJWwshTJdxIVsMDGmPqEmHgovPQyAnnmHBcdTuDL
0OMl3G8psSlCYNIS/grD3y0Y3jPxCA8Mmr6i0aYnvaIm+i266CnkAI25LQh5ZaIaH4N9TajF+6FE
a6+T3Adx5UAtmrCYpRKSIDg0zana+TosAv+UAAGDYzq9XiutQZnPawTIlqhzcAxzXEhUEtVfJhko
/BeTJHiWvasqyHIvyvIkakhX/B3AaXFFgOxsTz3zNIC/yezH50TyfLBgCsUhW0sZVreb48bDSdyX
DM+FjyRL/Ic+jeqPN7FiV+geUpNLbwrAmD4Rj/Rp0huvzihDLZ3GnIVPIOuMLE6Gle2YM+ze1aCY
86ZiUcix60ODIy/6MawvendPIedHjYktqTnUx+EzAOio4M0thJSHtYkr4QX9XGYeGKPw6/KPU+Pe
5fYtUhVl1h8TDr5/YNh+yXu/nNlUPi5pXP1vpwGrTv43ACZEvihw15cvqvbTGUvdwkpZIia/mrqW
qT2mKzik1YjF8ed+Ww8fz7lYezT/rX1Y/dft/16qcs18bLcn6zMeARRLTwyx0uj9JLSl5ndvwq95
bW2UykweidnN+8XVqtSZGy36yWBHEMiU3lB930C6Arx/vdridnZActomX+xFskQSD9BaaRqvlaUi
UyXBsAGPE2P653LoH/NxFGUZv6QV0R0/u+Dik+ONUJdiJgGM1NQhJ3M0GUE7udN1CJ6TL+hvSUr3
/9YMmQ2kiJLZx84oq6Yb+S9qjiaKtXziB5c49xGCZEyCvOhRT9zeYeHIWmSl+5J0mJipaA6lBbnO
eQok99W1ojtTmkSKNs2Wk5btIO63QQiFvaehPx7betpXQDTmn+ww2evWjV26+VHBHiBPO1JrRca6
Q7a/g3cGkbeGHAR+TuTxj/iu2wrqJNEkUj00/O2CkgBGZtnaaC11Jb0fERToZu7xs4ERzoUB0+6v
MmR9xY/UtcuUy1XH3amUtnWdpVs5bAM1FRT5Tn3Vwn7dCe3Ms0TeiAMiBtyNNQVuNIqo/Z93gRLZ
tQZfH7dfPnsxj6Td0kWCZRWDeryYOTwNhTCuFJyzhKBwt5oMV84qMD9GOb5ASdn7qnTIkxvpfb1t
/VF1F0rJaNxDPSgw8oWn71OM9ud2VBou+yz8rcXC5aCu3AoGh2U9HElONMPZQTNrFPg3mjknvtVB
4roAorLGBrNrP/rioNlIBzau4DeggdaEIAZIwEPEYY+o2Z46G2NbFgtWNIh3v+oTGyUsjd10CXMU
Ai5yUOv6MIFZFWt6ZmzcKrBvcIICevjS7sLIUCJTXdnf9V25UCpNL4xWGHjOi8TzeyCyNpL13hzi
pETX1QmtNA3Ocxpef7kE6MYAMlPGuWXQsKJmydUPZsTlhtMRSqm5uUigqPy3PTxby5HwlyT63wx9
SGLTH9NmmngnwZyvbwGJkbXrE+N6UxpwyZOy5xWM2/nE1vlFW/Tn4DsSBIidRNfGijcIWGK5vEsP
dAEcYncNW+Baoj4uehJnT+jIoeBIGbD3t31pyJ2CTMeZ8n6p64wS+qVt6wODXGJRXLtdH5z21KGa
iwbUUvc6fwNYj0v1c9U0Kp25EYF/bRYJXc44cRaJJ3MB1ceEPMX/uc8Qt65/YjZuNPJfNydqBOpc
4YldL+IvqRPSr2XEgCeaeVkelLMyaNztgE3PFt7Ho3p2nD5+SmNSMTvNtc8xHkI72Of0IoFcIrk+
u25MjpbLoZEW00LgrKSlutEC0vUzQ6vV2fA0JswIzBcXPfiEweJZNHbsFYvvs3wuhluX1+NM+h/c
9XIyU+YUEfQdI8Mqj8fwT8JqhpG5bbuFY8sPi6ZGcLpeQDvgUgzuHoczq6Hl4dutw0I+bwnd4LBc
PoJaTMMf33fEMZ+cKIS7xbZdfoTvcd8tda6YHmzJfkUydBQcFgThXi8bv/z1qpxx2RyU7FXNQsPM
UQbzrtTJJ4qm04s7G5zWpufwkuVdo4sU5+9R4SFGNIocqHFn9srIszVMEFVJf0II8BF5W56y7v99
MbjzPnmdimdR8xPbcn6Y5VzQfYI7TJ7y5oGllSHofVVeadAYzl+u3jD3W8tglSaeb5QLenose7Ul
FibmGJZZ92XpgNGo523nXX5DoWehtYthcsgUCe1g32pfbDODhiUfedHdwHOzlvNCygqVWeHsN2bp
v37sAKZcA0vNN1sCGpkCuQbM7bkeVGiG4K7l0ivaHm/oz4ak0Y4Gh6mmT5obbWeMWGUzn6c8niEW
+YftDBq/9fsicUKqIxhemnnFbqnlMZeMIvatmLXOvjrjh3lMP/0hj+UnTBJAdoZNRg4yKT/9j//v
3KVjZf1ANJWsm4kb97Jk7kHYo1INTFdFXOWuccJaJJ/Tb1Sz9bM/Z+jcwL/ViW7UwqsOQaxe8tPZ
rtOoFgODzLXcABv8O4Mif6jijnQYEQhEO1fJoL3vvQ5U2ITGaj9IYYgLFjITgms11LtVlaxFXxxE
/IjAIiea2rBIYbWEs1kV/1usCC8MWOeOK/0rRrPmb96UP19WpOyQ8wSw2ggc+890NjmVfz4txi05
4JRz1ATEpSKIepckRwDj+61pejgAmCpNBkxBkPZy63AfJ69s6zYyJyQRm1VyYHHztu5gfQc5hxXt
pENZlTIc2ALe8tVqOjEvgtm9n1rUXdbSsosT2xL5FcgFFyCvKBivMu8EK+lh/3V1q+XB0MUpqqda
gyLA4YYoTEItda2F4qe+McUVpf2r/aH/5PMDiKLJRQ8Q8DyUpxuHCwChtV0+BBTL75nkD76ah9EO
tYij1ODBUnChjewb+24ZwFTLSCdJMtov7CCq8jwZyCewRviKSVz9Qf8XK9WZ0cqwZE9pJKN/mMYC
KtH7eex+6tk7VFfpiAbtqvWgqq61kh7FT+xcttMbM0AFpPBmvVh7/v7aRca/aw83ELcWDZ7iJDjx
swW3XNg27hBHZnQ12zwLllDV4x+e7t3CVAfOPxPuLzBXsWbWt9xSaRvT4nrfc8E0a/oV8t91xq95
X1Mqirsv7zGTubynGi02m8tNzFwgPw9/dIVC2eUhzhFkywIF7mqyiBDR9CSm6YX5uaqXYJikg5Fv
1A3rR0p64tHHiUPWpXlkPnPeTmctsbUdP5cfdCjzbGKezPP2SdZglGxEaZWXVUz0xF00cL4R7PqT
b056lqSEFhbYj82W/IvNjuJzTyz/ReBu3aOkHaMjwK/c7gSPb4iPmEifuRQAl8gzKOV16SdNbMnd
MPDR9BV0mZweeY0j7S2TI4gkE8XGtT62/ve94lltJyjOR5fM3dvwl0bJishBDr0I6aNQWBw3wzgb
jnDFpL/IkKH3GrrCnjxyGdGB6ytHvAQ/plBylpdBkY7xZMkIYFRhFlXtTSeDMRr4DLbDtv/kR4OP
TvIIVYF2mLCEZkO3nub0BmErI1RKQbCTShoGf/1UCYf2XjwWVWxrDVrODbGjtOQhSESe6B7kCYFc
A6Rutc8n9ii6QFtLXI/7GgaXp7rNuTTEmcFe9S7x7yDsRf9lM2OMC2pyvaa+sRy76U9JhHAiPFjo
UtPOcq2myaa6Q4kdRrayhIXfKlvw6ivg2UKKLGTlJLc/qPicnQJHuG+uWZ040hbupyTVAJAXdSdm
tX/X9ZmDEpl6UkKf0U21qK7x3NLJzJoygl1z4tZ9Dx4CZ39eYFnoptVKJg0CWkOSKVBKGkq4ny5r
lKOCK6qGy+hcv41vH6d7vJTsNnMo9ZN44Q0cs9F5TxJgkOcP/u/xihXdCXsJYLss1nV2Q9A03VdZ
7Bg6dDFSi36Lm+e32iuObcZpOhBVdB8O7L7MAEehYeRQNjifgDPeTTfTf5u6QHVICUM0D1nLZ2xQ
Icn3oxaigiEI2GG02XP2oPsVtkpULnWsm8fOuX9/gKSzJgqC3ehuoZCZyR1mf+O3GkHZkwDtolB9
XebMVtyf26xI7A1H29jWpxDHwhCOxCMLOiThwpzXgG/5giDKYOfMc4JvY/uu5vaukXzyY3kiZCzK
uhLmIUNSLzBD9QEh9nOVaHUBYvW5iDBTaZh/4tzExitysib3Ti/NGYK6JkH/pAnxjf6DBxZArADo
xZXtAfEHQzsnCp8Hj2hqi8+1PkzCBU5REohpuu+MHn8nSlwHxEWtwCVrtyeZulD69/K+4Bhc8vcz
U61pLRGjMrEC5/cQfU+K0RorMLyy1qYmvjVFhs+eLWGqHTxfj5ETmUcwnAwqxsGiwqv1fxI0A0J7
oqEsxSwJegKFtcFWZBR04s88nnppdYb2qVZX/IEIMCut75OJpd2PSvT4tMWf2AntkEPKnVKSO0tM
gHDU5QxqHfFDMJHNQTUqcflu1MMQE4ka7JfRA84+glUr8q61/0ueQePdM8jahVjC8MV8C5+gsuG+
+TeQnuD7YSauvDN8s8pVfO4k2VfCLpoRq0Axuk0V9YHlNlwhRx1VJ5ntCtAecl0ynAE7KjdqNCGz
OdQjSJlJwGHH0pUmNYL0usnLNiwazNFwTHwetJMXqzG6Xl4klwt01k8VrNgEIhJm+40x4oZDlNSI
gosSMjoiVefKUa86xqnn/mgeu8t4c3dGFw+ZVCxRUjJYSUW7g+4gZ/pm21GZdHvbx4JEBcB+EzAZ
ufC+wl0ekeBM0I21fy+1Ksy3u4q5txC09vWYSRB+Ulb6q9+hJaQsArmIKsH4Og==
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/fifo_generator_v11_0/fifo_generator_top.vhd | 2 | 34425 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DjXQaT9F31fosyYRaG1Uo6gZbVO5OGjdfQCr7Z8lo1MZiMNDhSkJCmCyeLNV/JWpbsAQpXn1l+Ol
pqNHN0F3xA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
L49KGpoY+h+5aedjMscH+i9cQuDk2QKC9MmUqucGo2R5YyBeGt9Tw0IFWaRHEx08BcROYJiqz85Z
l45DBawZlWIgF0nxkRm2dBaeQj4yFlCz1DFev36vl6ocHoJYZQQphtBrOjUj2mnGvrhuEfBDlyrA
te4UYLdH6lmWVhIwEuA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tK/Oi5gCl1vSNMcN/hLovMhIIH6YwzOy22zSL6ic+G2bpefi3iRcYlC7Gh9SMATxB776pCi/Tk/H
b8vpFjFlBI7/vr05H1tbrryj/LY+nyhUhfex38l5B1WC/miIT/PpuRgm8rSmgKv4Zs4J+3CLg6tL
2Z6PrIrVabG4loS3jCUD/HATBguaKsur7K+35CP1HaG77lGi7m+4Hb148sBe4Qzipr/5usk12apt
REYy2P4U28VjP9cGJtZoNC/68tRs3ptkSxyGrkJjWUEgILbpbav1XRpIlyFH+K5MUbbc1HumdpE4
nGjOK+7qPAbQiG5Se80nsdKHj8Jm4Js7xt6mtw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
wEAV6gVNHHl6St6UNSFN0mvO8pJIj3YasIG6CD8hRLAedoSDDa/qJ1XQI4O+F7jk8viVcdY4zm28
L7qtWlus4NcAenl0RWiQajqfvMh4AU79RzNQQzn4lUbcOPvueJV3oETdhhCyRZd7693xPDWDtQSW
q8HVqGQWMsM9l288okQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tbYL4pwKL1+pNF+qGjYtGkK7cdc+MKJbywWyiyyEHhv6+ueqcdHTSWdLK/6IZMKBVQUY89qmzRPu
LQ0aJTDGrB8dSSZMu2/EgzLj6bR5aWbaN89gc8rraR36tC3YvPtlmoCFv3q9nW5PKcBrreTP3AOd
nfqeenJHyyWjUHu9XBWcR+C2s3Ph7oxlCs8BJf37Y3KehDgdrTKJgx2aJ2Cpzx5PrDb61BGkMTi6
hM1+bLmxn7InN/KUbAwqKa1DFXUGNIF01f/cQu7dInwF+Pm83xnjLOeFQcTHKc5XKpgSrprQzr0B
0vPPPqjnyW4PxadlsRIlxFpl2iBOUIJITf9qow==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23744)
`protect data_block
4epkPmYNzN5HcAsLautWBgziTa6wcSztWoFmhIEN6ws5vIVhIx+DpWE8zW98Mx6D6JyhPDKMrtJd
FXuhRsHf0LGM2xAuIacv9UIAGEPID2NwGt+2JtK25uwxonAVImXJpgQ6ZDemJAh5H1tGJuVLFvy3
kZ9GDH/ngubWOPmm/yaSb4vg+8N11/DPA+KNMHflPa1wdLDgA5sddAWjckrlw+CKToFTsYPm//WD
H3SwhX5ArqyvE4hS7jee/gqTJxT+H+fay+s7IJ1vYwUaywEMQNOpYhDQsLjZZF3mYgn2CSYXOZOK
jiic63yYLhhhFmTjWBZhizJuAy1qA7KGQ+wgGe9pDflMXE7tSPo5Vcw+bW1je5Lw/L/RXvZAHUkW
jGHNpngW/BpdE4wVHyEyUD/rlkV4sZ8PIwX34yecYAyXTN6TaGjMaCmtdpqfSjcQQ0WUQ5t0TibN
WmZbwM+5XYXZHGmOLvRo/E2KnH9preFOuxtktWfQQaWaM1lgYVVUUE5fPzUIz+UDZTJL7Hgxx3E7
ibXPhTX43MLb543stjxNvAdNzQ/77oj54PkokOWlAiNPYZr5EokYF/rIy6edWm+T0m+VPoM2YNAe
HM3+E5MqdGpYB5w0ULg+Kbaoy2Dri9oveHMXN9XoDBv81pEeLF6rNxGaXffLVaOpnt9HAWoW4EIZ
OaTO0HgH5KPcT5YQr3JI3GbqCkNKu1eJ1xnIv1sOi1Tvf4v+8U2DTC1EdUvw32baLAPGw1u5fekf
b0w/C5iUg2feVljlCcJ+3xBiOcDRYdybCFZYcZpbZg9uP/BW8vuNvmwAsalf0plUPZYwTfBNTrYg
+y0p9NeMjUVyx+Fk21CwGmeG6Mz1RMFFk6TSfz4x9p5PsclcCUbx//8oESC++RlfX4MZyU/eo4vm
ace8w8Thb5ItxA5pqY34qe9JKdw3k4B4eg6KKkRIB4dDfcSgQWPbZJ1pT9g0Se1UtA9aXtU1UfO8
h131KQpcY3rnNBLRmSggef4I+38uNFDVnRPUj6UJZxCnzn4pP8AJflpbNF/k2m4Fcmb+Uq1kmi7A
z2zCnBcOwYg9yPvEmXfy1SwpEnZyQhQ6JLY8hLfR2jZIFAIPaE88/xozEwXQFqJP6WSNZfQCHBVu
vqDL06F4TFho3CQxfbj7sDYHAi6vaA3Zf+pM6OdFG61bsTDxVG3xailuVn7JLcCTsm6vb5dduk/C
0jJLshef7GheXMwS9xNGZ2q8cJuB/GukceOentQIfnS6aQ1tU4HRZ7iymNoNuUZQcrYMZOMaZ9eW
E/1U6APxSy56S5DUzysmkeGSus7IxutTJwBLdwsnj0VYULQnC9agLOeTsLdn5jvciKW62ieyy5rK
bnt6OsTIm+8CZh6rn5y9P4+u999ehuUsnntOrvcU8a2RcuY5/dsyzc0/kRH9oqh8C1Ko9ssCZCi3
/2tDtup4meMJPJZZlWGaswoI1xqFZYrXOBfFUK8Y8xgjrzUjHmg5FkiJKO1w3eJn4or4PtaZfzwN
GmlbJ4pTjG90/HP1IMRGzrJRDNc6ap/2H1oo2lVKxDBfz/3WCB7ee+SynOtlNLSXvtLjAKkf1Iuq
ayde0z90Ota5sXKnhWPVtAa+uhz4ntH9FpMq8cYZ5zk1B7cjhNNcF9tO+qALj7Fni0oU45/+OKJQ
O3AUDSPLc4xnqxs6OM4FFAzpnpmsg5iUnSvdq7E4H6LHgXDxEWd3PR9he/2zxxPFcpki19XqPtBq
XtMasensEtJd2C23NNR3DsqfaCO3dGxCmD5ZYLRjutVKBLc/e1G1ZlzmgqC5vvEJ+yvSMazUATK3
xXMhRTmGrxukFQBh8z6qE4EMRakGiQmE+9DuHR7OmbvZBD0oVfMEUehxcL9mKp0lLGCIolWJEPob
B91zg9AFN206vK1vct7h60giOe8S1o21XW3BujyTONnftFXFFQ+C+nMtM/MKoRmRnfDCxgHPqI5N
7UIgcag3pKKvtZhNf/9AlHaa0JCjyPUWPWQ5omBbcNl6c2f3rsmP0tfIIM2nMZ7VJpp5rOoCN6gE
xqHRM9LHsDRKOnH6w7gUOC6NOU0tsyfUD3lQ+zS0Q+dCVutrGuStzgD2XubVshwsHaHKhVj0bb+X
kmn89hBtERmEuNamE0EZTodQahMc3JAM1qkrEShXFTF92moqrJ73qloDqJSrD8NkZ2KZDGtH7BIX
pkJtDDWIKsvQBMERLqiaIzp40Q0TyJUQUQBGOruuF/URx6iureHvLfiSNy/uf9LTBqnqLVdCzJc+
4d5giIyWQTOO8VQRBzQX7hlQChTC5sxHuNoPortFBbPliXT/hEOgYDooZYOnL6DSc4YHwJLa74WI
rpHOZHdXf7/GZJQ9QcsyRok2gdqyXuzbDYjfy7nTN7vUv/fytZthQ3ShmQ7p8+j4Er6eaTpL5VHz
rrPaRVvqUu6CKhXAdezkmmN39FAgvnG2xKVkri3g5Ys5ENAgkrcj+y5k/4ZvI3Zhh0gOXcKQO1KR
cCyND2G75eT60qDfXwn5TXb8zXV769u0VpZ3ix4WGgz1Njye1qhc6J9Jao+C+UrJbAu+WMidspnu
VQXnpKyZWIZBEALR5lK92j+4R4aooThTrMMCanWIi96bWHJtAK5fWhd0XzOzrey9OuLSV6wASIvm
CVwqfGW5IIc2suLXi9CP8XKaze1CTdE/AX/l9STPDcndugSEIy/tvpvqw3WHMju210yIR7PoMGrz
D4ddDZktalJLgSi2D6N/3Ttf+DF358A5aAuNO53awskMQ5Gt7usQgbzrapcfHdd3j6OVgEoGm6W/
LvSGBCGNQgTGOQPplxSX07WyL17Z3M8eGKNOAJme9GunBAKvF4ibs2VNlDCQFg4o2Dqy4Up+riyB
FRAXRoRQni1Bu3aS/gBhbZwjJWBfhc79MvarmAMtZqC+uBMB9Y/Bd4fWkODXi9RB/BDq/3oL1e9Y
AW1RYi7NV6D9TLWI0Eajl8tSGoa6W3/k4lvXBcIHCo9lpF/iiJ97y4+0YBu55qibsn3XDKRq4vHF
kBYRyVUERTQXF77R4KHykb4IAXe5DLwBQkcsj4Wx2tLAlM5WlGMKvAJ5ndluiVNuaz3KCLyMuje7
umQEErvfDz3rRXBAvJSsjtAfZZXRMcx4mO1MhM/D4RVAopV72ZymaURRwt3FwOIta7O/9DT0dkY1
5xdIgDUDS99L4Egfcn+ryJtWmCyOlbzb5EBFS21VnsvXDmv4Xq3KUzyLWr3q5utXn00pFFgop6WO
+pqpa2Ya0Gn+Nr/jOqNJAMY8674+b0WIt1CLYtCXPi/YHbdcrvAafyd4scUZ0geJyO9D0ptA7neQ
Xlv0EWSQRMqxp5DaQY2Irsmh95S1bjuvEXQpgFWHmqiEVKOoEhB9EwVaEdg2n7AbRQkoL19lh5bz
f47fF8itAqFfFIqoeRDInKLx8N/HtPGQA4fw94SQ3B2+R3xpiin6bBmxCZqJTkGN4yUQjHpMsXhE
u0u+W5D4rF09X4lrNFxBdC6f3kIzm84Ez/BpcbsWb/azkG3GI+laUPSdVr+1SyOhSdqTiOlgJnOL
/jIWBCc6P5aad95IcPNrd8kzPssqFlg42xwVR4VY82qEEGadB9ybZZdQUZuZHDiMPJwRFsCkMhHk
SazNZYyRtzwJBAEFWlTJRyTDLDCcka0TI+R7do1y1HupOILOhdByHOI3FG3lzjjR9+S0FpkOdLoH
xwAa1KWrWzPdgDeysXTeHvVU6X8N6ZRfyLEMaThBZSudA5J32jAqFm68eg9cq92d68doFrdsj6Ow
sqRepG3Vek+56i9ykAThpDazYHrX0jv4ZadPueXjXD9NZEQ50JapKtSTJWqTEcdKcGQLuu2CwtBx
d1JhJxMXKc9rUAfzzKLukIyfdbmOSF2l9if8r7iSHHkIR/Akcw4QwWmBcqgcUtw4j2H8QSxiIwVz
IOqlDSzHPBOhMrI5GFfylhn4MVbfryzpLSJdXIgXjfWxzCsQ8qL8vxkp8aGWp4CXLhyEbzuk+aNJ
VdWTCeEsSWfer9Fti/JofE8StLccL8KbTIbVnM6vRf1lRErRL8+MvWFc/Lwdd2FXRKyIPgE9qK1P
LHowgt1AWOCluCoJgjIx272qDSbNU1pauEfB+f597WosWcfz5Ni4vzEtegjTWzbZro4irKt6ZCUv
Dx/IsNN5QVixO4sD0b3xjMZ0Ij0anIZ0GMvYr0qNbDZO/iGZhezB8q7wyHCleSxKQdXkfSIdY7PS
Or7v7JhlTW8vxU4bmjBdbSaOFc0vHNNLr0609iRhM62/cz7LkAYo3q1pMzXrGK3oIy9aZo71DT/l
9QiSR3jUk5hoB1gCbaUbavSUOAVPhRdY1xVu+FXtIzEqnwa+WGS/OCoIy2g2kovoGKElszGejVlf
7QK96VHtr84p2P19N83Vb1M+iITM0+dgtXq+FEjQlN7fPfVr8vCtKhXiP7yCpVvmy+4qxu3dZGsV
DjZzm+YX9v+vFdRfe4Lm/Mm64z+TZs81WAmk6HRlvOk6VWa5za4wr+RywyHYehxMybV/Xtqmuqem
Xzt5zIgTxzKzTmQUY2sa7tKtfIelKeygyaHT9s7yzFcpOzoaxTdu6IiH+KtBuZEQxHSIpcq35EMG
VZ9PUoH6tra/1fNcZkXVgIGuPkae6t58O49citUtjqnf8iSVEAa9rMXiwZd5ttmALhwaSqBucjOw
nOC963XVH0iWdOfXf1phR3eL9y3OzL27qHmtr9Vx9xqOTCtSRicDltWYlMBmUdfqg5fjHGMJUWit
BVMYYnrV5mEWB60pNdrrExBwHIqvEWmo8B8FZtW5pdlDru/cmr/pd488drjd3Qo3jBwvbBXGAcs4
MdgIW43pUQ88AVolcRq2SX1GXZabEn+dkts6fDAFS/own2pW+0pexcIJa6QQ0V05j+hkPPtocxji
vt6peiwdkQCseS9hn7iJzzNY0p5TU/bTovxu2Dv1qHZubrrXtEVlLonMWunxDi0zmHsUnNjwrsKG
CjDp5rpL7tl+QfZvLaRH8Yd/i3K8gZe/7WAOq68JbMrey/9fPaLAs+fja9Dzj3NpYeJ11coj1fIZ
Hnz5LF/+sV26vU0YiexNSBLuXRR0sGnIWakMTI3imRzeXZrhgfIOeYNvTwTrVwYPKIe6qd2OiPR7
u2Lhs3cv98BrvSKt2FSuA0B4x6MCBryEUXBR1TAQTPNwNZXI21XI2w5ao2aNhfsEem5ORGsQOmfC
dVUfP8LTlp8luydfM/WyJDsCkItgKCh44EMVIgVB6OeqThnQrQ3VKPEggNLOBlNqiaTDD+Q0IEvU
XsLjYl//MxgmHcikZC6oh3bo/mAOC3C6RKqYU92fvIvHqP8mCZkD9y7AcEvfblsha8Dr2ij4IM8Z
lnFRQMhC2Bf2eg4VZ7UhVn4/+bXObA7O2H5/tLyuE6F7Lhteh5IhYyI3IHYc17l9rVfdvCXwAFRi
ISOkXFBLQT4u+lqi9MZrCtI6W+5dE2y8xbJ5SCp441G/WIFnLmC3MquzcIWUMJXnUhEBNJ4NFJpY
benNhHQWvsNlYIJ4nSaS3R0jpndHroiPz/hg2lDw+wQYizOZTaGsg2+QemKzAJdHNzAonujLJTLK
I50JaGJcWPIcKloI1u+J5BgW3fjpJUXzTUeldsBUR9PA+6bOWh34BKe7T++MGLCi7GRR9TyTxhcf
rnMtQs2AXtRCncitbmBm16CZTFd1IxDqNFZlAFE//58apWxd2UPMoSA/t31QkiGf7yYHy/ZGxrvV
AS9VvOE7w+6MRzzeUkkAiAHP972QVLV6ikZQ7tLTnNs1wnKlI2GJ8SChTfn4hYBemPKmVrussQBb
a5x3ip9fmM7aI5s/KiMljrSARRnaAuZKhMfR+ySrRnYika5ClFvFY/ijtAB7URMhG2BfIL/sz6wl
qDXV2Ar4nHotgbEJAMcA+rUYo+poGKVemNjEd/IgV53MD+0bJLl/c3MDRhx96BiqOtqCYL/DZjMR
XYAXP0+t/juudmqJ6ENICtRCUFeU53Ruu+Ok37hI09LTUziDlaeyokr+FnacTepAwcZbHn4UwM+O
vliYWjBD9xhbu7+5elS4rrtoUtxyf6W6w5uG7IXml72rVXB51zs8Oek71cJG4aWV+CIPfSEEgM8e
ib/z/DH8JWC9IDK5KxtJC73suE4wUcCktdY+XAytwNywDepzvJPa4tqYC0GYSx7veFAWoCqZ1kbl
5+j/kT7FUhlRZd5aaRNkhwM7UrPHe0z73WnTDBmjGGNWJ7Gf8NkOpMqg8FM63IgFyTFPZyBHVxdt
WrcN9i7ItpuXCBhOFkp1yLFSP55cM0StEZDCB7gNBS+Xfc2W/34OfZ84RjRQRIUrTlJd/gxlPkx9
DH5gM4gADohxc6+dMc8HGn7fR2kUAYJr43JZWYUjCS8Gjf2kzrWZ6qxmzHwTcax7n6KldBY/iv0P
MjbK3PNLkGxNxkOvJ7Zr5MDps0rj5NdnyMtNpc+ctIJduNr2P1Uv1zFVnOMbe3UY973zqsDk0Scp
99xVqK6HypYfc6qQYX5CvWpd+1x0HoXwvEPsbNtzweKlF7Ns088tsJOFQ+QSsPiecOcHhipzML6t
pDJUVujk+IwVqgp8Ph/bsCICPp5FFr+mESRehKPq3QpiaL6VxF8LunwIFXAtJqnZdHDLN4LPX0Rw
6yNf3reF/DmzUJWIEKMISfzAgwp2JztTaEWlizjoXPcv4G1smyVxX9EOBTpq4CbZXojxsLTpgAT5
EXYQzM5LsUo1bZ194L3ytKanaiuAQdHb3Tk1KftlwdVIhSLwvbUqIvEGoM41W7rxAxEZR2JeALpi
Nk8jDbtc2FlnYqXvgJ8AkWfrH6eZdrOLkfLKD2r4VO30gI6qYKitPJl6Ztu6fjMhrQm8VZwtpHr6
ckL7Cj3hv9anNZJDyx1NdlRMol8Ev7CfWwhAsoUI4gIBVmb/EoA5fIDwgAyJ2mgJD3LLBALw+rSe
p5qWOEDEJFGap2Z+TIeFFhi8uBQ7pK1IcFDCpJJ/+wcxNa91SbTqe0RQ6Bvsvts1RYM6bqMsMzuf
HdF++DwMfe77tsst2Jwq+YQpHo/pGyKCKUYtEGlby2zAb21puYUsqDxXC1C3Va5msBOc+mWQ1Uo9
tIJtQMS/1LJgTu+pYD4viJg5jASR7y9s25VfnYGjK67E6lyY9jZ+rAOjM49+XCwXQyK5BmS5+jEp
tkHlvi7J++edWDEfQucpASukYl7JFnkxmpxgo8HFfbx1P77krpqY0Ej7UELXdlbFXfeKt4OXX7BQ
H5pTY0uHhrbW9zvLEy9CDAZL0CaD6d1Y0zLPcnCPmALq9ih4JOR9/j9e5DIJ1xOUwBW0lMEUTl4P
DdkG4sNxtlkfHNkAkB2auKdmMfb0r68N6PRwzBVc8H2uVLo8luQKqmUMmkI5HRPiYJ/Nshn79qNV
zO/x0BW/sJePFm6CEEg8bk2yRIBspYQ8DcRjJinqZE7IkAZNVyMc3K7IGDDZEbWe7ZMvwRMUaEX3
jqj/wxBZnhQi8aXO93NexsMgkAcGqppRQ32M3AgZSGezPJLY22eqbsspMrrYUWsthRTv7PY1uQlf
ZE6QtWruNteUgF9HJ08IDU03Vpj72XCQRjj/9fm8pOjo/nfm/3LZWVkhUFev1xv2bNRftGDgQ5wR
WGlaSKTUoYdT65dnPofitcZEsKzxNrq5EDY+AFZ9Bh99Sh4afhfBv2HzLh2UUzaNDIxVRUWJY0+6
F4ZzLxHUSyOGEjTw1dvHkYo31l9JtrkdI3HIu5gIeSKDTOZViSRY6HkfV+N2EeS+qd8oohLlnRq0
GZDkJJnMuf44SIGYyfGEo0FymINvtQhIQaTQEKs7uWINhJC6hjBI5Bm7l1m0XE4KOjLgaUNwTqKs
oR81WZkpK6yvx1nFvuNLJfuti97rAGFWH1UYC0GfElorVMWt1puNjLlIdGP8UhhsKDjN9//3n/lb
JDEILteuJIP+/W2DimSuLYbqUG509tocj2jW+LYWo7yUutZw5S/YLdsB202yETZDT4xGVIbceUub
QXaNvx9NDctegBFL8MbkLKnnofoxREt4D3y14SS64lB03mfdy7xqH6iOXyCkpbyPHf+q8fp28Kr6
4TgduKszDxYBdwKhHy+FnZmN2QJ11SpnGkCiyCT/S6Yb37FBWDpECALP5tGZAyiUR4hGi3/5gQ9c
OMGrc3RocdU9SjvwvLw4zaPd3j1x0bMDGFKvndo+4sI8iwqiW+CVph2KBIpo7cHU0TT9+FTn6D2f
qRe+fNlSsgjGHmfyKyTOcH0GkUOH1BrYSwKiJnWK57HdNTEcKstlmzQiitdwXVrJrozWVrFZEt6u
nmcZ9qme1l1iGLDUgCIPypVbJyaFWYkzjmtbZgL+xlWd3ixFYXxYKg1IeKQJYmj9uAJcCZpQzBfV
BeqFOFwHlf6Rfstc15N2Hgp1erqtu9qneWNwAhROtG9za2Q9FXYJo30eEfZgIYltQi7WDJ4A70D8
bxWKLM1mrSkgkYGHjZzc9+EOYm0OvvxqhXbC1vCMZ3dja0IGUn5DB81OrYWmlGaodpcqnymW80t5
Dkt0EW4F32pAj/eXIt5W9k9er8xKGDOHCS1J9I4K+EYL+DLCQseyfUtpH2ETL+WzqSl24EPG9Ir3
18K005jUE/y1S7YdvKgLvfD6L4NPWR4yh7gbu/qoPLJcTlWmQH9SJ9acKPLhbGurIHLrT+SveGF2
2PUWVMNrKQpWfWjPt5LhJS2X4nbFvL6dnPyEtPzCAxc70z/FZzGiFx4X9WI/1NC+Lp8tc1/KrIoA
pdL5axw4nVMiw7jSz3jTLGZnNNftFnal+JNzxXevnxatFhxGxf5YMCJVqCPZw0BloNAu3J+81N8H
jjLg4JFWETPRYVVVowb/7JxEtE6IqwYyIF/tr3p+C/1HUc7jb3ZvvGhH/WBI7xtJmwNds+CezeIM
OFwHGT3wlGtLdRUnaJjiFUalVHCJE+wbL7B+2Jkiud9jthKQRqeK49SlPf5Rae7hahLXDIstkPzW
EjtsJ5zszxU1+2ywupoxr0JeiItzV3c/Cm2O1uJhGh5AZ9H7IGGXbTcL2ybWehSI9MHr3Fe4zCuj
fbadS3y7gWrIz1jrGzXnZJwsNIo1p0SdpTq8F+WNSj48cVIZcVVwu9j8WbfhKBeNblGXz/GfFZi1
xHQuuRDoY5kmDzp3SgnpkPPHwTOO1pmqE6OLdiAdtIdKlTvPpeHYop5fPNp2IMMpPvDEHPSk8eWh
EcK7o37zfvX25WkPYtxjRI7fBgc/7JUAaiCDUwWGY2OdAxzpG43Ac4nNF8ERP/ki/4nPD5DWfyq6
5aQgUWm71VBou6pihNdQiSZjqxT8MP83rPoU9404R+cfz8GE5GJw0x1qXAKPJQ3Z+pc8JdZ1Rtbn
XSbgiN78XtiyTxqzOqhoRePbP7RXSo2AeqrKbv57Eli5lXGsQ1bs7kfQeNVMIwNZHlreCVi3CsNx
M8T6B1UlJJ6m0GY0Zf7GioGVK5nx4rx6p8oDBc4epkRoQeuCPN08x7lWYZvGACyktrndDi1eAOuw
xz7NveqzypMcBpdgtXEbauItUK1/2F8yzBNPPpX8n3nsxQNDsalOVnIjKlt7iqaJxxXcOh+jS9SD
tibk2gubXpgebpO2O9MVe0BwNfEviqErNzqGCyOvJBkg9Ej7srp3yZeYIbyCtglq/54YnU2WbGB+
NDw++lLsc/vKKmEkYeU/KPCibm9yADLEgFBYXxz+p0+Wth4DXJ/d9gjTJlUPInnkG7nwTG0xoxVw
3mpsiPh0/KCFFCkuCg8267tkY8anQWq+AU1Bw4MpTFZC7o6py5QALyPdCO+2fu269grkUzxeMMQ6
JQyVHNQIT5vfDsT1+c7hOIM2bxlTimRYOoE0/hVwNjTjqLyvMW4UiLAnAz9A9z1jGx0ua1X7KlUX
hHD8M9QCydPn4BHmSG7VgyWzxJqbjNSL28TW/Ik6VPmpVIDsgTHpij1cJEMGBLyqvSUxRVv1FgZ+
6dhSLsW409xxou+m/LxCupWMr5Ce+i0GErknux+RsWpcBdwTkLoNJiODXrR4fU2F1EV9ONSfvIM9
tLnCqBxlLmgJDGsjrRonKlBrpAWTgy6uvEjVsnofpCWx5DT9rT3ef9hT7CAb88asD3+4Q9ugvjEz
IT1nuekAMAtMcb9jr8Sr33ftyaRxutw+1aLskZg+Jo/1frqhK4XOeHo1uA4hp/d0Kzryz2OguDXX
NTQB8O2UzHVrwt01+kxpAkxZtWgMKQHZOWmXV7ZxMNHbmy1dRCXbUfEkIga9tL4nFxjrRYEqiQfG
IG3LkGjwWMh+4biqYj8CfK4pEqtI5DLVT2Mr8rhp5/Jo+hfusAJGcBbSNwDfztHUJIx8xdEbj0m1
R7jlKUA1BTQ1HUr8COs8ftezfQaOitlKvrzaProPiESgLK9pCEgE5dmw7LMyyF2SNdLR3pvDJGYM
U1sQ6VfD+ohu2We9951JAhSeDfU9p04rNh/+KY49eq5RTfeMRJhriF66rcFZBe23TIWD9kjaAsAO
9ZhwBx3w4hl915PNYEBQ8FzL/Fj3jdSB5FjXjlZnKyJivAYrtnws7GLN0uVq5BEuZqmsV3puHTLP
Wo4RO5ZOq7RpbU2eQ2ytdPMEhKjd8GZw7aD/bfc3We5nmsx3HdzZPXTXFyVWJRrCdDcIBWke/a4t
CXcBEdKBQ+aeDhvDDNR+/ddfVUUmYog/TExRplgq4h9jGVs1C0CD2EERDSZ8jvGXNPnBvznG6zfe
30MW9Esc5AwyNiUnx/jLb+1HDUPx6+yFwMQxxmbj0yXqO8SVZ0PTd8gR6a8/b1+lI8XbY13ETNRJ
yrIZBRDl9HE8oKf0AHOyTqWjD68g3Ptrm3cLr5O56Wrvf8aBzRB0uXpdBatM0J039kpDxC3fCcwL
hSMyOYI0msd3mvbMJ1+ku5hQsMb00OUDL2OTtaTBjF7gkksqhBDj0cCrJKdGCULaVw50iMYOclpB
RaNQ6arhcsUbMsGcjUObqhDjRR1umSmjaZ2Rk5p8llkhpFNhi7YeGtcs3sWmvD8TIJGBsO5ARgvY
C6Q1bFpYbKZFjewTZ6T/FLRqnb2RWD+V0YfkG3A5nUmkpdhzgK79rSRTQINv+3u3wnIlRxBbEiuT
XaNreQTDU8pdjKkfajR64LcpNN8mje75OjYbyy71w0mBx8pFFCsVR2JdKh4RDQmBLHh/gZNwgEzq
ESOR3Maeq3ANzlginNwD35mDf6nxDA4HqQhD0zO0SIZrVn1dotP9soerhjExqIXDBAz7mPu6kmfE
6a4KBKYnGqz02XWw0njBM4M6+MBRY6N+JQAG79IWUV84aYONe4pzzVbdpMpAUK5rf6ntMOuVrwHC
Y9nm+8Y3Ny/+M12zJQk6nuDsAZXawlaibbzWQUZ1sUwrUUZ4WY1BWcsf4hPxfqwMlw5umEQVe22F
/DhmwIzh6didP2VXvqJLzz1jpMcvLAcO12650NxnZkUzrHTo+Wc74WGPbbkTt6avXpabZKVPHje0
s1tnapom7N38uxkp7HLqFPpuhrDSM+dbQcctZYjYA9Hyreo/I+wEm+ZpWvHkF8Sk4F+Laf5kr+Lm
jzXwV/MhJy4/vY6dDIvUNiC1O0dIgu5yIjdk5Ut71w++oFRHnlWaBmuuT/ifTn5jZkn6XajK5tGe
F+JRqawVqndTgUvMxVxBDOYa6pokvgpAGfHrWGijI0vvKvgmw8YGtfHeDDRxewBzl8XIWT1mJ5bT
rrLoP/1/RWyobsXRSRPwtXuiO84oRGVcIy47jE4efK84fUpkFFPLXOnPjVk1Q6by8V8x8XBqUSzS
e66QIE0TMfO/0H5Eez2Aucg6LqPbZORG3Ed+Hnm273se6mrTd7vnQ0EdlmWbzDGIgSVzvJ/R4c96
IhzJj16ieGmbS7O7RCSY/VUcS/AiS6aK+y+44gec8MMP1YU5eDSgApopFdvlLR+6c5ZG63WlT1EU
1ncfv9XO/9LuCnXPFj0vwwkEI8MB9UrO1lnz1V0YpdUZyR8jmCB6eXmg8ypcXMHTthb6HQvj4c/7
z7yo1PU0whmwBwR4oS8ShNG9BIhYLCIfMLNHVmMWtv6YosnLNvbIU2JcJ4EUWgUEPmHH0HlFSkJ1
oJJP3kdZL9uEonyztkF87A/YXOX89E/+w5CpzsYMD/cROzdjCG6R1hVahnTs/N73aQmdRQLWLisS
9sUzHiTf99uUICqJFaz0hD9O/UX8FWxXBl9Hac6EUNkfhUhdkFqfyBo3RH1aD4cAsyJBSosb545h
vcECRYwk1VWzFwwyhMunHDucbUnuCAzOSqcZbF25SJN8YrF/Z0wQCPDeVuQAR3iP0tYMjVvEJHkL
XO1qXHKdlItiqgSvLHOAtAcycXqTVhOhAGzKU9K//5vRhz9PTva7/3CKqGEvnOJcpC2/iQoayXKw
YcILUUzhMmRfz66mOLj3c/3tP6ksyd4P6VBHyO3+RHPDa1eAyIvHmOxjYVmOHJG2pZQcKtPOCu7S
ciYjQ7OfF/Rq5WqarkLL0NY/D8yEXSei0wYyxRusD3jn84Ms/+osYBY3hz/rL5RNgjGecCqXWQNc
yXE5rn4fGjveSNeNXr/8bVW3ZJrOegBo9BprfEVqv2CRJbVEVBTQz+O6fjQF8F6QL++yPRNnmz94
9kkW+Vn7xXNmqghsB/9kLvMTeF3ZanrNw035BegoGfuo2VzIiBfmNXU+SsvLYUA2MFYnlKO4D/wO
Alrp/U+cBe/rFvuHuktgNma4AvJuB8NXarYxWB3O/9FDQZVohIBAEIHpvhJAS3O+vPeIWBkC9wvX
uvm5CpNiJWp58K5oeGvQUx+hxUQ0lBktY98pOyVGBNtx4pcaB8zEbZKEkR3bCiksL9qOmsiZdqIm
IcW7AAHuJeTMcpwzrCJACWSmhQ4EF6uJ9kvTHCTC+f+HJaZNO5mxp0wukRkFIMUY0WcwR68Tu162
KVC/u6uNXcnp6Hte3DWEO9r+/MDu+4cXOuPwUhcC9R7s+xn57O6g57E9yP0JeR65Oqaa5drNUcdn
3vi66RI4jLpx9GiJ/4dBVFD38IUEIhDe/aG+QDVtK4Zhm907CA1Gp3x7kxqZaYJitvFo+QYMur/0
CiM1reWQy5xy7z+Cho3oGepTskEDoCjuezbwE70awbF9vOZpA1NiVYxv7wXDtcxpKBHrshhdabS8
cajd1oFNWkiYcFG2ed6POprtHiipqYDLa33aL/4sbwBqaYigKkIUo3ze2jD94Xn99TTGPUTygEM5
gNMcQh1wVceb/+daeF3lYkMI1erosKVVUSPpz0EiZLKMLJjqV5AtuzAqh9kHEKbclAqeS+0SPmgg
A1axvqdGKDaJIQxIp7mW4ExDOIgWus7pDGK55YOAMRq6wpz9GulMm/SZMeeEq3UlAUOgwsMV4YZk
7jtO4EIFTKFTOmw2wXdqiz+nQHEWEGKHOkgrOMmEWNYqexFqBPWXnLQj1poEs07iwIah2/mu86YV
HC9nhjFRwoGn6mGgRrRI9QE+8rDuDKM45wjLJCjfwC047RDOEOW+Fg8msw6JYmonaKLk8/NlS5CN
ljSgJ9bEz45ArvjbqwTsdw9EyFXnMb9aaegI8MjclXpCTTQ/N0Y14zNVAedL+RCiMMNtPjCPK0dz
0uo2jxQX8U3dF6It5grh8aA/y4zUWnSApITV8urEix5LZuKiQN5c8JW0nPSbcdFbOSkHi71CmBGk
RvPp1vdJdp9P4Pwt4D/mBQ/CCYSK8aG41Ba0j+BhOoPBJcz47O43sTAISFgGrdOL8JDoSkY+oY4F
nVxOL0kKvLrgpdTwslR76iB/UXwrfmQwBthxjPIUQsL85ZTSkEIo7Ejxgy9PmOQ4C6/sBkY1bjL8
HEAwb5K02WPHCk2LekR8QOyDt1qyukXKc+KuMcem0qUtE17uNPbz2g71PbGar9sQDSmvDqT0emca
mNdcpLY6SHhxJeQGnKH9CxgY8PLn4AHyhB+QDa4N7n6Y5WUVmz5BYVm9PeKu7/wzudXGxA3TvPIc
rxO/t5AvKOpc2sPUTiceCdceARZtP1l9idoDJ16Q2CY1QS2wAH7pIs0lNhbILLb3h07vGcjdlP9o
mzhL+eJ85UJ6L9M0Gc0KXcYpdFRlJjJcLfBapg13I06Mxtva1uOZ5XFmuPufAt8ymi3J4F5J3Fyw
QjvC/Tb2g0uf85kiTm2H42DLqhgSvxz15CbmgOWmMaqmgf+4o/ohXoiHOZf5UopznoT7w1hm/Odr
xLE+aRC250RLlvQAMNLJdUP+kSEnvFzW1krIXvZLYioi+UYkRJnrCdqGYo/597jTJOP607AeEY65
ifZlnTW1ZBVXf+aSdebbFtkSEtV4X2aWmOW8bRrp4kBX59Q9AbPKFVcUtL0ruhNWvntSXPckA9C3
hdxiuIqxrPQ4plBjV4CWHmIJBTq66P8bh2ochWpTrghTiAtGV59YQCpndiRd8pxdeZsOtLA7asmb
83PMg15fTAijMkHqYt9RhAMFfAYfdQ5BIMOBwNYduMXAX2K+QQQR0/xzHd+aL/8OK0/e/zMDlWtY
8IoC9gKm2QWM+ApfFCJ/BxH+IIiYX/EovqBtHAz1CSn61uM0Kg4gNo1R0bzxw+mCP5KEbexAWycq
AEX2aGONEcr6N5lP5YkOHvdQoWdoP6BxozM1+VGp3wWH2NBzhF0KQiOlrpaqqphkvi3KvDW2XvIZ
lO6Ej9PcEUkLCbCPTMzx0efiH7RsJrOuGzrrUFVaMHLkP3NObLu/rpKexr5mapHCE6+sZ7HDLUnk
F6zrnd8ObM1xkQUPjL5sVUKjhGgu2vHBMBgFoPrL6ime0PPGYxSRSEF7sX0+2PD1xQtY5TI7mrFk
jSwv3DPyklu6TIJEQE+hJqCipY9knyP59GPA2u0Nfzjp6boncRp9+1jLaBhiUmoFXKYbzWFGWpgB
6UX34f1ImV5T/+DJKsiqlh60oGyiSZi3RhN+Ib+pzZZaPIE+THe4pnOEVevrBE/qmPV8eyEyo7JE
i7kRPP8PF1opsj8ydeDCogbVO+dXnetbqj/QEoD5l1cGJJOeYKDcxVVuNXxL1gCGnOrkDx5X4hWd
EpFwnh95AsgfyNziPrDiuZz8+QdIkh8LIVIA6xFnbO9GrIVViqxkkwnLr1YIqk5eiSLMDjB/cQrS
xUMOmHqK6qM0Fw5U/S/5N6zCVTVvBtlyvUWoSq4gM+sOies9SzFbjyXNcuKX46hHv9n+EblnkOkd
MGFSoFJPAeTuXvTRbRKWLAzXhEUyP9mAJqBrcN8G9/nApAND83VNe9BhKaxnsxVV+q/d7gUg90g1
TedvbYXO/PJgyo4t5b46vJ4Cn4kYdDqDo0imKVX4CpUmI/vZS+SIXpABi52cPKNclqOWy97Ophfb
2xHVIvuHJcKaGHGg41vIsB+ZJ56DqVAv2Lr+yGSnVVtHyxig9wKVFu74F0S6z9AQLkaZ80N2UPcr
p/97PKGcA/KdkgR9pF/hqfTfwY8Pof0QzzXd2Df3Tq02pVdQxJ4Ud8q63sK3mAMq2UY/FgDSp+ul
y1S2UEOIC6zYhcX5boorJr+UXILhvqchE5BsH9nQVWM4huOp0aE1Zpg0gJgMqpXIaFN/MYkueBQ/
KW1EO4wsdpxoYWA+HDtqEGxba66Dc0OmqfRyUrYNwjXW0Qav+v45MdCIpzjsp5wClP6E9BlLhMjD
0cotJVr99IrQoqKXw5AwsbJUymdy/vfG0rM/8LGPZZUeuXnU6RxO8qyz51wYikHLAo6fNroFPxoR
f8qTy3MZfQ3YmzISo4EF4fbE+TG484zi7yuG/1ikqbOCed3V8T+QPjY0NFSHs6M87/aFJRB0xPc1
8X/W2yYWPwzvYfSPh/XIlpqbTkrWKB3O3HtYDqLoUVMKPQjHVJfTmuIvhX0uOg2SFmLnJYW4aL4R
tN1252mQxgyAnVaq1EllLqq2FqQdW8TEodyP0NGSfkEkGTVPBzwc+1TqPBjSOAkKixbBrlTz2d84
n/+qNuFOogP4u6PqpWkBuW4UzAhFB1TInFaPkweu63T9D6LBUybPgtuXqUw9Rhc/wn1J1Z7xWJPp
La21YJGdZ1Q35IflIqJ+NtG76/mPsWhCOjsuqXlJ/fR/GksAkVH+FDB50/UitUqibEaz6XaI4Dt6
Nd8ui0QawBGqjap47RlI8dS20TuecvKAXSbeRCkE+WpQI99z53CnuhaxY2IUuXf/IE98VmhS3Qsb
5iacEuz7zzveoVyLVdy+xdEtua+NOP5p0D1GbmAetjtVf5F20gIm0U4iOOPQUcOgWE1YdyCg4fkN
Fp9CLT8DE9GDiOzSM2t9bowlOCUNdngYIcrOmszNstX10iL8In/8IdpQ8cSXOhIqK8t9PLaon9jW
V2L1ktm2nirUxsuvNUR9M3HFzo95OQ11mhvFsiAjblQurYfiC0wSoBB4x8BKsFMVrgplxICWcq3A
/TseWHROKqOsWzJs9i+PLT/dYlRy3IN3F/fkuMwwlEDvgDAVYlSU6wCTyLAoCnIokbRWXK0x4n07
lTClm57D7SGuZg2kT/sv58AEaeYq6c9u5gLNAAdwHEyhyNYH1CXs2eCqKViaUUCfZxgbGUB/NA/p
FfXsSyLb10gYzyfCfK3ZGRro+NdfN9dJroJsTxwWxnWufpWjIb/eyma584aZx1pONXRDQbE3y0/G
I2OsOQZhSNVatpgk29J/5C/9bhno2QuBq2SAbJzt6d0GfNxQtFiTNkmjYj8UiDcyiYpmuanayN16
Jswxzbp5I8w0rw+yZfozT1kTu9HXhXlgftenLAu6fxMl17rsl66zJU4/FBDbqAaWGC2+HuDDbBxR
pbvxaqJ+nOSifBFhKnEryp8dfzA0yuJT59wRoFpP+zR6riNUkmnMfPbe22YBVsaJ/7JP0odjV4py
SedmYq093H6wpxraejEaK+sXlPYotoHj5I1O0YVmnFPXUD8WkBT4yu2OYC3L1RpKhKk7KRSmTNvI
EFIbKXjVxVbOEP7ipDgnvV6z2URyKEb+53DeIJsBOdYCxUdASMqJX3Jyjz2S1QlxxR9cE757E7jr
V1ugZGY4hosre5ZNrIDMVH5tuld0bwwxQ4j0oFsx3W3T2leeAgVr5oyXmxBf6nm+BdokcJ+Y60+B
p9uM8xX2SslqNEv4t4Vd/RT623+c5OGKAgO/rwB7mFrpEdcocCtNYTwtzl5yXL8PNVQnmbFl+8HY
xlSVjWmFve8yWfUy78aka1s82G87y0Y3Z0Cf04e3QRRv4RhR/E6acCRN5stTrRgQhC20sTpGt9nO
89A/QDf1NjtkdoREgQfqwo37JXAWRoyGMEa9hhQfeHp61Fqg5BLes75FXYzf6bqchBTNkpxgw81o
bjmjm5ELyJ/55D24jzieh3LGKq5sbjSVjUyWJYc01oiuTb3l826TV7I05fLtKudblFdrBEH1JxRM
i7f4AhKk6XfYpsz5KsWoqOtYglYep2BivIE+61QrQXCPX9EKVqxMMY5yNz4IUa9FzBxL35hlf1cB
iCv/cq47SMTtJ9LOufMn3FSPQrKhjKoyhDILc0U/gICm4ess0U/IszU37C1JVdA0w7aPqqOuZddS
B+OgFMiIVdbSPD6EONH+5uWoio35y9t1R5t0M/sVIh2+whqADigch5btCbNTtmX02Kohwq4riU64
IerMXedD0X81PEKuvIjElSjP9h046CuGlv9zL0+267knZflDGVSboj1hWyvz5JmR29Qm4dncROB8
qLLYuf1ehIBN3Q9gPZ7T/QAFDsrjz/xU4YBH1AvzUg88zMptifLKmOsikNJ59SG7eZgeBGkZybWU
nsC1dS2Muq64Mv284x7kVALA7G5hZ82p1QWvkvnq9lncL97oxaO8j+hE7Oeyd94Bn8G8i2Bgr98X
lctfU1SVhM62IFj+ilSS34GGKO3ivcgIcs+RdakPwrKlfPQYouUklMZumTjHVD42Ofp3PpV9LJq1
fuNszdnp0jnpSRsc+veqYjiZuWvmu+Lr4b4vt3L+ebWkR4FtaJ5rW/hdYoKc3K53C4HftRLH3QM0
Kmy9p53m1+4xU22BhfciqXzvLshTAvlkQC0DmJBA0AUCgHh3PkJcZqEvqwsNPu8noCJZvnGGwom2
blPzby0Uu7ZNdmvDJKfoR46EfxsTT39CscAhXq4ZmY2//IZPlcDvkuWQitDr+mjvgfojlg1RJxCT
o7y/XysVeodlejJVptC7/4Mw4XmX2nBhqxvgtKX8F9rItfDTLPIhvFn3if4uuPHQLn4N33KbUZ44
MgYnlDwhgF6R/cTSy7worVATk8ixcWqR89nAbZBlYstM0+XlkY7Ij3K9LRLwUaxw9xjwFqI9rvEF
V04t+gw3QBcsZ5sMqSpDgaoBB1Z0yJBSqEA0e0FCsHNgU/VYXShW6GQbFkJ0lkfuLh+2pyx7vx/s
lSJdK7yFqMEnksbp5QCWcDpZ3E1DGUwa9zkeeUoNqsZBNZHjA78zKPI88ANSySTTzdPYM3ZfRHXg
DLE8uD+Qh/nRKJSPbzxEYnh9nuHdNvjSY/Ooh3DY6Qz9bQPNd+fJGvlT5veDOLgyuMtX47oHOLCA
ed9sdHjFtYnavjPnhVEAvMk0o/QB6fsejWq99183O5AwxTVZaRiP9MRsHVztTOLOzHVW+optph6C
GEds1iMga/wC78T/NTmMi72mB8it5rIgDScVnGNMghMV9scv3YVb4Bt0BXCRJjG57qyZ8kiezOmA
PEERtSuLewNQiCvf3Y4uOxD/mVWEAKzpRvJ3aWsOXLnhNM9RmRbmkR7DAYWQHOGb0m3VyeBTZCdI
uma1Z+TXjwbxqHijJuqTvRETkLtsjQpZFZ5cQrXZ5kn2R5KqDgbMoFilB5M/SveD+WoHBp/FugQ/
KVl5v6glMvz02VPlS/mo9kKJ0UHQzEOfY225otID/QKEKoSDFBgBxXGtwl9j9RvOcnMGWWTJqONE
pzmrzSqT4gX3KHdnXwSDojVIdpDXs3nkvz8P+zFcpkPO3xRAFI9eMarNSV6eK5Gifb7D6ZSGPXNJ
mMh3Gjy7zdnMyJLIWLNlA7mwWclsbzoL42wCU2xZM4liLOFviMbG6bhH0XS0W8WctVTOu1pAI7eh
legWUfyi2mN6kQyqtoL5mRS3dpNRpkvFGEeZFCurGlpFwa7/ZdreI42KynB/X7NvuGGnFXSl3K7F
kY3dzUcjVhzaeL4Fj7Ayja9Axe9xP4aNyQXjzY3HJ75YzOi/+/uXUT0OEaOkrzv+PeNMwc8UGsoU
mLwGBLfvK/Jyz9AmmnGjucY2uX5h/iwQbIMW80TFtKFz6loE97mHEX3GghqPes4ZCdl+2mQKPlPb
Cqy2uG0L0kBf1Rydvmenrkr/iFQ5dKrxRaTSSQoG3YmC8vaLtdZFQOuaBFzlYdZ9wuKip3aru4AI
j/aF1I5MdzrZj+sOQjtIXtNzqLb4aBudms8yQdfCxlHz/Qz3foeLSH7w0NPozUXnbPKzt6INFC8c
s0dmBl6Ay1kUOjlV7PF8AsaAYtx8cMwHR5//8Y9Fbw2YkmkIxz/96XyE6qiWvqVyvJLamXlqaAd0
T9iw77+hmW5yEi70RrTdABWYfGLIgM1dUxWOQ3upvJvBgvvrs5cg3kawJ3BJTNeRIU+XyX8WFxml
ixaYu+WH3VtclLati6V7ShQrzEV3zHgd1xz3lzBdtn4rv7bIG+Y7ay1/+6nzsoDOWOqu143MidAI
fkyQ14W0KHC0wQhaByi4vn7VsMFpebr+4GVaH6Zk3CVovIyTdLRvrNh3X11X9d2WOHVJTBXHkrQz
SD/didTVyN/nuDsqh7SZv4Gi26hetPwKlarFw9f1Lkg0ouVOC2DHIQ/j+Xs1sguRaruDhCGRTxSs
IDXserKuy4obKbNFTxYMN8iRqVCMccMaleOlXMPP3nS4Ur4mpAK+hkQO/Gkvr0fyPTdm6/prfC4c
5LS+1ZgENdBy0DsDZcPRkzY7ikOYejdo5oE+DwNlYOdG9/CK324ZgE7EjYuLGcbGe0xzOgnrMaH0
TM2NTbaK4iJX1UHGBUE914jsrM5nJEoDLoeUGe9uqzFIf7UX3MkkQAnDL1Xdb6WaS6LXvjryrY7v
OM636jUtrC1qquBDPe3IZPYvKm2AiahI3KRmg2pWnXqzFZjSJ+RtArAz4YcS6rig4BtUNmzuiOdb
TSb7VnirpagBSxoJ3+6TcUE7NN3P9NKbLgnYOC1sftKej5Mezgkyyj7A3g4LB1055Z9o+FeBpF6z
kSG2Tj7Om5ae61k6L6qYSOr/tvCikxz8Dw8PhCNaV03S+KJ773Ha+PGa8K3vl4uUILfhvHC0CWfD
6piHbL0CIcxLX/QguB6/Didbw7oV2HWWvBKXpFScfUioxvRpMDXkvnZR7K6BXan6gtr4OjglwymB
p2YotLWyKjqyah73/n2+FFAQ5oZCy15gGOyfT7ojkKUjxij01AEgXTiqiIy8x0Qka9OepsRF8MEq
cMKSI8svKZglb+L5zLxxhJdi7UC672TaD4zUsol2VJSoL4hrCc4JH3cXLbDxz485rBznWJHB62Ol
HdJ/j0CxjV7LaOwP2fIkbXfWW+McBThvQgiobTKsvXcWQ1rRg8Qio8OrBvg9VRx+079KxdQT7j1o
ZpLjD+DNBDvXKzbSB6DQo1w5U4kvJ+FEAnDsH1lGIYPi6ACbCxusOHnFmxCitHuQcwr+eetThXkR
3Ylb1JnrHPF5Uvw/8/OK8+Wd7OGatv9ifKPwofaLDpk+5sd9KGf+Wu11qziWsd5sIj128fiRcuTg
vqHUwn4tHboZOYs6dFv5ENYO9vcWu4TFI3nS98afVeTCDrWSLIn5dvDfU8XyRIyrG/Ux1X1GxKIs
NSvh6RDjo+bv9fQJGPE6S7xgKTKOmg/V8poWeaUxSry2OvjMvTk7iMWmdWLrz3hqCFQKkxfma5D4
7qHbrkioss9yNQNxCiKch5MdCGa8PHMxeDG+Mo2OoiiboRBjF52yLjZBAorV46E8S1NSWvRqeurB
+6MCxw1VQn5C9xlqVCIkzBoyHsCdKexSAjTHotTM5zzl6pj+5Xgjm1D/gTHtBvH11m1XIIxIACHk
lo9JVWypGgeXHbaR5k9/cVKWxihfUe2JG8Ih/Wvelo5bpjsJgoY56ercu/6bpoJiW6Q807iqCxYr
yA45Z381McvRfgdmVXpXCEP5df0zdKs+v1f6fyDmnAxlNOg7UUo5YGT2GKDlJXx1DH05mDTE9kO4
Dy2JBQBA4j3R21DYslp8Mm5KdczvEzbSh9jR/eMrCiHFsPlwUiIYGPEMmnl290g5XJJlK/a+QNw8
1D0p/3REEV1+iPh9k4hVxJSUreertHzFP1Bwad2KJGsKCJNRwrKb9oZ9K3zPR7lvo8Y6+ud2HDYR
3d9ttFyZ99Rn/ADzjEKliBYzngz8f508iVCr/Y7XvWPDlqVhuJiBwDi6BIhYwjKSLYqdERf2ORVk
Rf5KX4YCtOZ5ym6KwkCXGi3PbdeLAj3sdwo4VyMnm3q95g4rXT7CNbIYA7CFueGZF+sY6R3ppF2A
E59ar412gUGXfbGWNYd3f/vUux59SVcu7gpHSv73M2xc8CehpKq4icDDP3Deqc1egFJEa+XyAExB
YQEPr72GGuScOX7T6E1SVyAnCELPM4I/SIzktYmFrdvN8cgmvgcr5re/ZouGfHVMLRBHfKlWtfWD
4UULKza7aMijo+TudroRzERkCkn/vMB2baX4V0HGVz7EaWmg5j8VazLm4sPkBg+oRYkSw6MKcCQD
O4BoM4uwMM2+0UhEDXaiZjBGvexWkpgMnEZZKc0V1ik5gWdZn/LqijAearjRwCCOEpxNZF35b5XH
pVWAmyojqTQKHk7Wi4h9NVSlO4TwSD8nsA/Q0tCxW4t0rhK8yKNxso4YASUOE89Ng2SJvh5UadAY
PAq2JxNa0gDQxYDOPiAavX38CX3G/mP7PNYmxmTlOchznebm87kNIZKC/Sfa7/UOHZDwTaEBlCpW
A8Z3pwtD5HSEjziHCFlsPD0BZzce7v3gwKw+cZpRNIu/GEVWKZ/Jmwylp9k+nSRcDDcO5PsFFVY8
i/olWdUDfgLDIYF67ECtwjd0hO1kGa1HnzVtVb7HbR+vt3wEE8O+zEPv/Zd6p5wrkXzoGIdOBBBq
1mnaOx7tH/TFySacmSKDVwurJTmCl18vIfsieF9yhAQ0WskDJ01yaVpAtnBz48F8M1GeTIQiaxS8
Sz1rZZvzLlnpj973rwKdbSzz2XeJ/1fZlgJMH3BTxthn6FRfL8rY0IyQG18amkBRUjuOw7WJ4b7P
dcOCKZluklME5/6YNY+moUTgWQ6YC+zat/DxmE8cr1PRiHIPKnyAdLgQ128WDMH1UDhPoBaZ6sbX
XLfDF3t6YHVPn5F2M2XGlmlLOc1VtBeVHgSK+t1f1AfG2rl0I09NBrn4sEdUPQ4OkS1nhIJGq+Op
JLi+hwRZlFvyj53HmTAlLVxl4yDMgH9Uw21DDwxpc9sCDT5NFPLsefenRn+tswitVxxoKKUbImnW
r9bYQjS5w5wsq20eoUQASpkZ8hWbzLZn3sNwvo2ju3MnOdIzjAHWbWZMjdkKv6aUop0KTXMhjJH/
u4XbFNlGwFYvBAhocffiPlxp9tb9Gf4L1vVRogDqb6ABnLLPUEctElHJae8W/hAZseyfsyQ/fXcW
qLFdsC3pT7E1NhPka1AoVZOk8blCs//hcGkQ5HFlvR2FYVuZDoamU6rtUSpRbFbhLPr+TGUVGrRs
QQnZwHw2WtSk/A0r8k4HGnoU1lwNTstL8OcArSOtKotS2aGdmsNqyi/UTLeGy/VbPMaS88l1DGVB
mHbykc8mBbclJxNt+LH+VCCBXMXnDv6Ey29tAWlHq3i3VwGp26LjunqtAdMvLwa+EsvUiaN2lXo6
lTJYYBzlc8TbDC19P3ICsn1xAWMzXz1vxpw8jRIyI1XZ0yQmpnpSVqUItBhTl8KChGcXQB0/qOz7
WbuQhhKldNOVvt9CjF8Q8X/x+/Km6SCGyK8xGP2GlVNhh6ZrwOfFh7KoID5w9g6Kh1szO7gm/Ikm
REFCQgpTklo9ropAKKX6S5vezqAJ+h3UxULIO2QUTYThkk890p1NyfDHKSaNq56JJYshUh17jmcD
Li2uI2PgfSfatFXsP2GydFjP/lkU7R443moeWwqaoYdBKjOGnFHBsFvRVqzCQcmHzdOucWpTPdcQ
am6r0Ju7mAE2n4dclJp7DcSMPdlGnLorTWkD0eBqwAqgvRXLUINEf1crq64bWBeSewNOIy4D/UBE
CRyE8bdfNkAqEtkqshtsOQGBpTgPKI7+tOW6pFA6QB8PL76EiUop9y13mbnpm/Xw+hTqkgMe3QCT
n7TG7GebUcU/uNMLjlLJI/KC+Jz6m3f2ZpJ/VM7neBt8yPLNvtNjApEYjZlqYhMagJbz005J4eHg
7fbsmD8js/RRer4bwiqeBklBbyZau9h7FqDcyR8Wva0/A89irjsQ7JzuetFQKsjMSiOEgJSwfhrC
1x+FAuLs8CNONtwdWLM6yrZ4A+yj9ya7Zg7Iowt559jCaopDTBJa1Z05QFppzIcC/ZeymgXMWFmd
HAM1vTkDIIvKBpENk6/OLhq3c1rrC/DPwU7T9xVA5AD2xBjrAvimcGBw8k8Csm9NzpsweAjeZBXJ
+uUDV8c6CEzKkfEVbcNeXNAms0ipVbgV1kwTNPo1pJmRIKdZNxkaYLH61dS9I45QHcd6IMyDJDQd
zXS4THfnM3+0Jficj/DfmzoQrDabfXGr/QoWTj9LMCwJ69e9QAgbu2t3L58CiaZE/p2igTDyzGT9
a07MF4aiArvN85iZv5axcjffa/zjIA/cpAqhjmhls5cb8D/sPxNxnLZO/BXdEGk/CvGM3QYJyhFk
L5s3SOOejbVtMaTaiB4+I66IAjCPc264oqN7j+TFu990mXXvmDNNgrGZzoDiW/AKSJKWCYunsOy7
dLI7VWzPZQWKOPD7WVJ+9TfASTOkT+EKE1nAiO2PwJVeDJPMlvWJo6YRv98P5xtL2YiUbbzTto1x
zGSps9LUEoBdksWdWJ53gNwi8ZOMSgOxQky7bnxNkZTUIyoyg6OWNQ7FALsy9CgToy5+WMnS+uV1
ESJx0j48JTDImcVwi/T1EKE6oNhBD4TFZixOEGtbYmzHUG133pS7ga0Nvd0UQUVfVR038bhd3ovy
dRlMIbH70X13Oh4jgdHib+C8ocoVvNvWjaOtmmM5Ou7NLzT4/FapxnumLKTL0Qv2LKZ4s3go5PXO
LiE6Rwe/cSNyXjc0XiElfLyN6/IA/naJiM43KeOXcSAMu0Sui19Lh9KqUxwpp9EChXQi6HBKJ7t5
Z2+9LCjbHRH8RW634IX2bUHoZyyk8h5weU5zCgXoZFsw7t/7Rf/8TLgDPonUaftwcHRX8smRWtw2
lxxUqdK4zmwrHduN1m7+FQGzykbVwY/pITm0lx5YUGBovOo50Q0jV4RJ8dUpDXoWt2pssVpMali8
3jCZStLjl+aHFIK1UTsVqqcy9doSHBUvFtLobl+C/dnD+CxjRrN8VvRA0bi/gSAoPWdHCpuY70Od
LM004Imoo3nayNDFq3w8hhHlurYr7ScMdQ0TzWDjtQxHai9JjoZfkhVihlDCIulRGDjtZ7+eFuOV
SNBnptTWxza7YxFt2XOipofx1LicB9e9GRGbYgOU/gv6i/9KDkyUOg1n63LxzaS9bdptfgvGEDrI
1tzaiWQ2hTZXnNWgPDcfvhDva3oemPQPg9vPWBHmWEZVddTqhxdmQROqEE//aE6eAtbSaq0q3xRy
k+LafYegYhJ4pnIUqLdA9udiMhrME0pBmlSbscv7CTW7DjaxTjhkova2CbrZEKUnVzfXdcJysRxU
rwrgXjLfsAWCaVQgsVgYJfDOp8vsl7EnGA2NsmEGViEUCIczEBLT3GIw+alm5QK0M9oIHhEHE1uO
SHlfRj4XOGBhI2VnX9o8bcYrAATWdBgOaZg5DK8Ro7+/Jed5HQv1zL9vpgC/iz6np8xDboEjVwkg
s/L3iSo3qaHfbsZkn7jK8zifwro7Gq3uLlBjIq843kRgwGU43yeP17hH5zxHikXX0SowVjm1p8Wt
iOYI4C8b5v/401pASEsPzhGIVE1aqkDHYb41yDBAz2KLTARY3r/60a3vNInK75Ox5Q1CdViic/Qz
vLe5Zd03wKqyNyNWd+DiV8BmSZW1hFz376ixbdHhoKerQwe7fBYj3iFMUnmA9K5m7gYbOfS4U7aI
a/aRH5vzxGOufZSKyazHpQRckV7+hJIshtDMBbA7BhRznSS9dYYSL1mUQeh8GeBCaT6g6e3TsNpr
KEvIJe9Y+8qyEQmAfd/ggbr01SaE2fMgmLyf5bL9HWs2nKdGI9q3LQJyZlwiljXqDp9KeFrSfIrW
0tu8hOnjeTNm/b48/gyJ5bQh2+kcZjH+Y84ZG58wAhMq0Gn47nGnxWwebnaW7WnaDdDlNruazVgX
FP0pHphBU1ECmvktGmhX67ODylI9mfa4FMz8ExA1meRVPve9qyCga16OmvFkbDvbnOteRiPSp/ns
4Mlu9Z6wxPgkIw28z1m/58QlK2+GjWhVL393cWdphwUf0rbJuhLVVW5HZy3XvRUFseTm2K/bSAPb
ZszA2IxqseTurbn/YUyf3VW9dOUdL1zBvUiqX3xgR5nD/jrFzKQ8WRTxcXJb/arxGGV/gpauh5hv
qFIBcW5b1wr5WSXIy7W7ttdBnx/bn/jhEUPBlLijBoM18NaF2ngLGZbfwJqFKJNWtIC7qqHxCggZ
bRE/HuntWIBLkPpL/B4MA8YcdMuB8nMISIHVRnRtjWAYF9RJfnQ7SuhPUYBnbIqfJOKvXa+Mafqs
+5NqUJ3f/hK3Bnip65opuhCrBo+vzW8Zlr0u5oa4alhHII5VXGf561AhZthij33XUWjMR5OgBc++
wn5VqifbDJS9KhrOoqTRyyMHo9Yz3ni9VA8x8tlsA7aaTTYZrg1VSmP3S9yQnn3Br2WzxxKJaNEo
rnWMMICHQPKcRh6UEVXZ68u1Ph595kiO9uxtnKaitX3P/xhNc7zxjyTLTRSepTPc/HrBuUy4XPJd
54gFL4zDvdJ8HWqTLnVuCRrl4IFqDCgBK013JNvcAzoov/H81hvUf5k3gZjO/RRPVL1zfeIyU+r+
2AbrwYrtZ6GvjV/IyaG7O9HzU9xw+Q/NzRtqfpOTzEnKJWxvBBOYdcAKH41Ho1g5cOkPPRPdJWz4
vof3JrDUHjnj30aFPhjb/YaxJCdj8dFwFm/aubpSeOo84wJi1APc9AOXH2Z7p26Ag/69z7vLJWL+
nWQMNXitmkwK5AXNOZflD5u1I9fLrAU61X/pVmxe0kyrXxPGtOviIiVoQV+Lzq/sxD8zT2zQa3De
iADIMu/o4g3oP3AhjFMe0+vid5HnIWrv9+dYLKqAEggov3J6IYUsbXlzARLJH+pyWMKKXjyOiubT
CM/haROF1DEmphP9pbvhatKqRXgcdM+pGXR6sA4DfoKsAGMj70ST7QONTHXmXWPQt8SxDtODVEfb
Mm9UPNBIZ8CSwNfy0GM09/SenNXxrHHNUfk7+1ifAud2bRRdHKnW6fgYdFKDg3TdUzLwZa4k/W0v
Zy5/mGYnt3ccMiWXj407kaFNNZeRoIMiywRmZ4uLWIbpHPYxgj1BZisQvMcwCkSBNN3m4pgvx+s0
V7+aNIRJKk4eujmt4SUhSdZj1+niphZ6nCSyDF/aZ0LoFW0G03rKrUTPRZLmX0iME61AS8sWrQqT
9ZLW2vumLsoknn1Lvo+pqQ1ZLzkTdkC/HiDDpBFUJH2wW8Lf7M38MGknDpWApUJ36UH/SQ5j4fE5
80jB0P4/FaAlhMHlukXZUJjP3tlBKQ7Cl3eTlr61yA64joZfFDvLSbxEit3A5Z2iNUsSxINekSqR
InQuQr4h2DEZD0Crct9SYMSBAzNhZNf1N070hSQlTeuqcpXjGZtBxYx1L4C8qsuhFIfC6ghHyZcH
0jSM12gRmgmXXShiWKBTk0lONJClUaxRBYKEG+DF92aW9ZIg7RLzqClSVNGQJyItBUyBYy7ctUTa
a+EEsRPbL/2i3yf5be8DR+90QBhFFG4dU9YEEood0YOWJQnQBwaGS75JXg0TSy6Hsn6JKllN6eKJ
qavxgWZIVCPVg7twhwAUR/Sy2pqRyHZpvaH3MDvcazd676th21ePONmlvB3S2U2JoshSGG3xUHJX
NG1WNHS9TrgZyVVjLnOIze38HMS0Pv96euTNq1yRadm1h3nzwv1mGWiMhqA21FgwLDuqweGakp0b
l7SeJkCMUf3NTr1B1Ij/i6ytBl54tWeEasDQD7smrvFDfSSGEgheLJoQWJ8k5Ys9ks1o96u/AUsI
SxPKnp9j33G+esimkj1i5RGjdMJNmcV+69tBPkceYOoyqDAFvFh3CM0mZBGED6AzyLLs+tW1cfWv
hOSh/9wj3Z+8pIO0t5rEUftxRilR9useJKX3bYUKySuMJK8OW+i/Zi9ON4fzqpdDRRPlO0gXCNQE
PkStwvthtE4R9o/1E7bvtJlgQtx5N+s9tc4I3EvGGtUBoE72DEHpTDhx/Q1rgGeHri/OxV4LicOu
xJLyxUvIHjusCD+23rkMqIosMEmTvUyDW1Deo1VV16BfZeYgO+Wcyi8xly6GsbpK446XAuWlzl1R
O0DqbKLFYqRzSdv8jnkw0aRSoX2BR5R6fMDPeDgfCIeCt1JRFuluArXg3kG+Q0XD14BEWLYrZXbo
7ZFNWsb6U+oYHjw02KX5veA3UsYHU41FjO9kMsWLzG9R5Ep82yJoL3vWWVkmBMHBxqyntBQ0/zfv
JxZx1BwZX7LhBmCBOcGlvj1JrnicvHLdiSpbLj9tPnobQymzm3rzjVNzq2my+PT5XXNgSoACaPpg
euhoQOLTMtT7IJ+2Vn6xp3J6TvvWlMHCekEifvAVL07nk1AWpcTwgKzOw+SYeKUWcbqN4nJh+7BW
RhL4HCcFJdfZZNCBDg458bJfAdGNVDf4ZQtVtYmT4DFmKWj/B8Kw1rObzhz3GH/wKXMGB6dVLb+c
fKq7xxwEvvnwlbhVEz8Qe6455pzsJqd/2gNsp7prVFYYXzq3wwRP+PMlCWTSXoCLqYNUWS53zbLO
uYQ4BhjTgfRruHCNZ/fcYT7HVK4yAWNdqTcQvWdGWln9FasgzDNedhYd8bCHhChzkZp6dauLqaeO
HJWRy+TM1aCoEzh0G2iWk1/7xo3hFaduLiMMIB49zJs+GyAUEBUM3hU+ggvg1M+mL6FwmMxFD/tN
BfcEuvvroqWyP6zuaNMUJYMDumf9FUCq5TYXQvmUCTn2kO9tO5Y60/O0rINNRmZSmVFXx1vYHfxO
SBZDoTPdBGzKxlIccfVt4x9rjTQbNdCuyGWnspKRQaChAAeIZV/xYzGXoxzGuC0JJ+tqWfvFkdlD
jbVZgFheXunBcFGoGHdsnmZS7H6cTPuEDiSkjPns23remFnKeCLUNF/tb8FnQ3T1aNNLXBMKhHzf
wg3EAl74fOEcbgrNR7VmVMRWldClhRtkqaa9iKj47xeKDng2zYLnlyBR7J931dK5d202cddJj9x+
CL9RHwc3snjlo62YU2z0R7Ev5CYT6URXwhtuO/1cCE7LL1X5vzbS4W38mk1rQ3yBYvSDDvBx0Rbu
QJKaJVJM7GgHhbmgGiP5xA1Al1eZRuEC3ylPFHn2RsBcYJrPnu8O3rP0crFqB+jnCnNgsjSsS1Il
nRvAjcE7ygvz4onvQ+NX53+JbQ6MogT4FIrhLDxIyrG9u2goO4XwuZ4nL/we96VBHz3hL+wo4SJt
Q1lAnrH8ZNdYdGnWfxHEXf8ixg9mD/iTfG1ZIa8AtCP0tPl7A+3OjkxIFibQGzwuYxTeV2NTC5R1
K/KP31Wb5EbeYG83CpF++ToGD3C8WnewnJSW0TPS+8xjkvpeoQzEcNInv9pfxw9qaPBHq01XMNX1
2JZx4YX8LEzSDDqAZSHtJ5Y+x8iBcAndOZwdPAHqGUVVzPMa+QQJyf0p72B0D86yU/ZV8UOOtEsA
dOGdII+DJ2vnCx9TWB13zGhATyqX6rhResH/0+iVyfi+MWwRaU7CeSDDHuvAaHEipkXWNJOiiPt5
QjlGabOChX6FDxhqoU0AxGBWOqtkaVjc5fsDr08QlAYnM86P/uF9LRBUwWsrtBxjQPAIn7Blbgsg
gmY2jdfmVw4ojMKSyq0cEhTOBFezIcS8Rm2HjOIRn2OzMOCmKOdjCDojVUrsskljUL97Q1BiRPTJ
VdjZAnpgJhwUhLePLU5p4upoq3gI4gottlF3QUsB74SplNFyjn7ECLvxdglxI3J2xIbwhWK36JNY
pwziMh8apV1bBQq8RjHEeF0cr65mY+RRecM25YeWolKicuwF8r42cRPCBhfrcydh952cxjZCcBBu
jIHv7dAdE67NTxe987aMQEawg3Vyo5jhIgn+4ADBYmwgB5F7cr/AVDdtkC8Kh0W6h2cnDUkjXwnx
Jsk8kEWM129G4nzNHZeCDjIOkhOhSxcmR/9UFATi8ug2mZl6fwsEwTnqdnyvgV10ziKQetGsSoWa
CfxBkwaIlze4jd7yDnyS94bxToFZ8dp6yTeHkgluEyRj1R/yqDfO6m7rDVbPsVCfdkBGaund5u2B
gJGBzMMNoNNt0xYORRWDLq/HS+Ic/fXRJdAisdKoXbOkH0WPSXAkuH7PqBRfDlrRFTf3B+TLfmNU
P+rPK7ZA2760urCwh6VR+Y777NrD4c/9ynRIQPi0Rql8zwMjjOKOxlvovpJDUpSLZ+sVLJyi6aua
UUyzZ3tN4u96ccVcHRXaj02jHuWZCg6JwpvkVXPUk04v8nr6jQGVhvs2YHTkdS4/gYeC/KdbB+6I
1LIfR+Eh2AjTsUGYWCzaeRS4p7QmzYdeiO+G7+i0RitC20ZNiyaDY0xV2gxvbIlOhjWL0whtiTYb
kYGcIQKM0sKPV2Xd+BVKmetei9gmvBeW1rl81rV0Y7E1rt9VjdnuYkBqgGFAVoZhNh/Wm4HgwMwj
WzEYwK3NOi8IG5VLVX+ZBT5lZa1X6ytKve97y3+cu0cR6cz3e4GvWmwBtCzcwrRjp6MaHf5hexvr
TfoVRnGjmmtuvI5cXrcUiyY1gN7wD2jKa/r/2uOqXRTZB9V8a6j2gD1mlLMzuLOkh9Ws2o6iCf1R
Ld4xRxveyyiS3nEa1TpusEJGpgXGMcx4FSQO4oYPpoInxwFv1MDHhmaDPOdX9vtKPBWZFNo6Zh8J
I2oB4KlsBJ0oEsajbnMZeY6fyTPKsxkHMhm1gfOy7fd3sLdbXdaDhG+NphPJuaRXXFNtyM+LgkqW
LMD+jhuboO7oh34ffsK/DbueyhPsY/KIYmHgiUJOhHnJFc0I2vy8D5h4n9qxRrX1zsD16bIb/Q4o
uO4o+5OzBBwReA6D7oqC9z55x2iYA10ijtkB9gsTE6XkV2OeCD2fcEJKpN2TA4C/SzXEAyzM43J6
CFV1gmtTKTnXaaKZzsKmr+xtCpWPwZf1PBPALBj63P7jqEVXZoVTPkR4IpX5gnSuKl24fqYQXcBM
7ZIUYlY9a6NviAlsp7k8DyRi7hjZ9MMBmeBSFav4pIWlvGng7ozrUna6G6uIzdrbVzvW0HqVKCwJ
MMErrEEEsGkKsfEpRVjbJcE1n9Whwb7imDFKGYQ05iRPJtfmzct4DMaKEUyFel2b26YDuFDnLixa
/aOE/nPItclb2O6nkUzeNnjf2Vw2HB/G3FYsYSsJryZHgD7v2Shf8279km1MSOUqwHdjwXATXPje
z2YU68ux7Te8ir6bVpmx8y7V6VHw4P0faVeGZGNb3ub08rV99AwON52MkerevICsCdUPJVj4MuPo
TPnGRTLxp3PRBoMjW+1WAPdq38JpeIJNUDX4jU2XP0tGK6W9Ci1BvTB8iv0nuQ/epLHJBz4jvOUV
qhOoT0l8/yZKkmECe3LVc99qys7Qlh7xAk+67Oj39lnSV46gskxeiqEG08EaaduKWVUuitz37jrh
v/a70ST3FAR+6VJ0VbZiKkPaCYijrXxca6uLHfga/urVGh48/nABU8KRpTWRR1VUOuT2Oiy/exUR
yY8/uo9SgkYKTj+8PApdUPYScHU0ymYvpcBY57/nBH7orurt9DhfgdtSkTertqmGGdOW5yxcBF47
xAI+7AcgD9lQBiebDHabTbrgW2/qEWzS/1Rw5StxDFuLM2uIFyPykitW1GQeSdAIRUeOLx6mHZqB
MbBKVmW90HaoYmElug/YQwwb/Hq2PiuUTi8nYiKcsyCpPmLvXuDJtkolEzYug5Z+h7V9aU8nw1h0
NcRykqcwmq6LMbAsieq70kupiPgxw0YvKamGZL2IQyGCzEUePlizk4U1cutPrsxz/H7kWsxh0TEH
JVQizBVOip0j3nmcOjabVd/i8UHvHIrYiWBrXts+LYbeB7ZcBKTP5CU/eJsG8PkqNvui93ZMUVmi
iVTVHgYOeF7pYeI+jVJTnB/mHz5sx8NCsa4jmHSSRWlfSYcQVYwMZ8mwCDQ0fU0/gJaiXvHJnUrO
4JohQNz+pQgStZRafQcDeAEpwpkuV8mLWQ1vKVgWf6E=
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/ipif_steer128.vhd | 15 | 44922 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
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-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
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-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
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-- ** code, or information as one possible implementation of **
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-- ** code IP shall only address issues and questions related **
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-- ** indirectly, the original core source). **
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-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
-- GAB 06-27-2005
-- ~~~~~~
-- Modified to support C_DWIDTH=128
-- Added second Decode_size input to reduce fanout for 128-bit cases
-- Renamed to ipif_steer128.vhd
-- ^^^^^^
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_steer128 is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64, 128
C_SMALLEST : integer := 32; -- 8, 16, 32, 64, 128
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size1 : in std_logic_vector(0 to 2);
Decode_size2 : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_steer128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_steer128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
-- Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_128_8: if C_DWIDTH = 128 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 3);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-1);
case addr_bits is
when "0001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "0010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "1000" =>
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(8);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(64 to 71) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(72 to 79);
Wr_Data_Out(8 to 15) <= Wr_Data_In(72 to 79);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(9);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(72 to 79) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(10);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(80 to 87) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(88 to 95);
Wr_Data_Out(8 to 15) <= Wr_Data_In(88 to 95);
Wr_Data_Out(24 to 31) <= Wr_Data_In(88 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(11);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(88 to 95) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(12);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(96 to 103) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(104 to 111);
Wr_Data_Out(8 to 15) <= Wr_Data_In(104 to 111);
Wr_Data_Out(40 to 47) <= Wr_Data_In(104 to 111);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(13);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(104 to 111) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(14);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(112 to 119) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(120 to 127);
Wr_Data_Out(8 to 15) <= Wr_Data_In(120 to 127);
Wr_Data_Out(24 to 31) <= Wr_Data_In(120 to 127);
Wr_Data_Out(56 to 63) <= Wr_Data_In(120 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(15);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(120 to 127) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_8;
GEN_128_16: if C_DWIDTH = 128 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-2);
case addr_bits is
when "001" => --2
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "010" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "011" => --6
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "100" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "101" => --A
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "110" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "111" => --E
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_16;
GEN_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "10" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "11" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_32;
GEN_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_64;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/common_types_pkg.vhd | 15 | 12094 | -------------------------------------------------------------------------------
-- $Id: common_types_pkg.vhd,v 1.1.4.4 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Common_Types - package and package body
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: common_types_pkg.vhd
-- Version: v1.00a
-- Description: A package with common type definition and help functions
--
--
-------------------------------------------------------------------------------
-- Structure:
-- common_types_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT (from goran's microblaze_types_pkg.vhd)
-- History:
-- BLT 6-29-2001 -- First version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 10/7/2010 v3_0_a
-- ~~~~~~
-- - Changed Get_RLOC_Name function implementation to an equivalent version
-- that addresses CR 574505.
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package Common_Types is
type RLOC_POS_TYPE is
record
X : natural;
Y : natural;
end record RLOC_POS_TYPE;
type TARGET_FAMILY_TYPE is (VIRTEX, VIRTEX2);
function log2(x : natural) return integer;
function String_To_Int(S : string) return integer;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string;
end package Common_Types;
-------------------------------------------------------------------------------
-- Package Body section
-------------------------------------------------------------------------------
package body Common_Types is
-- log2 function returns the number of bits required to encode x choices
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
--itoa function converts integer to a text string
--this function is required since 'image doesn't work
--in synplicity
-- valid range for input to the function is -9999 to 9999
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end function itoa;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string is
variable Col : integer;
variable Row : integer;
variable S : integer;
begin
if Target = VIRTEX then
Row := -Y;
Col := X/2;
S := 1 - (X mod 2);
return 'R' & itoa(Row) &
'C' & itoa(Col) &
".S" & itoa(S);
else -- Target = VIRTEX2
return 'X' & itoa(X) & 'Y' & itoa(Y);
end if;
end function Get_RLOC_Name;
type POS_RECORD is
record
X : natural;
Y : natural;
end record POS_RECORD;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
-----------------------------------------------------------------------------
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end function String_To_Int;
-- function Get_RLOC ( Target : TARGET_FAMILY_TYPE;
-- Module : MODULE_TYPE;
-- Index : natural) return string is
-- begin -- function Get_RLOC
-- end function Get_RLOC;
end package body Common_Types;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/fifo_generator_v11_0/ramfifo/wr_bin_cntr.vhd | 2 | 21890 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IF50xG9xCtZcedpw2Ony1SNid0mhsZreE+6q+qkBhi9W2pU5WEDTCOAxGsgI97/ehaEIiABvxuAq
tsT5lmM+Mw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JiMjGSLOcBjHhL9UYXG3CBppUD6KR6qGgDknYhRUNdf6c2gTFamTdp34KK+KoMzNgSu5Lwgl9Vsz
TaIVdXvHuJ40nMwDBMRV+xUUwwBbC5vJG+06wzb+FQ0r1FPEnpYYqHlTrgH3W8qAFjV+R7KLfpvV
QZDMkaNEL0kWpwzW7SI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
EBCZHVNKma7ERgzcywCUqBwUPkrxH7OcKBqbFZB0n/KwCh3MExUa36pdA2Q7WQqsSYYTMvxNqe7s
RKjJR/z3mXS/5JNmuHtIfKKqJhUlFYF/XN2AhPSv962hwW6Ymjw66R1rreWfY70W3ABfqZRZ7dqp
bw27YITxC0ODsSQi7nbR3f52nqTjUBkOJ7uE189I2IsD5iYdGcBDVMhbl45zy1ou3SIatU1nXOp6
v4ysUHq5e1Mj8DLE6kmjvKqnS0kw2jWpzdv7CfjM5DXr9irYi5QPdpuGnTbHM8y1yfJoSdZ5yPgA
XRMFA9HrHc1x3iIlP2bO9Sprs6C6Y862tAq2Ag==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HksAvRsLhqYE107FDID8LlfAed2qdGBZwtVvs0Ln/ul51YRazl2a21/BepGygdqp4eTI2HaPojFz
0QKktVP+oZJ3HErwp2qdiMMiQlOgFJJjuekWnwOdM7PD2Ozs4kICF2aVaDA/GBdWaZcFsLtHKLJo
Q6g3CTzb3wx0EWTXKs8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
j3HP0hRnrj36ObxibMN+NKkM6e6Ojtt1SoJz/e4eQkRuTWSOhgv4GqxwIrqjrl+uII6DaaCex2DN
i0NzQUztTTbleWyqBVFc2Qvyy4Nw+FHJbRomLGLsCKDxWj0T4fJcEidWWiRBTN1BkVE4uIdyv4SV
Eb4OfFyNflSdWy75gX6rVpXnnMN6LqXFfSobSbfTj7AEnlGKJV5bgoi4W7r50ub/F4C4puhmQSQD
jGGMLzTH0cb3YUGgULUhvlVOfCLDcDBq/5+vBktoYH4DzdnJG97LopT91NQi/QVxcfZtqHdyv/e1
2cyAfTA5q1srxwYQHVuKkAX1Lz/oOPbPKH2xOA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14464)
`protect data_block
C8OihyeMSVT42TNy41ypgAqMXBuVqyKlRDj+WgM4HDeLO+kmKUqOqaRnAkt7kpwAeuoojchwqd9U
9/hWVaFmHR58siRwoxIlpCubPLEbwm5D2i2mVcTCbrp++ODjMtcsi0AZMPLwxZP0GlmpTIIYKQ3D
zVuzHYId+DKXBD73Ddb8FxqqX5ELpzvQyiwcgdKEJ0GDt+r3xMzLHQX8zl+fMhKGmW238nnOcC35
9Fao/fSiBtRa2qL+E5o/eLi6tndXlT/SsqX7f2xX07XRjhew2RrouU2KTQI9jN47+TspSvwalX6A
7U5R/0BuWJhdISB9Swsdhdsl+HHFrGbKzbRqWunWMnpoi4H8t3ZtiVbfzWcrp5Ludenl2mQ8F0TU
0FzsxlZn+Lz7riZq7+fMKdjL4IxtQkVpG6qFyHNBLncqQv3uKJ3b4E1bHjpGVoVBei7VS1X3dnsF
8gYkngpt8Gy8Cy9QqgvSrQ+AzHtwQ2YKh0tQbLHqnbdXrN2dp+jr5o1wiYUtGTmKLXdrd2ffgyhF
UQZ3iXeEL9CQSLY+6rkC04SKhIKFRUS1lGaipzb8e/JjN4kYWc6gVeQliQi8zj5UkejTmek4UPRK
ApEkVrtp0vAh5k6Wl9FSpkArWlxZcrjnbX578wfUWkIuGaee0s8JJqe2vxeiU7C37I55wP7akfC3
NV1iYzq81WmvcbH6/tkr6GOO16niVqinCYvF5ULuqOxxzJW+OssPJvUY1GUp7G8l9Da/X7flbYIY
Tm8Po4HpdksZaZ/0MJS/iioL3ixANr93x8hE3X3Mt9/ND1qspHYB9hWhkA0/Sda4Lr5Vs/uQapNA
Qj/r7lsCDVJCifaitkxZoWWJ3RZW0lHBqQpkX/2Du+cJaSLgs6fsUqtYfnJMva/GtxDTMsZzIm7K
fSlLu3JBBoD984skkEDy+3iQj/b8xxIF6YeFFT8DxGBH0n0f2Y5uHU+vj0GeIcF8VP6JYOAEJafH
bBh80DMoP9JRw57I6tPVcaeGPihV2VIwWBmr3Zlmrtnf9eEj0C+j44EAuQTUlL1sCKFKTNEUSUNW
rw8lESuO/+oMlBPIjlVgL6hbwOZy5I4xCX0nc0wSVOxo2Va7TeIhbet+Tc0+gMBHSTgNUKjYUUkV
6fdcQiVHLexCV21F/IQCLWnz3b3zJBJSVmsLQzKUKupchvXi8fNc+/u+xo5AoL3RiMIWv6xNBkrp
bmDzlXGWbc4e5EQGtY8noQIpxgLFl62NnyrFtBZtkkA42ZCsjxiiCXQBADCJ+rZl4JSCXuNqWTgb
rJSypy3fRhCLcAUhfN3FxQFEy1F0Y5GoxoRMLujjxANXpgaG4m4BRt61P7fpmXwaaS9ZHdFLpVar
393YkUx27PPGpzjvht67KD9xGgQdAHvEK1VOtdLzBMw0aMqSW9RV6HrA2s2oMDLN6xpaVOFEgJ2U
8Jc8DdCmY0TP6crBGIG6SVTVaMuE7l9UB7aLhUZ5YhnrtIy8w9T4GJWfyOucv+zJuJOIuIvGSxze
zWbzym/NpJz4tjssrlQb4Lwiztm9eEoUQZVgM0+kOMzK1w9vtpkdmnUlT6Zdjl8Lu86/HoHwqWvh
3+/V/SJ84Po91i8dfmMdgl/kJnjoyBxkBTHlIGo4neroLg8lq/U9JVk+iIv0Q+9bJNV9/A9oJpkl
Xzj9EEFq4mtuuSs3Cxc/fLhFSe3kWqzyw+jb4z2x7aC5CGbyGYq/lnhroIb210sl+WD74tJ353Te
4w2lOecapYhGY6Nhlm8bOK1xwQZtNahJDop3xiTx/cV98cvQkJeV6YzWhoVoyFrvFuxKUJM4A2+2
9GJeKwkbNY+CrMbnw8z+wFLhvwKl+hrH5erny75GaiyKOyp57nNWwyKkO7unhal4VVfeWCfqKfNk
hANdNwcK0ipSGxHQssY3HVeEftBIVryZoH1RwiQpZ7n5poBD+qyrQ3wa0fXGCudJhqP2c/jti+HI
07VBvnUDM+Xsup0UD7xZnLsf33gZ+IT9LGPNOr8iHkbiTkyufVlnYUv4PR9RaNwPqQiJjRMI2uf4
SnbPplw2Z4c1FM7p2ipVFdRDZaYtpbnvR3HAsBEZ+cYLL8Y0lkp/guh9v+4StHMQ/ukD9TEdzYkc
H9IiqNyHCY/96rFBEgAegErKuS3Gn5qrqYVjRS6Z8jp6tmM+BKh8QB6kYn3FBpbIF77+gX3YLXTr
46DcEI5Bd/u/aQzDQOnEIvmg8x12rEsGxMEu34OOFpt1893F6eTKJ7MkXwlc7aN7Xw00EnkE4Tlz
O9m1dob4OjTLqQwxnvW5pqGhNlN4UiuqE+IJPxFGHghTWmzasI6xJ+t91Es7lR4wJtYQTSNW6Nwg
TeyquZRBoITAEkm/t4lKsa7D1adQJ0zz54RQhTCY5zQrqC3uWCkmZ6UwkdBlBKNx+fyZqm2L2cf0
uLIq13EYib6LpJ9b6N0mstMZ2Yd9/LlIzrBB+AvlCa2+UmPCENxoNM53qBkZQqlv93gvzn+LJ54C
BLLKe4ziQvUbP4CKBJez+C3QR3J36ZcWKk7XorNQbUQ2DZv0ySsN4+fqsIHwVcZoIs7zgorzR4tu
uQh2fYOkZbDD8K2AHtqo6B3/GFfWkYmZrWiX/obM8garso2F61qUXl4cOZ/DlBmO5fqeClrLEDaN
mnJ7J9vxZlmVxTz+UTMsFByyyRAwS8+/j61PoFUUKwsVD3uDmRQfNgNh5AlP0hgBP1v9ooviQJyC
fizBVECGZ44vCgrzDnNwir/7j16fkLqvKBWcnKZhDqH3ZcJPvRcY/CiPH67jxeyYPM6XFAX04kG7
ZCOV3s6mxil6VdfHuJioiKDReP4HbzxzBB6ErbKczNpgf9HQO2OeM/i9bDeqjC7cvok9qIpPEsSS
MX3iihl6tH004ovwuhHcv15eshzXvsAqWnZ5jMUVtSuebMNU4Wbd7jPE+vB+WpywW+ILnooiKVxR
cRbrIPZ8CWo6+t/RY08d4yr0FL2MA5EbzJeaBASumMQy8qtnPxAyViY99ERJqHQTED0ZBCaeXoO4
McwdMciwNRcWyA0crKGwut2fjualfnxWBZw6jre8ywhun+oFTjBEThRPGgpTjFTM3l1Hb+3/heEj
9g3gw8P08CECdit7ziyyutoZ4IfpyWFXMquksIuMNRtu34zeIuW/Rvd1y2EIHszq86kA7BHyjOAf
xaBE70Weni3eGnRL/z7mYCqq2eq9KlTDAaFetDRpQZEwdW+XbFiv/9iXkgWsvvKBFOrTr4f2C53f
IWYYFNNwg+ZOJiqYnHa8oGeqpVRrxz/twJj3jtP8LZMSx8T9uqY0/ua3dRpHZmwDOlliJUWW2TQ1
VMcvJsSwfhBTPMPxAoZHZCkqrDkDNxLtvnK0YGUfk3q1kE4jyC8+vdqFqfljYYdL06U707l4hPV2
P0qyxKWbe2cGJiswDMkAOtYsnTPKAH+OVSv7YR7C9BIm7uILiyquVfOrnLH9b3GFbj4H7+xpLUkN
yCuGo/YWmGpnqXsE4u8Y1muRsORJLXqgIH8xxUumOutCpba5G1RilvNzRH7EQRKaIqVlxN7BK9g7
pVraRKW1asbxBKHST67VG5yBQANECGjnGTcIUVYEby/OBkkWrEYwdh/xwJAJMOapUrtITXEllQQR
Q6Mfpkim0d3HSjFYkWKLWAk4GijB0/mjnbRVl8odBfzmnO/lQoaFjumr1moveBp+xtZd4GfqT//q
Ou9PAQEhf73Q/abGY+v7AaRJaTFqAkXj5g2fcSBtPdKXP9t7FaGUzPivxTIEEoPOO+UTQwJnGoCO
DsgUef0j+Uxjlm/yu1R+ezHgkOlcCO0+4C788cqRPTj6O8kCfz61hyJRQ6SOymwtHlW+/K5WuPxI
Db8CPlqX+WGA55K0AKShtSuA0ySCgQoAsDR7RdiJPy3d3aG5VEgsE+P0TIw7mNET4rssbI557Li5
Jy3fGS7zFnSxa6uSrsIaSpeGFopo6trjxASWfKibaWGIG6bmWQsPbNP7AqKRswu0YxqQ9lDtxOpj
26mnRWiTKw9oTvZfwBc6Oy9+wsLhhornL/2+kykp4wrIMaKtd1+LvGtahUUh2gPdOFpWF9flGWLr
hxOIhQewjgNGTiK4Yem7+RmMFAKmuq3iTitbMdixZ8Dv6pz9+/+fL1ErRNhxw46xgrdwBnlz0icI
U6iwtE24JlMVQDbsv8sNZ8hPNBiFHHW0pXfX0cOQYX3NBLW4/u34vw9Cv2hmESVG9KRdDUhE55FP
TwqIxIXRhbd3Z/mOqa1YHQq9WzJMG//+qNhSg2ZiMPZHjpZyNdmms9KiMZKAwNeq8beEAQMdBVAD
bRWm6Nr5zrRdmOc2HxdIpc1L7B3yU4oIt0njVCrOmgxELup2UYnqL5Kb0UpmYXDm1dx5976/5c93
gzJ1UiWdBTYH55rNS2jNo4A+z0guv2osCDnBqODFs+Z0gfj0Kyu+wpt7Mr3pKpMKgjHSZlwcODvr
2gkE6o7hKH6PKy7yZls11YnR8+ELF5Z+JHsyalXwatV+irYiOrnsR6DfZwKoQVYWBArUDvKCAYo8
KcXIV+6bkXlwcM3Vi9t2yLtTwR5mw7YoXp6gWYilDNMMFyWrDUAmNcgDzuGUPhilbzoWtN384Nq5
BfoRhvs1qt5Kb0LMMcWdWAEwTSZ6vEHZYOkFiVYcOmFKGBFHuQ0RLR9pPXo41mcwwVcvxPTLZiic
XrTI5UYBWK83APQQKKIVqCLy/a3R5XTlniOC5MhXN1GCffLKjXQJA4p1t5M6vweqY+8VbOMKUyGj
QEJt0o7yvBSgyjA+JWbV6N/LGQ0VLIW8QScfapjFD+BRfQ2dXuU4mDqIABvDBRao4dnJ4nZV3r0c
Je8CT/HsuCsaTSEwLqcoTQQw3bcjwquMz/MP1l1bn2T9oKR0zG4fG4gCX4dIqRvNG3+6kLJ3p3/m
IofZ3gN4iKUJX51T1hvfJll2AowJ0U5AdwNosjMBaofahGK+rtTJMZ+PsGqRSE9hDHcTwm1+3JsQ
5M99sox8MaMDgQLPVIn0UoI/79XNLvHVkHQhST5oMt4yt2Fql299DakVCAdUqC5IOdEh+Mhz4FYY
hdT425nXfP6A2vLgp5Z++cGZCVoL78QZUAp1elaxmprEGQG2ZvWo9sayUcNwQgBnVw4DBtj4GZ/5
isqLTt8VATwLsDzyrmYw2Z+YBK+E8EDfef9QD7mpNNhKo/aWbu5y03UsqodmT2GllfsOBhTynQeq
XtiXQ5hXH7K4eaOjohLMD63TKTkuqYSDnbPawHnDQ//6NJxm+GAWqVzhGsWv1N7N2YtmuZa/BDCm
ltE4NCP47Dq+Kma2c12c0Mk8FxrWEjgwQDeE90dZZV2mJ4MruHug4PArQC9ks6FuE79uoR5pVXqL
0z5I2MSKu9ItM1Q79CjFaIkkkyPD/A5xM1O7F2OldMB+EqSL0GfqUmaPj2r1CYi6qie4kiVIMBA2
pk9Lm2bQz/aiID6aD9BZbJjPFAB6vHXeFD2INrm35mV0FVA8gHp4sRkJxr4FxkdeKLUfrldgesQf
3hh+e4DBn56LChaMFO5sQ2FtwK8cEkHf3WukJFSlX4ZZUdtmdh2ENLdyCTlUZ4Fj3cA5RtctFgNe
cU4GGsu3pRC6t1thw1VviRS9vljIx9qdL2Hnk57Ch8bJU0mOSj37sZFqtpQSkSBuycTkPymNBmMA
LrVd/1lizXYQBgk8msRSGQ97d/gSXRk3pnGZDnGn9idqe/IaRVd8Yh91NnY3ckYvolNqAGWUJlje
YghdVH3HFsBzsmWPOAYlsG9fBoTnTslmQmVMGKlGH28AKsI+y0CpsutWWJypcAo02/Esy1xBt9RE
vEdvHa+dgZ53ec4DEf/qBbvqotmsxVfXEw2CueFxMUefCfMEBY5t32ZM2lXKq9tudj4o7weq8A6S
mVKljQeA4jqP2Xgfzh8q2vowfNqE6QHIRz6U21vGTG2qP/zcBF4xMVKuAc63rPOxaDmMpG/fe6tK
2K2QpqW23pq7JQ9VAMOOt/Oo24KcLxlHaeo5uvlM/9yddwgJ1DaEoIzZcY6COgAHOildgHevO2hq
EZ8EgxguZZUoCtTLn34zCxKhKJUuifJU2Ki61pQy2JOvu1NAvba+yyNP0es0wsUK5W5yYuiKzrlS
0u1gLAbtemzbiugYMWvLb75xD5Sy1Ri/sX1HL1hMsM4nFBxrJJfbrl0AO0/fdnu2eceV0rU2JE2p
3Bec8ngMHlKhnKlz9ol/uwjxxiUgCE013Rpr5aqeGWPowPvaE+W3juQlyG4JUcfPk/zJsZotsLtx
M74PQy1epeXv9dLeLIqpVjSw8MmZaoEGWZLMilCmxNA4cwDwxtbmYPJVWOzcPqQSdw7EcHG+aArY
hH8EkG4Sf16f4IwI55OPptR6x2AICznAswsChGmRXhma7D4KlDN91Mo+f5L1NkZvToao5+zloiTK
IPqMJ00IxKPO2mFdTlkWDaCy9m8+mlCB5yvjnB6kf+jq+pl17lKhB07ZvNJeJFoCHskhZ5RXOowE
B9XpSWtCjiEYyaIvjiH5yk+YEEsCTfFBiGiuW+OriguMEIq0minpURbmRVWAucI342Tqv4Fc5Gks
Oyl0feT7/PwrzF4QQcDNo0PjbjDpAi4GNESuKYmFscCwaRIzYId8ZyYU8qZcO07yI6c4+91oBej1
bOfsfdrvOeqDvLNiK703eT1Pa7xJcLMbngkpv6f4KTF/YcFSDeNR8tKPkdtXIAYYdgic93lmhOpa
j9JWJOvGvwTOef3apN/ZYZhczsWV4mGTJgQGyuzYS1xKcpFnxmrUKlyXr6Lspvrt7Px3sg33jnv0
fBgWsSQ9NLq2imvvMRCIWUsPiA92riOFnto32bvLzkb/9CaXvziU9cwXQwwGCLLAKn1y6YcIntsS
egi7TJR62UYZ0XDneOA/HP7Qv3Dk2qV7iCOUlflGxcnShlASR40hmu9zVVD8af91CG+0TLjVyAvJ
M88QPhzXUtK8MEK5xeVmegzLjUujr0Hdzg+0YWqyK2g8xxLyKdoxsSrTNhagVjNwm9us8I1tIk0J
3mGI4SlwKtef6ap6IyZ4GLeuKhveEvxXxJTcqHYcxWYmwojoeg8GqZzVeY5hsK7Ns+t+JD29B+3Q
inn8sX5f2NdD8HubZf0LEbKYZ4Pos/PJsMdYXLpZ6DZKavCAMnCy8KS3IDk2KyTRDScKJBrjnZb4
ighWzkvv1thStUzryuyCzWGrJU2tKWUUwsMNt0jQ3Goqo3oNe/xSv1FFHmm66Q62dufdfC9o+E8s
zs7RHZ6jqDatT2Rc7h+E4V1QmKhEJj2J7xt62ABfbyyl2FucweuupPZO3ldqW+il6DaFx4KzrRRm
kcLtb+5S4xz2Xgy4Mdu3P24inqrKvmIWPrpF0mWH8EJMDp70CwQiWhTM9xiJ5BJeYL4L5ejirpMA
r3+ljl/Ll4xVw7UvA8R7KrBk4EynXvmMRDer1S4h0KiIIhdwT0eJcZWtEmIEjOrzOPFIwglpDFMc
njr0ADwYEQPplcHdfElkMyZtk//3tZVDAZVwsKOGEDeYUAAKVdfDTtqqR6/x9XgbQ0IE0Kc3kZd9
95O2qUaBdYfWhATFXTiFJcKt2CFzMKJ1VX3V+pVUEYOswKO5yBnmHIGOrk2yXAKer4Br/O4rac1X
dsR5HuOj+jBgS1XrqIkzRGKy52QsS8CjDcVTSFxQ1fJRA/sj5WQGliB69MK7zHl0Unsp0mNFlS1u
zp3U+Jol30fpYpMguVomJiwKXlzj/leTICQ4yC5Alyg4yrORNlPA+/MzTd2yuB32I5vkgso7/tRk
JU7Fj8/FCvuCfx+LMuLFEIxzpt0AfujsgnycbqMCI4thqm2iRWB/0Xdbd1fAiZY8DJw9hnRpTwa+
XNESeni1lKiTw0IjztzEl6WKO7gM1sOsMO1tgfN14d/nDeldcmsWwlQthGCfv4VE3fpGKm39V2hD
1NRSzJiFpYDQuxg/drM82OZvX98fC+yYR9eXjZckS71Aka661ZdFs8XL7QrYeAhASZu0DADmyEiE
9IoKSVrWEX4F2gV1UkWUx+aG0GAIGKp3KYxTrKfQjodT/w6Hlf3HuQzf26sHdr51/eFfpkcPsxqS
oH/jT7KYs9rm3aWbyD/ZZa5DITdo9eGsj6T0256m4B9QTbkd/SJENznB8r3kavW+ZgXN7WNomf+1
Cns2zhxNU5zqyRPY1JGYwQdiVD/da7pXo2bo8cz4J2yTO/H73i0+izH5lLBkrQFcku1h0hX/Xj4N
89B0TiH+5nmj9J3HmPHox2qdLCcxDfdw/4EhEnat17HUMYUrhnr3S9yJFnFJ8+JOXGY/aKrsiy7v
Igee2liXSBwpWxhBq1EQX3v1YJuu9WvpxqXMAsrm1mUPouBq2yKFT5v9LbLF5UVFPrRNmcxnZ+Un
UNfhKRlk4T68boRCo/ONe/SxX+SE+2tP8I9H9YA42ktCkoDFGDKJAUSIJxp6aVbj6C3G4DCCXN6I
/dLOC8NwFJ1arkW9BW/F4VvHcznsjt4x8EnKMf1m2Y3w6J6r+EewCcN6vkUaJTo9C2xPOJGVM4/n
R7CaVMh4gG7FcW+JkSVts2iXfIU1/l1J6QImtbC5gZved2u7qHr+/0rtcwcalIebWSR2x/Pv2Vdz
TX6579wvzh5lH9FHfG64FZf0yBM07GJn/Svwcn+8ecNd+k8F2UNZnBcXBNdoOAnT3tKYQNlQT9C5
dpJeNeOb+wS4JpauKdaH5N7xKDLKRk9mycSqOpxw4uqpnTXIGtxIoKlZJdiXx/Yddhnqwterj64K
dv7C1DVUzgfUUxWq1jna+W1Hxx6u38zjSx7kkn9U/nc+qt6zEnO4VerGkCY3w0R5qAWkWUoDph5S
RVYY51IQ50PS3VUa4WtBtYjpFwQFIy15jbL5Orb30QGV2cqOT3sCK9MizPeRBQ6rpGv0rIkmcTt4
DS298E3zv+LcqKoToyy9oRzVDz2fbssDkJhof2j2auihDd/gY3IHu4r8ZXsy/UjwIt8rWXi7EZSi
MmTFij0GwACA0uiTc36sKosBDkYbnn+Wvnb/0jSAC8WOOWgs9FfIKVAGWtu5sIQIOU2T278teOqM
CbMqYL1YXGcCqz2MJewMxEC17Q+rU7EuNAccGh/MU2QxwQ90r06yB4RmL4MBK5R9izLHOeiRFMDH
WJ0q0dCU4QyLNjUQM48mkJKOTUx5DIYi03qXps7jK2s2qnLN63LX90gZGY52/lCoJTijuH0T5wb/
8Stga5QxcaQHINYMRRr+ab2RedqBvdWOZ7t8Yapyk66g/RK2TYuQGlamVxbewA8uyoQexjbuZRSU
JNAX9NX/OIysVQPhfjqiY+4zC8ysg7DiBdH3ycLOtq9Up0yH88CxpHkvemikoy8zH6ccDtm2xweQ
sIAYvcUUY7Xh7ZkmdB/TQfV7VirvnyA+eZwJ4lJXfCnGJJq2mKkH7EBEaB7t7YEakcjpyhxTMens
z0y/VGzu1heCmeFuXfW2cKPgCexIOTLVsemPTSI7fFOq0ojHjVV0JNtKvS7fsS6DrI1BfNcC85pG
aDUvHXCymMT9gLtqt93b7MC/r0bC0eQIFSbM44HZunpCIPPDCf4vuQbz3TuXjruDxJbW8NounEKX
WnDB+biky0vj/L1DYNzErV9GRZMgP/iVkvLAtu2l8j3CpHU8Bo1UjUi8kQtPUD4BboPi19mbSW7D
Eh+d7F02XzLYHJfdHI9iruhwg8aIjm/F66P5p5zroCSlxdoYN4ZFQh5CXTrcwJPJULXPZLtHZGc+
FPBz/B/JxW3LwGFu5UvMjvpSyil/X/BjLCtplWvdOnbJtlaumRoDmCem5Yye799p7BMh1YgopHms
wIyobEkFxCU3PmwjOPnzzNYi4knXU5/muAJ+CpaiTa0EQWep2O1mmjd//alySeTl3x/AfR2ArceD
8lnqIoNHuhyvRhvW3X1WV0fiWRBa/PNZjECwhQX3M5tjSVt56IL2axKkmd1y58Qh3DpVFhoqebk9
9SswdEp/APVF+VhY+f9V118FuFB5dmnPu9VA5moQpIvAyYvK6kifzldifN+5vcO8S9OAJlYIN0tP
iDIwEaAIc6Qurb7C7CF7P9Euu9wdEI+58MTGNwyvMNTRR19iezvR/4NWKrGFmJSJU392w3kCnvFo
+1OzGXb45h+/qXzm5DppmGu6qoHiVgFENrHJAXMD02sfjr7vifKtdqYPBmYKoOzaDqsm5UaC6n/w
MkEhuPaJS/k2p2A8jaCVy8Fx88sUoeWiGT4BJZTBY01ZLQxsbG69DW7uDc6y+EP6gooYCzgAC9be
jjTtoTcGTtTcUAe0t9ewhJjP4BhYEJhT7M/64kK7+GGrK2Uig2OiebPQ9ucXqIJLHqEtzUq9qpQ0
l0HUw6IKkJw0OIn7+CMShiu4SxpAIr9xIKsSXMdIpeTjx0DJPIHo+lOYQ/qJioUez5JF1SGgQ0QF
Dt1jStVmWYAd7EIfAosG0znOZq5DmZIIqdb0MyCt7mvIoarKtU/O4B3xfFgHXiDvtbfCCVnvICkt
GdvNogtEAcySbrB9E4JMdIzY1PDa9ohzqPExWQrZ2ZuQGSgYJpfjJJ3Ov/kWQ/ytwp2M+pnvtMOr
to6ekKBgkzvXR+RAPdhIg+PaFrzOYUT3PclMn/o6Dah+ge3rPhvOASgHwlbf8Wnton/uPWi05yaZ
NBpfUyw6bPgc3+j1t+aaNWU849eyY7SwKjJyO03NBPd2YIDvPgyZFb3Urx14ZcxDcBcNCDdIwTfo
NXxCxiLF0oGdAyyCmwpCSv1heQvWkz/jpy0Pgv4xEGky9VrFdy3AEQ3R0ReUHIZV+jgCTFv75QJD
hUUO/GHmi3g9fjm/MnhBor7o7Px9XeYw9KgUIyThSH0jSF0J8brfLdEdmvinyT0p4KUnxlA+AI6h
emPt6o1kHi2v7AwgqmaHdV1pOWc37hcM7G2FD/ki0GjMWVaSA7N0ZX4XmX2DdcUOs9Lq9+2QsGvz
wtEySHIEQdeYws6DYtiOSoIjB2WepY/HnJAc+/VpzYV1+KP4p/fw5DnuOMsjsmkbS+hpp7zsaboB
p/oqWyHrsFmH2B9FtACmQ2fxev+MIW5G/m94zLkca1/fqaBXS8EAOOqeThVC+ZbRsu+fjk7u0GEB
KlpgVk9RseaSsVSnPzqA+XAZhKVYrwLL6GtHxfKcheMHDAd2zA7ar8FEd9q8A2zB8PbaKY21hxP7
0emnNCpYHcUW8kp47cNwDKNyrWqPX+lIC2o0N7Pv38o9I2/+p/8KcSA9nLX+ZCRuf/ixmcFzPEIM
anhdEBTvkTYwovHzEPy9BLg96Wyj2cz2LT0XcrW0SlmiHjM9drF+OOeDOgCBoPFbjhOBre/4zOGZ
Hrn2gqmPvFqVa5DK8AF3MoTeFb2wrflJJdjVF2Y2kY4VpC5G6ZnqMSpFkciGzWJjuLrssNzVat3/
VssX9fuYNc1KJX3h7vUakXWNaWWNWWB19pKmnP1fVHKLcxNX6WSwlHdw8/yPLij4QryuelR0ww8f
zvBJkhLY7AlHepAegyK6RfxuoWFLG4NHQaPnBsx8C2POzCBmXsx+qDJoGFOQcyrJ+FhQ57k68AxE
lbV42PhLBJnN3EbyROX0LgVKGfWAKnKQPreOOu2SHUmrBjNFzmy/Fhc7x3hl76FILxtMdNlKRRWw
JUhP3CfMQs1aWMxvnQ/RnxErwlkJhs6LmHuqDoylihmr+3uOKTfa0r9e0LY4zQvh+KskCaBXyBmB
eUwvsA5akd9sRZaqpGTlc9xeswHX7FP4mE7scD4K5wrk7flxuP1erFNCW9G84IG6E/fXB8P4V8Je
9JIbnh6aJ1AMoMMHd8Y6LGgqTNOH0zbl8iYHVSpVqOfocjmmoVeJXFjxoBQdU6kZIi0jaklA/SEa
5KCn60uPAPbR67FA/1ZcyDBSdEows2ZAL2mq/U73SbdD5ieaHCk91f8tP16OWoyp/t/S8sbNsMR7
bsux0IyZA4JwSquVBJsDAnEd8/LNMsLpN5UYA/FrjkUNo0c1Q9+5bUTHkHt+GAbw3nNjI3VXVsqc
nHvqrGzwNgaZFVX5TINPqgj5walnpsZrBktg7ZfzzSf4Mzd532NpB7U7XZl60zCdRyYwYrvS/tMW
HSBqrlSe1ftQ6R0zIFF5CKG+fe8WizUzg97axeKF6ttVtfoP1PoIDpnmQgRMcKQaAr1+9GW0XuX9
D/kZf2Rfd2P2nyzeppu0z9CtcvtP5Ec11C0ZXW29BvenQaYAmkAiC2CofD02g7TNcJhEbIBPDpYQ
h6/SoWd+35ObMH6X1dYAX6c30X6ez2PbLrrLtIt8GeXWZVA7neiq7ncjoDZmC7IWdBtz+VKSbAPZ
ZHvqwnT7u0Q7OUC+n458GVV7sZR5RvAp68YaBrH/gmjFigNEMXmj7uqbPhtB4+exuZbRpkjA+PGT
tnzIdiRLJ301U0ejn2A7+q0XOSr34EQPYzBGHsB9KdXBOZrLQD0oY99AFgLniXYQ02qbfalIWtQz
VCjdkKW4K6QSN/T5c/oKWwRejf3b28Lk1yZXAn321gGMXyhCJffIuIfh9JQPagbtxxXMYml8NN0+
UfoViYFaGj3dJPv4EbeyBw+cAf2UY9pHVocaD4iz7IMPbhlkkG/h53U/KQxnhgJzgc7yczenKqFx
wRWrljds+FU8qoc+I1DdXVYEZ3H9sHK1C4piQ8Mt1UNchXOAS+NBLyYY+9WA/LfmojZgFRtPpLYl
TMYdZVyZ5vS4rgIlJw/zw3jPBepg1ahuHSG8Dsl/SHzfPjSBejNgv1+La3PkOVbkCqS26jsP14f8
Rcszzkiof9JXW06ZU+VO981AVb+FLzVDKVeSLTi4rDeRJYdVsVy20Hwq4M/KNhJKls+eMjaiouNH
YITn5jHLvjKNQCP6AK2p+xC8nw0TP3trCX/FtON155LM31uLnRFebKYsbmN3DvrG9i892VkjzrLN
wyYN4gps/1aSAuKLSdJtTil3SIePX1iczYPSE0j5Io3SQExWV8a0lrN75uGPKMRCuZAhCGw5U0il
RwFxQyB7VVXcmhSIIDUgHnkL/G2TGfKuhv5sCEyv/kusmF9uPxWy7bq3eoP4mBl/19HZx+5pxzlx
AOrWB90D32keJcS8KezML6D7b/8vFYR8Oz6N5M5YF0Ms7/WlISBWJwI2EScVYpU2SeU2o4rJUotJ
/HkM1JyXQQIsBXWMm1W6HpjkLUzoD8J39ABTZqoxZcUnIqdxGBGifQrgqQB/lbwT0rAxUityU6ur
m7M/TZ6fBUWoUsELAi5Arb6cqtII+lfmqwbfFu8yPe8uZrAOCSg+t20xwKamZDeLG7dywUksyq8r
VBFs/VhpLiU5X9PijdwcIcnjByWrDPGdfxpWnjHpl9w/yRE4yLypZnZ4XJdTyoSl1P9hYVPm8V0d
YAZ1nNAkjCQP48BpGv1VgrwMhwS3wD2BGjlV12flyB18+hL7VrsRYa7pRDeuugjtjkBO/187ZX9P
mOBL2bhLSv3CXTWTOHKmKAZYL/26uz7Fe94F1NXSbmlzw9ddyH00zXzFIVGZeoIGsAvJsx+plQ75
EEBI6hjmRt9PlQxFA0Vfbhg77do+fDguJkuLjQmqi3ubQ9p3u7wjBWzzYqb52xj5j/xgwRBlXDl8
X94HVK1FDwAs5lHMZhCVpOU4COlEt0mUmvXg3RroYkUCWf7E8R/wBdt4ZOn35yVHn/r0IVHrSSAL
80BO0XjCoTqcfTbTQ2vhpVyNKhxAwHUfu0nDOMGgvjDZvgODuc7+JvjaCQHGPKVaJIQ0V+MiNac7
38DbjsYoR3eI/U39LWm3FBA/1yKXX7cZcaPKIa8cvPWruZbEipm6aqMc4u3ZFMEHTz0Hae/wyU18
kfctFkDtqFehvysuNFlyWfGw+OTkrsA1mnlA/8v8TVXBmtfdTqzjrLezcMAaPap9zncarorB8h5w
zz2jShZ5pORfw5r2+PjaBp3zDigozLIqyw2r07e3A0mdNCmT3SH0iLkUnkTU1Ctl8AqsMuN4Hcts
dX+iAOo45OKNFdYDPdc+R5mLluLLbOL5ABwfApJdGqXqWMVDvp/Tf5YgykJqxjIzpoLTqJ8QOubL
j4OIWrMQX+Y2t3mjMu/xYoyoegP7Db4me8LLVSG4XrruF04aIJCprSCkUE4KvY0kis9Cz5SjUDXc
K1Y6+mtNaa0eyYZytJYiigMOy7q1jML4sTGQXeVcYGAVFhE0e9mAjqBOmrhtsOaKYc9PN1YFxk1M
8yRYu3zWo2gPDgmdise3IJ2IIdjmmgWmgSR7PImGlDCd34T7LDJ5l4QmhrternMcUbhq4UAMTNbr
movOkrX3mDp+loArmXhh8aKHYiZUMvY9Wc3sLD7AVrS/cYcZl+P4ov8kqtdNm9FPw8Ut4aZ725C1
048gfix8VCP3xZTE967aIdyIyEutjQ6B3XlaGTGKKA2WAUF2MZRES831jGrz7bogg6nCxSNxjOh7
OZG5k5ZSrRrgcrRqnpUwq55hHEwNwtrYzih1LBlB0KktCVUFulPJSAP3/14B8HThUpSe4l0lBa3P
+ZgIOxHcJnnKJT7i38zGRwO/N+ypXh+q7Kx2OSGGtbbZOrZCnWSM2CHXkVV9wZwCPyKD7NQUcBcd
NaZy3tZdCGVOZvYYpHQHPArSQ9zjYbMeWZ1m+WiPh7qJTVbcFTA/Znq8z7B+80gubQ9drEk/ZFWf
MPN3ryzWbSkThTg/taydn3mSE+KjKV3IXO/wD0TDPdDOCd5E4X9TKiunPNqawQ0xv9FFyXyxWkY/
yMsxpPR+X5DLfWQErgxnt/0mppL9Fj08BME18i1/dOgBpFV0u6xb6ScCIai3KoWVMjPP8+ej9GLB
Z2iY2E+RhmB96hL3QF4HtJ6DDLS7cOrJPpe1KKrCOD7FG3AKa/XznTr17m0cRez4/20GhL569d97
0slQGkDMOXXzftlcXGDhgaq2fj5eiw98GXEfaeKqdPvAgLD83G2I5twRE364hAM4bbsCiEhGsx6f
LkhOGiHiUyrUkDc0vFdADgT1gWmdVqj5PVAiSRrsOAAUH9z57byxhXGgKX8h6BKItTSGtqFhQDt/
/fOpM6rmrRLqFm9c86NYS1KF0hDXPNP6BSMxiYNU5zG9bde7cHEgMsEJnAB/JYwy3KTIpXzNdkuR
NRndYUtnEya7Nn/gZwVchCnoFAnZzJ+H++u4yfQetacpydwXQHHAnjBrF6o8W5IbCQ3k3iMbdIcV
P177o9EI9fwZr4fpyqTaCG2uAfPoq43EbIWjm7R8/f6txrJXG9FB3xcHh5yzO8O3BNmpBJzBdfH9
XMuhjU0MQGiJVB0g6nD+B40FujuLMyTVBmV/TC7DFc3qMw3s4DomdlySCfgNrf65eAQUicb+tRpJ
EzGXnoQHrSo4T2BAgEAIceRNvDVSmf/eZwYmt7p9LaIFVLNueuZNjaWhW0PVZYGzI7DkGoB2F98c
9Q/AP2Ijo9D+0q92kk8FEYHA2SfZBdN3XLOKb9ZfwA7UUr/r6oOSdp3kYUMwjCxtyHVEebsZt7aF
haWbiIt+1m73WJdyvGzxe+uJk5opCEdc6Fzlu+spSo/mwC6oiDre2b4US4rH36BG7sSUeYS5Dndc
oQSLG75JQsN0wYMombpjkeOOoypOFwzOD31ZYtiD4cETZFYa+MfxQWTkMEBI/wdPC6KU2JkDVa+f
qXbljn5yWHNxgFjjqq6yNKZ5Ex+Z6XXzfocx+M67evMNcNnjz18gcJmynxWNCtets0h7htrYia3m
pQjp7mwzlAqqTC3XShM38NMEUcgxiQCtzR5BYnhLNQB+Dfq77AfiE1NbT9HxkG7uy1679DG2/UBX
yQbbGBnxmlWywGr13fdtR77LuVeHnxFwEDqgROAL1KAhjZNl7MVfiyfdsFBhu8S8XZPinvWVjsT9
nPyrnlDWDPrzSLBEmRqBWyxV0T1QMz1q94RMKaqMfSMrT5WFobxh4H6ad0pCoQJ/JeiMBx/zDIsy
xb9b/Ylh39Nwj82k2FsTzH+fInZCWdEGhscDBMO/DRlKQ7qWqpenrz+l92bKoKKNuggBUzuHbCLU
Ey7U2SMTZaHfDRKd1kB2LrXjnnzVEyKMu0t0ed7rewS/2U7xHQ0zYzN8k75Eas6JllRjLY74lIPn
pfQs9K/nVax731DXq47+bHSlg+hu+IO9NU3gF0I5aCAREW5Ll37ybLD7/JjuiBjhaRss/nCYPRQI
RHPtPuaEsd3iHAx68hGNq7Znd8TVCo/jFcYunTxsSFOk5w+aKwr3wiQFqRrAPK4zXgNCKkL6CUHt
p0wCfmEbRE6gP4MejRgx+kZKbO2xQZwjG29WwRLoxSCDoxZPv6jcwGmstcmB7xLr8RIA9tdFD7tO
XBx3d+tz+xKI2kCiUYJduYKWxMVuSoM2DI93tezUcJl7OghJMJoefWr9gnWZNq9LJjD4wv1XuFyf
clsM/52mEOqBxXOMwhqvBgmuyCC1zBpkgZpHCxANfB28r4388hR3Pb0cQXQ2+l0G/urGOmM0wO5l
H3dSvvwM0dj4f2RtKyrZT5pkw7S7hQfTLh+Re1Rv2nD+pdvlla32/MMc//KI22rJQNpYHiiN9V2e
kav7StxgE8ztQi0NAfuRewpvfwjBYk3pbYcDJPdp+7ZGnW9XKfKKRCiUhIx073AlmCz35PHO0ssF
dLea9lyAcNMr648VPo/ZoccHQ5NJH7HlH8v3rg4i6x+rzxELAw21oXTD1Ek6JvGxlRKO3kaBt+na
1rjqJo7rDNutNGITxL4WNPwRL7nD5ivlqE9ksO39Es6qCxrQYDy4Z8iXHL3zy9nRzYdzZdWL+/28
0WoSV8E5d0PNPq2yNSHxwKdIAh4dk8aYKT4grtILOAsJoJHVB7GxtQnnkc/m2+uz0RDqPQx2Pjne
n+jLQaYm6dURRwk2I3IShP7fVqBVpp320hMHkJZsW3rrf+UYDQXAhr6EbcqaYUjz2gQFfgETgPH5
2IHIuxUO7t+ABGBWK3KtQZBbxQe70h0ZJDrNhG4UznPYuhOT0yt40i5jDfxQ/tf9eK4+CMc91m8x
U9UsZAwylNw9vjGxy0a02u+MZgyIbB456hMp+T7y9YwbVd1Sw7FjWzPs/zCCnkDjzdxGNOPJVaOb
xSJY0lZ493mdke6C4TMdJ/bzpwVz4I92ZO3gXBVWCdPyNaQ2NYm/wHOdAfRX9mp0J65zGhOjkrxQ
M15QsR4TyUfZhBzaj0q+760TDL/Ot2h6NGRQB8ePKnRiXCD9XF8I5mdphX4zCgymOU44AwNtzb45
GU0dcjNYsAXrDD5c1sBqlF9DkVu+Q4+lPqsz4jMOa2wH37oXtUnMvmGjzT5gaMtqnlkIylbAuOj+
L4HrNzJajlBgawi7/VNEW/oGLFarRK85fkGrmVQVrIZW/ws89Kb6WZ2mvk/fFDj/rRh/gJzOqC+O
lpkRXVI8EBUGhmnsvy56kxjQUvVgal7FiLe8E67vgdYEwSt+m0KIQEhn7tamQddOueodE7uGd92m
V3IN7vL+olXmd7IRBYUHESlbx3UZYWSwjUW6oqW1ykgvznoRugKQ0H0UBEZcRWcFscRfo3bzhJUE
gQ7O58csNoZlXA0ev6w4djvF8HfGF3z3l2Cpt+/FtS8mZkqyO6cPzdQikcD6XuxqGXN6800l5w5W
z7zRVM96dcQhHTVNTRxsLl57nZOa0w6NVR1Ohu9ngV21bXy+sWXtvY4NYJ4kjzKoEuaADmpRcDmH
sKvTJuTei0SQqiInlsxtB5bV1WZvE82dtMqND3f2aimJBzr4TdHx0fi8FN4WvAZyo+NXuEkv6A+R
ru64gqmWknTupcrur7my3Eq5OlIgRBrm6+54pjjOcDEogBvpDdh5WSiUSW64qoWwltJvmK3uiKTn
VQ6yCNLNSvLjpOMXwOJqB6NBUR2XiS9KOI2BcK9KcrCPIge5kP3+z9+nUTjtJqLNhWnvUmcsf4SJ
aREWqhzEk1TS6HFO7NVjnIN2NNajvcCcT0vEeX9gyUVArtbxVpG5l8rzOt7NxLzaCR/bWI6vf0y6
Pm3GDn49TXB76wOchXiiUQcp5RsZLwZiOPki4qmoLJNh6q4dSuXWVEeKr/jIQ2PpkfqiWTz9Avtn
2PmzRLWYXT++ZAE7ckkYdxCAeAC4DZkmAxQsVLxVOg+dG0Ee8ee2mkxXGL+nsYbhNFjGa8fc6Dsa
y/Md48O/8uIRbI+xVBFb03UBeMyHrxye8qsSvt/aAvRAyuwERD2swAUR2eYMtvbyCS3Npl6csIhk
Tj0gL41YUhuFEy08vEvRIb14MPYw6dSXw7CfaoxjGTIX/EZ0pun0Aa8ceJHYiPkQJSn7UmfcRIv0
09hq5GtdLbhg49/Lm8lWPD3tSwBPwg7kB8gnyZQyxAZnAECQeGHKoFSSMY3aqeHSVMS+5Gjx7dro
MBcbVH5K0v7d2282mA+NVaak3GIFPVyTzjVnFtXYRFQDZk3uGIOt+yVOKYWSgFdfsyo6Y+SEDX/O
QdBHtX5Mhqt5xTQnR2nhj22jvA64NtbeywSqN6bu34XNH/HJKYPDLkZJfPuuVsX0GlEN1Wxgzq+T
J6dvDgKx3UuDOxffO9WExEoANZ6Hoc0uvfsraaF9pG5X+Mv15q5xZBp3JptpQAQqyLmkRjrwDmcJ
ZHFBDv3YpqIaD5ekxDXmTa4kycFQELPjECvyd9PyXf1xBgewqMoAxOEsmB06Lj3wZV3fISFdpiWe
dhrwKtSVS/Btlk9tCybWgeyrdYiGMPGgyv05nJPIHfkSdmiJ6jPqI4vyQ+lTlHSsS1IGyQ8PPdAD
Kvc/cCEIwdzXvithe0qgu0NaD7FFQkToCgzTYyi+EgHDGgj1nw4jnHQRwXBOaXvjS01w0LO4S3y0
eULVs5ycNkY8RFa1lIWCbpI4BI9uQwoOwfl9fJkQc45vCTKOkm8wfYn0XN394uz58Yi9Lk64BYI+
b9VfFbTZONNNZFPe+jpEnLTXeruTFrptLiErrWmBWm4YtSkuVIjntUIR602yndUphPVi0ikm2PqQ
uAA6aofZiIvJHqKaEMTzMWiJEyAtPF9LNC8GiIsKqN+W4Pa02CJS+9k2Y5R7XIKWSFfzVsyFYn75
TBnTc2n1v9lwcMKyFgPOZPdOLXsTPgeVnVCkTY2nDw0F7jGvXn+TXxpkbUCq8DGnQah0aKUDjZ7P
YPBJyulRYe37bPP7idzU7xL8reie+EAYdblW246b7Fv6IHvaYuTNE3cnrA==
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/blk_mem_gen_v8_0/blk_mem_axi_regs_fwd.vhd | 2 | 9545 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JwdwTKlrHwgkvBbwH7LntTUTFNPDpZB1lSDxpBPoK0DWPN7zGE1FP3dnEjy+jYza6V6pSy2AGJ1a
0wVLVsSbEA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
KjGqPf4SrylkHLAhhgwiNHK2hHuUjQgOVdDdCrrCk5pEoDBXQ/WXGHBs3wcX0fYuAvReSTRsI7E/
mIMqyltnAcQeJ/HsZXyPyzcjU8CSiRUEPpJyoKcOn9TVyN50RAc4SVUSyn6ppbgn+4qGQgDc8sJQ
PRsnwZLnTOXJPq5bTdM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eERgT89aNx/J9zcV0PeNXPrHfxzezlg1erG7X3LaN6MF6cECcWip/MSAxOjvfi1p6R4n3Xp/T0U0
fKNMlj5TS953zEo+ckpjha/tRYe3WgNn8iADld6VLaLCXUbWD7ulUilQXiwbS2pSw/dmK+vIzJ1b
4yMDsIOW3yy1Y9cebn3TkU5IxMHp6JQIh2e0TXG//09kCSO2nSk8IsDi/hZrcrUAEjhXpjTuJ7qa
TF3mZouUf+EvZA8VCPPKHN+vcq/KVmK4+J4zoJ9KrXT7cED/97AhBQJJO948RgafMJHuSTz0fRcu
TcPqIwlvoo9hMKjAsJhQO3y2PjZ/yBpngB090Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Fwh5lsoqJZLexlu+UAMXPOwaZkCPNyFfKXicqepxBdP+WJPS4D1VBOeWUH++tMx2Z2X70ntY4Jj7
TJfbZck/K5Vo012qGy7G4e5RJgN5OQD6NaSn8waZgBz6fG9Kt9XEWgVWif/1flJHPoC5Nu7EztZM
ZjEaBvUxY6zVZFA6CEM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZmFg5OE17jzss9M553UQlmBnYojvcQ8fPEW9mRHIb++ZQmGM0vN4p3DGVmoTd8svZhWMopk72FA6
KLEy5aKL2/oQOlXOkQdluObZHgbjUAJlIeVCAlV+rsRj0KOBSb7lVS8/fhZdJ6R0o2UX5XXgTQwu
k+ds7WSqQAN4JWZZqmLuatZ0jtB/w/XfN9rce9U2uySqT7q4FRzQ/e4VvyLIxhxUazYwXf7/bViT
oLkAI31LO+ibTaqyNFhcJN1vv1Z/2okTEzzpjMI3CH6dwhFY6+/07FyX7mAf1kcggv99q1Mjqv4P
k8VhmfluJL4AC97pw8/UFk5TeeFbKw7LkLAEvQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
CokSkHbYROyWXZPlri5gf1aH3l817oUA0wKzggiijJdsiITERjKWs7EvYAUjcTKDwxAnScpb6Qla
K+MTaHe1c9qpIerWp5DcWFsmGnZOcSyffFKsu+e2HOClQDCsAwCzxxKB915wPbY4x2GPBdEqfS0u
kz7c5UN1peX1EDIAC2bggPDUCIuaJrTv7AC+3/d5q0yz1DlJkL4UC9OxP8KIFoiF2psXomUWKGmn
KzQDip1uTUwCHuKJ+IyfGRoBIj4j/ou8DejTi5+KwQMwD5RbRIepd/RFvD44eCSd0xWMcNlzkiXu
CUau7aB9q0EBf58BqdmuodtwJ26NBYmVbWH/WSJYodjUvx1FSrH5m4f5TzTBbeOUlzk9ZEWeKCHA
bJI/9KE57RqqaS8U024jGVSqBo+6ryQZcZOVUTUQL8u0ve6J68O6xyomz3bzv0uXCBTue9Gf5yPN
bZMs65Vb/Rl9V7BC+LuV3wttxcbqzsJY7hs8vsBpHmgWc0KpF6DKqcn7i+BqrDMgoNO0wvvkWo6d
Zh0MDPkdlmKlBavJjsMfjb0T3Zu299XTW0EWZlv98l0Lou9pFnFQ9+aS81J/Ui6dm1+y7o/+HsoZ
x/vPSKKND6xzGq2gy6sIBCukpHIAkgCwtEfcOfoX2mhXMXJ6V122z3PJ7/mpW2nr9/8mCPvw+Oek
MbnpILD3l8iHq56pvG3lXA570pD55+1Yu0jmhKGtZSRiwMs+XAKQWzZJvR/i0n0e9yyb+Fde91IF
gpaUCBV0mbrbPIvyxYmQ57Uk20Uc8O1M163BQc9ELcyEucHspChD0tbaEucUr5vw2gqtU4dWLyqE
g0gnIUvWBgVv0QKFYyqQHSTre1WAn9fOBRqBi+oiqFTp/Ayti0Ui6O6WgPmHAVtEwnP3wuiIGSuv
o8tdF0D+CWvUWah6y7YcWr3IMfDOKWSVbnPrPhQ5OgNEMo0Yh5EZg6l/8w39Q/Z+YkO8Hg+RKybg
12V5rXZHZuGvSkMv38rwzapKEVUoAGo/n/g962s/z93Xe0wA2UOYjsV9tISXcyO20+RIbgssVgVY
n5L1xS0jiOFHWQBFNKwa6/5KeIIabCgaLVTzGOgyt+L5gT7j3SN33QnU4pFGEwAW+7z16sNzJgJI
qvCNCIOqIuPFkmsKGmVljjnokGXN+XFAIbJeQHFLQC+GA8yIMES+5TbSJbwjBhDnoL3aNbJoIhSX
E4emTRRSmyte2OEy2sV+spLai4s1f2ZWNJtX/eOCFuecMoezsBuKmLji1gnr3gl/2/2KnQDn34Dx
/yZge1EEGI8+5iE/hH8fHAr8fMb6bg25l79YABlxooXP5xuSxw5cYBkAwzQ30h7NcTWRPGM4inDh
A+qkJje0xoyYQdXRf2rF4VyhqhSdZzMce38Mn5wl2yarJgql0xoj5OsuH4m/LRJxCGvnhQtSShwF
I+1Pi/zwKkZUNLSirxmSbtPVydMhuqgDANKlYhpwtptQkCzVWLefXKeNLmLy2zBLl1GQMqQ7vwbB
VZJIH2WuSyObPHFCIhR9P143bQW2/i6DJV2XdcvErwqzAOAcwjVLNM27OhLOjEPZ6wYs5ZJJS0Fg
zlSkjX0p/ZKbrUVa/Zq5hWFVXlUU9jHQWZN+5dvFRt/pcf25WdxINi9/4XyG8mj+oiEa3Ye/x0JH
KAiZTO+r1/YqpISvv5pYUfgkB3kKFyNI0VXjiavPYCDylSM+qfSWVSVRBbGqtBrSop6m3TmkfBIr
RfreEtcjZuX9nZLZw6t7d6xL0zXfh05CKYOYeLjHcP7ofd1N2pRHOi6jORqQg6V/Wa0CfC6TBx8Z
r9rT+Q2GSLnf9qPbjNe0j3YNWo/IMv4/wKdsL8+djppw/l0GmQGcc0MJDsJ94pqmDUvSLbyQRsZO
K1mecGygoxY/G0bNGRqz6fHsVHwJlCJnWPZbLKxnEcoFlCrbQIDDtWptPgB/NGOEMJFFRQpCCQvQ
yZCfVC/bA0o+Jyb8zn44wTYYC1IzR04WaeIaj1w1DWWJxCZF/vY4BhOC0HB5TINl5bFocm/X+ywb
vy52eUI4vR6OI1B4Sb4Wmafo1oxDvxubN3OHqlXjrgl+gsSclSo32AH1kyeBIqAErEtGbCJR3bRa
x981M0V1gd90jsKV9WVWEP7agEcjV5KNVGolEk6CwfcgGSbAwcgMCsdXB75emtdiFUMmBpXGfSX2
EnwJ4K4M1qxwro+Qp+RNUfsIiUE24exezNklDFqxECp55eqmO0KCStKU2UcXtfczwpqBX7dabi/Y
mXeUNGLnnwJYkwnpcarH+iS/3IP4v4+szNJQ8uD1g7NL/52/y0uSR21o8SkL6PJnFWSqpjwqAyR4
CGsn4VGZ3yoxe5NZkPFBTbBH9wBc5rwOdM1Iaw1lOIowXOR4mBKxkAmVARSjDiiOVanwDEXNI3lQ
X18+UY09GJQl8ONaYll8jF9BXGYQeIfmQ0titTGWVueM70VMfqQPd5hrXWz/GAe3JvoSs50qz2hF
9uhIDCQCvFVQqkkSE83r2ZiJCVnlzpiG0PGDh8eChs1xWe2HJwNiY89mASBuURmn+dcyaac5aC2A
jb+6Kg/xhnTLx0xO7QtmM8kDSFFyXNjPzge69aGldORi8EPVtlS8qdpG97dw5HMLFCvUzSBP3dlV
8WCh9VfJgIjTd8ijDAeqHRVh9duhqiSRL4rwWFCdYuC9Ysh+HZHuDlcnJcngpqo/Q0aKKAJhf/P0
3yQipmf6aDCL5WOOxtUSMdp96K/KDOxJZyaBh2J/ACxdBGb9IyaafcHPyhZ9jaDv2m/PD7Q0SgmR
f6MvaCcwiCEwPWtvjiADLRE8T7HO8Km+b17D9RrlduGYalfJ5ByCg3Myhk6P4z4cUG9FnMil+sDd
Ihs9WMrSZ+uQo9XUcWUepniH01PVYZ3Xanv4/dHHQBrymaTDCnqK5fo52aj+k6JkhEkngP2gpgbB
UM3tI807izhgKYFiyUEBxH+71NgBdQ5DB9Umht9Hw2I9okJi+i/BMYPQJ0oiBjUMrUFYQ5GtkcnO
Ddl3QaUCIIOH3Vw61sAzR2IBTk43Z97gG94upzN7hi6efBBc5njVbn6OVvwktVeeO8dvJslf+xBF
fZk8/WHq3U6DX/ntNitbV+dsxXgI0HSYbEQ95TWQxsYZ9YMNCycPzQXRRH3v1q0MbVEl6PwMUdW6
+4Htjs8pewZTbpdak5nLZFxlsT70US04iGemAXur+3RgVLVAo6QCdZVh5oiIhOia7UEqBXIy5uIC
mnZqwSg2q+/HDwSgpKG4qxQtOscozK8IWB09E4kivnNqTdZvPRmDSzU2KLTFSKplc2EzdnvcLkNm
tZeQcGUJphJ7jwWT0/j5qOFOnIl/oOPx0R2v7W50TcQBG9B8z0nWQDglhLy9Pqpzb/dfK/qfR0uH
8PRnkEsORjqr94HyO2guB5jc52jsfvx4ZbLvpkyyp6cmS1I9mLfm3AV3+RzNElcAzjnqJ0X7gGyy
RhYUp/PYc+MRizgi/PRUZKSI3KVqgez81pfRlT1gkyx61Zq9FKCqAPvNCSzTMkSt3YI65C4z/jdM
dmUOXHVNKEY8BAo9IAn6Eesz7A4Dbt77dIZ3pysZVgGigpUvO7RL6oOe8TaSc4cjTx3AAwTj0cBl
uPK7ci22XVhriTAt2Lv7zWsKiyEaI5s9a6X9TPEL+MIQw1IgJwPi4EePpRQqrNLn/X78SlOR5vgM
WHtH3EfdBbpL390nXuhYWVpGpw+PPNBvTwD9FjthCFI3gxebYqo3vlUPdYWPTs7RsrpSL9NL+g5U
TRonJ2ems3+v8Y1BKyFk961cd0CqTrnRYpUT8Fe+a1UZTlOGTdCYYZiWAFCQC8EACBwwt7ItZhzX
J1F28cyYGCK0Fgd0FIgL26NFtoaKUOX3KmsY85pglt19Ai3UrZA50k4A7aC3dK5s9mf52d8USd0W
mxBM01HFVzNAlH0htSwm1RLvkd+XHk9ZqN66h6+7bcrHN3366C6b6RYJ7viP2v2BgrZ62M8KvC5u
qWUHqUAfdsqNmVOqvcerRSzbME3p4uBIyY4DytFInB839S4vKYznO3c/5tbu2xuMhZ94BssDjQag
j7PwEV5cvFre8/rf9KMjYQzBV0R2NQXTvYd+S3QnKG7lt+fCDdKAAMKBVjQiaIk9aVSvCkdLVL4I
y9KMNN6rKthkrLfE600BgepdbhcYoqSNILpxzh5glYuIOv5w0wdYX/LQ/U8nqkKObOnoL3wUy40V
697vn1MbKu/38wn84XBEH0Ndw3YZm7ccW3+/zNgwrFSu4mpudBVGIA8YxkjSHz+k69mvHuRlf63i
U/7yoQNuerX4COYzom1ui/GsxsaTwZ465yK2l0Vu3icNOT6qYqiDzpj/v88A2SWHtYZuyohk/cRp
HoQqirSy1MzdYUnci1+NHuXHHLr3xzn6ZyGUX4Qz0ukNeYbfE6+jsbZsFz30Tw+5Xr4MHUGo8dp0
5x6lvPbwSEmbnUER+jWLi7yAw7KackOqC95Co3lLKuxseQN6SOMNeooW709KOR40jh8KgNV7S6GI
NwPCJLgBsk9HooDPDxqGHjp8QxwViwr8PQaLNNqCS+w0D3xIU/2D+FsZRxxnd6bB8DV7kHbmllBT
yQFfZ0QhDkltrqPZKPnoZqzq6ddBIgl8FiUUh0jXoDlMbcuyaRA+cw48YYlIJeT2W1dpEfTpxd1m
Lwrfb1f1XT7BfuRaJQTsF5o7DfLPTgZrVpts6a7H5biKjJNgqu9654bEBpLxjeVNFXWCMc22UIZH
LIUpHw06LopaU+kTgc6JR/gOwPT/mmzUD8OGKDCJPpndIYxopJKHY9DKoKsxF1JbrQa6+gt4xHTm
N3zsKWfPyZvtRPN3wt+p7Fw8j4kkKAjZ0vx0C0RBMnDCja8NlfpmGJ0x5MCTo1fCxHFzirXKPxwN
NRhHVcvSf6Tm6ewkDs0prGDtlPrSbJ2Gx3TMcWLIPGTl3pNoe+7smQHBq6Z7tTAhQ7489vcwfUma
aPh+vwDmQUaM9z1N08BLp23UTQSCvx12BfdHg+s2WBICEVYyX5v0WHngyd9DYzV16XQI65xPw1jf
flMRLtsNj4a0NFHFYbFo2bG1LqZiFAnCVz8CnJC5xOv97FQZn048PoTKH4GoypClO76qvBs/4inr
8OwF4smYbMVdB9XQxZLaBr9gkcTcUPnyYZKYvsHmopC/DtA8EHqbXWUNjN2R9SGoY6JwFMzOHivC
4tWgaNSDUCykD0xJ3+hKZe3WM5+blwm/26rD8GI4514YHPqF8UBevOKqayG5FquteAtKNSQ9QlB6
6vw0CCxLYou2q48Rx/d2ANdpUIjo4wYscMvTaoDQsdF7w1m4TnAw0a8WGBR8lPLFg4hOj8YZ6w5g
6BkZjzH4CSzYdkfBAkW2zP28IoJ90eoesSrjuEqP7xHPRpFcprSkbmN9yXxdQgeDW2lGOsy1P/i3
ryZLGlgVPUae8wtX97uywag8pl7M9XgoMBYONKwT+qvFN2StwC1snS2zuW57UKg6D+vnPdYARjYK
c5oo0SxbwSP66zzTAwekpddCEWTH5XjvO8dzaTGStvBtlArPLb3elGzSoyrt3Ohdp7A6/TYV3gNy
KfrD2MakOJqOt+oOTlpRCFOWEJZ8TSPCADP2JykPzo9jks1g1T0v/L4Nbzu8gj3IvaHQQRDoDjEu
V9fhqa6C7SfWzEQpiNQfvNIDCxpiw3kKbDTq2sNn4DiJy5WCpH7gLbuN4Br9oRnT3CsAed14ojKP
rLKK6mReCeT/WOzPJa9Uw93f08cD7s8IiV9G066I3TwBfvejqfnKJwkHRvlPEwVB3oU0+PN3uTAU
J4dkBAcvgVDKBvZqonoR/MjeJo3k5tQAra3t+AtoRSTGZ3fxgHAKro32wCYxrLzYvo/rO0jUDlJM
34b8n4MH43n8l15oCOKKBugfGAmvhAi9kh/SdVL5ivdqq3W0BpKFBWb27HYQFBEbVIAvNg7A2EJ6
aAlS2lP0gZVB/xBDAnzRMz3a9RJQwpsGJnCTHRI0iHYmcvtdnsIfeEXMHqe4+ad12aGY+xpFxiMy
ZlCXyAR31xQS3zeRSISp0Y3yCaBzycPpy+WBYkSpPNb8Ks2MVaaSiWFLTENEFMp3XINogG3zffhN
vZS2a5MxBXsnsmrNA1DRPrQsMZUrX/9tLpjXFmK1gYWBjbYkSphi8ni2hlg2g545EXerpsxAteNz
w98VQl4APcgd9cjhXEv5FcpDfSM60RbB2AYGE5m1sj4JzQ/GsTmF2j9FmMDHdNVKW0L3dGjBeHM2
4h/oQJ2mLuJrvKdLU03xJCBdITezQKwPSEfe7AdffSLAT6tYzNsbF1ewPB8mR3x5ccgvb8l+rAyg
+hlXkNTazhvwyDSbFJtBEED7kmKZmjyq0eQ0GnUPhcn27/1Gj090o+hlPS5dh48s6/deLZEbmhO2
8NtwoEN6A3i3BALPtFewagLMg1znCew94GYP9xrbKuQl3w/xnMFc36NaMj1XQn3GuOI4FNAHs4V6
wmXHAUhyr+DdrLQDO7b+f9XHrgQyBbFerOSJs30kYleCZ+NpwUzIt2Z4k27aPFgJxrGiucEYMvPE
vnr9093k7vJnr0j1ymGXvFirtNqlkShpkn5714SD8ZL8yTY4yzlWYTFbKcG1ezvf0iAJ4hf/t2D4
u1fDEvmRAcqSZQG+GQKasy858c8GTtJ7PT6WjyiLoutevHOPOJrQ9eWWiinmKtfkqk9L3akZHmH+
F9rs38pmYNYORvGOwJVlE/dH89z2Lck1REBuhmEIla9eMRH/o6v74Aw+UqwO+VjVV0e9i2XhSODs
S7D6NgxXfXdBGa+THHwQYkEJE7AMo/JogdDNoUP0VmARuN9IHU5ZS2EbmD8U9GGr9XSOTpzPiIB7
jmqd5LIr8e4XBR2+qZ3UnBRZMpa+OEj4Qxlw4hXvtm/RPtN3JrtpsDiPBl9Cuol4fHX4AqCCoNX7
Os0qA5UprKmAG4X97tA4ji5l8fO76Mz1Y7Q0womoj+XNaGin5XsCpnyuxSZTOS8FmUAZDjmuerIq
bn5K7F/bLJvtuINhENbaguYdPvXzA5YB4lXm
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_builtin.vhd | 2 | 49294 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
kx6QEnnQuEnjQwji3i09IhLVWc8Tpl8x0WPPKnTIdiQs0i5dVHu00GjvvkJceFh+nsgIIwTdSr4J
k2gNiiPDCw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
LpBP7EUkcwo74M3Dlvw1oRfOdq4lHJVKb5OHuPblML2Vp7TqgpBb7iEc4m6j6wfYvJQHtUTBEXoT
cOPwu+SaqmN+dzai12qBI2i0YVPirnl1t1k0yXeDUnJhjm/FahxWmvyQBCOFXU6xUTAKhVtCBu5b
mdlLAQ9wx8pQNE+COCg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
1DlkekL4AVj7HehJoxWTCIFDxSscBxE055kFsMrVCUN40tlkvguP6Rn9gNhe4IDMfHcf7TDFyNWz
AWIwE2CxHCCGDSjze72tyu4/M7tWG3zoTLpKXCk6ZNpkAu1JEZqIfzV3hAcElXiBu0I3LekkOCnA
dlcMlV6UP3fBbjPBR1h2lYBOprAlqktIouAmLuPpVY/tQw39ABNw/zz7BTKW8AswSxh80QomY7HJ
RhVEthvkLR57viUWQm3Y8WIMoJ/3aNlamztOmhJWRceBIvo9duk1dI1v7DOgqdekCOz1v+luxRpp
714AJrHvJbqo5m3MdBGwyGcrBJ+/1IOvXZfTrw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
nT226lVSCbh7cZIGcWPjQ8oEBkxh+GSBql50XHGxvqMSu5AduaUzAwERt9rbzVwt0sk7fxwIDrU1
8FckXgE+7KIpWuJKHh3U4SBlIJSUNNz/+xnrc5cXlPIW9iegQNMtDJwkYu6U+kqGbn3dfvB3euLg
GGfQGteYV0qm1e50rus=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
PGYRh3Xf6UjfS1w7zXQjhV14852ZeRKkMIyfW5QiJ2fhhIfhRAv2MU8vbBpu68sxHlw1vBHn1tZt
SzUizYjb+93uDq7MfHXULqlG/6Zh4xU1y9dZddgJeXa9Jmzc2B9FbzQJrIXPJjPpyh5JkXv8OWsb
CVTHtjeFJ8H+xFlQUcpSRsIhaNpgMRuRyDuVq72eLQQSXM1ZSWmIGfYY1hKLcrTGD9uprL5kwtiv
3PLX4mOhPAK1+2hNnEXTnCYNN80FR8IWjG339/F3Ft2PBjeRR2pCHqqg0vS86xWjMiiQA3NXxIkf
fkowTMhGEJgGXe49UXTLflfjcSss1rSNqj8JPw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 34752)
`protect data_block
e7SymfPpWv+WUQ7WjG81vB+4Zf8yQDdO9R8p4TgFHYD6S4Y3Iuu4nqUri2bQHyYGYBm6Zu4JE7lS
v7b5f2BY/jHHcno2MGGbhGmewtFgvfkUaIzuDmirtm+tI0XhZ8MmZS6wHN6qXSteWJNgrBm1D4AG
nKU4x5ws55p00eo75Vp6+17RDtt2dEzwEfZ9780IEnhkvSlWcPqihWFdLgVh0tfF5fWe3VjFgS9L
HDEGIKbTNMC68qPFgECHE62TOsAsRVBzARWtWG64622+7gSsaIvFxJUfKWCbhC9Oh1yDdyQ7UDzy
k5BQXX6LyuuzHBa2p9uPvBtG7OMy1OZqdI7XSRaqul/F7Y2A4XGR4HCQicm1HQNF+DNJbPVanjuK
apb2Sgiu6ganKDXd0iIdjitBeN1lO24DS3nEwqiMIJ94LM/NC6uJiVpWI0juZOkvPsuzFfDd8LTT
8gmjIcIFCubmLw1VzcYF7LCix6Uq0FRBqp/L2FukHQJX2UrUb0fXp+U2scK4/F1ioEXb2o7eC0u2
Rx5vL/tdw+aP6euVxunJQKiJZPS/8x2H0z9d7GCdVFLDkuM8ubcWs3swSwW9IeCYNP33+d2SLjoW
I1Qj0cacDImkcEwl8IKuVJNyACW+M79Et2MM51kknCL1imDVLW3OAMIvMK69PoG+1V467UwYfqIY
gsXZUTkksi++/EhvURxgUPFhdM+kl4VZQzgn8rjnQIAIiqNGZ2mOF7oepZG+d0sx0pw/FuD9x6eu
ZsnfKBGr2HDP/r0rOqi+qcSwuKUYlDkkGztzvg26bhjJN8FsV+kn5Ya2Ah6r5DmTyPD2jsP7AFhQ
KX8Ph9iF6L692+v6yJfmcpyBiSp3R64eDcUAibBMxkIlE6+MkV5EZp5AF/WL382no0sUzkI75ayP
yK2vxNflWJeJGQYzXmwRl0+9MfgTSHfTQ2re5WiaeGiNabVafrI8/lewB9GpifV1dl/EshcNVifw
R/MYftYsRApqpE4bL8SdhO/1RzM/kk/nRPwByeZNS4golVRb7BQG160QMmjj4rd4usWFDSjK14ZD
k+BzUQoeg9KrAarU0q82UaW506lLBual1oYn6BNAu2VYflwxJEHLRDEkkxQCMAAZUZIo92ks7w4M
jcWewpjOyefvzHkRWJ9duZUopvqjXpVVJ5EQShzok1gS/efp47pdV6hVZRGL7+jPUjbz1CsB5x5z
2MpQDWwg75fUS/mOOOXREvLW9e0VVY0iPLfsgsBgBWDDeu6ZnpwNkhLgqJpggCj86Wb30PW1cuK3
67xGmyaep8JEzkBtMXzrtfwgjc35wpqyJknM4hQhNvnkAL2Sl3aD+I8z/DQSU1m1uoPHpLOB5sGe
k2cEruaI5rnn5uM3CZyGF2tuq+n2nBnQUgOdbWGW8oOYGLP4gVx1Reo2S6a2/9Jasoe5e4yRslBN
QKZRGz1K24PexDQZFxApTqLF6zGmUA0DTEaKi+n6hlgXC+BpfUnQnYnwVO3I0rfRejfiOsRBbb9T
UYQCd+nrqLah94EZr92TzGIEJStqwLXwtIFCONliJU+yUo89HhQXKy2GAeqKJGoipcOKGWGWczjp
Dre2f0PHTMFq/Fv2+RfWn9pVVynXMwAVOLyok0ihsH1JeVpvpG6PGiD/ZSFQzpJ7BbOQ8SYwagxu
DN7dntRAGlgspTUXdTcnaUgkPI/ShcdoZqEOUZFF8V1vO3AhduO+SvpemEBuI7/XXwJQfHSoaFfo
4NAgB8uNPEuaY24kkz4iPhbKX12y7VBkpsTSiTj25r0ZFaJPpSnXXrBcM5cLmT1BzxUmAhkjvul/
Kq/WEG6PKO2CZVFhNY9NnpMe6GVa7JTrzu/rqe2RZDZw7jP34MwMKm1MdO821gvG+/O2pk9w5WnN
3lpXyLV4+CS9xOm/PXvuP6/zw2ZJC9aC88lCEmZ7gSV4JAY/fiplfocJqgGXk08DpfU86fds1xpJ
jwvUEyu2z+FrytZMiV2sOv7IO3sskXxB5UlUQ7Onp/lCjSFI+el3JYIXSPoEWcwqZer8xg4PI7Xd
6/qnRjBTVfuMeRyUXjtibhtgQVL2VMhGryVS6CZAyLeao1XOQB1NKOY0Ct5JixTwwMhbvw8kyX3a
kc6NEDD2uIuQEc9FtW3uRFXoAV76hLDJ3Haysu8/w7QcX5RLzeCme0ueyG53kf+sV82tRjLfnemE
juyxWTYuA/Wyv/OBsGYgSZf94z7K9DxWtPZpI60DRaN40GW+96DV9dceQR5mBSJVNmyhd/XOLEKH
2N21DwTXbhH3PT5hVPZbfeCXjG/qkYZbwVhMk62N6iyQk1Qbd5WAXZzsr5bioK0YmHCiI67kTdqh
9JijQ9g1/zX/XjP6g2UOqxcsg5qKzVoGgCaPsAgBOF3p9YtJ7EJYEcbxghgG6FMvTY4GvDCVG9kB
nrBbtWKdTucLUejtMVzwRI66Q8ejIcVb2uo7FHuExu6N3l2vWxGhvBmbKtHwiI1FG9yg9WRjYfbZ
ji+J3Pxa+J2D7Gr7T58a+ABOUCy8W11oVncHt1q43OVezxFN3bKk0EInpCA/0cl/BZL4vBKHS7kg
fZ/RdZAUrqc41So5m9qZ4aJ6hEtEinJgzn78cNteOAEpE45oGMKYSoiR/7uCplbR5YdnZZuHDGhF
2vh6Ru9wE8gsO9c3+DeNmn7fbYZwzklnYNfMZ3HrMhSVl/6CPJzfzf5MOABVxKJ64jEs1kfWD+OX
mxsCHKnIwudfZq1tA7+1wF1TrxpmwCGrg4AovPBmaqafjbRfSIVGJt6MeZ4haIGNYe3hoAdJrRAA
yO8Z3kSl4QBHzJa0YsW05Oejn3MYHXceJTn4o06IajVgh5cOg68Ugg8T67ugv5nsrj9DCLrpms9s
2fYTsDNuUby3SmnYyOzVz/91v0uQ+f7t/b/Q6c3jcjXNXiXM3xHS9F7fVWaTxg1mKf/VuPb9mZ2z
vyX4VKcTgFybQbtMgljnAdZqH7pTXem2zHHy8pzRRjyw6Ia66WVlNi9Pd24uPxyQoMz5N2ykVj5m
9qfHHiBMhIFTAVS6zM5AuGwRwzyD5bkPTC3GYPFnegfu9xQHFto2xyo9OsxJu+qDlfepRK2GSnqS
Tybr4cy/s1mV+bHcj8ub3o8yKjsgLyUfe7lJpy9ZhR/D2GIOLVwIhB3S7GReTg0V/AR9YAMFm4vz
Y6Im7kKgd22L3ETseHNf6sCpzaFsmRKrtkEJEaD9q7MQh0DxOyRaYsKaIbDjkOPJ63bH2gPp2gEt
a4uSpQXNZKeM1icaz2fca0emRZfemYGNLjLVWg/OgpCN1Vy4aderTRV1/SbsmbHtdSIGYj2xw/gp
B2ad1AhtjGTUsxLcO511DdSUZAoR2y9wrkxwRW5W7Gmm9MBgCNid6j1Nawgo0PdLlo/7S5YpZsDF
j3BrM9OCk6Q0jt76QzCQ0O/+6Fq+e/WJiKkQj33oLoMpFNZE1Zx5gGK1fNzxXEf9+oj9dKRf/2XT
tnIvLr5qi+4UT4nNnt8M/yGUPcGiqdcBHT2bsOj4jQdjo/BMxfFCHAQ0zbGM6wdGIt3RMRHxBpJ9
fmD0d/a33/6nAPG7H/JeILkQIIO6BFtenoeNR0SqBAOlMUmZoL4XYgXWTwQoPZoJwgbVpGFGSfCV
TliJ+sWhxiWZdf1d1ttxfyqsfndt1Q8CQq4Tf7X5omVgFeZZQPAa7lihrAbL5BgE97Yug2tjdbJS
ZLy7OGVemOSHUuwfci9JP3Ps8GTBZEXQ4Pgr8e5qBRdxP79692Lp2wtx0hpzbe+G+J2lTEC4cEoo
0Iqmqe7HA71mPFX+kDoDg8uiYBChLSDfZVYQXoU8a5MNG01xTk+kgbRaLDqoKa8RtVV1EUB6Ia1e
AJ/8Pb8Dx/kVH2MEPBDsAy+CgMI2F3KBO3KjdhXUbC2TYKDEoSvoYjvxRLc4kBcbSuaTXuDUzUXG
RJFa2uKOZmod68URWpLSsbNxQAsK5z8r+ZIpVL4eo54R73QgINzbGoAiUfsiJ1Eu1pysNk5z91dZ
yDJypLnGV+Ow7aMQODzVEzQP5G2Ekm89uRZz+qayk3HPzRE7GAFFACrMahZJoHrIfhQLPWCBocFU
9eu9Wp4NCOAX4Nd/jKUpdYZUqgLz2navV6xP1O8aVAMgqJIT4kF8zf5TJGDYmPLQ7IWppT/IN7wT
32geaKo1ZO3Va4gwwz8VsMUk7Oi/HMQJN0ujOoUQUMKAnywo8TnffW/O0vgIJRXS/ZISX13lnVNK
gNQjJNuShJgm+cqrDN1zUycNdCHbDn6n0cspDF1qCdftfYn2leyL5Y1PiVRFzirlQFdVd4DpyBoO
jTiG1oaid4ABUZRpTowhlvcfIgbKUTc0sEHriYRmerktz6SUEpGaOqgRMPTJJm7EhE0nX/gCK4cw
Rusn1brJRa/aZrk8pKdaTbLU6MR/Vs6n0Ca3SphabjcomryEUAG/dool8KIUI40jTd6eURpBpE7d
XRuQ8QGkpEodJpLIyXfPZA4Kh6tGrIZIn079yfnxu+nVgAxVpvkqHPsVOnsivOOnPFxx0KU+/vVP
n+XO7phEPZuFpVHAVw/uWSFLna9Muv/8TYhuw20qVgfPutQFSymPOFgL1ysVpxzF+Hqya3UY3Wmd
keQ8bghXgCaXejkS9/gypB1yobS88VBaTWs56InXhsFc7MoNcnjFV6CpDHsVifdDDKgwyyrW+J8P
pD6D2TEgkC7YHZnNIx7mB6w/xE8gpjQybsSC9Oia3DD1biwIbjC5twR6SUtib79PPF0XB1DlEW+n
cf7K3LZLQAAqmkGPUXw7Hbv/OA9cXj8GsTi7SgGuUlTw5KDM1ONNIf1SDj6n+nKmDK3w5SdZAwYN
bqxbGGiBL45enlRDmBHfq2r2/LZJthsGO8ng/3O78hMpZJNponqi5p5eH4wpkMAL1EYOZ0HtEtDI
+8Q0O8juwJ6Q3RQbL5gDh0avJBKuwmz714KmC34LVwAya5kNd7wMwbjM/7wn8ju8ETWk38C51ehC
2OhXEueTEugI6ORrZpWjNP850f4nOyigxOE42lkYDPwY1zZ9gstQqXpdR8YrKgnq26i4sdpjKm/b
VzovleGvqnS+BL7HAWsnapuUfsuDmxhGWxtdvKM5QpoGT4xugc3dLJtA8sIUQSI/YomqQMe+Vfz/
sFmYzBY4QzlIDyxh2Y3mCf+43Lk0RepJiWrWnvi2C0rSGl8n1C1noVQDltSXDSkDlOvLnuJI/o3n
drV7szjbse93SczmFDW1iajPtzoqQI6XZUV6XD4LJ2J3Varaz0q2V2cUPlfebdWbzFLpeoWeNHdH
06PcbgCEOMR0VWdvbcfs6qg3JbgKFH+NSar+iU1ADlwlo0DDnZmSZdxLOfDlyDZXMhygFoV3GkMo
nBHJskI4W1utRkkIDrG5VCLnlIxA337vpEGwxDZZ/5+CxeWdIIvNHRycsURIxXQcpKt1HF271f3J
HOz6lrhgf2hOz2VkLR3N6hxX4GzJLjeQjzoopsLwe8F1vPfqGV484r3pvGKI+/2AkL1Avdy3suI7
+8JIZYNcWVm3VcDT5Sm03LukA6eVRO0kAOqWgGM2V46a2qJXiHVhsfUW61NxAqLA3cU/RpnZt17e
4m9MknhgMgH5mG6pwrxkhRVJT1DUC44M5J6iWPjHjzdAULHjqtEXhPOiATfBgAG9EHrfiZ8quokQ
YsJwaILkTZ0H3W2b406cAaejhuMf2L+4AcUpIi187KHbVyuWacDHLgule9IQHEjLxDoZUHcl2KDQ
gTsfCy0QFdfby3k3wDKwfVP09HqY3Z3oEPqSm5hFsOoRhfyxjL905etTJKy2W/xkoYsrESile3CV
Q7xZtpxejxiizDzJxfZrkuyUNzw0mPowZgcWVHhSNCVlQAhanGx1C8FwgWIY9V9E5SgfTYUFatL9
CVwyam+RAFe+p7CwK6mYSlADs775VKKHXMqZyFnzoIe8MeMOcKbKd/xV+5txnMiaxSTEHDRUvxT1
WdTi3JRSkkoMeCsA5cbYB3Dg8xX8RD1YLdyWBImarh36CvyNojsU9edz+chB8CR7pkTcIWcWdoOJ
trB7qZs8tr8gjuC+ua2Dhd0x8GTEHyHEmpwFmKz/JsCYK5mc0m+im+EQQoGe3MgC+YYifIj9SvNO
AIFuXjKIQ4dPM2IGQNJT1fYBNR6Wyk533EQiTS4ttaQIkgxGHSt1CMaXuIy592z9xGofg/YZ6xhB
tQi7kN1e7BGuk3bgbuTsAynQZxLrbQIa/skSqX/vaqR2TysB67Gyr1r1JRQ2P8U9+Ts1VkryWgL2
9x5/wUI5KgsRVl9E6ZRzTz9gv9KIGPsxTiTGMSWEDfaK4pCEsld+y5O1mCsjLrLP8fddtnxfNGXK
mHx0n6aqUln/e11k7SjNChhV7QjDPDpSbf9sKLSItdXb/e3CoyXOJV2rl+09lh16E0CORSeB20T6
rvtrV4DF/TpKB3lz6zFgAVVZocBx6quUvvSPeHyFnNURe6dSIvAJK+kA8yuc4aFFTGGhmpmNSdEj
/SlAe/KR5kIzzObjSx3jp/YFFPF5WCmX6+QtbtkNi17WcvxICr9utLdh81m512NzCmj2h3l8u+eI
gbGIAffK4ZlfpB9bUVjzmSfrR6nWnbT1aG4SW/tIs6JWkFXx4EUeVWyP+6ly7QK113Be1CIusKUX
FXcaz7sQ1BIw/PySxaB12+kFjjZvGwkg5Xp4ni4nfGxSl8lCeZGW4mKlInty85jU3GdQ4G9GKuUD
3M/Sla9/Fh0Kw45es8louQjskp/KgYTogR1hJxBaScR5nE+Qsk34TX7K5Nx2Yy85IVEluLI51By6
NnGQ4lgqVtFU6a6oZZCZskI4gEVsHNtAxD2rjzVrPY3imUfaE6VJqfN4T05zv/4K8S8pKaNc7PRl
f3f7+KCjyW5Ihghw3QUPxXl2ptzZkWqcF4v2Pk1TS18ThWGVpoFrZBLMb9IPw0ZrekcMMQgKjS22
h9qeONP10JB4AfrOcChSWNE+9BwoX+M+XZzASXZlSCTEl1CTmzv20PwO8Tnpiyw8YZU0JERHvOio
a3JlDcgUKVgbQTyL13+z3lVoVUvlLdZlFm0VyjK8rjZE99Vug2lWuHRrtAHuUbaXsRdgCz5Es0Sn
T2gKTiRo3hM2//dfW2dq90SpTKkcAM4760XjaPLlf+iORLyGRmFxtEC1exj4+KjNx++qkm/kBIRm
7USSERPgBp9RQViz3q87RvlLCL4SqwNtQt06xC/fR1QBBWEDr9Fsy1YJ4eF2rUHJLd3HdToiBR5G
5xyyaLwT9KvAjpqaz6rUIMIdgyVuukpja/RItFDhN/gix5oXmw/YHkTlwvu4Sf7T854iQ7qmhTBX
nk4TWDn1h57bscciffVO/Z4oeXJyjp4qjyNboxRPYMbxzHsTXVKPtjyIeaIipxWk5VZwFETlUUrb
NR6uovT0TaRdG+hg0ZYlFpAkXfNgJH6z1UOkY37cRGWQUfCGk7LUpEBSMQf4Nc6Ij4NqAHjPaKEQ
uAHbeLzmASY1vUoOSat2AfDSykDAzP894pctEmv13WGpFk7X3WqaWEk2WtODez3pdJXkHBBo1taw
8Jb20/Z/mTUEupPWqYvM5gLYjD0YKHWUJeFgOlNJCI70hqeIYhlhdydH0HTxD2owukxT/HN9rtxO
J1/o6Eukwye0eBQULP0bhAUCRYgz0agit+lVYOJE6GOdFVsC7SuGHBnHuSjFv+17YUba1VxXvSZK
Fcw+0tIsigYZNEnn+PS8MFFVWxCQA14ABwi983kDhwui0NuCBkFMlL3wQ989RNbvDUYHR4hDCdhc
ff5y2wY7e8wHrO1d+uks6rs0KhvTox++yMi8NWIE+0T3uRCGl/KaqbXFoxbPHqn/9lQQLeI/mPXk
oX2RTR/701O7bxhRc4qKcTq8oL8rBvdy/D9JmYvPRkNJrWqR05j106XCbdMqZqPfvM9iCT2oJ4L3
Pi7BGNYCjiHHIuA9r9Rel3Y814pbx5uIA6VapkQxg6bc/7asqaM1HAHtn7LZ6g0IIa6ypa51e4DE
6fz/la6czNNoOumOlHsHgchZ9ytDwP+2DjqxKJwYZphr4ZGlZL72iMKr+tUsgdSjUQ2MDIrFt6f8
Tg8Ud7mQZFMn+0zOEmf/9gkfqOsePXxnZZfPpsMZgIvlAN2w1SMhBHSYu4HsPyPDP3ZKCHN18zdO
+mpIC6E8Mi57prQwvJDGJLEunOu5SL6ZzPwPoaDyh+/KmLVevq1YVmBbD5UqY55SR37oLhs+MFxU
gdYD5Km4sclcIn03X6ERItqVGMvEB+esiP0Et0tinzy3dpuzVnPQPLIeZL5PEgJei0tJ8Ib3sjG3
RTaXqqbehAL4mF7L9d78on6MauNXIHMZ7FFrYxMEQVA9dok0IpE6u0OWVIp8zbREUri1pviteMlJ
hGjm2hN/T/gLTzpuoVj49Sqb5+Zh6uKFdGnAyu4y8OgKgtTUgI99iECQ4/ByaC0eVAey3InW+sXw
gY2j2+3SCcyGE1TKEhxCPdGjm9uYfYbaIKPvhImbGzubPbUqwJACMQEJEOKxAUHgnAiRG+YGG34f
kLHyS+/aqSTp2NnJ2CE5tdPGb/ruIdys07DUj5RJfDqtflgJCRYc6FLfTBvU40WPtgv2PBWp2ecO
OZKUCi9544ArDBYWvTs8bysu7Rxh8k12v+xof1YQQ5xQnriWy+g7TwQPGXzGhPpmXjNmlXIzBaBy
nadnZCxDKoVaLWaPw8Y3eKBatiaP68vkAlW55iV8yPngB5c00icX7YJiH6Bx3lZmsa5SsAY2ZOXY
c3vl4PaTnNKSqva0HJXFMNvMZRWohtJttx2ILwIWn8K6wgFgvzB7K7tKYLuq0DDW5gin5Ai9/eL3
k+LKpCc6ktWB3gerBAWFLjJE7/F5FfnioVJACl/i9XNpDM4RrkDYOvTVE8U+UCE1anUJrSdUoUvi
1MU0DezdY4xyuRNXu2QIODAzIXWogIbRpJ0UHmVtnpMBEG1/LxSKAiOiEIF7wHZ4aL4jZvunVgsl
WrV0lcSBOWyAvocV3uCtlZKnU8KerHIAQQNW2y9coROVfb1XeKgNTd8QI2IHIYfqBKB8EJfroLPp
XGCbTOEfI/91upYpwGFC+r5W521SOnotPbYF3PnEonivMSyToneoV4mwB/JtGKpTW/vvf0ssr2Pb
9QT/BQRqxOyoxY7Z17fcEtb8cMIz3hQiXe60gEn4IWwFzUu/eNCYnOAuz7F5dscGpZJJMoVCjH3F
QTv3M+RUSYhY/lOz9j9gjZU2WM+HBY92GV4t/8q6NDm7LFWMIrqj7tSOcqVY48lhfoIN8RUxuepX
oK824blmMBYKqavDviQSfDqrzf0kZeRpLH2KYQl7JvE7QfbwHul/Fh83GD8YBswtJf4CQvUIMJ9z
ysuv5U0V+Y3U+8UbbgfY9F9JyPTIl7raksYtJK/jBbyYFr+kXlnAb5LeLBzRHidiWUhUZ4+psyph
sT7n/FyuUsDaeMDE0oVTZW1ze9lnQcmimEGveqbT0+JZkuf/aYcT7NLC/eCTAnyjjN25LnEZRRrV
BzB28YwVVayssxM1x+yXyB9PTWLKxKDlHAykSx+f6kPWB9OpyzB6LeDWIhBbX970ZA6gEcitpiCs
7MQ/Vxiq5+C7aY2wA6TuFLgFAOQH4IwQOsNvHZnbN/xcFk01V00epxGuhiaoxqAqL8/+A8rVWQ1A
1rp/xViduuL5Ht+H338TcETeMfeTISWsLisSkv8DjAp5G0dCO+/yq9d6D6lIXdnGb76ymzTEDhMh
+n3KrFsSlCbj4+89p/1P71AMGZOQEMRq+65CNAmpMnZ633osu49FMqHAiYg8DAa06JldiZra5sQR
CsfUbz9S7j6YdDNKZbqvlyjCLohhZhL6FMhBnJLxN+PDrgwfcoD0uAe6s46QiSKRFAkI0UJzXGxs
qBqthcpGCk05aDmHMLcAAJ3sTQrD+1mDiKJ0mAShsRkP1bniDS4t9J9zQG/Tj0wpAoNWOF7K3lNh
7SBb+hWb+goEaR2raWaIQhVkfMCZrTHeM/bQm3IgoiAlvdFujk6M79AFduILAngiedMuLa+/yvUY
c65xOuzzqNkG34ZJ8Cj1hsAALxNCyFKRfIQU1dFpf1ALHaZIh3ne4tZ6Kc266xB5cWztlq6bxepe
phDVWtkGCKsvYA5+t8q4f+oBII+iI1pSEnMPbvVpBKHGnhc7vJd7Vgi86dQ4NmeSbY/8aOpw4t5R
zcn+yseG6re3caiOgC+j59OoGXt9SrEnL82qbR1uKkGWMivlBOvJRWdxfUJSFETuKUBlAeCmYgG/
QMoz7zxPwNR5au1KVKH5DYaqp5Rcnk+XpIvfP5w1CxJLAi73wzpTnGv2vY+TUX8j+Bmv7Mw73fyr
oxaZnubjW4/P2LlD3gsp1bK30eZtFgxfChOZvEL0JSCLhEFKJIwU+yJYzrHuzi67cgtt7pNxRJCp
ayXasJ9MKiu05qPEDLXmubIogumxZne7f5yEEX2Ga7qJO55zJMOVSmq9LymQ7LOMpdkcL4g4Cssg
+0sBtw1VYyZJUTSyTB4IO3mqWdzNBwSZMUbfaNK0cr3MexSaWcGxl2GhvVpTk1bRcTU34aNVudIr
9aN94XvLHiS+WNWH3CznohTuFM5CzqIm0Ldt1dECj979Evyxy1i1NzamRzKrBCcmJJKLF0ORgzgc
J+gK2fe8XC0lu7mHUMBlPEDpO/F7pDBh5K2xK1YSRPgIgM37Ho4cBwxd50P3F8Dqf9WC5x9F/QgG
gM9sCrF9so1FMicfDUaQh/Nnvua6YbWXvzPvEqtD5Cd1mj447V5kge+NXh3Hb12HUrIbMgtVV5z0
SnjzLuoYcKtrmRB7zQzVWDxoIVDlE7qOtxb36t0NstQKUfV9qKBBzrxvc8nMmmububhOyLvDYh30
5pTjQUHo2fliliGSUHhBYo4qfO+ZnDPK5ShE9nxANshI1aUbL9rxjguI3LV+z3fUGHbEDxqZ3H/n
hUo6G8yICKKJlp4U+zPvFf17yncUxfWG4SW4XSjjmAO5rwEFsFGP4tHOsz1LG8PpW0Q31ThjZXOS
rHtfnlxWrl34UA5KOTj0fgdoE0sgHCk1L3v+G0HHDO1R7/eap7YBZa1qtxoFwRwwrBB7U4JnK8fV
M9keRwXhk77sehTtCUrCzbP3N17qAtqunecZ8/PWzTsspcWfYlvNdm8Lbw9+L3fCWKoeOiUygiWm
ScMp+8EWHKRES0w3z9gEDue+fr1xwACbwmYe+SmN0j92NaBbGuYZ6DFq/QZLmkVEFuenbS0AOTsy
CPgGAM0LQ3Uao90nsx0vh01mil8pOBc+EGgVSZjV9o3OIWAeGQQ4WgKqynN4PQE5Jb3yf9cYA8FE
SPIEM/faP+HrOn2rmFAcz5OofXgOvzchKx3BposEoI7w/mU1dbmMG7lI7eBNECySDIlSmIEWGtEm
cm9rJfpOPzqle4FU0xr06rz+Zv1M8jUwDNxqzu2psLS/zDEnJSw5ajiJ1qNmZI591pXaMTF7Y/aE
ZccxVX6OCSjt42Zs4Mg231RgHBqViFYWDhPZse49O4hdN4dz40nV8I1KkCd/Vu4GkohZW7PrdAq1
hRvoF/boIgYOKxs03DRxvkva44yUKqWi53B26UrzmUV7GqVtGJsuWLjAHUkHMV59kTZDkKVzVeEU
jertwCwrlkBOA7lqk7bGFFokS5ChL0jHd3nQ1hsYTPI0bE9a3fs3vO7ZO6MgPwnuOdrMwtjUNTBI
OjBji6JxfIPSggqHaPn5VK55DGRmw+cHEzPXdeMfE5LNEVHTvRleNHK/nx2+jX8VXX9yhkXFo3de
IHa/F6IYi/HAXVPDEB/JCrTHYe3NMQEtyJsRZMsrU5nz9F7zE2Xr+MTkSY8cm7wLQdvHPXjENX+g
V4dL91hSuLqR0J2PgGj3W9H0xbteAjEsctqFwEgAT/8fT6Sm+ZbnxvWan364AlOQRXeDzwzXP1Tj
FalVKqrPmboamb0PTqyWt+kuSfIdHTTHtDPlbHquKIcuZ5xAUr0ohjALLrSEkTFtluzvurd+/RZJ
mTfYdteWafMDmRPceBkhIkcC/6x4pa7rh7qloK/CGmcBI1J4TM//a98mRfUH1vYQX/diApXvhjTf
5XCcjtqK9OUe/F0Tz5PK34WOMKxl6qi1NSdrrO9OeQHIf6DJ67k3FhRi+KmVy7PJw+/M+XTL8Ej4
69x4Xd0KskwnKjKEy2d4c5XhQwHwrt+jfJpK0BCpOHS5evtBhgjwgU3ZoPVX1cqK4C6ndwkVb1YX
tYsOR+5TI+VYDBeFUD2YIbCDxhCXslPe67BnRChleSfAKGbRb0lYs7P6xj5uqcMToMTzJdZ+4fl1
wR0H+uHm8HsvbrpySD5oQZQx/rH+BnwUGAM9xBHeIQRRnoJ2iVKNLRFGHFzzvqkTEAe0g5zQnGVi
zU+hXf9EMtJxk2+UYDm3Jp4CVo3XecCzmbbwVi/C4vSsPFq97OoWRCIY71qMTVxpQhvnSGl9oc2s
NwRXsN0WdmqDcC3CLaIkY2JlqMXCYX/KsydrVAPwGlu84ZMdPtLl3odZvpQ9MOQ0E+pFRFqqBez1
fLkIjIulk8LnZnfY/rha/TK3HXVBwyEEDi8XcfQjQ30gULKk0TpsPBSxFJN94IOQGGMIfkCRC55p
awxgph6L5SFIKXoDeM08wMLE2lslfhA1MUeDtFqFvv+9dXUCiXaZ0zgU7f0lZD0lV17yPwI5wTgE
Saf3/jIDUo1pAloNtQW2TGcudiSC3DYCKQ+iHe9afGBMAwgQha/5y2Zc5FfW6xhw0leEL2eBHbtm
3pzm6EAXmPnN87trebfYbKEXTmQ4gaftaxJX2RsgPyxA4baaYa1G00cH5FBy3/s+lRvCBom/Kfp5
JndjMgsfssxzSzY8Izzh+iMTDmiPqhE/QAFHTuRqQVAnDFoQRh1CYnhCuvahL0g0KWGoxAkXdbRw
BVLp+vh4ihcA9aH/hBXzcolyeRbdOuHzbY69K0S/0JVtrPv1Mg8CjrNMj6OxcQ3gJJUoEWqqapdu
XdZwEZHHgvCCiekVc9LOfm3ASwgEz8/7Sh/JJIBfuHbjG/yNrDeKYEX1hNfyJlGGPXpiBKP2mZVX
CbcrgmH9ftyiL34EWzu3GQ+PE+Xgr1W3cQRVaGNQbAZTmgCO+C3Nf5W9UggMUH9fFp5VqUUwdzCU
p52c9mI23Mny5yr2Nq9R8HdyFbR1fzSowRipmqPczcFcHUal9CNsYki0uyndvXPLT2EYU2gt/szV
3VELj4VybJ5K8b4jHbi5pssJVffe0d1CnZ7Bo9aqnU/9PWreLVVhLWCzPHa9MSHwSJ1n1tOhnxJr
WGtWROghRjrx5SWT53bvIPH18yRwcLbm0gmRviyA9FuOCgkbNuIFv6pdJP1ajA3mLscGJdv9xp3o
kBmVDqM15w+Ak2TxSSdVbTFQxbxvJ7+3U5D0W0YNDgD0v+sEw6/nISNKsxN23MaCZBwMez4ru/nY
LYNkh/8bFWYem3+wE6YCK6xG6PX12kY0EWiF0mjylAVv6rRLhGa5yl0FBnhZJC7piDagy1qDFjEL
4BsDlXKLAcet4s20GqJJkaMjX5JLdK8+4r99SK/TK9gia44f6Ml3UJCeA9kkhFuDGA4v0QTLm2FF
q5K9WSxGpN/9FR2Ke/g3t9zpgs5cdgjjd0U8wEQF7JiRXVHasbE1r4fMTaTZ9+Z4JnsspFZQoSDs
l+a+cpC5eETQTfvT/eiuPZcNbtz/Viu76xS3KhEH9Mjzv+NNW+1n+TsHrPMNyNtkFVxKilm+bKMB
p8aVcQQtI5riM+CQIzEVU0i54aMTUKVcQPnzNPhr3iOVdQ/OF7FyX0eMuMLfjAmYhtKKvrfL1uqp
Z+1/C7EEJRNB9vRaTfpnM6UTHeT7jLOnItdhLRfhwIEdu95JHpRwv3cAjcw+lFH+NYmeFnKgP2eq
uVQRbDzpXPM51H9huszmJi0HJ4GkaPjZLxhgCo8PHvKd9Vs6EJ6wVNoJhfMdogc1ioCQ2KMVgd80
bC4qTJkXBNA1UaJdKEOc6kx3Q9gl1bVLCtQKIqdJI/KiZbflVg5b2bII5ALl1C/QRIS77thplmkk
vA7l3EcMqNUtAyl+RPgBGVw1ZE+Pi7sD0JUhr9a0HTs6pfLP0aM4Vy+bq/4lXXb0kYARjyVOvCSe
3xMJrbBe3XAYUmtXRufLsFKP+a/NiFzIYkPYeJABa9x2KkBN9y4adUtt04CqW4JDA+JPcgA2szTx
/qNOts1tYk4q1TG5ihDffCESyDUVxAJlpi5ApcQJ2RNewBSZA5r5cpWz+dmd/Qcpk5ZS0+KY1lN9
KS6sNnreWXNqvQCu4NevlBbEYLLuUYqSv37wvq0/Rj3jhbWqKcVl425cAsckCOlLXst+OqMIHgzC
BBScr+8wGzu+a2Hz1O72qkpHnCmEq6MUJiQzKMnOHu6hKf5KXkMvu40TDdcfJ3HYWYKYk+37AufL
VMBQg87ya7dyeoGcQHazfzoTz0z7wgc2sPjnOzo4bEs2Tkn4geMaGAYTi/8LUHdwr2QtSFyzxMxP
Mn8nhyKsWFCPerQTp7xFN5jbrO7qgU5BEz0TXAoxI1SIgFzAwnj3s0yNeEL3B0dFZz7pMbCCfJDq
1NWA+s2/MAleasQ8sx54vZdLMz+A8D7o8rfdZckEfKEY6G20G+ZE65r8CKwe6jHQxp7gLlg/w20i
88+ipYxOTYS88BPlAJ/jRD6AoQLC7Ba5CIVrG+ikeL1mHS5X1mP06F//zlSC55i51+Tu/v61XoQG
0r1WATSl5ZUWxwJJmNpqIPagpd+fQmB6V2CZVg0SZvCcNGXTopmfAwUv1VOPWI78Pop0pI4PqqwD
U8Hm/HO64X/30eN4GOjmmSmSOqyh3eChGLeVy6CCtsbkNUuNbd9PSMWI/lTBsgacZUoue90w7c3A
i39t8onG1s+eXNutwNvE/Ni/Qe0LvAFRQty7f09nF8at6A8j9uGCsSHtBdO1zNzXW/evFQPN+Lpk
aEb+tQqz1W2Te3IP3Wj5a3vQq7Q1eih0NFklGoFJ83Mx+ganT/vCjjThLQ2nk2ku7AAzzE8yU7tH
tH/8rujtyVavnnM4jmYBT3Edd5wHSKE7044TDvjkIjhiJsj/2LT9ITyRYN1crwQhDeRuS7MpHh0R
CnUKnUraPqDy627pyYlzBoBk5j2Mx/G0BvooUiJlTBTVC2mRaL9sagiGu2dNnFqtQ1aDdI+wl2Ra
TAToSY+0Y2NROAXxaqMrSCeLBRw/kQWin1ExMnU/iiJCXf4/zviN93uLRUv3wD31ZP/MFCsa0TtF
1nP14eR9qXW97ggykmfMACO3KY7a7jKTVOilwKmWaagcg6bI/jK2sZAzU9A8vIJbJ6GFY5ORONgO
gdZ47bo3OUUbniK7RJp6x6iZaWhXN0KaxDHZB4hHUh7UUMYqzv5btJXIb/TnYgsiMai4S5OCG/dM
wDDUJiRKv3ws5KDUHklceZGsJqi9pQSnZM0TWfYPystXt8aU+FEWFDlSt8mwfGoTLcgCpyubvrsL
ntSJfOvQHOnxpRzgvh0N5HbGkgI5hnmIWQtsfuiHt6M6KELW2QFs1b/WuOvVJaVtYFQBaIf9uR2u
Pu0h0a4j3hBfPK0tjBxss+lzu8GlhtLXoUc6sNkxA2HFaAokzFdBME66ytAaGLA4spgL40ar5dIU
MxEjf96/D9NhtCHs5MSLxJ8Bc0C4VD6Jipvl7ZFegMNVYwk08GvrczHro/7waWOatnyIc1ZNG279
yNtI82LL6ZLmF390TgS895xMPSmvkGAJiGRZxb8AvepJuU+Wnc92XyhU7vBMVST7UO0uFGZo3r3P
s3vBehsGbMrVQ/8k4eHYyEO+yc8MLNDEJU/oKpIVnNThBTZADtlCmUYxX1wMZ8oMfcG7O8FkPFdH
cH4nJv5WOP3cSCKM5bIpzyaODATyrCugtyf75s2EqZdqp3o6CQfHjlepjW/dDMNdS2k8Ekhdik/I
QIkhSZLN++TvSE6ynvcyRu34+/mXwPg688a0efNBQ3SN27YPmMu31gBTCICUj7PgTeVuPWSF2ULL
oljRFzw3nUjXX20ENIS9hD2RHhNVlM1LJuOGJC1yNchKlVKt2KCaHpnJpLZja9lmjSnOQc23VeCT
ibGDjD2ksBCwlhZUvq4pezQjGGn+Zs87phXixmubW43xnULBLkswTMcs++q79MyXgQmVSEFBBTSZ
QOhMfhUVKWJRI0sYweJ1g6UKkHxyB6Q55eOd5MhYCyBtFDSrmr6GMU2qHF5pcziM8Rybw/8MiUcP
OtQNYv5qK6HUXRoK0b5NLHc9155bCNIPW88ph53sUsM2VcKjXjE5Xsvhcdt/QWLTM4hfmr1WTL99
3VEWxSeOhQomwLVfYdokgwRwnx7JcPFnxKD6HiUzSXW6rCUIIT4Vr7qb7TCLzD+8sSQL2opyBD5k
099GSeBm4boKaoIuO5J2W74WjQR7826JM/zI5s9WotHKR+bHAp+3nYgvSpLYKRQKcaXEYO2L2VHk
Led69MnDH6Ri5z726TQO3tKSgpj09bV/0NImVmTdH7LChnzBcVeKuyxAqYQRXSBKc4bC3r6v1ABs
MjdLNvEnzBiP2Q8UMKEbnsvCPS9TdSZ565aS/DcKh7qeMXY4c5hMqQzqLFGpcBs01mYoqcB56EZR
HuWzlQsyZ2Xu2mVIGLkA3h/ESVILxnSh6qxXr4aq7n2qIH8xJeYNSke5PfUCgZV1Sl2jUPuELn9J
03wIBbfMCR/zEWTKtNwPC3dlwAUvMuhjL8Ke+Easy0WZ6VMdtVvvFWcMssOwfCCD+HYQ4WGj2INA
08C8GeVlDQjI+0xkiXql+NPEwNYbClmt1bMkY82n8PvJ5jsEExbBVSxNuw2vVNb6szgGphOG0gTo
6/1Hj7tmmmw0Z5/08JZBSO4uqW6z8M2a+ZocZKqRiFss2Az9wYIfUS/L8jOjphmZ3z95z0VExQQA
uyjrCICPeVXZC1Hep1VdN1Xt07PqGi/trDZpEZT2a/wGxmuQujcCffqh791rjRMYaaFxJzZNKw1e
TbQPnQNK3XArgVXdP/C/zb/O+IJsgOYMHW+vGYG6d5NMzv9sxo+1maT+DUoBfiLAj020sIMxzujq
K49GEYV3fxSiLWmXay08GUQrUB/bfOnHsWuuoXvfHE3+NRljitHdP/8YirlMr6pEbbduK4qKKclC
SgRg4MKEVLW2i2+UKHul8wwlZFRMNzbgNnyvk/D3S6d5MNfzRy5S21043gQI6PicxYmPYNXp0bda
5v02rc/qCGFcTgdNsCoKk1L2NqSZOwVhcvDoWY94WzDJgt6tfZhVfoSpPDs7+30K16lHBylPX+Ea
OscQyt/pCJi07kKwA74CkodiuQTquyJau3Hc8ErqNx2PDSN5vqRXWYHV/gVOlL1OTpFRCxUwXMaL
d3tttsBEwlQyPyH5SEBHsWer/MMLTdgboVu56+nBgv68m2KTV4BI5ihPk7HU2nhaqNzcwCg5FWey
JeklVio6cssv9OeSNKM3Ugg4xcCpowJti7Ydt8VmDj5KrajaNP92W34A8H9RJOTTiFxBMWSF0bBW
8xCkDSfypzNoQIO2mC13J1bQzjJ7/374HP5od1uHiaStDz5aLb+7KlotOfbXqpMlTi+EdvLfpcNV
Fmmr0mbInhTCmSCOepH3By10n17/0S3oAz7r/loQAZVswP+ZgSLuQNJlfpHc+BgL3vCGJ8kLnoqN
WbUX+vwFjcjz1yXwwqskhU4BAHYCbo48lQaXETYxwDIDo0WmgsJVnuts3ErwMVhgYBMVRrhZvJ1P
fLEWkCoyE3I+9QkuWWN/Q2sTkY49mp+S9YF4rA6NlGLfZrIV6QP+pRBdgo3yQzVuFb5jETg7YLcj
aACzxo9doyj0ZY3WbH21YW/sYDw4KgwP7okCf/VNwihN+bcJ4dH86YAYSzyvk4TR2BFXQO3Rgc1+
WJ/duW3bAsdVR1ZN7sqyPndLQis9lPkPz+9p8Yaa1fXNaK7tP6c8xZ8sbCYWfhGvRHfp1rhCquew
S8fu3/iobr3JPAZbtLkZCzLA/CYHAdM2I/aH9wt7teRWrC1o9SUU3FUTdUa9qcZvl3tFFwzfq6ld
iIvScxn4J8jw39ubZS8Hqf+hGSf9f5dKN8h/KkBNrZVMzMflaAXqR5L2IiGscBiZZzSjxvs7QWRD
GhZYYbC2x9zUKu0AOCWyCnR4kCWZSwO+nZjxzpB+tsqFTpn8gygae59IP9X5iOEAJwzLptajieOL
fnMBRjGKHYAoirEJ+nhW4gm/T0+hMIRzeMLwCFe0j0fm3V3wV00z16uITbP414MyPfKUYcy2osxZ
JTl9ZutCL0yPnuB/TYAFT5jpnPZN4ZjDNZhIWJnvknE4c9SkVspmoqcYM7QFQ6WFyUkXzi052p2f
9rzx8mD1OWgls+egVsrArXgBmhunxpFSMS7/PfRbb7FXpQOQEsxz98Gm4KNYiSb4Gw8tOGZXGwNt
nAkMnBvlZ9zcszqTvPv0vFi8lkC6D3+D8XxFw6OvSybjYPFYEeOEZZ6fVPWebBMxWIgQqg85VKAF
p9DPHhQGeZIjTK1+6iYhqeJ77X8jxC8A0I89/+4ygjKah+dDyfwGXQnDj6KHddivGpEwruZEttZk
QZhhgpaJLeL5otn3+8zduFJj26i33Myj+GL0WL46+2yl01mRx8mH0jDqyHNDoxCKYUCyNAr+98Vh
+hxiI4CBOiwxG8qhMlbFSp+y5kH7p4rEMkXt+EWszFriTWchNyDtqowlQyX41pJjtHNr36Ol97bP
0h7zCard5ANca/uI/fFIRHpy8pqXAe4p527lnrmuCrNFaJq0LSweUO6fXgGC8KKIkEd11ruWl06G
qUH8tkCSOp9OcBpzu1fNcR3iErm5HjI/p2URx+NECSAi3eS5+ROP5Qxw4KT7jIU72OjDqTSUh7+N
dGBBZZ01EBPzPjXN9PE0qWxk+J8tXCLb4LHDnlJ2VSPnfOMSisHt1cr8pM7rdXTOPXY+ksn4YZKm
VJ7m9ZyKcDPP6qrKB4l58pTTnhkpS4PA8nw6Bp4wpXldIlZxFVyo1drBnYv8oRHrw7Lc2fTAxw5n
vW/YFMe2zqmkR1FmpvqIDxOXVy0AA2/Pw9hZwuBJoeWJrr+SrNl/4L07Xelrsy5b8gqNhqdIajyI
y+u30MeSeKs7lqEWgbU+hmJmjxWyVoFgsHdsY/o0bvlsWse5/4aBHxF0OTv/PyW1XmpE6xCJQP9Y
T/GDIoiyU2YIolatUy61w6AYRmy2dpyoLsl/7wXaHaNFwl+5MuDHeGeEA/cTh2+u+Ve51ijROsdt
7+b1SrLDh5lfhGeg0GTPlnTbI+hpulOLj5dUztyAQF8bI/0nQ5ar1+4BpWwEDSlw8v9g+v9FQBra
WfoVYI/6FIQ0e2oyA0ZLabpceJVeGMeXrZ8BGARnQDkLZtzU3qr8wrpFW6dfcBCZet8GkwIxR2du
H76lUETq+++Sgof2TZapPqyUngcjt45lZUmbjfypxBpNG6PwQK6V215sAdhokbW/IwLobLVeMawL
AQs6bNYYPqgbIEkUtATTEZtz0nSo/Ukqvc5kRRXT3lC3g6BWCYFkz5QlHEWDqOV6JCxYvpZgmPf5
BA9R3jL70tPNcf/qB6mNPp08/s7MXowWK3P+7Rgvbu6uAdOM0VpzfJvOGsDBj8KR/uKI1fMz26a3
oD8lCohwMhyhukrhg4gOcbrS/MJgX1zP4KqNYGvmOtMC3fULa4vtYEi6MIQfzqu1a5aPoByoVa96
P6be5cxqEtqi2HgJQrfD9wTpH13ByHLEZbHT6Jf4u2lMJMKD0w8CtaLVsvHON1daJ25ECxjxMSZS
RoRlinW5cR8wGHLtTh09xKeQgWuHRKXzH1zkxCa/D/+uf0hfl3ZDMdQhATXURgXXHPwQpGz2g+2/
s/2JORpcZF/ivblFSCIc5Gyjw+2fTFkiwkxdNPsOA9uLSub3hCaSvtk/w6FKNvGxnDT/sSPB89/k
mtf2I590EHAilLEMRkIr1TUgGDMpBp+9Q8KKUzIFpf0DarP8ymsyDDbC8ZuX/fWyNI6U3o+DhDUU
bbbRvf6LKoJ8jTNmDonSy+Y0pIH5QrIoz+J+PwatA6bu0875tBKW/IrnRdp2IAc6R4Dw7/1BCJNa
lsHr5wzGOJD6TWAWJ816vQDl5bQI0DyBqySxAOd7sICDsD3zYkcBnbzL5yF5Hb+7f7U729l+hYBp
0KkQbF5ZflAwuDzm4zkfS/Z533e0wdtJaHjgVye92Ko6tsEVqcAH6IbfHAShNd/ywpEsywFyf69W
hItGYgpVX2qWcX6KXMv/XcJ94XPSQ7W77PeeNui5FARAJ/UtFA+2QE/lX+1bYGeYa06LJEi1xJLz
sWAXApGxBkCvdnndzPjgKqhSl668qJCjALdVV36Drvqq6XtrdbmsMk903tvOadoo05MOOq+48YIa
RP8TT45EicZa+0wU+fUeH7wB999mdND+G/UyYaAok/61j03y3wjK+Yzu+fbKZn7ihvkQYk1xi2Ym
/C3TsQV/Yw9Zu6P2SoZ8ejUqfbzeIzADqt8gUpu5mm3LMdxZUeyhIUZGizVC1bsDXKlu/2eyGBKy
lOMRhNZzvBaPx3gBH3ny6+VAPht72ZoLbGG3dNplSsYYjmwtuH+YChLAT0zQ2WamfemiHKtsrcMn
4+haPfBN5otNSG3+kX7g68p6F9Gmg94epYj/3PzmyrPs1xI8a2ufr4YAsFhfsR3+1hvGzv/g+Xpo
LWB8e2JiErpFG1tfupPQFtTtLf1m+Z5fBpyHVBikRx65MUTZRoeRSypc5P+hnBpyvDvpggNZaAR9
lzqj4ActwToPiQAs/sTLmViUcHEUL1sKzFLEi5RwCA2gR+51xHoxiYtVZkiTasDpQJPgIP287EQ4
h9WIKtsZJGNg2roroCxKICJnW/syzNS/0lEXCg8o1JZEuDe086cPKrCw/O53/3ODqf+QPoVG4bBb
EKx2OU70T/rHX7DfEx2ANjSLgvu5+UzCkUGwR2TVIQ5KHIoprdvyip3qQ1Ap918BsEouGOd+cBuz
MABtvdtN0QlkrZwF53KYwgeYZdfPqZqcKfSuLUnJdTXJJNTdt1sYlg9JQkwlscYsTzdqHzWDGBoO
UFc4h34zAiGBnjmkShUJ4GsHncVgomT6/UyTd46uHoV132LcBFKsasxQPcEEpe66bb8dXfBvEq2A
QCw2hK7Q+0ei3vP3aMhS2yaEyUIGrP2dJyISfvgHJn2pAGb+JBKYV5UvtG4IVlDxxkEJltJKgssM
gb4VOYUuSxsNvMx2YCrCoTwwg7BX/O0TJHdc4WwdLT13aDsnmfUzQMnceAnQHRstQdsbxn3EVVui
A1G0pnFmh+fMoHSMrfUOEVPQ2BKbJARxA4ttUteKkTwmW8EXBoP3qsJFUiv0YQLHuLM55D0kSu7w
4ZJJkoOzDSwoXeB6bKDm6QYB22/zj7XXLji/vneLShF2vP0zbnyjJq5s+q+O1WDA9r7B1ZQpjhRU
Vd4J4dQ8yjarZcSH2TwKf7ywlsMHb1y/A5m4/0LGar7zRS+zlKJKnemAA9r3R+Fu4C+J40eU2K1p
DG66HnXRNaA6fDsoXjEsV6LZYVpQxzNjJZx9Djgz/+w5GZ6miRk3LXMpiN4WHElX+eMCG6mE/T6k
rO5JMoQ71NpC/TUeixei1U3wV0O6oka2pliOLynlf83YnJ2HU0W58iJ2YlbFLQvajGekURfmQ5Bo
7SI6lBS94Jc26MxpyJTI7XPSq1j1QpGW1MK90uenDT/7klnMnabBfpfXh2KdsPeCZQGZ3Rnao7/p
sRnYwngtatw0hrTJyUvaUrZAEO9/V/by//hoTi/njXm/Ol0UtnJ2H8NQKJ5IqOSy1pqLzmn16t26
HujSOY4BcJbgKfwpZm2VK+XbRSup8tkT4nbSf3oKlrOTKZOmyXyl+m5TPU9ymMgWV5JvjLrYwudh
rCFYde0UeP7q4xsv/26VvXd0AUd552gsrihEYIYd73f1YMwmhlKQHrdJvSAnM7+qjooiSlm3UOaz
5TbynsODItElwWyiBq1ybl82IslS4zpNWkNHjrFI9zAyBhtr168PoCmDr1wwqkEnGUYKRkN4x6Hb
uz4RoM7Wk15SaMEoSdWn2dDdp15xlw3UTH0UyCiCHI8ePSOJCmCajJNPds3s9RpQbNnR5ZGtoiVn
n9aY+lqe4m1iSZBLAVs5zQHqFsmnNR4VljMH5nNeQaLlj05lsHhB3RzoIMl1DmLpSHxF6H6tSjom
FWmd0YeCQlYyEVNZUlFAI01mJbnBIDfl5Zo6jojsNZQCgXqBDqO+E/jV0Gyyexuwjf63Z0CDaV07
Yss0tpxp6K4UVxQRitFM61m7bTLvzEI4xVlBJbZDrGMJeAb601LlBoQmWHv26bZL/LP8tBqxZwWz
Z24B9mnR6BA8vVvMIDzQcpKDcm+oy4yfy3fQhGcEbHiot3BDU1fiG/76GX4SUa2ZG0EqR+pK0gjX
lzRRlJrYke5xueXbyGM4j/mU10FMfoFG9Y+u98aK4p5IsHAQ2fXH2yUND7Mz54ijJZw7mo/DftgL
drAN+yG+HdQQbHL12alc8oYvSlCw3NbZ/4o+dVvZaxNOuzLBJzjKKaarO+VFTODUXSVVNZv1o9KY
q3NYHsmWrzyWKhI9HWWD1rtT9MEFgzHhrqLXSarjilTGD7L6x1rtGwDN/UA1q+YFbYAjzLXZQjic
aB8trlvjaRx0JfidYM/dLZLRr26KOSlXa4fTHNpwXDZmOGM7SPFw2EE9yaSp/HtwIlC0oYOmQEIM
3fvmk6YEUtmPYT2jka+jiFrYpOWyuq9gjPuEpY6sNWePa73r6ZDBanQbEqM4cPVdDY3lNLGF50eR
RGiCM5Mz14ZOQZ25ixojkU86uUy4ssD/hDhY1IQuNhmoYdxCGOK/jVaDRDAROp391cuWSP2HDIJA
BsJz1jYTtF3abdooKljaQwGIXceIdypXdsa7m7IOICkmFfVBwzrX6XfR5FCUx6WYEWKYWSttNf8L
2O6gmuPotkzK6x4gosShzSPI9ULTxlpPmflQt1dURKpNxrNtpo9jYAQo+ZjDAh91ibonOMwWQZ0V
p8Z8VcQGVaUW/71xgU8slcOa1j55hgk2Pcmkrpw9/Kxn64hTutbN6ygOr3SO+dp5el7kIT800K+M
G1LCgRHPunReUptYo4JBTx6ZE86a3BgP3MSYNVezzFzRa9uXEqT8ADKnRaDIG62FiqAwnKkP4qtq
ZLmWowkEv8au0Pj3hlpd9VjMZlF4GMOpaBaf/HhTjOUwQAQdBc0usxblH0Ayuby9IHzy6+TGYa/J
sxiXVzDgLshXs7aKEEaDidnX/hquuTrD1/ee+fUKbMX17+0GQntiO6ijZc5EUY4gzYZmeZhFwauz
LZFhqRKOJT2Q3wtA6b/XK2mveylDddPFVA8grmo1PNRvk/sI2oZo7jX6t3+WQzPTfdvIg9w98+j1
tuc/xvCdFanVnYlc9sIWw+qqQJP1cdDcuQi34PTi5ov12TCtfvsNdYFwFn3yOUJ9KKXnJ7TDD6aR
qPyNI6cnc4mTbFc2bBvpskYkNJAHQ/bB0i6YIy7sbFF34bbxmBBN2QfymI6q9HrJ1vwY97Fgz/h+
26mGTUJLTbUIcp47f1S47oH/haDkryPhQUbU1CGb8G0UZjXOR2ZxA+BmbK4B8XKIxkysyDg4+OJp
lzMfo6FnsiOQLzZDxn3A95XxUUrxHGc8FcM3xuoKu/ZP4omH+8AjsOV4uq/G83arH7LLKTAsSx5n
aoDqmTuxbNGKOe/RO0wj0ZNKB62gPdAJ4KHqJ7POvpCeQhKuFWw5EV1PGEcw9PBg3RUf8jjZaaVC
/CIB9u6na4BFKFw8yTVDO3YAvbsyXQZzj1oKn3Gg1g4Fk/5W6It7QNHbGdunpJ9GQkOpOW/bu5XZ
HQqGzNKzRdhHvUPvRt+fXVtEPJh0TmV+4FOmotH7SnWN26Cz2MacsLW9fdgaR8ZT0iCHkY2b1Wsy
2MEE/0vQgilwzcwBAJS585D0E1fsyg/LLJG9QkoGYSlccnniXxf3QIhu8MzEukQWU8l/C7+LlMmT
faT/mbXa7Ruh/nXcw7xkPDyN4wmkekD5cXIIhQzESvdBQwy+uWvgrChA1stI0suxDi+S2eb4avzu
E8n6Q98FQlSuK+caieXy67TSdt3CGm+dR5tbWJGJQZSNvSifNBjpNA4YZVvRsuT51SurX9PBVpQU
1R4/VmAlrUvMULdX3v7jXA3aDNZM8UoHcD8BcsEMPGaR4jcbIr7M4dP1rUk9uAcOI0MCHv148vk4
DFVN0tVnk063ziv/hqhwADyJEzDSdeyBMN7r02IBi2boJhkcZWP9RRqD623FBzHGVKumHlanxa0X
U8ot04Gf3vpHHJj2Gl0Lbb5pSe3Fjozg1hAFxOKWFOYbCrJIlGbfi+xh9NVZgfmlPEOvnOGWToDW
BMN7Tm6kUx27DnFlM+aw2q3U1U3z3rAFJKyrKl/OWbrtWW2cVcgfBz1FLdznDOkwuduLdLuVgHt2
gNAUj+1JVbXUNHQ87MD9dRRRPgrO2Ll3G1i/Pe7uTdFxTLePDtPkFYmBAyZUDLaSCc2o9flr8LTk
SJ5mEXzztC1qHTbl8+kzDlwv6Ljx5IOnXFBwaW+chO+H9qcJV0bMrqlsPAcBWipGnOmxseMKM9NR
SiL3AuLti2OTWesOE/cL5T7moslzciQXz6pCY1a4e6Z/fVmWy2mokwJIveR39xqBMhh1LZJAXei+
Io4FZ0yZwUiNvQFxmeoKNFG9pQVl/mUe4EQ0Xs6J+bj0OHwH3UpCBVdsMM603M5zfAZBlbq6nl/Y
Wi0iBrW1XEtJr8jMzr7+Y56qwrPqhWt7kZAjuWI3E/Pr7UFsKcxR5pOPksa3QrfVaX72HCuo/Bjp
EQJoC3Hv05fPlscxJR3gfAXEcCodDnC2kNvLLMtnHAlE0plGZuJD8KWpc7OWGLop1XgEXUklO9x3
1TiB/VX0TYMVu0S05C8/C2+Rwn7Bz2oxhPSBrPf72Xz610WjUI4oA6MPpQZ+X7mujCC52gvec4Kv
bf91E12/nkjJqMgPT9j1WQcRNX6CwJ2n102T4fxp7+ZXqdWhYANuTX3PUy6BEaMXU2r2bo+Xyu5K
7DPplgOQcH5CCzhsJcEKbj+nFQ9irsh3+Ba9UQKgi30YyzKYi46sP3Wu1p5ra2Uw5WCKLRE2Y0iM
BMHXYawjGDWVRtwbVMkfcctY+OEmPmPQvadwZmVBVF/rWcm/hp+na93RD7pKfuiAOtcWgcWx0pNH
FOVemJpHF8W5nNLAoQGjZJk94N49Ife3jOXsSpL3WsBXDlpszIgtniZOsLD57HSMHRHgYdxrWrtb
MD+oBqCwzyPQjhXM01nRRXUsWIaknp2doAA1oktPfLl8WNHkvXhuZd6ABL79zFnZu+LB19BMo0AR
0UJp9QuYe70KjbgF7mjVk8cvdVyNP6xFuyPoMFs0d/Uw382oDQTglNx3pEHPRlp0qGqFLYn/M+TU
YzQyqKEZxIEIz4lihDZtWrQLP6IBtsdPQadI3oZOBvl4KQsTajmWy7oZYkBVgyU1RemfFkm5BjVz
4dMhggoQOrENKSYmLEiMtekMewllX0fQMwhFlWHoBQLhZZahrtUpu6p8SmIM+jAnoSWSh662y+H8
0+rJzPOLEBWBTIaMmNAKKbvhnqNA+U1v04fbv477J5jNFSqNU5rjBF5ueAqBNB5lFoNb3Gpe+pL8
DLmm7SBgXhiBGPcUwv8b11IAC0p9pFgdD1tIFEHtTgqWaM0cEa2v25QVUCkPTb8Uv4fGsxI6Q6+K
IGQ/D0+cygIJ6cFJjaujJgeaH6NbS9eb+zs34lo8ZE1Fcsi2xeRBRA0k/QZZzmEvyWiv40T6UaVa
BfyTGfenaz12hw7fdc98tWddDd5X3TOEXlZU3XYwj65mpmjdXxXsMhujs+gZdvN2MYgRFaZe6zf0
DJtjvhAmldWY4XA0ekE92sNMquC+zvd6SuhuKAmDpicBZpHtJVoS2im35aKTZLjkT9OZBMKyRkRu
WEQLeatqzdJvhRXRnm2GxrUwjLekfok8im43vpE4STCyJUQ5AScYtphKXvmBzY0wHk1M2ix9a8A+
FX4cFdG1vuhlPAPGG8wwfmhB5dbcQIhejerL+O2W5kUn+aVjqXKCeR0OfQMqtLAkUDqAJ9k6w9RJ
FHhL/MfluzGwkBSckNe8UMnYQ2Tolr2KgL9eJ1xJz1dxWHb5g1JUpz2o4RsGkQ5GMJlyh1/t3Wwu
4hWgTREYXEHiZxleGHILfa6HI4iEWk8F2FFM5l7LetseQ+Si7c6WQJ6QoFwucZUNEBwUZRIDSCwr
NlY3tXVhAUry7sxSKAAAOX7vtFQI831ezu9cQQ2N4oM1H3wSepZK+gVCNosMNVguVj69MO27HJWF
Z1+mzflTGolRs0aMrjB9Wio1ktordTyTPxmD/1UblUs+fMKawGXYK2WIpmgheWkUdlDHAcJwQJzm
6kTXKXzUTHmcGB+CjKmBvb2OZqIvx6Tb2FbynjfO6chNq6TbHeXL19KbLgCafOPmKmG/526ZXWc/
3NNlLXjaUamCSX4xSKfPMnTk8OsCsA86Yd5DBK0z/683hCNmIvJknvbuY3sUIehiY0qdbMc1C/Ew
vjQQgSXZBOCH1EFsyM0jozqAjMA1KGqTTVxCGGw8ShMGLC4weWU+GggsW3TNrYUqiB3aDJP5AcFf
ZFGUHCUXp2D198e+ZW0dR95FX+my1uOK53+v7dAk93N0Ch3HJkCyR3MLC74nnzuicFq4AqqCq5TI
XnM5Y4a5dPbWl2kEgDYkluAmpHKk7AqWeANw56lv8Q4xe0/EaqczRH9rmqablKDRWVpjc/tJNyqu
1g7B0KC6H7u8rvzXpO1SGdyK9J9IxX08FBtsNgI85EpkAdeHsZ+RK3s5BwgaUkue7TXRM180Z3SV
ziVbbcfxuyXLJnjxNIq1jVVOonm03+x3Ag7NSScY7G0o6wFugyiKuhZmBi8rcR7a+alT2Wlh0ysD
upOVl5Q9x4B0rmOv+HYztZcI44yzvyQZVGDXw+kDFkrn533WXqkK34DethV4jaaCHJVGSa22cA2F
MzqQvAYkTCYupK7Z/fT3E6QQpnJp/qM9lFi5XstFHoCRZkuKJWZx2BRqHqk2MVjhITXstlhrIwFK
oFxZqvKKW0Qttw85ed5TMfqvej0vkp2r5AILLLXmXx0onhMUu4ozmoA5Hv1+SRgqNDq9JttAdaZI
JflruqsoxpB6WLEz6vUohINO9FZwYUvkt868kPa9QhrSaYZDF23rvWzkw2hYu8QgpCTZAk4KvzJ/
Gyh5YLSu9UiuFEwJAp/6EpQdjInjhja98f1FkYuawgkXtNaH41DsIKnPyTC6Ye0gltMpczPMGQd2
BKVbJ9xCSTGxXdeEYhP52dSBBvRYBOKOHtg2woBpb1wmQdVENojfrGMyvWR+vuxc99Cci6O0Flih
QZxF5A4264FjlsDkV/Z1HDnC3R6a9oLcybPOF+QmY3+7paSHh8NNmSL27f5XussWdVvLLmD0YDOs
nWwtGTm95TQ82RvFMNssJngZbSG/MB/j8U6ea37hH9I0A9xQCaDvJM+q6bZWQDRjSu7Vru/kxI5+
/hOImRlmaa6fyRJBLpqnf1lcQg7fQaiesSqjOUP4ev/gfl8f9qV/YFtRuuH9AKy/XsKB4f4oJAyI
b+NYPYTZi3eN1i1DgNoIhEZVp7F0ojvwe7JtkopHia5DEbVTljezXxWxfKEtQS6qzvuHbIWoRZZA
NCwf7urhGI+XzVDGZqAfaCDx6YkL8sxpJOfn3o6O1JE70wl0wWO95iDX4LEbZSzE38ffPwSCzR/g
nrn8UcFQk5mtADrm2brlGV18FCt1Rd1QuW+vFK9zb7mxkChktpRCrNJQK5/GHADihocYdWuMMuWs
dr00+9/Ah6xlvPEn5EJQwojcRFkN3KGuDH77q8q4+IdV6l31jU5fQNc0AdhLySY+dIoPJfBd1I51
o/VXnE7824B+OKNpbKDF8pQj/5/gsG1JtfYVkQBVC0DJIvMZY6L3hCeh2k5Y8omYR3CZUbp4fxl9
No5qJ+gB4DYcfcxdqGQ1jTZe2OORE2HopqAphm0fjt3ACeQjbRYe4HEa+01YKzqD9lzmxZoSVfJK
Dk2Et5/75Ha6koFPxRsvmUV5q0ZCVzOOj+6To4XKkeyEuWSBe3LeOV//htMtJPBv6GZ6wVpgmrfl
y6RZP/drwYOkf8ya3ugz8bVQYa7B17vfICWPVNH02R/SpaVhlk0hlZibJ4PRhSZN5xGq4ab0WQPQ
P2SHMCYqBjVT/+WPMdmphjRxcI53qEo2mCqR7St6Cm18ktWS+MHdaQs5v3H0nSXpiUKwVjTf8EuW
Pc+BViZbCQTYvikj0E/eabXNZQSk22KABOXh252dq+KFwb66m2CmOt1TpgHCZzVJz17wUhvMLCnz
x80mhlQGR8o6S5THM33jIwnVDoJFalc+IKbKxXAtuAWJ1PZFo5l+kQEq1+t9tRHrHuC+Svz8A10B
82sFUCr2NzcXPqZVsCqxhs7Mdnysbnu+ivXPcJ2ewMGCANN+Cmfef6RvTyxba/kM540E4i1hlZak
jWU2w5myq3jUtEuLdold+h+eEXvR/dR9Qv72QhvhgEcD1fOx/9fn37rd4oHU0CiwWqj+PFy/Jh9T
VgMNawqMh+Pch5bzXDposmEZkbBdNsaxKKkUSvj48xVc8c7ONXgSGWG52EfabwfRkWZUg02nmtM3
6tbfmv+G7F0WVcpJmmU3LOtDQ4Dq49sGW1Qnsq+QLJ4Me5eKCQuraFjhHqP2Dd8loUR7isFBv7Jw
uWUmRjR6Jp7VS0aVLlm5XhjNhNMnq7ZEULMteRyt96QLwL4Uivzwy2CLU8LhAxh7P1QFLZIbOy7Y
gaFOvV75dVC3FTQpiDKHSq54NmzxfIC/mC0hvuAyUsByifOaKQA3Hkhx+IUc7/QI+xDCUJYYIzQZ
ZiR7IqHfp1MGBMy9/zO2RGAnUrRyp5NuGuLD2H9I9tjuoVD5wrdorXPi1+hzI9r1xgJTY1Cin3BA
Mmhu8ifJ0inzBftl8gU2GF0y3qp/hGy+8tou9jy82P2KvZuFj+l0uCGGGuqyxM8VRoY+V75OQQwX
AEEShwKaE1hRkaRgLegfHyrkYswplULPlYyhaqKpcWR+Y4KW0wTelJUAOKzcXIWRk2DH7r8fv5Gm
4yiEt7XkNmnVkYYnIfLeFC4TLv6PxmcMSPR8a4QUuUIFxgAEpiu53N3OsnZn3sb+NmrdnXB88BoR
Qqie6i0MBo2WEzGS3ROr5yd3zqyoucTZwfpaxJ1Pb+MLOGoNBxAw6ZgIwSeXjbOlZUzxDDwnpUkn
cVi4IRD6yMW0xhXNRhhb+xvdXOgge2bHT+4CUjMuOTmQV1iRNmZrMwPrEPJBYvRUOIBagAGbVoJy
I2BGOjQ1PlayB8UM4et6mzb0F44Mn/v3ld9N3bwU3Hs1Y4tYAvA1yEP6oasSzo53gldGSK8L3TYv
MGEtZ6uoLs/+DkKW6ijjiPqndcy+H3yTB+CXNoCVkTprgixGQVxBIIkQE9LEhsnF8pS96ip9blUQ
UB7ejgh95KRvATZp1dkn0N2iszVvpJ7XROaR86eBAQi74FEvdoFrsYHjrmvRUQU6Lvb8U0RB8W4N
JXeeqglU41ALFffNVkkCubnAAbWC+Ez1xjJ2Zif588bTtfqLHo81rHP7tnbHDUeUv8zNZqDOJH9c
8U8RujkfZfLdixO/hp0jxzhQfaqYzoQdHexKay0oPZWyUi306dSkp63N5dArtN+fpyIk5MUrOUCU
bY5knuhf9dDupx+qWEG+q/fU9mLZ5eG8V+JLNSRBfyOlBaqZBJeIjlxgfjAjQyROwpJ4OudaoKJ1
VKo+PPnr2B89D+C2ohIO3UHrTIG0/KS2ES13GAjabIYjL8X8IZ8XkjBz4US2GTDsYynDHWOt2Bh3
rK74WXbvOholMsdbAo5PuFixKSE57hCfvdDUP6gmDhv1uuc5jcm8JeCZuENVPRLK37M8R8NWALxE
cZKJ/sCma7cR9ooPMIt2J8XE38UTiTCNme6xLdMPgFGuwgdMyTEyDsBoVvPv2CMnw9BgoVGIQLFV
x/tJX/hqyD2wjTvm/+nw5A2p0nRRobk/g4pbuIdR/PK5++F+3RaaedxsvftVfxxUpCaEh7BlsvJM
uS/cZS7btl0AUyrsG6ISUcPhRqHj2Nmg2CORf4mIjuoXpbo7cpH9uza0fOzZfCKpiqoHy58jwbiY
x88OCuC1s5iHEEwllACpQ7XgIoHIqbZ6QhfYCBHXaN7IjpH10d9REMKkE+n7v4JrloecqI8kMLVx
hdn5rjfbpSIUv0LpZmsLGmBhyJJ/duyWZ027L9Wr460WByXbGDrR3M00+4mq/TuMjJi9gEoyjUV+
rxQjxXyirG41tqOGAqfUu4YG0FR1qzJ3nNbV3fmkjX8A5oIQj0OIyeuJRizUFw2LgMS47FIb2Vwl
To1bNuXpihadRVL1b+Vm7XXRhPglr4YmlBlwm0uiIqsv7Ru85g58rIg5Qe6CkX6pq5LC3tfZaAKY
P7G+9N6+C582ZWXKDfsOPZuSHHbpbfp9D3JbaRQVdK5ovDERhcY7jnXJaliv6GbuFM4eZxZ/u0RD
RfAZ25prTivb0kMhyU3KKL3qEqxZ+ZKh7sKb5JYJA8xPgUYGI+s374R1xAQDjMs/ZhbSNIgZyOm+
pmVy7alwMxGGBgQzN0o1UzU28UwCf4t1qAt4LIUgm+QXKfq+Rqq/UXFPfGySbPi4uI1z+CBMdqhz
mxfmofY5lACubBptDzjSR/n4Qf1KtO2ADGGVf5AGVO6RBQOSrd2k15qwaueLOXINzyQe4v3k+1iY
13jV+jlhziKrSmhcx0lYqTQS8XABb4GbbLDgolCDzfJnrWzRgvPtel3Qx9v8YUtcWotHynGQzed9
PsGF/P2exVU2xNJ+26+cE95vKWJO+KGpJ+WYLwNoqP7UwG7EOSy/ZWoRESjfPOEb6vRwxZA1+1++
nb7pdGP6VUkbIayB6T4fVqWGl3qfTXCh+FQcd0RNlp54ldP43X/bpVzzvhzv8gA8gFXuWUJ4Q2It
e6pNGqYVj0EOKNxGXW86Q2yadUH1/IJRQbYOebv7g3aHFD/+DOyVj1R/hf0OZCz9nrNO9HfLvuKf
SDwB2PKEAGgoS0n8Cd00uvh7W0PDisSOzHft1E+LPkuDpzY1w94w52yDxBe2qV0Be2UslGwxQFC/
P9sG//gErOdUKS3rl++uMlGqBANXzkYOEdpuNoQ6ov3QhQ6Zow6hQfvk78NmsYSgemgJXmBFNJ6s
t7fJGkJugsAL+ArGdZA2zGQM38ccjK7KFng9Dg6Y5R7EkX/qf4lhBpF3cXoVbAu/kALHieKKO3mF
3Xsrmuh63ISwqgz/2XCiaqeqGjm7KP0gEoI6FBT8bCBbRQvly03H0rb3qE3JjUdiQ/KMVQO+VO7G
LCHPdcibpMh6Kv4km0QSXEufWQTBEzxYfrwKnCUtbndAhJGcKcdG55JtpzjbTBVL8rVc1p9NpW3f
gW+oAbAbr6ofrRK42/aULcLpd1TipRftsXpt2dAcmLUYuTJjep8vjjyV/kBRHSOamabLut9IwYYn
xUxymnrqg5mIFV2UHZrXoT4eetAFDBeDOwtDlKiwH4SBC4r/16aopAAe9CKRHwDrYiVONT8NQN13
EJHjwxVwsyDy/Eknus1km6gWTtRkix5LYnxkQMjATzfoSSq6yjuUJ5jaj/vW05bIjJSZBJ/ULaz7
jGc6HJi8BvV0SuXtUTAugB1TkRs1k9OPqn7MYUbJgi4sxJkY9c171YcUvVAXkAs8Ah5489P0UutK
M4dqPzKWANEiLP+pPHTUTANjHbUtQF+sO/+D8zN8kbnrCj7/UPPvB9hoE99ecTZ6HgHQ7nqcjcvm
lizEP5ezG/iYvptrQzgFvRbUGYV/V7cBfzRTG811UvTAIpOh4qtzH5pnD6671Ei1ja2lXOMgmxu9
vLFdh+OLKVdrzUghH5HZFIj9Vk2QIzBs+iGrdT7+F9xjs9oi/ihqe8N1s+f0OzHVd7V45kxyBerl
e/+i5Hvn/k5dQq+etc1aiyFd6MFJmnc4yuRH9qJZuDuLrreci1HQqTSdB9KcL/V1G+IKGeWreeVL
O/B6nh6PkQFoHzjd5pYskEzjwn6ICbL1aCwabAbekufvOZlt4zSunES6tVa3il/eSO0/S3JD1xHT
C8BqNl3gBDaGcQN7VN8qSX+BU1Y5F6j0Iyaej8K+9uKytTSXkXf8lmZSik1T7AkefBzc386kXlyR
nNTQlHaCHgoPKfOZdSL1Xzr5LOUyMJYRJIfmWNsVFD48h9B5EYMQpWNIRSG93LfOEKTHNux71yCO
Xk8WksZ3j03dAZv+N5INJU4eqEA991PjR0FYElR32Bmu/YmhXKnQgkEdf1NbwhhJV2Q2R5ssjDD9
ZcVMjRunWBegt2EKEM5tdO4shHJG1sjRgFNxJPGmFaGbai6JaSI1lphNQueIvK39ohpCdISlxK0R
HW4fiHRTKEzqHP2rw4A22Rvyq6XwxW8yPJAyzGxwgerR9XdDVvF9NUv2/6qSnMacha0KS2fODhGo
B1zBVjgky83wXIeF9FYRcMes280jsHSXx+SnbhHVn9r18NXS3yiMQWm/3d0DeLlwYkxf+CRNM/Xw
hR51LKHo+31qXkxoaCP/a9UULhacFZQbsyRMV9ITOh/2lyCNF//FkUFBLnuAq2Y0xdKte+H9b0a2
dOaGR0E63p8uNtCSuPXwdsiLvIAucetK1F5ERzmisgx65o/81BVbFVFTwxHKB5GG1tMRlWv2Qczq
Yi7ogIdiOdRmk1dGsvnOamjNjywwRdGCbpm60LP3uP3b4IEDfRZgZmDlYKyPTlBktm1AIXsbZbYQ
70vj8+4t3AKKMahvbOEjn4FK7oSmTWFvIflRZcoo5pgzxztc5nV+6r353sMaJhcRBK+gBiHtfx/6
p+95KnQ6vnwMACnq7RKZPYnVTBUfbcUPz95E/cyhZ+oo2H6E3nfCJZgwhj1iNoAcmZ6oaMjni+Ok
fWfru3Hml3cvyV5ABj5EK1SX5tCe0VhUtWzjScumrrMJulyiMtnPI6UG5X7e3c5UCndfubS8zqUR
YhaCy//+odwxDfrlfaJrk1km5t4K7d//n4JkA4RvGtK+WsfYG1uZLqjzzQaaPkv1rriIjpPJrkxZ
fBxGUWg3Ghe3HRO2RM+7YvptoKyTM5jErIkP4kEycrPd5c5cY5MO/1KNrJEUfu3ETxSDT1NqNXsn
iPATehnSWd5WPlC8h6umq3eXYrm/STV9lCSLOO15iGGrRLKg6zqAt/+rSs9K0Ezm4OuVitlDTd2d
oFSY4KPkoZ8npnp9OiwTlz6uAdM9EFglPAHLHBIQdmmJrsBG0KhPTPw5nN7sbXx+INWL29p9kjuQ
RGjU8QOAul7A+/IAkkWmXm/8ftt3EdFpOpUeH6wXHXWbtGk8ePig+Vduw+/GzCbEe89nGOwwU9Fc
t8nBTRekRfPBZXFuqH2a8otMThaMP2x2yiutyWgBXvSff3nMcJCoIWqDjVFgOs+6VHh+fORHnxwC
DU3CQ5lmhej2Mg6jiOT1QlR5i5ZasrdPiISBGBhYX8vXr0BvwbuJASxFSZSOR0gCIDEcv2DZ2J/g
ITcifCv9lTSflrk1GT1XGyC8lAu3aj/j4WHAG7/jlLtHQXu72ecDrx2pKz/GymYl/YZ6eiPXCW/p
x93IN+Ap6THVwlQ/mUTqQXa1iSr8I3qFSWkGiemRNwEzvoAmnnJeX9BntZId1GWPBNGvM4fiqJQp
bqHV07ihZ2zUs6KSw6zCWjtFgYppHAmJ20mixaMhlBZx7Kmz7JZehXxt0ZTrJ21cQWYI+odQzW4z
/IbaEEIGUoFgXeBLaguDD7uvgspiZiF4B3wg62Myxnn+dqnNnPdgAu7khq1X6JLrOBd4SlVc8eu/
ZWCaE+t69r3n8ohyORc0WwHvKUTaNmwFU5GJkcSc1Yvl0+Qr3mUvs33/3jFIB99WhWP3ZDVnnmmr
zMpME/Sk0Oi64upnEfk32CpfUQ05+aj6hpJ/swo3+qGjsSIHayYuet/DEIaCheg45IbCrmN+39pI
14qZIlbpbypby0bBXU8qD2PbLrN/6wdjbPeH07lI8PiWffquGMHkCy47493btRJM75VHA1h0q3G4
g0N41lzQCeC8tD1MePZDG9+eSmyCuUhk+aTxXmIAEBu6g/EMrmZ08yS0ji/49FM64Kc1D0SDmLKH
oFolJFaNF5fZ5RV4/exCX+f64MrPfmbG1cJ7OE1UnRNHdqloGox2BaXQZQxXLUKcbXrwuC/04IFQ
MKmBLh/QhYyOlcDwlsuxzjoKG/B3c8cagacYcelQf1Jsla5m0XsP9oNWd4EF+yZJnfNtPHPDuYxD
VrabsXNgSSy8gS848JEP6srr1r6qphrzvW7O4B3x2C5IZghrxMlZP179D8OngxqyckblVHVDFUP/
jd79LAZRfkc3JL/ohePscqamWZEP6kfpv3CK2DXFIORUcu1pwfPV4Wu2YoDRR32t4wFmFuoZ26o5
KyTIztlbInNRk9D+6WFyBlxCipnE9fDlvLbV3hGZWcavaaNijFPnvl+7pFMXuigRH3PjrYi6e2aD
dsghdY8Qjbjx5rboTicOG5BIeshojPjxWr01+q8IkFjMrx+JZ1W2zpR0I0r8zoBhGYaodnSZ2oYT
jS8jpbjxFhU+6cDhaoeUcPAVyoaJHKv3RpbvGzH3vywTAfShz4xF9YAtO+JlzOu/KFitTSsf6qk1
DaAGKejHouSQ1beqPytE211ad74pmtVOXlGFzQQ0HSfoqTHJPhKFwV2mAML/mwh5gSN17uNKGVdK
UMJypul0lu8q71XgeNGUnqG8uqssTgqRxhh2t+CnR9Lje0ap7Oz63KzveBHbvZjtE7j9buL/kGhR
oKoXzZJWlgBxPrwK+1S1dAPeBuJvUXW5oxeouOwcsmFyJ1ZxUyEUq90aClgKCAFN7b7PHOcpJabC
q7aLtcODKctUV+wj6MXLhDTc9FmTJoQghAmp/6CkUEw785/SRfMjvdgrg82QgaxbKAOiSjHkxcEI
DPproGFWZ0wh+lJYbfpMZG8iU+9pbAbN2E53k5Jr1/vtTw6PRz4S3ohX/aEkcLk2US+ij+Lwv9iU
fNdgd7ihqY1ZzSCZoIF8ROCT923HC6bCQsIaIqqb6Qj/laBNWCNP11w+jOjgLlQue6GwG2uCpORi
zUTNVW26UgGLgzOg/neVusPtc8Kvv+iZXNTFoOTLHCCC6Yd5/E1WRgHog0WjBUrIfT+Feo8WQHr0
NpD+syLHH5yf8uUcyy2ON+isNEzSDJp2syIUIoz2ZQ4hpCeU5Ras3Q2h8X3RGyYhUEL31xw/SCg4
xMLa1V9BI8d5qaFKYzPi+m8DGn9l7pP6GCS999cnu7ldD+W+mc+XVliiTRWQLDpRZf/CTCTcRB4m
X3ThhzxQIXuVA1c3UrYLVz0nhAk9dMf7MZbnyzMen5qtLrAT1xREKGzarZVCJQBbooINIqN2G4Ki
kMWecoI7KxRzTiaAE+UGhzJiWtGSf+xE8Zrcy16IBRYahte6o05vqGJmILVFIroqUSr9bbV9yvor
DAT7+ahK2ha8ln3lD+a6k1ejPudjb6WsdUN+u8JFwk0gVrf1dsVXU02/9RaidKdK4iyMXUTbNPkx
IugAgCIAhQNHNyONco68caHrJ7+5LYGnoQ0IUovUdCjky/K0g8dxBCJoWPfUKDcQwQ+5nZNwuazv
1cG//k/tzVo/5C2SI8Z9YKT8wUQmblMhRxaeYO7ARZZpvXR28GpSaJhq7/oXJVfpNjbYMhwRGORi
3C5FPTBVj6e452+V2ZLkQYfIsXWXVcYdsNi78CfwwEka9NcwL9i8ZxExo3zOlJM67NCoOOhVA0KD
q1CAxf4pGh17dhGhNOjlDU+vKnhlFheYbhBEnvjldryPk5zIkW2LgztUb2q/rz34+ntZAVvbX1Ec
izUeYQLyg5oUuQvZ8fHcm9i+DFV4rMRfiCDVJC6hzGlyJuitcKoCVMTC7GEa42gOFrcf/AQUDZMX
oNaCLoxK7C6Ft9ewfV7JdfB1YaPCFsRa2INCddvPykzw1pGWQlZc67x3ajxURHxtOxn13EwatWSK
XGHIvWWS7WcoCZiEqVK0x5zCOmRahjI+PXhbiYmQQYu6aTE9TLY6CFD+cpvVhytzH1offbOnUdEW
Fig5UL7w+rRmD7PZifsSAMMzC4OQ1Chtm6HZqDt7FYbiwZvIHv6nhc+nt2gt6Vztpr/Im0oMznmV
FX/8eGc2ujDMsADXSFceBzQAQCFhtq/uGIXDy7KzdORmnOROw2IF7Iu782ecN2H2d84DjHTNldqH
kEi5Gm9pq9G4oT7SRF+PJhxGsU8Fq955nHpygFJX9Eg6W8nad4JZui86M1f72ezY6CqO7uW+TvRY
4kz6craTOXzbG8VfBpA9vf05v1CteAObmM062t4/8NA/OG3ek6p4yJax12Gtb2Hxj01YT19YNXTW
KvqXZ8DsqZOaNQTdlcFuwnHRyT3T+vf9Xag+tgXJkKR3FsAvSnAklNgGCZd9yCPhVuxCCrmMsC8s
Gk0CaPzO9MGjQw7uZUsV5RN+ivnVqlzIn3yVpT0tmyOoR/Pt5BXhfTJ7mvae7uV0b2ttSebw9wmM
lZapOgUnwlO3Il7TCUal3NtgMVc+L5UW4vqV4JeuKZX2nkSn33aXvTEc4+dK+iToWCOnqDb/5E/q
wwjjFACAjHA4KmmSNR5oLReyQXFtFboyi2tAv3S5SsUp3EnLYxu/zKpGTAyxxTVtoE+0FQACLrCy
gGWpG4L4wTFvsduMrMD16isDpl+oz65bUyP2i+eUu90WuTPDN6lhJ26NMJtmFAa45ZfNhEatY/s3
lxEFkscru3j47c8g1l4tuG9Rz0dJIoImMT4I/xhWWT2BuWLTKIqIwYu5litLXs/L+Z60DkB/aFEN
B3Q16H/yD1R7VjoGDSt+c2ThbK7GFzpnjH5l5Srd+Cfg9eVGFDpEbi1IXZSgM5h3kJuPhvIGpNeP
4w+nMPh5CcjLE1FitMHk+JsrtyKUEOt61ZgsVbhXvJ3E4WCaGsSWs/xgGGJC4KLinUF1WVGRMwty
11m5LOAkUjsIfa2GHtj8i0aAIej8xrVSX4pVs2qIUAvD/arlFzDBVanGjQwK7Qs+QurGU0lQg7c0
c2TM+D39EmkmjXlwk6edgu/uSvOMNOeKgOZJvlk6XLfVK9F7wb+WntMJwe7ytKwKPZmL1nTpHQjw
kTxm+OcqJqzqtsQ7RQzZhpoJTjQ2iX7LntzLZ922b+6mFdvM6TaQuCiP2SzXCNe5ow4+yxVTKe/Y
EySG8B3lVYYlDb57BDmr+oYdFhqj9VvkVTf9v9kmlwY1uJ4/aTusx4LAsvclC7IYhnSovtrTNaHq
pcGOSlCCyu3Q7Y8ecV0kutLCwFx3FR1ciqDowdkrG32R7rumvD+DZQO+5ldMO8velDMk1xiypz5t
UwLTabwwyrVRi6n2yT+IDpWSAeeF2SI52kBTQ+6ipuvD+uLye+n8Yjpn8A1CeXGzr+U7Q0z3hVCW
wOcQJihL6M9YA38diVDXoHA4sPJ7s48aM4WOMNdsVKvU3wc4OI1K/4CqMT2tEfUgCNgZvbXBcAa1
FvdQUJgWcxRKPwd9TpHntdZTj/NwjbMGSS4kyiGSiG4QR0atzO73UIM4OmXdOJLHUk/TWvlmVZMV
JlTXdtk2POs0l+HQs4eElUH3IklpEswW0b4iBpp1zAz9AHiwluYrn3cr1OgaulHVWgjYSMCe7Yq1
btKYgWzWhlNO42CjapCT0QVhhA8O+MsVeIQWnPkWBtV1Ph1POG1ipb7GuBus2R/x2mxtWybAgi8x
/QmPz+KQBa5K8wQSjNtlUJW/Q+29YjBXRaWmtUCYsPaFOUU1BW3kZBWwRi4/rWCUbxCsUXrDj6QS
fwZrY+Z0VKEJvN+5UuI8ZOWFjhPs86fGf7QTbPAy3N30AtfXixQf8N2YTNK168LUcFVcMA0QbM8K
ss+7WupauwK7byPdj1jVgR/nzIQcTEG+ji7ZA1NE48KnnhpH55zwLIf+koH3JpaCLfnwJWiYTps5
lghP1zS1ALrSanvPyMIxDXEvn+lMXsNcxxAQxGqiBPlNpQ43pv4L9TyuyYpsfVf9J4WIRgYWDlTv
Me1gQEbbtXYJb2ibbOWRFn3pykdtZyVEVzSkrbnT+TPLAwia8+kiRdu6SyuuVfQYH4HWVO8dHWa9
l9+fSTJCsPuf9pOjERIRj64aw1Y9JOyhrz7ERE2mJOdw3omP/1oiCmlReBssu9qMnP7zeVczwEHV
hNsm+3LmE4L0huly4iaN9YrWovP7CDuqHVQ90KsSagbCMgOx0yCcsdDT4F/OJxicy6lENaKylU0i
3hnuz0X0juhUkoFl0y1Xn9oxhZA4TRyhicU/cdWFoRpRBBLMUqd/j/u3eSXdaME51/wNb4EpjV91
KX4xuDdCztSLQ2yN9RqsDyOmQtRgsqwrrFtDwCeCijaV3CYRaXBPk2OiZUF5eZp72H4g+/KIsneC
LqnR3KSaDzvhwgcSGoJ90ZDR+pKro/wnwjgGZjefUF7rL5d7anhQYifaxVdOsPTVgiCDEm30Yos7
oBKNlbq/oFOSef9Dem/sXwQwr9EfK8yWBazrNhNJX9obmoFGZyufa+tOWkO4w+Gmf4Cni614SJ4Q
3V8tLI0b6poobWWSlUgc6k0dfB5a+MoB+Uv9Apmzf0ilrJINcHraJIJ+BSCx1LCkQSWvWxlPK+Ah
kekEegTd157q/owutdoyGnNnLmUMIF6HeLB7Jel5D1+zP5nMnqvtHcy8oZ03AoRXmeN+68bUGvqT
qfB3SHKZx2JdEi+RCxVM8MzcEVHIuTtpLTYOWLEmV4BLSpQ64IGJMKSXGDPs+EJryMenE2ai7RbE
1PtF/KmnCw4kLLZKdC/n0PjSsLcpLVjGPw+OOaKv7KjCgst1v/CCpiT6r15WrVDxD7wAgumtIYH2
A6hT5vzUUepTJj0WT9YDY9VSOpZV+teOWgM51QVh8JA9RI0L5WfWKkXmtSfjQsvO7VcUQ04WxdyR
eqt//DdCD6Oqsc0USKIpDQD4GJFYr7QhiKm46CP9LfSkGKSY5mF4B/GZVQO5Iy7tp1diZiGZCZGZ
N0iXqcXflXN7giZxgMR/dSVGUQKqjgQC64PAp763ODPGC2ArBhJl0AnzsRy1LupdDOLVNYk2EZaT
mowv7RdGvAsiAVVR0Sd1Adedp7hXk1Kg2q7gi1UPiCJNVfwxZp2hcUdPQEP0c2+z/VABVyV38ilC
5eIdt4q5tcWwK8/2r+v3LPCDnGP5Kx783jSuE9x8Nl/0WodEXe6jNlSbhqMToDh3AUmCnIlZz8Mb
6dYw0gTt5nGVp9/kHwfj3RHg0WCHv+YBtFnTZ39RXqjnOhF9PY5df76bBkRQiFqH0bbqIkeSMaXv
RbFpdNBXfsZKM7Fi5VUZo9dg30wE7A+ufRvL4CFqk0YtZpv10cfwn0I2lKWljEivy9yqi/C3MyWf
qxL1CQTGd3FTw+Wfe1xiwjji69akh/mERwuxY9hmwrejWXnFX1ZQKPrkD3U8Ti+AEb86QA8X3AyH
FikCSgkkkQon/yz382R8xlnqwCO5Z2357qAx2Ir0XBmZSi5TVLpvulujF3QzMe/4VUlHHVeg70OU
CxIZtis85INwUnODnCTzahxjpHFXyZt13XYi+TSubMaIU1/MUAloOXEHplNIiGonKgCsD1GrrbcU
WHLjLv5wp9iC0VUMt+OzKlyATWqlLOhrAh96sPiHH5iFmuIlF3vxE/GgMrTPf1i4uxLnaPVvPqJL
vpKtihMyd74CswPvZy1kLC0ZpT49n3QyeAVK1GUBc8tOBT/8y+v7xi7Y4bck9wFs76KUXG3iUD1M
+HU37JjT41RNdNN40oS2sbbmpPgtbcCQsMydW6IcXmtWBwp9LqKs1kSvHNZa1Hkh1HGDkjqCkbMb
2vv/176nOI8SihRxW6e/YZ5eKoOT5K2+joKPJgViq2uNChRYSqvIBayfr9EqYMJEHeGZMJRA69D3
H7PFX9aF4hf76t+cpd5BqZW+luPEu9wbohiy4brmIrEsslJ4jqmIyaljaIJsp1D87eAH0nlnRINV
9ktaPFY9DznJSZld3RybZUcJj+pPhcDwZLAw/sVB2WbhX/fosHKSwa5IJWETtJkqDQnXi4Limm3Y
T6VVAMI4Cy2gFM3nw6ti/RS9hz7Gq5SWGnYvzoWaQwknIoH+EtwiDB8Sgy2dgAVct6Qk3lJZjzuu
sjbd+/qAfm6VFDnDySQLbfW1M5Je3lwmARks89x1n3LAXJLRmY3jnIjoRMukRNgmYpltIpjxQPaa
jOUkDP0jzrLtThSVDC2nKvO2b/K0lU2vQ6Nai5RtCMoJAyErGAJfj6DSKEEUK63kbah9aKk4ZHds
AwXN3nF0W44Ik5y7HMh4Sps1lMk31P6Wtn9lwCmBHqIAGYx4ZVemX6NcQ0trHzGDuvwDplIiYJdH
3wwuZzGsPi/Inpb1xQ08BMJJxgSTB6/UF5QNehPKfOW51Rca24wSML5/6kFvyyEPF7xoZgB3m7sH
DHu06FBhLSy8/6ls0EGwfhkMt98sN4ormlt4cP35GmLRN6QfaxC0TPPWFmITdiyDffWaSenRZ1Rd
QIGAPDq5BoiGoC6CQbxfg4yA3qH8OnbNWT4MQL5kILBfLTiCbgzOREFbYEtJNgIkgRPoUz5trcRW
NBOx2Gy5ak2C2rLMHL3UR5Y2tE5cXQ7jLdxBeEdIAzcHdLPSgBtP1QzAdQkLYbi5LDeteyKSD/lu
Hn2nxYg796OOwYir8Nq4SABwefGA6eoxz6XHSe9JWwQPrdvUFDnj0ycEEbsvqhgCaa9S2K+DWOf6
9d6OQN9usVAv54qP+LVarIKOgItMumwp/cwg6159pE0mONgeOxqsWOTBEvvjh6e35zs+/AeUjTqe
L03yp2ntd7z9Sx6jMHivO/NMXtMuRGwcSZYjVzyd6AbYxSEW1aZ/w/yo6TIwtfHgBSPDi9Py77WH
yihfyozSnEu3G8io7a0xlJTVhUADOX0PuPLCC6ZX1ytdh9nzfhkMUGa0PREcXpB1IOCKlSSDUqro
vexIyg4mlIfyGePLnJfd5lqiy0E2E5MLinwl1YQdiNOmFO+cAqiWntEEvyllqesN1n9SlmBcQBaz
BLuQzDgWVmi5SFblghnuNnijEQWuLeiyDVPlzfqAiFMAg97kzxzDzlo05gKrS6AbUM0rozv/bOGt
ddUEkQO3NyHCDSqsMAdJ4jcwAM6guYum4tLOwHVgWIAGlKLPF0v0ZBCbcNBazou1V2as5xOPWnqA
U1dxOPZ651aPh+37Bn53qdHf588VspA+TXZMcM8ZDHy+0/gBZ6pVSR4NNyc4W8udw/SDXB5vwKJH
lmpMEvvsGpIjo+dP618gvP0yACjD8ZSjyG0USXWuFr8mmOjh0gY5Dw8DE7bzRMqXCVXlFn22q/Pg
A4+4f+tsQ1ii6ns2gpkaOrOE2JaU+RCfD2w7HIJZFG5dE5BwCp/22bUUGewtU0Yi+oFcLPACZfDB
m3Z7s7tJLXczwp+UGBrolKlM0skpkl25Z08ECjxlbdCpJkahzQCQR6uZmYlYGrSFHVMxMkP5mTiP
AfitjuHTJ1EBaQAyhHVc4MIPrXxDE97aQRiqw9c6ZvXFt2SU2f3hr1RYj0LkXduLrvv7qsuwFX+q
opvS2afmLT/16KiTLXe8cX08dxBR793MHo6z0aEnakRh2WIW54h3G8Xw2U8DJwr7AL5y4pHGe2lp
pLZmH2blyN44QlAg5gwUBOp1ZGqiMt4jBRBKw8XvYHzZdf1kWH+X6FdDSnjTYpY6CDyeUljqcYOf
qdhwnJKk9FPSbMQvn8y/1JGXwjsz+6QHMXHrJ9Dd8D6/Qk8OneTgdrOl4t1FcgAijYxZYWKrPH36
M3h6DbdU5U92dM4eUXCFiGCekAqCGZlMT9lwdiBeS+tFdQ71evdMJQnY4uvmfN6Zs2VFJsDyQUMG
X8Vr/MJPYQUp9tuSn2iFWR0OcmUlZao4E7bo85lV2bLaJ93K8fAwN8xA1abpAE4QKcxaIjWwWRU1
8qZcfK0EugGzj/hv8jA88qymNU3dLMtW7twIm+uyFujxMNjcTutCoCjzMos+M9u6uQ6/qzKUM54U
J5WBNOIA1tFeCK5GcGyf/G1AspcJdRd+NQrD+UBI3h6coE9h+PQ0IEw67HvCmppWmqi2YLgdXFg+
f7t3EyiSG4U3tg37RKsZzX745e+qCVvKTDl7zvPojLDs6SqVQUSrmT8xa6VsblwhTY1WiDaheNWR
KZOzL1CwZ0htwDXv9/jpxzPkHMeoM9gPD4azYEjMxzBkao0CEv4Gb3SoweHiQTcDvYdWZITwl1vw
r8kzUlRHpLvwffIAxaIFyPnu5ck9GPTkWONbjEgodkHsL6pgkitwHFSvxeD8brVWpGVqQoatI7CK
Kbqn0qNTNrmbG5xAd4SuIh3ZfsHJljpJ2gCl0j00zIYM+mLrw1vguDm4mJCbfFAUhe0OJ8eNcPGD
JSI+eR5PcVFC3xg9ahZ0h/odESi96gsQhAaKj/z4bBHe7pLuw5i+ApMP2sSpgwGAfzt7r8fKXrSi
JlWOPN04aHHAF56OO4iHCX8BLWBOme4j7GOR4+OLAxxrs/wYFsPZQRDzkB+qaZDG8DOmjx5UUQRX
1vXAaq4MLuVrZtlZRhyoqOmRVWNhuSl6wOpnGOGKuFkS/Dw+a1cF8HWJcgPFYjoZqPFVyXB9FhF9
IX1+eGSiEH42sMQe4Ojw21D2PHjUy+tFUKtX6Kr7EIDCasjYEGNyVFCCe6xThG1bKG9S3Wz4obPi
8Hi2YPCe4M9ajr/cp0Sn2NfYmWlKq8Ia/UzctgTPJGJHnludQHaA5MoTAV4LGEVkrQUS0Z/mTpAC
FLuXRV5uWN0UZaUVYVshzaaYs/p7Bl4OojtpAwiPMc6aEi2FIaA05zE3osE8h8aHFnycegQLcx2y
/Rlduoerdy6/sPhZFiBOEbDyz7XEnNel9RYpTS+PXdgzUJV62SLo+MtjbuMGAnLIwN5mxxriMO/b
eljMReX2Ep/YVmwTxgJd72xt1jdlYfdGxE4fLzksNboHq0w7llD20s2qhQlgGhiY4N4rs8VRyqnl
UZnnCN3jNRABeNHbM+z5ZoPnUPh5SydI9TYLAoAc/Zcy/uSKugBo6zUbf9Ux6/K+hDUABkUkOeVx
VacSBkkDHw6lzQ9nTGUK0EOCHCcS7greiObW9PB72GcJho4HYyE9xNm86fqQz1SVi73Ga2gBjNFm
UkqiXDFmV4HOM6+elr2VvAl6TwOMiDKCOKBw4EueJ5BzRDNkUdPYLHQcbtB3Xq6Fp0xrEUW7TlvS
2eO9RK2+TxkGsXphpEUswcPFj+hZIzY3alfNQAh42vnJBhdX2mAel421uCJBSi5t3mCPBsca2dH4
WkyZazjR7D6lbMvAcVcFzUT3/EYIgx+QMEm559ySIbMcf3d2ktYk5WiTLYTi3RbL55nAa9pmvG/A
EKtsLYRMBccWCyBztrkqu04Sr1bK6FFA21+4l3KUW4emyGdXlI46iNvoAAWPhSMZ/VpEcIheH+Eh
l64zL3BJzszCwlps+e6vM979XiPk6tITlyyhDUh7ZW3hrvNITqXfUjYXtf9gHPXZ8LjveVAAImiv
b627YKL6LTxLB/YlVbGgrlj4OYa4ZdF/yuAg/M7nyvIwK1bV820ozRefCVO5qH9iEeMRP9GXOTsN
I5Y3mTQA4juHqdx6cjrtMxbudV7+ayGZKvdQe7HQWNgoWEamp7ph1iXhsVCqNGgC5HMkFZG/J5Ak
z0MvaQWRhQiI9j2dEm8yQ7U00Ku0iNDpldNO0ln7Dlh8NHTH3AaFvgZI8UNsxU3S1w4UBKYYmZc0
z2u3OSl4U3UFYBnaOq07G376TtwCWNZa24gvb4AqILZPJrn6NdOcw5hyOwLc8ViBejTYzhcfiqiv
4RvXI6iMM0EwIcamSBiICBMLJZdhIwg+Dl4ruHTW2Pq4sanDpE6ke/WoYA6PiYa6CfD2zpwI9+gy
qSvS1pjabRqEuZT6frLe0HXV6VMwVe2wkz59TA+N6Q5UmtsEBOKOFRvifCrIM5l/g5uYomQ1FB1I
U4rAW2l859eYuMGqIiz9FXL42OdmomaViS7JtAi+pDSuZtcqyOxBWLJGSgYdomji35h6KkhWmeEf
12ayWxgKrJquh6DMrOemj1GENENOE7/Ko1Wv/FlEZo8ZtSh3yUeNzHBmkgKe3lo5RIfqSpvMzpXp
4ksi+gxq0cNzlcQskt2VWZhB0EtJpN6Usz1rYAT+DLjyOrWaEQk2EnTbBDtMfka5sw1ewaZ+4aTO
h028thnn43p1vlVCcXdP5rBRPfLXJ6K0vFn52aQrbl2PnSWmhKzJdekdUGRvnI7wjLr32dM86iSH
uBDT7KZ3Mj2n5O/viYYnTUMHAcyL6WgIy82k2FzE9VG/9H8+BPoSAdSK+ASWGAltQcfeRA44fyd1
9CznTDYU7x02pMkZwDXhqVdN56MqZyFiq7VG2eHJMkeFx4G5mMD6vsREJVlZI8K30sdemVO/u6N/
WefwhH5D+NUEjEmI4fBM2kazZTQG/KAHxlGVS7yww5w/OpqmCw6cT/N8w/8VoFYdCFLId2rJyQjD
UByA5uXUfahVw8+vqYZDs8KkOLn3URjbuZv6ABwzAnwAMNzLzfB66I9REixdGJvjiGmVPqoF8f4z
rQw9SXOGzGd7M5Qsx8kM7sQkzyc8lmdjrmRVj/F52G65KuleXxZojJyny+o0XAvZBhLyOu83CKiI
roE9Umzu/+J4QsvNKnx7fO+kVYw5HlYwsaBCoqfGAuapIz2suWZlfRfxPdAXqJ1yb8sgPs5sSUsl
VIGuzx9Pm3YyOdLqBXSi5QiVurtYyIz5sLmp2T4kH/U4YndTUyXEbgxLqgNtEgQdixohYLtDrvVu
KGh70DxwrTViQJ9bMTGsroH4lhGmF0rOEUW3ULRsmKvbpiekz3/VZLvkJ1Wo7WTcdwpcqeI3euig
Dhk3zAMnaw8GUVi1UFbJQed67wq65VQ4pWNkSDoLXEaQR9ESMT+4RnvkKYGXdSESjRpUYWIKcG8O
wBgao7SpgWx9W8+l5bIQ/3EGOkVkjn4nf2qs3okszXFEjh1NkJYs3ejao1BSkWDudcEj45oYQgOF
XropuU0fYbN6lfb3XFycJE3oZ4FrtFlkzwvvW5D3/Wl7erSFMRGje/Yu21F/OVSQeCOE7GFm/vBx
YhoTrKqueu2cH48bAEp6BZQZ+2uFMvxMpXB2SxB951WHM5lGBpR7JmOgoYZskQLAL3Gpgu/hgIxN
g2SVdz5H50F56DJYKIpyGRVbbEsvHcr59Y2fLls+7vyvLVmytzlTwDlr7rcoK1LFIuMzsQwftWdC
L8s5Fyo3rIyc8FsF8XKHOpvfvadR+yb6PnAmfRXS7kAq3Y9LW5HwbRj0iB/vKTXLXhX31XOXqMDY
LDJSG+x5Sx30E6rHrDaXO633he+BG2OzoWX6KGvLjgBRrXOVwamGBe2fao6KAVP9bCT9x/kMrxuG
pTBz52MQVr6Ii74YJMqwH5itviSHuu3C67ridmD+ytiwL/sI3KVbbQ1mk5ztaGkC4YJonl2BD/UL
18Q8WwVfUq2BP4aZ7Ssigw29I666QKXc7v4Z525aiQx8jVWaPS2Nc1rLsQYsmLROKrpayyYPMgLG
vE8a6/0NRjwTGw1xpkqNoo9bRF/12uL5bH3vJTmmlJsCaZRnATkDHFyE55yEMuLtw/IR+X93hOsG
PjGlj3kVw/9yQ8YcVv3ZsYjkl3/ON+nNugF/Hpdx6UJcuadzGhtZADPQAwUn2CQbTUSGu+9Z0Jp3
/WYLb1GOO6ZbKVDUSw+hFWOgkpIo4ov6kORA1TzhM3c540OlwWsUXcHQJQkH5khKRhCUeHNbMP+9
YSsXEvL141eLmMZeubrxwYZ+amMxA1+GsWyV45Z6YOLrc7Iob6rxrdzuya9pn4hbFwtaBwEK4skY
y+/FCZxSAK4ehIj2132pOoOf/3cXApqm9fzhDCrQYrlXXohzgcA8
`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_mux.vhd | 2 | 91985 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dkahayCYqd+IN1ynrpiAawhApGkbRzkAoSRCTbdudNr613vDedV/sXDi4HfrK2UNGQUEwTAUekds
x3EDMqmkrQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WJ2GpXVWOumM7PSkskdGIaHGp+trqchuHYOmxLQtMzjzbjBh5Dtfmw3eX9nZMwQDqvlUdkI4ymLg
in2ZHA8VIwRRm/VCG1YyamxLxvEFgPwCOi4o8HZIo/biO9JgXdYQoxMhPDmYJvl1njAtIVgQtfnv
wYv4vPMmlP3IWsic6Jc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bDgtqkvJT2kgMrIvHxJydVEsv6eAfSIRygTmZ5ZSiZ83xBoCwSR77PlIot51gU4UiOVAKKrNH4bD
z+pqKlVF4dWPPRp7nIj8Vi6GTb3SK57Dos4KDWgzfI3UyGQQljrvUD3lO3bvIDSJ1UC+irU/rgIq
ejxA8in8aYzX+rkFeirBBCHnoSV9IPMfws4g3AS1n7na7YHXxinoaHLxJLWSo2Gkh99JLJXNWFLe
PaZxuQaxCx+Q/uqBdi7/R6IjFP2JLcQKuGs8EE6Hh1uH2i7UNzd4Kv+pH+d9SQGW2+8rzhbflRlk
fC62SMgfydBz4uL5zhKNslko3Wa8av/8/VLAfA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
0E4Vgc8exwEdGz1IVS4sBw2GCZBJMj1LUDKd9/kQc53O/1jd2Nx9eCho99HcWnEL2hLJaM/fzZH0
gAEUWAdIAVxeBBdDaA/HJX954xPtPK/OIUA9hZo3t2/DXh+NyWyUWeP6grGmsx84XSdh6jevopgQ
T2XWcpWcGOaMjtQLen0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ioWzirej46wj/Ulk1KwDz1Ni0CnjYCU2T8EDx4vz99q3k1XRJLviGTSKfaFJZ13K40eY+4vYI8DQ
MzmwjrcW+5zup/72KgrkQ0bd72JGGaqwdwdw/C2Uq7eJeF7elWqJh0NE69DrhqzzbxU6ssIJ1dB/
4dVb6GcewsZnHNvOYyoQ+v1nnugVqBYFeYnyNgI3xvtlsClGSdBynn6sw9mMJ5oRW5jhKEQ4m4/k
33ONzcx0exM8hBY4B2gL6DiXByk6DS9HA8cVqDMvkshlxO3Ie82glSV8OSzr3UKqaq1jQ71c1iV/
kfrGxN0avm5huwXB9RBOIqWD/t78xzRvyUHmLQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 66352)
`protect data_block
jnhx6SBMs6lPLHukA0kQLb8HoaSvs3P3JD9kIf0rrC3OqGdUoWm8HvXmEhgVzbDjSlnRakI2YITH
8eQ7lYOMHIgnC0AbGwCZtIAhiQaozcCKws/nJ+j+bi9ZgwvdxXQV+/HX5OHldvq8OW6mC+suxj+0
ZkLvQacUFaINhXBXjjtDgyBjZg8i9NcdXPtyPEhnOXkULWH1r2ZSXsfVF4IlqHogP6VvOTY+ZoRw
jHuzNriIBJ2i4io+hvRkfDuY2rJ7FPkK3MRM6utblESkVuoL/CwBuJz2yW1aw72g98lJctj98J6P
y5coBsUt+or7635Wi0+HOKRooPAVA6RjH8jIt/J91bscGW9U5K0haw5p8Ysr2umcDsUat9wZ7weJ
7Ol1p9Tiuuk4PWxpiKmcaj5c2XcP7W59D2rIJFNrKUsJoJ4mBVokEfmfgvMaKnNueeYUJQfsYPbI
ygfUMjPMB2W3YbMIBbHUz1Cqr8cA4QA+y780jjJ+rvCx8cKrDVcx+79JH8kjTfc6h2c57Gh+DYA8
M2XjFj20ZtDfn4MxnwJ6DlVHFJXIPaOAa7PHQfD1EarsD7GGwdFSXgf/4S/fL1/Q0KirTjBEOFT0
t0HoGoxnZdaOKSNcw6gBQxRbNDNJqzxJLxCdzZRDcm85XX4INqeoXcKdCackDpdxtKs0zKDoM/bi
QGVg34cTzJSBB4PZEdgHKe0HuEQcWfLXq5W23ata7v/iC5ZZfSYs8+r4uiJ5MKkBrIPqdfPq4Fc8
Z2sSqTqb5+ZQfjgqTetp9j1Y1ANA0qzMzk+I41nODaE5njBKlegSJ3PlsF/q1NHDsGR0jtJI0mco
NO687/0Kk6p9bjqOA2x9oSym/xpEoaVLZew8SVcQpROzwO7ogCwmhgo0DeEjvtSt+CgeMXWnYr0H
HhfrFYPCP/CxEB420a2mmQwe7YBqt92HJhDBC4XmgKC1qf4YZqCicrbQA4PNFp9w21/P9M5D3pjF
b6Dxewp19IsbNXF0KwLPgqTdSGs+bPOjzNz9lo9g4+fVNqyOcwpcfFR6idwUOIRW73doBrJi61Hu
1KCZboZ9xspA3W4ahptjuPEQ10FFKbxLSHVLmg1xh6/26xUjR8R9KXwjPtY4RPcj/eQphPJSxL4o
mCG3QEfl2f6oAQtCvc8OU3NUrysRBt7Xd/jZS0Rfext2wtQOCCskB3uQt0OXPw9Z+u21PSRKw5O1
raaPzeRIM8vIl5S9v0cRj3J4uVi8t3ans+qiSj/RFjp/TWmwP7ynjE7P3RtYXnPzHKISPg+ER+NG
PwypghohscRc8n9bgdtCNZPIZdTHSygqq5MSDInIqXINLhlbPkMzkv31EZvaaBidq8fdJs90Ilau
PNQP1JEPLx/9lEe/rtD1k5kM3Bsj4wVoyrDZv/eZBwYvFdQGVRkm3YOlLYd6W7JthJ2NuSyK2xob
j+jLpNoA2aO3KNVCa9OEyszxIJG9PVHqnFrTa18W+J82ocpJ9FkVZtZ7CgspXGlV95NcKscceI8L
OOHk9O3ygCxrpVT8did/sxUhdJ/4vs3nHAVgqoFclCN65661PhiuLN4yf2pTvI7gEX10+Lrzo0cc
A4Jtypcy01v7Ut4d1Mr+iNWyLTESld6JExBQEU4gpSUrkShiR5BUkszCkVMJ9uUeOeAIYNPH4GTG
pdnYcVb6K3UutvohfdKdHEH+kF4tHOV+EcHrorvnb40VvD/JEHfSzjk9J8UUGEwF9pYtd9plodjT
2DtRn5Ohp9UU1bpyXINjr9glBRUvslikCKuiEFLMcW4VmuzEdIBSmPNSvsjcWk7PE2Na2+x2hxB2
4Bnk6U4LNqMOgXkxBrrhnSXCwmx3Oztu+Yv8CP9pRmOyYCBmgeIGfGdr0rKTomm/XsKEhUJ8KNuR
UtNMGIk33DR7BADcOcjdox+4MN+V2cWInFiVkHG1NaZmWo9PnnWnvyjNMbKb8keKgeVrWXf6ok+i
5xKvlxU4ooPeBv8qAtBMlVO48/qqaf3CqDZAA//KhEgyxVqQDfUWQ2310hPAy8VUtEPf7DMhMdc0
pcENeQGrGKNF3jF5hPAfY6Eh9rn0kPsCAESf1jqeNCI52h+BjaNfoQEv4/sik27/CKp9ZstwdAkZ
FF9dtzARp4F/ZZ6T8jqXnY75Ol095njPkNIRK4TF2h2/ULadHIRMFv+9u2p7uU/5PCBqgjabEvZ/
VeFvhaVlbDWOIQFqbjNnZxlqtCm/nKzZVpAWk/9on+x4hffjSC7YNiqyp9yozUZsxjIb/wxnNqNt
v9K1kKy+pCy2LHRaQgBlwl5ncMnwgt8mgE6YVishL9YgQhjSAaBP2NlJwooz1XcfVulJVGyr9Fl6
+04RzNWBwIsGVYPquCA5P7+soejMHyL9wvcx8kCXqw8XYwAJ8qxrFBjnkRPPKZZfleUQKN2m6UHk
+EkCBoOOlNSje553VDSkNW9y5SHKbGCjy0NsjhDsDmEIWvmKlnjA59q8gEfJuJOH3ZE8EXgnHajx
dX/dB95zwecCUKturUD/uZDlUsyUofqKFr09GlKqnR4tT+M0BoaNpIQwJzTBellPwXy13lOI9L/f
/31m2FzYj3lBKsZq53IfvKl9hTPoOeFc1hgabFbgqXDoWvnGkB7pMoT34HfuTJ0smfOPPq88Y9p6
riA6Ed3J9Waa8Y8Atjvy+OdF9LA1SC4LFxTceBdcNY1FGP+/jtDcT1gRgMZeKUfx2l3E6q1E+6WH
N0wDFtokjhushyZtCHbEs1/HnVqIkszSqMwyFfbVsgMTt8rmsxBg0pHHo2oeR3tTuo6LH38ahNky
X1BMausLcDkvAiAe7re4E6Y2xyqtMGU3vRgB0NpkB5xEMmKXwnVlKvPXHFoxoJEKqgYtU+T7NfdL
z3pfts6VaunTDzdQPRw2ERZnnf9sc6pfot92/EGd4zzx5pCfManXPQoK1EotOuLNJzrdTP8qJefS
aH2AfVVx+h/Jl7ydRK8Rq2DHB9ttz4he4mArTGjXx9ZP1ULE/aehaaKZxlyiJxXzr2JgTM0v3gdu
D0Hzovy/G9nt5JpSAiFsBavPSUAL7+dGXPDHo4cbcSn//8XR9PO43frZUjan1UWWLdqa12qcW5Be
YckBIULO1w51ZqcX74vIOpR4W+l4B3h0/Ms0zI+/C2zvR8Qcf0Mgu7qnUyAD5dE6M7DgmPlFS9Y4
qaHtdNPzN5iNISTMa74kxWXe+yp4FnWVRJYI3d+UaIMEMx2NVs5Ej2XtGDyQbzzVu7jylpNG12c/
NmfGdaku+NNkpPy5VRIvP+g6tZjyW5yOsiUyLbr4JCFk3crGbZiGM6tsHSSdUEQG/3itLL619QdX
qNBtsAhRuDI5jzjuy5QUA3AiqKK4RkC+MvE6F7DNq3tOritsHhzA0jOHh4zq7MOfOYkmIYaF2Vqj
rHewRF1R9Shul8WD/v7vUqAWupDmKVxSoAgxFn4mxhLCBA/I9wn3jBTXCGURGZmZ4D2iTXsTh/NN
iimgu/aMf7+nBRU1SYjSPlZuIiO60xL9AN+J8Ghoa6Q1Cd5yV08YaKgytMUiYzAWxSaxnK5xa94D
LpJZJgozH7Z0wc1YuY4B9LtfQvvrsJmrIqdRvsChhvo5mPXELUG3QM7KIYeLX1qavqXQxYPeWfOH
IuBmONwklpD7RjAKZXwa5xQ09nxHuM79BBjiuZBaCWYLuzALMR5qNh530j20MVtZFpDPnvqfxtNp
q5Ts5w3qu38IjNBiVyiTt+vhY5gLi1QGRFRxIcMlbCOgQY6uHARYCJ58yUgwDZkV2942KFT7V1St
kNPfpTsYyZxfvP13THstd+yQxYtW2c9PRXaYMpKrEa+BR4CvYG9pV90WkAAZJDiK6qUs7EG7tUr+
oQtDxsHz0dQmtUyMPIEydM+E1DdmQPV4w6fjDOyZd0syD1/YoSKH88xIJ7gTDuggcbmoRcHPzM0d
e+wLtD/WLCt33ZW5sG/+mLnZhWtFY7MqEkN3/Tvd+PIlqBb2xH4YVdWv8P1SSXiZmacxdBkqVwof
fkxXqDIpMKhr8fo30akqFEmNnjdNxQO1cjcbaX4G9XEAyrVHZ78o5T0dZ9Wb4C4Tf/CaBfPuyxd0
5gOsQ2xwFu8r2h753YUuwIUTnrFZMtUddET2TkCLOLoYnlImZGZG/FeJWYrhtB6kgdQjFVAUaXlm
6bzsqQcdh1UhjQDq2eFq3K/CsXfKVcm0m+U4Pxzs/bsjKTaDB+WkASB3JdhCg5OtNWXhgPYIui30
/vEg2sscoaBGxBBJvCzv/lk+MNt8bbon6dbU/NYnClksYP369GN2sMxpbxCxrIemY8M1jNyYo4BI
Tkg2pX16Zx+mUB+Ez1gvXQsR1GgCWaxSRIqPmruLBltZ/k3e/g+Rc367Cam1P+uoUd8yQWY9ML/9
6MK6OU08eCY1mh9XGpZ7k5iVxvBpW3VNusKavUcqNstPsKUeAqQrLlw9+kJNKHSw5I3G8Fqd2SyH
2I+rt1sWwJloDajUShb2bBcVXbI9MT2iCt8FRdAfGZ5Wex9J4sag16a8uWBEZ7ENVKqco7dDZppF
TzpPUPtnf5HD9hMfjOS/aS37rdN8MKcbhU7UYEg9FxBQojkEZZscx5f4ZpLV8GCaCErRM9QlzoY1
PkWfFO4XJCL6PST9wqzGBzKw9372uHqBhd/49YceNESKgarf3+9qEEzfOElN4sm6OB/VNKDAkQ6p
NoJSvcf4yBrboipgde68UPvgXAdzb+j/w9UD8RcO9Muo4NjruPR1H4Lt4YKgVshx/Aqh2+f4FRtB
ETAL6EvTn8qQvuUouvPUjbWBOX8K8Whi1E8rHAtqo+kS7dp4/XMeisgi+gTvaq25ZuqGLkgrNnAy
Qx2kI8i5crnRMckupmVecNfyume/jTKcHwoQ+v7GITpMXTKlKG4jqiq1IJ7oS7/2DxYHnJzJAMq5
HPDlEP+CLeZFh6OQQhnitujXLH6mt/v8+YEKYLhh2PkaltIv+4joqDGckkradI6MH6I2WLbywycZ
PZDxS7KNAWgjmCEoWf/rzM3/yngHzt+ywtVJScrV9rflezyZmmjzVfOFeQDNza1j+lHwnvxsdgps
eT3wNjnMsFZENuUPyyqhnuJmn4aYfekTHoVON824Agv8hRZpefWj3PhW7xdV2d/Yj7/A+QeVrUcu
4mKG02Zgns8oiCL2mzP86WLbfoOwnUUbRHqHXN+cBU9TrFZ2qCBdnvR69mRuvnbedWl38bBCEw1X
iRdQLgDURUW1VgyfVckjM1XOTINXA7jcypp86hRsUmYFSfwkwavvTvTro5nH5/fc5CPNc308PJjj
3oZL3j+LlhfH6ofzoi8QqRjSFC16mxNSjTMQ1IBN5VjN/GeL0XEXaK5UIwaip27ywVmSJb+/Gqy7
R2taK1/DWJVlYB2V8+lHWuKg0aGavofRmd5Vb3VS2eEXnno0o/C1M6851FMBDkiPf8yz6+Tub3Py
mblDm2ERLzuToqQYnG9CgNrJ/m1UWmybWxdj4ZHV8BGfB8eseuh/Vq13b415PkG6UXuisEMPOaM3
W+clsW9LeE4UA90PyxcHfJqJfKsFUVyYu60vCoK7Bs+XJ552wd0vRfzCVq2llRvaVBhG8y/ZUIvd
3f+RblNKHPUfkxSCiqyQO1w+GgkH621Xt3n4XmlbQIXDpY1Q8eI3C27sPAqxxa0GX0PuasjXs8yV
RmPyRVbaGpUBsDrpibHFgqAPRyZS27uxuq40ar2NOxqDTiWyPBP7er6cS8Dz1kv+aenLST1hh8Mh
OO5LUpe8D5jkhyq7GWTJOTEb3d03xOh9SnhLw2wLfE9aVButGEwO2go2Nv9Qy1Y1P8NcxbL21S9u
QQ120QJCP0/2Xao0yUWWtSqi3hYT5j4DSdOxEuX2xnw7oRisW/clImlddVaaF32JpcFYEqhojKMs
J5Pf6ZzUYf4eyMqw8a2t9zuqG+PmbmC3kX8jrbIgJupNWIMhI12R5NVWD0c89a5GCwQ04XVH/AMO
DoxhWRA/hNJlSnlpNRew/e5hH6rZq0vwQNnKw75BFYHVn+zetsi3acdWMO+hOeRMCok/JXhyUCwX
8hZZEgNorwt22OVzmq33hul6rXsLNdYSZOmu9wurI4rKozLM2fJwKGfBwILdrBM6rbyBe8du8qNJ
bwqfhYqEDuIIJudNRP9VyDcuvW2CFuOieGXMr3trjjHRHIv87j7rvxx4JAsgjoZ7kOowYijRKUPK
uO1DU3oGNP5EydMPdGx9ILaEs4GjOvSnlGmMUsvl+F6nVaH6wE7DvQH/bOO7+q0dqMAr/21TZGA/
nlNLVvV5MODn88+3g2v8vYAAx5Q+LxWWqpj1I8TdkLdfyjghdYTI0FgZoAjyGYhK5AZShKmdX+DY
gI9ki/VUmrSQZOItrdN2TIaJs4VrwFPA1Kk74zyCOrdFyRZAtzPcqF5n16otFkN+vF0oelesKipb
KYeKuN2zOI+Z7Fpynv5H3Lie9UCKbIg2aiADqQCnHYcmfjwwp6sONgUU27G+efbor8djjUoxG4FP
DVk+b1W4zLZXeVZ/sd8bfOdoDH2dLICpTyxcQczWZ6aluydEBigdV6Xug98goe5zMSogaZR5lqWn
seT/Sda6a3wsXpOme6r8NxN3vMIKEWntno1uQNGm2brfDFWx1DOe5BLQ9zr/Vads/1TvLM03STwI
OiFpg3mmEH9UMpzaGjyUI4X2jfSN1VTvtiKgW+PdYmTwW91NlJiFk5TGPfrOu2T+LnsLdpJy02YU
lADOkW8GgJwDN2otj5McqrQm9TFjVKzE/0gmKvkboDJL91HCdXWGcDsCom9A8kSa2/VF7N6rG2SJ
wuX4z/u1aAKRhEK0gcTXg177ru0tYpYtzTgHw4PDk/Bem2BPxtnJIITQefE7ZIwCyS7tO4hIXY+j
B8I+wLRQUEDfd1oEs7PsRdBFjQFUp1I6fwAS9mDxVgVUn2YK9FsvFQMSXoOzWGYot8GSm0bvQfk9
Uw5WhXLMBWLmspIQeb2F6jOh+xZYtc3AC60XMPK4sjAgouZK7xBTVk+kk4DddS+nxZ5RJW0EYmmU
KRGZUqwpwgjWpVUsd1ChPiVor+yWn57XnvrEV/62RCtFO+2SpUR6EbmdmDoX1JcHKMb9BbNIILET
OnASl1DnnCO9j3Zg6QQ8eL7gdZJvbYB3zBxFuGBzzPe6fThN+p+gVhN23Nf2r/mi0186Ucp/9+0j
ZArD3jJO1syKKKZATwVc+1Ic6ryPcJGAVXIVjVOfTuH5thiQ0bRq37/cdvCOVa6D5C1COy6KaVB7
TaWx8tuiFcS8abxjtam9WRXgtByHTzAP2kQNUC88znHP3L2FOpJFoD2VTi1oAJqoT5775Ewwpr5e
2K5koP3aGwLgOU6dSA03ViYDL6p78myh/WvJLw6z/WZbF5tuytKUjhUGP7UX/IA6omV6tL2+GwSL
Lkxo7+PEAYLF3CPvmKzftQtzK6mlvN7LelOKDqwCSkbJZpJL8JmXAdssURL+ozYQcRY7saJy4wNf
9HyN6SdZXXmxcGQl7ovZJG+Ck4bfFYaVD0ii00mmE6JH1SMtErthjzaBIvPQnzMCVFXE4wilo92P
atafIIZsScs0Xb9GXgtUKqhN9yvy98uNN+1NXcUIrKrzd6gUhNwyB+TC0fsw9vcyKbmIgTWXLImq
/xc+b4IKLSqmVRUI0qwTiYHik+txw1UH4dVxQVeMCoGAbcrlNE5zSiuuxPrqWrvOfsf2yTc0U9TJ
pkZT3PMbGB1woefhj3/NcqAaVodtjVpormb61sQne1JE5xEK0TLVY2q3US+ArMds3VN9oWHZH1Tv
tcbYLhb8IFnR4nAU5gDqPZb3dnGUBUtDUzkZrwyxXON90mGV4nUNSTQohnqVXwZ5G4Bp6FWiiVm1
lZkJQbf2hmbOZlwPT79zO0l9vILDMEqeLVg/QmCyfsjiDvGu4phTCC14Zqd1R1QQl0iqACsl2N20
paGvmKAtPIaepAMSIpDHzo05N4Jbsd/xC0UGoUQUwhhSstmRgOu/HeFkbu3Epi/aRQcgtjOsFib0
4S699pTKdY/6CmwZ68UX8D/2KHEujHVGnNFThNH7GpfAtO0MO6f/ApcsWM7LdaBqv5A/yDCCR1kv
XWmQv+ieCi/2iclCcl/VUEervHA60ZuOYDfYY/+kQJhvI1eEYVMDr23Z9PsH+HEmBTv7N1mMF+Zu
tRJ+VjWl/96SrB6jp+R1QwcnkD9mxjfE0pYkNSRcWriFs7LIWmFsDlGT1WgoOwPnOlxi1iP2AQ/j
F/QSnA3k/ZnV7cMs8A8EUyL0wObmwY15rFj8Tl/+ELdTZteYMk6qHW2neHWDAwxmBsJ08IAzYxx0
UH7WpvBAxRgwmdzzvlf1u6hz1E1zPj2kDEw1PWWkW/n/Y0U51UqTSenc8nAR5h7bsmEgCtWAGwN9
ek4tPCBtQqeLWD+0MM4miVRiS31VhHTRRbwVjWMsDGz/LrMDO/l15LU1zmdsMbxF3odtJaK7kmIQ
CuFjzGrgDCI1Zm4Iz5VFHaJ5aBG7XmXcz9jU1JG88+FLJ6XGvjIM2MLJwYbAJZN+Y09oXK3tjA0v
TElAcoKyY083r7fHaifQEM657VsorLm4NrHj50Cz1EzOLMj1+ZZe3qQzCgBCFW0cx9HDKRVp+Epu
jFRjHs62+RLg7g0uTl4LM9yZg3lWJgi3EZ0mFJ6d76YULNrJt0dgU0Aq5UWyqPSKXJLV/c7SBtIH
f5ZC2pfYV4KaDVmQXHLhGGHlHTzAIABEAV+2TgWPQpn1hwM7YaySPZPGP1/6q+zpbU+mrxjxLCh0
kS05uuLqeveOIx++SDqz67ACpNTMEHZqXv/kPfE2FqoTFG93Lc25TndUoq8X6Cq4iYrEmmfMhDEm
tHlGYgDEDZsBLJmbz6yR8VYq4qMEYjvpd8k+FTXVNJaoHsEBbP8z5eXa7KGJ82JK0MPHEIOFkl7m
Gju1h04iX7y2dd+J7QrIRPFOAtfP/jnln7omSvBaWScvSsfTbYxAR80wjn3+8iWtIG42yS8XOphp
Ot+T9lOXwoIE3fi7kLFqk+CyQkd05a2q/a65ro35nCjngFz6JAA5ik7dwbnskxrPmj4h+4nDzhSJ
xO3iG3CHS/tj+wAGCgM1Tfb8LfmE/Vec7nWs5JgRQ5ZDAzHsLtRWlLrsXC6uDz5yhGWklLEr5XBE
mZFzQ327U0TTyqmjzKP53nzQ93c+B/AImFYDt2LLSzSvQoOn0m7SA6PKFb/YYwzGMZEujJ6DVR51
QYLbu0A2sdZlb41v/Ue6qFXc/cIrysGSXWMrhTpQAr1Vu+JIJzoeIWkZuFzCsznp4pVN0W9dlHi4
8waWJS1312tXk0wpwvMP9iEPNPBSKM1m/pk5Cd0kkWbOXPiQR7FJG4AFCR7b5UdjnXTo2kE3HV0k
HhIulO4HzujBB/xTda4oTNjK+k5+WerXTiUpAHJu8j6uBOpgkn8fLYUrVj86GwBGAojyL3OQw5Z6
bqGC9ldV+DezT0Y/OkY/m0njm/42V92f7ysjmwTxMLltjdEtLXBw90K944ddhsGCLkvLqrLlVyW8
tkjRmf5lJf4S1HvF0nh+rmFEFRrHCRtV6HFhFYngjJQJCdL0QpJpZglM2jmftazcusrcVcSoDD7P
k1d7ok5tQM7VtKeMXTv0IvVLzfHoEj5MdoR94FK4JaPzoDcSf2SLIWaAfhlfjKmZWw+6N8gJjD6v
rgh785Abh15qfrAk5FOUjYS28mwkzZaNCc7U2ZBIrKdHW/HhoF77jPoPF2IbzYbmrdlUwyryb0VW
7vSGSDCRTsQieUXbdnGl/lD35nXfIqAJGAPqmcqQ9AcDBnPVtY13SX8GOrAeyMpvNZBNzJwJiHYj
1RfdHzIrs9qAPebocvW6KfWJfHOMhu6wjBrIkHighW72OaeZhKtW5eW41Kpcek/tZG2ITXuTxG4k
fv0ub2zpEozDIq4wKogkBpmbZfdh1U6E+GnZKB2InSt7/TZRxCMJ5iUDu0YjPl9YUFMam48zPR+6
hmNJobTPBHYLuhpky8NGcCV5GZw/ov0kyR5dDz2supbADbZSEVhB1w4nv4j3zdWKU1T/XS15JFFx
E9sX2aTZx+3JzsipT2UiY/ViL+xLwvgTc3dElPPc53ajP5OSfLKJhzfM3t7Sd5AMmIfPc3a/2tjc
AfE3uPgNTL+8cNSuIMxtEx+U96Wb3/06UZxn1q2RL+GEatt8X3EPfWcroyn7O17LK1nQdbbHKgNp
T9qSNEcuPfyncnPIgOGOyfnfv98nGPxoQcV9/A27/IDBRIyCMqGutwca58qo1h0S2gPgwQ2vsOdm
yVYmoQkGYfFIzwiocsNZ9MghRke0xHm2PEnnh6DfiETcEDLecNRExFGv4Qm0DRnWwR/eCWdTtU+R
r1pnr/Oi25rsv7ADj00+gJerJ5nYygjcvcb2eIrGRM+QQkTp4GJwEYkuiVDRvUFPIB9qB9YTc0s1
qPgYu8sifMnOK2VTTP07VRTmFi8TJdrZuBk6UHGko0yznx+YrlvUEkwea9qxIuzYV1Kd74tm0VRb
kCY5dMdu2lxFCjpVe5//PDuGxdxVbHleWJfmaYXN4CGQyqSztdCJYoxethDeIa9/SoUddA4FAHWd
IOV0TmLHz2SKCuDWXil5r3Ecsx9N2ptXA8pNt6azR5yA8rFnA0hw/rqkYSYjQ1VdOwcsyoRkl/lx
jyEOe+6kyCGRrGhGBxbHu/1T10v0Fkzs86bicrAa3zh4+NVcc4DlV/yvW+OtPaOKza3PCoVnmqav
NCvPOYWioUfc9VFhq2Vjdy+JvuRw/qGJqest8NWIKcU0PgZDaEfuAP6ny+ipLeZ+1tB7fUa3Nrcq
1RCdz6l/X10cM4iiVcUPY1qhpaD45nUcEYFkHaedfq8cJwO552UgBYUbfIy0gXFgPhdgIP9vu4hY
jmKFrt5JM7BYym+ZE3/M6doaZVhRoOBWBNM582zHcLfYKCNg4R1aIOWFy4Pri0PF0pFAra5If2dv
3zmnGbQL2CYGi0sDraDRhvqwPFO1FPiMkAr66Sgb1rfyma6NNREX9JbF9RNgLagDGGSUj9ijCxst
tvbLj+EVh8W7b8pHvR1Zx5U5HbLeisO21ulaSIF0tbDTCoM/YV3//J5p5/r5XYA+eYzCKDlYaOxW
UdZ/B9NyIwg31URY7gllDd/upVkepIewDgL37Ptu6aJtU9B8HW1eaosOSa8N7r4TyizcRARrJxrV
79sLewmPmEJqUzGZsUhi2xjoT6SbymtFm04/cLrehmervRFQhSYOGV6Suv5jh0Xyk/ZGsfnl5ZfA
YP7IdNwZozzN1BYFxDT1jhHXQjhZyBOUjlCVotl60uzzxEzwEHi8fRFE5hroUrGoeH2I9RnqIcVY
oQm218AuAgYl3MPHn4bRhnAFSiMZOP2LWa+f/U1If7K17aLT+FbWdJPqBaKjMC/gkoAuWtPZxZdD
vl8msEedEivBCdJUHZ/kTmVZ8PDVlciFR5EfHoV71ds22Pifg2Gol2YC1SqZLA7P8FtLsOYHGnMm
XagDyN/s72UiVr62Ws425mlsOIbG0beAKfK8jhWDmiuOHd5Uuygun7sRjEVSTMa/w8nm5xQcwYXL
EpIOZfzCMEo++10WDVdYKdS9IBevvzqiHaug+AhcNQ7zZ6THvcx4uO3uy0TP/VI3LkvQFqkURcXe
8dMc+l/Wu7mUBA9P8JXImxQwLFq2aGuIK7gr1AiODcqvLI1Q/RJJGycidENuC+q0E/XVbs7XTWmO
Rmsxir2wloSJoCzIN99DNOkoO4ofouufFGBynHyN4HeIw2CNHVFMv2dupFCiYRDE9cGLAmBsfMbh
krw47VhL6nBJUbity/tajSq/kwWNp5C5sH48Gu8ltaH1ladjNiqx2zsfcwGurGH4q9WwBI6a+5km
667chlN59gSbk8fzlhPU1F5rSYFfdIDuF/BBpqdUNwxNX0EgnjI3xM48+ICkwwXFUgPud/1WHCFH
VbOJORL8cgckF7J3IUxbtZWcrNzn+5LYeg9tMEZxfvbhUJ59uQnwJzYx5sWU4/R4ZWBrjM/7dwBf
shp7FgIFkTmT0vfYlAGSf+Vnjf2IC+JNvC64WqCxF6mo+gRpFodnIpFEZAH0Xve1XMzadOBFqd9u
DvfmRlRI+ErGbQ4uaolb/hy23cf7bO9N84o95iwVXvSFuTpjutqnKFnfTaA3aPgEuT2AhUH8TiRn
6Wfnq2sTR5f69zphbJWQ5t8rtnhyWdmYjI2xxzXvuSAVDbVN76CxBkwl0/ImPWJtJ9rDkGib4Q68
KpRE79d8051LONkVNaeQbnM7d+19DLVdcIg/sbZ88Qpm6/SdYzlpNnR5r0p9/55gd+VH7jTi2QD0
YhXHwZfgKtBDcN2HP1lHuNFLEKHEN3cpWxRgDJwRCEBCq9Tw6845vfgvtREQvLE8ElorGyqgL/s8
0hnLvAB9Ad0x0rGNLYuZblqL3/K91/Ia0OpOfYfccB35n9fWoPaSBpVvXdmpm55DHVHftYZguqnt
Xms3soG4ZaUwdnJAFsmiixhX9JHfFQ2MOk50rMJ0MZmzLzqQq5Me7uY+DK8Bk+NJg+UwIbLBFdDN
OkDbiZZIH3TbPgu4hpPo2yL6/fIQc/s37bcba0v9cccxs09Z+peFtUgrxwXDlFGgdlmOZWvv+Uz8
jF9+iHcg6xP9DkRotDaa9nRSBE1kK18CcS8oV3jkYqGztggkFsXrTWhN4Wllht7j1Nepmy3B4MvU
vHUiwwZ8SR5OpKa+qFZM7K9kID8ObZfqvN/yjrw0zNGrnBKChmRQZGPFwNkjuhavL4kZ/R7b3UXa
teCYbhSD44/MvU5TlTmzFaB+exnirHvJS0m2by/9ccDid+6Rq7jCGmZVOgzl2VDMcOnbLE281abD
B6bQPUSzqASHp1U9o1jXUgi94Drfo1HddX2fdv+rTS3o07rGFBf/1pr+a3OgwbI6AoqYU6/pmwq1
EQXPVJZ6a5O+ZqEu0CB4R4y0RBsex6lJamQ/hFgRvD6yh8lv+Pv7S95FtdLLcOpQMIbezLp6I7tt
G2INy/iVFBP0JbLNdZfbEo7LlDxZPzxRLVpxnbSSPltZ9WH1fAA6rGK1Se1gbAuccYHw55aU7iC7
rsaJ7At5ICBrxrkAi9ouf1oFfSiBLx0eAm14NShs6LPP6qCCu8Y0MzzCMAiBX3rf75iS6cBWR2+2
/Gr8KFHCy1Yjm/GpXRtWv5H0oakDJH640E6HDEDi9KRqExNP9+nwQwl3jiw1aTRo+a9zZCxzqzC1
h2iEJ77qzY0AXkkV4HuN+ieBO5eyCbbbbs/V8vFfIw2/uCFPXGob3LHdKxF1jWeD9v/s+Z0jZSti
tSTCREQnVVchZB55m5L6yZ68k9xZ0n+/FXZVCkJpP6A0PrmQ/rks33xqjLXmngcsXMNYm/DfGlKC
c+IsvmQI5diOq3kSfzYo0M59kQ9hkMyLZwokbaHvJDNuCH0eMD/cnRrOY810+3Atl1QTnvIAHXXC
IpdSZLqQ+0Bad1203ljB2SeIbR0jRrxqUZzOfCovkVqagPSRPq3OdDNCNk965OeslTSbo6nGHer7
OSfXltJW0t7znA7CFWGRWXVFAVzVNALXQ8aj4Sd0IcmY8/kge73yGMD8PO6YeuQmbXmVvV+no2TO
dgWxQMBYfq5mjFzlIEosLypntaDqXHbFcgmGpJHfKKL/1nmoLdfDnvAN/lgE/FyDXCUheew7c72c
tKLspYwLLKkqSb6CsWWIRJy5IBUx8+48hv0fgAWXCEoqyY40lUdO98zQcjvOQa+/p2WwhpGz/AfW
o9lonTXfIwvjQhQkaKwfEk864zJPWS3kIC8MSlmB0v7nqwJ1FBKLGghodskTfGRq3N74aCbXEpNM
4T+9/iPSGZ2D66tUCjmew34udOCYGFSO7OM37FHd6uSJG24U8a+eOY5HxnCJLXRyNDkqH6lONp+d
YhhX4E9oDmx7Nv8tXgVhilIDzFBXJES0AVTg/yDAkHn+aXMPc9vBiuRzlL9OJcym0JF2DbxFaQMy
kZhaESQhHzAA6iqIb1rRpCZeHWl9/M1O6xXlf5vnjh+h1etBqLVNXNaQ9a4WZ963TVfGJdfaUj8i
h1UCxKbRbXCuKtXudzzMFGjPFKmr17A3WZ124QQzRc6DKM8bqv8pUKzPKAvgdcPXjqqAhrGBxtmJ
zsfts13mTks5RLC4f/6GsMppPGLINrhaDoRjtizyV3Gz+UVWfRqeCbLZnYfNtRrLwEJVKGBve/ny
Q0ry+4bRAnvKFmltFJRjgybao4En9AR9p0e2U420RHxdVh1qzZ4lZ21wF8LeLan3tg7ggd1ijPyx
IJCIIi8gr8ZxF7ZaUi7nnRUZoBt9pRHRDVlHwGWPt+vop3y1mNBFbpaNX2eOtyf29obu4M+xjUgX
J68eaVn5Pj0w1M8LB4B/xaDMu1Mh+fex26mwZnVGqPZSoQEQ2EpgvUjICuVAS+80q8NLPVAHFlMZ
+s51BXWl/JRlBh1Wcuzz8stYKPsnmpeFqiNVH+kQHNtnTkEa549HuLVj+ILJNU6FKGSLzGTfFs2u
XbvjUnrJm3L9mWP2YhnhKIct0YfCgT8NvDmsuwo/IVjbEj5K6MhaliEwH0MfLN1PaNIZtEcSdAq6
4qUhASmEAI+NnSlnHnOzBD+jZR01SoLQJUJBdlAirNhB8XtM5XvF5aP66HuZ+TnmD51pklyLLZo6
L2KKjvMoCflEo/HzuaGb8uTRKggVXe532ifVhYXam9TLb60EVq5UDZRzf1Zqv9LHvF3A93NHLqMh
X1FoaGqldru2dNR69IegjDwFWr0NlA5aBEQa1ty4+7jykkrrlPaIeVWF4r1t6/DGYNKqhVY7bxg5
VyQvOz9avy01BQ2dsKfek9aGVAeIzKu7J8YmPWXNDLy//nATDDlpGIK3zoWOA8rUwcJX73Q++f3q
mpZH4nCJado7RzM9XSRHomy8rOIldgBu1EgD/N6UU7DvCQr6PbkiECiAF2eMk+M0LV18v4bZ442n
/D9TULd/b7nDOGllraN0WPVaYFuCg5gsw9ejjOaQZQyKIifOxjcsXy2g1Amoiis6WjclQaKrDsUD
+UQBS90Xd6NUi0exAAJD3TZdTxd9cYuCTetMym6ZG0R5CpGwuJSVfjUr2f6KjevGv0sJEkE/79gs
NAU13oG4kHZi2JhOxNDK0XrbzT9kZ6kBhVZHhp66J5MT7wGJ/IoxOYl/Fs2Usfc1j8v7F+uehi2B
f7/03W4JxMGFkov/tLGPTmQWacaTFexntUb860ZI04TerIQ5Ey5ICUebgAmhSJe5W3vUwJ/KZeVi
GUOuaxKdwgY8VOptOI6yQQSqoRcwzLrbnC1EUXm0tf5P/pSgol/Tqk8ywIUWAIEZnhKmOIEPR0N5
MRfg2fgVkI6PTYMFz/xIMkL23gcLG+M6v3S6X6RI2jRUDc6UiWXB8T03p1sy56Anq3BzZzF5fz00
/NsJeKWp0LR4MJzwAEbMj6Th4lMWJ819ai6vnjIzl5v/A84Rdn0AfrbMOkJy/nv9Vv64gu/iENUi
GIK9YCq6SoKiYcThbj48YindgNww0SeIYCkClHORAeYcr++no+2BsZL/GjlLDmT/0Jzq/CwHpnFY
kDnT5mbWepn15dTWDHIOt/sHjDbcJPAOThaG6Lstyj3QfVM58nMELcz/MUmsMsuoGIfRRMb86kYD
vfR6OPzCZ+hjBQq5RgcDfyUk3Zt5Yuhp5UpeGy7EF2ktvD2NO2kaJ6NlO9kBhPsA1uBscW/4ScaE
ine3LQ2ez78AWlwDM4755FvsaN3Y3ChjzfTcG0LBflW+2nl+wHDzPh4DodJtiQAyB0bMGtctBXA8
44+zlB9yyyYlnOaWolOp+ar6Oap+I/LK4MlDDjzzffXAq9o+Tct9palLzpU8O3zCo9w0fT/vLW1X
JtEQ7AsUmTS14aVpuik0V23bPxdWrKl1xELnnbfmkM9sAnG573gfPwy8dn2gxzckdwbGFTGa/bdy
rZXK7f2iakZ2vGqMt40Yh2Ga9vyQXd7FiyEiUEVf8wKQZNqxZ0qs/rkhRgK1EHHVEVqasVVb4RoI
WiHRvuZY/SMLEKsUvFoxjNG36303DWzrvf7dPBzb8M5pogTi8C4xV82YmvmYf7sb9Mfkd8PklRsN
WN33jpIw3z8Sz4/hoGlQ+kp1p2KiMRwuB06u/2XxnBKJcQN3owsqc3f7+W1w8YjaqxPN/+Wp2rPe
lrPhzVHnsnxZ9+V0dm3f574DBa+LXwYzUVFap0owuWchDc8xmuJLDp1UO4P+P2IntJ7jXzKCrRgm
I7VrrfS8Jr+HPxvSJXiqaZQ7HBChGal92VKOZJEEEyiLXHsOwGoijREsnj9gGb+zjwe0aeTJew/1
+nuDcJSIauhb9IpjIQ4BC4zH3iKkpy+I+RbfjdUNbNPZpYMnPs07u/yk+gWy7s2yDJe4COKaPVJt
hfnS6HPgBlp/haWcqJhKv03NL+cnINco7/KA+UnEGNdzZCJ3r+1gT5FCOzKhybegq2OUd6llWgUo
5jq167tXluzZdbkp8fJDc+75JUUCzpDjqTk1Nk2A30KqMRyKkg2HEZie9pIjAervwAjwB6diVEMW
3eeNPPw3tJ88HLnItoQqJj60ggVFPWZmJoMBqwD+pcOlhdU4tP4h2C/QP3c0ZXzREMuzTF/7MYAC
LodPuDmnQs3LL9SO5vW0Z4bNVer1uTlCZnFVOMwG7uPan6jG2jT7bFZjT+0tz25inDh3pCBq90mE
VwNqTPpGPRZAJNRX8e+TqNBbl3Duq3j4PNJGIpP5qOFLfQ39KN6k5hDK+OjG581/Zzgq8L1FkzTn
SPz+jRwS2D8dQ6BSM6JeH0U0eMSNUpMn3OFO3N994FkxFS8j6oN0U6JDT9ZXeS4xAU+FeAlDd07d
mOynQy8dg34/LI9RoGebG5VFYmW4bM/EtYPg1NOiYeimJV9FWXvmEHhC23MD++giToqpk4iuBqcm
nW68RJaxx2PrjcuPjo2iUHn0M4NDKn/3Xd2rfjcHaCHefe8WYLsODq6o6zUkRtRQj1EhQFERPRrb
hgCLeSLHre11qAvF4Zidw4C1wQja9UqSFvMndZFsbAGOhsoAOdzLsayOvLr4a1Jtx2+RzBovZU/M
xW154sUDVS8hGwAynpqfRH+yLHhulVtd05XfZg5kQqxgjf42s2nJl6XQUpTmsre7a2wEfEhB3c+8
TOX+UkfOpbPmLs8c7U5WxaOr7WXFycK7nga9V1HO95hcAxn+RNbEH5TjLFk9+WbQaKfy7bXZdVmh
ALV6kMZzac72dTOUnqzHRdeA99Ieo01KkqXYlvTcGD2sOkGGdSWzVLy7tMONiHR3S4GHEIRLmxPN
cOox1avC99tTCF7BLN7YSO6nH0RwdDsXjutEi9YN31kpHDJj3gqFA3iEDbk30q3tGvu8ZtgOYFkn
V/mCaqGDkmreVTS6+Pv5o5k9hj5clqtQQKHWmzmB7MG60wAahRkNLDcZDEnxB47PDzWIzJ29MMuf
TVdoOTuJFDefUBXhyX5UyriklqOZqumgQcTAMolqcBRPBrOpFYPXhW/qDhzDBI0Zz6ATbRaKZA2G
+OnJMd/vHzPN1JzGkdIC20tHik2Ja1lMY1p6TYMPuzlq4AaPjp0XKxkz/l1IiPpTMTs/NGCYPp0x
kcsmM1h0kQi9QOL2FPv8+2LE71yo8VaFhGhnn6/vRGDXxItOL9EOV08YNS7NU2zjMFzG6QXk0gZw
WgTuFEA+1Kpz9NR7eb/dvBT8+Ybz1cnRASVSZx5FuDr0pMLkaeJOF9rGLXUQiozCVb42h6+zmBrt
YYydjUpwb83Je7jfdX6mWy8qdz8l2rLWZJc1c+LUMK0Rw7HUUV4Gb/oR+Gh53SGpAbwLvJ0zt3f7
7AaJKA0MfSTNWcvCMRwiIdRmx0fJdgYKhPWEDrMUleYnXCgHbn+i1DxJBY5sOLJ/iV9Sk9eRk+yi
dKl7i2xEMuEGB2j8YkUKyuH2X9az1eIQQ1HtWTg+5ObfvkcwwK5va3dOKCMyl5cydLm3J0ElVXsd
4kmgAojqZumHVdJPkEvzvENH3fdOEKXSd2LPGNfyDllJW3cyLVLUWYahXKb4vzo4nsfnhQvKRIHc
2RXiseKk4TzaaGEu4uqzHPgGABcG81s8y0MwV65/mz4CiPgTsAG9uDTZnFxDBH96J0lzmDtrl3//
sJhXapx6w05Ajmnfd66Q9YftdNQk4PVnTJsQeMLIg7orjYTR4uKu2aGZPKaKRpVDZLSwYExHS7RQ
Othg4mlEaLUoHnBkVkcj7jLWFRkbfYZMVPD+IvwpaaxeCwWcFgWhIiMqJ87qpTGrZCMi5de1AkfH
ECQVaj8XsNE+WnzUeXt3SIwH+Q12fJ6aMhX6JdW5clZ19AwAalU1dWcfZHfwC/jEdNg+mXZaiVt1
EVNhKyrYzMe9XQFVCRYdTpTmTp5fJJXXJQujw1KRCgoeqy8pByXO/Bkwh9/aG3XWttOwD22qnlMJ
h2h+2vxsiT7jracXVP9FEoccMSg7w8tZmVdvQJIczrxpcBl4Yb9Ah5kIZ7EmV+z8bWAnOFZwiqBz
cvUNsGjN/QfB0qZlzafeOvKwrB6yqdZ7X4Wth3LM2qopZEB/IEQ1LwnBwmIFmUULdo7kz+/gr+jk
bZERFX2KeiaIcm7URuZGULMrml7EipaL9Rk3Zi/4w7739HndRBSIyTIKwAkH08s/zGKKW6YZnxS4
tmOR1bFHdnRje6bJrk40QYTfJvvJWGHvbLXO8XC3F02i86TroEdXk31oAIIOLNSwhZiZ1BSoM0/w
ddebfiTJvp6l6QC+xBMuVpK4+jqSXh5cEGT3LyFdMQIL3eY7mthURcbwwAG9OzmaH2IxWqRtF2EV
xMCPepkqj5w6DcUjJ2o1BDVnP7AImTZdUjotwd0+AVFwgyIyanq1JecQ8M5mT7PQrrq50SUBhDHH
eBwzHFF2Gb2RJhzB46GPNnyQZ+6JeAMmkT4atIrIsZTzBAwR39SZatx2Dw7bKVw4NVxaFqmf3aCM
t8QICEyuK34Ap0sUsKJqUaZlIqUsM5XW+3oKzlWBDXiaD0gbEtFTTDyhIvXBuJSSbfbXUedavWmH
dkAE3JtPlEJzyOItKkB4eMMza6sUWM/1xaQnj30a9sGC5sd9i1gfIPKLA90kW+JsegpG/wH8VPLX
VnvLMS6OhdXyLUxd95DgwIHxoJgITBSXmW0kgslEKLj++CmoaFVBtyGdzGspQ8e4u1WrRgJvu3e9
fqmqysgRls9hEOeWQOcgZhcuA6/ron9hTaorFRPrcSTMdqLQL32OcMb38Ti6kkgVCfwIJr4Eod66
tft2WfMO+9rpFuCnMvFBmCFV4DbfG54qwy9OL/ewyQTF/yNOgStaCl+Zo5TGsT993RmcFhSiyW7r
6/HSQ71l4PMwx4fP8Qk9i4ZxItCft1qP3hmLOOyF+UeOev+WaXIfQ7F0Et3andZJVHUr5DgiNAg6
n9XdkrF96MSKr17KzYkG3Ac4lL8O9gpHekLZiCkdzjgsr8eEWL3xaUAuahpVyQbIZfcnK3bYqq8d
S1f1T6gMKoHwjTXdw7wh0INcSPgT2AhizTKH+x3CZo578uGevLILpus42QfLZ3yRVpicwLX2mqsK
FnlilNWFV8iWZZLzHz/0kqoPf4+XUoVa4WGEo0hkRaYPyzMi8FwPcIExMwV1B/Bg/KtdPrfHE5j7
BFopu5LFTQi3BkAgZfCg8CqFbY8N2Fh9oCavVNGQ+Vg6bZCRV8oXNJrlWTmH0ST61mlOkrfaEkjL
I+lW2z3sd38vPVzCjC6k0OAI6LYBz9U7geX+iYoRqK0jt6nmOMpq51wfd+gkF1GNGfg9PgnyiX0Z
7esE1TO8zGx4WdKtV25bZccy4xTOqz8T5SFNqIQGtGT/5F/ipXyCAyAMU7t+WD+XMlIyS55eRa/A
9EJY9PHFIMEWoUVzJRELgbSrd8/g5dTIhrWPBQqMs7tgYz0S94kZ30oe5Sn22DsJwTYCl9ko8xvp
zHEIRBkyFAxWDv9CDrO7eHadn8UrICmC0Hpq9/u6iQ1I2F/wlV/AqCaA8KP+idiavysTV2Ea6glE
AysXvTP5N5iNV0GuFq+t00dN7000fDPORug/DnplF7b8052XuSsDq/l6ovc/61OszC5LV9ZbU4e7
FMWwchEG9AG/5Uc9roQkGsp/CDzuhMh1qSGjOwmDU/3yu9w7WmXO5xkjs9UujG9IpZVrjKLnMW0K
Bc8LmMe6p3qnUnvx3IlYF8Io3qb1T55RTO+N/A5/OID9myUrATh5uN7xVeNQex3mbZjB4y9f3JK/
pLR2fufSfRtBGFIww+E7sHwpexNpFh63QvH5dNtilPCDhtoe55+GZcBgyzMf+trCaiQimi8AVkgb
TwZtr/DAvEa1dJRgvqyVsKousRQweKtwAdI9GlUa/dUAb5KdRltxBs+WL9AdGy2Pty1SjucS1n2x
Ulhda5q5mJO4qL0SFb9IDUjP1gIbQUSa/LL98hxryHkcX/4myd5IppuUjTbpnKBZcDuHKnaYjdvn
wrXcO4UG3tjYICPleCx5u70P/OYfr+sqtOI2NOcs2YIdREl6uBfEkL+cw8Shf7NcHkvMC+cBrP6W
qFXx7sX75Q3/hlDAU6WNxg5J9jNp03VW1uP/Dk63k3ccVa/WtwpOVxOwqaFMMuTjIK8SdoTBEl3N
vmsmlCgfMwW/Rbw00wU09FfRr299fxqYowOjhcSczaqAK5Q+T1yBUKPrZUcG32Dg1EbewiSqnzn/
lebwQoUlts3e8DX7ThIRkqGyoy3NoZkhiJTLXN5+/WsW9CU5WkMGWwaGkSOZXND8am63dN8L2G7M
579XDUhR2obm9nujxvV4aVFZZaCtF4r6K9aTo6F9yP+bq8oRSWr3gBwPGbl9+jyIrRwV02tJplbU
9E/d47tdCOoK+T/NvA0v37gc/4b3+LduwP5Z9H+4CUDGUkGN9KhfTA/QOgIqN8Ctigj0iy8bOgvm
JYTmbrXtGt25qe6HqSt1kXh7Cbo238mT6BR58ozUrOeZ46a02f6xtD25Pu9ml+0iRivghATOpA5z
rnxQqhvbxslpKGJ9rUHDGxQp2ZLELULiBv6D0wuvsW93JVGsu5hPlZviS67pobR1SvTxJWwBDAbY
//EUdHG7Let/pI0ESEGQqWeb6uc8fRQ2BKmegF3m1z4FVKgInGbKh8RRjeDunq/68Mn+gczZuRX7
3ahe3nMmd6xc4HLp65RfuTCezfyxMeJDJYhi2nUGXG1MKT7VHNL/HJcqCtY+V9MrTL+EcaTITRs4
SjMR+yf9tnACT3BXjRa38tU3mT4vS6cS+slfhXnPQxMZtmbQOz+X/yQH9V8VD+eyv85YgwWJXBVi
Mu1afbKM3EhL8RP81AiEsaYr55pIrq1LnJVT/sXm7uwkKSFCU9rFrh8RWsC+vqjoS1/Ifb868X5K
G8TnsQztJGLvNKwMDTuUKfzqyDOr9eypbVpIwPPhnfNG7euhGWgepy0sewYlk5vrtnzjnxN/3lVf
/HKmLumkbKY+Wpx8zNjopgSWDdjPetXbxYP2/JECmAoqRf2a1vsJp5oW1HP+H8CqTF2JMAbxsSjv
3O70DhsNpxCYOusQuyIhQIr4TbXgW8Edzv46rGyy/TO9PtG42McD9w3oKSVzteL6/VJTpLcWCNG8
bn3q3YoiWS0xoonGA39g8tg+zyLdwQB9pIvxiI00+Xbjx7UEjjeKP55ctvlCQRtxSTOh9beVT2vL
8ch4veBepWf3nsI7hjczb8RFYlM4Vj60ueTnEuLzEu/0zTXFtvU4Fh9azPAQ2rMOLg7NEgB5qUcD
j1dVetnPx4ktf5avPozipbGidPo2Zek2YqAR0boQYvz3F23wOmkoZ7nmJNOWwfFE0fz5cjuDwTKW
URbkCkUksV40MnQwdgMFz4CfY65i2ZEmgjEquaVOrUTK+sepJqbScHreDnqfXGlEuES/3DroqJbA
RTpOqDjg7abzQeMuckX8B/jPvcQMpiVwhiRkD+TwPD333yDrsA/LBGd9J4KLDGwgFMQULkNvs2ek
rIuGE1Zk1JeFy8Nf5c9gqbzkj434rEeSNHpXfJ5m206iOrF69LatUq/9FvWCgSJdIq1sp4SsqIlG
3p0s2NQZUDVnVdatM2ygPI8wOhKJQBeqMpl3pOZ5s+l+G8fRTgRcK7h2xfzvZGETqxUJmznyECB8
Gt2eI465R3btdifaYJAt9nz+kb4EtcDZNZErP/OHjrAHsuvG2TW69u1zfgGV4PleDh1YAjHZ8H+G
1pZ4v96k0vECpRS9BP8tjAD9htPff0J9Qb7Ofs5BdreO9fLGdjOWnbV4PmBtDVLCRSFJYGmHO+Nl
ha/ALYGRPRN4nk6Ae03BNF6xBwKUwsg1Cb+egoRXCbih1rFgceYtHdmb6SfcoQGjXxJxbA6KwfTC
DXhBxb7ZVsA6O7IIY+mt5jmcYERNNEsVta1GO2lupdZuOFjszbO2UZB4BBcM11yjA109UCFQij+w
AJ9ulMLSHFV6GTBm2qCVC5IULIhlx0ztneMGcpv0w2sbNcC+T7PGZhJIw7AixqF6N7YmszGj939U
r0zQONxkXuPGdzRjFkZLH1mb3HCVX/tvHBZSWudG8i8a5CgBjSZxbiddL9/Sxcji61hDzFh9fgAF
jhUxkcOxQljBk5FfVeB7EvRV6UvZr9R26i6fwEqokpWv5YL+X/wCBNd97IqmL+c5cqcC7MYOt0Zy
S+j1uYdyyJcIgmCfOW5kvT5MTtL8TZk0hIqUbM64+1iIHr074PJgK6mBvn6Vwy17yBIEYrglQ3qd
S3maMbvsn/5EZE2J5CROtHepfgDloL9b+1+zzPBd1u6uRLnxlJqtb/fA3d86KV03HQJqjSkwEIkw
vraO0AMi6p5kJbWymUJr5rcgt5/45AQcsqkRQdV1x3gFz9CIXw4Tizl2qOPcfz74d4UPCFWEbi6R
Z6herKDW1LRwjQ2B/SxDdzcnerSII/c6tkEUFwqjoY1PP8dLIiTNak9wytR+AjSDia66vfxj3tD3
UXjWgN2qV6Qav90pyZDQyTd6AslXv/BxPDdCNCDtZj82DsxYWajN7SlmwWJCjBuPdnf2TngyhkXs
64OXKGdYDpSIgbS/YYeHyHBEQs+bKnysEtq6xVxdqF93YeZHZzkW7SOzGeQkp/aB0D4yePMzaeeC
SYtg3bW9JJ4Kg7sbsdFJGtI8iAB2Ab+2BbRn0D3NdWqG3X2Zy80QmJzWmHOiwy4U+Vp1Toxdvgrz
4+Ga1IQWBWS73cFL0OoCE5NGRCR0StD9/e1aOkxL+Emqr2+IleZA4hNRYiCaRiasLg2HM6YkUSFk
Oaflu++oPUDgIHJ7kiCGes25CXPT5KzwR1XHXwxUVjol0XUW46QHwG2I7Yg6rG89xq2JPdTwVawD
FHPtTbBZqMWbRXpDCmWGeFxG3KN2PNbGfNnCykSWu4D4Y/os4onZ5JQKtk1NrVpDuK/ziFG4oVD/
O1vuvZ8vrBUhbmz6v+R1nmvpV4wvbimfaaBHuRU3vgUwbUbrem4lP9zKtcQDwVzZCLg0Qh6Gof6L
XQsxyIitFxRwUBzM6L1TP+bUhfa8J+b8swp9ej1aGMXdhCyCKVFWnNi5FlMjAa7UK+FX7idt+LGH
1Y9PtwvN9so2nAkiACTxEZJsf2llUNWnlls9XJ3kyAkdzfw/u7bjK3zhONpyOdeFrBUk4xJ7Yrmz
iUS4Zfiqc9XyOx0Qlu/2RbOhToX7cBRJzDotcL4f3FGQMZaCRVzeO7xF9VgPzv8XaitpzzxRbhsb
RSYsaCNzt9/d/VknqqOKelZvko7YAaMa6qpbTo3J+VX+7zc11efgq8P1Ssr1z7qKKj+MAlpyDN2k
KdmoAZeom0uMnv7taTAOpbsHZXe+f0VSmZKHZ+UMSk+s25HlnGqKsPgp7yix1yWW8wfh4OMc80oU
/wS3lUXsSXMDBqgcYcamIeltj7aZKV0dkBj7OF/nYar3lrs+CXoXngoRkRwejT77ix1YUDtaVEMZ
FVKjqt4fW/p67TdOllDDP6Jp8RvJxfeoqHKaAQBUScd7tmITq2IwyzisI9R4B7jrizwrcU1p51jT
hPMyckL5sSlTCZb4R4K48r/IXOfFcbeWMa10hhUl0VOfjY44R7hSeyBORrCvR22ldu3CsPYx8u/i
Xsd1I3Z/+7RWy9ntHQO38hQ2nCGvTD9UiDqTqWZAzsh9MsDAG/Kkk9H3p0mfDxiQ5MR3EQsNW8/V
XIofw1i1OmcnAYVipKj08udURXkz8NCfA1KdtYBBC0hehgjyYdk0gj70d65VrX7vs1gNrTGXKtD2
m0ZrISwJUMZVKyGR6CMTZYZLanUwhYk3AxYJF2ltOxTTsT2OpsvJZqHZe3pYCXW+sS4qFfguVnYT
Uw7lU7CBEl9s7DWwDykIboubCwtukNwE0aM/nmvcqwetik/vvtB0oxYHisnnF7G1Yy9G8oRrx2kU
lQmPzFDFFOxX66hvjXfQJbvxWdxcshuqgoMPu+f+WC+Dpb2u4q7NxkspwN3ZGogv3VqIU9WCQsCu
/s6CeEUWMaChB/nRXSmygl38zNEybWRqOHxb0o2fpJSA1Qha0YO4IY/UMUuh6Mozy1c0qLKfuO9/
cAE+jQFGrWtRB4unLm9cla1N908cs9LfjEwrcsphDcNRCqzBhNPvgxjLKwMHORAdMrhx9OkBrmWS
nX8vydrl2An5aiFuQWIOh5pQIiTeAyf2OIfkQW0wMTPiZgpydyyWEZEeCkGzdAoTeThGJh2og0eb
vUNV71DIFsleQSaG1A2Nd0ES0hsxfBuGTy2N0tU35gejIcZ8tYdaORO1p/uRO6uO8Amm8O/UbHsg
We5CPZY9Qd26szaoE0FtPTPtb/lvcCYF2RfVfsBoEoo9AvdnPGzyT4ORfL/qOQMA6LWocM9rjuRJ
5Kg9uctjReC1uZocQ/lD36stwvEEEqt1uUZXnq7HSxmZmVmdoyAPaPPWzmmRNZ0wxtRz2UevU7bM
AMrXO8IMWrnvT4PmrOJ+B3En4g+zw1m9XWkjwvj6lHd8U1rTTucaT1HaauSHP6DyBZLYquVWOrTl
46MsVHndESTPFRyevfzJyE1dKCSiUDHnm+aczeTeoRVGs1BW6G/qFyF/O7bLbbd0g5A1/4MAEwRG
UdFIeLm1UMNr4Q7cbSR1/fpS/6dPX9Ji5yOdL2crLZs9Wu3JRhWTukDqVH4KvcNWgj1LqPQzJa15
d3utXQ3m75O1msx7d7ViinCrlCOLluDfLrcGXASk0Ugktcp3+/BiY7LSACRCrKmvD67QjKnXbl0o
qYEoSP5N777wvEgNHOqmkRwxg9PfwplmJUfqKPl0ARKXnZyyYygXRXSwTJAhFglrrLzAGu4ZmUfn
vrcRrOVP1ovZs89pPRCnm9yYhTOkRgkfGyUHty+NF6msX0jZ427e3FsYjX+IettkCsHeUkaGkFOI
g3A/iPnPlKvtIpi1aUl4jwuLjkXG18fJmka8AHKOek16bKKbDB7AS6ErGDvd3L6vyU4YiXNejJQr
HgLNfpvCoB4VP86BN0cPc5rOzclOyL03cmQF8P2zHVqUiOXIMe5gl4KxNObsMFEBIuVTqqy/dwP6
T67Dc4Ohf6PCMxeA6Gun0VeQ6Or0FNb2oH/9fJ1QkbeIEpljYDr1pSNZceQ5sGP7+3/7d3d9iufg
A/gwB5NM2xn5vmE60yMpuwXWOsvLN34kEZzoa+X5P6f3fZtWgf38j8VDAZZ/wbv5OLJcz9eTsKjl
W5EZTsfCPJtOIzZ2rwACihbnZ7d4n7VbZdC5FF9C/NPS891OalCAMVbrLJMj6QFAmPqCOVZ0zv5Y
r8MBq+OU3hMlYN1U7t7OONbpiqXf8F9JKLh62sI7WXnZnblDI3LaMIZMBaX0sKTMR2XzemafgguE
1KIHHHaNBoGHvsjdIzR+n2tlUS4EmmBR2VPxkgn6R3jsnvplnajN/pZ2Exd6FFwbtS3Y0e0nIeGi
R5LRSMixiVo+Ug17lFaCobIYHxvGII0nWWg/zeknbw3MwXaslGMTMJGTcPzCxAGo85md4ViND/CH
R1BhdL9bg93xASHhuHVpWQeW/Kj6tWQpa0rjTwvAP8gxZI55yji6JgSpq+pnNOmLi6AR1lvUudYX
8K61RULmV6x3IM61iHl4cMajPFsi7tgu6CodeycuJEzJybBfDTbo0mvY+6DAmNl8MrOSD/7iWZme
94B0dhwTpetvY9DP+BxIlBu/Z2Oux4Fm0MWBM3vd1WzK9b5dlbUf8/hsN3IAA9AyO+H4kNBJXPgT
OBywobp2kcyZMGpoEwcpQaNRHxUNcMYZG+G3lmCO2FD6Q7cPHHPb48Ch+6DVvFEVBjZ5Z7d6w6Cj
Gnu/PAIBJvH+ZuLHQQKdATCmL9nnBwUCnmRZWbq/6ysFyvyGiu/QGrlRk421kWn3PuYk6ObM+NCi
rALNYGAlE5li6YtzfNC0fwfja7NZ1kV2XOb5R559DHcgRN1lZ7qMz+/QUV4yK7WsybvTvFiLyeDm
7IY/kaA1ZY5ULuCqHdNXegDDGMxJUUO2HRDJJwMhCUf7oGs3ld31YLiW1caw31It+pZD7iq3MAKU
6ZQl7zc2AZvTlKXbsKzNd4487u7zNPOM/gkCRFiFKN0ghL603gH5NRnB0G84GL4c6jvJGxwOkhL6
hmSWaTcxbFcgXoJipK++J4DTfr3XV7My/dCH34O6vdt4KcpwZnoqS7duAjFGGnrQMbUEeKokSLnA
bg3KSvuRTHEdxt0MTMTl3L+eUFIBvLim978S90jRihJgsCs7dRAr2VIxisl2WRfojWPaGAQ/vT23
ye7gq69HPv7miPmn0BS0aopi0P9uC/8iBKW+Y9vnfL/0wcxHyJuaxZEcL1VCOLeELq8b+IRs1O6s
73B0oA5kJTCj4yQuY5+KIOYLj3MaEci37CGk6m7Ajg0cO2d8yEZ3PTGXWE7YHGtHADbTr4CyGPBO
V6o9Tup4xSvbPeBoiey8nF8yO6x3tPYwSlPr/97BBeq9gWcxLndPnOrAJAfCThVC96nIiV8dLURq
gyw+ie2ziyd9G2RPBw28UtNnzSEHKJrOTyQGfzWUpP/d3liJe+R+1c6i1ikBOb8TZNaoDORrigUm
UsbiXFFDmFehHP0aGnoV/TF2vVxrhtecPPKk9bhTSSaSEtkw0i4QTKDd2A3P3QAwzTuBfgeGLDvs
06qmYMqLX9No1SsmjMt4esPc9wtn7KqBDxvc73KL1tBaqmBDMQUIFp+Z8C6cydQVXYj8gFOWJKl3
kkL69Z/uvw+KER/NP5prJD6CPoIZSCeNsYhuRb6dQlA73MI2hOenP0OgyuzJD5qvAwHegoFzGYWh
DLWLyKp9GuYj32gAKNYiOasnNlZjh590X2f0Ze+a6YcYE9640cJS3apqIbdzFY2HyYjYNluJGoQZ
BumgOUzHy2iNX8jcZPB2cry+GBk2pg6iHAmX2n3NoPvC9NfrktK6OTg4fInZdLuXRrJ59xRJTpHs
UmU8VgsCKmTR1cBtdfomTzIaeZ7d6Mln3kNbz+EHTUG7A7G9CqXPaW6AXvPrv74OO0j38kclQgrE
Ykp8P7uoS/PEpPsLLyLCy2LLsN2/7oVxcMF35nK3kcK3ba+Me9Syv2j5HZk2ALLGGiQcZquqwDBE
uwlcy1ACmrwUnREVSNqudqOq2PgrkrwabEU8mwmqFrRATVm7l1DulOF8YRHpGkoaxXKk8HlkhONe
OrNLkbLn3g0QJO8NkVH7paYxleDkfm0TnsxPUaGqNG1EcZWBSsZj7Sris72fZlmRhoLq2VYfHm3B
bq/UeF2DKFPylw4aLN2QX01Y/XVRfx6tTdZPt3qk2S9RnMvGeRtg+1k9KV4uwCA6DjY5W9pt7kcK
dl7Nlzk/ZavDtxZ8qyGH0KJ9ZFtEv79MjksvGDd8jwK78/mDmtzBZdimQOFgijVe1+KejMTqnfss
5ExuWzUCR9zEX8qglhkNcZuevX2D1YN2Nh0wcguRbwhcGdM1+CcLN+/TqJfIx1eY2+63FFWqsuNF
7q2Uh89sVmodNsI0iJYoGU4JriGtT8w01NFmSbFu7L2I9SQsjhIDJQgSLSGtJHTPDHW3l0dhCsZ7
PFPnzh5TaatBK2d7KXTFlczxYZrCVrDS+wdiQTPPlHwjgkBfnqgSn2NwCDGAxiOFaeRyKmpR8DYi
ekLRhtTCbE5t6WcN1bnZ/VoqnhjcSqL/pnoArNeWuLB8Gwig0Ub7xkFoH9xok5TthhhWLtwYe6Cv
aXaBLDBAnF3R2aw1sHKsRBeHKtzrgSzxnowzeMyY59pDGfaSxg5pDYnRGOgnxWEAPrKt+I7fEkWz
EcY/yoZQ4pAJBmsO2CnoaCnKxz++fY6U2m8o5ki4n7Nuls3xSeqmFfEGgfcLZefqF5Jyrf2tbFnl
3cB2Ds/q9FGy3AacQjQ3s7vPvsK2opRaakYWKxWLZbUSHj7zAvW4rkwXPVCgLzzTnERAASdUZhHX
eHrYFAs9G8BTz7PRqflfaNzeccuAySuD2cNnqx1Pi+U5BvDHydrJOxH31IHtQXmZDfdC6A91ilsq
lVSuZmiw0sQTNUnWeDL1+GSAPpvca1MOKrulKnYecPK0v/MB0lDNHF5tQ0SkE1hLGUk05Nu1X6Tc
+9r4Sd+Yp2kmWL5kcizPvIPoO7b/RacnNnf78XVg8YDU2XvLdJEPnipcBDMcIxkS1q6MROH0YEqn
gth7DWIgVwAm47fSZNUah9iKRUbz/lnjno91Onq1zYDxclSX5jXmiAYq/YO7aq8UKR7FMP2Roz97
N4j1ngZa7z4cSY02p7xCtPKwtpfimY9ZUNznysJwH0E/K/57xMalwPX1Il1+8guHTNTMi5dOgegd
QQRBnLsladKFwRR858KDhiZf4sOl4BXAwSD1p41DZBbPOw9R5BoyWEGh2E6FB6dAEHjgzuN4bYfH
cJgu3Za/FdlO1a6bdg9UuimjeHt7B9OUv1g0A3gvbYUC0925Dqpzexzbh0cfW8lUVHASeeKbkVNE
/ON+s7foIGKM7dAXXLdfGxP14JbRUbmVhF28pDgXagmbM7z7ymvmQKOS/DCu8HCGzG7Il4WO+/2O
BaAXnDMb9nBt8sa6sQiKmr25m5RmJVDeSzLcr29dPDVFsv01n3aaI+RUHJFJRvUTV9WV7PelHTac
iLbaa1Y8uJvLpUDDpicQ5TmnLbmqaFrSUMZ4a5/sGyj9ZQHfu+v9TnEVVO17e9w9UgUfxtcsBax3
01iVQR8Y4hNXzeYZtkmpC3UBCP1YrluH2RayyGQUcR79qFYVTiLURRiY88fDYC2Cq3U8QHqciotP
VPmq17cYjHFt601p1z/Ne1eGqyHAmvByURSuWDrxSa0Dgwz/QAsz1DGdVT29UL7HHGmhj40bZBB4
9/QwZ5fBGGBouxM7vkyNwVButlgcrhh3+yPOmbuZPRsxvKNlbRTOBv5E2Zyedal593BqNhVC0ag0
BvG4BWDlt93YtIZ1SK5w0KOH1xJiazkinZ2XCJqk7tvjxtgxMeNHgdgxdXmmGhpgBHyeYMxzjrUo
ueG1psyhTDvpNZZvRlHgy9cNSxwXZMd2r4sG1P+MvXT7/q0DWTZaLXJ79p48OHb5X9JESZu4ytHQ
8Ukd67fjruRSRx9zp7UR61WnIOHQO+02IduIH7+o1NiNFDyrTAabfxE40YzHzD2yQgS41NqP3W6h
VPPNRNrLXEsDBsxvS+99yeVkbX1V40yT613G7MVmsytHCUKHA5VW373d4pfGNrl3xQtrXT8a5tZN
tpX7uXwn/P8uDyWsWOqVLoW6sA2Hi/JMQCotQB5chcR292nH+T0vQW8BwWr3wcp9epNhPgmkiOwu
feqyXaa3YGW7nEFNpCeIZan0PEGMwP/sP+lWmCgiuiiMLqgUhDV2hanGTIJILaJLrJp6otKaQyyI
V5eSgSqGQgnZhMtiIFwiProWLr1Xy8PJJ5JCJM0m00ox054VgvC+Q96Kca0eq2edqeovRH34VvDj
mx1Jjam3tu630kBBRRhgvzLN9LLkMv00x75xZjbjTijcdluu/QdDc7wM9yb0g92LcEQhMoYeLIyH
r1+jtBYcLed5i6TggHC9UN/tbuLrWGALnc9v5tRsYILhc5xN1jwpl1QIxdjIABnSE7YcilVSQXhv
uonvxDRtmoRSWN0HFnE4NRLDjOyfiAGTZG+0UKik7/m3/xMQrMyly1v36Kf4jajc5spfZdLKBGHL
cof8YSA/eB58sB4PUKs3dh97MqgUQmw11FiRCFb3P2j9LQN+SeFfB5U21Lw4zrqaNnGf0qRSsRo5
U4zs/w4H8kh+nRh0TBWCG9HjIgnS5SCHGki42hKtREUsGNP4hJUg/Uny4Zqum61qr2SCqY2kNCcQ
AhNsQ/tqMzoqFvqXmPC5YxQxzuRCI0xzLTGSyOgB8MxNrGlLgQG4MP2Pom1DAWSDneZLARIDjKG1
XSH22/x135uDikpSOsATfqLMuOLhMaMLiGbDlc6osRWNpoyXzvHjglolLIp6QKYRJ6Qf5f8raj/A
3w95gx6vbAddMeLDrkvAaORWblJxVaBUe8fR2JeMAsJTz3s3qMZqlv7dCCYv/nWKzblnxptvw69A
o+pxdGnUVWRD7KP5mPaAb1dxquKsurgojQeS1xqOkfXJcy2TnaUN6hQzXXzKsZzfBhP1DtnsjEIk
sK0WgNNeYtgurNqD2KQiJQfX+vR9RfqC3dkW0BYps3K2F4oNrRapkHXWkUnze8rga/3t11qsoA1X
wmpwHMTo+5zVprWpZ1Vw5uuF4Sr5n1YfZSTvUKQpYQQMqJkvKsSJyxVxeB2EAHWejCC95bR+gWiM
wpV/CtyWzrzW2rXXLyC9IpALoogM2Ab7lTO5eAQuf68JFl6hSnqoQJQ869VyUEVB3LbMtywzsWeI
Vs45XQM4tW6GDNM51ZvmhP9vppDo2hdkbNf6+kEpMAmZfBfnD3GpTH/wTPrUhhja6LP0yOtpQwhU
Uo80FLUwnwOzbUMaAIgRvXL3idNkkucVaNWdd7NwMWBP611CzKhbJjzQnSUItbVVm4NS/jB7Svdf
PfoQ9MB2B/1BU+kp0ySqNulbca7TVEJ/3JS5FrfJU9xHklrp3LREBUTGBFA9xs5koaLUHiEiTQ/g
jEVfM788lHIJ3WIqQH8Qbdd45BKgAVJQmG8B5uNgWQbF5UrHoEzbmJtSiiXVshqbPFn8Hmw9Ttoc
fX344YRsfEIOBNKmvEx7pyCxRprDQ4gu7qxW6VBuB8QuMLBRKBxPtLH9BGu7m50G2saFVGjXOkJd
vByHwAoQ3IGY26SwKEq0Rh5KK7VHGPIbuBzNSEczKpBf6xJMq9HHjQdrHgNysUCzpitGN3evayAp
tx5Pp/1FcE2lZP7zq88/GeTS6ipF0MytIalINT4D6ur9sNiIXtaNpZxeQBMkT+mw0ROC6kO/dpkR
9MWRCyk447fMT6HAq79JFVrxPodd9+xzI4IdUKmTVvdaKMBIjKC9L2olXwca605lgWGbWrhxaSgg
J8+1YG63DsTqp8U3twf62DCdHaotO96jfEZYXAakii63hYwn8emNe6HfzbUjferiK3+axz+onBPY
IJqTJ7i5PnUo4YuEfjLhYPP+GNdja9dXoT5Yi/O1xoiHOTeCWWNeK52KyawMx17A7r0hjlgT99yH
XL923wF+pE6gg36pRjSQxvAjWQma4wdZ3fRGIKmPpfxBLyNVfhro2nLtGYdxUra5MpMA3d7YGiph
pPPafjldLNcdmMwJxJIgYwZx2Z7Jwv8x4l6qRtjHHHYz9T25hW0Z7QwLevg9QLVZpU+Y20pmOF05
eZ4avh/5de+zJ0RKQbJTpBRTUk01qrBWwFXyg8cBsbMF0r/c7KHcg3S8QQwTUVTgIbhMufpFdQIF
LYVrhhi2jAkABmu2IozJJnunsCkfc4O8vj0HxRVaF8rernq0KGMQNKU6PJSWp7GXeMssGjcUCCB6
EitWCwGlOKep5TMNTVqh0yWl3Umy4Ksf3iGdyI8BhaHx+k6VUu37rVrGav8eDVfkFHsKLAVm7+lH
M0HM7ZQBbjgEBlqfDU0vSrcW9pubtcHu7JLIBB3NQfnPhkA9uDL6zT5oqlRiVjQ+Zj5cWkmXItiL
+xMNzpJMuzvXtw8YuUONZH11t76Y/06/b8YHwexsS/8NYUJ5zlPlCiXWKx2Lig09R3V8M6HSc2nl
37dQlOU3/blBE6TKazVDFPbg5nQzcHMgly8XFJUcGCaWe1e1EcWv8zbbjLH2eaOGV21fQZaww9ev
YQ2891IxS68kndawAqfJoI7xtxzrSl01pZb4UO0xsciuZthvNB/V1ZmMZSN1Fuww6dW4UyyRmgd/
uDUZSHky3P3QjcTz4k0Hzof10uuyHhANhgXgDEWV1n5E8qq2bc7Za10lP1fkQoTO05v71Z650TUZ
zp6EogwcMMu0+Ms0zdhspLmfiSdd85Go2GE1jhTT6LrzLmRYtzF8Am2Pv/gHhn+5FT7o8ky1mqgR
s6LjcStIJL4k29KRQTTs4d915jt1FXV2Zg5N+VTwAD5xMf/usDNzdUKQ2cRsZMWI9/GVlmgAXXO4
vbmmBOP8eOV9VAAaB0WIJKWTA5/I2uDrxVqzufqvBznSs4A1Ki3Vx0FwwPY50Vu+bzM8B8LuRqCx
zyu20s0Q+3vC3nz5n8D6kc3o1zlj57eLhcvxciCSdRC2SwaaBSs7LlSqqgTWN076CJg3QtTs2xZh
plcPf+di0PG8lDe/frI5aSO4FQ1AFcW/n9l+oZ9QzNp2CrOceZznHEhMg7f2zKhY2ED7mtgORGEE
DN0lO6IYh0+jPwdWoJfIQU4pCVdnRMrNB+Ev172iB2dSm8JegYYUJf2IjNdCgP5dz7llb/fAFY3w
znOstyzSN7bWJkSNXEWvcKbj/Q/9FSoDkPj3xRDgVX5lEOQJKdlaF74Jj1tJN6CsoULvk173YyMk
iWuNOnaga6mx2r92uTBLMXVm/S8iIYnBoQjhPFlq+QEqHie+8oUfMQbYl2p0AMMEx+u15fSQVMYu
kEZAsbA5X/e3rrHpMAM8+qQ5Bqlkq/67ntiYR0AFXh9wBmi/piyVfiTPUQx8qfAnTyjTD93gPN05
EWvTIiJuHQ9lH5uiyuDITXb0q7U6hsFyWNLBj5yuQeQ8JOjzUx9w3E5IwYRgBWLRnG4YuoSWlJMW
RLSm0z9p5jBgq7dT8/5IY1TmhPyoH7voyFTWU3Y6lPLb7k0W1hWX6APuebkihFk0Tbvpj/rikDoJ
3t1CyXt+V4qGtwXHtFJ/aLkbzIj4VZwO2L9fVEG0HUzfhG7ewJX0TLzZD4/i4jQ0DDtkhQ+ZorLA
Qn6u9Iwr9eIPRnvk6kBgbJUOJTDnBbgk7H04jwCi6WKZnj5EvSTqegx47ZALyFNdrd/ChXV8G7bp
8LEVcl0STYom7qiJQusK5Uh4nJV82AQU1/ZLN3AntALl/ZehfOcRvgZ63c4m2GYVefs7UUeQeX3c
aaqVpYbujb+7LQ57yij7q0jDwEDGYbRlhXlhakB/vg7i20TRAjDQw7YgXxSAEpIMM60ztgVCoGI7
czPFiwwI++keyuF2oECn9/dawhs6WqHwihn39mcTspP3QFYFWjRAwIInoykK/6eiB51ZJiFca2yQ
br13/x91FizneIVBQFAZ2EXmx4zkNLtJOzmwigsvZWgysE/f1dXz3JmO7VeMB+3/ZskXsIUG3orc
sILmsVxolTqR2y1On4mcbW0V0ZPqD3+pqX3lbAbtRVuoCs+iwi8h0ulzyhu/W67wrl3LlDu0V67c
4mbC9S31r5DZXSJvVtwZ3cujgz1aApJfNT3fRmtt77y+s+iYCcdKPFAlvXvxI93SkpLQl8EAMm9X
UUd26DeSBcgRhcZ2b9k7/yVb1ZbIoIdwtM1Ml799y/N9lAq0ynSlDv5i8iSjApedVmmZ6dxvrjIA
ccugKGomo0b+7Gha+ogdkaJbXC8i7QuQQ3GSdC6c2FN1Cvptbr+d26VQyXz/oe5J54D4DuEpbB6l
RLPp1zSFmqbZL8ceRi22MquXkRu3xoLEW2UzUojZ9en+k7drEssHiA5XuOCOi0CpNtm9/mlg8sqP
a76BeBZJRniUu2jDak9Z/ZJNWs5Tyq4Ql15v2JFvjX/q6NsnpGQ2mdbdaOvJ/BRmx/coAbQ+2feN
PgZYE/6fNzFNosozIN5YDu631iQ9lABMy5km0YsgI8kTSYDoIDfe5/OtQao4/FBQInJsASerr/MA
YBz90Zp//X1DoISwUhuqk57otYW3UVqLerp6IDi7Q14jVBBO17Ajrif/mxJLODk/wTIkFks2pusL
YqboSR+uVNbqxrUTrzMC/Xgg3v+9zTmv4IPVfBj23YhAjBFEW/2zahUEkAqaEDxc2jyIVVKqKSL0
TwfMjyEZy1xc4B6f4+em2mRzOag91/MzMgmZrMN5dHbsykaFPezc2KIg5p/dEM2X97b2DItxI9Oy
HHVT3kuho5h4N9/H+oVLWlWrgyOf5fjx8tznFfNBZzN6mdJVmezGlPxU2UjC6rWiv9OTQd3pDD3E
QOb7F4/Xi1Cc0xPuq3Tt/xjYURGtAyPS+pe4/9DrTK7ZPj4PrYwr1eRE3yVWVdrRJx7vNuFEe54W
jMI0YqOwv3kzgnG/JRRAuHWstgjH+p1Jq55qaDgpxEBXnhqqoYB64qaM3HrbPIfgx3F1OStp0mFQ
QdVRhykM/d5HPATqpT0Nf/ZneF7tDoB1ZkT7gAKz+VcKcJH4ZPjd0KYfdKFl8m0lzvcIlf6b5XSi
fVFyukIDYpo8Xl+T8NvEtt6h9OfCc/scKkEOg2msuzXHCuEn92PmM3vsTJrwU8+0VYBFScJ6dJdO
qkHzKdQKa967Z3tsGaChTLOBxQvbGzXP02kql2rYVi0g0NUhTHeOLMO6usPiYS9YdZo5oZWKdeeR
9f2EcnziZe3jXg2CxGpUwlyIWOceTkOr9IiiipRRpVosLhFrF6PyMqBQMrtaWHQIV0m7fMsp2dQg
yr7jTA4aYLTvsL1ek38mjaA/wY/4A4kQfyzledaqtZBr1ebLnQujvq4z5aJCH60uSK9qXANk8M8m
g20Z2tD+5eJByWwIDTpQQI5t/xSgBMFLL9HkWEwZ19NLPOR88zqJ2sbmd3g3BvGoKPIMS8jq5t1g
J19emSfov3wEr0fzEuk71EoD94RO6r4V0hbvm1PgUi6bDgnDdhZg9r58hD95MNajP9XP6Av9zAA7
293LO1kUyzxA9o7RO/nM3VD1Z/p4NJ8eflmg/Ssp0q0HWNvEYRE6SmAVBZa7RqKM4yVp8elnnslx
4s+M+yJhaalGUwotL9BvIJBu2s4en7xyyMppF9j5jcOgkEVyOTDo2JZpPcgWMXHsmiWtDZ2lCzR+
zXSE5Q3QLE2K6rAKzxkQ9I5JkAEsceppOzb8f87aHKpyitX8N6h2oSRkhOsuMcoVc/Dt/iVBQHVd
Um1pbPFRItdnVUoqIoQJL/R9v7cVDhtlP8ZFIAYH6Rc8J0eVgFR/TROTtSLt2k3vCw0Kh9Z/P1yt
8+7cleV4BU/vPIYTVXrfVyRpPFTpB5OHHt6y4NpZNtGWjdFe3QTXSoknr8ALQ0dDwb/4kem1JMkk
JdvVaUWCBtoW2oDNYSVqHxSCEeROMthgC2I+eUk8TOZO5oHE90wk5Yh5haE8Fu0cQsYYO3dNe8+O
vvqQN6ELqy3m7HbnB2qN/BlEVx3JPl4Het4AQOaWWOkFSjPdOxhGEdL1VwY52Qu0z4Rs6W3MwmP4
vzyiKf2U8E5k3RNF/1bdAA+FXF9h+ihQODkX9TQwTTcAzwtd6t+4ne7NL+D/a7i8t0HP2rQCaG0d
pavcMQcVYQCOQZ+u9c+lIhlxpr8qUamvi8LhqE60rghs0y2pBMmat1BrxikNQHcCCUnCAi6tTI7k
/44WpIc0lMEzJ9v3h30cMs1/AjBU7T87/AB36EbNMhkhV6L/MxxugByYCYMJq5toy5fqMDZOblpO
7QywO9uE9TwKHoFG7ju5WB3J1ltKySDUlwcBiaw5RMq+uzLl0fSHvF0jJKHde9sKa7nrYLbJ9sKN
h7BEIMWhrS4BtGfp5wfJItRjj7sIF4kzCDoYJA+n9H6IIwUQA7/ZvzQPwvTnHxN7l/9+l4gXH0xk
bSLQzkXI61tarolpMlGrzkp2MJWlGtbQj9SshgMuLjH62m+lf6B8x9248+0qhy4jRt5uHFha+hzZ
sCTFAlzxYWv1FUa85Ai6C2rqe5q6emcFU4BMiZI4q4FLGfXfQi0CXhKh7TJ7sVuyAgZmXwQHPthv
lAKVk1UeHV7GAxRKklI1PShCSCs7uMFMZC04+vhuRSPdyvKX+b++QcniV9goyEKVx29xIx3NrljA
D0mlKkJhPQljniLWXiW8VdZhmeaMDUE+P+6tybczeVYjZJIhemL0KfkDm/ssIms1GRPgwSWvfkAm
HddwDQB9Ml7LIO2X6fmbAOThce5ov3JpEakPqeD/eBlLnQA7nZ3UGBmx0EHtd5HBTbjRz7VK24/n
8fbLnq26AVDXwAM8NH4H3XbJd+WGTCLTSRcH9rEPJmXXAmfOcubEtDlmJIfxB00a2NsAIfI4NCr9
0s13zm7wdHHF6IJNrp8SDSgzuwMlk0uZ6FgKYYWtddTTTykrpnSbaWInS387zFFO0/HSv0478GKq
No412jDXun94dd6dQ7X26l8v9dO7musFBQqRMX/F+3ztBY1vPijcDKwWoGBR/L8qhgDMC606u3Q/
hopXJ7YlJa9oe/F2R9ufiBk6jHM7hmF0+y5dFtEP0qQC+IcKQdFssP1D2EFS/606pgcnGb98YIvO
9+SrSZ3Z+pm51QKrwEU4tFoFwoYvuohuLvAUTukUtOehIfvcZt9FR9DGr7oVMumLSln5biRMYAeL
4+EeEPtuNKXeag3RyaCsUY9jcA5fmYHAEshW78a5MCYCmJzixbkPjOxa7t0DVer6FIY+TQHmQ7d1
csUxJ0IjBduZwSplpAs/nYzL8MdGb6IZQ6HM5pNjOjBpTqrebVltgu/Vw3F1oAYegkaFfUfVsGU2
G82SMivNti+suDCX8wvBPJi80OshXzehtoDB5XorOBGOL/jY1tsEgWL+4olxaRr+RGTmadoWInCU
A/OEoMJf6Rtq+8KHFY8jJcqfczK5ylNZjwUUVh4HFz57bjOQVtodLaSS0bHEsh6OKfW7RcBWvjKl
gxpG852+iSLPOLHwvxklXtoyNYfrGKNZwKW3ot008lsxdhbQXCiWlviOJ/NGBVaMIUY7MN1h8n1t
zAW2hveAUM24xfA0vYR+9FyNRHrwlnjb5UDNKiPTGVLe6X6Irib6AgA38KimEGt0eOJbBCpPEAPj
yNNl8qYJIcwe1B80p5yfYtaaY0llBjOc/KukS+qxKbxenriI8d28gM9El9Du6/tuXD0cc/F2kK8K
mbQTOJfgaVf8uVoSlFWMrD2mQfPW44ADCzjuqdPr/pE3q8Ygj0n128ajUtiRTojjIqDHQTMaCdDV
2R3+wQOD2GxqvNXVSxvWosQ790Rzdr01M9dKw4WfetFZOlyDNk5arHeq4DoKZul2JQuUY2nScS3A
zlKFBX/DToM8IIZALJ58mb/1AZmhd9NNrUyoxWHgUvVgIks8mz6e7lqWqyGUdEQF034Wk7E16IId
TUMXWdjkkzUixp4HDx0g9Aw6m6/MHSyRz66WRz3MVz7CRpb/8E4v8/OJLauBQ005DLTYW+517aik
RAWYec34KqqbOjMSlCdYJwyy+KoY2yjEDrLpQ3kyKW7FhmHFm93Q6lWfkRnYg9WltT4NXpvHnbv+
z1roOeom80KNZ71BunQNGJz2Q2Hw4mCjdGaqkZUb5RgsY/W8OODX1RWf53fhLGuyI0y+XhkD01A7
UneTUxf6SrBXhcnjzGvv7i92I62M7Z7s96BdzRdGwVWnRBP1fq4czX7FguqTFwg1HLzy4r82rhsy
sPSbNTf3nacxU0hjAx9Bx3vLto3BEaycXtePY/lvNzvEuu/qhptMI/TD1gIgcZZObfhgsogmEZHM
9/bTRyMrMdf9w3GGtPCNVrU9mwbqy6egESCnY4OwQHNUB3Dr0La1KTfUX/4CvDVO2sCXu8/kUz+F
CD3qoHY+GWHSG8TaoZY7TWaFU6Vfyc7diVDKPxWp75/BbkKUZKv8kK/Y11TOUk9WcqmlOMFVv9aU
cAUaVi2B91DPS5J0J1C6lFiu46tELGCNufTaFDVKZOFvM/VRF1Bqb4k6/hPxWO0tn+Gr0s4Ro+oE
VJeadDXOkwjle70fpQdcOP4pDFlfzXKmTlSLIVGTnO2lsjGuodC3KltXa1LzTJX2RRjqYOkzjXRE
1SUZdVUPdELQBxEgxQcV3U5MQE648/1MMl86icYg7Ga3XQz/OYVKbJ5SYRHAenpmF4sV4zmrJySh
crXMsCZRAg8BDUc/hDkRZyfCvGca9kBoL0sRjK27vLawL4xy0x1TK9Aoo52iCJPksAMRlDpRB7jR
WhbGdk2197KYvqmvwkxaQOdodJ06ZIDm6CbqQbCXWOTC84YbSFrqlrEPxdEVbR+MyxXslFfRYVgb
LCNSAtAe2+J5jIqDpCOx9mWrokteXGR8k+jffgtX5OtEQc6145HAJ0GG5L110SmEmhwHjiUJXm88
e61VsTAUietNyPRO6wk0l7IjQSZbrlXgWb8h7jrnQBmV8zwk84WDjLzwkj1fJ0RSYwDRr9wQz8qo
IDURiFVKc9A96rWaF9BrMxk8nb2KXyNH2HfuE0rYD4EyyVsk8eBPsXkKVdxeoD3XuW++Nl+g8VwT
DCEiZ0x0kgr7Bs68ZIQ0seHcqZz6i0d1yQgfSuMWLnr3dh//cfiZtOP3rNreFZq500A6/nqw+LF5
q0RrDocS6sPWOmAOjtvc7iaMNUDyqfLJ0m50VzDVTvPvLPQIm0USYqVOw5RTu4DvLOxPZjkXCycv
aBQdDwpt3azimN1zWEgQyhygghlK8EnvU2gs6vZyQC7jqR3W9gigaf08ASxBxSXJMNdc/SGrQ9xu
yXswuwEiquAYvSpJAcPr/fLoqH6gDlFuQopHYLtR2EILncW6PAlJKPZntAtVmzJNXWiEwDuHhrew
8zabqy0QpHlvUULJ0LlWRINwGNJEDwFOk/Wq0wcKFMjYT4byEQUPWPXXXzszpFLwRj534oW2Usni
ijXp5kQEFDQL1HV+o68y2LjLwlphcH57QejTgk1z9yZIROrF+pOxKBSQf5L36u7JEymzHjPM1J5S
IviaYZaoQmorkHGOtJmzmVXAmkoUJ11lwLbkwaXKdnLCNC2W5r6fT6qUu3Vjy5/wrGz42mzttr9x
pR2MuwbbHPqUg8sQ8MYSLCJiJ2O1bKjrZy8/zg2aXDwMJCHh/N+X0KkSvD1dG+FmbJTk3fXcofqd
NCVW1n8+00ZUax+yEBnGzewIQbGspLwUudpbwwy1zcI80KbQc+yfTvyVTWMP3K3+uwne4uM3TqD5
/BHAYPLOQiVR4Sv1brXu4gWJ7gQOVUti9I/X6q7zHrsmu8TpotcNCAuZOzFXfxXV56juyhm72MTD
JO+j3Yh+TIVBENdnn5i3tnDkAisj8vp0+rU2CY49Zr9sZbMJgyCxkXCZOEj2pvNMMKQw+C3Pefnk
Z138y5f0cy6I6HGW3U+b5gg7i8kSo51FZ79Tb+Zz+qz0QUJ8kWt16uoRDMnsBO/fYB8rOkFPVuVW
hrNmi7Xg+bTRyVBHGHYxy9Lmi3nUdp3zs23TWldF4z2Rbf6j0Y81fI/vkguuooUGtKftKg3Gco1Y
20w/tZ9i6+Jn4gmzIDIOsrwbOPcwzfhRtEUoUPei9+g03zfnW96ywCxroI++EF5AmHHiXyHkXYWV
b3XM5u5gUVsWe5MV72nZfm08AEUhfqS3vEw5/je+bc3Q0h2Ub2h1nmVNBc1gydwm8jjwZAbl4LAG
FNmPjKyzKajFXMOMgSRUM8M9jIgz69fK6VZOaLdPmSyZ8xeYsvHy4BUREs3+10eY09NKi8qyZtkK
n0lnckVv41z6EVZZ3htnwdJD835Mibr3NKwnj1DsGEobP+IEWkWJPjdb5znyul2lPBssk8Fo4x/g
mhzoa05iyLvaV3kX55k9RH/D8GfSEjI3Exi+oVJdgsp6S3vWye4Gdd4MofUCHS8VGcI8KiW6P5Z9
1NTJuwt0+jMOCHkVa7i/aVWq2mhY8WDnelHXKc7gvt72imcLkvMOROUQab3uK70TrBbS44tPsomW
AAG2l+iZE5eemTdWEh8ncY5u1MwKD28YnlVGt5y7QyVYI1SyaRI5lkJdxH8SF9vyLmCLGBX7/Z9q
SoBtk7py06cZyUwQRVMA0LC9IGBjHnScfClGPOxnqtXrM6r03K7eNIAXHXeMvJ6CaRTKd/D+S/cw
fOfrDeNFG7oP3R5ihT2g6Y0fy1iN1XVGHLR1f9tlkXBT27I17WNz0GxygfjRpxf4ZDbl1OLNH+Ww
6G2UikDCEna6DRKf3yTqLHq7dqREIpeK/KUzYw+jp5HOpG4Nd1xw6DGTETCgw3w3f7t1+tjHWjP+
bKycPQAuBic+3mNRnAP7yZo7ocKiDe1JTlpKgOsjfhsTxLPm8uzlT1xP9GuWQeSQo2V6L5LRSWu7
PejwjWxVdmMNVUPOrK2Tnhp1Q84AnUeC3e9VFJIUgv3hWxtgoxw6KRbwo5wzTbzDosdlHTvkERHW
+BMykm3aPzcpPuhDgTELhqiF80ElDtwIHXHidUlvmaXQNsmsUO10ittPowwN6UAIuDI525gWm34m
elcdOC/kdfQCAw8GiKCiXq6pqIvlVRkNc68PwNf1MFKlDuIRM8RNh6152mrQCVRSdkEBf3q6iV8H
IPvJVJ9uW2243EPW/iSfU4Xo5gXqmn9XZLUe4o6Oj67s+kqJOYytP9ZKLV88NpUnXPS05mP1Ls0i
ma7WVhD6i3lf/dVTA3xbP1vK1fYGDAflKlMLH2ssxULIX1oav4saSKrTy3MmDqyQ6ol5EsSL1WaH
C7slsqEs55FL6Hgts9jvC1wGFfM8TIoXj7fPu5H5XLplRNmkD81UPl9d7RD9kT4cDTmN/E4n4Gol
ecoucUPB7eLWGApdVvDXVjkiqYqC3Npe50n/Tn44vKjPIaRxt2uKK0IDOPDVKYxuyPtmzOkWXt2l
9zsdZTjjSrnctnRJBRWo1qBGoMaKzz9f5cSEeFRoihHETBADCUmM5LYLY1Hyze9dSaP73CE5K6O3
zKJ3UkcKtqH/b4uKPO0riFtcBsbZwCHYI0oZ25Y5gfgFXVn+Spkz+6PRY8e7J7XPUWm36q4xALh8
olpXW6x6w5GUJsTlKwM4F+I7my9LEPyv4eg7aQ/9bvzDlr2P5NusKpIR/tySgYAVcBa+KyRPC2ig
8gzKeUy9IFm7O/uykHjKN66Jj+79v3xDguTdeSy/nOB5V6UzEmLr8jXU4M0wvewP810POaj2/GhY
FpPBG5Aj2jhGNXFaIHPatd6GvqAtoEGaCOFOryfY/+0sBLe8/xwgKDOlAhODkNJ+OssUbNAxe3mW
8U+Owv8TMf93qz5C+cD0G5fX15wKVf5opPepbSB4NOn1BCgU8IxVTIsOtu98ToJ3nStNM6L29Uhr
g21v31pPKKl6HX1VmHrHFSGMH7c6HQbfO3qj5YAzSKcPuiB5kSFStsoFCCi8YKSDBufT/aTIQBwI
oGta7jm5SD6RC+GMgmsx534gze1kyz6AxuIdnrLdsYLTosSZSZGPemv+xQZ+kMQ8dTdtSKMVoqcs
xUNC4GDpuaBIUurWTMpkoBJveuFUmC5rGMXNuQcA3Jxkme843A2p1M26MnCVyuz1O17hwyUyjAto
AMfmKy8dNqUvDwhlRoRXqWbETJA06s1MuwwaInN4C8gUOPGedkK709EdTC8GnFBYne7pJzwb1huf
j0wdfXNlduD6orcI5lI5/LvdyFlXjLm1Q4Q9DtpTYLSWldGAGNxlGvLJq4TmkhjqRqMLTUrPDeSJ
PDTwT3N500yz6vgjYV7BGUooHWggSZ/dqQcasuk53KTirSVUhw5/0eQTtlEHT7x7R5RVYKdVnRTj
/PUoBYKNg+AhkvnjvpO4vynBchOIUnLq7/glMmZEmyTklXdnwq8UATPTFQL0xdE5WwQPoxOqEGY9
Vl3n2P5HcfQYi/VqDkQo0YfPdaMWH6mG6GxXrHLNueoc/0J1100tGUrZFcMAZsIfPMjsC+Ha3Lvs
mwzhXAqn+muQ4YA57igfsJTS5iGpnNyzAn1QEq74bTMIOV1aJRl66yXl6to2E6MapvlaH6Q7dnxr
TgwzXhrDl3N+1xec+1gBnQSSAK9N6hfcnQqTdDkobNHVaVI4xCFfM/hE5RAz0ZVbm36W/rWAF2xW
tFhMDdCSF8oRycFq5TskkyvTNafPTFa+Y5xcykxqXl2hkVc1sBx80KTTWYvKfHUl040PaONKpWoh
OBJz5I/kyvFk32VJ89eU5EnTmbxl1KKKTOxF1DBevGJY4Dz2uORaPvow2QCx74Bo/JAEh6ODqSYk
y7ZQADZCxd7hTCU0wtC29pKPST0n0UwB4ggNshjT2XCaecbviiZMsWSPqVNSWjemSc+U8v2/uzdS
1AGNhhesAPhp0qAic0rq09u9sAzlPm+KiDFgy+LzQAm3WGQDyIwtQnHlBFEvg4uVaKUGFkZv52MM
It5vBrZx9B++Q1VcFkF8XZJ/KuasNfOvVCpzBtM3otiPaLB6Tt9x4dItviw2bVlcrKwBKxOBMrjC
VGpQJ75KL5UoZ5RpUTpuzREfYRWg8gH/PM5ZtYrE1xogObBAtOSK/l7rPJsmDAtkEaN6P5fiTfGY
4FU2dlvxA7kmsKmNyt7eREImY97hcQ/Vc56GBIRMBUcqHNmgMVgjBvGZWZByQEEgyIaUXsPDT3FF
37PS2vHO4SIkQC5t+ZoEeR5BQXs+tluMFI6zlp45k2u7lm+8B0+3aJbkCJQBLDUcCyFycrcFfpyp
ykeehgjeEd9YEKR6huaBJEl+Xffj13ApN6PWDSSNE9v3D2W50laf+JzO3rCFnddya3COaY41wfDS
VbxBlog0kvqWpPsVFBsv6KPx6qagzi78E/szWpPQbJ2O3Ho+Z8F4g7Cq6PNxTJVJ21NTgB3mw/fD
XXwLh2jU+bdTfhdgkhGd53kKuIOYDgQTSv/By31GdPD+LVaSU30C4DHIFiOWwScUZTyEOyHQIPY/
I5CVipS6SMr2qXvlzB3VmUqzzh1OZrmG+Q9BQ4SzI7O0Gd72X5aFxbJ0cSG3T8cU+eEGqH+9sCXh
W+J+FtxT4peKUjz3ZTGEZSLDEjqBuNqNjQPXx4lyBfN+Y92fQKopZbzbB8u+Gy369/Ac2B1t5K59
OtU+4xF4Bqvp/4OJcZqVu0AuW0OVgDVS9FOhHEr+kWjKR0qfhTT+VGOXAUvRjijBexbifMf99+iF
a7hn/JNKZH+hzQH+xOWKFr+j7jWHP2LwLKv2YlQEV3cBzWbb6lIczu9SPYu1PdD8zfLpvilupgAJ
k5coMqmik5VzbrZCjKmR+PvGNscvzw0MaFXAvtXvC3BS7OcWHcQ075W0VPVOnB0wJEF/quxgC8BY
ttPjp4UNmeAizy43pksjNDGcYefNRHA0pPoKYDycPkrbv5vp4L4a23IS/K7zaQBl4sgA/cgFwKd8
TGStDr+zTOfB2b8/LRWyjWrIZz0Em4nKHxL2TqDj+ZZHA+V2Qg8E19mYNxyScuHKgvb3WTZr48Xd
fmUjhibrWpn1seHa7oRO6sTgqp5mNpOp4acSlKZeef64CQH9U90IAK7/n3zpj8ZB2z7uTn0tks4W
Qsw6o8aIbJDotF4ABsBkErJzeUHF0nDJKHiBIbTn5hDawISZWf4nXQ6N2/r1IQJiJH/RWRwe+EZu
OOerrvVCGXNy6lHvZuT0RtKHQVQZbmwvbWU7zQI8Nd1CYeQc+cvnL5D+d0gTnd0E9JCfyz0ASNE4
XOJWnSLH3Mo/MY2qhxG7nYUDAefoF+UWg+V9SiY2zSjsZhPGmVoh4aUowcoyl9mL9phiMK55Qfs+
UxmdKYb1HmKI6dQ/6iEF12Jm1dGrbs5d+5Fg2j2V8MG/tuB30bmWLKjX2zgfI75EeFxMBkeRuIJ4
wo0ICJ63taX2w9QejEnKntp1nwU8knwFI+VBhGBT3AOrt/mOvEKiyWqXG0UZ6oCSUqtXeaYj0V1M
mhjZddnlYC/oBZMETLAHBKUxg02OQfXncf1gUm5ai/27cWOrh55Q6+N3xC4AMxL7GHkzv9pcXbIr
aLyZjebgSnqIUNWclXr/EHIBVk9c3bXJAQiIEuDi/vdrXQvXGI0n1A6O1lkcNUo6DWch63nPMeIX
nLCXmGyBHV/B3cfevwvGOdTvQ3vI3hncVdF+4yEfx2mAm4FiSjEye/Y2LLomdejJcASdJhzVQQZR
1rZme46R2TEjxH/i6plJxY5DnzGdhftBGomG9CaIXZptIzRoxxQaWIr3DT8l3KW7tdRkeoqFRNsv
sHV8fE0GsIxFiG3ha2UmT8dhpyUgyCNEoqKsPnU6AxpOoMZnfr0cVMG89R4iKKSfqLfcqMUZMqqr
w1GBbSB4G8sGxvvNs0zQW3jrNZE9s6zxLbhtpuaGaOP8yrSPwpl9jqx9R6CyMVYlrJw5LTnpZWzW
h4/ofiyHMP5aaBJdI6GdqTRFpSSyOCb/TdvkzQaTAs0cuWGz4EbbMPVGjz1aAkfeGJbfcbo2klH2
7Bq4+jb5IJg7/5ELP/IK7ZaIUSiaqBlrKYmjsCSPEes49YuVVxnQleWDQd9Bn4PH6YnfA9wllNGA
tiH7XThw6EHFBseYNM1Pp2W55v2ZRvxZpTSa+hmt+Ver+iISBi5VnP88ILwjihzi82tifLAM6ZNT
iwOoxSVjQ23JE0OIQPkGFVQVRpFG6pqIgmtrB6fBaZpDKNWO/cH/GdDDNZucA9gYVdt/agDkhamg
saNzn6awUxsHynziCProTaS8cy+iGfE2dpJwQlFPxk3PMPsqxr3VUp0gOR2FP9Vg7CS/4tJ+t/6U
t16Lg14cS2DfF0/AWOQi/q2wEtEWI91OBb3AFzcasYzERSkZ/cwGsRyIZRbY9/VZaQcFXKP/KV/i
tZhBxuHjgh4iYM+biYmhO4Rh6YfQ5TBNhutcykOM6ksjV6V9MQ+VozoXA5GAYeNm5XfTdLgVx8pz
y2pc63K+tTqU6dWM0WIgxNdLqi5lek8iI9QGnSzx/wKEFB7JTtfD3xUOVXMLb9F3aLJ7p4SK+xtD
7wQokYTiR/MWbOA31R7d8q0IW9nn+hiJFo6Hm+dr1X9GhfIdHDl8uYoYesOZ/qgzRoUx6/rYtkAW
eN5Sa1ZtolCeJ3iQWMSGEdX5DrCjcrZ6WfOyax5XkJ/W5zdOI5EQnFINCDBALDF3nK/GB1tAfy71
jaZOnXhJZaV5F8fBiY/2dlQqaV4ZbUVm+/e5JACw/3rjegwLSoH/C6RXOb5vr1Q1F2DFfP6WhIkJ
gh5DrulNPKef0N5Suzr4qzzz9IqK3Op/SBqbp4MrG8ViSmeeiouhcryrPe11pvqybPqJydf7JFiX
GuwwwuhSAqlS7xAK0qWF9rHN2pOFpAtpiNgBU12oBy7KFml0kWsxUIH3z7HzOV+f4tcE4v5j6eB9
bbjXKT+IRDL0mzpxDNZ6Kjt7fwM5Skx61lQ/ICdvwsmdX1AAY8wLRJRYud0/dOTnRQYs54/qfQlE
cl6BkViRy9X/mHavEdAvgYhbyVyffgIIgpeUMR5RYZh8vk6J625Erl5r2/ytmAmxQKlJgCRiOi02
szZqX+WIsOQD1sSBjJ1Zwgh0p5hIWwei1p+xYaNiTR2t+wTo1jrmaKereOYMwlKsHbJQeODwl6W8
Qs6nefX6H/BaDuB89SR6AG487eissF5BJpPeb/CcKs5hEkFfAem/KVjZXJaB8Z4pne0ybhJdtq2W
Oadh4KZLBoLBQ1hzJXbzUTDc2+2gbfZxMnjZ2+AV3h9bKe+UxYbQgjgIWqKJ76Hz7fH/awztkzSW
gLcwW0d0/3f61tel75iEOWfhk2E3HEIsGGLwdJ9vltM1QSdK43WUJ3cRFJI3iWYC0qrcY94DISe9
LX3KQaVtY1Rids2ussfIijU5pKz0g3sd+A4CWovYZmDjg0q2H6gUD4+nDK7NquVomKEZogQOzz52
xhnuBkwb0xhW+Eq1aXh2FuNZm8X+7dG4vcX2nGP6izeIXI9x7ZjgcEs+3RdwgVRUEZez61PlE0Bq
r95N0Wl7Qa+wLatD1WjF2cf0ZsE+R2bZYT8U10fIK+2J9/92mPn8/RhTb6k68kIzNf7SBmgPtiwd
jsJLDV2m0uEhQDKj0QIy0RlQh5DmNUF76KwBgNjFvfVSQYYtOvchS/6+yO6VAJeiIpon5L2Su8vE
XRvuScl8bcmjBvvMDntqEsnYQGaP6al8kELv/P8BoZPC5g6iiZqjI3grmqXCXDGwYwcj3qODy3od
ExVoH0KzRMKSMGEJugTRNRqvQNwVIDj1tRpvj48BsUtS3UJyHyTwZf4Cn3QJiJwJY0PiX6DIYVWd
rVrlEE7FPqSkmJeugC7JApOFl3F7MbBj/qM05ufgq8A9PeZ1SlVDi11jtSPZf0LKBrobd9+LFik3
EvYBLKE/6w3C8yd1kFjax1Qie4SmVCUOpijWEgp3SDkjK2XfBLtP4fcOIX9U1M4omHnisCP7wgeI
Mp33v7rzzFO/ZR6KivGxDZmRRZhTcsF8Gx7vvxir+Cqet1RojQkqlXc5MtRYoRLJxWLTzahPa5Mh
EO2Fw+wI/3axpht82/vkgW+6Lv4tJkmlT+pBE5z2IAtmCXDWW9AT3XEoZAooMEoCojVnTAxEz9ON
mca0Q1o7JCsWBoH7fWaeckugFiySmMjIdbX5tzDa5dlYJ6w/78u2rnO7HdItI8Lu+kJmGaDl6xwC
IbkiavOjYSowrJjNG7dCk9F9Jr9Tf3W90Eg8g6fn0mdWHFNIzWKP1gE9M0p75pnxFdRBVa3GfCdB
sUNK4bVBfEgznSQmqzGk26Q1n0Z0hiHrGuF8hgHD8k4lmvjLiqqN3yd1tOqbtMLy8we+kmZCcIV4
3Ql5VhunhF2c7kTgKx3dDT+ZOdFk8RfuHi0e+OjwkNJAM31STVPSe3atrkZk6kHpWIb72t+M1gvp
oMkZNsP4tgG00Pq2fCvKEiD1/kRrC29T/2tCB74tchP3deQuJ3uNT9tuiZBa0MLFoJ24+mMNeDUH
075R+ms21HKZTPcNi6knCgNfJhoL7DA3ymr8hUH24WZanrK59M390E9KyB7DUCfqOgYHJkx7UqOO
1CWIuGI3syzOpalSUAz0ME2ks+qrh5DXvjeW9+DDpQ+x2w8Tfcrk3fPs/UUrKIrY87MpZ2Upsfnu
GmONoODlUzgtfnVbJkqT/QG968YatZJXvMYPCd0QhQAxXdoROjrzAovevx/sMBJJ0b+mc5xk7F+F
GF3Q4/mMv2YGOUXw6A8dbwzr7NSwBVUBMVdvS+9TiZlz1w/wyHbGcNcwHqjwE70oQzSTxMPnHZIW
odwDLgUBpVJrngFDLbpt27R7DbbsFNAzj+HbW6oJBh6PXPvWhrakjwJgjcHNweVIGKR4dJRiGsKr
+uLTcdEW1syl7FEHu82bWDQL8v0pQGvqwwSQK4/wcC1bXM9N+DviAR72IS+nsDRMO0bwo3EI4YhD
djtGdLuQfhe1BnZ4tvhPRuNjMtPzy5oYKcbiYjYG8685RoD31FbOPSVhBkRgthzMnK4Pn1rge+Zy
wQhv9yboc+8hB05xmwM6RR/upfqrgO9BokC7QzDZy71kTM2xhgbRrn6X8pvx+IA5hKUW3VwLJtZe
QR/d4oqvRwUQ4WyLQT/ucKeyv0pLubhA2KIxSkxLoVeq/c4NWg2/Vz5i45n+BgG8Q/q0uKxeDaRm
zECbH7kUOjLphjftD5LH9K7xTWGiaJ51kjm+IbEjVBFHbaFppLjSZnC8Bw/GxmBTYirrBpikFYfJ
ATck+nhAcCozV6n7jtjX2uYV4UyW9DN7QWoiubhr9h8FkdTp20Zq3z1+B0oiaXo4Hy2FaI/Ne/Rf
m6TtWkAiPQOCc5UHgUlNo44ycclLgSOuF1vcyPH4EeP6CWqY3SZ3jBMBXsbRM4GmzlHWAhX6IiUZ
k+oFt1qenGb2SidJfju+En0OarXcYJ8qMaXszpT8Rk8LYBAkkCFyoIBhemxH9Zw+uP543v9dr1B5
q+sADAIroSmYz1oBAFufmobLw50igl7fYQRGtuXMMoZg7LFCLqSJ3E66x1yaZR2sD0DqOnDw3bf8
Qr1ubgQ6DFUQQTTpeG7jk9/OiK4riYnZ63rgICTy8DXuFusv9ODgLdZcDZ7YtUV//7T4QKwq344I
CVumOmxJNiQJUaxw0M8gPhXtnOPX6uUfEe8LxaEKY5TtocmP/Opmm/diJhJ8WBBAG0uc+VLcaoMc
meT5gd7b20mUCh/JFyyHnzu5QiZE/oG7kMI4VQmLJvViDin51xVApJ3iw+k+GfNTSl2cI3NoyMJ/
iXV8qEn59wt7ASgwdEor+5SWlr2skkX2lmZfsM5ZSZagycjoJplHavLRIdzn+Zg/6ogUgpPv41W2
ON3DV1a/rbSTzK3e4VUhPUImfxGTb1emTUSz32FYjcNSstuDR3/JaDJ+oIGckueibtmqilksWbhE
ScPhjLtx0mYQs/cIj9lcmbWq/xIIsnGpYtAM3Gzt1K6BAQEKP/8pa2gnYMLO7bZaXSjRmyyMbYTI
zxaOWgn4jE/EERh+E2R9QvuXLE9OnSSkvQA9Q+XLhQNND0yyYncl2cNLmIzk6pkVhhRg1jYfiNQP
FDSAkjmgsu4jLZV3F6zzSGAzok5aGmUmSv8t/B/UKJB/nCnYI6i4XnxbT/Xoanzw5PfZkV18JP6B
DAv+1ceIqenyxCahpPWP2Fu5Vk5e5gHxT2q4BtiZd9H4F2R/GWGsCr6oU5kwmd2H+yn0OR67GKdv
J3iZhQgHWuDLFKy+JJNqzmT9XQ/iyUewHJ5JaiSY/PWirLM+/5Kcu7h/tqzFhJ4yx/7g7NwsC1xl
RgV55wOtyTOny5xisbGwl7p0eWw7W5hnzRsxBuufxHzKsTQ31cAYPb1ZYRJBKC4RMM6zp25CFWZb
XMkC3AEVY5T70nVi9dQPaomhLQrClKEO7XnDQDaNS0WtQDRquHmX/Td44Tg+gMOXk9ybbQ3NelYW
t6egyTqElb6Sz01Epne+X8yTpV7zjFWAQvFYSlzUMOPnZG/+PLaU4H9pWUtLcTmfbaqsDIMoIi/J
Qk1NBBWcsN07vsE6FVscTXYSB5Cu5UpfctEha5Xxb6XFJbPLGK8JN9wQPAn16l+JHE0BSh2g9JvJ
nCQLN0ele2MN56ZOm4sQmZsN2h3o1I92RVucJWykFg8jsMTC6rq0jMoZUwNy1mCpuuyMUFGR9may
Iecme/JeNbdKH8dRzMDla62YX+Ikbk2quxsi3ZcbuEnfHCBTpPX3DARr22xvTaP2iP6dbuiRKMEV
KluY7A83za+sOia3r1asb7eqjrvNAZmxuzsENL0qOX82/XvxZBqraIdMNpUv4LGSvAKQxFM/2CYW
8nq7h+URVEEs31YXBIDgSOjSbcJmDwhTutTGx7H/PCQcU/6unpLKTGzcW1QdFwdulZsYHe14o+SS
D3DGbRYqnaCC9GatgnZlBdQq6XRMc7VEH0MFjg+bzesgBKTgkpq3b/1PuJEWelY+yH1zA23NrNPT
cYyPUFLOjTBYk8DeEUo7KLgibl2+UaMjzpKBPF+3TGhZxj0cCQu1xQKxO2oEhcFb9f8SLARvRwhF
8ivZDJU0QVTfwMSqyxqcDFHknlGWIcdq4FpV4sDK0BB4Hz6BRS09sS5+nkCfOYa/eDGHGK0Uk51l
050YKA9/RcPO+0ttn+oqj5qC+aqel8wSGiOGMeK2XZwQ8xb0b149P36HA0r4rgrtdPGxvi+Oju2J
YJmsLBbE5EKDWjxlE6UWCRxBPGO1mNWrj1A+Fa7i34ESkLgv0J5eC+v11+RC4uTVvtlk0VdNhTaV
RbZdU7avvmugdt1hV8NPGDsHEuOBwHVNeYMlSef49aEKu8PTCbthXZEY1Vb6d18EcifRomGMUkI8
ENjiHlKKhA7D3Hr0J2IKuEnQAF9Rc1uCuQhEd5K9DfJADRrxBQRdFmweeml231/qtmsxZktSYU3F
22IcMyDZv6Nvk6iLum9Q/qrzW6snPrO6sMUelH6xt/7riN4NUGSGuVkIB2MK9tLzR46ikf/Nl6ol
y0DFfpMWs58IfMI2ysDHW952lMhyjC9uu/AvwCm6aKLqaE9aTW7xvqyLCPJuYqR1PPrBL28Rlxiw
xTwJb2kfwSyMdbRZRPJzHhUTDCdBXTepdv0JBWSisK0QEILvT6i/2PFFi4F+lDxQL+BJjjCn/t1w
xhlllCAnAGf/dEgkMF0zoZBz/9+C05mNaXpFL4ai4+wUUWffxPYcRMgPmcCXJIgMqXU87s+zW5sL
qVf+378nyYzWu69Z225z75gbuoPoEQYpqT4uVlu3+/3iTHBTA1VKlGEHtvizmNxSX5d/3rbxgKYk
36RwQFFTjRWbtdYu3Y9X7Jv29PHRaya3wLQjNaoEYJR7pzZ8XyGWrvEYqDT1yHxFUMXD8iZUYnKg
o7zAlldZCKz6z23LfMxQubfarjFB1QHpRXRZjfpaZ7YYzM9lzeuMprToOelXgwdPhgMDbrPXsXwf
ijo9bIinvyHupUjDcnVYaDeBFypFqQ7cOfAS+gbK2yuM9wYIps4PSkfSToIv7uegcA1/mIRl1pkD
B0tK87aQie0dGWIFHfDBXKSIv+6XF4Ybzf7GvxwLl9J366lR53/ZS3GocQ39K3zSYBG0gocdRCrG
n/Ql8VXdS4LxFz99N6G8ZItPf4G+gbWOyyO1wIVDvFOo1R0i/iiXtni59PdXbDO6qray2XDowKwI
qyo8ep8MbohhhfPYCin/JjHfAe3Ar2lGOU93VH2UV0k0E+w6h+yHPLZP8Gq/EelIMP1JbQTFX3bn
2ZP1I1l2de5FLatxcDsRoe2fFDot6AZk8vCpjpj7zF+GX/R2ptYVAXuauRznhLvjOuueaQDX03to
mzsGt8AI/yI8H93CjvitZi3TXUyORIWd5KRP0stXzCIR4e0mhPbCwgG28paGNQgMFY0U1i9NNkoU
lAhfdc3c/3Aw/UG3Zfv+r+vcMD5yd4pg0zGVNs3dvOyLUqubiBSUyCe0/0ujUvAkDFlDC3RsK2kD
ObH1fruvLUbjrHTPp5XKTTRzKSXLls4EdVsggNSLh+tPlKSn3uvR1IdeZyr9++aAXnf5Jj5Rhwqv
fZnwcyc55x39QGb04dUFonTTqVkd9ZcE4obuZ15F/EBBSyPuBCyIFGXL/qRawrbbHyeonQrjgv+H
g4cuwYK6NL5RTYrJIYE5PuulndfDnBsyt6PNJQnu4On1YuqczBg/BM7scwI3ENXytWaDcuxiztXQ
ikgXKBwUPvHdLhSxnW3zDaySwl1tqGyBYtLjXFaGICuEO5mgOxL3XPTdqnRyGIDlSeIwol0THDmC
vHsfcQyTY0s44t64GlK1ERtnBxswL1yflE6CpyRZNWebRMFULi3F9BIgqR+nikfk02q6ahbIKxVU
1PLyNHdx33S+RZFwSuljnyg09ik95kcnsKc9ET6iEyehRyA979bt/8OzWQRamZKSdZ2zXOoyjfs6
1bij1DqXJnvmAfzyN8Saz3rcEoqQOS02kUr7Z41nFVvA2jpskNmDfFm/hCZhY6X4fMHa5FMxg43X
wLsyPvIUn/OfPZugxcPwvvxZaB8XTY2n80jHqQYsWq63ARrMyLZlAgAgnsWfngLVOK/01D6avNG8
VQi4MtWIl8ey4KavG/A9AcPWv+jB7kuxf8z5XsBS/cXMyoBPQ1rBDEdms6+dIlUpB5CQpsUzdQDU
h8Hx4Igl3PAhA77ORm4GnRilDl/eobsP9HDBzZP2rWu/q8sPg/hAL5xiwB2j08xj5aQw/vHVe2m7
DrPIehijRFzCJJtnbanSq5QybkvcBrY9+/n8eaVqbrppqu60lIVy845uNsDWJF72x2SmKWUbA6xk
VoVA4lec4QIVPTUDxFmJc+xNgVZwe9WsgibeFkYzdvMwOuADAbkRaQFqe1Oy+lswJg9naTN2DsFy
flwZa1xnspkAcPEiu1e9xtfZnNNYTNbdHZunEWZ2BeitdBu7+VY04ZP1YJe+Xq2kW8p0L1rrvWXw
NA5SdhYHd17RxtnZosRIKiE6HgCFMfUB/SA2sPwWUJbMk92BzGNH+IFIVnvgQn6dbTHqUPZRbYBt
q1JKwCrS9bqsa+SH2QylwmEIbqt284n57/jKLp0h+JznNEmFYRCQuDYW3IUlrhpykyVFKz01j4Hp
B1AuWUsMaNdAKa6Yw6FdEYDpLBch1iX3Mq8ySUxKP74VA6FmVSn+fVDchj0gFRwTde8WEnqM19uu
IK7wIOIE92Vmra2LSB1qqOA8ksRnLxeMwcTBLDVHWkxxTpoWIrgLVsbrfrCAupxvVj6PXrwnIW7Z
7f4o9zLBg/G9pS6S5lO3R3vihcN5+We1aRibllKoVBiapUqDMwkL9axTlVyWurzxMny8PRbnseAF
Bg6ShaCgzDsze+DE5oLR1AztkamjkgL/yY/vkC2ysIcuVxFRdppjSCG6sV5DZZb1AGHI+kjuCbrQ
S2BjOMkhhoJJT+HYu1l4LGn92Qd8GsB1R1RizgG/88bEirxNUO2DO9i06PEzyfXAwn/ac3JV6VkL
raLlKdMZZF8+uTttRIAOryvZDI/fUGEhxNJ65jkEArCVjQtc4x6l2qcRqgkU5VBdaS8Ezibmymqk
D6VooR1cuhrumQn2I6F906Oeo76oI/y+EwFWxyl+s4757E09T1SyGeZdZWzzZv7udFtYHJ+Aaa2R
XS/oF2qWshogA23MEZJTwO/jIOpZ3UE0Cq3H9Sr9AllPryYj3WP+lO7zA2An6H0shEUUDYCFXVJp
+OTJD2EAfFDfw/99gAFwZoodWlrQjlp0W82ANtTYCil3Z8ZZVUhu1Kx/ggd1v4U7EEMdI9spBSCG
OLULBNJ1C7iv7iYc4m5WrWmiHqp0ahsE61v3yektnkdf1L5G6FPUBfAsjbXqpJJ7PJmH6Ew0Q6qd
dm0RjHT2zZZBHZu+EsPMISOCuvPvvfC0F1i6xdrTEg0NQYCBQurYca3owoI4YhWeP3EhfQRaIyIv
S3A8RkOi4nJjnp6mbRM/5B9GMu7OsYGyQbApxIKKtw75npexnZz7T3L68rTi+Qtcz+T3qAg43PBv
8sIb7Sgqb2wzfnoKwyN66arnrmCm6hKyt0/u47TkwicjrpZdlGgagj2PcHDp14WvvgWc+e05h+SB
uCTXBacaBknT4apwyuHKB+PdVrm2giyFshRJdm/aQay193JVU8Q2EgHMHv2WDwCwY7DP0+c4yHWC
XzB/JLCwKC385y0wu03n5eFiSMzozg5LpDjydTcOTlDhpEjRNP5FPtj62awYn9kc+uYnsMrg39zY
QlX/aBQ2NImRdaA3/Nn/fuuSKeRXRckyG5o+5CXz2xvV983mZvvWnGHpdYzCmQfJQldpYOwQKGUx
7Q9xj69ITJU3htH6lJle/X3Uqo9lI++lkHfnW+mLnBzTXbVUiI7SXUJecvJHQttsa9BUeS1RLAvA
85YFYlAQoD0r7hf9A/qOCWxLDGz7Z7bfLsnhv7Ekg9XEAYI249/M5IobgaCI2udAEp66/v/wWPt6
7U+XOJXUbqPkX1HcvrK+tzzr61LhsARoBds2buqlEaCZh9sZlNUI3StaXu1B1FJOlUHm2V3tYKCk
pUIPKFJwT4YSAJV6cKAg390bqKLl9V/ww6li3K5k0Nmfgy5WkBkaB82EO81UEgYO/2STjDRL5Zom
QxQ/4twZ03tZG+9EH8fsW4TJhUuNGSotsIsfruM1M86LmmzT0blBrXT0F45+9rdW7ujNIegOGdxX
rhiMHDx9wAdU/xpP3KHSG6zAb8zbthvgmQ1fjH34A79pIr0yktgNan39UrYTj87PU6Ixk+YGssBi
C2sntbSW5Y2HtNW8ICHvRwDM1iYJrM39R9AmpfoxIAKaHfq28vj1ylu9z/yw0xgv53Jf83CmXeNt
cToNLmhTQjT1HOwSeOXLMWaWG/IlBRkibTlL3X4ze642Ndf9H5ji1zvXmiPEytWquLRVxkwp2rNj
aITb7cLMnwikJpOMIW2WYLHybCte2uV2ZO9nuFy8x5TqMRVpoujW8ZVenarbSghLHzSi5HvWIg+4
XE/kazX8ISvYyJuPMH5fBsgDlTZxgFigBtz9Vdm6Cv/m9xSQT8CZVS13YYZgYf69K6domSwYxqU8
f/O5Nj5ft5pIfhp4S9XcW+uEyB0pPkbeGnMdx0zUbCcI9PwGhvrIIANhpTsSY6uY7QSKcMTtyX1K
IXNg5LKQtY10Oph9XKM9wPEkMvKhqsAs8FqEF0QUbAkqv9mN7TLJUGJ8fOG43MrWTLrxq6Ka1Ogw
IIjNl/vmXForc5ZDPuE2eS2Lz98oSkgyk0C1wxMnxvQXrvRJMCc+86j++7OHsi5kFJGfIEpI2Eqd
1fR2HPxzCK1DGHMQny+wc6DGjLzM7B+TOu6CUlxba3Sdiy8mAcae1sIhuxijq9nL3UzUKwxbLSAp
WxQ40OYOMBSvRfNeIlfiSDiVuvoy6aULEB/0tqGxq+iuC/ppSFdV8Yi1KFb9+bON2ddDc0/E1k9Y
sdS4pU4eun0ZsZeN5vwpdd4qd9STMzI6TGTodk50O09SnAdnt73BJ/ffK+05LhnGu/WOXM0ko7kR
80hWf7wcVZMLoWYloCk1heNrSk8xw+Rj22O0FtQ/UFNxCD8QmHTJtsaxIscKKw41SftVk+6wxfJT
g/qmvuy6yAxfmTIw4nEL3CdYfl6QsNwqq8HkuUz/aEIKQKiI6NOeWauuOkbhmzGkSMSiurN2uVQ8
yBX4aPa/3FnMsBMXCoK1WPFyGBXFwcL6mR3+oMPx3budRFM+Xl54zJB9f1H20idJLd/H62+0Q4Hy
OYFjjdSKt7GY4UUKO6bpZIG54QA1Wd9STlPXTyvrj6jnKttcZ9ktx3dYlQmodW1AGSadq0MBGJz8
zO9i1TIQJiJrvxJFml04e8O6MMXLeyFpqUY/UjpWWaWnD/aI+Jwm69qDBdb3C7ruXYmQ6lEWRMZq
KLPokuHWQX46fTAFt1qFY3LxJMc8fGLRDM70mNU7hfBrs77crhqh4L8BS/hL6rjyQIctCLSM+u4h
50l0eMKnosw/eB8S7FQzn/W19Tm8PSPVLyp9IRjwvmBmn0Vuvqfwp5/OzyhuJVgxNMSQYLPLxNoZ
AEnUSl0zhGU7cDMDVhw+6UzvqU0PvkT5Lz7j/Ipa2kd0wYRYGLvi68saJx77ETuJiDT5kz88yElU
Fk1NYiIQYRbWtXtV88MJQka77p8Ikqvz8FEipGSudchA5gp9gplm5nlGDT/YFRuhwrsZYX8LkStk
It42PFLJUREdAJ/w170VDfaFnwz+TKysb+2DvXupZ+geNNl0hxfKg1r/9zrPmVGtWeTkH6Gs1iau
oHTXHTLE68HxPc6fGh9k7Ha9ifZfYf4kZ+CJNa62GvWf72sDC3CUSeBm6AJYDeTFtGlte5enaFh3
wGWPHbUyImN9gdBAMKzdzjcT25i5pfzqKhgryIX9QHDcTJhklWJF2j16flBC8B3oewHBffCjqIJ+
6AhOBg5qz7nmN8OdqWYfdqqVYbV0147yn1NiI2G+DVZQbUQrWeshrjh4ZgWyMQQY4qExsWyB9NVy
YOkMDhRTUgJa7JNDAfd45j6LHZ864sZrJpDRfEdvcTKSDss4PGOsbrIZrLk2Z/IqfwKHZc5gmEzE
5B3gqrPDeVcBgjMxmGxiWOR0x5dw9cUgj1RWbM+N0YqaWtvQIusjp3XPCvwPzrhQBIMai2swwfJx
NZ1TQ23ImyVweqJb+0RDFFzIfOw1LRPAoSIBrscZYqKPDG+zrOyHWOyqH5VbX1k6u1o3CeHd+coQ
C83NpyCBXaT5+6AMw7CMGKIYRWtNqSV9ufhhdvtyjsRj0c2mdVTYemnO2SN5aTovBbcpLL9tPnC2
FuVhxrhgIQb1Nr2AqyjUQHmUhFQ4qbey0+NCQbpvJIsz/qCgvLPPT3+QDyO1q9fO+Tx+Zg/GIisW
xAx+Bb68yLNO8RAXm7ssNieg8t0uxACIodbn5N3UTlzl8Bhb4tmcUslctJNNZBpqQyZ/EpsvdOed
d+cPCary+zMh0vwtySExbbt419uxtt5PIqzNzuuAoYsQ2PAeu45xPPKdCapuKSHPNyeXVAg76E5H
eR3nlpAZATFV9Mg0OX1gi6gLi2HkHMuyA3k6TEKcQvHIfPU0hQNaN7ovZ1VrT3OPwFOrpiQIMDEs
lpTyw5bp0wCUcrq9z5p2ADFfAL1uyMptVflkNc7d8w2Y+f1UeURi1ZbcVEb9pxmXZOkaZYj7oNND
I+AVle3z6eNO33oH5nP3a/Yqkj3Y9GOYNmc0rEIWe597oqqedbpo12UxCqfDx2ncf3ojsSGaCg+N
EBfkCftJhOQrxJV/7O9f/fz2WK3++b6DMVLJVXDID9vkIWJ3ghEM8xP6B6o9PKuZhw4j3hM+9WCA
da2e1WCwBv0E6eQjfQqT4MBls7/1kG78/y7yHvW+d6lAIwLeOwWqQ+rDJbcuIpENW/kRCBCsYTRr
0V7C/OpTHT0wdQBQusKEvJr9v/rhVbWaoWs/gb9ldt2s5Wgd3ZAZye2d86JHxW4XNasq5jZ+VdO8
tdtb8RAdB73T3/9wzSJvQCORhf8Lfc8qnZScUU88WEQVo+MIL91gV/yvJ1TMb597QmX6N2W/eWVM
OFLbGdifl6/BIrL0JSf6WaskL7PgC9L5hMgrC3lFKWu2ayc5lWvN55VegB8d8KDVGeX/3k4yZ6G0
dqJ3eihHU/ThmnBFrXu6eH1wertMY2t3mgP5apaTlm79rX7BdtYo9jIn9buZlRwnUdVZhXcilcti
DzKSURqKtPM2oyp1W88bO4LJkWH6nGb3z/qEQFtIxXnln+vKrwPzUHLIcbXPzTtUNeunYDqyTc5K
BGLwWOEZJdJip9Wn1HgndeeqIesVcWznt89tJhcuuqXXiLP3yld5DocCrROzXixv+P6XRsAcMp1h
ep7MbG1/p9ALVOihsjqNbvA8VrU7dEHvvmXwnlk7QmhniZbDFwV57r1XfteWo86REid8gx0TnLLl
FzaJo6jMsh/9XQDj1cxiYEc53f3dfznQxDyiZnh0bWGRhYFX8+PYj/jNargKSrrT6NQ71ge51OW4
7SauopNwsDJ7ztuJn9kw6Ay+7OXxqT8/d/v6hnOfmQ0oVXFfQnINaT4f/sRpmcIaGOMsOItXEqrT
mQo21v6bgVbIiT0el6pZP6NSvlaULRIlWbty/AdKwy4okAkF5aifOB4ThSS/x3LzY1HBfypaVSrS
9YFePwNi9GvAoy0NOYeMgcGN2tP3SyGy1fSEWFt1lo46R2snXJiErJPCds0EvpzKlNaeHNBtgZFB
X/pd+hT3Udtpyn53/s5EUUmhmF10QjAnHdN0AouyPytJAeqZKUmM3HT/Ew1wTyHyZP9TF+quHvdv
jDny0RhZJW+EMz3gb7KaPL45SutkezmWVPJsAAhgqOAAAj7GbAGszTNa+xEgY/jCTiZfxqj24RlS
8XQr6rRhI3Txx+8q3hJb9Eq9w0o7aM3lRdA86jswza0M3ylWeY0vh9i5EML1ybQSfJ3qXmkBx+O7
UW6zvwkM9+Uidpr8O4ByxBbpO9ITcuCLjJLaa1Henmb4SjNUR1qAyetNSaM1BdRJzOMdFSAaXP1X
zm7tUJDIQbQk+hRN/olm3XrJf9hl6XcV6xUGz6KN/BHs/3ylYfb5KIGUtbXHU3I8GAR5tJQHQnLT
bPTvYVzZMDUmGFNOu7+9j077OuCmu6vj1j4AMSU8ljx/vRDEIDYCWJNxUF3QirD+Fey8V09/TAx+
OqsTaMCm6tCwsyD/HLBaMhvQy/d9DXOoBttR8iagWejzGhdR62CxIX0CI1qRf7NYKkAIRkMOSeYl
knSNV9JeKklMH4PVPU0YkMmxV67wJ7DlCci9Kn1IQo9/vOMBXF1u71FfNWA+KjHjHU0iwwJlLs3t
uL0xcKLiT5Rumw1svjzKZZqoc1/zXwe2q6P4A8tSh8/CAYm3F16n6qxY1SjGqB0wrzypzWRwpXvK
lgcjpSbRNBqlVZ9TbvUBlp0oqsF96AFECOcyDOliuo1w56vgfh+pGx7AW8EHhwdZVDRnjqgA3xQv
xGfaTL9XjT8a8zGIp+wAqVrxvvVW3t5VLy2N2CjC+BLSVr4L5diWZ4wSkbJl3bJC003gHLR297t2
LxATh8MghKWZ/5NMS40fwIOu+5o5snoz2FYN9GHx8JTGCwJvTP/Y3vmhwmQ6aCIoCvmmMYPwaMZS
OKJzNyueyNHanxuH4O8aFDwtgq+sdIYDD/n0+gsjcBeUzImcm+KFkXONYq+/TMCRWVEw9HQzA4/w
xkTJ6d8OOKXSkufovu9tFmrEQqEn8MST90xZvDw7zQxRf7qDm3+u/dLYuRuzp/wPr/jJBUjpLIQa
r6xZY4v49EofyxUsLJBHy69GR4Z/stZ30S8ECckHDyQDuZLBEH+FOQi/lFn2A1kfAvSGFTTk5Iwy
SF3pO9V/YAhdGUAuigK/NEZ8li9epZxmrM85wcHQvXmJh5uHRvt/uJMCkwtE+vtKEm4rqB1L0W+f
z7dOK6DQhlZoUJwL3yvLiLbkgyclAya9z0B/PBEcy+Ydgg17m13Um7wqRRkEIENsCB4U4SJPYUXl
jkHjM6J1fI2dt7K7GXI80PNvdF887e+WM4vJvgp330eJOsuCJD+1M5Vium3QcZZlgET8LFwtme85
Chx6Ilb6Tup1ElEXGqKGKrH+smGCCz9K6yLzYYCytwCUdFsfC+dLak82fsQYJwYFeeGnvuj2mKou
8SjJ/twmvuvhs0twzkCKLu3r2Da9og8nM11NhxIX135CKPOHV5rfWqxifO8eXZtjRnOFFA5/r7U2
kuXHAUjL/S473ugd3ZFonLesxU+vgxploeGDwsIgRkXx3NM8a2ocEXDUDYljb9o4koDA+pon/UsR
rdRDJXTM/u/IaJS4EeOwmge2Ayi6n3TdZj9eRsUAv1MntapDgeIc3pUiByYKWqTsFYqfnOtog5Ey
6RynRX8S9q/RFy9sypeDuuRgwqE0jpyUYz9K9Cz3SCwrSZTF/0j0vIcXPRwnTUUu+9VJAEcg1Qsa
/ZY0U/GrBC1ZDwYpTOoR359TLdZwz5NhvBtvsx3S5XdNRCwr2jbqzfMRkU6PWWr6RBu7H0SV25JV
s8GvaMy6flMYCv0Pe8awInV2Qe8j4fopoRd0mev0TNfYgSoyKYVgfgqFkE4TSDu5NkhiI+G03mSV
8KP6dlC8czqmOMbc/LUckKP6QF0HvnD14176jQsIhcCIIxcqvoAM7Cm5dct+15ylO6Q1viL0BJ6w
vUNFCaW7y9lok8s1TkDicxSI+WZkxmztgz+3tVyaDkbOUV9O7bs3+uKlMZ3cHqQ/Zz56DsJlwI9B
vFnEUDFDIKBClw1jEv6tWdAR0s0xK18pb30VGW/WoJvU5rFR/hy2Q5eYI388ruTR0zKbQ1WLBnAt
OKs2ELtzgCLgQAk0J5FfOX8QRBMbGcOX/9n4pnjlSU0P1KFxe5hTPjAe8NB+uU8q25q7XW1E2mC8
DxEboIkM3HMraGCaIETqtgc7yM2FrgB8pvaqaGpgHCtJXS5gR1W9YUzvsgR6uho+lTni9pva2gek
RX6qe1XpqvhgUiDdCEQ9rPmoy4pswCnqN8Kgxq1ZTKIataYidOTCi0dAeWg9pa8nRH4KtI5qa6Hk
YJMwgZw8xHs+jnaIhkVqhNqLE+OJQvNVEQ2F2UaDm0YUhcKZYFgQV9WLhMYuZzhEH6g30nGPutX5
Pc8daKyQFZQWfTCW/bcTGWgIJ7XFb9lSgVqv4eZglpRgWMo67EF5p9JLcn9klO7poH7X07AHN7DB
iqVpEscO3OVtenaNzgVc/gOveiZsMvlWaR98LUn7nzHih5+a5ciTYU9AfNFXEESrkH3nTM4vKtrr
Bb2icGKkKS6PAI+46dD8OpdHJe0K+3SyqAGaFCNdUX0/uYV7gL1vefaq4A2qTdxP/dFMGw76v7u8
D9Pcjoev3oGOZT5jkzuH/T5kmOQLVeylExRvcL9ZPmdgtzXzPKVuAqr21BwvIDseQwk3GMHGUzax
Vk6/25jXNkgbyWBKLtgtu/cE2gxHUQVQ9nJPvgD86dhpT+YhUFzEFip/5Qrg64L1vBZ0tz0i+caG
6rY4Ji9nCIB7UOefqLiK8qU7K61qA6mqTIRKx0CLg5qV4ZJf1nKQDKgBClZmH/+fs5/bT07gyJXB
PuWLI1U3ICfLhHv3DlZWXREa7eRXs5OPrtsTTXhtCa/lwubJHVFyoEvHYYYySMNxOHI8Ew1EjLE1
BLzL5nhohiX8LWhDzPiDC16QkLRhN3BpVoXC/4kcDqba4LkDXqbtAkK9waaAmzw7YYgprTHzFDxj
hGqN9xFaZtaeQe3LRmXWhGCq0Z8NO+teguicMVEFqD3RA/8nDSW/aR1uy1kj0NHSdBSDVU+DD9RV
U/l6QcnfdgVokhM8+mUIjHbG2NA2w9+eYQr+GsmHwe3qMIcDE79j1+/OD/TWbSDQwTxVBEuPrFwU
8RNhHRohNxLN8XneLYfseZrx95crs5o7omwWaeEtmyRDgPp26TKeTy/9g90jLAKfe85GTDAwZ7Wy
OgCJ/BMWITjJ3kauuKPL2droWzzDLG5sA1x+n0C9adblWGHPjhob1t1XqrXD+Ov/p1JlM3zJmL+l
0k5gz/Y+kUIjxm2SZMdjcEbTxAdRP5ozW0vS2lOmBAEKIN3CG18qKuU5enpnjmlb5HAe7vWWpENd
YCkK4eKF1paXIJb2vDt/mcpXDXB1KTbE/zdpSsSteSe6rbxzvQgZ9Vpi1rKd7P9fStgdwVLWsMmG
stPz9LpxBme1GGd5hrdpA8Fmvzx0GmZFucHoOzNcC1QACtJtvpCdA0c+EZYHwS2e6Qj+UYuouXBl
mhMz3H344FOo7qVxIam01FDrzZodyEAHJs0ryCbD9OSeuG49pdfahy1lKbcqZLwoVEs0hJSYsRHD
tKn6jEkDrS78yIGZYmuiYn1pOoZ/NyAFNmIEeDNDIgMTSlL/VmPDQygayn4m0IG6JPI6qdBaDvbB
A8/9aIgWns0ey1c8J7sV75Wycvz7CG1WgRef8lSiOiwxaQhqZ6TunRXGvfoXIXicsQ0YMLF0pQqg
eEmQD57olUt70TZl0k8FskYkI+sXyQleZ5gr+1OPIPgmG08VUW8y1s3/ZoVGnRTKcLofYHQtKoap
ZHsgOoimx3O0sXtLG7E7LW14CzfqYdBCvKCH+NChgiKjAZHDexfhyJtd19UnxruVqLY7tc5xjzak
0Uii49BsoNZ9TV5ag5EYUx8GbuYQ28AJpIt4p0PXgclQntpL4rKCiaYhN9U7fzw3xH+12M09gc5z
1fdMP2v0jKx9tHvb0g5T5gF3AeEdGnEpPoJLzhEW/OoCKQEbkq6rO1R/5LJjHSbeAak1vaj3BZiV
dCZZTCxk05Cu9fDeg8qIw26M2ZsSJSkspNpmFFXOKjtftjwsNBEherdULdqCikrZ0H9EJeBt6jKv
Dm4D5g2CNPA1R7K/cVssrZ1qm7OBfdWGpOi4tLYKcsoE290p/lKEayoM7MuJ24CSDGVB0dXNdu1c
9fvqqHJ9q+7DNo7B8Z0d6ouyI4fTJdgiBRBkwxs+IMrnBCPvsy3OhBdJhMsrJ6pcJVhj2rCwXn6C
otI8Mjy8M/W9WQKaVCnF/GwQ4Pwggjr+0MzS/+BuTPFwx9OmFd6DSe1UMVMJLHWyqMqh8eQvPgaf
impKMVhsfpgxvjy6MwD21pOlrC+vY+lYkQPdPzEULk0gADOLjOG7Uc0KjJVaCkqjItu9N4iseCn1
GnnHAjszDiNCghOdyswyLCmD+2+LgYJf+DLoBE5FUIqu+/BQus23Dl8cGTrMx0rYTEGhYzcwm8Xw
s0uzfvm86xkscwaf2jp1O2bO+gDY2EoEH3GN0gajqd8RO/JILLWRPLnVtaAXVN56T61m4+hixOiL
jhPsIGNDwLSdBd3sREi8jASxp+4ogolR7GA+l9984OxREdCHYInj7k+xEjoVGvEO3LLOID/KH8MR
AANYiLLCrhiqfTrFXuEnXGHvjZuhCfF0VqSwgQpnAn25zFDSki7CNVxoqxVda/n43g3+D3AmLoaI
78sZ58ihTEuNEVaJtQ8XHv2tJVCEgLwydTIGdsKtivgWOG7cHoXPOco82jpGVrytvBPCLcuKDCxo
/dGMUn5cKXYC7JEkfjSNAts24KP0+USxjQzbgmW5RcCIA3s+I/xoKW8//es/wwBOcDA6oryi5o2u
jZyNCnF9cwduhtAGbS7aJ/CVmfivbzvHhXta/mwvjMNu1iTg+FteeGgyjfIshIAHJ2IbJmlG+2uG
BvM0QOycdyprwp3euBLhaRZKJMHqwEqkBP8gNdGYBbLu0NQ8QAIXtphUVotIMOb8B9MEI+T5TEGK
WzLPpwR6ywcUtQL7eVumarkXYRG7yjgeIBBFYqET/nisAsv+/JOQFs6yX9taCTFi4WBCMAqPxMpx
+xbu7aJ+jsHhYxGVMJMXjRAWuCfp+CmGlDrAIfFFpXwKHdTohCvi1NSjUEJdZZk4do89poq6yKCH
FHG5KlmESA26ucTjTeGBcrOz0ZyWpL3DYrDKKeF/KaNwPEsoKTGUSlAjaZxH+g0LHy0ighDWd7Lg
PTvuWDqacReO+VrBo8zPkzuuJtH2WAQ7KvfNytFcuDE8V7IOBfim1ScgDLqO0l116ercyDvdCHrH
zyFnCOy4WDATSK36E6PbhOfGvbqPrquL51kMTFbjroZ2zlElVT4knduPdb1C/393RvtoYc80z2d/
1kMNs/bCxetwDB8wryGYF1D7TgaMKFjcA1RAm9HrnvPFy+xqsVNUsnbs4X8XP4edyeTASlGxiMtY
zj2Ru8V0U9s9ChIPbxeDjuw3yyoXWlaQCLxXJryO0OJKaIyynoyDKTSbeTvCy57O5UPFHX1bUk++
4UUPm8dVtKJMd8xqkKGO+Aac0DDPb6QwqMkdKHf3FEmG+mU5WloObxOE+sj9yeUB4Zrk1SKj4VFI
IDEGD3Kt4yumPOTaWz2t5gevxcGSMkz/zMLqktDWahQQ9mtbiWHcFtOrHPrN56nCciYYUSefhOvO
Ie/6YHH2ZiKO2XRxp9ZUc2CNUWtUGu0hN60RwBrALECEn1CJQzsZmDl/I8XVQ1nGIIsFaYXyA7gA
MzRSYop6gcnvdm+HOuKeAc1djU2Oj0Y2osYgHNVHCkWMjTQI8gUpctocBFzeL8bU71QXylGqPS8j
ViqrjTPTt7NfKBA8DSzQmyGAv5uFGKB1fTSpaq7TMel9r6pLdWWkU8mFbIYgG3D4mQgjVjYL8W1+
o8abiylmH4LJ+xMe/CP+r3Vx6shzZM4wkc/IUew/gwDv0FnEZwmiBZghkUnRkNjhLf/h0lCepTuj
6cWDenYjrr4jONjXtq3vcRtvQ3K2lCSJrn+AjOdvv2Tfjux2uXgHTz5d0TfP98DlGSc+hxHbRtwJ
ntZH8RzTqQxqnN317rkD6GPDoHJ1+PgI287lOXbd+FRy/JYSaFvCglI8PN50qiNVc8O9tgmpOdv4
PJ9qsxJJcpGf5ciLO5gD87NOoc1KWC8h/mC6PhlhBcH407UQfeEPDcnuZb1Sb6AzGVmx3H+VHBFD
+OusYwCZHJA8VBHQqRYRMo1yXjdaL94X/XT1fCJnnmhZDmf85acNRuN70QzHPjxYozoUFRrLJ/BB
Vx3uA1f07WTyfwLfMGCzQEckIamojSN2WOieYhuKUXbp+x1lw01wQm/nGWejHvu//eb/sWFE8uBI
lACrxXaWgBx1g1bshM6wafvz2XhRHU8vMgwoLdfnxVL2yfKf3Z47LkPyGESA6YMMJrg+7JTYghJF
3HDF4+qE8zRYGlJyOwYJzeNUVqLNyKXiyLiE65kjEiWjPO1W/Q1LTQLl2e5QK1dAKky9XtQxMpo9
iT8WFYdOQ6X8ieEOxKeFSZRPdpDK3Hmnb2mH7OgUktrxVEp8fYRVsl07dnfEz11OccXuZkVfbix+
tn/lbsXbBThkGDPZLW2tCf4m6vnxt/sLM7XqYNtQoe0zCHRVnbB5VoC7h+mFwVqZYEdTvvTh5giU
8XAiPCS46Iqlz4hDHucJt/vC6BmP0CoW+RfsMSlu0EPaEmfUaXfneIqjbp+AOyzkBZiFfiuiSGqs
rYF+qVxcW6Yb223rMaZ6SoQcbVjMgsyG72X69gbvuUZvEAFkO/xDvHCkU2uQJSqdcX75WMUngvSk
yDQqhc4nPaGSCJ3B5T69+SdpPpMDdc5XDskigBTejdGV96sfVW8MeC4YGG005UmT9Gnev2SEtqYN
wQWP/UqgHvnZojbGFSPxovQ6km4RSnu+RRvNdkS4URkoSZ3yzggC6AyXBMJjib6VUJgPW8BaqAyG
UUrbR5y3DIGohVQQk63DxqzaFYKLpogXNZ7bnWCcIxh/eFZiUEbU8LXr34W3vgePMoZ3w3nEbBy4
QciA31K59+Chl0l3nHdwT+e86vI3FNskiHwCdi1Wang2QPueH+FrnikQkjLM1ZW9iHagqfBvhubA
qFHl7bNK1TYrucqgItauZY6n6Q22QYLQ0tH2xkdS9KdmYEmIM0gYxIdjL3TESatn6sYtsiOGPVS6
nHM/RVhap0UF2iC7X/A5+XxxDt0hPpu+iQKcuOQ2tS/lo87IGXg1CzpteLOb38WZrFvJKUtngSj5
8SfQsb1smA6RS3n7x1t7G6WgitWEnnVCcoAEzpc0Kd8RuAeUvrDTrWVkouVfS2NkB1GYEo7bjyQg
p9nP2K3kyDkUK2QL+p4HG4585hpfHFY+mxc213n8/wN/UTeUs8sk+yICNUPKHGRBCuj1FJLw4sN8
PUEVrtdB9FLOhmGq82nXKfqc/EdQTwOV4yJRH52PF4vOM9OWxfYjnjGJr+rxTCuZYswYRjXCm96J
fRXFGhEiU6gL8ugCDREMQC3GIIHTcGsLua+m8cLyYiEPx3vAHpwXqI3/Hg8KPyUjatYn074hoEDJ
FQVJ3mzCpz/ClDY27ZJMJ8HFaOmoMRTTjJtEMNXKJbp4N766DN7dMxszx2dXjOFYhJ7Rq+D6ljdg
9vZ3vd9UbOCajagtluVTLrnJhhbL3ZhaDVL00dPWaIF9e0w1FuQAYZhyNidWkVGlUIJzTEQeA/TF
pZqe58Fsjg2x8kTOL6kJJwq9cssKx45Sw9QXWU8K/VPWkBiobxIRmFZwM6fAZP9OTr+7Mi0GP6Xd
LPeAJQTyaqBEbwcIBB0iRU7XSzso79QVpfRVPo9mv07z6kz+Dj7r36HF89Xvdpoy6zKhux0kYdX4
QKZ59McQlXP7FDRBpHmRtBey/yWPZ4+2d/kumzph4qY0QC57Ga7DPZgrnSZS04yHRftYHEn5R1Ip
tP7hopb98PLUIYsfANvrY+LzUPmoWzUVZtwjZljZiML6fYR/IP6y47lOc6Q2yPeA2ZnmcBc+3dcX
SjvysqvbHOh9GF9Etaw1p/bWEIjUEChsAO8dlBgX7O8DMJYIsMgIevVOlTk/kpYnIKnBeDU8sRRu
EmzJsQddZXFOAS2aTiJ8FZDc/6yzU/psJiOXjr66pC/bER+1Z0z3V2sru1VRZZNcK1wy0xVdmZDN
VpDvSJVw2ZQBzJjahBEQhKONpEbWM7q0ebfbRYrtNwykAPaMrECuEUAa7Kj+vUxZlZeozln6nSte
18UVtQziKfscBghqDO5ww6O6YeP//ZRlMXfDhXCqA0x0BWSOOtRqS1bHa4pqvMoBccGWc9T+O0i3
qjmKQt3Lp4qvuTrNIq8U9mszRuC8AUccUTP2Akowqw3hQ6H8eidAJwQDequFFqjDxdnT87nlz3k8
fHpGGyuZoNjUpXNETEzyeuuBeR0/oLr3t6gtpg7aIpNT/gmeQ/RycyhINLd0ieqTCsK4eQmz3UBn
1AVcSYnEAHVi2QZM+PN9bPCMk0aBfJk7f7F1UQ4GXOF9DJSCbd7WUTE/N+veNJc4mvSaB/980ptX
+IUmoCsIVws6TZ7KAVunzrdzNy3mO0gGLIWxej2zd5yE0TJ3iQrta66iQWCpLlWLUT6ngbmiZ79Z
hafnMr3LbB9FA4znl9QVcKGX03NmQDnBi39YaH2CuNTcYg+oDbbAsT2ytKvSCLASxHcoJ2ZrEMBr
SFX6aSwr49WkByYZ5AHwrGmB5py2j3zpua/fY5iAYNXDVKqVNwpAK5LPqi4acpLISrBdB5TzcxcE
umZ3siN6GUtnkfDyIAqsT6o9FqBhis5NxasK//VBfp/D0qYTW9x7YqeeWKfkOOaZVbgyN6aVSk6d
ywpn5CyleFa6N65gENCADQreGJVVSEgnfOM13A/30pOyCjgghQTjxHLomdrSr1wZOqarhySVgikC
7q5qBTmPNxfcMS2Df14pWbCUYO0Cs0UatEcq8roPOtSrZ55CMO+hziyKCQoTqyQlBHBt+IObpBWr
9Xc5AWYf65nJ2NmPBG43ZxZAoYH016N91zsZejTyS6TzXWJGJLqBmJ4kIyvhyXI+XYAPwDgc4vrp
WXKeudAoTLbJq+7AFzLedeyXstibhFLwnELPwueB9qEBMwTuJ5EwzGndNRbNOsaBBhM6rdG06e0b
rnDo2/U67SJ7j0wywW6y47HmAaDMO0lkJfFFVGYDZGoA3Bo5gq26iU5eFbnpISwfBL25RquiEPGU
afArdu1NJHuAyhCJ3ZAsTC//A+vntKuDyBi4maH7lrRVlCXEdhk/MM8z4jk5+lVrw73zWsLZm12T
yncHLhE2GYC4lfXIdwwJpoS6M67hfp7xMTdVrmLeYKXpBt8/gkRMjb6PCKvtyY0bRo7LeROZNS5u
XpuGv1FAFrfr9PkHaLFMOOVTlW+jzNjAaEZPzy4xZFpAdkpGgOcqFNXV4PcXiEiLU+BoHk3+ZhIB
mbdwV42Vcza/Xcan8pgPU39Xy+gmQkB7GUprqmSCsAuJ7F5Bnn1raz47nvbRd2zsYMgIe+rRDRWq
sharc0CqtNYUy9r1PAvDuWtiwLiJ2jkX98ta5E8rV6aj3gRbbZt5L0BushYooHM12yIhWfUoRpNb
ytIomtx8Env+7XJklQgxDzL5LdmCDUKP2/835YFmUrvwhGUtQICKOANWXvK3mcvEa8z6MIeBqf5c
jdphs0xbJgyzT7kZ1+YKVa8aReabrEKFp7Fkxm7rA3qID0R4XVxWsgnSwwM+Kl2LpPI9HFCY2sZy
46nGpQgN3gXxTghxD2g33mrw/er0Nf6eLWJ7T28jhers0rGw3C2SyOHfWBDATgelc2NDETiix/Uk
gCoVwO5xV72RY65/UGhGUee6YsM36ZzwTwiDymV8TleOtcE2Y7WJy10GJsA1gAdpkHO4L17Gfbvm
/OK0zX79vnoxCkS0KZKR+w6quMssiwFADT5Hd2nnhBY03fHdIm01qjm7vgv2pPxI9E88iDRr8l7s
G+v3+JWMhnPIJTeG4EY/sK8ogUupLueW49kheVtwPz+rtbDU/S3lAbRmc/GfMCEDkU5NVo5L57QY
ggMmcTDYukcYrCfOispZv5oamfWUGvdNmzFKHkbM2QADuhyvyZQpCyQBhPZzdDt5DCbHz/7UO+sq
8UKkIJjysp0eszxze/FJvLZZepZ7pkwDpGsQbiXJzyf2WbKLXHfU+TwKj7VQYiFgyZPgMurnoMod
XccpFhM2b/exDaJer/n1b65bLHC2pqeH1/RAgNxcg4bQf/3mNLZMpEKzQQxFDtI6WZLxLw9dPDoO
lOseDgtlRuizFgeOlYtY3EC+EDoY6hrLl7nzD8NiJPszH1LNrU4Q01da97l0Znx58vhApV3yuaom
/j6qdUGO7Wcu6ZTkVuNWvv/dUL0N6G1rASC25qpgISG+jqbcgvggxE5oVIbzlJmBSr51klFCeOJS
33kq0IJBN/S36MlpFez7OckAdijtenqyvvTzDkcNtD1uZ7NKGC4vNOZnqhTCtEtAgMk5cphuw7NP
MZD6I5nNELav+/iTOCCc5paHHmw2kx0y5WGMKIlWCaTRH5JkmgrwpySWnl7vHXzrAZLRSNC0DLGt
xQjk0CZ81n7eqbDQsTJHv8xNXHJbHMCHcTqyOoh75agsDDNARdUr88lMwzwp6m7RGKYdBY0fHATD
cuHvS5Y+btJCymKLOo3BmCU5ytX+1O+cmSO7kKT6fxRAoM6hMdBlwfBQDVE4xBr97a08YNRLdHbX
8yV0/lEG7cDAoTDIbfTVa6JCw+rM7iD4a1s2xDWaLWjGPPJYeGN9IesiItx32IjZi2+ukIql7PsT
TGMc7WejlpitbnU35G+17hRPQe7SLbR3bHv14idEiMqU9LoEuekCQDv3NEl8/wi02SJT2prhI4Up
J13o8AjIHdslB7zyPS/Ah1FLOqgwKkcJKQ+xdvAqdZp8eOdyePAqaCCcbr0+S4lOJ32tQnhz7nTh
GoYy7hXYT/hZY5DXezY5b2x2Zaww2PaTH2UMEMm/hQapVcXyPvjikfirwTKmVcvJHH98lcOav0xe
i1Q3FuBOyX+tJc3dBJVlP6qgR7/IjGkAOquczgVEtPVy6yiia/EFVx1kjL2qr15AluJxuVG832xe
16v+WD/TumRuiE+nvLtn9SuYCsEM1dqVKLfVxdnggChc5jNlwstumT3gfvfzblSOMOcpDbkHh1o8
t9oxfs+ZqmoLTCDXxX9l5ZAqMlYeZKGTA9e9ARdsr5GmC01/d2yapW6JFvoPqOBjyzy39YuRvPVv
LaHGwyp8uVOHBPNxvkpiNJYcai6jBqIuQBImg3f2Tma0EE+eIvIo+nGUpCdzi0UrulDTQJYdq/rj
M8iOKPheNQ0fgKF1IspSJ3qLcowm0ICJdcCPqx3Lby8Xdiizo2IlbdYHlNJBSCgRgn0Dx/0uTv+f
4fUKLsk7f85ijIu7ayuf0VDb7nDU+NAieod6XqbvOx+j2ELqjYspoLZCr0wNVZJOHLcMr727US6v
YlvANBygsoFFQ9kYMX2JNeV9DpioAkpL1NaKZQ1WTM9xNr8hXPua2SmbPcmB7fn19u28+UYHFNov
hVLtMgFv1Te1Z0uuzLqDbppIfXdzJsndtT8FIRHPVFnhoOPnKdjnCb6eMEwqqLWeF/CQpf3dyt/i
eM6wHysFlXi8hEniJ6XDrDsD16LHIlvJK0F5l/cCJJyekIkDoJybioL7q2dzcLByp8Xed8ne6BM6
3PvlEHzsbd/wy3xXQ8RtMxgS8vXJmXVT6fn/RYqoEZNfZ7+Qp5qq0aq0gxyLNpKjPzOHNrbt30Z8
KPy+equqxKXJGM2CDKiCQg69IqCTu3ioRLTiD62Ei2/IWLO6ZkncN58wrdyknlKMb3iNdCYd+1OL
IwxZkyJ22lfXXlfraPx3y95BG+TQg7DdrzNgDq8L8bObtowxuavO9G0sfG+z975fOFW/nmabcDdA
Z3dhGjgdRIaxN/NVAB4H22F1PGdjHE4sfRG33S6wu5rZv4x8Au9f0eTCR+saS5xSMf6egA+nPmdK
208yAdxv1iOPF7IAl0vPT+uKXFdtuVNsjJDHkSUq9V+s5aZ/CH/J6y0zv/+2spSIT0gQI81xRINS
yDg76tobCElzam0j7GBkvPmSmtDfhI1qYd6aiftk2wjX9aTSq4BCglu1J3zyxg6HpP1d0yWazDic
5ez7WaiZ8gDQIEYTSekF0ZreQQt+x+TmNQNz6cnsV+29k/HauKDDUCmXRZbThWXYORiE89jc/+Jj
mR7HI9MO7tKu9b0WcALhKVBVxXhYYakHQNxIHbJCjvmpG8gg/gEk1ChFMANt43EvjWVdPtt64hkW
Zo2vd3FzGkprOvnuVosw75qYkohUrbpSXWNN0nFtRaptP+VYghezWB2VpU6i17PfVgULrKuLdi7N
mqlOeR/dh0F5EH6m4lbGcEz0f27L4muL33TxH28Inud8wIAfhYUAnQd6IDDc6pUlsxYeEWbNAOB7
MtHWIftPXse0exzU+IRPeTD1tpVPMtpyxxivMM2cf4A1ezJZmWenneKKDLnHiVVNZSm+iVkJuWyo
jpPEkLGgzof9bUPPgpQWrxpuRDvw+I9pr120wz7PCK2/Iw9Hq78JAPfX+PQI1k/Z895tVP4sahUp
CN93LRuETiOR4zOvdciIzsNX17jskggVWQelfln2nO1Cx6TXVXFkEtkHNlX5DHmEZ04RXwGQ+80C
nBh5LK5UR09N73NuDsMraie7DaQJgk4u/oRBJemfbOsrVT4b5qzGrWGS7Ug4uxOtCHPZiaFkFFnV
V5nimnu5q1stRz/wmE6qUuV6CKaYFGhZG9zqNf7zWNCJCECAfIh5YqHyx5cfIe6jQ4I5byuuHP7d
uYeiVXNX6JhHdwt8lVJK7UN5cDEbNZ6uR42YZtgAldxTsXtD2fzD7/9JXeIdZz/YEbdo420OD9EF
AJ1x1kh56OY7QCRpFTSUorudegTTRHWddaO1pu0QcpuKRRgqF6z0fLSL6342XXkWZ/U7oqc1DTDF
5+OncK38IP5PPfu4KmTInIEWChEwLowcPXc4HHzLSFhKNw2e+sFNaiTyF6yU32GSNMnR07NbY5rR
zRZ6YYzQfDaPhHfT8hSAPSptQ8wiHLvFIIDr00O6pPFn7Fq2pAxqtMe8NmP/h/azoNboIG4HdFUH
XgcdANebPKnbSbh2JSK9cFyrwE3J7IkSQ9ZZpFI9dJm5pLa+cpIRKmWRCX0EpxL5GI1HuhUB9aDK
CRoev4oNeXKboRoXc9GKj8cyF+dUm7cDkOpOlqere03h7bnusprHV2RBMVIVir8CjviddFsMGxoD
7kuIFTH2/3QbO/alFre936BEWDXNgGdZcRkphTbSYuf8FcNXM9H8MADLjUHNP8rJ6VkcRgvScxVj
Y5A+iEi4M2PR0cxoNKXbgaAL89F+o1tkT2t5daWgYdPw+bquH12f5dRxpQ/aOYAW9SCq2rdob30e
0g1o8OWoAf1KB7rfy6rK+I4fnkZN4rO+XW5yc1h4qlV2iUFtSKxsNIl1WhcSGC3SBtc/clOUYPa1
HluwYOnn6LwanRo4vEEBB7F9pAGTe+UxvKeLy58LzJjCIEZq0PSUxoW/prPbf7bJa/7Mpj7zQBZT
ytRrkzhHtJU7UBBgCaotuiopU65sXtV0LH8mBWUVX8/2djdroxMuV3PSxhEAR8wH/tDQmmooWKTr
2bJQYjF2jstYftoA+lr4HuhGOngokwZDJCLUD0+Zq44oCHPpUvdXx+VhN5+WkbjfUn499XlkUX5n
3okTRS/COXlTON6Nfjnr8hYQFCZNzqVWeRPyHnYQX+Sx7/UzgrHvaRQWP2QJv3V8vcyX1Uny319w
ka++p/RWO/2X8Zrpe9ldYoE/z8a1dTqUUjIA54Yjn8/Xb0Cgf0PV2bQWomJUZpwPmEQCF1ARhi5m
G2qDAN01AbcfXQfXR8TVL2TfRIrWyfNluxapkyewAqVd+yVyPu78E9XSSzGRTWGGGp+isp7U0H5q
OeUaHbyiQ/5bOBuupHEe8Z3NuKuZk1q31RzRY6fG5Tv7pITTbLdrjVcD+ISrVqvPDWTqSOU8S0tL
MFQwqiqa4BkHuw+loV65i8EZa29eanf7bHgIMIj5qEdoPJEmgZu/AHkfwHeh5PAw4d2Z2OVXbujL
6SUjumeZYQBWFLEMDcbNp4L+egdk+HRsrXO8PBu/LsKgtXQn3aLNG8l4vU3K+PTgsRUwr+VQb1UO
pCScL19REcd1YBaIWo+MdR6GBQYh0mkS/+tPlW/l5kfMtSAUSMHA85zpILeysQ//EPq4eZGe6Xy+
fF395yV8DLQPqjgcUxhrq4NPMDB02LuPfiktWAvDJzp2oVyP3UKfKg2+ohGxbPeNrLQIsWAnRs4A
Vj/27It5lEx8HBh8g2pZ/AegyC022FYD2a0SHFezQgbKbaCGIyy1ztN1cV1hx0iqJhcH5uXeVHBF
jObI1lh9wA6eaud3CO1RDjLirt0fvU+l97E/gmWVeis6uP6aFWJ7YIfz6YBr27XE0tSTDzVkTdlA
84eeNTlj9RW7wI8/mxoayY109br95KZ5RnUHmyjrJOZq00+HJsOMgF79z0VypsXHU500iX7Pgcn4
orkBYfw7u9to/aGCifW2TJM1fgO97/Qiw/50+KV580dV7oUUT5Yr4fYg/7fOLUELG3tQe7mkhqM2
QQEpFGY9Sx/h9njyGUxAxx/EUfooBkSBDkoSTkKMiX9CqEcr0MSPatES2v/nRhVCm+fbcwDmrcqD
+/1RqynYIlbrN0F2Ip4EPXelqjqZqcHYqEHs385u1bbh+BZbyxkcRLGhvlvDPLJhMLze983+sVMO
9+Qz08KbWJYci0d3LCHodjQBV7ITOcKNT3u8x/2EoBeqShso0E4i/hzuqeW0P2Vc+TPLe3gXjKQT
N9wamLciNeurMR4QXKStxuiM0maLs2BGmTLetU9Os0sT7l3k7zIyZDUEc1a5vw2u9DCcUUyfhADO
pphOuEnLhX5c737qyJtr4jxq05gi161KBqgY82k2lVa3VKKKmrHb52xLNAVpw95xYxkZSvAC/ZyT
Yv+CbRv+kLC/vB1TIm0YkK9QQp6hlX9HFbzRSChnStm7MM8X/J7cWfG/l3ZhN1PdrT+IOJOtIcPN
PZuAzy4/k27UclTxRMKHDPMRytsQOBIHn2qooHGJokjLpIIFvL2/g8AZ/HZu5lOTQZ+VZ2/twc8/
zDhAJ/q71XK39gIon9RYDJLbBpJTj4za0tWlmcJHLVrcsvMipWHlG9TB+sc1YNKEmC/QdteatKtl
0dDAktmY0Di78trRCWLrIW23nHYckX1FCoy4oxvgH7Kc7vCBVSemN6VWYWQc8HPX155aSbHwymnr
gr+35mqqkVI9VA/qUoz1RjncMzGmewSC9hM9LVdpff5c6EfTix3zM3rK5jDeNb8/WljeMmzchYK7
J3JLUwwSgmDvyZ2P7MvnO1XAcNU19G1CNjnmeUEReBWyg1czoBY0cSdtQoMxElAURfpxqRywwTb9
IvF9nanEReHiTwZDReQbSXwGhHbWdWJV0yrGTQzGeeTyI4sWcJ+OO3k8jg3ZmQy3mcZDt1DOhlqM
J3XucUmouwK1ENok5C7cW6/IAtLXEZl+fuxi41cJk0UUn1bXc6an5ivuX/OnXHmKob/meR1SQ7bb
H6sYRW9bd+wAdDJx1npAC4x+GmNAE4o8Cp8quX87RbhG/tfPCEZubfp7XSes0lWwEMDrVFdBcJUb
8oaX4b2F7greidaLvQe3di64wqjffaWlQSm/nOmDKcFUQJLJpudcxhFo0fEsfqDsu/Hevw895ZeR
PL/5Vn7b1qw3HQoOcH86+5WWFvKnNUUGfJpjExKaWkvuhFZeYG1rQYnpFTEPRgsPrLWnbLabOd0W
TALTsC0rxe1QWWgX9yb+nyD+aqAsCUA8lftkRjKVfY2BH61qrTwhn66ziw3E3julamQ30ZZJlUEu
F0EvVW21pEzp/6nnaMXvagsxoQFv9aUCTac9RYws1Wucu+GS0dHRgLV9PCcRKP8xvVL8VxNyVyB6
THa/5Nas5lgQ6SN0dmO0qEesEd+1Om+QjubyTEcafNOO0VkgsGq28BDmNzmIXOrw196lsiy9rQ62
lSvdFB3WhkYkO/jZvKccADJ41t+/3NJcrGWZR83TM3sUfDOisVAVvpSkJ8aK40KTLzLvxuCEl0PW
/FDL//b1lSOuzdCyrsY3QwQxzxKGtDn5pIwl6u+9xibBgIV+V0F9QhBnX7+ds63Opm7+xvwR8H30
M1w/avGhUO//ZoQHL6+fEjy75injRn75/WR4GL5lCeWORPWl1f4lvuIGURH5ayQ368L+DK6iSH5s
u5cdz2a/WbniJL3ar64SESVLI5lPuXh6cZRcde2/dIivYIkhSIBJyFbF3KT1lsIZh9L8sTIQf+TX
tI3olrSLmhzGvzCwS/qMEgBJ9vMmV2WYGDEnE8dIpAS8T/AawPepVdhQbiDcswzWb304kFW2Zxae
OT73itSCbiTJJFSz2/19QyWO75mEdKnQC+0DItLD/o6DWl+BsnDqpQAVZgjSyjPQTaAo6xrwrPFQ
i5q8wMdQ8xTP0fkZg4qesLu5qUG/AXLL7AX/vkp+LVjdG6IGRnI66uG6XejgegTAHIw3KP6b897x
pEhEUQxFhBWxLnxZTzc+rhUb1uZP+B6keyuFgAm8Za7RPo3+jRU+MFiWPpZhIwEvzsHJm+yEmvBV
dr6gwPA4KmZVBGrdxh8MU26uh58IJq8u61wORJ75WMDWC1FBkerjh8K3czTyw/l2LlvUkjQozJ83
oYVDvHkD4WQsRFMV4xRKIZBGlp4Z7ZA+1w4N+Hlz3Uk5DcE+vP9ZQQ+vs36/iFeI0fTY+YTHe3MJ
pgKLxPsH5p5H4YQoeQyJwYzJwmVxcIeMLqNnYESWEyKHJ9ENyNSX2U3/I00oPBFrsqktTjYmid0v
fuhDpXcZT6pymappXz22AwP66V6e/anI/YHfJFPTldVoTSdUYnJogiCut+qEpWyRv4l/4zTfkwLe
8SOgnViAtf48VZhSMpMd78UwjMS5rOHmP0BtHumq9y85+6JLCyrJJ/ACZLdNMeU7G9+1wxumruB3
2cuE5++QOxvHw9JtK0inPd/glCEjCWl+CTv0Vv+DdJg7Pj5ayK2CBbf8GLXQaw7+a7n6SAY7pEZR
Kck9NfQFU7KKolxBEP6FkoSsSCKOdCqWwRk1niy9KzJIKCoKyepg0fmL99QhKa5eyfx8HvrwFF5v
Nd6E+7B5pp1dUaQq3huKKSoYIGqnJtaRRFtoMkcCaSQlyi/8CJHX6+rwRHU8Gdv2ZEIO3FqboR4H
ddK+aK2Ovdb8MOidZuugEIdz96wctds+LjO6NTyD9jG8SqKjdv/0Xe9ePlSfTMPJ0jDkwoyM+LdY
1bIZL2unuG7dXhjl08oSWaDWikfwx/MH2yA1IISkUVM020nJ0CUV7dskoeN8FrPiLQpV0ncCDsr+
76H9MzetF+e/fkgn6Z6HqIF7bXQE3RL6YA9w5itr+0QjQljDOQ0O0ykW2p0wfCA4vfQe6yJbIhh2
ZiUV2X+jOe88KX0A6p8dAyZsgc8c2Gv6a+G0MX1GgXMietGG+lSw/O/I2JpL4hws8EVs/MZCw6AB
qFtsCXpgbE9UWaOzbStXc4vReodTpDxxe/Y1mQcXx7III7f57EeqDO0O9P+loeeZU2egbVqGZsRm
hgjkXudFno4Yntb/BzueYnqWXd0Ov39ThouZ55aEwsQpef4/VtcfsoBZDoG9HXw4+5j0B7MvQaqJ
OMjewLwPg0FFYYry0DtzAWqiYFhc2473e0nSz0PpMNqmL+DtSURlBi5SmM7wMEb4htLa0AwHTNAM
WBnNEKyyqvWQIh0sdM0ImsKZ6YPHb35TnvVS1LRdj42LbTvlm8AHUFyD+m6M+hrDW37b52t2jf28
n4v05Y9NlH2kaELaqsjxrAyqEqXDNNv4mhtBVq3ZjchTafbEXgjuGkmyFftYZ/ei4pBELRSIrhtR
NOWxWwDbBpZttxBQwtl3XFlsUrTLweQDrrB+6KcoJyM2PI7WGMaPWgLRqRcMw3Jz2sHJEUoxxVw9
MqzaLuJM7mL46WBX6lHmd7Vi2CmaRpVRk/8a5z0clqVOyGYz7/E1u7ayVMqDeodAMkqkLGbOjhbD
S+nk4O00Uk+BE8T9PInP6lsnKxBX5UHImCuM0F0t0A+C+95pd5LkVfWAuQH/JjkMGYxgk51PcvjU
22e5+Vei1T+aydFZECG9zQMSYFPo9WbRpIbJbl5zdzkIEVdQXypgLJ3C4omcxqsZbuEzO/NQZQp2
HsS7rIFhmCVfGVYMIrdlWeM62dUqvZ0jHNALkIw2xnMNPns0Pmq6rcmiztUAkyGvAwfzjtpKGBDc
MMC1b0k/RGz9EzDFsbzsQkb765lPiZ0cCzW+I4cG5nl4JCZOO48+V7StZ8R3T+VyV5dJketw9RQu
+ZnffM8Jm728PWbVf7jWCilcVfM3Ho2tVP93wboJ+Tg6yafejRM54VA3S/L3guoNJMXiIwefNG12
dSKO/euZoiMDXjQ6xsWS1cVTdZAVewt1+ngRlrayE4VMXu634XS/exFGat9nJyVsMmXrzrtzA7Sl
mWFOV1sbiclzINqes98pIDMUqly1IDCGgR1nvcpIs6pyWTdYeD7A6SE9HHc2vNllznnugnSb+Xom
iY2uwBnsCMizfgsuiUTEr7xtHjcz4SYvUc4QWkHJ9DIv87btj8XZ/S6oi49IZEG/Q7JFDLrfuueS
A6u2tgAvcnlHmkBfMzWoosILZNtQ3+zABKdXBf08DZxUgQ9qPlBJxZFLeN97S328ZzNBf5+B3lvz
AxdCzYOhSC5dfgSYZGc8SZjuDEv0FBD9eAhTcDSyFZbgNAf0qWaGjSpvwQTHgja2fdBkDblYVsQY
9GdUQyMb/W5HqlhfHO3QVrZRihuRs1evJ7sN1inGbibr/ukqikwh0JBCWlYlD88RdQVAGTyxYXJE
dCcLXp6DWi5k/qnB9aCWZP2WazHHYB52OCofE5HVMDlb3hnMEQP+TWU/s5CLKan2pGwZVDtlSdya
l4zWAY9Dzsit+056YIIDYnC2U+S/bP2huLjZv0hBmnHq1H0MX38MPoOMp4TcjYG0WH+hwpp1n9TA
iex/qgaD8YxTcs2CLs4YeNhaUIAEOyTqH0KOSGmorQdz86kzw+IrF1FVeGrVtgAjqI7ySr+msvWP
VCjT7pa9rB/GRdhps+s19Qi/FcZ7QnAosESdVepU9oVPG8Ravsxy+7JKfpj8Eogmx5/JPQzI2N4g
e+dheo5zxJ5wvloh5wMavnMmZLabIValNY6WxLuZjavl++alSUK0Agus5K47/BdmPujyG8GGyuRV
kofcWyVp3+1fvVc47oXaY0jEJtkS6OHkPusYSXAgi/LOq66xBbPnaFkJ+vSpkPcZflAAOiILVOOf
kv/LZHTrOS6t3KquIR6Nr7NRUTq/nG7iNiw9OHF2/KkYV1QT0uv6fI8Mwt6igsdq7AltSjEkPVfD
VIFgnCOhl78As3AXIRfZA/Jt4b53QMR797XF6U3SCOzjDpbZCxVU3om5beZRFjZ1rZA4yV0wPYRh
MYLKmMd9LGp2Av0VDPXWBgZZCPcHc9FDMYcmY0sxUu0YwEwN7XvIYA15hz+K5PGsfUPrDACKNZf7
XUAFLiTuc3dIsMTx0r2pvdZMlAZI4BzLf3jSvSYul/sxVGUB4wLBfVrIF0Slni2m48OmXCMGJKGK
BEwLwEGx8AqvpEZ07vT5Z9Pr5n2pWUPB7i5aoFVFkG9QJ5Fg0pHnmLgHiIMFhWCerGZX1OGoY2bt
eh5jgdVKxgi7Kpo9q7onMTRJ8jK3zfnndQ+hUnOckjnAGV+rS1rxQc2qEofxaxMEkrDOsjezb9Qu
SY0dZs02SppDVf6Iu3JfkSOglnM7xqPwRVeFbzEoQgrS1p3v+4eq9DtWJe+d5wh70vER8BK/CvEv
pyy/3rA7pW78zHLtMY9kBapdI+QhiwuLQElWkzYwr0Qew/xDX3RFYjy3x/jAWetbrUkG1mKD3TqO
rx7BTuu9h/2DHbNQozMO44Ek+pSdfGKg2OpUQ5Wb3Kqv0QSdmL8YfpLZxowY0mrh3MGLCDiTON+u
FKEhJtM7c3GnpTyHop5IuP67XHfX5j/6Z/zcaNnPPloDlGvmNYIeYTQkKyz3aNlv3jvWqsFgNI32
nugGYRuDCy4r7GeFUftKlmrOowWZEvD79j71swwTVeJmMyQ/YQE2CfluOdshUhFPILFPYTG4rfQV
LlV2+XWqSGau+WGz9a65qFC0ALnL1fSyusVdss6HGJTgolpyMVMdcf9pjwCiUJazGQFvV2eYAQ6J
PgaWLP3USWZ1RI68qLbGODszXTghsw+chn6yPhVSeOlKV+LMuM3z8Z7OBZU0npNM599od7+FeDie
fxRVEo/GiKhFkiToDI0JiVbzy/XA8e3dZW1KjtQTVgwjbR9yq7DSKqNlZPqY/BEEWHSO4Mt+ScYi
R3C66qqrJuiHPpiUGS3tWM3NuOw8kBLsvGksm0WG6ZgRvPzvIvqYvQt6SEjugeWjWXd7wQqxlspj
kVzlse+2f+xONtZEOU4+IOKEq66xOD4iimvlZkpQqnv8LWdXBPkcc31oQNH5Vga7+ll9bxaL18ZF
8qppo+BaybUiaPifQ7OgfFLd/FBGPbXg3040sHkTBPpXURSPR9Tw4FhUtOjs3XHEU3cjnngUALHi
YUdcKz1n0+zcf+V7zLP5qjxohEGRJpxcWeGDsRQyR+Jecvs/RJC+tWJnXQQQZHUzYyhLCn5nBxb6
2PpGQ6+BSWtWOunObG5sBfb8t6RVmmw+3s1ZzWdVm4+Yo0DwKqQtUYG15X/jMo6Rdos5ZZZ5qRSQ
d/XnHgJIgfjnNnX3OBWhJcXi2Y+ylE1jNXa1xRdKW3PxHQus3wwqhVZoZxwxcpTxwiNH69P2GL6l
Hf9DEB3JJ8DweYDLpKFIGg37TkWMZFgrrBTCBaLnOK+zeoYdBNucj3PbQkxhJY017VY7TWi5U8sk
oy47Oflhu/JIM1lCe6mihuNqfVlBSNmMYM56a6sTM6KZYjz3z/yKNV74ja4SYXcxEVJ7AQtMqcHm
7a+IkPWUQMdNp5ktRHnIB6cc4Vv2J7J2Dui0gGF1IOkZKW1S6/GT/2IINOV9XIQvYmMcXwN2rXUS
KzFO8MTjank2MBJM2IvhBFqCJ18Q2AlLZHudddPfXzRd6XCeDk4Bm8DlE/jYBcQDmLWYn8N/y6DD
ECT00Pp6Kn8NPXOYvCYFCGX9eRkyfw07T/q+TGF5cDqCsWmxXDer9WeS7oRFMIIWSitunLbBnLd9
sG1FAcI8YY7GhTST/ZQ+ZrwGRmrPklNdY9kpVsA0rh4aypwHye0epSKqP/Fw9GUYPWWojpHvaK3/
qISpD+jjBhbwMSqoBP3Ijq0qG1AATnBnKZSnkrnMLkjpiGarG7slj18FsAV0vdS9Wz0VMtqwPzu5
hx5syoiG2CWMUGopizL+glpp1D5Kp2ywUr51d+V81bT5T0VPl9XNQy5J4S78aU0IQws1QNOx2DJL
ghuJ0nh1vhmNFUUwWtGT8KA6rZSYR2VZB2WHvYpdsTJkADVQuLjRI0UvNJNdM1rb8Sdcnluu7eiV
ScZvEnv/HDpWwT70LbGEAVgxpbB+WHd7EJvYLzJ2c6FvSxhSPWj2Pd6Rx8LF4NV0ACBDjFtOVJBZ
FBFz/eWSwG4QYdy0neoTsUERlc0nGxaogI83ylGW7JHzDlXq+jgEIZxF3AfDNBmEFFeTYRBZeNP7
yYHPe1g9+oey7CmgyJQ1b8FczQLjbfYE9pJllR6o29CYkznKGJITWyTVH1MejNR/k847KcbHo+EK
VreI5OV67g/wHRFR/2QO6cdrvdIzwH7HT3UN3ck5VwnPdKxTzTi5xFAwmwDgUr2GQ8KqM5k7f42Q
SDyxtJBbx//35osZEVDlGDSsypRgH/Kg0SJskkOi+dlmSIHYYbwdcEnFNBGfUuYyX3WEhQwnUIw5
Ss8uDm95fJePqaGyK25nP4k19FZhwVMiqEeQhyfxMsS9JHk0JEm6sMBgVOBWSpW9hoFD0KQDXMBM
ovToeHSdOfJltpPQtm8kKR7RrsLA6bOxMzonKj7wFwfxylnmJBFMqd36Joo8AVezQeaS4hs6g1d0
9xMe9OZ6IqQbDHlNbvKil6cS55P+MxUlcNl1OnOprOzyMkyxr6o6UY8cVe6wyieFWTWnU4ddgwGx
ITKQ8Eh3PD/rrQJVFnLkfk4/UTGrUf0EDiMruMlMV6XuCI8NJeIU7fS5bIsxPSzKjkJ2nez4igHc
QYPEmCXJZmO0aumo6nXalQhKL3J5frfkphWFDUGjzt0Mkd6xkh1P+dKg3Jwz0G5jI9M7SCE25pSD
sd/cYcTEqK2fE+KvpT0bfTkkEoCFUBccvTojEsyUS4R76GCU3bvqugwVb1mrPfIR8SYJZU7ugeTc
FmHzaFUEu4Kr9R8RJOezgGCRRyo6VT+WxpqtPJRtSHVgXjcfSYVxOeIVxEdJBqSuwnDgXqZmmvqu
ZwehLgl4TSvygKgfPOnw8GFY2gTR3v/F4k0arXfSGO0rLAtD2E+e2vDAOt8hdCF65pTiwMrOVmfO
G/uIN4Bh2OOj0DBKgRzpRES2WyfPs0YOVGSYCDj0FdXRoGxbzSkxscWvUlsOhowdlmJ0iUh9FbY3
r6Lab0qwlpUAXlj4a6nDcMz6yoMsHfAMXn1ztm3qaYJXtviOYTAcXKRYh4SZ082wHdHb8D9bhlUO
PwEPf9WG6KAtfe4TA2/CvsRyKRoY8GrbOEagEbWFIw8XSYRJEx91I5Xf/F2Xxsa9gS26pOCepBSp
3Op3MpDbSE6AOSrbQ9SZpmTa6A2vfm5K6/thdKkspAxTAC314Zn6N20W9mjxWRPTu5YXAaJLiumt
5kmTYijFo4PhqzAaWX/kJa+CpQvTvR4wxM8ZbWa1wYQdd+zrPiJvyW6lR0PxbU6rPM3hvgeOlLbh
ifV087TWZ0WWR9ohUGVh/+4nIeahJZnQ6wkBZeEqZAtMke7lUbQpiY4cj/kOIK1kooEK+ZLAKwax
ouAN1HXLNn28TJZyh5awoVbwdHL6LD5xc0MQyrEBT7Y6IDBl0ADNlLcmCkGHgf5G+l0kBS4yw/7l
d2RWwlwt5IYSeORXRHlmjq8ubTnG/5l5egusbATbfJ4j9OXSQ7BEHdzw1fJ4YNU+nvHPB1Lj8VfX
hptzJxfk2J2owzDZhCn/PnGVX6vaRZYRtorAnVaM9xaIhe+HoYt/LLgLxuYfKxDqeAyULxfGgFP+
5MjJKvafKpZgSwbREGvyzsZguuYb4KD8rgJr2SkeRn9o+WVc5Tw/r1/jOre31i1zuKrWr/tZQ+M8
4rnE5BQExaM7ZY3JbQpGDADq5aSju6W6pOwWq0wOnb0KZun4SmNi6LYoZO1rnt1i3wguWef7XJpi
35xEu8j3iprqeGT+4mRzhedajBUW7ff3odR7hIbcA7nCtOwcmfnkkJw/mVjVSCLk55z8TyEKIfjR
Ix9L4ralHXVabTN5KSzwirXhLjJoESH3PzdWX+xF8Ojb7e3xDB1rAqanQQb9Hd5e9TVnalAJtnI9
z7hlEDB0fuKruoHIsyw6vv/WCXmnlxGZf8tV69eENIrwqzxXqPoKSLUftseNVUhcdZE6hYYS2SWF
w6iNp8FNX17U/HgtZfC7RgLh0hmNxrH/HPT+ZWtjCCt93f4FRaMLFLPWcHKN6UOQVp+8pFVC9vYA
L0ec1WrZsfQXlGkt6AELWHgaDslcj8+hJV82JGYerk7inf90Fxz2zkgxBIwyeJlGDDC1ogs4W8V4
S308sOGDD0azbRz11jVjbnFcZ7104OJ6qgC8WzB/B75GPbgs3Og1aclyPql+L8BwWi7XsDO4Pyft
tbQys/IAZ28S1+bOkQ7z2LJGc8W6SXJHlnp2YtdgAhB7Xrfoj8ch00YhChK9mouyboLiIDQxKMca
QEQl9+xomCwho6GsxumMbzbzzCJRyW7K2Z2/fVgIaKxAxjBJNPXTGMaW/hOOIeckHbOZSUo/CLbj
XfK4uNbUlHgQRk2/+pIR7tkCVQKfyMjuegI4Na/yZXz/wBRu+3o3bdAyqNTajI0WD8OZrvk+hYSx
qMWX2LWW3qgyU5PeM7YogO7RDm/MsEzDbQVfpsY6s5HlR9eDbxCJH85YRJ1qt37IUWchfjgTC1Fd
Gewk4acx1bGSMyyvlAkA5tpaTjOuw/ai7Xw1AlF5roGSyMiBHdhT/ZKLjVwlkzN8PjMj6SNaArr/
IDxjOu3+PAYax/6sg7nFLYD82DpwiaEeJApcYho/9fxU6U5rX0cMTA2IK/5tNmuEK2p8FO2SQ0hk
nlXdOlrvdj0INmrSoI+9mjG4EmO3MgOP7ZOXkiYVq1x7tTSnX8CWG+E4YNgwngcqGqLCUaXfjWrW
mx2Ow0mhzm2fTfaXW25cfCa0HDtpgH80lcdrBUzFSsnFrK/OYlVetxGhQQCK0N915ycAXR7h5MD1
Fmyq9Ag+pC1fsHsK6J+bq3C0Taa0dQ/nMbDTR53aIBp4FqkReZjj42C+54LbOAr9UHTGebIAs6Ay
uFTiWj5fGkwc6jmxIF5Dzk9b6elg7uObhm0wqR6Mp6b5rS7GHAyaGyyhhY3Ospjj+65LM5MqaOVl
+BlEjrw2RwniZYZ11f/31BKxlfQIO4W2HQh7b7SMjn40bKsj9UHiSKC8NG2+43cbdgVcOxrC2cmK
lWiHNjKm42gQetvuvWaGmILKhhXV2siS1SRo3gfO05wABdVvunnCSf3HuKP2pR0CT6LC7uOVilPv
DoZPU0+iv3OJti8A60mg3CaCc7gHHaQHu4c8IsmwWOtkUBnWC9usCsRoovBa02fAoFMU9KmZIlvw
eJ+0qAV23F1LjT6KAvJ/w4unNJ4sPZQBlq/MYj3VdathOnqpRpGl2C4E0VKekD3FvweLCgtwpChI
qGP/778USZUPZUPsfRHblms9zne7Dl8pvbwGIVXhwNHpIl5ZwM8/Q6SdbiU20OcYyjvm2vKdtZk5
G2qobHjr7YEhbySnNoR6mbZl8aWK1to5q4J7tLhoogC0lB5kLKQRuSMJbQOx6Akg/LWvWLa/PiTt
WUQuGqppYzfk5j31HeQKqn/iE6d4TJBt8Djpf1lfUS4fVrM01ZQJTzG6BRjW84o6b81dlaUbJqfo
NgsYhZ9V1iYcBfuSVtl1S9qDqobPb8DE53Miz5oDbOr6C4aO7d+25heJdl7pqoDeQoXEnevDupZf
0JDT0cfrv7AwAeamtMp8pSXZsV/BaeVLGfGdAYl082DwQ8SzQJXf9fGvxXGOCuOXA5I6tlIjPOZu
ZBOTbf+lAIVEpuIPQQBlC39QB5Ik9QqKUIR/nKO9c6wgaO8HVzUcDTNm7qXx+qXBaE/yrc5hSx1p
l2yVnGhAOjDCHHDrnP452MV1NC9TvnM8C3XVHLIWYmnS3dNlXRmHor/CrjmEir5UE6pQD4YLCJ1Y
fi+ADyAnpe8T+FzS6jlkXPa4f70vtalDeqplbMN6xKKmVax8HjSpHsgnbbQdMVGTmijisN8KBoC9
Xe6CkDfv3XCZ078n6iIj53LiTjJOiOPwskT9jvRVLrB9pU6rsxOFHkZBuVtjnHdq7LEeaWJmSni1
jW6kLu98p1sf8aKe9AE7wbL0N6TEAZO6SKscGMxW7e7wtyVBnHZB7+nRi8Mlv4NSdiT27XNk4e6k
ElooORa/gqxFgI1QRAyESqD5+shgQ5l7MclGiS9KGyZdlqcgA+t2mdJp/cVrqKhLDYW0DsW2kNJE
w438Q1rUKyTcFGTW6E72f4RxVMFPJa80jR5OvOMhNe+AXsNlR3wZPNZTbF2nSaNQmYwOPHr+LLo8
f7FUXkcs8D6ab0nuKcj8cxWb1h2QtROWQXS0eoO1EYyY7hLzZZuY9ohD/NFUCPjXCORD5KGPeqSV
cwkw/h91c126CLzb1vJeu2oEfULlWAQTxKmTdru8++Up3yQi0aDWkF8jl2hPAFA+cOU7jr4c73ih
QptfT08GPmeZkCw4oIAMxNlqn3iNGhz11msj9YzE5et8rAuJLztYbR88xnoAFpGobHDkWbLIyHcW
ARm121CNcbT7i3ErlP3H4YWvZ1dvQBFpn/rsrL85CE8B+aavhzwcvjYlr/VMOry6HYv+dFIdPe1F
0NunoR4A/1KTi5RallLiucfknM88WyPX+97MmdMNDy2Ade5APbKvqx0wkJdykZFKY89oaeWjI8Vv
U+66OIKgF0I41mFCDU2htp6SlkHzJSV+/inTBjQseXdfTJx4wlKXwOC5y39xZNzZgdQyO+MgWYRD
eUP09yvnf27eg8lKF4YIdBap1bo5gHzafwLO/V/wlPAXqWjytCqqWdWCnTQOg8LMcdwjvG3kA33a
Gwu+Pqv4tYWrB7B439MJnMwmsDu7uu4aLhj/J7Uyfo1zuFbDJvYAROu5p0Mf77Z5d/j0m3kbd1GY
+OQ7PNvXaCq9SgK8J/0kZoo3AXTPGuhSoxxT48/v0y73WBb10YoSGJtec/9gXBUgoVvCpiWkMy17
pQ8V3jwaEM4Soy9xmnzqjrQkn+nM3QV9HOKhv6RLIpM1XKvfc4MXFHhIbJY7+Cm5PrQFXCOzLMS0
PShNnNwV+1Q6Bs6RAFxCV/IeSdWKGwJqOAh4h/BGIsHY+uYcHNfNdywTuMpdiJzee6IYbISARXln
I972gqneGejh3GtYJsjQgoLFZtTHB+MBznRR7xYtvhWMf5BdfPezSdGFhSs6G1rzHabbitcPs7G+
NEIVK9v29UCZv/N0XgYaZ7FXygw8lsBLoMm5vQQ+Z8H139f/phNQFoT0Ad5HVuF7vMBW+G243LhM
A9b6vgoCLFfVAFeZRt3tn2tSovafARBRWYAKOgHFuc544l3txDYrFIMTRwP6nOxFRweVn1Fd8ebS
E0gDc9Hz70FIMWUf6tOqP5VOdDaYlnH5OIv5lkgU+lHZgHMt6oQmIKsmetyFGqtr/GbIh4440EOc
UBaPwTpumMVu+4CwZEyIAzrPkm0EvICg9dnW9BVr7HEbljPzs8vv2LMGj5h2goofANuPOxJRyiCZ
c+y9pYOzevDyezTm+IOIPE4pZnLHNriPCWr7rWEzzr3UXt98vje9daRLF2YnRyeSiLOhE6uSw0Xb
ffbBamKU4sVD8/YdQ7pPo0zx7fUnHoAn8p8eqS3Au+vfZ9K2wJ3ug2AMTzK8ntzPlUWB+eVdKjAk
nMEvDbo3tfNm1nYniZQQMoyot7gWizeEH0i+9FKyjn6N3SzU2yvc3WFJAyt9g3/S56yUCGbsftoF
rmXhcOPgPbCdOcvQF/MbzVYRcBtMdkGk56rzdzLP7Zb5SRtCDrgiPQ6g+EWHe6zWVWTOeHn9Sv0B
26AtaRmODNi08lMSJ+bijbvn4CJaw0gY/FGA1FRBx/LvNkXCyMwiYuY/FdkYG0CdSZ/UM8RaeQbe
CcJiP2BeNDNsZkfu6yUwcurhMxqWiu4gELvJlHRATsg01xauvuzuWXVnZ+3xdAeT+UrqCoA/qQkp
e0TzylfHIP1t9AfWn5WzROZm82Zxw4Q3+s5HSRjaoRMCSAL8OlOHFnOcO7zJrShZmZvRxoLNA2f4
eeqeAcw/odsC35KgAouByj3iaSQbeqEnPm/Agq2TzS6rK4inhJtuMo6nGU+Ik4nSICmpaF0l43/e
1VgHeCYUiMmCSgY0ZHfu9FFohOGvgZq+jZcZbOCTByKzN3yVHxaBVy/W9yqJ/srS6fwAhShlkj3g
RDqbSIx0k7mD0U8MsbH7VgyNdLxjauscEqARwRHKsZJQ33fdG7C2wYXfgTsIugbhELg02FK0V3Rh
KvYZpAF8QP1qysU4OgvDclnz9GUfp/bI3CctS4szgKRPBfSZfqGZAk5f4RxBe6vsS4qUSdQojXP/
HL8x/Xr7UpD6alLK0tKnU97lqVB7RxvieJAOTKeN+JgVOARI3+xC+5P8ScggDCogXAuXB/DFyIkz
HAIY5GHdcvA3idsqdphaTXlxzHMpvw/n2+oyGB4+dj0lDNdC52iDfHohp8xOxpj+nY7tM9pVwi+P
LCcK3FbBYwJRuO4/TxpugPrhrm9lwJy9wOs4RRcpqM/oGQO5HpH9ESU/whVAUfHzpZ2hReSTfJ5V
tIbLdZSwvnxmUAIbvRt/cZNDAgSAa6J65LRNHNRI9DTbvddz//bfylHb1PLfrojGshaJI+Lzi0Fh
t+eSPFhs+PIT38rztzHw8V5FtFNGw5jxQ38Es+f3l2W9POMw/fapcZyHS+OiLrwEQpcQTyYEISgj
W1HIn5d9AlSJr0ytqm67Cj63kftOfbfYAeSX6JZsHT8GPJZWGW4Tro6hho4wnU1kT0acHIE9uDPi
0EZOHGBr7Xg1A+P7cuuOyfa9qGsUWTyTX2Akzs+vP2wlxnoMMXbIzhWmHdthlwJ+BOKN+GeiYJqp
ULXDIUUk+lJtjYseT8Rp4vNWkK3LJDmSOC5xXB6r3qEtHakiAUIM0SDfUDVyBqf1hTqJEqcCTLXc
vln1L50VZLJ5RQqpxT1Nk8Xx18AUieqXwTDRYFOgU5uZ2bTGJ3UmFkMH8waw22LCXD+X8cEUCU8W
cKXPLuIyfb2kryD2lOXe552nRunqDY+4G6kyLHwkJdJNvC5qNjSjG4RGw107bWMlm24QzLeUVFkB
9KJwUSd1TLAEJgS6Q291f5H1FeeMS29V/GQ/N1SHCGUYbLZe67k0zxkZbQFEIcS4SOJvj7UB1PKK
Kq3I0co4L/W26y9u2k099Xnm8q9O+BZ2ba8bODZLlt3/0ucMTF18FqWVXaCz934VnVDl6+N2g4GM
DjMkoVOh66LH3fQi6WYo/elJQdkWk4Ne8XszcLKgI56g8MAee4WsCuIVyj3TzpTONHNYSscsoQO2
INRWFUNv/cbGcQLde2Z4QhQe3puPuP+rWWD+TCPKsZUDWezoWNQ/Clh9jtVD9QS8/t5ULzbgD0L3
fvVt5Em82IaewEJIb2E85OKvn5pvQ3vHZnYcGyjdjnxPWJDhkkThZ+g21Vxd2K1jF6olmeLlC32X
F4IJ9LYOU3wCXtnWhiUMCySsQyPpYq+ZsN4+itIdEdvswK91sHf8yQpur7+2c6y1M+WRi07ez/Yi
leoFZeS/dCZDGAIvvwfSc4cLcnOFBFCrn5/hje6GxC4v0Iasjllejb4zVdNE+hZ8hjj9VeAPjV5i
1seOjClPhTbEgORqQ9LfmfOVApDBn22wYbsv0k1dw9MaytNn+eUyN3UtDNTFUejEopMP7ueWBBoR
NQa49xrCiUP95N7tQpUxwdF4pUdkfvGQt7mzX+j7ZqkuaJ+a+CXOXyLs66X+bg5Nwkl4oPdKGvsq
dCivjm3nP9uvHIbONeQ0J3gQi6AkQoIoGhlOVH2+/+lEyiIkdGQKDM8IeM6JHjuor2Zk0XvMxHy7
neklKWtEM0IoPtp6kGVCMHSyhim55W0gOoxh6InDYipNVIk0QAX/BLp9AwC7e8/BMpUXo69JtoM/
nT7J/N3B+LKQke+BsrI9V6mFl2D+gtZn2zZPp6reSp8PB+FLWGELHUjTq60HwzTTCUq0BFFLttNJ
WKzh+cF2udqcTy2+T+Zqk7PXCXN4pYhSFM9ETCG2pucFJ1U0fkrTuoiNyr05AyCjPtFKwCsCrBBl
oY5Lraqv1jIcS7Vw2Exevn2KdQAdm5GiQBHFTFBmGPFjY9NBEKPZ7NRbhE2UbL9ToejOtwvV+4xh
FB6TIJQf7GE/yF66Cpk25/SWbRrAv5OpY0zo6LEq45lQDXjedmh0A4eNmJSSiJKWdUAqRLRqKyXp
96m4HpMcwvILdLO9R+8OLa6s1laAoZdOXvXRai0F5q3Ra6KyxZBm0UDreAL7+RDKZlD24NFKNzIE
bVnpwTUXxH+4n9rB8uvydNl8kcB2x84GAFv17/uqMRPAzr/Lf+OqEa1xTkq7qnbjFf8UmQMHIZBg
U5LmxsakDvUy4Sep+IcyzQ+a2M+Jc3Xi33aShOI4X2nUaoxgLExYOlFvmEFI8EwT3vfUUwR+J/lC
To/pVfFWGJYu9HriHV/309/ZeV8+dSuYa7LCnJ37O4ggln24Z5nZVQ0VVzpbOjcEoD7Mo2pWoMWP
mBbeLyTNHgEf/d7+3sz6XbhEAQh36OClcqo0zPDMv/+lOiP/0i5LUjcilVjsCe4YzE32pvgXFl9g
eVeV+z68Hlm5Fd5f5doc4Tp/67tJfIfR3n7lTuPmtd+zhUIy075yTgG+wewk97E5oU2pcPiBr411
1EYArZBRUoAWitKrlCJEZNCSg7RgO2oaoyjc8kQK6w8aqj+K6S/XuZ+nyyCwhw/X/JWIBVuR4Zu+
xMZDBHSVISx7sP8X4C1ZUofRdX8bXd/pwP0kwztssv3DuiTfptsgxURmUEOViFdz662CvREh7C9c
gxtAPfcFuhyyBPn9kcJxD1TaeUL3xDBOq04jicIGmKw9lqNY4szjOfZ2doClrt2M1zJBTxQ3ov4V
ZmlQnXQRpb9uOtkwT96E3xwsi0zXHbm5qyDldc1XjjVqLn01xuHgbWB2XTzASKUBz2hUsodFdo9a
j8YTeg==
`protect end_protected
| bsd-2-clause |
ambikeshwar1991/nghdl | Example/2-bit-inverter/inverter.vhdl | 1 | 257 | library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port ( i: in std_logic_vector(1 downto 0);
o: out std_logic_vector(1 downto 0));
end inverter;
architecture inverter_beh of inverter is
begin
o <= not i;
end architecture;
| bsd-2-clause |
armandas/FPGalaxy | explosion.vhd | 2 | 3788 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity explosion is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
destruction: in std_logic;
origin_x, origin_y: std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(2 downto 0)
);
end explosion;
architecture behaviour of explosion is
-- frame size (32x32 px)
constant SIZE: integer := 32;
-- colour masks
constant RED: std_logic_vector := "100";
constant YELLOW: std_logic_vector := "110";
-- for delay of 100ms
constant DELAY: integer := 2000000;
signal counter, counter_next: std_logic_vector(20 downto 0);
type states is (idle, state1, state2, state3);
signal state, state_next: states;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal explosion_rgb, explosion_mask: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
state <= idle;
counter <= (others => '0');
elsif falling_edge(clk) then
state <= state_next;
counter <= counter_next;
end if;
end process;
animation: process(state, counter, destruction)
begin
state_next <= state;
counter_next <= counter;
case state is
when idle =>
counter_next <= (others => '0');
if destruction = '1' then
state_next <= state1;
end if;
when state1 =>
if counter = DELAY - 1 then
counter_next <= (others => '0');
state_next <= state2;
else
counter_next <= counter + 1;
end if;
when state2 =>
if counter = DELAY - 1 then
counter_next <= (others => '0');
state_next <= state3;
else
counter_next <= counter + 1;
end if;
when state3 =>
if counter = DELAY - 1 then
counter_next <= (others => '0');
state_next <= idle;
else
counter_next <= counter + 1;
end if;
end case;
end process;
output_enable <= '1' when (state /= idle and
px_x >= origin_x and
px_x < origin_x + SIZE and
px_y >= origin_y and
px_y < origin_y + SIZE) else
'0';
explosion_mask <= explosion_rgb when state = state1 and
-- only allow reg through
explosion_rgb(1) = '0' else
explosion_rgb when state = state2 and
-- allow red and yellow through
explosion_rgb(0) = '0' else
-- allow all colours through
explosion_rgb when state = state3 else
(others => '0');
rgb_pixel <= explosion_mask when output_enable = '1' else (others => '0');
row_address <= px_y(4 downto 0) - origin_y(4 downto 0);
col_address <= px_x(4 downto 0) - origin_x(4 downto 0);
addr <= row_address & col_address;
explosion:
entity work.explosion_rom(content)
port map(addr => addr, data => explosion_rgb);
end behaviour; | bsd-2-clause |
ambikeshwar1991/nghdl | src/ghdlserver/Utility_Package.vhdl | 2 | 7046 | -- author: Madhav P. Desai
library ieee;
use ieee.std_logic_1164.all;
package Utility_Package is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant c_word_length : integer := 32;
constant c_vhpi_max_string_length : integer := 1024;
-----------------------------------------------------------------------------
-- types
-----------------------------------------------------------------------------
subtype VhpiString is string(1 to c_vhpi_max_string_length);
-----------------------------------------------------------------------------
-- utility functions
-----------------------------------------------------------------------------
function Minimum(x,y: integer) return integer; -- returns minimum
function Pack_String_To_Vhpi_String(x: string) return VhpiString; -- converts x to null terminated string
function Pack_SLV_To_Vhpi_String(x: std_logic_vector) return VhpiString; -- converts slv x to null terminated string
function Unpack_String(x: VhpiString; lgth: integer) return std_logic_vector; -- convert null term string to slv
function To_Std_Logic(x: VhpiString) return std_logic; -- string to sl
function To_String(x: std_logic) return VhpiString; -- string to sl
function Convert_To_String(val : natural) return STRING; -- convert val to string.
function Convert_SLV_To_String(val : std_logic_vector) return STRING; -- convert val to string.
function To_Hex_Char (constant val: std_logic_vector) return character;
function Convert_SLV_To_Hex_String(val : std_logic_vector) return STRING; -- convert val to string.
end package Utility_Package;
package body Utility_Package is
-----------------------------------------------------------------------------
-- utility functions
-----------------------------------------------------------------------------
function Minimum(x,y: integer) return integer is
begin
if( x < y) then return x; else return y; end if;
end Minimum;
function Ceiling(x,y: integer) return integer is
variable ret_var : integer;
begin
assert x /= 0 report "divide by zero in ceiling function" severity failure;
ret_var := x/y;
if(ret_var*y < x) then ret_var := ret_var + 1; end if;
return(ret_var);
end Ceiling;
function Pack_String_To_Vhpi_String(x: string) return VhpiString is
alias lx: string(1 to x'length) is x;
variable strlen: integer;
variable ret_var : VhpiString;
begin
strlen := Minimum(c_vhpi_max_string_length-1,x'length);
for I in 1 to strlen loop
ret_var(I) := lx(I);
end loop;
ret_var(strlen+1) := nul;
return(ret_var);
end Pack_String_To_Vhpi_String;
function Pack_SLV_To_Vhpi_String(x: std_logic_vector) return VhpiString is
alias lx : std_logic_vector(1 to x'length) is x;
variable strlen: integer;
variable ret_var : VhpiString;
begin
strlen := Minimum(c_vhpi_max_string_length-1,x'length);
for I in 1 to strlen loop
if(lx(I) = '1') then
ret_var(I) := '1';
else
ret_var(I) := '0';
end if;
end loop;
ret_var(strlen+1) := nul;
return(ret_var);
end Pack_SLV_To_Vhpi_String;
function Unpack_String(x: VhpiString; lgth: integer) return std_logic_vector is
variable ret_var : std_logic_vector(1 to lgth);
variable strlen: integer;
begin
strlen := Minimum(c_vhpi_max_string_length-1,lgth);
for I in 1 to strlen loop
if(x(I) = '1') then
ret_var(I) := '1';
else
ret_var(I) := '0';
end if;
end loop;
return(ret_var);
end Unpack_String;
function To_Std_Logic(x: VhpiString) return std_logic is
variable s: std_logic_vector(0 downto 0);
begin
s := Unpack_String(x,1);
return(s(0));
end To_Std_Logic;
function To_String(x: std_logic) return VhpiString is
variable s: std_logic_vector(0 downto 0);
begin
s(0) := x;
return(Pack_SLV_To_Vhpi_String(s));
end To_String;
-- Thanks to: D. Calvet calvet@hep.saclay.cea.fr
function Convert_To_String(val : NATURAL) return STRING is
variable result : STRING(10 downto 1) := (others => '0'); -- smallest natural, longest string
variable pos : NATURAL := 1;
variable tmp, digit : NATURAL;
begin
tmp := val;
loop
digit := abs(tmp MOD 10);
tmp := tmp / 10;
result(pos) := character'val(character'pos('0') + digit);
pos := pos + 1;
exit when tmp = 0;
end loop;
return result((pos-1) downto 1);
end Convert_To_String;
function Convert_SLV_To_String(val : std_logic_vector) return STRING is
alias lval: std_logic_vector(1 to val'length) is val;
variable ret_var: string( 1 to lval'length);
begin
for I in lval'range loop
if(lval(I) = '1') then
ret_var(I) := '1';
elsif (lval(I) = '0') then
ret_var(I) := '0';
else
ret_var(I) := 'X';
end if;
end loop;
return(ret_var);
end Convert_SLV_To_String;
function To_Hex_Char (constant val: std_logic_vector) return character is
alias lval: std_logic_vector(1 to val'length) is val;
variable tvar : std_logic_vector(1 to 4);
variable ret_val : character;
begin
if(lval'length >= 4) then
tvar := lval(1 to 4);
else
tvar := (others => '0');
tvar(1 to lval'length) := lval;
end if;
case tvar is
when "0000" => ret_val := '0';
when "0001" => ret_val := '1';
when "0010" => ret_val := '2';
when "0011" => ret_val := '3';
when "0100" => ret_val := '4';
when "0101" => ret_val := '5';
when "0110" => ret_val := '6';
when "0111" => ret_val := '7';
when "1000" => ret_val := '8';
when "1001" => ret_val := '9';
when "1010" => ret_val := 'a';
when "1011" => ret_val := 'b';
when "1100" => ret_val := 'c';
when "1101" => ret_val := 'd';
when "1110" => ret_val := 'e';
when "1111" => ret_val := 'f';
when others => ret_val := 'f';
end case;
return(ret_val);
end To_Hex_Char;
function Convert_SLV_To_Hex_String(val : std_logic_vector) return STRING is
alias lval: std_logic_vector(val'length downto 1) is val;
variable ret_var: string( 1 to Ceiling(lval'length,4));
variable hstr : std_logic_vector(4 downto 1);
variable I : integer;
begin
I := 0;
while I < (lval'length/4) loop
hstr := lval(4*(I+1) downto (4*I)+1);
ret_var(ret_var'length - I) := To_Hex_Char(hstr);
I := (I + 1);
end loop; -- I
hstr := (others => '0');
if(ret_var'length > (lval'length/4)) then
hstr((lval'length-((lval'length/4)*4)) downto 1) := lval(lval'length downto (4*(lval'length/4))+1);
ret_var(1) := To_Hex_Char(hstr);
end if;
return(ret_var);
end Convert_SLV_To_Hex_String;
end Utility_Package;
| bsd-2-clause |
armandas/FPGalaxy | destruction_sound_rom.vhd | 2 | 1204 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity explosion_sound is
generic(
ADDR_WIDTH: integer := 5
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(8 downto 0)
);
end explosion_sound;
architecture content of explosion_sound is
type tune is array(0 to 2 ** ADDR_WIDTH - 1)
of std_logic_vector(8 downto 0);
constant TEST: tune :=
(
"001001001",
"010001001",
"001001001",
"010001001",
"001001010",
"010001010",
"001001010",
"010001010",
"001001011",
"010001011",
"001001011",
"010001011",
"001001100",
"010001100",
"001001100",
"010001100",
"001001101",
"010001101",
"001001101",
"010001101",
"001001110",
"010001110",
"001001110",
"010001110",
"001001111",
"010001111",
"001001111",
"010001111",
"001001111",
"000000000",
"000000000",
"000000000"
);
begin
data <= TEST(conv_integer(addr));
end content;
| bsd-2-clause |
grafi-tt/Maizul | src/Unit/ALU.vhd | 1 | 3369 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity ALU is
port (
clk : in std_logic;
code : in std_logic_vector(3 downto 0);
tagD : in tag_t;
valA : in value_t;
valB : in value_t;
emitTag : out tag_t := (others => '0');
emitVal : out value_t);
end ALU;
architecture twoproc of ALU is
signal c : std_logic_vector(3 downto 0) := "0000";
signal s : value_t := (others => '0');
signal t : value_t := (others => '0');
function boolean_value(b : boolean) return value_t;
function boolean_value(b : boolean) return value_t is
constant z31 : std_logic_vector(31 downto 1) := (others => '0');
begin
if b then
return z31 & '1';
else
return z31 & '0';
end if;
end boolean_value;
begin
sequential : process(clk)
begin
if rising_edge(clk) then
c <= code;
emitTag <= tagD;
s <= valA;
t <= valB;
end if;
end process;
combinatorial : process(c, s, t)
variable d_add, d_sub, d_xor, d_and, d_or, d_sll, d_srl, d_sra, d_cat, d_mul : value_t;
variable d_eq, d_lt, d_feq, d_flt : boolean;
variable tmp_lt, tmp_z_s, tmp_z_t : boolean;
begin
d_add := std_logic_vector(unsigned(s) + unsigned(t));
d_sub := std_logic_vector(unsigned(s) - unsigned(t));
tmp_lt := unsigned(s(30 downto 0)) < unsigned(t(30 downto 0));
tmp_z_s := unsigned(s(30 downto 0)) = 0;
tmp_z_t := unsigned(t(30 downto 0)) = 0;
d_eq := s = t;
d_lt := (s(31) = '1' and t(31) = '0') or (s(31) = t(31) and tmp_lt);
d_and := s and t;
d_xor := s xor t;
d_or := s or t;
d_sll := std_logic_vector(shift_left(unsigned(s), to_integer(unsigned(t(4 downto 0)))));
d_srl := std_logic_vector(shift_right(unsigned(s), to_integer(unsigned(t(4 downto 0)))));
d_sra := std_logic_vector(shift_right(signed(s), to_integer(unsigned(t(4 downto 0)))));
d_cat := t(15 downto 0) & s(15 downto 0);
d_mul := value_t((unsigned(s(15 downto 0)) * unsigned(t(15 downto 0))));
d_feq := d_eq or (tmp_z_s and tmp_z_t);
d_flt := not d_feq and
( (s(31) = '1' and t(31) = '0') or
(s(31) = '0' and t(31) = '0' and tmp_lt) or
(s(31) = '1' and t(31) = '1' and not tmp_lt));
case c is
when "0000" => emitVal <= d_add;
when "0001" => emitVal <= d_sub;
when "0010" => emitVal <= boolean_value(d_eq);
when "0011" => emitVal <= boolean_value(d_lt);
when "0100" => emitVal <= d_and;
when "0101" => emitVal <= d_or;
when "0110" => emitVal <= d_xor;
when "0111" => emitVal <= d_sll;
when "1000" => emitVal <= d_srl;
when "1001" => emitVal <= d_sra;
when "1010" => emitVal <= d_cat;
when "1011" => emitVal <= d_mul;
when "1100" => emitVal <= s;
when "1101" => assert(false); emitVal <= s;
when "1110" => emitVal <= boolean_value(d_feq);
when "1111" => emitVal <= boolean_value(d_flt);
when others => assert false;
end case;
end process;
end twoproc;
| bsd-2-clause |
grafi-tt/Maizul | src/Unit/Branch.vhd | 1 | 2343 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity Branch is
port (
clk : in std_logic;
d : in branch_in_t;
q : out branch_out_t := (
emit_tag => (others => '0'),
emit_link => (others => '0'),
emit_target => (others => '0')));
end Branch;
architecture twoproc of Branch is
signal c : std_logic_vector(2 downto 0) := "000";
signal a : value_t := (others => '0');
signal b : value_t := (others => '0');
signal target : blkram_addr := (others => '0');
signal link : blkram_addr := (others => '0');
begin
sequential : process(clk)
begin
if rising_edge(clk) then
c <= d.code; -- eliminating redundant bit
a <= d.val_a;
b <= d.val_b;
q.emit_tag <= d.tag_l;
q.emit_link <= d.val_l;
target <= d.val_t;
link <= d.val_l;
end if;
end process;
combinatorial : process(c, a, b, target, link)
variable ieq, ilt, feq, flt : boolean;
variable tmp_lt, tmp_z_a, tmp_z_b : boolean;
variable result : boolean;
constant z31 : std_logic_vector(30 downto 0) := (others => '0');
begin
tmp_lt := unsigned(a(30 downto 0)) < unsigned(b(30 downto 0));
tmp_z_a := a(30 downto 0) = z31;
tmp_z_b := b(30 downto 0) = z31;
ieq := a = b;
ilt := (a(31) = '1' and b(31) = '0') or
((a(31) = b(31)) and tmp_lt);
feq := ieq or (tmp_z_a and tmp_z_b);
flt := (a(31) = '1' and b(31) = '0') or
(a(31) = '0' and b(31) = '0' and tmp_lt) or
(a(31) = '1' and b(31) = '1' and not tmp_lt);
case c is
when "000" => result := ieq;
when "001" => result := not ieq;
when "010" => result := ilt;
when "011" => result := not ilt and not ieq;
when "100" => result := feq;
when "101" => result := not feq;
when "110" => result := flt and not feq;
when "111" => result := not flt and not feq;
when others => assert false;
end case;
if result then
q.emit_target <= target;
else
q.emit_target <= link;
end if;
end process;
end twoproc;
| bsd-2-clause |
grafi-tt/Maizul | src/Top.vhd | 1 | 5527 | library ieee;
library unisim;
use ieee.std_logic_1164.all;
use unisim.vcomponents.all;
use work.types.all;
entity Top is
port (
-- Clock
MCLK1 : in std_logic;
XRST : in std_logic;
-- RS-232C
RS_RX : in std_logic;
RS_TX : out std_logic;
-- SRAM
ZCLKMA : out std_logic_vector(1 downto 0);
ZD : inout std_logic_vector(31 downto 0);
ZA : out std_logic_vector(19 downto 0);
XWA : out std_logic;
XE1 : out std_logic;
E2A : out std_logic;
XE3 : out std_logic;
XGA : out std_logic;
XZCKE : out std_logic;
ADVA : out std_logic;
XLBO : out std_logic;
ZZA : out std_logic;
XFT : out std_logic;
XZBE : out std_logic_vector(3 downto 0));
end Top;
architecture structural of Top is
component DCM1
port(
CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end component;
component U232CRecv is
generic (
-- 9600bps
-- wTime : std_logic_vector(15 downto 0) := x"1B17"
-- 115200bps, 66MHz (perfectly works)
-- wTime : std_logic_vector(15 downto 0) := x"0255"
-- 115200bps, 72MHz
-- wTime : std_logic_vector(15 downto 0) := x"028b"
-- 115200bps, 84MHz
-- wTime : std_logic_vector(15 downto 0) := x"02f7"
-- 115200bps, 99MHz
-- wTime : std_logic_vector(15 downto 0) := x"037f"
-- 115200bps, 99MHz
wTime : std_logic_vector(15 downto 0) := x"03e3"
);
port (
clk : in std_logic;
ok : in std_logic;
rx_pin : in std_logic;
data : out std_logic_vector (7 downto 0);
recf : out std_logic);
end component;
component U232CSend is
generic (
-- 9600bps
-- wTime : std_logic_vector(15 downto 0) := x"1ADB"
-- 115200bps, 66MHz (perfectly works)
-- wTime : std_logic_vector(15 downto 0) := x"0240"
-- 115200bps, 72MHz
-- wTime : std_logic_vector(15 downto 0) := x"0274"
-- 115200bps, 84MHz
-- wTime : std_logic_vector(15 downto 0) := x"02dd"
-- 115200bps, 99MHz
-- wTime : std_logic_vector(15 downto 0) := x"0360"
-- 115200bps, 110MHz
wTime : std_logic_vector(15 downto 0) := x"03c0"
);
port (
clk : in std_logic;
go : in std_logic;
data : in std_logic_vector (7 downto 0);
tx_pin : out std_logic;
sent : out std_logic);
end component;
component SRAM is
port (
clk : in std_logic;
load : in boolean;
addr : in std_logic_vector(19 downto 0);
data : inout std_logic_vector(31 downto 0);
clkPin1 : out std_logic;
clkPin2 : out std_logic;
xStorePin : out std_logic;
xMaskPin : out std_logic_vector(3 downto 0);
addrPin : out std_logic_vector(19 downto 0);
dataPin : inout std_logic_vector(31 downto 0);
xEnablePin1 : out std_logic;
enablePin2 : out std_logic;
xEnablePin3 : out std_logic;
xOutEnablePin : out std_logic;
xClkEnablePin : out std_logic;
advancePin : out std_logic;
xLinearOrderPin : out std_logic;
sleepPin : out std_logic;
xFlowThruPin : out std_logic);
end component;
component DataPath is
port (
clk : in std_logic;
u232c_in : out u232c_in_t;
u232c_out : in u232c_out_t;
sramLoad : out boolean;
sramAddr : out sram_addr;
sramData : inout value_t);
end component;
signal clkfx, clk0, iclk : std_logic;
signal u232c_in : u232c_in_t;
signal u232c_out : u232c_out_t;
signal load : boolean;
signal addr : sram_addr := (others => '0');
signal dataLine : value_t;
begin
dcm_map : DCM1 port map (
CLKIN_IN => MCLK1,
RST_IN => not XRST,
CLKFX_OUT => clkfx,
CLKIN_IBUFG_OUT => iclk,
CLK0_OUT => clk0);
u232c_recv_map : U232CRecv port map (
clk => clkfx,
ok => u232c_in.ok,
data => u232c_out.recv_data,
rx_pin => RS_RX,
recf => u232c_out.recf);
u232c_send_map : U232CSend port map (
clk => clkfx,
go => u232c_in.go,
data => u232c_in.send_data,
tx_pin => RS_TX,
sent => u232c_out.sent);
sram_map : SRAM port map (
clk => clkfx,
load => load,
addr => std_logic_vector(addr),
data => dataLine,
clkPin1 => ZCLKMA(0),
clkPin2 => ZCLKMA(1),
xStorePin => XWA,
xMaskPin => XZBE,
addrPin => ZA,
dataPin => ZD,
xEnablePin1 => XE1,
enablePin2 => E2A,
xEnablePin3 => XE3,
xOutEnablePin => XGA,
xClkEnablePin => XZCKE,
advancePin => ADVA,
xLinearOrderPin => XLBO,
sleepPin => ZZA,
xFlowThruPin => XFT);
data_path_map : DataPath port map (
clk => clkfx,
u232c_in => u232c_in,
u232c_out => u232c_out,
sramLoad => load,
sramAddr => addr,
sramData => dataLine);
end structural;
| bsd-2-clause |
grafi-tt/Maizul | fpu-misc/original/fadd-grafi/fadd/u232c_send.vhd | 1 | 1225 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232C_SEND is
generic (
WTIME : std_logic_vector(15 downto 0) := x"1ADB");
port (
CLK : in std_logic;
GO : in std_logic;
DATA : in std_logic_vector (7 downto 0);
TX : out std_logic;
SENT : out std_logic);
end U232C_SEND;
architecture blackbox of U232C_SEND is
signal countdown : std_logic_vector(15 downto 0) := WTIME;
signal sendbuf : std_logic_vector(8 downto 0) := (others => '1');
signal state : integer range 0 to 10 := 10;
signal sig_sent : std_logic := '1';
begin
SENT <= sig_sent;
TX <= sendbuf(0);
statemachine : process(CLK)
begin
if rising_edge(CLK) then
case state is
when 10 =>
if GO = '1' then
sendbuf <= DATA&"0";
sig_sent <= '0';
countdown <= WTIME;
state <= state-1;
end if;
when 0 =>
if countdown = 0 then
sig_sent <= '1';
state <= 10;
else
countdown <= countdown-1;
end if;
when others =>
if countdown = 0 then
sendbuf <= "1"&sendbuf(8 downto 1);
countdown <= WTIME;
state <= state-1;
else
countdown <= countdown-1;
end if;
end case;
end if;
end process;
end blackbox;
| bsd-2-clause |
armandas/VHDL-School | 7Seg/sseg_mux.vhd | 1 | 1213 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sseg_mux is
port(
clk, reset: in std_logic;
in0, in1, in2, in3: in std_logic_vector(7 downto 0);
en: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector(7 downto 0)
);
end sseg_mux;
architecture mux_arch of sseg_mux is
constant N: integer := 10;
signal q, q_next: std_logic_vector(N - 1 downto 0);
signal sel: std_logic_vector(1 downto 0);
begin
q_next <= q + 1;
process(clk, reset)
begin
if (reset = '1') then
q <= (others => '0');
elsif (clk'event and clk = '0') then
q <= q_next;
end if;
end process;
sel <= q(N - 1 downto N - 2);
process(sel, in0, in1, in2, in3)
begin
case sel is
when "00" =>
en <= "1110";
sseg <= in0;
when "01" =>
en <= "1101";
sseg <= in1;
when "10" =>
en <= "1011";
sseg <= in2;
when others =>
en <= "0111";
sseg <= in3;
end case;
end process;
end mux_arch;
| bsd-2-clause |
szanni/aeshw | aes-core/sbox_inv.vhd | 1 | 2229 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sbox_inv is
port (
d_in : in std_logic_vector(7 downto 0);
d_out : out std_logic_vector(7 downto 0)
);
end sbox_inv;
architecture behavioral of sbox_inv is
type sbox_lut is array(0 to 255) of std_logic_vector(7 downto 0);
constant lut : sbox_lut := (
x"52", x"09", x"6A", x"D5", x"30", x"36", x"A5", x"38", x"BF", x"40", x"A3", x"9E", x"81", x"F3", x"D7", x"FB",
x"7C", x"E3", x"39", x"82", x"9B", x"2F", x"FF", x"87", x"34", x"8E", x"43", x"44", x"C4", x"DE", x"E9", x"CB",
x"54", x"7B", x"94", x"32", x"A6", x"C2", x"23", x"3D", x"EE", x"4C", x"95", x"0B", x"42", x"FA", x"C3", x"4E",
x"08", x"2E", x"A1", x"66", x"28", x"D9", x"24", x"B2", x"76", x"5B", x"A2", x"49", x"6D", x"8B", x"D1", x"25",
x"72", x"F8", x"F6", x"64", x"86", x"68", x"98", x"16", x"D4", x"A4", x"5C", x"CC", x"5D", x"65", x"B6", x"92",
x"6C", x"70", x"48", x"50", x"FD", x"ED", x"B9", x"DA", x"5E", x"15", x"46", x"57", x"A7", x"8D", x"9D", x"84",
x"90", x"D8", x"AB", x"00", x"8C", x"BC", x"D3", x"0A", x"F7", x"E4", x"58", x"05", x"B8", x"B3", x"45", x"06",
x"D0", x"2C", x"1E", x"8F", x"CA", x"3F", x"0F", x"02", x"C1", x"AF", x"BD", x"03", x"01", x"13", x"8A", x"6B",
x"3A", x"91", x"11", x"41", x"4F", x"67", x"DC", x"EA", x"97", x"F2", x"CF", x"CE", x"F0", x"B4", x"E6", x"73",
x"96", x"AC", x"74", x"22", x"E7", x"AD", x"35", x"85", x"E2", x"F9", x"37", x"E8", x"1C", x"75", x"DF", x"6E",
x"47", x"F1", x"1A", x"71", x"1D", x"29", x"C5", x"89", x"6F", x"B7", x"62", x"0E", x"AA", x"18", x"BE", x"1B",
x"FC", x"56", x"3E", x"4B", x"C6", x"D2", x"79", x"20", x"9A", x"DB", x"C0", x"FE", x"78", x"CD", x"5A", x"F4",
x"1F", x"DD", x"A8", x"33", x"88", x"07", x"C7", x"31", x"B1", x"12", x"10", x"59", x"27", x"80", x"EC", x"5F",
x"60", x"51", x"7F", x"A9", x"19", x"B5", x"4A", x"0D", x"2D", x"E5", x"7A", x"9F", x"93", x"C9", x"9C", x"EF",
x"A0", x"E0", x"3B", x"4D", x"AE", x"2A", x"F5", x"B0", x"C8", x"EB", x"BB", x"3C", x"83", x"53", x"99", x"61",
x"17", x"2B", x"04", x"7E", x"BA", x"77", x"D6", x"26", x"E1", x"69", x"14", x"63", x"55", x"21", x"0C", x"7D"
);
begin
d_out <= lut(conv_integer(d_in(7 downto 0)));
end behavioral;
| bsd-2-clause |
codepainters/vhdl-utils | i2c_slave.vhd | 1 | 11677 | ----------------------------------------------------------------------------------
-- Copyright (c) 2015, Przemyslaw Wegrzyn <pwegrzyn@codepainters.com>
-- This file is distributed under the Modified BSD License.
--
-- This module implements a simple I2C bus slave interface.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity i2c_slave is
generic (
-- address on the I2C bus
address: std_logic_vector(6 downto 0)
);
port (
-- should be ~10 times the I2C bitrate or more, all activity is performed
-- on the rising edge od this clock signal
clk : in std_logic;
-- I2C bidirectional pins (should be connected directly to FPGA pins,
-- allowing fot the synthesis tool to infer proper 3-state buffers)
scl : inout std_logic;
sda : inout std_logic;
-- user interface below. Note rd/wr naming is from the master perspective,
-- so wr_ is for master->slave writes, and rd_ is for slave->master reads.
-- The wr_data_valid goes high each time a new byte is received (available
-- on wr_data). It is held high until receiving side acknowledges by putting
-- wr_data_ack high for one clock cycle.
wr_data : out std_logic_vector (7 downto 0);
wr_data_valid : out std_logic;
wr_data_ack : in std_logic;
-- The rd_data_req goes high whenever there's a byte about to be transmitted
-- to the master. It stays high until user puts the data on rd_data and sets
-- rd_data_valid high for one clock cycle.
rd_data : in std_logic_vector (7 downto 0);
rd_data_req : out std_logic;
rd_data_valid : in std_logic
);
end i2c_slave;
architecture behavioral of i2c_slave is
signal scl_in : std_logic;
signal scl_pull : std_logic := '0';
signal sda_in : std_logic;
signal sda_pull : std_logic := '0';
-- deglitcher shift registers
signal scl_sreg : std_logic_vector(2 downto 0) := (others => '1');
signal sda_sreg : std_logic_vector(2 downto 0) := (others => '1');
-- reclocked and deglitched SCL/SDA inputs
signal scl_in_clean : std_logic := '1';
signal sda_in_clean : std_logic := '1';
-- previous states
signal scl_in_prev : std_logic;
signal sda_in_prev : std_logic;
-- helper signals - start/stop/edge conditions
signal start_condition : boolean;
signal stop_condition : boolean;
signal rising_clk_edge : boolean;
signal falling_clk_edge : boolean;
-- FSM states
type fsm_state_t is (s_idle, s_addr, s_addr_ack,
s_read_ws, s_read, s_read_ack,
s_write, s_write_ws, s_write_ack);
signal fsm_state : fsm_state_t := s_idle;
-- input shift register
signal rx_sreg : std_logic_vector(7 downto 0);
-- TODO: convert to SREG once we have FSM fully working
-- count of rx/tx bits
signal bit_counter : integer;
-- TODO: check if it is better to latch SDA on raising or falling SCL edge
begin
-- concurrent statements for the bidirectional pins
scl_in <= scl;
scl <= '0' when scl_pull = '1' else 'Z';
sda_in <= sda;
sda <= '0' when sda_pull = '1' else 'Z';
-- deglitching / reclocking (because I2C inputs are not aligned to CLK)
i2c_deglitch: process(clk) is
begin
if rising_edge(clk) then
-- shift SCL/SDA into MSB of the shift registers
scl_sreg <= to_X01(scl_in) & scl_sreg(scl_sreg'high downto 1);
sda_sreg <= to_X01(sda_in) & sda_sreg(sda_sreg'high downto 1);
if scl_sreg = (scl_sreg'range => '1') then
scl_in_clean <= '1';
elsif scl_sreg = (scl_sreg'range => '0') then
scl_in_clean <= '0';
end if;
if sda_sreg = (sda_sreg'range => '1') then
sda_in_clean <= '1';
elsif sda_sreg = (sda_sreg'range => '0') then
sda_in_clean <= '0';
end if;
scl_in_prev <= scl_in_clean;
sda_in_prev <= sda_in_clean;
end if;
end process;
-- start/stop conditions
start_condition <= scl_in_prev = '1' and scl_in_clean = '1' and
sda_in_prev = '1' and sda_in_clean = '0';
stop_condition <= scl_in_prev = '1' and scl_in_clean = '1' and
sda_in_prev = '0' and sda_in_clean = '1';
rising_clk_edge <= scl_in_prev = '0' and scl_in_clean = '1';
falling_clk_edge <= scl_in_prev = '1' and scl_in_clean = '0';
-- main I2C slave FSM
i2c_fsm: process(clk) is
begin
if rising_edge(clk) then
case fsm_state is
when s_idle =>
-- detect start condition
if start_condition then
rx_sreg <= (others => '0');
bit_counter <= 8;
fsm_state <= s_addr;
end if;
when s_addr =>
if stop_condition then
-- stop condition during the address phase - go back to idle
fsm_state <= s_idle;
elsif start_condition then
-- start condition means sync error, treat it as a (re)start
-- of a new transaction
rx_sreg <= (others => '0');
bit_counter <= 8;
fsm_state <= s_addr;
elsif rising_clk_edge then
-- shift in next bit on each rising SCL edge
rx_sreg <= rx_sreg(6 downto 0) & sda_in_clean;
bit_counter <= bit_counter - 1;
elsif falling_clk_edge then
-- note: it's a signal, so we "see" previous state
-- if all 8 bits are clocked in, is it addressed to us?
if bit_counter = 0 then
if rx_sreg(7 downto 1) = address then
fsm_state <= s_addr_ack;
else
fsm_state <= s_idle;
end if;
end if;
end if;
when s_addr_ack =>
-- note: sda_pull is set high in this state by concurrent statement
-- we only wait for the clock pulse
if falling_clk_edge then
if rx_sreg(0) = '1' then
fsm_state <= s_read_ws;
scl_pull <= '1';
rd_data_req <= '1';
else
fsm_state <= s_write;
bit_counter <= 8;
end if;
rx_sreg <= (0 => '1', others => '0');
end if;
-- read states
when s_read_ws =>
-- in this state we pull SCL down and wait for the user to provide
-- a byte to send, then we go to s_read. Note: because we pull SCL
-- down, start/stop conditions can't occur.
if rd_data_valid = '1' then
-- latch the data
rd_data_req <= '0';
rx_sreg <= rd_data;
fsm_state <= s_read;
scl_pull <= '0';
bit_counter <= 8;
end if;
when s_read =>
-- there's a byte to send to master,
if stop_condition then
fsm_state <= s_idle;
elsif start_condition then
-- start condition means sync error, treat it as a (re)start
-- of a new transaction
rx_sreg <= (others => '0');
bit_counter <= 8;
fsm_state <= s_addr;
elsif falling_clk_edge then
-- was it the last bit?
if bit_counter = 0 then
-- yes, go wait for master's ACK
fsm_state <= s_read_ack;
else
-- nope, continue
bit_counter <= bit_counter - 1;
rx_sreg <= rx_sreg(6 downto 0) & '0';
end if;
end if;
when s_read_ack =>
-- all bits shifted out, here we wait for falling edge to
-- check if master ACKs the byte
if stop_condition then
fsm_state <= s_idle;
elsif start_condition then
-- start condition means sync error, treat it as a (re)start
-- of a new transaction
rx_sreg <= (others => '0');
bit_counter <= 8;
fsm_state <= s_addr;
elsif falling_clk_edge then
if sda_in_clean = '1' then
-- byte acked, fetch the next one
fsm_state <= s_read_ws;
scl_pull <= '1';
rd_data_req <= '1';
else
-- shortcut - go idle before the stop condition
fsm_state <= s_idle;
end if;
end if;
-- write states
when s_write =>
-- TODO: star/stop conditions
if falling_clk_edge then
-- last bit ?
if bit_counter = 0 then
-- yes, push it out
fsm_state <= s_write_ws;
scl_pull <= '1';
wr_data_valid <= '1';
else
-- nope, continue
bit_counter <= bit_counter - 1;
rx_sreg <= rx_sreg(6 downto 0) & sda_in_clean;
end if;
end if;
when s_write_ws =>
-- waiting for user to pick the byte received
if wr_data_ack = '1' then
scl_pull <= '0';
wr_data_valid <= '0';
fsm_state <= s_write_ack;
end if;
when s_write_ack =>
-- this simple implementation always ACKs writes (SDA is always high here)
if falling_clk_edge then
-- once ACK'ed, wait for next byte (or stop condition)
fsm_state <= s_write;
end if;
end case;
end if;
end process;
-- SDA output is mux'ed based on fsm_state
sda_pull <= '1' when fsm_state = s_addr_ack
else not rx_sreg(7) when fsm_state = s_read
else '0';
end behavioral;
| bsd-2-clause |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/logic_builtin.vhd | 19 | 30579 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QA13xX+R/ACi8km79qumYiCoL95/JTNXmw/Mv/Sollu1nSewLnwk6qQvytLuy2zqP8g5ZHUfDkXy
dYJVTyRzKA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
nii8tC6PWRY1wcl+Yj+dJQmorGaa82N6txtyUcQdtmyxn18ohe6n/SpcWdMXBCN1HiV+XVlZhDEw
KvXEmx5H6nBr5/f6eVRIc3k7vZjXpluRFM7lDsLgIpfE0fW00UnX/0rMYgmxn+5+4dG7smGpX72S
zm4Z5q7tYiBa+z76ex0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
yppU6wpcO6vEUEaOZTTT6jS7XbaY+e5Jeh6nknICBRlkmT5DzQmd7eWK0ShMWSlNt0Fv0kuxSdt3
PRQVKoJayZoHlh1UH0U//6ySDV8PrR8ZKYbnb5G7lC3+6hAsVS0WEHoXFsxe3QTXWezPX8OXISSE
YYTVzXqeBUtBDqueK1cvQyMM7IWnXgyQ/0dRh7UmnEpiOonlQALl1eEnWSxVZ0L5cd+jDbcSlWqj
VgoBh9A+IbjGjOjE8FOaFLUMzvKXmpjNiGzhwyN1qXczrRlE54AWkRUECVVEGR4zuEA7VTQH6H/B
e1HQhNsFNtK03nDJRyhoiacaeHGOBo4yneyZRQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xoEHrB3Q0Yfcf3MYYTBHkrbmS0WN00JVFDeAhGuvxPP5kv5812Q+oIM0e+z8RwGLEwQ4F0j3UPw9
LR04YDkbyd4XfjRJQED6GhUyhlVHkeZ0vYn6D/hB6y5zA45LPFz5aqbLudigfR6lDZgyof50XSaT
wkqaJ1dNbsbYXDGYiiI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
SZoZou8zrLQYkyuoYxGz7q7TKCLXDf41gJHR/eNOYbjhVAUcJLojwHpmGq29Knnj056DtiEpAnUR
HkNwqIIUQ/PzBp2ZRgLcYUhgAGFauW9u5fA3Qe79SJmVAKU55R6eP+5h6YaMx1oo7Myp8ZHgv9LK
0atkww+rNUFhc/kS4ivaypKADJgY/Slv1X55We59ldg5OMI3+jFcKD4Ow4Gbs5tHnIUzKQ507yjR
1wg0oIoTMEm7GhN3wZnee1A7XeomsW7IrTE+3/M1cRWhdrj0rq5nqrI9yilbmzqQyqntfJK6N8Y0
QQNZFJ8oCjr3X+2kFBb+Pd3/scpZe1PtOU8TgQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20896)
`protect data_block
nLAzd6tD/6N1xeuFIPhzEQzyt6Ku1YDjA3mlpYOLPC0m/bRyjQbNmJtiEmofL/CbUL8pX7SL8mgi
QBU+0zdta42eIxLDUURKTtWe8dppPr3HZo8r4f/C8TLsQf4RD7QV0GouBiPeFQIjr4/M01WWilf7
Tyn6RtjtffHFNDLNvddK19bmaK8R6piu/Kpz8jCVCVAPEQNZYXP1C+7k+M+4c+4u2U3t+GW9C7T1
01EStW+6qVi14dc7EfHKv0wT34zWlhn9yX6JRVtXbQMqhvn8LrjCnz9Zbp48RZzMN4BkowfOcphR
RSpZVzg2AvuBFcD0zlZlEMUy8w3MlwIca/c9wjZYXLFno6QyfCgjsnzkEir2HqtaYW29G5SttkS3
6mRqGqK9YVlcWmfoqfMmcWzu1KwrUHzWmRlxkt4EIqGWS7K9VRzGYB3LQUtIlNnd4cvXrnxIVFvp
mx1o0V/bn4w3Ulle+qg/n392U9QP2jzLL2eN7i7JOvx6jCGIt2ea42sjxS4Y0FHRT7djl4I+F1Is
u16Ybxq7aHpKG1dwcwHxK26FDjNUt3UQ/hJJ1co6AKRyhq45aMd9Cno8dJbnntQrP5xKoB0gubRE
9lHoDlFzIUc7Tfrzo3zvgYHZ+XfUExSBZY+BFS55OOYr9fvcX1XnSVrzMtzfb1GFvU1Tm+CnuWJr
7Dh/ZgnwY9t5yWpsB/hRX8o94mOuemehcdi648bIY4rGqPImAFjDKsVtsT6fGJ9RLEUnW57WzT9g
LhzFC8YnRYcOYtmNxWraKA1v7M7oPmQuXvmVRAsHj9JrgS+WO+x5tmBlDfMtSQmJnZqyw9/ZPdHM
p8Og+6BUyg6jqao6Pu1xCvu7A6BZGqClbiYWfucsRJm8v5ex1ViQtsvnwP7s77Gnz8KhfE5NsLtE
gf3G2DNW9Nv7QgnCmyS0Sj8CJ1Qam8UNIzUvcMnjcmwTFMS1+MuM9pX51vJsOFyd7R6GfNwbrJI9
WsY9BSVaSunki9wuvGw8zHFxAYybVZ4Pgk/cxrNynsQVVN64+X88woztR7cNRRR38XPbvbXEciHm
ckcYHN63dqcAq/D3ecYZ97I78W2Q3LHd6H5LHlbiTKHbLmXP/3Pbc1iqsn3XlFxLRDDGq8eUlw03
MPeo6iyQaDxq97ui9McNr8SlKlWTDgZI3ANV1LXlQimIZB2gVsXF3uyi49OgPYo1SV7Tp7ZHdh1s
HYQS6vLEBaPLoiPsWr5MYcmPsGz0ADZta7/JdC/jvurFPVeQ5BYoEB5KL3FPCQ9PKLxkoyOgfnpB
zrsHV5Ydxo4S/4lPhLyApq8zXwzMNYffr2FiPmk9UFFU3wd64uw1ockXJHHQDVj+8A2x/3W2PyMx
Fb8YIdgr0KyzHe30NyPL3OUU2kPSrZpJFEcapuNh8pMP/v88fhRRcoelCgGhSDvAXRyfm30isazd
nigZR+63l7ExudTIdSYpF4KVLrD5ven8HEH6UgJwjpyaPb+TntOPa6ZvW9E8Y+efKLi0Bz4qcjUZ
a7cKKL25/Yt2ASpIRUa/OgfjWqODkfVDaC0S7CODedFwXEtB+l93q7ZDEgDrp/jHLhaey4rtD9J3
Pd60FSRUtxsMDijt9zPUaHAWCGFK+clFQB3r/iISFZyxblkBIN5jNt1JDPAdwaJ4Oq81taBFUJ7I
dFcWaLRdUm0+VCoHZZ4nzCz+pVd3SyOrXfXwV8VnTIK+qSZjuHluk+Y4YwtmUQPt+FJ9Bb3M6Bs/
pb+prl4R/TmaDG8kJROOxG+F04NXFo2r/Uv7oM1vpJmDEuoi1vDNe4BEOO9vbIPgTRRHP2wv6VqO
volj7ihPfIncX774QC8BIWGzQxgtA4/cJ09ybFXTsbswmEUFVrm+jzfK50Af86vD71HIMyUsosro
nTkf2qp3g4yS0INZOFCaXmUyUjINorfaVntOt3r6egsNNoLNNkMyZieESgG9U29AOHeTg0r7+seQ
7aKUEIZEq7W7MOUEIPvy2NQmXDskpz2sqt8ADb8v5WKn5JpMqGIY3N8d6LgMUAInyejzD+7HTHsd
EmenQ6utwaewitziz/pmEQJK4ViDmMpdISdotQj+l7saL+8dTBmxaeEJ6ebiesxrkJUPEuWnb5/D
/h8m2Mzuc/U1/VDbO6rwxdo7ZB+MAikLhl/UW0FesCcDRJMj71nSR4q34to5idMFICGxXOvlERqx
Cm+BPasUpQzr8ZF2wopCZlYpAYguSrqUonT/qjKQbPduUahOS15T9I4hrv+rZPmfiLg35Z6aIvuB
M3z9XgTZ3+vaRJiBR9ROriDhx8mIDGo7xMIX1q0rT26R+VB3Io+9mfnM2/sHYiYeoejsap4SihD/
7lCkb1EgiuJe+Lrq3DyGz34Gq+ileYeSjhBVY5Y6xpT9sRpJ4NkaeQJVuY/LWA+5iXHDCcXb5l3/
kAGEKnA/4o+MbOBbbRfqm/WTFoyCYe9dOH8t4yo1LWShnGlN7hwKfOK7Ss8y+6AcD2k4wg5ejjGM
+VPUHyVGPGEZfScrg7C4UbVQSdFzX0ztN/whCqZX29VLnZWJtXXy75QkrDCfcaPHCtkWXMLncl6v
8G9WpceODmO1SpuyTDBTaH3fzzrbfhSvQCdqD3DRtvb2FM5+UsCQhkNo79mjEWLgyn3/xhb7uX/L
eIiGiakFk4/EHG5JkPuqNeDFAUgZ6NaS1P9E7T2TJr8trSaVnSg3Q5TUVFHGpBaspwMOl+3l5Xhr
4KLV5FUS4ruhsTsK5mwkqWcpXk8YaBhGummWPAaNxRrPcJMt/CW3MgYSxUEWAAwkCUD5ZL6EZnAb
VGG+z38z0ENSWtkojT5+A/czpwHhv2PdLGxdU6SwpWwQ9rUwSjVgbpaw6Q86avNBOZltTnp407dF
w7AY6aw9o3gaKCOktzmCB8xBVb+Mt5drkgN6mg9JpJzLYEyK7ULKjfnNKHgGXtX7cw/LikAO6MKG
6bD31uCieHbz+ealZhRvJNqkzKNGR20RQJ34CVnKXRrLimYAyr8bc5nejUd9v4u8WZSI7A3ljd2C
YJlOyH2o3JJGvXuQA5/wKG221s2RV3RmR5090MawiVx4LUw3I1dOYaaagqbEt9y89kAGRiRGu8p6
HZp+chpKxbEgVzlfe6VmSzS1PN0M5rOJ6ihk3WFjviJKdy0wR3Vd1qj/J/h9pB0jTGqg6aAJqBc7
2Y1qR4g+7hgOh7LJtV+x5yFg8matX8/uVNQuCtIGU7d9reFIAbrxI0iZFts5P23pqwy5aZzoFD3R
vj1MN1soDoAFfHB1f+4n32oEHTPa21P/IHxYGTmTKOh2VHA0wIMZ+NSAUtJWH/JwjsJPRzjIB7c6
o5+6TGw8K7+Kf1xOkCC968HDuTGHvOcMHzIJ5YPmJr1khUqq5cxsMWyGJ6b+Z1CjAybJpkBTl1UJ
xWuU3qC+hzAbon5yefuxbr0pkiRkKAjWZ0/dGLnMIw6wXv3ElS9zuZyH0GrTzUpnKgutTWFW1ipj
vivHHsL8A4AOxLzL4v0WSpyTNk6DYKu6QgCWeNNS2+XbDIT7WQXpzcF9R1ngKoDFrbTJ4y3aJASj
IaVWUYzQenRCLThylTaTji8d08gVO/KAaaK0ncg+jh63mydh6SVlVv6yMSzbdAE3MvVBWW4E3gM+
Nb2Xh/t2/Gg72kUNDsFv54nQQG/KPTfwfGo77zk4HQlmIVdzj0Pj5iENiP2IMD/79aeRfVgXNEF8
bNFFec2+VsdZjXPiBKlUG1vL4XSY+uRbDAX1BRBKzBbBEILryA4oj8GIyHulAoYysZnCGMLVlC2c
R6SbYFHrBByG53X3zSzjcMsCSw+QXDGSzcIfi7OYBendlylhV9nFpDtJNblHU3WQahkz6rB1QbVj
0PkPJ//Pdwz3O6/XokwPHL+tZMmAM7PrOcQqYnnVCKqRpicXscbNS8PBzSM9obuVu5fC8luTTnNO
gJm5fG1CJcf+oylv97tOIX1N0ZISvHikdeaOkPKSjirzRbkeNVR5Ulb59v8HG50Kb8um2W1X7aNk
WC8YOrd1np6rKF/DBx54VINmbMWFeCWqqPjVv6fFgkB/+h5Bs53Uhn/uclhzIqoCmhX7isHYJmN/
PmLx3FpGtty7eCxm1kI/8tjGl/+//C/avj9RQxel9nbFGcVIu2RsSshiPpfWOqjFv/XeeRZLpNWE
2QVrRZ38N6qcj9DKPhUYkxFb/oiU6pnHKwWrXHT7hFj+q1jFtaTSV86PoVAJzMBB94LUWjRngOTV
sR3Cm+jGoAzb27S3yh7Js0B0zqUNaZlV9qkwIdnpt7mmAh5VtOoAfe/w8R2yZS6ae7clUTJ4mTQ0
IurauXHG8Re6QWUt0efzkMjXyyVhNsPWpvKeHplX1xJDleuI/xXsL375QPnr/pXfGIpMpLZNeArC
WrEdbdWvfCG8AdH7G61bf1wm+Q+vYpXpb9GxPRzplaAJuQrRQUiNAJPGT27DNMtdtNvcC6+dC+w1
N7+iMLYIfWfvQBYOkot5PsL6l5j9IYdy2d8IpsKiE1mT0dhSoSX32BXpIuYmDZ78T/5m+S3g/PRH
zmMV6mYNgDCLjyYndF41eTqqzBVqEAXa6cmT5JaIonQTaLxzT+k6zdbvdnBkkr1uIviXKnc0THew
gjxfiibkHUYhz8UzKrNqr+mLDfGn/qcg4+y3vT9lX037kU/G9G/uxiKJtaPWYaMrxN1/+etoqE6Y
H9g8JYnP5NWBxF1LntWqDhU5qYJmlLIYWLT1TjzGRPVZznuEdxxUndoAB+KAUzpNBgOIpXgSJVVW
T2csPCRgcvnNlfrXcwdo4S9fl8LVouTt1Z0y8xQNp+FrQKahey84h9HS6LomG7fwi3NL4kDxvYq3
PEKzYbXLCL57bzjKso99wBl9PuUW+uSwOvorNr3/34YdDrHRlXLNNhh+yg0p7NVsGH+5mcqbgS6Y
IdCXQXMpEkKZfIOzCF6GNZp66vhNPsh/+myQYrjUceZA2TUNFgdaIf4GwzIml2akN5n9YicV9XQH
0ughtoH6BnKxqtKSHKCe+CXea+pIeNgo/YWJlbqzibZaawkIE3kFEl0rkpIr1IYouHJNSGPb4vcN
BI0kbV+RLGHq15HoWvyrJSxgUjkHJp5qdcPK+2V9Km7Qh/HW+Ae4nrjf9f4O7sSz1vW1XmXfpq92
PiZaQLr4WOEPHpIcT8heSL5BILm+jS1f074zmN7ZQMA+FRIDJLbdKDwaM5fvlD/eQfIjXQYwdcEL
IW3syGnMSoy1fp6wO1OUAP5E87aCK54c04Z43tfU97Aiypst+Dds2SN+mVHEb4LzFxDKC5rZURdW
a/n+Ay/lMR6WrzBET341hG43HB2cVYJkQyYSPCxjWTduFb3mJ5KiPBfJBQfBBvIWUb5SGLQ4BCpq
CbXDNIcifKy2nW68jSuc/0Ea2IIhTpYgWRvnvcA4ckS/nprsb3YWpZYa0xUZBUoJVRgb3DKDZqH4
QB6zre9fMxXTWApwRX5FjcKi+50ax317TbHhzyiCMvOEVEJPqJJjbGA+9a2fQpMuAtMGHrD7vxhJ
GWDZq9D24YDrGU7RJXHrLRJK3bYj0Qqyl7atFQXpo7/S1C7bLCvd5PNn8jZ90UU1ojvc9dEuvKOF
SPMEIaE/X2t+7JrhtZNwEbygH17f4vAFASS3O4M+KiszKkSpmvSm9neMEbI3P8gjd+euNW+qKSwH
0s3on2PBtUPOLfWb03Owa41A7wy9bIqXE074i875M3D8bBujeTbKQvJvLooIGpzN+khx6Ap8P5Ti
s8JvjQ4Fu/hmNOjL+bhWmjNemLKbRmjV7bXdjpb8Cb7EeEl9IsU6olCiF1Wj7EMjyD+XTFB6oOPv
j+e/Z/BbnPFqeNq4iyCyTn214y/LhTPBW9t60eR3mvo2xrC00ekwBzv/RPmihpp8h+iRbaMy30ci
QSRTQiFRJZEuq8ExZnJg6K0Bk24co4fXcLwNhapLvJKtRWGgimt7Tg2/uFBwj1oo9pNCQQkC5UL6
DQHk1JJy/Pr/0QZ0S6X/v1XXLrPM365wb+J4qHruEswgDXWBmb8BJo/lZPKJdMR7pHZ7Y8tfMEAL
tt50yNasIlZPJFmYXTBDeKOmUVeXKE2SB6R8/9Z+IHquP32lYTwnXFMJMnUdzSROvVlOO+kMoNVv
ivNQhZdgpfHL0AnkSC7NV6Zj/2JtsUW9eH0PDglPVEfCuAEAvQPVJBxoprxFF0FLXwvbgSxvoV4d
bNdUnZ82hGfM9SaMcIjKPZKHbmbiUAsVf4ar/ptmcp0V4Z/J5itQX1yXwrmFE1csQWDssfC1NLV8
yG8GGcuYkpUTeG+iYZQ6q4UbAJYE3FA56l1JvoSnnJaK5FBJ+9EFRFvGJUavYX/BDJxL10PNrm6m
FfcwAh2F0if+IlvhZ4ssP3pLl+ZlwddhsKRH0ucXjSxh5dYLq400Z9pYZMjMVPP3FWH4ionBZxX5
Xutz7jdSB3cnMz4toJ0wi/hRj7yq/oeVE08WuxheSHNQffEtVtokBiAZfxWPD3FopjtCYFQgchjS
/+VDp0Oi+D6vdl5kd4H5+WYK0Uom+h2RE0T66qGykUaRENsObKyMYMs2GgJ8FxCwhyivcP2w7muV
9EwuZepO893GjvUy5gWRicIaRaJQrJLgpjaoar9c1V3DyEbVkHQuvxYf0Te3ozeIoh6ECiMAL1lX
bPJrvMnPSzMPCFR1DE7gBJvpNp0sI5JXcJBrclErWoZkOjOwbiyBPQpsDktityEhq9U/28xqeY18
cu7D/bvQ0I3dcPE+bQfB3M5INtofEPIJuHQ0X46y94uNiQk5Takcd7JAA2Vv0ldQ0KcKXSBkRckS
wVWdoAiuQPsx7wP8NfSy4j0pivctOVlWZ+2AYGXT9Rsx3Ic10sRcOOz54wX9b7UOg2SEGafT/FA2
xfiyWrQ50ax+VAIaXfSZtJMyAkFCRbWinr8NSenQRSHlAcB06x6vx9qXy1tpoRCbAfewVS4o1ZwS
fw7ZbNnWiJJkTvjetjEsXYuvM6BBLyJncz7vkykuBTNBz04+6/Ct7+eea6yhNk+pIDoxeXC07YML
d6P3y1mVRmzbQkDHp2aiajraJiJA9+SVVUdFRxCcCb9BGsrjSr1fndxRo4LjJ5WAnZ80cR5w0Ct1
21uK3n7o1xKek8hxqCPig46EcnPWfB1pn7GRJyLBLir55SCVal5nK3/dJLk3u1It942Kdle94prL
U2bAHWYO4tb5Igqulx+do5PA7ds/BwjBc5ywyZqxRehBmh69wyR2KTQ2qXo8nfN9VxnUdSr0tjwf
86JGX42xahy1iGtn8RCK53ow6AVFaUb4CYta/1yW90fz2+F9PDV7HsfCUJiReOFCuthMNJPq0THS
Gr5LyMgeCB2n4d8LdYOv3fyMCDtcCngQqpmWxYtb/HEo4HwY7yQgM/x0NZ0MBD03+789ZYxbyIIa
UyvPHje0uXVUuCSDwRGmrQv5xiJycZ+bTY3PEXWTyBI2XW67gzZiox3clSAUCzRx6D5pnc8tjGc4
K9OIE7Wyk4Mq62AMxQXCXyM1CbbaXZe2u1yQdEnO0JZvU0mnhbXaHJ7iqcFF7XAHhDVSLLy6XT7m
ADZolAZFXI2K8qfGUS0KGaPPoj3XiTMAt7sMuNU53objSw473mJGgY/FKSExJaerVsCTcuVjUG7H
VYo3gui1FCvIIxiAoElOF1L+nosDgFx7aqhFATNI1IebUuJzBswFBjJBKKwRvOW8uOheLOZPKIot
WBYBSRL44iWJxK+mQ0GaIwtfrqwjvbNzPl93GzUB5QBYPHSfjw/UFqj7qpJaSgG82LI5DRJvlcxy
4B4Kdc1dvZICt5ucxxyntdl2MnRiHWEVFPz1TUAOiUJ1l1xyopAX06/Iwy/ZXuR9bOXMvmvETOPF
wSwQnFPN/9C3EwQVcsdwe6nBuvX9ih/LdsB87RrJK03rchw4TzBGThip41UOWn/xX+EVh3GlnDQi
Q4qa4/7V7tEhymIHFZhhkDpydu/cP0yvAZeSP1Xjq1A58jNOrU6igYQc2GK5zYaR6P6F7pS/4/44
S5FjK11K8GW4/85h5dHbrEQRAPkK2QdMLPrmd7nQgaVX3p6/C9w4J4//b7ey/kXFF77JHJJszW0i
zm3GnozNFwxPeuTD2yxlTpZVopGYruicFywGuDG6uCUujkul+JEIBnNP1Aq+PPGqeXtR17XLYIVQ
U9dNTXceC1gZDcHdmQxbOAO9YwVWU1rARKnnUylb5DZneWOAjVyFL/piV4BkZ0HzQ68vWUxhHhI8
44qDeHUzW9naJmaTloNfbgk+laeFcGhWrbwVgCsAuDNKw6M/1zsgDP2+FcWzhmJOzMl9hbDv594/
smhxackiFuCtc0lAvv/UF8d0itMjc26y6gnKOLAxke4DnEje1UeqMRCW+NoquLCUuPJxuKZGWhrY
hBwRDtOSDRAtlkpnvP4JtQkNt3zYn4L55I5jsWXC7lKwpmtowLKtO88w125VzyBhrpojDmI0dP97
iHviMMhpYqT17+oIRSKp4JLbmNg/xlRlQqmQLErEysCL5og7fgnA1+pKtRSS09AK8e40F6sMWmM+
asFyZ2hekc9MlJYXKTo85qqKxjyqKHpdYCKWPgm0IKWJLC6oP25PHwB8Ih0zkHD2+6T4YTxL9xFO
I8pkW6y0+rLaIIMmBVCvdcxYpWwp4nPLQ4KsYksxTA/nuVa74TGCS6GZpRTouqHnTfI2mCdBOPhI
hCgm2wxRjfB1/GKQGg52JvtvVuFhxcllXImtjuq5/8YuuiW6lvcRJiKIoxERp3YiJewOOdraPoJ7
KwHqhNIrgKtOKoV4zM8FLJiejDCioO0/YLLTwAUuT3lfIxBWeLzJsQI4PEJQaCHkdBRirr3XwoZy
7n/7hYhDdUxSOJ/Jiw06yMvQf7ulfRG6Rw9Xg7E83medIEllnds/K2zR+AEpGK6cKMOIUn9GL5Ql
hBTpAa6uuAHup9r/zDLML+mMD1Dr7CvkGqcXObEDXBnAXQHw38Y1AvHRSD10JsBuU5XDu0S/BQ6E
XVXuscSYbrSj7DYOnjlJ0l7wUbFs7Gr2rvMQXBu6Hmhzd9+vjaCDL3s2skWl92NDsfvgB07IoTjF
TtX8dNo4vQF9Pa8M7zBxKklqCYLN7lgJk++3wWuXgYejzNPiEtE1kF/mwnSj+Ja236fZqtB4ZaA9
OUSVOeqQBuIG1v3xXjNuL5nETkMPF8UiMJUEkN/C2yaCPQ1wkMVtDHJamfDGdsN4hDOIeMjNFtyK
dHfoQ72G7guQnmPcZDnCzcMvWG/EcP63MMnjV3BQJsrd58MtDSU7DUHUyQPk6Fch7GjWQNLa3ojR
UBKi1PSgiIEy9GV1JrQmNuco3NltSMEe/roaOmnLASWETGJ42/XeVYBXwP8Ld3HI5gRRqYXU1fmD
cY3v0e2x0+3hYn19VJQcYLsls+B+W23xwI51tovIx/1Wt49sFLe+5wwucVrl3RFV5pI6mETfYZaf
yqW1uRz6brKg3ZUzpwSCcLHZP513smHySlbYJ+99c6bZ6pt5mv07r8LJPBws5Vh6nSZGZ3xMoOGB
V5v3JaVq1LWJq1LpGA7z6KCcapZ8Mt25+Eh7V7guzQ9VGfMgk+d7ACSC4BUKMAlWOtrxultX+3Is
h0zvahE7sZiD+YCkuwiocTbqNBd7FHIH8pVkUbh/kqSH8SFmewvSJWJsDkxqUcEfdqQw4ebSxS8s
gsZjbNY4D1tqSXlrPK9LAGEzBNJuH4JrgO/LYH8txfyYw4VBu9/UFvqOXVBukykhyCrD08sQXgJM
4feAi5ZYX5whfycVMe7MV7iSVFTJJDRDz/KCtJv7c7QOSlwOJ89SJG3oIEqB2qowcQXD5dzEcLIs
oMECtDHu8lTGO1ZbCOTlBKSOQERFx/84rm4MzRpMdExBQIY9bXC5nb+m5+LbimCuOoz5JKjB6+iU
53GE+4gKZObGMoSg7o/ROhelsmhRjBCXt0qtDCGYXMLAXhU8xtPiwuJM5UVLFuaQhLnIhYHKnK66
dEVJr7brjdM78V3wjQU2QVAOq+fZUVCG8lYm+Z1Ts1qvlt9fwNCcEBsYu+2iOZib7DBfXlmSbH/P
Ij7SqBNnRB3c55Q/LmUrBLDP2HGHqNyLdNNMPktbTd1n4mxmtBDzN/9Thm13BiDM8fnA+kwLZaOt
pA9yaDW0iwb5VcvWOqWgXbYCnIC7ypoPBUY1de1s3oGEX2wMVBZbovKzAOU70PkGBJjBVc1QFU4Q
VV0Js0sAAIV+y3uTLm5jBgJkqFNC0R6qxkiaOBjJKJqlhKHqWgeXtSOLsHk+aWg49Pt3ebVoDuv0
F7nBPDYf2lCQnVPXe5UMtfDYBS7P5aWccg5/dQUMvmCXEh4xVUg10VxbBWOMABaZtWaJBU+vgYTp
IwYcErUKyBUA0g1PMqQKBma97Hfr9Jifc0R6sFsTmlH6LyKVvsb/s6og5MTO2HtgMMUHWS5Wltx8
7ZYY+s/LZoQrcvcEvow9v2wh/iD/V+zjOQViWdmpx2ZKxKNDkje2IQO545J7XINyZFNKJdoZnPl4
rK0OdB07O9BjPYU4ooJprpOFyg+YDAsMi5KKArIvu734UUfdCt3Tx48ArR/TrW9CVg8ZO7c9a65X
MsJOeXGdI8p4MgWK2YjArnzM8+jZAYlNHSDIcXT+O1HiXIAmm+/W6EdL0uvrGuLENtwIhPTybOK3
39WqE2foxGthsaA7wZqDmA/FurKwr8PJ3o2Tg4IiVPuyyzksLW4lA/cp4dJiz7VFeWJWyLGkQskU
dbm9+zpiaIRzpvtnI8/CRGJstIPYdxIXqnr3hAKD5hr9GgGqfvmcUeBvmBAsz6FKm+RK6+mZKOAM
6b+AzllJu2I78ZHoUxm9DgbSt5L53eB0gfzR4sAgfLwoBl5nBoNBNkgm5xSPm3kvZdY1pDlC9FiG
sfY1XR4QH+nv+29tUEx2JxEAwZCIL7l9p4tUGibiidk3lJZWnbYDpytyLspGacTF49TKylucFj6T
FlUuUTaIX64IvnSeAQhpHSwJRwYEep9nrLZ1/ok2GVjHBxyrqJcbdVxhIQ143RH18nLPmzcyzfVD
YSxEL8wR2ykG7FC1aCJF6/Cs/ztlTnacb8ur8L/fak6kei6f60Fnkd1G0NfyqdkQIxR70y5KM1Hk
mPcZtIb0cfRcZ6eJV5IWN9Ap4yUFLzO1rOJcg5wdk3t9ZmufqHIAXDhEtV5cXU6mTTW9v+X8c1fK
tE8/SUzDzN4RRGCSN4JP2xMTg/jf0fmlugCeRnCSW4gUd/Gvo0SBQW8CLcqZr3/tMamADKrBg1rr
lS5YWhrDntOrIvE+oyZnI9zPDupzhfh1NaeGQaTcyJIAkwRFTmb02A46vWJtrHlfyEQQ5MgfaQIr
AGUiPHB15Y1NDiX8cUzYWg5m99YL3pjyuMOzXv4O4p8csMhCA3iBNYQlQZ59OgXBuGR93iwnAMAo
4W4Kzyi6UOLyhZ9muaSn0qmB/Hz7aWTDoTxxwtmi5oCe97kBKFi820Kooc0HmILnkxlQR99/lr+4
8SYp7Zu5VW6JdLJvebuNurzVsLMBg3yo+YAbsNnlZZzQfEN/NfmglH5FXcu38yfBevzq9m4qCPEG
VVV5sndGRX4AySwISpsO63gL49cwgzbEM/BuL/lrUAKK/2xN1mAy5fOBhi3M7gOQfG4556Odl1jq
0LnJJptC0OIHIrhQwmjRKMM/3uVXinOSqBJjbYMXdS/sgS1EhT34RHnugn3XHDdBNe8fjYM2hfjG
XHlAo/YVaExdjy0kjwIymFDfbe89REFJkEWtur04VqWa4tMomIm+O/81vQiEU4aWY8/7ROKEBOB5
eEPEzH4YoWGhHFd3Z/268kkfbvFvaP4zX8i9+mw7W53ZOTBgSmlucBDacuwBlQfX9s4kTwzg0gPa
5U8egwW/RS8EGogas9GXBf95y6/hM3GsQ55tQRimrsMmfcQS6SyN4frYBJWHZyEjPLYraMfiIGPu
4R+pbEuihHkdKDOPz0lCIfXX1NJiLFsnpj3mu6du2OAyRGnoyhVsS2nal0q3OVqSG/zKQ4poXMR8
HtogboN0K7DKcLYeTBWViST95SXaIf2f6PilwlG9/sdGvDJnnfwcXk04Ziz8U6xCqi7EBoNCcujw
ohuScBM0WOfoZcoQSqqwxrx7pwLsW3ijLhEnGYtpJCMTrtclrWkpiy8vmkOuvFV46r7iqdOWmL+T
qxm8bm/vvZpMtmhVpsmVwqUUgqyUiAUP0ZFIz/e+CffjhQIMFefnX6vTlQrRASw4x0wXL02dUJKv
ojSXn7DTEvwzubqVQMzaMNKkb0m/M2e7ehJL8DwVTUev0Dow8mQmY3tAFyixcuIcNx6cskJnyp6o
q5mzTTjDXBhYub3iwP241C32XqsfRn+F47KIM0LW0FGnEEhxoJfKC/x5HxBteFm+5eaHO5AxQFr3
l0tLNAG3pOs5dvZkg96RLqKT/nad/DwPiZRry9d/ecWIrnN17j2COQoPmCBWNnbZcqknVzgn9kx0
+es66q/31FY/YOI4llXqpRHB5HxnBDrgL/iWTe8Qqjq404lxTI8DH8t93cQ3uOrFMkdPLZ1U8j+J
pjLz1hB0HBpUSE5fpy+UBI/O5dEgHdCgWgGQ63XDNx8kW8Fx3K9DXKnIOl5ohzNfOE0dQlmIDTdV
Vcgvs2j2Us/Lexd+JtUTHHQSEJrhkebruYi+yV/g3J0AY9v0RiBkPxhQ1d+n4aOFpNmxO5U4DONK
1K8L7b9YRPCbfVhTXiQ/BICrIRMl/5iFsIjW4YxSQeeDhl6xfmp6I9SiZ6oJK6FHAFXplMOOXslB
glbcHPR+N4HvZaokA0SfzE4ODyfHr//J+ar0LOvJEm8/Wl69YCIlHziRMChCMLudOn0DSpK5oUgU
kMdMfzOVXtXXffQx7D8FxVzQ29hsUaiaGiqS75E8KvFoYvghT2n82JSFVyv0JgVhPshSmVTMMTJa
IuCtHVsQJRpNQ7fdy7mSBkaf7AgBGYboVv1fudJSgYB7g6oHVQ0GaQ6vJOHYJyaiuR9iG1C9t1hR
94PKXuW9KL5Nnt9/18LeEeuIY+zRIRtvzbYStpEncaUqYjKer0EtLZaQBYBtGtab2NM/F8WrnvRE
fzfFilssfhlaOL/wQItv3QKBREtwdkDLwt7YLsMhniJt7XHGD8RVWD1loPOe9mVbheo1xL6ctgON
6FnRg43OGVi5YLz5CyWfBsqZ2o3zRTmLL6MvHW6Bpi2Dn0xBNLH5yUSfes0b7JZvEUphK4XIvNLH
hHKfaMVltekZO15axKJIvqiaChA7Qc6hkclFcbCrLimvmcuIiTmr64BNSWJ/YVxS0zQn7aVfg7nx
hrbjBDKRexSouLIw2ijYXSjeJ6eIydjaLGjGA2YQ52+7JD2JIQGUVDWay440AJ++XzSAhvh72zQG
ideLfCnFc3DsQlAZF2yYnO31TTmpuNfvXkza5C24A/dHQY1mQREMhFELjZa/SD2UODyEjpicChqW
kuiL+6cWAlHld8bjM9dwQruDLqY+7wJJW7thaOmOq0jcxEwhximwlA78bKeG2zGtFaMAniKUgBAI
j/9d3LhgsYd41dMxgJ+6ophFO+rfzlOterNzeF01aUer5xXuRID1GCR6CbOmDg7MAwE/dWcUfR3E
8PE49cpMwILtyE6+M46LSTu9ZYdIU+7UwkZ4QUaq6jpFKHgNQCM7iJATwD0kCpVuCOopHdpqpl6m
0J10tse3e1BvOMuJbiwDt/Hu+oOhOsE95RF75ZXnIbJp0JR20UybaB/lgEoNoIW1jxZTsQqOLa/P
ynpyUyXWH0lB/PrDliDbprBTpi3kCWCnTUd7QHgLJM2Bb+09bjHkdiTyoO3wNPR0IBe75itWiulL
UXB+5MfSkHkXSnAHsPHNzbvLuA3dQTzFE6ZWc+d8+w2vuGKNlHM3k3310p3ydDDz/vBqxmc8J/HA
S/1E5+lGm6u/lyQGc89VNO6Xh2vRfEKDeLXS9ihz+vAOBYNUguDlzKCpFwfR7IDpZ/eUBojdq8Ds
pKrhHgC1aoAOmpx1Cmj/+gu4xgRE4m1nxzxXd7tyFgkrEEZliEpIKH00G9k1BYCTMQ6sn0C5xBqi
BZnAabdtgGhKf3CGXxOvbs4yIaZDUufGxx3IBh8lktUbGi7DzSYOfjNxIxamRMweZfNB2C8p4m29
wwhDkqHkLZtXNOtnNXKovf4MPCnipJ23LIW26NkejMC0i3eQqHqxFqocdwVM/XzIJ0XkSKlHtxm9
wvYE4fAu93rwevJ1ItR6ewNW930BNPbmxIR/IimAws7+QBmL652vSK7lKGnI9dRSZZc1wph1gyc+
6J0tdsyOrM/qrbUwzUbnPpeoivHeCeuk/LRBuGVOZLtjlTc2OiCFMPWLHEcDh55E3g7Rg91XLxy4
7YJmPgl8tRYz3WMT2slzhZZe8JqOduvmKVQwhU3fTx/A4nrR81xN8izFDY1Qv/0I9GqcBpqEanPM
j7tzQjcvle1ShR6Eg5OlT2fPEsG3bl0YtHFCz8NWGy/gnFKnr144xOOyIVGB03UwTGCVpUzqboxF
zDKMN+7uPOMuCkwv31A6I8LWqIQV/Ua4/cbhMJzU2xKKB6MM96JW6GRAd5PRB9vAERqtckzxNk4l
dX5rRukiC1Srg/ghSXwUkkLhLHx4BOw5yWJa18WfQEB4A8tbaOV3cLEe6ckV1QRE8Whpwleg8ZhL
CGlz1tWPSoBYrlHkukuvxeomAGMsh4MgkC6iBU4J+l2rRmAOfN9+wslfqrK9X0uOsq6DvMyiuxya
TP/UfDE3fDofsByUjR7RokjgKjoZI6hH5uZcrAwm+VFPbVyMqq/PvgQCphq9h7SsSOYQobKgEbkP
o6bsdjtq0QoWwbdmP43GDPszDrP3BpH2u5+ZQd/XxdrfOwXHNbim4Thcnf1F2tS44pR+OEee8ClT
6d+//StkBqVT1Y48EP/U11QIqowt0q1crfPMJi0d9lUozG5dmShsHEGC4/y6o5NCdNDi9rsCxM6B
xQyQKLo3GURAVsJw/Zq+7uVodCUkbpqro4LYk+PLADfNqgki9Hr0iXHEzKLtJz8Yq0Y2GkglAdVX
VO9xTRybProhZeXFse1qT2l2+8hyxzREUUPGSG5thZMOP/bQLJTV7+JD+5BuDJbMHwYyloDxNolF
JizckK42Qn6feKN8usl4qRLMApLnIHrmabJ2F45soD0dj3UDeR/pjy4PDjVHBTFkR1TMS0qUkttd
W45OhRlGQmDmfJdYxu3xmiPgCumhV3mjKz2zJKfSOGUoQIXnEuHh6umq/hOagQvNN2gbcY0uJLWl
i9eSqsUv8sDs3QwlhaQTAX9vp8YxAf1R1sy4TCAg7lAl7Wiq6lUdpRsyizNQYRZrcRtnUyhFnleD
IijQez/l1RxhzkNfpEiNPA82POosMRfY3NOZdddAT/zo6liBEuqRkQLx1GVXFbXDc3b08Dno3xdW
NXqev5u1ycJMbMdRw1C3z8A4DPDz+VJw0rzND0mOQWpLnxdl17bIkApGF/ULWpJEM8ne8WFLaHK4
exgKo9z636D0Zmxq1ubXcYVmeCxyGSCRVZh+6xIB1LDRjqA2kyvo79KI4Gfi6XtIutXkL1NnkP5B
xLBR9WpkyodQxQPPv6hRoi/cQeUvtpm5cFATpIUCdbDV3td9o5BJD9f3zBHXmfOt8HP20/+ae3Li
nBeYbq1FxxgSr0VPSB9HY+r/N9H17VKlDihSHon98pL608fA7mTH+7wr0k2OcrMV4QGheqM1NHTh
yR31lYiiIbaUb3y0wbCbOmxMDTpypLqmeMKcivzJeRIOK65n7oPJpSWTBazddR9GrAFJ8YjME4gd
Wfh+jsnn461/cdCxhJvM+JBlwdeM5z1oyaN2ZpyiJFudco7H4a9z9YPJZAUWrTIvN/4DMIYY5Klr
dJw5C56BdIY/uqSndVL/gmmeKcSyvMmPqkrdYdvZUQ2Pov4R3mRbf5tRy550dH34yjL7nsPaI2UW
+p2CYTHK7Y0R6LPiaspHmUfawHcJHLrOyIbyVC/1bCPU0ynlPlk9a8vs7VoadKBdmckril5mhxbU
JCTDJwY2KRmIGumsebmtTICaL4/dw2Ym7/bgJJzlzAr2aFz4Qpb4/Qw6hVCIVjk1vOdSxh6LvZPv
5I8xk3pX/jMxnxT02ThqgaH3+6/Ut8IM0DTChpAGTcSAx8e6nsoRMOuyARsHrnte/CsfpamWdE6w
uWuThQHMKLSSi0rXTInBlUSptm0r3KF923XbPFiFBNrtuWt1EIog++2ZMC04rZEfIBmzjXCEjNdU
O8Yu8V75qt9zCp+7wVYFc0534KwdZZsnl5nSIrM5mLg6ZT3kCOHlGhbsiBlxkrl19gK0zr5aism0
ofmIaIoA7xiU7TIxdtSRV1F67SNKhTJJ42InszYZ6FOHnWRPOVT8s0gC/Lg8t3ijs+Bmk8ECN5C2
hRCzM9dJdLega3Ld3ukfhrJv7RXVZ1g3QhQcaXZKHLAedJDu9UeUe+4G9ejKQk6VoR/Zatmwbo4L
lDz6y2UZRleqSmq2B7z56FWW1yDk6kkMkuDlGvKky0BTQB6axVxyk32a58q/7i3GSyEIXLM0o4sP
6rRNdg4InTtdQdu3MWhe8h5o7rlPsN1DHcM5jvWftLX6gMMU349DPaogRXRATxOUUnhU0kJpEIi5
+1EwBkOAizSQkWTlNDTh9UfnH5NfT80FjqCCzeXhwBhGKWZYh8tLTWmNv5Kid3AweaGTZyLH6M7L
Hl8ONaqJ+jc80TkisyTZQXbINGX03dBtFdzBhYCgrMhZFTDwlRxHnF9dpwDlD0q+1kgC3alHDiJk
2Dpd6aAnxeJzM3p+z3/BNRqDS/XRtX9SKXnMnKq6uei2YZHNhrVvpHFXr5oTg+n7EXP6zkNt0jh5
aBNxooaOgzE1mfm/WeUrYVqxl7+D+BQ4mFOXF1JUuw1t/JwrOmbp89vJmvm/MHAl0icBpSJvjpko
69YrkQ4LamjYp8n0PAMk4rFCbgoT/AxOb2ZUMnZqdtvN5QB6byPnqaCdh78I2KATCk2A9MTty9UV
peVqcKCsIJr+sAHVAKXlue4fUls6Gc8rm0yATfm15fd+0mKyRuQ0yq6WLzzzHyBssRHTciVl44x3
a+1PcPm6uXMzzk8UYSL07WO4sSk9SQdPETLNn0ECuLAAFd1fQWEJ2i/jvyNQMnbirFMuj5qTy4nV
DNKCdIAlHLDqL6MI/uhelxy6QhdN2Utxf/DrmM7Uk4PPSzMlqNL9T9SNTYxJS3kiFEi+4YRSgL8L
G0NNHQaU+R6mmqPrWbDOqiKSCrpYoOCGvpgGJPCBORJT5DQCgRZN4wjVtU696tOkThMpt9Q4EMqK
3lk74mnlfjwMlsf8wChJWVlgkqI/JSRLJexfh/SK+eH4oU15TPiEjJ9UQj+0H+CjUYoyGL/EeDHF
A3GpyDj19YbMZn1egEpx2shpe34MmOFit0qZHuRCGZYKGB/KyCryYpUyUngbxzD+kQwiWCLzD+j/
1W0aZBAjK5C3Nwz7Wyiqhxs/HC97Y4OyXLlkEleaEJEB/eOi+6K7G7sZrItBo0OfQXXx8BfY62jb
YjLOwcb8u83HoBAOiBPSx729SDPIWwH8F3fB57z6dkpvY0hxY7yQ+tZ/H20Qw97ECdslrMnW5pdn
SQCzP9fBK5IO2eA+NYzwCsqdU10gRk+ebfzyf3EV9KcdQKeNFHeI/o60uCvvDcAWexRE/hOTtkoD
f381YKCV6oYSBoE7GSEnU0gku1ZwmnlIK7GECSkBVSD8u6xFlg04oAbi/XW3wdpzSyvhbIksHAxi
6NqD6mTydBQzavQKyy7EQnmmBefCm50g8p7vwHEcGvXPAO2niR16q4hBYTavmiAHE9VUUZ+aNQrV
/hH6T5n9wVitM/9dqa9E1UAX4NZCumfzNf+8xtsSuIH+lIDQuWQtSFlkV8J+DfoaJKb8Yrk2ti+o
Pq6Lu2/hhkuIs8fbIpizYuQ1KtPWjtSH2ER7QFfEF32xIQqhuO3zhJZHwyIKRn8dnTnldpY8diEu
SDbHO8NkaQjem9r2qZ7wApY3zeRQeZVW4lUu8xg1WuZOrrNX0i9TLKAgWnRWoATfKiPvHEh/tEWi
NeBb1/hepookNUCUl5GPWnySyCpjSUAX+OwgnoLMxiH2SNetPl/b9g+bMJ5zKY0vAUUgHBCqB4LV
0FuCnwhfxHPz92IDnJSs7KNP9xn799QqpzpqOTgp/ccYmmTFLWpsXQLUZIm8TiiADlFKz+LslSIy
3e6Jt8UZtJhqD4db7RH7NDDvOBX95+0tWxTCCnRvKlURX7uH+/aMuC+0ulzSvM8g2Zj66+jL0J1D
Ua9F+nOGxn4Et8gWy3/K6wAZxy4PATv/OOVvgROeW2idaA2f/Q+HjvcfgWZcjeb/8XzEwmHQSPrK
OPEILFbhjrpjWlcEukpYcE3ycm65HCxNfSNbkYYCZFQy+7SJMQaZELBDcQD6GrAa1JZdm4Zk3n6S
+8b/m5vBPIKfHU1BwOnk6ytdRLg1bGdL4lKkGrJwLKWgClCb4UloMF8I5DKT+3iYFt271FKIGId2
jO3ZUrvNHw7FkogfqM6LDqV0b1+8lVJkRb+VCCfvSLYk0HA8ts9jYmUjSkkx2j/qDWKrmUTi5tf0
mwaHTjwlk7sOGB8G/gGx9I6NDW7+u3bpIQvwOAAP5YFw0rrStfiAvAdeVKbSV524dEF+Nl9kZ3Er
fleUC2brxUvywRdvjCU2JyAwcmfk/tlOqzKnatxhMDMaB0zHZTQ4Pjelsxugfl1ZTRwLa7y86s0X
wOvYe+Bf4n8267yZeq2w27lHjHDM/UvBcP6zqCPgXuDd5SHN1BddWHWEjQYqNpE/XHQvbdC+B43Q
i4/UDSk4GpDLAldfpDvYV17uhWzcR5p1PboEDXg0WC5ES9zX9k+HHTZHxGJDNRTVn+LR168dMFTM
hnZ7U8c7KcLzwZO9kC86prC/mGwhuzAb56vGuG0qyKWqHq9j33OPRDjbR3q/aGkcFoEd9qKv+nUh
SdfL6SXi917EITRL2y/m1z3oGS+CaRUAjcU0qyaBAzrpZMngtBf4s+nB0SjBZKNUlbYnKUt3O3rt
G9MRaiwcJPzM+SFO1T/Ss1FM9OKQFU9rsLBx3/1w6pjjKZ7BhHtb2ztO0JeZY7p8Br5XyOsh0+4a
OVhPqdrNoO5Eo9eQy7iLDc1HVy+QUhVG8FgO1/DqcmSdIFGZiCtkcZFnslVbdaJxGIKJf2mZ3glw
C1ldzp2dsfZAsqNYSA5h6O9rX0xLKq7Jd77mVe31GxaMZkzagjiC3/L8/itcwuEq55LENe5ZO1k0
vC1RqVaUhGNRlkbVyEgSrEZ7ZJtC5OrikfS0aAA7WMWEUuQztN2rsFumogAg8Hts2gnuL7LamdG9
EUviaNoi8yTlOBs8KCmhG9CHjawEQOe5He1Eju4Cn0KY901GrVpweqZFYoEQD7sdfdsb4rj76z97
T8wOEaFa/7rKXlq3anFiZ6L+DaCBHoRCqwZegRgG+vOq8cNT3rv0Q4e+mMSeoos1OngXEgRAHYYB
yCo7FZu4nrTQAt1lphT4Vj4kymFFjpQ6pwailHgc+BUZqH/4Wi7KwQ9UnxaQCz5hu4dPeO1a08td
H6irWnL40k3XQmPXQlR359Yv8Y0G5g4FtrW5kv8f333AQnYM6HyWNfN33wtZHRgS228T1rA2MF7D
4Ut5a68fC4UcUmNJq5v67xHBgYXOjD8FDl1EVl71ph0f3/f8gyNb/wMyZzsStNdypx1ln25qvJeT
eoRyI3L3EwtedKjF5zxsPZcqihzC+psVnAJYEgaEY40JdpTnaal5HdlJJvHKLXaa4KC8zTBlDWYg
NeuKQjKxB84RnoIvE3fKHRSOHCDvQ42Hc6wRbVa8MCwT7pclhd2GnK3CN0TYGFTGFnHjDRP99gDy
KbRiq/RHcvgJb3pKVF+iy8CSELvPiCnY90aYayTIOizTQXrtBWN94Jwoo7dDK23Cno9MfPy72hZr
YSI+9fMhqojnKnAAmIkxVdLkGVZ9eQtKc9DAAinyBN0FkNqErXz5ktJkFW0ladfCNtRkwhloybCl
qW2RmeDhYsgvxD+GAJAk47JRVIkFwV7onYHy2qNJX23Ky9xI3ZOqaelhc5Ts0hc9Ay3TmoQA7mcl
AE6r8brDfvUxey0SPokIOS5Bm5FVnh0DSkfF0wEZU00/vc0jN6p4LPOYznapNsQB5Em2rAdoIzG+
xOgWTuY/qtphRJw7ICAYDS64XZMN728XVO4LbMkGeaxDFNvjJHobyKRHIwUK/sy297wD2p1nqsKS
PA773sH0056gzjDWtzProKK1t3Uw1z4TAS7l2p7If54ya9YRvyFQvcqI0/3j/Aj7CzIAm8NwxuqQ
sHRQthlpp6DtQKzhPKWYphec1fgem+PMd6i2gaJjhJnzNyCxx82TBnvheD4+bM+e5AFAJrMWNcxb
2hShByg2nCpTYUT4vK2zLET2YtVEKHmBvrJuSeDX4ELWWEhDcJ8dm21vQwNtY7ntGRZ029sLCP8B
iZH9Q6g9tSmCtEMF9FTMRxtq6SGZ+5DYF/HPuNyXeFEojfv3aPIcSeXTdDxqwoF2IZKHs7xm7GYj
6UouKl2T9Unb9REZ46ENsBgmalXcOKgmprcZcQJ4pVLl1oG7COF05WYo+dpbRa7Ko4X9UQJ+7jnT
JLet3K3UvoIOIY4/9qGDhBh8aJX33uQxvh/5pQ6CVRgAaz3bL061kHQDL52/LbYgyEa0UsHW5RNd
KjgiAKNVvnqtW2FBorMt9gU0CeSCQ6nRhiJkxe1bjqw1+xkV3C0jl25rLXgfSIrimfxP03hS5KoR
y/jYgtOtp/gW+yVSJkE4hqKT55ntTJVP0/Jo67j8cUK++eGyP2zzLEYXHgpukEtgHhGDEpLTJR6x
iy7Xz+NWNc2EAYK7+IuJepe4eYg2OT7SDkOklF70yEvq10nsQWDqVdcYG01vhQ3wGba4Xt6MyAFq
ICRiWxWi6CbmU9BvDrbv5DNkpuwfJUao/0Ocd1+GniZyNOupFTM6RkFzvLTZmCwZw8At5jWVba2j
MN76S//JCc7xDx0NrU3XOchp9f/4vmzOlmp6JxlAh+jg3w9Mh1XbtOJJj74llGNVj+iaVUExi/+T
7M5MXGb5puHNAFx4IufrJ5Hg7EEzCsPi+X8V94F5jj5Kxg+2MzU9U+5LxHNexDhUGTOmOSMRA8Zi
CPsM68fFDfBwtvTcwY1WYm9Hdq1FiWiOzdlTTkcnZfVW98y7NVDZIGWf3Hxn/qPhVOHvwQn3tECU
wgCBdbMMbFqQSPzia+Ua+bn92KOgzUb+/TpBVpDI12gfT/4IHEDchzp8U+jmeoQz7uk5C71Y7FE6
BUFcGIfLXvyKycHKQrCUP5CHgoTjyt2CdYQSvEuDWBdQOuARemjmvA4doXbswkDYv4ah/QtPtc6X
ddoiSgrHU/ZMdewoTEeam/o+4q3VlShvLdRmXBN/0L7GqnB0QX48SQ45ViHsC3eQleHuewEbzWyt
dJytGimVeW4EcOhl1RTDmiTL/XhuuQyX9r5wW3tYPU9TLRpcoQQORzh4yyVznNd3EJLcmPrDzI9B
iP0fSIqIZvm6k2X/CPSvw2g+/fdwHYApY1Y4XVJ3q3qjn347a6qY6ingn2QZ9ZChUQCswHJul/Ge
/FMOMyPchAy1VmdPQUTi4C3k2WmaL6WTMsjlIfTdmQs7pup9dkPe3on5iToXFbUVgIQuTgCEMLZN
DiJjFMvFT4EXNxWDWAT5bjYw4JuWfwcM/bwgRtsxHojzyLSPnejOIgLRG1jUQbmXtifvF9Hf2iF3
1hWPvXsxOHq7EQlLpMbu2odVIL3s3dG4Jdhx1KyUJbj6CJYBHVnpeyMXHNSuwQEcSZfDpVYTmLvc
ePdgnqknOqnP5UNT7wPoMF013XDL1csI+aOgoPBfbXn/hGDPl9cKG4nLggttDZVlSfBL/3Qxf5C1
Zomhg9QrPuvdxT5ZDAdTg2yCeNW18Aa5sVg0ZKaumHmFbImUkmEjjktdxe+MSSy/R5LKLX7GPwiP
W60CpwLbx4PNtI54elkAa0V1Atkko/yQ/ceBDRASVJj41Sn2614nMzzHfw9g49jmpWNLL029QLS8
j+oJxbmx+Ni48K81NlJoA6K9S8SSST6ksqNT8fkrtgYMotG53FHYUZLJ4hULUmq+eF+b2thDOBDL
iI8Yc5Co/019QwD0MUijKTkZe2G1AyEAc93kWyJoyA8hQ4j73TZpz+D1u9XQUgWB6VSdh7FmIcGd
1iyfSK1v2KjjzgGhvw5lSLA5gSVKLMPU01KZjQ+c7/V0YCxnD3OtLaNM1pm4rc2MbMjAZT0MAjkt
6DAtJzgEbZSgT2vLqeH3sb9R8JjL9+Ul6/HpaE8ZRzfbmda1C5d2BL1rxQF+7/tSYFZZP94ntuub
tu+RGkcxfaI8fGPcIZqrpIh+V1yBMLEvbZbj/y9TIhjuFrEt2YIY9eAgT09VW/KtUOwFhzqfwc5q
KCg74CSqSSpmV5YefROkcw1nd9KYH/TURIapYAevuCwpaC01l2FGhQ/9a6MlPpc9/DVEiN+PvJsz
kLbbZYeCu1EYYV45sAzOQu4LFVamu+Un5Z4oxePzdIg6mBTtOUns/MwGo33vCJXKGUEDSLPyejzl
M6oBR+SXC1e+ShZ2BptGr+kkG+PzunK13GUYL0Ejz0WIltfzBadCXB7mWM5cy/gYs4OGQCPauOTM
Xo+DfDdZ+GpLgQeAnYOJQIGEugrHhbh6UD0LUHFn5NmuoyJdgpQHPRZ0CyKBFogNhngNnYouJZAR
cvbVhENMKLFQQgQJ7QwKUXwXgSARq7bPfTVGrzm4zgB0SrWy4vuF1MUX0T7W4VB6JkrgH9qqBYTo
Z6TEq6K6bf4I+5I12KQ+Q9T7KsHZ7W0ak/qhyxGbmOuPpAkvhdYRAKTVpHWMcWV2F7bP8zk1AWXB
D154IjkA5/EVXnQ57zjv3dpD2nSK9Quupz5krFA/9V+OTZL/NjW8yfejzgdBXvAeaA2EFaaloER8
wGCRp671r7iIoCLk/ty1bbI3czDPKhSjv85pOxhhrxKmNVg1lndT11lmy0+Ue2Ofoq1jrFTg/X9f
fCOqAqiUgM62kk2qLxYrczc4ZitFufnUFQJ9SV5b3FeusIwaxpVsyv3dAMSt6UwkkuxlLZ19WGRe
oEGLkOHT2uvHOdLtue90d8FjH+95xxl2iFjKOSIQJqPcJ3PMaeBKqOqFOluAWAldf94PkQht55Oj
wtfYOQzHtM7ZaVjp/LDHJLYEpBBLQf1EYb67IPonr3gq9KL79TTbjX9FZ4dkqIfy62ZlfhJeOyG9
RQcmXmUUsrpKAPaG16NDu38oMfNiOMf5AFwi+xbyX6i+zi7VuyuURkKOtQOOC5XFTnb+DUGMfb60
MnUJZVWjXvAsXagEOl8r0DyGSD5Y3icLbIKukKXvHGHyd5c3EfXZxL5oOTwdVwKkY3bfumfqN1qi
OXtYM3v88yc5Lh5hwC8HL6FXOcu64qq0CoPBhqgL6CX+39gWVotPRcXg7QkyExaMMEXGr3qaYa7+
hDqZt6kXaRYzJGtFCOEz1iqjHnEwm4Ssjtriy2KYtsUYyjEEROgqw0cvT7v5dpXaUV04/CMpqrX/
Y3kvSdE3QQYCEQ118LwcbwEag0ucLxfhxqCU6WuU0SIkAxxxkTflLAEpnlCP9Ow0VWRXRK9tOcPv
64v9pjqWVaXJedrWQy6Z4MrGThYClY6bTEehFrnBAcERF1ZKEhDHB1kJK+eZ572RRZ8tDJtlFJrP
hdbZZXotSaCDf2IahixsX7gFUKgsq8omkiytNP53NpCFLBLBb/oEJ+8iFYkIreGWW51QosCqiv0O
+o9VZ86qzu7+nWGdkNQ2ip4o0wC02p+GF3KFS1pk3DoP4cLdhvGC+boqVEmKVHm8QpEHykjBsIg1
20QF3005UPB6JEokEB3JxP675k1XgDX3cKaF+8oouN5Ede9IFinR581Bu3BhTDcaYJO38cdMfkI0
cpXJQUJe8SwYgWxUWt/RvWTggYas4fYfSu51DXhLJbg+8q0giQTCtynTy12TL+8Nk4WUAnbxwhtH
95mfi+XKQ4ZBTCMfgrk8sEAS6DEennqeXN1Rbf+5vRKkC405iU5pkfwmak7aStTdcunrW+sfpM7S
GerIxICxeEW9fjaMFpVdY8NVwblUAKpyOJZuISskIvqwcE8SgkfTPm/Gv6FTrS/vdYHmOayW8d9X
veFi0pLYydP0e/hETSfnYcG+OD10Bj7vQpjZ4TmKXudpUFksRqaNCEwXkAk+4N1Kyx1OqrXI0dUW
G4wzu7OxwJmzsc28e+uiu+qjqwaXUneW7qKnwPor7YzcGo5KVySMLGa/VJ5CvgCZq2Tm8qRt5dKx
drX8/VnkIKtmG61Tmxxf/EFheFknGLjxgvXp2Xno0MpP8E0RNGtp/rFDA48uktYcmzCShkqAvunV
4saPGXWcGQoqxhGhRVyRlsS8vrE9hz5+gxfSyY44nFPRNFw1dK6mJ9nWA6BLf7rUvHSBp5FupfOr
gu/ZKi4t4Lym3a4BlSOOl5Qb1SdFxSiOMDqFO+yncQkSZ1reHjEZRNxprxG9/pfWHPNOovz+hIxi
idcEZ8aacHVv/1VL6CE51TQtNwr8TPHAddRLgVoZTXfN9jzBKJSCeaLUzM0G+KzZOuHecfB6gUcl
J8SjZdd6TdYtNLpNCKMfOKEbL+gU3khDVgkqsNZOjwzAKespWg8DxoVFzHqgFJ4NEkX1Z89c/4R4
YUJbg0fTAAOnUWtS6Ttk7J+CQ15ZVk18+BVTKuNOa2UnFwra1htSNtvgvuZj0PXzDMuOO+rhzArL
3KFi1GYffsfXeNpSF2Y+RBmncQZCFGxTb+kFllt60QNIcw8i4K7ECihIZ1mvVHtjUErUFb5wPmJh
HjFnaV2/oyNR8uQwi5vL+eT3RkLsseI6i3v6j+zLbTztNB6btFWCpA0okavw+FtlNlJe8b7HM1Tt
Cj1NKGfddpIeZyY+imCc0NuKiv8Ui8hPgA2vWl62dB4u/4IagXm28k78AXW1vfSnAadXzKhxBmev
zgwa/uCXxn4oPszDwTtj2IvhL+DhOu+qZ6YZ4ph2mYprYPAZTJameCWbJDeO0YEVj09jvj/BZy8e
kjk+crWYszUAZqRe8tIXcsW59lAz1YJaVrkr/dIC1hDPsvT4GZHwUauuozgA0T56MVjYeIOkxCWN
3nrm1ltPOVrnSGszISMo5GafM8CpZzaS3WG4sxlR2bYE2j9ldoSoVEGx3jB56EPtH4uvhGXK/LAb
ZFgHbxBEcdQKQUDB3+xz5S8Hz0RNCSk2Eadx3OHc4brH5TyQU/nIYM/4lFSVRs7Wq9ntqXVKjTLo
kQINEaI72Mbr3gTXB43PzDEypkwc2buZS7ENr3xoGC5LVP7khAaXMr+NqW/JxTZzynUmGo3a0AQK
tzUXcu5iqri4fKPV6yJH6MVLeciOQhsMnactTw3d9h9Cs+YJDGcvDEtFp04AHyIHd0BD2iM0M0ww
5fdbnUvW37a3XztgyM011xg6Zg2EosD/lNDVsWtfhcaPE8uoW6r4YfoA7qaPbXApJC0wMUfhE5g0
WpFLoXIEd3UGPmzTIRs0bjNALW3wYkcN8En5UZidOib7KyZGMYmXoa3vGQZm8iOwcE4jGE81KhOH
dbe4J4FkM5NP69LWDkt63lJjRTEV29y5UtkgzCKtKBjWmLzMSkWDpT42peEwL/Dh5zbkdoE0pGBR
dyyMy7K8LXUM4kfzSg2YAMfbqb3/c7ofIWRblbSDORChjcwV3Jp3nhGDdKXmNqolNkOt5yXNG0gn
OTtriS5Gi98iQqy5T6kk5kt9RFSPOXD6N5IUifFgZsEU7+ncn4PvE+zmSWVaOMU+x1drtlrpD0qu
rpKQaBW17oeozlNheQTXAHL9x7HdHS1flHewyhLjnDmKcrQYyCWdq1Ld/3OXLviDjAGT8ceNzhIN
PBJe/VTE2ahJNPnC58zAxmb7vs36sxv//LOujTNUuRKZjLvOa+99pYSfIQ+Tiyl1fDnBoTnyDYmb
tKTJDtsxCyffpYQNrnV5rz4eiC825KAnn1NjqiRn9yAEgsRXx11+8zo5JpRVaeJcA6J1/t6oHmLn
1l3VnPhXlasMHiuCu3K+B8mSTSXRRWVTN2Lk9VYOELk0YMY6E4ZAyyrrmjpcV4KQQnJv4AfThAGL
ah79+l+oZ94DKdoKgpnVINXhyvEYa4e0QI2HH0QnlXxNb5fg7Nmjhf3B/Mdp4EK2JvXygkTheaHG
RaFdSo540cGaRcpQafTvCUG2mS8uJVeFz/G04csJybyM5qK2iTzQTAsYzWz9hL7pAzVOAzqlRGKO
EKl/rJ85hWX26B/B3BQXmc1Df7A00ip1dsXETbqZ5ax4r2ipm7eZqbSRnH4Y2F4hoAh8mDMJ+BcD
L6ZXXeGGajeBwAfxjySStWoDdFDj/mCdetFhOt6vJQ8QABAy/4GUBFowPeX1DimokXkI9r+WPDyW
GJ9aQv6Rh0XnmOfJbewo08UH3XoeavfkaI0XdZfXublo8heMR/JE8nFcBQXE5jVzuml4TbU3Os/R
T/Y723+jeJDG8Et3ESiExP7fQMlEo3wJKy+RJoQUcuODMGwSQHHQBL2BHNH3Fh+1ZFz2Li9HfsEl
U5NsdgRXXvHVmHDo2nxYnIFPEBClJ9UDoHTpIaxv2YfagckWXCdgxzVelArBv1zTF01NN3xxyuuM
sObo//1hSf0wS1byzhaY3cZ7kAw28RX/bSYcAuKkx9YgixelX5D6OWmUTx7DHW9cxwcCchAX96P7
GC51Okq7O7Uxina11ojG3AjObZhyfQnE6ys/7mExEyculGHr5sdkSmZX4mRgsHJ+d/Mg3xLrmP7K
I0nQTOdVax1aTb8Zo2m9bZ0sue6D1cBF8PyELeEHsFS1jYyi0NiFg5VBDkUw1AxTsA8pH0n3o0SP
eS2BkDnivVmQU29xYzb2V+RXoDHvLpnVyARqEzF0xpB3nFuefaT9zzEovRfnqrmC9ZZx6GtVOIhn
+gSgtPXu1Vo+AJ8yLElnBZNWzbAkRAkWP7ZRZHogPQ/nr6jw4EyeunQ58zGT37HEqZuwxhp9gjQX
kAXKdc4c8q1lJZ3P0TXMb6v9rh3Pi9znYdNnyyEmYUpiFhbx281v8FTX9UhyAbuLJPA7DawVZUqr
rRyN7vdv23mZiSSsbh1PmVRyjSouEkbn/MC3/2Q3rTvJ1qzlN31V6EjmhAnJpS3dWk9PcFp6kEqp
89Bs9GqYVuhXzPhklTB/vOy4l+FQkGZNzX5/Cju3g0rJBvnl1Jl8DI3WUEa7CzBHfbdENLWkRYu7
KcD5OEIBe0wCvYAQ4AnxnzimkqLenUvWUFlnG6+o1kBhWimEjJqiq2RJEs1M+dXhvQio1Apb6n+4
fmIGQZcu6/2DV+YHKm+bAXiSmEg+cJEdSrspW+RsQ1ShwPKirXyJLSDdOgyYd7l0w6Mj248mEDJ7
3KvxC7c5P9mSzEwPzUBOUhOpu4fOAlduCJGtB6fnJTbKZDCl61EDTf65oAW4F/DCqfQNR6shfZcH
BQUlPCVCGzvwLHRZsOzfCJJ20kYsnCf5J+FkbXdkSYzS8cmKSIH4/0YUL7AVKvSm7w+lWS2nPIDo
L/jDDhLekV/BAL0sc2J97x/99rCUFWw2mthR4GypfARqPLsWYrj1A8dqXpJZChKbOk0qzqkHmIlI
J+J8ocM1KS0Ls0Tidwku64854g7VY8vRRwJxPYoOeYoA6w==
`protect end_protected
| bsd-2-clause |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_fwft.vhd | 19 | 38466 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PpoeUczC12+YQ6zcBW/hk7KVg+x7UTioMUTG7QSkaE8DKLm5OzMFnRnSP2RdM8C+WL55mLvLDYfA
5lOC4Ruqpw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
K3yZ7/h8XZC4VnxKqSX+X1dWQEKELq4EziAIjvSKKzex+MM5ch0NyAGabLWybM0VZcnyA2IuBQRw
LXtEZmU52Vw900CqGAC8j1ob1JJokunlfDgROKOp9VekmhrNu0zlywHl+eh6CQ/t5W76EWfCnLXS
TKcvUxKzMPqBkiVg3Y8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NSAGB2MTAPfuv2AfQtQrWIP89UNTneL4Bk6/B2TdOO+6mmG5j3iveazvIvg7qIHwAqHfCGACbbAp
fGS79Be+x6ilLMPgwgbPlwYl5oARsjb29GILZJJbq65kaBdWWJCFrRmIDIFHXq65c5qChGV/7EF5
BRY2p2sjUe67cd7MFOLVO0mKHurU5wiieT+wdpbGs9uEgt/pGFeQKlj4ch2XzN03R8Lg3KmqOC6w
j6pa6lYe8j+sQMdh+WMN3EmYurAN2aA01NOtdnD7EoaLrP3ByXrwCKFB06hQfAMKudCun+42nXbW
17uiY727vjm9PIB2xOmQazUdPEZbwz2Eeua7KQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NPiHNhu2YI6wz7attBCDx15tEqFL81ie9/7cRUJzlr+aO842fU7+GGF/JOlqWsuQg2RB92onmIR9
gKmj6xIVPN77wRnezyej9aQsYy3bBfOSvbf7a7d2lZQT1pTZcYMfp3xveVQ5gTGk/1BN6rnnT8J4
QRALHC2oqPHhQZ427wg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aHttOHUQP+m+tZmSEhqIMk3Jbc86fWQ1/2LKPbbHBoOHb+XyETCjDqnDo9IWfpo+m+LC80obW4Zd
cXgM5NoQ9F1AYdG2ggcdGNXeaparpheOz+XWEe8nirOAN+Ks5VYo+yRWYwO3R0Y+0V6Yw8r7cd48
CXttfKVhu2QOlKTiKegYDKMRGhVyrdNkx/KDldRFk70rkBceBbiSjdBniOrozyhG2imBoMkKkCmI
8TwlLhPf5Ra+r8wceN6j4BjOnyQ3EtzJgw91ujnHo20MZFiaPiqLQIavDgBT1y7leXT7TIK9Z2uu
L3Oj5XHzPc1v3FMsMkjnu8xWqC9pP05Ha8xR1w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26736)
`protect data_block
Lw3ntSlrCokmfZtclotQk75wzvGS8NAVbfW40Ny0M3qGBUgwlKBkocOK4usgGsCHzLcvJEWmwBj1
3wfmeMovQ6E1L9p0zv5fHQAI3pbG1yrQ5Pb1RchCkOLmGsOWkL4hI8Ky5pymEJV1Gy/67VFKPPHp
STpFio7hukOaG6yOfVLFz3BjqWEdbVfaa9tRGugyO+5FcqZfTxEa4Si03udjzcqO/H35KmceoELJ
CVHDK/c/EMXh6yS70PdLGd7LXJrWz9BaflTPsqg0SsBoypFIhqc0Akrc6Kfn7npE84ChKUB4GlGU
vUH+XOAK6WZPYMBbzSFb2EyB4R0MDSlk6yQ7bouMsCbdpYezi8JoXVkuvdBh8eAVMDcTUpO+zHOG
cOhyf2+W/j2t4Rh6DPo6Z7SQW+ZD5XKHwTANc3xKbL5GImmKo65uLWHhs8yeUBgjO7ez9gSK9ImO
TXfAwYByaTC96hkCbSVgknq1RpqhWgk7oqBSVuVVqqhPaXvMQT5WlE9ztefbtuw8ZR+KnU+Uqy5O
JJkSpS8ZMay7i5oG3XwXhDgjmrvEnj8zjpyY32Xi3vfWU6pKwGxia+3B95RJhTv9ClBA54bT8zyn
U6mU0a8h6xBr8FxQ9eJysWb9Nv5iWvzi8gdfy2MV6utnvncbYWX8Fk2rhNw2f/AktfVi8tMpALIt
bxb8I2ZUMW0W+WltnNR87F5nSLBowjwjsMwTWxfpUuY/YP5S0670UjEkm1+47MHIZBqku1kyACFP
k9BkHGzAiMYJRg99p2SRFHgz7hT1RjKIV63TDKmuGyNxCxNCkr2Cwr3bbvBfiG8OszPfP+ysR3Q4
TFS1vrC00M1tevsr3RKo5v+s/ovLj6NHEk6qwKfHxuRCcwZkzF7cIeSEHQnxikAkVdqFsfC2B+YC
vcJ8p/3cu3a9TGi1sRbsSy66u1WDHPtO5BiRYtsSsgomPsPCrD5QSVQFy196L/XxJiJoQgvyrJxJ
VoM5Eu4fLnoDPTJQlWEm8ZFxKYOWGilL0jBLq+2A2HRn6DfPTbzzYQ5gPbuhOcoXKhgj836wPGQF
LYoKMxERfnDJPDheayMnhe1OG/yb0VfkicRPAqDZ/LQtZ/aqSAJzt6wVQSEU+y/45UM+sfJ1C/ax
E0sgloo0mQjB3Ge2WPuZBXkL8NC7fqBaaDAznRlwPR8e+E5S9ShyZNxXvOqFUCyRYQqPJAn+qxfb
rdaHg5saIk3JlY0bKk3AQR86bCmRQUw0UtJDcI6LPYVXSp9Z67HTWKCeT0Z1bEb2jJnj3DFzG9aK
1mP6KXkgXiGamu1TZlDfezhuHNc7vZufwldz6XmnipHBg4sZIxcJbNqP1GIquwbz4hpCK58WsSla
JYl464gMCafm22GcbZ+fhcPqzjM5NytZOkhaeGsZU9LLxcBxs50J76MuNbI3BW+n2nlJiHDNrHJk
1GY00lltSVFIe/BeK/m7GHHH/WSloyiLGSTX7DqndwaltYCkLSvtam+prvHLOrmkZg+Nh9XDR0y7
xzXHbjq4DSC0FGKJSsb1AmbqNDlcHyLaCxhWlYEWUPrVyqEozMKlFmf+PSz385P9HAbbOdqMFoz5
qJLPdc42fgT/S49tB4mn5iX9jC0flJ4VfoT3HRu6EN93FreG4iqGIIjf0caLMMhxn9aBJFdygvCZ
jCviqiwiDLMsbAqzezwNRcpMrbv1cb5LuQCzOFJOckCv+HI7kRsZSa68sfVe7FyWS2gc4DCJCB00
JEUoMtzJVvGKYd08xQS4c3B4GTvKhdUY7mYIT/HWri+psziRwLykLQP/O9ajxz0Qt+9eeJAEERaW
/nQFXhuXiaWgBMVlusuhvkE7RNk0N6dvFXQazYsCDbPk6UbKS0W319a4zh4brl5bEa5d7WbLHG6H
8ut/H8gJG7GvYleoc39l7tExXA7K1jc5SbOsey7ZqwtffKnm5L6ZnKMCnWXMxRcbajQfpuyEVry7
I2VkzhoI/A7fMaGK3fTMQ1PHeurlQ8JIFKRnc+IxGcUjlzdk3UV18Ym8NasQe5mah8YpL/YvEdTc
+jXmBOOcfk8iXefsTsy9pYy512a8G67Q5AMRi7yszcz4V6O/CiRieoyMS6FRljneBOF9Q6e1R3Ch
Rvh3hANMssokfb+YDaU/rTn0G+CGzMo6jY8HbH+xzJcYozxBqw+AfNmEefSJmpWcE7hkRtptmyEB
VlJKtTwZYOtDLat1vyzp+ED91waawyn06GO76JUuogC4FuNpr4vFQQMmcn+A/S06UzHmRS2ao0yw
mHgOKp1mVXg75qdKYRXkPqV2wcfDB4/XDp/D+fCIRFE2DZ5TxIAwVM2fdQ6PtID+ddt2Q2Q6flFv
P6vpj/r6Gm/O5U/JpHuCqeLLLdIbQmQKWYKfPaYHPlLTjcLXjuFgdS6hhTtgoaUWOR6MNBBkdcNT
MZPBu+NZPt6E2alYtBmRE33wKFznrtKa6thViDReJiHfqdZjU15OdG98JXO1stHbdfN/hqpwQFvA
Jx5vInTvHLhfMTDybDsT+ACrnKGOOOXGGB2Ri3HRwELiPoWlGpjXEPTcfvwz3714B4x79nRMyNSw
zey2GPL2cEbYmATOXXTAKAqW86h1yqqV/kGJ6eN42IlOBgK2jXw/l3ieazFfa5Hosw6IyvLPkaDK
Zaq0eR/ok9uzGU/3NxLo7wKxjLxcxU2ZK/4ECTJrcded8Lnw4yEJjUxQ4jGOJ2TjnjIFD9MvimB3
wDSN0kUsnwqd6HVX3pa804dFSm3TZWdfUh4iOzK/BAuVt8ZYfqpTiS44DSvcRAfxmQEjlsMH0RUI
/mMU6i4GND5Z/SXqDywA21y5ODYfFIMT9sDgv+PRyym22+CMVnxZh2kXlQAlBnN/dXKo4AKAjiQ9
E8X67Y7OkJmw2Em/7QmPTkg24nsx7mEewtZ1B56MdwFXNFs3ZrA2b8BqLeJHswdRsTlthGYcZkAT
uZaW9B9eDy0UbL4/bqv0N0JqHBD/ndg4Z6ceZXJRykGEm0GU3dYJxCdw4CO6ca5scsyNtCB8ovQR
KB8wyIuexIfPvxTxqF5PDuWQEi0CWipY8UHu7ZT3S+TCB3cusDj9X1zeR1HQpiaWK1GQeyPSsMu9
QNM5z9qbNfqADWdgWrH6+fIm5UD3sGD38lDVceO2TjiGpnqlfS3W5BltJ1rtm3sANUNl7HNkZvrY
fJqDp9j4pcDWOBbDsGZe0crIkERuFXNPmfWHYc7vFvLrNxPDWOC3DckbiNb34RSQnYFDTVFJWZs0
KNmXnwFGigPbNYuyexyWQ+D427YtA3CT9l7DsGvLZbu3NMfB0PoH2xslyp/uhf940tyOekpWdAPN
9qtZI5jmyRt4JT2Hz1O9Jrfdqbd3rXyRh71k6bmNVQpK1vQVQirsDi5z2n3MZOx7PfZpBxWsgIOo
PrckF6FUdeE4dRFrNo2eNTOH+DtZ1KOB3UhD1tMu2PoZTLy/wT3arR62+eDmdG2mvfUC9+B/IHxF
K0HZXFJ7UVC83T1u+iBh/3/ggH2tttccOCC/tnxqnc9yIJ9eGkUgjUs4UcP3lL+FTn6/QNxdEccr
EFJcLEZ8c+lCjG1By+omLwkI7pp7dS6b9YH4thdSuXCCGQErgeq4oLNj5jMUtz9mJOtGGtbrv0vH
W8IrAhVEM+VtJEQSW6U/4K6a6GMM8f3wK0zk/U7SD52ioV6lmHZ0jb8vTN/ProLgEuoudfyd38cI
1mD5ljwoaYHdXz3uZ8iIG411D+7lHjZ/WETTu4zWM4XbF4JUlKPpgqgvJhFRo/glaciAQICq4LoT
KA63mC4AlH+bh4Y3Sw6/V7Fa4nWfobUqZOXBaHpGZ1OZ3YAN+7jZqfHjYIyTCq5ugV6dX5787TkF
HGJizTdNtlQfPoxBjTQNRLu+mCLJaMaylv7GFIPDRBO/5V9KHQvKGFoG5HDjF+J3z/FIUr3jguCu
9yWUoqz8pEz2yC+pr9vWblKM544Q5No9kWQkc6wmP/mPrx9V08O3KX4YtlusbUiTIC4RpQADjrNC
7rMCq3mnt9kzCX/8HGEcrCh+0LVEf1PlGzCVrxC7JovzEeoqcu4ioeftuYrRhRfTSWVTebZUwXqp
Ur9lzR5L6f7sT0n7Bu3sDC0eHZ2C5fr8KmrXKuDTrjlPtpFk+AW//Y0+wY4feCNFZwMeKvRXZ7p1
GQH4n1j9J8ROPfWVvnpqP6eDuMA2hLgjKFeL4mCWk+iQC36hmKFU6E3nyNfazdoH3as8ufwNQDNQ
qtqiUytBNkcieqcyh+fuKZ7tmSmldj0ZPqCC5SwmxHMwhtE7/6T1uMUr9kFyXFAeJnlQRiBuQE8Y
Lw9BkAlhhH2QeFHaw4m73iN8EZAxqvjrf4obRT3xuwoOvgedGAhdztlHfedlyOCPITMYJNa63JTL
NvdNVYd7bIjKs8uK3r/LgPE82b+pgr0IEDPdKWHnqYtuKhN27KFEYPZ6NTFzi9Bltupvaeh6GnYH
QAJ+KaA/OWfVyFfMMUZbDAoFuEUp2CCyyltaeVVv6rxTHvlO4cliqBLmzSG+UD5m16eoNc9vsvGX
pfQlCGfvX43mjbL7YD9NQmaIJC5kMAF0NrLEEi0LfrO/F9ju12O0bq56igJSsLestY7cEqxWJCcM
WgcEs/DYbdTQFjBhBSp58ZbUH8awJYgVc+dBmlFT5nbuxKaDCY69FN3okAoZSAzoNa6djAnhtcc0
gC5bI3gYwkX4QdJGYTAY0+kCzlyynES44iJBfc+aFlyOhBsCQfXMFH569pKknjvRb4So4hbrnc9I
3e/0C4b/XdlrOsooZt1N3Be4H93+MADHdwR6cvVYXRbQ7ThSZx7jo/FzoUXPLTyLRK/8HW8M9quy
mvOWzJOcn36uHbrSm3Er8aA1aGToYtXXyw29HTFcUvGsk2/7IDtJ2k/h4SANe6cTpbXbyFUBdif2
4hX9/5hOaPRU2eoxiKExILa2O7x13CWZ2OAcAWjf/KZ0X8kMEJks8WFEVdflHLkLn/Z7OIWpXjO1
rc7x95D98U/2dNX5604RRqSEnsbKVASNF04dYsiQL6ijON6rVKC6WyMHLTVIwwpAGnmYHLYCdJAF
SV/cdCTP/CeXFs9T4HP3JiSpjeCtWzyd2scUM2TYSaaqQ4mutitqrtqUtLawz7DxfkIUwShpXlLf
1v6CLFAnzn32J/LobO4q1w7qFjBUfny4CPn0qlhxyp2l1wRxyDQZ2J0+jctygeAVv9cOlaWUYjsM
MrKvYc5urUnJPNmLfH5+cVHa9NHpowUv85QOT4nYSFrRinaJuG9V9WCrXMFJyIXx/0rI2oO+Ikqo
7GUHPV63fC32gzPNDiIap007yeb2lfxU39RWTMYwpkuoBqGR2y45sBgHR+jNqnEPuDCoZFQlCKq9
gWRH97PBdNdRHEuwzaiOQ1Wu8xeFtJnCuqS2TcaVZEKtffmRc1mA9reUBEhxl7hPhMTW75k2pL4k
wNK/NFVIfMcjNP3QDuoblGYqNI6PC3EUmTM/DqeOIp904HMAn/Ke2pLUgCladI4dVKUeEtbsgWp8
xQGvn95RAZazqo9C/xeVeboyPhzUszpbA2NBduuKb5usRw9VM8K+LTqzipUecNvxjP/OQtqwkvna
kM32DH9/Ej19uVZuHb3tzJmJvsjWA5O9ZQYrZlwpvK0uHNi3upfdo7DkCJvn/1LYHMBVupLUGfyt
/dGLEug1PP1yiwREeV3lrytLAy6OKwY/XT5Ov8tBIpO/kNbTIQ79KOKVm46yuvBWoDvy8kHtiCWz
/i/cAQZQslWd+2rFt0uSk+t5PdIDxMkpz0FWaxZZ2Qf5JzBQ1P1q96HD3V6FQwc3Xl8KtIFUkRQU
hpSGgSTxSc/J2PsT+1z/sRFbALESLAu8InYOUstooK0gUCOlUpU3w4Q9xrzEuY1Z0Uxq0IPFOe4+
mhESdybX1xpq9kEZXniPBFiIeKyN66/eFeZaiAra4wQLjfDhytle+j8F/B1dCFeGt/0bTaUvae1Y
wlxdRrkLTdkKby9CjZBKUX9TIgcS3D0GYjixUKtIWo3Axk7ZTGEvU5pBrXaB/iGnd9HYdW6mWzz8
H22hWbJ0YctA5dedBGvfyPA5DAhSdTlYk0iYcnY9aIjvQwPZSQ4LxeOJCMpgLeUVM0Lm/o+avmwT
I8c4s081KdkH8wHD1etb4hnx5Pz/SszlXMMjFhC+vFQg8bEhXmib67GtCSPbe6mk9NQ6bOIlnn2L
JoN2Lbgdp/KVSFwIyQs63o6GIQiiylU+Oq+LkFIjqtutzIaH2aG32bRcdAiAQ18fitq8YXmdz1po
0N7gFYNzXjTRnnRx+7uvgW4cMsovSTSivavYsJOH8imKLHeYqNs7CmQWxnIMDrtX36XPjK2IcJG1
EJ7Q9UeKwUvk3kVLUo545OJvf2shAv+e8/kwHwAXiiGpHt7ekEgR9wydPBpS3D4xRSrDz9ecqGTZ
XCoAiN+cGi82aAwoVCG9PssXL73n8amozvxEVDEIntMma3UMtzVrXAseC14SjgK5fi+Nf0weLidc
/iSRc+CWDYpFb5tOVjXWZVk/swW0yZ2NK0gbJJLPRVpGlqLeeJenXF/G6R15m1yIgWFwXjdCIHr7
KCgiayIQqC51JKL3Mj1I7FmsotXuX69+esp1qo55s3DnfF7vvbud5Sjgesb0nsYpJlcfRVx2lvb1
SK29UPVa1em+lTPmZioE+R8hChU7ZAH80XNP5XdUjDmE0r3qf16x+lHDcB3TyDwvxmlR5nGnHC/4
eseu22nWxUj1r2aecSY0PIldYjDq97E7CG7/FDxuFm08hgL3/oMiBxff1KzGOvJlsSLbMtesg5sQ
4dAZp+2uNJu0WU5PuKBVRsxRpY6fYGhqdGsHUzJPylsM0+dRP46L+DSPmniHSrY/yyW3mc/1Q5NJ
mu9KcRfexlWwbj1V2yjVSKkuNEFOYbr2IkBNTP8fKW5sFiPVYGywYMhCDwcfyRK+f6ZEf3ijQnpO
P2AxHwIRfj2tzD2Ub+FBtOBB0OrOsJHL5rF1070YFaDdCqNyiU0oObZkzDz3SfsOrEeTm5Xz2zni
48uZWqRUGLFYaSsY0mo6K3Fki+36Buqqq69X67ghss6+XCeH2Zz5xOxUt2o624SU/L8WplBkVZ51
XqUsmshngRZxXEJw/S2wsoVprmXtByLf2UwilMp4NF6wfP+xfd+OKvwflceHaASKA6seNn5bsw8j
32kPAHChGF4HyHBUH8CIwOTNHtq47WPEJ2HciS69bV33HCBsd72DZqSuG90dFPRVsdnVK5ulxS2G
qZyQhSeP5uAJA4Bd4phbyCaaO3FTR+ySim38emCA4sbK3/47tBsA/N5gRUP6pezpPflLUpbanIeQ
ZpCDzSV9RYgoY4H/sGl17eBl4q9G6FNm9eOvz5zk8OOz/VSItbiAymMPtkPlKPaMHUTHLb85Ubw+
K6BNYgZmfjJMeMlpaK756Ik1WPM6n5lwjStREKYJ5f0fuSFBORfMYfFZzgDkn9eZPVrsXT0y6HDG
bAe8Ov8ZU2boLIaQj7iLaAmYOVSauhihKocfIAXq2llCxX5uFFy/uEsi7Hrdzu/4gC/HPOlnRmjN
kzH3ckFwEiaKQXwcshIjlQy5hfSE3Ubz1OlD04/pyIN3lypzK/CM6qSx7JJZPPMhzuk+QnxY62WR
62xlz8YDTuXadJHWFr22kwNnKpkFRr/Yy0HXZ/16idN5UmBu3c9bjq3LuxJoolpf9dG8srziMxkZ
xgti3rTYaRZmrG1EUNvjbQCPdS8LDkPJAox+lkIMuHzAMd+/2KiqcZwpSNJRQo0N6Pa2MmkUWOj9
jN5Dj+mRDWz/CNQplmX3TBTlhKJ1CuTeQeyRZk5VgSZpf6GKvjQ48+6/bu4jRrVxK6Bm3GBaji4s
qMB4c7yxy5C3gGN8A2IhiseGtywpg3DHOF4fd0f7QEuZid037zqZmLCIgteIKGneq5XSUpKiadVm
gXEhD2/Y/Lq6YNr0CB92TUoEf2SRavepT/kSXqTpZJRiUTS/wHPkiys7KCjDOYpvuZerwIPePFAn
jsZpk8cOxhveIG3QevMoDm3OEWMy9NJJkCBzvhuFRieqnz4dzyAOf8BWCpcJ7byxU79+3hyWXODI
wBaDr6SSUgxBqej5BofbG2a9ztxWQLPnxBvoIj+56mR1HRgjPlke9KtQSlRkwottVs22CzcoXmg7
cI/QKF9v4kBM6iZ9ZHE2a4ayvon8yzFAb+N8bnQn5kLgZj1KKuYul2zxw56iHepRUs2G8vGBS1gf
8kgow14QTBaPh8qBgairIrtkuB12qg3daoBdvH96MySHZVM/VexuhRbTlNual4a4ch6Ee1tfaiVh
2qsyLRlGsdz5UfGdElwBcgsmgPyF6wDaEprDcyo/eW5pGv6/m0N5fUDJ8swXvJtTT5ew0bc4XWG9
c+S9S3+y4QxWVvA2PWAgUUhqt1sYInAlwhSkl6XkesHLD9M1YplPvJDmov2O70sRQt8pO/FjIHh4
mGSWz5S9tq0b5yrPX/UruWCfIP4zt7p0W9Iiu6E4Vc+q9wZiVMEBuD7hOVSbltZDn0cb5ol+a+S4
mBKxx21M6Ak1qjNbc+bw8WAZdx6u8gs6E/fTAVEn90Z+Kr5VfIubb/HBOrfL4760Jk/IPaWtebED
6STx/YTc+u003dYWEP+2QdRTSXF8JdXcPf8p3kpxx14B2AZjoP5U6ZOT3CVmEJI69iGESwiupftz
KZK5bByE1TGqnFOTeoGvfn4KPxAIKgjVRBgDR7uFQjUFrr8f7x3QGwWMacytQMw1eeza0ha32K9b
DM26nybZuU0by51DX/Ji6mooALTWVqc7NYqXVoU03PjkrAW5zzlHULbuJTbET0awZoB1jIQ4wyNs
Btr4fjF+1tLTsj4vY2R1PphD9XxpJ+S0odaotskCVC0HP/FcnsYa+O04BQSHwVww3fxJ6dHN3xxt
mINi0RogqeD9qti6BJfsYMBLR3gUrh1+KY0bP5EIQyPZlvybTI0HhZgSbOTWo8DpHQCVQDcqZS0x
mbB+HQlJwUxvXVRSNj/3pdvkG96tRU+qznfLRUJe9j79aBuksDEcEPNwx0VAE4xD9LwPh9VdW9jC
SRbbhYHcX2OVQ2AZSSJEhf5BvNPrzDglNlHcVeqQVtzs8PogzJ++vr8PF+TlzNP7CxRIPjd4yQjG
8MXz97wzr5xto2W6mnCg7XFkhK+Tyx2+UJrZnQ2Bw5t0GcJikn8kLnjVwEQl2ByjFO5msIpbmGtf
1c2qjEQNcGuCNocSVCVFcY5o6CqZ16w4iTIn2pcnBVW6likUMK7hjj2m6+oIHfMT31V3X+5xYKWb
47Yt8e2GaePgLGShMsuuxkaeKlO76rGa20Xn4zlvf0yG8kDsufPt+OZgSxQEnMAynrnUqAISov9a
fKk8u0f/lizi0jKvuYP/mMXVNmexwMbY5YEXcG4CBjt9SFrmnQmQWUOgKBWmDi/JdZMfp2FXGDXD
vOtfWhcTjRF7/cEgaPRAGRP63yap0KUG3ThtG8mUPAk5akGwTHdAGL8tiVaR83duT/AXDJLnetMW
yJgk6FZqQpPDKgHuWclrWGJiom7o+1Q6CYsxQFcgQEtbWpPktba2pgGJoBxBbOHYlgiFC+g5HoII
i86DH6rDJ6d2uHBfqffXCqomigEmpDkPkL3hRjHajorvfS39lvuc/s9VLBq0AnDPFz9m9xEX1I2Y
1KnSGdWaxDOVHf/050U8NMDz7abagg44SCSTOyTR8YJub0vWfmYyy1NZF9c466njfN+sEk8KCSeZ
RvX42SC4U4MJAanFOQSzun6hF8jniTbkHYVmzj2dX0NS4ayGjODaFJPfywT3Dkj2QPZbKuTprAbL
WjsgiSnPgwRftXywPU7PuU4x299CUz6ywyn5TDmSl9N8jSdd062TtZ84PATISVVZ9kEAigO861tk
sgsyrCPWvkCKr9poZZTciL/uP+EINRQuf3uG0J4IOS+SvAC6EvYd9dpwqUqOr7SKbtx4CEwC7JYQ
8VABySrRmoatZ8vb9r3CZ/8Vx0soTEwwJroNlT1fBc752xwFNAkxr+xEJe0Kl1Iu1KUljT7Q287o
V0sfNvtYMgWg3q1tbscV/tp59qzCD3qJdxIR4uv/IeRlDJkq2qR7VZtGgNr3iJSvS+8naM1slJJk
Z0uhhPD5oy03fQ/TJbZkVj/Dxpn/KqN4S1iHK+8NhH+s+S+5LlmiyLM5B9smSyWwQHS0FPHCsCBm
IC3UToAEWw6UMf3kcSjAMLgN1IspxJCVAGVVkKb9o8suiYq0RwhN/efH0gUDyxXV/Nifa0JEDn6m
ZyY2nvIofZpq0FBueDZDbismkwoWRtD8Wqz+rPOcXjgHWWRUcI6rvNtOV25a+SgkpZmZW14Z9xed
Q+LTNpdwZcIS0SipIRl5/cCFxn4cYnlCzHEo+jVSMQUT7/v8+bRxhuVb7CHMI/WC8o1itIPbvpxy
Oml7Juy3vdKpWEmqW/zzBI3eIxhSzZgTugYoStSSY9HQP3l1Hva/c+KC9LQyC9F8NSBiD2bMvkDC
8ZDmWofngPiu+N3C1nbwndEHphdrc6GtgYyCsx3ma3h85hrmfDqdLjMJW4lcIcxJKhA3SiV+5+me
Ek8xb9PV5RuXgKfhUK3MUa63LcWV2z5wb53XbEPRvtp408TyG+blePGJTya0kvoFq017UivioHZ1
fSuK55Gqhr7UogaAm+nwS9UL1IZyNmPDvmthUmclG/fcntqK58A4ObS9s4VZDzLqenaI/4Mm2iJS
JDrdizUsIR9wwqx/coTaRR1gOH7Pa19cjNgWctfA7+wRsT4cluSPz1d1ygleVuiF2nz7+e/274ql
s/FzOhbLORmGe1u7ifPEcmfR2FX/5y8XkfzaQjzpd+bc2tWRhyQ1HIQMNIfRM95GQt8kr68bmSwX
0RhwndVfsERpwFJo7R8uxNyYdGCVno+UZc6nTsBZi4RDi6dx5jOKtD86DT2oQQOiaGkHWfTzutct
BzAkw1sN4d8AKEux8YlSIgqoqGFvghTn8H2F4y4nfquDDKPIsiuGmtw9JMG0pciXw3x223gCFadh
ZCx5fk5Oy4LuvR3EseBwROWwYCs41AhyQEOkNaDtp23I/GZqGsRbgK78PMyb8TV/n4f1o681x0yA
DtFeRT+b29Xej3TzbpIxW4JI5EpFKRlG5XUi2wz76NI7HWv6HKj+q0nr67uPihhOy7KpHfHiJk12
MuVL6kOZ0tKd+bcS2iLuc9vpQG5QOiRi++SPzkWCj9OTPJVKzBU77Tr3MPk2ybbiQQCGPTYVTsWx
h1nKC3He1IDtOzYBm7xkHbSWlsKoymAGgezUHlxNbzin96sEtlqA+eBGqyeqUKbE2+n5WnXwzf2+
OBZ0Wo30CsKFKDceV/izLfLXGVNaqGos1nImVEfy8j1Q2pvlW1K0nRjhm3Q+T1yDaH+JDSPg+MRl
QY9cZWurmrmw0bTcGA3GFtk+kYZ1dsQT41epNYh96eN9XitKlhOSiV4bmpd0q2iRflqxsrpjzO+U
dScO/PsEnSY2f0LqOcHGKPtYK74GXXwtVBY8JWC5L62+Azou2zkckYRtKV638hWYm/WJ81MUUMac
EIWG6pRHiE53G7weZwv+jrazsL+Jz1LziMHiMtKYWNW5pKCfmYE4/7SBX/ZjaP6D/NvhKe0jbPPN
yjKS8cLtOH4Z1z7D5zE1o6NR6ORxgBaCSgmX294sFYObYsrQTRW9ZzKCX13Xka4sdTaitoDgcMYR
2Ax6CYbp3a8MTsNRglw6/Z2tGThN1NGQJhtHeLTU5YwNbt27cqru5AfhHMml/7bRWxVT8CvL3dqY
KkdGlH0xeZ1zxvuy6pgpKUmWJ5J9G+VUgpxa4f0CeHmuIo8M8c8g0mZ3C/vf/SNNJ78hpXQm18Rz
4rXZE/OLzRBbKTV8o4KN/iQcLOAPjF99N5ElhShQHeTOcfe+Utt8A9HVHXdlCNMPZqZXA8eZ6/lT
Lbv+4bCUoZ+HFjG/jnez/2sSbpKp2QhN1AER89mdQbLI4kCi1lQKK04sMJr9iTo3anPg9YQzaHR8
1+kRHEg5h7U1uExMxcVyiiY2rWQLc3mDp37Cfzs9YCpsQAQ8VbnhaC3uef33svl0UW74/fAKyhda
PSq8bGE6grAlKon3odOzoVLoRIO0i37F8biDmhwfe/w7AcK0JNaN7aRS3eekDy4w9Pp6G6u7C0E+
xdq++l/TbwLhpOWj2Ogt9sjuqMD3L1yZCUIcf9EEh5YTlHX4GNzeOGKbypzQItopPZl7LceF7Vqw
Qq7601wLQy6kmJCIfZjVusZ98brePrFjx/qy+cnwIzmPf4QofyefPYoD/tK0JBaK/9QzTKtCwtG7
z7CHiz3rxfeC05KTnIzYtsNZZjrWEKNYPm6TeLUoKUIJ5ypUlO9fdlMXh9OKfGebrBev0HedgN2F
qDIswDYhJAXwS3CySlUK0tSNgkv0Wxcmg2fgzYJV0DIIemhuwOlZl5nDv7gINtpehHCbz1Vy4tA6
1bXARXo6qKtFhkI0og4Qnz8hLdoOCmTwDZF+QizHhAssp48cwZAg68xKuYIXLr1KjEhGKtw9YvaB
ebLYNbScUydoZbOBM3Xl/q6DVWW7nQfvxdpcv7DvVHIRBvtxrEbaH8APBrhKiTE1jSenWi3dQTk6
8WWtqF2kFNPixzFgeYrCDQhBMEW30l7g8YzWpkM+basAkEGuQXdHyWDH/Zyyy8lqzmTN+Owd77xY
/icgU9j0gf4K8a2tVAiE7jEZHPuyGRje63RygWHy7DOmrlMHcO9JBwVNoU9LOHMxbTwxbo7iCMnn
En9ys2zgvOfgLNwqW7pYmLY0rIeB/Laek67DEwPPW6V1bNb4OxCjrxQqwejdLdS2nWM42DcgNqen
Pcjka+qTlEFNOzY1ZvxUX6IEb8tbJ6wsbtuawwnFX6pxbOIx7Sb1ywczKh07+b0BRNWys3zCXJN/
Oug9iWdV5knBmTnh5U6pJemVj9jftQGRNCmgkkFrV93F+g8UHCVEpJ7/9T2NN8xzK26gF6BtDXzs
zmOMZZbrN/q6atj++AyM6OKlNPc8iUpV8550duLbcEemAoPOnu094W6uPAumLRUUvrlsyj8fdHz4
N6GPc7O53tfI2u3bvQJ26Lu+6hkkkagH88Kq5DjqrPwmrwIGacerIyiURruYx8frWiAss7jnAoN/
PuId8nI352XK5b2WOpvX2yEbRvrC8NPfvkTTypHMgm+cwEjDGHAz9D6BFTfwD0Q5jfzE3KnjXQjY
mHWFD1wl64k6TNY4Be9yYIFWE4x6Q2WLg0e8Mp+ZdUhIkDvNL/m6ZMmcNknKhFTMWisMdF0b7oLm
EEmTzpMd3qj4Oaw/G3+Oacm3a1WlIepMA+ev9aZIFIOvPoncpF8hjbPW5JP8CupXOgyXiIKgyu/M
X+I9yEuA/+TxSdFWYUyvzusOoBGQKWPcn97R/tKGLRDpb2tTE2ZA0X/zjtaWZ6BicRZ7CzSJX4Ct
bCQ11l3g8kwpNwWNMw4jNpGCebwk85fXpFdqGyqTDY1dp3Em0783k4rv7giYVFhpa+qyAOqakpvR
lz0OmQV76yygXG3EwO2E/7lXUdhsNSO0CzYvNsjryW2Cd/7hg6XQR4NIOezyxYmM7rvBrrF3hJrn
tr7AA8+Ye8xiljZ+8XEIZESKE4Jrq+qXDkmpb9rMEZHEZ73qTtPU7FrGrnZzdp1ZPG5myK8CE94O
VfTe3Dxs7ECFt+DGMhWSkSVql3j9mrlqUIj6HPNu0NkyysFIiGke7Ef6kIIJQWJaVZj0R8Kfcl65
CvsNxLh5+bBJOJQx5gnR3gBNczxxmu9NuSDXmVXc4sohECHYndGulH9U02n7I/Awk2yHOsmyN+vb
az6yKn6jz1zDtqq0Q4+aln5tTJNYQ+ArYAUG5dhOR50XYMNY4VMNln9dDknE53E10pGGTPEvt7G0
GsoTKAK46bv/MuAzXsUshDSUsn6yWsn2Vam9btjkgmWHCSxVmR4RQsiu5rZhthFY5WW3U1zhliiJ
aT4+ZuADWNz/cZVdmS4lxaT6JxugAs7VBMCbT4FA0WcmqmptiWEDgYfTAHOLVStHDU52KWdbER7+
JDU2d9+Pk1wjnDW/jCgVNQ8wM7MEVYDJIVT7WbzLemlA/zbjNRLjZo3zePVwFi00FKFsYP8hIU8e
ta2RK5vqED5cLXd1VolQsJUzkw65EsUlHMo2hAsub3UuxdIk5aBlocu2OWlERafcpmlZeb95+9+Y
z6In4Ob1sl9L80c8zRmdSARiEpw0Z4cWojpjjseJ5fRtwIU704i93egLSdIfBwUIePrjwWeO8Hk5
GsKriQHbEzDmhwEktQKDyLjTyY5ia6GaaYtg62LiX7016m9jYqZ1xVm2JkKj1UR5d9WXF6Ehu7a6
DyginRrF42CfuqJSw+JxVeL50KfC++9Pl8TA55qxsXFq94rJtOphAeAGG771B9946w0Qk5DUfj4f
w60KSj9zXIlubH37uOyLLwgn3c9TVMkIoy7Ue7tAXbXR16rc8/F7Y4I7ry+7tU9KUAbGpTOlJxR4
azdC06e9VKNDK2YFI/8xnZmRwEmOsFGneDPCnq02s61y73Bgh1AiFwzrPg4YcuYBAAdkWups7Jf0
+mpALaacmO6uYI+LHCjfeOR4rsR/t45Pi4wUJWrL/EYHojENJWlTF06TtlcUbyQvzr7jGMfbx1DM
IaFgeg1hcgp0XuIwTcEjdw+W7yt8MUn2zFi7VX2+PIfzY+XJKynsX2g2e9guZ2vj6A4OAPMDxmxo
k+S0Mt1zp4sAMKWiXZcgGnJqOl+EkyymKh7j+A3+gyQUlfhquIq1ljZEemFQ+DZkTE4drZ01gG93
VmJEuaf4zYljOqu0+BUZEQOE4pUriU4/7+VKqTGxXW6DHG6M726yL28nbulOPRKLcqV/x4UzX815
4hAnfFxU5L+IOnN5Xm70K1Ui4R2u9XPnMwHVI4h1nW2zUEgyGDMcWRc16ry4TaDxlGNQ26VpO1V7
1ikwqqNSWcpmc4u9L/CPX/bR084u+lUUzYhgPeVfP8F8VcbhmT23m1ENv2X55VAk+pp1KrJI1VDa
XtJtUjC013WRv0iNOiTuHzG8SXYK7h9uvf1vP/LUzuF2n1awWpoAQHorYO9zVcN+e2SV2F0mKlH7
2uhjk71xcqzID9HSBRutAJMTjgU0RGGp10sKN3a9ynkE5Q01MIrp0dRKuD5ro3hQtQdkdPrXKZgi
JWe8QBPM08mOWeXjy1AACqkFt1THu+7MjClxdopu39k9oG9HCALL2HAmq7qnsbVVobhbUcyx6lD0
SI12AOmB3g27fJcgzdlUQw6w7dRIH0YzK43cYyHLnC9sbbRqe5eG/2p3l4lHWpsohoqmDeBDuJ4R
vBeJspUxgW342DZ5bk4FFOv2XFZtPnlEPdcl485Wxy7oIKB8bHPPyd0QofuyKSU7x5AJLwIsB9aT
jqdb1FGFIyNJ2N5ucEHCUaTfRO0PgFTO3mYwXqe7di6gRFHxZtLD0ogBxfaQ8/jFdqQCMLFmETvP
HSl1WFzDTl3RiE8zwbhMvtbt0l1Eqeht4caJbrYHeLXIUrAaAktjEqal5rVVwlxhXc8K3n5Kraxi
O2s+6GWkR8v5MHKj4cp8+y574HfBHTAxTQDPqcpOTFkFxE8XLLXaudd2vmPaQauoeJPnJAjQwFXG
bDq3d+ockHiB6tJatYio9nP+1zK2JzVza2V37H9Qbk+04+EbOxPEouQ6qmmdGY0HoeP0h4w6GLa+
Ae36r6hm3w1En5d2AKm4CL7Ir08/aqnY9iFB8QGBEsupGYAZHwRBEvvfhaQ+Y9n4TQop2jvDy7SH
2Dwa39L4EywRCNsrcMQKPreJcA9T6bJfxrdmW9pe9XJ0GmPEr49v6oCXiJuY21/sDzAUd6ca1zJB
uyr7QZ80xjG6rOznLtDhPggSS+jz5wickB1tKHorBLCAM+2pnbhxQw/gm73+KozL7LcdeQKCfrdb
F+L3CScadTF2ndkL7pcbDpWTS8mFCf5mT4+UQpq5AtPKDp/ImfrjhmnKaBTxj/T0NBNpkttzZn+P
I/NqBx9kEIAAMJW/ID7km3v3QOhO8H/I5SKikOD3UO1FMg5vMdi0R+r8NiSrZ7XzBko3rmOFJUMP
JEDPmktp7TVLsYxp9qfkOhkQPcVWWomTkTPaR3PHGp1iW47Pw97DIMCyPPWXoJrZSkjp9wvNTJqw
CocPAhRffkfu1XVQ74GOw8NOYq7R8CBG9Ps0ETWvprDOJ9y7jUxz7rmpAOewDmfSsktOWs+rTr9i
wvQfNp39JW1+C75INnTQjslFKjpwlIqbfmbXmVU/Vf0BEENllYzjMtryaVNADObEnf3zA0gwDPjt
yWkfeWsEYiLZKyIcjSy1HITc6PCZ0+9aBUlAg6sk2cs31D5BJu+MYOxaqC/iDirFTbLU1cfAsSpz
mX1gO+1FAducj9nwRfQBn1RfqLiIody8juZqTwo7w/Nq+hZ6J5YFP8oamw0Sxn0TiNeIn0esvIv9
q266ZMHylQC5qeSQHALej3AJqmDwbMEa7ZcMc6js+KSiDAW2QCqyewvjLKIfHCdkdlNDdgBrmC8E
1i7dDcopUP7RZ86w3A5kcG3p8EZEENkJ8SIQKlCyVbBCMQK4LWD0lITGhAOdKQGTAmehyGapyu22
/0FHGcpLlqE2GPeAaNRXUsUik5RqcleyuhVMiO5nHWV/vsUutd2Qob71+k/9wnGlKCDvGoUqNBv8
SQ38FhNSF3lCwizFHKpPeZFK2Ms5Ir5VM9snWEXvNwMmXcu+/9bVfFAMeuYAQc6YpekFDpt7CfCO
jbGKRowMsNT1KkhoGXz/L9LWwUblkXPDgKmBU4YA/8ceatLV0I86CBq4QQFtvX2UWH/YK9aCk07C
jvnvTRoDqReDPxXlLGIW/DcXlyPldzKM20xt/ko10FY7kIokwZ4n9HC4+C35p989KJvzwUoMnoBb
BcUERTrNUh6hLbc5/hPTlrdUGhMEf5W1KTs6L9xBG1c8Kvlp3O9iDt30H8SXnS7pCrCtg6Pc0cxr
Am63Cfv+IT2BXqUz/elv7Su53fsci3mjo+fmWU2SWOksvGYgAwJ+ff+r6Vv4+U3XI0qWP7mWEqcY
wT8B/Ei9RABEPKsT6MSxiGCY2LrCb9l+fZhoDBJVH0lBg/Aad2A5DoLgysG3WpC0a97pyIz5gUR8
udP/Ro0yWKln4iBdlkcIkBe9zjxhWtKWmPxavC9Nn6Cof20qsjNSQY2EM4IA7xM4Kok073BQWF5l
ldVSAGw+fk55ugzeO6KLlrE904XQLcyRUf/ZRrnCfBNz5ENaFno0dPduobYBo6sXT3jvNla2vaiF
E5bU9/6OqtgYjDQewGcy2Kx1IsVQTeg8tmIoKRv9BXIdP2QzN4Z1oONaZeLrrR8JeO3iuEjObI7A
CxevMZmLG7eNG1Q3WSB3eI3iiH8JfDQb6EnQ5/N/asi4E4HOHS4gC/Aor+gTZe7Dr9sXkhtBl0Dk
+tSEFKWgDwkF0kSv26oE46KxEwTMUh1dh32H0SE/7XBZ05HdLFpzWKmWOcx9c6BR+ByQaJpRt1yQ
cgTzqDNvDE98Olf6zgVTyTH8NizzlIjueqgZh7OG90/poTrqE2kMuG41sOaHQxj4T1jHmhvQwgSw
EW5I5Nh5r0hulXj09EiKzRfDmmqJVV7V9QRhePx8kCZ6vMx8H+CRTKRjcBCKyMY/oLt0mh/5nNW7
Q1H36JpvacFMvDK8fTfQF5nt/fyv53+dCmDHbW4VSYc/ov5h9YPxPcO/jtaNl1JJRmp9N32kawEg
9/Tc8DteuPrrHcWcyerl6fQzDrw9txx+6Cf+5+gUx6vdQ+O02zfAYRUVul126FCNEjHBy5MBAGBP
f8N/u1LC8VU+CM1Mm3e5RE7YkqgDmV/AguocCkPWPxzLfpghTWLU7nANahYrl9MluatM3Pb/sRVZ
s8AgHnSZ58wGG91EE6D7zil7f4ovyaBlgg02TufpQKvuwOFXCpF1kmwsmdvSMQ3j1dS2UN4neKJ8
gNf9LefbfIG61dYHQisKSP8dsYfJyA+KL6cKUh7ENY1fVHxKKAvXGy3S3tK8l00u1Fyi3nNnY3gk
5CMy49b3cBg8qDjmsIbr6YEtWPN3z0Zo8jxrCL/7JXo0Rx5l4KvrK9INza1bOhpaBtIfHwYFDBlE
IleY2I/LvYeYF6H0NpAypkTks+kH9aKhK9R+HumfL3WdbNi5NRqYzlg8Q1E/pmO20e+vra9unF5b
vDGjjtb42nTx1emnnvqXqHK0wOpdxMyiux3PWAQafouDru1ctOQOX8h6y5jMNrP2Et5jCUagfuEB
/gs1heduLisb+fWvwEy0oD6UhO8TggkaFynCzinI8xV9zItGMQCCb3tLDlmWKTL9KMPY83xPOXG3
j0HddnRhGRGKRa6jbtLnDzoNburhltzdeeth+sBOqFX1gZz21Ks6NIOJm9I31HtRbGmRJ54kwfz5
ZtI45Qef0jruvjruXalCOtRL/WDMx86xh5qRipO/9K0nzryUbPjDl0FXqlRYUV5vr3IF5nvt9E1T
ofZvQi/djdlmxnEfwIxOmNcNitnv7Jb8XSGwsstdvB7P6ChFMZ5QIqSpIfnxHD14Ed/X500HWWRP
hh7quDb8cedxvPGjSAM58sfQ7BSJGTKRlJEB3RvhpZfQbZNlHilKyjsbAdN/ctcdqhOQldFUgQaK
NzxEIO7xOi+22kRyGcCbEmPZENw98bB8FC0AajvyN4ev5+9yJRACfK+huayLcT0I9ZvZkQ2FlinK
WurXR9WJ1L/YNsptbiX60ivgqk/dZzpbIDf1/bAB9bmBaDN/37qSHDkW4u2XtSEFhZ9BHzi/gYh5
gNzCzV24RIjA88pTHZguyChCrA6Ma9fJWPAZCI55+7dd2P3El8+jXodANbfkVRH1TVZ7T/cnUt8G
/Ke9v4X8aUQToW+G2dlKZsnqyVjqa/EduWrWcOKTy3IqnHiZ9NRXFo4dSQoJzadVzu01+rx6pSJz
1Jk/d/2RbuLaRLNzWxBjEPbsgeW/kLwIABsGJX+i2thVRYly+215ITYz+PSbHDodP0JCgJGOwDVu
woiBZPRyJ0oC8UqnJ+pnD2MEUNk2lZjmz9zzQZ3s3eLoh5Ur/Ymszb9qzFzZl0PcgN3bGX9+Dapk
erN0KFM4ORIoXBa8R71i7lZL8ZeRuoiIrCQhhdlfzTwwaEv0kxZAnMWPHXJe2SXV3K/kqR61sv4f
kpaw9R6WL0BBQuNiE1GunO8zYqUXX18g6h8c+VrkZOlJnhoTyMr4J22lKvDHlhjAEXA25EQ0E5lv
ZD5zk2/QdbWTo+OYo8uGQ0MBeXRW/8A00ZrWMivosQWM1Vtc0DsjVEa0HC9krTWvJeGutNeXfb3C
Yo4Iv5k7BwcZCRVhGuXrUHhBOx7+c2X8dBewOXEWiLeYGQ4lEqU9l/SmZHjWpqYDUe0OjWNhyZtd
apv05T66JhzNXf3tatFazZojaqGwpax5EopQGkc7GtFXf6SNV7U+r5ZCF5xjzXwnUJQ9uW9s/YEJ
kD3lsiUoofZW7IGyS5V5xT0Vq6a5M8NipcL8AcJXP8UMVHYvkSIv6Fw9mfAHTxG7j/I0eBa3fXyk
yBHqTefw0GT1lUyBWcmrlrduEopz5ff3x1bDhEj4IWE0fv8VEdIA3u+8sMmPbMvcMzQFQMAmColG
KntcvVhAkrGNFu/wz9glT9hDOz/YOL1nN4twkUqH2D5n/+CyGfYRGzC91YETD3wRprsChCBNOIIK
LeoCgrJv4XwCWuOk5b9h4W1m41svN+VHtrxCRmUuH8JXAMgMgtwNoqynQy3edWwj85MB4WCK9/fj
UsU3/AnznjxNB4kyge621o4qO7+/dnnxaIcxKEqyj5FPAQ+lIO0r2pmeNyIajX9FyC7sjV2Jk/pF
aZqR7x5THuRgXiPvoI93Gn/OYiU3oCzSDMsRrZczAGtkFGEndj00IvLRMm9CIbvrD16d/Y3CtNjM
MDG45/J1uj6lEaWn0lEzIvCQM7PJM7uliYv2O7MR7Ljult9FYakBMlLUg8sj+CCyj4l12Z5KibN/
uehUtKRgpDkEWJy7hZWnRl3iydzZSVJjRXpjlcgd862Atw4lel1oYL0dvqi7nUDgbhZ/CQsxbzuP
VgssNZXQ74fQXNFA32ES1mtU7m/ItcuNXw40WbE8PuIx623lOqdugn106FQZN6R6/+gtTdQxM3Lq
7eA122Ur4I2bfkbfLCMBjDPaG9jCDzuDJdacOVYKiiSLEzabZGUKsEo6wvIfjuIZVQ9YIlg76RFL
KRlQDtotRHGkdG0/GcpqVQrEkAbXFpios4yh+mAvJc1u8V7FFRtsJBZRnoR6a+0OsL3rcLxoxeZU
8YUiaFxhW0Lujd0bbmOd+efFzvVDznhcVUNcSOWw/oMwJakna/GtvmLxYvmV77xlua+l2yVLLUVT
AToQsU62zFAqVklDTIaXhvSS0FuwqWJb6A/PBo2nOIF9hhrsaveo6WtdKDdYmpKOJscgBb3sgWoe
9q8u5EbIh9sKNMxjRKjnirHi2E/NY1Xlt790SAMweLS85glL8qtoMG/aZwEgnids8a3JdeV6Wg2i
dto5EAQ2nTQVA4qk/ZxL4BmMUlpKOWnjd4NRZYgWtQGk2pQPT5QKDA/KqVhKmoX7X4Did6e7wtPN
yhJBYglsDAzNCD72iKoBpzjIrPfLqvr5t7PmK++mmkqiPkMkRdW2XmdwVn46MPmnA7jn5azmtuLY
MGLBZyzov2KHih9KqDGfEhyfpmdXS7ouflITOdT0IVdCE4gdfnUuxuJ0bPN7/p4UdAbmfdaYjO5T
x+9AC1E1VOGeRy1rFJw4w6oGyqe1N6KNtTapQpawYJx8QKG1JrNz/+sp9cXKhU7crsidJztp+DVA
YRbxT1izS7518NWbIU8t6dbMQ0UFpUpQmscJY/OC2yafL0RGGrp8JTe9g5kkURrNcSbkMharcgDO
Dl0T/k6o2cFiHhVqiAoTSICbDIEQex+HNf/JqGGcL5D5Wr/XCQiFarhSQtjbuO4D0XZ0qipOUfoh
2ZU8y4iH9Q190hIbB/CHyUrT1TaqJpb6ZM+6fVhU7O0EHGWqAr7pfG/iKCQvFSRYcBVizTrBsJ8C
zvvRKnaT9az155sVXsA5v700rntM4nIJKf9MkjrGVXx+/pIDM6kD9CN32wl0FXT8mGluMNaJRN6o
iu0MvyP/gO/tBCxMNvG9q8ZJh8clRrt300QN5j0GdZx6/3JN/CRrquhhau+zQguAYiLkuKbuQf6G
mfhHjUAikhW40EgEVk6V9JxgQWOufISgpkLwjYuePEaBKBupJVuiF24bD+XSof+G7UC41LCpWkGV
jxYoG1ltW92ew94Qmc+ausrMDVjCL+IP1XDB9K+LmjMSDa8KdkKcg77rLZZQTw1xP6g4SvELaQvI
f5S8M/W8ae8aoS/JzdswDi0IFm6TDdYa6TZWXBX+bFxb56pSycxAVCHJL4QdZv/E1glFTm/DEKFU
FCAYx2h0K2h/nYYcKP2sM+61dhxU3ouhR5LnWWfkD+RXEZu0fVgqNroMKbZNIkGbjdvgJCcU9o4Y
1pbv7xjub7F9/znZblZNE1Q9C+b+u2gQI1zhf+RNXYWOHQhGMi1o9AFABhknmTRi9FEqJXUaDh94
Srk+KRHwRRB2tY7hLZAny2kOlkZQu+Fw1HU5Wxxjc2zh3x4oFma7aqWmy4MKpSNRbex6dqvxwjHU
313wbC78Cq39qSHHDHod/ARjhBScK5vUvae/ft1JXkpvMF+s4VPpZ+WnwP8xQAeqig+eyKA3gmAH
8S3deXf8GmToM65erw9ixbpH2iE2m72Q87Yl1l5Qp5YPffbedw+kdRdEP+guXxTzr5zMdxkXDJ+2
n27Prio5yKTdvMPEy/6vNwlM1+Nd06M2QiDnP31ng0ZLAGkMc0rVlzkGjTwmvp4kkRa8y+9Ljb/U
31AB2isWMCpWDXuX+WVfFLpTjBuek+KvrLnAP2i1LLE9SBVo88EMEAhE6F/4cM7nD+Vq0OBIXiXs
E2TU0OyN3q1LATBJqRlEmeG/w+Dk6hjg4SQWr2qWuGppaGENEmOuKOkAMQ5Bu7+WUzNtrYbGknht
u9MJc6vc2a2blZPi+8GYnhdMNICvfPs+SqmxE+zusSl9f36hFsB1YjbZogYIw3f1pFl5ygdTvzMl
GXfPBlfF2u55zpDe3Rq+d1Ci6zK2dfuXm04gLDFGszAKMW/dVV7Dp3UYedmIkVP/5p115BUx/4/k
aC3HqFiPVpMR5vOy1h3DmtAlCjVsgtp9WQHNIanH21pPZksPdR4Nw8c/1ZYGCiGReqG4m2OvU751
k3hT2dyCcurh6WkAcOJ3PYvg/Oc6uC7WYgd6xfi5cqEBTRtaQcsByzNeyjsCClA6OFSoyhlj96C/
oRqGynUW5mbM20i9fq+XGjObKNyM0tLHmCeUZcotKX2PEXDf2v702gMmoi8YnPpN0NV5FxMUvf2o
hwyC/AX4q2ScU1ph3/exI2BnBOj3keIqjX+jNxst4YdC6KJ2ewbKIdyi5qIlaD5oLvn9j281sZrm
fyk/gnjIX5H3Hw2MZG8B8AOhD/BBmCm9MMvk32ozWuhq2EtyVzQ40PpK5M5Q/zxuWiGENmH+/1Cf
zuph6ViLg55M1ofmF3zlPQLmMRMAd45dr6qj1/+mw+FDpQgxBZoniRamR0RKQUzXJ/mpXwANrGLg
nR+iLFYUPk/9gPoXcRsl5juw/AoGEHAUFhYFOGH2VSz2bKWVRFlOJ/yEMuWd5XbX+DN4KKLMgHfq
ngCSEXuOhTpLszK5b41DSTEwyf85Sz9WoHC6z4UTjY38uz0/rGyLkxETSVxzN9B8tgCcKkmuj/rF
U71Uqk3PJl2E53HZTLemaw2s4erXZd+TZ/s+abTi1H19gHKCxXGwmhsFZm/ke8m1Vaz7feQibx0F
J5/v0ucrcV1pvSr49CHBdkhC6NzgpHPab1ts/TXPziVgmAV5VWi6Q63O+2SjSR6YOE/1QGB8BdyB
xZRiCNjWWRDq8cw32d3j0q4sXcXTKt6rj0zwvT0YgsIx2jJOR7b+x6E5HdWscONR7GKpaool0lnx
zUdNNl38OXypp3q3ktT5wpVsGpdNL6sl/Ebix0PlepT6XbsOlaqzIi5RAro8auFcL8Mh1ulQHYBr
G1iozRUcVVG0fjLL/U/bJGkwYxNLBlFOt3NtNvcufPJh0HfDdFRrJWxKUmkgL4N77ig4gmVywORz
j53MojfAR6B5GAuALgvh3LR+gtI6dC26SKJdTu7rOQZWYLZJDbq6j/x5nu7YuFze82ENn/QSM1Qn
bJ7Mrcx8CbtWwA64jsUgofdAF+HCcew8u/HTL1ibZFNbHTWVTOOl0luq3ebtTTcEtd26OoFwnUQz
4uOVlsK2WN4QpyuULabU40I+2pTC/kfEbSEVVNN7CHOagRW1mYXH+uEOK6k50sm9YSg2a40fazC6
ij48T/PMobr3w7hIm+78Nq99dzRxBsMFZZASknBqK393yllm6ynUO/XOT9kezsd1meIZxVEI2SJY
I4J/Zclj8Q1ejJ4tfr+MhbuQ8UmpJDSGDdG+k7ytGCVsTSSFqUJxxCnp/BMnu218aL9Ij1x0Y0kO
boaMM+zlLYPs6poVQZZ0URHoU03+hx0/N/mlk78fYVNQ3oPRBu40TLqNDZGJM7PEcVU+e7G07XgR
FoNwjepkKZTzW009KYiMoBemv64X/oCKwYhDVq3OGIzsqdT6ZDyadYNecTX9Q3D5Yei80G+VFht7
9NJR/c2RBXjVVG/WEOknfMVxfMvYx3aiyMdNHz7wxudgOgcjKDtTGnxJcEFwJp6ZmZeARwhj05FO
3xj7Bsg+8OAHwODqwI7XGdOGVGDq2HDJpQe8k3dXSodQ06NmNULUOteX+gzuB/m5CSO9Fu9i5mCh
Hgkc3ttEN/xmAdUKfRpgCuq7DDvkVbMP+mwK3FVL8Qzs/nNpWbij8c3PKnki5RQRKEIbYbBIS8OV
OjqZ+iXaVRGkrfriTnSjdqtPErJCuZksvI4XGWgo1sGiw7AF6fIDOqSN7yX1u3eg/B4Zch3ojhP7
GithoxFaFoEeFXg9z63oySD8F8VxFjJFvDWJ55oUDJl3FirxDZGh1byjA2o78SoCxtv21wn2JnZc
WlGpfkED1vlm/tBZrG4Rty9B6pDu88iN1dGuTqF25p4X0uSLWbvVh6O41jUSeBsyDz/ZIJ9xfw4J
aBMVOB9Z+fqatUra2QiyDHMOzHHa8H5PBFZWjbLp1C/rlljvusYo3qBOGnyJbspe2hCvp1uMM/Ci
1GbGQNGQk9ZxvJT5qX93/CQi3Ds1PFpIDCE5mqmwLzdH4BKzs+n04B2fa2BRfTx5a8hmp9sga4W7
iP4zkvq13b6dPnUtGyTX+Qb8yfZHSkB/L1yDrszWtCCam6Aeu4nPbsLAHvsK/Qn/gzHRvp9VoHOr
YyKQTzXroB2XPY+KSO+n7t+se7oNzv36bnRG1g/dw0Rl9JHPIZRgBm1mWrzs2gYeQibhnnqNIJG8
kPqn447JmLAkeOr8RipEo4E198O3qmG+0box7Chm6kv4+K1v6CoFp3Cq58dqO6pFqN69cmrNrMm2
0HpYOkC0ZS/fxjKgoXT+j7kUiNew0bjdyBGThdcac2aQJEyztqe+sdzWkol2cb2Xe3gdqFdtFuHP
8p4LJwWzhds5tDl23wgMItt+GY3rlOds+SKBvlE0VSuueoqx1I10YXjasBDIgrpqldE5sG8F9JRK
DX/7Ub7Qnxr372ytvHGd8J9jGPAymCdZKSEm29bIfZ1FjNUVp10wlbYkRr2QIjoT4MmhIC7LvTSp
GWbxdtCBNYtj1ovTOXgpvefZAFSuPeO/8e+JI4j/aj8p6YlH0daBD7MEW0lZCa47g0q/08UDxtaG
HJKIfA7qEg3/MyyxQ76bnOIhEyWcWSZB7gxm4D1NXlzogQTkThlNKYx26BCDdfbDaOIw5Epq0lMH
ZKZWbKb7l2bAyTkhFdnse3uRF7h3/70MG6iBZ9Cow2dk0gpx6lwbH8N1UHVk7WgDxCKYONkMlVHm
SbUwFq7NQHdgg7Z0H2eQGGHRZE3VIplXav22dCX9K8js0gZGWolDjbIxbfRQK+6sg8Yx5XYhDuor
2OkB31WSvN2bXpuOHd6vUcWPRXZhx3hkyMiSMjXVIXtr3LtZryiD15TTV5HMt/w8vKhnUTB8MmRI
SPIlpE/Y1uQBKDlkXCH9IofoDST1wgFIWwKLsY1Lmna2BxKFeUFx5kEJUSJIRMGCRenakP8SpAll
oDOA61YWnhCOP93mVxOPwaIcMUDPXlM+166Hl/HM1eraDy47iEaEuHVbitS1aVvzKlFnvteZEMUJ
VJV5+RuahPljAxNQTgTs4E2MsbrcQfeM47Q0nETMp/KkftU9dRab8TUFZL72/GUAPLDqjNmE/1Ny
IdZwM8bzCon3XdM+gTDIINzlRKStuJMGmJdboCm5ELDsMFpt6/lkBmByYAGDNvoqeobBvAPBymU9
zSqo0Er4KUPA5NVlHcVroZoaMjO3F6sUf21LIkSTFTcftFSlpeugRFgFpQ7rfGrjkKqAiFhEAh+9
1U6eeda5kwlsx3kmki8478c/VHHEN87VUo3KSGwdGEopey9YKruBRdMJgsesUVAyrmXX1uTj8+5Y
Ea/psoJJYj2kVdSaEOQOVLwlAGR379U0zAvDme66IINbbBxqxiYSjFceeOXezs9rST02zfB2HQa0
HUojaFiWKsGSaquR/pXCSahRqkYls1ikXBeSl8OV2nTb6CplBoBhXAVSaMBtJc4ayUfpJwpxfxzz
U9L+PQSOIuYx1GgbSc9gxadPLJGcklDs7rbVrn8mPXRK8bNBd8VRVlVuIkenrumMR4qztNQpQ0Ft
53EArDuZRTGPYNhlaJqhpvpKn35evmrjClMEd9TMPnCTFtQpUbBrZSAEgc4EBWqPodYKy/3NkuYZ
5X07iyzxb50y8Gjd8UsBKK/nokqSfD7Xi4NCst/GvjPjUX12N6gb2ck+1NGaW4+4jNnoWpQR0Olz
+17TZcUen9/S6kf6NSMnkot/EzpRzBG7rzo/3rREk3hJoz39mUd/dT013Ii2+L4qOoT/mQsUkobJ
ExvyAh5Gs/VubpSaq5COFC1LtUN9TpLLNhuPV7hiTPlMcexJFS4D4iHwloDVMR2famqGDa4SvmHQ
xN2ziPbNxG6fobXpK/9bqTwn58D/FgX7l0bc23eN9X7xiSYhYtllxVbQ6Ya9SPDN3U5xTiV8e9r0
FGMWVFJh50vGW/Ug6dPK417UP3d2GNmZW4MLeUWxSBngDwbo06iTNTMdwH8IAm7R1Vvz2Yep3gwh
EFCNWAIfCj8B9Zi1kpbfodKH2DlNw7LcmLIUoKm/TYHlt3TooymCb10x8by5eB8rbI4wiZZidyFI
6uU+9MBAlFb/bFESiMUGlNmXkdWiTaNkrqKJnfHuZCD5YhJ/2GxFJUduuntsdUef1RN4fT5Tk5mt
8SlCloFh1mtYX20IGvhSRJzCDytLd5ydJMVzruw6RVgt6cmi9BOM3sqSsIuiQPYBJVHQgd4aR3uv
DC8gVE0apAsmn6ZN1nlZEVv+dYg60+X7JrebhIxbQ2QCIZku90ebw+xobP+oldvQpHJLxpIMApC1
CGZn4WY1uPXeQbIBrhANIz6XZW0Q+G4xxxRkCkxcPihrz+j3hkmsclgEG07knCfbNFOysULlh310
TrNzXMdWrNaL/I0OdM52LKUcT268Vc5m7f8IuyX/YmNHfM6I+/ZM8C2dCuh0f6dySwUj3iNtIwGs
macxgIJqTiaMxDVyLOZbYieh4y8Om5WVRuBPuPK7W9lGU+ja9sBB5wEdRzEI7AkmeKWvFLg9KMw7
BwapDp0AiQZsLEFrvVsLkDuLU7v7d+/To0EAb1jtHAQm3znZ0/dDnyZJd70Lm7aZ8qMrMotBbQ6G
nxQ+IdeQQZXX9fau3I+SjDuazCn6xhaDv/DaFmSWyze/KZJCLSvTbnV+MGs4nevfCv598apEE3Po
90zaQMHGaOlowo+p/yEMyjFFGX1xinWYiRKyjK6k7cYozskd0RvVi4sPA+qhCmhc0Z0DVuVhz/wH
ImPWEnP3PQMAt6ZTmaQbpDseZ9sJEzhm3hITuewI6/fzG0i9TPNvAkQuUnWrBwe60AAHbOo9qt9C
PT5SZXk5u/1iwkGeUEiC2fw71zKxjksSx+GUg21SaOZTriudJeCka0h8Y6Up0L4pZv8MdqpEyCxH
wB6ZKDpYfgiiwn/zpCbzHD+SIkG4DoCaITSyY1KXJuEtyLfzjEa8VI0+xCg78pCtsXtYf6D2b+or
5n/qPtF5wZVNOpVySTfJEDQpstROCCGGf5O9NobHPWenLDxZFzBGKZZuvHKnBGkrL8BZrzoJFBi6
BdwHfElG4jH8jRWITn7AYIpPhJgC731WnqG7drW0+XXNnzRfMOPYb+MeAIgm3dNP00sE/2jwfRoo
+POx1GBWnQWXr504efi5Si9czzAZo9B3cOxCaoWy0RQ4XmBr3e+XvstBGFnlqNPQqKBDPE8KFy9C
oEQ38qwFFJ5V9GpDXG4XoAd3IcEgqNzzuGNc8drpfHXn5IjeszwSqGu08n022LdGfKQp1QgPchTy
ZgNFr5cUjmErZmykm46ltTXPQ1D0gcjskh6djbdwrjuohJCyl8GZcYoeOpjJRSf9zb3QZRfrmvpp
jc0uVraPEE/HNfctOtRu528NQoKHf+2ElD3FAhwQ1HZArT5s/qrm/4BClcWfjsSgmgNos+JmTP9U
4EUq+F80PhOElSgChm2s4O2I2vwSuP43iMPu1OD8x2TJlooCUVUeUgTTQakIbKX+NfN7fwMawgGU
XJgvnLWyIPF5R/1g6SvmAVI5L/rsGuIJdXluR1dxah434NO7flgGEuh8yRbsxKtxdKVv5RDOK95A
FuDFsonXSXfTuNMaEJ2YNg7h3vcOzeLVZWTxu0NElfjqYCZ5QqYOKLVMhfTTWdDG3LacOymcTJS8
3e0rkp9jq139qWlVxaoGu2vh+8N6/+W/NyTS+/L/z/KXGphN5u0RuvPGIZZeY6jK1ert6IOQ28N8
yH9Mz70yfe+CRdCJgIYFRaUEDU4eIX92aVXbD2Vrhc1+FYJXHdjoIts110FKy86XI+zyAQxhTI9p
v2r0vfzgRCkkUoK6Czg43aJCFyEE+RIzXhlR+jiUJOMq1jyk+XX6Oj+pSy6Rp2WBDVHqkZAp9Sns
AkApXG/ajA85sgBLg94J94AzJJEtBW0uUlkPHIh9ZfXByNFF6MN3Zs54D17VaKn9G273UrR9rCyz
UFpsyr4s6sCpLgL+xsWTcMqoxva/NhguzXhfP8ERJqlSvkBt4R8GMUpDCzqlpAlMsQaE4tdTIA9e
P101Yy9qa/Uo0CB6infhmSH3ODBw9G0/0tWgqbr3EytEVcDhYAMt/E2vpHJZv7aVnq+z34eN78HS
NN9aAxuvz3eLBVzn0sRK/PdvZ20ApAA4uXH+c3zOIhzNF1W1K7EqzAlYkNaghx3rgLGw8cIdeE05
5BJXKPTX66x4oHP2+rrkUDw9FDHvbaLvlxYg0AdouEE2ZSStoASF+jWrpJv4EmedHxGCPtFumC1M
+/XEmM/oF9gr1giJSzm6k0HqP4Q+eBb/6hgQShOujLpSAnBwvK1j7RhJp+ExkrNMxqsZCJ0wmSzh
tHWscF+HqD7sMeemopvghBQ3uJfL7F6ELWc8Axjfx3yoR+RikJ5RvTwaDZLdHzy1hF9SaKDqwL69
vqfFDMnlIUp3gCH9nhhFOpecppt95dVGL1QXvcnni4AEjfejLNmwXk/N0UvUw+oHOxp7EEK6NyVI
D+xIGzq2hYSbLh6NSr8XMDeDq9nyK4FhpLV7b7LA0bsscN4n0lFRcgM6a5nH9YZOxC2JOs2p+IeE
ux5N4byAXShNtJiAr8TRetlmY4Ppe2DBr2Wi1MLKJ91Wkx5gEqewI2mk0tQCckvM4hWE5cocalZt
dXZo3wxg3lhsCH6jsxDK5jfCacDtlfxNjFs8rhXaMEUUDhB1tHxxTt54wnYL7pLBLcKBJ63kgSUf
qLCmpmBgUlMRLaPJ8gOjf9MhZqBlQt367FUJ00unk84llHm6zm1+H7oCSby8j75vwQICU9QhZKZI
1dfmLXL9fxQSI5zfVnJj1HEomw1p6JcE2lT3z0SgMh9nKa2p9AxZA0yhNVfXIqIMwCFTb6ReG997
B1eImeW2/iFskmEETYJVA5mTCi/OwOZkjp1RJ+QiMrg3Z6y0Fq47TcFhKDzTtGOE82koI6lsL/Ww
oEUwFQVCXbNGMjv2sFVK9SQ2S+y7uSJnqUBIuSFm/rt4dkrAiixiNZ+cCis+Zrn90EG3SzWXKRRM
lrUNuYIlX0onfVpQ6RI+fBlnjuCuoSKrOesvDXh+kgjOezTHztoXD6wwZvF/GFTB/Bvl3ebBmHel
NlKZqSEryVCgezgdbnHRrXD3fr8T0EjRKM0fWUhDnrlCuqgaNfZla+7upFivwtqYAnAFTjR9gWtD
fGKMUoAbDqyTaqMWouVEbcJ1xxuOICs2CS9VL65qUcmhKV9aZMil7PeMnyxH1QIPBbKjLeZDeOzB
QSzVxKu0m64+FklhvC7DUCqSxC2iHcuYbiE+XAfsB3lcsD26kAoACSJYcaoT8o59WakNoQ2XHMCf
3XnVUbuOHqK7bSUSMCFxi6PyEehvTN6Aajk2EKJTv706GxPUqHArw7f+bhVQFkBKFL9LJVh0xJFj
LR8WCCZMi/4bEUIkwKdKPAk1q4e8LT8foxPVYv5r3K8DjetzX1bCAtzugmaIlFJhVJcuhdXQ1fw5
twEz6GbYOjtDMsW1Ls33S+fk7RguUrumYxKnLfBNBrmz0f0BAD8vHHCv7FQD3c/LgfpirWp1gUUn
XYMSqc52XkSLuJr1KsopMSNFYNsojiYJbSdvPRxRli/DtV2gyFcorWiOhzdg2Dm0YLhbDoKjBPyx
w2cap7upbIjZBMj0Oa4etRJR4ZZQxAaCnJ8bxabaLZSlVQ6tssiIjb/NfkgqiiA8WsPBwr4/eKMT
j5XRvikDCA7jTGwnl9pVutABhU9SoSg6ufQZeHjKXxINANygDYtXQ3P/1zZhgmz/jkpzOsHMht5N
xW22bGnsF8jmBU111J4MchpsOUSCmd3lVXrYMAOW5Ji6+Adn62dQJK6YIVHnFCAL1iefyjmiU4zb
aC3zoTuP9JSMAU7s+/6IKpumN/NcjlLkfFyIiZJXkSzk38syUZPPY+uH4LbPhaUFHpymY5J6tfvQ
0fLk6elsLsxHQVbq4zMg9QdOs185UV3u08fZAXxe9NthmUseVdySQdii2kcJh4oVZxmGIHCj8fz5
n4FYUDUQOzsxl6WlZCKO1Dj9kOmswbYhbQMwi44LFTmBmzp1Fp1dOR/LSxc1CPN6oMJHgHql2soY
nG/AtmUsJOHgofh/FRQMEwJuk8bDfbFHQDVRLOWLq8Eu+fDvJw61jjDpAfxqD1WrDN7q/itL1RR6
bfSVBFrWXBgcXNexlCYAFdjLkGj0Hp9TbiyNmTf8obKxnOqxtI+EXAoTysxIgWK2DPIohyxkNeiO
1TxX3XKcTk4rsJwcRE80vR1CQ39f3S15akzm3HyhxH1lrIdsF2FaFe1fosUla4+YccU1/UeEaZRe
eMe2jTXKTKahtJVQfKIePRQPVvMVr2JU4e21N7cSXUdrhbDoODc/MhbrlDz+IyGN/n37kIeEwsVf
b+eEIRGo22fRCkcG18BxACsaKoLefDBRJMq+N+mAK6E1KaBumuG5ZmkZPPocyHtw+irOEUQwqM2e
iCKoE32oe4kBTNJ3S6dg/aOFs44kNazih0cF1QDt/LQ5FNbZMYGN7vaV5lPyAdOeOxvWssEkI6i+
Wyns9LejizpZsTEG2f4jZXKaHOlBkCNJ9hBneUZZBDyKht8CQdYNjEq4E409YLGUVLXKaqi0oF7w
DO3g51YM4CaYy9RhbC0HaQ3P24pCY5IR5k9fRIJXpfpuf/3V7cSjN2AzdE6hwI9NJY+AtBEH5UqP
Y0NVlFfPKt8WDY5oEw1XXZSaCoJPdwt7Ccdkk5q1XZmNRglIYGi/CSXMkym2Wakx/5eRufH3yAbV
mdyWphPj5r/F365iCVhZkSVR3vz9O3Ajn4IEJZLIHjZwP3FQMAtykL80lgJxe0Kj4SNPEhD6Zd5C
CCWYE7qvt6rEHjHwZF7SISkvtAUV7OoqvRisAWhyVNfcrahDUPZfXgkRXPxsWTTVs4oYFXUMjjeE
pdCvBo/A+mbi9vGnAkvR7Y3w2QzKpyLAb/CLhdpNB5r11BZaNt+/qTemWRZ2K4mVwypE6eGGr81c
tGTyar8qarmeL2vKZ/6dRom256TFgStoCrC+UE/colUxvOaPNE0aj6M/yw4vxkGxzrT08scJvkbQ
IC8OniPI81pg/CtfUmKS9PThK+kuHpp8lWeil6fNvWWE/RbemHmQPKt7/w0oIjkaa6KI/HmcXuhc
NFyQIeHJiyatYLbq5MGL3BHYDJPCdp+pOUqnSQWlIapQ2L2B2DhUHtmkhaIQOf6uenSqdPuFqqhA
+i6HJzjmzPNpOfr44cWXhNTcffWSGGUTerT6/8R0PUDHMQaWOaUM+O8x3bXskaglxou2HkV7o1wy
mSOriigVK2y/ar4rp6ULcGCXD3yooZRMlY+/JzYkCKa3IydmXJSm0JKntAA5jnbrsgsM2l1XY1MZ
h4U+wq+kjY87cR6C17weiHKZ4kQR4cQwNwkHg2aBiEhTSus7hE0KBQAmoIv8oLzvyTWAVL5BJ4vy
eGLy4QNgs5It6PHm+upmCjBDo6vklaSAmhED+gYTe2AWnnZlHKdCU/l6YyAxD2LobU+9ChUT+6MH
YMbmgib8SggIukwtFkI+iqPhFY3NJoZ6QX7BDq2nER6bii7AUh92hLwXY3G7hUYWwIxJu2tIkEyj
RemT/Yh9nJ5SRI90LXP9/C8KS6clYvKqj+8rofpP5bvHwImbDfYsrh0dLmHthQBJqBVPSnMXKtYT
qt6wBb597Dy460ghzeeV8AvV23p/zAVHhMvqzZZntnNBhlrNFvdzkrBdxU2DMzefHKcgjL3rAJ8G
MTi4C7XTX8oWdjpIIZJS0UW3kAiVlW+4cYO0U1RtY5t/vjMhHuuPEx/v3xufCidvc7mBA/X7Ec/5
f8mXEvXvBnEMwJqKrGy3SbdZUKFbk2IB8JsLFFHT7f1woObMQBFryV1PUzK1eNHhfoU5j93ESHTP
zfwwawc7/zfg6mte0Hg7j6dKmVsuQ5uyaAgbmfmUCDwkZm6USPaVSssctEEQyMffYl3TxjY+5LtZ
EpNUfw84eglQvW7G1n3c9vSnk4Vmax2fezp7NQh4MwBP32jA7/cFntC9o4BJoPjXW/YLQhzGd7WH
mCq1yVyEEzi4vEIGQTeYIbM6V5ss0YTlaEaSymJTaPrpNgvEUQ/DsKoSv/1Ti7lsh9MYoD/CN9LY
PajB7kN3Ga7pRs069WK5aDoOW7KuIv0rpgOzQ2MQl9yBbn+9WxuzT5P4GkF6FmlEiX/MCj47qtz9
atFkgXiWsU4xyQLQSG7WaQosNBeE4kR1BmXv8B9C3E+izjV5kYZ0065m64IUniFy16tW0xXop+/l
Ikx4QjXEnzSDJ08ar1+o+8ak32Bt4QC+974DUz0Xn5wPN94qUhFehNX8U/KbTJTI0Mde1d9sWclq
RDGq8yIF4cX3lvH6wYtYFcailL9QWioaINjMRF90wYwD6dDub+8feqpSGTiYDTUaqgtw9+wqtpAd
Wzy9zPfD0dQpZb6v1Tl7sL8kZVYxBbn1pjNsP2Oz9W9PxW1Kf7RB3hjjiPsyudZoTCGpJqZrTBy2
tehA+autgvMmi06UHE4gEJ8HWHFdrhjBZCmLzRdTi7V9NuO2X5OUCE8cw2RVJ9screAOrJez1z3c
UhjBn4ILycbI/IATR/g6K3SS1SRp+Gd5VtwnckgmWo6eZQctkRp4EsDfVLM3tilMOnLg3qRrd0o2
gvnAZ1yKkINYw6QjdC0F02U188McHDXnok5OOkYcofFfPv7yvx3AlgiScpYQje6WTlBwKFHSvp1n
gvA1Qs4QzPbriV1TowrglhpgUUgM8dxtlAFqgL5iKM8t0KZpi+a1Bo8KQmmpOfsXETfbKV95rhf1
sjdQlHHplEO3V+WfI/hPVyNi4nuB16EBOw6fVD4PqM6K7TmOwPUf49gNUyYH7Tq36LEn7xjD1Aps
5PQeBKjWPYhOcNBLipoia3+0Mi6SHSTN2ryOPn4+77FcjTHRXI9JhtUZZKRtTipgSCiuPGUwgCrv
05XnGfUAQCq6eUdL1MeFfQQe5WZj5rVJl1hp5jEpj7Qr0eohUGdSpa8o2Ue27R1S0tCTM8nhDRD3
S5G/uG+7dL56L+kQUe2t6+OGtV42ZCYn4OHcp8LAvQt6JyIzJisYBHTR5Gu75QlRzhU9oRiVLnOu
AutOCQ7C9N7sr73DMcbfqds7vw8jFZBfgwf+vlrpVDHwMdMLixecEXP2dMwMDNr7qSU3eXpU1d+3
rg9PtoABuuLyf5h7gLTUr1EvkKI9KxPzuU3NC9vZQrvad8oeQ2DfKKg8pdaZR6XteZSHfvluWUhw
2NL14LGH/Holc7q1s6ZZb2aEvUADCesf1+SdxQC2LigEbBEAxC9P8c64qE3TVH8+dI1QifMP6kaC
IUCDW4QNeLp4+6XIj4O18QE2GfMxK96VOk+U1TRjD8SO1YVZwP42TScGNfxw0Wnz8CzTiygN4cFw
Y5fGmtn6337DBtUJXHG5GEmKZBwQe5MuH4rvlMgaea6ldFcF9N2RQMzM79YHIxKvlpu54Y5LPA6K
nhO2W1TMfxxxF/Fun/R9aIs47CIzbYr45DrCFh9BY5sokSE9/JO4GSn7EJ++7BhL7pskZCu1ClxX
vgGYcqoZyhMWTVGyqdI9ViDVjMDFbDicQ2va4KOyDI6qeNk8l0E9vOr/2FlTunSelN/z/pDXt5hf
JcT9aW58I2vil42qQbh0sDwbjyK8VZ6TwCb5hzbm+cFNdILl9vwOnFwSZmFqmVT0j0fcNlER8sBh
a+9XorUGbZSyyss7KdlHHcLEDfViS8cJ9diZX95RdRA0IcOb8ReZAC/firfS/RrNOGU/X63+huYM
XY4Zo5SaSjYKiWQVabdeSSWKt4N3ujMDRBQiuBszerhzYqIGUjTemWTM7GtqfNNX1SpIbtMIUoN3
6nawiL19A4qdOcsA8htVmk4xxBwOistAuZlLbliVXofJTS89fs9i02EgcZMWj829NC9GAjzAq9+F
a/cihxWO2OPul2TKFsQ+7xlIZ5KFFSRnnYGlxLfIq+TAY3fpf3QUBLGNSLFV3wlsAM3NOieRsBsv
GujtiO6vcqo9B+V5nYeeBR6/n+5p+0xSUoscusRQNKSOYTgESDQ/I9MvT+xYsTYMF+347Dp9BIWI
OxZvjfhjYz5+DShWHtNM7+Y/fswy4l1Ec6qtWH4FJPJKJXNkyGbIaMdi0clPVCy9/c2cgEJNNsnU
Xt+Byxjrs4Yt+ORhcN6iPQvY98tFq56EL6yYD8S9ZhqSIJ2Ix+A8n9emyzhEFJzrhiajTj0vIEmE
eJ1j2r853a4PTTcssrBiR2FHN4MAZS0oD5EyxfMi3TAbNelYY5gDeYyRLhVixopcndnKmNzMT94g
IWDQ/BiXF4HBpQ/22aYyDaI8JZDlCq4FJAOdH7CfdcVxqmP/06SnlrUGCbySpk4WbC6JiU/GLTnr
MISlLVan9YKNhSQUaSaT9/z+gi96oVyyLCOg5J8LHUqpAuDkUAUpIjAQ+Gy2LX0KiCTCBkunAkQQ
qSrOlBRwm1NG3L91YM4icqJ7LyCRTqo9NXoLVlgrI+VoWRuOcOczU9tYx/3SkiG+8eubizBiw0qP
07Jb98P+SPWI388Qwl2KsIKOlXRcznpVvNEY6kap552Ex7a/WvpBeQwXTasoi0PV3AZUfYIF7hAg
6vg/+kklM3bnYo4b/H4b2aYA3Sj+zBCVtawCMX+5YLitqVOl4uWgH5gYnPg+mGURoN2dq8Lh/fTA
Q5VaYf9LZ1nqNtb80vtCbSSbi1Ob6KQbZDlGCGN0OKKLtyWbMAGpTarbcx1nIR/VSTE9HunN0vwd
jwxJCw4qLbeU9eJqqxuN2DSWSeaaGaPfTKZ6+ywJ9NFNuueJdy1NRF0wZ4hsc+c3a/wuN2sMeNgp
vBsvH7o17wS82JNQok6IGCCfbrIdOkhnuEdtbIEq7VHjoLwEgtgzsPZ4TsZ7GINnEC8c6R4RxNmm
Dl09wAUBehCU3Yw1KLqZNqDkvUemvUeyX3QCuLEYLhEaK/NbqJRNJbl+yFVmm3nR9+waBiVbeWpY
5taWNCkJh16EkuACDkmc4aeM7MowLkC11omcJdNumaZXZ8QOHVe+i7WYDi0jZy+nIPHzd/Jr2VQx
b1sRRHGgYWw9vHfk/JTJIx26x0QIdzP2VHY3lVl0ZIiLBeiViNPE8d0LOKBTk5mCwkk8iL/xqoOF
dfAy
`protect end_protected
| bsd-2-clause |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_dc_as.vhd | 19 | 10777 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EHhlU67zSXzve/de+KpY85nXXvMNuZL7tYgf9fn2xs2MMX6KZ+NkxxVYV7RC95SlNzgUt4DfQ4/9
3ul1mLnDjQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UlAZFSxNoqgvPPKliBxVt5c0coSpd2sh9B8mE9L64FOLOsIE10QbDZBGLO1c2gEWIwuQ23M7QvQA
5NLCK/AU93Cer6u3Y5Kw85Zu7Q3cTJ6gtsPScNo+F/wtG37D/TBvZy9QIxLBvCRLOZx77GL+Y61M
X3HQ3kaL5tpBN9LRA7Y=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BhywTGDm5IJZmP+63CSoL/TDCpGJVG3VkCIbV3f5gGTJ6iLDPwvtFhhY8681GBR+EoOyUSMbP3AZ
DMFHBgscpLa8vafzBYp5kDkIAp6zpVke5p8WT0T374mfT86d/rJV4lUvVArJtTXZ7Qb2BRu+oMwW
4NXsxCdhgqbldJw6uUCqk28aEPgcbivrgwKY8foWfBnTw+EKHyn/oWDvwghTokcxfEnmhIMsR0T3
yD/98FKNKviERlHfn1BhQ/aqkW51Vp/q5U9qrKs/+lZwoRMsy8lRZRggDQnNmQrFO+0t1Oq/DlpL
Pzgpskdyam5KjVkaaUDiD9LunE1mnunv1fkvkQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
M0G+I4o5qs/wY3cBNkJHuC5SdvD7yJrXn6vr03zDaDrjCzuSM2xSWnhAroxnc+rs8YiB5XG+kxRS
nfrpZghhDmt8SYAMsT5eb/ToWHwFcmxPkOwf0TCRf7UHox/rcVr0f6gppZYuBp8i/HMdTy7/9hVi
Jazk/jJ0qiENaXH3lhU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
II8O6ksX/NQP2v4t19inJMyzBruYXofFp7EnZduWuRh3lmwU4/uZj2tsoMzEFI9GURJGr6OGMrIR
LHPoTtEBaHFBnPNcL2m+mOF2hh90g7CmgF4J8nr08oNvCPZORB5fd/Cj4ujbrC4saBHdapCX/nOt
W3mratI2AGAl+T3t7Q0k1PLokEpC1hOrn+eLqLqV9hKaNBlW7DfM0Swj9M60AbHp0kL8sQjj6PfO
zKNcq6Xvq1JnJLzZ115Py+hhtw8g3az1/vAI3s/sf20/ggZ0t1s4m7+wPif6Tf6IZJCySXPmKW47
LjAxEb+MGgXZe5eFDZ4nbVPt5Q03mtQWzOAzTQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240)
`protect data_block
KjU9w7W+EMycYBwWubdK4cdo2TVOg7IXnsAenMl8Ozs+YPsIVEz9JLFHnXtP+EnrqLSP6JpsfCDv
c5EY5IiZohLLsnigtGQoAbw3xJrNfW7odSYx5OD4rGw1worABRCGX65sm+Dz/Wupvrnmbf1sWTzb
I1Yb+4MVfrIKHdMbYrS9PLjZ7K2J3YbboHo5MI6h5AlOz/+wGnMsAEaQbMYvqJbaN2FCbAce2hhV
fy/iMb+u44tGRUobF7EBOM25t3AN6z0qAN8B8tt70gHhP7G2dr/q/u0VygxQRtQ4Qwop7a1Y+Y/Y
vKnqlKUJJW1lNtGrDOjKvANBtviInxNmIJJuTt9TX6ORbWBArIhf4J6Swg7TRMm+PSivJewPvN7T
YlACXXW8PSBf7kQxUv1GmNucJA2TdwxipfmPsgFE9jFxlJzGdnUSgScm1bb+uhyB4SFKWJtjiUfk
ChVZ1dA71YVoQibyJENp2WllpAlhr57uOo5B3OboE31a8NK0MnpKkDvAFfCKtRNWChM61a50DzPs
x1ya5DsBYVEJE0yQqZaMTKjONm1Q2quPFAsNFlIParq8YIf+YJI1h2iCp3VNOolk3dXcZ5+dFf9A
5lFIch83dsv7U9xkziK3ZOXOGSAKe7ZuKMduaZS/faR4T7ZaQ8Dnr6BOjylOmEwycfepVvnpgQkU
P2jdhLwiosu6YGAjUzolNsxAZE+sMJ80VQSxu+dfjyT7buiY0oLLoZrCeLdIHrJAIBSBkt9PUppT
rEvWd3qEWeh+cRk0qVqy8k41MvEg2jAtAcZwP06/lVrGvtQRiB44kWdpJUC73xqVc5F2sDuWVYfX
ItM4rOxLGOjc+JhvqhFPqYLepDQFcz23kjWAaIp5z4Wa6AAYrhw0t+0FrnsRp/vvhdQb9wVWj5SR
9IPA+3c2CP2uDvkHbm4qfXQpOUplq7T5+r17VfKonq8y3TepvMT2CJyp1Et2UGI5paOFkMGQfb6j
KgH+9hqhTaCeKynmIF/WVAwvmw4MK5K3mIyBgTu67u1VlOIiT7jyCVc6UM+8YKnMW0bGA5Owy4o4
bH0qDAUvCp25DSbPUfVvg6qUSpHuepCIxnVO4fcrknYmhLSPF1oeNQCJsVkX8OqLwTa6Y66Nn12C
yJ06vsMa4TLKWHzIp5FhBIFCTVHFV6DqNVBBEty81GRMwHIQKnJsziUfTQunlfoTTe09MT4VYem1
JR9qHh8Xq9h2Mmd6kAoNyP10G34oyVKq5WUkaTmHuDZEzONtfQ9eYbyiCvLbx/rwenhiGuaIjFA8
qUpm7XmYDatnG5yhquyKCEYoNpe8yJBUaShg9Gldmnxo9vwa0Q2JtqA741aspVRtIx+ebh9d8me5
o6VAeWToXdA3tEzz7lT/7u4OTR6OzjIDVlOMDGJty45RUN9219if9lcBbxEvwDXV6YgAG+wZebE3
wuE83MwN7As9EDPxC3boQMqzDvVgKZSr70o/08jjb9dB/p3vjw+nwuYd4xzPLI+ZB9s6k6xNf4HB
Ck1RrL5Qo+56iyJC2smH4sKP6Y+W2QcYA9ZCvCnzsSJZqgwKuGNbtMwAi9TYd3KlyRcSZ+kXdLcu
J++NMX2z6jAn73e+iRBQ1HnxRp3OV5Ow8LnVLUD9kkfGuRMmxREgNHdH/Q4JJRQL/Kbn+JKttwzj
3NnV/Q3Rvv25dflq+WytAtxKz6x8J/iShR+b/PFS3nLI0as7Wc08d0XcTgivltF8gXAFME38kEhz
LWd3xy7WO9pp9kVQ2mBQcFM0IFS1fIFdlia+lz2ahyZ2GlMA5hx0CoVNEgX/Y0zndSpyVUb5W4zW
hLWph1aw3YTJQ5ae2ZI+BkzaapyF9d1cn4iId6yN4jotmC6btlrlvNCCXIkmQIUswF3mrXc5rEbW
PSV9t0/hho6lE3+B17Cu/NOIQq5gaUinTfCC89mKYwaVN+0/q3JJvOIeHc9LrOJcBpxKx7hfMZSk
a5KPoDp2JWpXxFGDnteZ5sCm9Z1/n/BB6v7WirmQrzd3VckoX6bh1+OVF8eq0SQ4ewiJDcYQRvl5
vGRTaQnEUxQ3dY+CD8d5vfU1ttwQZyV/t8kuUn3wtmN6q5O6qeEDCc69Vs01v/K20/2qRkpemzi4
vHzYf0UWqtCkZBmNZhuAe6T2uSP8aD4swtzxVlIgjenx618ljrBfxMBUNu5zlkkO//eppVOZZ3eQ
3ZQ+gKF61Yb485fHH5K0N0+69hMjt+c8mHTgxq1r9lIstt4GVIOk7t6hYEIj5zAB9Cr7jB9dhZJH
W6+bNSs2ND5fs34wXhV7QfCSw/lqkqAoWRjMXI/QaDHltstQR1SWTkGmIi51DZhWyVamFnXXVDTn
HGjS7OfRJ2uOreyQhYkTgF/6wt0/pz26j3JWShhGauXx4QPBAKbmFNlNG4BUMWBJqT6PQzqPrJ/F
zkC1JHRwlJzPanaZKUkNwSQbb9jSQFo88u8qOMRwLACi0QaMyEDzjDhUKBTFhtkNv+PE473gNVTu
dsh00VAJs9qI3Hn71rRiHCOVBTlsmSgR93k3nWX1XnVUEFd2w8RYacOI4FzVNmfVdB8CFXW8x1MI
XNkWyeCIfPtZXI9nIHQjU8O+SMIFQxNCDVv3OK/hDvTlABDMnorSePsakt7H+S29pO27i7tlBluH
IibyZMBi4ZCOVtbw0gJAQTqBunz6xI3f+jYU8LWkw5JUUv3qa1MPzBi9dGDkx8cCsUyPeNfMzvZq
qXu+q54Ph4x4N4TYy9kUR+faW99xbXYMtwCT1rIegoAFsH17fj0chu8s2IpZBzVLPrtOYbWFCLys
D4v5twypLkZUMfyO0o/QuQkHJVLms6Tmue2s8fKAM9CRturZt21W2rMkVPQk93mlcE9esvJvzYp6
0zl9OMmTiX+14q0pVSiTgMk0n387MXfY+lNk3w6ufLZ5bVEthiktsRZfI2m3YpVy+Bb+JJi0ZrTN
3qPzechDhnxe08dNumoKP8C0N9qCUSwwAjAgVxWsePL51iNn8W2ny1vslQBVKss4X6VNV93bzN7Y
pTzexLphfNpq5ylQ8m23Gn1cFhII5SzJvxdtrZ/aw5GefPFKHq8DUlkDi/o13opwW1Rudh1/7e6i
QGThg51wgrH3lhgGKsRV2ZPRowf303ZguR2y9Cb6g7WXWuT4hfzHnreW2MCTy2v5vTN9s3RH8rw6
T0SNO53iN3FLiTX08m+lHto2cZiRbsfJtC7q4ueY7rMofv5Qtcl5/IyuoC/3cQ903bEId59UKzMY
umv695NMs84zzX8csSPDhWT+7Tgsvb6w0OK4tsUipFScSUYXO2qWUZAyURWFHNUpI6MyCPUVtyxR
6w6QLfIsISkvQ1Qgsr60Eu/tFlvu5y8Gw3YwVZe5gsekdIqIKo+StixkAg7sFZDu+DKh8CqjpUzG
FSbT4O66nnBTo+FV9PM1oHTKb+mbC20KpeH59wqWOA6P80vAwi30okV0T+GfgTCrXmDN9A6inzbj
tXkhBd81pgRkHSH6NG+2iSgpl4ArLZDP/SgiIFfopv3GGevpKW6mBOGTj7L1ay8ecl441bPadA4w
ly1qyjVk13dRWAF/Q6r5foqht1VxP99OY+WyYuK39t+cyUbbPaHXJoV7p+EzpLyDlWi4f7o7XJ95
G/vCQ9WDlBLg9ySIyVPRyEs9UBE4770bLaLEQ8LPmRzOEvKU01Z2njPkITN4qi5Y7hwuCea95Hz6
nfVMlN9nvZea5nlaVYU7OcWlTcGqfnqF1jUmel7Vzu5t43tqS/SY3fhJlOveToOUwG5ZvUEGZ8Vl
yvsIZPgTpQNpsjd3G/+XdjlqFH4Bn1E7rpNJ3Do3vGcA0n4BGpbyy1XVBMJWm4ISLKC2T7v1mQgk
YXf1goSB2GgWsn7zo120p1WfzA5uqIfRVPdYDNkt1tvuxseRPyI2G7sRaI+U4b4Mr8vnAK/xQ/ZQ
bhKCmy7hHe+5b+TAs7cN+PFwFfTjboS8ob0gRtlwDRhuNx9vARvnyTKf/v2FlhqYnmLO7OygE6NM
MvWQjcHRlQ7U1mbmMJLupQM0xU2z8x0EYh9ZwLvfPe2+s5y7+ZJIiUT1ZJfte99H/UUfcjvRcMxu
K5WNcSVFY4Wwbyoc6c33aoyPL1hKB7MuaXjdpwXPnoytM0Bmefl5y6zJVDhn9f6EgVm9vwldGzpJ
Rcv1MZ5o+Xz6ewQZPnfqW/IFdVa4hKIYiGsJa88rqTpnRWVlxw9wh3aKL0CNpR3YgNpJITrqN0NY
LNor1+ITn95qrsU1f56R5P7pjpyIQU2+oHFSewnCsdOu3BMbGh20EFIGyzUIbDnFnjAr9BAvtrJi
ECSswhcR5GcntzjfbdkiZdF1VlhVXPvTcuzmlu0s5NaHBxa5UL7dCOEjD31YFJumOz0HZOBuprDV
zwYpzI1Rn6DXuVWncio9rog6qk+gSTTLsYhXgJt179BcqMMfy6iwia46hioq58+WgIHx85l8PNIc
J8Wqqvtqrz51OpeHn9RL6CDT9WM0kBq/S8ZqtCaZRlhMLR2uSWc3+Ajsv2lNh82Ft3xGf17pCFdc
v4dMZD1kHYdyLsyh5wZZIqwniillJDKGt2SHfkZEs357oP/58CiGR7HqqxlIMuX/FPdjMvtUnY3k
9GtabkoYXsw6yyuYj3vW0wcaGlpRmJPy7Cwfcu+NrioQB45ZRgJ+QKBrKcXMWyMDq7u3St+cikUz
sLavLUyILtCX/g1/Vi0eUg6L+Ucae0AIHJfDyGQLeM/7LKEE7HDoSRCTOpRvskTmATZ6HRiDqDVi
i5ajpg9IC27m/mzhvhaUcqae1sZY6RjDCKoV9ZYJFlHl2Pj++Na2wBBBhSN8Zyd4N5vwn/dcK22A
9RlOhqY6eLE1RKF4/L3UK/Xo03TxT1H+qX4uZ/sjvadrip22KLIFkazxHxoNW4OFEaGfagi98BSZ
HfFyv4+i3R6ElzL4pJotn/RY6nQ/RRqmiRKMqBpqR/zmisLHCYIwsVOaI7UjJoadoSkPrwRP3/s4
FMJGHD/xgZOOzDHySq/rwoVLOEDg2wsLxZLBF+MeXlDrf5ErQ6e8Df5FpcHX96E9VlvWoWHIyLZf
PjmMwsqSilfSSDdjyN3+HjPVBWdH3NOG8ftg/VCat/kLbVNILhjbRXlMbnYv0hXMELTYqDME0agq
MQR3/V+OD8ayhGnvwgnjaR0KSVolk16J3xYG6WWPjxyK5ZfesItCG5J7h70/lr+6mhz35z9B+Oe7
gH+b3q88UfE5i2fJgimvv+k4qxy5PuPnQnS/wSibTI1CMOHB/RVEptCmrmbmtehzkgJYfLJ/HV2K
fq0FfBRHgfchpZczvxl6kwo/IBmkorYvHAT6UyCH/S9lx+ZVlhHT9RhTGC8schH2WK/3NGBk3YN0
hqXu2lPsYmnuylISAeZINjVZBMOcdYOPojd+qwJ8lMmdszi4y/Rd5T4fcNL8RPlC4Zis81kYrOrq
1bXONdnD2Zkdpt69NklwEDjEBTpvChAlShyoDes1EnRCS5g/PbIe0Sr1EoahHzhgBR8nR8xpfoQa
A2ELvnuj44fZEVKNdmrXdk76Rx7CnkqnLZcw5CLT8e2/1d4n9Le18lAjOBhVjSNPqYxqVGdOv+90
z/EeVaHTMpZopWqO+urdTiOgFYkUdW4cycOsPIGqc25QtlPaHbl+kkI+8Ja43ohgHSulzqD7rg19
e441QqOh8cVzOXKQ7KR1NUbTWKxbWXPzrPe8pcXQNO+ZM0aTjAgmO1pg0wvzzrzE3zHiDzzDiLw7
LcPnZrLgxl4uRF/Amvgc57aQsKX+xZ1DoeopcoBkTFFtRIXRxbebWJBJXvHETQYBrK/PPQK1/0dj
2LgyOvwScij1T6S+AXwZ/E/96/PjsbFtRzB1RYhI2USIxTFC9VzNzy4QweJJccLVX1ngrWJZwNG4
0s5BVlvSDhXvcUxLPs5JgGrrDNeZkBUHC6qChGSLZ4iy5SUAq851+llkJjtGNh7aQe5yfNUvZGXi
Poq4aupTbfQ2VZe3L4c3ZHX+hM349R2pUr7mFiosmG/k5QUF8KvDCUVQeWRw9zZ71cLjYF24+cDS
hcdR2p48A6uJtHrx25jxiYvlULgN3wsJl4VxsacJ6iLYE2JsEVZH5HsIm9lCRRweYJGA1rkXrX9V
W966Fh+8QPzTh+OJcjIOwK55ziN1OewT5udp/kseHK1upjRH63mw1C6+NTFVTW0zddpmnm4MsfXN
xCiOUbE/u8woN0L3f/bUoLoBb+JLo97+Qi7TCEXgiQScFGMkl90SaoOe4f5r+1hyze8bF+pwSMoE
t5vH3k+xIYqH+EMyt6Tv031CZEcuyJsWA/BTBCcWie2M1s5VkzV1vVKh+JLd/PgHM6prq+PgdVpa
KP9Y3Xj2ThNzOb9wdU4EHKiLooW+qSv0Ucyb9sn9PXFQKhWd9CuaOevHurHShyHGPfLTCwM8JzzA
Q5WHHtD6RRo0dH2NC6YKbemtXRyUWY5chnNgGKy/tbC/GPQV1XH22nBt8dmq5+Kr/A6nj+rPmoLp
+28uOLkhmiWed1Fa5x3okuUeRTZDDcVozRmeHXAE6aRWnKe+Xp/kELYNT58781JmyF6QMsE9+f8e
fPebURfrIFGdHW1EHd+sq1dArvUf3MNP2l7OacdRXuN3CwWj981u3cC7l/WgP7qEzJgAmr6IebEq
XGxWldGXS1AhBU8dIEWsLRRQH0X6FaKTMQKyGnQkX9nIXKTMkIWoqtgJLEoUHXDqDl9+CaB0pqBj
5PmpneFM+t4DxlnWwLPKEMakAugbg2XJXFSIzDR/U+C7Y2YCXAoZiL1AcKXMyRHp9xB8Nya/9QRe
4VoLms5Bq3GSp1zU1sCofg3x6grhWXFdVj4ISfTztjWNfQ31zEFx1/Lqsn8utwHkDLzzYvaqSBv5
v0R+WdwAFrd5IXXmWewka4CscS7Weq61tW1/Ueg5MMCqQJ+SZPLtCQQNiGS9msr6vTcX0m2Nc8Kq
+WRd41/K09XWVV5vG7GDRcgDeABBbZT/5lRZne9OJhWEJh2Pd4jKXyRtj3XefzpY4RHpENgchHBI
CZq1eUU64j1zMI2MWlK8tvJeQOCJ/zgvuS9H4VjyOttYO/88EOpUrJH1MYp0JHbxZoNX9y/BqREw
vAX9U7E+1K3EF0oyFS4z8TdxLt0Osr/8TB0lhKt907mqp4vDKO2Amz8dU0S7DLa256p2KtFxP84g
yTEWYJHzw5QVbhC85j5zbmsMyTiME5+pu1SnJjflcwMnq1krNk8Y1JWBmlBe2uSsmkZjIRrysIs1
DW1whU2fBSdiMRESHY33H8wPHGA81hQ17pF4wCGFSG6mNtNwUb+NA6bXZorDmEMmLf6BfgGQfx6q
2xT9YXuw/KEC0Qb4/8TXIYtMeObaFAPMwPM1ueH/q2GRBJuBLDQYHOOvOyCGXxgYxj9LZ+9U64rr
yaqrYtCQy/AtPyGW1xaMiLw5FeEoEQrt66kwqIkuUXZftATG4TDIVO239uMumZFgHWUksN3bLoCq
QcmAM7+Zb9SlUc7QWkD2p179PcRjDBRxvi66jJiWtm9EGGZ/i3R+JNQEZKfzppHwsACRetKhmFAa
4IpYOATGHTlPWaRfAmZyFCEe7Zp27x7FLOK1pnoEmfuBCuTtX+03L/QsLKEjELAccXBDD++PWcJ4
yR+Xzcw19BqvUsEOSduJk1aDRUxHKVAIrmB1XEPsQW0oaBVp0ju2+IcfQ30Nc9JqM4MW+VsJy9JL
4Ib2mfkizlZyb86Jv43u1NYdCnx9uioKSPNJoabHF4DFdax9d0uISC5KDT+JHQOZjWtIq1YMBOiw
hY9W4iZ3SPFboYzsOMjkZPmBtfuMpfGjVc3h0pWQk03S2vx6FTVTnZaKUrB2LUh7qrHt2OUA/9Ew
y7qbQDe59drGmedYTvjYiSFJewzHBN8C6jEd1GDMN7B1hPGK1r+0gAQsTDbKnNmqcB6h4rQZqVHl
pPB5v+ZDRLUPYqY8dHofgZCXjeJUbAdd1ZQ8xMJP0Uamm0jChwad3bcNGiihLvwrhB+72V3jnhcg
BcDmVPfM2+vgzpiBEE2LfWEgA9OuA15/hI1VbSN44ga+R6Gp6Ss8F5PLAgvx1DNkjrnjvDOlrzea
tV47ZAFdv2JD81L9UxFeXHN/+NBrqHj04HxCX0Mo6QiFUWBivOjzuJMo6y+VyEC+4L9EllJARzLQ
DE911LdeTdqyTWxBrTlQ8wrGcPiZgVsTmedJidbagT19F8bs/+xgDmVOo2ewxfV9syoGjlMwVmmg
Ul4iJv6lX4gQUMP6uU2Hcb5Rv7AZL4lkOzek
`protect end_protected
| bsd-2-clause |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/builtin_extdepth_v6.vhd | 19 | 50137 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
hezhI5arYh5Ll2LsYr9SKRVb8M09iAN2m4JSbciXeqmprOA6kAYKyNVYZrZl+7uJ9rCbSy2t8SS7
C18wuehlMQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iG3qoWxeKUs22C9+IygRgNw/Ob9GNJdHtLxrQAtYdMzP86eceFi53EP4Epvud6QFqZ+YCcJAJz6X
BiP6+zFZ6SCjFFuXw9pefFKNSIH8+q7UF5dPb1d06lbHzIZD+3mRDkhnSZjrqT/zLAUZb/IQ1Lbm
Z5oVMb2d2CoW5etMngE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lCcH3M3hshWBn3vT8V7Ds2ckpLb00IXg/NREvwDTgQ0x1n/TYrAfJvH7lJwH3QNYGbvde2S4oTtp
dxVz5eb3NKybz4CG1wYBC2N8cyfQblBGlezgCm3PFTB/fb7+0CJP6o+JNkedc2s49uA9zPZB2axM
QOZ+WiL1UDOqHRt1CYUPiwYxRC9z2R+kY3HwbNnbrtScHXOfjyqwc/ifFZR8DvMU1CEJYRjuFvoW
cH+V2gM6YyOHMcuZuaYjA16MxseT+50plqCZJKvjkYTDhSYcuZeDAun28dPbdfRu3AO52/Kq9gTu
MLy1G+7O2B+746vqe0NC8W62Tyb+rHxVnOWRgw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NvvNy4fG+VCfM9NYumsm2clZ8IZDrJQ3Wi+cnwU6WbSkr/joDlB0ZRXsdo0mhVbkhlHdY0OhRpkR
3RYDWBuljULA6BTyF1sag+KB46HFjV7grhZmVLUbBkCWRKYz0xq7bDcNxf7s4evpI4rWpbAGWyJ9
TlfOT5npzM2PM090g2k=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KN7EzciqITw/PNwj48fL1Z5o1AjZa3hMKXx25N37JjIMxkR/++b3PX0LoYvLH1v4MmFRO2F2HE6o
+A9StU1NJwej2oLxLD63NMJa+VjJBFCfkNayO25s8BHSFsZkhjc8mIC5S+PHU5t+p8zDOXzJvXOx
j/qM+zNzxFnZOpagckJWraMSJbbFjRIGq2RuUI6DTykdz7949XyxajpE+pE2TrgIaNudJhMJkV8s
PmKxeai9osJTVlAQyTdS+HOwcKIcXexlGTP+JSkiagntbBuHEhDR83LTtvkaJx0GY9b8oHB0RXsI
Jp2E0CkC4MgVpkaduxkwBZ7NjlyO6dFeIGiehA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35376)
`protect data_block
/woyh6GJLpiwOUul1TNz4DVoF2tJq/d6R8jRy1QYhHHYUMhWROwDb8Z8HuZ1A9UehYJWQ2146G90
sGmxawsm8YvYNUVd6v7T0YYtEaCbTcGwMWUvsMPnsi+x0acBae6oHA7iCXjCClgN7+Xpgrd3hsTK
bDmhpohSJ2hTEYVRU1jjkieYe2gxAw97DeiNjI9eWmeHH+G/LBkAj0DEYo3Su++WRTsKAs+9bf0i
5Q+RqZKtI4JTLUqv+JsA9t9csGY2uadHOdF4yoBMCrbUMkgZRmOimzKfx7wmIgMYe+OtyXXh/M2J
D1De/Em76Ky0qEkgYLyFxDvtyF/erCwQjivqQmUlFp/gQi53TVXsEXggZB5wiH54KylVNvOLI4uA
cWS2Qkt9vl6ZYzJseyCdM4PveCWsb3wl94ieTLedmzcfUmNdcAUr3GoC7Eknao3kkiy624knjWrI
XxoI2/EpmI7Jk2WIwEcaObi+Obg3SDkAGNOcQA4zbK0Vp3MCR59F0xvE2nGoO4kxKe5vg0nJgx44
nO9fCRi3cy8XUrIkAbXXcPypWDq/r19aBvbIjPIOXU2qpZdZ2LNlKlYNB+h7tP0pKopYLILxo1KW
MjbXaahngTWlP8zRJDI5R8dzFeK/jJUlmWRGmSXHeMm00vxXmwkoLUWUHbNEi2yychNphy20WEt3
g8Y1OjDfoG0Rw9S+xgUhCXM7dDb56Kj+IGdL4F0KeRPhf35aILlbqWe30BH7JHbXH5EVGxVOsnKr
t21iAoFcXSclPglG+vMitZBb+tza5htPN6BzNwcoSmztAqMaJOthhROtN4/oS9GHuB9RU8/Ioz/d
HLYbea/5F33NXNQPVeRZblrdWdhgHHBknCoL40jLnjSGdrbBlE2Uon+BrexaZOMsG2OOH4XtDtVT
w7RNfIdn49ZyvrmiEOgBb1nz3a0n0Vo4dLdHJsM6ktKLh6a4azZwzlu+YE2DMkzog1mu3GRScM3D
i9pIiIzxCREv0lw0v9RaTLOZz49es5cD4pbWeHPmFpV4Sa/8r4ByrwSQcSz0v8PWvZ4Bo9K9zdBT
OIs9VBvw5pSORfYTnVeVfD4krQuPHh0v5lr0MiIFR6fUVRRM/QMaDz+A+Ym422pLkYvW6uTSXfUc
DqTI2cnqChNiMiLp2uUHU5zD7XHZWggwCthE3HhpP4cAT18Wlrg4ncpxFroDLE2rROtqcON/ddBd
HyS9bL/vIPCKiHI3aRxRW86um/+Iu+OW54bTnF31gkA6LiKfaVlC5h3VL+6KKd9UFvm5gwePugzQ
D8/f3DJqNs4ZTpL9EIUSYyE68X1Y8rtACcmJlupFJwai+r1gHXjtJcsoZWS9vpls+/uZ5mc2/K8J
Gn9jI93hchqElDY6CZHhdDNcVMW52AE/HMtFYCOc9SssGbYaaqz1lB+9URQp6qCvsh9uz7xNfJmr
mGEuPkWkKC8m/Z9TTEWrPBcHhl7Q6f5705phwva3PDu6ZX/3pl29JS3XL+DiQH+jU9i5w5OrsNZT
mS2C/TMFoUDDWx2VnahP5Tj0ufb+5Yeyw1OVaNfuLKrGzNa8bYl8u4Nsw6PVLDtvtoXgAAS2bgjB
JPq7GuydHqS0UnqQ6DdRXRtGHZjiuMCST+IebXwo63eBdDQTEW9S6LcEoQTC7IR+WAon+1d0GzI2
GRZ9gAtjeCaNuPhiHPNcdJ5bEfR7IHUtV0HKeDtR/KLS5YJoZp7IU5VWRV9xinwkIZC03sO/roCD
Dodxamfl9LrN3Q50ba6JY0BA5UOHjbY/xZ2zAj5vPLbTlbeVkg1G5FI22/Fa97ZZiiqXEk4ZL5Cm
Mh18am7aBApHzNJsaSdGr//nVTdT5MMF6yznTv9H9CYhGQ28ZvCT1SSAWoJ7Xa7BKJLfWBaUtmE0
cTVxpD/Q2/Hx4xJTHVg5lW11XJOKNyoNuVSoWofmKIf3jVRYBHuOEKBI3ZanmraRlrZkKTxCM1AO
1VvHkboRDtfkjUY9KWOY0wcoVdvR7ZOYfV1AY2THNA4SqQ3SF9vy3z9GaoHIfYAmlMkyhvugEHpe
/Qa1Xuc1bXu1WygGC2F9m2cdGWvF/v6QUczmmeL+L+tB+QHFwAFeMfiKHJLKdQrtYPj8foPftS02
lZMU7Ta/WWbSd42kCXUofqtlqIbHdy6o+Qum5GJZIci6dj3CtcmBh/lGzHli+v5xyu+nHnQBow3t
3FWVRszXlmQm/Ys+45FTaA51O3tSTVcB7D7ue8ga2fR2o7lQT6kqAcwuipXfHGVDCrXFMzEJIx4V
oFJI+02FSLbhKeDWuArd+YwDIkttXFjMSkceZBrD+ODYh0/p4a//AI6LgMu7k5b5+UpMto2Jcm11
EGZnh6Dk0iuTSWd2rPt8vmFQ1J+9f8VU2sBYslzsc2aoIuAsI7SAtzRKKgukET5L+kQMyOwU5RrK
9o67PVwLzPD36pqdonYAhsHqHzyH+gHes+lH6ug33fkeWLyCegIYV7D/gwNf6YT+6p0W4j4+V4vX
RoK0K2C7gv6nO79ew5tIGztdL0UvcDTF4lo2JqRzF/v3dZnLF3MzzIgY2b4Zmo3TFca0A+ArHp2A
UQiPwTO9r9OLrHaxLx6LHRbA2BSuXoaAm4W4w7Uxth3UC1PTfmv9Xr33178Scij4TSK0PsYy6mqB
4xp4+GTr6I8rVSBJ1GElg188Ndwg8GfFpkuYiX7wVv9Jq7v3t77CWutRE79+XuwQeClVBf5fBU4n
7tqkFsbDkoe2Si1k68B+rAPsU4H5bFzRd4Tlv+YB6FdL3Qy4SuCShGJeJ2w/8QznqbKsRr67tHqe
m1bMRLxV36TlNOvX3mmAAdDN0ZWXkrOSRRLiwB3gSjsZ063Il4SAIZzNu+gln8KfCCIA77e2PpnQ
k57snmvCq5lrpLjYdEz6B0uUw/DczsejlUzigqVhB+3hSHahQYP8xy0Cu18DEOysjystYhk3pvuf
ra4JuxaSLqgH/f5RFEZA4rQNbTFmkWloXuMk2zULOP17ylPfZIjIEF9OSsrTAS74KeEg3s6oXfxH
J432XRNCgdZBNOLaWKlbp0uKFDqHMuqPPzAoNDlhx6zQ99wig0aLV0AqyraTCc95f1xmPTfGj0Ox
FLsUbQGCuK5rTuBx51u9MpVUUyNQDW52Y4aPteBw6YQkwS8qEqmWwJtqhqaa9a4AE2WGQsNcTXk3
w/zW+nMiMUwEuXp/ztZgZtKlAem7gJi/mGQsVGoGOt8DcY7Hqijn5NK0RfXSNpiZlfjCzSsqCTsi
gRfQQEc2vaxjbG+QaSPpxsuR+sTO8Qxw3m7Sdn6htAUuOcC3jcTOMz5ZMycO/eYi3+hjgurK5x/z
5QSnScYX+cQdUTuB6ZGj+Z1NY1RwoXKTp9/ISmrn1cCQTRJ1dRhtz7yX30soEgMrMyFcEKCQhs/0
dNtGoUzRFxsY8YG7DDzF4cD4S6J1BMrQyBflIswjrFxNiJcP/Bfe/Q4bJ5Mq4zhBVqwSyT37sTvs
GqKMl+oTVxViejFvdoNz8J66391edE9hziAnJX+4stIdzCgrhVCY4WWw922xSExhDoLtP9dXYXOH
1LdX5JkeHZ2Dz1PCZ1bro3ZEU9od0niYz1UOFIaqoE9hkTwo4LFcBatHBg8ThnNGJmYdMRTA5Dmn
KqR5tqWxjJcMX4jiXTBMwwNQkzv1IMiuth8UsoMG8Uzrxf7xNQcidBaSRgbaTwD64JSV+bnzl0Vx
N4XqyqFSozGzoqyUCF5ma0vd+Eyb7oAZwM9ff2gpnkFbEXY1/VZQQpGM3LrYUho7hlvt5WVoBliE
GTiscVtXC1s6FE2ht6vipKGmB0mGZ4mIWnu/a2XMOAo86iirmWaedQMjjWQO2nvBPYwGPKTyIudX
DRBRugVUp2q6Hycgyn7sD1/L2guqlrrzgjib0JvZis+OYh1slMu7aMOxnrnt6cGhp+0sHJI5kA3i
xP0MUgQoHgOMDG8czEHn5tqaDfFm4tI3BHVnxcV9bamSez8aBtlFKesYTn/GkEURuotQwdqt7HBy
PHpW5W5pimUOCnpyt7NYRNVl4rvumjqSm8rc9pnSb8tYe/ehIAHvc2DNOyNuSwRuiMt2kPJOElib
FJLu4Cd06dZuebBFZZKr97WEsW1Wl9xaP5bQ1dCFdqxUvkhu6GHzUu3l47aHuGSYyLkN4Kdhn5ix
gBY4WbDx+7ZQbWbS2KrgcjLNq1mkZbQhITQvBCUV9RurhqksTisL3b3f2nPHiQuPZEHCnpEvP7SE
5KLZ0aZ/Cc8TD/soSestbdxLwEliA3ZUOjJD1ZpbHf8mfQ4ze6D1bU9iGhCn7cGagdcBrTt/ig/Q
xB1avnT17DNsv/Pyt73y+t0mXNp3qfC+Sp2u7J78iySB+vKP65cbMzHjyEHib2u9OB6TJHtBJbt8
dHjSeELf8hDHfkzFdxY+sgDbw9d82uZoiGbD8VolFvUklBRKgla433ap1bHdwIve1/ZQkPmEROaK
cEbmj4A8hqZXcVLwxb4YCKna9BAH6H5SSSrnZ+GWGNrArImlEROVIv4Ukbt493hagfcDe66vdJC6
lhT2x1TczMwXNKVXv8xTYk578F1TF/KPr0XS3ikI/zWlH8NXcuoWlO3CibBFDg7+DifY4FA3400R
7V4+qA5vItKy8j+7h5ojMIEU4PJB9iUph3vyljoc5hhYzFBCftIBgLlDutlfhnrFOPLW5urReXmv
bIBLds3Tnqs3/F2WvX96zLT5OOVk0Ma2bgeLYXNz+vAF64cOIA/VdHEMxj3xnODR1mk+rPPHsfma
iyfh/izsDpsB9pFxUPx4eqvcIi41cTWPY+EBkyE/wLEZNZOdFm8QuJjfbLO15GII6utvj6Ieogwe
LbmeWJajdQRLHiSXM1dmgu0Hd+ocVBV4D8KbKECjaXeAxnCCsKhyJVUDw3E56te97301GF0vYr/m
/NswrjvvWBu+l13clWAA1lanYAnOt0SsWhZFs92611LnE7hMLiU4uwPPXTfPZ0oe4VEFBiVb2sne
lEBkWmP00u/YbYyyDZlRoffmUbTCVP6B5nUR97Waw7SE4gGzcIFsdjbBRL17xV8t8IQ/3jmXj4Yh
//XnbCsvPVsC2o+MugLxY2+Kchzy/JeqCL1ycwuXxUjleWd+q3bw6RIkF3n3Nyi7pd29Qqo4hmoy
Q7SjpU8KLKxzzTSb6vbtFw4KUVvfwZkNw+BFjZ9hjZ6qEJcmGHS6w/jZQtqCvkCefowGE/Mb0h0O
+PcS0XphJw4ISjcc++/wrVat7AQjE+pRVcC1N/42Ln3jD08/uS2kSWQmdLEphCq3b5ZtpoxSjDTD
VoW2DO0db3xlxinOhiT9N6YI+d0/SsQOPQHwjmylTK9JVQu0uTa2xiy3r9FJ46p/fYftUZbbVw/g
0evK4uJwWApwUlcdhVEkWuJj+RXBqQemPdSZrzwHsB/jKemAQggKi9cxJH3JKnffROJ8EvEyrrO4
goyddjzyBNQtye0GUCrS5m7C+F6ymlQv5KE72kl3/lJtYtG02DjIGi29Lkw+hOiBTCpqasRH0ZPE
qgZxFv/YSCVwARamM7YYIRtUGleDIjFgAGkUmmKGjX6RLw3v49uxrRVfBAGuigl9CPe6HGujcvXj
6UintTwLSgLyPExZS4vEI/dwQUMCjuu+Dxsy4yLWoFQAi46HIahzksns2wpPwCV2fi8DG/8egRXe
AVnxz9gDVDbUOJ4OX8cEoZa/eQjTYzVHgtx8ZksKyD/ftgf4TBf6pQaAHo78GfT304vXEcNNPLVU
aU7P5Nuxt81SYKJY21P+iXDZHKOPEdmP88uHBsI4Q2qdXHb73/VZIv4p7Lch1B5zT07fnsRpTnSg
71mOHLfSKsfBoFq/wBr8E1e9QuyCI7qMVeP1aHPmkqs6Ys2uwszRt05S3uVQajB1e/QYUEAU5vGQ
pUiZjizt7Ve3XI/E5u63dAKhBcWsxC+zjMAAoyLAX801ls0pxy3MP+XROb6ACjorhfy5Pn0w/pJ6
Td+jrlXUOmPOaOyLqcriqw2Z7AbIlw0FLgfwKg94lVntoMhBZS3CYl0My7PppsQBaFhcLvqeEzQ9
dIcFrmzmmQtPsm2neu1Ou+vje1HnSN7vGihgYDwAovitLyMEecfQ/dN8ck98bP+fqVdbszIORL72
bM4+J6872gFfaymvAmh3fTR3vWgyAfNohBqKzzDhkqCQ6HYqqRK169GZ31FQvcOQg3vRWvZ68vkI
OBlrwoU/0ZdEwBt1x9d/KrMvOT84QAuIZEoh9dh4ZrVRyW9QCpq5pRydOIzZqC/alNXxE40Zq7a2
itkEjrkCdvZBTW5j+eS2AYeRuwFT2AtuMTLFqlwgE1j6q8l1jGjWJisq4fGFpDOPQNYrFaFHasEQ
c6W3THOCPR4Vkke21tYqHryxsn2gJ/vkUBk3OymACrsOts6XFDir8PAVAz00JwHZi2VwhRUnpCJq
3WZw+5vjktzcazWYWTAgmBZMQ9seAeqZp81G1frSfnq6IPQJ+/y3/Vv8fh06gUhfSgK0CLgjMFrT
EVSLyoLRbdig1CAR47Y6HVfaG0vcm66Fwt9n9c9fTfaWodmMb0QU2Snz3glx+sDBbpeR+l0edgfH
0gF6c/MsWqtylvuo6GxQZa9lJlPVQBnL8nJK7XAnMH88xSFzrMPaETMw8bVxSrHbT0Q4bSYRBUw3
fvZ4wDJLMhmUTKTiHrmfUA6pJNaXepcTtaDBuW+LfcgQM+m/kkwb0WJ1hcjdFqrOBR5Ma2JVLEyX
eBQHJSTJitSNTfkTF6Wqyg2LokKaPhu0YyFKZ9T8gA9waD2rhO2hn62o0Kmh6OL26DXcs7KeskcK
nnYxH45j7HczKPZ7VZVERvGPULxdOqHp8CcTO80oEod0nsllWEc1ihikNs2PP9LtEFdiBtXN4urV
ckorhh5anrtwb2HrKJEY7Am0rOxJ9Cmlo22Ym0WI7P+SbGUaZ4TqCO0sXdHr/I1aKTqS8SD4yse0
8IbmkGqjBReFTCxCLiEWTrPN/bBFZoEZjp70zjNv9NevmS2E2ur6VmAqlrIPEtox+dCtDaPAStoq
ZG/FRFlsHw2FFdCmJ1/8+fs3zXCSliAdJwvME8XrchbpzGAicWGbjTJyk6j9hhm5Ymj0oRBDA4RS
bcB4eaGXtCkaYATI6Puqp4QOws9iex5fO2FvruR/FsrPQWFuRlbC4BQEI1JE/yGwwhmpi9fguNBz
qQxZFZNO8qdeaDrkAdfwPnPGpiYScIfRLjvnGEDioFsFiz7pSyC9ciZMInuyvMGrAAor8A4pD77I
p8D4dznYtvZdNKneZbWFwAiYzTApnYbGUylyCW2BWIBKsuhpTTihCKr76v/gn7RUZxanBXt1BYlU
Ksijn+65D6QyTWhUS6jeIm6UDnytu/xLVIo+Cmj6tDMHOU+FBY10rH45nuFzcm1ocV9MpDctottF
HuTDKahe6Ozct6GKkSp2oUTfBE2vVo0tdcz3y6MVVp57wOOG1OhbisMNkC6+3qFx7hZWyvGYVi6L
7DEq5lTFqT7Y56waTzjH0XTrSoYS3PKsxHNZ90ntYK4sum+SWsgVBZpvsMGIdIrLxvCqUvWYWvVH
/BTSe43LdttccbUVZRTXE2Lt8SgsEzkLqGmUx7Hbc38jfBVLHGr4mh9hZMfUS72RIin0kWD9637g
vkD6OH6n2cNZxEGIhRYdqdXz94FRl+Ln4aOtkd2cYyGE/F67QQ2gIio+dUi1ni4zmqjTkueLPQxU
hLXYrr/osHrUA7JxUhw6ZKIbwnW8m6uFjUDqmMK+IcOiCmc3Q9LJY+TnvuJG01nQdZMHOOy5TprK
o3aoGn3jbsg/UJvLzgI+sVC0atHDGcdr1Q3SDMfl3sLLHMHzon0pvAcnwEpe666VYUMnsycijAEr
3TmWVfL7G37QP2B5uBtQsfiEFn23klb7bVkstSK8QEWXrEI4hqvQkSzyUPBz0MUb9rC/qSqb5AwC
rPA2GExzByoTkygcyOF0Fp/X6TeGVGnryu26fJ1Hx+aScqx2GdIGZf198UE9x88/x9wBasgbqkB4
sZP49BJnt3YYnXu2VtHi25ohXOeQH9IeyXlZNN75NoAh1a5j0troyagJv42tIYyeLpovG8sqiqcI
j3hHA2Hetb6BWqVFCDwJQruwq9z50VmC2C2SX4q2DOLVYOEE9JaRpZbPrMBn3LpLA5GKhpD46zlY
2VwRj6tMf/orqsQJkdxvQRkeAGyb1tvIa3XJVHf2prKN12Urdl0Uqk2QoHG0LoJRqBuTYcm8KJXa
AVUQfVnnav0HwDJgz1WFYSv6mA6btXg/Dh1qDVabwFTcm852b8v1UgwQCzFd/VTET5I6eRQTNDEe
LacGo5hj9rbN1inoOFCRoTN3ykBpZfMfROobiaLAUXepgTI6m+E8wStQW7BCWaEbCstDcd+BYIo3
Db3SvT4L0qPxOANkzbtg1knPU41tKLg3phA+iQ+aJV+HMmfABYHquyolYvbRBr/pAeOe0WaPBLXu
GK3fI5A8nvq0O/1JRC42CUAk19leAAKkI5M6NzEUqDjHWVzCjwMCgewIMql9lTYmwlkLeWVM11uA
ReR+/WixaATpjNrJLYTBQnuGjaVcbaRoxWsBENDYgLlhkJeihtsS6mb4O64swXE0oP4r/uTjquIn
uPcr6EO/gduxH3HfkNjUqmfwHuj1d8YHnA2DECBk+LgoGmo6vyq+sUrDEyJZgmXUPFlWgZDdeo9w
Ae4jH6uk81l8xVV6q2WmJyXylMXvnwYMSihRuiTJdZqTvnaKH27tWdl4o00WwbcIeQ9muM5mJgOo
lfKqrjk4fFNR7CHSgZRXp1bd/08zGp7B7L4clbcPBjNVBHcuCSLE14mmzBjm28WqnwwkDxsBUvTA
WDzlaZtyWa5lI7jzS5qwGwoOMx0/tBL/q0zMD+xU2WITJBOE4P/7vff4bWCPp8iV+cYU3dYWoRKe
17taX27sRsr3na+VQeK8EE2UE1V4nRuG5WOQLLtu2z4UM5Y58DI3KPq+0WyWzhYGQeXh58HpQOCp
7YheiKmaVKx0UbFEb5ow6WltcVQwWrrSFzFlO5DEShNKIaMI46JWbM+c4ucz333xPccfhqsRZr/F
9RTLJke82Z/UbcZu4OAnGvey7lRFmqU3M7H/yU02xscfoGXK932ArFVER62/O8ogLU+kNF26nFAL
V95sde8NgV/LBJMYfiT6osdaSI2dkrtIXTBzZxP2v0BT326p7WfmMdI7tGojxkjtECl8ockFhBLY
x7uT+VXnHP+5IOzcJ5vuZHFKhmgaOrYzpMNi2Sd1RoNuc2lYt9MNOz/CRHVZ/x20IoyFLUXgScGz
CF//a8fl5bgNZPpJ/gZeyKwiYP+Zju7EAC2A0wQKym5dqbmX2BhiN88htwVzk4ofRogmj7Yw39fg
yMEZ1/nGGhwdvXlooZcp+zXtPEICYbwLj4IgjIIedbMwV9GNQVbd+IuG6nPgKE2GBFCODrlmRh/x
nW5z57tOaBggOzYhSxw2qfF47T4t243m3IAIBx1ycLYWUibUfOgB6hRquE/5Km1XZCCgy+cb8cs6
BC3GUDByVY7ur/GBPk9uof1R7ga+Z+C5nFwV17LN1OM1OnLTpnUVDo0+5SNNMVhZDOFE0rVJw4QN
f3EUidmHQ2fFMIpfB0LgxMg5r91kFqY00d6Sia89JIdOj7VArf7jXwp8ni3hbex8a8+51NP2M260
FmAXRkOI2uamWt/l2huCeXOeHGx/+QZSz5HglDf6Vx7EQVPHZZ6wqCLRDxZwsqgtzWwQRa0xF8dn
lzX7+BITCZMhqkl69O6YXNd9r6wKrZF+23obVdVOwkTwLacKKcn5GWEJ/F5hQagUBFzXQykgKYgw
75smryGjou1SVTv4mR5q005ioz6HTiJO+Is29jXZb3tH+YaRRNqFoUS2oNtO60h1yROZBTvUZVUf
6FwfzAr/wYigXz6hjf1C4ipChRQzARloXfu2ejffyOQGVKSbtJCugAEtIG34uS2lqskusLBM5N75
4B1OBE1BrZC8QZP9fQ+0ZrFSKMLqfSVTimemZFMV1EuztOO5HM8z5d+7mxrzxXgNyqDCLl5wyA4K
UcexG8Ly7HVoZQyAO1AxQCsQPrUj/z+LLx2EmF8SmOj6QhaYIAYCeQJCs6u8rrFsU3T4SvlWVMGa
NH7iECOko3lmw5NaYJjpJlt1+5Qxe1tW8hyf/dM8zG1n8o39sk2mqXFJovhQGqoEO3Mvyk4pFA26
mOOFcPHpk4343KA2nmuh6psfR7sybQwHnCUCYCYCg8UJBf7Zx7xMEJ1MoV1HQ8ccuj4ypilO1avF
tWIQrUGMNPt/elkjRpMefuwGHYdOzyQaviMdU6hlB6HZEK3voSF7ZS+hdE8lEZa/rkOMPZSii3K+
ZWviJXvaVWYHidEyv6Ot8sIlf8Y9j8O831UjsEWSXwzoANdVei/CXmt2W7UCj/pu3CEN0CX88THO
prfMveVzJKAGM6J+4ALdN6CuU8iJdAuJk3Vny0xK8hKYhcQfHYBLeqxQ0WurXFc0Q/zxqkDMT92t
p9/48RUqYADe348SQPbAGSV7E4eY6n32N70NqHjcsZt8UBof9xEtp5uVsYLiANVPVKpEKRLMpAmc
S9O/ZXlfXHJbxJXP6b8JxguqjyvpXNL2QX4Ux3Z4HWHrGhtmkWd4N4VanLEAIc7KvvxfAScjpJCo
t73fdoLnOIypKpL3nfwxYb2EBCiGA3A3ivg1CfOpyRCu8pPViGoAzT/11n5TYxynOZqS4k2VBA+L
zrfD5Lsuscy5mjGpa5Ycact+pu6rOZcJs0HVjndUkl0k9SnEUJvG6kAvAZ6FqnxBpfCpOqYqEvLc
cxQLwQ6EHVXq5+yBm9i+cZU715XFV2AGkCW1ODdgR98BMM1a7m7pNRDv44C/jtT6sP9BaJ5ivbiM
6dt8rqurDm4Q9vPIy0+f+1rT9HNs128X8m50uIRQu1flkuvHd+H+ZJe297WwBwqSjEFkPgoVuJ3+
wj+l/eP+Mr9CyWW7AGtjhjhrZkeZwpa1LOPRkM73Mx45nUQWYyUw7HK/6c0iHCrtRKSse3pGesW7
+c3ka0ccq+f8Dgxc+CHmiGm48WxCndQ+T6RsyR2o8CKkOnOLKE3BnlRk+lhf7XxZ5DF426hxeAmh
mbI8qJh43dG+CwIkDiQtt+FKIJZJLEu4oUa72vLdK//JLMJTbAsnJvVfB7vhMc1tu2XspWx6vbB8
77dx9S5Yi8NC574YUjcIFKWYODc+NMOmF5V0t/GbsvF0gXKF/qxMRewqw+QGVagVSIV0VE7pHYij
93gTqdhCmoXQ8LQqEsse47ZJOYtOfI6hGYj38l+VyxketxoHsCA8JeDQlB+UwT0kBqZbeRy0cBwR
TnwvkglRBExFESoPLQ6z5aPoGMsa89enyic2NFpojJj3zGsOUj9r0hJrZX9+3AYMf+F+8JuzJfd6
GHtA56VICYm3w7Xg/4gofreZ8JUgD/bdc1Aagw4Xw0AVAt+iFohbJQchPwMoAvutIHeNlTw21yZB
6nnvRJUfZHOadLiUngnjRArsyqbKRyd/glba4Xa9if5y4vnyL+mP2O/qp1oPyVQYSJlWIIG5+5Yf
DuuDoANI+8a8OF9ql6Z8aScwuhQgXanikFcbu4xn/4W0XxtISe0cqdla91OOhZD7DUy9tHLrgZET
+FIXC6yTgm2e/RB3uzamDW5BX4zuuK5Cx63XcmyuFX/t/x2b+c1SDsA4gRfdaTDFSxDRvzmbLqsm
S4FjLXAW5tu6jhagnWt6pjT1ajAVcGd6Q9CuOaVDj/sSwPDim4iaGGkupQwWUQUQfKQXI6tEFDHE
3I8J2oLyIDCf7j+awKvGeUg5mgvVDAXtC9tBJEd78RL2bwJZ04KI4oXNbbphvl8iOeHGa+61rwzk
R21vVEdXe7GemqF5pl5xUuvxUNE0Kn1pXZgaIMFPYPj3R5yiDAg2DkwVog6hr/971YLJ494SCnZb
8ieF8b2WBKStYMyHKPXTvzIVvRyp3yZbh1/Qi4rteE7qBDPfYQiG/+DaUsn7FFhsnXzzffM0SqIu
0pt2HSkl1GPuC3t/bK18yQYV2CTOXCop1SjeC+LObFtIJiKeFs8iBzMIS2C563mpQsbL7wbk/VMc
r8mY1HW/0P2eTtZANqGY+Cy2iwOfywZUlTWdG5fimZjg5mlN38c5IcPoBU56IW3CokzAgB+C/sLQ
6AANfxPRU4KrK84EDHL26i7FkeHIct4bd6nmkcGLRu4zGVGXbhD6aCQECNByDMHwzsL/vExmxJ5n
19nUn2Mua2BSYiKOTqWHEg/JyRAx34GGJp9KMisrWq4g45n5edkg8Od8gRwQ2b40yhGyxs30gDLg
+eWoJJ/mlMXxhaVz6u+qaoDdbUIFcSNXXJDRSd73gFsiL88t6JPO2WXr+Jyg8d5zuqTOu8T/vDGT
brk7kvOGY0MeHqbuahIDCkg0/traRgZ5pviQ5b4xh+4uWgV6c7feuXMAz8OXIWPbUxiujd1ZBdTg
VMEXf1utnh63DeblFX7maksD8NIm0y01lW9F6x7WLQb1rE+qA+gRkn4P9MLcI/IHEtKFk1x0OV8t
2tnNcTWMkqYpQQ0Vezn0PMWmVvdZVcK+TrR9y8Vtp+6cykvZgjsHJfCeMwPq9ALpEUnZbm4Blbx+
3nTaa9udZ4aETwMqty9OvZ0yLPN1dXTcpQ5/liLEXqXh3MzWhvieEkJzrawqKlbCpKqjsnmWy9cG
PIaxG2UxnYTA8syXOQOGmKdTfmAwpBthl9hUXf9eY1wAd6sBaEtheDvCxMe5XAj8wr2N8udBPhwJ
wsLNF4bPi4T8SrnwFnXWoijYb+oFgwIxXNEsfBalD1qIfuq0PWLFNH5xyvPcJ4GxDN1axfjUtZAR
RkirC7yreG+3YVqFQuqr7zK9Sqt4zUzBReqvjmu9XzFW9uWBI1idrgZvq3OMdU6JZdCu9JBwSsc5
U0J7GlDaZKveFGCpDo/POjAaAw2Hxyr2olLN5DRXw7uO73T1iQoAEkA53p1tsJCcU04xjS/208o+
PPc+sIMTyzxOw5wnLn0V9xk3KRznkeaVe7MvF+T2B5nbWC9Gaga0h8fCzbYR9x9+WsEzoaL86ORE
F30l1ql+zgi1aoMsS/niY7X8cE+TN14JehW3LkKDedxolnHG35DoqVtHO9Dt2ZNr1OIpa9X/T6EH
YzlJey2XqrNDeJr1enACfKrrnkcAwQFXqHpQaPCtlmx1TcQXAlZKPBbwhcVgsQ0pfzVP+tCleHXL
d1Laz7kdLIMrqfPGe2V/fnGVYd+Rj8O9TWFlsFFVNuCHu38KBu8uoAZ73+CKgZkhGXW/ADUKID4q
qeHyBU/3veVX0dJF4u7ys/uOJxULF4vBUBPaoqxW1OV6oF5aZhII5UFlxJApov3GfvNmDbSizCsU
V9+mB4eFi0IHRKdYKSQZ5XvpVCyl63xSw39dTogwjN/j5jZH0oGSS2BD382x8SV/2qnohG9wKDXk
6MR9WNuGBOxADaQYIV4zHohLts6wYZG3bax6Dh60+0SaaWvTrradilTp3ZiNAqJsGiS8oQxAWGCv
noP31nXhNa4/gjAnXRZ0xN733zEuB7x3g3AB/XpXE0JvOspAUkrPzUyvz12tIA7vbBTYqXzUgnJN
eI7gJvGxxOTgPd4iJ3We/woZq4+9PVZ+CoadBKjgBRk77FqXPK3sWfHHE9O7K1J/VOm9a1S1C7Kh
xYop4V7PEOAmfE8zdF2eEDLS9i+cPYIZfu5YfkvF7459QZf5S6L6qrPdBwjQAcYfZCj+wssB42pD
Xik5sSIlHUbynzCNekIlhmR/FSwfPojjzkp/OeO8jvoqJO5S5nqshoAbf6RN+0kG0KobpdEI0EnP
uWMUDkHj6UAFab4riMpga4abhyLZxezRbQjbe/ihYNf5hGe+H14fYz24EPdVrfcCCt2RbcTSy3Fu
5zG6U1M0nxy5o090BPE7Htj3vVW1CcyjJ5i/YColo5kIXGDExJ80fqJixuLmGSd8bykI6E59qzLw
WTM+nc+WJ2O63au6lAgILR5igRko99Pt+BX8H+NGElDsyn7mpX1kDuACpaaJHBumhKAOEoWsQoSe
yM+POI+oeMtxx9+n+5ezq7DEBk6IIDd/IJWQ/7U/X/gLphlj9qtuXaUKyRdK78PNPRpzcONKwHce
D8nZ7lS+VsqGQxgVwd0yQF/vW+sGSc0QodWXjh2utjWUmaJnN5/2O9cJATbgn2IMPFhOU5Soz7/b
ekAjdqPGOFMb/kXXOEOj334aIH4TwmfS1Wafcx+37PE7wna/9v4o4wkub3OHpUgplU0nZsMjjjoe
4NOeXlkKeVanvxuRZa8ZBk541rcB5f6mXm7WgjZyPKHAa66YID0aaifD7CJmjdKw+e8yQmfyvkBE
yhl037/4nQl8S/fJo1BDvv9pPq/Wz7XL7F2kqw/U781LOPTpJUU2PSGdo4afopS1GrUHAFsiRyjU
GgCj+FkPE1chE7ypWWHpxJLBHiWMlhsdbt68LXpJb/8fmJmNf+bhyA6XJFt8rTsp/53lcQyvvXDM
h+rINkvF6RYrFW8umYmM1XE3IfvrRwVSJgXxcDUNRgu4hQ/eNEGlS2jb0pkU/rU5w0NRGRiVS6xC
i9KTq9ffaffxIceJsLbteCZTNI+BkrNEmTQidNIX29hyX1q7RymGO+VMZpxb5N9XbWKJXQPy9Itm
5yNMQntM7JPLrSJSYQ0/tcLK7n9iGAK3Di2muOfG+bjp4/O7N6kD8tQ3Ia4gcmS9BKUDUpyZlwlg
wPK4iPdTCKq98HjHagKdpMq5cNviD3IxwdUxPDQcg0qjsh4OT+O+CHQmI6z2MowoKIe7gXXVQarp
E/QwPUYDQ2fyXf+Nm9aZHBJFtncE09BHJu9P7DWyl3H+R0tq00se/k1nmE7wvInkuZjY2JerHnQn
2HyHkKb5cjmbwD//EyufDfTagsrzkck5m3MpUD95DW6XXTORkt0rd1173JDLvTPQpXJ8XR1asl/N
opUhP2ltEjj+3rlaVPPr7nyLArSXoYxnNoOFG5yKlvKmWoH43Ofdye9b3/P+c7VqKgTw4+t2GLl3
bBaE0rr33+Iv+sa8qr8f+QfvW7XlSBnu5r9tl7pnjyY6lfMfA+mAG7d6vAW1/A8RyXYoMr5QM+10
UBxhlO48QqMIeJQusHNHhQUi2PaiqAqz8VlDDKMxfDDox4311Y0nuFTX3oaRq4jPVulH1Mmlo5Hy
XUF/+Km3dI3/5WW4zI/5MQYnvle8CGXvCLPQ0eWzBGGqeGn51PpHQ93XhoMDDDSBCSQgqj7xc3vI
eWd1VXveiGxWgXR/87yjp6Q7UhgYiEHXg9JMkOBCF+A3JGlEWKn2swVzyRMDmOBqOORsJDYPwZ2P
cAU54CUSOScMFtx+6ieDKu/K5I//jtLS2eXxrCV76FC9EJsnSf7/9HBCm44RLEB5ANyQYfnn5Qwb
qDarBiKOfiakPk2AzW6A4VxWSMPkLndDAsmMOWD69+p/aHUV0zS1ruuZT1YDsbgv5fKFY2oCT0VF
GQLXCJh0Rn3Q/0OPOblzTi/nLRCkmT7/vqdIj3Zw34/1l+/reT9v/9chhK8xH9u4i3z/JZJ5Fcfd
muNX5LzoVm4fhbpCkwr9jRcwYgOuPC0d8BrW4WZGGx6ZIxkcAaZugGLaQ8P/dGnpCCrD9oUdI9sc
azYD8sUf3daY6uJc92qpUK6w3A8RpfQMELXgo4wR3p2D5Q94LHlLiDETUb33A+e01MRewrqe2wGq
MfzbvJaJQOcj9HRvnA1hLotLPCmEbZPL6MHOwEvactCG8yqg/0sXc4I1egEImgOtfrvXRtvADSta
Gziin9ZFAxtnshHvVZlpdstgUeH0E778e/QV/mcmWP+pHzJ9mOrnVCYkQTIlcBtNh1j48+433hid
b7o+bPyEinJKTnNTRixtduRLZogOL2csMf1GeLPhn5rkEzm1V74ge/S/igYZQGK1u66stv1zkQRn
uwQSdXcURH7Xe2VxkNSu1YF13NTrVnwIhGscieeFWlgd9VWhZo+9WXWyfb4xSWqGXI09P/HE/8Lz
tl4Gw/wZ+sZcAN4aRYtaM1nqULPess5K9MVvuLwJolPEJmkYv+Api/eoglyuShxTc4UvW8rjdA8L
D6qV0rsEcJSPnIU3V6iiq1wbyuqVSJcudM7P5I73wGx+VSUp7sNwKID2rUBJR+gnKdSOaa1+p425
cNEnSO9lrcJGkp5NBd5aIDzVAKuhob6eKJjudZd3cYSQ6Psrz6jXlT9UoESky+VloDGnjiF+cpMo
D+RRyXQIqH8j5GhvAQZG1MlgXzZ7Rvq879+5NidYYJwbfKxzOoRE3rn3uXTQQJohDdH/Cw01y0z2
VpN1lEuUmeZm1sKAFRIMUiGz40WFGy28mwAm8xHRaGn9+IB6Mm/VarJMDNOuZ+GT4xHf7lSHxJDc
OZdwLEbNmNQPimR1b4bjiN5/7MsD9ilgJrozzg3aSk9cH8tJAgCtY23kDL8Gcg1QW6QoaG8tBCPn
vsApHqvp8z7vzluKdfxxlvMW9kgoaL+eQQHg3xuqF88ROFoU5Y0D0G2ZFilleEJqvCHUsYIPEr4I
VmKsowibjJCyIR8zr39MwkWlfS8PD31yXyv6ZnzpZFNwtOpW2EZnjxupLjqPuLEAdoavTB6X8bJQ
R1GlNpFjOUuBDwmdsLa9S7s8MdUcqA+e0OLNlW6h/Nk9AxuKRfauAwudVjHISah40HpL2MBY7g6b
RbPPEJkiSLvsrS9TBzeHIwq9Cr4ZDlLiYeeEYqE99djGYRyNYG9TVwiPFO+8qeK+7AhDKWxqj9xr
n0reJSMkhf0ZbosWbk9BVrh8xOigWPXQTAUpnVkwasM+a5QkyZvmDn+rlqXQ2fZvpJKUHGPu/F/e
tZHcpbJnkd2bo9LH1BLpPEcgTOcXUpoDcR+j9rTieCrprvzPmza69GT7vpolQpa7lLncXKXHxpgy
21A64a6dU8GEexxdg2s9bd4tT8pmEpM4TEkOqdyIu9Kv4Opuf4ApodamktdgBWsMaeIzortGwwYA
weJADn+siXTnAhw8jWk/JuW8ayH1n4SDeXmMxCWs1nJ0ML5cAqO6gB0UdQWanNhpAgzr1in7xEbD
jg1dSG0uY6GnDIhJvMXootTdMpSGwH5RR2uBcnJq7EzOK0x6qlK2P1WR0VFhajRZASbN54b+nsRq
ryCD4QbwokRUJqQ1MbS7We/CMrwjFOCx0wrI9KYaLWjvSlDdCZkuB7WQThGkxFpIfAp0zkG4eHc9
eX7qHhM1yc5Q4RMphOO1JYRHHPQXfzPintpk0/Az9YhsEJZTZh8F3GR35KmRXwAg6btq80YCoMFs
Nb2vOVUxy0YXVuFuNS2gATeBNBP62uU9ehNA6sKrmnRtu318i+B/3CdxAa/6IVgKUfDpi+3MVZZ3
NDgi4d6fXCNorRx/2+wAOPTVEOSa8iQXr43lZxXp80oDxdA6u57vX5mHPjQaDFk91Xnk+wag/yyb
Xkxe7y/0F0kmjPMBULUetx57I4BlkE5X8Sb3sSBqi9+q4ZjaU2aoPDN5yB98175jshAkevQdE7K7
Jv4aF5q8hVBttdJpxCPbElfwes46bo/vN1hwoO4nlQ3UGIVMjK59oDlUsQ1NqQGa01TzJyVTighV
sZcsr7I2wpLU/zIbeOvpUCFbeWzkkB9qPvz0K0rNa23jVdhTY+xwtKKVOUdHReLL+B+z9bVI2gND
WtSeTOVrHcUKK9kts3lbIwVzYu4sB/cJnSMQA6t5lyqHfy2bcA2fa2M5/6gZZR2LYCcNbihAxllJ
w/oBl/FMazGxhRqSm/AeOw1GX1QhdG/XOfYInRt6R3jt48PdkYURlG+j1RxYmp9BRDOHTCgrHSH0
b8xGRg2hkvd/ks33ivsRtlsqbrZ5AcWhS5S1qiEl6RfOFNGlCMydWHMXpq0y7nNkhlSjh9BFgXQO
fp9eF5AqsfL31ckvgtxb3D2EnhFmjMgdFEW8tBwvUFQfrTbO/fQgCmMN2Oh+v377GplbdEdis1L8
Bepc6QYZwukTTvK9WTjvnapMFpFYDzm77jRTClDPoiv9FuRpVbR6rH5g+pVmRS2t9cLJs46qKCqM
/Zcnr5HWHJbgWEw7E0p8WYxf9Chn6NqZdvncZDYBEt652Enqg1sUe0nlRTbR0EQSkuWid74xoIs4
TciNblW27Pn5JLxO77KxoXuFjZsXwac7K7NFsfxvZ3jGVyvIZvh2nGYmNqOmSWvrLxDHdl6bj/eP
IU4oVpxM5R5Ox2zsVktf1sHfUqNiE+9g0ggHZmiSahcNBjTHpj43Y1TiVx0iuZ8EjunWZFUzYSlI
8hTjnRELEmLDDg2H58Ug3gDOx181tDCZITDNVB7lOeFmyao4X/pEsxhe4IUny4/LDNWJOlZ5wHWi
Kg2WlfD68ygdSxhsO6I3gP9/g/xgFSEXD6tWshX46xvik8xwmqVovwBSN279nFWyOLCGQ7lF6J9+
W44MAPvKG8FPPjP+Y+pfPSdKJS2R7+EZmrJdeuGlEfM/+plC+VcmvGbGfDZJDpsgKNkOb+ZvCav7
WnrMF23xPqtQzC99BotKmPtZTGfiviu4myN+4ooqPK2qFGZIGuTO71aZTRFnBflu54nErs3fmJUl
bTQscZZc4lXGRoccd1ChOuaeeFxKarIFljPvHIqeTUi9EJDhgqbGw2MkTV0B1beOm90Gw1xBatGC
Tjmqd+4i+gwIduz+SJHw22A4q2LOjlwD3MUdqJj3FOQ88v22RLvPL3aO+qGS5cO+ZA18m/L20PVE
VBGxt9a2HzLG0xNn2q14qLbZPKpWz5GJNuiSyHjnjtKZnpvug8OwOscmpFRPT86g8ZEiW+s/tsxF
ib+ASA4FX1Lm6dMIgkcMO94Jr1zwni31OoDxRvAdBbojQ7yECm3w+9PlXaFJDpEYFHEtAZHFCb/f
PkFzOg2MnJ8JxD1EXaWG5eufiR8oZecz/SV6zj7NdLhYi/KYgIhLzVv4fIwh/y2Oi2xZWE498wkm
9qlUQqvNRX4wK+kVpAv5dzkKSZLgQD9qecpt8CB3lHJPO3WvCtWG2dJv/OorRMwaseHwi72fCHBk
lqNL93pGznhRfU9cIOkeI/t8aAyr9Z/YDOnqKSNNKdc1RwhUkuMLAzsyp57fYXmZwXSWSQvBhIWm
Nt7Wxz3X0soau2ad7uZeiNIXJUiylO9KGvLLLNUCUvkApKZxCI+HsthAmFZakgRKdAtaC/Ke9Jx9
bTtV5wnrG9vIQg4EB2qLmCP8DkqVZRj+q86XztwCsjr7s8F49fyU8Ny4KN/OSGwhRx7ZHH5G7u6G
vozEEBvoGYfo4uueJdVOTOjsAsievgycOVPAtjA2X7IhqmLMvdG74wVOrHHV1pyvInCnd+kBZwMF
v1zGQSCqoGonH6jc7yoaob0ouODoCKffgcituC0rYwhxbLtOZ2bS+uKOmkWVxY0VVkhWgviQDtgw
+glBBg684JJmUpoGJGxd3fKEeQ2fkl5tng2b3yLvOw7F46EkHi00ysfsTf5df1jaorAsZ9Pq8tlI
MOga3ob8NwFeqbwjXM1bJWQBHkA4b32pfZOyUosP4KyELogcL+L4744Z1aK/2ltUgwmmE4JqTBUs
gWLcaUACFGoVSEw8FsYI9TrlHWFjHlMLWSTM26gm96oDS5dT4OMERo22W0TB9kadMDMMeHM+X7W0
XRGZkHfo3in/UCxwg2NGILkNXWeChd73e/j5ZysK2VakG/Vx0bvrLUQzObY0DSQUmSx1N5t0KXO1
8p/TMcAvcfxepbgoqZ91QoyKCJzgF5pdCsDd+w2X8H7KAUizim3nGIKEIZxIrrto7AxWE0kQkG/m
3jGqX0vrNV4N+eyMT+30vQ8b7jgV554Uv5lDX0KB3HqvvX5/4h5FFyTtpHWeU/scI3S4Z132cbYU
cR1UeMS8dhNZFKXQjpIZduY9h84xm5cj4mxF/QlGROGb+Ywu952M6q25vBTtagfjWKjEhKofOYgF
T3St+BzNtjmhTJFm0aNtffi0TKVcK2P7rpHuqC6g2SJ2knWjXQWv/VHc7xmvvPFO81fiocb/Zsog
RY2AALpEHmp+aAZk0Y9P0S5+34ASyOOT9z4D0sbY1ivxr05kcH3fQ19DAqIb+D+QXN9qgsGtH4H0
ehHt/aVPgi+30AL5CZeaZzrPNH6cfHsJ1J9BxbkRSsS2iOMpajfDiQT5aUC3ep5ORtAfGbzamZt2
cVMlUIEuZD9ru9Z1kM0T9JffqlAZTL60OWlZL1c5JZclsWMkCXqCU82cRYn1Ih897moxrcDPhBGM
bxy3PRVGORFmHr1LhVxLJmTfIhUtbIVWbuN1ZK2t89bp4u5LPkWgpFBiGen3fcStoC2Y9y3hY74X
85MhNRhMuVUChKSzmT5KhcJMArBeie/cFLhxXwVx9g7SpfuLbK5glyuPSw1FUX7VryHGK/WYPIY1
mGSxeCFpD27/1XShaxWANbYwrJ+rLIZzc7Zm+S082aEXo5iNHTqgz3MWGkGJLQCMA1eGLTprOQPy
DT5AHdGDs3QxOiWlZ0QhTWGwV0xyfNkZqR8Npp0m15guffvuf5zMgO7gv4XjUbEO/7JbD5p4lh/J
btH+auHDfoQ07W98nJISOvCG4j+i0OaKumnZJ1xifykdb9ou6NUtt8lOg8ZOEZ1yA6B6pV5bFarw
vvRAZTFySkBIm2A9Z5cDGG1D2HE4tXw7WcwJ04eTe+kmzmf2DsoJzGrR0yVfs/kugVrymLStIfC5
cNR6n+8FKHJAfOS/3U4Gqb0i3XumzD5ZfljW8hz7F7RU7nAW/mvPj7P2VifYWnlkMnROAUW9Z+tZ
NC6Mateg5aTHPNI2NY6qPY+ZHODfs29Zkgl6DrWeNdKk+mWkGXLY8Oe+toOYQ2Z4uY3gK38hlR4K
N4qyPgsseEgYFmfQuNkmRsn57jEkHrpf34VtbgegyXcP7qaDkTiCGPVBbd9TKxodhgkmAmbkDBxb
2YfhIsjkWLjMZXvUlI2nQ0lbUh9Yq/VblD1XzerHY2hX0c70gCv0FH2ULymaafE3yYvTv1nGqZ2r
QZ0h+PRQ2Ank01A3dJiy6CY8APrgVODRDooycbcRWejG+4XF5CtfEkJ7gMRjTTNdXf2kqSqnuzE7
JqU46c9KXLbhlMF3m8Sgsoz3E5hv2uS5Q3dN3KKTQOvvCql8/OEthuQ4aLaOzaRTWdAAY40uXanO
ldaJbo0I+2xTFV3orcQ+HYClpJAslnExz1Bt8MBzIpdy0Tzr62Y4SwWfc6QmGRXYedMY/dw0vbUS
1CEUwNoh4wYWa1qFsvVTOTRef1k9NHH+CCUxYOdm2tSu6YOcNJMtBlO/NqLiqDiWG/IzAxhiJ84P
0evJb0PyTRA50jOqMJMnaCLcG+g8ItoPw0A6Qgy1O3/TxtFU3qgpBO9vN9QK2ggjQtG1eAMQ0jiz
5dCAU+EXS63hHET7fWYfcE75z3tcqm4JIe6PLeORiYYHL2dssJo+005z0qhXdsRs6B24E6RQIRaF
5n9BO23M2ueoe6983Ei2O+hsQNHpUlkvJzOPAFSl4OFIa9EJ4bMDny31A7TUgfOXwSQY0VCXMjM4
mVeYbwSspm+Er/9O5fPKFxoVIG4Z6kQcG+1f7CFaotRVzwxQTaAMu3Gu/bQsCWDc1CtLqXLbv9oL
EeMDp/t6IpeG87jkAUvcBBnwjhC0e7YhfMAvr3PoRuc4xv2UJZdQNpP2EUVQEcbXfuakp1lkbd6j
uOaWZeLjP4Y9LcVxnUSetqFVqbklome1SicGIW8JOSylCas4odLad/GdNAWY1QO7eIvOxt4auGDB
Oj8HRbpC6xRXNaN05pyl/YpRxDPK9Da6H4/Ky08jIvhP4tzKoG0Ln9s+F4hrB3v2NlBOGvfEBaVL
RxyVANPcpY7XNSL6+Z2fm2w4zH23PPK/GH9INxC2wFOftBUud7RxpV/PHrf8N5rjCPaiVhdNZAo6
me/TUe2HdwTt40tdCvtKzpVqZsOBd34zK1TpS1RcjJjkQhU3VOgaKnV9I5NOJlOHoc5KXyR5zoCY
Rm4wSiZ0xVIIU9jloh/D9P8gk+K5itxo6csQxzNRlEO9p27dc6KeF9SHBkQ8LwHx4hUj2zs/yG6Z
t8suK7LehApf4SI5h3LPFgpuy2opMt074Vpk5HHl62TwbgHiczdnOoNuPVMTZGNb1Z/mDS+Kf1cw
dqCLzoNLkTQcnJFKH8ODlfIG087vK09MIjbBJzmjrjpAfdBImd9qjuS3PB2OkD6OrFX/DOaoxRZU
eIUk5DMV/ySMyXAqlas9BGyZbcNlskOFV/aLndEitiGTxer+QACGoyZUjYJwE/yRqACuqJLKuxry
z/lTjwMVrtWsAje0iJCg4wKM8R/xDIHtfnMNKSuykceXaso97SbhOPemEvwAuztyILLbPf4gPNF5
b6NzmII0M6GOQFOR1NQhn/Fip+HgiyjBIIbuxWQUsjWc5lo1v4F5Gt+I8Nuso6UjwdtfAxCEWTxm
k7tD80XxprjqNxMNoo6SDLCiNmsKervgfyg66l5eMvXCYpBvVCAUJQXCPwB8T+gPBSMbSX2cKtGl
jWmrWxIPGlm1gyL4cb+mQIsuztdn31GNG0zen7QT22wwURpQ0zE5BRPHT5JI2IVAXCxVmgiI6YLR
u94CtW81fO4TWz4bQZm2TMmkgI91GvSyxZI7rzfl1eKSt2dRPeMy8I1IEfOhpOg8EI+3VBynunfB
eHPX1QseWyaV7LIJTztKh1mnH7UgNCfeLdQb0UjKJTT21KLZq7qylscoOy2VWXM6Yh8tCD5BwXon
f3U+4namfKIUfVZpqr99r+JfOo14fLG8SHqJtKFB/raa27fOS3XpXmoMMjzhEKUB2Xzlmp3DtJP8
TeCpTBqs8/jl1ggfiiiPMGlGbUDt0BTa7WR1C2QVSpiDerhCClV4fbxWlj1K7AM50gqfX3/sGWJx
mvR7qJcrr7kvoxwEVH6n/PMkgU4NSjK1d9wfRS8hyCOSHp2YL5GJZ3I3kZZw9T5pssLTEqWpHzU+
zFUTUF2DZT2qp49E5zH7KMoejjpZcnZwMbjZqaC1sbWQMtSoqiaSpeFC0Yyk2f6/6mF8ro9liba9
8HzojbNq1cCrVAqinDQoEUt7bDeAZqoJo7yUWGhFQFFDK7BihfqcmGz93cPSPq8RxjHgrMkilLri
aralk37moO2RnAVug2Fogp0zof/c0oZ5K8plex9JkxRXmKGjBHHq8oi+OrtWWfJAA1+Pb2QOX1Ca
2yAvZFmu1J5t7V5RnXaDiuoYf0HtNIKa0EhhtnUIUKoJjGkTrCvpAL+ARlq7Y5dmdGNaUf0GEW2/
3TJWuubXCUY9/+R+7SXznWL13Vcv1Asg0nLE+88x0hYPyG7uwF49iVlCIYNWHk3JtiRtENXLQfjU
wmr3dizFA5Bc4J3agol63yLPCRYcpd2ka6V15DWdLsynqleaQZLRoOd+hMHN17Iqmunm0CTGZznR
yRRBJmoX7hnPWLWNUXUXGWwLk2N9vDk1tt1OJ8/ikgkX6RAhU6EjSego+HmYTCXCAvcPSYITCJGg
Y6M4FgP3XzCw/8LcMhQpIet3KdVnSPtVY0TltP9QBVvvZ5750Kn3eIQPF9Y8pRN8NYJ27wPhWXFo
ydAwS7RyZIdozLacFEDME7LVlaI4ygB1OZmBCoFansWCdVll6NcxpHPYcTMI3ao0yfR2McB4nWGi
aZ8gRY7lw4YNz/kQEd8Gn9znYYIOitdx0IHR2Z0CFDyySjNMBO08BPv31RMvjUoH4BUGQdDdNrsJ
DnWki8b+/Q6/eDm7/qEp6APZAWDHfOR+4DRW+ghBl8i45Q5+ETdgovkcw5NzEa3YFupL1hFyF8O3
W+bzGsIEaXAQirdxXJhUhGixZDE3HbDBQ2iEUigIcdek/u3ML+1Brx+viMIDlNoU7hNbvIKKTtzV
USlkXKZ6b5DvNOYPdOiPPq3VmNSvX42LcEcf42iaKA4cbXnMHxGojijoo5Lo5W6xHHw2L9obe0G+
nYGUsPWdo2AjpEEw+mgCEcMJAW4F9qSdUDHuYsdK6Ku1LbwYq5MuAQ5OlcEPE9zfHBySOo6VxF3A
1TsCoP3npDKxMZRszA9H7G2lIWjvodP0H4YTrDfWxzvC+V/OMZQgXpULJo/OgNt4YMqbdmnoxVMa
CktsyAk4GvsXGYkYUfg8P7YfJCvtFo99bdwZYv9ZWybQFmN2Ocv9/l87KiWFoMiuxj/dCTX/Hmwg
tk8wUrkCUDacoD90l+miN2FqX43XsLa+8ypqs6mL5zVcAjfUV4IrFPRgJrXpyjb4EVucAg2+avDj
z3P8RL3vOLBYSpEq0Osps8bgeeVx5XYELR1G8K/SoC2l1ZEghC/hThxEnhG5EmJ9B521cBtMFAVF
/PBV6keGlaKi2uk6m0+FapHQgHLfNdbVVPQ0BI+VbXffTrTF7O93M/YOdC4GOKXzDIIKsY5/GI2j
8o8L/LNn8YRtcbHJutRntCVc9DmRyXod+3djwnEZepfrhsuQTYHRZaTlFVw0Vk4FnJHJ3kb52vOb
t2lpPDeEVSjFkuuhFOy714gVHjq4OJNUaS1O/1XABfjEpDzWhAWnY9eJ1DtsmKKJrozWM4VS5kQL
YGR9tXAc+3/x9QgJBDt5GasG72I6rVEbTChpiMKLSQBtTyYSit6uprxwUPveIyOHgVBGhJkEQrLL
fVKbqn0Cdpbssr+XXqeZmmzFzVYqCjJhFyHjBQHkut6UD7vNTikWLGYYu61yr8O/AI2xcwYOAbqL
6h6Iu1PsZdkicNyfRpkfGTGj8C9n8cLjZsoPOJAAPT3qMETQn740+MOB3HTsof/DoItWdMvN1gSb
RwqBu3gVgWFhxD2MUjVQQF8fenODeM4RU/XV+bm/O7NYfja/bQpd5WtaFSrUtXRlzsSCAM+uQ/3+
LFiBqbRtnGXp8XopMt5OHyU2A7kD7GaDqbyQ32+Af3gHjiRqAQDjKPUDsFQPPg9mpFaGJBa0pWDX
oCAmQ//5D7j+D/8BXFNCtZoin5+Wmp0N3gHNbt1c3TKMoXB65D/Z1JHWHVeGxIgjW9ncKfp+8kA3
M+/aMvMV6z3Nk2+Nu1eUpM0p2yR3Dx6Jaun1OmLsJgWNhpU2F64UWqLnoFkK/5AU8rWNhhw1ymLB
Scr0Yu1PBz3Fjd+8tGDseX7VSi0WSVK9kvxlwA4pBaIm413FD8Edp1TS+B0MimnaELcEIZKqdJK9
HcNnKYMEzXVJZRpisCvW8fbUJb7P7z3ahZ5F5vYxoEwabfAplk28ZX2ckJsnmkJu3GIeJwzlO3Ja
mSY9H3VkqHWsNlkCqJ+QOHU3cCuNhV9qo0GUi+iDdSDvVzDhuExen0tsDI0g/Q6gK8Ae/+EUzwi+
F3S8hUPzA3GQrp4NcKXl1wi0GMFGqOLvTQ27Hv3yrnddTT+s6s+epXck28dAVTwfGiys3iEcdUJj
ZXPCM2/1TbnwZRqp4nl1WBHKh9+LkGh0rmtCrIuXAG+w14+0EKASSIMgFheuKTwInfnqDYXSC9Kk
s3/mrwcOoRV4Bsu5QvYTxP5hWUX+/j7YZtDZNRDpTcI//vpMLj9YywqMTamgK29A5gAMm/5h8F2J
FE9ZY039Lpa0tOllgFs4nSjKJgyyl2rsIUe9O1S42EdsW1mEl1erwwlS53hLW2amxKKwbzkGtIpO
30Li3gf+vGEDb1N6zDpuavpE0a/lJbNOlUIEzHKqYIAr48KmeMWjF14XyqJvHdIvKeWF5I48DRJT
Aafq6jfbRSpvv49dYGUcumjwXCNyvWJ/GKq6f+UmgUJxvMPd28MpUxc7MEcGsZsbIpTi/daOLKjL
Itbt61g8dLUFQ1fd/cqpbsM7iOA7VuNdjbsGCRGY/igq3/Dlo6efSiuPBkBV4DOQGfwDSaUhteIs
bImq7LpvmVA2Wls6cWJ64QtqFxutmQXqSSSvnqInMwOC8KnFpoM0qnzKWE7I00fRAcl1JfTp83qO
P9tjKjqkVrC8IG2chYmttQWygH4rkmsTUFjzWgJYnqwe2obHVWloLgS0p5RxkoCP6AthnzLnc/ve
6EYzmpo8oM/QrVVRpsSQNkc8ojf0hh2LxjNIVNccPEbpjDIBB0tEbCbCMcPV+1jjvwT+yG+o3o4Z
oQCRU84A1g4Fl4wUy08ltg7LaEbVPcWE2SbGOEzmOCkk6kke++zjRgYqXdsnIQxeKZFacSBC8X83
k19Z+BlDYPLOx2XsCRftheIt0aBuVN0Q45C2MKmeASpa273ZzEBl/Zlw/plIB9nf//kgAnJZbWWW
wP1gIbbmD31ala/tflXBHMim6AkO8qXnfRT/Tzc0OOWNQX6UfhxCvt7uCnXkPUgjGpG9gRDJ9GUt
6SydJB+YeSiUFk2CjD6a9afgSZJDrcE/wMSUzTj8rxc+x0REyVKwxu1FnKA7q6my2PmvdYALi7gM
z6sQxfJdO9SE8VcYi8kOI3WWshf+vPZ3ro3JtxUbHkmRIh74we1TGDnKoM2SKZD8KNO0kF4GpjHt
yzHGJ+ijMvMWEN2lnj+239S6IP/zJGZkNKjVCjUyBS++fw8Ty7JL6+1XUWBzYFO2Fd44bwC/axfs
HqcaP5JsbADB3pIU1anZbg1uWi8fOWALSwZ8GbNGXVu3MuiXZEu2Sk4w0TyC/0PRZ2sOpo6KvPHQ
h7Cg23L25JqtkDNb0hJvr4PA4aKq5WqupYDxu3jnz5D9e2f/YdFG+zSvHJgPH1fuBsyWcXLmzkpA
6VN6GmxOlXeJLnQHMa+/xmrO00RvD/as4X7pyVCq3b5eSZRIsJxaHRLSs1k8Qu7rMAUQm38ax91m
poamnoQw0FlrIMRjgtlC+NHSzjifiC8QCsoK8K8xl6ZRG5q46qzdy4rR0MJ0mLyqv0W00sbrnTKf
G2Y6upfF4w8XfYE1gYe+OGRTFxghQu9LMJ7HbGxu4D6prt4eMd6/1Ao2D1zrpGIkR1DqXiEOqEwp
Et9VpHWFpv3bhSgrrqY0GUi3L1uZeKhr+wWOtGtQg0rmxpkUjRzevHhyKt4DdFaDU1qpqXaUpfCE
EtfBHSWeN3F1cERneLKrOydaXgV26Nqw+iIGsGjtiNPNE0p4QFh/0LdIpZtpJ5YX8t5P91z31Hl1
VQkflCZ3aI30lT53b5yOcW1hvE9f4gA0BWyngk/lPD8G/xh3WJBkrfHc7DmAj9A8hTD+uVJxk207
R7ZyJlJPZiNn/kPhVEF0rXbHPk9cAeAvubM2RsOFFmsil1aw7ks8k+05FLGpmDEZ9C4oYIuLdedq
t+uRMDCoy8qatJPhHxS6/KFZP3ID9csDJfHrbs4khn7bMas3HIo9X4AJbWu8jNpodgbyVMq+WVBe
gQj0P3ocuTs2UULoRy3wRhM/Si93QpCc/0uIdA6ptsNcFXZuWu7IoujMYY5YJ41ueLCTOmtPmEAD
jVgh5DZKh1qrLfbtHgVO8wtOJ0oAsFzCv9iYQx4gYTxPx/+iomgFES0IvH0bXRfzWZlArVI273AC
Bo636g0pjo4ZlD4da3iC6wJpvUS5xXelVVJzF5Pp2H/tSIMnDaIw/UpwJ5IIHoEoYO0SGh8w+7+o
8QHO+/PLM49RAKGn+2dOhNqthR8B9/eNcCyMxgSmHIpZzfJ6/gJoRA+WTpwVrFjYX4GnW0JIhkKi
cKCih86Rgxk5Mi3T7g7CtDfu2UdsD+ZwQVw6F77dbQlBwlgyLi76jLJlW2Ipx5+wVLGmJFhBA7we
EfKlJNAtZCbvCu6YJM2qpnZlX0bEk50H8n5H23u0/smQSZHCzYDQ/m+tLnPeZLMFo2rAgxXihv4V
UNtD/xtwelVoifp6KmIZOMZFx+EcMNDqdQtccaTnaIIujoUeovQDFh3h3LVbOBY/Xr3IY22JscmH
tENoaax3spsnLu9UdVPuLwpJw+yoyee/SE+krcdbQcko5WyTUWu8owxh4dy7x1BGtbXnuCXEyARn
sNKSpIgL6SGTDTonRjxYWkQpNF96SYJzQgE1Imr3Ej5JeYRMBuxOF62TrBvxApMvbK4NbYiZshgh
OWrshnmXvbMPkf80Ed1USBwTRuSN11Wl14qOxBKAMeu/BxutQDFd0D1zIi3WukBHkO6r/OLff9OE
DZUB+7jGlI1OFsZt8XUflOjIX36totcHG7RYBh+VQ+kOpdMv+z6f8UPx85gbonomE5iDvy9ejTEi
iAp0bylMpJDQbxQm5DKNxGGRLpOjRveamfY7hOSG5A73LVTJTurZ/5b1cGnPzoab9QJFR5GRSLed
+gaX0TflLjUHEGA6NhizyHwQQ+dsHCIIBb7TeaCAmezK6CfN3oey3ipinsY0KTblo5KBr9cCbohw
J9MT1iyHWRHlShcibphljrWoGFyANMdranhDyaZ/J1WCZgCj1cIJ2foB+z1v2SB+vYWZmLrbEV5A
2D/WNGugqP827g8A8670Ak3qqUNdV33BwfYTfrA1ZgD5VfQJhAf1g7wmhuqZWFEqERXUDwvtrdr7
HKha0sC3g5FGMCt6a2KJD/OWBmSlVbtyHgatJEEwegNJi+YNFSHDGToUq6DZLhY30diSE9jGbcIW
4E+thyNhsSfUI8j5k5IKhdfDt9eth9N0EcjhrdTZhFrATNGuI+JoTIr+/0JfsZxt/8igLf/MAno8
YKTsSeslX1VDnCYqo5Fd7TgnyGTqu+0LRG835lJEnv7n5tAfZvVeypH6mC1tNk2wYhjy/x+VDv9y
N2WCH3QcaezBnwSvbnrZcArh7NGSQYfL6gZnlClcDpVQ/YaJ6R57AQTgmlk/3+jNPlzVCKfVowB8
KaQjFwgDslT8HIH1Is/yttJ6fu6wN3CRxg/r7KIG/zJTXkBNtyp+nJGkGQvmasbXc42yW8H6906L
ci170sAl1dBZNgxvOQG6xE4V9x9BSgnMaVrp3yTzY8scbw4NpuyxoUEEKtlQHLh9BPXC+2wZF7zH
ZjLjMtWIOjgKejbFvy0KXsOr9AaJilo5pU0muUsun3oG/a/1gONgbo1xua28IkDA4VM/NSeNq95W
ubSf3IOZ5csuUlleZrJx/A0/KzXBCT5Gh34lUNeU7aSjUvYHfpurX8H79nZbbKrkk1UrMoRGp2i3
gHQID9sxZJp6wiXMR0KvmpEuYCLDhwxNxmqLH2ImXeGYp2FIS8oRGCx/O1Bgxr40aickwf9rJ5oU
sPUzqYZ6De0ZT0DB5l/DMDUmNJgLn/bb2oVYvgovMGGUU2kU4v5M49kUH8UTylpgg1BdmvJjx5Gm
LSo5QiMei6pTCO2LDi14CCQnQxyN9ZWUA1tAVYkSAgHNUyim5Ka4RA7rNn/PfkEXQi2pkNs+xvD4
AX0P0S6ujG2OvqQIyi3E5R/lFAAZMPcINTonJTlIgNMhB9X1DyKbMpRVFr8YvVB4VQ95EJpeSKM7
8+K6HG0n7u7dejPZZrvLUAzaB2PXt0jifEodZbrAd3eVnW73J3snHmC3L29Emt5WjAs9weurx00Q
QdwmKa1HrVp5wcX8bXmVjitiQs7yoUuNiRyPA76/5bed4WsVZ7ezjXWBDcqboRII7ndtuuFghql5
fD+xFGQu08yV/PdpQFqvughW12sy1g3wUQROadsAsp7mIsuaVZtEyEAgfkJ3OHqLyKCxyIDriKMl
ForirbXoBabRmmE8FjYvEpREwLVMhW/RpqMEf1oeaGSlKcTHfG2KX2pyabSSqEoZYWOvYDCtJRfU
5FlHUxELs4crC+Ts8rRo8rcJKBtKy/VRC1pB4fuMAm8cCVF+14oKEMNXqFll4Bw5Vgp6zKTawmWS
CbZWE9oUe/57MrWRDImqxbP7UX4k1XXN063tXjNGWpgVflHT0dQNqh+Q8eI56doUOxVTkmRzc65w
kx3lJYb5VRFaXEvw27dIt9Df5U1HZCXc8CsbOVlZS++4IvjV0rd+4HilKn8bZVsxD3mzGxFF56G8
AZ/UrfFbyywsZAW/B6JyplrsMjqt8jePwK4I4VE+L9tIqO+VY1VPsN5Yk86pZWCyvsVYyp1DrQgN
YBhtSatrDSuloo0zrZnilfjOt4hztmnqOC5g3QD6KkZvO5zLTkjdessYVQYX0cgbNXQRlNL7d6c1
IANDliP90De2sM14KDhg36cBnX1AZiMWSWoFyzK6rhuDcg+FrRwBRHFuypN8LLkoqDwNX+kH+kVD
xKzsPJj6DTc4CsD5BGdIrHuNV6oHTD7i28A/GVmDPCBQapHPe/MJbm2a30C4YWkSjlytBnfJVCm6
fUVR3vc93qCE19AzC9PN4avxestc20seSTxtnWPX4sFeq1ZhgkAKMq9GVLL4wsqwZFftRZ/ieKgw
a4h2Sx+tsPrgmswhGzP1Axd0nPhIKA1XTZmK1LWnKCCPBUhcQZpZYfGJRdVEIPPdVbTVSJ/4T9U5
Mi9TbaycIxuhQtcQl/OhAHzl2qgsfwYFwYHYIL3aVwGoZ1cvi3U0MBjIbvoAS3rJylE29qn32yaz
fIqcCVN6WpYA+1BKyk3+WVkHwJtr/SYRzUfGfQY6kZs2/vJUKO+a4550zANR18ObfaOjsh71wPGM
C99HEwbarIaLvoYqtj+6OGMsKZfYyiu4BTHcvHc3UjLuMCbc90sYLdFDJisSk0+DR5YMW5Ww4rGd
N4Xtimfib0PB5WY0v4Hwrb3SJ2Flt/FnecOxj3B23nugSt8YVEWnPCG7oKzL+uhQyt1avpqEH/Dz
x2+H2bAnBlD4N52J886yHeztrBzRTpWhIkAqDebThIxOZ7sbdgqPrl2fwttGjXxb0/qYUrKaUywq
nIOXUg4ZDRIeGb0dLI36CkPGdh/ejS+pf/vbvmCxgUIZjjBDRMIpuHyi22xnJKcf2IRy/qwfgUYR
ET+11cznyvsv2yugmGB3yc3FcqDHkL/VYUpi7G804N4thpg+3aHkF1fkb6FcK4HPQ4tg6sdXP8IQ
J0Jdn1DMGzgIlUgM8eiRh7otuG/srvYEnsibgvxOE12Knm40fLjXX864T7F/inEefHHyufeKrsE2
9+5nawfUsu97vo7ZUOPmD5g+X9tjtLl15Qd4v8N4DAoWh5hApPg6ZGq9dCO4A7LCPoA6333DVbHc
Vk2vCmfVE5oj501zDPiO/Z51l3zQOHLBe4mLjJw7WosWmfnmS9f0z5uR/aYTObc4K3YWVzG9mgMt
QT5sfnok7GyPODGKB6sAsAG+lVRDswKfYUICVt/dM+pPQF4ekYsICdGkG8KLl6RGJDyjYtWA5nhs
khg0fPOVCtghp+hZk5vVqiEt2/ysTsy2/hNNnrEdnCXemkU6j42QLkpp3hJOSnPwV2n5pDpYwwcz
Hq7KjmzkBQcRWOCCBZMMCA+pqCIg9wzmDqijhtepdHiaf0l3rmX17B6oc+x+JpFRa6xsMZFcDcDO
F0ck3QY/JiojS9FLzIGgGk7NzvLLw09k+ypt/oimUVsdTUnRLbirYP1wiak52T+D3N3k9WyG70VA
3BqgtJJ7aYmNQ+iYJyope+TG4lp1mrOed80FqIsj5qsu8epOCc+tRu4R/pFkYoJ1D/ZiQAUOefWA
eJ/Cw4eUoqMb8mHQQkKEFfjTTlDQHqW/+ERU0krNKMjYp0Bdojl++RhKN4kzfqTFBv2NJNOhB7Ua
OJP1iymNVnf7E5f5ctj8iBhet2j3JlMUiyWXeK2uvXukUYN8RGN9EcIFKceq/B87gr8/D2xzHV4x
8gNrmFZN5Vo+MCtUOGKaIFReVxXpNc8PQUDhTT/Ng7r3A3zHFWJVsbxXwLlfkFU3wRFIMWDr1JVY
2HBbhXd7MT7BR/z7Jsp3Z3iYMk49swSOSstFK7BhYC22UmSzd0WDzOES4vS3YcIi1zXqolcPUa0Y
UE8SASFaTLbl2z/P/zoV3DrF6fImgvQtlUOvotryRdTdrEqESrN82L9OZ+TpCmqPGGFn7IIw2qTp
/DNT9Hz26s/43J9kwpnXB5yObdkvmmV+MXruCimRLDlkuT8iGhBgrsARS9QvU6WaHwOflquHcla+
cC2so74uZcVOwl2D2zAnudycBuYv0NmuXhZEGTW/2I8kACGlsIEmpgg9RGwQaHwY1ugmGk5atXIu
uuTeubJRnL3SjsILfUVgdLg9uUAdS9UJ67HOE9gTp86ie6eVe7J3pT13o5Ud6Hs/ig4kdZz+qiyd
rpU338F/EeNl6VZx6eGQ3IfArbFOVOe1KPE3PSltwviBZoBukMhUdcw9PIxokjBsMWCBbJfqixyj
N4D6Hi4SwDbY0VmdzDyCuH6z/diEdeOaF433+37xqd6Age9GtTkL+mmQxRI72QrgNMTeqlG+X0+d
T7vPjNtM+hXJm8xcy7cXLvsBPGwrUBWZz15faJZshxpkKHEiSVs9ciVuHTAB70GYk0iZK5l36wKD
xRlqdIdXB75IrUYoA4Vna0WwRouHwNCiXfcDSnjFLfQkizvZ3zjJ0UNROAOLzhruWr4TAok96Pq2
2f6vBj6+XBxSWzSl9TBFhEgXI7UtBCrexFXsxQW2YwM7owVHRmJCn5cTHcbVOqulkwnyFzdC4mT3
mR0rA3EFoobsrWnQgpBR7p3LGawPHSWkiKAlwKA6G60lSsZVM2ov+QyaBXneHBLBpf7HBu6QsQdB
KCn3TmxzNMsUoMsXuVeLbO0mWhtZkVZv7Gf8e011aRt0kRnC+I68J7geatYYja4BuzVNYkkMjjoI
zaBSjqA/AexuBq48djBGAO3zyxqVDmsnNbt9250yuT86Pd505ybJMPLc7wvO3L3WbeU8e4zayuof
RIVusEdEmtegXG7Y7cj5yCjDynDTdApOk9jcgVtFEJ3UHbh3cvaCM67ndqQApsZ4Z3mjzQ8HOnPn
SaY1Zssg7tJc2bhXWUTehrp/Wk3fYxY1VLg7USDP+Ob0NAb+oapbILww51Kq2ajyzQl2AkVXWkXA
/czRQaNG5okTP3NQb6JHL9pcsIpQDnlj/caO54jK8/Q4aayTC6Ya01ZTM+Jh/CkLKkkPYEUb6p75
OaCVuz4NdS94DLk6anNyANQ2PKrWyWulJAFZcnzC+W9joNw/RN7vjyTbbL+jDC1iwMJfseN5YeBn
Eak0dbA4zDc0godSBi20z9X7V3IGWok6PP8HTXw4Ez+aBr5YpIk37ypKoP6Lve1fi5HUyPA7Dhtb
nYQfZcrY9XF0ECRNXclg/rMSwaVDE3sZOPiOgWMlD/Kv3vudbmvMgjsaBcYZERx+SAXoM5BDOT0F
VzWk04pNZ6wd2/Rr/Jkxh9nonmXc38YNgIP6C/wjLTUdFFVcshun+PzRKSKMabZu//+pPFlpdDFG
0iAblNQxQNGJTmPT2aHDv/GPxVVUwlYtU6UqTSeznwSpIoAl/5ejFLqQuqh7WPqjN3E0Jt2VcudC
zFjUEeuriKSCWGCUnytNjHLD7CJYbRv0u1rar0V1oNCU9T/DUAZBOd8n0I+PANjuZf/0e/Nfq2ro
0MbjtGrB58vjQYMaAbL25VshZCbJmlvNukTTKGKN0a3IBlw/cX5PBiRayAyNFgWC5bV7u7LIaHrt
+Jms3++jlO5H4CqQosRPn+MNQj4tPjDJCQi2yG0U14nMXq4AswifWMsODA2P8GN065sEo9rMtK2y
vHmE355b4P+nXmJR1R2nKAV9YnIrqWSX9SbPe2m7CdJIOr3c0QJC8dTncd9wduxEX9Dpr9tLqB/U
BgKU7EAH1uxDK8sB8ecw9ik0+rL2Wt82JbGJ2O4Cqhc276Z/y42c3pBNGABPmPLbyHLshQdnX67O
dzHhYjTh5sWFxFY7IXXJU/XE7Rfaq4h7hHszmDEH+R5V/Vj7rpr4rXw6NMVpCgFeNQEz1bIghmSF
3bfgSo8yWvqsqo/4b8E1qiXySL2qxzOXGX8tQFf5S7zhAmYoja7P3hIBtUABuDiyWneceFdA777N
GixiRvuxD/ziwRU++C+2RG+ud24quWbQGwaSJxei3XPDn2xQVEbfDI4zd6DSmzk5dhMHdmNImFoM
OeVnLdhibfVuMY8bSErZDnVU/j+FKGYwSHb1FH2PbLxKRIx8ibOdOMJ5AGzbWmnUyZ0U2soTIBaR
Umc3ogyPlbDuYknpBrOexv9x7goMnee2hrAHieOhvnoL8sUlEgidB4sZBmOk0QN1TKVVRyappyaS
yBebLXUxD3Z8RUe2s5L/ag6Gg8JO8EcOhRUmxJLKnZHcOBQ/IxbpUVTzW8fTNS2fOmlUkT71myds
DglfnU+EYNlu0gEPnOX2qBr0HibdbceayJDWkvTVHPpCSErqpADzbhq8DD93ycPCsE8wYT3fet9+
kOcTe0yec4NN4VN3p/nXfE8WErZId9A15T15ZMmpwNatIVgoGIUHpy+pcTQZ9hGoz7dy8uivr3zG
IRkKhJhBsiOrghvIeBvocXqZXsyPN1eipkNwAhHpXnH8z2fSw4zCrKTiiNlgdlZMAQs+HB7kYXQn
BiLL+iESeDnD5sPn9bxQjOfiYJvQe4oPTIfRa4smOPyj9ziS1/QmNXslJeqRJ2hNlN6rvOO6WIzG
IiiNQNwOgu8KiQsLvGK4cvDW7Zc7GKZFCGCyYNTs2KzgCkUNsJx3PErs710MZ2g6MCubZYAMrfMq
TJd+uvC5Q7W09oXy3E7pGsx7ZyH/jVaaIj64pxyacDHf7DAEM+GbnZMWvBzm2HCurCqysy02E2Iv
vcHHRPUj7fq97+P3LyYwt1b58ZRNfKoKFZxSzbWNXKSFktUFdETLZYf1U+4v+/LTfpuanSWL8Lot
PtSTDBTqXbUeSdL95abEx7FfOQrydPdN99AfUNSf6Q3gKrOGQQa0CVPRf07LIZ1xQVx9ylK6byFM
hEO2KC2lbe4wkG2Ns+ln4bRkjPbxjzNIYpoO1+5TKHA3iat4XP05ZUcxGbZ8kDy2XhWqDVNOkoor
n6chYUfTVpOF2cKquMwo2r6A123pMxWwCA8B4Cexp1deNlKK+gP24QhJXTYyqlqWamzhVksF8N4F
D1A39sImu7V6cBu6VepHCbbjQ+MbQ1qghtT/btIHJL3AkpCbgqMww5rNBzBFUIbEh8kx1K1vrGzd
kaEsU10xE/hrM6uyf2EsReIYWZiLQuRPs0zSCmwP8j7xWoZnRuf72VShYt+tcYrBKIeJEus68M/x
hGcCKANqBU/xqQeVFKK4Ni54LRVIX0+gsXL0q23zdWMcYpUi9FMdCMIlVJP+9lFfq6SpfDLN9xDt
jQ1G1gPggS5B5xJV8fKJFUl+VGwhBXl/1XqB4HgPzwQiL79hztlrZPvRIL3N/BZAUewI+PIH+QQS
P7myeZpkvcfycLruT/uj/VtJ62Hcs90Rvxgsk8b4beWXse+fqYOdobcfeU1m5yELm76PcbSmz8I1
G6Oq9WBv/fds3UKjUVVJmQ+ZOCI8uoqSEPqLdJ5RiM4+lV6ZlFaLY3OFhOBZl8g3b3a5cFvZPe8p
jdOPLrppFb0j8S/emjUrj5e39413d7FlC40pwOfjOzmdLVy3jCQge0ZW+zHNoUTSCN115HL3SvFW
R8gqfWXfqOoYlaN4Rk7obGBvI3H/BTTLCem4V2s3JP4vI+pDGvraSai0n7JdBKiI3JF0taWmFELb
c9aOMV+HSWgHtTJVoWsyNuBlv5aIbr9w2zR+vC26TuNDI1Typ3JUVsCrp6kMwI2lBnbs6CDTQoLZ
1zqbwC7VyvfCXkxfF4VsFHUKd4HlMkpp3kMNAsmKOTFc1I9X72EHoorqdVcg9bmoCfz+c1aQADQW
5hkm+PbS25Sgmz8ZTF81EUH9sg+fYygPORu5r2nbf/+zWfviitzB/ooUXciOjkUC/zHLQRcgSsGs
z8ZwT8AbeC6UoHPQ9m3JRXNB6EChefivfkkpWLQx99ipntpOHlonBbqvj9nf9cYjDDGOcyvxJ+Ff
5QyqAZlJ3TjVlATJL0YTaH2KtU6IYsa/4a1ubD3Rj++RJo+bQAqwsD6fCHUTXy+b/7z+w+QgiEZf
A0v3YZhVVYIdBDbyaqnOlbwFABgkYgMlLCvJK5e7a+Vdx3WHONYiuSKKSEicW6XGtHmUb0OOtnhx
KcvPueDr48/Hk8xxpTQlOfSVtkI9Mb6MhW2mQY2wCAkqtjf3Jm2YEiz2vOgqdtO701vTTPhcvQ1O
Hgp3ilPwk531NyO2QQKACZNRGoCLnMv0+kAmeiiNCWrK5WOG0qUtJYcOZXHZqYSREf2xoEg6zF3/
R21vnQyNFFEIiZKCbsI/e1wHhWj5jwSmXP8rUCxsL8p/Hh6LE+tFIcq5p9Rg7g4eiueqqcbBWZEu
YkjWNRkDzv9r6cuSOiWCoqJZVutSSvgm9xDdne+vE8KbR9/8rXgS5q9AGdScBx68O4fyTJHXpFD9
RgOJ7D2LKRQBPiW2+yYB8pfvZ/xCERotOfUcjHp/zbTSafLgjgOXuatBUhDg83SJd7ItNLkuBtrb
MnpD9w6S5nkZvW1pJPgrYdRp0NthR0jCcBGRbNREV4cW3d/uqK/rRX2AYj7h454o2gHVu9BALYi9
J+ZjnSq9V4iIafL5YxbmvPrEgRv99/5EvpwnNMX4AmxcP3Wxb2C1tFqOkTb7rChG6gCd2x8C251p
RxqYpiPV+zjHLcMjmYCSa4FAAjkA+HUYFgxGHREWE82T6uDTv+im88DSXSWHgckry0urE5bgPa7j
V+ptAbEJ0qk+fd7MqifDSbWBYH7hCQtppogW0ubyEbq6ncYXKWPDqfgNbKgkX9kQmlFvyvhXpZMD
Pr2GW28dQHyenIu8UQ38ey+TOBlaV5bTIe+7O2WLUnuECoFCObKpTs2ZSyzrgzFc9S0OEzyJFzin
E41VQwLZ//UbGGIa3+6vKEPwOr/oCl8gswLxHzvko9dGnwYy78xKwL3cyhrpoVl29KrYc1qImsi5
CHXARt7vDm0g5hEpwIDzO/LbA6fEcdFz8F1jqj8FFZRHVNgUGCzYABWIUP6tr2sz5WS+OUbn9/WK
VeoWQ15uX7231X02LlE8bOkWiHUeDy7h8PkPV+XgYvQjNhKc1hL1XizEaF+ms0eS4jFItJ6dHlDj
hMabUP0PIMObWtAHRcNG09jPmL9oGy/2VrOpLTUlp5nRaxzoTpw3qST1s5DxijCzpN2XrKbcbpsY
c1KbcfzAgeTCufkCkrs57Wq7juAlclEBV5tjPQhZHwvoedV4NPdu+0fpV+y85ieIQ8/YIJHM05Jk
JyuK72ouC60JD5Oamewv89sOv+c5KAA//IOgMXAm0JfenDW0WZQVQYzoUrsv97ZIIIRYgbsABc8m
wkkMlz+cmFvqJOKNbSENEXGWO1mYtxc5ZZ2KqsfNCHUfKU+mtqV30eIKHommSRPPP3bBIJF5MSxI
3DJSNE9umIwfXrCit7SGWO+8NwXLneh5tPTlG2Nwoy23Wk3HocJf8J4JUE4P7Y0Yk4X6VcmkWODZ
KanCDCFfAKBM9CjR3c4rT8oWIytJPhoXqOR8GhibviLHTN6yPACGTs7DqF95hfvdmLqGppXerAb1
oVLfzgw5UjBjJ3JkcmbkEDYZAl2RAUzSQxze2VLR3HnL7RDl4S0UNx4A5yLNsMiOFUe3mjHnT4dH
3Vm1oLPGeGzNfPnRB4PFwiWRIEkJ91wwzKONdi3NeGVBDIWTko7ekNeXNHaLlOd6aW8C4VA2k5t0
oBqCZIANvKkHdBC14au80tgoeuVPd8P/v+iKKd3UHGJrRmRRUltyT6yhUiHBuaMTPiUXkuFTg6Yf
WXNsMk3i2A8u3vlfhpo52ZQ4TVCKE2XLO3jNwisjQCmSTMKyJ6xcAzcQrFi5xkBJPPTf3BWYrbQh
fNgmIMYZAUqmfszyvXDIFhGXutE7Z9GTxVED7+cE/9OYVwCUYY70VtuD72UKbbsROVxGOJPio+Wh
hVdXhYiwWfZxKnlUKzWjOP2zNH92Dk9kp7ZhUl/goXvT/d+EmTPxM0SgqxNVWTXQtgLynlRZMoRb
efgfTtsaRwdakL83MnDmYN+RxIN9fve/rOqbtczs+hia0S3TjI0sJ5OyAGEf+T1RfvvJHsYidJEM
+taKHMvrt0yDNaTrPLpB/yT1J+T7cgb4kMYqSNq9lgtLTX7bBlr3ScUvNnOn2YecEw8Upaqt8f3m
3CiOXFR+0VyT9PjeEKQiIdU5SgRYqkSHkYy50XmC8HGnJ5oSc/YM0G7cLU/wTqNQb6AIh468VajA
m66AMtGLsX7Q3QGVideDDsbwxf837saxg4dd7IqZjXC31xOv3ZqcfNa+n2XOr/5jNX0EWlawFCAQ
YukyRDixpogp11I1rvRY9RKOTs9UjcQAXsby1MTZqEDuHJloAS7nyzC0qdhbaij95JXMgoGIAuq1
uZeoECrgnGzlmYjmxZyG4sychRdfJp0KPtyT50aGSTT3CO38PrzOphBv+Dvm5OV7tj0IK2fPwUDI
q2tQme421Jp+Tit02U1XCdTpz4ZfGPPkwsZ0W2FjOYWKWbQfDYJQ9F7uxCwCIh1i11Fu7lu22Os0
W6calsIZnDW4O0k9knYgDI8+EK0eLiEbfuUslz2P0wVUehjkgp2nZelkPrvXtPTZHrY+tDtjPk/b
8bZw7pc8K7va1ZeNUwiWNGOGzNzLSOqEo7dJIn0p7V/iZnNFvfruOVLhx8sqxN/2sC3SrSYWql0G
dSNqVASuwJZEnXMKmoGFuRadI8SUviFVcBidGC0c2iNW5s/iqfGx7B/jyITfNroTOv6NH9J3CBY+
TtAggsbnMbDy2u0SOx/BzdsP4ECUkQZknY55z97K4p1RXwTqr4bmPwW/iEC/a88yJK+BtrOZ4jpn
Ky4+5XgyMauTJ3HyVuwRPww+hZ2kpDXEUf7hCbegSvK7sd0MRpCCx/4QlguK8eZDkuMEm1fEDuDk
1W3XFegO+B3sPxMH8gIXz07a/HEW4KDWLQVkfePFewQgQLgHyDs4UaGsguAFvmJyoO8uYf8Ag6gs
5sdDlwVvxgytl7k4kpSmX77gtc6U+p6cV2x7IXJ5Hggfx7xxSq9kD5jqu3284R3YYBZj/92L63Wj
MhoSR388VzrNXgt7jjSyXpuORi9XPkLa3Py1p/t+UvCNHoFZX9MBCMK1lpJGo/Xk+q4ym1pRKK8P
po5+RScMG81vWTo/BA5UDQmWueiInKL7TU/NPt3/BOOPK4W9tRnJobta4Lc0Z/iQMP8NvN7MvzV0
EhW7nPgRyFcsZiAibQ+h5bAy9HxLky/daFGS55TntrYYL0/VrOGvntvhkmRZHsJP5ztdn0lfWmlB
GwEYhmi9P2o8FGrCsXabzAjjQL/Rh1bb1CblYiqlkbpXdGhnThizm8gfh0wgkcAyXU/+R8ItC58M
bb4QCJkuPjRSClBQ5W4sHO0mu/vUTgXIsva2q3dD6p3NeNQXoVvBv7Hw2FirQgOb+21rpuKPeG0d
7Wi0goVXW4SSHKKw5XZ4yh1CT+u03MzByl1s/Ph42tsfnPY4cqMglqnjhzH9xsmXrYJ+CwiFYqss
++2bG4F/czokO+9oRKMY3BsyU+43100wwr96z1PpMeL0mPOSNQ0J1Jhc3DoN0VGD9oG0LJoE7OiW
UGF07kndcAFb5LFqDrmBZ6cyjICc4mYDN/NOSPwfNgRlOsrk9s+EaefxTBvuL4rDTYA1D8Y0rDI5
AWHRbLJzIkYqWUC4tn6SVntbYWeoWXPFbfS4D1tGeZ5WjkzU/O/x/My/GwOpE5YFr5bU+6eS0VJ3
OZkgSrdw6Ym/LlrXlnIHLeyPYp+r6fu4xX2Ncdnql3jAZQpPVlXlngAwI9BbprbV+KxjF0dAj44V
KLPQY9HB92XEXwfQ6FDdRO1n8Z9oiY8u4bgOPA350B0pLb283WS50WrFXKAy56NtRW1+DE2o4y4C
NgvEJUlM+6HdJZZZ5BhriMOEJzpwugJcddXLhx5ZT0AbudI5Vy1NcYsLUamVfm29h/t6z9FLBEWy
MaJkw1QxXAPd00k9d3TGRZDjoiFWsgiBG/DE69RA4v0g57cgchpmFUjMrwd+EQ3OJWUt/szN2Gca
mJne6DukRedEbjqXfoTsBWt8PqK0OSzxQXKCBleYmtGk2q/NTlhxInXSDBc000AxxGf0moch2B6S
8c0jheCr8vOZ/LSFmG0WuYeTKENyfs98hBctKwiYMAjcPuX8sN/b3MkpxiwB+XC8b1c8JLMAePw4
YigurJeZAj1CKpnEUQ2WQuNIA3xz388rubzvxqeBajRAyU8V6Pl381j1SXFdhnbBe9tvAPE7b7G2
YTrofeavBQYm9mCiGonDq/zGtToY42CC6dJlz/Bq/C/dQ9LYjP6aUa8QDoCQsuwC7oIRD9BEKsvU
YQjlaLJWnE7p2XG4m8W21k4VDExtwRUYvsC/KHcgIx+vBO9EUuSoQhJHMP9jAnLGMB5Zyv0IwGL4
v3PwyOF2XZqU346ZK+UIiCwUyanOgh1P7kQACz9QkYRED185CvHQHEM9krP9IcwZZmGtjP4F2pM2
kExq5Yhl0YU5rSuEla+l2yHTOfaCLUKm+wgPNhyt5GGgT2I9HSfYjmrSQqGfSWzdBRzDLGXAdxzg
SomD2OuzMNztoGhyRbtPYdOpZOd143CwLot1Q4BdywLD65n7F4KCcs/5eNvXGfP5wJao0EfTCGxB
PLAt0KBBmEXeRgU2K04zn7Z110DtLtarH7OgddeYaADDxphrvdlSrAdjc/jLsD51wDUWU7gs8XqJ
O6zg1xkAwZaHWFY6aqGT/qq3MRSUboKGyUts8menn37xvgqMhEOy7YPcGFr1yqChVS+1h+LJPKvU
vNwbfhvXk1do6R7Kc3Cd3j+AtM2UDJRkG3O+D1RXq70+KBJDvESR8W66oVsX+BySlDKtWJOWtTCb
dxx+s3/3QWt4Ej3edELZrrGet//DSJWXeNlfCvR78RvH+y/+yq50asr0ZFPFVe0aC3W50/iC+b/1
OSNbwsJO9S8weqMjVhdCrJKtNAoyLqfUyeP59lD1ZQMMCt1Re21V/5abJe/0z4cItIowbnnExnnk
Z2pJic+ijZym+AXmLIR+sdcIUKEx84AJPJxIfYnrAcGPUk71nuxPN3r6aWxuiIA7H5kNxqfXbDXf
F5nyBMdWnuXVPfC0RbBFb4zRC7cwTCUVy+sA4pR/wJBPnRIQ72K8mRc5PeCUa4vTzA+vcMH23Txj
ebXokDwHRkvPdp2fdsDe8nc9JDxfOSr7YdamsOBcup87mfbJE3Ns9JMtx7NAUklG9MZUKohCeV4B
C6ZxX0V0q6PjpFq7WWY+i6tLyTM9g60sgLV90QDsR10EiJCa2zhSItmrbqB2QZz9cY3S7A2kflPV
s1foYED/0W1YhB9qI5v7m40+sgVSJjDn+/QZfK6qMRjk25L27vg2wxqtD70NPMQlkiTnfWC4+yjk
NPOYVFMtTMdxYmuwK+5W1sOXPurDTmYTU+MrhUhZFOgjhyuKYA2MjEkVy9+n0u62CIvg70sSRcin
hZ1soItMy/zt+xOYM+nNRGBymeXOhBLTaMBRtDyQtcu1w7RXwshV4kXSv3AWufj2P1LuDJEu9YzW
GTnjqKWOpp0pODUpz/X9dTvRmRtJcQJpiM5Tq7CohaVeJFYBumdX9ZSuKipjOOpfSKWWG2rkqmxP
bToNtfFmPkMvz/5vkA/ECamk7CRe33lRKXSsyLArhUQjvl22N6DXeRSZAcNI6eUERKtHzwEwrW6Y
y4OWtRpFIqWPeD3Nq/AM6/nH83qgX2OuQJEZmmOJF7Mw6QuInvilgp2LFGQL74EJ/402lhF1GPMe
u7KJJ9D2cDiNkTDAW8Xg0ZhOq8vySetWEB0LJzM4QNhG+9dXR/bJ1LR++wc1QQRNShFqaa4C1Bqc
HbRLmAvTDs1W+nt+BSjEyt2260x3jgb3Bdgzqv5+eofGnul7MBJtVTFVPOHyBcrSmzI6m+Ayu/Kr
UGO+alxGeosRSwHekRecFMCUNbnyOZSa2h+qC7JfZeIzXyRD6ynUOp70tkqIHd5M4WEiX0Yl7Di/
4KfskBC1N0rKEr2Nw3DJL8KY0aMHo7tngc28m6mtA91BO1JMB9dEOd+zZAGMlFHfpTwJ7PorChrU
EsBv2xK9vqYXm1hlgufifhU1s+OxpW1Z1KvtCDgrUwAcuxsw4e3xf4/hGh1maFzeHoZ4Ywrg03RA
EGODr8uSwl+rbHTnYMqod5Jo7pdrBymYP0QxbWi0SoB17jEUFooyHhuCwcZTe+k9rpHFmq+9L3zY
+i3OGzzQ4/7Wt0LxsiFY7EiX19s6zTA3t4nZdVN4YlzpMXeZoDpT2RSj9645nCrWJx9e7fI+eN+2
gwzSZkMKxn0PJCXwNiBiuKSxYvYaimDP/T8s7Vbrxc/2Ipycg0OE4w1NtOHnNZbs3OKP4pSOSjO3
KvACL6UtOX9zF4r34Gs+fqIKO3C+6KEfUGgFBcFMv6UGF7siwE8vbVaM2ZTXWah7KDGZnKPDkO26
VAzFgVtrAXBViKLmkZi7MbmDlRfhdJjw3I+Ywe3H38lLpQl6VUVIPAFAftrIT8MtA47Gqbu2K+OW
9o2OOx5nlREdkSVfT0SpBktySJcQErHNkFPrkD0Rnp8jFLmFldLr0Udhl1czXQLH4B9LFkJcyrun
/kpnpIjCxK7hXrlzPH5XHjCLuJzdNylII1k3K2+3ceVlXYRlBmHv0BMyGGOFXtPU+JOr1jOr4LJ6
NcKwh3Dgme8FxmiGvln5l8nded12isZK1K2hY+kePfkDuN/qnTa+85gbIvb/PHaYjRek2Nr6RJFq
Pt/5JbgJtyfq8ayj86vJwTldZSqLHugTqorXhkxJwNc4MQpwV60crt1XRm5dz4T85hUZj81Fftpa
dQ3ubWu+T22RlIrr4YzDvfJ2GPwXXwgxf/hp6S5k5H4kre3wDyJvyEp3R0QxFf/laP96giGq6viN
zB/leG6OhPrVAdobLehcFaw2eYg3cLp6aM2yMU6b95CsyKA+SbosKBmcOJ9VachEAUNobPc9FkiX
bhXgh7jsL5fPsN+uwcA3lrXQs+sUBe5GOIBoxv2yQbX6EoOZlBCe4SUCscKn+RJDaex/lTTpqnOq
FV3og+959z46KVKPzjLA1qFchel4zKg8N3ra4fWC0IuHYO/3nxCWM6sym9vKQY4tExH1ePTAsTfj
t6AAEA80QyUYvlYiw1vxcAloXL0x/xSshquNQ8z/MPd/9vdCkWusDmfR165g//9hruu2KR0pR7O7
4C7cNPsRbBG6ygv/1ujZvmztMQCxl345zr+47Ljvc7ivsm+ydNZ7m7ja0XKMOfwb/9uU1CcQqIrX
fw39tAHwU4Kmo367Y4IdwkHEDqH1fNegwFLjFA6Ld292IyBvrw3klNhZjNxU5ekKbNK8/TK3/veF
ZVVTrNyDjTbbiEelnxgFf6mI76wQWU6ttKoHXcbrrJowuY72amncA9UST56PhUQJ5JVi9ilHboFb
HL0S7QdrnNaupQ91DH2myOIyXivDBqi1aYy0sMEsAuG2qs1sVXMTJOaFOp0dlV8eWUB7ePLdAozd
YJcY3XylWGMhqbyXgnq8Gp07w/Aw41hxix1xF71ZvrKOKjcwJfMyQTu2rsCwS44mIQXYUsTwX57e
KT/dx/mK4HhdSIVLgeI9GSz48JMQLBPg1EsMic7qbHEu1Y9ylbOMz1yosT7D0GR3bv//aHJnyDJm
dtCNUiTrHC9hPu9fz9S5fi3XnL6tkLIAtmtOUmMcw8NKOwimYu0brfEROnKGCBmMzOqIsE7ccYGK
ri4bCVIaM12QSnjzUi1WrSkj/drjh0Xw2SlJQXHRsCl6KGJWXmu4ywxLuf/VAqZEXzT/eM7C3lhO
q8Qw7qB/j9NyKVimF7EqONBMyW9TfDhW+fOiRkqfs8MluM8nxfQl9B9jSeJorssGQbSoJB/E14qJ
zQmr29q4gaPmln9u9JD9zbewRCPZVjQpacFZTDvgXJ7v7eXGGzp8HqH1ykMjF7KMXT3uwAPjC1sq
68krFDdUS3rHCSxH3bHTQAC1WA5H1QX7kWzWQZzvxhCJz5CCrzit0GMEhXrhSISHLCdX1FDwEQ1y
Ldp7CFWj9jKSMJGQht+G46keMBnWkH+1Mk4ZdmQeg74ojxv4BAauJxVPSzD7qvNDUrvobcNfjI1Y
mBvvtJ8j/U7BdaZWftPEuoMLIsvHdSraRZEkyWMAUWND18d7av/BFwzQwyK/uUlQ+EZC2wCs72NR
v4QVUvHPj+JlH1mNbt/pmw0MG9+ZjTOcHolA+YVfZWbWO97AKm5eazVWfQu8HnfJ9LEMJzaQnIv6
HrdMPVzgxt9kg3TfmwWgFPBbQf1dc5cX1+u9v234lV4U1UvFFms11GVwN2id4jzDZaua4nEMNjUY
iW4KYGoid9yeqp38lCPyHlBJGUx86hGC8PeKGpcipKhwQDdes8SXSiwpq7kY/Yh9g2re+wAf5Qpq
0g5DPX9dQjrR1TT0aJ1AilWd9vnbgP/ZoQ3Hyf5aOF9akaX6lYa+JC6G7PsrjRuAHf+FCrUBo7cL
ZuH77pfCY/MfcSgBrw4ZP4ZCYfxqJL55H9bPBKe+En4liJtedpondLn/YyWuu7YXtj2Bhp6MyRl0
ahvJV23QyovmwevfjcXXT0Q0VUh7y1649rVvSpjLYMg6Vu6AvPSbYFpCIK97KijjRYrSe3NGOB9C
MB5Ty6/xm1Uv8NcxHCxla4zNhWvRSVdcv24qYtcW7A4zZqlStOi2t5IOJmqNfjHEwC2FsXZHLJRh
yOl5eX/uKgZNU/MeHCueZFbFjG6oX5lzK+mhRU2MhCoO7zK4a4akhxRpMQbQ5POvYew3VRiltTtt
UhjanJ7h6xrbukcp/G/AGSoFq1fLIv4r4RrIMGMVsWA3RU4YPKXDZ5ali3iO3SNsj+8bAvp1RmHP
lSagKVspinwODsUZhPRO+rDkrGbgHX80o0W2tP9sI+Dhu40FaVtzAF7qBzmurylHHUIIre9U0kai
eC30Fex3b03wenF8nvxlGjRKQO+LLfbzZl1fphZ3mLRr1vvVdWFpeWOIlI2pxQvKpDM6+LKQesLT
Qp7EYDopbYmdXvm7Uj2THdx07oq8ZdzXPEU8ZJw6lqlmGHHIGkOVPm8m/tg/by8j2mqtX3X4ZT9R
zSwIAJyALzC5ABD8nyscsiVO6yy5rnhWcX8XaiBGjAi7kgmPaGY34P5hu5ST/bPrWXRdMlGxUCnI
Ymece1MuzUwmmhK/QbgmwP+ndlfTAsGnMJbWRZtwjUrWxgbp9QFgshiKB9HrpJVXHDs0mKt5Z4PJ
B9LOwObL3KACDCtd29IVEfUkb3d8v1/C3C/Fe3b7VdxKu4QActUvpN9lk9exgiBINBOAUeSv+tvJ
Yl1aEFmdmV/RW9p/1fs6Wyu02jd2ETyC97CRYtbdZ1typ62hcJXqWMZHE41wR9e2ZZyeaPgqiyzc
7p3s14d6zL91qEkZXnDtlykf3ZEbRRfBftY5im6kkBZpJYMg6Q+juRzH+iV6kFc8DvmINGLQPCtc
YFW3cKyoY+X15COi1b4RPqc1WXEBpGuhJeJES/XYE9sgDNzRY/UQsBi30UNU7Bv/X22Mw05HEK45
lghz3TbCEimkfQfUmFUsZEX3P19zv14dCFF0eNO3RVgDes0v6X9cv3vuvQjTESWT21KPtNH31c77
JpZglXY2qajXf4eIKrDE6ptCBd1Ik2ePCrlDzaY38/YpHk41yOBRICnWJ7RMG65COAaE6q1VGU9z
1lQPOvyLQXt7D90mwprVuZDyvNLUC6/UfZctY5NdogUT/zZJFVW8+5vyTLb6di1igFIBFjJKkRp5
KefXafaFFy3ApG09cmZ1ZBr4khKGpPIe2II7cEHSswRtzwPeAL3Q6PTXBbNuU3gaJEPBVMrZkRcp
PotFXz5KcZNZOzgBVj3rT/jBl1HaSuvDbV6LXrHfdl5w/itldzVngVfKUMPJTfbeCxKBVlp69i29
CEC47VTari6W6/LPBJbS2fDWcXInfvoCI+k9eIf9K4bzhOwpUKJecf+AXDAXKHxjOqw9zK1zqYPy
vuTp0MFpdXSUj1nc10QjF7wFYYzelTvIeQwTjNOqA8Y9lxFLJK3mtOox3Tr69W33hVMNukLUl09Y
EUiTVf5nI15Jk2pxUDa95LfvwH4WTIn1DJLNsIOuv4pSPbcY2Dg8dnWQfW8SOhFxKLGc7n6w4w5H
HLLvz39htOmBOC1IKLIEpow5IaGQou/rFEyHz9TJXQSKUhSX4ifR5B+QE7wyPiYUa6XX9uDlZp9E
O+KTOq5N7DHWgvAsZc7+P9hdO9WgfJUdL3rcBtx9+ZcAEhOsXeWxAXa7OG5rd/tQDCjSGy64ny6q
v+zNxbEnUQo5E3Qz8ZAImKQJd7Ol7+BPyyPtKHJvFzLmuQgFI0lvfyrMZ67/E+BTVNBZtlIA6w8H
DiKkXyV7N/pWYYvshI0+HK16i7Q0rPZ1nswXqdiTiK4D7ElKu1X8MYluQtUs6qdBQCpEkgMNs3eU
DoeZQD3ZAbBnueqlJ5CU0oHDoxPIONUYXU7SOKumLk9z8m2jx3nnhePQqX6t1hIhSbk7avLnQhAu
iewxGkWiuFgTwwAT7sg8KhDAv1olD9b7Nk+hJqRGBtEwvaUGg9AOZy75of5w2VNM0ICNxLrqyYjs
Uuag63/6AHTL7QEig5Oyw1BtOcJwPrY0WVUx4JFas6ihTzGtAxrFQaxL28RUcIjk7GuLm5rsLsrK
vYReU2NSte/IVsCA5VV0Q5/75a5QhkEB+vvn78j3ggJDiQVi7Wg82w6zw8MNrKlplI9OCnLtuPUz
H3SvFH/CCOtLiHksKNNws0ASCxl+i+C3fPQufSNTynpSh+8zDwFHSe/hyhbOgdE01gPaTCFaECOC
8TovEWHmd4Z4gLESO47Y/8C2LR9Nr3CZ9VDkgxWy9IuEmLJIylQY+QZKh0kv2e+5BbmA919Gs/1R
8IsG6tmjxHWRJomispqB+ihc8RCoXvZ5OcQrhEuQQL1PoRkwHzhR7deIVCI+mlnhjwIQyg4AFb6O
zANpMQIz2L2mqgIv7eaZcUpaaIwSNr3kXwjiGedmthnV/8RP04jxGUslwMctXIF3ZZfBEJude8tP
JAsXWc7W98lijA5BPDHr+w5g/nApUhozi8xSHLPAe7Psuyiw
`protect end_protected
| bsd-2-clause |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_status_flags_ss.vhd | 19 | 18129 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVTcVKz+qqR6KelbIxn6hKss0fyLwIejVgwej+TN1ST/vU6syUW6hxZyGugx/VRu65UT+0QU+88C
5SDN434/fA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
W0uuDuJZlgdtFvYMz+doOP0vwnGc2SXfLiGH2a5FulZQF1GjNx3fjKnarWbbCm92Rksm2FFSGof4
SgtGKAeCq4Yz/Vqm5xuP6QHmdBwou49vkKDs52HUud9c3EaEYtdNlkb4+DCcueqZu76yWN8rf2DJ
ekmu+LGiL1dmyzv30tE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Da9hmR0COgf/nsNRjZU5mrjIzRjN0/ufJQ7crbPh82WrNgInUm192216ks1D/Quh1gQ5TieAOChY
26CHNdLfPPmjLAo5/cOIRsIuy2JD7JAEIDFhFO2BcC4GrUAhSArSC4/9FyqXrVJUKuDybwv0tWSf
qpHjmJw18CiVw84ne90mESBOJ0fW1ujayfbI70yaGaFjJM/DPm4Lq+TC+TFlaimxpTFNrAUzQNVF
VSkf44Zb11D7if2jaL6ua4hPGgYpPcisaJtcEYpURXS8Lw+NjmMExnMpUW39NqnMiTEPom3YBwag
JMKm6/EZOnBvVc8SljH7y69fXiGUXgw6Z6POkg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
1/llP5a+sEX6Ky1I5ak8Fr3e35uMro1bXNqkrntPBRVTqUhQPFl7wfr/6Abnu74l73YggylsZJi1
1Erm6sC9oDhL9IE4pENErrDQRZHuFnl4+DlguLd11swTlNfBwauGoCBXbTtZ8+O70UI/sRzXqbZc
NDH1RywyQLhMRmSOjCU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OI4vyCtRzSCtjYNsCqL7rYkcvPw30aumOHoxNPQx0NU0Kc5/zvGo5pjE7sDqPsv0b00mAjKXUE8e
pVllo+uquegdt9Smrq3DaiQC/9hKGiZzOG1rJH9JbLcfPMXDGpwm1inP51BNgkQwocfUEAVndeWo
GE1Y28I9gt/5q5Fs/OUAX9cAh1VoS1OcnYX2wbgJSlzuLqnGWRIxOHl4+NkNkBq5Q3Xm589bPnnz
m+d2tBEPyqaCTvb13xXW7hqIf0ahuv0AQTuiClY+KmF0GjLdJTWJjDWPuRd9WYhybCp/lrgDnhAK
cnRXJnAOwP1Vgr7EPuoyVc3UkNsZTxEr3wrouw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11680)
`protect data_block
tdwK5ZdqC1lTmlGUnRR7Yt2xC9sSxvluJ8GKoF4/PBy8cuepaO0uf0LYKTkNKeeHpd3Wema6aqcj
srLXXbWWz4UGB4hdvxBJtYqwadIfgGECjDVXp6uQrfP31vtCOA9+FmtMLs4FfxWATHXFb0PTQw3G
isIc6KFtVvVydNQmy1ZLPS6jP6h/lwbX8n/pnSL2WZXvrD1jm2jXxu1cc7g9OeoazdHUZzZvFix6
FgwGMXR3s27tEh4f9m5V/ihoSjMFOz87/tU/DB+DnLn7awHkl/wkbteyhhrGIUjKmzrL5F65y7N1
pUUhXTAj3RgbYQVgjkkS98xFL2X8ivYVa26+AF8gdleuWtFIrRpG06eNFIhnSLPq9gGIspbM+Ihw
+/YB5GhQ/v9g9jT6Se5RLKCmFbky/wpFSjcJLcsaM2PCKL11Y5V3YFUJ6xRDmvlC9enre5fbsqYr
oVKyuImicTyq766kky/w1DFftyYF+uDdELG/BJXjAVf5Dbqkuj+h9X2mDZCvDHV5eEOZOBUHv1HM
w1c3bMciXl6IirH9ceKXAyLYRMGE8y08oF+dc3esWGKi6HhUfyWgpLcJnlHwYq4Fb+giAnpcCxJ5
NZ8i4ehC4UWAkjVwL8HEAM3nIoVkqkkb79Dr+wwQBwujGmKHgN/mXEPQ7jkubQycywuiD6Y3xl5O
hsp0166L7MapBJIdm0w4Up1QZhpSk4tE1lfL13LNE+N2i529RDBoTe0Vit/LBVoyV2tlqhw31Ftb
tfUyjtFAvv8f0a5PcqK/r7TDHRo+aMD31KHzmO9pF/Nd9rA9wfacjLHDd2zBvByrCYa8rpHlEogh
TqP0bTw0hOmSogQYpzI0Ox0Gh+koPbCM+Fbmr8gLyYJDfJ4lpSryewcZChK61FlkGTR0jkyAgCDW
S6A0OzHQ3wMh2yg2fg0if+CX6+dD3C7PreGY4GCn6i+6DzsNTIqKKwZ8ddQnOevzjYMS3JVkF4ZU
3UbUrXI8xS4Vtvm6/RVEdqf7VlskrtbintlAQF0/xfYcL+ADJYcaijwDMo9LQwVF4T9HPNvX6s4p
GRr2VnS7WN4QXsCIc5y8zkTN+hROBRujh1e0YqNF/LULtt9SvYEbBQo0m1ujOQZYz3R0pZ4Jm1k9
qb5gVFPCQF2HUByXHwB4mV8MbvcJgtal+jQe+9X8pJf6+WV/grrQ7Dxmpl+5uiY6G9wP1ixVoT/L
sYaHOCQ2iKleCpslejQNJ6bat5jnYhNGSUAttQC1mYqXVxdcpxpTqNYsGnrEWUHwp4FJ4aqV79BU
NkfURkorAehgVCWZOc+z0DbGaNTvnuc0SqWJUgoinr+JONjWy1Eoj1uocEfTE/xGj+1r7WxQ3S9n
r4z2TeXtY3+VbZNC1kdXBHWUx8y9O80uGAHGLzPYK/hO18WjHr0tDjR+JxuBNXIdU2LCp2JtiX47
+6Z95G9t/6N7etlQRiG/eUyv5iEKWL8PU2T1Vo8Ny2sqfbwJV6y5zed3iRA+CJQYI1cv3mzSomfL
QoV0R/8i/678Uj31aTt8tzoAkd7yXbKXrdb4Fc/9k+GSFctBLy4OhHUi92zadkZ27B2ZaHudPUSy
LqRLzpaEf6Ej80Ply8DFJInCAVJo/3GxLqHfRcXA3oTyzeeAJEf4GplXBDcJpDYi04EdJt525a9k
3z/hew+ozl4W/+N84qIUV3JWDphWSPrzAJli/k9N2BvayDt3M873cpxowZDtdUYThQ+b/cotSjRv
HUzVRlrHgRQhEtpWyZvoN+Nao7LR0jbisuEMig5vnVvJ8UDkXKXHCfDHSWpLDqOtHHQ/iDvzdfUi
R+ftpt0VoWiU4lqgUpBEHEto9EdtXy7Vv4EvB9I3AuC4Fc2XoeH4ZNsWETe2Irh8bH668e7m5mmP
gUjc3OxnICCMeCyJQwRbIAxfZ6HHBlawdSxYSu9sTWnKiC1JOebMMQPnwdYx8KL7yUT3K0lvLGkZ
bjuqSRPMLIrOHb4/zPbZIGTElJSkvpras7Sgdh1Ie+Qp8MrGZIpGfccJ3G2tUh4OwdPcjj5xByjk
1l32Yt/L1/H5D398cXhQwytU8tvUvr1UN6AtAeTr6YWgAkv33BhicVQKtpy5eLuUoiM+AWofiIJV
Y7ydKSU3x+lTKPM3DXsOGlPx3uet+cCCXQGf6Ncf6WCyCkOtBi3XAbmUYyrnKih85SeWGK4WeV97
m0xXU52EHE/a6wtXNoZBWLCeSpgi5eaAtejXs8ZMeA9VvHFxc1VTC0HBoN7fuyTyEl2O8vn+vmrO
ixjaZAMgf6SjLBBp13sGV82vInPGC/xOLSNE5HaM9CvLDTKDo6MeOshm4FuMUZp/2b/B92n/Tu0O
KGG6iMJmd+khGegWrxfBy6bj9qITebx3c8pB8pi+Ld09AYi0DxcZ7OkiVlPFLZTlOHL5IejAwE6L
s0+T+QBJfSE69uKQH42canp3wQzbV0w9/RxRw/LG5o9xV8G5NBp/qU280uxfYyOeUB5jwrH06wiP
6ZWXD16uH6tvqrAQOnf8BETBG3VvY5KSnNQbPc82ZkuP7TciW1YS+iVi7NnprIsN1Y7UoI49nClN
BuObMUSDlCkP13roJ/kUYtsncaLYsI5O7PDku4/Tcm7j1ruauBlN1Y6ihcAAfkpE/AbPJsPfOZO1
JEn+wU/aIQhApPhMOPOvCnwwkQd9e5+7AA/tEHeBeCRFl1N8SLHzyOOfrmgYbH7lmN+CD0gO2m4U
EIwdNqCNLa082b5GcPRaSxMyNBbJO+dzWjLzH7nMYL7fxjzI2JuULbcyW1zhDSKNmSi3+1fJxO2S
0C6/saTsbW3oMLxIR5WSd4vJoHrMla6DAG4mfxeI/pnkKySFvtjb/ZoiOJTo80pd2Hh87lJyqBDc
gr/fn8ebTBf8snksxjD/r7KfaHc6Noe39nEnqS2jEt5s8dVYADEQi3ZJsBiSusyKLx8Ca5xEo8Fs
VIGdKSndheyin8lzRyI02gn+nFxdFb4vYDUwD8e/CzG/j+AycPxuv0MgnQKZyeHtAD9fJeLal/XN
1o82aEmBu+DFrFFFW5I9FHHcTH5gQMV8+5uLE3wtNBMkAc0f5u4K8lfN+a6EwNCiJJNzpHZNr04f
5siOgdC93QlJUgruIvtrukvy1tEXmFVHFmnIiW0067zp7cDkJ+kV8n1VY14bim+uRhhgd8QZw1hp
PTfBconCg+yYaye4/NSIFk0KBnGfM5Imosz7HTJ1Ae1DHXktFmMJoN7nUV0YIqfU+cNs9JuxgxkZ
8GekY9USUd0Fn+xEusdUPCDznmp2oETw0/6eZZXhhpAnbO7CP19WWSlNmB4DKVEN5mSvePk62+pD
YMwZlnre8JlOHlyptsAtnskjaZZp53rjzhn1AofmbGZiBOrkzPcVTOtcvVm9oODXZrMpUehcdR9l
Vg/COg1z5AJWw+2UKLU91GarmI3uCMBt04ivnpjK8MhQfWe8X1GSUfxh5X7PMyvcOpRtVILp3Tpr
8fjAjwi8YXlB10XHiF4SzWjg4TG2FA+bcqR22Exag1NngU2fEdrwNPFxQ4+4h/ZqtDi4oHoBiMce
74VuASYlkc6uc+K9lTL+HLhQBef/XMnVpkJxOFo4wotvs+lDztPO6mnRki3Au64+bO6OdWpNeZFK
uc6xHJuJ/c9ykXuGXPHdMrZiDk/i7qrj79PjT9EcYGafcsj74MZ+3TPD6GRAi0E7Gqsl60TpEWwe
Z0zLz7eBtOTosH+eQ9K6ClLpzlw1gAt1dz4Yy7AjJfKl1rOhAkiLlcm5DB0G75uDnRG/ppz78m+q
zw01AAqC2abL7ukVT7MKFp8qEQ7CLWE5E3Nhh9HPeH3HuM+Y05JWFWjX/ok6MiV9DH/HuI04U167
XbvZk2wNxC7D7KHsN3LfNotdKykG03cRNqkScyqQkXyd32UE58LxXLzH5LHGedfOSEZs5Z8KM/yh
XgZMZmYpw3iEXhmvPtkwLKyQCdovRiRkXqwJ2jEQg65M+Sfwvmp12kCobVltApn442laaz+4yTss
QFMPH7aB6zRpYWwh0YrdMrNlRLQAZ+cHmY85mZlHgp4BV9rPdZCimo6FeagNZ13uKjE4fbz7jieb
/oWGqv5imXMgD0plwlMWva01WxzWdfShex8wtAdVZtk9B47MS1Xh+zfLKTRo2RlZH7/pTDmjVKO2
3crzXes6nMR4ttwVYs2Y1hXWoD0o1PNoSr+YLN9a9wpJ0INFBaVHhY+GbU4fJXxDe3ydi2w9rMnz
5reFJdmWxJH6HBVJVcFOOgxmHh2xm2rbX8rx4obLfMxNzDUXJniKNUFAyIwizmw/0vMzBvdTPgas
bbu1keKSl6ndJF/x/p4yBNUo3SZeElYMU+Vcry98h+dbiX0DDItgxVEGrOPNecRXI4hgjzUpu78j
QVhGwBmysFD9beH27ubO98gvxNtgTGFEZtlfgOzZd6ZIYUoMeJWmg6x5Rs4YUzrEIah5lAnaY5+i
5txSY9PdnKARrmlmgvzXNqb7EqRokg3B+ZAakmNV9LQfjFTjKUB29DhGhQ6oBKR/BG7Hp5Hg5ue7
lBCAc9gAk1qneV0/PJfPhJaTBvGd4j5RDTxVZb7ABVzAB7a+GF9Dbm+c5U0HCg4uA2z69SKfhaJy
IP02mwiB25hfvtR0zfQtser5hHaD5ILBZ7betTurxvyUcZ65j8YDeuaK8oI4qK9uCU1Er794xD8c
htBXMGT/fQoMvaoTrjnoTmZuByMJPbEYD42XPCZZf5M84JpJ0GaSIq+N8n1bQY1VH8ypQ+dM3Gz1
0AQPaD3owA7yxz8za+WzFmLOBwG8y/01WZSqCcFGqXSJeqV1iepVdmcv5OiTLLPf7ObUV95TGyKk
mJDofdo/tZpKkS8vajnpcsww3NE4sCT2Fce2ioSOiSmee+9APRhlCEqv3B5kIXcxKk8ZvCj77OXN
yqJ2J3KigOUIs7T6uBoWWS0UaV+in8JlPGascUK0swMiz6HTr0u89sEuX4DI5TJ3S3CmQrmpbLTv
yeczJ+dnKzpn9JpM787xOqWHJ5DL1t8B/fnhLW7DSNB8xNBrufFISN3qjvSNFfBPUlCeliUuho5h
vmQq3ZI2I/nsNTkIQkq4285v2e31q2XDU/W9mzdXFLL92IvLrMx44y7/MVWGPfs8SuZ043BEx+7z
JuofAF+h2dYqReLTQySbcK6cNNnle4bCv6n9EI1bSnDqDZ6p9WMYbmF78t9YssQbDp1p523iH7LD
XXs1dV5FDGDSKsPQe9iZ3Rk6mRIUkmAqd0fmqbHGTsD5NNWV8AIUOcMN4fkPmdL/e+vwJPl67gzi
kgqCRLy9JPgQL/ZLC4PI3Fm5/QhpJ9SB5oyp2K2J+iOxuWuSoUEGdnUi+ot0qEhvrZStoygO1pbc
CpgPxvJdHoTNTF2Hy8QLhqTEvEOClU1eVUpgRDu6virzeEhnujIxeCT31Le1FkEX4oHJTxMCUd6Q
ItqZe2MMRS0Pu9imfDqfDHD7wIXukPIXG5myKGg96twbGi5SfbVD+3vaHAhLGaLLSQCSASSNQpmh
68fwBVCI2IpA5nt7/v4iWcdDCBRyW1koCCXRzgGm1SNuDClZiIGRknhJvYPFbcv2n9K4GXpw9fJm
JXj4YwXv7IBxckPIn4ys3M4Mu/cZCMP/pR4uTLiaEk1ICifLYv+KWUyqe2UUd6W+EzWgzs+1zQgI
N0xN6JEaMbxuKQ6sJQnS6ABIGSBIywd3XKwilalcK7iLb5ZdMeagPSh5ndV1GejolHZwMDXFz2sF
lIUpKB0mCh1r9gMToEzmsl+MVD3vIeMF4LG6799vpW8euBMl26Xmi4w4V4KsWGWXXTfLNy5kmlM1
w9bPQiH774bK/qLbxHNBJXxJPKK2pJt6jKsWNh2I8FzYnzoCrS70FqVx96Z3B1mPp4JvSkhvov5j
LpgCegNvsqdESlKcKsU/1xL3evCXjTjg12XH0zljhMOyGpAkp+PvEOIknslOE8q7hUpF8FsN5gfy
ghQ539vTsy8TJVUdv30xv8ndHQUHhsqcozD2MpdffZ5PhlP8Z2AE/2vrRBZWwXMFD+7xNLQ1fMEq
63aXQbTsoG7EtSPzwWE0CfdLy/oJsh+I/6VQpcdOJDLcg3dP3G5BXIS/198czt7OR9G57o4araOw
E8ilAQNi2t8KGiyyPQxbTGT60bW+a6pdJ8IEqJ8Nxt435Mil6nXPvJ2P8WaZdXVcrVzWVcJjMzyI
gEcQKw4s8VSIO60UYNL9FLAZ4rEDcRgrmjpemAUZEo/EqpdGoj4WatITG5oOXiTdlYHO4gF9nIaL
OgIOG+W/eevmoTCfXpd674+Cc+E1rL+whWlCGiwgX4m0SCLtyQe5ZxLjvbLNN7komRpvJEA16HjE
XpAA87vDt3Qn6BmNQH9R9nk+HYNfz5oIiOgIcwnfcTGQkUBR7xY00CmnGEoaie8uOQ2v1D7XxNOP
iSduSmdD1D84/I72gyJ569IqJ/ngJrkWT9kv3L0LiDgVxlDOwd6vMM/sbjdpg8RL6hBsYndjKc5N
fKXogtYiNcJvqEZTOQnfsoku8cj0jU4Z+g10qx4jP5dnUDzfDwx1WC6LG2cL5CHqJUtS0hyHN2nR
Do4RP1nytrMUIScEUx8ymIkf8Dc0QUU85ioRwQ5oOmUM+BzhZEk+Fa04DXHmk4FzAMYJaNz0uVWr
izWxyFBFn3LOleEoj2ffNnoWWSNLZYzcf1pnVO4RSPujMTCefH8iK/fboTHDVJiLd8qkup7q1onM
DfOf5VeVopMC+WDV/7iHCtarrq3Q7bjRJyWEZWM2/Ob+tHju8S0khQplCAsOZtnUQukRvhO2p8dD
5LhW24nniWXjotqlnb4wjczRQhEelWY1+D7vXN1q5lsygIrmxRlmRNEdoPp4d8+oi0PpkpkqICOD
hNzPAEiabJRXrO1w6Y3fU4y3/AvImo8U7jziFSfYF8vBFEQdDg1S7kWl/QjP5T3QbvS0rVV5GhBn
Law4487uZ5DaP4IYSt5EVXCpSVk/ncnDGtu7vLqMJ3pyihI79q/JqBeUhMHmbOYhsoG6I3ycBGGR
o4WQhi+WknLA6UPWJFeeE0Oj+7Gi/eXFO3DeJXLUdeSelgGGff4JOX5A6GdoNyVWVL7J/+nOnlfx
yLv0HtDa8kodWTVoW/gCXKnoqRcDVVPE6KsdEbcQztH9Qgn1Gr0tnaO6QFm9HsOzxXKHjHGEFtRA
hIe8dmHyD5CW87t57sUWzkopazJPPmJViTpb6lbsR8HPpa/I6SuHq5eGHxImRkVWNZQWrWSDYRBL
rEqoABfZpuIctlEXHhs5KUqw3GP9A8kTLi9iPuCmtoDMy/OT5rRMac+6csBjwj5E7s805jITswjn
qB+HIpk0qUNHS9SozZPrW/DntkUr198/JMEEjsgqlk6yq/kzjT3BjIRefT4lYqQnrFyo2n3dHn7g
01WbF1D+td80CdjJbd4e5e7BjA1DQ3PwcOdmJ7XndmnB/LEoJUrQYF43uAt0hRSnwUE0DQZjHPlb
jw0SiD2S949P3SBdnCVIbte8U7RzH04g5R75wc47LRR2sILzn1iQOttGVfVxZbB1C+kGhNrq65I8
T4ZE+k2D94jMA8viBY1QU2geEcsEThPvqZ2zXEf89qZneBqT5dzNSifWKFqLDhxqrU0wRUq8HZ1A
7mnweEAbSDX6z2uYi54+fsrvPB9T7/DODkzTVuXNp+KPy+6RTOlgcsLT79lliaaDoaEbaqZ8+Yu2
tdZN/ioGt3bvloUvp+yNgxycdXWdFLuy74erxnPUQbHUU2W13aZnF1rQnGU2y6MPNx7kbft4PUc1
Yk8byYAeKKrpkm2BnttHk55HAIhFf2f55FxV6XWJ5UQQA+PBGg7TYXgJbB2IkjnRhzDVad6hZiw1
l0x32SnUdsIlEEUJ5Npu5GVyvZeaj1DXIY80q0AnV1R7mWFO21ilrLUC4ow1YoO3XOpZI9+89yzm
KgJsbUXZeaIg6jkxA6/9+fFTiHZyy311Csfd+gzC+X8VjcFoEQipgq42yf7Kg0W9y4FV3JY0YRvw
4PllaNT2l1nEdtwTmeEjnBz9dTSeuTWi1+UBAUQQ+TBHho8eYgVaMXKJYHl9s1nbf9jCxLOojU6J
2Mkk4HjyVSU3scZohpKZs/RLGb/+DwoJcwbi53wQVPqI8BXSsKpUcc6vT6RLMNsYTLsqy1T3sJT3
rvob6YZy9uzK4T1dGIZrxFoO7TpLluMp8ZOiMPyhJzTD0vk4ZR/c0AIzs2L774dIitQKzEvf7yhN
bgdjrXnqwN/2H3vFXKevM6qn2Xha1T8buWUkuGJryLyGiJhZVk14EtZC6TGCGLZ4Kl64ZAR6+2EV
MS8hmAkc0ozs2lU4SffmAMqEvwu4M1glqDvWWNCTxopKe0RpzxhE+B47COrlWIu7Mn/lQfab4OSm
PmZcnOcW0DtUwXc1XOyX1BVXFOWkGw+MUr0CFJbRjkmOs0hV6f4Ty7R02gFG0VpTNyGDFJJqoSTn
AnlalsxtC7VKbtZc2AhiIfBDwmYRd9OWtg9zOttJ+beFJKLOWgQmzdYTGyl+dDR/2cBZN2+lKOft
ctThp0yFSpFyQczSzwkvjPLQxGwx4JQSEgi621f7ncvgXy7ygAkrFVvY26WdQ7mb/ugvoE21Wmdu
iL99Y4slqI1Bco2o3kaHVQN1aTwacbdLr3ZssDPLO5r5NuoYA1JbINAsylLYqXLxZpt405I7RfKR
yI7XpeNTdsj3gCSguGwnPd11PoL+q2yxMK1z3HfReTU4d0aMcZ8qz1VOIyQnW/JEzNzou/r8kJlX
aqCyQ7awvcxS5oXSfJzCumacqqOSER8ff1CPrDmakNuPQJABjFwPVpClgMv4IxITvxxChdDrKrGX
/m8SpKE1zxlZKVGkk9kdRlVnbwjCHmBgP82B9I+RhmQBzFM6FGM9CSmOZ12Uxt+u8ZsywnymX8oj
HOJ5zzRiqDsW51hKwTS4B2IZKV7BSEP3GqmqXaLA5NUaf7DDJ6a49K1Py5kcUa/+eR3vIY7Q2fWg
vR56WCSUnxK243BJ9B3P02YKZK8uzAjPx6NqM9XrV2O+mx+tcVnGBkgqBI19aobooKWJYT0KQdko
/5ZK1vmjrnHLb/FwWe+pduQDKJFZMVtXUWlVW3hDu0oe/pEbepPKnh/319Xp/3byg8yEqYcOf+0D
f7Qv1u0tHa5oG7nzk/wOfMHMgrmb/PZYIvsAYzN1QMJnW+jpkSu/Wlgbj8M+qdqrXQoprkT514F0
cp3howbognf53wG/OTcqWUJM5ZGnRWlrdJ8PIIsotUml0jyaWgVBexK3dXSWQ0xZH0y4FKjxtF9a
k3CX6D1mjL8eNWHst/V6ThKwHV3ebCTAxWgHS3YXu1w096gntDZRUra7pqc61DLGCNDdiolIirtf
t4QxAIah2dTt7k+AsRfuBx8nPRGuUQKIkT8YJyQ75wqtzO0VCQ4en7yV0zH+lcdjycLeIEtmwwzo
9SahCBqXNLBXXdZLXkPDl6GpRGkGXigmdGB4G3G14UsfexLOcB8XhwvZayMR7uYFpMhvNDCDf2Be
epYiwZLfiJZPvaxXVmnkFNMnKFTcB1vTQ/QOMccppu1TW1C5PQyADHvtrq+LGlsRWDU4S0X+pLul
HLAkrFdUCrJD+IbOZ3Ftk2ABLTAbZqNjmqeVjRqRdGBxkOyE9sO8rMy7+ql9CbA/Z0fUI2rQ0Msl
K2E6rz2R36JyLbiD3P/4TyOvAoiMSHEDRsKDa5I5OVL2jmEWl/o2GrKRAukJcGJIdeiIHpzXH57k
PM7TAMhFXDwFtAuHuqy9KnejIXlhds7ZDaspLo2uVA85vvm9fds1oNgX2hyNtL81a7HVYGcU4ykj
g9Y1BcTdJzn8cFAGi+xAL+pDk2mn+Odbk+0pq55wFW6eZSMs7eyLJEIy++Pxd+IJVVPbBYRKVkXj
whpLo4PLbAnNCSd+Y7EkfZRU4zCZ1Z3h9bAjmtdi3fDiJlx1IUYCDcTyGFvXnj0RjMZLKIiYNBZ7
3RFVWY4HWp0ykat9cPvfXQvTRItv4dVt41YdWLxcmYRtf8l0eCzXYXk5QTFigmBPOfBmQnxpgb9J
2IgcV1vcbRPiq8zLEq8ivBDCog6vZNeysPGrGmUgyxqH6nf0G8matPJDvIDkWGr1E8BhENlXXaJy
N47txnqYIoiND46mbDO5P5Rs99tttkkxpMbLQylX+YkFgbvwQ0j5G61gqJmuNss+v1uW0boZhH3P
ha5Qi7FoxReMkWPxbb+euxX9Qt022CvgIO0oFQ7GjRPhowfl18ZD0NbD9JDvMpZKALV8/xqVRv2M
+1kLAyQS9DwsH5mb6fCadCRYhLKWqhTfOTfbE9d1b4/wBojJIsAz1rSQM4dJxNA7PHPo+Fy9/kyl
AVhx54stPhbDdpCxstG/f7xpu9KHxxKWcP2xmgOF/Zz+//lecrJDELZCc74l0iJtokQVdHVcdxRN
1WG4TsO8/b4jJ6vWZC0xtwHklnOFiroEvA5Nr9GNPKuKIE/SdIwfLg175JZl2+Oi3lK+M9IIOCh7
M+ktv6ZigYbzxoMf6EmIiQc226n41SD68/SVbmeMMnHX5VpMPRQschJcxkT+VQUXxUVXVjP5DHwq
JqPPYiJQkJiENFDoggvo0etEOTxIWddTKL0lvIG+V7Ge8EspEmd7n0QlIn0Q8UU5hMeIRyS4fM6v
7BClmO4YOHVvtZgGvMIjuZEVzt7dhpQDfb2ni0NP7ixw5lC9K2tUaKJ8gvHnldgVredqD02YINbx
CaAQ91oyiKXUcHLDlOZv1FAThDmzgKep8TQLXWmkJx5VA52ut8gHrcMa/JkajlTEJlrR9lhb3+eq
BOfmI0cLIgjtx2/bgRC2SITw+G8jkBoIM6tQkiCcS5pDhQMPmYVd+KGoPRosyBW1tUWvacX2Oon/
U3ljzZjoo6ZLGMLAQQEMx9mUWKDwL8wb4hXz83zSXIrv3tV/ujAPQCarHuLhIKs41vvGsRlbCGW5
TSRw/wk45sA9HWtj53jmy2BZdYoKGQF18XIMaf1jFeg8n5hr7zMisxA4iauMI+f2GoS+oTvLenBX
kJXNuObAqx4DrXJvkioK/3bi/qFbI/EmY0sFHmPCvL1ReYF1GPMhWZV6ymAbpDEz8glyMEDmMBUf
f4HSFz6PxiqCACAa3VBN6uwBhY7KsglVuBKcaGd67a+/ZMP+u2TKtGH3Yb99V2CZ5fB7l4CnQwqi
YNffqC2MKi2p0GYXHNchqNPepC1ygbnIoKd0ZIjP6XmjkggzfM8nYuoVlBr7fb3Hs4yVzEgazzdQ
HL6SEepuoO+tu8S0LRSFYzd7MlFh0aFzrHv4KaQCcxKZREPNCUyzybPHq26qBwrg1BvVR9dTY/NE
WyT51jLifHp/uXHKyVwX32hu+7hQHGTDO9DLWeZTZ4H+0dgqM0EC11h9MsHVmK8pTPEa1RfLnz+l
BJOj1E6KiiQeoKeWH7UL9yN7oIcW+wYANWyyDE/pTCzqjiENdhco77ide/wzcRQBddp1+1GJkZLb
eF5sIGKU13f3wcf3MGGtnzDznxRK7mM80Bc54aZElBrBEHr0B7S+mhiuw5NpK+VHn4uwZ8eVdayy
EtQbV78BCQSpylskz78k7pKs1v8u0tamFs1R10ol2oiRSGJ/7QcNiVRVI6KhjW+KCW9MdH5/7GAp
QHEt2GZHVhvrTSS16stwFY61TupoXNq1dZwDA42MApQcTAEtpqIoIMHI2RVav/LcggDCr9bQd+03
sXOYNZy7OLxL6qUg38FeC/1lP4L+bOT9mZqWp4WGnBvWAfPjZHo2lkNyAHWUEreXvjvziGLDzAUg
rLkMQUzobPuBuKkrxZpewFVHlHc1BRCc/pCYA21JePJDzT4ydDfKeqC4slxq72i0yHMB7Sp9yYQa
fsq7ryDkkhpmmxL4r8nmXfCMg2pLxK5qBeaFy6PuwdYkQBO14aPlDMjB35ls+IELYm+G1t/wc9oh
/+vSIs9QQTCehFEVvIpgcDLzJ/AUNnMmEw2EB3AFb5tjV+jfSSB+rEi8QpnO4L55/sBnWlMIN5JK
KDrCOaE2FJGLromfJAvD9NvupSQ7h25HM4ACgeGqPhjVKldhJqeyGGX4ItI5A87lIVEWwICSP7H+
6g4dLXFYqO4PqFIBBnWnS/EohA21t0UECIWCQ8RyRdZHFb3Ec13xNAMUBYVcLl6q9cUElvzHUdPh
iFv36u293bkG01Nmy5bpnOR06WrLkd1uKK/N1hDxpDBxHVxdWW24KJYhwUSF25IRfHWzypeCIbh9
uKilKxNn7+WRDj1b7kM6nzKv+3Y5XGGDKDumPvx8jmNQd7Hy5Va73PBA5NtB/uJXVexF/3/LQW6X
ORFL6jTlcBr4F4Wlzggxq7b3tVcRbYit0P663UIUQelE/4UlT3zJ99KTxelkNTuJBZ6h2qx2zNvh
6G862eA0Uq1zxrH9D9gPQc0yUIHOMoF653AzYMG+WcMDBvr7wNbZadOpN9iRDq5qRmp4CtkVArEy
/Bhd145IDGnbBoWYXUbI+YG59LLH82nFLZrzC2FIFMvmfS7VMkbFj7PeWtvzcWhmmublOLgX3e9Y
6zKJS/Q+StidMbei9KZktLAqH0AeDpMpeHKK+lXuf/m8MF2t3cD0raK+J+sKbbC6qmQM6mls/AvT
xodVOFBHgQDa2y/nyqnwCZpd8fSwb7HjNMLoL3XZL6ZVFV98DymgJKnwVL/P88tw6lGACqiENTNh
EQkQgnWT4cXg4WDKwE5yAcZN0jbYgbUnsnCKEUxKfPWMJZFt65b3UhMpwOKWXNt3RmUNFZZWSIB3
WciWFswr4hKng4cb78vkkE9mt7omWKg+qzy2GtimvDcl6atqhmQbMKoY4DsHhwGmGacrEpYHgW3/
C+v+NitqbVx1ttuvtCiBOiQJuGSiM9W9B2zZIhWBRG2GLVblnhia/aYEQOk98yJ4eKKEnyoABhdX
Ldbjh9z1j4bEUUwPUn2pd4exsYOLEKqLXrTXKDb9kym42+QJGUyHhx4mFeLBOBuOvWk8yMb1AwFH
JFFYIOIR4mlMhWxqDG6gtxo3Bv/ZVNX9IJdL5N8N9i1bvgfD2GtgrpCgfiRUvasTNQyvrtYxXj/Q
m159Mh5WifPnsF1yR4WfBFKYIh4PiLZU5qFSXFUqUxAgam/KUbuC7/wdxmWRlpyv53WKyDY5yMIE
2zdSymez2BkUWFO0pdmBE3Bqh54wp1NEO9iKrGg86xVI3iNoba+XRnYv+Mmq96jG4MDrkwf9FV9r
pAwhFACApnDgF18Z5+tsoR5FOQNlxOFjIMC29EzuFN9Uwf5a3Plei8PRxnQuinBn/xVIZRTvFuo7
DEohRBRx5VSNpn9RqlkOFxyTcKBG18rpVAsIfHootUxAWM1nT9yEqzxawmpkyCmeSirJLXdopz2n
IVa6nKkcFhCU0gDZtJtFDPuX8ySXOPYgBheSwO3PGsQlOwV4aM4r17nUmqUrTlY8NlBtAS7D+nku
GQYB4adZDRrBX2+i7hiBJNMjt4/zIobAkOGaXCRaeR4wiQ2jYp7WhjMCqa15Ff+Mpkw5aPvIT3Ex
GBpM2k802SlOOBjG8ViU5NZgnR0XDedU5U0mJmf6U5XP4vQldHKtnYdY+YHUHc4JIvLZvNDayo1G
vvAHdfjssnr4UpnKHMErYpXqohhwxV0xhz/CIXPCZyz+kRUok0YkuQvTxA0sSuyQoJf51lN6t4jW
Hr3MZA+5X0WSWRZu+cyoUV9/vd5be+cwoFJSrgWo0zapmK54nEyUP7DD7B68XyAlWB3DrLAMLF2T
Zroxki8MsiBU+ecnYnwCiwD0ZaYKYrfIdVgZJP7yZViyoGTZfZ2VCgZFnuMiSPK7PUs+VPVxVPIy
B6GiV7n2JpjcmTjUsrJEJ7cZuNG01Lz1fuIRDQb+beRm6i487+bEIYKMsFj5cvM9o+zqxqv7G15x
CdvFrsnnVK4JFFnOaVvBN2koNyah6/yLVL9wFdsp1JvmIEEhsU5YLxqUNbcpFiNSELe5TuPdxsdW
klnyI6l2zLE8dUSgOJcUORdCTjJvgYAfoYRLvIZw6ZgPB7XTkEtJQ54fgXwkAIWfCu4B6ZwEm04n
UMdNu1ZcYvxmDLujC+uaKpX+SJWO3B5rc71+98aMevdwnLWG42cCPI+f6Qwprc2avfxifpbQefLe
Xm5R5gfzqMYnNL07FhtleqCSg7GBJTrC8t4QUgi6eRZzx1n9iX3srjoejcZ8O3LGpxEB4KOSOrGr
Okpu76b96KHfkZXhOFGmbvf5wpeIt7XSm/BfprZpdbvKkTDeBA1Jc4lE6QjruabZY6ZA25nX7JQF
8EwUOUmzhJtwak7htM7d35NfYBWpI63jKWkIddBX3xj3XNEfysqrHni0ELrE/azMdo6nksk6TTyH
vWiV0+2rCRUmqHbDEYJdYmMrj+gW0b+3x5QNtJN1IojQSKs0h5jVXOxxH/fKvGve2Q3IXM4HTeaC
evgZoxkSxrJ+vyaNGEIQjye2oQ+SWaPzbskY6m1+zXxykHihJn+Mrf0ri7yh49lAHcrB3jcU7Ga+
AFpyUs6rZhuUm3kpjtUIRELZXlDI6FKXgJ2tZ9Wr/DsoOjVx2AX/ehWlGo4KijNIQ0oy7P9savIP
UzozFg+58dy3BkELEqus+8eYfXz7A0OAxCic2hcrVlg6zPwosW9sQo+30emdtuaPGfqhUOjHE9nQ
NUlm3Q9gwgqP0rAm5bjzvzKvLwa0zvSU28RUKAjq9LInvpxeDed2r2QCpOf0kQH1gEEpC2/4oJhV
BzyvB1ZsBsd+mKu2K0s37FprDJfZIiwOAAzbVySM+rLeSoeQrsOiXw7zresRkcgWIS/uVzTSidRW
Q0Y3bLJ8s4Qmu9gVD2mLHm5JEfIMAJua2Fk5x7RwyO8NaTKtGyJC0GItTq6VDiGnP8mtNtmsoTSk
5GWe/+dgQ4Q2hYY+mn/hDTihSxXRo/0HJH9ueF591j3bW5GSLFeYhbaIptcx/p5GjjZC/49pY3kf
/XiA/tvpP35CeJXqSfvTipIT6+8G9dpBHP3Qi1763AD6N0/1XhaO8YMF6067AB9UcwFSAS/6UEXS
Amroc/v9/+yCrvDp3epMSCRl8rfZqAI9VTuaxd83mz6rzwwCBSRRJB2T0riBIENt1P7UX2CQpZ7m
yjexm6Y811AtzI/xMHkUkCfmrftT7pKCGrHR+qR5vMkRb4SRfjVafDK4R0DZnpQ03T+uX12IQYTR
DN0RaAVXQMuE1MS1rCeluu4N+Nei0W8bMPlQ6KumfagrXzfxRMgAvKgCDtOOh7pPgaFJvZwuyP0h
/0gjSPWqMYGwIRV9B6fqeEjWItRMK7BTgC1zVIq48Jhnm7EBjnvYB7oiJQUAvN9mULSGeZRpuYuc
ipTNwdPnp0qA8Sc+UDMUCMIKnNlzvBaXWoCnxLmp5k8LSgIugYwRMzrf8w2FNwpx7C6+wokHvhfu
WN/P2U8o56QhRl0UrqJj0Mo2F4haOU36qfFXN/OZo3D7iV6G0rwrEHiKRT72C1iWK8VEjg==
`protect end_protected
| bsd-2-clause |
szanni/aeshw | aes-core/counter.vhd | 1 | 1712 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:57:31 07/13/2014
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
port(
clk : in std_logic;
reset : in std_logic;
y : in std_logic_vector(1 downto 0);
d_out : out byte;
x : out std_logic -- boolean indicating if the tenth round is reached (d_out = 'A')
);
end counter;
architecture Behavioral of counter is
signal reg_D, reg_Q : byte;
begin
mux_3_1 : process(y, reg_Q)
begin
case y is
when "00" => reg_D <= (others => '0');
when "01" => reg_D <= reg_Q + 1;
when others => reg_D <= reg_Q;
end case;
end process mux_3_1;
reg : process (reset, clk, reg_D)
begin
if reset = '1' then
reg_Q <= (others => '0');
elsif rising_edge(clk) then
reg_Q <= reg_D;
end if;
end process reg;
comp : process (reg_Q)
begin
if reg_Q = x"0A" then
x <= '1';
else
x <= '0';
end if;
end process comp;
d_out <= reg_Q;
end Behavioral;
| bsd-2-clause |
armandas/Arcade | explosion_rom.vhd | 2 | 8092 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity explosion_rom is
port(
addr: in std_logic_vector(9 downto 0);
data: out std_logic_vector(2 downto 0)
);
end explosion_rom;
architecture content of explosion_rom is
type rgb_array is array(0 to 31) of std_logic_vector(2 downto 0);
type rom_type is array(0 to 31) of rgb_array;
signal rgb_row: rgb_array;
constant EXPLOSION: rom_type :=
(
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "100", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "110", "111", "110", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "111", "111", "000", "000", "100", "000", "000", "000", "100", "000", "111", "110", "110", "110", "000", "000", "100", "100", "000", "110", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "111", "110", "110", "110", "111", "000", "000", "100", "000", "110", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "111", "110", "110", "110", "110", "111", "100", "100", "111", "111", "110", "100", "110", "111", "111", "000", "000", "100", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "100", "000", "111", "110", "110", "100", "110", "110", "110", "110", "110", "110", "100", "110", "110", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "111", "110", "100", "100", "100", "110", "100", "100", "100", "100", "100", "100", "110", "110", "110", "110", "110", "110", "110", "111", "111", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "100", "000", "111", "111", "110", "100", "100", "110", "110", "000", "110", "100", "110", "100", "100", "100", "100", "110", "110", "111", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "110", "000", "100", "100", "110", "000", "000", "000", "000", "100", "100", "110", "110", "111", "111", "110", "110", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "100", "000", "111", "111", "000", "110", "110", "000", "100", "100", "100", "100", "100", "000", "000", "110", "111", "111", "000", "000", "000", "100", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "111", "111", "111", "111", "110", "110", "110", "100", "000", "110", "110", "100", "000", "100", "100", "100", "000", "000", "000", "000", "100", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "111", "111", "110", "110", "110", "100", "000", "100", "110", "100", "100", "000", "110", "110", "110", "100", "110", "100", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000"),
("000", "000", "000", "111", "111", "110", "110", "100", "100", "000", "110", "110", "100", "100", "100", "110", "100", "100", "110", "000", "110", "110", "100", "110", "110", "110", "100", "110", "111", "000", "000", "000"),
("000", "000", "000", "000", "111", "111", "111", "110", "110", "000", "100", "100", "100", "100", "110", "110", "000", "100", "100", "100", "100", "100", "100", "100", "100", "100", "100", "110", "111", "000", "000", "000"),
("000", "000", "000", "000", "000", "100", "111", "111", "111", "110", "110", "110", "100", "000", "000", "100", "100", "000", "110", "100", "110", "110", "000", "110", "110", "100", "100", "110", "111", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "100", "000", "111", "111", "110", "110", "100", "110", "110", "100", "100", "110", "100", "000", "111", "111", "111", "111", "110", "110", "110", "111", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "110", "100", "000", "000", "111", "110", "000", "100", "110", "110", "000", "110", "110", "100", "100", "110", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "110", "110", "100", "000", "110", "100", "100", "100", "110", "110", "100", "110", "110", "111", "111", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "110", "000", "000", "111", "110", "100", "100", "110", "110", "100", "100", "110", "100", "000", "100", "100", "000", "110", "111", "111", "100", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "111", "110", "100", "100", "110", "000", "000", "110", "110", "110", "110", "000", "000", "100", "100", "100", "110", "100", "111", "110", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "100", "000", "111", "000", "000", "110", "000", "100", "100", "100", "100", "100", "100", "111", "110", "000", "110", "110", "100", "110", "111", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "100", "111", "111", "110", "100", "100", "100", "100", "100", "000", "110", "100", "100", "111", "111", "111", "111", "110", "110", "100", "111", "111", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "111", "110", "100", "100", "110", "110", "110", "100", "100", "110", "100", "110", "111", "000", "000", "000", "111", "111", "111", "110", "111", "000", "000", "000", "000"),
("000", "000", "000", "000", "110", "100", "111", "110", "100", "110", "000", "100", "100", "100", "110", "110", "110", "100", "111", "000", "110", "000", "100", "000", "000", "111", "111", "111", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "111", "110", "100", "110", "110", "110", "110", "100", "000", "100", "100", "000", "111", "100", "100", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "100", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "110", "100", "100", "110", "111", "000", "100", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "111", "111", "111", "100", "000", "000", "000", "000", "111", "111", "110", "110", "110", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "110", "000", "100", "000", "000", "111", "111", "111", "111", "111", "000", "100", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000")
);
begin
rgb_row <= EXPLOSION(conv_integer(addr(9 downto 5)));
data <= rgb_row(conv_integer(addr(4 downto 0)));
end content;
| bsd-2-clause |
weblabdeusto/weblabdeusto | server/launch/sample/main_machine/main_instance/experiment_fpga/files/base.vhd | 4 | 1972 | -- @@@CLOCK:WEBLAB@@@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity base is
Port (
inicio : in std_logic;
clk : in std_logic;
led0 : inout std_logic;
led1 : inout std_logic;
led2 : inout std_logic;
led3 : inout std_logic;
led4 : inout std_logic;
led5 : inout std_logic;
led6 : inout std_logic;
led7 : inout std_logic;
ena0 : inout std_logic;
ena1 : inout std_logic;
ena2 : inout std_logic;
ena3 : inout std_logic;
seg0 : inout std_logic;
seg1 : inout std_logic;
seg2 : inout std_logic;
seg3 : inout std_logic;
seg4 : inout std_logic;
seg5 : inout std_logic;
seg6 : inout std_logic;
dot : inout std_logic;
but0 : in std_logic;
but1 : in std_logic;
but2 : in std_logic;
but3 : in std_logic;
swi0 : in std_logic;
swi1 : in std_logic;
swi2 : in std_logic;
swi3 : in std_logic;
swi4 : in std_logic;
swi5 : in std_logic;
swi6 : in std_logic;
swi7 : in std_logic;
swi8 : in std_logic;
swi9 : in std_logic;
vleds : out std_logic_vector (7 downto 0)
);
end base;
architecture behavioral of base is
begin
led0 <= swi6;
led1 <= swi5;
led2 <= swi4;
led3 <= swi3;
vleds(0) <= led7;
vleds(1) <= led6;
vleds(2) <= led5;
vleds(3) <= led4;
vleds(4) <= led3;
vleds(5) <= led2;
vleds(6) <= led1;
vleds(7) <= led0;
end behavioral
;
| bsd-2-clause |
rohit91/HDMI2USB | ipcore_dir/edidram_synth.vhd | 3 | 4441 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 --
-- --
-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port --
-- Block Memory and Single Port Block Memory LogiCOREs, but is not a --
-- direct drop-in replacement. It should be used in all new Xilinx --
-- designs. The core supports RAM and ROM functions over a wide range of --
-- widths and depths. Use this core to generate block memories with --
-- symmetric or asymmetric read and write port widths, as well as cores --
-- which can perform simultaneous write operations to separate --
-- locations, and simultaneous read operations from the same location. --
-- For more information on differences in interface and feature support --
-- between this core and the Dual Port Block Memory and Single Port --
-- Block Memory LogiCOREs, please consult the data sheet. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- CLK.ACLK
-- AXI4 Interconnect Clock Input
-- RST.ARESETN
-- AXI4 Interconnect Reset Input
-- AXI_SLAVE_S_AXI
-- AXI_SLAVE
-- AXILite_SLAVE_S_AXI
-- AXILite_SLAVE
-- BRAM_PORTA
-- BRAM_PORTA
-- BRAM_PORTB
-- BRAM_PORTB
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY edidram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END edidram;
ARCHITECTURE spartan6 OF edidram IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
| bsd-2-clause |
rohit91/HDMI2USB | ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/sp6_data_gen.vhd | 20 | 37259 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: sp6_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Spartan 6 family.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity sp6_data_gen is
generic (
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
user_burst_cnt : in std_logic_vector(6 downto 0); -- generated burst length for control the burst data
fifo_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity sp6_data_gen;
architecture trans of sp6_data_gen is
COMPONENT data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
--
signal prbs_data : std_logic_vector(31 downto 0);
signal adata : std_logic_vector(31 downto 0);
signal hdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata : std_logic_vector(DWIDTH - 1 downto 0);
signal w1data : std_logic_vector(DWIDTH - 1 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i : integer;
signal j : integer;
signal user_bl : std_logic_vector(BL_WIDTH - 1 downto 0);
signal BLANK : std_logic_vector(7 downto 0);
signal SHIFT_0 : std_logic_vector(7 downto 0);
signal SHIFT_1 : std_logic_vector(7 downto 0);
signal SHIFT_2 : std_logic_vector(7 downto 0);
signal SHIFT_3 : std_logic_vector(7 downto 0);
signal SHIFT_4 : std_logic_vector(7 downto 0);
signal SHIFT_5 : std_logic_vector(7 downto 0);
signal SHIFT_6 : std_logic_vector(7 downto 0);
signal SHIFT_7 : std_logic_vector(7 downto 0);
signal SHIFTB_0 : std_logic_vector(31 downto 0);
signal SHIFTB_1 : std_logic_vector(31 downto 0);
signal SHIFTB_2 : std_logic_vector(31 downto 0);
signal SHIFTB_3 : std_logic_vector(31 downto 0);
signal SHIFTB_4 : std_logic_vector(31 downto 0);
signal SHIFTB_5 : std_logic_vector(31 downto 0);
signal SHIFTB_6 : std_logic_vector(31 downto 0);
signal SHIFTB_7 : std_logic_vector(31 downto 0);
signal TSTB : std_logic_vector(3 downto 0);
--*********************************************************************************************
-- 4'b0000: data = 32'b0; //bram
-- 4'b0001: data = 32'b0; // fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
-- WALKING ONES:
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
signal tmpdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata_rising : std_logic;
signal shift_en : std_logic;
signal data_clk_en : std_logic;
SIGNAL ZEROS : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
begin
ZEROS <= (others => '0');
data_o <= data;
xhdl0 : if (DWIDTH = 32) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0001" =>
data <= fixed_data_i;
when "0010" =>
data <= adata;
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
data <= prbs_data;
WHEN OTHERS =>
data <= (others => '0');
END CASE;
END PROCESS;
end generate;
xhdl1 : if (DWIDTH = 64) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata)(31 downto 0);
data <= (adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data);
when others =>
data <= (others => '0');
end case;
end process;
end generate;
xhdl2 : if (DWIDTH = 128) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata & adata & adata)(31 downto 0);
data <= (adata & adata & adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data & prbs_data & prbs_data);
when others =>
data <= (others => '0');--"00000000000000000000000000000000";
end case;
end process;
end generate;
xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
process (data_mode_i)
begin
if (data_mode_i = "0101" or data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0110") then
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
else
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
end if;
end process;
end generate;
process (data_mode_i)
begin
if (data_mode_i = "0101") then
SHIFTB_0 <= "00000000000000100000000000000001";
SHIFTB_1 <= "00000000000010000000000000000100";
SHIFTB_2 <= "00000000001000000000000000010000";
SHIFTB_3 <= "00000000100000000000000001000000";
SHIFTB_4 <= "00000010000000000000000100000000";
SHIFTB_5 <= "00001000000000000000010000000000";
SHIFTB_6 <= "00100000000000000001000000000000";
SHIFTB_7 <= "10000000000000000100000000000000";
elsif (data_mode_i = "0100") then
SHIFTB_0 <= "00000000000000000000000000000001";
SHIFTB_1 <= "00000000000000000000000000000010";
SHIFTB_2 <= "00000000000000000000000000000100";
SHIFTB_3 <= "00000000000000000000000000001000";
SHIFTB_4 <= "00000000000000000000000000010000";
SHIFTB_5 <= "00000000000000000000000000100000";
SHIFTB_6 <= "00000000000000000000000001000000";
SHIFTB_7 <= "00000000000000000000000010000000";
else
SHIFTB_0 <= "11111111111111011111111111111110";
SHIFTB_1 <= "11111111111101111111111111111011";
SHIFTB_2 <= "11111111110111111111111111101111";
SHIFTB_3 <= "11111111011111111111111110111111";
SHIFTB_4 <= "11111101111111111111111011111111";
SHIFTB_5 <= "11110111111111111111101111111111";
SHIFTB_6 <= "11011111111111111110111111111111";
SHIFTB_7 <= "01111111111111111011111111111111";
end if;
end process;
xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
ndata_rising <= '1';
shift_en <= '0';
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 2) is
when "000" =>
w1data <= SHIFTB_0;
when "001" =>
w1data <= SHIFTB_1;
when "010" =>
w1data <= SHIFTB_2;
when "011" =>
w1data <= SHIFTB_3;
when "100" =>
w1data <= SHIFTB_4;
when "101" =>
w1data <= SHIFTB_5;
when "110" =>
w1data <= SHIFTB_6;
when "111" =>
w1data <= SHIFTB_7;
when others =>
w1data <= SHIFTB_0;
end case;
ndata_rising <= '0'; --(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
elsif (data_mode_i = "0100") then
w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
else
w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14)); --(DQ_PINS == 16
end if;
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
case addr_i(2) is
when '0' =>
w1data <= SHIFTB_0;
when '1' =>
w1data <= SHIFTB_1;
when others =>
w1data <= SHIFTB_0;
end case;
else
-- (cmd_startC)
-- Shifting
-- need neigbour pattern ********************
w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4)); --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
-- need neigbour pattern ********************
if (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001"; -- (NUM_DQ_PINS_4
end if;
end if;
end if;
end if;
end process;
-- <outdent> -- DWIDTH == 32
end generate;
xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 3) is
-- 7:0
when "00" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
when "01" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
when "10" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
when "11" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
else
-- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
case addr_i(3) is
when '0' =>
w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
when '1' =>
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
--15:8
when others =>
w1data <= (others => '0');--"00000000000000000000000000000000";
end case;
else
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
end if;
-- Shifting
elsif (data_mode_i = "0100") then
w1data(63 downto 56) <= "00000000";
w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
w1data(47 downto 40) <= "00000000";
w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
w1data(31 downto 24) <= "00000000";
w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
w1data(15 downto 8) <= "00000000";
w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
else
w1data <= w1data; --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
if (data_mode_i = "0100") then
w1data <= "0000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end if;
end process;
end generate;
xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4) is
-- 32
when '0' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
-- 32
when '1' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(127 downto 112) <= "0000000000000000";
w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
w1data(95 downto 80) <= "0000000000000000";
w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
else
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
else
w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0); -- (cmd_startC)
end if;
else
-- Shifting
--{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
w1data <= w1data; -- else
end if;
--(NUM_DQ_PINS == 8)
elsif (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end process;
end generate;
-- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
-- => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
-- elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111"; -- NUM_DQ_PINS == 4
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
process (w1data, hdata)
begin
for i in 0 to DWIDTH - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
-- HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
-- the position of the pin driving oppsite polarity
-- addr_i[6:2] = 5'h0f ; 32 bit data port
-- => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
-- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
-- => the 1st data pattern : 32'h12345678
-- => the 2nd data pattern : 32'h12345679
-- => the 3rd data pattern : 32'h1234567a
-- => the 4th data pattern : 32'h1234567b
--data_rdy_i
xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
--data_o logic
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
adata <= addr_i;
elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
if (DWIDTH = 128) then
adata <= adata + "00000000000000000000000000010000";
elsif (DWIDTH = 64) then
adata <= adata + "00000000000000000000000000001000"; -- DWIDTH == 32
else
adata <= adata + "00000000000000000000000000000100";
end if;
end if;
end if;
end process;
end generate;
-- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
--
xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
-- data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';
data_prbs_gen_inst : data_prbs_gen
generic map (
prbs_width => 32,
seed_width => 32
)
port map (
clk_i => clk_i,
clk_en => data_clk_en,
rst_i => rst_i,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => addr_i(31 downto 0),
prbs_o => prbs_data
);
end generate;
end architecture trans;
| bsd-2-clause |
rohit91/HDMI2USB | ipcore_dir/patternClk/simulation/patternClk_tb.vhd | 3 | 6141 | -- file: patternClk_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity patternClk_tb is
end patternClk_tb;
architecture test of patternClk_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component patternClk_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : patternClk_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| bsd-2-clause |
rohit91/HDMI2USB | ipcore_dir/ddr2ram/user_design/sim/data_prbs_gen.vhd | 20 | 4942 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: data_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is used LFSR to generate random data for memory
-- data write or memory data read comparison.The first data is
-- seeded by the input prbs_seed_i which is connected to memory address.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
-- TAPS : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END data_prbs_gen;
ARCHITECTURE trans OF data_prbs_gen IS
SIGNAL prbs : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
SIGNAL i : INTEGER;
BEGIN
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
lfsr_q(2) <= lfsr_q(1);
lfsr_q(1) <= lfsr_q(32);
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
BEGIN
prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
END PROCESS;
prbs_o <= prbs;
END trans;
| bsd-2-clause |
rohit91/HDMI2USB | ipcore_dir/ddr2ram/user_design/sim/cmd_gen.vhd | 20 | 39433 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
| bsd-2-clause |
tommylommykins/logipi-midi-player | hdl/sinewave/sine_rom.vhd | 1 | 3973 | -- Returns the sine of a value from 0 to 1 (scaled as - to sine_addr_max)
--
-- The lookup table actually stores the first quarter of each sine wave, so
-- this entity transforms the stored first quarter to be able to calculate the
-- sine of any quarter of the wave. The following graph shoes the relation
-- between inputs to the entity (x axis) and outputs from the module (y axis)
--
-- y=1.0
-- | -------------
-- | / \
-- | / \
-- | / \
-- |/ \
-- |--------------------------------------------
-- | \ /
-- | \ /
-- | \ /
-- | \-------------/
-- |<---a---->|<---b---->|<---c---->|<---d---->|
-- x=0 0.25 0.5 0.75 1
-- y=-1
--
-- In Section a, the output value is directly read from the LUT.
-- In Section b, the output value is directly read but the LUT is indexed by 0.25-x
-- In Section c, the LUT output is negates and the LUT is indexed by x-0.5
-- In Section d, the LUT output is negates and the LUT is indexed by 0.75-x
--
-- The implementation is gently pipelined.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.sine_lut_pkg.all;
use virtual_button_lib.utils.all;
entity sine_rom is
port(
ctrl : in ctrl_t;
read_address_d0 : in integer range 0 to sine_addr_max;
read_out_d1 : out signed(15 downto 0)
);
end;
architecture rtl of sine_rom is
signal sine_rom : sine_lut_arr := calc_sine_lut;
attribute ram_style : string;
attribute ram_style of sine_rom : signal is "block";
constant address_width : integer := integer(ceil(log2(real(sine_addr_max))));
signal read_address_d1 : integer range 0 to sine_addr_max;
signal read_address_int_d0 : integer range 0 to sine_lut_bram_depth - 1;
signal negative_read_out_int_d1 : signed(lut_width - 1 downto 0);
signal read_out_int_d1 : signed(lut_width - 1 downto 0);
type modes is (normal_inc, normal_dec, inv_inc, inv_dec);
--signal mode : modes;
function calc_mode(read_address : in integer range 0 to sine_addr_max) return modes is
begin
if read_address < sine_lut_bram_depth then
return normal_inc;
elsif read_address < 2 * sine_lut_bram_depth then
return normal_dec;
elsif read_address < 3 * sine_lut_bram_depth then
return inv_inc;
else
return inv_dec;
end if;
end;
begin
negative_read_out_int_d1 <= -read_out_int_d1;
delay_read_address : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_address_d1 <= read_address_d0;
end if;
end process;
ram_proc : process (read_address_d0) is
--variable mode : modes;
begin
--if rising_edge(ctrl.clk) then
if calc_mode(read_address_d0) = normal_inc then
read_address_int_d0 <= read_address_d0;
elsif calc_mode(read_address_d0) = normal_dec then
read_address_int_d0 <= (sine_lut_bram_depth * 2) - 1 - read_address_d0;
elsif calc_mode(read_address_d0) = inv_inc then
read_address_int_d0 <= read_address_d0 - (2 * sine_lut_bram_depth);
else
read_address_int_d0 <= (sine_lut_bram_depth * 4) - 1 - read_address_d0;
end if;
--end if;
end process;
ram_read_proc : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_out_int_d1 <= sine_rom(read_address_int_d0);
end if;
end process;
assign_outputs : process(read_address_d1, read_out_int_d1, negative_read_out_int_d1)
variable mode : modes;
begin
mode := calc_mode(read_address_d1);
if mode = normal_inc or mode = normal_dec then
read_out_d1 <= read_out_int_d1;
else
read_out_d1 <= negative_read_out_int_d1;
end if;
end process;
end;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/ttn_n_cntr/_primary.vhd | 1 | 288 | library verilog;
use verilog.vl_types.all;
entity ttn_n_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
modulus : in vl_logic_vector(31 downto 0)
);
end ttn_n_cntr;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/flexible_lvds_rx/_primary.vhd | 1 | 2016 | library verilog;
use verilog.vl_types.all;
entity flexible_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_extra_ddio_register: string := "YES";
use_extra_pll_clk: string := "NO";
buffer_implementation: string := "RAM";
registered_data_align_input: string := "OFF";
use_external_pll: string := "OFF";
registered_output: string := "ON";
add_latency : string := "YES";
REGISTER_WIDTH : vl_notype;
LATENCY : vl_notype;
NUM_OF_SYNC_STAGES: vl_notype
);
port(
rx_in : in vl_logic_vector;
rx_fastclk : in vl_logic;
rx_slowclk : in vl_logic;
rx_syncclk : in vl_logic;
pll_areset : in vl_logic;
rx_data_align : in vl_logic_vector;
rx_cda_reset : in vl_logic_vector;
rx_locked : in vl_logic;
rx_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of use_extra_ddio_register : constant is 1;
attribute mti_svvh_generic_type of use_extra_pll_clk : constant is 1;
attribute mti_svvh_generic_type of buffer_implementation : constant is 1;
attribute mti_svvh_generic_type of registered_data_align_input : constant is 1;
attribute mti_svvh_generic_type of use_external_pll : constant is 1;
attribute mti_svvh_generic_type of registered_output : constant is 1;
attribute mti_svvh_generic_type of add_latency : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
attribute mti_svvh_generic_type of LATENCY : constant is 3;
attribute mti_svvh_generic_type of NUM_OF_SYNC_STAGES : constant is 3;
end flexible_lvds_rx;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/mist1032sa_uart_transmitter_double_flipflop/_primary.vhd | 1 | 512 | library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_transmitter_double_flipflop is
generic(
N : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREQ_DATA : in vl_logic_vector;
oOUT_DATA : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of N : constant is 1;
end mist1032sa_uart_transmitter_double_flipflop;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/execute_port2/_primary.vhd | 1 | 2111 | library verilog;
use verilog.vl_types.all;
entity execute_port2 is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iFREE_EX : in vl_logic;
iPREVIOUS_EX_ALU2_VALID: in vl_logic;
iPREVIOUS_EX_ALU2_WRITEBACK: in vl_logic;
iPREVIOUS_EX_ALU2_COMMIT_TAG: in vl_logic_vector(5 downto 0);
iPREVIOUS_EX_ALU2_CMD: in vl_logic_vector(4 downto 0);
iPREVIOUS_EX_ALU2_AFE: in vl_logic_vector(3 downto 0);
iPREVIOUS_EX_ALU2_SYS_REG: in vl_logic;
iPREVIOUS_EX_ALU2_LOGIC: in vl_logic;
iPREVIOUS_EX_ALU2_SHIFT: in vl_logic;
iPREVIOUS_EX_ALU2_ADDER: in vl_logic;
iPREVIOUS_EX_ALU2_SOURCE0: in vl_logic_vector(31 downto 0);
iPREVIOUS_EX_ALU2_SOURCE1: in vl_logic_vector(31 downto 0);
iPREVIOUS_EX_ALU2_DESTINATION_SYSREG: in vl_logic;
iPREVIOUS_EX_ALU2_LOGIC_DEST: in vl_logic_vector(4 downto 0);
iPREVIOUS_EX_ALU2_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iPREVIOUS_EX_ALU2_FLAGS_WRITEBACK: in vl_logic;
iPREVIOUS_EX_ALU2_FLAGS_REGNAME: in vl_logic_vector(3 downto 0);
iPREVIOUS_EX_ALU2_PCR: in vl_logic_vector(31 downto 0);
oPREVIOUS_EX_ALU2_LOCK: out vl_logic;
oSCHE1_EX_ALU2_VALID: out vl_logic;
oSCHE1_EX_ALU2_COMMIT_TAG: out vl_logic_vector(5 downto 0);
oSCHE2_EX_ALU2_VALID: out vl_logic;
oSCHE2_EX_ALU2_COMMIT_TAG: out vl_logic_vector(5 downto 0);
oSCHE2_EX_ALU2_SYSREG: out vl_logic;
oSCHE2_EX_ALU2_LOGIC_DEST: out vl_logic_vector(4 downto 0);
oSCHE2_EX_ALU2_DESTINATION_REGNAME: out vl_logic_vector(5 downto 0);
oSCHE2_EX_ALU2_WRITEBACK: out vl_logic;
oSCHE2_EX_ALU2_DATA: out vl_logic_vector(31 downto 0);
oSCHE2_EX_ALU2_FLAG: out vl_logic_vector(4 downto 0);
oSCHE2_EX_ALU2_FLAGS_WRITEBACK: out vl_logic;
oSCHE2_EX_ALU2_FLAGS_REGNAME: out vl_logic_vector(3 downto 0)
);
end execute_port2;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/comparator_counter/_primary.vhd | 1 | 730 | library verilog;
use verilog.vl_types.all;
entity comparator_counter is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iMTIMER_WORKING : in vl_logic;
iMTIMER_COUNT : in vl_logic_vector(63 downto 0);
iCONF_WRITE : in vl_logic;
iCONF_ENA : in vl_logic;
iCONF_IRQENA : in vl_logic;
iCONF_64MODE : in vl_logic;
iCONF_PERIODIC : in vl_logic;
iCOUNT_WRITE : in vl_logic;
inCOUNT_DQM : in vl_logic_vector(1 downto 0);
iCOUNT_COUNTER : in vl_logic_vector(63 downto 0);
oIRQ : out vl_logic
);
end comparator_counter;
| bsd-2-clause |
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