File size: 67,866 Bytes
8b7c501 |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 |
#include <stdint.h>
#include <cpuinfo.h>
#include <cpuinfo/internal-api.h>
#include <cpuinfo/log.h>
#include <arm/api.h>
#include <arm/midr.h>
void cpuinfo_arm_decode_cache(
enum cpuinfo_uarch uarch,
uint32_t cluster_cores,
uint32_t midr,
const struct cpuinfo_arm_chipset chipset[restrict static 1],
uint32_t cluster_id,
uint32_t arch_version,
struct cpuinfo_cache l1i[restrict static 1],
struct cpuinfo_cache l1d[restrict static 1],
struct cpuinfo_cache l2[restrict static 1],
struct cpuinfo_cache l3[restrict static 1])
{
switch (uarch) {
#if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__)
case cpuinfo_uarch_xscale:
switch (midr_get_part(midr) >> 8) {
case 2:
/*
* PXA 210/25X/26X
*
* See "Computer Organization and Design, Revised Printing: The Hardware/Software Interface"
* by David A. Patterson, John L. Hennessy
*/
*l1i = (struct cpuinfo_cache) {
.size = 16 * 1024,
.associativity = 32,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 16 * 1024,
.associativity = 4,
.line_size = 64
};
break;
case 4:
/* PXA 27X */
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 32,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 32,
.line_size = 32
};
break;
case 6:
/*
* PXA 3XX
*
* See http://download.intel.com/design/intelxscale/31628302.pdf
*/
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 32
};
*l2 = (struct cpuinfo_cache) {
.size = 256 * 1024,
.associativity = 8,
.line_size = 32
};
break;
}
break;
case cpuinfo_uarch_arm11:
*l1i = (struct cpuinfo_cache) {
.size = 16 * 1024,
.associativity = 4,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 16 * 1024,
.associativity = 4,
.line_size = 32
};
break;
#endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) */
#if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
case cpuinfo_uarch_cortex_a5:
/*
* Cortex-A5 Technical Reference Manual:
* 7.1.1. Memory system
* The Cortex-A5 processor has separate instruction and data caches.
* The caches have the following features:
* - Data cache is 4-way set-associative.
* - Instruction cache is 2-way set-associative.
* - The cache line length is eight words.
* - You can configure the instruction and data caches independently during implementation
* to sizes of 4KB, 8KB, 16KB, 32KB, or 64KB.
* 1.1.3. System design components
* PrimeCell Level 2 Cache Controller (PL310)
* The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a
* recognized method of improving the performance of ARM-based systems when significant memory traffic
* is generated by the processor. The PrimeCell Level 2 Cache Controller reduces the number of external
* memory accesses and has been optimized for use with the Cortex-A5 processor.
* 8.1.7. Exclusive L2 cache
* The Cortex-A5 processor can be connected to an L2 cache that supports an exclusive cache mode.
* This mode must be activated both in the Cortex-A5 processor and in the L2 cache controller.
*
* +--------------------+-----------+-----------+----------+-----------+
* | Processor model | L1D cache | L1I cache | L2 cache | Reference |
* +--------------------+-----------+-----------+----------+-----------+
* | Qualcomm MSM7225A | | | | |
* | Qualcomm MSM7625A | | | | |
* | Qualcomm MSM7227A | | | | |
* | Qualcomm MSM7627A | 32K | 32K | 256K | Wiki [1] |
* | Qualcomm MSM7225AB | | | | |
* | Qualcomm MSM7225AB | | | | |
* | Qualcomm QSD8250 | | | | |
* | Qualcomm QSD8650 | | | | |
* +--------------------+-----------+-----------+----------+-----------+
* | Spreadtrum SC6821 | 32K | 32K | ? | |
* | Spreadtrum SC6825 | 32K | 32K | 256K | Wiki [2] |
* | Spreadtrum SC8810 | ? | ? | ? | |
* | Spreadtrum SC8825 | 32K | 32K | ? | |
* +--------------------+-----------+-----------+----------+-----------+
*
* [1] https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1
* [2] https://en.wikipedia.org/wiki/Spreadtrum
*/
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 2,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 32
};
*l2 = (struct cpuinfo_cache) {
.size = 256 * 1024,
/*
* Follow NXP specification: "Eight-way set-associative 512 kB L2 cache with 32B line size"
* Reference: http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf
*/
.associativity = 8,
.line_size = 32
};
break;
case cpuinfo_uarch_cortex_a7:
/*
* Cortex-A7 MPCore Technical Reference Manual:
* 6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches. You can configure the
* instruction and data caches independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB.
*
* The L1 instruction memory system has the following features:
* - Instruction side cache line length of 32-bytes.
* - 2-way set-associative instruction cache.
*
* The L1 data memory system has the following features:
* - Data side cache line length of 64-bytes.
* - 4-way set-associative data cache.
*
* 7.1. About the L2 Memory system
* The L2 memory system consists of an:
* - Optional tightly-coupled L2 cache that includes:
* - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB.
* - Fixed line length of 64 bytes
* - 8-way set-associative cache structure
*
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Allwinner A20 | 2 | 32K | 32K | 256K | [1] |
* | Allwinner A23 | 2 | 32K | 32K | 256K | [2] |
* | Allwinner A31 | 4 | 32K | 32K | 1M | [3] |
* | Allwinner A31s | 4 | 32K | 32K | 1M | [4] |
* | Allwinner A33 | 4 | 32K | 32K | 512K | [5] |
* | Allwinner A80 Octa | 4(+4) | 32K | 32K | 512K(+2M) | [6] |
* | Allwinner A81T | 8 | 32K | 32K | 1M | [7] |
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Broadcom BCM2836 | 4 | 32K | 32K | 512K | [8] |
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Kirin 920 | 4(+4) | ? | ? | 512K | [9] |
* +--------------------+-------+-----------+-----------+-----------+-----------+
*
* [1] https://linux-sunxi.org/A20
* [2] https://linux-sunxi.org/A23
* [3] http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf
* [4] https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf
* [5] http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf
* [6] https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf
* [7] http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
* [8] https://www.raspberrypi.org/forums/viewtopic.php?t=98428
* [9] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/
*/
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 2,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = 128 * 1024 * cluster_cores,
.associativity = 8,
.line_size = 64
};
break;
case cpuinfo_uarch_cortex_a8:
/*
* Cortex-A8 Technical Reference Manual:
* 7.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches in a Harvard arrangement.
* The L1 memory system provides the core with:
* - fixed line length of 64 bytes
* - support for 16KB or 32KB caches
* - 4-way set associative cache structure
* 8.1. About the L2 memory system
* The L2 memory system is tightly coupled to the L1 data cache and L1 instruction cache.
* The key features of the L2 memory system include:
* - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB
* - fixed line length of 64 bytes
* - 8-way set associative cache structure
*
* +----------------------+-----------+-----------+-----------+-----------+
* | Processor model | L1D cache | L1I cache | L2 cache | Reference |
* +----------------------+-----------+-----------+-----------+-----------+
* | Exynos 3 Single 3110 | 32K | 32K | 512K | [1] |
* +----------------------+-----------+-----------+-----------+-----------+
* | TI DM 3730 | 32K | 32K | 256K | [2] |
* +----------------------+-----------+-----------+-----------+-----------+
*
* [1] https://en.wikichip.org/w/images/0/04/Exynos_3110.pdf
* [2] https://www.ti.com/lit/ds/symlink/dm3725.pdf
*/
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.associativity = 8,
.line_size = 64
};
switch (chipset->vendor) {
case cpuinfo_arm_chipset_vendor_samsung:
l2->size = 512 * 1024;
break;
default:
l2->size = 256 * 1024;
break;
}
break;
case cpuinfo_uarch_cortex_a9:
/*
* ARM Cortex‑A9 Technical Reference Manual:
* 7.1.1 Memory system
* The Cortex‑A9 processor has separate instruction and data caches.
* The caches have the following features:
* - Both caches are 4-way set-associative.
* - The cache line length is eight words.
* - You can configure the instruction and data caches independently during implementation
* to sizes of 16KB, 32KB, or 64KB.
* 8.1.5 Exclusive L2 cache
* The Cortex‑A9 processor can be connected to an L2 cache that supports an exclusive cache mode.
* This mode must be activated both in the Cortex‑A9 processor and in the L2 cache controller.
*
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Exynos 4 Dual 4210 | 2 | 32K | 32K | 1M | [1] |
* | Exynos 4 Dual 4212 | 2 | 32K | 32K | 1M | [2] |
* | Exynos 4 Quad 4412 | 4 | 32K | 32K | 1M | [3] |
* | Exynos 4 Quad 4415 | 4 | 32K | 32K | 1M | |
* | TI OMAP 4430 | 2 | 32K | 32K | 1M | [4] |
* | TI OMAP 4460 | 2 | 32K | 32K | 1M | [5] |
* +--------------------+-------+-----------+-----------+-----------+-----------+
*
* [1] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf
* [2] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf
* [3] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf
* [4] https://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.421.Witt-OMAP4430.pdf
* [5] http://www.anandtech.com/show/5310/samsung-galaxy-nexus-ice-cream-sandwich-review/9
*/
/* Use Exynos 4 specs */
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 32
};
*l2 = (struct cpuinfo_cache) {
.size = 1024 * 1024,
/* OMAP4460 in Pandaboard ES has 16-way set-associative L2 cache */
.associativity = 16,
.line_size = 32
};
break;
case cpuinfo_uarch_cortex_a15:
/*
* 6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches.
* The L1 instruction memory system has the following features:
* - 32KB 2-way set-associative instruction cache.
* - Fixed line length of 64 bytes.
* The L1 data memory system has the following features:
* - 32KB 2-way set-associative data cache.
* - Fixed line length of 64 bytes.
* 7.1. About the L2 memory system
* The features of the L2 memory system include:
* - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
* - Fixed line length of 64 bytes.
* - 16-way set-associative cache structure.
*
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Exynos 5 Dual 5250 | 2 | 32K | 32K | 1M | [1] |
* | Exynos 5 Hexa 5260 | 2(+4) | 32K | 32K | 1M(+512K) | [2] |
* | Exynos 5 Octa 5410 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
* | Exynos 5 Octa 5420 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
* | Exynos 5 Octa 5422 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
* | Exynos 5 Octa 5430 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
* | Exynos 5 Octa 5800 | 4(+4) | 32K | 32K | 2M(+512K) | [3] |
* | Kirin 920 | 4(+4) | ? | ? | 2M(+512K) | [4] |
* +--------------------+-------+-----------+-----------+-----------+-----------+
*
* [1] http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf
* [2] http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf
* [3] http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13
* [4] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/
*/
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 2,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 2,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = cluster_cores * 512 * 1024,
.associativity = 16,
.line_size = 64
};
break;
case cpuinfo_uarch_cortex_a17:
/*
* ARM Cortex-A17 MPCore Processor Technical Reference Manual:
* 6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches.
* The size of the instruction cache is implemented as either 32KB or 64KB.
* The size of the data cache is 32KB.
*
* The L1 instruction cache has the following features:
* - Instruction side cache line length of 64-bytes.
* - 4-way set-associative instruction cache.
*
* The L1 data cache has the following features:
* - Data side cache line length of 64-bytes.
* - 4-way set-associative data cache.
*
* 7.1. About the L2 Memory system
* An integrated L2 cache:
* - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB.
* - A fixed line length of 64 bytes.
* - 16-way set-associative cache structure.
*
* +------------------+-------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +------------------+-------+-----------+-----------+-----------+-----------+
* | MediaTek MT6595 | 4(+4) | 32K | 32K | 2M(+512K) | [1] |
* +------------------+-------+-----------+-----------+-----------+-----------+
*
* [1] https://blog.osakana.net/archives/5268
*/
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = cluster_cores * 512 * 1024,
.associativity = 16,
.line_size = 64
};
break;
#endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */
case cpuinfo_uarch_cortex_a35:
/*
* ARM Cortex‑A35 Processor Technical Reference Manual:
* 6.1. About the L1 memory system
* The L1 memory system includes several power-saving and performance-enhancing features.
* These include separate instruction and data caches, which can be configured
* independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB.
*
* L1 instruction-side memory system
* A dedicated instruction cache that:
* - is virtually indexed and physically tagged.
* - is 2-way set associative.
* - is configurable to be 8KB, 16KB, 32KB, or 64KB.
* - uses a cache line length of 64 bytes.
*
* L1 data-side memory system
* A dedicated data cache that:
* - is physically indexed and physically tagged.
* - is 4-way set associative.
* - is configurable to be 8KB, 16KB, 32KB, or 64KB.
* - uses a cache line length of 64 bytes.
*
* 7.1. About the L2 memory system
* The L2 cache is 8-way set associative.
* Further features of the L2 cache are:
* - Configurable size of 128KB, 256KB, 512KB, and 1MB.
* - Fixed line length of 64 bytes.
* - Physically indexed and tagged.
*
* +-----------------+---------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +-----------------+---------+-----------+-----------+-----------+-----------+
* | MediaTek MT6599 | 4(+4+2) | ? | ? | ? | |
* +-----------------+---------+-----------+-----------+-----------+-----------+
*/
*l1i = (struct cpuinfo_cache) {
.size = 16 * 1024, /* assumption based on low-end Cortex-A53 */
.associativity = 2,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 16 * 1024, /* assumption based on low-end Cortex-A53 */
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = 256 * 1024, /* assumption based on low-end Cortex-A53 */
.associativity = 8,
.line_size = 64
};
break;
case cpuinfo_uarch_cortex_a53:
/*
* ARM Cortex-A53 MPCore Processor Technical Reference Manual:
* 6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches. The implementer configures the
* instruction and data caches independently during implementation, to sizes of 8KB, 16KB, 32KB, or 64KB.
*
* The L1 Instruction memory system has the following key features:
* - Instruction side cache line length of 64 bytes.
* - 2-way set associative L1 Instruction cache.
*
* The L1 Data memory system has the following features:
* - Data side cache line length of 64 bytes.
* - 4-way set associative L1 Data cache.
*
* 7.1. About the L2 memory system
* The L2 memory system consists of an:
* - Optional tightly-coupled L2 cache that includes:
* - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB.
* - Fixed line length of 64 bytes.
* - 16-way set-associative cache structure.
*
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Broadcom BCM2837 | 4 | 16K | 16K | 512K | [1] |
* | Exynos 7420 | 4(+4) | 32K | 32K | 256K | [2, 3] |
* | Exynos 8890 | 4(+4) | 32K | 32K | 256K | [4] |
* | Rochchip RK3368 | 4+4 | 32K | 32K | 512K+256K | sysfs |
* | MediaTek MT8173C | 2(+2) | 32K | 32K | 512K(+1M) | sysfs |
* | Snapdragon 410 | 4 | 32K | 32K | 512K | [3] |
* | Snapdragon 630 | 4+4 | 32K | 32K | 1M+512K | sysfs |
* | Snapdragon 636 | 4(+4) | 32K+64K | 32K+64K | 1M+1M | sysfs |
* | Snapdragon 660 | 4(+4) | 32K+64K | 32K+64K | 1M+1M | sysfs |
* | Snapdragon 835 | 4(+4) | 32K+64K | 32K+64K | 1M(+2M) | sysfs |
* | Kirin 620 | 4+4 | 32K | 32K | 512K | [5] |
* +--------------------+-------+-----------+-----------+-----------+-----------+
*
* [1] https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766
* [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2
* [3] https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_lipp.pdf
* [4] http://www.boardset.com/products/products_v8890.php
* [5] http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
*/
if (midr_is_qualcomm_cortex_a53_silver(midr)) {
/* Qualcomm-modified Cortex-A53 in Snapdragon 630/660/835 */
uint32_t l2_size = 512 * 1024;
switch (chipset->series) {
case cpuinfo_arm_chipset_series_qualcomm_msm:
if (chipset->model == 8998) {
/* Snapdragon 835 (MSM8998): 1 MB L2 (little cores only) */
l2_size = 1024 * 1024;
}
break;
case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
switch (chipset->model) {
case 630:
if (cluster_id == 0) {
/* Snapdragon 630: 1 MB L2 for the big cores */
l2_size = 1024 * 1024;
}
break;
case 636:
/* Snapdragon 636: 1 MB L2 (little cores only) */
l2_size = 1024 * 1024;
break;
case 660:
case 662:
/* Snapdragon 660: 1 MB L2 (little cores only) */
l2_size = 1024 * 1024;
break;
}
break;
default:
break;
}
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 2,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = l2_size,
.associativity = 16,
.line_size = 64
};
} else {
/* Standard Cortex-A53 */
/* Use conservative values by default */
uint32_t l1_size = 16 * 1024;
uint32_t l2_size = 256 * 1024;
switch (chipset->series) {
case cpuinfo_arm_chipset_series_qualcomm_msm:
l1_size = 32 * 1024;
l2_size = 512 * 1024;
switch (chipset->model) {
case 8937: /* Snapdragon 430 */
case 8940: /* Snapdragon 435 */
case 8953: /* Snapdragon 625 or 626 (8953PRO) */
if (cluster_id == 0) {
/* 1M L2 for big cluster */
l2_size = 1024 * 1024;
}
break;
case 8952: /* Snapdragon 617 */
if (cluster_id != 0) {
/* 256K L2 for LITTLE cluster */
l2_size = 256 * 1024;
}
break;
default:
/* Silence compiler warning about unhandled enum values */
break;
}
break;
case cpuinfo_arm_chipset_series_qualcomm_apq:
l1_size = 32 * 1024;
l2_size = 512 * 1024;
break;
case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
l1_size = 32 * 1024;
l2_size = 512 * 1024;
if (chipset->model == 450 && cluster_id == 0) {
/* Snapdragon 450: 1M L2 for big cluster */
l2_size = 1024 * 1024;
}
break;
case cpuinfo_arm_chipset_series_hisilicon_hi:
l1_size = 32 * 1024;
l2_size = 512 * 1024;
break;
case cpuinfo_arm_chipset_series_hisilicon_kirin:
l1_size = 32 * 1024;
switch (chipset->model) {
case 970: /* Kirin 970 */
l2_size = 1024 * 1024;
break;
default:
l2_size = 512 * 1024;
break;
}
break;
case cpuinfo_arm_chipset_series_mediatek_mt:
switch (chipset->model) {
case 8173:
l1_size = 32 * 1024;
l2_size = 512 * 1024;
break;
}
break;
case cpuinfo_arm_chipset_series_rockchip_rk:
l1_size = 32 * 1024;
switch (chipset->model) {
case 3368:
if (cluster_id == 0) {
/* RK3368: 512 KB L2 for the big cores */
l2_size = 512 * 1024;
}
break;
}
break;
case cpuinfo_arm_chipset_series_broadcom_bcm:
switch (chipset->model) {
case 2837: /* BCM2837 */
l2_size = 512 * 1024;
break;
}
break;
case cpuinfo_arm_chipset_series_samsung_exynos:
l1_size = 32 * 1024;
break;
default:
/* Silence compiler warning about unhandled enum values */
break;
}
*l1i = (struct cpuinfo_cache) {
.size = l1_size,
.associativity = 2,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = l1_size,
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = l2_size,
.associativity = 16,
.line_size = 64
};
}
break;
case cpuinfo_uarch_cortex_a55r0:
case cpuinfo_uarch_cortex_a55:
/*
* ARM Cortex-A55 Core Technical Reference Manual
* A6.1. About the L1 memory system
* The Cortex®-A55 core's L1 memory system enhances core performance and power efficiency.
* It consists of separate instruction and data caches. You can configure instruction and data caches
* independently during implementation to sizes of 16KB, 32KB, or 64KB.
*
* L1 instruction-side memory system
* The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are:
* - 64-byte instruction side cache line length.
* - 4-way set associative L1 instruction cache.
*
* L1 data-side memory system
* - 64-byte data side cache line length.
* - 4-way set associative L1 data cache.
*
* A7.1 About the L2 memory system
* The Cortex-A55 L2 memory system is required to interface the Cortex-A55 cores to the L3 memory system.
* The L2 memory subsystem consists of:
* - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB or 256KB. Cache
* lines have a fixed length of 64 bytes.
*
* The main features of the L2 memory system are:
* - Strictly exclusive with L1 data cache.
* - Pseudo-inclusive with L1 instruction cache.
* - Private per-core unified L2 cache.
*
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
* | Snapdragon 845 | 4(+4) | 32K | 32K | 128K | 2M | [1], sysfs |
* | Exynos 9810 | 4(+4) | ? | ? | None | 512K | [2] |
* | Kirin 980 | 4(+4) | 32K | 32K | 128K | 4M | [3] |
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
*
* [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
* [2] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
* [3] https://en.wikichip.org/wiki/hisilicon/kirin/980
*/
if (midr_is_qualcomm_cortex_a55_silver(midr)) {
/* Qualcomm-modified Cortex-A55 in Snapdragon 670 / 710 / 845 */
uint32_t l3_size = 1024 * 1024;
switch (chipset->series) {
case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
/* Snapdragon 845: 2M L3 cache */
if (chipset->model == 845) {
l3_size = 2 * 1024 * 1024;
}
break;
default:
break;
}
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64,
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64,
};
*l2 = (struct cpuinfo_cache) {
.size = 128 * 1024,
.associativity = 4,
.line_size = 64,
};
*l3 = (struct cpuinfo_cache) {
.size = l3_size,
.associativity = 16,
.line_size = 64,
};
} else {
/* Standard Cortex-A55 */
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64,
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64,
};
if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos) {
*l2 = (struct cpuinfo_cache) {
.size = 512 * 1024,
/* DynamIQ */
.associativity = 16,
.line_size = 64,
};
} else {
uint32_t l3_size = 1024 * 1024;
switch (chipset->series) {
case cpuinfo_arm_chipset_series_hisilicon_kirin:
/* Kirin 980: 4M L3 cache */
if (chipset->model == 980) {
l3_size = 4 * 1024 * 1024;
}
break;
default:
break;
}
*l2 = (struct cpuinfo_cache) {
.size = 128 * 1024,
.associativity = 4,
.line_size = 64,
};
*l3 = (struct cpuinfo_cache) {
.size = l3_size,
/* DynamIQ */
.associativity = 16,
.line_size = 64,
};
}
}
break;
case cpuinfo_uarch_cortex_a57:
/*
* ARM Cortex-A57 MPCore Processor Technical Reference Manual:
* 6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches.
*
* The L1 instruction memory system has the following features:
* - 48KB 3-way set-associative instruction cache.
* - Fixed line length of 64 bytes.
*
* The L1 data memory system has the following features:
* - 32KB 2-way set-associative data cache.
* - Fixed line length of 64 bytes.
*
* 7.1 About the L2 memory system
* The features of the L2 memory system include:
* - Configurable L2 cache size of 512KB, 1MB, and 2MB.
* - Fixed line length of 64 bytes.
* - 16-way set-associative cache structure.
* - Inclusion property with L1 data caches.
*
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Snapdragon 810 | 4(+4) | 32K | 48K | 2M | [1] |
* | Exynos 7420 | 4(+4) | 32K | 48K | 2M | [2] |
* | Jetson TX1 | 4 | 32K | 48K | 2M | [3] |
* +--------------------+-------+-----------+-----------+-----------+-----------+
*
* [1] http://www.anandtech.com/show/9837/snapdragon-820-preview
* [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2
* [3] https://devblogs.nvidia.com/parallelforall/jetson-tx2-delivers-twice-intelligence-edge/
*/
*l1i = (struct cpuinfo_cache) {
.size = 48 * 1024,
.associativity = 3,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 2,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = cluster_cores * 512 * 1024,
.associativity = 16,
.line_size = 64,
.flags = CPUINFO_CACHE_INCLUSIVE
};
break;
case cpuinfo_uarch_cortex_a65:
{
/*
* ARM Cortex‑A65 Core Technical Reference Manual
* A6.1. About the L1 memory system
* The L1 memory system enhances the performance and power efficiency in the Cortex‑A65 core.
* It consists of separate instruction and data caches. You can configure instruction and data caches
* independently during implementation to sizes of 32KB or 64KB.
*
* L1 instruction-side memory system
* The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are:
* - 64-byte instruction side cache line length.
* - 4-way set associative L1 instruction cache.
*
* L1 data-side memory system
* - 64-byte data side cache line length.
* - 4-way set associative L1 data cache.
*
* A7.1 About the L2 memory system
* The Cortex‑A65 L2 memory system is required to interface the Cortex‑A65 cores to the L3 memory system.
* The L2 memory subsystem consists of:
* - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB, or 256KB.
* Cache lines have a fixed length of 64 bytes.
*
* The main features of the L2 memory system are:
* - Strictly exclusive with L1 data cache.
* - Pseudo-inclusive with L1 instruction cache.
* - Private per-core unified L2 cache.
*/
const uint32_t l1_size = 32 * 1024;
const uint32_t l2_size = 128 * 1024;
const uint32_t l3_size = 512 * 1024;
*l1i = (struct cpuinfo_cache) {
.size = l1_size,
.associativity = 4,
.line_size = 64,
};
*l1d = (struct cpuinfo_cache) {
.size = l1_size,
.associativity = 4,
.line_size = 64,
};
*l2 = (struct cpuinfo_cache) {
.size = l2_size,
.associativity = 4,
.line_size = 64,
.flags = CPUINFO_CACHE_INCLUSIVE
};
*l3 = (struct cpuinfo_cache) {
.size = l3_size,
/* DynamIQ */
.associativity = 16,
.line_size = 64,
};
break;
}
case cpuinfo_uarch_cortex_a72:
{
/*
* ARM Cortex-A72 MPCore Processor Technical Reference Manual
* 6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches.
*
* The L1 instruction memory system has the following features:
* - 48KB 3-way set-associative instruction cache.
* - Fixed line length of 64 bytes.
*
* The L1 data memory system has the following features:
* - 32KB 2-way set-associative data cache.
* - Fixed cache line length of 64 bytes.
*
* 7.1 About the L2 memory system
* The features of the L2 memory system include:
* - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
* - Fixed line length of 64 bytes.
* - Banked pipeline structures.
* - Inclusion property with L1 data caches.
* - 16-way set-associative cache structure.
*
* +---------------------+---------+-----------+-----------+------------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +---------------------+---------+-----------+-----------+------------+-----------+
* | Snapdragon 650 | 2(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [1] |
* | Snapdragon 652 | 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [2] |
* | Snapdragon 653 | 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [3] |
* | HiSilicon Kirin 950 | 4(+4) | 32K+32K | 48K+32K | ? | |
* | HiSilicon Kirin 955 | 4(+4) | 32K+32K | 48K+32K | ? | |
* | MediaTek MT8173C | 2(+2) | 32K(+32K) | 48K(+32K) | 1M(+512K) | sysfs |
* | MediaTek Helio X20 | 2(+4+4) | ? | ? | ? | |
* | MediaTek Helio X23 | 2(+4+4) | ? | ? | ? | |
* | MediaTek Helio X25 | 2(+4+4) | ? | ? | ? | |
* | MediaTek Helio X27 | 2(+4+4) | ? | ? | ? | |
* | Broadcom BCM2711 | 4 | 32K | 48K | 1M | [4] |
* +---------------------+---------+-----------+-----------+------------+-----------+
*
* [1] http://pdadb.net/index.php?m=processor&id=578&c=qualcomm_snapdragon_618_msm8956__snapdragon_650
* [2] http://pdadb.net/index.php?m=processor&id=667&c=qualcomm_snapdragon_620_apq8076__snapdragon_652
* [3] http://pdadb.net/index.php?m=processor&id=692&c=qualcomm_snapdragon_653_msm8976sg__msm8976_pro
* [4] https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
*/
uint32_t l2_size;
switch (chipset->series) {
case cpuinfo_arm_chipset_series_hisilicon_kirin:
l2_size = 2 * 1024 * 1024;
break;
default:
l2_size = 1024 * 1024;
break;
}
*l1i = (struct cpuinfo_cache) {
.size = 48 * 1024,
.associativity = 3,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 2,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = l2_size,
.associativity = 16,
.line_size = 64,
.flags = CPUINFO_CACHE_INCLUSIVE
};
break;
}
case cpuinfo_uarch_cortex_a73:
{
/*
* ARM Cortex‑A73 MPCore Processor Technical Reference Manual
* 6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches.
* The size of the instruction cache is 64KB.
* The size of the data cache is configurable to either 32KB or 64KB.
*
* The L1 instruction memory system has the following key features:
* - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache.
* - Fixed cache line length of 64 bytes.
*
* The L1 data memory system has the following features:
* - ...the data cache behaves like an eight-way set associative PIPT cache (for 32KB configurations)
* and a 16-way set associative PIPT cache (for 64KB configurations).
* - Fixed cache line length of 64 bytes.
*
* 7.1 About the L2 memory system
* The L2 memory system consists of:
* - A tightly-integrated L2 cache with:
* - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB.
* - A 16-way, set-associative structure.
* - A fixed line length of 64 bytes.
*
* The ARM Cortex A73 - Artemis Unveiled [1]
* "ARM still envisions that most vendors will choose to use configurations of 1 to
* 2MB in consumer products. The L2 cache is inclusive of the L1 cache. "
*
* +---------------------+---------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +---------------------+---------+-----------+-----------+-----------+-----------+
* | HiSilicon Kirin 960 | 4(+4) | 64K+32K | 64K+32K | ? | [2] |
* | MediaTek Helio X30 | 2(+4+4) | ? | 64K+ ? | ? | |
* | Snapdragon 636 | 4(+4) | 64K(+32K) | 64K(+32K) | 1M(+1M) | sysfs |
* | Snapdragon 660 | 4(+4) | 64K+32K | 64K+32K | 1M(+1M) | [3] |
* | Snapdragon 835 | 4(+4) | 64K+32K | 64K+32K | 2M(+1M) | sysfs |
* +---------------------+---------+-----------+-----------+-----------+-----------+
*
* [1] http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2
* [2] http://www.anandtech.com/show/11088/hisilicon-kirin-960-performance-and-power/3
* [3] https://arstechnica.com/gadgets/2017/05/qualcomms-snapdragon-660-and-630-bring-more-high-end-features-to-midrange-chips/
*/
uint32_t l1d_size = 32 * 1024;
uint32_t l2_size = 512 * 1024;
switch (chipset->series) {
case cpuinfo_arm_chipset_series_hisilicon_kirin:
l1d_size = 64 * 1024;
l2_size = 2 * 1024 * 1024;
break;
case cpuinfo_arm_chipset_series_mediatek_mt:
l1d_size = 64 * 1024;
l2_size = 1 * 1024 * 1024; /* TODO: verify assumption */
break;
default:
switch (midr) {
case UINT32_C(0x51AF8001): /* Kryo 280 Gold */
l1d_size = 64 * 1024;
l2_size = 2 * 1024 * 1024;
break;
case UINT32_C(0x51AF8002): /* Kryo 260 Gold */
l1d_size = 64 * 1024;
l2_size = 1 * 1024 * 1024;
break;
}
}
*l1i = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = l1d_size,
.associativity = (l1d_size >> 12),
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = l2_size,
.associativity = 16,
.line_size = 64,
.flags = CPUINFO_CACHE_INCLUSIVE
};
break;
}
case cpuinfo_uarch_cortex_a75:
{
/*
* ARM Cortex-A75 Core Technical Reference Manual
* A6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
*
* A6.1.1 L1 instruction-side memory system
* The L1 instruction memory system has the following key features:
* - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache.
* - Fixed cache line length of 64 bytes.
*
* A6.1.2 L1 data-side memory system
* The L1 data memory system has the following features:
* - Physically Indexed, Physically Tagged (PIPT), 16-way set-associative L1 data cache.
* - Fixed cache line length of 64 bytes.
* - Pseudo-random cache replacement policy.
*
* A7.1 About the L2 memory system
* The L2 memory subsystem consist of:
* - An 8-way set associative L2 cache with a configurable size of 256KB or 512KB.
* Cache lines have a fixed length of 64 bytes.
*
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
* | Snapdragon 845 | 4(+4) | 64K | 64K | 256K | 2M | [1], sysfs |
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
*
* [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
*/
uint32_t l3_size = 1024 * 1024;
switch (chipset->series) {
case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
/* Snapdragon 845: 2M L3 cache */
if (chipset->model == 845) {
l3_size = 2 * 1024 * 1024;
}
break;
default:
break;
}
*l1i = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 16,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = 256 * 1024,
.associativity = 8,
.line_size = 64
};
*l3 = (struct cpuinfo_cache) {
.size = l3_size,
.associativity = 16,
.line_size = 64
};
break;
}
case cpuinfo_uarch_cortex_a76:
{
/*
* ARM Cortex-A76 Core Technical Reference Manual
* A6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
*
* A6.1.1 L1 instruction-side memory system
* The L1 instruction memory system has the following key features:
* - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
* Physically Tagged (PIPT) 4-way set-associative L1 data cache.
* - Fixed cache line length of 64 bytes.
*
* A6.1.2 L1 data-side memory system
* The L1 data memory system has the following features:
* - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
* Physically Tagged (PIPT) 4-way set-associative L1 data cache.
* - Fixed cache line length of 64 bytes.
* - Pseudo-LRU cache replacement policy.
*
* A7.1 About the L2 memory system
* The L2 memory subsystem consist of:
* - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB.
* Cache lines have a fixed length of 64 bytes.
* - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
* - Dynamic biased replacement policy.
* - Modified Exclusive Shared Invalid (MESI) coherency.
*
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
* | Kirin 980 | 4(+4) | 64K | 64K | 512K | 4M | [1], [2] |
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
*
* [1] https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm
* [2] https://en.wikichip.org/wiki/hisilicon/kirin/980
*/
uint32_t l2_size = 256 * 1024;
uint32_t l3_size = 1024 * 1024;
switch (chipset->series) {
case cpuinfo_arm_chipset_series_hisilicon_kirin:
/* Kirin 980: 512K L2 cache + 4M L3 cache */
if (chipset->model == 980) {
l2_size = 512 * 1024;
l3_size = 4 * 1024 * 1024;
}
break;
default:
break;
}
*l1i = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64,
};
*l1d = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64,
};
*l2 = (struct cpuinfo_cache) {
.size = l2_size,
.associativity = 8,
.line_size = 64,
.flags = CPUINFO_CACHE_INCLUSIVE,
};
*l3 = (struct cpuinfo_cache) {
.size = l3_size,
.associativity = 16,
.line_size = 64,
};
break;
}
case cpuinfo_uarch_cortex_a77:
{
/*
* ARM Cortex-A77 Core Technical Reference Manual
* A6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
*
* A6.1.1 L1 instruction-side memory system
* The L1 instruction memory system has the following key features:
* - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
* Physically Tagged (PIPT) 4-way set-associative L1 data cache.
* - Fixed cache line length of 64 bytes.
*
* A6.1.2 L1 data-side memory system
* The L1 data memory system has the following features:
* - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
* Physically Tagged (PIPT) 4-way set-associative L1 data cache.
* - Fixed cache line length of 64 bytes.
* - Pseudo-LRU cache replacement policy.
*
* A7.1 About the L2 memory system
* The L2 memory subsystem consist of:
* - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. Cache lines
* have a fixed length of 64 bytes.
* - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
*/
const uint32_t l2_size = 256 * 1024;
const uint32_t l3_size = 1024 * 1024;
*l1i = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64,
};
*l1d = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64,
};
*l2 = (struct cpuinfo_cache) {
.size = l2_size,
.associativity = 8,
.line_size = 64,
.flags = CPUINFO_CACHE_INCLUSIVE,
};
*l3 = (struct cpuinfo_cache) {
.size = l3_size,
.associativity = 16,
.line_size = 64,
};
break;
}
case cpuinfo_uarch_neoverse_n1:
case cpuinfo_uarch_neoverse_v1:
case cpuinfo_uarch_neoverse_n2:
{
/*
* ARM Neoverse-n1 Core Technical Reference Manual
* A6.1. About the L1 memory system
* The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
*
* A6.1.1 L1 instruction-side memory system
* The L1 instruction memory system has the following key features:
* - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
* Physically Tagged (PIPT) 4-way set-associative L1 data cache.
* - Fixed cache line length of 64 bytes.
*
* A6.1.2 L1 data-side memory system
* The L1 data memory system has the following features:
* - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
* Physically Tagged (PIPT) 4-way set-associative L1 data cache.
* - Fixed cache line length of 64 bytes.
* - Pseudo-LRU cache replacement policy.
*
* A7.1 About the L2 memory system
* The L2 memory subsystem consist of:
* - An 8-way set associative L2 cache with a configurable size of 256KB, 512KB, or 1024KB. Cache lines
* have a fixed length of 64 bytes.
* - Strictly inclusive with L1 data cache.
* - When configured with instruction cache hardware coherency, strictly inclusive with L1 instruction cache.
* - When configured without instruction cache hardware coherency, weakly inclusive with L1 instruction cache.
*/
const uint32_t min_l2_size_KB= 256;
const uint32_t min_l3_size_KB = 0;
*l1i = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64,
};
*l1d = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64,
};
*l2 = (struct cpuinfo_cache) {
.size = min_l2_size_KB * 1024,
.associativity = 8,
.line_size = 64,
.flags = CPUINFO_CACHE_INCLUSIVE,
};
*l3 = (struct cpuinfo_cache) {
.size = min_l3_size_KB * 1024,
.associativity = 16,
.line_size = 64,
};
break;
}
#if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
case cpuinfo_uarch_scorpion:
/*
* - "The CPU includes 32KB instruction and data caches as
* well as a complete memory-management unit (MMU) suitable
* for high-level operating systems. The CPU also has
* 256KB of SRAM that can be allocated in 64KB increments
* to level-two (L2) cache or tightly coupled memory (TCM)." [1]
* We interpret it as L2 cache being 4-way set-associative on single-core Scorpion.
* - L1 Data Cache = 32 KB. 32 B/line. [2]
* - L2 Cache = 256 KB. 128 B/line. [2]
* - 256 KB (single-core) or 512 KB (dual-core) L2 cache [3]
* - Single or dual-core configuration [3]
* - For L1 cache assume the same associativity as Krait
*
* [1] https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf
* [2] http://www.7-cpu.com/cpu/Snapdragon.html
* [3] https://en.wikipedia.org/wiki/Scorpion_(CPU)
*/
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 32
};
*l2 = (struct cpuinfo_cache) {
.size = cluster_cores * 256 * 1024,
.associativity = 4,
.line_size = 128
};
break;
case cpuinfo_uarch_krait:
/*
* - L0 Data cache = 4 KB. 64 B/line, direct mapped [1]
* - L0 Instruction cache = 4 KB. [1]
* - L1 Data cache = 16 KB. 64 B/line, 4-way [1]
* - L1 Instruction cache = 16 KB, 4-way [1]
* - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has fast access only to 512 KB of L2 cache. [1]
* - L2 = 1MB (dual core) or 2MB (quad core), 8-way set associative [2]
*
* [1] http://www.7-cpu.com/cpu/Krait.html
* [2] http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2
*/
*l1i = (struct cpuinfo_cache) {
.size = 16 * 1024,
.associativity = 4,
.line_size = 64 /* assume same as L1D */
};
*l1d = (struct cpuinfo_cache) {
.size = 16 * 1024,
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = cluster_cores * 512 * 1024,
.associativity = 8,
.line_size = 128
};
break;
#endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */
case cpuinfo_uarch_kryo:
/*
* +-----------------+-------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +-----------------+-------+-----------+-----------+-----------+-----------+
* | Snapdragon 820 | 2+2 | 24K | 32K | 1M+512K | [1, 2] |
* | Snapdragon 821 | 2+2 | ? | ? | 1M+512K | [1] |
* +-----------------+-------+-----------+-----------+-----------+-----------+
*
* [1] http://www.anandtech.com/show/9837/snapdragon-820-preview/2
* [2] https://www.inforcecomputing.com/public_docs/Inforce6601/Inforce_6601_Micro-SOM_FAQs_04-2016-1.pdf
*/
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 24 * 1024,
.associativity = 3,
.line_size = 64
};
if (midr_is_kryo_silver(midr)) {
/* Kryo "Silver" */
*l2 = (struct cpuinfo_cache) {
.size = 512 * 1024,
.associativity = 8,
.line_size = 128
};
} else {
/* Kryo "Gold" */
*l2 = (struct cpuinfo_cache) {
.size = 1024 * 1024,
.associativity = 8,
.line_size = 128
};
}
break;
case cpuinfo_uarch_denver:
case cpuinfo_uarch_denver2:
/*
* The Denver chip includes a 128KB, 4-way level 1 instruction cache, a 64KB, 4-way level 2 data cache,
* and a 2MB, 16-way level 2 cache, all of which can service both cores. [1]
*
* All the caches have 64-byte lines. [2]
*
* [1] http://www.pcworld.com/article/2463900/nvidia-reveals-pc-like-performance-for-denver-tegra-k1.html
* [2] http://linleygroup.com/newsletters/newsletter_detail.php?num=5205&year=2014
*/
*l1i = (struct cpuinfo_cache) {
.size = 128 * 1024,
.associativity = 4,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = 2 * 1024 * 1024,
.associativity = 16,
.line_size = 64
};
break;
case cpuinfo_uarch_exynos_m1:
case cpuinfo_uarch_exynos_m2:
/*
* - "Moving past branch prediction we can see some elements of how the cache is set up for the L1 I$,
* namely 64 KB split into four sets with 128-byte line sizes for 128 cache lines per set" [1]
* - "For loads and stores, a 32 KB, 8-way set associative cache with 64 byte line size is used" [1]
* - "The L2 cache here is 2MB shared across all cores split into 16 sets. This memory is also split
* into 4 banks and has a 22 cycle latency" [1]
*
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+-----------+
* | Exynos 8 Octa 8890 | 4(+4) | 64K | 32K | 2M | [1] |
* | Exynos 8 Octa 8895 | 4(+4) | 64K | 32K | 2M | [2] |
* +--------------------+-------+-----------+-----------+-----------+-----------+
*
* [1] http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed
* [2] https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market
*/
*l1i = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4,
.line_size = 128
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 8,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = 2 * 1024 * 1024,
.associativity = 16,
.line_size = 64
};
break;
case cpuinfo_uarch_exynos_m3:
/*
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
* | Exynos 9810 | 4(+4) | 64K | ? | 512K | 4M | [1] |
* +--------------------+-------+-----------+-----------+-----------+----------+------------+
*
* [1] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
*/
*l1i = (struct cpuinfo_cache) {
.size = 64 * 1024 /* assume same as in Exynos M1/M2 cores */,
.associativity = 4 /* assume same as in Exynos M1/M2 cores */,
.line_size = 128 /* assume same as in Exynos M1/M2 cores */
};
*l1d = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 8 /* assume same as in Exynos M1/M2 cores */,
.line_size = 64 /* assume same as in Exynos M1/M2 cores */,
};
*l2 = (struct cpuinfo_cache) {
.size = 512 * 1024,
.associativity = 16 /* assume same as in Exynos M1/M2 cores */,
.line_size = 64 /* assume same as in Exynos M1/M2 cores */,
};
*l3 = (struct cpuinfo_cache) {
.size = 4 * 1024 * 1024,
.associativity = 16 /* assume DynamIQ cache */,
.line_size = 64 /* assume DynamIQ cache */,
};
break;
#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__)
case cpuinfo_uarch_thunderx:
/*
* "78K-Icache and 32K-D cache per core, 16 MB shared L2 cache" [1]
*
* [1] https://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf
*/
*l1i = (struct cpuinfo_cache) {
.size = 78 * 1024,
.associativity = 4 /* assumption */,
.line_size = 64 /* assumption */
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4 /* assumption */,
.line_size = 64 /* assumption */
};
*l2 = (struct cpuinfo_cache) {
.size = 16 * 1024 * 1024,
.associativity = 8 /* assumption */,
.line_size = 64 /* assumption */
};
break;
case cpuinfo_uarch_taishan_v110:
/*
* It features private 64 KiB L1 instruction and data caches as well as 512 KiB of private L2. [1]
*
* +------------------+-------+-----------+-----------+-----------+----------+-----------+
* | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
* +------------------+-------+-----------+-----------+-----------+----------+-----------+
* | Kunpeng 920-3226 | 32 | 64K | 64K | 512K | 32M | [2] |
* +------------------+-------+-----------+-----------+-----------+----------+-----------+
* | Kunpeng 920-4826 | 48 | 64K | 64K | 512K | 48M | [3] |
* +------------------+-------+-----------+-----------+-----------+----------+-----------+
* | Kunpeng 920-6426 | 64 | 64K | 64K | 512K | 64M | [4] |
* +------------------+-------+-----------+-----------+-----------+----------+-----------+
*
* [1] https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110
* [2] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226
* [3] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826
* [4] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426
*/
*l1i = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4 /* assumption */,
.line_size = 128 /* assumption */,
};
*l1d = (struct cpuinfo_cache) {
.size = 64 * 1024,
.associativity = 4 /* assumption */,
.line_size = 128 /* assumption */,
};
*l2 = (struct cpuinfo_cache) {
.size = 512 * 1024,
.associativity = 8 /* assumption */,
.line_size = 128 /* assumption */,
.flags = CPUINFO_CACHE_INCLUSIVE /* assumption */,
};
*l3 = (struct cpuinfo_cache) {
.size = cluster_cores * 1024 * 1024,
.associativity = 16 /* assumption */,
.line_size = 128 /* assumption */,
};
break;
#endif
case cpuinfo_uarch_cortex_a12:
case cpuinfo_uarch_cortex_a32:
default:
cpuinfo_log_warning("target uarch not recognized; using generic cache parameters");
/* Follow OpenBLAS */
if (arch_version >= 8) {
*l1i = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l1d = (struct cpuinfo_cache) {
.size = 32 * 1024,
.associativity = 4,
.line_size = 64
};
*l2 = (struct cpuinfo_cache) {
.size = cluster_cores * 256 * 1024,
.associativity = 8,
.line_size = 64
};
} else {
*l1i = (struct cpuinfo_cache) {
.size = 16 * 1024,
.associativity = 4,
.line_size = 32
};
*l1d = (struct cpuinfo_cache) {
.size = 16 * 1024,
.associativity = 4,
.line_size = 32
};
if (arch_version >= 7) {
*l2 = (struct cpuinfo_cache) {
.size = cluster_cores * 128 * 1024,
.associativity = 8,
.line_size = 32
};
}
}
break;
}
l1i->sets = l1i->size / (l1i->associativity * l1i->line_size);
l1i->partitions = 1;
l1d->sets = l1d->size / (l1d->associativity * l1d->line_size);
l1d->partitions = 1;
if (l2->size != 0) {
l2->sets = l2->size / (l2->associativity * l2->line_size);
l2->partitions = 1;
if (l3->size != 0) {
l3->sets = l3->size / (l3->associativity * l3->line_size);
l3->partitions = 1;
}
}
}
uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* processor) {
/*
* There is no precise way to detect cache size on ARM/ARM64, and cache size reported by cpuinfo
* may underestimate the actual cache size. Thus, we use microarchitecture-specific maximum.
*/
switch (processor->core->uarch) {
case cpuinfo_uarch_xscale:
case cpuinfo_uarch_arm11:
case cpuinfo_uarch_scorpion:
case cpuinfo_uarch_krait:
case cpuinfo_uarch_kryo:
case cpuinfo_uarch_exynos_m1:
case cpuinfo_uarch_exynos_m2:
case cpuinfo_uarch_exynos_m3:
/* cpuinfo-detected cache size always correct */
return cpuinfo_compute_max_cache_size(processor);
case cpuinfo_uarch_cortex_a5:
/* Max observed (NXP Vybrid SoC) */
return 512 * 1024;
case cpuinfo_uarch_cortex_a7:
/*
* Cortex-A7 MPCore Technical Reference Manual:
* 7.1. About the L2 Memory system
* The L2 memory system consists of an:
* - Optional tightly-coupled L2 cache that includes:
* - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB.
*/
return 1024 * 1024;
case cpuinfo_uarch_cortex_a8:
/*
* Cortex-A8 Technical Reference Manual:
* 8.1. About the L2 memory system
* The key features of the L2 memory system include:
* - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB
*/
return 1024 * 1024;
case cpuinfo_uarch_cortex_a9:
/* Max observed (e.g. Exynos 4212) */
return 1024 * 1024;
case cpuinfo_uarch_cortex_a12:
case cpuinfo_uarch_cortex_a17:
/*
* ARM Cortex-A17 MPCore Processor Technical Reference Manual:
* 7.1. About the L2 Memory system
* The key features of the L2 memory system include:
* - An integrated L2 cache:
* - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB.
*/
return 8 * 1024 * 1024;
case cpuinfo_uarch_cortex_a15:
/*
* ARM Cortex-A15 MPCore Processor Technical Reference Manual:
* 7.1. About the L2 memory system
* The features of the L2 memory system include:
* - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
*/
return 4 * 1024 * 1024;
case cpuinfo_uarch_cortex_a35:
/*
* ARM Cortex‑A35 Processor Technical Reference Manual:
* 7.1 About the L2 memory system
* L2 cache
* - Further features of the L2 cache are:
* - Configurable size of 128KB, 256KB, 512KB, and 1MB.
*/
return 1024 * 1024;
case cpuinfo_uarch_cortex_a53:
/*
* ARM Cortex-A53 MPCore Processor Technical Reference Manual:
* 7.1. About the L2 memory system
* The L2 memory system consists of an:
* - Optional tightly-coupled L2 cache that includes:
* - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB.
*/
return 2 * 1024 * 1024;
case cpuinfo_uarch_cortex_a57:
/*
* ARM Cortex-A57 MPCore Processor Technical Reference Manual:
* 7.1 About the L2 memory system
* The features of the L2 memory system include:
* - Configurable L2 cache size of 512KB, 1MB, and 2MB.
*/
return 2 * 1024 * 1024;
case cpuinfo_uarch_cortex_a72:
/*
* ARM Cortex-A72 MPCore Processor Technical Reference Manual:
* 7.1 About the L2 memory system
* The features of the L2 memory system include:
* - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
*/
return 4 * 1024 * 1024;
case cpuinfo_uarch_cortex_a73:
/*
* ARM Cortex‑A73 MPCore Processor Technical Reference Manual
* 7.1 About the L2 memory system
* The L2 memory system consists of:
* - A tightly-integrated L2 cache with:
* - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB.
*/
return 8 * 1024 * 1024;
case cpuinfo_uarch_cortex_a55:
case cpuinfo_uarch_neoverse_n1:
case cpuinfo_uarch_neoverse_v1:
case cpuinfo_uarch_neoverse_n2:
case cpuinfo_uarch_cortex_a75:
case cpuinfo_uarch_cortex_a76:
case cpuinfo_uarch_exynos_m4:
default:
/*
* ARM DynamIQ Shared Unit Technical Reference Manual
* 1.3 Implementation options
* L3_CACHE_SIZE
* - 256KB
* - 512KB
* - 1024KB
* - 1536KB
* - 2048KB
* - 3072KB
* - 4096KB
*/
return 4 * 1024 * 1024;
}
}
|