Upload 70 files

src_en/man.geco_multiflops.txt

@@ -0,0 +1,89 @@
+<h3>2.2.7 Multibit flops in ECO</h3>
+<p>Multibit flops can pose a challenge in logic equivalence check and ECO due to the different naming conventions used by various synthesis tools. For example, as depicted in Figure 5, a four-bit multibit flop has a different naming style in Cadence Genus compared to Synopsys Design Compiler after name changing. Additionally, backend tools may split some multibit flops into single bit flops to address timing issues. These factors make key point mapping a complex task.</p>
+<p>In logic equivalence check, multibit flops need to be mapped to single flops. However, the mapping of single flops to multibit flops from the Reference Netlist may differ from the Implementation Netlist. For instance, in Figure 5, the Implementation Netlist has a four-bit multibit flop instance named 'a_reg_0_2_4_', whereas the Reference Netlist after Synthesis may have two-bit multibit flops named 'a_reg_0_1_' and 'a_reg_2_4_'. Depending solely on naming conventions may not lead to the correct multibit to single bit mapping. Although LEC and ECO tools can handle some limited multibit to single bit mapping using comprehensive algorithms, there is no guarantee of complete successful mapping.</p>
+<div><img class='img-fluid' src='tp_image/autoeco/MULTIBIT_FLOP.png' /></div>
+<p><b>Figure 5: Multibit flop naming in synthesis tools</b></p>
+<p>GOF provides support for accurate and reliable key point mapping through the use of text mode SVF files from Design Compiler. These SVF files are encrypted by default, but can be converted to text mode when using Formality to read the encrypted file. Additionally, GOF can convert backend multibit flop split/merge information into an SVF file. By reading both the synthesis SVF and the converted SVF file, GOF is able to completely resolve the mapping of multibit flops to single bit flops.</p>
+<p>For instance, Innovus generates a multi_bit_pin_mapping file to store split and merge information. This file can be converted to an SVF text file using a GOF script.</p>
+<p>Here is an example script for converting an Innovus multi_bit_pin_mapping file:</p>
+<div class='gofscript'><pre><a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"libdir/art.lib"</span>);
+<a class='n' href='#___set_multibit_blasting'>set_multibit_blasting</a>(0); <span style='color:#b34c0a'># Disable multibit blasting</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>"imp_net.v"</span>);
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"the_top"</span>);
+
+open(FIN, <span style='color:#63ac0a'>"./multi_bit_pin_mapping"</span>);
+my $mbit_split = {};
+my $mbit_merge = {};
+while(&lt;FIN&gt;){
+  my ($from, $to) = (m/(\S+)\s+(\S+)/);
+  $from =~ s/\/\w+$<span style='color:#b34c0a'>//; # remove the pin</span>
+  $to =~ s/\/\w+$<span style='color:#b34c0a'>//; </span>
+  my ($module, $to_inst) = <a class='n' href='#___get_resolved'>get_resolved</a>($to);
+  my ($from_inst) = ($from =~ m/([^\/]+)$/);
+  my $libcell = <a class='n' href='#___get_ref'>get_ref</a>($to);
+  <a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"get ref of $to as $libcell\n"</span>);
+  my $is_ff = <a class='n' href='#___is_seq'>is_seq</a>($libcell, <span style='color:#63ac0a'>"-ff"</span>);
+  if($is_ff){
+    if(<a class='n' href='#___is_seq'>is_seq</a>($libcell, <span style='color:#63ac0a'>"-bank"</span>)==0){
+      if(!exists $mbit_split->{$module}{$from_inst}){
+	$mbit_split->{$module}{$from_inst} = [];
+      }
+      if(grep($_ eq $to_inst, @{$mbit_split->{$module}{$from_inst}})==0){
+	<a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"Multibit split in $module $from_inst to $to_inst\n"</span>);
+	push @{$mbit_split->{$module}{$from_inst}}, $to_inst;
+      }
+    }else{
+      <span style='color:#b34c0a'># Bank</span>
+      if(!exists $mbit_merge->{$module}{$to_inst}){
+	$mbit_merge->{$module}{$to_inst} = [];
+      }
+      if(grep($_ eq $from_inst, @{$mbit_merge->{$module}{$to_inst}})==0){
+	<a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"Multibit merge in $module $from_inst to $to_inst\n"</span>);
+	push @{$mbit_merge->{$module}{$to_inst}}, $from_inst;
+      }
+    }
+  }
+}
+close(FIN);
+
+my $svf = <span style='color:#63ac0a'>""</span>;
+foreach my $module (keys %$mbit_merge){
+  $svf .= <span style='color:#63ac0a'>"guide_multibit -design $module -type { svfMultibitTypeBank } \\\n"</span>;
+  $svf .= <span style='color:#63ac0a'>"  -groups { \\\n"</span>;
+  foreach my $mbit_inst (keys %{$mbit_merge->{$module}}){
+    my $i_st = <span style='color:#63ac0a'>""</span>;
+    my $cnt = 0;
+    foreach my $s_bit (@{$mbit_merge->{$module}{$mbit_inst}}){
+      $i_st .= <span style='color:#63ac0a'>" $s_bit 1"</span>;
+      $cnt++;
+    }
+    $i_st .= <span style='color:#63ac0a'>" $mbit_inst $cnt"</span>;
+    $svf .= <span style='color:#63ac0a'>"\t{ $i_st } \\\n"</span>;
+  }
+  $svf .= <span style='color:#63ac0a'>"    }\n"</span>;
+}
+foreach my $module (keys %$mbit_split){
+  $svf .= <span style='color:#63ac0a'>"guide_multibit -design $module -type { svfMultibitTypeSplit } \\\n"</span>;
+  $svf .= <span style='color:#63ac0a'>"  -groups { \\\n"</span>;
+  foreach my $mbit_inst (keys %{$mbit_split->{$module}}){
+    my $i_st = <span style='color:#63ac0a'>""</span>;
+    my $cnt = 0;
+    foreach my $s_bit (@{$mbit_split->{$module}{$mbit_inst}}){
+      $i_st .= <span style='color:#63ac0a'>" $s_bit 1"</span>;
+      $cnt++;
+    }
+    $i_st = <span style='color:#63ac0a'>" $mbit_inst $cnt $i_st"</span>;
+    $svf .= <span style='color:#63ac0a'>"\t{ $i_st } \\\n"</span>;
+  }
+  $svf .= <span style='color:#63ac0a'>"    }\n"</span>;
+}
+open(FOUT, <span style='color:#63ac0a'>">backend_multibit.svf.txt"</span>);
+print FOUT $svf;
+close(FOUT);
+</pre></div>
+<p>Two SVF files for Implementation are loaded in the implementation read_svf:</p>
+<div class='gofscript'><pre><a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>, <span style='color:#63ac0a'>"backend_multibit.svf.txt"</span>);  <span style='color:#b34c0a'># Two SVF files are loaded</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
+</pre></div>

src_en/man.geco_noexactpinmatch.txt

@@ -0,0 +1,34 @@
+<h3>2.2.11 No Exact Pin Match</h3>
+<p>Physical Synthesis is more and more popular in logic synthesis. Physical Synthesis tool, Design Compiler Topographical(DCT) or Design Compiler Graphical(DCG) for example, may add hierarchical pins that are not in RTL code and it may cause mapping issue when Implementation Netlist is comparing with Reference Netlist in ECO.</p>
+<p>For example, DCT may add 'IN0', 'IN1', 'IN2', 'IN2_BAR' ... to hierarchical modules. The new added pins are not necessarily matching to each other in Implementation Netlist and Reference Netlist. That is, IN0 in module A in Reference Netlist maybe a different signal from IN0 in module A in Implementation Netlist.</p>
+<div><img class='img-fluid' src='./tp_image/GvC/noexact_pin_match.png' /></div>
+<p><b>Figure 12: No Exact Pin Match</b></p>
+These pins are randomly named in each run. They won't affect logic equivalence check, but they need to be excluded in pin matching in ECO. Otherwise, the ECO tool would insert redundant logic or wrong logic.</p>
+<p>API set_noexact_pin_match can be used to resolve the mapping issue between Implementation Netlist and Reference Netlist.</p>
+<p>By adding the port naming regular expression in the API argument, set_noexact_pin_match('\bIN\d+(_BAR)?\b'), these ports will be remapped.</p>
+<p>Note: This API should be run before reading designs.</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># GOF ECO script, run_example_noexact_pin_match.pl</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;<span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.90nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span></br>
+<span style='background-color:yellow'><a class='n' href='#___set_noexact_pin_match'>set_noexact_pin_match</a>(<span style='color:#63ac0a'>'\bIN\d+(_BAR)?\b'</span>); <span style='color:#b34c0a'># The argument is in REGEX format to detect IN0/IN0_BAR/IN1...</span></span></br>
+<span style='color:#b34c0a'># Note: set_noexact_pin_match API should be run before reading designs!</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span></br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SOC_TOP"</span>); <span style='color:#b34c0a'># Set the top to&nbsp;the most top module SOC_TOP</span></br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);  </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0); </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0); </br>
+<a class='n' href='#___fix_design'>fix_design</a>;</br>
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span></br>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span></br>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span></br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+exit;<span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears</span></br>
+
+</div>
+<p></p>

src_en/man.geco_noteinrtlmod.txt

@@ -0,0 +1,15 @@
+<h3>2.2.16 Note in RTL modification and re-synthesis</h3>
+<p>When modifying RTL and do re-synthesis, care should be taken to maintain the database as much alike Implementation Netlist as possible.</p>
+<h4>2.2.16.1 Keep sequential signal name</h4>
+<p>A common problem in modifying RTL is having sequential signal name changed, which appears in Reference Netlist as a different flop instance. For example</p>
+<div class='gofscript'>
+always &#64;(posedge clk) abc &lt;= abc_next;
+</div>
+<p>It creates a flop instance 'abc_reg' in synthesis. If the ECO in RTL change this to</p>
+<div class='gofscript'>
+always &#64;(posedge clk) abc_new &lt;= abc_next;
+</div>
+<p>After synthesis, a new flop instance 'abc_new_reg' is created. GOF may fail to find that 'abc_new_reg' being able to merge with 'abc_reg', due to other non-equivalent points present, which brings a redundant fix in the new register creation.</p>
+<p>So it is highly recommended to keep the sequential signal names in re-synthesis.</p>
+<h4>2.2.16.2 Use the same synthesis constraints</h4>
+<p>When do re-synthesis, the same constraints should be used as what has been used in Implementation Netlist synthesis. If any hierarchy is not present in Implementation Netlist, it's better to flatten the module in synthesis to maintain the same hierarchies.</p>

src_en/man.geco_phaseinvert.txt

@@ -0,0 +1,31 @@
+<h3>2.2.12 Flip-flop Phase Inverted</h3>
+<p>During the pre-mask design stage, transitioning a flip-flop from resettable to settable type or vice versa is a relatively straightforward task. However, making such changes during the post-mask design stage can be challenging because it can be difficult to locate an available spare flip-flop to replace the original one. To overcome this challenge, a common approach is to add inverters to the input and output pins of the flip-flop while maintaining its original set/reset type.</p>
+<p>Aside from resolving the issue of locating spare flip-flops, adding inverters to the flip-flop input and output pins can also address timing or power-related concerns. In some cases, this technique can help with timing closure or reduce power consumption.</p>
+<p>It is essential to note, however, that implementing such changes can lead to challenges during logic equivalence checking. Incorrectly addressing these changes can result in false non-equivalent points, leading to design uncertainty. As such, appropriate measures should be taken to ensure that the changes made to the flip-flop type do not affect logic equivalence checking.</p>
+<div><img class='img-fluid' src='./tp_image/GvC/phase_invert.png' /></div>
+<p><b>Figure 13: Flip-flop Phase Inverted</b></p>
+<p>To address this issue, the GOF platform provides an API command to configure these cases. The set_mapping_method('-phase') API is utilized to handle such situations and ensure that the changes made to the flop type do not cause false non-equivalent result.</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># GOF ECO script, run_example_ff_phase_inverted.pl</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;<span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.90nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span></br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SOC_TOP"</span>); <span style='color:#b34c0a'># Set the top to&nbsp;the most top module SOC_TOP</span></br>
+<span style='background-color:yellow'><a class='n' href='#___set_mapping_method'>set_mapping_method</a>(<span style='color:#63ac0a'>'-phase'</span>); <span style='color:#b34c0a'># Check flop phase during LEC</span></span></br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);  </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0); </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0); </br>
+<a class='n' href='#___fix_design'>fix_design</a>;</br>
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span></br>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span></br>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span></br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+exit;<span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears</span></br>
+
+</div>
+<p></p>

src_en/man.geco_reporttimingapi.txt

@@ -0,0 +1,17 @@
+<h2>2.10 Report Timing</h2>
+<p>Timing can be reported before or after ECO by report_timing API.</p>
+<h3>2.10.1 Report Timing APIs</h3>
+<p>Timing report related APIs are these:</p>
+<div class='gofscript'>
+<a class='n' href='#___create_clock'>create_clock</a>: Timing command and GOF Formal command. Create clock for fault verification<br>
+<a class='n' href='#___set_initial_trans'>set_initial_trans</a>: Timing command. Set initial transition for clock<br>
+<a class='n' href='#___set_input_delay'>set_input_delay</a>: Timing command. Set input delay<br>
+<a class='n' href='#___set_output_delay'>set_output_delay</a>: Timing command. Set output delay<br>
+<a class='n' href='#___set_output_load'>set_output_load</a>: Timing command. Set output load to all output ports<br>
+<a class='n' href='#___set_input_transition'>set_input_transition</a>: Timing command. Set input transition to all input ports<br>
+<a class='n' href='#___set_false_path'>set_false_path</a>: Timing command. Set false path<br>
+<a class='n' href='#___set_clock_uncertainty'>set_clock_uncertainty</a>: Timing command. Set clock uncertainty<br>
+<a class='n' href='#___report_timing'>report_timing</a>: Timing command. Report timing<br>
+<a class='n' href='#___list_wireload'>list_wireload</a>: Timing command. List all wireload defined in the liberty files<br>
+<a class='n' href='#___set_wireload'>set_wireload</a>: Command for Timing Report. Set wireload for one liberty library<br>
+</div>

src_en/man.geco_rundebugautoeco.txt

@@ -0,0 +1,6 @@
+<h3>2.2.4 Run and debug in automatic functional ECO</h3>
+<p>The ECO Script can be run by '-run' option.</p>
+<div class='gofscript'>
+<strong>gof -run run_example.pl</strong>
+</div>
+<p>Check <a href='gof_manual.php#-run-and-debug-gof-script'>Run and debug ECO script section</a> in User Manual for more detail</p>

src_en/man.geco_script4gatearray.txt

@@ -0,0 +1,33 @@
+<h3>2.4.5 Example GOF script for gate array cells ECO flow</h3>
+<p>GOF script has the exact same syntax of Perl script. It runs the exported commands that access the netlist database and modify the netlist.</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># GOF ECO script, run_gate_array_cells_eco_example.pl</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;<span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_gate_array_example"</span> );</br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span></br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module that ECO is working on</span></br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);</br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);</br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);</br>
+<a class='n' href='#___read_lef'>read_lef</a>(<span style='color:#63ac0a'>"tsmc.lef"</span>);   <span style='color:#b34c0a'># Read LEF</span></br>
+<a class='n' href='#___read_def'>read_def</a>(<span style='color:#63ac0a'>"topmod.def"</span>); <span style='color:#b34c0a'># Read Design Exchange Format file</span></br>
+<a class='n' href='#___fix_design'>fix_design</a>;</br>
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span></br>
+<span style='color:#b34c0a'># Specify gate array cells, spare and functional</span></br>
+<span style='color:#b34c0a'># set_dont_use command can be used to exclude some gate array cells</span></br>
+<span style='background-color:yellow'><a class='n' href='#___get_spare_cells'>get_spare_cells</a>(<span style='color:#63ac0a'>"-gate_array"</span>, <span style='color:#63ac0a'>"G*"</span>, <span style='color:#63ac0a'>"-gate_array_filler"</span>, <span style='color:#63ac0a'>"GFILL*"</span>); <span style='color:#b34c0a'># Gate array cells extraction</span></span></br>
+<a class='n' href='#___map_spare_cells'>map_spare_cells</a>();</br>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span></br>
+<a class='n' href='#___check_design'>check_design</a>();<span style='color:#b34c0a'># Check design</span></br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+<a class='n' href='#___write_tcl'>write_tcl</a>(<span style='color:#63ac0a'>"eco_icc.tcl"</span>);<span style='color:#b34c0a'># Write out TCL script for ICC</span></br>
+exit;<span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears</span></br>
+
+</div>
+<p></p>

src_en/man.geco_script4manualeco.txt

@@ -0,0 +1,20 @@
+<h3>2.6.4 Example GOF script for Manual ECO</h3>
+<div class='gofscript'>
+# GOF ECO script, run_example.pl
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;<span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in implementation Netlist Which is under ECO</span></br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the scope to the module that ECO is working on</span></br>
+<span style='color:#b34c0a'># The following API adds a mux in flop 'state_reg_0_' D input pin,</span></br>
+<span style='color:#b34c0a'># and connect up the original connection to pin 'A',</span></br>
+<span style='color:#b34c0a'># pin 'B' connect to net 'next_state[7]', and pin 'S' to net 'sel_mode'</span></br>
+<span style='color:#b34c0a'># the net can be replaced by format of 'instance/pin' , E.G. '.S(state_reg_2_/Q)'</span></br>
+<a class='n' href='#___change_pin'>change_pin</a>(<span style='color:#63ac0a'>"state_reg_0_/D"</span>, <span style='color:#63ac0a'>"MX2X4"</span>, <span style='color:#63ac0a'>""</span>, <span style='color:#63ac0a'>".A(-),.B(next_state[7]),.S0(sel_mode)"</span>);</br>
+<a class='n' href='#___report_eco'>report_eco</a>();</br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+exit;<span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears</span></br>
+
+</div>

src_en/man.geco_script4manualmetalonly.txt

@@ -0,0 +1,39 @@
+<h3>2.7.2 Example GOF script for Manual Metal Only ECO</h3>
+<div class='gofscript'>
+<span style='color:#b34c0a'># Manual Metal Only ECO, manual_metal_eco.pl</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;</br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"metal_eco0123"</span>);</br>
+<a class='n' href='#___set_log_file'>set_log_file</a>(<span style='color:#63ac0a'>"metal_eco0123.log"</span>);</br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"/prj/lib/tsmc40.lib"</span>);</br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"/prj/netlist/imp_net.v"</span>);</br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"mtop"</span>);</br>
+&nbsp;</br>
+<a class='n' href='#___new_port'>new_port</a>(<span style='color:#63ac0a'>"nout7"</span>, <span style='color:#63ac0a'>"-output"</span>);<span style='color:#b34c0a'># Create a new port 'nout7'</span></br>
+<span style='color:#b34c0a'># Place the port to 60000, 1000000. It's approximate position, the main purpose is for</span></br>
+<span style='color:#b34c0a'># spare instances selection</span></br>
+<a class='n' href='#___place_port'>place_port</a>(<span style='color:#63ac0a'>"nout7"</span>, 60000, 100000);</br>
+<a class='n' href='#___new_port'>new_port</a>(<span style='color:#63ac0a'>"nout8"</span>, <span style='color:#63ac0a'>"-output"</span>);<span style='color:#b34c0a'># Create another port</span></br>
+<a class='n' href='#___place_port'>place_port</a>(<span style='color:#63ac0a'>"nout8"</span>, 120000, 81000);</br>
+<span style='color:#b34c0a'># 'nout8' is driven by an invert first, and the invert's input is driven by pin 'cmpmod/rego/QN'</span></br>
+<a class='n' href='#___change_port'>change_port</a>(<span style='color:#63ac0a'>"nout8"</span>, <span style='color:#63ac0a'>"INV_X1M"</span>, <span style='color:#63ac0a'>""</span>, <span style='color:#63ac0a'>"cmpmod/rego/QN"</span>);</br>
+<span style='color:#b34c0a'># Drive the 'nout7' by 'INV_X1M' and leave the input unconnected, but the mapped</span></br>
+<span style='color:#b34c0a'># spare instance name is returned.</span></br>
+my $inst = <a class='n' href='#___change_port'>change_port</a>(<span style='color:#63ac0a'>"nout7"</span>, <span style='color:#63ac0a'>"INV_X1M"</span>, <span style='color:#63ac0a'>""</span>, <span style='color:#63ac0a'>""</span>);</br>
+<span style='color:#b34c0a'># Drive the new instance's input by a flop, and specify the flop's connection in the 4<sup>th</sup> argument</span></br>
+<a class='n' href='#___change_pin'>change_pin</a>(<span style='color:#63ac0a'>"$inst/A"</span>, <span style='color:#63ac0a'>"SDFFRPQ_X4M"</span>, <span style='color:#63ac0a'>""</span>, \n<span style='color:#63ac0a'>".CK(cmpmod/rego/CK),.D(cmpmod/rego/QN),.R(1'b0),.SE(1'b0),.SI(1'b0)"</span>);</br>
+&nbsp;</br>
+<a class='n' href='#___read_def'>read_def</a>(<span style='color:#63ac0a'>"/prj/def/imp_net.def"</span>);</br>
+<a class='n' href='#___get_spare_cells'>get_spare_cells</a>(<span style='color:#63ac0a'>"Spare_*/*_SPARE_GATE*"</span>);</br>
+<span style='color:#b34c0a'># Before mapping to spare gates, set a large number in buffer distance, so that GOF does&nbsp;not</span></br>
+<span style='color:#b34c0a'># add buffers for long connections.</span></br>
+<a class='n' href='#___set_buffer_distance'>set_buffer_distance</a>(9999999);</br>
+<span style='color:#b34c0a'># The following 'map_spare_cells' command maps the three new ECO instances to the optimal</span></br>
+<span style='color:#b34c0a'># spare instances.</span></br>
+<a class='n' href='#___map_spare_cells'>map_spare_cells</a>;</br>
+&nbsp;</br>
+<a class='n' href='#___report_eco'>report_eco</a>;</br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"imp_eco0123.v"</span>);</br>
+
+</div>
+<p></p>

src_en/man.geco_script4metaleco.txt

@@ -0,0 +1,40 @@
+<h3>2.3.6 Example GOF script for Metal Only ECO</h3>
+<p>GOF script has the exact same syntax of Perl script. It runs the exported commands that access the netlist database and modify the netlist.</p>
+<p>The following shows an example of an automatic Metal Only ECO:</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># GOF ECO script, run_metal_only_example.pl</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;<span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_metalonly_example "</span> );</br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span></br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module that ECO is working on</span></br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);  </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0); </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0); </br>
+<a class='n' href='#___read_def'>read_def</a>(<span style='color:#63ac0a'>"topmod.def"</span>);<span style='color:#b34c0a'># Read Design Exchange Format file, optional. Loading DEF file before fix_design makes ECO physical aware</span></br>
+<a class='n' href='#___fix_design'>fix_design</a>;</br>
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span></br>
+<span style='color:#b34c0a'># The following is metal ECO related</span></br>
+<span style='color:#b34c0a'># Specify spare cell pattern, when 'map_spare_cells' is done, a new spare list file is&nbsp;written out</span></br>
+<span style='color:#b34c0a'># with updated spare list.</span></br>
+<a class='n' href='#___get_spare_cells'>get_spare_cells</a>(<span style='color:#63ac0a'>"*/*_SPARE*"</span>);</br>
+<span style='color:#b34c0a'># Comment the above line and use the following line to use spare list file</span></br>
+<span style='color:#b34c0a'># if the spare list file has been generated already and gone through other ECOs</span></br>
+<span style='color:#b34c0a'># get_spare_cells("-file", "spare_list_file.txt");</span></br>
+<span style='color:#b34c0a'># set_constraints("-num", "and<20"); # set_constraints is optional to control AND cell usage under 20 counts</span></br>
+<a class='n' href='#___map_spare_cells'>map_spare_cells</a>();</br>
+<span style='color:#b34c0a'># Use one of the following lines if external Synthesis Tool is used</span></br>
+<span style='color:#b34c0a'>#map_spare_cells ( "-syn", "rc" );</span></br>
+<span style='color:#b34c0a'>#map_spare_cells ( "-syn", "dc_shell" );</span></br>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span></br>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span></br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+exit;<span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears</span></br>
+
+</div>
+<p></p>

src_en/man.geco_scriptmodemanualeco.txt

@@ -0,0 +1,13 @@
+<h2>2.7 Script Mode Metal Only Manual ECO Flow</h2>
+<p>In Manual Metal Only ECO, any new added gates are&nbsp;automatically mapped to spare gate instances by 'map_spare_cells' command. A Design Exchange Format file has to be loaded for the tool to find optimal spare instances. If the file is not present, the mapping is skipped.</p>
+<h3>2.7.1 Files and data requirements in Metal Only Manual ECO</h3>
+<ul>
+	<li>Standard library (Synopsys Liberty) files with extension '.'lib'</li>
+	<li>Other Verilog libraries</li>
+	<li>Implementation Netlist</li>
+	<li>DEF (Design Exchange Format) file. If it is not loaded, GOF won&rsquo;t map the spare gate type cells to the exact spare instances</li>
+	<li>Spare gates pattern. It is in &lsquo;hierarchical_instance/leaf_instance&rsquo; format. It has wild card '*' to match the spare gates in Implementation Netlist</li>
+	<li>Spare gates list file. If several users work on the same Implementation Netlist, the initial spare gates list file should be generated only once. And a new spare gates list file should be created every time ECO is done</li>
+	<li>ECO locations</li>
+</ul>
+<p></p>

src_en/man.geco_scriptmodmanulaeco.txt

@@ -0,0 +1,3 @@
+<h2>2.6 Script Mode Full Layers Manual ECO Flow</h2>
+<p>In many cases, the ECO operations are well known by users. They can be inserting buffers to a 128bits bus, or adding isolation AND gates to all outputs of a module. In these cases, manual ECO by scripts is more efficient and resource saving.</p>
+<p>GOF exports many APIs for ECO operations in GOF script.</p>

src_en/man.geco_sparegatesnumanddis.txt

@@ -0,0 +1,13 @@
+<h3>2.3.3 Spare Gates Number and Distribution</h3>
+<p>Spare gates are incorporated into the design and their percentage relative to the entire digital area is usually dependent on the design maturity. For instance, the first version of a design typically requires a higher percentage of spare cells, usually around 8-10% of the entire digital area. As the design progresses to the second version, a lower percentage of spare cells, approximately 4-5% of the total digital area, is sufficient. By the third version, less than 3% additional spare cells may be necessary. Additionally, during the backend placement process, any remaining empty space can be filled with extra spare gates.</p>
+<p>Besides the spare gate area percentage, the proportion of various spare gate types is also crucial. For example, a design with 126K instances may have spare gates in different categories, as depicted in the following figure:</p>
+<ul>
+  <li>Red: 126 spare flip-flops</li>
+  <li>Green: 252 spare NAND2 gates</li>
+  <li>Yellow: 252 spare NOR2 gates</li>
+  <li>Blue: 882 spare inverters (INV)</li>
+  <li>Purple: 126 spare multiplexers (MUX)</li>
+  <li>Black: 126 spare tie-lo (TIELO) gates</li>
+</ul><div><img class='img-fluid' src='tp_image/autoeco/spare_gate_distribute.png' /></div>
+<p><b>Figure 19: Spare Gates numbers and distribution</b></p>
+<p>Usually, spare gates are uniformly distributed on the floor plan, as shown in figure 19. Nevertheless, if accessible, users can adjust the distribution based on historical metal-only ECO data. Blocks that are prone to design changes may require more spare gates, while mature logic may require fewer spare gates.</p>

src_en/man.geco_sparegatessyn.txt

@@ -0,0 +1,4 @@
+<h3>2.3.2 Spare Gates Synthesis</h3>
+<p>GOF ECO utilizes a heuristic method that employs constraints to identify the optimal mapping of spare gates. The process involves setting constraints to restrict the types of NAND/NOR/AND/OR gates to be considered, and then conducting a mapping exercise to identify the nearest available spare gates. The cost of the mapping is determined by adding the distance between the measured location and the actual location of the spare gate. For example, if a NAND gate needs to be mapped in a metal-only ECO, and the measured location is (100, 100), while the closest spare gate (spare_0) is located at (120, 120), then the cost is calculated as (120-100)+(120-100)=40. The method involves multiple iterations, and the optimal solution is selected based on the lowest cost.</p>
+<p>To ensure that new instances are accurately mapped to the nearest spare gate instances, it is necessary to have a Design Exchange Format (DEF) file. Without loading the DEF file, the GOF process will use spare gate types without precise mapping to exact spare instances. However, P&R tools like SOC Encounter will map new instances in the new netlist to the closest spare gates.</p>
+<p>During the 'fix_design' command, GOF examines the top-level module and its sub-modules to identify any non-equivalent points and optimize the logic cone to create a patch circuit with the minimum number of gates.</p>

src_en/man.geco_specialcharacters.txt

@@ -0,0 +1,12 @@
+<h3>2.6.7 Special characters</h3>
+<p>The special character '-' is used to represent existing connection. For example</p>
+<div class='gofscript'>
+<a class='n' href='#___change_pin'>change_pin</a>("U0/A", "BUFFX1", "eco_buf","-");
+</div>
+<p>A buffer is inserted into A pin of instance U0. The old existing net drives the new buffer now.</p>
+<p>The special character '.' is used in ECO new instance name if the new instance needs to be in the same hierarchy as the ECO spot.</p>
+<div class='gofscript'>
+<a class='n' href='#___change_pin'>change_pin</a>("u_qcif/u_num2/u_spare1/B", "AOI21X2",".", "net1,net2,net3");
+</div>
+<p>If the instance is empty, GOF creates 'AOI21X2' in the current top level. With ".", GOF creates 'AOI21X2' new instance in hierarchy "u_qcif/u_num2/u_spare1".</p>
+<p></p>

src_en/man.geco_standcellmapping.txt

@@ -0,0 +1,14 @@
+<p>In Metal Only ECO, the design has completed place and route. Any new gates added should map to spare gates that located in the design. GOF supports Standard Spare Cells and Metal Configurable Gate Array Spare Cells post-mask metal only ECO.</p>
+<div><img class='img-fluid' alt='' src='/tp_image/auto_eco_metalonly.png' /></div>
+<p><b>Figure 17: Metal Only ECO</b></p>
+<h3>2.3.1 Standard Cells Spare Gates Mapping</h3>
+<p>GOF employs an internal synthesis engine to map patch logic onto spare gates. These spare gates must consist of the following spare type combinations.</p>
+<ol>
+  <li>Two ports 'and/or' gates, 'inv' gates and flops, 'mux' is optional.</li>
+  <li>Two ports 'nand/nor' gates, 'inv' gates and flops, 'mux' is optional.</li>
+  <li>Two ports 'nand/nor/and/or' gates, 'inv' gates and flops, 'mux' is optional.</li>
+</ol>
+<p>Out of the three combinations, the second combination has the least area and the third combination has the best performance in metal only EOC. </p>
+<p>In Figure 18, the circuit produced by ECO on the left-hand side contains arbitrary standard cells. During the mapping process, gates of type MUX and flop are mapped directly onto the spare gates, as they have a one-to-one correspondence with the spare gate list. However, for more complex cell types such as AO32, they must be synthesized and mapped onto three AND gates and one NOR gate.</p>
+<div><img class='img-fluid' alt='' src='/tp_image/spare_gates_mapping.png' /></div>
+<p><b>Figure 18: Standard Cells Spare Gates Mapping</b></p>

src_en/man.geco_stepstodofullfuneco.txt

@@ -0,0 +1,16 @@
+<h3>2.2.2 Steps to do automatic functional ECO</h3>
+<p>Steps for an automatic functional ECO:</p>
+<ul>
+  <li>Modify the original RTL</li>
+  <li>Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist</li>
+  <li>Create GOF ECO script:
+    <ul>
+      <li>Specify ECO name in 'setup_eco'</li>
+      <li>Load Liberty files and Verilog libraries</li>
+      <li>Load the Reference Netlist and the Implementation Netlist</li>
+      <li>Fix the design by 'fix_design'</li>
+      <li>Report ECO status and write out ECO results</li>
+    </ul>
+  </li>
+  <li>Run the above ECO script by "gof -run eco_script.pl"</li>
+</ul>

src_en/man.geco_stepstodomanecoscript.txt

@@ -0,0 +1,17 @@
+<h3>2.6.2 Steps to do Manual ECO In Scripts</h3>
+<p>A typical situation for a Manual ECO:</p>
+<ul>
+	<li>Run LEC on modified RTL to Implementation Netlist</li>
+	<li>Collect the failing points in the above run</li>
+    <li>Create a GOF ECO script:
+    <ul>
+	  <li>Define ECO name in &lsquo;setup_eco&rsquo;</li>
+	  <li>Load Standard Cell libraries and Verilog libraries</li>
+	  <li>Load Implementation Netlist</li>
+	  <li>Locate ECO point</li>
+	  <li>Use ECO APIs to fix the logic</li>
+      <li>Report ECO status and write out ECO results</li>
+    </ul>
+	<li>Run the script</li>
+</ul>
+<p></p>

src_en/man.geco_stepstorungatearray.txt

@@ -0,0 +1,20 @@
+<h3>2.4.4 Steps to do gate array spare cells ECO</h3>
+<p>A typical process for gate array spare cells ECO:</p>
+<ul>
+  <li>Modify the original RTL</li>
+  <li>Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist</li>
+  <li>Create GOF ECO script:
+    <ul>
+      <li>Specify ECO name in 'setup_eco'</li>
+      <li>Load Liberty files and Verilog libraries</li>
+      <li>Load the Reference Netlist and the Implementation Netlist</li>
+      <li>Fix the design by 'fix_design'</li>
+      <li>Load LEF files</li>
+      <li>Load DEF files</li>
+      <li>Extract gate array spare cells and functional cells by 'get_spare_cells'</li>
+      <li>Run 'map_spare_cells' to convert the patch all gate array functional cells type and map to optimal gate array spare cells</li>
+      <li>Report ECO status and write out ECO results</li>
+    </ul>
+  </li>
+  <li>Run the above ECO script by "gof -run eco_script.pl"</li>
+</ul>

src_en/man.geco_stepstorunmetaleco.txt

@@ -0,0 +1,20 @@
+<h3>2.3.5 Steps to do automatic Metal Only ECO</h3>
+<p>A typical process for an automatic Metal Only ECO:</p>
+<ul>
+  <li>Modify the original RTL</li>
+  <li>Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist</li>
+  <li>Create GOF ECO script:
+    <ul>
+      <li>Specify ECO name in 'setup_eco'</li>
+      <li>Load Liberty files and Verilog libraries</li>
+      <li>Load the Reference Netlist and the Implementation Netlist</li>
+      <li>Fix the design by 'fix_design'</li>
+      <li>Load DEF file, optional</li>
+      <li>Load LEF file, optional. It's useful in LayoutViewer feature</li>
+      <li>Create Spare Gates List by Spare Gates pattern or by reading in spare list file</li>
+      <li>Run 'map_spare_cells' to remap the patch from 'fix_design' command to all spare -type gates patch netlist and select the closest spare instances for each gate in the patch netlist</li>
+      <li>Report ECO status and write out ECO results</li>
+    </ul>
+  </li>
+  <li>Run the above ECO script by "gof -run eco_script.pl"</li>
+</ul>

src_en/man.geco_svffilessupport.txt

@@ -0,0 +1,2 @@
+<h3>2.2.6 SVF files support</h3>
+<p>When working with designs that include multibit flops or significant name changes, SVF files can be a valuable tool for facilitating key point mapping. Although multibit flops are used to reduce silicon area and power consumption, the different combinations of single bit flop instances in each multibit flop instance can create challenges for key point mapping, especially when combined with name changes. Additionally, backend tools may split or merge multibit flops, further complicating the process. To avoid these challenges and ensure accurate key point mapping, it's highly recommended to load SVF files when working with multibit flops. For more information on this topic, please refer to the <a href='gof_manual.php#-multibit-flops-in-eco'>Multibit Flops in ECO</a> section.</p>

src_en/man.geco_synsubmod.txt

@@ -0,0 +1,54 @@
+<h3>2.2.5 Synthesize sub-modules only</h3>
+<p>Performing a complete top-level netlist synthesis can be time-consuming. GOF provides APIs enabling the integration of newly synthesized sub-modules into the original pre-layout netlist, along with updates to the top-level SVF file. This incremental approach allows the generation of the large top-level netlist and the top-level SVF file, resulting in significant time and effort savings. At the RTL level, designers identify modified RTL modules during ECO and synthesize them to create netlist and SVF files. Some altered RTL modules, particularly sub-parent modules with only sub-module instantiations, may not require synthesis.</p>
+<p>In Figure 4, only two sub-modules, SUB_MOD31 and SUB_MOD32, require re-synthesis in the extensive SOC_TOP design. Their parent module has only experienced connection changes and remains in netlist format, eliminating the need for synthesis. The example below illustrates how to process these files and generate a new SOC_TOP level netlist and SVF file.</p>
+<div><img class='img-fluid' src='tp_image/autoeco/syn_sub_module.png' /></div>
+<p><b>Figure 4: Sub-modules to be synthesized</b></p>
+<p><b>Step 1: Add missing DFT ports</b></p>
+<p>The newly synthesized sub-modules may lack certain ports present in the original netlist. Notably, ports essential for scan in and scan out are typically added by the DFT tool. Since the DFT process is not applied to the new synthesized sub-modules, it's necessary to incorporate these ports as dummy ones within the modules to avoid syntax errors.</p>
+<p>The procedure for incorporating DFT ports into the newly synthesized modules is as follows:</p>
+<div class='gofscript'><pre>use strict;
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"SOC_TOP.pre_layout.gv"</span>);<span style='color:#b34c0a'># Read in the original pre_layout netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"SUB_MOD31.new_syn.gv"</span>);<span style='color:#b34c0a'># Read in new synthesized netlist</span>
+<a class='n' href='#___set_tree'>set_tree</a>(<span style='color:#63ac0a'>"ref"</span>);
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SUB_MOD31_1"</span>); <span style='color:#b34c0a'># The old pre-layout netlist may have this module with prefix or suffix added in uniquify</span>
+my @ref_port_ins = <a class='n' href='#___get_ports'>get_ports</a>(<span style='color:#63ac0a'>"-input"</span>);
+my @ref_port_outs = <a class='n' href='#___get_ports'>get_ports</a>(<span style='color:#63ac0a'>"-output"</span>);
+<a class='n' href='#___set_tree'>set_tree</a>(<span style='color:#63ac0a'>"imp"</span>);
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SUB_MOD31"</span>);
+my @imp_port_ins = <a class='n' href='#___get_ports'>get_ports</a>(<span style='color:#63ac0a'>"-input"</span>);
+my @imp_port_outs = <a class='n' href='#___get_ports'>get_ports</a>(<span style='color:#63ac0a'>"-output"</span>);
+my $cnt = 0;
+foreach my $port (@ref_port_ins){
+  if(!grep($port eq $_, @imp_port_ins)){ <span style='color:#b34c0a'># The input port is not in the new synthesized module</span>
+    <a class='n' href='#___new_port'>new_port</a>($port, <span style='color:#63ac0a'>"-input"</span>);
+    <a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"$cnt: Warning input $port is not in the new synthesized sub-module\n"</span>); $cnt++;
+  }
+}
+foreach my $port (@ref_port_outs){
+  if(!grep($port eq $_, @imp_port_outs)){ <span style='color:#b34c0a'># The output port is not in the new synthesized module</span>
+    <a class='n' href='#___new_port'>new_port</a>($port, <span style='color:#63ac0a'>"-output"</span>);
+    <a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"$cnt: Warning output $port is not in the new synthesized sub-module\n"</span>); $cnt++;
+  }
+}
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"SUB_MOD31.dft_ports_added.gv"</span>);
+exit;
+</pre></div>
+<p>The identical process should be executed on SUB_MOD32 to include the necessary DFT-related ports.</p>
+<p><b>Step 2: Replace sub-modules netlist and SVF</b></p>
+<p>During this step, the DFT ports added netlist and SVF files of the synthesized sub-modules are read to substitute the original pre-layout netlist and SVF files.</p>
+<p>The procedure for replacing netlist and SVF:</p>
+<div class='gofscript'><pre><a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"SOC_TOP.pre_layout.svf"</span>);
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"SOC_TOP.pre_layout.gv"</span>);
+<a class='n' href='#___read_sub_module_svf'>read_sub_module_svf</a>(<span style='color:#63ac0a'>"SUB_MOD31.svf.txt"</span>, <span style='color:#63ac0a'>"-module"</span>, <span style='color:#63ac0a'>"SUB_MOD31_1"</span>, <span style='color:#63ac0a'>"-syn_module"</span>, <span style='color:#63ac0a'>"SUB_MOD31"</span>);
+<a class='n' href='#___read_sub_module_svf'>read_sub_module_svf</a>(<span style='color:#63ac0a'>"SUB_MOD32.svf.txt"</span>, <span style='color:#63ac0a'>"-module"</span>, <span style='color:#63ac0a'>"SUB_MOD32_1"</span>, <span style='color:#63ac0a'>"-syn_module"</span>, <span style='color:#63ac0a'>"SUB_MOD32"</span>);
+<a class='n' href='#___read_sub_module_netlist'>read_sub_module_netlist</a>(<span style='color:#63ac0a'>"SUB_MOD31.dft_ports_added.gv"</span>, <span style='color:#63ac0a'>"-module"</span>, <span style='color:#63ac0a'>"SUB_MOD31_1"</span>, <span style='color:#63ac0a'>"-syn_module"</span>, <span style='color:#63ac0a'>"SUB_MOD31"</span>);
+<a class='n' href='#___read_sub_module_netlist'>read_sub_module_netlist</a>(<span style='color:#63ac0a'>"SUB_MOD32.dft_ports_added.gv"</span>, <span style='color:#63ac0a'>"-module"</span>, <span style='color:#63ac0a'>"SUB_MOD32_1"</span>, <span style='color:#63ac0a'>"-syn_module"</span>, <span style='color:#63ac0a'>"SUB_MOD32"</span>);
+<a class='n' href='#___read_sub_module_netlist'>read_sub_module_netlist</a>(<span style='color:#63ac0a'>"SUB_MOD3.new.v"</span>, <span style='color:#63ac0a'>"-module"</span>, <span style='color:#63ac0a'>"SUB_MOD3_1"</span>, <span style='color:#63ac0a'>"-syn_module"</span>, <span style='color:#63ac0a'>"SUB_MOD3"</span>, <span style='color:#63ac0a'>"-sub_only"</span>); <span style='color:#b34c0a'># Need sub_only option</span>
+
+<a class='n' href='#___replace_sub_module_netlist'>replace_sub_module_netlist</a>(<span style='color:#63ac0a'>"SOC_TOP.new_reference.gv"</span>); <span style='color:#b34c0a'># Replace netlist should be run first</span>
+<a class='n' href='#___replace_sub_module_svf'>replace_sub_module_svf</a>(<span style='color:#63ac0a'>"SOC_TOP.new_reference.svf"</span>);    <span style='color:#b34c0a'># Then replace SVF</span>
+
+</pre></div>
+<p>After the generation of both the top-level netlist and SVF files, they can be incorporated into the complete top-level automatic ECO process.</p>

src_en/man.geco_tcloutaftergatearray.txt

@@ -0,0 +1,39 @@
+<h3>2.4.6 TCL output file format after Gate Array ECO</h3>
+<div class='gofscript'>
+current_instance
+current_instance up_ma/utx_afe_if
+create_net eco_ganet_wire270244
+create_net eco_ganet_gofrev_net_on19915
+create_net eco_ganet_wire270246
+create_net eco_ganet_gofrev_net_on19913
+disconnect_net [get_nets n_223] [get_pins slow_cnt_reg_1/D]
+connect_net [get_nets eco_ganet_wire270244] [get_pins slow_cnt_reg_1/D]
+create_cell eco_gacell_gofrev_inst_19916 GND2D1
+create_cell eco_gacell_gofrev_inst_19914 GOR2D1
+create_cell eco_gacell_inst270245 GMX2D1
+create_cell eco_gacell_gofrev_inst_19912 GAN2D1
+connect_net [get_nets eco_ganet_gofrev_net_on19915] [get_pins eco_gacell_gofrev_inst_19916/A]
+connect_net [get_nets slow_cnt_2] [get_pins eco_gacell_gofrev_inst_19916/B]
+connect_net [get_nets eco_ganet_wire270244] [get_pins eco_gacell_gofrev_inst_19916/Y]
+connect_net [get_nets eco_ganet_gofrev_net_on19913] [get_pins eco_gacell_gofrev_inst_19914/A]
+connect_net [get_nets xg_prbs_0] [get_pins eco_gacell_gofrev_inst_19914/B]
+connect_net [get_nets eco_ganet_gofrev_net_on19915] [get_pins eco_gacell_gofrev_inst_19914/Y]
+connect_net [get_nets n_221] [get_pins eco_gacell_inst270245/A]
+connect_net [get_nets slow_cnt_0] [get_pins eco_gacell_inst270245/B]
+connect_net [get_nets fast_data_9] [get_pins eco_gacell_inst270245/S0]
+connect_net [get_nets eco_ganet_wire270246] [get_pins eco_gacell_inst270245/Y]
+connect_net [get_nets n_223] [get_pins eco_gacell_gofrev_inst_19912/A]
+connect_net [get_nets eco_ganet_wire270246] [get_pins eco_gacell_gofrev_inst_19912/B]
+connect_net [get_nets eco_ganet_gofrev_net_on19913] [get_pins eco_gacell_gofrev_inst_19912/Y]
+set_cell_location -ignore_fixed -coordinates <span style='color:#63ac0a'>"253.84 413.28"</span> eco_gacell_inst270245
+set_cell_location -ignore_fixed -coordinates <span style='color:#63ac0a'>"250.42 390.60"</span> eco_gacell_gofrev_inst_19912
+set_cell_location -ignore_fixed -coordinates <span style='color:#63ac0a'>"288.04 497.70"</span> eco_gacell_gofrev_inst_19914
+set_cell_location -ignore_fixed -coordinates <span style='color:#63ac0a'>"204.25 267.12"</span> eco_gacell_gofrev_inst_19916
+current_instance
+size_cell FILLER_impl0_7256 GFILL3
+size_cell FILLER_impl1_30700 GFILL2
+current_instance
+remove_cell FILLER_impl1_20939
+remove_cell FILLER_impl1_40219
+
+</div>

src_en/man.geco_tienetcell.txt

@@ -0,0 +1,9 @@
+<h3>2.2.13 Tie High Tie Low nets</h3>
+<p>By default, GOF uses 1'b0 for tie low net and 1'b1 for tie high net. Some designs may prefer tie cell over 1'b0/1'b1. API set_tiehi_net and set_tielo_net can be used to control which tie format is used. To overwrite the default 1'b0/1'b1, simply set empty argument to the APIs.</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># Set empty argument to set_tiehi_net/set_tielow_net to use Tie Cells</span></br>
+<a class='n' href='#___set_tiehi_net'>set_tiehi_net</a>(<span style='color:#63ac0a'>""</span>); <span style='color:#b34c0a'># Tie High cell will be used instead of 1'b1</span></br>
+<a class='n' href='#___set_tielo_net'>set_tielo_net</a>(<span style='color:#63ac0a'>""</span>); <span style='color:#b34c0a'># Tie Low cell will be used instead of 1'b0</span></br>
+
+</div>
+<p></p>

src_en/man.geco_timingbeforeaftereco.txt

@@ -0,0 +1,6 @@
+<h3>2.10.2 Timing before ECO</h3>
+<p>In order to report the timing in paths of interest before a functional ECO, it is necessary to specify the option of 'from,' 'to,' or 'through' in the report_timing function. By comparing the numbers obtained before and after a functional ECO, an appropriate timing ECO method can be selected.</p>
+<h3>2.10.3 Timing after ECO</h3>
+<p>After performing a functional ECO, report_timing can utilize the 'from,' 'to,' or 'through' options. If the function is executed without specifying any of these options, it will report the timing of paths that traverse the ECO instances.</p>
+<div><img class='img-fluid' src='tp_image/gofdoc/report_timing.png' /></div>
+<p><b>Figure 29: Report timing on paths through ECO instances</b></p>

src_en/man.geco_tstitchscanchain.txt

@@ -0,0 +1,67 @@
+<h3>2.2.14 Stitch new flops into scan chain</h3>
+<p>To prevent any loss of DFT coverage, it is recommended to integrate new flops added in an ECO into the existing scan chains. Industrial data suggests that in a design with 100K flops, 100 newly added non-scan flops can lead to a DFT coverage loss of over 0.1%. Such loss of DFT coverage is unacceptable for high-reliability chips, such as those used in automobiles. Therefore, if there are any new flops introduced in a functional ECO, it is necessary to redo the scan chain to incorporate the new flops.</p>
+<div><img class='img-fluid' src='tp_image/GvC/stitch_scan_chain_qt.png' /></div>
+<p><b>Figure 14: Stitch scan chain</b></p>
+<p>There are multiple methods available in GOF to insert new flops into scan chains. One option is to utilize the 'stitch_scan_chain' API, which automatically integrates the new flops into the scan chains. Alternatively, there are several netlist processing APIs that can be used to manually insert the new flops into the scan chains.</p>
+<p><strong>Automatic mode to insert flops into a scan chain in the local modules</strong></p>
+<p>An automatic method can be used to integrate flops into a scan chain within local modules. In the following example script, suppose the 'fix_design' command adds eight new flops named 'state_new_reg_0' to 'state_new_reg_7'. To integrate these flops into the scan chain within the local module: </p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># API stitch_scan_chain without any argument to insert new flops in the local modules</span></br>
+<a class='n' href='#___stitch_scan_chain'>stitch_scan_chain</a>();</br>
+
+</div>
+<p><strong>Automatic mode to insert flops before one flop</strong></p>
+<p>GOF offers an automatic method to insert new flops before a specified flop instance. Users can identify the instance name of one flop, and GOF will insert all new flops into the scan chain before that instance.</p><p>For instance, let's say it is required to integrate all the new flops into the scan chain prior to the instance named 'u_pixel_ctrl/pulse_reg':</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># API stitch_scan_chain with -to option</span></br>
+<a class='n' href='#___stitch_scan_chain'>stitch_scan_chain</a>(<span style='color:#63ac0a'>'-to'</span>, <span style='color:#63ac0a'>'u_pixel_ctrl/pulse_reg'</span>);</br>
+
+</div>
+<p><strong>Manual mode to connect up all new flops</strong></p>
+<p>The scan chain can be re-connected up manually by ECO APIs. And new scan in/out ports are created.</p>
+<div class='gofscript'>
+<pre>
+<span style='color:#b34c0a'># GOF ECO script, run_manual_stitch_scan_chain_example.pl</span>
+use strict;
+<a class='n' href='#___undo_eco'>undo_eco</a>; <span style='color:#b34c0a'># Discard previous ECO operations</span>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_manual_stitch_scan_chain_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module</span>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);
+<a class='n' href='#___fix_design'>fix_design</a>;
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span>
+<a class='n' href='#___set_error_out'>set_error_out</a>(0); <span style='color:#b34c0a'># Don't exit if finds error</span>
+my @flops = <a class='n' href='#___get_cells'>get_cells</a>(<span style='color:#63ac0a'>"-hier"</span>, <span style='color:#63ac0a'>"-nonscan"</span>); <span style='color:#b34c0a'># Find all new flops that are not in scan chain yet</span>
+<span style='color:#b34c0a'># @flops can be defined by reading a list file</span>
+if(scalar(@flops)){ <span style='color:#b34c0a'># If there are new flops, start the work</span>
+  <a class='n' href='#___new_port'>new_port</a>(<span style='color:#63ac0a'>"so1"</span>, <span style='color:#63ac0a'>"-output"</span>); <span style='color:#b34c0a'># New a scan out port so1</span>
+  <a class='n' href='#___new_port'>new_port</a>(<span style='color:#63ac0a'>"si1"</span>, <span style='color:#63ac0a'>"-input"</span>); <span style='color:#b34c0a'># New a scan in port si1</span>
+  my $cnt = 0;
+  my $now_si;
+  foreach my $flop (@flops){
+    $cnt++;
+    if(<a class='n' href='#___is_scan_flop'>is_scan_flop</a>($flop)==0){
+      my $flop_name = <a class='n' href='#___get_ref'>get_ref</a>($flop);
+      my $scanflop = <a class='n' href='#___get_scan_flop'>get_scan_flop</a>($flop_name); <span style='color:#b34c0a'># If the flop is not scan type, change to scan type flop</span>
+      <a class='n' href='#___change_gate'>change_gate</a>($flop, $scanflop);
+    }
+    if($cnt==1){
+      <a class='n' href='#___change_port'>change_port</a>(<span style='color:#63ac0a'>"so1"</span>, <span style='color:#63ac0a'>"$flop/Q"</span>); <span style='color:#b34c0a'># The first flop drives the new scan out port</span>
+    }else{
+      <a class='n' href='#___change_pin'>change_pin</a>($now_si, <span style='color:#63ac0a'>"$flop/Q"</span>);
+    }
+    $now_si = <span style='color:#63ac0a'>"$flop/SI"</span>;
+    <a class='n' href='#___change_pin'>change_pin</a>(<span style='color:#63ac0a'>"$flop/SE"</span>, <span style='color:#63ac0a'>"te"</span>); <span style='color:#b34c0a'># All scan enable pin is connected to scan enable signal</span>
+  }
+  <a class='n' href='#___change_pin'>change_pin</a>($now_si, <span style='color:#63ac0a'>"si1"</span>); <span style='color:#b34c0a'># The last flop has the new scan in port driving SI pin</span>
+}
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span>
+exit; 
+
+</pre></div>

src_en/man.gformal_coneofinf.txt

@@ -0,0 +1,8 @@
+<h3>3.1.3 Cone of Influence</h3>
+<p>SPFM and LFM metrics can be calculated in two methods, rough mode and detail mode. The rough mode is done by structural analysis of the Cone of Influence. The detail mode is calculated by formal analysis of the Cone of Influence. </p>
+<p>Two types of strobing points shall be defined for the Cone of Influence extraction.</p>
+<ul><li>Observation Points</li><li>Diagnostic Points</li></ul>
+<p>The observation points are the outputs or registers that are impacted by the injected faults which affect functional safety and violate safety goal. The diagnostic points are the outputs or registers to check if injected faults can be detected at these strobing points or perceived by the up level driver.</p>
+<p>The logic back traced starting from the observation points and the diagnostic points all the way to the inputs or black boxes. The Cone of Influence (COI) is created for the observation points and the diagnostic points respectively. Each cell and each input port in the cones will be injected faults according to the Fault Model section.</p>
+<div><img class='img-fluid' src='tp_image/fusa/fusa_coverage.png' /></div>
+<p><b>Figure 31: Cone of Influence</b></p>

src_en/man.gformal_debugonefault.txt

@@ -0,0 +1,15 @@
+<h3>3.2.2 FUSA Debug One Fault</h3>
+<p>The API verify_faults can run on an individual fault to check if the fault can propagate to the observation points. If the fault is observable, a VCD file can be dumped to show how to toggle the input ports cycle by cycle to propagate the fault. All internal signals waveforms are captured in the VCD file.</p>
+<p>The following script is to check if one SEU fault can propagate. If yes, a VCD file is dumped:</p>
+<div class='gofscript'><pre>
+<a class='n' href='#___set_log_file'>set_log_file</a>(<span style='color:#63ac0a'>"spfm_lfm.log"</span>);     <span style='color:#b34c0a'># Set log file name</span>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);      <span style='color:#b34c0a'># Read in liberty file</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>'ecc_process.v'</span>); <span style='color:#b34c0a'># Read in the design block</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"ecc_top"</span>);               <span style='color:#b34c0a'># Set the top module name</span>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"test_mode"</span>, 0); <span style='color:#b34c0a'># Set pin constraint</span>
+<a class='n' href='#___set_observe_points'>set_observe_points</a>(<span style='color:#63ac0a'>"data_out*"</span>);  <span style='color:#b34c0a'># data_out[31:0] affects functional safety</span>
+<a class='n' href='#___set_observe_points'>set_observe_points</a>(<span style='color:#63ac0a'>"synd_out"</span>);   <span style='color:#b34c0a'># synd_out affects functional safety</span>
+<span style='color:#b34c0a'># To check if the fault can be propagated to the detect points, set_observe_points on the detect points</span>
+<a class='n' href='#___verify_faults'>verify_faults</a>(<span style='color:#63ac0a'>"u_ecc_ops/bit_reg:SEU"</span>, <span style='color:#63ac0a'>"-vcd"</span>, <span style='color:#63ac0a'>"debug_seu.vcd"</span>);    <span style='color:#b34c0a'># Check if the Single Event Upset on the flop can propagate</span>
+<a class='n' href='#___gexit'>gexit</a>;
+</pre></div>

src_en/man.gformal_faltsinjectveri.txt

@@ -0,0 +1,4 @@
+<h3>3.1.6 Faults Injection Formal Verification</h3>
+<p>The formal COI analysis needs to be run to get the final accurate metrics. For each fault injected, GOF Formal either proves that a path exists to propagate the fault to the observation or diagnostic points, or disprove there is such path. A path means by toggling input ports in some limited clock cycles, the fault can propagate to the observation/diagnostic points.</p>
+<p>GOF Formal doesn't require stimulus nor is a testbench required. The tool automatically determines the stimulus. For each fault injected, two designs are compared to see if the specified outputs are equal. One design is the fault injected design, the other is the original design. The specified outputs are the observation points or the diagnostic points set by user. The faults to be injects can be thousands or millions. GOF Formal uses cluster command to fully utilize the cluster computing power. Thousands of jobs can be submitted in parallel to the cluster machines with only one license being used.</p>
+<p>After the detail formal COI analysis of the above example, the residual fault number is 178, and the final SPFM is 96%. The latent fault number is 260, so the final LFM is 94%.</p>

src_en/man.gformal_falutmodel.txt

@@ -0,0 +1,4 @@
+<h3>3.1.2 Fault Model</h3>
+<p>GOF Formal injects faults to each input port and each pin of logic gates. Each input port has stuck-at 0 and stuck-at 1 faults injected. Every combinational gate has stuck-at 0 and stuck-at 1 faults injected into each pin. For flip-flop, stuck-at 0 and stuck-at 1 faults are injected into each data and clock pin. And flip-flop has Single Event Upset (SEU) fault injected to the state in random time.</p>
+<div><img class='img-fluid' src='tp_image/fusa/fault_mode.png' /></div>
+<p><b>Figure 30: Fault model for logic gates</b></p>

src_en/man.gformal_goformaloverview.txt

@@ -0,0 +1,15 @@
+<h2>3.1 GOF Formal</h2>
+<p>GOF Formal is one of the function components integrated in GOF platform. It provides a formal method to calculate fault coverage in an IC design in functional safety.</p>
+<p>ISO26262 defines functional safety as "the absence of unreasonable risk due to hazards caused by malfunctioning behavior of electrical and electronic systems". Four ASILs are proposed to represent four degrees of automotive hazards. In IC component, the coverage in the ASIL requirement is the fault coverage in the logic circuit. Specifically, single point fault metric (SPFM) and latent fault metric (LFM) should meet minimum numbers for the corresponding ASIL levels. The following table lists the three ASIL levels with specific coverage numbers defined in the standard. </p>
+<table border=1 class='lefttable'>
+<thead><tr>
+<th style='width:180px'>ASIL</th><th style='width:180px'>SPFM</th><th style='width:180px'>LFM</th></tr></thead>
+<tr>
+<td>B</td><td>&ge;90%</td><td>&ge;60%</td></tr>
+<tr>
+<td>C</td><td>&ge;97%</td><td>&ge;80%</td></tr>
+<tr>
+<td>D</td><td>&ge;99%</td><td>&ge;90%</td></tr>
+</table>
+<p></p>
+<p>The traditional method to calculate the fault coverage is pure simulation based. It's inefficient and time consuming. GOF Formal provides a formal and efficient way to calculate the SPFM and LFM numbers of a logic design. It can work in a standalone mode to calculate the coverage metric. And it can also work as a supplemental method to cover the faults left over from simulation based process.</p>

src_en/man.gformal_metricsimprovement.txt

@@ -0,0 +1,8 @@
+<h3>3.1.7 FUSA Metrics Improvement</h3>
+<p>In order to improve the fault coverage, safety mechanisms should be built in the IC design. There are several approaches for safety mechanism implementation.</p>
+<ul>
+<li>Redundancy design, double modular and triple modular redundancy</li>
+<li>Parity or error correction implementation</li>
+<li>Periodically self check</li>
+</ul>
+<p>In Figure 32, a safety mechanism can be a double modular design or ECC design. The diagnostic points would be the alarm bits in the double modular error bit, or ECC error recovering signals. For SPFM metric improvement, those gates in Area A that are not covered by safety mechanism can be modified to support TMR (Triple Module Redundancy), so that <span style='font-size:18.0pt'>&lambda;</span>SPF can be further reduced and SPFM improved accordingly. See this <a href='gof_display_doc.php?document_type=tmr_eco'>TMR ECO Case</a></p>

src_en/man.gformal_roughmethodbycoi.txt

@@ -0,0 +1,13 @@
+<h3>3.1.5 Rough Method by COI Analysis</h3>
+<p>In the rough method calculation by analyzing COI structure, the best and worst metrics can be quickly calculated.</p>
+<p>In the example shown in Figure 32, the faults are distributed as:</p>
+<ul><li>Safe Faults: 550</li>
+<li>Residual Faults in Area A: 122</i>
+<li>Multiple Point Faults in Area B: 1208</li>
+<li>Multiple Point Faults in Area C: 2582</li>
+</ul>
+<p>The best SPFM assumes the faults in Area B are propagatable to the diagnostic points. The single-point/residual faults <span style='font-size:18.0pt'>&Sigma;(</span><span style='font-size:18.0pt'>&lambda;</span>SPF+<span style='font-size:18.0pt'>&lambda;</span>RF<span style='font-size:18.0pt'>)</span> has number 122 only in Area A. Therefore, the best case SPFM is 97.3%.</p>
+<p>The worst SPFM assumes the faults in Area B are all residual faults, so <span style='font-size:18.0pt'>&Sigma;(</span><span style='font-size:18.0pt'>&lambda;</span>SPF+<span style='font-size:18.0pt'>&lambda;</span>RF<span style='font-size:18.0pt'>)</span> has number 1330 which is 1208 plus 122, and get calculated metric to be 70%.</p>
+<p>The best LFM assumes the faults in Area C are all detectable. <span style='font-size:18.0pt'>&Sigma;(</span><span style='font-size:18.0pt'>&lambda;</span>MPF_UD<span style='font-size:18.0pt'>)</span> is zero, So LFM is 100% in the rough structural COI analysis.</p>
+<p>The worst LFM assumes the faults in Area C can not propagate to the diagnostic points, and they are not detectable. Therefore, <span style='font-size:18.0pt'>&Sigma;(</span><span style='font-size:18.0pt'>&lambda;</span>MPF_UD<span style='font-size:18.0pt'>)</span> has the number of 2582, and the worst LFM is 59.5%.</p><div><img class='img-fluid' src='tp_image/fusa/fusa_coverage_numbers.png' /></div>
+<p><b>Figure 32: Example fault numbers in COI</b></p>

src_en/man.gformal_scriptspfmlfmcal.txt

@@ -0,0 +1,17 @@
+<h2>3.2 FUSA Example Code</h2>
+<h3>3.2.1 Script for SPFM and LFM Calculation</h3>
+<p>One example script for SPFM and LFM calculation:</p>
+<div class='gofscript'><pre>
+<a class='n' href='#___set_log_file'>set_log_file</a>(<span style='color:#63ac0a'>"spfm_lfm.log"</span>);     <span style='color:#b34c0a'># Set log file name</span>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);      <span style='color:#b34c0a'># Read in liberty file</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>'ecc_process.v'</span>); <span style='color:#b34c0a'># Read in the design block</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"ecc_top"</span>);               <span style='color:#b34c0a'># Set the top module name</span>
+<a class='n' href='#___create_clock'>create_clock</a>(<span style='color:#63ac0a'>"data_clk"</span>, 2);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"test_mode"</span>, 0); <span style='color:#b34c0a'># Set pin constraint</span>
+<a class='n' href='#___set_observe_points'>set_observe_points</a>(<span style='color:#63ac0a'>"data_out*"</span>);  <span style='color:#b34c0a'># data_out[31:0] affects functional safety</span>
+<a class='n' href='#___set_observe_points'>set_observe_points</a>(<span style='color:#63ac0a'>"synd_out"</span>);   <span style='color:#b34c0a'># synd_out affects functional safety</span>
+<a class='n' href='#___set_detect_points'>set_detect_points</a>(<span style='color:#63ac0a'>"sb_err_o"</span>);    <span style='color:#b34c0a'># Safety mechanism detecting output</span>
+<a class='n' href='#___set_detect_points'>set_detect_points</a>(<span style='color:#63ac0a'>"db_err_o"</span>);    <span style='color:#b34c0a'># Safety mechanism detecting output</span>
+<a class='n' href='#___verify_faults'>verify_faults</a>(<span style='color:#63ac0a'>"-full"</span>);           <span style='color:#b34c0a'># Calculate and print SPFM and LFM, Use verify_faults("-coi") for fast SPFM/LFM calculation </span>
+<a class='n' href='#___gexit'>gexit</a>;
+</pre></div>

src_en/man.gformal_singlepointfaultandlatentfault.txt

@@ -0,0 +1,2 @@
+<h3>3.1.1 Single Point Fault and Latent Fault</h3>
+<p>Single point fault (SPF) is the fault in the IC design that leads directly to the violation of a safety goal which is defined as observation point in the "Cone of Influence" section below and no fault in the IC circuit is covered by any safety mechanism. However, if there is safety mechanism, but the fault can't be covered by the safety mechanism, the fault is called residual fault according to the standard. In calculating SPFM, residual fault is treated as single point fault. Latent faults are multiple-point faults not detected by a safety mechanism or perceived by the driver. The latent fault metric is to determine whether coverage by safety mechanisms is sufficient to protect against risk from latent faults in the IC design.</p>

src_en/man.gformal_spfmlfmcal.txt

@@ -0,0 +1,18 @@
+<h3>3.1.4 SPFM and LFM Calculation</h3>
+<p>In Figure 31, all faults that are outside of the two COIs are safe faults.</p>
+<p>Area A has faults that are observable but not detectable, so they can be classified as residual faults. And they are called single point faults if safety mechanism is not implemented for the design, in which case the diagnostic points are not present and Area B and Area C are zero size. However, if they don't propagate to the observation points in the detail formal COI analysis, they can be classified as multiple point faults. For example, TMR is implemented on Area A. The majority faults in this area will become multiple point faults.</p>
+<p>Area B has faults that are classified as multiple point faults, since they are observable and detectable. In the rough structural COI analysis, the worst SPFM metric can be calculated by assuming them as all residual faults and the best SPFM metric by assuming them as propagatable to the diagnostic points. So the detail formal COI analysis will determined the fault classification.</p>
+<p>Area C has faults that are classified as detectable multiple point faults, but they are not observable. The detail formal COI analysis will be run on Area C to check if the faults in this area can not propagate to the diagnostic points, then they can be classified officially as latent faults. The best and worst LFM metrics can be gained by the rough structural COI analysis method.</p>
+<p>The Single Point Fault Metric (SPFM) can be calculated according to the following equation. </p>
+<p style='text-indent:2.0em;'>SPFM = 1 - <span style='font-size:18.0pt'>&Sigma;(</span><span style='font-size:18.0pt'>&lambda;</span>SPF+<span style='font-size:18.0pt'>&lambda;</span>RF<span style='font-size:18.0pt'>)</span><span style='font-size:18.0pt'>/</span><span style='font-size:18.0pt'>&Sigma;(</span><span style='font-size:18.0pt'>&lambda;</span><span style='font-size:18.0pt'>)</span> </p>
+<p style='text-indent:2.0em;'>where:</p>
+<p style='text-indent:3.0em;'><span style='font-size:18.0pt'>&lambda;</span>SPF: Single Point Fault when there is no safety mechanism</p>
+<p style='text-indent:3.0em;'><span style='font-size:18.0pt'>&lambda;</span>RF: Residual Fault</p>
+<p style='text-indent:3.0em;'><span style='font-size:18.0pt'>&lambda;</span>: Any Fault</p>
+<p>The Latent Fault Metric (LFM) can be calculated according to the following equation.</p>
+<p style='text-indent:2.0em;'>LFM = 1 - <span style='font-size:18.0pt'>&Sigma;(</span><span style='font-size:18.0pt'>&lambda;</span>MPF_UD<span style='font-size:18.0pt'>)</span><span style='font-size:18.0pt'>/</span><span style='font-size:18.0pt'>&Sigma;(</span><span style='font-size:18.0pt'>&lambda;</span>MPF - <span style='font-size:18.0pt'>&lambda;</span>SPF - <span style='font-size:18.0pt'>&lambda;</span>RF<span style='font-size:18.0pt'>)</span></p>
+<p style='text-indent:2.0em;'>where:</p>
+<p style='text-indent:3.0em;'><span style='font-size:18.0pt'>&lambda;</span>MPF_UD: Multiple Point Fault not detected by the driver</p>
+<p style='text-indent:3.0em;'><span style='font-size:18.0pt'>&lambda;</span>MPF: Any Multiple Point Fault</p>
+<p style='text-indent:3.0em;'><span style='font-size:18.0pt'>&lambda;</span>SPF: Single Point Fault when there is no safety mechanism</p>
+<p style='text-indent:3.0em;'><span style='font-size:18.0pt'>&lambda;</span>RF: Residual Fault</p>

src_en/man.gofdebug_guidetail.txt

@@ -0,0 +1,2 @@
+<h1>6 GOF Debug: Netlist Debug and Schematic</h1>
+<p>For all GUI mode operations and schematic usage, refer to this chapter.</p>

src_en/man.gofecguimode.txt

@@ -0,0 +1,4 @@
+<ul>
+  <li><big><strong>GUI mode ECO</strong></big></li>
+</ul>
+<p>GUI mode ECO has advantage of fast ramping up. It's good for small size ECOs. The incremental schematic feature is very helpful for analyzing the netlist before the next step is decided.</p>

src_en/man.gofechiereco.txt

@@ -0,0 +1,4 @@
+<ul>
+  <li><big><strong>Hierarchical ECO</strong></big></li>
+</ul>
+<p>GOF supports hierarchical ECO by set the ECO scope to the sub-modules. Some Logic Equivalence Check cases can only be resolved in flatten mode. Since GOF only focuses on the modules or spots that user specifies, it can avoid to get false non-equivalence in hierarchical netlist.</p>

src_en/man.gofecintegratedenv.txt

@@ -0,0 +1,4 @@
+<ul>
+  <li><big><strong>Integrated environment</strong></big></li>
+</ul>
+<p>The ECO modes listed above are integrated into one work environment seamlessly. The mixing of ECO modes can produce most optimal ECO result. For example, automatic ECO and manual script ECO can be done in one ECO script, so that the minimum size ECO patch can be achieved.</p>

src_en/man.gofecmetalonly.txt

@@ -0,0 +1,4 @@
+<ul>
+  <li><big><strong>Metal Only ECO</strong></big></li>
+</ul>
+<p>When ECO is done in either automatic mode or manual mode, 'map_spare_cells' command is run to convert the newly added cells to spare gate types cells. Users can control only spare gate type cells being used in manual mode ECO, so that the converting stage can be bypassed. The flow supports both standard spare cells and gate array spare cells.</p>

src_en/man.gofecoautomode.txt

@@ -0,0 +1,5 @@
+<p></p>
+<ul>
+<li><big><strong>Automatic mode ECO</strong></big></li>
+</ul>
+<p>The automatic functional ECO is carried out using a GOF ECO script, which requires an Implementation Netlist that is currently under ECO and a Reference Netlist that is re-synthesized from the modified RTL with the same constraints as the pre-layout netlist. The 'fix_design' API is utilized to execute a top-down global ECO. GOF leverages its built-in Logic Equivalence Check engine to identify and analyze non-equivalent points in both the top-level module and its sub-modules. Logic patches are generated to rectify any non-equivalent modules, and the final patches are optimized circuits that minimize the gate count required to make the Implementation Netlist equivalent to the Reference Netlist. Finally, the 'map_spare_cells' API is used to map these patches to spare-type-gates.</p>

src_en/man.gofecofeatures.txt

@@ -0,0 +1,13 @@
+<h2>2.1 Netlist ECO Solutions</h2>
+<p>GOF ECO incorporates the following features:</p>
+<ul>  <li>Automatic functional ECO uses the Reference Netlist to fix the Implementation Netlist</li>
+  <li>RTL-guided automatic functional ECO produces quicker and more targeted ECO results</li>
+  <li>RTL patch ECO can speed up the turnaround time by avoiding full-scale and lengthy synthesis processes</li>
+  <li>Built-in logic equivalence check engine makes the ECO self contained</li>
+  <li>Parallel processing fully utilizes multiple CPU cores to reduce ECO run time</li>
+  <li>Standard spare cells in Metal only ECO remaps only spare gates in post-mask ECO</li>
+  <li>Metal Configurable Gate Array Spare Cells makes larger Metal Only ECO possible</li>
+  <li>Auto mode ECO mixed with GUI and Script mode ECO optimizes ECO patches to the full extent</li>
+  <li>ECO retargeting achieves huge netlist ECO in short period of time</li>
+  <li>DFT friendly maintains test logic untouched to avoid second time ECO in late design stage</li>
+</ul>

src_en/man.gofecomanmode.txt

@@ -0,0 +1,4 @@
+<ul>
+  <li><big><strong>Manual mode ECO</strong></big></li>
+</ul>
+<p>If the ECO changes are limited in scope and size or involve repetitive operations such as adding inverts on a bus, it is more efficient to use the manual mode ECO. This mode is a better option as it results in fewer final gates being touched compared to automatic mode ECO. Additionally, both automatic and manual modes can be combined and executed within a single GOF ECO script.</p>

src_en/man.gofecovariousmethods.txt

@@ -0,0 +1,10 @@
+<p></p>
+<p>GOF ECO utilizes various advanced ECO methodologies, as netlist ECO can vary significantly in terms of size and complexity across different cases and companies. To provide users with maximum flexibility, GOF offers a range of methodologies to choose from, allowing them to select one or multiple options based on the specific requirements of the changes involved.</p>
+<div><img class='img-fluid' src='tp_image/gofdoc/COMPLETE_ECO_SOLUTIONS.png' /></div>
+<p><b>Figure 1: Complete Functional ECO Solutions</b></p>
+<ul>
+  <li>Automatic ECO and Manual ECO</li>
+  <li>RTL to Netlist and Netlist to Netlist</li>
+  <li>Script Mode and GUI Mode</li>
+  <li>Metal Only ECO and All Layers ECO</li>
+</ul>

src_en/man.goflec_net2netlec.txt

@@ -0,0 +1,24 @@
+<h2>5.1 GOF LEC Overview</h2>
+<p>The GOF platform features a logic equivalence checker tool called GOF LEC. While not mandatory, the tool can benefit from SVF files in certain cases. It is strongly advised to utilize SVF files if they are obtainable. The two designs being compared can either be in RTL or Netlist format, with RTL supporting SystemVerilog2017. The read design method differs depending on whether RTL or Netlist is being supported.</p>
+<div><img class='img-fluid' src='/tp_image/GOF_LEC.png' /></div>
+<p><b>Figure 38: GOF LEC Engine</b></p>
+<h3>5.1.1 Netlist to Netlist LEC</h3>
+<p>The following is the example script for Netlist to Netlist LEC:</p>
+<div class='gofscript'><pre><span style='color:#b34c0a'># LEC script, run_net2net_lec.pl</span>
+use strict;
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>); <span style='color:#b34c0a'># Read in standard library</span>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>'-ref'</span>, <span style='color:#63ac0a'>'AI2023_top_syn.svf.txt'</span>); <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>'AI2023_top_pr.svf.txt'</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-ref'</span>, <span style='color:#63ac0a'>'AI2023_top_syn.v'</span>); <span style='color:#b34c0a'># Read in the Reference Netlist, prelayout netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>'AI2023_top_pr.v'</span>); <span style='color:#b34c0a'># Read in the Implementation Netlist, postlayout netlist</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"AI2021_top"</span>); <span style='color:#b34c0a'># Set the top module</span>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);
+my $non_equal = <a class='n' href='#___run_lec'>run_lec</a>; <span style='color:#b34c0a'># Run logic equivalence check on the two netlists</span>
+if($non_equal){
+  <a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"LEC failed with $non_equal non-equivalent points"</span>);
+}else{
+  <a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"LEC passed"</span>);
+}
+</pre></div>

src_en/man.goflec_rtl2netlec.txt

@@ -0,0 +1,23 @@
+<h3>5.1.2 RTL to Netlist LEC</h3>
+<p>The following is the example script for RTL to Netlist LEC:</p>
+<div class='gofscript'><pre><span style='color:#b34c0a'># LEC script, run_rtl2net_lec.pl</span>
+use strict;
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>); <span style='color:#b34c0a'># Read in standard library</span>
+<a class='n' href='#___set_inc_dirs'>set_inc_dirs</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"inc_dir_path/include"</span>);
+<a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"NO_SIMULATION"</span>, 1);
+my @rtl_files = (<span style='color:#63ac0a'>"cpu_core.sv"</span>, <span style='color:#63ac0a'>"mem_ctrl.sv"</span>, <span style='color:#63ac0a'>"display_sys.sv"</span>, <span style='color:#63ac0a'>"chip_top.sv"</span>);
+<a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>"-ref"</span>, @rtl_files); <span style='color:#b34c0a'># Read in the Reference RTL files</span>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>'chip_top.svf.txt'</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>'chip_top.v'</span>); <span style='color:#b34c0a'># Read in the Synthesis Netlist</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"CHIP_TOP"</span>); <span style='color:#b34c0a'># Set the top module</span>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);
+<a class='n' href='#___elab_rtl'>elab_rtl</a>(); <span style='color:#b34c0a'># RTL processing</span>
+my $non_equal = <a class='n' href='#___run_lec'>run_lec</a>; <span style='color:#b34c0a'># Run logic equivalence checking on RTL vs Netlist</span>
+if($non_equal){
+  <a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"LEC failed with $non_equal non-equivalent points"</span>);
+}else{
+  <a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"LEC passed"</span>);
+}
+</pre></div>

src_en/man.gsc_automaticecoapis.txt

@@ -0,0 +1,14 @@
+<h4>4.1.4.2 Automatic ECO APIs</h4>
+<p>These APIs are for Automatic ECO</p>
+<div class='gofscript'>
+<a class='n' href='#___fix_design'>fix_design</a>: ECO command to fix the design in automatic ECO (LLM: automatic eco)<br>
+<a class='n' href='#___fix_logic'>fix_logic</a>: ECO command. Fix listed points<br>
+<a class='n' href='#___map_spare_cells'>map_spare_cells</a>: ECO command. Map all new created cells to spare cells (LLM: metal only)<br>
+</div>
+<p>Combining netlist browsing APIs, users can come up a short script to do complicated changes.</p>
+<p>For example, to fix all modules named "tx_machine_*"</p>
+<div class='gofscript'>
+my @modules = <a class='n' href='#___get_modules'>get_modules</a>(<span style='color:#63ac0a'>"-hier"</span>, <span style='color:#63ac0a'>"tx_machine_*"</span>);</br>
+fix_modules(@modules);</br>
+
+</div>

src_en/man.gsc_bexampletosch.txt

@@ -0,0 +1,7 @@
+<h3>4.3.6 Counter-example back-annotated to schematic</h3>
+<p>In GOF shell 'GOF > sch the_non_equivalent_point -both', so that both instances/ports in the Implementation and Reference Netlists are loaded into a schematic. Select both of them, right the mouse and select 'LEC Debug the_non_equivalent_point'. After the run finishes, use mouse middle button to expand the schematic, and the counter-example values are back-annotated on the schematic.</p>
+<div><img class='img-fluid' src='tp_image/debug/run_lec_debug.PNG' /></div>
+<p><b>Figure 36: Debug non-equivalence by counter-example back-annotated</b></p>
+<p>Two corresponding flops, two corresponding output ports, and any two nets in the Reference Netlist and the Implementation Netlist can be compared in debug mode. In cases where the outcome is non-equivalent, the counterexample will be presented to the gate pins on the schematic.</p>
+<div><img class='img-fluid' src='tp_image/debug/trace_one_for_noneq.png' /></div>
+<p><b>Figure 37: Counter-example back-annotated on the schematic</b></p>

src_en/man.gsc_breakfordebug.txt

@@ -0,0 +1,24 @@
+<h3>4.3.5 Break points for debug</h3>
+<p>'sch' fast schematic launch command can be used as break points for debug. For example, 'sch' commands are inserted in GOF script, when the tool runs to the point, a schematic is launched.</p>
+<div class='gofscript'>
+&hellip;</br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_3821"</span>);</br>
+<a class='n' href='#___set_log_file'>set_log_file</a>(<span style='color:#63ac0a'>"t_eco_3821.log"</span>);</br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.m.simple.lib"</span>);</br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"./cdir/imp_name.v"</span>);</br>
+<a class='n' href='#___change_pin'>change_pin</a>(<span style='color:#63ac0a'>"state_reg_0_/D"</span>, <span style='color:#63ac0a'>"MX2X4"</span>, <span style='color:#63ac0a'>"eco_inst_1"</span>, <span style='color:#63ac0a'>".A(-),.B(next_state[7]),.S0(sel_mode)"</span>);</br>
+<a class='n' href='#___sch'>sch</a>(<span style='color:#63ac0a'>"state_reg_0_"</span>);</br>
+&hellip;</br>
+
+</div>
+<p>&nbsp;</p>
+<p>On the schematic, user can use mouse-middle-button clicking on the pin 'D' to see if the ECO is done as expected.</p>
+<p>&nbsp;</p>
+<p><img class='img-fluid' src='/gof_manual_files/image016.gif' style='border:none; height:405px; width:578px' /></p>
+<p>&nbsp;</p>
+<p><b>Figure 34: Launch schematic at break point</b></p>
+<p>Note: 'ECO' check-button is enabled automatically, since there is ECO having been done.</p>
+<p>To compare with the logic before ECO, launch a new schematic by menu Schematic-&gt;'New Schematic'. On the new schematic, press 'ctrl-g' or by menu Schematic-&gt;'Load Gate' to load in the flop under ECO.</p>
+<p><img class='img-fluid' src='/gof_manual_files/image017.gif' style='border:none; height:400px; width:574px' /></p>
+<p><b>Figure 35: Launch schematic before ECO</b></p>
+<p>Note: 'ECO' check-button is un-checked.</p>