Upload 39 files

src_en/api.source.txt

@@ -0,0 +1,11 @@
+<h3 id='___source'>source</h3>
+<pre>Run Netlist processing script. 
+<b>Usage:</b> source($script_name);
+
+<b>Examples:</b>
+
+source("eco2.pl");
+
+<b>Note:</b>
+It has the same behavior as 'run' command
+</pre>

src_en/api.start_gui.txt

@@ -0,0 +1,7 @@
+<h3 id='___start_gui'>start_gui</h3>
+<pre>Start GUI windows
+<b>Usage:</b> start_gui(@options);
+@options:
+   -source: Read in Reference RTL file if it exists
+   -noblock: The process is not blocked by start_gui, by default the process is blocked by the GUI window
+</pre>

src_en/api.stitch_scan_chain.txt

@@ -0,0 +1,12 @@
+<h3 id='___stitch_scan_chain'>stitch_scan_chain</h3>
+<pre>ECO command. Stitch scan chain
+<b>Usage:</b> stitch_scan_chain(@options);
+@options:
+   -to $flop_inst: Stitch all new flops into the flop_inst or stitch each module's new flops into one flop in this module 
+<b>Note:</b> If -to option doesn't exist, the new flops in each module are connected up in one chain and stitched into one existing scan flop 
+  
+<b>Examples:</b>
+
+stitch_scan_chain("-to", "abc_reg"); # Insert new flops' scan chain into the existing flop 'abc_reg'
+stitch_scan_chain();                 # Stitch the new flops into local scan chains
+</pre>

src_en/api.suppress_errors.txt

@@ -0,0 +1,5 @@
+<h3 id='___suppress_errors'>suppress_errors</h3>
+<pre>Suppress error messages
+<b>Usage:</b> suppress_errors(@messages)
+@messages: Error messages. 'E-001', 'E-132'
+</pre>

src_en/api.suppress_warnings.txt

@@ -0,0 +1,8 @@
+<h3 id='___suppress_warnings'>suppress_warnings</h3>
+<pre>Suppress warning messages
+<b>Usage:</b> suppress_warnings(@messages)
+@messages: Warning messages. 'W-001', 'W-002'
+
+<b>Examples:</b>
+   suppress_warnings("W-001", "W-002", "W-003"); # Suppress these three warnings
+</pre>

src_en/api.swap_inst.txt

@@ -0,0 +1,10 @@
+<h3 id='___swap_inst'>swap_inst</h3>
+<pre>ECO command. Swap two instances with same input/output pins.
+<b>Usage:</b> swap_inst($inst1, $inst2);
+$inst1,$inst2: Swap these two instances.
+<b>Note:</b> $inst1 and $inst2 should have the same input/output pins.
+
+<b>Examples:</b>
+
+swap_inst("spare1/spr_and0", "spare2/spr_and1");
+</pre>

src_en/api.undo_eco.txt

@@ -0,0 +1,4 @@
+<h3 id='___undo_eco'>undo_eco</h3>
+<pre>ECO command. Undo eco operations, restore the database to the original state.
+<b>Usage:</b> undo_eco();
+</pre>

src_en/api.verify_faults.txt

@@ -0,0 +1,20 @@
+<h3 id='___verify_faults'>verify_faults</h3>
+<pre>GOF Formal only. Verify fault in stuck-0 or stuck-1 mode
+<b>Usage:</b> my $status = verify_faults($one_fault, @options);
+$one_fault: Optional, to test one fault only 
+@options:
+   -help: Print this info
+   -rough: Calculate SPFM/LFM only by structural COI analysis
+   -full: Run full formal process in calculating SPFM/LFM
+   -vcd vcd_file_name: Dump the sequence to the VCD file when $one_fault is defined
+$status: Return 1 if a sequence exists
+
+<b>Examples:</b>
+
+#1. Check all fault in the whole design
+verify_faults("-full");
+
+#2. Check one fault stuck-0 and dump the sequence to the VCD file
+verify_faults("u_master/U12/Y:0", "-vcd", "seq_u12.vcd");
+
+</pre>

src_en/api.verify_state.txt

@@ -0,0 +1,16 @@
+<h3 id='___verify_state'>verify_state</h3>
+<pre>GOF Formal only. Verify if a sequence exists to set the signal
+<b>Usage:</b> my $status = verify_state(@sig_seq, @options);
+@sig_seq: Signals and its value 
+@options:
+   -help: Print this info
+   -or:  The signals are 'or' relationship, default 'and' relationship
+   -vcd vcd_file_name: Dump the sequence to the VCD file when $one_fault is defined
+$status: Return 1 if a sequence exists
+
+<b>Examples:</b>
+
+#1. Check one instance input A can be set to 0, dump to VCD file dump_seq.vcd 
+verify_state("u_spi/U10/A:0", "-vcd", "dump_seq.vcd");
+
+</pre>

src_en/api.write_compare_points.txt

@@ -0,0 +1,13 @@
+<h3 id='___write_compare_points'>write_compare_points</h3>
+<pre>Write all compare points to a report file
+<b>Usage:</b> write_compare_points($file_name, @options);
+$file_name: The report file name
+@options:
+    -all:  Include name matching instances
+
+<b>Examples:</b>
+
+write_Compare_points("compare_points.rep"); # Write compare points with different naming
+write_Compare_points("-all", "all_compare_points.rep"); # Write all compare points
+
+</pre>

src_en/api.write_dcsh.txt

@@ -0,0 +1,9 @@
+<h3 id='___write_dcsh'>write_dcsh</h3>
+<pre>ECO command. Write ECO result in Design Compiler dcsh script format
+<b>Usage:</b> write_dcsh($dc_script_name);
+$dc_script_name: Synopsys Design Compiler dcsh script name.
+
+<b>Examples:</b>
+
+write_dcsh("eco12345.dcsh");
+</pre>

src_en/api.write_formality_help_files.txt

@@ -0,0 +1,13 @@
+<h3 id='___write_formality_help_files'>write_formality_help_files</h3>
+<pre>Write formality help files including mapped instance list and modified netlist files if necessary
+<b>Usage:</b> write_formality_help_files($help_name);
+$help_name: Help name which can have directory specified
+
+<b>Note:</b> 
+
+<b>Examples:</b>
+
+#1. Write out Formality help files into directory fm_help with the base name eco_1225
+write_formality_help_files("fm_help/eco_1225"); 
+ 
+</pre>

src_en/api.write_perl.txt

@@ -0,0 +1,6 @@
+<h3 id='___write_perl'>write_perl</h3>
+<pre>ECO command to write ECO result in Perl script (LLM: result in perl)
+<b>Usage:</b> write_perl($eco_script_name);
+$eco_script_name: ECO script name
+<b>Note:</b> The command can be used after 'fix_design' API. Detail ECO operations are written out.
+</pre>

src_en/api.write_soce.txt

@@ -0,0 +1,11 @@
+<h3 id='___write_soce'>write_soce</h3>
+<pre>ECO command. Write ECO result in Cadence SOC Encounter script format
+<b>Usage:</b> write_soce($soc_encounter_script_name, @options);
+$soc_encounter_script_name: Cadence SOC Encounter script name.
+@options:
+    -type1: Alternate SOC Encounter script type
+
+<b>Examples:</b>
+
+write_soce("eco12345.soce");
+</pre>

src_en/api.write_spare_file.txt

@@ -0,0 +1,7 @@
+<h3 id='___write_spare_file'>write_spare_file</h3>
+<pre>ECO command. Write spare cells list to a file
+<b>Usage:</b> write_spare_file($filename);
+$filename: Spare cells file name to be written out
+
+<b>Note:</b> Any used spare cell has '#' in the start of the line
+</pre>

src_en/api.write_tcl.txt

@@ -0,0 +1,9 @@
+<h3 id='___write_tcl'>write_tcl</h3>
+<pre>ECO command to write ECO result in Design Compiler tcl script format (LLM: result in tcl)
+<b>Usage:</b> write_tcl($tcl_script_name);
+$tcl_script_name: Synopsys Design Compiler tcl script name.
+
+<b>Examples:</b>
+
+write_tcl("eco12345.tcl");
+</pre>

src_en/api.write_verilog.txt

@@ -0,0 +1,31 @@
+<h3 id='___write_verilog'>write_verilog</h3>
+<pre>ECO command to write ECO result in Verilog netlist (LLM: result in verilog)
+<b>Usage:</b> write_verilog($verilog_file, @options);
+@options:
+    -help: Print this information
+    -all:  Keep the modules in the netlist file even they are not the sub-modules of the top module
+$verilog_file: The Verilog netlist file name, should be different from the existing Implementation Netlist file name.
+
+<b>Note:</b> When the Implementation design is read in by multiple netlist files, set_top command should be used to 
+      make the correct file saved
+      
+<b>Examples:</b> 
+
+#1. Write out ECOed netlist to imp_eco.v
+read_design("-ref", "reference.v");
+read_design("-imp", "implementation.v");
+fix_design;
+write_verilog("imp_eco.v");
+
+#2. The design is read in by command line 'gof -lib tsmc.lib ethernet_top.v'
+#   After ECO, to write ECO netlist use command 
+write_verilog("ethernet_top_eco.v");
+
+#3. The design is read in by multiple netlist files in command line, 
+#   'gof -lib tsmc.lib mem_control.v dsp.v ethernet_top.v'
+#   The ECO is done on 'mem_control' module, to save the netlist
+set_top("mem_control");
+write_verilog("mem_control_eco.v");
+
+ 
+</pre>

src_en/man.geco_addmewmodule.txt

@@ -0,0 +1,27 @@
+<h3>2.2.15 Add a new module</h3>
+<p>The module mentioned in the section above can have hierarchy kept instead of flatten, and being written into ECO netlist as whole. This flow needs the module and its sub-modules written out in a separate verilog file, then uses read_library to load the file with '-vmacro' option. GOF treats the module as a leaf cell.</p>
+<p>An example for adding a new module:</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># GOF ECO script, run_new_module_example.pl</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;<span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_hier_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span></br>
+<span style='background-color:yellow'><a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"-vmicro"</span>, <span style='color:#63ac0a'>"syn_macro.v"</span>); <span style='color:#b34c0a'># The syn_macro module is added into the netlist</span></span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in the Reference Netlist</span></br>
+<span style='color:#b34c0a'># Read in the implementation netlist which is under ECO</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);</br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>'top'</span>);<span style='color:#b34c0a'># Set the top module</span></br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);  </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0); </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0); </br>
+<a class='n' href='#___fix_design'>fix_design</a>;</br>
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span></br>
+<a class='n' href='#___report_eco'>report_eco</a>();<span style='color:#b34c0a'># ECO report</span></br>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span></br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+
+</div>
+<p>The content in file syn_macro.v is&nbsp;written into the ECO file eco_verilo.v as a whole. The corresponding instance is&nbsp;created as well with ports connected correctly according to Reference Netlist.</p>

src_en/man.geco_autoecoscript.txt

@@ -0,0 +1,28 @@
+<h3>2.2.3 Automatic Functional ECO example script</h3>
+<p>The ECO script employs the exact syntax of a Perl script. It executes exported APIs that interact with the netlist database, facilitating modifications to the netlist.</p>
+<p>The following is the example script for automatic functional ECO:</p>
+<div class='gofscript'><pre><span style='color:#b34c0a'># GOF ECO script, run_example.pl</span>
+use strict;
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
+<span style='color:#b34c0a'># SVF files are optional, best to be used when the design involves multibit flops</span>
+<span style='color:#b34c0a'>#read_svf("-ref", "reference.svf.txt");       # Optional, must be loaded before read_design, must be in text format</span>
+<span style='color:#b34c0a'>#read_svf("-imp", "implementation.svf.txt");  # Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module</span>
+<span style='color:#b34c0a'># Preserve DFT Test Logic</span>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);
+<a class='n' href='#___fix_design'>fix_design</a>();
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span>
+<a class='n' href='#___run_lec'>run_lec</a>(); <span style='color:#b34c0a'># Run GOF LEC to generate Formality help files</span>
+<a class='n' href='#___write_compare_points'>write_compare_points</a>(<span style='color:#63ac0a'>"compare_points.report"</span>);
+<a class='n' href='#___write_formality_help_files'>write_formality_help_files</a>(<span style='color:#63ac0a'>"fm_dir/formality_help"</span>); <span style='color:#b34c0a'># formality_help files are generated in fm_dir folder</span>
+<span style='color:#b34c0a'># fm_dir/formality_help.config.tcl can be used in Formality script to pass logic equivalence checking</span>
+exit; <span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears</span>
+</pre></div>

src_en/man.geco_autofullfuneco.txt

@@ -0,0 +1,11 @@
+<h2>2.2 Automatic Full-Layers Functional ECO Flow</h2>
+<p>The Full Layers Functional ECO allows for the addition or removal of gates in a flexible manner. The ECO operations are performed using a script in Perl syntax, which accesses, modifies, and saves the netlist database using exported APIs. GOF ECO reads in two netlist files: the Implementation Netlist (which is under ECO) and the Reference Netlist (which is re-synthesized from modified RTL with the same constraints as the pre-layout netlist). In the ECO script, the 'fix_design' API is used to fix the top-level module and its sub-modules in global mode. GOF utilizes its built-in Logic Equivalent Check Engine to identify non-equivalent points and applies optimized minimum size gate patches to fix the non-equivalent modules.</p>
+<p>Figure 2 shows that two logic cones are extracted from the Implementation and Reference Netlist for the same comparison point. Initially, the implementation point does not match the reference point. GOF compares the two points and generates a patch from the Reference logic cone, which it applies to the Implementation Netlist. After patching, the two points become equivalent.</p>
+<p></p>
+<p></p>
+<div><img class='img-fluid' src='/gof_manual_files/image001.gif'/></div>
+<p><b>Figure 2: Logic Cone Optimization</b></p>
+<p>GOF performs logic cone analysis and optimization for each failing point discovered during top-down logic equivalence checks. The failing point takes the form of an output port or input pin of a sequential element, such as a flip-flop's D input. The final patch contains the fewest number of gates required to ensure that the implementation logic cone matches the reference logic cone.</p>
+<p>Figure 3 depicts the flow chart of the process.</p>
+<div><img class='img-fluid' src='/tp_image/autoeco_flow.png' style='border:none;' /></div>
+<p><b>Figure 3: Automatic functional ECO flow</b></p>

src_en/man.geco_checkdesignaftereco.txt

@@ -0,0 +1,6 @@
+<h3>2.2.18 Check design after ECO</h3>
+<p>It is highly recommended to run 'check_design' after ECO, to speed up, users can specify '-eco' option,</p>
+<div class='gofscript'>
+<a class='n' href='#___check_design'>check_design</a>('-eco')
+</div>
+<p>It can detect if there is any floating or multiple drivers after ECO.</p>

src_en/man.geco_debugnoneqinlargeeco.txt

@@ -0,0 +1,2 @@
+<h3>2.2.17 Debug non-equivalence in large ECO</h3>
+<p>It happens that an ECO doesn't pass logic equivalence checker, especially for a large ECO. GOF can run individual logic equivalence checking for flop pairs, output port pairs or any two nets. Check  <a href='gof_manual.php#-counterexample-backannotated-to-schematic'>annotating to schematic</a> for more detail.</p>

src_en/man.geco_dftconstraints.txt

@@ -0,0 +1,78 @@
+<h3>2.2.9 DFT Constraints</h3>
+<p>To prevent false non-equivalence in LEC and ECO, constraints must be placed on the DFT logic. In the traditional DFT flow, the DFT logic is typically incorporated into the RTL design, which appears in both the Reference Netlist and the Implementation Netlist. In contrast, the modern DFT flow, which supports IEEE1687 and IEEE1500 standards, inserts the DFT logic into the Implementation Netlist using a DFT tool like Mentor Tessent. To ensure that the Implementation Netlist, which contains DFT logic inserted by the DFT tool, matches the Reference Netlist, which lacks DFT logic, a Logic Equivalence Check must be performed. To prevent redundant or false ECO fixes, the DFT logic must be correctly constrained in the automatic functional ECO process.</p><p>In the traditional DFT flow, as illustrated in the left side of Figure 7, constraints are placed on the ports. For instance, DFT control signals such as TEST_EN are set to zero, while the normal functional ports are left unconstrained.</p><div class='gofscript'>
+<span style='color:#b34c0a'># Set DFT Constraints</span></br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"TEST_EN"</span>, 0); </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0); </br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);  </br>
+
+</div>
+<div><img class='img-fluid' src='./tp_image/gofdoc/dft_constrain_lec.png' style='width:800px' /></div>
+<p><b>Figure 7: DFT Constraints in Automatic Functional ECO</b></p>
+<p>In the modern DFT flow, these inserted DFT logic by the DFT tool as shown in the right side of Figure 7 should be constrained to be in inactive state. The control signals driven by TDR registers should be constrained to zeros.</p>
+<p>GOF provides several APIs to constrain the DFT logic, set_ignore_output, set_pin_constant and set_net_constant. The API set_net_constant can be used to constrain the TDR registers signals. Since TDR registers are not ports, so they have be treated as nets.</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># Set DFT Constraints for the modern DFT flow</span></br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"TEST_EN"</span>, 0); </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0); </br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);  </br>
+<span style='background-color:yellow'><a class='n' href='#___set_net_constant'>set_net_constant</a>(<span style='color:#63ac0a'>"TDR_SEL0"</span>, 0, <span style='color:#63ac0a'>"-imp"</span>); <span style='color:#b34c0a'># TDR register net only exists in Implementation Netlist</span></span></br>
+<a class='n' href='#___set_net_constant'>set_net_constant</a>(<span style='color:#63ac0a'>"TDR_SEL1"</span>, 0, <span style='color:#63ac0a'>"-imp"</span>); </br>
+<a class='n' href='#___set_net_constant'>set_net_constant</a>(<span style='color:#63ac0a'>"all_test"</span>, 0, <span style='color:#63ac0a'>"-imp"</span>); </br>
+<span style='color:#b34c0a'># For memories that have pins directly controlled by TDRs</span></br>
+<a class='n' href='#___set_ignore_pin'>set_ignore_pin</a>(<span style='color:#63ac0a'>"TSMC_MEM_256X29/TCEN*"</span>);</br>
+
+</div>
+<p></p>
+<p>The full script with constraints on the traditional DFT flow is shown below:</p><div class='gofscript'>
+<span style='color:#b34c0a'># GOF ECO script, run_example_exclude_test_logic.pl</span></br>
+<span style='color:#b34c0a'># The SOC_TOP design should have scan insertion test logic excluded in ECO. </span></br>
+<span style='color:#b34c0a'># The scan out bus pin has naming of scan_out[199:0] and API set_ignore_output can be used to exclude LEC check on scan_out in ECO.</span></br>
+<span style='color:#b34c0a'># And TEST_EN and scan_mode are two scan set up signals which can be forced to zeros by API set_pin_constant.</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;<span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span></br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SOC_TOP"</span>); <span style='color:#b34c0a'># Set the top to&nbsp;the most top module SOC_TOP</span></br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);  </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"TEST_EN"</span>, 0); </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0); </br>
+<a class='n' href='#___fix_design'>fix_design</a>;</br>
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span></br>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span></br>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span></br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+exit;<span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears</span></br>
+
+</div>
+<p></p>
+<p>The full script with constraints on the modern DFT flow is shown below: </p><div class='gofscript'>
+<span style='color:#b34c0a'># GOF ECO script, dft_constraints_on_inserted_test_logic.pl</span></br>
+<span style='color:#b34c0a'># set_net_constant is used to constrain TDR register nets to zeros</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>;<span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span></br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SOC_TOP"</span>); <span style='color:#b34c0a'># Set the top to&nbsp;the most top module SOC_TOP</span></br>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);  </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"TEST_EN"</span>, 0); </br>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0); </br>
+<span style='background-color:yellow'><a class='n' href='#___set_net_constant'>set_net_constant</a>(<span style='color:#63ac0a'>"TDR_SEL0"</span>, 0, <span style='color:#63ac0a'>"-imp"</span>); <span style='color:#b34c0a'># TDR register net only exists in Implementation Netlist</span></span></br>
+<a class='n' href='#___set_net_constant'>set_net_constant</a>(<span style='color:#63ac0a'>"TDR_SEL1"</span>, 0, <span style='color:#63ac0a'>"-imp"</span>); </br>
+<a class='n' href='#___set_net_constant'>set_net_constant</a>(<span style='color:#63ac0a'>"all_test"</span>, 0, <span style='color:#63ac0a'>"-imp"</span>); </br>
+<a class='n' href='#___fix_design'>fix_design</a>;</br>
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span></br>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span></br>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span></br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+exit;<span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears</span></br>
+
+</div>
+<p></p>

src_en/man.geco_dftdrc.txt

@@ -0,0 +1,58 @@
+<h3>2.2.10 DFT Design Rule Checker</h3>
+<p>It's common for DFT logic to be broken during functional ECO processes, which involve modifying a design for functional reasons after it has already been verified. Since DFT control signals are disabled during functional ECO, the ECO tool is not aware that DFT logic has been modified and cannot verify its functionality. When the modified netlist is ready to be tested using DFT tool, it can take a long time to identify issues. GOF provides a fast DFT Design Rule Checker that can quickly identify issues with DFT logic. A fundamental design rule for DFT is to ensure that the scan chain is complete, meaning that it can be used to capture and output test patterns during testing. Additionally, clock and reset signals should be controllable during test mode to enable proper test pattern application.</p>
+<div><img class='img-fluid' src='tp_image/dft/dft_drc.png' /></div>
+<p><b>Figure 8: DFT Design Rule Checker</b></p>
+<p>The script to do DFT Design Rule Check:</p>
+<div class='gofscript'><pre>
+<a class='n' href='#___set_log_file'>set_log_file</a>(<span style='color:#63ac0a'>"dft_drc.log"</span>);      <span style='color:#b34c0a'># Set log file name</span>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);      <span style='color:#b34c0a'># Read in liberty file</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>'dft_top.v'</span>); <span style='color:#b34c0a'># Read in the design with DFT implemented</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"DFT_TOP"</span>);               <span style='color:#b34c0a'># Set the top module name</span>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"test_scan_shift"</span>, 1); <span style='color:#b34c0a'># Set scan shift pin to 1</span>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"all_test_reg/Q"</span>, 1);  <span style='color:#b34c0a'># Set TDR all_test register Q to 1</span>
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"test_mode_reg/Q"</span>, 1);  <span style='color:#b34c0a'># Set TDR test_mode register Q to 1</span>
+<a class='n' href='#___create_clock'>create_clock</a>(<span style='color:#63ac0a'>"occ_add_1_inst/U0/Z"</span>, 10); <span style='color:#b34c0a'># Set clock on OCC drivers, maybe multiple</span>
+<a class='n' href='#___create_clock'>create_clock</a>(<span style='color:#63ac0a'>"occ_add_2_inst/U0/Z"</span>, 10); <span style='color:#b34c0a'># Set clock on OCC drivers, maybe multiple</span>
+<a class='n' href='#___create_reset'>create_reset</a>(<span style='color:#63ac0a'>"power_on_reset"</span>, 0);       <span style='color:#b34c0a'># Set reset pin</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"DESIGN_TOP"</span>);                   <span style='color:#b34c0a'># pin_si/pin_so is internal pins of DFT_TOP</span>
+<a class='n' href='#___set_scan_pairs'>set_scan_pairs</a>(<span style='color:#63ac0a'>"pin_si[0]"</span>, <span style='color:#63ac0a'>"pin_so[0]"</span>); <span style='color:#b34c0a'># Add scan chain pair 0</span>
+<a class='n' href='#___set_scan_pairs'>set_scan_pairs</a>(<span style='color:#63ac0a'>"pin_si[1]"</span>, <span style='color:#63ac0a'>"pin_so[1]"</span>); <span style='color:#b34c0a'># Add scan chain pair 1</span>
+<span style='color:#b34c0a'># More scan chain can be added. These codes can be handled by a for loop command</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"DFT_TOP"</span>); 
+my $err = <a class='n' href='#___dft_drc'>dft_drc</a>;
+if($err){
+  <a class='n' href='#___gprint'>gprint</a>(<span style='color:#63ac0a'>"DFT DRC found $err errors\n"</span>);
+}
+</pre></div>
+<p>The Design Rule Checker can catch these issues by error codes:</p>
+<ul>
+<li>ERROR_CLOSE_LOOP: A flop driving its own SI by Q pin</li>
+<li>ERROR_CLOCK: A flop having clock that cannot be controllable in DFT mode</li>
+<li>ERROR_CLOCK_UNDEFINED: A flop driven by a clock not defined as DFT clock</li>
+<li>ERROR_MULTI_PATHS: Scan chain having multiple paths</li>
+<li>ERROR_SE_NOT_ASSERT: A flop having shift enable pin not asserted</li>
+<li>ERROR_RESET_GLITCH: A flop having reset pin with multiple active paths which may cause glitch</li>
+<li>ERROR_RESET: A flop having reset pin not controllable in DFT mode</li>
+<li>ERROR_SET_GLITCH: A flop having set pin with multiple active paths which may cause glitch</li>
+<li>ERROR_SET: A flop having set pin not controllable in DFT mode</li>
+<li>ERROR_END_CONST: A scan chain ending with constant</li>
+<li>ERROR_END_AT_INST: A scan chain ending with a non-flop, nor EDT logic </li>
+</ul>
+<p>For instance, DFT DRC catches ERROR_MULTI_PATHS error in a functional ECO when an NAND gate is inserted between back-to-back flops.</p>
+<div><img class='img-fluid' src='tp_image/dft/scan_chain_broken_in_eco.png' /></div>
+<p><b>Figure 9: Broken scan chain in functional ECO</b></p>
+<p>There are two solutions to fix the error. The first solution involves changing the drain flop, FLOP_B, to a scan type flop with scan_in and scan_enable pins.</p>
+<div><img class='img-fluid' src='tp_image/dft/DFT_SOLUTION1.png' /></div>
+<p><b>Figure 10: Solution 1 to change the drain flop scan type</b></p>
+<p>The second solution involves inserting a MUX before the D input of FLOP_B. The selection signal of the MUX is controlled by the scan_enable signal to select the output of the previous flop, FLOP_A, when scan_enable is asserted.</p>
+<div><img class='img-fluid' src='tp_image/dft/DFT_SOLUTION2.png' /></div>
+<p><b>Figure 11: Solution 2 to insert a MUX to fix the scan chain</b></p>
+<p>Both solutions can be implemented using GOF in either GUI mode ECO or script mode ECO. After the necessary fixes have been made, the DFT DRC will be free of errors.</p>
+<p>For more information on GUI mode ECO, please refer to <a href='gvt_netlist_debug.php'>this page</a>.</p>
+<p>The commands to fix the logic in script mode:</p>
+<div class='gofscript'><pre>
+<span style='color:#b34c0a'>#Solution 1</span>
+<a class='n' href='#___change_gate'>change_gate</a>(<span style='color:#63ac0a'>"FLOP_B"</span>, <span style='color:#63ac0a'>"SDFFHQX1"</span>, <span style='color:#63ac0a'>".SI(FLOP_A/Q),.SE(FLOP_A/SE)"</span>);
+<span style='color:#b34c0a'>#Solution 2</span>
+<a class='n' href='#___change_pin'>change_pin</a>(<span style='color:#63ac0a'>"FLOP_B/D"</span>, <span style='color:#63ac0a'>"MX2X4"</span>, <span style='color:#63ac0a'>"u_dft_eco_mux"</span>, <span style='color:#63ac0a'>"-,FLOP_A/Q,FLOP_A/SE"</span>);
+</pre></div>

src_en/man.geco_ecoretarget.txt

@@ -0,0 +1,26 @@
+<h3>2.2.8 ECO Retargeting</h3>
+<p>The synthesis of a large SOC design is known for its time-intensive nature, often taking several days to complete. In cases where a functional ECO is necessary, particularly concerning a specific sub-module, the design team opts to confine the ECO to that particular sub-module instead of initiating synthesis for the entire design. Following this, the ECO results for the sub-module are retargeted onto the full top-level netlist. This strategy significantly accelerates the turnaround time and ensures the project schedule remains on track.</p>
+<p>However, the team must factor in the boundary optimization of the sub-modules during backend processing. A given sub-module may have undergone unique transformations, resulting in the creation of multiple distinct physical modules with diverse backend optimizations. Illustrated in Figure 6, an instance of SUB_MOD_A may exemplify a backend modification, such as a port inversion.</p>
+<p>Consequently, the automatic ECO process must be designed to account for these variations in backend processing, ensuring a comprehensive and accurate adaptation to the specific characteristics of each sub-module.</p>
+<div><img class='img-fluid' src='tp_image/gofdoc/retart_sub_mod.png' /></div>
+<p><b>Figure 6: Instances of one sub-module have different boundary optimization</b></p>
+<p>The boundary optimization challenge in GOF is addressed by incorporating the original pre-layout netlist. This is possible because the pre-layout netlist should mirror the state of the netlist before any ECO is implemented, with the boundary remaining unchanged prior to the placement and routing phase.</p>
+<p>To extract the boundary optimization of sub-modules during ECO, a comparison is made between the pre-layout netlist and the netlist under ECO. As the automatic ECO is applied to individual sub-modules, the relevant boundary optimization information is retroactively annotated. This ensures the precision of the ECO and establishes equivalence when comparing top-level designs.</p>
+<p>The loading of the pre-layout netlist is facilitated by using the "-ori_syn" option in the "read_design" command.</p>
+<p>ECO retargeting script:</p>
+<div class='gofscript'><pre><a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-ref'</span>, <span style='color:#63ac0a'>"new_sub_mode_a.gv"</span>); <span style='color:#b34c0a'># New synthesized sub-module-A</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>"post_layout.gv"</span>); <span style='color:#b34c0a'># Full post layout netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>'-ori_syn'</span>, <span style='color:#63ac0a'>"pre_layout.gv"</span>); <span style='color:#b34c0a'># Full prelayout, equal to post_layout.gv</span>
+<span style='color:#b34c0a'># Apply ECO to the first instance</span>
+<a class='n' href='#___set_top_ref'>set_top_ref</a>(<span style='color:#63ac0a'>"SUB_MOD_A"</span>); <span style='color:#b34c0a'># Must set REF scope</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SUB_MOD_A_0"</span>); <span style='color:#b34c0a'># Uniquified name for the first instance</span>
+<a class='n' href='#___fix_design'>fix_design</a>;
+<span style='color:#b34c0a'># Apply ECO to the second instance</span>
+<a class='n' href='#___set_top_ref'>set_top_ref</a>(<span style='color:#63ac0a'>"SUB_MOD_A"</span>); <span style='color:#b34c0a'># Must set REF scope</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SUB_MOD_A_1"</span>); <span style='color:#b34c0a'># Uniquified name for the second instance</span>
+<a class='n' href='#___fix_design'>fix_design</a>;
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SOC_TOP"</span>);
+<a class='n' href='#___report_eco'>report_eco</a>();
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"post_layout.eco.gv"</span>); <span style='color:#b34c0a'># Full post layout netlist after ECO</span>
+</pre></div>
+<p>This entire retargeting procedure is notably more time-efficient compared to performing a full netlist ECO. With the boundary information being meticulously addressed, the resulting ECO is highly accurate.</p>

src_en/man.geco_filereq4fullfuneco.txt

@@ -0,0 +1,10 @@
+<h3>2.2.1 Files and data requirements in automatic functional ECO</h3>
+<ul>
+  <li>Liberty files with extension '.lib'</li>
+  <li>Other Verilog libraries files for modules not covered in '.lib' files</li>
+  <li>Implementation SVF and Reference SVF file, required for designs with multibit flops</li>
+  <li>Implementation Netlist on which ECO will be done</li>
+  <li>Reference Netlist synthesized with the same constraints as the pre-layout netlist</li>
+  <li>The top level module name under ECO</li>
+</ul>
+<p></p>

src_en/man.geco_filereqingatearray.txt

@@ -0,0 +1,9 @@
+<h3>2.4.3 Files and data requirements in Gate Array ECO</h3>
+<ul>
+  <li>Standard library (Synopsys Liberty) files with extension '.lib'</li>
+  <li>Other Verilog libraries if '.lib' files can't cover</li>
+  <li>Implementation Netlist</li>
+  <li>Reference Netlist</li>
+  <li>LEF files</li>
+  <li>DEF (Design Exchange Format) files</li>
+</ul>

src_en/man.geco_filereqinmanualeco.txt

@@ -0,0 +1,7 @@
+<h3>2.6.1 Files and data requirements in Manual ECO</h3>
+<ul>
+	<li>Standard library (Synopsys Liberty) files with extension &lsquo;.lib&rsquo;</li>
+	<li>Other Verilog libraries</li>
+	<li>Implementation Netlist</li>
+	<li>ECO locations</li>
+</ul>

src_en/man.geco_filereqinmetaleco.txt

@@ -0,0 +1,10 @@
+<h3>2.3.4 Files and data requirements in Metal Only ECO</h3>
+<ul>
+  <li>Liberty files with extension '.lib'</li>
+  <li>Other Verilog libraries if '.lib' files can't cover</li>
+  <li>Implementation Netlist</li>
+  <li>Reference Netlist</li>
+  <li>DEF (Design Exchange Format) file. It's optional. If it is not loaded, GOF won&rsquo;t map the spare gate type cells to the exact spare instances</li>
+  <li>Spare gates pattern. It is in 'hierarchical_instance/leaf_instance' format. It has wild card '*' to match the spare gates in Implementation Netlist</li>
+  <li>Spare gates list file. If several users work on the same Implementation Netlist, the initial spare gates list file should be generated only once. And new spare gates list file must&nbsp;be created every time an ECO is done</li>
+</ul>

src_en/man.geco_findequalnetrtlnet.txt

@@ -0,0 +1,19 @@
+<h2>2.5 Find Equal Nets between RTL and Netlist</h2>
+<p>For certain ECO cases, specifically those involving changes to combinational signals, manual ECOs may prove to be quicker and more effective. However, identifying equivalent wires in the netlist for RTL signals can be a challenging aspect of such manual ECOs. This is primarily due to the fact that combinational signals are often optimized during synthesis. To help alleviate this issue, GOF offers an API called 'find_equal_nets' as well as GUI operations to assist in the search for equivalent nets in the netlist for RTL signals.</p>
+<h3>2.5.1 Example script to find equal nets</h3>
+<p>The following is the example script for finding equal nets in netlist for RTL:</p>
+<div class='gofscript'><pre><span style='color:#b34c0a'># GOF script, find_equal_nets.pl</span>
+use strict;
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
+<a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"SYNTHESIS"</span>);
+<a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"NO_SIM"</span>);
+<a class='n' href='#___set_inc_dirs'>set_inc_dirs</a>(<span style='color:#63ac0a'>"/project/nd900/vlib/include"</span>, <span style='color:#63ac0a'>"/project/nd900/IPS/include"</span>);
+<a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-ref'</span>, <span style='color:#63ac0a'>"ref0.sv"</span>, <span style='color:#63ac0a'>"ref1.sv"</span>, <span style='color:#63ac0a'>"ref2.sv"</span>);
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist </span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module</span>
+<a class='n' href='#___elab_rtl'>elab_rtl</a>;
+<a class='n' href='#___find_equal_nets'>find_equal_nets</a>(<span style='color:#63ac0a'>"row_full"</span>, <span style='color:#63ac0a'>"sync_start"</span>); <span style='color:#b34c0a'># Find row_full and sync_start in the netlist</span>
+</pre></div>
+<h3>2.5.2 GUI Mode to find equal nets</h3>
+<p>Please refer to <a href='#-find-equal-nets-of-the-selected-reference-net'>'Find Equal Nets in Netlist Window'</a> for the detail</p>

src_en/man.geco_formalityhelp.txt

@@ -0,0 +1,178 @@
+<h3>2.2.19 Formality help files generation</h3>
+<p>GOF LEC logic equivalence checking can be performed on any two netlists or on the results after GOF ECO run. Subsequently, Formality help files can be generated for use in Formality, significantly enhancing the success rate of the Formality tool.</p>
+<p>Formality help files generation:</p>
+<div class='gofscript'><pre><a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.v"</span>); <span style='color:#b34c0a'># Reference netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"eco_netlist.v"</span>); <span style='color:#b34c0a'># ECOed netlist</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"CHIP_TOP"</span>);
+<a class='n' href='#___run_lec'>run_lec</a>(); <span style='color:#b34c0a'># Run GOF LEC</span>
+<a class='n' href='#___write_compare_points'>write_compare_points</a>(<span style='color:#63ac0a'>"compare_points.report"</span>);
+<a class='n' href='#___write_formality_help_files'>write_formality_help_files</a>(<span style='color:#63ac0a'>"fm_dir/formality_help"</span>); <span style='color:#b34c0a'># formality_help files are generated in fm_dir folder</span>
+</pre></div>
+<p>In the above example, the assistance configuration file "fm_dir/formality_help.config.tcl" contains a compilation of set_user_match, rewire_connection, and set_constant commands designed to aid Formality in successfully achieving logic equivalence checking.</p>
+<p>Integrated the file into Formality script:</p>
+<div class='gofscript'><pre><span style='color:#b34c0a'># Formality netlist vs netlist script</span>
+read_db -tech tsmc.db
+read_verilog -r reference.v
+read_verilog -i eco_netlist.v
+<span style='color:#b34c0a'>#Setup constraint</span>
+<span style='color:#b34c0a'>#Read in the help config file </span>
+source fm_dir/formality_help.config.tcl
+match
+verify
+</pre></div>
+<h3>2.2.20 RTL Guided ECO Flow</h3>
+<p>RTL-guided ECO employs two approaches: utilizing the built-in RTL logic equivalence checking engine of GOF or incorporating results from third-party LEC tools to pinpoint areas needing ECO adjustments. The advantage of the internal RTL LEC is its speed and efficiency. However, a drawback arises when hierarchies mismatch with synthesized netlists, particularly in designs with extensive SystemVerilog statements. To address this, third-party RTL LEC tool results can be utilized to resolve hierarchy inconsistencies. For example, GOF ECO can process a list file of non-equivalent results from tools like Synopsys Formality, allowing it to concentrate ECO efforts solely on identified areas.</p>
+<h3>2.2.21 Internal RTL to RTL Guidance</h3>
+<p>The RTL Guided ECO Flow is an additional step in the netlist ECO process, which involves comparing RTL designs to identify any discrepancies. Unlike Gate to Gate comparison, this method is faster and more targeted. The ECO process can be slowed down by the insertion of DFT logic and boundary optimization, making gate-to-gate comparison more complicated. Additionally, the use of RTL comparison can prevent the generation of redundant ECO fixes during patch generation.</p>
+<p>Figure 15 illustrates how RTL to RTL comparison runs parallel to the key-point mapping of two gate-level netlists. If the non-equivalent points identified by RTL comparison have been integrated into the ECO flow successfully, gate-to-gate comparison can be bypassed.</p>
+<div><img class='img-fluid' src='tp_image/rtl2rtl/RTL_ECO.png' /></div>
+<p><b>Figure 15: RTL Guided ECO Flow</b></p>
+<h4>2.2.21.1 Files and data requirements in RTL guided ECO</h4>
+<ul>
+  <li>Liberty files with extension '.lib'</li>
+  <li>Other Verilog libraries files for modules not covered in '.lib' files</li>
+  <li>Implementation SVF and Reference SVF file, required for designs with multibit flops</li>
+  <li>Implementation Netlist on which ECO will be done</li>
+  <li>Reference Netlist synthesized with the same constraints as the pre-layout netlist</li>
+  <li>Implementation RTL which is logically equivalent to the Implementation Netlist</li>
+  <li>Reference RTL which is logically equivalent to the Reference Netlist</li>
+  <li>The top level module name under ECO</li>
+</ul>
+<h4>2.2.21.2 Steps to do RTL guided ECO</h4>
+<ul>
+  <li>Modify the original RTL</li>
+  <li>Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist</li>
+  <li>Create GOF ECO script:
+    <ul>
+      <li>Specify ECO name in 'setup_eco'</li>
+      <li>Load Liberty files and Verilog libraries</li>
+      <li>Load Reference RTL (the modified RTL) and Implementation RTL (the original RTL)</li>
+      <li>Check non-equivalent points by 'rtl_compare'</li>
+      <li>Load the Reference Netlist and the Implementation Netlist</li>
+      <li>Fix the design by 'fix_design'</li>
+      <li>Report ECO status and write out ECO results</li>
+    </ul>
+  </li>
+  <li>Run the above ECO script by "gof -run eco_script.pl"</li>
+</ul>
+<h4>2.2.21.3 RTL guided ECO example script</h4>
+<p>GOF script has the exact same syntax as Perl script and runs the exported APIs that access the netlist database and modify the netlist.</p>
+<p>The following is the example script for RTL guided ECO:</p>
+<div class='gofscript'><pre><span style='color:#b34c0a'># GOF ECO script, rtl_guided.pl</span>
+use strict;
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"rtl_guided_eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
+my $rtl2rtl = 1;
+if($rtl2rtl){
+  <a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"SYNTHESIS"</span>);
+  <a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"NO_SIM"</span>);
+  <a class='n' href='#___set_inc_dirs'>set_inc_dirs</a>(<span style='color:#63ac0a'>"/project/nd900/vlib/include"</span>, <span style='color:#63ac0a'>"/project/nd900/IPS/include"</span>);
+  <a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-ref'</span>, <span style='color:#63ac0a'>"ref0.sv"</span>, <span style='color:#63ac0a'>"ref1.sv"</span>, <span style='color:#63ac0a'>"ref2.sv"</span>);
+  <a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>"imp0.sv"</span>, <span style='color:#63ac0a'>"imp1.sv"</span>, <span style='color:#63ac0a'>"imp2.sv"</span>);
+  <a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);
+  <a class='n' href='#___rtl_compare'>rtl_compare</a>;
+}
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module</span>
+<span style='color:#b34c0a'># Preserve DFT Test Logic</span>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);
+<a class='n' href='#___fix_design'>fix_design</a>;
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span>
+exit; <span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears</span>
+</pre></div>
+<h4>2.2.21.4 Synthesize Reference RTL to Reference Netlist</h4>
+<p>If Reference Netlist is not provided, it can be synthesized from Reference RTL by 'synthesize' command.</p>
+<p>As shown in Figure 16, Reference RTL is directly synthesized into Reference Netlist and used in the ECO.</p>
+<div><img class='img-fluid' src='tp_image/rtl2rtl/RTL_GUIDE_SYN.png' /></div>
+<p><b>Figure 16: RTL Guided ECO Flow</b></p>
+<p>The following is the example script for Reference RTL synthesis in RTL guided ECO:</p>
+<div class='gofscript'><pre><span style='color:#b34c0a'># GOF ECO script, rtl_guided_synthesis.pl</span>
+use strict;
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"rtl_guided_eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
+<a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"SYNTHESIS"</span>);
+<a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"NO_SIM"</span>);
+<a class='n' href='#___set_inc_dirs'>set_inc_dirs</a>(<span style='color:#63ac0a'>"/project/nd900/vlib/include"</span>, <span style='color:#63ac0a'>"/project/nd900/IPS/include"</span>);
+<a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-ref'</span>, <span style='color:#63ac0a'>"ref0.sv"</span>, <span style='color:#63ac0a'>"ref1.sv"</span>, <span style='color:#63ac0a'>"ref2.sv"</span>);
+<a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>"imp0.sv"</span>, <span style='color:#63ac0a'>"imp1.sv"</span>, <span style='color:#63ac0a'>"imp2.sv"</span>);
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);
+<a class='n' href='#___rtl_compare'>rtl_compare</a>;
+
+<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module</span>
+<a class='n' href='#___elaborate'>elaborate</a>; <span style='color:#b34c0a'># The command synthesizes the Reference RTL to Reference Netlist </span>
+<span style='color:#b34c0a'># Preserve DFT Test Logic</span>
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);
+<a class='n' href='#___fix_design'>fix_design</a>;
+<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span>
+<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span>
+<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span>
+exit; <span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears</span>
+</pre></div>
+<h3>2.2.22 Third Party RTL LEC Result Processing</h3>
+<p>GOF ECO has the capability to ingest a list of ECO points, enabling it to concentrate exclusively on the items specified in the list. The format of the list file comprises a type designation followed by one or multiple spaces and then the non-equivalence point.</p>
+<div class='gofscript'>
+<pre>
+inst yak_zcvg_inst/skip_pix_reg
+port te_coord[5]
+inst yak_hah_inst/x_start_pa_reg_31_
+inst yak_hah_inst/x_end_pa_reg_30_
+inst yak_hah_inst/x_end_pa_reg_29_
+inst yak_hah_inst/x_end_pa_reg_28_
+inst yak_hah_inst/x_end_pa_reg_27_
+inst yak_hah_inst/x_end_pa_reg_26_
+pin yak_hah_inst/u_sync_cell/D
+</pre>
+</div>
+<p>The ECO list file is incorporated using the '-list_file' option within the 'read_design' command. It can be generated from a Third Party LEC non-equivalence result file. For instance, in Synopsys Formality, the command 'report_failing_points > formality_non_eq.report' generates such a file. In a GOF ECO script, this report file is then read in and converted into the list file.</p>
+<p>Below is an example script demonstrating the conversion of Third Party LEC results and execution of GOF ECO with the 'list_file' option:</p>
+<div class='gofscript'><pre>use strict;
+my $list_cont = <span style='color:#63ac0a'>""</span>;
+open(FIN, <span style='color:#63ac0a'>"formality_non_eq.report"</span>);
+while(&lt;FIN&gt;){
+  if(m/Ref\s+(\w+)\s+r:\/\w+\/\w+\/(.+)/){
+    my $fm_type = $1;
+    my $point = $2;
+    my $gof_type = <span style='color:#63ac0a'>"inst"</span>;
+    if($fm_type =~ m/Pin/){
+      $gof_type = <span style='color:#63ac0a'>"pin"</span>;
+    }elsif($fm_type =~ m/Port/){
+      $gof_type = <span style='color:#63ac0a'>"port"</span>;
+    }else{
+      <span style='color:#b34c0a'># For instance type</span>
+      $point =~ s/\[/_/g; <span style='color:#b34c0a'># Mostly abc_reg[0] has name changed to abc_reg_0_ in the netlist</span>
+      $point =~ s/\]/_/g;
+    }
+    $list_cont .= <span style='color:#63ac0a'>"$gof_type $point\n"</span>;
+  }
+}
+close(FIN);
+open(FOUT, <span style='color:#63ac0a'>">eco_list.txt"</span>);
+print FOUT $list_cont;
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_list_file"</span>); <span style='color:#b34c0a'># Setup ECO name</span>
+<a class='n' href='#___set_log_file'>set_log_file</a>(<span style='color:#63ac0a'>"eco_list_file.log"</span>);
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SOC_TOP"</span>);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"test_mode"</span>, 0);
+<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_en"</span>, 0);
+<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"test_so*"</span>);
+<a class='n' href='#___fix_design'>fix_design</a>(<span style='color:#63ac0a'>"-list_file"</span>, <span style='color:#63ac0a'>"eco_list.txt"</span>); <span style='color:#b34c0a'># -list_file option to read in the ECO list file with the ECO points</span>
+<a class='n' href='#___report_eco'>report_eco</a>();
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);
+exit;
+</pre></div>

src_en/man.geco_gatearrayautomapping.txt

@@ -0,0 +1,28 @@
+<h3>2.4.2 Gate Array Automatic Mapping</h3>
+<p>When generating a patch, GOF synthesizes it using only gate array functional cell types. These functional cells are then mapped to the most optimal nearby gate array spare cells with the minimum wire connection costs.</p>
+<div><img class='img-fluid' src='./tp_image/gofdoc/metal_gate_array.png' width='800'/></div>
+<p><b>Figure 21: Gate Array Spare Cells Mapping to Functional Cells</b></p>
+<p>Once the mapping and swapping process is complete, some gate array spare cells may have portions of their tiles being used by several functional cells, as shown in Figure 21. To properly save the ECO results, the type of these gate array spare cells should be changed. For instance, gate array A should have its type changed from GFILL8 to GFILL4. Any completely used up gate array spare cells, such as gate array B with type GFILL4 and all four tiles being used, should be deleted.</p>
+<p>The mapped gate array functional cells need to be moved to the locations of their corresponding gate array spare cells, with the horizontal location X adjusted based on the starting tile location. For example, the GINVD1 instance should be moved to (Xg+TW, Yg), and the GBUFFD1 instance should be moved to (Xg+TW*6, Yg), as shown in Figure 20.</p>
+<p>GOF writes out an ECO verilog file and backend tools ECO scripts. In the verilog file, the location of the newly added gate array functional cells is written in comments. GOF supports both Synopsys ICC script and Cadence Encounter script, both of which have cell location placement support.</p>
+<p>For example, when saving the result in an ICC TCL script, the cells in Figure 20 would have the following commands:</p>
+<div class='gofscript'>
+size_cell GFILLER_7256 GFILL1 <span style='color:#b34c0a'># The original GFILL8 resized</span></br>
+create_cell eco_3821_ubuf GBUFD1</br>
+create_cell eco_3821_uan4 GAN4D1</br>
+create_cell eco_3821_und2 GND2D1</br>
+create_cell eco_3821_uinv GINVD1</br>
+set_cell_location -ignore_fixed -coordinates <span style='color:#63ac0a'>"255.02 413.28"</span> eco_3821_ubuf <span style='color:#b34c0a'># Xg+WT*6, Yg</span></br>
+set_cell_location -ignore_fixed -coordinates <span style='color:#63ac0a'>"254.42 413.28"</span> eco_3821_uan4 <span style='color:#b34c0a'># Xg+WT*3, Yg</span></br>
+set_cell_location -ignore_fixed -coordinates <span style='color:#63ac0a'>"254.22 413.28"</span> eco_3821_und2 <span style='color:#b34c0a'># Xg+WT*2, Yg</span></br>
+set_cell_location -ignore_fixed -coordinates <span style='color:#63ac0a'>"254.02 413.28"</span> eco_3821_uinv <span style='color:#b34c0a'># Xg+WT*1, Yg</span></br>
+</div>
+<p>Encounter script format:</p>
+<div class='gofscript'>
+ecoChangeCell -inst GFILLER_7256 -cell GFILL1 <span style='color:#b34c0a'># The original GFILL8 resized</span></br>
+addInst -loc 255.02 413.28 -inst eco_3821_ubuf -cell GBUFD1 <span style='color:#b34c0a'># Xg+WT*6, Yg</span></br>
+addInst -loc 254.42 413.28 -inst eco_3821_uan4 -cell GAN4D1 <span style='color:#b34c0a'># Xg+WT*3, Yg</span></br>
+addInst -loc 254.22 413.28 -inst eco_3821_und2 -cell GND2D1 <span style='color:#b34c0a'># Xg+WT*2, Yg</span></br>
+addInst -loc 254.02 413.28 -inst eco_3821_uinv -cell GINVD1 <span style='color:#b34c0a'># Xg+WT*1, Yg</span></br>
+</div>
+<p>Note:Tile size assumed to be 0.20 X 0.22; GFILL8 location (Xg, Yg)=(253.82, 413.28)</p>

src_en/man.geco_gatearraybasetile.txt

@@ -0,0 +1,28 @@
+<h3>2.4.1 Gate Array Cell Base Tile</h3>
+<p>The base unit of gate array cell is a tile. Every gate array cell consists of one or more tiles. Use one 5nm standard library as example:</p>
+<table border=1 class='lefttable'>
+<thead><tr>
+<th>Tile Numbers</th><th>Spare Cells</th><th>Functional Cells</th></tr></thead>
+<tr>
+<td>1</td><td>GFILL1</td><td>GTIE GINVD1 GND2D1 GNR2D1</td></tr>
+<tr>
+<td>2</td><td>GFILL2</td><td>GBUFD1 GAN2D1 GOR2D1 GAOI21D1 GDN3D1</td></tr>
+<tr>
+<td>3</td><td>GFILL3</td><td>GAO21D1 GAN4D1 GOR4D1</td></tr>
+<tr>
+<td>4</td><td>GFILL4</td><td>GINVD8 GAN2D4</td></tr>
+<tr>
+<td>5</td><td>GFILL5</td><td>GMUX2D1 GXOR2D1 GXNOR2D1</td></tr>
+<tr>
+<td>6</td><td>GFILL6</td><td>GBUFD8 GSDFFRQD1 GSDFFSQD1</td></tr>
+<tr>
+<td>8</td><td>GFILL8</td><td>GINVD16</td></tr>
+<tr>
+<td>12</td><td>GFILL12</td><td>GCKLNQD6</td></tr>
+</table>
+<p><b>Table: Tile Numbers in Gate Array Spare Cells and Functional Cells</b></p>
+<p>Gate array cells have a larger size than normal standard cells. For instance, GFILL1 is four times larger than FILL1, and GND2D1 is 25% larger than ND2D1. However, the power consumption and timing of these cells are similar.</p>
+<p>Each gate array spare cell has a location defined by a DEF file. In Figure 20, the location of one GFILL8 spare cell is defined as (Xg, Yg), with a tile height equivalent to that of GFILL1 and a tile width eight times that of GFILL1.</p>
+<p>GFILL8 tiles can be regrouped and rewired in metal layers to create different functional cells. For example, GBUFD1 requires two tiles and implements a buffer function, while GAN4D1 uses three tiles to create a 4-input AND function.</p>
+<div><img class='img-fluid' src='./tp_image/gofdoc/metal_tie_functional_cell.png' width='800'/></div>
+<p><b>Figure 20: Gate Array Spare Cell GFILL8 Regrouped Tiles to Form Functional Cells</b></p>

src_en/man.geco_gatearrayeco.txt

@@ -0,0 +1 @@
+<p>Metal configurable gate array cells are specially developed for Metal Only ECO. These cells come in two types, which are used in different backend stages. The first type is gate array spare cells, which are typical filler or decap cells used in the original flow. During the backend P&R stage, gate array spare cells such as GFILL/GDCAP are incorporated and distributed throughout the design. The second type is gate array functional cells, which are used in post-mask ECO. Gate array spare cells are replaced with gate array functional cells such as GAN2, GND2, and GXOR2.</p>

src_en/man.geco_gclockinmetaleco.txt

@@ -0,0 +1,8 @@
+<h3>2.3.8 Gated clocks in Automatic Metal Only ECO</h3>
+<p>If the automatic metal only ECO has new gated clock cells added while the spare gates list doesn't have gated clock cell, "convert_gated_clocks" API should be run to convert gated clock cells to 'MUX' type logic. GOF maps the 'MUX' type logic to the spare type gates in 'map_spare_cells' API.</p>
+<div class='gofscript'>
+<a class='n' href='#___get_spare_cells'>get_spare_cells</a>(<span style='color:#63ac0a'>"*/*_SPARE*"</span>);</br>
+<a class='n' href='#___convert_gated_clocks'>convert_gated_clocks</a>();</br>
+<a class='n' href='#___map_spare_cells'>map_spare_cells</a>();</br>
+
+</div>

src_en/man.geco_guimodefulllayereco.txt

@@ -0,0 +1,38 @@
+<h2>2.8 GUI Mode Full Layers ECO Flow</h2>
+<p>The following paragraph demonstrates how to insert buffers and inverters into a circuit in GUI mode.</p>
+<p></p>
+<h3>2.8.1 Start up GOF in GUI Mode</h3>
+<p></p>
+<p>Start up GOF by the command line</p>
+<div class='gofscript'>
+<strong>gof -lib t65nm.lib -lib io.lib netlist_port.v</strong>
+</div>
+<p>For detail usage, visit this link</p>
+<p><a href='/usage.htm'>https://nandigits.com/usage.htm</a></p>
+<p>In GofViewer netlist window, press ctrl-g or menu commands-&gt;&rsquo;Launch GofTrace with gate&rsquo;. Fill in the instance name that needs ECO.</p>
+<p><img class='img-fluid' src='/gof_manual_files/image007.jpg' style='border:none; height:294px; width:611px' /></p>
+<p><b>Figure 22: Load gate to schematic</b></p>
+<h3>2.8.2 Create Partial Schematic</h3>
+<p>In GofTrace schematic window, use mouse middle button to expand the schematic. In this case, pin D of the flop should be inserted an invert.</p>
+<p><img class='img-fluid' src='/gof_manual_files/image008.jpg' style='border:none; height:362px; width:611px' /></p>
+<p><b>Figure 23: Partial Schematic for GUI ECO</b></p>
+<p></p>
+<h3>2.8.3 Do ECO on schematic</h3>
+<p></p>
+<p>Check ECO button to enable ECO mode</p>
+<p><img class='img-fluid' src='/gof_manual_files/image009.jpg' style='border:none; height:385px; width:613px' /></p>
+<p><b>Figure 24: Schematic in ECO Mode</b></p>
+<p>Press mouse-left-button on the wire to select it. Click ECO button &lsquo;Insert gates into connections&rsquo;, select the right invert in the gate type selection window.</p>
+<p><img class='img-fluid' src='/gof_manual_files/image010.jpg' style='border:none; height:391px; width:623px' /></p>
+<p><b>Figure 25: Select Gate in GUI ECO</b></p>
+<p>In &lsquo;Pin Connections&rsquo; setup window, use default &lsquo;Complete Loop&rsquo; option, so that the gate can be inserted in the net.</p>
+<p><img class='img-fluid' src='/gof_manual_files/image011.gif' style='border:none; height:103px; width:505px' /></p>
+<p><b>Figure 26: New Cell Pin Connection Selections</b></p>
+<p></p>
+<p>Click OK and the invert is inserted.</p>
+<p><img class='img-fluid' src='/gof_manual_files/image012.jpg' style='border:none; height:305px; width:527px' /></p>
+<p><b>Figure 27: Manual ECO with New Gate Inserted</b></p>
+<h3>2.8.4 Save ECO in GUI Mode</h3>
+<p>Press ECO button &lsquo;Save ECO result to file&rsquo;. And select the format to be saved. The supported formats include verilog netlist, SOC Encounter ECO script, GOF script, TCL script and DCShell script.</p>
+<p><img class='img-fluid' src='/gof_manual_files/image013.jpg' style='border:none; height:359px; width:600px' /></p>
+<p><b>Figure 28: Save ECO in GUI Mode</b></p>

src_en/man.geco_guimodemetalonlyeco.txt

@@ -0,0 +1,13 @@
+<h2>2.9 GUI Mode Metal Only ECO Flow</h2>
+<p>Metal ECO can only use existing spare gates on the silicon. GOF controls how to use these spare gates.</p>
+<h3>2.9.1 Methods for Metal Only ECO</h3>
+<p>Four methods are supported in Metal Only ECO:</p>
+<ol>
+<li>User can add any type of gates and let the tool map to the spare type gates, Place and Route tool should map the spare type gates to the exact spare gate instances</li>
+<li>User can add any type of gates and let the tool map to the exact spare gate instances</li>
+<li>User can add only spare type gates and let the tool map to the exact spare gate instances</li>
+<li>User can pick the exact spare gate instances, and connect and disconnect up the instances in ECO</li>
+</ol>
+<p>Note: 'Spare type gate' refers to the gate type, 'INVX2', 'NAND2X2'. 'Exact spare gate instance' refers to the spare instances in the design, E.G. 'spare1/spare_invx2'</p>
+<h3>2.9.2 Setup and use cases</h3>
+<p>The detail setup for four method can be found in <a href='#-metal-only-eco'>GOF ECO Metal Only ECO</a>. Use cases can be found in <a href='/gof_usecases.php'>online document</a>.</p>

src_en/man.geco_handlrepwork.txt

@@ -0,0 +1,24 @@
+<h3>2.6.6 Handle repetitive work</h3>
+<p>A Perl 'for' or 'foreach' loop can handle repetitive work efficiently. For example, to add a 'AND' isolation gate for every output port of a module.</p>
+<div class='gofscript'>
+<span style='color:#b34c0a'># GOF ECO script, add_ands.pl</span></br>
+use strict;</br>
+<a class='n' href='#___undo_eco'>undo_eco</a>; <span style='color:#b34c0a'># Discard previous ECO operations</span></br>
+<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_example"</span>); <span style='color:#b34c0a'># Setup ECO name</span></br>
+<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>); <span style='color:#b34c0a'># Read in standard library</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>); <span style='color:#b34c0a'># Read in Reference Netlist</span></br>
+<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>); <span style='color:#b34c0a'># Read in implementation Netlist which is under ECO</span></br>
+<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>); <span style='color:#b34c0a'># Set the top module that ECO is working on</span></br>
+my @ports = <a class='n' href='#___get_ports'>get_ports</a>(<span style='color:#63ac0a'>"-output"</span>); <span style='color:#b34c0a'># Get all output ports of module 'topmod'</span></br>
+<span style='color:#b34c0a'># For each output port of 'topmod', insert an 'AND' gate to enable it only when 'enable_out' is high</span></br>
+my $cnt = 0;</br>
+foreach my $port (@ports){</br>
+&nbsp;&nbsp;<a class='n' href='#___change_port'>change_port</a>($port, <span style='color:#63ac0a'>"AND2X2"</span>, <span style='color:#63ac0a'>"eco_add_and_$cnt"</span>, <span style='color:#63ac0a'>"-,enable_out"</span>);</br>
+&nbsp;&nbsp;$cnt++;</br>
+}</br>
+<a class='n' href='#___report_eco'>report_eco</a>();</br>
+<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span></br>
+exit;<span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when &rsquo;GOF &gt;&rsquo; appears</span></br>
+
+</div>
+<p></p>

src_en/man.geco_manualecoapilist.txt

@@ -0,0 +1,35 @@
+<h3>2.6.3 Manual ECO APIs list</h3>
+<p>These APIs change Implementation Netlist</p>
+<div class='gofscript'>
+<a class='n' href='#___buffer'>buffer</a>: ECO command. Buffer high fanout ECO nets<br>
+<a class='n' href='#___change_gate'>change_gate</a>: ECO command. Modify an instance in ECO<br>
+<a class='n' href='#___change_net'>change_net</a>: ECO command. Change a existing net's driver<br>
+<a class='n' href='#___change_pin'>change_pin</a>: ECO command. Modify pin connection of instances by inserting gates, changing connection to other signal (LLM: change pin insert gate)<br>
+<a class='n' href='#___change_port'>change_port</a>: ECO command. Change an output port's driver, or add gate after input port <br>
+<a class='n' href='#___del_gate'>del_gate</a>: ECO command. Delete gate<br>
+<a class='n' href='#___del_net'>del_net</a>: ECO command. Delete net<br>
+<a class='n' href='#___del_port'>del_port</a>: ECO command. Delete port<br>
+<a class='n' href='#___new_gate'>new_gate</a>: ECO command. Create new gate<br>
+<a class='n' href='#___new_net'>new_net</a>: ECO command. Create a new net<br>
+<a class='n' href='#___new_port'>new_port</a>: ECO command. Create a new port for the current top level module<br>
+</div>
+<p>For the full list of the APIs, user can type 'help' in 'GOF &gt;' shell.</p>
+<p>For the individual API, type 'help api_name' . For example:</p>
+<div class='gofscript'>
+GOF > help <a class='n' href='#___new_port'>new_port</a></br>
+Help for <a class='n' href='#___new_port'>new_port</a></br>
+<a class='n' href='#___new_port'>new_port</a>: ECO command. Create a new port for the current top level module</br>
+ECO command. Create a new port for the current top level module</br>
+Usage: <a class='n' href='#___new_port'>new_port</a>($name, @options);</br>
+$name: Port name</br>
+@options:</br>
+-input: New an input port</br>
+-output: New an output port</br>
+-inout: New an inout port</br>
+Note: The port name has to be pure words or with bus bit, like, abc[0], abc[1]</br>
+Examples:</br>
+<a class='n' href='#___new_port'>new_port</a>(<span style='color:#63ac0a'>'prop_control_en'</span>, <span style='color:#63ac0a'>'-input'</span>); <span style='color:#b34c0a'># create an input port naming prop_control_en</span></br>
+<a class='n' href='#___new_port'>new_port</a>(<span style='color:#63ac0a'>'prop_state[2]'</span>, <span style='color:#63ac0a'>'-output'</span>); <span style='color:#b34c0a'># create an output port with bus bit prop_state[2]</span></br>
+<a class='n' href='#___new_port'>new_port</a>(<span style='color:#63ac0a'>'prop_state[3]'</span>, <span style='color:#63ac0a'>'-output'</span>); <span style='color:#b34c0a'># create an output port with bus bit prop_state[3]</span></br>
+
+</div>