rtl-llm
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qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate

Text Generation

text-generation-inference

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qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate

Commit History

Upload Qwen2ForCausalLM

7a05376
verified

charleshong3 commited on May 30

Upload tokenizer

6d7dc1b
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charleshong3 commited on May 30

initial commit

9fd43cc
verified

charleshong3 commited on May 30