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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_0_0_arch : ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_0_0_arch : ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
|
-- $Id: simlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simlib - sim
-- Description: Support routines for test benches
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.3.8 now numeric_std clean
-- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm
-- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp()
-- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.3.4 added readempty (to discard rest of line)
-- 2007-12-27 106 1.3.3 added simclk2v
-- 2007-12-15 101 1.3.2 add read_ea(time), readtagval[_ea](std_logic)
-- 2007-10-12 88 1.3.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-28 76 1.3 added writehex and writegen
-- 2007-08-10 72 1.2.2 remove entity simclk, put into separate source
-- 2007-08-03 71 1.2.1 readgen, readtagval, readtagval2: add base arg
-- 2007-07-29 70 1.2 readtagval2: add tag=- support; add readword_ea,
-- readoptchar, writetimestamp
-- 2007-07-28 69 1.1.1 rename readrest -> testempty; add readgen
-- use readgen in readtagval() and readtagval2()
-- 2007-07-22 68 1.1 add readrest, readtagval, readtagval2
-- 2007-06-30 62 1.0.1 remove clock_period ect constant defs
-- 2007-06-14 56 1.0 Initial version (renamed from pdp11_sim.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
package simlib is
constant null_char : character := character'val(0); -- '\0'
constant null_string : string(1 to 1) := (others=>null_char); -- "\0"
procedure readwhite( -- read over white space
L: inout line); -- line
procedure readoct( -- read slv in octal base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean); -- success flag
procedure readhex( -- read slv in hex base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean); -- success flag
procedure readgen( -- read slv generic base
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean; -- success flag
base: in integer:= 2); -- default base
procedure readcomment(
L: inout line;
good: out boolean);
procedure readdotcomm(
L: inout line;
name: out string;
good: out boolean);
procedure readword(
L: inout line;
name: out string;
good: out boolean);
procedure readoptchar(
L: inout line;
char: in character;
good: out boolean);
procedure readempty(
L: inout line);
procedure testempty(
L: inout line;
good: out boolean);
procedure testempty_ea(
L: inout line);
procedure read_ea(
L: inout line;
value: out integer);
procedure read_ea(
L: inout line;
value: out time);
procedure read_ea(
L: inout line;
value: out std_logic);
procedure read_ea(
L: inout line;
value: out std_logic_vector);
procedure readoct_ea(
L: inout line;
value: out std_logic_vector);
procedure readhex_ea(
L: inout line;
value: out std_logic_vector);
procedure readgen_ea(
L: inout line;
value: out std_logic_vector;
base: in integer:= 2);
procedure readword_ea(
L: inout line;
name: out string);
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
good: out boolean;
base: in integer:= 2);
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
base: in integer:= 2);
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic;
good: out boolean);
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic);
procedure readtagval2(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
good: out boolean;
base: in integer:= 2);
procedure readtagval2_ea(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
base: in integer:= 2);
procedure writeoct( -- write slv in octal base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0); -- field width
procedure writehex( -- write slv in hex base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0); -- field width
procedure writegen( -- write slv in generic base (arb. lth)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0; -- field width
base: in integer:= 2); -- default base
procedure writetimestamp(
L: inout line;
clkcyc: in slv31;
str : in string := null_string);
-- ----------------------------------------------------------------------------
component simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_CYCLE : out slv31; -- clock cycle number
CLK_STOP : in slbit -- clock stop trigger
);
end component;
component simclkv is -- test bench clock generator
-- with variable periods
port (
CLK : out slbit; -- clock
CLK_CYCLE : out slv31; -- clock cycle number
CLK_PERIOD : in time; -- clock period
CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit -- clock stop trigger
);
end component;
component simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out slv31 -- clock cycle number
);
end component;
end package simlib;
-- ----------------------------------------------------------------------------
package body simlib is
procedure readwhite( -- read over white space
L: inout line) is -- line
variable ch : character;
begin
while L'length>0 loop
ch := L(L'left);
exit when (ch/=' ' and ch/=HT);
read(L,ch);
end loop;
end procedure readwhite;
-- -------------------------------------
procedure readoct( -- read slv in octal base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean) is -- success flag
variable nibble : std_logic_vector(2 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable ndig : integer; -- number of digits
variable ok : boolean;
variable ichar : character;
begin
assert not value'ascending(1)
report "readoct called with ascending range"
severity failure;
assert value'length<=32
report "readoct called with value'length > 32"
severity failure;
readwhite(L);
ndig := 0;
sum := (others=>'U');
while L'length>0 loop
ok := true;
case L(L'left) is
when '0' => nibble := "000";
when '1' => nibble := "001";
when '2' => nibble := "010";
when '3' => nibble := "011";
when '4' => nibble := "100";
when '5' => nibble := "101";
when '6' => nibble := "110";
when '7' => nibble := "111";
when 'u'|'U' => nibble := "UUU";
when 'x'|'X' => nibble := "XXX";
when 'z'|'Z' => nibble := "ZZZ";
when '-' => nibble := "---";
when others => ok := false;
end case;
exit when not ok;
read(L,ichar);
ndig := ndig + 1;
sum(sum'left downto 3) := sum(sum'left-3 downto 0);
sum(2 downto 0) := nibble;
end loop;
ok := ndig>0;
value := sum(value'range);
good := ok;
end procedure readoct;
-- -------------------------------------
procedure readhex( -- read slv in hex base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean) is -- success flag
variable nibble : std_logic_vector(3 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable ndig : integer; -- number of digits
variable ok : boolean;
variable ichar : character;
begin
assert not value'ascending(1)
report "readhex called with ascending range"
severity failure;
assert value'length<=32
report "readhex called with value'length > 32"
severity failure;
readwhite(L);
ndig := 0;
sum := (others=>'U');
while L'length>0 loop
ok := true;
case L(L'left) is
when '0' => nibble := "0000";
when '1' => nibble := "0001";
when '2' => nibble := "0010";
when '3' => nibble := "0011";
when '4' => nibble := "0100";
when '5' => nibble := "0101";
when '6' => nibble := "0110";
when '7' => nibble := "0111";
when '8' => nibble := "1000";
when '9' => nibble := "1001";
when 'a'|'A' => nibble := "1010";
when 'b'|'B' => nibble := "1011";
when 'c'|'C' => nibble := "1100";
when 'd'|'D' => nibble := "1101";
when 'e'|'E' => nibble := "1110";
when 'f'|'F' => nibble := "1111";
when 'u'|'U' => nibble := "UUUU";
when 'x'|'X' => nibble := "XXXX";
when 'z'|'Z' => nibble := "ZZZZ";
when '-' => nibble := "----";
when others => ok := false;
end case;
exit when not ok;
read(L,ichar);
ndig := ndig + 1;
sum(sum'left downto 4) := sum(sum'left-4 downto 0);
sum(3 downto 0) := nibble;
end loop;
ok := ndig>0;
value := sum(value'range);
good := ok;
end procedure readhex;
-- -------------------------------------
procedure readgen( -- read slv generic base
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean; -- success flag
base: in integer := 2) is -- default base
variable nibble : std_logic_vector(3 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable lbase : integer; -- local base
variable cbase : integer; -- current base
variable ok : boolean;
variable ivalue : integer;
variable ichar : character;
begin
assert not value'ascending(1)
report "readgen called with ascending range"
severity failure;
assert value'length<=32
report "readgen called with value'length > 32"
severity failure;
assert base=2 or base=8 or base=10 or base=16
report "readgen base not 2,8,10, or 16"
severity failure;
readwhite(L);
cbase := base;
lbase := 0;
ok := true;
if L'length >= 2 then
if L(L'left+1) = '"' then
case L(L'left) is
when 'b'|'B' => lbase := 2;
when 'o'|'O' => lbase := 8;
when 'd'|'D' => lbase := 10;
when 'x'|'X' => lbase := 16;
when others => ok := false;
end case;
end if;
if lbase /= 0 then
read(L, ichar);
read(L, ichar);
cbase := lbase;
end if;
end if;
if ok then
case cbase is
when 2 => read(L, value, ok);
when 8 => readoct(L, value, ok);
when 16 => readhex(L, value, ok);
when 10 =>
read(L, ivalue, ok);
-- the following if allows to enter negative integers, e.g. -1 for all-1
if ivalue >= 0 then
value := slv(to_unsigned(ivalue, value'length));
else
value := slv(to_signed(ivalue, value'length));
end if;
when others => null;
end case;
end if;
if ok and lbase/=0 then
if L'length>0 and L(L'left)='"' then
read(L, ichar);
else
ok := false;
end if;
end if;
good := ok;
end procedure readgen;
-- -------------------------------------
procedure readcomment(
L: inout line;
good: out boolean) is
variable ichar : character;
begin
readwhite(L);
good := true;
if L'length > 0 then
good := false;
if L(L'left) = '#' then
good := true;
elsif L(L'left) = 'C' then
good := true;
writeline(output, L);
end if;
end if;
end procedure readcomment;
-- -------------------------------------
procedure readdotcomm(
L: inout line;
name: out string;
good: out boolean) is
begin
for i in name'range loop
name(i) := ' ';
end loop;
good := false;
if L'length>0 and L(L'left)='.' then
readword(L, name, good);
end if;
end procedure readdotcomm;
-- -------------------------------------
procedure readword(
L: inout line;
name: out string;
good: out boolean) is
variable ichar : character;
variable ind : integer;
begin
assert name'ascending(1)
report "readword called with descending range for name"
severity failure;
readwhite(L);
for i in name'range loop
name(i) := ' ';
end loop;
ind := name'left;
while L'length>0 and ind<=name'right loop
ichar := L(L'left);
exit when ichar=' ' or ichar=',' or ichar='|';
read(L,ichar);
name(ind) := ichar;
ind := ind + 1;
end loop;
good := ind /= name'left; -- ok if one non-blank found
end procedure readword;
-- -------------------------------------
procedure readoptchar(
L: inout line;
char: in character;
good: out boolean) is
variable ichar : character;
begin
good := false;
if L'length > 0 then
if L(L'left) = char then
read(L, ichar);
good := true;
end if;
end if;
end procedure readoptchar;
-- -------------------------------------
procedure readempty(
L: inout line) is
variable ch : character;
begin
while L'length>0 loop -- anything left ?
read(L,ch); -- read and discard it
end loop;
end procedure readempty;
-- -------------------------------------
procedure testempty(
L: inout line;
good: out boolean) is
begin
readwhite(L); -- discard white space
good := true; -- good if now empty
if L'length > 0 then -- anything left ?
good := false; -- assume bad
if L'length >= 2 and -- check for "--"
L(L'left)='-' and L(L'left+1)='-' then
good := true; -- in that case comment -> good
end if;
end if;
end procedure testempty;
-- -------------------------------------
procedure testempty_ea(
L: inout line) is
variable ok : boolean := false;
begin
testempty(L, ok);
assert ok report "extra chars in """ & L.all & """" severity failure;
end procedure testempty_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out integer) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(integer) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out time) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(time) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out std_logic) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(std_logic) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(std_logic_vector) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure readoct_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
readoct(L, value, ok);
assert ok report "readoct() conversion error in """ &
L.all & """" severity failure;
end procedure readoct_ea;
-- -------------------------------------
procedure readhex_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
readhex(L, value, ok);
assert ok report "readhex() conversion error in """ &
L.all & """" severity failure;
end procedure readhex_ea;
-- -------------------------------------
procedure readgen_ea(
L: inout line;
value: out std_logic_vector;
base: in integer := 2) is
variable ok : boolean := false;
begin
readgen(L, value, ok, base);
assert ok report "readgen() conversion error in """ &
L.all & """" severity failure;
end procedure readgen_ea;
-- -------------------------------------
procedure readword_ea(
L: inout line;
name: out string) is
variable ok : boolean := false;
begin
readword(L, name, ok);
assert ok report "readword() read error in """ &
L.all & """" severity failure;
end procedure readword_ea;
-- -------------------------------------
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
good: out boolean;
base: in integer:= 2) is
variable itag : string(tag'range);
variable ichar : character;
variable imatch : boolean;
begin
readwhite(L);
for i in val'range loop
val(i) := '0';
end loop;
good := true;
imatch := false;
if L'length > tag'length then
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then
read(L, itag);
read(L, ichar);
readgen(L, val, good, base);
end if;
end if;
match := imatch;
end procedure readtagval;
-- -------------------------------------
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
base: in integer:= 2) is
variable ok : boolean := false;
begin
readtagval(L, tag, match, val, ok, base);
assert ok report "readtagval(std_logic_vector) conversion error in """ &
L.all & """" severity failure;
end procedure readtagval_ea;
-- -------------------------------------
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic;
good: out boolean) is
variable itag : string(tag'range);
variable ichar : character;
variable imatch : boolean;
begin
readwhite(L);
val := '0';
good := true;
imatch := false;
if L'length > tag'length then
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then
read(L, itag);
read(L, ichar);
read(L, val, good);
end if;
end if;
match := imatch;
end procedure readtagval;
-- -------------------------------------
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic) is
variable ok : boolean := false;
begin
readtagval(L, tag, match, val, ok);
assert ok report "readtagval(std_logic) conversion error in """ &
L.all & """" severity failure;
end procedure readtagval_ea;
-- -------------------------------------
procedure readtagval2(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
good: out boolean;
base: in integer:= 2) is
variable itag : string(tag'range);
variable imatch : boolean;
variable igood : boolean;
variable ichar : character;
variable ok : boolean;
begin
readwhite(L);
for i in val1'range loop -- zero val1
val1(i) := '0';
end loop;
for i in val2'range loop -- zero val2
val2(i) := '0';
end loop;
igood := true;
imatch := false;
if L'length > tag'length then -- check for tag
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then -- if found
read(L, itag); -- remove tag
read(L, ichar); -- remove =
igood := false;
readoptchar(L, '-', ok); -- check for tag=-
if ok then
for i in val2'range loop -- set mask to all 1 (ignore)
val2(i) := '1';
end loop;
igood := true;
else -- here if tag=bit[,bit]
readgen(L, val1, igood, base); -- read val1
if igood then
readoptchar(L, ',', ok); -- check(and remove) ,
if ok then
readgen(L, val2, igood, base); -- and read val2
end if;
end if;
end if;
end if;
end if;
match := imatch;
good := igood;
end procedure readtagval2;
-- -------------------------------------
procedure readtagval2_ea(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
base: in integer:= 2) is
variable ok : boolean := false;
begin
readtagval2(L, tag, match, val1, val2, ok, base);
assert ok report "readtagval2() conversion error in """ &
L.all & """" severity failure;
end procedure readtagval2_ea;
-- -------------------------------------
procedure writeoct( -- write slv in octal base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0) is -- field width
variable nbit : integer; -- number of bits
variable ndig : integer; -- number of digits
variable iwidth : integer;
variable ioffset : integer;
variable nibble : std_logic_vector(2 downto 0);
variable ochar : character;
begin
assert not value'ascending(1)
report "writeoct called with ascending range"
severity failure;
nbit := value'length(1);
ndig := (nbit+2)/3;
iwidth := nbit mod 3;
if iwidth = 0 then
iwidth := 3;
end if;
ioffset := value'left(1) - iwidth+1;
if justified=right and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
for i in 0 to ndig-1 loop
nibble := "000";
nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
ochar := ' ';
for i in nibble'range loop
case nibble(i) is
when 'U' => ochar := 'U';
when 'X' => ochar := 'X';
when 'Z' => ochar := 'Z';
when '-' => ochar := '-';
when others => null;
end case;
end loop; -- i
if ochar = ' ' then
write(L,to_integer(unsigned(nibble)));
else
write(L,ochar);
end if;
iwidth := 3;
ioffset := ioffset - 3;
end loop; -- i
if justified=left and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
end procedure writeoct;
-- -------------------------------------
procedure writehex( -- write slv in hex base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0) is -- field width
variable nbit : integer; -- number of bits
variable ndig : integer; -- number of digits
variable iwidth : integer;
variable ioffset : integer;
variable nibble : std_logic_vector(3 downto 0);
variable ochar : character;
variable hextab : string(1 to 16) := "0123456789abcdef";
begin
assert not value'ascending(1)
report "writehex called with ascending range"
severity failure;
nbit := value'length(1);
ndig := (nbit+3)/4;
iwidth := nbit mod 4;
if iwidth = 0 then
iwidth := 4;
end if;
ioffset := value'left(1) - iwidth+1;
if justified=right and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
for i in 0 to ndig-1 loop
nibble := "0000";
nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
ochar := ' ';
for i in nibble'range loop
case nibble(i) is
when 'U' => ochar := 'U';
when 'X' => ochar := 'X';
when 'Z' => ochar := 'Z';
when '-' => ochar := '-';
when others => null;
end case;
end loop; -- i
if ochar = ' ' then
write(L,hextab(to_integer(unsigned(nibble))+1));
else
write(L,ochar);
end if;
iwidth := 4;
ioffset := ioffset - 4;
end loop; -- i
if justified=left and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
end procedure writehex;
-- -------------------------------------
procedure writegen( -- write slv in generic base (arb. lth)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0; -- field width
base: in integer:=2) is -- default base
begin
case base is
when 2 => write(L, value, justified, field);
when 8 => writeoct(L, value, justified, field);
when 16 => writehex(L, value, justified, field);
when others => report "writegen base not 2,8, or 16"
severity failure;
end case;
end procedure writegen;
-- -------------------------------------
procedure writetimestamp(
L: inout line;
clkcyc: in slv31;
str: in string := null_string) is
variable t_nsec : integer := 0;
variable t_psec : integer := 0;
variable t_dnsec : integer := 0;
begin
t_nsec := now / 1 ns;
t_psec := (now - t_nsec * 1 ns) / 1 ps;
t_dnsec := t_psec/100;
-- write(L, now, right, 12);
write(L, t_nsec, right, 8);
write(L,'.');
write(L, t_dnsec, right, 1);
write(L, string'(" ns"));
write(L, to_integer(unsigned(clkcyc)), right, 7);
if str /= null_string then
write(L, str);
end if;
end procedure writetimestamp;
end package body simlib;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ExtIntr_tb is
end ExtIntr_tb;
architecture behavior of ExtIntr_tb is
component ExtIntr
port (
ExtIntrOut_o : out std_logic;
ExtIntrIn_i : in std_logic
);
end component;
signal ExtIntrOut_o : std_logic;
signal ExtIntrIn_i : std_logic;
begin
DUT: ExtIntr
port map (
ExtIntrOut_o => ExtIntrOut_o,
ExtIntrIn_i => ExtIntrIn_i
);
StimulusProc: process
begin
ExtIntrIn_i <= '0';
-- Check constant values of dynamic signals coming out of the application modules
wait for 1 ns;
assert ExtIntrOut_o = ExtIntrIn_i report "Wrong output value" severity failure;
wait for 1 us;
ExtIntrIn_i <= '1';
wait for 1 us;
assert ExtIntrOut_o = ExtIntrIn_i report "Wrong output value" severity failure;
wait for 1 us;
ExtIntrIn_i <= '0';
wait for 1 us;
assert ExtIntrOut_o = ExtIntrIn_i report "Wrong output value" severity failure;
wait for 1 us;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_pixel_1/ball_pixel_sim_netlist.vhdl
-- Design : ball_pixel
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end ball_pixel_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of ball_pixel_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000001950000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000042000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000045300000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000129B92000000000000000000000",
INIT_06 => X"00000000000000000000000000000000000000007AAABB940000000000000000",
INIT_07 => X"00000000000000000000000000000000000000000025ACB9ABB4000000000000",
INIT_08 => X"00000000000000000000000000000000000000000000006BBA9A99A400000000",
INIT_09 => X"40000000000000000000000000000000000000000000000007BBA9ABAAC50000",
INIT_0A => X"ABAA91000000000000000000000000000000000000000000000359BBAA9ABBB8",
INIT_0B => X"9BBA9ABB810000000000000000000000000000000000000000000005BA9ABB99",
INIT_0C => X"BBA9ABA9AABB800000000000000000000000000000000000000000000004ABA9",
INIT_0D => X"029BB99ABA99BB9A920000000000000000000000000000000000000000000038",
INIT_0E => X"000049BB99ABA9ABB99BB9300000000000000000000000000000000000000000",
INIT_0F => X"000000147ABBA9ABAA9ABA9ABC50000000000000000000000000000000000000",
INIT_10 => X"000000000019AA9ABA9ABB99ABA9AC5000000000000000000000000000000000",
INIT_11 => X"0000000000000018BBA9ABA99BBA9ABA9A400000000000000000000000000000",
INIT_12 => X"0000000000000000B209BA9AABA9ABA9AABAAB84000000000000000000000000",
INIT_13 => X"00000000000000000000941AB99BB99ABA99BB99AAA810000000000000000000",
INIT_14 => X"000000000000000000000000149A9ABB99ABA9ABB99BA2110000000000000000",
INIT_15 => X"000000000000000000000000000005CAABBA9ABA9ABBA9AB9000000000000000",
INIT_16 => X"0000000000000000000000000000000006CAABA9ABB99ABA9ABB810000000000",
INIT_17 => X"00068888600000000000000000000000000005AA9ABA99BBA9ABA99A91000000",
INIT_18 => X"0000003FFEEFF30000000000000000000000000005BAAABA9ABA9AABA9B84000",
INIT_19 => X"ABB4000007EF8119FE6000000000000000000000000006CAAB99ABA99BB99AC5",
INIT_1A => X"ABA9AA52000009F866669F8000000000000000000000000005AAAA9ABA9ABB99",
INIT_1B => X"ABB99ABAA810000009E07FF60E8000000000000000000000000005BAAA9ABAA9",
INIT_1C => X"9ABA99BBA9A9AB93000009E07FF60E8000000000000000000000000006CAABA9",
INIT_1D => X"05BAAABA9ABA999ABBB4000009F867768F8000000000000000000000000005AA",
INIT_1E => X"000006CAAB99ABA9A9ABBAA4000007EF8119FE60000000000000000000000000",
INIT_1F => X"0000000005AAAA9ABA9ABA9ABBA40000013FFEEFF30000000000000000000000",
INIT_20 => X"00000000000005BAAA9ABAA9ABA9ABB840000007899870000000000000000000",
INIT_21 => X"000000000000000006CAABA9ABB99ABA9ABB9100000000000000000000000000",
INIT_22 => X"0000000000000000000005B99ABA9ABB99ABA9AA800000000000000000000000",
INIT_23 => X"000000000000000000000000036AA9ABA9ABBA9ABA9AA5100000000000000000",
INIT_24 => X"0000000000000000000000000000000AB99BBA9ABA99BBAABB51100000000000",
INIT_25 => X"240000000000000000000000000000000018AABB99ABA9ABB999ABA893000000",
INIT_26 => X"AA916A200000000000000000000000000000001AB9ABA9ABAA9ABA999ABBA730",
INIT_27 => X"ABB99BB8AB9400000000000000000000000000000019BA9ABA9ABB99ABA999BB",
INIT_28 => X"AABA9AA9ABBAABB4000000000000000000000000000000017CA9ABA99BBA9ABA",
INIT_29 => X"BA99BB99A99ABA9A99A4000000000000000000000000000000005B9AABA9ABA9",
INIT_2A => X"99ABA9ABB99ABAABA9ABAAC5000000000000000000000000000000005AABB99A",
INIT_2B => X"36ABA9ABAA9ABA9AA9ABAA9ABBB8400000000000000000000000000000005BBA",
INIT_2C => X"0000007BBA9ABB99ABA99A9ABB99ABAA91000000000000000000000000000000",
INIT_2D => X"000000000006BBA9ABB99ABA9BA99BBA9ABB8100000000000000000000000000",
INIT_2E => X"00000000000000026ABA9ABBA9ABBBA9ABA9AABB800000000000000000000000",
INIT_2F => X"0000000000000000000007BBA9ABA99BB99ABA99BB9A92000000000000000000",
INIT_30 => X"000000000000000000000000006BABBA9ABB99ABA9ABB99BB930000000000000",
INIT_31 => X"0000000000000000000000000000002558BBA9ABA9ABAA9ABA9ABC5000000000",
INIT_32 => X"000000000000000000000000000000000000049BBA9ABA9ABB99ABA9AC500000",
INIT_33 => X"9B840000000000000000000000000000000000000029CCA9ABA99BBA9ABA9A40",
INIT_34 => X"BBA9ABB91000000000000000000000000000000000000004669BBBA9ABA9AABA",
INIT_35 => X"AAACBAABCAB90000000000000000000000000000000000000000007AA99ABA9A",
INIT_36 => X"04665456545565554200000000000000000000000000000000000000001129CC",
INIT_37 => X"0000000000000000000079000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
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INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
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SIM_DEVICE => "7SERIES",
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SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end ball_pixel_blk_mem_gen_prim_width;
architecture STRUCTURE of ball_pixel_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.ball_pixel_blk_mem_gen_prim_wrapper_init
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ball_pixel_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ball_pixel_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \ball_pixel_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \ball_pixel_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end ball_pixel_blk_mem_gen_generic_cstr;
architecture STRUCTURE of ball_pixel_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.ball_pixel_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\ball_pixel_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
douta(7 downto 0) => douta(11 downto 4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_top : entity is "blk_mem_gen_top";
end ball_pixel_blk_mem_gen_top;
architecture STRUCTURE of ball_pixel_blk_mem_gen_top is
begin
\valid.cstr\: entity work.ball_pixel_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end ball_pixel_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of ball_pixel_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.ball_pixel_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of ball_pixel_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of ball_pixel_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of ball_pixel_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of ball_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of ball_pixel_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of ball_pixel_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.822999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of ball_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of ball_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of ball_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of ball_pixel_blk_mem_gen_v8_3_5 : entity is "ball_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of ball_pixel_blk_mem_gen_v8_3_5 : entity is "ball_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 3600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 3600;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of ball_pixel_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of ball_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of ball_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 3600;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 3600;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of ball_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of ball_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_pixel_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ball_pixel_blk_mem_gen_v8_3_5 : entity is "yes";
end ball_pixel_blk_mem_gen_v8_3_5;
architecture STRUCTURE of ball_pixel_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.ball_pixel_blk_mem_gen_v8_3_5_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_pixel is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ball_pixel : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ball_pixel : entity is "ball_pixel,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ball_pixel : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of ball_pixel : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end ball_pixel;
architecture STRUCTURE of ball_pixel is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.822999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "ball_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "ball_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 3600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 3600;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 3600;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 3600;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.ball_pixel_blk_mem_gen_v8_3_5
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => B"000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <kubakici@wp.pl>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_reg_dumper IS
END tb_reg_dumper;
ARCHITECTURE behavior OF tb_reg_dumper IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_dumper
GENERIC (N_BYTES : integer);
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
Trgr : IN std_logic;
Regs : IN std_logic_vector(N_BYTES*8-1 downto 0);
Request : OUT std_logic;
Grant : IN std_logic;
Byte : OUT std_logic_vector(7 downto 0);
ByteEna : OUT std_logic;
ReaderBusy : IN std_logic
);
END COMPONENT;
COMPONENT uart_tx
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
FreqEn : IN std_logic;
Byte : IN std_logic_vector(7 downto 0);
Kick : IN std_logic;
RsTx : OUT std_logic;
Busy : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '1';
signal Trgr : std_logic := '0';
signal Regs : std_logic_vector(31 downto 0) := X"11223344";
signal Grant : std_logic := '1';
signal ReaderBusy : std_logic := '0';
signal FreqEn : std_logic := '0';
signal Byte : std_logic_vector(7 downto 0) := X"AA";
--Outputs
signal Request : std_logic;
signal ByteEna : std_logic;
signal RsTx : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_dumper
GENERIC MAP ( N_BYTES => 4 )
PORT MAP (
Clk => Clk,
Rst => Rst,
Trgr => Trgr,
Regs => Regs,
Request => Request,
Grant => Grant,
Byte => Byte,
ByteEna => ByteEna,
ReaderBusy => ReaderBusy
);
uut2: uart_tx PORT MAP (
Clk => Clk,
Rst => Rst,
FreqEn => FreqEn,
Byte => Byte,
Kick => ByteEna,
RsTx => RsTx,
Busy => ReaderBusy
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Frequenct enable process
Freq_process :process
begin
FreqEn <= '0';
wait for Clk_period * 2;
FreqEn <= '1';
wait for Clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 20 ns;
Rst <= '0';
Trgr <= '1';
wait for 100 ns;
Trgr <= '0';
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_blkmem.vhd
--
-- Description: This file is the top level wrapper for properly configuring
-- and calling blk_mem_gen_wrapper
--
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_bmg_v1_0_5;
use lib_bmg_v1_0_5.blk_mem_gen_wrapper;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_blkmem is
generic (
C_DATA_WIDTH : integer := 32;
C_ADDR_WIDTH : integer := 9;
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
);
port(
Clk : in std_logic ;--
Rst : in std_logic ;--
--
--
-- Write Port signals --
Wr_Enable : in std_logic ;--
Wr_Req : in std_logic ;--
Wr_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Wr_Data : in std_logic_vector(0 to C_DATA_WIDTH-1) ;--
--
-- Read Port Signals --
Rd_Enable : in std_logic ;--
Rd_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Rd_Data : out std_logic_vector(0 to C_DATA_WIDTH-1) --
);
end axi_vdma_blkmem ;
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_blkmem is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
component xpm_memory_tdpram
generic (
MEMORY_SIZE : integer := 4096;
MEMORY_PRIMITIVE : string := "blockram";
CLOCKING_MODE : string := "common_clock";
ECC_MODE : string := "no_ecc";
MEMORY_INIT_FILE : string := "none";
WAKEUP_TIME : string := "disable_sleep";
MESSAGE_CONTROL : integer := 0;
WRITE_DATA_WIDTH_A : integer := 32;
READ_DATA_WIDTH_A : integer := 32;
BYTE_WRITE_WIDTH_A : integer := 32;
ADDR_WIDTH_A : integer := 12;
READ_RESET_VALUE_A : string := "0";
READ_LATENCY_A : integer := 1;
WRITE_MODE_A : string := "write_first";
WRITE_DATA_WIDTH_B : integer := 32;
READ_DATA_WIDTH_B : integer := 32;
BYTE_WRITE_WIDTH_B : integer := 32;
ADDR_WIDTH_B : integer := 12;
READ_RESET_VALUE_B : string := "0";
READ_LATENCY_B : integer := 1;
WRITE_MODE_B : string := "write_first"
);
port (
-- Common module ports
sleep : in std_logic;
-- Port A module ports
clka : in std_logic;
rsta : in std_logic;
ena : in std_logic;
regcea : in std_logic;
wea : in std_logic_vector (0 downto 0);
addra : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dina : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterra : in std_logic;
injectdbiterra : in std_logic;
douta : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterra : out std_logic;
dbiterra : out std_logic;
-- Port B module ports
clkb : in std_logic;
rstb : in std_logic;
enb : in std_logic;
regceb : in std_logic;
web : in std_logic_vector (0 downto 0);
addrb : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dinb : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterrb : in std_logic;
injectdbiterrb : in std_logic;
doutb : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterrb : out std_logic;
dbiterrb : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
function get_bram_primitive (target_width: integer)
return integer is
variable primitive_blk_mem : integer;
constant prim_type_1bit : integer := 0; -- ( 1-bit wide)
constant prim_type_2bit : integer := 1; -- ( 2-bit wide)
constant prim_type_4bit : integer := 2; -- ( 4-bit wide)
constant prim_type_9bit : integer := 3; -- ( 9-bit wide)
constant prim_type_18bit : integer := 4; -- (18-bit wide)
constant prim_type_36bit : integer := 5; -- (36-bit wide)
constant prim_type_72bit : integer := 6; -- (72-bit wide, single port only)
begin
case target_width Is
when 1 =>
primitive_blk_mem := prim_type_1bit;
when 2 =>
primitive_blk_mem := prim_type_2bit;
when 3 | 4 =>
primitive_blk_mem := prim_type_4bit;
when 5 | 6 | 7 | 8 | 9 =>
primitive_blk_mem := prim_type_9bit;
when 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive_blk_mem := prim_type_18bit;
when others =>
primitive_blk_mem := prim_type_36bit;
end case;
return primitive_blk_mem;
end function get_bram_primitive;
----------------------------------------------------------------------------
-- Constants Declarations
----------------------------------------------------------------------------
constant PRIM_TYPE : integer := get_bram_primitive(C_DATA_WIDTH);
constant MEM_TYPE : integer := 2; -- True dual port RAM
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : integer := 2**C_ADDR_WIDTH;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal port_a_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic_vector(0 downto 0);
signal port_b_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic_vector(0 downto 0);
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
begin
port_a_data_in <= (others => '0');
for i in C_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DATA_WIDTH-1-i);
Rd_Data(C_DATA_WIDTH-1-i) <= port_b_data_out(i);
end loop;
end process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_ADDR_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_ADDR_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_ADDR_WIDTH-1-i);
end loop;
end process TRANSLATE_ADDRESS;
port_a_enable <= Wr_Enable;
port_a_wr_enable(0) <= Wr_Req;
port_b_enable <= Rd_Enable;
port_b_data_in <= (others => '0');
port_b_wr_enable <= (others => '0');
xpm_mem_gen : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_tdpram
generic map (
MEMORY_SIZE => FIFO_DEPTH*C_DATA_WIDTH,
MEMORY_PRIMITIVE => "blockram",
CLOCKING_MODE => "common_clock",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "none",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 1,
WRITE_DATA_WIDTH_A => C_DATA_WIDTH,
READ_DATA_WIDTH_A => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_A => C_DATA_WIDTH,
ADDR_WIDTH_A => C_ADDR_WIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1,
WRITE_MODE_A => "write_first",
WRITE_DATA_WIDTH_B => C_DATA_WIDTH,
READ_DATA_WIDTH_B => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_B => C_DATA_WIDTH,
ADDR_WIDTH_B => C_ADDR_WIDTH,
READ_RESET_VALUE_B => "0",
READ_LATENCY_B => 1,
WRITE_MODE_B => "write_first"
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => Clk,
rsta => Rst,
ena => port_a_enable,
regcea => '0',
wea => port_a_wr_enable,
addra => port_a_addr,
dina => port_a_data_in,
injectsbiterra => '0',
injectdbiterra => '0',
douta => open,
sbiterra => open,
dbiterra => open,
-- Port B module ports
clkb => Clk,
rstb => Rst,
enb => port_b_enable,
regceb => '0',
web => port_b_wr_enable,
addrb => port_b_addr,
dinb => port_b_data_in,
injectsbiterrb => '0',
injectdbiterrb => '0',
doutb => port_b_data_out,
sbiterrb => open,
dbiterrb => open
);
end generate;
blk_mem_gen : if (C_SELECT_XPM = 0) generate
-- For V6 and S6 use block memory generator to
-- generate BRAM
I_BLK_MEM : entity lib_bmg_v1_0_5.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => MEM_TYPE,
c_algorithm => 1,
c_prim_type => PRIM_TYPE,
c_byte_size => 8,
c_sim_collision_check => "All",
c_common_clk => 1,
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0,
c_default_data => "0",
-- Port A Settings
c_has_mem_output_regs_a => 0,
c_has_mux_output_regs_a => 0,
c_write_width_a => C_DATA_WIDTH,
c_read_width_a => C_DATA_WIDTH,
c_write_depth_a => FIFO_DEPTH,
c_read_depth_a => FIFO_DEPTH,
c_addra_width => C_ADDR_WIDTH,
c_write_mode_a => "WRITE_FIRST",
c_has_ena => 1,
c_has_regcea => 0,
c_has_ssra => 0,
c_sinita_val => "0",
c_use_byte_wea => 0,
c_wea_width => 1,
-- Port B Settings
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_b => 0,
c_write_width_b => C_DATA_WIDTH,
c_read_width_b => C_DATA_WIDTH,
c_write_depth_b => FIFO_DEPTH,
c_read_depth_b => FIFO_DEPTH,
c_addrb_width => C_ADDR_WIDTH,
c_write_mode_b => "WRITE_FIRST",
c_has_enb => 1,
c_has_regceb => 0,
c_has_ssrb => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_web_width => 1,
-- Misc Settings
c_mux_pipeline_stages => 0,
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0 -- No use of S3A DSP embedded RAM primitives
)
port map (
clka => Clk ,
ssra => Rst ,
dina => port_a_data_in ,
addra => port_a_addr ,
ena => port_a_enable ,
regcea => '0' ,
wea => port_a_wr_enable ,
douta => open ,
clkb => Clk ,
ssrb => Rst ,
dinb => port_b_data_in ,
addrb => port_b_addr ,
enb => port_b_enable ,
regceb => '0' ,
web => port_b_wr_enable ,
doutb => port_b_data_out ,
dbiterr => open , -- No ECC
sbiterr => open -- No ECC
);
end generate;
end implementation;
|
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_blkmem.vhd
--
-- Description: This file is the top level wrapper for properly configuring
-- and calling blk_mem_gen_wrapper
--
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_bmg_v1_0_5;
use lib_bmg_v1_0_5.blk_mem_gen_wrapper;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_blkmem is
generic (
C_DATA_WIDTH : integer := 32;
C_ADDR_WIDTH : integer := 9;
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
);
port(
Clk : in std_logic ;--
Rst : in std_logic ;--
--
--
-- Write Port signals --
Wr_Enable : in std_logic ;--
Wr_Req : in std_logic ;--
Wr_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Wr_Data : in std_logic_vector(0 to C_DATA_WIDTH-1) ;--
--
-- Read Port Signals --
Rd_Enable : in std_logic ;--
Rd_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Rd_Data : out std_logic_vector(0 to C_DATA_WIDTH-1) --
);
end axi_vdma_blkmem ;
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_blkmem is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
component xpm_memory_tdpram
generic (
MEMORY_SIZE : integer := 4096;
MEMORY_PRIMITIVE : string := "blockram";
CLOCKING_MODE : string := "common_clock";
ECC_MODE : string := "no_ecc";
MEMORY_INIT_FILE : string := "none";
WAKEUP_TIME : string := "disable_sleep";
MESSAGE_CONTROL : integer := 0;
WRITE_DATA_WIDTH_A : integer := 32;
READ_DATA_WIDTH_A : integer := 32;
BYTE_WRITE_WIDTH_A : integer := 32;
ADDR_WIDTH_A : integer := 12;
READ_RESET_VALUE_A : string := "0";
READ_LATENCY_A : integer := 1;
WRITE_MODE_A : string := "write_first";
WRITE_DATA_WIDTH_B : integer := 32;
READ_DATA_WIDTH_B : integer := 32;
BYTE_WRITE_WIDTH_B : integer := 32;
ADDR_WIDTH_B : integer := 12;
READ_RESET_VALUE_B : string := "0";
READ_LATENCY_B : integer := 1;
WRITE_MODE_B : string := "write_first"
);
port (
-- Common module ports
sleep : in std_logic;
-- Port A module ports
clka : in std_logic;
rsta : in std_logic;
ena : in std_logic;
regcea : in std_logic;
wea : in std_logic_vector (0 downto 0);
addra : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dina : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterra : in std_logic;
injectdbiterra : in std_logic;
douta : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterra : out std_logic;
dbiterra : out std_logic;
-- Port B module ports
clkb : in std_logic;
rstb : in std_logic;
enb : in std_logic;
regceb : in std_logic;
web : in std_logic_vector (0 downto 0);
addrb : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dinb : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterrb : in std_logic;
injectdbiterrb : in std_logic;
doutb : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterrb : out std_logic;
dbiterrb : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
function get_bram_primitive (target_width: integer)
return integer is
variable primitive_blk_mem : integer;
constant prim_type_1bit : integer := 0; -- ( 1-bit wide)
constant prim_type_2bit : integer := 1; -- ( 2-bit wide)
constant prim_type_4bit : integer := 2; -- ( 4-bit wide)
constant prim_type_9bit : integer := 3; -- ( 9-bit wide)
constant prim_type_18bit : integer := 4; -- (18-bit wide)
constant prim_type_36bit : integer := 5; -- (36-bit wide)
constant prim_type_72bit : integer := 6; -- (72-bit wide, single port only)
begin
case target_width Is
when 1 =>
primitive_blk_mem := prim_type_1bit;
when 2 =>
primitive_blk_mem := prim_type_2bit;
when 3 | 4 =>
primitive_blk_mem := prim_type_4bit;
when 5 | 6 | 7 | 8 | 9 =>
primitive_blk_mem := prim_type_9bit;
when 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive_blk_mem := prim_type_18bit;
when others =>
primitive_blk_mem := prim_type_36bit;
end case;
return primitive_blk_mem;
end function get_bram_primitive;
----------------------------------------------------------------------------
-- Constants Declarations
----------------------------------------------------------------------------
constant PRIM_TYPE : integer := get_bram_primitive(C_DATA_WIDTH);
constant MEM_TYPE : integer := 2; -- True dual port RAM
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : integer := 2**C_ADDR_WIDTH;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal port_a_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic_vector(0 downto 0);
signal port_b_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic_vector(0 downto 0);
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
begin
port_a_data_in <= (others => '0');
for i in C_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DATA_WIDTH-1-i);
Rd_Data(C_DATA_WIDTH-1-i) <= port_b_data_out(i);
end loop;
end process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_ADDR_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_ADDR_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_ADDR_WIDTH-1-i);
end loop;
end process TRANSLATE_ADDRESS;
port_a_enable <= Wr_Enable;
port_a_wr_enable(0) <= Wr_Req;
port_b_enable <= Rd_Enable;
port_b_data_in <= (others => '0');
port_b_wr_enable <= (others => '0');
xpm_mem_gen : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_tdpram
generic map (
MEMORY_SIZE => FIFO_DEPTH*C_DATA_WIDTH,
MEMORY_PRIMITIVE => "blockram",
CLOCKING_MODE => "common_clock",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "none",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 1,
WRITE_DATA_WIDTH_A => C_DATA_WIDTH,
READ_DATA_WIDTH_A => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_A => C_DATA_WIDTH,
ADDR_WIDTH_A => C_ADDR_WIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1,
WRITE_MODE_A => "write_first",
WRITE_DATA_WIDTH_B => C_DATA_WIDTH,
READ_DATA_WIDTH_B => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_B => C_DATA_WIDTH,
ADDR_WIDTH_B => C_ADDR_WIDTH,
READ_RESET_VALUE_B => "0",
READ_LATENCY_B => 1,
WRITE_MODE_B => "write_first"
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => Clk,
rsta => Rst,
ena => port_a_enable,
regcea => '0',
wea => port_a_wr_enable,
addra => port_a_addr,
dina => port_a_data_in,
injectsbiterra => '0',
injectdbiterra => '0',
douta => open,
sbiterra => open,
dbiterra => open,
-- Port B module ports
clkb => Clk,
rstb => Rst,
enb => port_b_enable,
regceb => '0',
web => port_b_wr_enable,
addrb => port_b_addr,
dinb => port_b_data_in,
injectsbiterrb => '0',
injectdbiterrb => '0',
doutb => port_b_data_out,
sbiterrb => open,
dbiterrb => open
);
end generate;
blk_mem_gen : if (C_SELECT_XPM = 0) generate
-- For V6 and S6 use block memory generator to
-- generate BRAM
I_BLK_MEM : entity lib_bmg_v1_0_5.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => MEM_TYPE,
c_algorithm => 1,
c_prim_type => PRIM_TYPE,
c_byte_size => 8,
c_sim_collision_check => "All",
c_common_clk => 1,
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0,
c_default_data => "0",
-- Port A Settings
c_has_mem_output_regs_a => 0,
c_has_mux_output_regs_a => 0,
c_write_width_a => C_DATA_WIDTH,
c_read_width_a => C_DATA_WIDTH,
c_write_depth_a => FIFO_DEPTH,
c_read_depth_a => FIFO_DEPTH,
c_addra_width => C_ADDR_WIDTH,
c_write_mode_a => "WRITE_FIRST",
c_has_ena => 1,
c_has_regcea => 0,
c_has_ssra => 0,
c_sinita_val => "0",
c_use_byte_wea => 0,
c_wea_width => 1,
-- Port B Settings
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_b => 0,
c_write_width_b => C_DATA_WIDTH,
c_read_width_b => C_DATA_WIDTH,
c_write_depth_b => FIFO_DEPTH,
c_read_depth_b => FIFO_DEPTH,
c_addrb_width => C_ADDR_WIDTH,
c_write_mode_b => "WRITE_FIRST",
c_has_enb => 1,
c_has_regceb => 0,
c_has_ssrb => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_web_width => 1,
-- Misc Settings
c_mux_pipeline_stages => 0,
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0 -- No use of S3A DSP embedded RAM primitives
)
port map (
clka => Clk ,
ssra => Rst ,
dina => port_a_data_in ,
addra => port_a_addr ,
ena => port_a_enable ,
regcea => '0' ,
wea => port_a_wr_enable ,
douta => open ,
clkb => Clk ,
ssrb => Rst ,
dinb => port_b_data_in ,
addrb => port_b_addr ,
enb => port_b_enable ,
regceb => '0' ,
web => port_b_wr_enable ,
doutb => port_b_data_out ,
dbiterr => open , -- No ECC
sbiterr => open -- No ECC
);
end generate;
end implementation;
|
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_blkmem.vhd
--
-- Description: This file is the top level wrapper for properly configuring
-- and calling blk_mem_gen_wrapper
--
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_bmg_v1_0_5;
use lib_bmg_v1_0_5.blk_mem_gen_wrapper;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_blkmem is
generic (
C_DATA_WIDTH : integer := 32;
C_ADDR_WIDTH : integer := 9;
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
);
port(
Clk : in std_logic ;--
Rst : in std_logic ;--
--
--
-- Write Port signals --
Wr_Enable : in std_logic ;--
Wr_Req : in std_logic ;--
Wr_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Wr_Data : in std_logic_vector(0 to C_DATA_WIDTH-1) ;--
--
-- Read Port Signals --
Rd_Enable : in std_logic ;--
Rd_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Rd_Data : out std_logic_vector(0 to C_DATA_WIDTH-1) --
);
end axi_vdma_blkmem ;
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_blkmem is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
component xpm_memory_tdpram
generic (
MEMORY_SIZE : integer := 4096;
MEMORY_PRIMITIVE : string := "blockram";
CLOCKING_MODE : string := "common_clock";
ECC_MODE : string := "no_ecc";
MEMORY_INIT_FILE : string := "none";
WAKEUP_TIME : string := "disable_sleep";
MESSAGE_CONTROL : integer := 0;
WRITE_DATA_WIDTH_A : integer := 32;
READ_DATA_WIDTH_A : integer := 32;
BYTE_WRITE_WIDTH_A : integer := 32;
ADDR_WIDTH_A : integer := 12;
READ_RESET_VALUE_A : string := "0";
READ_LATENCY_A : integer := 1;
WRITE_MODE_A : string := "write_first";
WRITE_DATA_WIDTH_B : integer := 32;
READ_DATA_WIDTH_B : integer := 32;
BYTE_WRITE_WIDTH_B : integer := 32;
ADDR_WIDTH_B : integer := 12;
READ_RESET_VALUE_B : string := "0";
READ_LATENCY_B : integer := 1;
WRITE_MODE_B : string := "write_first"
);
port (
-- Common module ports
sleep : in std_logic;
-- Port A module ports
clka : in std_logic;
rsta : in std_logic;
ena : in std_logic;
regcea : in std_logic;
wea : in std_logic_vector (0 downto 0);
addra : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dina : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterra : in std_logic;
injectdbiterra : in std_logic;
douta : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterra : out std_logic;
dbiterra : out std_logic;
-- Port B module ports
clkb : in std_logic;
rstb : in std_logic;
enb : in std_logic;
regceb : in std_logic;
web : in std_logic_vector (0 downto 0);
addrb : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dinb : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterrb : in std_logic;
injectdbiterrb : in std_logic;
doutb : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterrb : out std_logic;
dbiterrb : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
function get_bram_primitive (target_width: integer)
return integer is
variable primitive_blk_mem : integer;
constant prim_type_1bit : integer := 0; -- ( 1-bit wide)
constant prim_type_2bit : integer := 1; -- ( 2-bit wide)
constant prim_type_4bit : integer := 2; -- ( 4-bit wide)
constant prim_type_9bit : integer := 3; -- ( 9-bit wide)
constant prim_type_18bit : integer := 4; -- (18-bit wide)
constant prim_type_36bit : integer := 5; -- (36-bit wide)
constant prim_type_72bit : integer := 6; -- (72-bit wide, single port only)
begin
case target_width Is
when 1 =>
primitive_blk_mem := prim_type_1bit;
when 2 =>
primitive_blk_mem := prim_type_2bit;
when 3 | 4 =>
primitive_blk_mem := prim_type_4bit;
when 5 | 6 | 7 | 8 | 9 =>
primitive_blk_mem := prim_type_9bit;
when 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive_blk_mem := prim_type_18bit;
when others =>
primitive_blk_mem := prim_type_36bit;
end case;
return primitive_blk_mem;
end function get_bram_primitive;
----------------------------------------------------------------------------
-- Constants Declarations
----------------------------------------------------------------------------
constant PRIM_TYPE : integer := get_bram_primitive(C_DATA_WIDTH);
constant MEM_TYPE : integer := 2; -- True dual port RAM
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : integer := 2**C_ADDR_WIDTH;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal port_a_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic_vector(0 downto 0);
signal port_b_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic_vector(0 downto 0);
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
begin
port_a_data_in <= (others => '0');
for i in C_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DATA_WIDTH-1-i);
Rd_Data(C_DATA_WIDTH-1-i) <= port_b_data_out(i);
end loop;
end process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_ADDR_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_ADDR_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_ADDR_WIDTH-1-i);
end loop;
end process TRANSLATE_ADDRESS;
port_a_enable <= Wr_Enable;
port_a_wr_enable(0) <= Wr_Req;
port_b_enable <= Rd_Enable;
port_b_data_in <= (others => '0');
port_b_wr_enable <= (others => '0');
xpm_mem_gen : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_tdpram
generic map (
MEMORY_SIZE => FIFO_DEPTH*C_DATA_WIDTH,
MEMORY_PRIMITIVE => "blockram",
CLOCKING_MODE => "common_clock",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "none",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 1,
WRITE_DATA_WIDTH_A => C_DATA_WIDTH,
READ_DATA_WIDTH_A => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_A => C_DATA_WIDTH,
ADDR_WIDTH_A => C_ADDR_WIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1,
WRITE_MODE_A => "write_first",
WRITE_DATA_WIDTH_B => C_DATA_WIDTH,
READ_DATA_WIDTH_B => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_B => C_DATA_WIDTH,
ADDR_WIDTH_B => C_ADDR_WIDTH,
READ_RESET_VALUE_B => "0",
READ_LATENCY_B => 1,
WRITE_MODE_B => "write_first"
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => Clk,
rsta => Rst,
ena => port_a_enable,
regcea => '0',
wea => port_a_wr_enable,
addra => port_a_addr,
dina => port_a_data_in,
injectsbiterra => '0',
injectdbiterra => '0',
douta => open,
sbiterra => open,
dbiterra => open,
-- Port B module ports
clkb => Clk,
rstb => Rst,
enb => port_b_enable,
regceb => '0',
web => port_b_wr_enable,
addrb => port_b_addr,
dinb => port_b_data_in,
injectsbiterrb => '0',
injectdbiterrb => '0',
doutb => port_b_data_out,
sbiterrb => open,
dbiterrb => open
);
end generate;
blk_mem_gen : if (C_SELECT_XPM = 0) generate
-- For V6 and S6 use block memory generator to
-- generate BRAM
I_BLK_MEM : entity lib_bmg_v1_0_5.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => MEM_TYPE,
c_algorithm => 1,
c_prim_type => PRIM_TYPE,
c_byte_size => 8,
c_sim_collision_check => "All",
c_common_clk => 1,
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0,
c_default_data => "0",
-- Port A Settings
c_has_mem_output_regs_a => 0,
c_has_mux_output_regs_a => 0,
c_write_width_a => C_DATA_WIDTH,
c_read_width_a => C_DATA_WIDTH,
c_write_depth_a => FIFO_DEPTH,
c_read_depth_a => FIFO_DEPTH,
c_addra_width => C_ADDR_WIDTH,
c_write_mode_a => "WRITE_FIRST",
c_has_ena => 1,
c_has_regcea => 0,
c_has_ssra => 0,
c_sinita_val => "0",
c_use_byte_wea => 0,
c_wea_width => 1,
-- Port B Settings
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_b => 0,
c_write_width_b => C_DATA_WIDTH,
c_read_width_b => C_DATA_WIDTH,
c_write_depth_b => FIFO_DEPTH,
c_read_depth_b => FIFO_DEPTH,
c_addrb_width => C_ADDR_WIDTH,
c_write_mode_b => "WRITE_FIRST",
c_has_enb => 1,
c_has_regceb => 0,
c_has_ssrb => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_web_width => 1,
-- Misc Settings
c_mux_pipeline_stages => 0,
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0 -- No use of S3A DSP embedded RAM primitives
)
port map (
clka => Clk ,
ssra => Rst ,
dina => port_a_data_in ,
addra => port_a_addr ,
ena => port_a_enable ,
regcea => '0' ,
wea => port_a_wr_enable ,
douta => open ,
clkb => Clk ,
ssrb => Rst ,
dinb => port_b_data_in ,
addrb => port_b_addr ,
enb => port_b_enable ,
regceb => '0' ,
web => port_b_wr_enable ,
doutb => port_b_data_out ,
dbiterr => open , -- No ECC
sbiterr => open -- No ECC
);
end generate;
end implementation;
|
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_blkmem.vhd
--
-- Description: This file is the top level wrapper for properly configuring
-- and calling blk_mem_gen_wrapper
--
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_bmg_v1_0_5;
use lib_bmg_v1_0_5.blk_mem_gen_wrapper;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_blkmem is
generic (
C_DATA_WIDTH : integer := 32;
C_ADDR_WIDTH : integer := 9;
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
);
port(
Clk : in std_logic ;--
Rst : in std_logic ;--
--
--
-- Write Port signals --
Wr_Enable : in std_logic ;--
Wr_Req : in std_logic ;--
Wr_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Wr_Data : in std_logic_vector(0 to C_DATA_WIDTH-1) ;--
--
-- Read Port Signals --
Rd_Enable : in std_logic ;--
Rd_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Rd_Data : out std_logic_vector(0 to C_DATA_WIDTH-1) --
);
end axi_vdma_blkmem ;
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_blkmem is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
component xpm_memory_tdpram
generic (
MEMORY_SIZE : integer := 4096;
MEMORY_PRIMITIVE : string := "blockram";
CLOCKING_MODE : string := "common_clock";
ECC_MODE : string := "no_ecc";
MEMORY_INIT_FILE : string := "none";
WAKEUP_TIME : string := "disable_sleep";
MESSAGE_CONTROL : integer := 0;
WRITE_DATA_WIDTH_A : integer := 32;
READ_DATA_WIDTH_A : integer := 32;
BYTE_WRITE_WIDTH_A : integer := 32;
ADDR_WIDTH_A : integer := 12;
READ_RESET_VALUE_A : string := "0";
READ_LATENCY_A : integer := 1;
WRITE_MODE_A : string := "write_first";
WRITE_DATA_WIDTH_B : integer := 32;
READ_DATA_WIDTH_B : integer := 32;
BYTE_WRITE_WIDTH_B : integer := 32;
ADDR_WIDTH_B : integer := 12;
READ_RESET_VALUE_B : string := "0";
READ_LATENCY_B : integer := 1;
WRITE_MODE_B : string := "write_first"
);
port (
-- Common module ports
sleep : in std_logic;
-- Port A module ports
clka : in std_logic;
rsta : in std_logic;
ena : in std_logic;
regcea : in std_logic;
wea : in std_logic_vector (0 downto 0);
addra : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dina : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterra : in std_logic;
injectdbiterra : in std_logic;
douta : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterra : out std_logic;
dbiterra : out std_logic;
-- Port B module ports
clkb : in std_logic;
rstb : in std_logic;
enb : in std_logic;
regceb : in std_logic;
web : in std_logic_vector (0 downto 0);
addrb : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dinb : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterrb : in std_logic;
injectdbiterrb : in std_logic;
doutb : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterrb : out std_logic;
dbiterrb : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
function get_bram_primitive (target_width: integer)
return integer is
variable primitive_blk_mem : integer;
constant prim_type_1bit : integer := 0; -- ( 1-bit wide)
constant prim_type_2bit : integer := 1; -- ( 2-bit wide)
constant prim_type_4bit : integer := 2; -- ( 4-bit wide)
constant prim_type_9bit : integer := 3; -- ( 9-bit wide)
constant prim_type_18bit : integer := 4; -- (18-bit wide)
constant prim_type_36bit : integer := 5; -- (36-bit wide)
constant prim_type_72bit : integer := 6; -- (72-bit wide, single port only)
begin
case target_width Is
when 1 =>
primitive_blk_mem := prim_type_1bit;
when 2 =>
primitive_blk_mem := prim_type_2bit;
when 3 | 4 =>
primitive_blk_mem := prim_type_4bit;
when 5 | 6 | 7 | 8 | 9 =>
primitive_blk_mem := prim_type_9bit;
when 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive_blk_mem := prim_type_18bit;
when others =>
primitive_blk_mem := prim_type_36bit;
end case;
return primitive_blk_mem;
end function get_bram_primitive;
----------------------------------------------------------------------------
-- Constants Declarations
----------------------------------------------------------------------------
constant PRIM_TYPE : integer := get_bram_primitive(C_DATA_WIDTH);
constant MEM_TYPE : integer := 2; -- True dual port RAM
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : integer := 2**C_ADDR_WIDTH;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal port_a_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic_vector(0 downto 0);
signal port_b_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic_vector(0 downto 0);
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
begin
port_a_data_in <= (others => '0');
for i in C_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DATA_WIDTH-1-i);
Rd_Data(C_DATA_WIDTH-1-i) <= port_b_data_out(i);
end loop;
end process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_ADDR_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_ADDR_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_ADDR_WIDTH-1-i);
end loop;
end process TRANSLATE_ADDRESS;
port_a_enable <= Wr_Enable;
port_a_wr_enable(0) <= Wr_Req;
port_b_enable <= Rd_Enable;
port_b_data_in <= (others => '0');
port_b_wr_enable <= (others => '0');
xpm_mem_gen : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_tdpram
generic map (
MEMORY_SIZE => FIFO_DEPTH*C_DATA_WIDTH,
MEMORY_PRIMITIVE => "blockram",
CLOCKING_MODE => "common_clock",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "none",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 1,
WRITE_DATA_WIDTH_A => C_DATA_WIDTH,
READ_DATA_WIDTH_A => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_A => C_DATA_WIDTH,
ADDR_WIDTH_A => C_ADDR_WIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1,
WRITE_MODE_A => "write_first",
WRITE_DATA_WIDTH_B => C_DATA_WIDTH,
READ_DATA_WIDTH_B => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_B => C_DATA_WIDTH,
ADDR_WIDTH_B => C_ADDR_WIDTH,
READ_RESET_VALUE_B => "0",
READ_LATENCY_B => 1,
WRITE_MODE_B => "write_first"
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => Clk,
rsta => Rst,
ena => port_a_enable,
regcea => '0',
wea => port_a_wr_enable,
addra => port_a_addr,
dina => port_a_data_in,
injectsbiterra => '0',
injectdbiterra => '0',
douta => open,
sbiterra => open,
dbiterra => open,
-- Port B module ports
clkb => Clk,
rstb => Rst,
enb => port_b_enable,
regceb => '0',
web => port_b_wr_enable,
addrb => port_b_addr,
dinb => port_b_data_in,
injectsbiterrb => '0',
injectdbiterrb => '0',
doutb => port_b_data_out,
sbiterrb => open,
dbiterrb => open
);
end generate;
blk_mem_gen : if (C_SELECT_XPM = 0) generate
-- For V6 and S6 use block memory generator to
-- generate BRAM
I_BLK_MEM : entity lib_bmg_v1_0_5.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => MEM_TYPE,
c_algorithm => 1,
c_prim_type => PRIM_TYPE,
c_byte_size => 8,
c_sim_collision_check => "All",
c_common_clk => 1,
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0,
c_default_data => "0",
-- Port A Settings
c_has_mem_output_regs_a => 0,
c_has_mux_output_regs_a => 0,
c_write_width_a => C_DATA_WIDTH,
c_read_width_a => C_DATA_WIDTH,
c_write_depth_a => FIFO_DEPTH,
c_read_depth_a => FIFO_DEPTH,
c_addra_width => C_ADDR_WIDTH,
c_write_mode_a => "WRITE_FIRST",
c_has_ena => 1,
c_has_regcea => 0,
c_has_ssra => 0,
c_sinita_val => "0",
c_use_byte_wea => 0,
c_wea_width => 1,
-- Port B Settings
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_b => 0,
c_write_width_b => C_DATA_WIDTH,
c_read_width_b => C_DATA_WIDTH,
c_write_depth_b => FIFO_DEPTH,
c_read_depth_b => FIFO_DEPTH,
c_addrb_width => C_ADDR_WIDTH,
c_write_mode_b => "WRITE_FIRST",
c_has_enb => 1,
c_has_regceb => 0,
c_has_ssrb => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_web_width => 1,
-- Misc Settings
c_mux_pipeline_stages => 0,
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0 -- No use of S3A DSP embedded RAM primitives
)
port map (
clka => Clk ,
ssra => Rst ,
dina => port_a_data_in ,
addra => port_a_addr ,
ena => port_a_enable ,
regcea => '0' ,
wea => port_a_wr_enable ,
douta => open ,
clkb => Clk ,
ssrb => Rst ,
dinb => port_b_data_in ,
addrb => port_b_addr ,
enb => port_b_enable ,
regceb => '0' ,
web => port_b_wr_enable ,
doutb => port_b_data_out ,
dbiterr => open , -- No ECC
sbiterr => open -- No ECC
);
end generate;
end implementation;
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant1.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant1 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant1;
ARCHITECTURE SYN OF lpm_constant1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=aas",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "aas"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=aas"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
entity file10 is
end entity;
architecture test of file10 is
type rec is record
x : integer;
s : string(1 to 5);
end record;
type rec_array is array (natural range <>) of rec;
type rf is file of rec_array;
begin
p1: process is
file f : rf;
variable v : rec_array(1 to 2);
variable len : integer;
begin
file_open(f, "file.bin", write_mode);
write(f, ((1, "hello"), (2, "world")));
file_close(f);
file_open(f, "file.bin", read_mode);
read(f, v, len);
assert len = 2;
assert v(1) = (1, "hello");
assert v(2) = (2, "world");
file_close(f);
wait;
end process;
end architecture;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone DMA Streaming Interface
---------------------------------------------------------------------------------------
-- File : xdma_interface_wb.vhd
-- Author : auto-generated by wbgen2 from xdma_interface_wb.wb
-- Created : Thu Sep 27 15:39:56 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xdma_interface_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.dma_iface_wbgen2_pkg.all;
entity wb_dma_interface_port is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
data_clk_i : in std_logic;
dma_clk_i : in std_logic;
regs_i : in t_dma_iface_in_registers;
regs_o : out t_dma_iface_out_registers
);
end wb_dma_interface_port;
architecture syn of wb_dma_interface_port is
signal dma_iface_ctl_start_int : std_logic ;
signal dma_iface_ctl_start_int_delay : std_logic ;
signal dma_iface_ctl_start_sync0 : std_logic ;
signal dma_iface_ctl_start_sync1 : std_logic ;
signal dma_iface_ctl_start_sync2 : std_logic ;
signal dma_iface_ctl_done_sync0 : std_logic ;
signal dma_iface_ctl_done_sync1 : std_logic ;
signal dma_iface_ctl_ovf_sync0 : std_logic ;
signal dma_iface_ctl_ovf_sync1 : std_logic ;
signal dma_iface_tr_cntr_int : std_logic_vector(31 downto 0);
signal dma_iface_tr_cntr_swb : std_logic ;
signal dma_iface_tr_cntr_swb_delay : std_logic ;
signal dma_iface_tr_cntr_swb_s0 : std_logic ;
signal dma_iface_tr_cntr_swb_s1 : std_logic ;
signal dma_iface_tr_cntr_swb_s2 : std_logic ;
signal dma_iface_fifo_c2b_rst_n : std_logic ;
signal dma_iface_fifo_c2b_in_int : std_logic_vector(32 downto 0);
signal dma_iface_fifo_c2b_out_int : std_logic_vector(32 downto 0);
signal dma_iface_fifo_c2b_rdreq_int : std_logic ;
signal dma_iface_fifo_c2b_rdreq_int_d0 : std_logic ;
signal dma_iface_fifo_b2c_rst_n : std_logic ;
signal dma_iface_fifo_b2c_in_int : std_logic_vector(31 downto 0);
signal dma_iface_fifo_b2c_out_int : std_logic_vector(31 downto 0);
signal dma_iface_fifo_b2c_wrreq_int : std_logic ;
signal dma_iface_fifo_c2b_full_int : std_logic ;
signal dma_iface_fifo_c2b_empty_int : std_logic ;
signal dma_iface_fifo_c2b_usedw_int : std_logic_vector(7 downto 0);
signal dma_iface_fifo_b2c_full_int : std_logic ;
signal dma_iface_fifo_b2c_empty_int : std_logic ;
signal dma_iface_fifo_b2c_usedw_int : std_logic_vector(7 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dma_iface_ctl_start_int <= '0';
dma_iface_ctl_start_int_delay <= '0';
dma_iface_tr_cntr_int <= "00000000000000000000000000000000";
dma_iface_tr_cntr_swb <= '0';
dma_iface_tr_cntr_swb_delay <= '0';
dma_iface_fifo_c2b_rdreq_int <= '0';
dma_iface_fifo_b2c_wrreq_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dma_iface_fifo_b2c_wrreq_int <= '0';
ack_in_progress <= '0';
else
dma_iface_ctl_start_int <= dma_iface_ctl_start_int_delay;
dma_iface_ctl_start_int_delay <= '0';
dma_iface_tr_cntr_swb <= dma_iface_tr_cntr_swb_delay;
dma_iface_tr_cntr_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
dma_iface_ctl_start_int <= wrdata_reg(0);
dma_iface_ctl_start_int_delay <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= dma_iface_ctl_done_sync1;
rddata_reg(2) <= dma_iface_ctl_ovf_sync1;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
dma_iface_tr_cntr_int <= wrdata_reg(31 downto 0);
dma_iface_tr_cntr_swb <= '1';
dma_iface_tr_cntr_swb_delay <= '1';
end if;
rddata_reg(31 downto 0) <= dma_iface_tr_cntr_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
end if;
if (dma_iface_fifo_c2b_rdreq_int_d0 = '0') then
dma_iface_fifo_c2b_rdreq_int <= not dma_iface_fifo_c2b_rdreq_int;
else
rddata_reg(31 downto 0) <= dma_iface_fifo_c2b_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= dma_iface_fifo_c2b_out_int(32);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dma_iface_fifo_c2b_full_int;
rddata_reg(17) <= dma_iface_fifo_c2b_empty_int;
rddata_reg(7 downto 0) <= dma_iface_fifo_c2b_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
dma_iface_fifo_b2c_in_int(31 downto 0) <= wrdata_reg(31 downto 0);
dma_iface_fifo_b2c_wrreq_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dma_iface_fifo_b2c_full_int;
rddata_reg(17) <= dma_iface_fifo_b2c_empty_int;
rddata_reg(7 downto 0) <= dma_iface_fifo_b2c_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Start Transaction
process (data_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ctl_start_o <= '0';
dma_iface_ctl_start_sync0 <= '0';
dma_iface_ctl_start_sync1 <= '0';
dma_iface_ctl_start_sync2 <= '0';
elsif rising_edge(data_clk_i) then
dma_iface_ctl_start_sync0 <= dma_iface_ctl_start_int;
dma_iface_ctl_start_sync1 <= dma_iface_ctl_start_sync0;
dma_iface_ctl_start_sync2 <= dma_iface_ctl_start_sync1;
regs_o.ctl_start_o <= dma_iface_ctl_start_sync2 and (not dma_iface_ctl_start_sync1);
end if;
end process;
-- DMA complete
-- synchronizer chain for field : DMA complete (type RO/WO, dma_clk_i -> clk_sys_i)
process (dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_iface_ctl_done_sync0 <= '0';
dma_iface_ctl_done_sync1 <= '0';
elsif rising_edge(dma_clk_i) then
dma_iface_ctl_done_sync0 <= regs_i.ctl_done_i;
dma_iface_ctl_done_sync1 <= dma_iface_ctl_done_sync0;
end if;
end process;
-- DMA overflow
-- synchronizer chain for field : DMA overflow (type RO/WO, dma_clk_i -> clk_sys_i)
process (dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_iface_ctl_ovf_sync0 <= '0';
dma_iface_ctl_ovf_sync1 <= '0';
elsif rising_edge(dma_clk_i) then
dma_iface_ctl_ovf_sync0 <= regs_i.ctl_ovf_i;
dma_iface_ctl_ovf_sync1 <= dma_iface_ctl_ovf_sync0;
end if;
end process;
-- Transactions Counter
-- asynchronous std_logic_vector register : Transactions Counter (type RW/RO, data_clk_i <-> clk_sys_i)
process (data_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_iface_tr_cntr_swb_s0 <= '0';
dma_iface_tr_cntr_swb_s1 <= '0';
dma_iface_tr_cntr_swb_s2 <= '0';
regs_o.tr_cntr_o <= "00000000000000000000000000000000";
elsif rising_edge(data_clk_i) then
dma_iface_tr_cntr_swb_s0 <= dma_iface_tr_cntr_swb;
dma_iface_tr_cntr_swb_s1 <= dma_iface_tr_cntr_swb_s0;
dma_iface_tr_cntr_swb_s2 <= dma_iface_tr_cntr_swb_s1;
if ((dma_iface_tr_cntr_swb_s2 = '0') and (dma_iface_tr_cntr_swb_s1 = '1')) then
regs_o.tr_cntr_o <= dma_iface_tr_cntr_int;
end if;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO C2B (Core -> DMA) synchronization
dma_iface_fifo_c2b_in_int(31 downto 0) <= regs_i.fifo_c2b_data_i;
dma_iface_fifo_c2b_in_int(32) <= regs_i.fifo_c2b_last_i;
dma_iface_fifo_c2b_rst_n <= rst_n_i;
dma_iface_fifo_c2b_INST : wbgen2_fifo_async
generic map (
g_size => 256,
g_width => 33,
g_usedw_size => 8
)
port map (
wr_req_i => regs_i.fifo_c2b_wr_req_i,
wr_full_o => regs_o.fifo_c2b_wr_full_o,
wr_empty_o => regs_o.fifo_c2b_wr_empty_o,
wr_usedw_o => regs_o.fifo_c2b_wr_usedw_o,
rd_full_o => dma_iface_fifo_c2b_full_int,
rd_empty_o => dma_iface_fifo_c2b_empty_int,
rd_usedw_o => dma_iface_fifo_c2b_usedw_int,
rd_req_i => dma_iface_fifo_c2b_rdreq_int,
rst_n_i => dma_iface_fifo_c2b_rst_n,
wr_clk_i => dma_clk_i,
rd_clk_i => clk_sys_i,
wr_data_i => dma_iface_fifo_c2b_in_int,
rd_data_o => dma_iface_fifo_c2b_out_int
);
-- extra code for reg/fifo/mem: FIFO B2C (Bus -> Core) synchronization
regs_o.fifo_b2c_data_o <= dma_iface_fifo_b2c_out_int(31 downto 0);
dma_iface_fifo_b2c_rst_n <= rst_n_i;
dma_iface_fifo_b2c_INST : wbgen2_fifo_async
generic map (
g_size => 256,
g_width => 32,
g_usedw_size => 8
)
port map (
rd_req_i => regs_i.fifo_b2c_rd_req_i,
rd_full_o => regs_o.fifo_b2c_rd_full_o,
rd_empty_o => regs_o.fifo_b2c_rd_empty_o,
rd_usedw_o => regs_o.fifo_b2c_rd_usedw_o,
wr_full_o => dma_iface_fifo_b2c_full_int,
wr_empty_o => dma_iface_fifo_b2c_empty_int,
wr_usedw_o => dma_iface_fifo_b2c_usedw_int,
wr_req_i => dma_iface_fifo_b2c_wrreq_int,
rst_n_i => dma_iface_fifo_b2c_rst_n,
rd_clk_i => data_clk_i,
wr_clk_i => clk_sys_i,
wr_data_i => dma_iface_fifo_b2c_in_int,
rd_data_o => dma_iface_fifo_b2c_out_int
);
-- extra code for reg/fifo/mem: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_iface_fifo_c2b_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dma_iface_fifo_c2b_rdreq_int_d0 <= dma_iface_fifo_c2b_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1
-- extra code for reg/fifo/mem: FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1884.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01884ent IS
END c07s01b00x00p08n01i01884ent;
ARCHITECTURE c07s01b00x00p08n01i01884arch OF c07s01b00x00p08n01i01884ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal s_int : small_int;
signal obus : cmd_bus(small_int);
BEGIN
blk : block (s_int = 0)
begin
end block blk;
TESTING : PROCESS
BEGIN
obus <= (0 => blk, others => 5) after 5 ns; -- block label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01884 - Block labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01884arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1884.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01884ent IS
END c07s01b00x00p08n01i01884ent;
ARCHITECTURE c07s01b00x00p08n01i01884arch OF c07s01b00x00p08n01i01884ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal s_int : small_int;
signal obus : cmd_bus(small_int);
BEGIN
blk : block (s_int = 0)
begin
end block blk;
TESTING : PROCESS
BEGIN
obus <= (0 => blk, others => 5) after 5 ns; -- block label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01884 - Block labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01884arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1884.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01884ent IS
END c07s01b00x00p08n01i01884ent;
ARCHITECTURE c07s01b00x00p08n01i01884arch OF c07s01b00x00p08n01i01884ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal s_int : small_int;
signal obus : cmd_bus(small_int);
BEGIN
blk : block (s_int = 0)
begin
end block blk;
TESTING : PROCESS
BEGIN
obus <= (0 => blk, others => 5) after 5 ns; -- block label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01884 - Block labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01884arch;
|
library ieee;
library ieee;
|
library ieee;
library ieee;
|
library ieee;
library ieee;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc595.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:17 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00595ent IS
END c03s04b01x00p01n01i00595ent;
ARCHITECTURE c03s04b01x00p01n01i00595arch OF c03s04b01x00p01n01i00595ent IS
constant C1 : boolean := true;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_st is boolean_vector(0 to 15);
type boolean_vector_st_file is file of boolean_vector_st;
constant C27 : boolean_vector_st := (others => C1);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : boolean_vector_st_file open read_mode is "iofile.28";
variable v : boolean_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00595"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00595 - File reading operation (boolean_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00595arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc595.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:17 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00595ent IS
END c03s04b01x00p01n01i00595ent;
ARCHITECTURE c03s04b01x00p01n01i00595arch OF c03s04b01x00p01n01i00595ent IS
constant C1 : boolean := true;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_st is boolean_vector(0 to 15);
type boolean_vector_st_file is file of boolean_vector_st;
constant C27 : boolean_vector_st := (others => C1);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : boolean_vector_st_file open read_mode is "iofile.28";
variable v : boolean_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00595"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00595 - File reading operation (boolean_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00595arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc595.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:17 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00595ent IS
END c03s04b01x00p01n01i00595ent;
ARCHITECTURE c03s04b01x00p01n01i00595arch OF c03s04b01x00p01n01i00595ent IS
constant C1 : boolean := true;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_st is boolean_vector(0 to 15);
type boolean_vector_st_file is file of boolean_vector_st;
constant C27 : boolean_vector_st := (others => C1);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : boolean_vector_st_file open read_mode is "iofile.28";
variable v : boolean_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00595"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00595 - File reading operation (boolean_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00595arch;
|
-------------------------------------------------------------------------------
-- system_sws_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_sws_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_sws_8bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_sws_8bits_wrapper;
architecture STRUCTURE of system_sws_8bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
SWs_8Bits : axi_gpio
generic map (
C_FAMILY => "zynq",
C_INSTANCE => "SWs_8Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_sws_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_sws_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_sws_8bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_sws_8bits_wrapper;
architecture STRUCTURE of system_sws_8bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
SWs_8Bits : axi_gpio
generic map (
C_FAMILY => "zynq",
C_INSTANCE => "SWs_8Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_sws_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_sws_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_sws_8bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_sws_8bits_wrapper;
architecture STRUCTURE of system_sws_8bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
SWs_8Bits : axi_gpio
generic map (
C_FAMILY => "zynq",
C_INSTANCE => "SWs_8Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
clk125 : in std_logic;
errorn : out std_logic;
flash_rstn : out std_logic;
addr : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(15 downto 0);
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
romsn : out std_logic;
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_logic; -- ddr write enable
ddr_rasb : out std_logic; -- ddr ras
ddr_casb : out std_logic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1+CFG_PCI;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, clkml, rstn, rstraw, pciclk, clkddr, ddrlock : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, rst, ndsuact : std_logic;
signal tck, tckn, tms, tdi, tdo : std_logic;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
signal lresetn, lclk125, lock : std_logic;
constant BOARD_FREQ : integer := 40000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
constant DDR_FREQ : integer := 125; --(CFG_DDRSP_FREQ/10)*10; -- DDR frequency in MHz
signal stati : ahbstat_in_type;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, CFG_PCI,
CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 0)
port map (lclk, pci_clk, clkm, open, open, open, pciclk, cgi, cgo);
resetn_pad : clkpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
flash_rstn_pad : outpad generic map (tech => padtech)
port map (flash_rstn, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0: ahbuart -- Debug UART
-- generic map (hindex => NCPU, pindex => 7, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
-- end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ramaddr => 16#C00#, rammask => 16#FFF#, iomask => 0,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (addr, memo.address(28 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
writen_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk125, lclk125);
ddr0 : ddrspa generic map (
fabtech => virtex2, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => DDR_FREQ,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000 )
port map (lresetn, rstn, lclk125, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk <= ddr_clkv(1 downto 0); ddr_clkb <= ddr_clkbv(1 downto 0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 16)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
nopads : if CFG_AHB_UART = 0 generate
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
upads : if CFG_AHB_UART = 1 generate
u1i.rxd <= u1o.txd;
end generate;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
-- pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
-- port map (pci_clk, pciclk);
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 7, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet Virtex2 XC2V1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 00:53:18
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/controller/col_mach.v
-- Component name : col_mach
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
library UNISIM;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use UNISIM.VCOMPONENTS.all;
-- The column machine manages the dq bus. Since there is a single DQ
-- bus, and the column part of the DRAM is tightly coupled to this DQ
-- bus, conceptually, the DQ bus and all of the column hardware in
-- a multi rank DRAM array are managed as a single unit.
--
--
-- The column machine does not "enforce" the column timing directly.
-- It generates information and sends it to the bank machines. If the
-- bank machines incorrectly make a request, the column machine will
-- simply overwrite the existing request with the new request even
-- if this would result in a timing or protocol violation.
--
-- The column machine
-- hosts the block that controls read and write data transfer
-- to and from the dq bus.
--
-- And if configured, there is provision for tracking the address
-- of a command as it moves through the column pipeline. This
-- address will be logged for detected ECC errors.
entity col_mach is
generic (
TCQ : integer := 100;
BANK_WIDTH : integer := 3;
BURST_MODE : string := "8";
COL_WIDTH : integer := 12;
CS_WIDTH : integer := 4;
DATA_BUF_ADDR_WIDTH : integer := 8;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DELAY_WR_DATA_CNTRL : integer := 0;
DQS_WIDTH : integer := 8;
DRAM_TYPE : string := "DDR3";
EARLY_WR_DATA_ADDR : string := "OFF";
ECC : string := "OFF";
MC_ERR_ADDR_WIDTH : integer := 31;
nCK_PER_CLK : integer := 2;
nPHY_WRLAT : integer := 0;
nRD_EN2CNFG_WR : integer := 6;
nWR_EN2CNFG_RD : integer := 4;
nWR_EN2CNFG_WR : integer := 4;
RANK_WIDTH : integer := 2;
ROW_WIDTH : integer := 16
);
port (
-- Outputs
-- Inputs
dq_busy_data : out std_logic; -- = 1'b0;
-- The following generates a column command disable based mostly on the type
-- of DRAM and the fabric to DRAM CK ratio.
-- This generates a data offset based on fabric clock to DRAM CK ratio and
-- the size bit. Note that this is different that the dq_busy_data signal
-- generated above.
wr_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
dfi_wrdata_en : out std_logic_vector(DQS_WIDTH - 1 downto 0);
wr_data_en : out std_logic;
wr_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
dfi_rddata_en : out std_logic_vector(DQS_WIDTH - 1 downto 0);
inhbt_wr_config : out std_logic;
inhbt_rd_config : out std_logic;
rd_rmw : out std_logic;
ecc_err_addr : out std_logic_vector(MC_ERR_ADDR_WIDTH - 1 downto 0);
ecc_status_valid : out std_logic;
wr_ecc_buf : out std_logic;
rd_data_end : out std_logic;
rd_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rd_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
rd_data_en : out std_logic;
clk : in std_logic;
rst : in std_logic;
sent_col : in std_logic;
col_size : in std_logic;
io_config : in std_logic_vector(RANK_WIDTH downto 0);
col_wr_data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
dfi_rddata_valid : in std_logic;
col_periodic_rd : in std_logic;
col_data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
col_rmw : in std_logic;
col_ra : in std_logic_vector(RANK_WIDTH - 1 downto 0);
col_ba : in std_logic_vector(BANK_WIDTH - 1 downto 0);
col_row : in std_logic_vector(ROW_WIDTH - 1 downto 0);
col_a : in std_logic_vector(ROW_WIDTH - 1 downto 0)
);
end entity col_mach;
architecture trans of col_mach is
component RAM32M
generic (
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
DOC : out std_logic_vector (1 downto 0);
DOD : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector(4 downto 0);
ADDRB : in std_logic_vector(4 downto 0);
ADDRC : in std_logic_vector(4 downto 0);
ADDRD : in std_logic_vector(4 downto 0);
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
DIC : in std_logic_vector (1 downto 0);
DID : in std_logic_vector (1 downto 0);
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
function nCOPY (A : in std_logic; B : in integer) return std_logic_vector is
variable tmp : std_logic_vector(B - 1 downto 0);
begin
for i in 0 to B - 1 loop
tmp(i) := A;
end loop;
return tmp;
end function nCOPY;
function clogb2(size: integer) return integer is
variable tmp : integer := 1;
variable tmp_size : std_logic_vector (31 downto 0);
begin
tmp_size := std_logic_vector(TO_UNSIGNED((size - 1),32));
while ( to_integer(UNSIGNED(tmp_size)) > 1 ) loop
tmp_size := std_logic_vector(UNSIGNED(tmp_size) srl 1);
tmp := tmp + 1;
end loop;
return tmp;
--for i in 23 downto 0 loop
-- if( size <= 2** i) then
-- tmp := i;
-- end if;
--end loop;
--return tmp;
end function clogb2;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
function f_FIFO_WIDTH (DATA_BUF_ADDR_WIDTH: integer; DATA_BUF_OFFSET_WIDTH : integer ;MC_ERR_LINE_WIDTH : integer; ECC : string)
return integer is
begin
if (ECC = "OFF") then
return ( 1 + 1 + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH );
else
return (1 + 1 + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + 1 + MC_ERR_LINE_WIDTH);
end if;
end function f_FIFO_WIDTH;
function f_RAM_CNT (FULL_RAM_CNT: integer; REMAINDER : integer )
return integer is
begin
if (REMAINDER = 0) then
return ( FULL_RAM_CNT );
else
return ( FULL_RAM_CNT + 1);
end if;
end function f_RAM_CNT;
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
constant ONE : integer := 1;
constant nRD_EN2CNFG_WR_LOCAL : integer := nRD_EN2CNFG_WR - 2;
constant nWR_EN2CNFG_WR_LOCAL : integer := nWR_EN2CNFG_WR - 2;
constant WR_WAIT_CNT_WIDTH : integer := clogb2(nRD_EN2CNFG_WR_LOCAL + 1);
constant nWR_EN2CNFG_RD_LOCAL : integer := nWR_EN2CNFG_RD - 2;
constant RD_WAIT_CNT_WIDTH : integer := clogb2(nWR_EN2CNFG_RD_LOCAL + 1);
constant MC_ERR_LINE_WIDTH : integer := MC_ERR_ADDR_WIDTH - DATA_BUF_OFFSET_WIDTH;
constant FIFO_WIDTH : integer := f_FIFO_WIDTH(DATA_BUF_ADDR_WIDTH ,DATA_BUF_OFFSET_WIDTH ,MC_ERR_LINE_WIDTH,ECC );
constant FULL_RAM_CNT : integer := (FIFO_WIDTH / 6);
constant REMAINDER : integer := FIFO_WIDTH mod 6;
constant RAM_CNT : integer := f_RAM_CNT(FULL_RAM_CNT ,REMAINDER ) ;
constant RAM_WIDTH : integer := (RAM_CNT * 6);
signal ecc_err_addr_ns : std_logic_vector(MC_ERR_ADDR_WIDTH - 1 downto 0);
signal offset_r : std_logic_vector(1 downto 0) := "00";
signal offset_ns : std_logic_vector(1 downto 0) := "00";
signal data_end : std_logic;
signal offset_r1 : std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0) := (others => '0' );
signal sent_col_r1 : std_logic;
signal wrdata_en : std_logic;
signal read_data_valid : std_logic;
signal cnfg_wr_wait_r : std_logic_vector(WR_WAIT_CNT_WIDTH - 1 downto 0);
signal cnfg_wr_wait_ns : std_logic_vector(WR_WAIT_CNT_WIDTH - 1 downto 0);
signal cnfg_rd_wait_r : std_logic_vector(RD_WAIT_CNT_WIDTH - 1 downto 0);
signal cnfg_rd_wait_ns : std_logic_vector(RD_WAIT_CNT_WIDTH - 1 downto 0);
signal inhbt_wr_config_ns : std_logic;
signal inhbt_wr_config_r : std_logic;
signal inhbt_rd_config_ns : std_logic;
signal inhbt_rd_config_r : std_logic;
signal col_a_full : std_logic_vector(11 downto 0);
signal col_a_extracted : std_logic_vector(COL_WIDTH - 1 downto 0);
signal granted_col_d_r : std_logic_vector(1 downto 0);
signal granted_col_d_ns : std_logic_vector(1 downto 0);
signal col_wr_data_buf_addr_r : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal ecc_line : std_logic_vector(MC_ERR_LINE_WIDTH downto 0);
signal rd_data_en_ns : std_logic;
signal real_fifo_data : std_logic_vector(FIFO_WIDTH - 1 downto 0);
signal fifo_in_data : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal fifo_in_data_r : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal fifo_out_data : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal fifo_out_data_ns : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal fifo_out_data_r : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal rd_data_end_ns : std_logic;
signal periodic_rd : std_logic;
signal rd_data_addr_ns : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal rd_data_offset_ns : std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
signal ecc_status_valid_ns : std_logic;
signal wr_ecc_buf_ns : std_logic;
signal head_ns,head_r : std_logic_vector(4 downto 0);
signal head_r1 : std_logic_vector(4 downto 0);
signal tail_ns,tail_r : std_logic_vector(4 downto 0);
signal int8 : std_logic;
-- Declare intermediate signals for referenced outputs
signal rd_rmw_int3 : std_logic;
signal rd_data_end_int1 : std_logic;
signal rd_data_addr_int0 : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal rd_data_offset_int2 : std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
--this signal is defined to initialize the dq_busy_data with a value of 0. for conditions where none of the generate block is triggered.
signal dq_busy_data_temp : std_logic := '0';
begin
-- Drive referenced outputs
rd_rmw <= rd_rmw_int3;
rd_data_end <= rd_data_end_int1;
rd_data_addr <= rd_data_addr_int0;
rd_data_offset <= rd_data_offset_int2;
dq_busy_data <= dq_busy_data_temp ;
int4 : if ((nCK_PER_CLK = 1) and ((BURST_MODE = "8") or (DRAM_TYPE = "DDR3"))) generate
granted_col_d_ns <= (sent_col & granted_col_d_r(1));
process (clk)
begin
if (clk'event and clk = '1') then
granted_col_d_r <= granted_col_d_ns after (TCQ)*1 ps;
end if;
end process;
process (granted_col_d_r, sent_col)
begin
dq_busy_data_temp <= sent_col or REDUCTION_OR(granted_col_d_r);
end process;
end generate;
int5 : if (((nCK_PER_CLK = 2) and ((BURST_MODE = "8") or (DRAM_TYPE = "DDR3"))) or ((nCK_PER_CLK = 1) and ((BURST_MODE = "4") or (DRAM_TYPE = "DDR2")))) generate
process (sent_col)
begin
dq_busy_data_temp <= sent_col;
end process;
end generate;
data_valid_1_1 : if (DATA_BUF_OFFSET_WIDTH = 2) generate
process (col_size, offset_r, rst, sent_col)
begin
if (rst = '1') then
offset_ns <= (others => '0');
else
offset_ns <= offset_r;
if (sent_col = '1') then
offset_ns <= "01";
elsif ((REDUCTION_OR(offset_r)) = '1' and (offset_r /= (col_size & '1'))) then
offset_ns <= offset_r + '1';
else
offset_ns <= "00";
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
offset_r <= offset_ns after (TCQ)*1 ps;
end if;
end process;
data_end <= BOOLEAN_TO_STD_LOGIC(offset_r = "11") when (col_size = '1') else
offset_r(0);
end generate;
--
data_valid_2_1 : if (not(DATA_BUF_OFFSET_WIDTH = 2)) generate
-- int8 <= '0' when (rst = '1') else
-- sent_col and col_size;
process (col_size, rst, sent_col)
begin
if (rst = '1') then
offset_ns(0) <= '0';
else
offset_ns(0) <= sent_col and col_size;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
offset_r(0) <= offset_ns(0) after (TCQ)*1 ps;
end if;
end process;
data_end <= offset_r(0) when (col_size = '1') else
'1';
end generate;
offset_pipe : if ((nPHY_WRLAT = 1) or (DELAY_WR_DATA_CNTRL = 1)) generate
process (clk)
begin
if (clk'event and clk = '1') then
offset_r1 <= offset_r(DATA_BUF_OFFSET_WIDTH - 1 downto 0) after (TCQ)*1 ps;
end if;
end process;
end generate;
wr_data_offset <= offset_r1(DATA_BUF_OFFSET_WIDTH - 1 downto 0) when (DELAY_WR_DATA_CNTRL = 1) else
offset_r(DATA_BUF_OFFSET_WIDTH - 1 downto 0) when (EARLY_WR_DATA_ADDR = "OFF") else
offset_ns(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
process (clk)
begin
if (clk'event and clk = '1') then
sent_col_r1 <= sent_col after (TCQ)*1 ps;
end if;
end process;
wrdata_en <= ((sent_col or REDUCTION_OR(offset_r)) and io_config(RANK_WIDTH)) when (nPHY_WRLAT = 0) else
((sent_col_r1 or REDUCTION_OR(offset_r1)) and io_config(RANK_WIDTH));
dfi_wrdata_en <= nCOPY(wrdata_en,DQS_WIDTH);
-- BAD
wr_data_en <= ((sent_col_r1 or REDUCTION_OR(offset_r1)) and io_config(RANK_WIDTH)) when (DELAY_WR_DATA_CNTRL = 1) else
((sent_col or REDUCTION_OR(offset_r)) and io_config(RANK_WIDTH));
delay_wr_data_cntrl_eq_1 : if (DELAY_WR_DATA_CNTRL = 1) generate
process (clk)
begin
if (clk'event and clk = '1') then
col_wr_data_buf_addr_r <= col_wr_data_buf_addr after (TCQ)*1 ps;
end if;
end process;
wr_data_addr <= col_wr_data_buf_addr_r;
end generate;
int11 : if (not(DELAY_WR_DATA_CNTRL = 1)) generate
wr_data_addr <= col_wr_data_buf_addr;
end generate;
read_data_valid <= (sent_col or REDUCTION_OR(offset_r)) and not(io_config(RANK_WIDTH));
process (read_data_valid)
begin
for i in dfi_rddata_en'range loop
dfi_rddata_en(i) <= read_data_valid;
end loop;
end process;
process (cnfg_wr_wait_r, read_data_valid, rst, wrdata_en)
variable cnfg_wr_wait_ns_tmp : std_logic_vector(WR_WAIT_CNT_WIDTH - 1 downto 0);
begin
if (rst = '1') then
cnfg_wr_wait_ns_tmp := (others => '0' );
else
cnfg_wr_wait_ns_tmp := cnfg_wr_wait_r;
if (wrdata_en = '1') then
cnfg_wr_wait_ns_tmp := std_logic_vector(TO_UNSIGNED(nWR_EN2CNFG_WR_LOCAL, WR_WAIT_CNT_WIDTH));
elsif (read_data_valid = '1') then
cnfg_wr_wait_ns_tmp := std_logic_vector(TO_UNSIGNED(nRD_EN2CNFG_WR_LOCAL, WR_WAIT_CNT_WIDTH));
elsif ((REDUCTION_OR(cnfg_wr_wait_r)) = '1') then
cnfg_wr_wait_ns_tmp := cnfg_wr_wait_r - '1';
end if;
end if;
cnfg_wr_wait_ns <= cnfg_wr_wait_ns_tmp;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
cnfg_wr_wait_r <= cnfg_wr_wait_ns after (TCQ)*1 ps;
end if;
end process;
process (cnfg_rd_wait_r, rst, wrdata_en)
variable cnfg_rd_wait_ns_tmp : std_logic_vector(RD_WAIT_CNT_WIDTH - 1 downto 0);
begin
if (rst = '1') then
cnfg_rd_wait_ns_tmp := (others => '0' );
else
cnfg_rd_wait_ns_tmp := cnfg_rd_wait_r;
if (wrdata_en = '1') then
cnfg_rd_wait_ns_tmp := std_logic_vector(TO_UNSIGNED(nWR_EN2CNFG_RD_LOCAL, RD_WAIT_CNT_WIDTH));
elsif ((REDUCTION_OR(cnfg_rd_wait_r)) = '1') then
cnfg_rd_wait_ns_tmp := cnfg_rd_wait_r - '1';
end if;
end if;
cnfg_rd_wait_ns <= cnfg_rd_wait_ns_tmp;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
cnfg_rd_wait_r <= cnfg_rd_wait_ns after (TCQ)*1 ps;
end if;
end process;
inhbt_wr_config_ns <= BOOLEAN_TO_STD_LOGIC(cnfg_wr_wait_ns /= nCOPY('0', WR_WAIT_CNT_WIDTH));
process (clk)
begin
if (clk'event and clk = '1') then
inhbt_wr_config_r <= inhbt_wr_config_ns after (TCQ)*1 ps;
end if;
end process;
inhbt_wr_config <= sent_col or wrdata_en or inhbt_wr_config_r;
inhbt_rd_config_ns <= BOOLEAN_TO_STD_LOGIC(cnfg_rd_wait_ns /= nCOPY('0',RD_WAIT_CNT_WIDTH));
process (clk)
begin
if (clk'event and clk = '1') then
inhbt_rd_config_r <= inhbt_rd_config_ns after (TCQ)*1 ps;
end if;
end process;
inhbt_rd_config <= sent_col or wrdata_en or inhbt_rd_config_r;
COL_SEL_0_13 : if ( ROW_WIDTH <= 13 ) generate
col_a_full <= ('0' & col_a(11) & col_a(9 downto 0));
end generate;
COL_SEL : if ( ROW_WIDTH > 13 ) generate
col_a_full <= (col_a(13) & col_a(11) & col_a(9 downto 0));
end generate;
col_a_extracted <= col_a_full(COL_WIDTH - 1 downto 0);
int12 : if (CS_WIDTH = 1) generate
ecc_line <= (col_rmw & col_ba & col_row & col_a_extracted);
end generate;
int13 : if (not(CS_WIDTH = 1)) generate
ecc_line <= (col_rmw & col_ra & col_ba & col_row & col_a_extracted);
end generate;
int14 : if (ECC = "OFF") generate
real_fifo_data <= (data_end & col_periodic_rd & col_data_buf_addr & offset_r(DATA_BUF_OFFSET_WIDTH - 1 downto 0));
end generate;
int15 : if (not(ECC = "OFF")) generate
real_fifo_data <= (data_end & col_periodic_rd & col_data_buf_addr & offset_r(DATA_BUF_OFFSET_WIDTH - 1 downto 0) & ecc_line);
end generate;
int16 : if (REMAINDER = 0) generate
fifo_in_data <= ( real_fifo_data);
end generate;
int17 : if (not(REMAINDER = 0)) generate
fifo_in_data <= nCOPY('0',6-REMAINDER) & real_fifo_data;
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
fifo_in_data_r <= fifo_in_data after (TCQ)*1 ps;
end if;
end process;
head_ns <= (others => '0' ) when (rst = '1') else
(head_r + "00001") when (read_data_valid = '1') else
head_r;
process (clk)
begin
if (clk'event and clk = '1') then
head_r <= head_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
head_r1 <= head_r after (TCQ)*1 ps;
end if;
end process;
tail_ns <= (others => '0' ) when (rst = '1') else
(tail_r + "00001") when (dfi_rddata_valid = '1') else
tail_r;
process (clk)
begin
if (clk'event and clk = '1') then
tail_r <= tail_ns after (TCQ)*1 ps;
end if;
end process;
fifo_ram : for i in 0 to RAM_CNT - 1 generate
RAM32M0 : RAM32M
generic map (
init_a => "0000000000000000000000000000000000000000000000000000000000000000",
init_b => "0000000000000000000000000000000000000000000000000000000000000000",
init_c => "0000000000000000000000000000000000000000000000000000000000000000",
init_d => "0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
doa => fifo_out_data_ns((i * 6) + 6 - 1 downto (i * 6) + 4),
dob => fifo_out_data_ns((i * 6) + 4 - 1 downto (i * 6) + 2),
doc => fifo_out_data_ns((i * 6) + 2 - 1 downto (i * 6) + 0),
dod => open,
dia => fifo_in_data_r((i * 6) + 6 - 1 downto (i * 6) + 4),
dib => fifo_in_data_r((i * 6) + 4 - 1 downto (i * 6) + 2),
dic => fifo_in_data_r((i * 6) + 2 - 1 downto (i * 6) + 0),
did => "00",
addra => tail_ns,
addrb => tail_ns,
addrc => tail_ns,
addrd => head_r1,
we => '1',
wclk => clk
);
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
fifo_out_data_r <= fifo_out_data_ns after (TCQ)*1 ps;
end if;
end process;
-- When ECC is ON, most of the FIFO output is delayed
-- by one state.
int18 : if (ECC = "OFF") generate
process (dfi_rddata_valid, fifo_out_data_r,periodic_rd)
begin
rd_data_offset_int2 <= fifo_out_data_r(DATA_BUF_OFFSET_WIDTH-1 downto 0);
rd_data_addr_int0 <= fifo_out_data_r(DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH -1 downto DATA_BUF_OFFSET_WIDTH );
periodic_rd <= fifo_out_data_r(DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH );
rd_data_end_int1 <= fifo_out_data_r(DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + 1 );
ecc_err_addr <= (others => '0' );
rd_data_en <= dfi_rddata_valid and not(periodic_rd);
ecc_status_valid <= '0';
wr_ecc_buf <= '0';
end process;
rd_rmw_int3 <= '0';
end generate;
int19 : if (not(ECC = "OFF")) generate
rd_data_end_ns <= fifo_out_data_r( DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH + DATA_BUF_ADDR_WIDTH + 2);
periodic_rd <= fifo_out_data_r( DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH + DATA_BUF_ADDR_WIDTH + 1);
rd_data_addr_ns <= fifo_out_data_r( DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH + DATA_BUF_ADDR_WIDTH downto DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH + 1);
rd_data_offset_ns <= fifo_out_data_r(DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH downto MC_ERR_LINE_WIDTH + 1);
rd_rmw_int3 <= fifo_out_data_r(MC_ERR_LINE_WIDTH);
ecc_err_addr_ns(DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH - 1 downto DATA_BUF_OFFSET_WIDTH) <= fifo_out_data_r(MC_ERR_LINE_WIDTH - 1 downto 0);
ecc_err_addr_ns(DATA_BUF_OFFSET_WIDTH - 1 downto 0) <= rd_data_offset_ns;
process (clk)
begin
if (clk'event and clk = '1') then
rd_data_end_int1 <= rd_data_end_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
rd_data_addr_int0 <= rd_data_addr_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
rd_data_offset_int2 <= rd_data_offset_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
ecc_err_addr <= ecc_err_addr_ns after (TCQ)*1 ps;
end if;
end process;
rd_data_en_ns <= dfi_rddata_valid and not((periodic_rd or rd_rmw_int3));
process (clk)
begin
if (clk'event and clk = '1') then
rd_data_en <= rd_data_en_ns;
end if;
end process;
ecc_status_valid_ns <= dfi_rddata_valid and not(periodic_rd);
process (clk)
begin
if (clk'event and clk = '1') then
ecc_status_valid <= ecc_status_valid_ns after (TCQ)*1 ps;
end if;
end process;
wr_ecc_buf_ns <= dfi_rddata_valid and not(periodic_rd) and rd_rmw_int3;
process (clk)
begin
if (clk'event and clk = '1') then
wr_ecc_buf <= wr_ecc_buf_ns after (TCQ)*1 ps;
end if;
end process;
end generate;
end architecture trans;
|
entity simple is
end;
architecture behav of simple is
begin
process
begin
assert false report "Test is running" severity note;
wait; -- Indefinite
end process;
end behav;
|
entity simple is
end;
architecture behav of simple is
begin
process
begin
assert false report "Test is running" severity note;
wait; -- Indefinite
end process;
end behav;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY counter IS
GENERIC ( WIDTH : integer := 32);
PORT (CLK : IN std_logic;
RST : IN std_logic;
LOAD : IN std_logic;
DATA : IN unsigned(WIDTH-1 DOWNTO 0);
Q : OUT unsigned(WIDTH-1 DOWNTO 0));
END counter;
ARCHITECTURE rtl OF counter IS
signal count : unsigned(WIDTH-1 DOWNTO 0);
BEGIN
process(RST, CLK) is
begin
if(RST = '1') then
count <= (others => '0');
elsif(CLK = '1' and CLK'event) then
if(LOAD = '1') then
count <= DATA;
else
count <= count + 1;
end if;
end if;
end process;
Q <= count;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity interleaver_tb is
end interleaver_tb;
architecture tb of interleaver_tb is
constant width : positive := 8;
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_logic := '0';
signal sync : std_logic := '0';
signal d : std_logic_vector(7 downto 0);
signal q : std_logic_vector(7 downto 0);
begin
dut : entity work.interleaver
generic map (I => 12, M => 17)
port map(clk => clk, rst => rst, clk_en => clk_en, sync => sync, d => d, q => q);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
test : process
variable cnt : unsigned(7 downto 0) := to_unsigned(0, 8);
begin
wait until falling_edge(rst);
while true loop
wait until rising_edge(clk);
clk_en <= '1';
d <= std_logic_vector(cnt);
cnt := cnt + to_unsigned(1, 8);
end loop;
end process;
end tb;
|
-- Copyright (C) 2009 OutputLogic.com
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-------------------------------------------------------------------------------
-- CRC module for data(7:0)
-- lfsr(15:0)=1+x^2+x^15+x^16;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity crc16 is
port ( data_in : in std_logic_vector (7 downto 0);
crc_en , rst, clk : in std_logic;
crc_out_res : out std_logic_vector (15 downto 0);
crc_out : out std_logic_vector (15 downto 0));
end crc16;
architecture imp_crc16 of crc16 is
signal lfsr_q: std_logic_vector (15 downto 0);
signal lfsr_c: std_logic_vector (15 downto 0);
signal data_in1 : std_logic_vector (7 downto 0);
signal crc_out1 : std_logic_vector (15 downto 0);
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of data_in : signal is "true";
--attribute keep of data_in : signal is "true";
begin
crc_out_res <= crc_out1;
crc_out(0) <=not crc_out1(7);
crc_out(1) <=not crc_out1(6);
crc_out(2) <=not crc_out1(5);
crc_out(3) <=not crc_out1(4);
crc_out(4) <=not crc_out1(3);
crc_out(5) <=not crc_out1(2);
crc_out(6) <=not crc_out1(1);
crc_out(7) <=not crc_out1(0);
crc_out(8) <=not crc_out1(15);
crc_out(9) <=not crc_out1(14);
crc_out(10) <=not crc_out1(13);
crc_out(11) <=not crc_out1(12);
crc_out(12) <=not crc_out1(11);
crc_out(13) <=not crc_out1(10);
crc_out(14) <=not crc_out1(9);
crc_out(15) <=not crc_out1(8);
--data_in1(7) <= data_in(0);
--data_in1(6) <= data_in(1);
--data_in1(5) <= data_in(2);
--data_in1(4) <= data_in(3);
--data_in1(3) <= data_in(4);
--data_in1(2) <= data_in(5);
--data_in1(1) <= data_in(6);
--data_in1(0) <= data_in(7);
data_in1 <= data_in;
crc_out1 <= lfsr_q;
lfsr_c(0) <= lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(0) xor data_in1(1) xor data_in1(2) xor data_in1(3) xor data_in1(4) xor data_in1(5) xor data_in1(6) xor data_in1(7);
lfsr_c(1) <= lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(1) xor data_in1(2) xor data_in1(3) xor data_in1(4) xor data_in1(5) xor data_in1(6) xor data_in1(7);
lfsr_c(2) <= lfsr_q(8) xor lfsr_q(9) xor data_in1(0) xor data_in1(1);
lfsr_c(3) <= lfsr_q(9) xor lfsr_q(10) xor data_in1(1) xor data_in1(2);
lfsr_c(4) <= lfsr_q(10) xor lfsr_q(11) xor data_in1(2) xor data_in1(3);
lfsr_c(5) <= lfsr_q(11) xor lfsr_q(12) xor data_in1(3) xor data_in1(4);
lfsr_c(6) <= lfsr_q(12) xor lfsr_q(13) xor data_in1(4) xor data_in1(5);
lfsr_c(7) <= lfsr_q(13) xor lfsr_q(14) xor data_in1(5) xor data_in1(6);
lfsr_c(8) <= lfsr_q(0) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(6) xor data_in1(7);
lfsr_c(9) <= lfsr_q(1) xor lfsr_q(15) xor data_in1(7);
lfsr_c(10) <= lfsr_q(2);
lfsr_c(11) <= lfsr_q(3);
lfsr_c(12) <= lfsr_q(4);
lfsr_c(13) <= lfsr_q(5);
lfsr_c(14) <= lfsr_q(6);
lfsr_c(15) <= lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in(0) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
process (clk,rst) begin
if (clk'EVENT and clk = '1') then
if (rst = '0') then
lfsr_q <= b"1111111111111111";
else
if (crc_en = '1') then
lfsr_q <= lfsr_c;
end if;
end if;
end if;
end process;
end architecture imp_crc16; |
-- Copyright (C) 2009 OutputLogic.com
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-------------------------------------------------------------------------------
-- CRC module for data(7:0)
-- lfsr(15:0)=1+x^2+x^15+x^16;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity crc16 is
port ( data_in : in std_logic_vector (7 downto 0);
crc_en , rst, clk : in std_logic;
crc_out_res : out std_logic_vector (15 downto 0);
crc_out : out std_logic_vector (15 downto 0));
end crc16;
architecture imp_crc16 of crc16 is
signal lfsr_q: std_logic_vector (15 downto 0);
signal lfsr_c: std_logic_vector (15 downto 0);
signal data_in1 : std_logic_vector (7 downto 0);
signal crc_out1 : std_logic_vector (15 downto 0);
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of data_in : signal is "true";
--attribute keep of data_in : signal is "true";
begin
crc_out_res <= crc_out1;
crc_out(0) <=not crc_out1(7);
crc_out(1) <=not crc_out1(6);
crc_out(2) <=not crc_out1(5);
crc_out(3) <=not crc_out1(4);
crc_out(4) <=not crc_out1(3);
crc_out(5) <=not crc_out1(2);
crc_out(6) <=not crc_out1(1);
crc_out(7) <=not crc_out1(0);
crc_out(8) <=not crc_out1(15);
crc_out(9) <=not crc_out1(14);
crc_out(10) <=not crc_out1(13);
crc_out(11) <=not crc_out1(12);
crc_out(12) <=not crc_out1(11);
crc_out(13) <=not crc_out1(10);
crc_out(14) <=not crc_out1(9);
crc_out(15) <=not crc_out1(8);
--data_in1(7) <= data_in(0);
--data_in1(6) <= data_in(1);
--data_in1(5) <= data_in(2);
--data_in1(4) <= data_in(3);
--data_in1(3) <= data_in(4);
--data_in1(2) <= data_in(5);
--data_in1(1) <= data_in(6);
--data_in1(0) <= data_in(7);
data_in1 <= data_in;
crc_out1 <= lfsr_q;
lfsr_c(0) <= lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(0) xor data_in1(1) xor data_in1(2) xor data_in1(3) xor data_in1(4) xor data_in1(5) xor data_in1(6) xor data_in1(7);
lfsr_c(1) <= lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(1) xor data_in1(2) xor data_in1(3) xor data_in1(4) xor data_in1(5) xor data_in1(6) xor data_in1(7);
lfsr_c(2) <= lfsr_q(8) xor lfsr_q(9) xor data_in1(0) xor data_in1(1);
lfsr_c(3) <= lfsr_q(9) xor lfsr_q(10) xor data_in1(1) xor data_in1(2);
lfsr_c(4) <= lfsr_q(10) xor lfsr_q(11) xor data_in1(2) xor data_in1(3);
lfsr_c(5) <= lfsr_q(11) xor lfsr_q(12) xor data_in1(3) xor data_in1(4);
lfsr_c(6) <= lfsr_q(12) xor lfsr_q(13) xor data_in1(4) xor data_in1(5);
lfsr_c(7) <= lfsr_q(13) xor lfsr_q(14) xor data_in1(5) xor data_in1(6);
lfsr_c(8) <= lfsr_q(0) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(6) xor data_in1(7);
lfsr_c(9) <= lfsr_q(1) xor lfsr_q(15) xor data_in1(7);
lfsr_c(10) <= lfsr_q(2);
lfsr_c(11) <= lfsr_q(3);
lfsr_c(12) <= lfsr_q(4);
lfsr_c(13) <= lfsr_q(5);
lfsr_c(14) <= lfsr_q(6);
lfsr_c(15) <= lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in(0) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
process (clk,rst) begin
if (clk'EVENT and clk = '1') then
if (rst = '0') then
lfsr_q <= b"1111111111111111";
else
if (crc_en = '1') then
lfsr_q <= lfsr_c;
end if;
end if;
end if;
end process;
end architecture imp_crc16; |
entity tb1 is
package pkg1 is
constant c : natural := 5;
function f return natural;
end pkg1;
end tb1;
architecture behav of tb1 is
begin
assert pkg1.c = 5 severity failure;
assert pkg1.c /= 5 report "value is correct" severity note;
end behav;
|
entity tb1 is
package pkg1 is
constant c : natural := 5;
function f return natural;
end pkg1;
end tb1;
architecture behav of tb1 is
begin
assert pkg1.c = 5 severity failure;
assert pkg1.c /= 5 report "value is correct" severity note;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Multiplier_tb is
end Multiplier_tb;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture Behaviour of Multiplier_tb is
component Multiplier is
generic (X_WIDTH : integer;
X_FRACTION : integer;
Y_WIDTH : integer;
Y_FRACTION : integer;
S_WIDTH : integer;
S_FRACTION : integer);
port(x : in std_logic_vector;
y : in std_logic_vector;
s : out std_logic_vector);
end component;
constant NO_OF_SAMPLES : integer := 10;
constant X_1_WIDTH : integer := 16;
constant X_1_FRACTION : integer := 14;
constant Y_1_WIDTH : integer := 16;
constant Y_1_FRACTION : integer := 14;
constant S_1_WIDTH : integer := 16;
constant S_1_FRACTION : integer := 13;
constant X_2_WIDTH : integer := 14;
constant X_2_FRACTION : integer := 10;
constant Y_2_WIDTH : integer := 8;
constant Y_2_FRACTION : integer := 6;
constant S_2_WIDTH : integer := 10;
constant S_2_FRACTION : integer := 6;
type x_1_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(X_1_WIDTH-1 downto 0);
type y_1_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(Y_1_WIDTH-1 downto 0);
type s_1_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(S_1_WIDTH-1 downto 0);
type x_2_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(X_2_WIDTH-1 downto 0);
type y_2_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(Y_2_WIDTH-1 downto 0);
type s_2_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(S_2_WIDTH-1 downto 0);
signal x_1 : x_1_array := ("1111100001010010",
"0001001001011001",
"0101011101011110",
"0011011100001000",
"0101011001110111",
"1111100011010000",
"0110100111011001",
"0111111011100010",
"0011100001010111",
"1000111111101101");
signal y_1 : y_1_array := ("0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000");
signal s_1 : s_1_array := ("1111110000101001",
"0000100100101100",
"0010101110101111",
"0001101110000100",
"0010101100111011",
"1111110001101000",
"0011010011101100",
"0011111101110001",
"0001110000101011",
"1100011111110110");
signal x_2 : x_2_array := ("01010111100101",
"10000001101101",
"00010100011110",
"01101101011010",
"11011111110111",
"01011101111111",
"00101101011011",
"00100100110000",
"11011010111001",
"01010000000101");
signal y_2 : y_2_array := ("01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000");
signal s_2 : s_2_array := ("0101011110",
"1000000110",
"0001010001",
"0110110101",
"1101111111",
"0101110111",
"0010110101",
"0010010011",
"1101101011",
"0101000000");
signal s1 : std_logic_vector(S_1_WIDTH-1 downto 0);
signal s2 : std_logic_vector(S_2_WIDTH-1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- End process
ending : process
begin
wait for 1050 ns;
assert false
report "Simulation Done!"
severity failure;
end process;
-- Test process
test : process
begin
wait for 100 ns;
assert (s1 = s_1(0))
report "Error: Multiplier 1 output wrong!"
severity Error;
assert (s2 = s_2(0))
report "Error: Multiplier 2 output wrong!"
severity Error;
x_1(0 to NO_OF_SAMPLES-2) <= x_1(1 to NO_OF_SAMPLES-1);
y_1(0 to NO_OF_SAMPLES-2) <= y_1(1 to NO_OF_SAMPLES-1);
s_1(0 to NO_OF_SAMPLES-2) <= s_1(1 to NO_OF_SAMPLES-1);
x_2(0 to NO_OF_SAMPLES-2) <= x_2(1 to NO_OF_SAMPLES-1);
y_2(0 to NO_OF_SAMPLES-2) <= y_2(1 to NO_OF_SAMPLES-1);
s_2(0 to NO_OF_SAMPLES-2) <= s_2(1 to NO_OF_SAMPLES-1);
end process;
Multiplier_1 : Multiplier
generic map(X_WIDTH => X_1_WIDTH,
X_FRACTION => X_1_FRACTION,
Y_WIDTH => Y_1_WIDTH,
Y_FRACTION => Y_1_FRACTION,
S_WIDTH => S_1_WIDTH,
S_FRACTION => S_1_FRACTION)
port map(x => x_1(0),
y => y_1(0),
s => s1);
Multiplier_2 : Multiplier
generic map(X_WIDTH => X_2_WIDTH,
X_FRACTION => X_2_FRACTION,
Y_WIDTH => Y_2_WIDTH,
Y_FRACTION => Y_2_FRACTION,
S_WIDTH => S_2_WIDTH,
S_FRACTION => S_2_FRACTION)
port map(x => x_2(0),
y => y_2(0),
s => s2);
end Behaviour; |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_14 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_14 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(14, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_14 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_14 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(14, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_14 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_14 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(14, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_14 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_14 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(14, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_14 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_14 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(14, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
MASTER_TRANSMIT, MASTER_RECEIVE, MASTER_CHECK,
SLAVE_TRANSMIT, SLAVE_RECEIVE, SLAVE_CHECK,
MASTER_QUICK_CMD);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 64;
constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 10;
--==========================================================================================
--
-- Transaction info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction
type t_base_transaction is record
operation : t_operation;
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
data : t_byte_array(0 to C_VVC_CMD_DATA_MAX_LENGTH-1);
num_bytes : natural;
action_when_transfer_is_done : t_action_when_transfer_is_done;
exp_ack : boolean;
rw_bit : std_logic;
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
addr => (others => '0'),
data => (others => (others => '0')),
num_bytes => 0,
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
exp_ack => true,
rw_bit => '0',
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT
);
-- Global transaction info trigger signal
type t_i2c_transaction_trigger_array is array (natural range <>) of std_logic;
signal global_i2c_vvc_transaction_trigger : t_i2c_transaction_trigger_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => '0');
-- Type is defined as array to coincide with channel based VVCs
type t_i2c_transaction_group_array is array (natural range <>) of t_transaction_group;
-- Shared transaction info variable
shared variable shared_i2c_vvc_transaction_info : t_i2c_transaction_group_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => C_TRANSACTION_GROUP_DEFAULT);
end package transaction_pkg; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc182.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p04n02i00182ent IS
END c04s04b00x00p04n02i00182ent;
ARCHITECTURE c04s04b00x00p04n02i00182arch OF c04s04b00x00p04n02i00182ent IS
type COORDINATE is
record
X, Y: INTEGER;
end record;
attribute LOCATION : COORDINATE;
signal loc1, loc2 : COORDINATE;
attribute LOCATION of loc1 : signal is (10, 15);
attribute LOCATION of others : signal is (25, 77);
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( loc1'LOCATION = (10, 15) and
loc2'LOCATION = (25, 77) )
report "***PASSED TEST: c04s04b00x00p04n02i00182"
severity NOTE;
assert ( loc1'LOCATION = (10, 15) and
loc2'LOCATION = (25, 77) )
report "***FAILED TEST: c04s04b00x00p04n02i00182 - Attribute associated with a signal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p04n02i00182arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc182.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p04n02i00182ent IS
END c04s04b00x00p04n02i00182ent;
ARCHITECTURE c04s04b00x00p04n02i00182arch OF c04s04b00x00p04n02i00182ent IS
type COORDINATE is
record
X, Y: INTEGER;
end record;
attribute LOCATION : COORDINATE;
signal loc1, loc2 : COORDINATE;
attribute LOCATION of loc1 : signal is (10, 15);
attribute LOCATION of others : signal is (25, 77);
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( loc1'LOCATION = (10, 15) and
loc2'LOCATION = (25, 77) )
report "***PASSED TEST: c04s04b00x00p04n02i00182"
severity NOTE;
assert ( loc1'LOCATION = (10, 15) and
loc2'LOCATION = (25, 77) )
report "***FAILED TEST: c04s04b00x00p04n02i00182 - Attribute associated with a signal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p04n02i00182arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc182.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p04n02i00182ent IS
END c04s04b00x00p04n02i00182ent;
ARCHITECTURE c04s04b00x00p04n02i00182arch OF c04s04b00x00p04n02i00182ent IS
type COORDINATE is
record
X, Y: INTEGER;
end record;
attribute LOCATION : COORDINATE;
signal loc1, loc2 : COORDINATE;
attribute LOCATION of loc1 : signal is (10, 15);
attribute LOCATION of others : signal is (25, 77);
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( loc1'LOCATION = (10, 15) and
loc2'LOCATION = (25, 77) )
report "***PASSED TEST: c04s04b00x00p04n02i00182"
severity NOTE;
assert ( loc1'LOCATION = (10, 15) and
loc2'LOCATION = (25, 77) )
report "***FAILED TEST: c04s04b00x00p04n02i00182 - Attribute associated with a signal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p04n02i00182arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use work.CONSTANTS.all;
use work.ROCACHE_PKG.all;
use work.RWCACHE_PKG.all;
use work.alu_types.all;
use work.cu.all;
entity DLX is
port (
-- Inputs
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset:Active-High
IRAM_ADDRESS : out std_logic_vector(Instr_size - 1 downto 0);
IRAM_ISSUE : out std_logic;
IRAM_READY : in std_logic;
IRAM_DATA : in std_logic_vector(2*Data_size-1 downto 0);
DRAM_ADDRESS : out std_logic_vector(Instr_size-1 downto 0);
DRAM_ISSUE : out std_logic;
DRAM_READNOTWRITE : out std_logic;
DRAM_READY : in std_logic;
DRAM_DATA : inout std_logic_vector(2*Data_size-1 downto 0)
);
end DLX;
architecture structural of DLX is
component CU_UP is
port (
-- Inputs
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset:Active-High
IR : in std_logic_vector(31 downto 0);
JMP_PREDICT : in std_logic; -- Jump Prediction
ICACHE_STALL: in std_logic; -- The instruction cache is in stall
DCACHE_STALL: in std_logic; -- The rwcache is busy
ISZERO : in std_logic; -- Needed for condizional jumps
JMP_ADDRESS : in std_logic_vector(31 downto 0);
NPC_ADDRESS : in std_logic_vector(31 downto 0);
PC : out std_logic_vector(31 downto 0);
-- Outputs
JUMP: out std_logic;
LATCHER: out std_logic;
MUXIMMEDIATE_CTR: out std_logic;
MUXJMPADDRESS_CTR: out std_logic;
MUXRD0_CTR: out std_logic;
MUXRD_CTR: out std_logic;
WRF_ENABLE: out std_logic;
WRF_CALL: out std_logic;
WRF_RET: out std_logic;
WRF_RS1_ENABLE: out std_logic;
WRF_RS2_ENABLE: out std_logic;
MUXALUOUT_CTR: out std_logic;
MUXALU_CTR: out std_logic;
ALU_FUNC: out std_logic_vector(4 downto 0);
MEMORY_ENABLE: out std_logic;
MEMORY_RNOTW: out std_logic;
WRF_RD_ENABLE: out std_logic;
ID_STALL: out std_logic;
EXE_STALL: out std_logic;
MEM_STALL: out std_logic;
WB_STALL: out std_logic
);
end component;
component ROCACHE is
port (
CLK : in std_logic;
RST : in std_logic; -- active high
ENABLE : in std_logic;
ADDRESS : in std_logic_vector(Instr_size - 1 downto 0);
OUT_DATA : out std_logic_vector(Instr_size - 1 downto 0);
STALL : out std_logic;
RAM_ISSUE : out std_logic;
RAM_ADDRESS : out std_logic_vector(Instr_size - 1 downto 0);
RAM_DATA : in std_logic_vector(2*Instr_size - 1 downto 0);
RAM_READY : in std_logic
);
end component;
component INCREMENTER is
generic (
N: integer := 32
);
port (
A: in std_logic_vector (N-1 downto 0);
Y: out std_logic_vector(N-1 downto 0)
);
end component;
component RCA_GENERIC is
generic (
NBIT : integer := 32
);
port (
A : in std_logic_vector(NBIT-1 downto 0);
B : in std_logic_vector(NBIT-1 downto 0);
Ci : in std_logic;
S : out std_logic_vector(NBIT-1 downto 0);
Co : out std_logic
);
end component;
component SGNEXT is
generic (
INBITS: integer;
OUTBITS: integer
);
port(
DIN : in std_logic_vector (INBITS-1 downto 0);
DOUT : out std_logic_vector (OUTBITS-1 downto 0)
);
end component;
component LATCH is
generic (
N: integer := 1
);
port (
DIN: in std_logic_vector(N-1 downto 0); -- Data in
EN: in std_logic;
RESET: in std_logic;
DOUT: out std_logic_vector(N-1 downto 0) -- Data out
);
end component;
component REGISTER_FDL is
generic (
N: integer := 32
);
port (
DIN: in std_logic_vector(N-1 downto 0); -- Data in
ENABLE: in std_logic; -- Enable
CLK: in std_logic; -- Clock
RESET: in std_logic; -- Reset
DOUT: out std_logic_vector(N-1 downto 0) -- Data out
);
end component;
component MUX is
generic (
N: integer := 1 -- Number of bits
);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
SEL: in std_logic;
Y: out std_logic_vector(N-1 downto 0)
);
end component;
component MUX4TO1 is
generic (
N: integer := NSUMG -- Number of bits
);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
C: in std_logic_vector(N-1 downto 0);
D: in std_logic_vector(N-1 downto 0);
SEL: in std_logic_vector(1 downto 0);
Y: out std_logic_vector(N-1 downto 0)
);
end component;
component WRF is
generic (
NBIT: integer;
numWindows: integer;
numRegsPerWin: integer;
logNumWindows: integer;
logNumRegsPerWin: integer
);
port (
CLK: IN std_logic;
RESET: IN std_logic;
ENABLE: IN std_logic;
CALL: IN std_logic; -- Call -> Next context
RET: IN std_logic; -- Return -> Previous context
RD1: IN std_logic; -- Read 1
RD2: IN std_logic; -- Read 2
WR: IN std_logic; -- Write
ADDR_RD1: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Read Address 1
ADDR_RD2: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Read Address 2
ADDR_WRC: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Write Address
ADDR_WR: IN std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Write Address
REAL_ADDR_RD1: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Read Address 1
REAL_ADDR_RD2: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Read Address 2
REAL_ADDR_WR: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Write Address
OUT1: OUT std_logic_vector(NBIT-1 downto 0); -- Read data 1
OUT2: OUT std_logic_vector(NBIT-1 downto 0); -- Read data 2
DATAIN: IN std_logic_vector(NBIT-1 downto 0) -- Write data
);
end component;
component ALU
generic (
N : integer := NSUMG
);
port (
FUNC: in TYPE_OP;
A, B: in std_logic_vector(N-1 downto 0);
CLK: in std_logic;
RESET: in std_logic;
OUTALU: out std_logic_vector(N-1 downto 0)
);
end component;
component RWCACHE is
generic (
regaddrsize : integer
);
port (
CLK : in std_logic;
RST : in std_logic; -- active high
ENABLE_EX : in std_logic;
READNOTWRITE_EX : in std_logic;
ALU_OUT_REAL : in std_logic_vector(DATA_SIZE - 1 downto 0);
RS2_DATA_EX : in std_logic_vector(DATA_SIZE - 1 downto 0);
RS2_EX : in std_logic_vector(regaddrsize-1 downto 0);
RD_MEM : in std_logic_vector(regaddrsize-1 downto 0);
MEM_STALL : in std_logic;
LATCHER : in std_logic;
MEM_DATA : out std_logic_vector(DATA_SIZE - 1 downto 0);
STALL : out std_logic;
RAM_ISSUE : out std_logic;
RAM_READNOTWRITE : out std_logic;
RAM_ADDRESS : out std_logic_vector(DATA_SIZE - 1 downto 0);
RAM_DATA : inout std_logic_vector(2*DATA_SIZE - 1 downto 0);
RAM_READY : in std_logic
);
end component;
signal IPC, PC, NPC : std_logic_vector(Instr_size-1 downto 0) := (others => '0');
signal IR, IR_RF, ICACHE_IR : std_logic_vector(Instr_size-1 downto 0) := (others => '0');
signal ICACHE_STALL, ICACHE_STALL_NOT : std_logic := '1';
signal JMP_PREDICT : std_logic; -- Jump Prediction
signal DCACHE_STALL : std_logic; -- The WRF is busy
signal DCACHE_STALL_NOT : std_logic; -- The WRF is busy
signal ICACHE_ENABLE : std_logic;
signal MUXRD_CTR : std_logic;
signal WRF_ENABLE : std_logic;
signal WRF_CALL : std_logic;
signal WRF_CALL_NS : std_logic;
signal WRF_RET : std_logic;
signal WRF_RET_R31 : std_logic;
signal WRF_RS1_ENABLE : std_logic;
signal WRF_RS2_ENABLE : std_logic;
signal WRF_RD_ENABLE : std_logic;
signal MUXALU_CTR : std_logic;
signal ALU_FUNC : std_logic_vector(4 downto 0);
signal MEMORY_ENABLE : std_logic;
signal MEMORY_RNOTW : std_logic;
signal JUMP : std_logic;
signal LATCHER : std_logic;
signal ID_STALL : std_logic;
signal EXE_STALL : std_logic;
signal MEM_STALL : std_logic;
signal WB_STALL : std_logic;
-- STAGE TWO
signal MUXIMMEDIATE_CTR : std_logic;
signal MUXJMPADDRESS_CTR : std_logic;
signal MUXRD0_CTR : std_logic;
signal IMMEDIATE : std_logic_vector(31 downto 0) := (others => '0');
signal IMMEDIATE_IR : std_logic_vector(31 downto 0) := (others => '0');
signal JMP_ADDRESS : std_logic_vector(31 downto 0) := (others => '0');
signal JMP_RELATIVE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0');
signal JMP_REGISTER_ADDRESS : std_logic_vector(31 downto 0) := (others => '0');
signal JMP_CARRYOUT : std_logic;
signal RD_TEMP : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); -- Write Address
signal RD : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); -- Write Address
signal RD0 : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0);
signal RS1 : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); -- Read Address 1
signal RS2 : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); -- Read Address 2
signal RS1_DATA : std_logic_vector(wrfNumBit-1 downto 0); -- Read data 1
signal RS1_DATA_ISZERO : std_logic;
signal RS2_DATA : std_logic_vector(wrfNumBit-1 downto 0); -- Read data 2
signal RS1_EX : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); -- Read Address 1
signal RS2_EX : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); -- Read Address 1
signal RS1_DATA_EX : std_logic_vector(wrfNumBit-1 downto 0);
signal RS2_DATA_EX : std_logic_vector(wrfNumBit-1 downto 0);
signal RD_EX : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0);
signal IMMEDIATE_EX : std_logic_vector(INSTR_SIZE-1 downto 0);
-- STAGE THREE
signal MUXALUOUT_CTR : std_logic;
signal FWDJ0 : std_logic_vector(WORD_SIZE-1 downto 0);
signal FWDJ : std_logic_vector(WORD_SIZE-1 downto 0);
signal FWDA0 : std_logic_vector(WORD_SIZE-1 downto 0);
signal FWDA1 : std_logic_vector(WORD_SIZE-1 downto 0);
signal FWDB0 : std_logic_vector(WORD_SIZE-1 downto 0);
signal FWDB1 : std_logic_vector(WORD_SIZE-1 downto 0);
signal ALU_IN1 : std_logic_vector(WORD_SIZE-1 downto 0);
signal ALU_IN2 : std_logic_vector(WORD_SIZE-1 downto 0);
signal ALU_OUT : std_logic_vector(WORD_SIZE-1 downto 0);
signal ALU_OUT_REAL : std_logic_vector(DATA_SIZE-1 downto 0);
signal RS2_MEM : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); -- Read Address 1
signal RS2_DATA_MEM : std_logic_vector(wrfNumBit-1 downto 0);
signal ALU_OUT_MEM : std_logic_vector(WORD_SIZE-1 downto 0);
signal RD_MEM : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0);
signal IMMEDIATE_MEM : std_logic_vector(wrfNumBit-1 downto 0);
-- STAGE FOUR
signal MEM_ADDRESS : std_logic_vector(WORD_SIZE-1 downto 0);
signal RS2_DATA_MEM1 : std_logic_vector(WORD_SIZE-1 downto 0);
signal MEM_DATA : std_logic_vector(WORD_SIZE-1 downto 0);
signal RD_WB : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0);
signal MEM_DATA_WB : std_logic_vector(WORD_SIZE-1 downto 0);
signal RD_DATA_WB : std_logic_vector(wrfNumBit-1 downto 0);
signal REAL_ADDR_RS1 : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0);
signal REAL_ADDR_RS2 : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0);
signal REAL_ADDR_WR : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0);
signal RS1_EQ_RD_EX : std_logic;
signal RS1_EQ_RD_MEM : std_logic;
signal RS1_EQ_RD_WB : std_logic;
signal RS1_EX_EQ_RD_MEM : std_logic;
signal RS1_EX_EQ_RD_WB : std_logic;
signal RS2_EX_EQ_RD_MEM : std_logic;
signal RS2_EX_EQ_RD_WB : std_logic;
signal RS2_MEM_EQ_RD_WB : std_logic;
begin
ICACHE_ENABLE <= not JUMP;
ICACHE_STALL_NOT <= not ICACHE_STALL;
JMP_PREDICT <= '0'; -- Always predict not taken
DCACHE_STALL_NOT <= not DCACHE_STALL;
-- Control Unit
CONTROL_UNIT : CU_UP
port map (CLK, RST, IR, JMP_PREDICT, ICACHE_STALL, DCACHE_STALL, RS1_DATA_ISZERO, JMP_ADDRESS, IPC, PC, JUMP, LATCHER, MUXIMMEDIATE_CTR, MUXJMPADDRESS_CTR, MUXRD0_CTR, MUXRD_CTR, WRF_ENABLE, WRF_CALL, WRF_RET, WRF_RS1_ENABLE, WRF_RS2_ENABLE, MUXALUOUT_CTR, MUXALU_CTR, ALU_FUNC, MEMORY_ENABLE, MEMORY_RNOTW, WRF_RD_ENABLE, ID_STALL, EXE_STALL, MEM_STALL, WB_STALL);
ICACHE : ROCACHE
port map (CLK, RST, '1', PC, ICACHE_IR, ICACHE_STALL, IRAM_ISSUE, IRAM_ADDRESS, IRAM_DATA, IRAM_READY);
MUX_IR : MUX
generic map ( 32 )
-- port map( (others => '0'), ICACHE_IR, LATCHER, IR );
port map( (others => '0'), ICACHE_IR, ICACHE_STALL_NOT, IR );
-- __ INCREMENTER
NPCEVAL: INCREMENTER
generic map (32)
port map (PC, IPC);
PROPAGATE_NPC: REGISTER_FDL
generic map (32)
port map(IPC, LATCHER, CLK, RST, NPC);
PROPAGATE_PC_IF_RF: REGISTER_FDL
generic map (32)
port map (IR, LATCHER, CLK, RST, IR_RF);
--
-- STAGE TWO
--
EXTENDER: SGNEXT
generic map (16, 32)
port map (IR_RF(15 downto 0), IMMEDIATE_IR);
MUX_IMMEDIATE : MUX
generic map ( DATA_SIZE )
port map ( IMMEDIATE_IR, NPC, MUXIMMEDIATE_CTR, IMMEDIATE );
JMP_ADDER: RCA_GENERIC
generic map (32)
port map(NPC, IMMEDIATE_IR, '0', JMP_RELATIVE_ADDRESS, JMP_CARRYOUT);
JMP_REGISTER_ADDRESS <= FWDJ;
MUX_JMP : MUX
generic map ( DATA_SIZE )
port map ( JMP_RELATIVE_ADDRESS, JMP_REGISTER_ADDRESS, MUXJMPADDRESS_CTR, JMP_ADDRESS );
-- WRF
RS1 <= IR_RF(25 downto 21);
RS2 <= IR_RF(20 downto 16);
RD_TEMP <= IR_RF(15 downto 11);
WRF_RET_R31 <= WRF_RET and ( not or_reduce( RS1 xor "11111" ) ) and ( not ID_STALL );
WRF_CALL_NS <= WRF_CALL and ( not ID_STALL );
REGISTERFILE: WRF
generic map (wrfNumBit, wrfNumWindows, wrfNumRegsPerWin, wrfLogNumWindows, wrfLogNumRegsPerWin)
port map (CLK, RST, WRF_ENABLE, WRF_CALL_NS, WRF_RET_R31, WRF_RS1_ENABLE, WRF_RS2_ENABLE, WRF_RD_ENABLE, RS1, RS2, RD, RD_WB, REAL_ADDR_RS1, REAL_ADDR_RS2, REAL_ADDR_WR, RS1_DATA, RS2_DATA, RD_DATA_WB);
MUX_RD: MUX
generic map (5)
port map (RD0, RD_TEMP, MUXRD_CTR, RD);
MUX_RD0: MUX
generic map (5)
port map (RS2, "11111", MUXRD0_CTR, RD0);
RS1_EQ_RD_EX <= not or_reduce( REAL_ADDR_RS1 xor RD_EX );
RS1_EQ_RD_MEM <= not or_reduce( REAL_ADDR_RS1 xor RD_MEM );
RS1_EQ_RD_WB <= not or_reduce( REAL_ADDR_RS1 xor RD_WB );
-- JUMPER forward logic
MUX_FWDJ1 : MUX
generic map ( WORD_SIZE )
port map ( FWDJ0, MEM_DATA, RS1_EQ_RD_MEM, FWDJ );
MUX_FWDJ0 : MUX
generic map ( WORD_SIZE )
port map ( RS1_DATA, RD_DATA_WB, RS1_EQ_RD_WB, FWDJ0 );
-- Comparator
RS1_DATA_ISZERO <= not or_reduce(FWDJ);
-- PIPES
PIPEREG_RD: REGISTER_FDL
generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2)
port map(REAL_ADDR_WR, LATCHER, CLK, RST, RD_EX);
PROPAGATE_RS1_ID_EX: REGISTER_FDL
generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2)
port map (REAL_ADDR_RS1, LATCHER, CLK, RST, RS1_EX);
PROPAGATE_RS2_ID_EX: REGISTER_FDL
generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2)
port map (REAL_ADDR_RS2, LATCHER, CLK, RST, RS2_EX);
PIPEREG_RS1_DATA: REGISTER_FDL
generic map (32)
port map(RS1_DATA, LATCHER, CLK, RST, RS1_DATA_EX);
PIPEREG_RS2_DATA: REGISTER_FDL
generic map (32)
port map(RS2_DATA, LATCHER, CLK, RST, RS2_DATA_EX);
PIPEREG_IMMEDIATE: REGISTER_FDL
generic map (32)
port map(IMMEDIATE, LATCHER, CLK, RST, IMMEDIATE_EX);
-- STAGE 3
RS1_EX_EQ_RD_MEM <= ( not or_reduce( RS1_EX xor RD_MEM )) and ( not MEM_STALL );
RS1_EX_EQ_RD_WB <= ( not or_reduce( RS1_EX xor RD_WB ) ) and ( not WB_STALL );
RS2_EX_EQ_RD_MEM <= ( not or_reduce( RS2_EX xor RD_MEM )) and ( not MEM_STALL );
RS2_EX_EQ_RD_WB <= ( not or_reduce( RS2_EX xor RD_WB ) ) and ( not WB_STALL );
-- ALU forward logic
MUX_FWDA1 : MUX
generic map ( WORD_SIZE )
port map ( FWDA0, MEM_DATA, RS1_EX_EQ_RD_MEM, FWDA1 );
MUX_FWDA0 : MUX
generic map ( WORD_SIZE )
port map ( RS1_DATA_EX, MEM_DATA_WB, RS1_EX_EQ_RD_WB, FWDA0 );
MUX_FWDB1 : MUX
generic map ( WORD_SIZE )
port map ( FWDB0, MEM_DATA, RS2_EX_EQ_RD_MEM, FWDB1 );
MUX_FWDB0 : MUX
generic map ( WORD_SIZE )
port map ( RS2_DATA_EX, MEM_DATA_WB, RS2_EX_EQ_RD_WB, FWDB0 );
-- ALU input muxes
MUX_ALU2 : MUX
generic map ( WORD_SIZE )
port map ( IMMEDIATE_EX, FWDB1, MUXALU_CTR, ALU_IN2 );
ALU_IN1 <= FWDA1;
-- ALU
EXECUTER : ALU
generic map ( WORD_SIZE )
port map ( ALU_FUNC, ALU_IN1, ALU_IN2, CLK, RST, ALU_OUT );
MUX_ALU_OUT : MUX
generic map ( DATA_SIZE )
port map ( ALU_OUT, IMMEDIATE_EX, MUXALUOUT_CTR, ALU_OUT_REAL );
-- PIPEREG_ALU_OUT: REGISTER_FDL
-- generic map (32)
-- port map(ALU_OUT_REAL, LATCHER, CLK, RST, ALU_OUT_MEM);
PIPEREG_IMMEDIATE_EX: REGISTER_FDL
generic map (32)
port map(IMMEDIATE_EX, LATCHER, CLK, RST, IMMEDIATE_MEM);
PIPEREG_RD_EX: REGISTER_FDL
generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2)
port map(RD_EX, LATCHER, CLK, RST, RD_MEM);
PIPEREG_RS2_DATA_EX: REGISTER_FDL
generic map (32)
port map(RS2_DATA_EX, LATCHER, CLK, RST, RS2_DATA_MEM);
PIPEREG_RS2_EX: REGISTER_FDL
generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2)
port map(RS2_EX, LATCHER, CLK, RST, RS2_MEM);
-- STAGE FOUR
DCACHE : RWCACHE
generic map ( wrfLogNumWindows+wrfLogNumRegsPerWin+2 )
port map ( CLK, RST, MEMORY_ENABLE, MEMORY_RNOTW, ALU_OUT_REAL, RS2_DATA_EX, RS2_EX, RD_MEM, MEM_STALL, LATCHER, MEM_DATA, DCACHE_STALL, DRAM_ISSUE, DRAM_READNOTWRITE, DRAM_ADDRESS, DRAM_DATA, DRAM_READY );
PIPEREG_RD_MEM: REGISTER_FDL
generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2)
port map(RD_MEM, '1', CLK, RST, RD_WB);
PIPEREG_MEM_DATA: REGISTER_FDL
generic map (32)
port map(MEM_DATA, '1', CLK, RST, MEM_DATA_WB);
-- STAGE FIVE
RD_DATA_WB <= MEM_DATA_WB;
-- Nothing
-- GO!
end structural;
|
----------------------------------------------------------------------
---- ----
---- iteration_synth.vhd ----
---- ----
---- This file is part of the turbo decoder IP core project ----
---- http://www.opencores.org/projects/turbocodes/ ----
---- ----
---- Author(s): ----
---- - David Brochart(dbrochart@opencores.org) ----
---- ----
---- All additional information is available in the README.txt ----
---- file. ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2005 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
architecture synth of iteration is
signal zout1 : ARRAY4c;
signal zout2 : ARRAY4c;
signal zout1Perm : ARRAY4c;
signal zoutInt1 : ARRAY4c;
signal zout2Int : ARRAY4c;
signal tmp0 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
signal tmp1 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
signal tmp2 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp3 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp4 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
signal tmp5 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
signal tmp6 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
signal tmp7 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
signal tmp8 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp9 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp10 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
signal tmp11 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
signal abDel1Perm : ARRAY2a;
signal abDel1PermInt: ARRAY2a;
signal aDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal aDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal aDecInt : std_logic;
signal bDecInt : std_logic;
signal aDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
begin
sova_i0 : sova port map (
clk => clk,
rst => rst,
aNoisy => a,
bNoisy => b,
yNoisy => y,
wNoisy => w,
zin => zin,
zout => zout1,
aClean => aDec,
bClean => bDec
);
zPermut_i0 : zPermut generic map (
flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
)
port map (
flipflop => flipflop,
z => zout1,
zPerm => zout1Perm
);
tmp0 <= zout1Perm(0) & zout1Perm(1) & zout1Perm(2) & zout1Perm(3) & abDel1Perm(0) & abDel1Perm(1);
interleaver_i0 : interleaver generic map (
delay => TREL1_LEN + TREL2_LEN + 2 + delay,
way => 0
)
port map (
clk => clk,
rst => rst,
d => tmp0,
q => tmp1
);
zoutInt1(0) <= tmp1(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 3 + SIG_WIDTH * 2);
zoutInt1(1) <= tmp1(Z_WIDTH * 3 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 2 + SIG_WIDTH * 2);
zoutInt1(2) <= tmp1(Z_WIDTH * 2 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 1 + SIG_WIDTH * 2);
zoutInt1(3) <= tmp1(Z_WIDTH * 1 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 0 + SIG_WIDTH * 2);
abDel1PermInt(0) <= tmp1(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
abDel1PermInt(1) <= tmp1(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
tmp2 <= a & b & y & w & yInt & wInt;
delayer_i0 : delayer generic map (
delay => TREL1_LEN + TREL2_LEN
)
port map (
clk => clk,
rst => rst,
d => tmp2,
q => tmp3
);
aDel1 <= tmp3(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
bDel1 <= tmp3(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yDel1 <= tmp3(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wDel1 <= tmp3(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel1 <= tmp3(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel1 <= tmp3(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
abPermut_i0 : abPermut generic map (
flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
)
port map (
flipflop => flipflop,
a => aDel1,
b => bDel1,
abPerm => abDel1Perm
);
tmp4 <= aDel1 & bDel1 & yDel1 & wDel1;
delayer_i1 : delayer generic map (
delay => FRSIZE
)
port map (
clk => clk,
rst => rst,
d => tmp4,
q => tmp5
);
aDel2 <= tmp5(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
bDel2 <= tmp5(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yDel2 <= tmp5(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wDel2 <= tmp5(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
sova_i1 : sova port map (
clk => clk,
rst => rst,
aNoisy => abDel1PermInt(1),
bNoisy => abDel1PermInt(0),
yNoisy => yIntDel1,
wNoisy => wIntDel1,
zin => zoutInt1,
zout => zout2,
aClean => aDecInt,
bClean => bDecInt
);
tmp6 <= zout2(0) & zout2(1) & zout2(2) & zout2(3);
deinterleaver_i0 : interleaver generic map (
delay => 2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay,
way => 1
)
port map (
clk => clk,
rst => rst,
d => tmp6,
q => tmp7
);
zout2Int(0) <= tmp7(Z_WIDTH * 4 - 1 downto Z_WIDTH * 3);
zout2Int(1) <= tmp7(Z_WIDTH * 3 - 1 downto Z_WIDTH * 2);
zout2Int(2) <= tmp7(Z_WIDTH * 2 - 1 downto Z_WIDTH * 1);
zout2Int(3) <= tmp7(Z_WIDTH * 1 - 1 downto Z_WIDTH * 0);
zPermut_i1 : zPermut generic map (
flip => (2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay) mod 2
)
port map (
flipflop => flipflop,
z => zout2Int,
zPerm => zout
);
tmp8 <= aDel2 & bDel2 & yDel2 & wDel2 & yIntDel1 & wIntDel1;
delayer_i2 : delayer generic map (
delay => TREL1_LEN + TREL2_LEN
)
port map (
clk => clk,
rst => rst,
d => tmp8,
q => tmp9
);
aDel3 <= tmp9(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
bDel3 <= tmp9(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yDel3 <= tmp9(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wDel3 <= tmp9(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel3 <= tmp9(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel3 <= tmp9(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
tmp10 <= aDel3 & bDel3 & yDel3 & wDel3 & yIntDel3 & wIntDel3 & yIntDel4 & wIntDel4;
delayer_i3 : delayer generic map (
delay => FRSIZE
)
port map (
clk => clk,
rst => rst,
d => tmp10,
q => tmp11
);
aDel <= tmp11(SIG_WIDTH * 8 - 1 downto SIG_WIDTH * 7);
bDel <= tmp11(SIG_WIDTH * 7 - 1 downto SIG_WIDTH * 6);
yDel <= tmp11(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
wDel <= tmp11(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yIntDel4 <= tmp11(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wIntDel4 <= tmp11(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel <= tmp11(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel <= tmp11(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
end;
|
----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 19:12:14 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity trigger is
port (
-- Inputs
nrst : in std_logic;
clk108 : in std_logic;
trigger_btn : in std_logic;
trigger_event : in TRIGGER_EVENT_T;
red_enable : in std_logic;
green_enable : in std_logic;
blue_enable : in std_logic;
continue_after_reading : in std_logic;
red_input : in std_logic;
green_input : in std_logic;
blue_input : in std_logic;
overflow_indicator : in std_logic;
-- Outputs
red_output : out std_logic;
green_output : out std_logic;
blue_output : out std_logic;
is_reading_active : out std_logic
);
end trigger;
architecture behavioral of trigger is
signal internal_is_reading_active : std_logic := '0';
signal previous_trigger_btn : std_logic := '0';
signal previous_red_input : std_logic := '0';
signal previous_green_input : std_logic := '0';
signal previous_blue_input : std_logic := '0';
begin
is_reading_active <= internal_is_reading_active;
process (nrst, clk108) is
begin
if nrst = '0' then
red_output <= '0';
green_output <= '0';
blue_output <= '0';
internal_is_reading_active <= '0';
previous_trigger_btn <= '0';
previous_red_input <= '0';
previous_green_input <= '0';
previous_blue_input <= '0';
elsif rising_edge (clk108) then
red_output <= red_input and red_enable;
green_output <= green_input and green_enable;
blue_output <= blue_input and blue_enable;
previous_trigger_btn <= trigger_btn;
previous_red_input <= red_input;
previous_green_input <= green_input;
previous_blue_input <= blue_input;
if internal_is_reading_active = '0' then
-- reading is currently not active
if trigger_event = BUTTON_TRIGGER_T and
previous_trigger_btn = '0' and
trigger_btn = '1' then
-- Rising edge on trigger button.
internal_is_reading_active <= '1';
elsif trigger_event = RED_TRIGGER_T and
previous_red_input = '0' and
red_input = '1' then
-- Rising edge on red input.
internal_is_reading_active <= '1';
elsif trigger_event = GREEN_TRIGGER_T and
previous_green_input = '0' and
green_input = '1' then
-- Rising edge on green input.
internal_is_reading_active <= '1';
elsif trigger_event = BLUE_TRIGGER_T and
previous_blue_input = '0' and
blue_input = '1' then
-- Rising edge on blue input.
internal_is_reading_active <= '1';
end if;
else
-- reading is currently active
if previous_trigger_btn = '0' and trigger_btn = '1' then
internal_is_reading_active <= '0';
elsif overflow_indicator = '1' and continue_after_reading = '0' then
internal_is_reading_active <= '0';
end if;
end if;
end if;
end process;
end behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spa_ahb
-- File: ddr2spa_ahb.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynch AHB interface for DDR memory controller
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog: out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end ddr2spax_ahb;
architecture rtl of ddr2spax_ahb is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant ramwt: integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, DEVID, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ahbw: integer := log2(ahbbits);
constant l2ddrw: integer := log2(2*ddrbits);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_wabits: integer := 1+l2blen-5; -- log2(burstlen);
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw; -- log2(burstlen*32/ahbbits);
constant rbuf_rdbits: integer := ahbbits;
type ahbstate is (asnormal,asw1,asw2,asww1,asww2,aswr,aswwx);
type ahb_reg_type is record
s : ahbstate;
start_tog : std_logic;
ramaddr : std_logic_vector(l2blen-4 downto 2);
-- These are sent to the DDR layer
req : ddr_request_type;
-- Posted write following current request
nreq : ddr_request_type;
-- Read flow control
rctr_lin : std_logic_vector(3 downto 0);
endpos : std_logic_vector(7 downto log2(ddrbits/4));
block_read: std_logic_vector(1 downto 0);
-- Current AHB control signals
haddr : std_logic_vector(31 downto 0);
haddr_nonseq: std_logic_vector(9 downto 0);
hio : std_logic;
hsize : std_logic_vector(2 downto 0);
hwrite : std_logic;
hburst0 : std_logic;
-- AHB slave outputs
so_hready : std_logic;
-- From DDR layer
resp1,resp2: ddr_response_type;
end record;
signal ar,nar : ahb_reg_type;
begin
ahbcomb : process(ahbsi,rst,ar,response,rbrdata,hwidth,beid)
variable av: ahb_reg_type;
variable va2d: ddr_request_type;
variable so: ahb_slv_out_type;
variable vdone: std_logic;
variable vresp: ddr_response_type;
variable bigsize,midsize,canburst: std_logic;
variable inc_ramaddr: std_logic;
variable row: std_logic_vector(14 downto 0);
variable wbwa: std_logic_vector(wbuf_wabits-1 downto 0);
variable wbwd: std_logic_vector(wbuf_wdbits-1 downto 0);
variable wbw,wbwb: std_logic;
variable rbra: std_logic_vector(rbuf_rabits-1 downto 0);
variable ha0: std_logic_vector(31 downto 0);
variable rend,nrend: std_logic_vector(7 downto log2(ddrbits/4));
variable datavalid, writedone: std_logic;
variable rctr_gray: std_logic_vector(3 downto 0);
variable tog_start: std_logic;
variable regdata: std_logic_vector(31 downto 0);
begin
ha0 := ahbsi.haddr;
ha0(31 downto 20) := ha0(31 downto 20) and not std_logic_vector(to_unsigned(hmask,12));
av := ar;
so := (hready => ar.so_hready, hresp => HRESP_OKAY, hrdata => (others => '0'),
hsplit => (others => '0'), hirq => (others => '0'),
hconfig => hconfig, hindex => hindex);
wbw := '0';
wbwb := '0';
wbwa := ar.start_tog & ar.ramaddr;
wbwd := ahbreaddata(ahbsi.hwdata,ar.haddr(4 downto 2),
std_logic_vector(to_unsigned(log2(ahbbits/8),3)));
rbra := ar.ramaddr(l2blen-4 downto l2ahbw-3);
-- Determine whether the current hsize is a big (ahbbits-width) access
bigsize := '0';
if (ahbbits = 256 and ar.hsize(2)='1' and ar.hsize(0)='1') or
(ahbbits = 128 and ar.hsize(2)='1') or
(ahbbits = 64 and ar.hsize="011") then
bigsize := '1';
end if;
midsize := '0';
if ( (ahbbits = 256 and ((ar.hsize(2)='1' and ar.hsize(0)='0') or (ar.hsize(1 downto 0)="11"))) or
(ahbbits = 128 and ar.hsize="011") ) then
midsize := '1';
end if;
-- Determine whether sequential burst is allowed after current access
canburst := '0';
if (bigsize='1' and ar.haddr(l2blen-4 downto l2ahbw-3)/=(not zerov(l2blen-l2ahbw))) or
(ar.hsize="010" and ar.haddr(l2blen-4 downto 2)/=(not zerov(l2blen-5))) then
canburst := '1';
end if;
-- if canburst='1' then
-- print("ar.hsize=" & tost(ar.hsize) & "ar.haddr: " & tost(ar.haddr(l2blen-4 downto 2)) & " /= " & tost(not zerov(l2blen-5)));
-- end if;
if ar.hio='1' then
canburst := '0';
end if;
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.haddr := ha0;
av.ramaddr := ha0(log2(4*burstlen)-1 downto 2);
av.hio := ahbsi.hmbsel(1);
av.hsize := ahbsi.hsize;
av.hwrite := ahbsi.hwrite;
av.hburst0 := ahbsi.hburst(0);
if ahbsi.htrans(0)='0' or canburst='0' then
av.haddr_nonseq := ha0(9 downto 0);
end if;
end if;
-- Synchronize from DDR domain
av.resp1:=response; av.resp2:=ar.resp1;
vresp := ar.resp2;
if nosync /= 0 then vresp := response; end if;
vdone := vresp.done_tog;
-- Determine whether we can read more data in burst
datavalid := '0';
writedone := '0';
if ar.start_tog=vdone then
datavalid := '1';
writedone := '1';
end if;
if ar.rctr_lin="0000" then rend:=ar.haddr(7 downto l2ddrw-3); else rend:=ar.endpos; end if;
nrend := std_logic_vector(unsigned(rend)+1);
rctr_gray := lin2gray(ar.rctr_lin);
if ar.start_tog/=vdone and rctr_gray /= vresp.rctr_gray and ar.block_read(0)='0' then
av.rctr_lin := std_logic_vector(unsigned(ar.rctr_lin)+1);
av.endpos := nrend;
rend := nrend;
end if;
if 2*ddrbits > ahbbits then
if rend /= ar.haddr(7 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
else
if rend(7 downto log2(ahbbits/8)) /= ar.haddr(7 downto log2(ahbbits/8)) then
datavalid := '1';
end if;
if 2*ddrbits < ahbbits and ahbbits > 32 then
if ar.hsize="010" or ar.hsize="001" or ar.hsize="000" then
if rend(log2(ahbbits/8)-1 downto log2(ddrbits/4)) /=
ar.haddr(log2(ahbbits/8)-1 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
end if;
end if;
end if;
if ar.block_read(1)='1' or (ar.start_tog/=vdone and ar.block_read(0)='1') then
datavalid := '0';
writedone := '0';
end if;
if ar.block_read(1)='1' and ar.start_tog/=vdone then
av.block_read(1) := '0';
end if;
if ar.block_read(1)='0' and vresp.rctr_gray="0000" then
av.block_read(0) := '0';
end if;
-- FSM
inc_ramaddr := '0';
tog_start := '0';
case ar.s is
when asnormal =>
-- Idle and memory read state
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
-- Pass on address immediately to request for read case
av.req := (startaddr => ha0,
endaddr => ha0(9 downto 0),
hsize => ahbsi.hsize,
hwrite => ahbsi.hwrite,
hio => ahbsi.hmbsel(1),
burst => ahbsi.hburst(0),
maskdata => '0', maskcb => '0');
if ahbsi.hwrite='0' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
tog_start := '1';
elsif datavalid='1' then
inc_ramaddr := '1';
else
av.so_hready := '0';
-- grlib.testlib.print("Going to waitstate!");
end if;
else
av.s := asw1;
end if;
end if;
if ar.so_hready='0' and datavalid='1' then
av.so_hready := '1';
inc_ramaddr := '1';
end if;
when asw1 =>
-- Transfer data for write request
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.req.endaddr := ar.haddr(9 downto 0);
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
tog_start := '1';
end if;
else
av.s := asw2;
tog_start := '1';
end if;
when asw2 =>
-- Write request ongoing
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
elsif writedone='1' then
av.s := asnormal;
end if;
when asww1 =>
-- Transfer data for second write while write request ongoing
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
av.s := aswwx;
end if;
else
av.s := asww2;
end if;
when asww2 =>
-- Second write enqueued, wait for first write to finish
-- Any new request here will cause HREADY to go low
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.so_hready := '0';
av.s := aswwx;
elsif writedone='1' then
av.req := ar.nreq;
tog_start := '1';
av.s := asw2;
end if;
when aswr =>
-- Read request following ongoing write request
-- HREADY is low in this state
av.so_hready := '0';
if writedone='1' then
av.req := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.hwrite := '0';
tog_start := '1';
av.s := asnormal;
end if;
when aswwx =>
-- Write ongoing + write posted + another AHB request (read or write)
-- Keep HREADY low
av.so_hready := '0';
if writedone='1' then
tog_start := '1';
av.req := ar.nreq;
if ar.hwrite='1' then
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.so_hready := '1';
av.s := asww1;
else
av.s := aswr;
end if;
end if;
end case;
if tog_start='1' and (regarea=0 or av.req.hio='0' or av.req.startaddr(5)='0') then
av.start_tog := not ar.start_tog;
av.rctr_lin := "0000";
if ar.start_tog /= vdone then
av.block_read(1) := '1';
end if;
av.block_read(0) := '1';
end if;
if inc_ramaddr='1' then
if bigsize='1' then
av.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)))+1);
else
av.ramaddr(log2(4*burstlen)-1 downto 2) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto 2))+1);
end if;
end if;
-- Used only if regarea /= 0
regdata := (others => '0');
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/8),3));
if hwidth/='0' then
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/16),3));
end if;
regdata(15 downto 12) := beid;
-- If we are using AMBA-compliant data muxing, nothing needs to be done to
-- the hrdata vector. Otherwise, we need to duplicate 32-bit lanes
if regarea/=0 and ar.req.hio='1' and ar.req.startaddr(5)='1' then
so.hrdata := ahbdrivedata(regdata);
elsif CORE_ACDM /= 0 then
so.hrdata := ahbdrivedata(rbrdata);
else
so.hrdata := ahbselectdata(ahbdrivedata(rbrdata),ar.haddr(4 downto 2),ar.hsize);
end if;
if rst='0' then
av.s := asnormal;
av.block_read := "00";
av.start_tog := '0';
av.so_hready := '1';
so.hready := '1';
so.hresp := HRESP_OKAY;
end if;
if l2blen-l2ddrw < 4 then
av.rctr_lin(3 downto l2blen-l2ddrw) := (others => '0');
end if;
nar <= av;
request <= ar.req;
start_tog <= ar.start_tog;
ahbso <= so;
wbwrite <= wbw;
wbwritebig <= wbwb;
wbwaddr <= wbwa;
wbwdata <= wbwd;
rbraddr <= rbra;
end process;
ahbregs : process(clk_ahb)
begin
if rising_edge(clk_ahb) then
ar <= nar;
end if;
end process;
end;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ALU IS
PORT (a: IN std_logic_vector(31 DOWNTO 0);
b: IN std_logic_vector(31 DOWNTO 0);
alucontrol: IN bit_vector(2 DOWNTO 0);
zero: OUT bit;
result: OUT std_logic_vector(31 DOWNTO 0));
END ALU;
ARCHITECTURE ALU_arq OF ALU IS
BEGIN
PROCESS(a, b, alucontrol)
VARIABLE temp: std_logic_vector(31 DOWNTO 0);
BEGIN
CASE alucontrol IS
WHEN "000" => temp:= a AND b;
WHEN "001" => temp:= a OR b;
WHEN "010" => temp:= std_logic_vector(unsigned(a) + unsigned(b));
WHEN "011" => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
WHEN "100" => temp:= a AND (NOT b);
WHEN "101" => temp:= a OR (NOT b);
WHEN "110" => temp:= std_logic_vector(unsigned(a) - unsigned(b));
WHEN "111" =>
IF a<b THEN
temp := x"00000001";
ELSE
temp := x"00000000";
END IF;
WHEN OTHERS => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
END CASE;
result <= temp;
IF temp=x"00000000" THEN
zero <= '1';
ELSIF temp=x"00000001" THEN
zero <= '0';
END IF;
END PROCESS;
END ARCHITECTURE;
|
architecture ARCH of ENTITY1 is
begin
-- Passing
LABEL : assert boolean report "Something" severity FAILURE;
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;
assert boolean report "Something" severity FAILURE;
assert boolean
report "Something" severity FAILURE;
assert boolean report "Something"
severity FAILURE;
assert boolean
report "Something"
severity FAILURE;
-- Failing
LABEL : assert boolean report "Something" severity FAILURE;
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;
assert boolean report "Something" severity FAILURE;
assert boolean
report "Something" severity FAILURE;
assert boolean report "Something"
severity FAILURE;
assert boolean
report "Something"
severity FAILURE;
end architecture ARCH;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_rl-c.vhd,v 1.1 2005/04/10 18:07:26 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_rl_behav_c0 of tb_rl is
for behav
for dut_b : chip
use configuration work.chip_full_c0;
end for;
for card_b : card
use configuration work.card_behav_c0;
end for;
for rl_b : ram_loader
use configuration work.ram_loader_rtl_c0;
end for;
end for;
end tb_rl_behav_c0;
|
-- $Id: rlinktblib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rlinktblib
-- Description: rlink test environment components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 3.0.1 add rbtba_aif;
-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*;
-- many rri->rlink renames; drop rbus parts;
-- 2010-11-13 338 2.5.2 add rritb_core_dcm
-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-05 301 2.1.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.1.1 rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
-- drop RP_IINT signal from interfaces
-- add sbcntl_sbf_(cp|rp)mon defs
-- 2010-04-24 282 2.1 add rritb_core
-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.5 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.1.4 add AP_LAM for rritb_rpmon(_sb)
-- 2007-11-24 98 1.1.3 add RP_IINT for rritb_rpmon(_sb)
-- 2007-09-01 78 1.1.2 add rricp_rp
-- 2007-08-25 75 1.1.1 add rritb_cpmon_sb, rritb_rpmon_sb
-- 2007-08-16 74 1.1 remove rritb_tt* component; some interface changes
-- 2007-08-03 71 1.0.2 use rrirp_acif; change generics for rritb_[cr]pmon
-- 2007-07-22 68 1.0.1 add rritb_cpmon rritb_rpmon monitors
-- 2007-07-15 66 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rlinklib.all;
package rlinktblib is
type rlink_tba_cntl_type is record -- rlink_tba control
cmd : slv3; -- command code
ena : slbit; -- command enable
addr : slv8; -- address
cnt : slv8; -- block size
eop : slbit; -- end packet after current command
end record rlink_tba_cntl_type;
constant rlink_tba_cntl_init : rlink_tba_cntl_type := (
(others=>'0'), -- cmd
'0', -- ena
(others=>'0'), -- addr
(others=>'0'), -- cnt
'0'); -- eop
type rlink_tba_stat_type is record -- rlink_tba status
busy : slbit; -- command busy
ack : slbit; -- command acknowledge
err : slbit; -- command error flag
stat : slv8; -- status flags
braddr : slv8; -- block read address (for wblk)
bre : slbit; -- block read enable (for wblk)
bwaddr : slv8; -- block write address (for rblk)
bwe : slbit; -- block write enable (for rblk)
attnpend : slbit; -- attn pending
attnint : slbit; -- attn interrupt
end record rlink_tba_stat_type;
constant rlink_tba_stat_init : rlink_tba_stat_type := (
'0','0','0', -- busy, ack, err
(others=>'0'), -- stat
(others=>'0'), -- braddr
'0', -- bre
(others=>'0'), -- bwaddr
'0', -- bwe
'0','0'); -- attnpend, attnint
component rlink_tba is -- rlink test bench adapter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CNTL : in rlink_tba_cntl_type; -- control port
DI : in slv16; -- input data
STAT : out rlink_tba_stat_type; -- status port
DO : out slv16; -- output data
RL_DI : out slv9; -- rlink: data in
RL_ENA : out slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv9; -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : out slbit -- rlink: data hold
);
end component;
component rbtba_aif is -- rbus tba, abstract interface
-- no generics, no records
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ_aval : in slbit; -- rbus: request - aval
RB_MREQ_re : in slbit; -- rbus: request - re
RB_MREQ_we : in slbit; -- rbus: request - we
RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : in slv8; -- rbus: request - addr
RB_MREQ_din : in slv16; -- rbus: request - din
RB_SRES_ack : out slbit; -- rbus: response - ack
RB_SRES_busy : out slbit; -- rbus: response - busy
RB_SRES_err : out slbit; -- rbus: response - err
RB_SRES_dout : out slv16; -- rbus: response - dout
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end component;
component tbcore_rlink is -- core of vhpi_cext based test bench
generic (
CLK_PERIOD : time := 20 ns; -- clock period
CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLK : out slbit; -- main clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end component;
component tbcore_rlink_dcm is -- dcm aware core of vhpi_cext based tb
generic (
CLKOSC_PERIOD : time := 20 ns; -- clock osc period
CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLKOSC : out slbit; -- clock osc
CLKSYS : in slbit; -- DCM derived system clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end component;
-- FIXME after this point !!
component rricp_rp is -- rri comm->reg port aif forwarder
-- implements rricp_aif, uses rrirp_aif
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit :='0'; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit := '0' -- rlink: data hold
);
end component;
end package rlinktblib;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_eaa_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eaa_e-rtl-conf-c.vhd,v 1.1 2004/04/06 10:50:44 wig Exp $
-- $Date: 2004/04/06 10:50:44 $
-- $Log: inst_eaa_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:50:44 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_eaa_e_rtl_conf / inst_eaa_e
--
configuration inst_eaa_e_rtl_conf of inst_eaa_e is
for rtl
-- Generated Configuration
end for;
end inst_eaa_e_rtl_conf;
--
-- End of Generated Configuration inst_eaa_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_as - syn
-- Description: Cypress EZ-USB FX2 driver (2 fifo; async)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_1c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 65 153 64 133 s 7.2
-- 2012-01-03 449 13.3 O76x xc3s1200e-4 67 149 64 133 s 7.2
-- 2011-12-25 445 13.3 O76x xc3s1200e-4 61 147 64 127 s 7.2
-- 2011-12-25 444 13.3 O76x xc3s1200e-4 54 140 64 123 s 7.2
-- 2011-07-07 389 12.1 M53d xc3s1200e-4 45 132 64 109 s 7.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-14 453 1.3 common DELAY for PE and WR; use aempty/afull logic
-- 2012-01-04 450 1.2.2 use new FLAG layout (EF,FF now fixed)
-- 2012-01-03 449 1.2.1 use new fx2ctl_moni layout; hardcode ep's
-- 2011-12-25 445 1.2 change pktend handling, now timer based
-- 2011-11-25 433 1.1.1 now numeric_std clean
-- 2011-07-30 400 1.1 capture rx data in 2nd last s_rdpwh cycle
-- 2011-07-24 389 1.0.2 use FX2_FLAG_N to signal that flags are act.low
-- 2011-07-17 394 1.0.1 (RX|TX)FIFOEP now generics; add MONI port
-- 2011-07-08 390 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_as;
architecture syn of fx2_2fifoctl_as is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_init, -- s_init: init state
s_rdprep, -- s_rdprep: prepare read
s_rdwait, -- s_rdwait: wait for data
s_rdpwl, -- s_rdpwl: read, strobe low
s_rdpwh, -- s_rdpwh: read, strobe high
s_wrprep, -- s_wrprep: prepare write
s_wrpwl, -- s_wrpwl: write, strobe low
s_wrpwh, -- s_wrpwh: write, strobe high
s_peprep, -- s_peprep: prepare pktend
s_pepwl, -- s_pepwl: pktend, strobe low
s_pepwh -- s_pepwh: pktend, strobe high
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
dlycnt : slv4; -- wait delay counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (rx) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_init, -- state
petocnt_init, -- petocnt
'0', -- pepend
(others=>'0'), -- cntdly
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE : slv(TXFAWIDTH downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
begin
assert RDPWLDELAY<=2**R_REGS.dlycnt'length and
RDPWHDELAY<=2**R_REGS.dlycnt'length and RDPWHDELAY>=2 and
WRPWLDELAY<=2**R_REGS.dlycnt'length and
WRPWHDELAY<=2**R_REGS.dlycnt'length and
FLAGDELAY<=2**R_REGS.dlycnt'length
report "assert(*DELAY <= 2**dlycnt'length and RDPWHDELAY >=2)"
severity failure;
assert RXAEMPTY_THRES<=2**RXFAWIDTH and
TXAFULL_THRES<=2**TXFAWIDTH
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => CLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => CLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXSIZE
);
TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => TXSIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_USEC,
FX2_FLAG_N, TXFIFO_VAL, RXFIFO_BUSY, TXBUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idly_ld : slbit := '0';
variable idly_val : slv(r.dlycnt'range) := (others=>'0');
variable idly_end : slbit := '0';
variable idly_end1 : slbit := '0';
variable iflag_rdok : slbit := '0';
variable iflag_wrok : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
procedure go_rdprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_rxfifo;
nstate := s_rdprep;
end procedure go_rdprep;
procedure go_wrprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_wrprep;
end procedure go_wrprep;
procedure go_peprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_peprep;
end procedure go_peprep;
procedure go_rdpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islrd : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWLDELAY-1, n.dlycnt'length));
islrd := '1';
nstate := s_rdpwl;
end procedure go_rdpwl;
procedure go_wrpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islwr : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
islwr := '1';
nstate := s_wrpwl;
end procedure go_wrpwl;
procedure go_pepwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ipktend : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
ipktend := '1';
nstate := s_pepwl;
end procedure go_pepwl;
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
imoni := fx2ctl_moni_init;
iflag_rdok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
iflag_wrok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
idly_ld := '0';
idly_val := (others=>'0');
idly_end := '1';
idly_end1 := '0';
if unsigned(r.dlycnt) /= 0 then
idly_end := '0';
end if;
if unsigned(r.dlycnt) = 1 then
idly_end1 := '1';
end if;
case r.state is
when s_init => -- s_init:
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
when s_rdprep => -- s_rdprep: prepare read
if idly_end = '1' then
n.state := s_rdwait;
end if;
when s_rdwait => -- s_rdwait: wait for data
if r.pepend='1' and TXFIFO_VAL='0' then
go_peprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
elsif iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when s_rdpwl => -- s_rdpwl: read, strobe low
idata_cei := '1';
isloe := '1';
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWHDELAY-1, n.dlycnt'length));
n.state := s_rdpwh;
else
islrd := '1';
n.state := s_rdpwl;
end if;
-- Note: data is sampled and written into rxfifo in 2nd last cycle in the
-- last cycle the rxfifo busy reflects therefore last written byte
-- and safely indicates whether another byte will fit.
when s_rdpwh => -- s_rdpwh: read, strobe high
idata_cei := '1';
isloe := '1';
if idly_end1 = '1' then -- 2nd last cycle
irxfifo_ena := '1'; -- capture rxdata
end if;
if idly_end = '1' then -- last cycle
if iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
else
n.state := s_rdwait;
end if;
end if;
when s_wrprep => -- s_wrprep: prepare write
if idly_end = '1' then
if iflag_wrok = '1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_wrpwl => -- s_wrpwl: write, strobe low
idata_ceo := '1';
idata_oe := '1';
if idly_end = '1' then
idata_ceo := '0';
itxfifo_hold := '0';
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_wrpwh;
else
islwr := '1';
n.state := s_wrpwl;
end if;
when s_wrpwh => -- s_wrpwh: write, strobe high
idata_oe := '1';
if idly_end = '1' then
if iflag_wrok='1' and TXFIFO_VAL='1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
elsif iflag_wrok='1' and r.pepend='1' and TXFIFO_VAL='0' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_peprep => -- s_peprep: prepare pktend
if idly_end = '1' then
if iflag_wrok = '1' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_pepwl => -- s_pepwl: pktend, strobe low
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_pepwh;
else
ipktend := '1';
n.state := s_pepwl;
end if;
when s_pepwh => -- s_pepwh: pktend, strobe high
if idly_end = '1' then
n.pepend := '0';
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when others => null;
end case;
if idly_ld = '1' then
n.dlycnt := idly_val;
elsif idly_end = '0' then
n.dlycnt := slv(unsigned(r.dlycnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if CE_USEC = '1' and unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_wrprep or r.state = s_wrpwl or r.state = s_wrpwh or
r.state = s_peprep or r.state = s_pepwl or r.state = s_pepwh then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
else
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
end if;
imoni.fifo_ep4 := r.moni_ep4_sel;
imoni.fifo_ep6 := r.moni_ep6_sel;
imoni.flag_ep4_empty := not FX2_FLAG_N(c_flag_rx_ef);
imoni.flag_ep4_almost := r.moni_ep4_pf;
imoni.flag_ep6_full := not FX2_FLAG_N(c_flag_tx_ff);
imoni.flag_ep6_almost := r.moni_ep6_pf;
imoni.slrd := islrd;
imoni.slwr := islwr;
imoni.pktend := ipktend;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
MONI <= imoni;
end process proc_next;
proc_almost: process (RXSIZE, TXSIZE)
begin
-- (rx|tx)size is the number of bytes in fifo
-- --> rxsize is number of bytes which can be read
-- --> 2**txfawidth-txsize is is number of bytes which can be written
if unsigned(RXSIZE) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE) >= 2**TXFAWIDTH-TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
end syn;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.FiFo512Core32W32R_pkg.ALL;
ENTITY FiFo512Core32W32R_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF FiFo512Core32W32R_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:FiFo512Core32W32R_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity spm is
port(
clk : in vl_logic;
if_spm_addr : in vl_logic_vector(11 downto 0);
if_spm_as_n : in vl_logic;
if_spm_rw : in vl_logic;
if_spm_wr_data : in vl_logic_vector(31 downto 0);
if_spm_rd_data : out vl_logic_vector(31 downto 0);
mem_spm_addr : in vl_logic_vector(11 downto 0);
mem_spm_as_n : in vl_logic;
mem_spm_rw : in vl_logic;
mem_spm_wr_data : in vl_logic_vector(31 downto 0);
mem_spm_rd_data : out vl_logic_vector(31 downto 0)
);
end spm;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_inst_pkg.all;
use work.cpu_l1mem_inst_cache_pkg.all;
entity cpu_l1mem_inst_cache is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_inst_ctrl_in : out cpu_mmu_inst_ctrl_in_type;
cpu_mmu_inst_dp_in : out cpu_mmu_inst_dp_in_type;
cpu_mmu_inst_ctrl_out : in cpu_mmu_inst_ctrl_out_type;
cpu_mmu_inst_dp_out : in cpu_mmu_inst_dp_out_type;
cpu_l1mem_inst_cache_ctrl_in : in cpu_l1mem_inst_cache_ctrl_in_type;
cpu_l1mem_inst_cache_dp_in : in cpu_l1mem_inst_cache_dp_in_type;
cpu_l1mem_inst_cache_ctrl_out : out cpu_l1mem_inst_cache_ctrl_out_type;
cpu_l1mem_inst_cache_dp_out : out cpu_l1mem_inst_cache_dp_out_type;
sys_master_ctrl_out : out sys_master_ctrl_out_type;
sys_master_dp_out : out sys_master_dp_out_type;
sys_slave_ctrl_out : in sys_slave_ctrl_out_type;
sys_slave_dp_out : in sys_slave_dp_out_type
);
end;
|
architecture RTL of FIFO is
procedure proc1 is begin end procedure proc1;
PROCEDURE PROC1 IS BEGIN END PROCEDURE PROC1;
function func1 return integer is begin End function func1;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2205.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02205ent IS
END c07s02b06x00p01n01i02205ent;
ARCHITECTURE c07s02b06x00p01n01i02205arch OF c07s02b06x00p01n01i02205ent IS
BEGIN
TESTING: PROCESS
constant a : real := 10.0 * 2.0;
BEGIN
assert NOT(a = 20.0)
report "***PASSED TEST: c07s02b06x00p01n01i02205"
severity NOTE;
assert (a = 20.0)
report "***FAILED TEST: c07s02b06x00p01n01i02205 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02205arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2205.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02205ent IS
END c07s02b06x00p01n01i02205ent;
ARCHITECTURE c07s02b06x00p01n01i02205arch OF c07s02b06x00p01n01i02205ent IS
BEGIN
TESTING: PROCESS
constant a : real := 10.0 * 2.0;
BEGIN
assert NOT(a = 20.0)
report "***PASSED TEST: c07s02b06x00p01n01i02205"
severity NOTE;
assert (a = 20.0)
report "***FAILED TEST: c07s02b06x00p01n01i02205 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02205arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2205.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02205ent IS
END c07s02b06x00p01n01i02205ent;
ARCHITECTURE c07s02b06x00p01n01i02205arch OF c07s02b06x00p01n01i02205ent IS
BEGIN
TESTING: PROCESS
constant a : real := 10.0 * 2.0;
BEGIN
assert NOT(a = 20.0)
report "***PASSED TEST: c07s02b06x00p01n01i02205"
severity NOTE;
assert (a = 20.0)
report "***FAILED TEST: c07s02b06x00p01n01i02205 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02205arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1419.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p02n01i01419ent IS
END c08s06b00x00p02n01i01419ent;
ARCHITECTURE c08s06b00x00p02n01i01419arch OF c08s06b00x00p02n01i01419ent IS
BEGIN
TESTING: PROCESS
signal some : integer := 12;
signal p : integer := 3;
signal q : boolean := true;
BEGIN
some (p,q);
assert FALSE
report "***FAILED TEST: c08s06b00x00p02n01i01419 - A name that is not a procedure is used in a procedure call statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p02n01i01419arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1419.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p02n01i01419ent IS
END c08s06b00x00p02n01i01419ent;
ARCHITECTURE c08s06b00x00p02n01i01419arch OF c08s06b00x00p02n01i01419ent IS
BEGIN
TESTING: PROCESS
signal some : integer := 12;
signal p : integer := 3;
signal q : boolean := true;
BEGIN
some (p,q);
assert FALSE
report "***FAILED TEST: c08s06b00x00p02n01i01419 - A name that is not a procedure is used in a procedure call statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p02n01i01419arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1419.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p02n01i01419ent IS
END c08s06b00x00p02n01i01419ent;
ARCHITECTURE c08s06b00x00p02n01i01419arch OF c08s06b00x00p02n01i01419ent IS
BEGIN
TESTING: PROCESS
signal some : integer := 12;
signal p : integer := 3;
signal q : boolean := true;
BEGIN
some (p,q);
assert FALSE
report "***FAILED TEST: c08s06b00x00p02n01i01419 - A name that is not a procedure is used in a procedure call statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p02n01i01419arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity HAM_ENC is
port
(
data_in : in regflit; -- data input
data_out : out reghamm -- data output
);
end HAM_ENC;
architecture HAM_ENC of HAM_ENC is
signal P : Std_logic_vector(5 downto 1); --Hamming bits
begin
P(1) <= xor_reduce(data_in and MaskP1);
P(2) <= xor_reduce(data_in and MaskP2);
P(3) <= xor_reduce(data_in and MaskP4);
P(4) <= xor_reduce(data_in and MaskP8);
P(5) <= xor_reduce(data_in and MaskP16);
data_out <= P & xor_reduce(P & data_in);
end HAM_ENC; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity HAM_ENC is
port
(
data_in : in regflit; -- data input
data_out : out reghamm -- data output
);
end HAM_ENC;
architecture HAM_ENC of HAM_ENC is
signal P : Std_logic_vector(5 downto 1); --Hamming bits
begin
P(1) <= xor_reduce(data_in and MaskP1);
P(2) <= xor_reduce(data_in and MaskP2);
P(3) <= xor_reduce(data_in and MaskP4);
P(4) <= xor_reduce(data_in and MaskP8);
P(5) <= xor_reduce(data_in and MaskP16);
data_out <= P & xor_reduce(P & data_in);
end HAM_ENC; |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RECV_REQ_QUEUE_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RECV_REQ_QUEUE_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end RECV_REQ_QUEUE_top_wrapper;
architecture xilinx of RECV_REQ_QUEUE_top_wrapper is
SIGNAL clk_i : std_logic;
component RECV_REQ_QUEUE_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : RECV_REQ_QUEUE_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-------------------------------------------------------------------------------
-- system_v_tc_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library v_tc_v5_01_a;
use v_tc_v5_01_a.all;
entity system_v_tc_0_wrapper is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector(8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_v_tc_0_wrapper : entity is "v_tc_v5_01_a";
end system_v_tc_0_wrapper;
architecture STRUCTURE of system_v_tc_0_wrapper is
component v_tc is
generic (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_AUTO_SWITCH : integer;
C_MAX_PIXELS : integer;
C_MAX_LINES : integer;
C_NUM_FSYNCS : integer;
C_DETECT_EN : integer;
C_GENERATE_EN : integer;
C_DET_HSYNC_EN : integer;
C_DET_VSYNC_EN : integer;
C_DET_HBLANK_EN : integer;
C_DET_VBLANK_EN : integer;
C_DET_AVIDEO_EN : integer;
C_DET_ACHROMA_EN : integer;
C_GEN_HSYNC_EN : integer;
C_GEN_VSYNC_EN : integer;
C_GEN_HBLANK_EN : integer;
C_GEN_VBLANK_EN : integer;
C_GEN_AVIDEO_EN : integer;
C_GEN_ACHROMA_EN : integer;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_CPARITY : integer;
C_SYNC_EN : integer;
C_GEN_VBLANK_POLARITY : integer;
C_GEN_HBLANK_POLARITY : integer;
C_GEN_VSYNC_POLARITY : integer;
C_GEN_HSYNC_POLARITY : integer;
C_GEN_AVIDEO_POLARITY : integer;
C_GEN_ACHROMA_POLARITY : integer;
C_GEN_VACTIVE_SIZE : integer;
C_GEN_HACTIVE_SIZE : integer;
C_GEN_HFRAME_SIZE : integer;
C_GEN_F0_VFRAME_SIZE : integer;
C_GEN_HSYNC_START : integer;
C_GEN_HSYNC_END : integer;
C_GEN_F0_VBLANK_HSTART : integer;
C_GEN_F0_VBLANK_HEND : integer;
C_GEN_F0_VSYNC_VSTART : integer;
C_GEN_F0_VSYNC_VEND : integer;
C_GEN_F0_VSYNC_HSTART : integer;
C_GEN_F0_VSYNC_HEND : integer;
C_FSYNC_HSTART0 : integer;
C_FSYNC_VSTART0 : integer;
C_FSYNC_HSTART1 : integer;
C_FSYNC_VSTART1 : integer;
C_FSYNC_HSTART2 : integer;
C_FSYNC_VSTART2 : integer;
C_FSYNC_HSTART3 : integer;
C_FSYNC_VSTART3 : integer;
C_FSYNC_HSTART4 : integer;
C_FSYNC_VSTART4 : integer;
C_FSYNC_HSTART5 : integer;
C_FSYNC_VSTART5 : integer;
C_FSYNC_HSTART6 : integer;
C_FSYNC_VSTART6 : integer;
C_FSYNC_HSTART7 : integer;
C_FSYNC_VSTART7 : integer;
C_FSYNC_HSTART8 : integer;
C_FSYNC_VSTART8 : integer;
C_FSYNC_HSTART9 : integer;
C_FSYNC_VSTART9 : integer;
C_FSYNC_HSTART10 : integer;
C_FSYNC_VSTART10 : integer;
C_FSYNC_HSTART11 : integer;
C_FSYNC_VSTART11 : integer;
C_FSYNC_HSTART12 : integer;
C_FSYNC_VSTART12 : integer;
C_FSYNC_HSTART13 : integer;
C_FSYNC_VSTART13 : integer;
C_FSYNC_HSTART14 : integer;
C_FSYNC_VSTART14 : integer;
C_FSYNC_HSTART15 : integer;
C_FSYNC_VSTART15 : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_FAMILY : STRING
);
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(C_NUM_FSYNCS-1 to 0)
);
end component;
begin
v_tc_0 : v_tc
generic map (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_AUTO_SWITCH => 1,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_DETECT_EN => 0,
C_GENERATE_EN => 1,
C_DET_HSYNC_EN => 1,
C_DET_VSYNC_EN => 1,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_VIDEO_FORMAT => 0,
C_GEN_CPARITY => 0,
C_SYNC_EN => 0,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VACTIVE_SIZE => 720,
C_GEN_HACTIVE_SIZE => 1280,
C_GEN_HFRAME_SIZE => 1650,
C_GEN_F0_VFRAME_SIZE => 750,
C_GEN_HSYNC_START => 1390,
C_GEN_HSYNC_END => 1430,
C_GEN_F0_VBLANK_HSTART => 1280,
C_GEN_F0_VBLANK_HEND => 1280,
C_GEN_F0_VSYNC_VSTART => 724,
C_GEN_F0_VSYNC_VEND => 729,
C_GEN_F0_VSYNC_HSTART => 1280,
C_GEN_F0_VSYNC_HEND => 1280,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_FAMILY => "zynq"
)
port map (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aclken => s_axi_aclken,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
intc_if => intc_if,
clk => clk,
resetn => resetn,
clken => clken,
det_clken => det_clken,
gen_clken => gen_clken,
fsync_in => fsync_in,
vblank_in => vblank_in,
vsync_in => vsync_in,
hblank_in => hblank_in,
hsync_in => hsync_in,
active_video_in => active_video_in,
active_chroma_in => active_chroma_in,
vblank_out => vblank_out,
vsync_out => vsync_out,
hblank_out => hblank_out,
hsync_out => hsync_out,
active_video_out => active_video_out,
active_chroma_out => active_chroma_out,
fsync_out => fsync_out
);
end architecture STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity SwitchControl is
generic(
address : regflit := (others=>'0');
ramInit : memory);
port(
clock : in std_logic;
reset : in std_logic;
h : in regNport;
ack_h : out regNport;
data : in arrayNport_regflit;
sender : in regNport;
free : out regNport;
mux_in : out arrayNport_reg3;
mux_out : out arrayNport_reg3);
end SwitchControl;
architecture RoutingTable of SwitchControl is
type state is (S0,S1,S2,S3,S4,S5);
signal ES, PES: state;
signal ask: std_logic := '0';
signal sel,prox: integer range 0 to (NPORT-1) := 0;
signal incoming: reg3 := (others=> '0');
signal header : regflit := (others=> '0');
signal ready, enable : std_logic;
signal indice_dir: integer range 0 to (NPORT-1) := 0;
signal auxfree: regNport := (others=> '0');
signal source: arrayNport_reg3 := (others=> (others=> '0'));
signal sender_ant: regNport := (others=> '0');
signal dir: regNport:= (others=> '0');
signal requests: regNport := (others=> '0');
signal find: RouterControl;
signal ceTable: std_logic := '0';
signal selectedOutput : integer := 0;
signal isOutputSelected : std_logic;
begin
ask <= '1' when OR_REDUCTION(h) else '0';
incoming <= std_logic_vector(to_unsigned(sel, incoming'length));
header <= data(TO_INTEGER(unsigned(incoming)));
RoundRobinArbiter : entity work.arbiter(RoundRobinArbiter)
generic map(size => requests'length)
port map(
requests => h,
enable => enable,
selectedOutput => prox,
isOutputSelected => ready
);
RoutingMechanism : entity work.routingMechanism
generic map(
ramInit => ramInit,
LOCAL_ADDRESS => address
)
port map(
clock => clock,
reset => reset,
oe => ceTable,
dst_address => header,
inputPort => sel,
outputPort => dir,
find => find
);
FixedPriorityArbiter : entity work.arbiter(FixedPriorityArbiter)
generic map(size => requests'length)
port map(
requests => requests,
enable => '1',
isOutputSelected => isOutputSelected,
selectedOutput => selectedOutput
);
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif rising_edge(clock) then
ES<=PES;
end if;
end process;
process(ES, ask, find, isOutputSelected)
begin
case ES is
when S0 => PES <= S1;
when S1 =>
if ask='1' then
PES <= S2;
else
PES <= S1;
end if;
when S2 => PES <= S3;
when S3 =>
if(find = validRegion) then
if (isOutputSelected = '1') then
PES <= S4;
else
PES <= S1;
end if;
elsif(find = portError) then
PES <= S1;
else
PES <= S3;
end if;
when S4 => PES <= S5;
when S5 => PES <= S1;
end case;
end process;
process(clock)
begin
if rising_edge(clock) then
case ES is
when S0 =>
ceTable <= '0';
sel <= 0;
ack_h <= (others => '0');
auxfree <= (others=> '1');
sender_ant <= (others=> '0');
mux_out <= (others=>(others=>'0'));
source <= (others=>(others=>'0'));
when S1=>
enable <= ask;
ceTable <= '0';
ack_h <= (others => '0');
when S2=>
sel <= prox;
enable <= not ready;
when S3 =>
if(find = validRegion and isOutputSelected = '1') then
indice_dir <= selectedOutput;
else
ceTable <= '1';
end if;
when S4 =>
source(TO_INTEGER(unsigned(incoming))) <= std_logic_vector(to_unsigned(indice_dir, incoming'length));
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel)<='1';
when others =>
ack_h(sel)<='0';
ceTable <= '0';
end case;
sender_ant <= sender;
for i in EAST to LOCAL loop
if sender(i)='0' and sender_ant(i)='1' then
auxfree(TO_INTEGER(unsigned(source(i)))) <= '1';
end if;
end loop;
end if;
end process;
mux_in <= source;
free <= auxfree;
requests <= auxfree AND dir;
end RoutingTable;
|
-- ALUNOS:
-- Bruno Luiz da Silva
-- Gustavo Fernades
--
--
-- TÍTULO:
-- Controle de entradas
--
--
-- RESUMO:
-- Bloco que envia a sua entrada para um dos registradores desejados dependendo somente dos argumentos dados
--
--
-- ENTRADAS/SAÍDAS (I/O):
-- (I) a: as chaves SW serão conectadas aqui e posteriormente enviadas para certos componentes dependendo de
-- "arguments".
-- (I) reg: a parte alta da saída do registrador de 16 bits será conectada aqui para então alimentar certas
-- partes do componente de multiplicação, como por exemplo o bloco de adição e deslocamento.
-- (I) arguments: argumentos que serão dados (valores de 3 bits) os quais serão interpretados e darão um valor
-- lógico alto para uma porta de habilitação específica e as outras receberão valor lógico baixo.
-- (I) clk,rst: clock e reset, sendo que o reset zera todas saídas.
-- (O) l1,l2,s1,shift,n1: saídas que serão conectadas nas portas de habilitação dos outros componentes.
-- (O) q: saída de dados que será ou o valor "a" ou "reg".
--
--
-- DESCRIÇÃO:
-- As entradas "a" e "reg" serão enviadas para a saída, sendo essa redirecionada para alguns componentes. Para
-- escolher qual componente "receberá" o dado deve-se enviar um argumento (comando de 3 bits) para esse componente
-- (input_control) sendo que a cada valor desse argumento um componente diferente será habilitado. Segue a relação:
--
-- 000: nada
-- 001: saída será "a" e l1 (load 1) será alto - carregará o registrador de 8 bits
-- 010: saída será "a" e s1 (start) será alto - carregará a parte baixa do registrador de 16 bits
-- 011: saída será "reg" e l2 será alto - ativa o somador e o registrador de 16 bits, sendo que a soma realizada
-- será entre o valor do registrador de 8 bits com "reg" que será a parte alta do registrador de 16 bits.
-- O resultado da soma é enviado para a parte alta do registrador de 16 bits que estará ativado enquanto l2
-- for alto.
-- 100: shift será alto - habilitará o deslocamento do registrador de 16 bits, deslocando os bits a esquerda
-- 101: normalize será alto - habilitará a normalização do registrador de 16 bits, normalizando o valor armazenado.
--
--
-- ANEXO:
-- Ainda existem mais dois argumentos porém eles não fazem nenhuma operação aqui. São eles:
--
-- 110: realiza a soma entre os dois expoentes dados (a e b).
-- 111: realiza a subtração do atual valor guardado (soma de a e b) com o número de deslocamentos
-- realizados na normalização da mantissa.
--
--
-- (I): INPUT / (O): OUTPUT
library ieee;
use ieee.std_logic_1164.all;
entity input_control is
generic(N: natural := 8);
port(
a,reg: in std_logic_vector((N-1) downto 0); -- Dados de entrada
arguments: in std_logic_vector(2 downto 0); -- Argumentos
clk,rst: in std_logic; -- Clock, reset
l1,l2,s1,shift,n1: out std_logic; -- Saída de controle
q: out std_logic_vector((N-1) downto 0) -- Saída de dados
);
end input_control;
architecture func of input_control is
begin
INPUT: process(a,reg)
begin
if(rst = '1') then
q <= (others => '0');
else
-- Checar lista da DESCRIÇÃO para entender o que cada argumento realiza
case arguments is
when "001" =>
q <= a;
l1 <= '1';
s1 <= '0';
l2 <= '0';
shift <= '0';
n1 <= '0';
when "010" =>
q <= a;
l1 <= '0';
s1 <= '1';
l2 <= '0';
shift <= '0';
n1 <= '0';
when "011" =>
q <= reg;
l1 <= '0';
s1 <= '0';
l2 <= '1';
shift <= '0';
n1 <= '0';
when "100" =>
l1 <= '0';
s1 <= '0';
l2 <= '0';
shift <= '1';
n1 <= '0';
when "101" =>
l1 <= '0';
s1 <= '0';
l2 <= '0';
shift <= '0';
n1 <= '1';
when others =>
q <= (others => '0');
l1 <= '0';
s1 <= '0';
l2 <= '0';
shift <= '0';
n1 <= '0';
end case;
end if;
end process;
end func; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram256bw
-- File: syncram256bw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 256-bit syncronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram256bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram256bw is
component unisim_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component altera_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component altera_syncram256bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0)
);
end component;
component tm65gplus_syncram256bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
component cmos9sf_syncram256bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
signal xenable, xwrite : std_logic_vector(31 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
custominx <= (others => '0');
nocust: if has_sram256bw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
s256 : if has_sram256bw(tech) = 1 generate
uni : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128bw generic map (abits)
port map (clk, address, datain(127 downto 0), dataout(127 downto 0),
xenable(15 downto 0), xwrite(15 downto 0));
x1 : unisim_syncram128bw generic map (abits)
port map (clk, address, datain(255 downto 128), dataout(255 downto 128),
xenable(31 downto 16), xwrite(31 downto 16));
end generate;
alt : if (tech = stratix2) or (tech = stratix3) or (tech = stratix4) or
(tech = cyclone3) or (tech = altera) generate
x0 : altera_syncram256bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
tm65: if tech = tm65gplus generate
x0 : tm65gplus_syncram256bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
cm9s: if tech = cmos9sf generate
x0 : cmos9sf_syncram256bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram256bw: " & tost(2**abits) & "x256" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos256 : if has_sram256bw(tech) = 0 generate
rx : for i in 0 to 31 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i), testin
);
end generate;
end generate;
end;
|
-------------------------------------------------------------------------------
-- Title : Vivado DDS cos lut for SIRIUS 250M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_cos_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2016-04-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary cosine lut for SIRIUS machine with 250M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity dds_cos_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_cos_lut;
architecture str of dds_cos_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_cos_lut_sirius_52_181_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 181,
g_init_file => "cos_lut_sirius_52_181.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (falling_edge(clk)) then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (rising_edge(clk)) then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This checks detection of after outside clock processes
a <= b after 10 ns;
-- Violations below -----------------------------------
-- This process checks for missing after statements
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (falling_edge(clk)) then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (rising_edge(clk)) then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
end architecture ARCH;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 2K program for KCPSM6 in a 7-Series device using a
RAMB36E1 primitive with a content verifying CRC-16 circuit.
PLEASE READ THE DESCRIPTIONS AND ADVICE LATER IN THIS TEMPLATE OR CONTAINED IN THE
ASSEMBLED FILE.
Ken Chapman (Xilinx Ltd)
9th August 2012 - Initial Release
8th October 2012 - Optimised implementation.
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production definition of a 2K program for KCPSM6 in a 7-Series device using a
-- RAMB36E1 primitive with a content verifying CRC-16 error detection circuit.
--
-- NOTE - Compared with any of the normal program memory definitions for KCPSM6 this
-- module has additional inputs and outputs associated with the error detection
-- feature. Only use this module if there is a clear requirement to perform
-- error detection and do consider all the factors described below when
-- incorporating it in a design.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_7S_2K_with_error_detection_14March13.vhd
--
--
-- Error Detection Feature
-- -----------------------
--
-- In this application the BRAM is being used as a ROM and therefore the contents should
-- not change during normal operation. If for any reason the contents of the memory should
-- change then there is the potential for KCPSM6 to execute an instruction that is either
-- different to that expected or even an invalid op-code neither of which would be
-- desirable. Obviously this should not happen and in majority of cases it will be more
-- than acceptable to assume that it never will. However, designs in which extreme levels
-- of reliability or design security are required may consider that the special error
-- detection feature provided in this memory definition is useful.
--
-- This memory definition provides KCPSM6 with access to the program in the conventional
-- way using the first port of the BRAM. Then the second port of the BRAM is used to
-- continuously scan the whole memory and compute the CRC-16 of the entire contents. At
-- the end of each scan the result of each CRC calculation is compared with the expected
-- value (which was computed by the KCPSM6 assembler). If the value does not match then
-- the 'scan_error' output is forced High to inform the system of a potential corruption
-- somewhere within the memory.
--
--
-- SEU Mitigation
-- --------------
--
-- One concern for the very highest reliability systems are Single Event Upsets (SEU)
-- caused by radiation. FIT rates for BRAM are published and updated quarterly in UG116
-- and these should be used to evaluate the potential failure rates prior to using this
-- memory with its error detection circuit. It is vital to remember that everything in a
-- system contributes to the overall reliability. As such, the thoughtless addition of
-- features such as BRAM content error detection could in fact lower the overall
-- reliability of the system which obviously wouldn't be the intention! Two of the factors
-- to consider are as follows:-
--
-- a) Configuration memory is also susceptible to SEU and may impact the operation of
-- a design. Again the FIT rates are published in UG116 and the failure rates need
-- to be estimated. PicoBlaze itself, the error detection circuit defined in this
-- file and whatever you monitor and control the error detection circuit with are
-- all associated with configuration memory and therefore the potential exists for
-- a 'false alarm'. For example, and SEU could flip a configuration memory cell that
-- altered the logic of the error detection circuit resulting in a 'scan_error' even
-- though the BRAM contents are good.
--
-- b) If one bit within the BRAM is flipped by an SEU (the typical effect), it could
-- take up to ~73,740 'scan_clk' cycles for the error to be detected and reported.
-- This worst case detection time is equivalent two complete scans of the memory
-- and would only occur if the SEU flips a bit very close to the start of the
-- memory (address zero) just after the scan has just passed that location. Hence,
-- the average detection time will be one complete scan (36,873 'scan_clk' cycles).
-- During the time taken to detect and report the error, and any time leading up to
-- your decision to take some suitable action, KCPSM6 may execute the instruction
-- that has been corrupted. The impact of executing that corrupted instruction is
-- anyone's guess! However, in terms of estimating the failure rate it is important
-- to recognise that KCPSM6 must actually read and execute the corrupted instruction
-- for anything unexpected to occur. So whilst the error detection circuit will
-- report when an error is present in the memory it definitely does not mean that
-- KCPSM6 has or will definitely go wrong. KCPSM6 programs rarely occupy all the
-- memory locations so the failure rate estimate should be scaled accordingly.
-- Likewise, most programs consist of some code that is used frequently and other
-- code which is only used occasionally (e.g. some code is only used during
-- initialisation). So once again the failure rate can often be scaled appropriately
-- to reflect the actual code. Due to these scaling factors there is quite a high
-- probability that a real upset will be detected and reported but for there to be
-- no effect on the program execution. Whilst this is not a 'false alarm' is may
-- appear to be. Detection of any error is valuable in a fail-safe system but it can
-- adversely impact the overall availability of systems if every alarm results in
-- an interruption to service. Therefore, deciding what action to take when an error
-- is detected is critical before opting to us this memory module with KCPSM6.
--
--
-- Design Security
-- ---------------
--
-- Devices of the 7-Series which this memory definition is intended to service provide
-- Bitstream Security in the form of AES encryption so obviously this should be of
-- high relevance for anyone concerned with design security. However, there may be
-- reasons not to use that feature or a desire to further enhance security in other ways.
-- Whilst it would be a significant challenge to reverse engineer a bitstream (assuming it
-- wasn't encrypted or was somehow decrypted), it is feasible to alter or tamper with the
-- bits in what is often referred to as 'side attacks'.
--
-- On a scale of difficulty it should be recognised that BRAM contents are one of the
-- easier targets for such attacks. Note that the DATA2MEM tool (see UG658) intended to
-- help accelerate design development would also be a useful tool for an attacker!
-- Obviously the ability to tamper with BRAM contents means that the program for a KCPSM6
-- processor could be altered or replaced. Depending on the purpose of that code it could
-- definitely compromise security.
--
-- Since the error detection circuit will report any changes to the memory contents this
-- scheme can also be used to detect attacks and somehow disable the design to prevent the
-- attacker making progress. For example, the 'scan_error' signal could be used to
-- permanently reset KCPSM6 or be used to disable something else in the design such as
-- putting critical output pins of the device into a high impedance state.
--
--
-- Using the Error Detection Feature in a Design
-- ---------------------------------------------
--
-- Whether this feature is used for SEU mitigation or design security it is highly
-- recommended that signals and logic associated with the error detection feature remain
-- isolated from the KCPSM6 processor; i.e. it certainly wouldn't be a good idea to
-- monitor the error signal with the same KCPSM6 given that any change to the
-- program may prevent KCPSM6 from reacting as intended in the first place. However,
-- it would be a valid arrangement for two or more KCPSM6 processors to monitor the
-- health of each other's memory providing they too had a reasonable degree of
-- independence(e.g. avoiding a common point such as using the same clock).
--
-- As with most digital circuits the clock is critical for reliable operation. In terms
-- failure rates then SEU are so rare that things like an irregular clock cycle or glitch
-- possibly caused by power surge could be as likely to impact the integrity of the
-- CRC-16 calculation and result in a false alarm. So always give consideration to the
-- source of your clock including any use of clock division or multiplication schemes
-- implemented within the FPGA before it is applied to the 'scan_clk' input of this module.
--
-- In most applications the 'scan_reset' control can be driven or tied Low. The report of
-- any error would be a rare event but would generally be considered a permanent error
-- until the device is reconfigured. However, there is the small possibility that an SEU
-- or clock glitch could impact the logical operation of the error detection circuit
-- resulting in a 'false alarm'. In these situations, the device level SEU mitigation
-- measures would detect and subsequently correct the configuration memory error or the
-- clock source would recover. Applying a synchronous pulse to 'scan_reset' would then
-- clear the false alarm and allow the memory checking to continue. Ultimately, design
-- for reliability must consider the interaction between all elements of the system and
-- can not simply focus on one issue like the BRAM contents.
--
-- In situations where the clock may take time to settle following device configuration
-- the error detection circuit should be held in reset until the integrity of the clock
-- can be assured.
--
-- Note that the 'scan_error' signal has be deliberately designed to 'latch' any error
-- that is detected (i.e. false alarms are not cleared automatically by a subsequent good
-- scan of the memory). This scheme ensures that no error reports can be missed by a
-- monitor which only checks occasionally. It is always the responsibility of the system
-- to decide what action to take when an error is reported. Some systems may initially
-- reset the error detection circuit in order to confirm the error is permanent before
-- taking more significant actions.
--
-- The 'scan_complete' signal is a single clock cycle pulse generated at the end of each
-- CRC-16 calculation. This signal could be ignored but for both reliability and security
-- purposes it is extremely useful to know that the error detection circuit is actually
-- working and these pulses will confirm that it is (one pulse every 36,873 'scan_clk'
-- cycles). For example, these pulses confirm that the clock is being supplied and has not
-- been disabled by an SEU, oscillator failure, board defect or a malicious attacker.
--
--
-------------------------------------------------------------------------------------------
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic;
scan_error : out std_logic;
scan_complete : out std_logic;
scan_reset : in std_logic;
scan_clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
--
signal previous_scan_address : std_logic_vector(11 downto 0);
signal sa_carry_primer : std_logic_vector(11 downto 0);
signal scan_address_carry : std_logic_vector(11 downto 0);
signal scan_address_value : std_logic_vector(11 downto 0);
signal scan_address : std_logic_vector(11 downto 0);
signal scan_address_ce_value : std_logic;
signal scan_address_ce : std_logic;
signal scan_data : std_logic_vector(8 downto 0);
signal scan_bit_value : std_logic_vector(3 downto 0);
signal scan_bit : std_logic_vector(3 downto 0);
signal scan_mid : std_logic;
signal scan_high : std_logic;
signal scan_byte : std_logic;
signal crc_reset_value : std_logic;
signal crc_reset : std_logic;
signal crc : std_logic_vector(16 downto 1);
signal crc1_value : std_logic;
signal crc2_value : std_logic;
signal crc3_value : std_logic;
signal crc16_value : std_logic;
signal serial_data_value : std_logic;
signal serial_data : std_logic;
signal last_address_value : std_logic;
signal last_address : std_logic;
signal last_bit : std_logic;
signal end_of_scan : std_logic;
signal crc_test : std_logic;
signal crc_check_value : std_logic;
signal crc_check : std_logic;
--
attribute hblknm : string;
attribute hblknm of crc16_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc1_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc2_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc3_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc4_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc5_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc6_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc7_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc1_lut : label is "kcpsm6_program_crc1";
attribute hblknm of crc3_lut : label is "kcpsm6_program_crc1";
--
attribute hblknm of crc8_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc9_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc10_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc11_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc12_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc13_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc14_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc15_flop : label is "kcpsm6_program_crc2";
--
attribute hblknm of scan_bit0_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit1_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit2_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit3_flop : label is "kcpsm6_program_crc3";
attribute hblknm of crc_reset_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_address_ce_flop : label is "kcpsm6_program_crc3";
attribute hblknm of crc_check_flop : label is "kcpsm6_program_crc3";
attribute hblknm of last_address_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit01_lut : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit23_lut : label is "kcpsm6_program_crc3";
attribute hblknm of crc_reset_lut : label is "kcpsm6_program_crc3";
attribute hblknm of crc_check_lut : label is "kcpsm6_program_crc3";
--
attribute hblknm of serial_data_flop : label is "kcpsm6_program_crc4";
attribute hblknm of last_bit_flop : label is "kcpsm6_program_crc4";
attribute hblknm of end_of_scan_flop : label is "kcpsm6_program_crc4";
attribute hblknm of scan_complete_flop : label is "kcpsm6_program_crc4";
attribute hblknm of serial_data_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_mid_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_high_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_byte_muxf7 : label is "kcpsm6_program_crc4";
--
attribute hblknm of scan_address0_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_muxcy : label is "kcpsm6_program_crc5";
--
attribute hblknm of scan_address4_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_muxcy : label is "kcpsm6_program_crc6";
--
attribute hblknm of scan_address8_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_muxcy : label is "kcpsm6_program_crc7";
--
begin
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
--
address_b <= '1' & scan_address(11 downto 0) & "111";
data_in_b <= "000000000000000000000000000000000000";
scan_data <= data_out_b(32) & data_out_b(7 downto 0);
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => '1',
CLKBWRCLK => scan_clk,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => "00000000",
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
-- Error Detection Circuit
--
scan_mid_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => scan_data(1),
I1 => scan_data(2),
I2 => scan_data(3),
I3 => scan_data(4),
I4 => scan_bit(0),
I5 => scan_bit(1),
O => scan_mid);
--
scan_high_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => scan_data(5),
I1 => scan_data(6),
I2 => scan_data(7),
I3 => scan_data(8),
I4 => scan_bit(0),
I5 => scan_bit(1),
O => scan_high);
--
scan_byte_muxf7: MUXF7
port map( I0 => scan_mid,
I1 => scan_high,
S => scan_bit(2),
O => scan_byte);
--
crc1_lut: LUT6_2
generic map (INIT => X"F0F0F0F066666666")
port map( I0 => serial_data,
I1 => crc(16),
I2 => crc(1),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => crc1_value,
O6 => crc2_value);
--
crc3_lut: LUT6_2
generic map (INIT => X"C33C0000A55A0000")
port map( I0 => crc(2),
I1 => crc(15),
I2 => crc(16),
I3 => serial_data,
I4 => '1',
I5 => '1',
O5 => crc3_value,
O6 => crc16_value);
--
crc1_flop: FDR
port map ( D => crc1_value,
Q => crc(1),
R => crc_reset,
C => scan_clk);
--
crc2_flop: FDR
port map ( D => crc2_value,
Q => crc(2),
R => crc_reset,
C => scan_clk);
--
crc3_flop: FDR
port map ( D => crc3_value,
Q => crc(3),
R => crc_reset,
C => scan_clk);
--
crc4_flop: FDR
port map ( D => crc(3),
Q => crc(4),
R => crc_reset,
C => scan_clk);
--
crc5_flop: FDR
port map ( D => crc(4),
Q => crc(5),
R => crc_reset,
C => scan_clk);
--
crc6_flop: FDR
port map ( D => crc(5),
Q => crc(6),
R => crc_reset,
C => scan_clk);
--
crc7_flop: FDR
port map ( D => crc(6),
Q => crc(7),
R => crc_reset,
C => scan_clk);
--
crc8_flop: FDR
port map ( D => crc(7),
Q => crc(8),
R => crc_reset,
C => scan_clk);
--
crc9_flop: FDR
port map ( D => crc(8),
Q => crc(9),
R => crc_reset,
C => scan_clk);
--
crc10_flop: FDR
port map ( D => crc(9),
Q => crc(10),
R => crc_reset,
C => scan_clk);
--
crc11_flop: FDR
port map ( D => crc(10),
Q => crc(11),
R => crc_reset,
C => scan_clk);
--
crc12_flop: FDR
port map ( D => crc(11),
Q => crc(12),
R => crc_reset,
C => scan_clk);
--
crc13_flop: FDR
port map ( D => crc(12),
Q => crc(13),
R => crc_reset,
C => scan_clk);
--
crc14_flop: FDR
port map ( D => crc(13),
Q => crc(14),
R => crc_reset,
C => scan_clk);
--
crc15_flop: FDR
port map ( D => crc(14),
Q => crc(15),
R => crc_reset,
C => scan_clk);
--
crc16_flop: FDR
port map ( D => crc16_value,
Q => crc(16),
R => crc_reset,
C => scan_clk);
--
scan_bit01_lut: LUT6_2
generic map (INIT => X"0000E6660000D555")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => end_of_scan,
I5 => '1',
O5 => scan_bit_value(0),
O6 => scan_bit_value(1));
--
scan_bit23_lut: LUT6_2
generic map (INIT => X"00007F800000F878")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => end_of_scan,
I5 => '1',
O5 => scan_bit_value(2),
O6 => scan_bit_value(3));
--
scan_bit0_flop: FDR
port map ( D => scan_bit_value(0),
Q => scan_bit(0),
R => scan_reset,
C => scan_clk);
--
scan_bit1_flop: FDR
port map ( D => scan_bit_value(1),
Q => scan_bit(1),
R => scan_reset,
C => scan_clk);
--
scan_bit2_flop: FDR
port map ( D => scan_bit_value(2),
Q => scan_bit(2),
R => scan_reset,
C => scan_clk);
--
scan_bit3_flop: FDR
port map ( D => scan_bit_value(3),
Q => scan_bit(3),
R => scan_reset,
C => scan_clk);
--
crc_reset_lut: LUT6_2
generic map (INIT => X"007F000020000000")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => '1',
I5 => '1',
O5 => scan_address_ce_value,
O6 => crc_reset_value);
--
scan_address_ce_flop: FDR
port map ( D => scan_address_ce_value,
Q => scan_address_ce,
R => scan_reset,
C => scan_clk);
--
crc_reset_flop: FDR
port map ( D => crc_reset_value,
Q => crc_reset,
R => scan_reset,
C => scan_clk);
--
crc_check_lut: LUT6_2
generic map (INIT => X"FF00F0F088888888")
port map( I0 => scan_address_carry(11),
I1 => scan_address_ce,
I2 => crc_check,
I3 => crc_test,
I4 => end_of_scan,
I5 => '1',
O5 => last_address_value,
O6 => crc_check_value);
--
crc_check_flop: FDR
port map ( D => crc_check_value,
Q => crc_check,
R => scan_reset,
C => scan_clk);
--
last_address_flop: FDR
port map ( D => last_address_value,
Q => last_address,
R => scan_reset,
C => scan_clk);
--
scan_address0_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(0),
I5 => '1',
O5 => sa_carry_primer(0),
O6 => previous_scan_address(0));
--
scan_address0_xorcy: XORCY
port map( LI => previous_scan_address(0),
CI => '1',
O => scan_address_value(0));
--
scan_address0_muxcy: MUXCY
port map( DI => sa_carry_primer(0),
CI => '1',
S => previous_scan_address(0),
O => scan_address_carry(0));
--
scan_address0_flop: FDRE
port map ( D => scan_address_value(0),
Q => scan_address(0),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address1_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(1),
I5 => '1',
O5 => sa_carry_primer(1),
O6 => previous_scan_address(1));
--
scan_address1_xorcy: XORCY
port map( LI => previous_scan_address(1),
CI => scan_address_carry(0),
O => scan_address_value(1));
--
scan_address1_muxcy: MUXCY
port map( DI => sa_carry_primer(1),
CI => scan_address_carry(0),
S => previous_scan_address(1),
O => scan_address_carry(1));
--
scan_address1_flop: FDRE
port map ( D => scan_address_value(1),
Q => scan_address(1),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address2_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(2),
I5 => '1',
O5 => sa_carry_primer(2),
O6 => previous_scan_address(2));
--
scan_address2_xorcy: XORCY
port map( LI => previous_scan_address(2),
CI => scan_address_carry(1),
O => scan_address_value(2));
--
scan_address2_muxcy: MUXCY
port map( DI => sa_carry_primer(2),
CI => scan_address_carry(1),
S => previous_scan_address(2),
O => scan_address_carry(2));
--
scan_address2_flop: FDRE
port map ( D => scan_address_value(2),
Q => scan_address(2),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address3_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(3),
I5 => '1',
O5 => sa_carry_primer(3),
O6 => previous_scan_address(3));
--
scan_address3_xorcy: XORCY
port map( LI => previous_scan_address(3),
CI => scan_address_carry(2),
O => scan_address_value(3));
--
scan_address3_muxcy: MUXCY
port map( DI => sa_carry_primer(3),
CI => scan_address_carry(2),
S => previous_scan_address(3),
O => scan_address_carry(3));
--
scan_address3_flop: FDRE
port map ( D => scan_address_value(3),
Q => scan_address(3),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address4_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(4),
I5 => '1',
O5 => sa_carry_primer(4),
O6 => previous_scan_address(4));
--
scan_address4_xorcy: XORCY
port map( LI => previous_scan_address(4),
CI => scan_address_carry(3),
O => scan_address_value(4));
--
scan_address4_muxcy: MUXCY
port map( DI => sa_carry_primer(4),
CI => scan_address_carry(3),
S => previous_scan_address(4),
O => scan_address_carry(4));
--
scan_address4_flop: FDRE
port map ( D => scan_address_value(4),
Q => scan_address(4),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address5_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(5),
I5 => '1',
O5 => sa_carry_primer(5),
O6 => previous_scan_address(5));
--
scan_address5_xorcy: XORCY
port map( LI => previous_scan_address(5),
CI => scan_address_carry(4),
O => scan_address_value(5));
--
scan_address5_muxcy: MUXCY
port map( DI => sa_carry_primer(5),
CI => scan_address_carry(4),
S => previous_scan_address(5),
O => scan_address_carry(5));
--
scan_address5_flop: FDRE
port map ( D => scan_address_value(5),
Q => scan_address(5),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address6_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(6),
I5 => '1',
O5 => sa_carry_primer(6),
O6 => previous_scan_address(6));
--
scan_address6_xorcy: XORCY
port map( LI => previous_scan_address(6),
CI => scan_address_carry(5),
O => scan_address_value(6));
--
scan_address6_muxcy: MUXCY
port map( DI => sa_carry_primer(6),
CI => scan_address_carry(5),
S => previous_scan_address(6),
O => scan_address_carry(6));
--
scan_address6_flop: FDRE
port map ( D => scan_address_value(6),
Q => scan_address(6),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address7_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(7),
I5 => '1',
O5 => sa_carry_primer(7),
O6 => previous_scan_address(7));
--
scan_address7_xorcy: XORCY
port map( LI => previous_scan_address(7),
CI => scan_address_carry(6),
O => scan_address_value(7));
--
scan_address7_muxcy: MUXCY
port map( DI => sa_carry_primer(7),
CI => scan_address_carry(6),
S => previous_scan_address(7),
O => scan_address_carry(7));
--
scan_address7_flop: FDRE
port map ( D => scan_address_value(7),
Q => scan_address(7),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address8_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(8),
I5 => '1',
O5 => sa_carry_primer(8),
O6 => previous_scan_address(8));
--
scan_address8_xorcy: XORCY
port map( LI => previous_scan_address(8),
CI => scan_address_carry(7),
O => scan_address_value(8));
--
scan_address8_muxcy: MUXCY
port map( DI => sa_carry_primer(8),
CI => scan_address_carry(7),
S => previous_scan_address(8),
O => scan_address_carry(8));
--
scan_address8_flop: FDRE
port map ( D => scan_address_value(8),
Q => scan_address(8),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address9_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(9),
I5 => '1',
O5 => sa_carry_primer(9),
O6 => previous_scan_address(9));
--
scan_address9_xorcy: XORCY
port map( LI => previous_scan_address(9),
CI => scan_address_carry(8),
O => scan_address_value(9));
--
scan_address9_muxcy: MUXCY
port map( DI => sa_carry_primer(9),
CI => scan_address_carry(8),
S => previous_scan_address(9),
O => scan_address_carry(9));
--
scan_address9_flop: FDRE
port map ( D => scan_address_value(9),
Q => scan_address(9),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address10_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(10),
I5 => '1',
O5 => sa_carry_primer(10),
O6 => previous_scan_address(10));
--
scan_address10_xorcy: XORCY
port map( LI => previous_scan_address(10),
CI => scan_address_carry(9),
O => scan_address_value(10));
--
scan_address10_muxcy: MUXCY
port map( DI => sa_carry_primer(10),
CI => scan_address_carry(9),
S => previous_scan_address(10),
O => scan_address_carry(10));
--
scan_address10_flop: FDRE
port map ( D => scan_address_value(10),
Q => scan_address(10),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address11_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(11),
I5 => '1',
O5 => sa_carry_primer(11),
O6 => previous_scan_address(11));
--
scan_address11_xorcy: XORCY
port map( LI => previous_scan_address(11),
CI => scan_address_carry(10),
O => scan_address_value(11));
--
scan_address11_muxcy: MUXCY
port map( DI => sa_carry_primer(11),
CI => scan_address_carry(10),
S => previous_scan_address(11),
O => scan_address_carry(11));
--
scan_address11_flop: FDRE
port map ( D => scan_address_value(11),
Q => scan_address(11),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
serial_data_lut: LUT6
generic map (INIT => X"CACACACACACACACA")
port map( I0 => scan_data(0),
I1 => scan_byte,
I2 => scan_bit(3),
I3 => '1',
I4 => '1',
I5 => '1',
O => serial_data_value);
--
serial_data_flop: FD
port map ( D => serial_data_value,
Q => serial_data,
C => scan_clk);
--
last_bit_flop: FD
port map ( D => last_address,
Q => last_bit,
C => scan_clk);
--
end_of_scan_flop: FD
port map ( D => last_bit,
Q => end_of_scan,
C => scan_clk);
--
scan_complete_flop: FD
port map ( D => end_of_scan,
Q => scan_complete,
C => scan_clk);
--
crc_test <= '0' when (crc = "{CRC_2K}") else '1';
--
scan_error <= crc_check;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_1 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_1;
ARCHITECTURE design_1_FIR_resized1_1_arch OF design_1_FIR_resized1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_1_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_FIR_resized1_1_arch: ARCHITECTURE IS "fir_compiler_v7_2_6,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_FIR_resized1_1_arch : ARCHITECTURE IS "design_1_FIR_resized1_1,fir_compiler_v7_2_6,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_FIR_resized1_1_arch: ARCHITECTURE IS "design_1_FIR_resized1_1,fir_compiler_v7_2_6,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=design_1_FIR_resized1_1,C_COEF_FILE=design_1_FIR_resized1_1.mif,C_COEF_FILE_LINES=16,C_FILTER_TYPE=0,C_INTERP_RATE=1,C_DECIM_RATE=1,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=32,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=f" &
"ixed,C_ROUND_MODE=1,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=1,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=24,C_DATA_IP_PATH_WIDTHS=24,C_DATA_PX_PATH_WIDTHS=24,C_DATA_WIDTH=24,C_COEF_PATH_WIDTHS=16,C_COEF_WIDTH=16,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_PX_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=41,C_OUTPUT_WIDTH=32,C_OUTPUT_PATH_WIDTHS=32,C_ACCUM_OP_PATH_WIDTHS=41,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_M" &
"ADDS=1,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=16,C_INPUT_RATE=25,C_OUTPUT_RATE=25,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=2,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=23,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=24,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_TUSER_WIDTH=1,C_HAS_C" &
"ONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_1",
C_COEF_FILE => "design_1_FIR_resized1_1.mif",
C_COEF_FILE_LINES => 16,
C_FILTER_TYPE => 0,
C_INTERP_RATE => 1,
C_DECIM_RATE => 1,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 32,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "1",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "41",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "41",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 1,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 16,
C_INPUT_RATE => 25,
C_OUTPUT_RATE => 25,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 23,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_1 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_1;
ARCHITECTURE design_1_FIR_resized1_1_arch OF design_1_FIR_resized1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_1_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_FIR_resized1_1_arch: ARCHITECTURE IS "fir_compiler_v7_2_6,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_FIR_resized1_1_arch : ARCHITECTURE IS "design_1_FIR_resized1_1,fir_compiler_v7_2_6,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_FIR_resized1_1_arch: ARCHITECTURE IS "design_1_FIR_resized1_1,fir_compiler_v7_2_6,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=design_1_FIR_resized1_1,C_COEF_FILE=design_1_FIR_resized1_1.mif,C_COEF_FILE_LINES=16,C_FILTER_TYPE=0,C_INTERP_RATE=1,C_DECIM_RATE=1,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=32,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=f" &
"ixed,C_ROUND_MODE=1,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=1,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=24,C_DATA_IP_PATH_WIDTHS=24,C_DATA_PX_PATH_WIDTHS=24,C_DATA_WIDTH=24,C_COEF_PATH_WIDTHS=16,C_COEF_WIDTH=16,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_PX_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=41,C_OUTPUT_WIDTH=32,C_OUTPUT_PATH_WIDTHS=32,C_ACCUM_OP_PATH_WIDTHS=41,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_M" &
"ADDS=1,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=16,C_INPUT_RATE=25,C_OUTPUT_RATE=25,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=2,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=23,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=24,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_TUSER_WIDTH=1,C_HAS_C" &
"ONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_1",
C_COEF_FILE => "design_1_FIR_resized1_1.mif",
C_COEF_FILE_LINES => 16,
C_FILTER_TYPE => 0,
C_INTERP_RATE => 1,
C_DECIM_RATE => 1,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 32,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "1",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "41",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "41",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 1,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 16,
C_INPUT_RATE => 25,
C_OUTPUT_RATE => 25,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 23,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_0;
ARCHITECTURE design_1_cic_compiler_0_0_arch OF design_1_cic_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_0",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 25,
C_INPUT_WIDTH => 14,
C_OUTPUT_WIDTH => 33,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 25,
C_MAX_RATE => 25,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 33,
C_C2 => 33,
C_C3 => 33,
C_C4 => 33,
C_C5 => 0,
C_C6 => 0,
C_I1 => 33,
C_I2 => 33,
C_I3 => 33,
C_I4 => 33,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 40,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_0;
ARCHITECTURE design_1_cic_compiler_0_0_arch OF design_1_cic_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_0",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 25,
C_INPUT_WIDTH => 14,
C_OUTPUT_WIDTH => 33,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 25,
C_MAX_RATE => 25,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 33,
C_C2 => 33,
C_C3 => 33,
C_C4 => 33,
C_C5 => 0,
C_C6 => 0,
C_I1 => 33,
C_I2 => 33,
C_I3 => 33,
C_I4 => 33,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 40,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_0_arch;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
--! @details This module absolutely similar to the 'inferred' implementation
--! but it support initialization of the SRAM.
--! This feature is very useful during RTL simulation so that
--! current FW supports skipping of the copying FwImage state.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity sram8_inferred_init is
generic (
abits : integer := 12;
byte_idx : integer := 0;
init_file : string
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end;
architecture arch_sram8_inferred_init of sram8_inferred_init is
constant SRAM_LENGTH : integer := 2**abits;
-- romimage only 256 KB, but SRAM is 512 KB so we initialize one
-- half of sram = 32768 * 8 = 256 KB
constant FILE_IMAGE_LINES_TOTAL : integer := 32768;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(7 downto 0);
impure function init_ram(file_name : in string) return ram_type is
file ram_file : text open read_mode is file_name;
variable ram_line : line;
variable temp_bv : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable temp_mem : ram_type;
begin
for i in 0 to (FILE_IMAGE_LINES_TOTAL-1) loop
readline(ram_file, ram_line);
hread(ram_line, temp_bv);
temp_mem(i) := temp_bv((byte_idx+1)*8-1 downto 8*byte_idx);
end loop;
return temp_mem;
end function;
--! @warning SIMULATION INITIALIZATION
signal ram : ram_type := init_ram(init_file);
signal adr : std_logic_vector(abits-1 downto 0);
begin
reg : process (clk, address, wdata) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
adr <= address;
end if;
end process;
rdata <= ram(conv_integer(adr));
end;
|
use work.mwe_pkg.all;
entity ent is
end;
architecture behav of ent is
function f1 (a, b : boolean) return integer is
begin
return 1;
end f1;
procedure p2 (v : bit_vector (3 downto 0)) is
begin
null;
end p2;
subtype byte is bit_vector (7 downto 0);
procedure p3 (a, b : byte) is
begin
null;
end p3;
procedure p4 (t : std.standard.natural range 0 to 4) is
begin
null;
end p4;
shared variable v : mwe_t;
begin
process
begin
v.send_random_data;
report f1'path_name;
assert f1'path_name = ":ent:f1[boolean,boolean return integer]:"
severity failure;
report p2'path_name;
assert p2'path_name = ":ent:p2[bit_vector]:"
severity failure;
report p3'path_name;
assert p3'path_name = ":ent:p3[byte,byte]:"
severity failure;
report p4'path_name;
assert p4'path_name = ":ent:p4[natural]:"
severity failure;
wait;
end process;
end behav;
|
--
-- PhaseMemory.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity PhaseMemory is
port (
clk : in std_logic;
reset : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
memwr : in std_logic;
memout : out std_logic_vector (17 downto 0);
memin : in std_logic_vector (17 downto 0)
);
end PhaseMemory;
architecture RTL of PhaseMemory is
type PHASE_ARRAY_TYPE is array (0 to 18-1) of std_logic_vector (17 downto 0);
signal phase_array : PHASE_ARRAY_TYPE;
signal init_slot : integer range 0 to 18;
signal mem_wr_s : std_logic;
signal mem_addr_s : integer;
signal mem_data_s : std_logic_vector (17 downto 0);
attribute ram_style : string;
attribute ram_style of phase_array : signal is "block";
begin
mem_wr_s <= '1' when init_slot /= 18 else memwr;
mem_addr_s <= init_slot when init_slot /= 18 else conv_integer(slot);
mem_data_s <= (others => '0') when init_slot /= 18 else memin;
process (clk, reset)
begin
if reset = '1' then
init_slot <= 0;
elsif rising_edge(clk) then
if mem_wr_s = '1' then
phase_array(mem_addr_s) <= mem_data_s;
end if;
memout <= phase_array(conv_integer(slot));
if init_slot /= 18 then
init_slot <= init_slot + 1;
end if;
end if;
end process;
end RTL; |
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
a := int_vec4x2'(b(1 to 2), b(3 to 4), b(5 to 6), b(7 to 8));
assert a(1) = (1, 2);
assert a(2) = (3, 4);
assert a(3) = (5, 6);
assert a(4) = (7, 8);
wait;
end process;
end architecture;
|
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
a := int_vec4x2'(b(1 to 2), b(3 to 4), b(5 to 6), b(7 to 8));
assert a(1) = (1, 2);
assert a(2) = (3, 4);
assert a(3) = (5, 6);
assert a(4) = (7, 8);
wait;
end process;
end architecture;
|
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
a := int_vec4x2'(b(1 to 2), b(3 to 4), b(5 to 6), b(7 to 8));
assert a(1) = (1, 2);
assert a(2) = (3, 4);
assert a(3) = (5, 6);
assert a(4) = (7, 8);
wait;
end process;
end architecture;
|
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
a := int_vec4x2'(b(1 to 2), b(3 to 4), b(5 to 6), b(7 to 8));
assert a(1) = (1, 2);
assert a(2) = (3, 4);
assert a(3) = (5, 6);
assert a(4) = (7, 8);
wait;
end process;
end architecture;
|
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
a := int_vec4x2'(b(1 to 2), b(3 to 4), b(5 to 6), b(7 to 8));
assert a(1) = (1, 2);
assert a(2) = (3, 4);
assert a(3) = (5, 6);
assert a(4) = (7, 8);
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity fsm_4s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_4s;
architecture behav of fsm_4s is
type state_t is (S0_1, S1_0, S2_0, S3_1);
signal s : state_t;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= S0_1;
done <= '0';
else
-- Reset by default
s <= S0_1;
done <= '0';
case s is
when S0_1 =>
if d = '1' then
s <= S1_0;
end if;
when S1_0 =>
if d = '0' then
s <= S2_0;
end if;
when S2_0 =>
if d = '0' then
s <= S3_1;
end if;
when S3_1 =>
if d = '1' then
done <= '1';
end if;
end case;
end if;
end if;
end process;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc743.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00743pkg is
type arrtype is array (1 to 5) of bit;
constant defcon1 : bit;
constant defcon2 : integer;
constant defcon3 : arrtype;
constant defcon4 : boolean;
component comp1
generic (
constant dgc1 : bit := defcon1;
constant dgc2 : integer := defcon2;
constant dgc3 : arrtype := defcon3;
constant dgc4 : boolean := defcon4
);
port ( signal dcent1 : inout bit := dgc1;
signal dcent2 : inout integer := dgc2;
signal dcent3 : inout arrtype := dgc3;
signal dcent4 : inout boolean := dgc4
);
end component;
end c01s01b01x01p04n01i00743pkg;
package body c01s01b01x01p04n01i00743pkg is
constant defcon1 : bit := '1';
constant defcon2 : integer := 113;
constant defcon3 : arrtype := ('1','0','1','0','1');
constant defcon4 : boolean := TRUE;
end c01s01b01x01p04n01i00743pkg;
use work.c01s01b01x01p04n01i00743pkg.all;
entity c01s01b01x01p04n01i00743ent_a is
generic (
constant gc1 : bit;
constant gc2 : integer;
constant gc3 : arrtype;
constant gc4 : boolean
);
port ( signal cent1 : inout bit;
signal cent2 : inout integer;
signal cent3 : inout arrtype;
signal cent4 : inout boolean
);
end c01s01b01x01p04n01i00743ent_a;
architecture c01s01b01x01p04n01i00743arch_a of c01s01b01x01p04n01i00743ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1='1') and (gc2=113) and (gc3=('1','0','1','0','1')) and (gc4) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00743"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00743 - Generic default to deferred constants."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00743arch_a;
use work.c01s01b01x01p04n01i00743pkg.all;
ENTITY c01s01b01x01p04n01i00743ent IS
generic ( constant gen_con : integer := 1334 );
port ( signal ee1 : inout boolean := TRUE;
signal ee2 : inout bit;
signal ee3 : inout integer;
signal ee4 : inout arrtype
);
END c01s01b01x01p04n01i00743ent;
ARCHITECTURE c01s01b01x01p04n01i00743arch OF c01s01b01x01p04n01i00743ent IS
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00743ent_a(c01s01b01x01p04n01i00743arch_a)
generic map ( dgc1, dgc2, dgc3, dgc4 )
port map ( dcent1, dcent2, dcent3, dcent4 );
BEGIN
u1 : comp1;
END c01s01b01x01p04n01i00743arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc743.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00743pkg is
type arrtype is array (1 to 5) of bit;
constant defcon1 : bit;
constant defcon2 : integer;
constant defcon3 : arrtype;
constant defcon4 : boolean;
component comp1
generic (
constant dgc1 : bit := defcon1;
constant dgc2 : integer := defcon2;
constant dgc3 : arrtype := defcon3;
constant dgc4 : boolean := defcon4
);
port ( signal dcent1 : inout bit := dgc1;
signal dcent2 : inout integer := dgc2;
signal dcent3 : inout arrtype := dgc3;
signal dcent4 : inout boolean := dgc4
);
end component;
end c01s01b01x01p04n01i00743pkg;
package body c01s01b01x01p04n01i00743pkg is
constant defcon1 : bit := '1';
constant defcon2 : integer := 113;
constant defcon3 : arrtype := ('1','0','1','0','1');
constant defcon4 : boolean := TRUE;
end c01s01b01x01p04n01i00743pkg;
use work.c01s01b01x01p04n01i00743pkg.all;
entity c01s01b01x01p04n01i00743ent_a is
generic (
constant gc1 : bit;
constant gc2 : integer;
constant gc3 : arrtype;
constant gc4 : boolean
);
port ( signal cent1 : inout bit;
signal cent2 : inout integer;
signal cent3 : inout arrtype;
signal cent4 : inout boolean
);
end c01s01b01x01p04n01i00743ent_a;
architecture c01s01b01x01p04n01i00743arch_a of c01s01b01x01p04n01i00743ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1='1') and (gc2=113) and (gc3=('1','0','1','0','1')) and (gc4) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00743"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00743 - Generic default to deferred constants."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00743arch_a;
use work.c01s01b01x01p04n01i00743pkg.all;
ENTITY c01s01b01x01p04n01i00743ent IS
generic ( constant gen_con : integer := 1334 );
port ( signal ee1 : inout boolean := TRUE;
signal ee2 : inout bit;
signal ee3 : inout integer;
signal ee4 : inout arrtype
);
END c01s01b01x01p04n01i00743ent;
ARCHITECTURE c01s01b01x01p04n01i00743arch OF c01s01b01x01p04n01i00743ent IS
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00743ent_a(c01s01b01x01p04n01i00743arch_a)
generic map ( dgc1, dgc2, dgc3, dgc4 )
port map ( dcent1, dcent2, dcent3, dcent4 );
BEGIN
u1 : comp1;
END c01s01b01x01p04n01i00743arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc743.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00743pkg is
type arrtype is array (1 to 5) of bit;
constant defcon1 : bit;
constant defcon2 : integer;
constant defcon3 : arrtype;
constant defcon4 : boolean;
component comp1
generic (
constant dgc1 : bit := defcon1;
constant dgc2 : integer := defcon2;
constant dgc3 : arrtype := defcon3;
constant dgc4 : boolean := defcon4
);
port ( signal dcent1 : inout bit := dgc1;
signal dcent2 : inout integer := dgc2;
signal dcent3 : inout arrtype := dgc3;
signal dcent4 : inout boolean := dgc4
);
end component;
end c01s01b01x01p04n01i00743pkg;
package body c01s01b01x01p04n01i00743pkg is
constant defcon1 : bit := '1';
constant defcon2 : integer := 113;
constant defcon3 : arrtype := ('1','0','1','0','1');
constant defcon4 : boolean := TRUE;
end c01s01b01x01p04n01i00743pkg;
use work.c01s01b01x01p04n01i00743pkg.all;
entity c01s01b01x01p04n01i00743ent_a is
generic (
constant gc1 : bit;
constant gc2 : integer;
constant gc3 : arrtype;
constant gc4 : boolean
);
port ( signal cent1 : inout bit;
signal cent2 : inout integer;
signal cent3 : inout arrtype;
signal cent4 : inout boolean
);
end c01s01b01x01p04n01i00743ent_a;
architecture c01s01b01x01p04n01i00743arch_a of c01s01b01x01p04n01i00743ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1='1') and (gc2=113) and (gc3=('1','0','1','0','1')) and (gc4) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00743"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00743 - Generic default to deferred constants."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00743arch_a;
use work.c01s01b01x01p04n01i00743pkg.all;
ENTITY c01s01b01x01p04n01i00743ent IS
generic ( constant gen_con : integer := 1334 );
port ( signal ee1 : inout boolean := TRUE;
signal ee2 : inout bit;
signal ee3 : inout integer;
signal ee4 : inout arrtype
);
END c01s01b01x01p04n01i00743ent;
ARCHITECTURE c01s01b01x01p04n01i00743arch OF c01s01b01x01p04n01i00743ent IS
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00743ent_a(c01s01b01x01p04n01i00743arch_a)
generic map ( dgc1, dgc2, dgc3, dgc4 )
port map ( dcent1, dcent2, dcent3, dcent4 );
BEGIN
u1 : comp1;
END c01s01b01x01p04n01i00743arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc865.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00865pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal dumy : bit_vector(0 to 3);
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00865pkg;
use work.c01s03b01x00p12n01i00865pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00865pkg.all;
ENTITY c01s03b01x00p12n01i00865ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
END c01s03b01x00p12n01i00865ent;
ARCHITECTURE c01s03b01x00p12n01i00865arch OF c01s03b01x00p12n01i00865ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00865"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00865 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00865arch;
configuration c01s03b01x00p12n01i00865cfg of c01s03b01x00p12n01i00865ent is
for c01s03b01x00p12n01i00865arch
for K
for T5:test use configuration work.testbench;
end for;
for G(zero to one)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(three downto two)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc865.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00865pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal dumy : bit_vector(0 to 3);
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00865pkg;
use work.c01s03b01x00p12n01i00865pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00865pkg.all;
ENTITY c01s03b01x00p12n01i00865ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
END c01s03b01x00p12n01i00865ent;
ARCHITECTURE c01s03b01x00p12n01i00865arch OF c01s03b01x00p12n01i00865ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00865"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00865 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00865arch;
configuration c01s03b01x00p12n01i00865cfg of c01s03b01x00p12n01i00865ent is
for c01s03b01x00p12n01i00865arch
for K
for T5:test use configuration work.testbench;
end for;
for G(zero to one)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(three downto two)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc865.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00865pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal dumy : bit_vector(0 to 3);
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00865pkg;
use work.c01s03b01x00p12n01i00865pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00865pkg.all;
ENTITY c01s03b01x00p12n01i00865ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
END c01s03b01x00p12n01i00865ent;
ARCHITECTURE c01s03b01x00p12n01i00865arch OF c01s03b01x00p12n01i00865ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00865"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00865 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00865arch;
configuration c01s03b01x00p12n01i00865cfg of c01s03b01x00p12n01i00865ent is
for c01s03b01x00p12n01i00865arch
for K
for T5:test use configuration work.testbench;
end for;
for G(zero to one)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(three downto two)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MAC_destination is
port( data_in : in std_logic_vector(7 downto 0);
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
destination_MAC : out std_logic_vector(47 downto 0)
);
end MAC_destination;
architecture Behavioral of MAC_destination is
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif enable = '1' then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
destination_MAC <= (others=>'0');
elsif address_counter = 1 then
destination_MAC(47 downto 40) <= data_in;
elsif address_counter = 2 then
destination_MAC(39 downto 32) <= data_in;
elsif address_counter = 3 then
destination_MAC(31 downto 24) <= data_in;
elsif address_counter = 4 then
destination_MAC(23 downto 16) <= data_in;
elsif address_counter = 5 then
destination_MAC(15 downto 8) <= data_in;
elsif address_counter = 6 then
destination_MAC(7 downto 0) <= data_in;
end if;
end if;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: basic_sfifo_fg.vhd
--
-- Description:
-- This HDL file implements a basic synchronous (single clock) fifo using the
-- FIFO Generator tool. It is intended to offer a simple interface to the user
-- with the complexity of the FIFO Generator interface hidden from the user.
--
-- Note that in normal op mode (not First Word Fall Through FWFT) the data count
-- output goes to zero when the FIFO goes full. This the way FIFO Generator works.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- basic_sfifo_fg.vhd
-- |
-- |-- fifo_generator_v8_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $3/07/2011$
--
-- History:
-- DET 3/07/2011 Initial Version
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
--use proc_common_v4_0.coregen_comp_defs.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity basic_sfifo_fg is
generic (
C_DWIDTH : Integer := 32 ;
-- FIFO data Width (Read and write data ports are symetric)
C_DEPTH : Integer := 512 ;
-- FIFO Depth (set to power of 2)
C_HAS_DATA_COUNT : integer := 1 ;
-- 0 = Data Count output not needed
-- 1 = Data Count output needed
C_DATA_COUNT_WIDTH : integer := 10 ;
-- Data Count bit width (Max value is log2(C_DEPTH))
C_IMPLEMENTATION_TYPE : integer range 0 to 1 := 0;
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
C_MEMORY_TYPE : integer := 1;
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
C_PRELOAD_REGS : integer := 1;
-- 0 = normal
-- 1 = FWFT
C_PRELOAD_LATENCY : integer := 0;
-- 0 = FWFT
-- 1 = normal
C_USE_FWFT_DATA_COUNT : integer := 0;
-- 0 = normal
-- 1 for FWFT
C_SYNCHRONIZER_STAGE : integer := 2; -- valid values are 0 to 8;
C_FAMILY : string := "virtex6"
);
port (
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DWIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DWIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic
);
end entity basic_sfifo_fg;
architecture implementation of basic_sfifo_fg is
-- Constant Declarations ----------------------------------------------
Constant POINTER_WIDTH : integer := log2(C_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_FULL : std_logic;
signal WR_ACK : std_logic;
signal OVERFLOW : std_logic;
signal VALID : std_logic;
signal UNDERFLOW : std_logic;
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a basic Sync FIFO
--
-------------------------------------------------------------------------------
I_BASIC_SFIFO : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DWIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0, -- n0
C_FAMILY => C_FAMILY,
C_HAS_ALMOST_EMPTY => 0, -- n0
C_HAS_ALMOST_FULL => 0, -- n0
C_HAS_BACKUP => 0, -- n0
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_MEMINIT_FILE => 0, -- n0
C_HAS_OVERFLOW => 0, -- n0
C_HAS_RD_DATA_COUNT => 0, -- n0
C_HAS_RD_RST => 0, -- n0
C_HAS_RST => 0, -- n0
C_HAS_SRST => 1, -- yes
C_HAS_UNDERFLOW => 0, -- n0
C_HAS_VALID => 0, -- n0
C_HAS_WR_ACK => 0, -- n0
C_HAS_WR_DATA_COUNT => 0, -- n0
C_HAS_WR_RST => 0, -- n0
C_IMPLEMENTATION_TYPE => 0, -- Common clock BRAM
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 0,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 0,
C_PROG_FULL_THRESH_NEGATE_VAL => 0,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => POINTER_WIDTH,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => POINTER_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => CLK,
rst => '0',
srst => SRST,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => DIN, -- uses this one
wr_en => WR_EN, -- uses this one
rd_en => RD_EN, -- uses this one
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => DOUT, -- uses this one
full => FULL, -- uses this one
almost_full => ALMOST_FULL,
wr_ack => WR_ACK,
overflow => OVERFLOW,
empty => EMPTY, -- uses this one
almost_empty => ALMOST_EMPTY,
valid => VALID,
underflow => UNDERFLOW,
data_count => DATA_COUNT, -- uses this one
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end implementation;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_processor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--TODO - make PC and address signals use std_logic_vector
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED;
--(dont)--use work.befunge_pkg.all;--not now anyway
entity befunge_processor_v2 is
generic
(
grid_power : integer := 3;
word_size : integer := 8;
instruction_size : integer := 16;
stack_size : integer := 4;
grid_width : integer := 8;
grid_height : integer := 8
);
port
(
--DEBUG
FDE_OUT : OUT std_logic_vector(word_size-1 downto 0);
INSTRUCTION_OUT : OUT std_logic_vector(word_size-1 downto 0);
GRID_ADDRESS_OUT : OUT std_logic_vector((grid_power * 2)-1 downto 0);
--DEBUG
clk,reset : in std_logic;
data_in : in std_logic_vector(word_size-1 downto 0);
data_out : out std_logic_vector(word_size-1 downto 0)
);
end befunge_processor_v2;
architecture processor_v1 of befunge_processor_v2 is
component befunge_pc_v2 is
generic(
grid_power : integer
);
port(
clk : in std_logic;
reset : in std_logic;
pc_address : out std_logic_vector((grid_power * 2)-1 downto 0);
dir : in std_logic_vector (1 downto 0);
skip : in std_logic;
en : in std_logic
);
end component;
component befunge_alu is
generic(
word_size : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
a : in std_logic_vector(word_size-1 downto 0);
b : in std_logic_vector(word_size-1 downto 0);
result : out std_logic_vector(word_size-1 downto 0);
op : in std_logic_vector(2 downto 0);
en : in std_logic;
working : out std_logic
);
end component;
component befunge_stack is
generic(
stack_depth_pow : integer;
word_size : integer
);
port(
clk : in std_logic;
reset : in std_logic;
stack_0_o : out std_logic_vector(word_size-1 downto 0);
stack_1_o : out std_logic_vector(word_size-1 downto 0);
stack_i : in std_logic_vector(word_size-1 downto 0);
pop1 : in std_logic;
pop2 : in std_logic;
push : in std_logic;
swap : in std_logic;
en : in std_logic
);
end component;
constant word_zero : std_logic_vector(word_size -1 downto 0) := (others => '0');
--((grid_height*grid_width)-1 downto 0)
type grid_declaration is array(0 to (2**(grid_power*2))-1) of std_logic_vector(word_size-1 downto 0);
signal grid : grid_declaration :=
(
std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('1'),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),
std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('1'),word_size)),std_logic_vector(to_unsigned(character'pos('+'),word_size)),std_logic_vector(to_unsigned(character'pos(':'),word_size)),std_logic_vector(to_unsigned(character'pos('2'),word_size)),std_logic_vector(to_unsigned(character'pos('-'),word_size)),
std_logic_vector(to_unsigned(character'pos('_'),word_size)),std_logic_vector(to_unsigned(character'pos('^'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),
std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('>'),word_size)),
std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('h'),word_size)),std_logic_vector(to_unsigned(character'pos('e'),word_size)),std_logic_vector(to_unsigned(character'pos('l'),word_size)),std_logic_vector(to_unsigned(character'pos('l'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),
std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('o'),word_size)),std_logic_vector(to_unsigned(character'pos('w'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('o'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('<'),word_size)),
std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('r'),word_size)),std_logic_vector(to_unsigned(character'pos('l'),word_size)),std_logic_vector(to_unsigned(character'pos('d'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),
std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('<'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size))
);
--(others =>(std_logic_vector(to_unsigned(character'pos('<'),word_size)))); --GO EAST!!!
--grid looks like
-- +----grid_width--------
-- |
-- |
--grid_height
-- |
-- |
--(x,y) is therefore x+(y*grid_width), which makes hardware a little more complex :(
type fde_cycle_states is (idle,fetch,decode,execute,step,nop, alu, alu2, get, get2, put, put2);
signal fde_cycle,fde_previous : fde_cycle_states := idle;
signal grid_data_in,grid_data_out : std_logic_vector(word_size-1 downto 0);
signal grid_address : std_logic_vector((grid_power * 2)-1 downto 0);
signal grid_load : std_logic;
signal grid_store : std_logic;
signal grid_access : std_logic;
signal grid_access_address : std_logic_vector((grid_power * 2)-1 downto 0);
signal dir : std_logic_vector(1 downto 0);
signal pc_address : std_logic_vector((grid_power * 2)-1 downto 0);
signal pc_skip : std_logic;
signal pc_enable : std_logic;
signal stack_0 : std_logic_vector(word_size-1 downto 0);
signal stack_1 : std_logic_vector(word_size-1 downto 0);
signal stack_i : std_logic_vector(word_size-1 downto 0);
signal stack_pop1 : std_logic;
signal stack_pop2 : std_logic;
signal stack_push : std_logic;
signal stack_swap : std_logic;
signal stack_en : std_logic;
signal alu_a : std_logic_vector(word_size-1 downto 0);
signal alu_b : std_logic_vector(word_size-1 downto 0);
signal alu_result : std_logic_vector(word_size-1 downto 0);
signal alu_op : std_logic_vector(2 downto 0);
signal alu_en : std_logic;
signal alu_working : std_logic;
signal string_mode : std_logic;
begin
--DEBUG
GRID_ADDRESS_OUT <= grid_address;
data_out <= grid_data_out;
-- grid_data_in <= data_in;
--DEBUG
alu_inst : befunge_alu
generic map
(
word_size
)
port map
(
clk,
reset,
alu_a,
alu_b,
alu_result,
alu_op,
alu_en,
alu_working
);
stack : befunge_stack
generic map
(
8,
word_size
)
port map
(
clk,
reset,
stack_0,
stack_1,
stack_i,
stack_pop1,
stack_pop2,
stack_push,
stack_swap,
stack_en
);
alu_a <= stack_0;
alu_b <= stack_1;
program_counter : befunge_pc_v2
generic map
(
grid_power
)
port map
(
clk,
reset,
pc_address,
dir,
pc_skip,
pc_enable
);
--Can't do that any more :(
--TODO : this shit needs casted
grid_address <= pc_address when grid_access = '0' else grid_access_address;--to_integer(signed(stack_top));
--grid_address_y <= stack_s1;
--The grid must handle a write from a store instruction
--the grid must handle a read from the pc address
--the grid must handle a read from a load instruction
grid_process : process(reset,clk)
variable push_flag : std_logic := '0';
begin
if(reset = '1') then
fde_cycle <= idle;
stack_pop1 <= '0';
stack_pop2 <= '0';
stack_push <= '0';
stack_swap <= '0';
string_mode <= '0';
pc_skip <= '0';
dir <= "00";
--grid_data_out <= grid(0);
else
if rising_edge(clk) then
--set all signals inside this and we're laughing
--fetch execute cycle that we can use to synchronise read/write signals
case fde_cycle is
when nop =>
FDE_OUT <= X"04";
fde_cycle <= fde_previous;
when idle =>
FDE_OUT <= X"00";
pc_enable <= '0';
pc_skip <= '0';
grid_load <= '0';
push_flag := '0';
stack_push <= '0';
stack_en <= '0';
stack_pop1 <= '0';
stack_pop2 <= '0';
stack_swap <= '0';
alu_en <= '0';
fde_cycle <= fetch;
when fetch =>
FDE_OUT <= X"01";
grid_load <= '1';
fde_cycle <= decode;
when decode =>
FDE_OUT <= X"02";
grid_load <= '0';
fde_cycle <= execute;
when execute =>
fde_cycle <= step; --this must be at the start of the case so it can be overriden
FDE_OUT <= X"03";
grid_load <= '0';
if (string_mode = '0' ) then
--*********************************************Load Literal************************************************************
if ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('0'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(0, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('1'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(1, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('2'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(2, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('3'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(3, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('4'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(4, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('5'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(5, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('6'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(6, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('7'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(7, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('8'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(8, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('9'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(9, word_size));
push_flag := '1';
--*********************************************Alu ops*****************************************************************
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('+'), word_size))) then
alu_op <= "000";
alu_en <= '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('-'), word_size))) then
alu_op <= "001";
alu_en <= '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('*'), word_size))) then
alu_op <= "010";
alu_en <= '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('/'), word_size))) then
alu_op <= "011";
alu_en <= '1';
push_flag := '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('%'), word_size))) then
alu_op <= "100";
alu_en <= '1';
push_flag := '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('!'), word_size))) then
alu_op <= "101";
alu_en <= '1';
push_flag := '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop1 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('''), word_size))) then
alu_op <= "110";
alu_en <= '1';
push_flag := '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop1 <= '1';
--*********************************************Control flow************************************************************
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('<'), word_size))) then --move left!!
INSTRUCTION_OUT <= X"00";
dir <= "10";
--fde_cycle <= nop;
--fde_previous <= idle;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('>'), word_size))) then --move right!!
INSTRUCTION_OUT <= X"01";
dir <= "00";
--fde_cycle <= nop;
--fde_previous <= idle;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('^'), word_size))) then --move up!!
INSTRUCTION_OUT <= X"02";
dir <= "01";
--fde_cycle <= nop;
--fde_previous <= idle;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('v'), word_size))) then --move down!!
INSTRUCTION_OUT <= X"03";
dir <= "11";
--fde_cycle <= nop;
--fde_previous <= idle;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('|'), word_size))) then --verticle switch!!
fde_cycle <= step;
stack_en <= '1';
stack_pop1 <= '1';
if ( stack_0 = word_zero ) then
dir <= "11";
else
dir <= "01";
end if;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('_'), word_size))) then --horizontal switch!!
fde_cycle <= step;
stack_en <= '1';
stack_pop1 <= '1';
if ( stack_0 = word_zero ) then
dir <= "00";
else
dir <= "10";
end if;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('?'), word_size))) then --move in random direction
fde_cycle <= step;
dir <= "10"; --High quality random number obtained using http://www.random.org/integers/
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos(':'), word_size))) then --duplicate stack
fde_cycle <= step;
stack_i <= stack_0;
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('\'), word_size))) then --swap stack
fde_cycle <= step;
stack_en <= '1';
stack_swap <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('$'), word_size))) then --discard stack
fde_cycle <= step;
stack_en <= '1';
stack_pop1 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('$'), word_size))) then --trampoline
fde_cycle <= step;
pc_skip <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('"'), word_size))) then --String mode
fde_cycle <= step;
string_mode <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('p'), word_size))) then --put
fde_cycle <= put;
grid_access_address((grid_power * 2)-1 downto ((grid_power*2)/2)) <= stack_0(grid_power-1 downto 0);
grid_access_address(((grid_power * 2)/2)-1 downto 0) <= stack_1(grid_power-1 downto 0);
grid_access <= '1';
stack_pop2 <= '1';
stack_en <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('g'), word_size))) then --get
fde_cycle <= get;
grid_access <= '1';
stack_pop2 <= '1';
stack_en <= '1';
grid_access_address((grid_power * 2)-1 downto ((grid_power*2)/2)) <= stack_0(grid_power-1 downto 0);
grid_access_address(((grid_power * 2)/2)-1 downto 0) <= stack_1(grid_power-1 downto 0);
else
INSTRUCTION_OUT <= X"04";
--fde_cycle <= nop;
--fde_previous <= idle;
end if;
else -- string mode
fde_cycle <= step;
if ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('"'), word_size))) then -- end string mode
string_mode <= '0';
else
push_flag := '1';
stack_i <= grid_data_out;
end if;
end if;
when alu =>
FDE_OUT <= X"04";
alu_en <= '0';
stack_en <= '0';
stack_pop1 <= '0';
stack_pop2 <= '0';
fde_cycle <= alu2;
when alu2 =>
FDE_OUT <= X"05";
if ( alu_working = '0' ) then
fde_cycle <= step;
stack_i <= alu_result;
push_flag := '1';
else
fde_cycle <= alu;
end if;
when get =>
fde_cycle <= get2;
stack_en <= '0';
stack_pop2 <= '0';
grid_load <= '1';
when get2 =>
fde_cycle <= step;
stack_i <= grid_data_out;
grid_load <= '0';
push_flag := '1';
when put =>
fde_cycle <= put2;
stack_en <= '1';
stack_pop1 <= '1';
grid_data_in <= stack_0;
when put2 =>
fde_cycle <= step;
stack_en <= '0';
stack_pop1 <= '0';
grid_store <= '1';
when step =>
if ( push_flag = '1' ) then
stack_en <= '1';
stack_push <= '1';
push_flag := '0';
else
stack_en <= '0';
end if;
stack_pop1 <= '0';
stack_pop2 <= '0';
stack_swap <= '0';
FDE_OUT <= X"06";
grid_load <= '0';
grid_store <= '0';
pc_enable <= '1';
fde_cycle <= idle;
grid_access <= '0';
end case;
--only write the grid when the grid_store flag is enabled
if (grid_store = '1') then
INSTRUCTION_OUT <= X"AD";
grid(to_integer(unsigned(grid_address))) <= grid_data_in;
end if;
if (grid_load = '1') then
INSTRUCTION_OUT <= X"FF";
grid_data_out <= grid(to_integer(unsigned(grid_address)));
--else
-- grid_data_out <= grid(pc_address);
end if;
end if;
end if;
end process;
end processor_v1;
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Sg==
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vector_dff_block is
Generic (
WIDTH : positive := 8
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
end vector_dff_block;
architecture Behavioral of vector_dff_block is
begin
process (RST, CLK)
begin
if RST = '1' then
Q <= (others => '0');
elsif (CLK'event AND CLK = '1') then
Q <= D;
end if;
end process;
end Behavioral; |
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