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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:48:29 11/18/2013
-- Design Name:
-- Module Name: My_16bitOr_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity My_16bitOr_948282 is
Port ( A_el_8282 : in STD_LOGIC_VECTOR (15 downto 0);
B_el_8282 : in STD_LOGIC_VECTOR (15 downto 0);
R_el_8282 : out STD_LOGIC_VECTOR (15 downto 0));
end My_16bitOr_948282;
architecture Behavioral of My_16bitOr_948282 is
component My_4bitOr_948282 is
Port ( A_el : in STD_LOGIC_VECTOR (3 downto 0);
B_el : in STD_LOGIC_VECTOR (3 downto 0);
R_el : out STD_LOGIC_VECTOR (3 downto 0));
end component;
begin
u0: My_4bitOr_948282 port map (A_el=>A_el_8282(3 downto 0), B_el=>B_el_8282(3 downto 0), R_el=>R_el_8282(3 downto 0));
u1: My_4bitOr_948282 port map (A_el=>A_el_8282(7 downto 4), B_el=>B_el_8282(7 downto 4), R_el=>R_el_8282(7 downto 4));
u2: My_4bitOr_948282 port map (A_el=>A_el_8282(11 downto 8), B_el=>B_el_8282(11 downto 8), R_el=>R_el_8282(11 downto 8));
u3: My_4bitOr_948282 port map (A_el=>A_el_8282(15 downto 12), B_el=>B_el_8282(15 downto 12), R_el=>R_el_8282(15 downto 12));
end Behavioral;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY tb_FramerTop IS
--port (
--);
END;
ARCHITECTURE structure of tb_FramerTop IS
Signal bits: integer:= 32;
Signal clk : STD_LOGIC;
Signal resetb : STD_LOGIC;
Signal sin : STD_LOGIC;
Signal sout : STD_ULOGIC;
Signal clk_div_8 : std_ulogic;
Signal decode_F628_out : std_ulogic;
Signal ram_wren : STD_LOGIC ;
Signal ram_address : STD_LOGIC_VECTOR (4 DOWNTO 0);
Signal ram_data : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal ram_q : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal add_data0x : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal add_data1x : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal add_result : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal divide_denom : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal divide_numer : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal divide_quotient : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal divide_remain : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
COMPONENT tb_Framer_generator
PORT (
clk : OUT STD_LOGIC;
ser_in : OUT STD_LOGIC;
resetb : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT Framer
PORT (
clk : in std_ulogic;
sin : in std_ulogic;
resetb : in std_ulogic;
SOUT : out std_ulogic;
clk_div_8 : out std_ulogic;
decode_F628_out : out std_ulogic
);
END COMPONENT;
Component Average
generic (
bits: integer
);
PORT (clk : in std_logic;
resetb : in std_logic;
data_sig_in : in std_ulogic;
clk_div_8 : in std_ulogic;
decode_F628_out : in std_ulogic;
ram_wren : out STD_LOGIC ;
ram_address : out STD_LOGIC_VECTOR (4 DOWNTO 0);
ram_data : out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
ram_q : in STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_value0x : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_value1x : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_sum : In STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
div_denom : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
div_numer : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
end Component;
Component Ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
END Component;
Component Add IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
END Component;
Component Divider IS
PORT
(
denom : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
END Component;
------------------PORT MAP
BEGIN
Gen: tb_Framer_generator
PORT Map (
clk => clk,
ser_in => sin,
resetb => resetb
);
UUT: Framer
PORT Map (
clk => clk,
sin => sin,
resetb => resetb,
sout => sout,
clk_div_8 => clk_div_8,
decode_F628_out => decode_F628_out
);
Avg: Average
generic map (
bits => bits
)
Port Map(
clk => clk,
resetb => resetb,
data_sig_in => sout,
clk_div_8 => clk_div_8,
decode_F628_out => decode_F628_out,
ram_wren => ram_wren,
ram_address => ram_address,
ram_data => ram_data,
ram_q => ram_q,
add_value0x => add_data0x,
add_value1x => add_data1x,
add_sum => add_result,
div_denom => divide_denom,
div_numer => divide_numer
);
RAM1: RAM
PORT map
(
address => ram_address,
clock => clk,
data => ram_data,
wren => ram_wren,
q => ram_q
);
Add1: Add
PORT map
(
data0x => add_data0x,
data1x => add_data1x,
result => add_result
);
Div1: Divider
PORT map
(
denom =>divide_denom,
numer => divide_numer,
quotient => divide_quotient,
remain => divide_remain
);
END ; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY rs IS
PORT
(
r : IN std_logic;
s : IN std_logic;
q : OUT std_logic;
qi : OUT std_logic
);
END rs;
ARCHITECTURE behavior OF rs IS
SIGNAL a, b : std_logic;
BEGIN
q <= a;
qi <= b;
a <= s nand b;
b <= r nand a;
END behavior;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- Configuration file for a Xilinx ML505 board.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
--
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505"; -- ML505 - Xilinx Virtex 5 reference design board: XC5VLX50T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
--
constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures
end package;
|
entity impure_ex2 is
port (
clk : in bit;
arg : in bit;
res : out bit
);
end impure_ex2;
architecture rtl of impure_ex2 is
-- An impure function called from a combinatorial process with "all"
-- sensitivity triggers an exception.
impure function foo return bit is
begin
return arg;
end function foo;
signal ns : bit;
begin
--comb_process : process(res) -- this works
comb_process : process(all)
begin
ns <= res XOR foo;
end process;
end rtl;
|
--===========================================================================--
-- --
-- Synthesizable 8 bit Timer --
-- --
--===========================================================================--
--
-- File name : timer.vhd
--
-- Entity name : timer
--
-- Purpose : 8 bit timer module for System09
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Uses : None
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Registers :
--
-- IO address + 0 Read - Down Count register
-- Bits[7..0] = Counter Value
--
-- IO address + 0 Write - Preset Count register
-- Bits[7..0] = Preset Value
--
-- IO address + 1 Read - Status register
-- Bit[7] = Interrupt Flag
-- Bits[6..0] = undefined
--
-- IO address + 1 Write - Control register
-- Bit[7] = Interrupt Enable
-- Bits[6..1] = Unedfined
-- Bit[0] = Counter enable
--
-- Operation :
--
-- Write count to counter register
-- Enable counter by setting bit 0 of the control register
-- Enable interrupts by setting bit 7 of the control register
-- Counter will count down to zero
-- When it reaches zero the terminal flag is set
-- If the interrupt is enabled an interrupt is generated
-- The interrupt may be disabled by writing a 0 to bit 7
-- of the control register or by loading a new down count
-- into the counter register.
--
-- Copyright (C) 2002 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 0.1 2002-09-06 John Kent Converted to a single timer
-- Made synchronous with system clock
-- 1.0 2003-09-06 John Kent Changed Clock Edge
-- Released to opencores.org
-- 2.0 2008-02-05 John Kent Removed Timer inputs and outputs
-- Made into a simple 8 bit interrupt down counter
-- 2.1 2010-06-17 John Kent Updated header and added GPL
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity timer is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic;
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end;
architecture rtl of timer is
signal timer_ctrl : std_logic_vector(7 downto 0);
signal timer_stat : std_logic_vector(7 downto 0);
signal timer_count : std_logic_vector(7 downto 0);
signal timer_term : std_logic; -- Timer terminal count
--
-- control/status register bits
--
constant BIT_ENB : integer := 0; -- 0=disable, 1=enabled
constant BIT_IRQ : integer := 7; -- 0=disabled, 1-enabled
begin
--------------------------------
--
-- write control registers
--
--------------------------------
timer_control : process( clk, rst, cs, rw, addr, data_in,
timer_ctrl, timer_term, timer_count )
begin
if clk'event and clk = '0' then
if rst = '1' then
timer_count <= (others=>'0');
timer_ctrl <= (others=>'0');
timer_term <= '0';
elsif cs = '1' and rw = '0' then
if addr='0' then
timer_count <= data_in;
timer_term <= '0';
else
timer_ctrl <= data_in;
end if;
else
if (timer_ctrl(BIT_ENB) = '1') then
if (timer_count = "00000000" ) then
timer_term <= '1';
else
timer_count <= timer_count - 1;
end if;
end if;
end if;
end if;
end process;
--
-- timer status register
--
timer_status : process( timer_ctrl, timer_term )
begin
timer_stat(6 downto 0) <= timer_ctrl(6 downto 0);
timer_stat(BIT_IRQ) <= timer_term;
end process;
--
-- timer data output mux
--
timer_data_out : process( addr, timer_count, timer_stat )
begin
if addr = '0' then
data_out <= timer_count;
else
data_out <= timer_stat;
end if;
end process;
--
-- read timer strobe to reset interrupts
--
timer_interrupt : process( timer_term, timer_ctrl )
begin
irq <= timer_term and timer_ctrl(BIT_IRQ);
end process;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity clock_gen is
generic (period : time := 10 ns);
port (clk, reset : out std_logic);
end clock_gen;
architecture clock_gen of clock_gen is
begin -- clock_gen
reset <= '1', '0' after period*2; -- asynchronous reset (active high)
process
begin
clk <= '1', '0' after period/2;
wait for period;
end process;
end clock_gen;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
entity logic_analyzer_32 is
generic (
g_timer_div : positive := 50 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(7 downto 0);
---
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer_32;
architecture gideon of logic_analyzer_32 is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(15 downto 0);
signal ev_data_d : std_logic_vector(15 downto 0);
signal ev_wdata : std_logic_vector(31 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
type t_state is (idle, writing);
signal state : t_state;
signal sub, task : std_logic_vector(3 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= sub & task & ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c /= ev_data_d) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
ev_data_d <= ev_data_c;
stamp <= (others => '0');
state <= writing;
end if;
end if;
end if;
when writing =>
mem_req.data <= byte_swap(ev_wdata);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 4;
mem_req.request <= '0';
state <= idle;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "011" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "000" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= X"0" & sub;
when "101" =>
io_resp.data <= X"0" & task;
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "111" =>
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
when "110" =>
enable_log <= '0';
when "101" =>
task <= io_req.data(3 downto 0);
when "100" =>
sub <= io_req.data(3 downto 0);
when others =>
null;
end case;
end if;
if reset='1' then
state <= idle;
sub <= X"0";
task <= X"0";
enable_log <= '0';
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.byte_en <= "1111";
end gideon;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
-- Concept:
-- The actual commands are implemented by the application software.
-- This allows direct coupling between a file and the read/write commands that
-- the drive performs. The drawback is maybe a timing incompatibility, but it
-- is currently assumed that this is not as strict as on a 1541. So this may
-- not be an issue. The "window" through which data is passed is located in
-- external memory. The location and length are determined by the software
-- and the actual transfer to/from the CPU in the 1571/1581 is done
-- autonomously by this block:
--
-- 'Read' command: (6502 <- data <- application)
-- * 1581 performs the seek (through other commands)
-- * 1581 writes the read command into the WD177x register
-- * This block generates an interrupt to the appication software
-- and sets the busy bit.
-- * Application software interprets the command, and places the
-- data to be read in a memory block and passes the pointer to
-- it to the 'DMA' registers. -> Can the pointer be fixed?!
-- * 1581 will see data appearing in the data register through the
-- data valid bit (S1). Reading the register pops the data, and
-- DMA controller places new data until all bytes have been
-- transferred.
-- * This block clears the busy bit and the command completes.
--
-- 'Write' commands: (6502 -> data -> application)
-- * 1581 writes the write command into the WD177x register
-- * Block sets the busy bit and generates the IRQ to the application
-- * Application software interprets the command, and sets the
-- memory write address in the DMA controller and starts it.
-- * The block keeps 'DRQ' (S1) asserted for as long as it accepts data
-- * When all bytes are transferred, another IRQ is generated.
-- * The application recognizes that a write has completed and
-- processes the data.
-- * Application clears the busy bit, possibly sets the status bits
-- and the command completes.
--
-- 'Force Interrupt' command aborts the current transfer. In case of
-- a read, the DMA controller is reset and the busy bit is cleared.
-- In case of a write, an interrupt is generated (because of the
-- command), and the DMA controller is stopped. The IRQ causes the
-- application software to know that the write has been aborted.
--
-- So, commands that transfer data TO the 1581 CPU are simply handled
-- by one call to the application software, and the logic completes it.
-- Commands that transfer data FROM the 1581 CPU are handled by two
-- calls to the application software; one to request a memory pointer
-- and one to process the data and reset the busy bit / complete the
-- command programmatically.
--
entity wd177x is
generic (
g_tag : std_logic_vector(7 downto 0) := X"03" );
port (
clock : in std_logic;
clock_en : in std_logic; -- only for register access
reset : in std_logic;
tick_1kHz : in std_logic;
tick_4MHz : in std_logic;
-- register interface from 6502
addr : in unsigned(1 downto 0);
wen : in std_logic;
ren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- track stepper interface (for audio samples)
motor_en : in std_logic; -- for index pulse
stepper_en : in std_logic;
step : out std_logic_vector(1 downto 0);
cur_track : in unsigned(6 downto 0) := (others => '0');
do_track_out : out std_logic;
do_track_in : out std_logic;
-- I/O interface from application CPU
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic );
end entity;
architecture behavioral of wd177x is
signal mem_rwn : std_logic;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_request : std_logic := '0';
signal status_idx : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal track : std_logic_vector(7 downto 0);
signal sector : std_logic_vector(7 downto 0);
signal command : std_logic_vector(7 downto 0) := X"00";
signal disk_data : std_logic_vector(7 downto 0) := X"00";
signal disk_wdata_valid : std_logic;
signal disk_rdata_valid : std_logic;
alias st_motor_on : std_logic is status(7);
alias st_write_prot : std_logic is status(6);
alias st_rectype_spinup : std_logic is status(5);
alias st_rec_not_found : std_logic is status(4);
alias st_crc_error : std_logic is status(3);
alias st_lost_data : std_logic is status(2);
alias st_data_request : std_logic is status(1);
alias st_busy : std_logic is status(0);
signal dma_mode : std_logic_vector(1 downto 0);
signal transfer_addr : unsigned(23 downto 0) := (others => '0');
signal transfer_len : unsigned(13 downto 0) := (others => '0');
type t_dma_state is (idle, do_read, reading, do_write, writing, write_delay);
signal dma_state : t_dma_state;
-- Command queue
signal command_fifo_din : std_logic_vector(8 downto 0);
signal command_fifo_dout : std_logic_vector(8 downto 0);
signal command_fifo_push : std_logic;
signal command_fifo_pop : std_logic;
signal command_fifo_valid : std_logic;
signal completion : std_logic;
signal write_delay_cnt : unsigned(7 downto 0);
-- Stepper
signal goto_track : unsigned(6 downto 0);
signal step_time : unsigned(4 downto 0);
signal step_busy : std_logic;
signal index_out : std_logic;
signal index_enable : std_logic := '0';
signal index_polarity : std_logic := '0';
begin
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
mem_req.address <= "00" & transfer_addr;
mem_req.data <= disk_data;
mem_req.read_writen <= mem_rwn;
mem_req.request <= mem_request;
mem_req.size <= "00"; -- one byte at a time
mem_req.tag <= g_tag;
process(status, index_out, index_enable, index_polarity, command)
begin
status_idx <= status;
if command(7) = '0' and index_enable = '1' then -- Type I command
status_idx(1) <= index_out xor index_polarity;
end if;
end process;
with addr select rdata <=
status_idx when "00",
track when "01",
sector when "10",
disk_data when others;
process(clock)
variable v_addr : unsigned(3 downto 0);
begin
if rising_edge(clock) then
command_fifo_push <= '0';
command_fifo_pop <= '0';
if wen = '1' and clock_en = '1' then
case addr is
when "00" =>
if st_busy = '0' or wdata(7 downto 4) = X"D" then
command <= wdata;
st_busy <= '1';
completion <= '0';
command_fifo_push <= '1';
disk_wdata_valid <= '0';
end if;
when "01" =>
track <= wdata;
when "10" =>
sector <= wdata;
when "11" =>
disk_data <= wdata;
disk_wdata_valid <= '1';
when others =>
null;
end case;
end if;
if ren = '1' and clock_en = '1' then
case addr is
when "11" =>
disk_rdata_valid <= '0';
if disk_rdata_valid = '1' then
st_data_request <= '0';
end if;
when others =>
null; -- no other operations upon a read so far
end case;
end if;
io_resp <= c_io_resp_init;
v_addr := io_req.address(3 downto 0);
if io_req.write = '1' then
io_resp.ack <= '1';
case v_addr is
when X"0" =>
index_enable <= io_req.data(0);
index_polarity <= io_req.data(1);
when X"1" =>
track <= io_req.data;
when X"4" =>
status <= status and not io_req.data;
when X"5" =>
status <= status or io_req.data;
when X"6" =>
command_fifo_pop <= '1';
when X"7" =>
dma_mode <= io_req.data(1 downto 0); -- 00 is off, 01 = read (to 1581), 10 = write (to appl)
when X"8" =>
transfer_addr(7 downto 0) <= unsigned(io_req.data);
when X"9" =>
transfer_addr(15 downto 8) <= unsigned(io_req.data);
when X"A" =>
transfer_addr(23 downto 16) <= unsigned(io_req.data);
when X"C" =>
transfer_len(7 downto 0) <= unsigned(io_req.data);
when X"D" =>
transfer_len(13 downto 8) <= unsigned(io_req.data(5 downto 0));
when X"E" =>
goto_track <= unsigned(io_req.data(goto_track'range));
when X"F" =>
step_time <= unsigned(io_req.data(4 downto 0));
when others =>
null;
end case;
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case v_addr is
when X"0" =>
io_resp.data <= command_fifo_dout(7 downto 0);
when X"1" =>
io_resp.data <= track;
when X"2" =>
io_resp.data <= sector;
when X"3" =>
io_resp.data <= disk_data;
when X"4"|X"5" =>
io_resp.data <= status;
when X"6" =>
io_resp.data(0) <= command_fifo_dout(8);
io_resp.data(7) <= command_fifo_valid;
when X"7" =>
io_resp.data(1 downto 0) <= dma_mode;
-- when X"8" =>
-- io_resp.data <= std_logic_vector(transfer_addr(7 downto 0));
-- when X"9" =>
-- io_resp.data <= std_logic_vector(transfer_addr(15 downto 8));
-- when X"A" =>
-- io_resp.data <= std_logic_vector(transfer_addr(23 downto 16));
when X"C" =>
io_resp.data <= std_logic_vector(transfer_len(7 downto 0));
when X"D" =>
io_resp.data(5 downto 0) <= std_logic_vector(transfer_len(13 downto 8));
when X"E" =>
io_resp.data(0) <= step_busy;
when X"F" =>
io_resp.data(4 downto 0) <= std_logic_vector(step_time);
when others =>
null;
end case;
end if;
case dma_state is
when idle =>
if dma_mode = "01" then
if disk_rdata_valid = '0' then
dma_state <= do_read;
end if;
elsif dma_mode = "10" then
st_data_request <= '1';
if disk_wdata_valid = '1' then
dma_state <= do_write;
st_data_request <= '0';
disk_wdata_valid <= '0';
end if;
else -- no dma
st_data_request <= '0';
disk_wdata_valid <= '0';
end if;
when do_read =>
if transfer_len = 0 then
st_busy <= '0';
dma_mode <= "00";
dma_state <= idle;
else
mem_request <= '1';
mem_rwn <= '1';
dma_state <= reading;
end if;
when reading =>
if mem_rack = '1' then
mem_request <= '0';
end if;
if mem_dack = '1' then
disk_data <= mem_resp.data;
disk_rdata_valid <= '1';
st_data_request <= '1';
transfer_len <= transfer_len - 1;
transfer_addr <= transfer_addr + 1;
dma_state <= idle;
end if;
when do_write =>
mem_request <= '1';
mem_rwn <= '0';
transfer_len <= transfer_len - 1;
dma_state <= writing;
when writing =>
write_delay_cnt <= X"FF"; -- 64 us
if mem_rack = '1' then
mem_request <= '0';
transfer_addr <= transfer_addr + 1;
dma_state <= idle;
if transfer_len = 0 then
dma_mode <= "11"; -- write complete
dma_state <= write_delay;
completion <= '1';
command_fifo_push <= '1';
end if;
end if;
when write_delay =>
if write_delay_cnt = 0 then
st_busy <= '0';
dma_state <= idle;
elsif tick_4MHz = '1' then
write_delay_cnt <= write_delay_cnt - 1;
end if;
when others =>
null;
end case;
if reset = '1' then
mem_request <= '0';
mem_rwn <= '1';
disk_wdata_valid <= '0';
disk_rdata_valid <= '0';
track <= X"01";
sector <= X"00";
command <= X"00";
status <= X"00";
dma_mode <= "00";
step_time <= "01100";
completion <= '0';
goto_track <= to_unsigned(0, goto_track'length);
write_delay_cnt <= X"00";
end if;
end if;
end process;
i_cmd_fifo: entity work.sync_fifo
generic map (
g_depth => 7,
g_data_width => 9,
g_threshold => 4,
g_storage => "MRAM",
g_fall_through => true
)
port map (
clock => clock,
reset => reset,
flush => '0',
rd_en => command_fifo_pop,
wr_en => command_fifo_push,
din => command_fifo_din,
dout => command_fifo_dout,
valid => command_fifo_valid
);
command_fifo_din <= completion & command;
io_irq <= command_fifo_valid;
i_stepper: entity work.stepper
port map (
clock => clock,
reset => reset,
tick_1KHz => tick_1KHz,
goto_track => goto_track,
cur_track => cur_track, -- from drive mechanics
step_time => step_time,
do_track_in => do_track_in,
do_track_out => do_track_out,
enable => stepper_en,
busy => step_busy,
step => step,
motor_en => motor_en,
index_out => index_out
);
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:02:32 10/20/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_SynthBench_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_SynthBench
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_SynthBench_TB IS
END TestCPU1_SynthBench_TB;
ARCHITECTURE behavior OF TestCPU1_SynthBench_TB IS
-- Component Declaration for the Unit Under Test (UUT)
component TestCPU1_SynthBench is
Port ( board_clk : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR(3 downto 0);
out_pins : out STD_LOGIC_VECTOR(31 downto 0);
LCD_DB : out STD_LOGIC_VECTOR(7 downto 0);
r2 : out STD_LOGIC_VECTOR(15 downto 0);
r5 : out STD_LOGIC_VECTOR(15 downto 0);
CPU_clk : out STD_LOGIC);
end component;
--Inputs
signal board_clk : std_logic := '0';
--Outputs
signal out_pins : std_logic_vector(31 downto 0);
signal LCD_DB : STD_LOGIC_VECTOR(7 downto 0);
signal r2 : STD_LOGIC_VECTOR(15 downto 0);
signal r5 : STD_LOGIC_VECTOR(15 downto 0);
signal CPU_clk : STD_LOGIC;
-- Clock period definitions
constant board_clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_SynthBench PORT MAP (
board_clk => board_clk,
out_pins => out_pins,
LCD_DB => LCD_DB,
r2 => r2,
r5 => r5,
CPU_clk => CPU_clk
);
-- Clock process definitions
board_clk_process :process
begin
board_clk <= '0';
wait for board_clk_period/2;
board_clk <= '1';
wait for board_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 19:57:07 12/03/2013
-- Design Name:
-- Module Name: VGA_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA_top is
port(
KEY16_INPUT: in std_logic_vector(15 downto 0);
CLK_0: in std_logic; -- must 50M
clk_out: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0'
);
end VGA_top;
architecture Behavioral of VGA_top is
component VGA_play
Port(
-- common port
CLK_0: in std_logic; -- must 50M
clkout: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0';
-- fifo memory
wctrl: in std_logic_vector(0 downto 0); -- 1 is write
waddr: in std_logic_vector(10 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end component;
-- display memory control
signal dwctrl: std_logic_vector(0 downto 0);
signal dwaddr : std_logic_vector(10 downto 0);
signal dwdata : std_logic_vector(7 downto 0);
signal dclk : std_logic;
type data is (
d1,
d2,
d3,
d4
);
type step is (
s1,
s2,
s3,
s4
);
signal datain : data := d1;
signal datast : step := s1;
begin
clk_out <= dclk;
vga : VGA_play port map(
CLK_0 => CLK_0,
clkout=> dclk,
reset=> reset,
-- vga port
R=> R,
G=> G,
B=> B,
Hs=> Hs,
Vs=> Vs,
-- fifo memory
wctrl=> dwctrl,
waddr=> dwaddr,
wdata => dwdata
);
process(dclk)
begin
if dclk'event and dclk = '1' then
dwctrl(0) <= '1';
case datain is
when d1 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "0000";
dwdata <= "0001" & input(15 downto 12);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "0001";
dwdata <= "0001" & input(11 downto 8);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "0010";
dwdata <= "0000000" & KEY16_INPUT(2);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "0011";
dwdata <= "0000000" & KEY16_INPUT(3);
datast <= s1;
datain <= d2;
end case;
when d2 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "0100";
dwdata <= "0000000" & KEY16_INPUT(4);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "0101";
dwdata <= "0000000" & KEY16_INPUT(5);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "0110";
dwdata <= "0000000" & KEY16_INPUT(6);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "0111";
dwdata <= "0000000" & KEY16_INPUT(7);
datast <= s1;
datain <= d3;
end case;
when d3 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "1000";
dwdata <= "0000000" & KEY16_INPUT(8);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "1001";
dwdata <= "0000000" & KEY16_INPUT(9);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "1010";
dwdata <= "0000000" & KEY16_INPUT(10);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "1011";
dwdata <= "0000000" & KEY16_INPUT(11);
datast <= s1;
datain <= d4;
end case;
when d4 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "1100";
dwdata <= "0000000" & KEY16_INPUT(12);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "1101";
dwdata <= "0000000" & KEY16_INPUT(13);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "1110";
dwdata <= "0000000" & KEY16_INPUT(14);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "1111";
dwdata <= "0000000" & KEY16_INPUT(15);
datast <= s1;
datain <= d1;
end case;
end case;
end if;
end process;
end Behavioral;
|
-- $Id: pdp11_ledmux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ledmux - syn
-- Description: pdp11: hio led mux
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-27 652 1.0 Initial version
-- 2015-02-20 649 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_ledmux is -- hio led mux
generic (
LWIDTH : positive := 8); -- led width
port (
SEL : in slbit; -- select (0=stat;1=dr)
STATLEDS : in slv8; -- 8 bit CPU status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
LED : out slv(LWIDTH-1 downto 0) -- hio leds
);
end pdp11_ledmux;
architecture syn of pdp11_ledmux is
begin
assert LWIDTH=8 or LWIDTH=16
report "assert(LWIDTH=8 or LWIDTH=16): unsupported LWIDTH"
severity failure;
proc_mux: process (SEL, STATLEDS, DM_STAT_EXP)
variable iled : slv(LWIDTH-1 downto 0) := (others=>'0');
begin
iled := (others=>'0');
if SEL = '0' then
iled(STATLEDS'range) := STATLEDS;
else
if LWIDTH=8 then
iled := DM_STAT_EXP.dp_dsrc(11 downto 4); --take middle part
else
iled := DM_STAT_EXP.dp_dsrc(iled'range);
end if;
end if;
LED <= iled;
end process proc_mux;
end syn;
|
-- NEED RESULT: ARCH00691: Allocators with generic composite qualified expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00691
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (3)
-- 7.3.6 (8)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00691)
-- ENT00691_Test_Bench(ARCH00691_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00691 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
begin
va_bit_vector_1 := new st_bit_vector ' (c_st_bit_vector_1) ;
va_string_1 := new st_string ' (c_st_string_1) ;
va_t_rec1_1 := new st_rec1 ' (c_st_rec1_1) ;
va_st_rec1_1 := new st_rec1 ' (c_st_rec1_1) ;
va_t_rec2_1 := new st_rec2 ' (c_st_rec2_1) ;
va_st_rec2_1 := new st_rec2 ' (c_st_rec2_1) ;
va_t_rec3_1 := new st_rec3 ' (c_st_rec3_1) ;
va_st_rec3_1 := new st_rec3 ' (c_st_rec3_1) ;
va_t_arr1_1 := new st_arr1 ' (c_st_arr1_1) ;
va_st_arr1_1 := new st_arr1 ' (c_st_arr1_1) ;
va_t_arr2_1 := new st_arr2 ' (c_st_arr2_1) ;
va_st_arr2_1 := new st_arr2 ' (c_st_arr2_1) ;
va_t_arr3_1 := new st_arr3 ' (c_st_arr3_1) ;
va_st_arr3_1 := new st_arr3 ' (c_st_arr3_1) ;
correct := correct and
va_bit_vector_1.all = c_st_bit_vector_1 ;
correct := correct and
va_string_1.all = c_st_string_1 ;
correct := correct and
va_t_rec1_1.all = c_st_rec1_1 ;
correct := correct and
va_st_rec1_1.all = c_st_rec1_1 ;
correct := correct and
va_t_rec2_1.all = c_st_rec2_1 ;
correct := correct and
va_st_rec2_1.all = c_st_rec2_1 ;
correct := correct and
va_t_rec3_1.all = c_st_rec3_1 ;
correct := correct and
va_st_rec3_1.all = c_st_rec3_1 ;
correct := correct and
va_t_arr1_1.all = c_st_arr1_1 ;
correct := correct and
va_st_arr1_1.all = c_st_arr1_1 ;
correct := correct and
va_t_arr2_1.all = c_st_arr2_1 ;
correct := correct and
va_st_arr2_1.all = c_st_arr2_1 ;
correct := correct and
va_t_arr3_1.all = c_st_arr3_1 ;
correct := correct and
va_st_arr3_1.all = c_st_arr3_1 ;
test_report ( "ARCH00691" ,
"Allocators with generic composite qualified expression" ,
correct) ;
wait ;
end process ;
end ARCH00691 ;
--
entity ENT00691_Test_Bench is
end ENT00691_Test_Bench ;
--
architecture ARCH00691_Test_Bench of ENT00691_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00691 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00691_Test_Bench ;
|
package p is
procedure foo(x : in integer; y : out integer);
procedure yah is -- Error
begin
null;
end procedure;
end package;
package body p is
procedure foo(x : in integer; y : out integer) is
variable i : integer;
begin
y := x + 1;
end procedure;
procedure bar(x : in integer; signal y : out integer) is
begin
y <= x + 1;
end procedure;
procedure yam is
begin
return; -- OK
return 5; -- Error
end procedure;
procedure foo_wrap(y : out integer) is
begin
foo(5, y);
end procedure;
procedure has_def(x : in integer; y : in integer := 7) is
begin
end procedure;
procedure calls_has_def is
begin
has_def(5);
end procedure;
procedure bad_def(x : in bit := 6) is
begin
end procedure;
procedure bad_def2(x : in bit := '1'; y : in integer) is
begin
end procedure;
procedure diff_types(x : in integer; y : in string) is
begin
end procedure;
procedure test_named is
begin
diff_types(1, "foo"); -- OK
diff_types(1, y => "bar"); -- OK
diff_types(x => 1, y => "foo"); -- OK
diff_types(y => "la", x => 6); -- OK
diff_types(y => "foo"); -- Error
diff_types(y => "f", 6); -- Error
end procedure;
procedure overload(x : in bit) is
begin
end procedure;
procedure overload(x : in integer) is
begin
end procedure;
procedure test_overload is
begin
overload('1');
overload(1);
end procedure;
procedure test1(x : in integer; y : out integer) is
begin
y := y + 1; -- Error
x := 6;
end procedure;
procedure test2(signal x : in bit) is
begin
-- These are errors according to LRM 93 section 2.1.1.2
assert x'stable;
assert x'quiet;
assert x'transaction = '1';
assert x'delayed(1 ns) = '1';
end procedure;
type int_ptr is access integer;
procedure test3(constant x : inout int_ptr); -- Error
procedure test4(x : in int_ptr); -- Error
procedure test4a(x : int_ptr); -- Error
procedure test4b(x : out int_ptr); -- OK
procedure test5_a(variable x : integer) is
begin
end procedure;
procedure test5_b(variable x : integer) is
alias a : integer is x;
begin
test5_a(a);
end procedure;
type int2d is array (natural range <>, natural range <>) of integer;
procedure test6 (
variable a : inout bit_vector;
constant b : in int2d;
constant c : in natural ) is
begin
end procedure;
procedure test6 (
variable a : inout bit_vector;
constant b : in int2d ) is
begin
test6 ( b => b,
c => 1,
a => a );
end procedure;
procedure test7a(x : in bit_vector(1 to 2)) is
begin
end procedure;
procedure test7b is
begin
test7a(x(1) => '0', x(2) => '1');
end procedure;
procedure test8(x : out int_ptr) is
begin
if x /= null then -- Error
end if;
end procedure;
procedure test9(x : out integer) is
begin
x <= 5; -- Error
end procedure;
type t_access_array is array (0 to 1) of int_ptr;
type t_access_record is record
a : integer;
b : int_ptr;
end record;
procedure test10(constant arg : t_access_array) is -- Error
begin
null;
end procedure;
procedure test11(constant arg : t_access_record) is -- Error
begin
null;
end procedure;
procedure test12(signal arg : t_access_array) is -- Error
begin
null;
end procedure;
procedure test13(signal arg : t_access_record) is -- Error
begin
null;
end procedure;
procedure test14 is
variable x : bit_vector(1 to 3);
begin
x(1); -- Error
end procedure;
procedure test15 (signal x : out bit bus) is -- Error
begin
end procedure;
procedure test16 (signal x : in bit_vector(1 to 3)) is
procedure test16_a (signal y : bit) is
begin
end procedure;
variable i : integer;
begin
test16_a(x(i)); -- Error, not static name
end procedure;
procedure test17 is
procedure test17_a (x, y : integer) is
begin
end procedure;
begin
test17_a(x => 1, x => 2); -- Error
test17_a(z => 1, x => 2); -- Error
end procedure;
procedure test18 (signal x : in bit) is
begin
x <= '1'; -- Error
end procedure;
end package body;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul_61x61
-- File: mul_61x61.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity mul_61x61 is
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of mul_61x61 is
component dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component axcel_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex4_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex6_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component kintex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
begin
gen0 : if multech = 0 generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
dw0 : if multech = 1 generate
mul0 : dw_mul_61x61 port map (A, B, CLK, PRODUCT);
end generate;
tech0 : if multech = 3 generate
axd0 : if fabtech = axdsp generate
mul0 : axcel_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc5v : if fabtech = virtex5 generate
mul0 : virtex4_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc6v : if fabtech = virtex6 generate
mul0 : virtex6_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
gen0 : if not ((fabtech = axdsp) or (fabtech = virtex5) or (fabtech = virtex6)) generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
end generate;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RF is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
we : in STD_LOGIC;
dwr : in STD_LOGIC_VECTOR (31 downto 0);
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0);
crd : out STD_LOGIC_VECTOR (31 downto 0)
);
end RF;
architecture Behavioral of RF is
type ram_type is array (0 to 39) of std_logic_vector (31 downto 0);
signal regs : ram_type := (others => x"00000000");
signal tmp : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
begin
process (reset,rs1,rs2,rd,we,dwr,regs,clk) is
begin
if (reset = '1') then
crs1 <= (others=>'0');
crs2 <= (others=>'0');
crd <= (others=>'0');
regs <= (others => x"00000000");
else
if falling_edge(clk) then
if(we = '1' and rd /= "000000") then
regs(conv_integer(rd)) <= dwr;
end if;
end if;
tmp <= regs(conv_integer(rd));
if rd = rs1 then
crs1 <= tmp;
crs2 <= regs(conv_integer(rs2));
crd <= regs(conv_integer(rd));
elsif rd = rs2 then
crs1 <= regs(conv_integer(rs1));
crs2 <= tmp;
crd <= regs(conv_integer(rd));
else
crs1 <= regs(conv_integer(rs1));
crs2 <= regs(conv_integer(rs2));
crd <= regs(conv_integer(rd));
end if;
end if;
-- elsif falling_edge(clk) then
--
-- if(we = '1' and rd /= "00000") then
-- regs(conv_integer(rd)) <= dwr;
-- end if;
--
-- else--if(rising_edge(clk)) then
-- tmp <= regs(conv_integer(rd));
-- if rd = rs1 then
-- crs1 <= tmp;
-- crs2 <= regs(conv_integer(rs2));
-- elsif rd = rs2 then
-- crs1 <= regs(conv_integer(rs1));
-- crs2 <= tmp;
-- else
-- crs1 <= regs(conv_integer(rs1));
-- crs2 <= regs(conv_integer(rs2));
-- end if;
-- end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
LIBRARY work;
entity ffd_en is
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
D : in std_logic;
Q : out std_logic
);
end entity ffd_en;
architecture Behavioral of ffd_en is
signal q_tmp : std_logic;
begin
process (CLK) is
begin
if rising_edge(CLK) then
if (RST='1') then
q_tmp <= '1';
elsif (EN='1') then
q_tmp <= D;
end if;
end if;
end process;
Q <= q_tmp;
end architecture Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity detectroi_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
in_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end detectroi_process;
architecture rtl of detectroi_process is
constant X_COUNTER_SIZE : integer := 12;
constant Y_COUNTER_SIZE : integer := 12;
--process data_process vars
--bin image reference coordinates
signal xBin_pos : unsigned(X_COUNTER_SIZE-1 downto 0);
signal yBin_pos : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal x_min : unsigned(X_COUNTER_SIZE-1 downto 0);
signal x_max : unsigned(X_COUNTER_SIZE-1 downto 0);
signal y_min : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal y_max : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal enabled : std_logic;
signal frame_buffer : std_logic_vector(63 downto 0);
signal frame_buffer_has_been_filled : std_logic;
signal frame_buffer_has_been_sent : std_logic;
signal frame_buffer_position : unsigned(6 downto 0);
begin
send_roi : process (clk_proc, reset_n)
-- Vars used to fill frame_buffer
variable x_to_send : unsigned(X_COUNTER_SIZE-1 downto 0);
variable y_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0);
variable w_to_send : unsigned(X_COUNTER_SIZE-1 downto 0);
variable h_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0);
begin
if(reset_n='0') then
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE);
--Cleaning frame coordinates
x_max <= (others=>'0');
y_max <= (others=>'0');
x_min <= (others=>'0');
y_min <= (others=>'0');
--Cleaning frame buffer
frame_buffer <= (others=>'0');
--Cleaning signals used to fill buffer
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '0';
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
enabled <= '0';
elsif(rising_edge(clk_proc)) then
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
if(in_fv = '0') then
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE);
--
if frame_buffer_has_been_filled = '0' then
--We send frame coordinates only if there is something to send
if enabled = '1' and frame_buffer_has_been_sent = '0' then
--something was detected
if x_max > 0 then
x_to_send := x_min;
y_to_send := y_min;
w_to_send := x_max-x_min;
h_to_send := y_max-y_min;
else
--nothing found -> empty rectangle at image center
x_to_send := unsigned(in_size_reg_in_w_reg)/2;
y_to_send := unsigned(in_size_reg_in_h_reg)/2;
w_to_send := (others=>'0');
h_to_send := (others=>'0');
end if;
--filling buffer with matching coordinates
frame_buffer(X_COUNTER_SIZE-1 downto 0) <= std_logic_vector(x_to_send);
frame_buffer(Y_COUNTER_SIZE+15 downto 16) <= std_logic_vector(y_to_send);
frame_buffer(X_COUNTER_SIZE+31 downto 32) <= std_logic_vector(w_to_send);
frame_buffer(Y_COUNTER_SIZE+47 downto 48) <= std_logic_vector(h_to_send);
--zero padding, each value has 16 bits but only uses XY_COUNTER_SIZE bits
frame_buffer(15 downto X_COUNTER_SIZE) <= (others=>'0');
frame_buffer(31 downto X_COUNTER_SIZE+16) <= (others=>'0');
frame_buffer(47 downto X_COUNTER_SIZE+32) <= (others=>'0');
frame_buffer(63 downto X_COUNTER_SIZE+48) <= (others=>'0');
-- Get buffer ready to send
frame_buffer_has_been_filled <= '1';
frame_buffer_position <= (others=>'0') ;
end if;
--Cleaning frame coordinates
x_max <= (others=>'0');
y_max <= (others=>'0');
x_min <= unsigned(in_size_reg_in_w_reg);
y_min <= unsigned(in_size_reg_in_h_reg);
else
--send roi coord
coord_fv <= '1';
coord_dv <= '1';
coord_data <= frame_buffer(to_integer(frame_buffer_position)+7 downto to_integer(frame_buffer_position));
if frame_buffer_position >= 56 then
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '1';
else
frame_buffer_position <= frame_buffer_position + to_unsigned(8, 7);
end if;
end if;
enabled <= status_reg_enable_bit;
else
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
frame_buffer_has_been_sent <= '0';
if status_reg_enable_bit = '1' and enabled = '1' then
if(in_dv = '1' ) then
--bin img pixel counter
xBin_pos <= xBin_pos + 1;
if(xBin_pos=unsigned(in_size_reg_in_w_reg)-1) then
yBin_pos <= yBin_pos + 1;
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
end if;
-- This will give the smallest area including all non-black points
if in_data /= (in_data'range => '0') then
if xBin_pos < x_min then
x_min <= xBin_pos;
end if;
if xBin_pos > x_max then
x_max <= xBin_pos;
end if;
--
if yBin_pos < y_min then
y_min <= yBin_pos;
end if;
if yBin_pos > y_max then
y_max <= yBin_pos;
end if;
end if;
end if;
else
enabled <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out integer );
end component;
signal x : integer;
begin
sub_i: component sub
port map ( x => x );
end architecture;
|
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out integer );
end component;
signal x : integer;
begin
sub_i: component sub
port map ( x => x );
end architecture;
|
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out integer );
end component;
signal x : integer;
begin
sub_i: component sub
port map ( x => x );
end architecture;
|
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out integer );
end component;
signal x : integer;
begin
sub_i: component sub
port map ( x => x );
end architecture;
|
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out integer );
end component;
signal x : integer;
begin
sub_i: component sub
port map ( x => x );
end architecture;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_sort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : out std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : in std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_sort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_sort is
component bubblesort is
port
(
array0_addr0 : out std_logic_vector(0 to (32 - 1));
array0_dIN0 : out std_logic_vector(0 to (32 - 1));
array0_dOUT0 : in std_logic_vector(0 to (32 - 1));
array0_rENA0 : out std_logic;
array0_wENA0 : out std_logic;
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal in_BRAM_A_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_A_wEN : std_logic;
signal ap_rst : STD_LOGIC;
-- Architecture Section
begin
ap_rst <= not ap_rst_n;
BRAM_A_addr <= in_BRAM_A_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_A_wEN <= in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN;
uut : bubblesort
port map (
array0_addr0 => in_BRAM_A_addr,
array0_dIN0 => BRAM_A_din,
array0_dOUT0 => BRAM_A_dout,
array0_rENA0 => BRAM_A_en,
array0_wENA0 => in_BRAM_A_wen,
chan1_channelDataIn => M_AXIS_TDATA,
chan1_channelDataOut => S_AXIS_TDATA,
chan1_exists => S_AXIS_Tvalid,
chan1_full => not M_AXIS_Tready,
chan1_channelRead => S_AXIS_Tready,
chan1_channelWrite => M_AXIS_tvalid,
clock_sig => ap_clk,
reset_sig => ap_rst
);
end architecture implementation;
|
------------------------------------------------------------------------------
---- ----
---- ZPU Trace Module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a module to log an ----
---- execution trace. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Trace(Behave) (Entity and architecture) ----
---- File name: trace.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- std.textio ----
---- zpu.zpupkg ----
---- zpu.txt_util ----
---- Target FPGA: N/A ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
library zpu;
use zpu.zpupkg.all;
use zpu.txt_util.all;
entity Trace is
generic(
LOG_FILE : string:="trace.txt"; -- Name of the trace file
ADDR_W : integer:=16; -- Address width
WORD_SIZE : integer:=32); -- 16/32
port(
clk_i : in std_logic;
dbg_i : in zpu_dbgo_t;
stop_i : in std_logic;
busy_i : in std_logic
);
end entity Trace;
architecture Behave of Trace is
file l_file : text open write_mode is LOG_FILE;
signal counter : unsigned(63 downto 0);
begin
-- write data and control information to a file
receive_data:
process
variable l : line;
variable stk_min : unsigned(31 downto 0):=(others => '1');
variable stk_ini : unsigned(31 downto 0);
variable first : boolean:=true;
variable sp_off : unsigned(4 downto 0);
variable idim : boolean:=false;
variable im_val : unsigned(31 downto 0):=(others => '0');
begin
counter <= to_unsigned(1,64);
-- print header for the logfile
print(l_file,"#PC Opcode SP A=[SP] B=[SP+1] Clk Counter Assembler");
print(l_file,"#---------------------------------------------------------------------------");
print(l_file," ");
wait until clk_i='1';
wait until clk_i='0';
while true loop
counter <= counter+1;
if dbg_i.b_inst='1' then
write(l, "0x"&hstr(dbg_i.pc(ADDR_W-1 downto 0))&
" 0x"&hstr(dbg_i.opcode)&
" 0x"&hstr(dbg_i.sp)&
" 0x"&hstr(dbg_i.stk_a)&
" 0x"&hstr(dbg_i.stk_b)&
" 0x"&hstr(counter)&" ");
--------------------------
-- Instruction Decoder --
--------------------------
sp_off(4):=not dbg_i.opcode(4);
sp_off(3 downto 0):=dbg_i.opcode(3 downto 0);
if dbg_i.opcode(7 downto 7)=OPCODE_IM then
if idim then
im_val(31 downto 7):=im_val(24 downto 0);
im_val(6 downto 0):=dbg_i.opcode(6 downto 0);
else
im_val:=unsigned(resize(signed(dbg_i.opcode(6 downto 0)),32));
end if;
idim:=true;
write(l,"im 0x"&hstr(dbg_i.opcode(6 downto 0))&" ; 0x"&hstr(im_val));
elsif dbg_i.opcode(7 downto 5)=OPCODE_STORESP then
if sp_off=0 then
write(l,string'("storesp 0 ; pop"));
elsif sp_off=1 then
write(l,string'("storesp 4 ; 1*4 = popdown"));
else
write(l,"storesp "&integer'image(to_integer(sp_off)*4)&" ; "&
integer'image(to_integer(sp_off))&"*4");
end if;
elsif dbg_i.opcode(7 downto 5)=OPCODE_LOADSP then
if sp_off=0 then
write(l,string'("loadsp 0 ; dup"));
elsif sp_off=1 then
write(l,string'("loadsp 4 ; 1*4 = dupstkb"));
else
write(l,"loadsp "&integer'image(to_integer(sp_off)*4)&" ; "&
integer'image(to_integer(sp_off))&"*4");
end if;
elsif dbg_i.opcode(7 downto 5)=OPCODE_EMULATE then
if dbg_i.opcode(5 downto 0)=OPCODE_EQ then
write(l,string'("eq"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADB then
write(l,string'("loadb"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQBRANCH then
write(l,string'("neqbranch"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHSPADD then
write(l,string'("pushspadd"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHAN then
write(l,string'("lessthan"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHAN then
write(l,string'("ulessthan"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_MULT then
write(l,string'("mult"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREB then
write(l,string'("storeb"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_CALLPCREL then
write(l,string'("callpcrel"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_SUB then
write(l,string'("sub"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
write(l,string'("lessthanorequal"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
write(l,string'("ulessthanorequal"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_CALL then
write(l,string'("call"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_POPPCREL then
write(l,string'("poppcrel"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
write(l,string'("lshiftright"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADH then
write(l,string'("loadh"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREH then
write(l,string'("storeh"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTLEFT then
write(l,string'("ashiftleft"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTRIGHT then
write(l,string'("ashiftright"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQ then
write(l,string'("neq"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_NEG then
write(l,string'("neg"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_XOR then
write(l,string'("xor"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_DIV then
write(l,string'("div"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_MOD then
write(l,string'("mod"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_EQBRANCH then
write(l,string'("eqbranch"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_CONFIG then
write(l,string'("config"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHPC then
write(l,string'("pushpc"));
else
write(l,integer'image(to_integer(dbg_i.opcode(5 downto 0)))&
" ; invalid emulated instruction");
end if;
elsif dbg_i.opcode(7 downto 4)=OPCODE_ADDSP then
if sp_off=0 then
write(l,string'("addsp 0 ; shift"));
elsif sp_off=1 then
write(l,string'("addsp 4 ; 1*4 = addtop"));
else
write(l,"addsp "&integer'image(to_integer(sp_off)*4)&" ; "&
integer'image(to_integer(sp_off))&"*4");
end if;
else -- OPCODE_SHORT
case dbg_i.opcode(3 downto 0) is
when OPCODE_BREAK =>
write(l,string'("break"));
when OPCODE_PUSHSP =>
write(l,string'("pushsp"));
when OPCODE_POPPC =>
write(l,string'("poppc"));
when OPCODE_ADD =>
write(l,string'("add"));
when OPCODE_OR =>
write(l,string'("or"));
when OPCODE_AND =>
write(l,string'("and"));
when OPCODE_LOAD =>
write(l,string'("load"));
when OPCODE_NOT =>
write(l,string'("not"));
when OPCODE_FLIP =>
write(l,string'("flip"));
when OPCODE_STORE =>
write(l,string'("store"));
when OPCODE_POPSP =>
write(l,string'("popsp"));
when OPCODE_NOP =>
write(l,string'("nop"));
when others =>
write(l,integer'image(to_integer(dbg_i.opcode))&
" ; invalid instruction");
end case;
end if;
if dbg_i.opcode(7 downto 7)/=OPCODE_IM then
idim:=false;
end if;
-----------------------------
-- End Instruction Decoder --
-----------------------------
writeline(l_file,l);
if dbg_i.sp<stk_min then
stk_min:=dbg_i.sp;
end if;
if first then
stk_ini:=dbg_i.sp+8;
first:=false;
end if;
end if;
wait until clk_i='0' or stop_i='1';
if stop_i='1' then
print(output,"Minimum SP: 0x"&hstr(stk_min)&" Size: 0x"&hstr(stk_ini-stk_min));
wait;
end if;
end loop;
end process receive_data;
end Behave;
|
library verilog;
use verilog.vl_types.all;
entity pll_testbench is
end pll_testbench;
|
library verilog;
use verilog.vl_types.all;
entity pll_testbench is
end pll_testbench;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: MMU
-- File: mmu.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: Leon3 MMU top level entity
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu is
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end mmu;
architecture rtl of mmu is
constant MMUCTX_BITS : integer := M_CTX_SZ;
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
type mmu_op is record
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
constant mmu_op_none : mmu_op := ('0', '0', '0');
type mmu_cmbpctrl is record
tlbowner : mmu_idcache;
tlbactive : std_logic;
op : mmu_op;
end record;
constant mmu_cmbpctrl_none : mmu_cmbpctrl := (id_icache, '0', mmu_op_none);
type mmu_rtype is record
cmb_s1 : mmu_cmbpctrl;
cmb_s2 : mmu_cmbpctrl;
splt_is1 : mmu_cmbpctrl;
splt_is2 : mmu_cmbpctrl;
splt_ds1 : mmu_cmbpctrl;
splt_ds2 : mmu_cmbpctrl;
twactive : std_logic; -- split tlb
twowner : mmu_idcache; -- split tlb
flush : std_logic;
mmctrl2 : mmctrl_type2;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : mmu_rtype := (
cmb_s1 => mmu_cmbpctrl_none,
cmb_s2 => mmu_cmbpctrl_none,
splt_is1 => mmu_cmbpctrl_none,
splt_is2 => mmu_cmbpctrl_none,
splt_ds1 => mmu_cmbpctrl_none,
splt_ds2 => mmu_cmbpctrl_none,
twactive => '0',
twowner => id_icache,
flush => '0',
mmctrl2 => mmctrl2_zero);
signal r, c : mmu_rtype;
-- tlb
component mmutlb
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
signal tlbi_a0 : mmutlb_in_type;
signal tlbi_a1 : mmutlb_in_type;
signal tlbo_a0 : mmutlb_out_type;
signal tlbo_a1 : mmutlb_out_type;
signal twi_a : mmutwi_a(1 downto 0);
signal two_a : mmutwo_a(1 downto 0);
-- table walk
component mmutw
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
signal twi : mmutw_in_type;
signal two : mmutw_out_type;
signal mmctrl1 : mmctrl_type1;
begin
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
p0: process (rst, r, mmudci, mmuici, mcmmo, tlbo_a0, tlbo_a1, tlbi_a0, tlbi_a1, two_a, twi_a, two)
variable cmbtlbin : mmuidc_data_in_type;
variable cmbtlbout : mmutlb_out_type;
variable spltitlbin : mmuidc_data_in_type;
variable spltdtlbin : mmuidc_data_in_type;
variable spltitlbout : mmutlb_out_type;
variable spltdtlbout : mmutlb_out_type;
variable mmuico_transdata : mmuidc_data_out_type;
variable mmudco_transdata : mmuidc_data_out_type;
variable mmuico_grant : std_logic;
variable mmudco_grant : std_logic;
variable v : mmu_rtype;
variable twiv : mmutw_in_type;
variable twod, twoi : mmutw_out_type;
variable fault : mmutlbfault_out_type;
variable wbtransdata : mmuidc_data_out_type;
variable fs : mmctrl_fs_type;
variable fa : std_logic_vector(VA_I_SZ-1 downto 0);
begin
v := r;
wbtransdata.finish := '0';
wbtransdata.data := (others => '0');
wbtransdata.cache := '0';
wbtransdata.accexc := '0';
if (M_TLB_TYPE = 0) and (M_TLB_FASTWRITE /= 0) then
wbtransdata := tlbo_a1.wbtransdata;
end if;
cmbtlbin.data := (others => '0');
cmbtlbin.su := '0';
cmbtlbin.read := '0';
cmbtlbin.isid := id_dcache;
cmbtlbout.transdata.finish := '0';
cmbtlbout.transdata.data := (others => '0');
cmbtlbout.transdata.cache := '0';
cmbtlbout.transdata.accexc := '0';
cmbtlbout.fault.fault_pro := '0';
cmbtlbout.fault.fault_pri := '0';
cmbtlbout.fault.fault_access := '0';
cmbtlbout.fault.fault_mexc := '0';
cmbtlbout.fault.fault_trans := '0';
cmbtlbout.fault.fault_inv := '0';
cmbtlbout.fault.fault_lvl := (others => '0');
cmbtlbout.fault.fault_su := '0';
cmbtlbout.fault.fault_read := '0';
cmbtlbout.fault.fault_isid := id_dcache;
cmbtlbout.fault.fault_addr := (others => '0');
cmbtlbout.nexttrans := '0';
cmbtlbout.s1finished := '0';
mmuico_transdata.finish := '0';
mmuico_transdata.data := (others => '0');
mmuico_transdata.cache := '0';
mmuico_transdata.accexc := '0';
mmudco_transdata.finish := '0';
mmudco_transdata.data := (others => '0');
mmudco_transdata.cache := '0';
mmudco_transdata.accexc := '0';
mmuico_grant := '0';
mmudco_grant := '0';
twiv.walk_op_ur := '0';
twiv.areq_ur := '0';
twiv.data := (others => '0');
twiv.adata := (others => '0');
twiv.aaddr := (others => '0');
twod.finish := '0';
twod.data := (others => '0');
twod.addr := (others => '0');
twod.lvl := (others => '0');
twod.fault_mexc := '0';
twod.fault_trans := '0';
twod.fault_inv := '0';
twod.fault_lvl := (others => '0');
twoi.finish := '0';
twoi.data := (others => '0');
twoi.addr := (others => '0');
twoi.lvl := (others => '0');
twoi.fault_mexc := '0';
twoi.fault_trans := '0';
twoi.fault_inv := '0';
twoi.fault_lvl := (others => '0');
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
fs.ow := '0';
fs.fav := '0';
fs.ft := (others => '0');
fs.at_ls := '0';
fs.at_id := '0';
fs.at_su := '0';
fs.l := (others => '0');
fs.ebe := (others => '0');
fa := (others => '0');
if M_TLB_TYPE = 0 then
spltitlbout := tlbo_a0;
spltdtlbout := tlbo_a1;
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
spltdtlbin := mmudci.transdata;
spltitlbin := mmuici.transdata;
mmudco_transdata := spltdtlbout.transdata;
mmuico_transdata := spltitlbout.transdata;
-- d-tlb
if ((not r.splt_ds1.tlbactive) or spltdtlbout.s1finished) = '1' then
v.splt_ds1.tlbactive := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds1.op.flush_op := '0';
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
v.flush := '1';
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.flush_op := '1';
end if;
end if;
-- i-tlb
if ((not r.splt_is1.tlbactive) or spltitlbout.s1finished) = '1' then
v.splt_is1.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
if v.flush = '1' then
v.flush := '0';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.trans_op := '1';
end if;
end if;
if spltitlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
fault := spltitlbout.fault;
end if;
if spltdtlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
if (spltdtlbout.fault.fault_mexc or
spltdtlbout.fault.fault_trans or
spltdtlbout.fault.fault_inv or
spltdtlbout.fault.fault_pro or
spltdtlbout.fault.fault_pri or
spltdtlbout.fault.fault_access) = '1' then
fault := spltdtlbout.fault; -- overwrite icache fault
end if;
end if;
if spltitlbout.s1finished = '1' then
v.splt_is2 := r.splt_is1;
end if;
if spltdtlbout.s1finished = '1' then
v.splt_ds2 := r.splt_ds1;
end if;
if ( r.splt_is2.op.flush_op ) = '1' then
mmuico_transdata.finish := '0';
end if;
-- share tw
if two.finish = '1' then
v.twactive := '0';
end if;
if r.twowner = id_icache then
twiv := twi_a(0);
twoi.finish := two.finish;
else
twiv := twi_a(1);
twod.finish := two.finish;
end if;
if (v.twactive) = '0' then
if (twi_a(1).areq_ur or twi_a(1).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_dcache;
elsif (twi_a(0).areq_ur or twi_a(0).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_icache;
end if;
end if;
else
--# combined i/d cache: 1 tlb, 1 tw
-- share one tlb among i and d cache
cmbtlbout := tlbo_a0;
mmuico_grant := '0'; mmudco_grant := '0';
mmuico_transdata.finish := '0'; mmudco_transdata.finish := '0';
twiv := twi_a(0);
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
-- twod.finish := two.finish;
twoi.finish := two.finish;
if ((not v.cmb_s1.tlbactive) or cmbtlbout.s1finished) = '1' then
v.cmb_s1.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
if (mmudci.trans_op or mmudci.flush_op or mmuici.trans_op) = '1' then
v.cmb_s1.tlbactive := '1';
end if;
if mmuici.trans_op = '1' then
mmuico_grant := '1';
v.cmb_s1.tlbowner := id_icache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.trans_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.flush_op := '1';
end if;
end if;
if (r.cmb_s1.tlbactive and not r.cmb_s2.tlbactive) = '1' then
end if;
if cmbtlbout.s1finished = '1' then
v.cmb_s2 := r.cmb_s1;
end if;
if r.cmb_s1.tlbowner = id_dcache then
cmbtlbin := mmudci.transdata;
else
cmbtlbin := mmuici.transdata;
end if;
if r.cmb_s2.tlbowner = id_dcache then
mmudco_transdata := cmbtlbout.transdata;
else
mmuico_transdata := cmbtlbout.transdata;
end if;
if cmbtlbout.transdata.finish = '1' and (r.cmb_s2.op.flush_op = '0') then
fault := cmbtlbout.fault;
end if;
end if;
-- # fault status register
if (mmudci.fsread) = '1' then
v.mmctrl2.valid := '0'; v.mmctrl2.fs.fav := '0';
end if;
-- SRMMU Fault Priorities
-- Pri Error
-------------------------
-- 1 Internal error
-- 2 Translation error
-- 3 Invalid address error
-- 4 Privilege violation error
-- 5 Protection error
-- 6 Access bus error
if (fault.fault_mexc) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_trans) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_inv) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_pri) = '1' then
fs.ft := FS_FT_PRI;
elsif (fault.fault_pro) = '1' then
fs.ft := FS_FT_PRO;
elsif (fault.fault_access) = '1' then
fs.ft := FS_FT_BUS;
else
fs.ft := FS_FT_NONE;
end if;
fs.ow := '0';
fs.l := fault.fault_lvl;
if fault.fault_isid = id_dcache then
fs.at_id := '0';
else
fs.at_id := '1';
end if;
fs.at_su := fault.fault_su;
fs.at_ls := not fault.fault_read;
fs.fav := '1';
fs.ebe := (others => '0');
fa := fault.fault_addr(VA_I_U downto VA_I_D);
if (fault.fault_mexc or
fault.fault_trans or
fault.fault_inv or
fault.fault_pro or
fault.fault_pri or
fault.fault_access) = '1' then
--# priority
--
if v.mmctrl2.valid = '1'then
if (fault.fault_mexc) = '1' then
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- An instruction or data access fault may not overwrite a
-- translation table access fault.
if (r.mmctrl2.fs.ft /= FS_FT_TRANS) then
if fault.fault_isid = id_dcache then
-- dcache, overwrite bit is cleared
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- icache
-- an inst access fault may not overwrite a data access fault:
if (not r.mmctrl2.fs.at_id) = '0' then
fs.ow := '1';
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
end if;
end if;
end if;
end if;
else
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
v.mmctrl2.valid := '1';
end if;
if (fault.fault_isid) = id_dcache then
mmudco_transdata.accexc := '1';
else
mmuico_transdata.accexc := '1';
end if;
end if;
-- # reset
if (not ASYNC_RESET) and ( not RESET_ALL ) and ( rst = '0' ) then
if M_TLB_TYPE = 0 then
v.splt_is1.tlbactive := RRES.splt_is1.tlbactive;
v.splt_is2.tlbactive := RRES.splt_is2.tlbactive;
v.splt_ds1.tlbactive := RRES.splt_ds1.tlbactive;
v.splt_ds2.tlbactive := RRES.splt_ds2.tlbactive;
v.splt_is1.op.trans_op := RRES.splt_is1.op.trans_op;
v.splt_is2.op.trans_op := RRES.splt_is2.op.trans_op;
v.splt_ds1.op.trans_op := RRES.splt_ds1.op.trans_op;
v.splt_ds2.op.trans_op := RRES.splt_ds2.op.trans_op;
v.splt_is1.op.flush_op := RRES.splt_is1.op.flush_op;
v.splt_is2.op.flush_op := RRES.splt_is2.op.flush_op;
v.splt_ds1.op.flush_op := RRES.splt_ds1.op.flush_op;
v.splt_ds2.op.flush_op := RRES.splt_ds2.op.flush_op;
else
v.cmb_s1.tlbactive := RRES.cmb_s1.tlbactive;
v.cmb_s2.tlbactive := RRES.cmb_s2.tlbactive;
v.cmb_s1.op.trans_op := RRES.cmb_s1.op.trans_op;
v.cmb_s2.op.trans_op := RRES.cmb_s2.op.trans_op;
v.cmb_s1.op.flush_op := RRES.cmb_s1.op.flush_op;
v.cmb_s2.op.flush_op := RRES.cmb_s2.op.flush_op;
end if;
v.flush := RRES.flush;
v.mmctrl2.valid := RRES.mmctrl2.valid;
v.twactive := RRES.twactive;
v.twowner := RRES.twowner;
end if;
-- drive signals
if M_TLB_TYPE = 0 then
tlbi_a0.trans_op <= r.splt_is1.op.trans_op;
tlbi_a0.flush_op <= r.splt_is1.op.flush_op;
tlbi_a0.transdata <= spltitlbin;
tlbi_a0.s2valid <= r.splt_is2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
tlbi_a1.trans_op <= r.splt_ds1.op.trans_op;
tlbi_a1.flush_op <= r.splt_ds1.op.flush_op;
tlbi_a1.transdata <= spltdtlbin;
tlbi_a1.s2valid <= r.splt_ds2.tlbactive;
tlbi_a1.mmctrl1 <= mmudci.mmctrl1;
tlbi_a1.wb_op <= mmudci.wb_op;
else
tlbi_a0.trans_op <= r.cmb_s1.op.trans_op;
tlbi_a0.flush_op <= r.cmb_s1.op.flush_op;
tlbi_a0.transdata <= cmbtlbin;
tlbi_a0.s2valid <= r.cmb_s2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
end if;
mmudco.transdata <= mmudco_transdata;
mmuico.transdata <= mmuico_transdata;
mmudco.grant <= mmudco_grant;
mmuico.grant <= mmuico_grant;
mmuico.tlbmiss <= twi_a(0).tlbmiss;
mmudco.mmctrl2 <= r.mmctrl2;
mmudco.wbtransdata <= wbtransdata;
twi <= twiv;
two_a(0) <= twoi;
two_a(1) <= twod;
mmctrl1 <= mmudci.mmctrl1;
c <= v;
end process p0;
tlbcomb0: if M_TLB_TYPE = 1 generate
-- i/d tlb
ctlb0 : mmutlb
generic map ( tech, M_ENT_C, 0, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0), testin
);
mmudco.tlbmiss <= twi_a(0).tlbmiss;
end generate tlbcomb0;
tlbsplit0: if M_TLB_TYPE = 0 generate
-- i tlb
itlb0 : mmutlb
generic map ( tech, M_ENT_I, 0, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0), testin
);
-- d tlb
dtlb0 : mmutlb
generic map ( tech, M_ENT_D, tlb_type, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a1, tlbo_a1, two_a(1), twi_a(1), testin
);
mmudco.tlbmiss <= twi_a(1).tlbmiss;
end generate tlbsplit0;
-- table walk component
tw0 : mmutw
generic map ( mmupgsz )
port map (rst, clk, mmctrl1, twi, two, mcmmo, mcmmi);
-- pragma translate_off
chk : process
begin
assert not ((M_TLB_TYPE = 1) and (M_TLB_FASTWRITE /= 0)) report
"Fast writebuffer only supported for combined cache"
severity failure;
wait;
end process;
-- pragma translate_on
end rtl;
|
-------------------------------------------------------------------------------
-- SPI Status Register Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2011] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xip_status_reg.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus. The file defines the logic for
-- status register in XIP mode.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.log2;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-- C_S_AXI_DATA_WIDTH -- Native data bus width 32 bits only
-- C_NUM_SS_BITS -- Number of bits in slave select
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- STATUS REGISTER RELATED SIGNALS
--================================
-- REGISTER/FIFO INTERFACE
-- Bus2IP_SPISR_RdCE -- Status register Read Chip Enable
-- IP2Bus_SPISR_Data -- Status register data to PLB based on PLB read
-- SR_3_modf -- Mode fault error status flag
-- SR_4_Tx_Full -- Transmit register full status flag
-- SR_5_Tx_Empty -- Transmit register empty status flag
-- SR_6_Rx_Full -- Receive register full status flag
-- SR_7_Rx_Empty -- Receive register empty stauts flag
-- ModeFault_Strobe -- Mode fault strobe
-- SLAVE REGISTER RELATED SIGNALS
--===============================
-- Bus2IP_SPISSR_WrCE -- slave select register write chip enable
-- Bus2IP_SPISSR_RdCE -- slave select register read chip enable
-- Bus2IP_SPISSR_Data -- slave register data from PLB Bus
-- IP2Bus_SPISSR_Data -- Data from slave select register during PLB rd
-- SPISSR_Data_reg_op -- Data to SPI Module
-- Wr_ce_reduce_ack_gen -- commaon write ack generation signal
-- Rd_ce_reduce_ack_gen -- commaon read ack generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity xip_status_reg is
generic
(
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
------------------------
C_XIP_SPISR_REG_WIDTH : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
--------------------------
XIPSR_AXI_TR_ERR : in std_logic; -- bit 4 of XIPSR
XIPSR_CPHA_CPOL_ERR : in std_logic; -- bit 3 of XIPSR
XIPSR_MST_MODF_ERR : in std_logic; -- bit 2 of XIPSR
XIPSR_AXI_RX_FULL : in std_logic; -- bit 1 of XIPSR
XIPSR_AXI_RX_EMPTY : in std_logic; -- bit 0 of XIPSR
--------------------------
Bus2IP_XIPSR_WrCE : in std_logic;
Bus2IP_XIPSR_RdCE : in std_logic;
--------------------------
--IP2Bus_XIPSR_RdAck : out std_logic;
--IP2Bus_XIPSR_WrAck : out std_logic;
IP2Bus_XIPSR_Data : out std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
ip2Bus_RdAck : in std_logic
);
end xip_status_reg;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of xip_status_reg is
----------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal XIPSR_data_int : std_logic_vector(C_XIP_SPISR_REG_WIDTH-1 downto 0);
--signal ip2Bus_RdAck_core_reg : std_logic;
--signal ip2Bus_RdAck_core_reg_d1 : std_logic;
--signal ip2Bus_WrAck_core_reg : std_logic;
--signal ip2Bus_WrAck_core_reg_d1 : std_logic;
----------------------
begin
-----
-- XIPSR - 31 -- -- 5 4 3 2 1 0
-- <-- NA --> AXI CPOL_CPHA MODF Rx Rx
-- Transaction Error Error Error Full Empty
-- Default 0 0 0 0 0
-------------------------------------------------------------------------------
--XIPSR_CMD_ERR <= '0';
---------------------------------------
XIPSR_DATA_STORE_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)<= (others => '0');
elsif(ip2Bus_RdAck = '1') then
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)<= (others => '0');
else
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)
<= XIPSR_AXI_TR_ERR & -- bit 4
XIPSR_CPHA_CPOL_ERR &
XIPSR_MST_MODF_ERR &
XIPSR_AXI_RX_FULL &
XIPSR_AXI_RX_EMPTY ; -- bit 0
end if;
end if;
end process XIPSR_DATA_STORE_P;
--------------------------------------------------
XIPSR_REG_RD_GENERATE: for i in C_XIP_SPISR_REG_WIDTH-1 downto 0 generate
-----
begin
-----
IP2Bus_XIPSR_Data(i) <= XIPSR_data_int(i) and Bus2IP_XIPSR_RdCE ; --and ip2Bus_RdAck_core_reg;
end generate XIPSR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo AudioVideo_Init.vhd
-- Versione 1.02 - 18.03.2013
-- **********************************************************
-- **********************************************************
-- Questo modulo si occupa del caricamento dati sui
-- registri di controllo Audio/Video della scheda dopo ogni
-- reset del sistema.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity AudioVideo_Init is generic (
MIN_ROM_ADDRESS: std_logic_vector(5 downto 0) := "000000"; --6'h00;
MAX_ROM_ADDRESS: std_logic_vector(5 downto 0) := "001010"; --6'h0A;
AUD_LINE_IN_LC: std_logic_vector(8 downto 0) := "000011000"; --9'd24;
AUD_LINE_IN_RC: std_logic_vector(8 downto 0) := "000011000"; --9'd24;
AUD_LINE_OUT_LC: std_logic_vector(8 downto 0) := "001110111"; --9'd119;
AUD_LINE_OUT_RC: std_logic_vector(8 downto 0) := "001110111"; --9'd119;
AUD_ADC_PATH: std_logic_vector(8 downto 0) := "000010001"; --9'd17;
AUD_DAC_PATH: std_logic_vector(8 downto 0) := "000000110"; --9'd6;
AUD_POWER: std_logic_vector(8 downto 0) := "000000000"; --9'h000;
AUD_DATA_FORMAT: std_logic_vector(8 downto 0) := "001001101"; --9'd77;
AUD_SAMPLE_CTRL: std_logic_vector(8 downto 0) := "000000000"; --9'd0;
AUD_SET_ACTIVE: std_logic_vector(8 downto 0) := "000000001" --9'h001;
);
port (
clk: in std_logic;
reset: in std_logic;
clear_error: in std_logic;
ack: in std_logic;
transfer_complete: in std_logic;
data_out: out std_logic_vector(7 downto 0);
transfer_data: buffer std_logic;
send_start_bit: out std_logic;
send_stop_bit: out std_logic;
auto_init_complete: out std_logic;
auto_init_error: out std_logic;
useMicInput: in std_logic
);
end AudioVideo_Init;
architecture behaviour of AudioVideo_Init is
-- Definizione stati della FSM per l'inizializzazione
constant AUTO_STATE_0_CHECK_STATUS: std_logic_vector(2 downto 0) := "000";
constant AUTO_STATE_1_SEND_START_BIT: std_logic_vector(2 downto 0) := "001";
constant AUTO_STATE_2_TRANSFER_BYTE_1: std_logic_vector(2 downto 0) := "010";
constant AUTO_STATE_3_TRANSFER_BYTE_2: std_logic_vector(2 downto 0) := "011";
constant AUTO_STATE_4_WAIT: std_logic_vector(2 downto 0) := "100";
constant AUTO_STATE_5_SEND_STOP_BIT: std_logic_vector(2 downto 0) := "101";
constant AUTO_STATE_6_INCREASE_COUNTER: std_logic_vector(2 downto 0) := "110";
constant AUTO_STATE_7_DONE: std_logic_vector(2 downto 0) := "111";
signal change_state: std_logic;
signal finished_auto_init: std_logic;
signal rom_address_counter: std_logic_vector(5 downto 0);
signal rom_data: std_logic_vector(25 downto 0);
signal ns_i2c_auto_init: std_logic_vector(2 downto 0);
signal s_i2c_auto_init: std_logic_vector(2 downto 0);
-- Segnale di buffer
signal rom_data_buff: std_logic_vector(27 downto 0);
begin
rom_data <= rom_data_buff(25 downto 0);
auto_init_complete <= '1' when (s_i2c_auto_init = AUTO_STATE_7_DONE) else '0';
change_state <= transfer_complete and transfer_data;
finished_auto_init <= '1' when (rom_address_counter = MAX_ROM_ADDRESS) else '0';
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
s_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
else
s_i2c_auto_init <= ns_i2c_auto_init;
end if;
end if;
end process;
process (all)
begin
ns_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
---------------------------------------------------------------------------------------------
------------------------------------------------------------------ FSM Inizializzazione Audio
---------------------------------------------------------------------------------------------
if (s_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS) then
if (finished_auto_init = '1') then
ns_i2c_auto_init <= AUTO_STATE_7_DONE;
elsif (rom_data(25) = '1') then
ns_i2c_auto_init <= AUTO_STATE_1_SEND_START_BIT;
else
ns_i2c_auto_init <= AUTO_STATE_3_TRANSFER_BYTE_2;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT) then
if (change_state = '1') then
ns_i2c_auto_init <= AUTO_STATE_2_TRANSFER_BYTE_1;
else
ns_i2c_auto_init <= AUTO_STATE_1_SEND_START_BIT;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1) then
if (change_state = '1') then
ns_i2c_auto_init <= AUTO_STATE_3_TRANSFER_BYTE_2;
else
ns_i2c_auto_init <= AUTO_STATE_2_TRANSFER_BYTE_1;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2) then
if ((change_state = '1') and (rom_data(24) = '1')) then
ns_i2c_auto_init <= AUTO_STATE_4_WAIT;
elsif (change_state = '1') then
ns_i2c_auto_init <= AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init <= AUTO_STATE_3_TRANSFER_BYTE_2;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_4_WAIT) then
if (transfer_complete = '0') then
ns_i2c_auto_init <= AUTO_STATE_5_SEND_STOP_BIT;
else
ns_i2c_auto_init <= AUTO_STATE_4_WAIT;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT) then
if (transfer_complete = '1') then
ns_i2c_auto_init <= AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init <= AUTO_STATE_5_SEND_STOP_BIT;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER) then
ns_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
elsif (s_i2c_auto_init = AUTO_STATE_7_DONE) then
ns_i2c_auto_init <= AUTO_STATE_7_DONE;
else
ns_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
data_out <= "00000000";
elsif (s_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT) then
data_out <= rom_data(23 downto 16);
elsif (s_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS) then
data_out <= rom_data(15 downto 8);
elsif (s_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1) then
data_out <= rom_data(15 downto 8);
elsif (s_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2) then
data_out <= rom_data( 7 downto 0);
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
transfer_data <= '0';
elsif (transfer_complete = '1') then
transfer_data <= '0';
elsif (s_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT) then
transfer_data <= '1';
elsif (s_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1) then
transfer_data <= '1';
elsif (s_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2) then
transfer_data <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
send_start_bit <= '0';
elsif (transfer_complete = '1') then
send_start_bit <= '0';
elsif (s_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT) then
send_start_bit <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
send_stop_bit <= '0';
elsif (transfer_complete = '1') then
send_stop_bit <= '0';
elsif (s_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT) then
send_stop_bit <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
auto_init_error <= '0';
elsif (clear_error = '1') then
auto_init_error <= '0';
elsif ((s_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER) and ack='1') then
auto_init_error <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
rom_address_counter <= MIN_ROM_ADDRESS;
elsif (s_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER) then
rom_address_counter <= rom_address_counter + "000001";
end if;
end if;
end process;
process (clk, reset, clear_error, ack, transfer_complete)
begin
case (rom_address_counter) is
-- Scrittura configurazione Audio: 7 bit di indirizzo + 9 bit di dati
-- Nota: i primi 2 bit sono usati per comodita' per portare a 28 i bit e usare valori esadecimali!
when "000000" => rom_data_buff <= "00" & "1100110100" & "0000000" & AUD_LINE_IN_LC;
when "000001" => rom_data_buff <= "00" & "1100110100" & "0000001" & AUD_LINE_IN_RC;
when "000010" => rom_data_buff <= "00" & "1100110100" & "0000010" & AUD_LINE_OUT_LC;
when "000011" => rom_data_buff <= "00" & "1100110100" & "0000011" & AUD_LINE_OUT_RC;
when "000100" => rom_data_buff <= ("00" & "1100110100" & "0000100" & AUD_ADC_PATH)
+ ("00" & "00000000000000000000000" & useMicInput & "00"); -- Microfono o Linein
when "000101" => rom_data_buff <= "00" & "1100110100" & "0000101" & AUD_DAC_PATH;
when "000110" => rom_data_buff <= "00" & "1100110100" & "0000110" & AUD_POWER;
when "000111" => rom_data_buff <= "00" & "1100110100" & "0000111" & AUD_DATA_FORMAT;
when "001000" => rom_data_buff <= "00" & "1100110100" & "0001000" & AUD_SAMPLE_CTRL;
when "001001" => rom_data_buff <= "00" & "1100110100" & "0001001" & AUD_SET_ACTIVE;
-- Scrittura configurazione Video
when "001010" => rom_data_buff <= X"3401500";
when "001011" => rom_data_buff <= X"3401741";
when "001100" => rom_data_buff <= X"3403a16";
when "001101" => rom_data_buff <= X"3405004";
when "001110" => rom_data_buff <= X"340c305";
when "001111" => rom_data_buff <= X"340c480";
when "010000" => rom_data_buff <= X"3400e80";
when "010001" => rom_data_buff <= X"3405020";
when "010010" => rom_data_buff <= X"3405218";
when "010011" => rom_data_buff <= X"34058ed";
when "010100" => rom_data_buff <= X"34077c5";
when "010101" => rom_data_buff <= X"3407c93";
when "010110" => rom_data_buff <= X"3407d00";
when "010111" => rom_data_buff <= X"340d048";
when "011000" => rom_data_buff <= X"340d5a0";
when "011001" => rom_data_buff <= X"340d7ea";
when "011010" => rom_data_buff <= X"340e43e";
when "011011" => rom_data_buff <= X"340ea0f";
when "011100" => rom_data_buff <= X"3403112";
when "011101" => rom_data_buff <= X"3403281";
when "011110" => rom_data_buff <= X"3403384";
when "011111" => rom_data_buff <= X"34037A0";
when "100000" => rom_data_buff <= X"340e580";
when "100001" => rom_data_buff <= X"340e603";
when "100010" => rom_data_buff <= X"340e785";
when "100011" => rom_data_buff <= X"3405000";
when "100100" => rom_data_buff <= X"3405100";
when "100101" => rom_data_buff <= X"3400070";
when "100110" => rom_data_buff <= X"3401010";
when "100111" => rom_data_buff <= X"3400482";
when "101000" => rom_data_buff <= X"3400860";
when "101001" => rom_data_buff <= X"3400a18";
when "101010" => rom_data_buff <= X"3401100";
when "101011" => rom_data_buff <= X"3402b00";
when "101100" => rom_data_buff <= X"3402c8c";
when "101101" => rom_data_buff <= X"3402df2";
when "101110" => rom_data_buff <= X"3402eee";
when "101111" => rom_data_buff <= X"3402ff4";
when "110000" => rom_data_buff <= X"34030d2";
when "110001" => rom_data_buff <= X"3400e05";
when others => rom_data_buff <= X"1000000";
end case;
end process;
end behaviour; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:04:53 01/02/2016
-- Design Name:
-- Module Name: C:/Users/Kurtis/Desktop/mtcSvn/temp/LucaIRS3D_Ethernet_firmware/src/firmware-general/General/sim/ByteLinkTest.vhd
-- Project Name: scrodMtc
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ByteLink
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ByteLinkTest IS
END ByteLinkTest;
ARCHITECTURE behavior OF ByteLinkTest IS
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rxData8bA : std_logic_vector(7 downto 0);
signal rxData8bValidA : std_logic;
signal rxData8bB : std_logic_vector(7 downto 0);
signal rxData8bValidB : std_logic;
signal alignedA : std_logic;
signal alignedB : std_logic;
signal txData10bA : std_logic_vector(9 downto 0);
signal txData10bB : std_logic_vector(9 downto 0);
signal txData8bA : std_logic_vector(7 downto 0) := (others => '0');
signal txData8bValidA : std_logic := '0';
signal txData8bB : std_logic_vector(7 downto 0) := (others => '0');
signal txData8bValidB : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
U_ByteLinkA : entity work.ByteLink PORT MAP (
clk => clk,
rst => rst,
rxData10b => txData10bB,
rxData8b => rxData8bA,
rxData8bValid => rxData8bValidA,
aligned => alignedA,
txData8b => txData8bA,
txData8bValid => txData8bValidA,
txData10b => txData10bA
);
U_ByteLinkB : entity work.ByteLink PORT MAP (
clk => clk,
rst => rst,
rxData10b => txData10bA,
rxData8b => rxData8bB,
rxData8bValid => rxData8bValidB,
aligned => alignedB,
txData8b => txData8bB,
txData8bValid => txData8bValidB,
txData10b => txData10bB
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
wait for clk_period*10;
rst <= '0';
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1640.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p06n01i01640ent IS
END c08s12b00x00p06n01i01640ent;
ARCHITECTURE c08s12b00x00p06n01i01640arch OF c08s12b00x00p06n01i01640ent IS
BEGIN
TESTING: PROCESS
function ts (x1:bit) return integer is
begin
return ('1');
end ts;
variable k : integer := 0;
BEGIN
k := ts('1');
assert FALSE
report "***FAILED TEST: c08s12b00x00p06n01i01640 - Value of the expression is of different subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p06n01i01640arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1640.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p06n01i01640ent IS
END c08s12b00x00p06n01i01640ent;
ARCHITECTURE c08s12b00x00p06n01i01640arch OF c08s12b00x00p06n01i01640ent IS
BEGIN
TESTING: PROCESS
function ts (x1:bit) return integer is
begin
return ('1');
end ts;
variable k : integer := 0;
BEGIN
k := ts('1');
assert FALSE
report "***FAILED TEST: c08s12b00x00p06n01i01640 - Value of the expression is of different subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p06n01i01640arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1640.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p06n01i01640ent IS
END c08s12b00x00p06n01i01640ent;
ARCHITECTURE c08s12b00x00p06n01i01640arch OF c08s12b00x00p06n01i01640ent IS
BEGIN
TESTING: PROCESS
function ts (x1:bit) return integer is
begin
return ('1');
end ts;
variable k : integer := 0;
BEGIN
k := ts('1');
assert FALSE
report "***FAILED TEST: c08s12b00x00p06n01i01640 - Value of the expression is of different subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p06n01i01640arch;
|
-- $Id: tst_serlooplib.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: tst_serlooplib
-- Description: Definitions for tst_serloop records and helpers
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-10-14 416 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.serportlib.all;
package tst_serlooplib is
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
type hio_cntl_type is record -- humanio controls
mode : slv2; -- mode (idle,(tx|tx)blast,loop)
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
end record hio_cntl_type;
constant hio_cntl_init : hio_cntl_type := (
c_mode_idle, -- mode
'0','0','0','0' -- enaxon,enaesc,enathrottle,enaftdi
);
type hio_stat_type is record -- humanio status
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
end record hio_stat_type;
constant hio_stat_init : hio_stat_type := (
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0') -- txokcnt
);
-- -------------------------------------
component tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end component;
component tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to display by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end component;
end package tst_serlooplib;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_502 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_502;
architecture augh of mul_502 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_502 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_502;
architecture augh of mul_502 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:28 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_0_0/ip_design_axi_gpio_0_0_stub.vhdl
-- Design : ip_design_axi_gpio_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ip_design_axi_gpio_0_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end ip_design_axi_gpio_0_0;
architecture stub of ip_design_axi_gpio_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[1:0],gpio_io_o[1:0],gpio_io_t[1:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2017.3";
begin
end;
|
--------------------------------------------------------------------------------
-- Entity: mul_add
-- Date:2018-08-02
-- Author: gideon
--
-- Description: VHDL only version of multiply accumulate with double accu
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mul_add is
port (
clock : in std_logic;
clear : in std_logic;
a : in signed(17 downto 0);
b : in signed(8 downto 0);
result : out signed(31 downto 0)
);
end entity;
architecture arch of mul_add is
signal mult : signed(26 downto 0);
signal accu_reg1 : signed(31 downto 0);
signal accu_reg2 : signed(31 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if clear = '1' then
accu_reg1 <= (others => '0');
accu_reg2 <= (others => '0');
else
accu_reg1 <= accu_reg2 + mult;
accu_reg2 <= accu_reg1;
end if;
mult <= a * b;
end if;
end process;
result <= accu_reg1;
end architecture;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity TBCommon is
port (
clk : buffer std_logic;
a : out std_logic_vector(31 downto 0) := (others => '0');
b : out std_logic_vector(31 downto 0) := (others => '0');
d : in std_logic_vector(31 downto 0));
end TBCommon;
architecture testbench_file of TBCommon is
signal delay1, delay2, delay3 : boolean := false;
begin
main : process(clk)
file testdata_in : text open read_mode is "testdata.in";
file testdata_out : text open write_mode is "testdata.out";
variable li, lo : line;
variable at, bt, dt : std_logic_vector(31 downto 0);
begin
if rising_edge(clk) then
if endfile(testdata_in) then
delay1 <= false;
else
readline(testdata_in, li);
hread(li, at);
hread(li, bt);
a <= at;
b <= bt;
delay1 <= true;
end if;
delay2 <= delay1;
delay3 <= delay2;
if delay3 then
dt := d;
hwrite(lo, dt);
writeline(testdata_out, lo);
end if;
end if;
end process;
clkgen : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
end testbench_file;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:45:59 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_transform_0_0/system_vga_transform_0_0_stub.vhdl
-- Design : system_vga_transform_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_transform_0_0 is
Port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_transform_0_0;
architecture stub of system_vga_transform_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,enable,x_addr_in[9:0],y_addr_in[9:0],rot_m00[15:0],rot_m01[15:0],rot_m10[15:0],rot_m11[15:0],t_x[9:0],t_y[9:0],x_addr_out[9:0],y_addr_out[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_transform,Vivado 2016.4";
begin
end;
|
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
|
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
|
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
entity msg_tap is
generic (
D : positive -- Message Buffer Depth (Size)
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Tap Input
iful : out std_logic;
idat : in byte;
ieof : in std_logic;
iput : in std_logic;
-- Tap Forward
oful : in std_logic;
odat : out byte;
oeof : out std_logic;
oput : out std_logic;
-- Tap
tful : in std_logic;
tdat : out std_logic_vector(0 to 8*D-1);
tput : out std_logic
);
end msg_tap;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of msg_tap is
type tState is (Receive, Hold, Transmit);
signal State : tState := Receive;
signal Buf : byte_vector(0 to D-1) := (others => (others => '-'));
signal Cnt : signed(log2ceil(imax(D-1, 1)) downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Receive;
Buf <= (others => (others => '-'));
Cnt <= (others => '-');
else
case State is
when Receive =>
Cnt <= (others => '-');
if iput = '1' then
Buf <= Buf(1 to D-1) & idat;
if ieof = '1' then
State <= Hold;
end if;
end if;
when Hold =>
Cnt <= (others => '-');
if tful = '0' then
State <= Receive;
elsif oful = '0' then
Cnt <= to_signed(D-2, Cnt'length);
State <= Transmit;
end if;
when Transmit =>
if oful = '0' then
Buf <= Buf(1 to D-1) & byte'(7 downto 0 => '-');
Cnt <= Cnt - 1;
if Cnt(Cnt'left) = '1' then
State <= Receive;
end if;
end if;
end case;
end if;
end if;
end process;
iful <= '0' when State = Receive else '1';
genParOut: for i in Buf'range generate
tdat(8*i to 8*i+7) <= Buf(i);
end generate genParOut;
tput <= not tful when State = Hold else '0';
odat <= Buf(0);
oeof <= Cnt(Cnt'left);
oput <= '0' when State /= Transmit else
'0' when oful = '1' else
'1';
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
entity msg_tap is
generic (
D : positive -- Message Buffer Depth (Size)
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Tap Input
iful : out std_logic;
idat : in byte;
ieof : in std_logic;
iput : in std_logic;
-- Tap Forward
oful : in std_logic;
odat : out byte;
oeof : out std_logic;
oput : out std_logic;
-- Tap
tful : in std_logic;
tdat : out std_logic_vector(0 to 8*D-1);
tput : out std_logic
);
end msg_tap;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of msg_tap is
type tState is (Receive, Hold, Transmit);
signal State : tState := Receive;
signal Buf : byte_vector(0 to D-1) := (others => (others => '-'));
signal Cnt : signed(log2ceil(imax(D-1, 1)) downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Receive;
Buf <= (others => (others => '-'));
Cnt <= (others => '-');
else
case State is
when Receive =>
Cnt <= (others => '-');
if iput = '1' then
Buf <= Buf(1 to D-1) & idat;
if ieof = '1' then
State <= Hold;
end if;
end if;
when Hold =>
Cnt <= (others => '-');
if tful = '0' then
State <= Receive;
elsif oful = '0' then
Cnt <= to_signed(D-2, Cnt'length);
State <= Transmit;
end if;
when Transmit =>
if oful = '0' then
Buf <= Buf(1 to D-1) & byte'(7 downto 0 => '-');
Cnt <= Cnt - 1;
if Cnt(Cnt'left) = '1' then
State <= Receive;
end if;
end if;
end case;
end if;
end if;
end process;
iful <= '0' when State = Receive else '1';
genParOut: for i in Buf'range generate
tdat(8*i to 8*i+7) <= Buf(i);
end generate genParOut;
tput <= not tful when State = Hold else '0';
odat <= Buf(0);
oeof <= Cnt(Cnt'left);
oput <= '0' when State /= Transmit else
'0' when oful = '1' else
'1';
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.i2s_controller;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_streaming_dma_rx_fifo;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl330_dma_fifo;
use adi_common_v1_00_a.axi_ctrlif;
entity axi_i2s_adi_v1_2 is
generic (
-- Users to add parameters here
C_SLOT_WIDTH : integer := 24;
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_DMA_TYPE : integer := 0;
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- Serial Data interface
DATA_CLK_I : in std_logic;
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0);
MUTEN_O : out std_logic;
-- AXI Streaming DMA TX interface
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- AXI Streaming DMA RX interface
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
--PL330 DMA TX interface
DMA_REQ_TX_ACLK : in std_logic;
DMA_REQ_TX_RSTN : in std_logic;
DMA_REQ_TX_DAVALID : in std_logic;
DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_TX_DAREADY : out std_logic;
DMA_REQ_TX_DRVALID : out std_logic;
DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_TX_DRLAST : out std_logic;
DMA_REQ_TX_DRREADY : in std_logic;
-- PL330 DMA RX interface
DMA_REQ_RX_ACLK : in std_logic;
DMA_REQ_RX_RSTN : in std_logic;
DMA_REQ_RX_DAVALID : in std_logic;
DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_RX_DAREADY : out std_logic;
DMA_REQ_RX_DRVALID : out std_logic;
DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_RX_DRLAST : out std_logic;
DMA_REQ_RX_DRREADY : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_i2s_adi_v1_2;
architecture arch_imp of axi_i2s_adi_v1_2 is
-- component declaration
component axi_i2s_adi_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
rd_addr : out integer range 0 to 12 - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_ack : out std_logic;
wr_addr : out integer range 0 to 12 - 1;
wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_stb : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_i2s_adi_S_AXI;
signal i2s_reset : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_enable : Boolean;
signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal tx_ack : std_logic;
signal tx_stb : std_logic;
signal tx_fifo_full : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_in_ack : std_logic;
signal rx_enable : Boolean;
signal rx_fifo_reset : std_logic;
signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal rx_ack : std_logic;
signal rx_stb : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_out_stb : std_logic;
signal bclk_div_rate : natural range 0 to 255;
signal lrclk_div_rate : natural range 0 to 255;
signal period_len : integer range 0 to 65535;
signal I2S_RESET_REG : std_logic_vector(31 downto 0);
signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8))));
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
-- RX FIFO signals
signal audio_fifo_rx : RAM_TYPE;
signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal tvalid : std_logic := '0';
signal rx_tlast : std_logic;
signal drain_tx_dma : std_logic;
signal rx_sample : std_logic_vector(23 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 11;
signal rd_addr : integer range 0 to 11;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
signal tx_fifo_stb : std_logic;
signal rx_fifo_ack : std_logic;
signal cnt : integer range 0 to 2**16-1;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_i2s_adi_S_AXI_inst : axi_i2s_adi_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
wr_addr => wr_addr,
wr_data => wr_data,
wr_stb => wr_stb,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
process (s00_axi_aclk)
begin
if rising_edge(s00_axi_aclk) then
if s00_axi_aresetn = '0' then
cnt <= 0;
else
cnt <= (cnt + 1) mod 2**16;
end if;
end if;
end process;
streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate
tx_fifo : entity axi_streaming_dma_tx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8),
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
out_stb => tx_stb,
out_ack => tx_ack,
out_data => tx_data
);
end generate;
streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
period_len => period_len,
in_stb => rx_stb,
in_ack => rx_ack,
in_data => rx_data,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8),
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
M_AXIS_TDATA(7 downto 0) <= (others => '0');
end generate;
pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
tx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 0
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
in_data => wr_data(31 downto 8),
in_stb => tx_fifo_stb,
in_ack => tx_in_ack,
out_ack => tx_ack,
out_stb => tx_stb,
out_data => tx_data,
dclk => DMA_REQ_TX_ACLK,
dresetn => DMA_REQ_TX_RSTN,
davalid => DMA_REQ_TX_DAVALID,
daready => DMA_REQ_TX_DAREADY,
datype => DMA_REQ_TX_DATYPE,
drvalid => DMA_REQ_TX_DRVALID,
drready => DMA_REQ_TX_DRREADY,
drtype => DMA_REQ_TX_DRTYPE,
drlast => DMA_REQ_TX_DRLAST
);
end generate;
pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
rx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 1
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => rx_fifo_reset,
enable => rx_enable,
in_ack => rx_ack,
in_stb => rx_stb,
in_data => rx_data,
out_data => rx_sample,
out_ack => rx_fifo_ack,
out_stb => rx_out_stb,
dclk => DMA_REQ_RX_ACLK,
dresetn => DMA_REQ_RX_RSTN,
davalid => DMA_REQ_RX_DAVALID,
daready => DMA_REQ_RX_DAREADY,
datype => DMA_REQ_RX_DATYPE,
drvalid => DMA_REQ_RX_DRVALID,
drready => DMA_REQ_RX_DRREADY,
drtype => DMA_REQ_RX_DRTYPE,
drlast => DMA_REQ_RX_DRLAST
);
end generate;
ctrl : entity i2s_controller
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_BCLK_POL => C_BCLK_POL,
C_LRCLK_POL => C_LRCLK_POL,
C_NUM_CH => C_NUM_CH,
C_HAS_TX => C_HAS_TX,
C_HAS_RX => C_HAS_RX
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
data_clk => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
tx_enable => tx_enable,
tx_ack => tx_ack,
tx_stb => tx_stb,
tx_data => tx_data,
rx_enable => rx_enable,
rx_ack => rx_ack,
rx_stb => rx_stb,
rx_data => rx_data,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate
);
tx_fifo_full <= not(tx_in_ack);
tx_fifo_empty <= not(tx_stb);
rx_fifo_full <= not(rx_ack);
rx_fifo_empty <= not(rx_out_stb);
i2s_reset <= I2S_RESET_REG(0);
tx_fifo_reset <= I2S_RESET_REG(1);
rx_fifo_reset <= I2S_RESET_REG(2);
tx_enable <= I2S_CONTROL_REG(0) = '1';
rx_enable <= I2S_CONTROL_REG(1) = '1';
MUTEN_O <= not(I2S_CONTROL_REG(2));
bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
process(rd_addr)
begin
case rd_addr is
when 1 => rd_data <= I2S_CONTROL_REG and x"00000007";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
when 8 => rd_data <= x"0000000" & rx_fifo_full & rx_fifo_empty & tx_fifo_full & tx_fifo_empty;
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
when others => rd_data <= (others => '0');
end case;
end process;
process(s00_axi_aclk) is
begin
if rising_edge(s00_axi_aclk) then
if s00_axi_aresetn = '0' then
I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0');
PERIOD_LEN_REG <= (others => '0');
else
-- Auto-clear the Reset Register bits
I2S_RESET_REG(0) <= '0';
I2S_RESET_REG(1) <= '0';
I2S_RESET_REG(2) <= '0';
if wr_stb = '1' then
case wr_addr is
when 0 => I2S_RESET_REG <= wr_data;
when 1 => I2S_CONTROL_REG <= wr_data;
when 2 => I2S_CLK_CONTROL_REG <= wr_data;
when 6 => PERIOD_LEN_REG <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.i2s_controller;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_streaming_dma_rx_fifo;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl330_dma_fifo;
use adi_common_v1_00_a.axi_ctrlif;
entity axi_i2s_adi_v1_2 is
generic (
-- Users to add parameters here
C_SLOT_WIDTH : integer := 24;
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_DMA_TYPE : integer := 0;
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- Serial Data interface
DATA_CLK_I : in std_logic;
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0);
MUTEN_O : out std_logic;
-- AXI Streaming DMA TX interface
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- AXI Streaming DMA RX interface
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
--PL330 DMA TX interface
DMA_REQ_TX_ACLK : in std_logic;
DMA_REQ_TX_RSTN : in std_logic;
DMA_REQ_TX_DAVALID : in std_logic;
DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_TX_DAREADY : out std_logic;
DMA_REQ_TX_DRVALID : out std_logic;
DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_TX_DRLAST : out std_logic;
DMA_REQ_TX_DRREADY : in std_logic;
-- PL330 DMA RX interface
DMA_REQ_RX_ACLK : in std_logic;
DMA_REQ_RX_RSTN : in std_logic;
DMA_REQ_RX_DAVALID : in std_logic;
DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_RX_DAREADY : out std_logic;
DMA_REQ_RX_DRVALID : out std_logic;
DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_RX_DRLAST : out std_logic;
DMA_REQ_RX_DRREADY : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_i2s_adi_v1_2;
architecture arch_imp of axi_i2s_adi_v1_2 is
-- component declaration
component axi_i2s_adi_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
rd_addr : out integer range 0 to 12 - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_ack : out std_logic;
wr_addr : out integer range 0 to 12 - 1;
wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_stb : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_i2s_adi_S_AXI;
signal i2s_reset : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_enable : Boolean;
signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal tx_ack : std_logic;
signal tx_stb : std_logic;
signal tx_fifo_full : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_in_ack : std_logic;
signal rx_enable : Boolean;
signal rx_fifo_reset : std_logic;
signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal rx_ack : std_logic;
signal rx_stb : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_out_stb : std_logic;
signal bclk_div_rate : natural range 0 to 255;
signal lrclk_div_rate : natural range 0 to 255;
signal period_len : integer range 0 to 65535;
signal I2S_RESET_REG : std_logic_vector(31 downto 0);
signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8))));
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
-- RX FIFO signals
signal audio_fifo_rx : RAM_TYPE;
signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal tvalid : std_logic := '0';
signal rx_tlast : std_logic;
signal drain_tx_dma : std_logic;
signal rx_sample : std_logic_vector(23 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 11;
signal rd_addr : integer range 0 to 11;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
signal tx_fifo_stb : std_logic;
signal rx_fifo_ack : std_logic;
signal cnt : integer range 0 to 2**16-1;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_i2s_adi_S_AXI_inst : axi_i2s_adi_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
wr_addr => wr_addr,
wr_data => wr_data,
wr_stb => wr_stb,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
process (s00_axi_aclk)
begin
if rising_edge(s00_axi_aclk) then
if s00_axi_aresetn = '0' then
cnt <= 0;
else
cnt <= (cnt + 1) mod 2**16;
end if;
end if;
end process;
streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate
tx_fifo : entity axi_streaming_dma_tx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8),
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
out_stb => tx_stb,
out_ack => tx_ack,
out_data => tx_data
);
end generate;
streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
period_len => period_len,
in_stb => rx_stb,
in_ack => rx_ack,
in_data => rx_data,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8),
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
M_AXIS_TDATA(7 downto 0) <= (others => '0');
end generate;
pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
tx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 0
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
in_data => wr_data(31 downto 8),
in_stb => tx_fifo_stb,
in_ack => tx_in_ack,
out_ack => tx_ack,
out_stb => tx_stb,
out_data => tx_data,
dclk => DMA_REQ_TX_ACLK,
dresetn => DMA_REQ_TX_RSTN,
davalid => DMA_REQ_TX_DAVALID,
daready => DMA_REQ_TX_DAREADY,
datype => DMA_REQ_TX_DATYPE,
drvalid => DMA_REQ_TX_DRVALID,
drready => DMA_REQ_TX_DRREADY,
drtype => DMA_REQ_TX_DRTYPE,
drlast => DMA_REQ_TX_DRLAST
);
end generate;
pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
rx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 1
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => rx_fifo_reset,
enable => rx_enable,
in_ack => rx_ack,
in_stb => rx_stb,
in_data => rx_data,
out_data => rx_sample,
out_ack => rx_fifo_ack,
out_stb => rx_out_stb,
dclk => DMA_REQ_RX_ACLK,
dresetn => DMA_REQ_RX_RSTN,
davalid => DMA_REQ_RX_DAVALID,
daready => DMA_REQ_RX_DAREADY,
datype => DMA_REQ_RX_DATYPE,
drvalid => DMA_REQ_RX_DRVALID,
drready => DMA_REQ_RX_DRREADY,
drtype => DMA_REQ_RX_DRTYPE,
drlast => DMA_REQ_RX_DRLAST
);
end generate;
ctrl : entity i2s_controller
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_BCLK_POL => C_BCLK_POL,
C_LRCLK_POL => C_LRCLK_POL,
C_NUM_CH => C_NUM_CH,
C_HAS_TX => C_HAS_TX,
C_HAS_RX => C_HAS_RX
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
data_clk => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
tx_enable => tx_enable,
tx_ack => tx_ack,
tx_stb => tx_stb,
tx_data => tx_data,
rx_enable => rx_enable,
rx_ack => rx_ack,
rx_stb => rx_stb,
rx_data => rx_data,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate
);
tx_fifo_full <= not(tx_in_ack);
tx_fifo_empty <= not(tx_stb);
rx_fifo_full <= not(rx_ack);
rx_fifo_empty <= not(rx_out_stb);
i2s_reset <= I2S_RESET_REG(0);
tx_fifo_reset <= I2S_RESET_REG(1);
rx_fifo_reset <= I2S_RESET_REG(2);
tx_enable <= I2S_CONTROL_REG(0) = '1';
rx_enable <= I2S_CONTROL_REG(1) = '1';
MUTEN_O <= not(I2S_CONTROL_REG(2));
bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
process(rd_addr)
begin
case rd_addr is
when 1 => rd_data <= I2S_CONTROL_REG and x"00000007";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
when 8 => rd_data <= x"0000000" & rx_fifo_full & rx_fifo_empty & tx_fifo_full & tx_fifo_empty;
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
when others => rd_data <= (others => '0');
end case;
end process;
process(s00_axi_aclk) is
begin
if rising_edge(s00_axi_aclk) then
if s00_axi_aresetn = '0' then
I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0');
PERIOD_LEN_REG <= (others => '0');
else
-- Auto-clear the Reset Register bits
I2S_RESET_REG(0) <= '0';
I2S_RESET_REG(1) <= '0';
I2S_RESET_REG(2) <= '0';
if wr_stb = '1' then
case wr_addr is
when 0 => I2S_RESET_REG <= wr_data;
when 1 => I2S_CONTROL_REG <= wr_data;
when 2 => I2S_CLK_CONTROL_REG <= wr_data;
when 6 => PERIOD_LEN_REG <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
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`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity uart_tx is
port(
clk : in vl_logic;
reset : in vl_logic;
tx_start : in vl_logic;
tx_data : in vl_logic_vector(7 downto 0);
tx_busy : out vl_logic;
tx_end : out vl_logic;
tx : out vl_logic
);
end uart_tx;
|
-- $Id: tb_nexys3_core.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_nexys3_core is
port (
I_SWI : out slv8; -- n3 switches
I_BTN : out slv5; -- n3 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys3_core;
architecture sim of tb_nexys3_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1650.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01650ent IS
END c08s13b00x00p03n01i01650ent;
ARCHITECTURE c08s13b00x00p03n01i01650arch OF c08s13b00x00p03n01i01650ent IS
BEGIN
TESTING: PROCESS
-- local variables
variable LOCALI : INTEGER := 47;
variable LOCALR : REAL := 47.0;
variable LOCALB : BOOLEAN := TRUE;
BEGIN
-- Check for proper initialization.
assert (LOCALI = 47);
assert (LOCALR = 47.0);
assert (LOCALB = TRUE);
-- Execute the NULL statement.
null;
-- Verify that nothing has changed as a result.
assert NOT((LOCALI = 47) and
(LOCALR = 47.0) and
(LOCALB = TRUE))
report "***PASSED TEST: c08s13b00x00p03n01i01650"
severity NOTE;
assert ((LOCALI = 47) and
(LOCALR = 47.0) and
(LOCALB = TRUE))
report "***FAILED TEST: c08s13b00x00p03n01i01650 - The execution of the null statement has no effect on any of the local variable within the process."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01650arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1650.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01650ent IS
END c08s13b00x00p03n01i01650ent;
ARCHITECTURE c08s13b00x00p03n01i01650arch OF c08s13b00x00p03n01i01650ent IS
BEGIN
TESTING: PROCESS
-- local variables
variable LOCALI : INTEGER := 47;
variable LOCALR : REAL := 47.0;
variable LOCALB : BOOLEAN := TRUE;
BEGIN
-- Check for proper initialization.
assert (LOCALI = 47);
assert (LOCALR = 47.0);
assert (LOCALB = TRUE);
-- Execute the NULL statement.
null;
-- Verify that nothing has changed as a result.
assert NOT((LOCALI = 47) and
(LOCALR = 47.0) and
(LOCALB = TRUE))
report "***PASSED TEST: c08s13b00x00p03n01i01650"
severity NOTE;
assert ((LOCALI = 47) and
(LOCALR = 47.0) and
(LOCALB = TRUE))
report "***FAILED TEST: c08s13b00x00p03n01i01650 - The execution of the null statement has no effect on any of the local variable within the process."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01650arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1650.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01650ent IS
END c08s13b00x00p03n01i01650ent;
ARCHITECTURE c08s13b00x00p03n01i01650arch OF c08s13b00x00p03n01i01650ent IS
BEGIN
TESTING: PROCESS
-- local variables
variable LOCALI : INTEGER := 47;
variable LOCALR : REAL := 47.0;
variable LOCALB : BOOLEAN := TRUE;
BEGIN
-- Check for proper initialization.
assert (LOCALI = 47);
assert (LOCALR = 47.0);
assert (LOCALB = TRUE);
-- Execute the NULL statement.
null;
-- Verify that nothing has changed as a result.
assert NOT((LOCALI = 47) and
(LOCALR = 47.0) and
(LOCALB = TRUE))
report "***PASSED TEST: c08s13b00x00p03n01i01650"
severity NOTE;
assert ((LOCALI = 47) and
(LOCALR = 47.0) and
(LOCALB = TRUE))
report "***FAILED TEST: c08s13b00x00p03n01i01650 - The execution of the null statement has no effect on any of the local variable within the process."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01650arch;
|
library verilog;
use verilog.vl_types.all;
entity select4_8 is
port(
in1 : in vl_logic_vector(7 downto 0);
in2 : in vl_logic_vector(7 downto 0);
in3 : in vl_logic_vector(7 downto 0);
in4 : in vl_logic_vector(7 downto 0);
choose : in vl_logic_vector(1 downto 0);
\out\ : out vl_logic_vector(7 downto 0)
);
end select4_8;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity FIFO_T is
end FIFO_T;
architecture Beh of FIFO_T is
component FIFO is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0);
EMPTY: out std_logic;
FULL: out std_logic
);
end component;
signal CLK: std_logic := '0';
signal WR: std_logic := '0';
signal DB: std_logic_vector(1 downto 0) := "00";
signal empty: std_logic;
signal full: std_logic;
constant CLK_Period: time := 10 ns;
begin
UFIFO: FIFO port map(
CLK => CLK,
WR => WR,
DB => DB,
empty => empty,
full => full
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
wait for clk_period;
WR <= '0';
DB <= "11";
wait for clk_period;
DB <= "10";
wait for clk_period;
DB <= "01";
wait for clk_period;
WR <= '1';
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait;
end process;
end Beh;
configuration config_L of FIFO_T is
for Beh
for UFIFO : FIFO
use entity work.fifo(Beh);
end for;
end for;
end config_L; |
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic;
--debug signal
frame_size : out std_logic_vector(23 downto 0)
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof
);
-------------------------------------------------------------------
-- BUF_FIFO
-------------------------------------------------------------------
U_BUF_FIFO : entity work.BUF_FIFO
port map
(
CLK => CLK,
RST => RST,
-- HOST PROG
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof,
-- HOST DATA
iram_wren => iram_wren,
iram_wdata => iram_wdata,
fifo_almost_full => iram_fifo_afull,
-- FDCT
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- output IF
outif_almost_full => outif_almost_full,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
huf_ready => huf_ready,
huf_sm_settings => huf_sm_settings,
-- ByteStuffdr
bs_start => bs_start,
bs_ready => bs_ready,
bs_sm_settings => bs_sm_settings,
-- JFIF GEN
jfif_start => jfif_start,
jfif_ready => jfif_ready,
jfif_eoi => jfif_eoi,
-- OUT MUX
out_mux_ctrl => out_mux_ctrl
);
-------------------------------------------------------------------
-- FDCT
-------------------------------------------------------------------
U_FDCT : entity work.FDCT
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => fdct_start,
ready_pb => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- BUF_FIFO
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
-- ZIG ZAG
zz_buf_sel => zz_buf_sel,
zz_rd_addr => zz_rd_addr,
zz_data => zz_data,
zz_rden => zz_rden,
-- HOST
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof
);
-------------------------------------------------------------------
-- ZigZag top level
-------------------------------------------------------------------
U_ZZ_TOP : entity work.ZZ_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
U_RLE_TOP : entity work.RLE_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => rle_start,
ready_pb => rle_ready,
rle_sm_settings => rle_sm_settings,
-- HUFFMAN
huf_buf_sel => huf_buf_sel,
huf_rden => huf_rden,
huf_runlength => huf_runlength,
huf_size => huf_size,
huf_amplitude => huf_amplitude,
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
);
-------------------------------------------------------------------
-- Huffman Encoder
-------------------------------------------------------------------
U_Huffman : entity work.Huffman
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => huf_start,
ready_pb => huf_ready,
huf_sm_settings => huf_sm_settings,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
-- RLE
rle_buf_sel => huf_buf_sel,
rd_en => huf_rden,
runlength => huf_runlength,
VLI_size => huf_size,
VLI => huf_amplitude,
d_val => huf_dval,
rle_fifo_empty => huf_fifo_empty,
-- Byte Stuffer
bs_buf_sel => bs_buf_sel,
bs_fifo_empty => bs_fifo_empty,
bs_rd_req => bs_rd_req,
bs_packed_byte => bs_packed_byte
);
-------------------------------------------------------------------
-- Byte Stuffer
-------------------------------------------------------------------
U_ByteStuffer : entity work.ByteStuffer
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => bs_start,
ready_pb => bs_ready,
-- HOST IF
sof => sof,
num_enc_bytes => num_enc_bytes,
outram_base_addr => outram_base_addr,
-- Huffman
huf_buf_sel => bs_buf_sel,
huf_fifo_empty => bs_fifo_empty,
huf_rd_req => bs_rd_req,
huf_packed_byte => bs_packed_byte,
-- OUT RAM
ram_byte => bs_ram_byte,
ram_wren => bs_ram_wren,
ram_wraddr => bs_ram_wraddr
);
--debug signal
frame_size <= num_enc_bytes;
-------------------------------------------------------------------
-- JFIF Generator
-------------------------------------------------------------------
U_JFIFGen : entity work.JFIFGen
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start => jfif_start,
ready => jfif_ready,
eoi => jfif_eoi,
-- ByteStuffer
num_enc_bytes => num_enc_bytes,
-- HOST IF
qwren => qwren,
qwaddr => qaddr,
qwdata => qdata,
image_size_reg => image_size_reg,
image_size_reg_wr => img_size_wr,
-- OUT RAM
ram_byte => jfif_ram_byte,
ram_wren => jfif_ram_wren,
ram_wraddr => jfif_ram_wraddr
);
image_size_reg <= img_size_x & img_size_y;
-------------------------------------------------------------------
-- OutMux
-------------------------------------------------------------------
U_OutMux : entity work.OutMux
port map
(
CLK => CLK,
RST => RST,
-- CTRL
out_mux_ctrl => out_mux_ctrl,
-- ByteStuffer
bs_ram_byte => bs_ram_byte,
bs_ram_wren => bs_ram_wren,
bs_ram_wraddr => bs_ram_wraddr,
-- ByteStuffer
jfif_ram_byte => jfif_ram_byte,
jfif_ram_wren => jfif_ram_wren,
jfif_ram_wraddr => jfif_ram_wraddr,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr
);
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic;
--debug signal
frame_size : out std_logic_vector(23 downto 0)
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof
);
-------------------------------------------------------------------
-- BUF_FIFO
-------------------------------------------------------------------
U_BUF_FIFO : entity work.BUF_FIFO
port map
(
CLK => CLK,
RST => RST,
-- HOST PROG
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof,
-- HOST DATA
iram_wren => iram_wren,
iram_wdata => iram_wdata,
fifo_almost_full => iram_fifo_afull,
-- FDCT
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- output IF
outif_almost_full => outif_almost_full,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
huf_ready => huf_ready,
huf_sm_settings => huf_sm_settings,
-- ByteStuffdr
bs_start => bs_start,
bs_ready => bs_ready,
bs_sm_settings => bs_sm_settings,
-- JFIF GEN
jfif_start => jfif_start,
jfif_ready => jfif_ready,
jfif_eoi => jfif_eoi,
-- OUT MUX
out_mux_ctrl => out_mux_ctrl
);
-------------------------------------------------------------------
-- FDCT
-------------------------------------------------------------------
U_FDCT : entity work.FDCT
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => fdct_start,
ready_pb => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- BUF_FIFO
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
-- ZIG ZAG
zz_buf_sel => zz_buf_sel,
zz_rd_addr => zz_rd_addr,
zz_data => zz_data,
zz_rden => zz_rden,
-- HOST
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof
);
-------------------------------------------------------------------
-- ZigZag top level
-------------------------------------------------------------------
U_ZZ_TOP : entity work.ZZ_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
U_RLE_TOP : entity work.RLE_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => rle_start,
ready_pb => rle_ready,
rle_sm_settings => rle_sm_settings,
-- HUFFMAN
huf_buf_sel => huf_buf_sel,
huf_rden => huf_rden,
huf_runlength => huf_runlength,
huf_size => huf_size,
huf_amplitude => huf_amplitude,
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
);
-------------------------------------------------------------------
-- Huffman Encoder
-------------------------------------------------------------------
U_Huffman : entity work.Huffman
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => huf_start,
ready_pb => huf_ready,
huf_sm_settings => huf_sm_settings,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
-- RLE
rle_buf_sel => huf_buf_sel,
rd_en => huf_rden,
runlength => huf_runlength,
VLI_size => huf_size,
VLI => huf_amplitude,
d_val => huf_dval,
rle_fifo_empty => huf_fifo_empty,
-- Byte Stuffer
bs_buf_sel => bs_buf_sel,
bs_fifo_empty => bs_fifo_empty,
bs_rd_req => bs_rd_req,
bs_packed_byte => bs_packed_byte
);
-------------------------------------------------------------------
-- Byte Stuffer
-------------------------------------------------------------------
U_ByteStuffer : entity work.ByteStuffer
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => bs_start,
ready_pb => bs_ready,
-- HOST IF
sof => sof,
num_enc_bytes => num_enc_bytes,
outram_base_addr => outram_base_addr,
-- Huffman
huf_buf_sel => bs_buf_sel,
huf_fifo_empty => bs_fifo_empty,
huf_rd_req => bs_rd_req,
huf_packed_byte => bs_packed_byte,
-- OUT RAM
ram_byte => bs_ram_byte,
ram_wren => bs_ram_wren,
ram_wraddr => bs_ram_wraddr
);
--debug signal
frame_size <= num_enc_bytes;
-------------------------------------------------------------------
-- JFIF Generator
-------------------------------------------------------------------
U_JFIFGen : entity work.JFIFGen
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start => jfif_start,
ready => jfif_ready,
eoi => jfif_eoi,
-- ByteStuffer
num_enc_bytes => num_enc_bytes,
-- HOST IF
qwren => qwren,
qwaddr => qaddr,
qwdata => qdata,
image_size_reg => image_size_reg,
image_size_reg_wr => img_size_wr,
-- OUT RAM
ram_byte => jfif_ram_byte,
ram_wren => jfif_ram_wren,
ram_wraddr => jfif_ram_wraddr
);
image_size_reg <= img_size_x & img_size_y;
-------------------------------------------------------------------
-- OutMux
-------------------------------------------------------------------
U_OutMux : entity work.OutMux
port map
(
CLK => CLK,
RST => RST,
-- CTRL
out_mux_ctrl => out_mux_ctrl,
-- ByteStuffer
bs_ram_byte => bs_ram_byte,
bs_ram_wren => bs_ram_wren,
bs_ram_wraddr => bs_ram_wraddr,
-- ByteStuffer
jfif_ram_byte => jfif_ram_byte,
jfif_ram_wren => jfif_ram_wren,
jfif_ram_wraddr => jfif_ram_wraddr,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr
);
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic;
--debug signal
frame_size : out std_logic_vector(23 downto 0)
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof
);
-------------------------------------------------------------------
-- BUF_FIFO
-------------------------------------------------------------------
U_BUF_FIFO : entity work.BUF_FIFO
port map
(
CLK => CLK,
RST => RST,
-- HOST PROG
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof,
-- HOST DATA
iram_wren => iram_wren,
iram_wdata => iram_wdata,
fifo_almost_full => iram_fifo_afull,
-- FDCT
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- output IF
outif_almost_full => outif_almost_full,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
huf_ready => huf_ready,
huf_sm_settings => huf_sm_settings,
-- ByteStuffdr
bs_start => bs_start,
bs_ready => bs_ready,
bs_sm_settings => bs_sm_settings,
-- JFIF GEN
jfif_start => jfif_start,
jfif_ready => jfif_ready,
jfif_eoi => jfif_eoi,
-- OUT MUX
out_mux_ctrl => out_mux_ctrl
);
-------------------------------------------------------------------
-- FDCT
-------------------------------------------------------------------
U_FDCT : entity work.FDCT
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => fdct_start,
ready_pb => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- BUF_FIFO
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
-- ZIG ZAG
zz_buf_sel => zz_buf_sel,
zz_rd_addr => zz_rd_addr,
zz_data => zz_data,
zz_rden => zz_rden,
-- HOST
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof
);
-------------------------------------------------------------------
-- ZigZag top level
-------------------------------------------------------------------
U_ZZ_TOP : entity work.ZZ_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
U_RLE_TOP : entity work.RLE_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => rle_start,
ready_pb => rle_ready,
rle_sm_settings => rle_sm_settings,
-- HUFFMAN
huf_buf_sel => huf_buf_sel,
huf_rden => huf_rden,
huf_runlength => huf_runlength,
huf_size => huf_size,
huf_amplitude => huf_amplitude,
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
);
-------------------------------------------------------------------
-- Huffman Encoder
-------------------------------------------------------------------
U_Huffman : entity work.Huffman
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => huf_start,
ready_pb => huf_ready,
huf_sm_settings => huf_sm_settings,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
-- RLE
rle_buf_sel => huf_buf_sel,
rd_en => huf_rden,
runlength => huf_runlength,
VLI_size => huf_size,
VLI => huf_amplitude,
d_val => huf_dval,
rle_fifo_empty => huf_fifo_empty,
-- Byte Stuffer
bs_buf_sel => bs_buf_sel,
bs_fifo_empty => bs_fifo_empty,
bs_rd_req => bs_rd_req,
bs_packed_byte => bs_packed_byte
);
-------------------------------------------------------------------
-- Byte Stuffer
-------------------------------------------------------------------
U_ByteStuffer : entity work.ByteStuffer
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => bs_start,
ready_pb => bs_ready,
-- HOST IF
sof => sof,
num_enc_bytes => num_enc_bytes,
outram_base_addr => outram_base_addr,
-- Huffman
huf_buf_sel => bs_buf_sel,
huf_fifo_empty => bs_fifo_empty,
huf_rd_req => bs_rd_req,
huf_packed_byte => bs_packed_byte,
-- OUT RAM
ram_byte => bs_ram_byte,
ram_wren => bs_ram_wren,
ram_wraddr => bs_ram_wraddr
);
--debug signal
frame_size <= num_enc_bytes;
-------------------------------------------------------------------
-- JFIF Generator
-------------------------------------------------------------------
U_JFIFGen : entity work.JFIFGen
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start => jfif_start,
ready => jfif_ready,
eoi => jfif_eoi,
-- ByteStuffer
num_enc_bytes => num_enc_bytes,
-- HOST IF
qwren => qwren,
qwaddr => qaddr,
qwdata => qdata,
image_size_reg => image_size_reg,
image_size_reg_wr => img_size_wr,
-- OUT RAM
ram_byte => jfif_ram_byte,
ram_wren => jfif_ram_wren,
ram_wraddr => jfif_ram_wraddr
);
image_size_reg <= img_size_x & img_size_y;
-------------------------------------------------------------------
-- OutMux
-------------------------------------------------------------------
U_OutMux : entity work.OutMux
port map
(
CLK => CLK,
RST => RST,
-- CTRL
out_mux_ctrl => out_mux_ctrl,
-- ByteStuffer
bs_ram_byte => bs_ram_byte,
bs_ram_wren => bs_ram_wren,
bs_ram_wraddr => bs_ram_wraddr,
-- ByteStuffer
jfif_ram_byte => jfif_ram_byte,
jfif_ram_wren => jfif_ram_wren,
jfif_ram_wraddr => jfif_ram_wraddr,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr
);
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memInst2 is
generic (
wlength: integer := 32;
words : integer := 10
);
Port(
data: IN std_logic_vector(wlength-1 downto 0);
address: IN std_logic_vector(words-1 downto 0);
clock, wren: IN std_logic;
q: OUT std_logic_vector(wlength-1 downto 0)
);
end memInst2;
ARCHITECTURE rlt OF memInst2 is
type memory_type is array (2**words-1 downto 0) of std_logic_vector(wlength -1 downto 0);
signal memory: memory_type;
begin
gen_init_mem: for i in 11 to 1023 generate
memory(i) <= "00000000000000000000000000000000";
end generate gen_init_mem;
memory(0) <= "00100000000000100000000000000011";
memory(1) <= "00100000000000110000000000000100";
memory(2) <= "00100000000001000000000000000101";
memory(3) <= "00100000011000110000000000000100";
memory(4) <= "00100000000001100000000000000111";
memory(5) <= "10101100000000100000000000000100";
memory(6) <= "10001100000001110000000000000100";
memory(7) <= "00000000000001111000100000100000";
memory(8) <= "00000000000001111001000000100000";
memory(9) <= "00000000000001111001100000100000";
memory(10) <= "00010000000000000000000000000010";
process (clock, memory, address, wren)
begin
-- if clock'event and clock ='1' then
-- if wren = '1' then
-- memory(to_integer(unsigned(address))) <= data;
-- end if;
-- end if;
q <= memory(to_integer(unsigned(address))) after 1ns;
end process;
end rlt; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FiRoCtrlE is
generic (
EXTRACT : boolean := true
);
port (
--+ system if
Clk_i : in std_logic;
Reset_i : in std_logic;
--+ ctrl/status
Start_i : in std_logic;
Wait_i : in std_logic_vector(7 downto 0);
Run_i : in std_logic_vector(7 downto 0);
--+ rnd data
DataValid_o : out std_logic;
Data_o : out std_logic_vector(7 downto 0);
-- firo
Run_o : out std_logic;
Data_i : in std_logic
);
end entity FiRoCtrlE;
architecture rtl of FiRoCtrlE is
signal s_firo_run : std_logic;
signal s_firo_valid : std_logic;
type t_neumann_state is (BIT1, BIT2, BIT3, BIT4);
signal s_neumann_state : t_neumann_state;
signal s_neumann_buffer : std_logic_vector(2 downto 0);
type t_register_state is (SLEEP, COLLECT);
signal s_register_state : t_register_state;
signal s_register_enable : std_logic;
signal s_register_din : std_logic_vector(1 downto 0);
signal s_register_data : std_logic_vector(8 downto 0);
signal s_register_counter : unsigned(2 downto 0);
signal s_register_length : natural range 1 to 2;
signal s_data : std_logic_vector(3 downto 0);
begin
Run_o <= s_run when s_register_state = COLLECT else '0';
s_data <= s_neumann_buffer & Data_i;
ControllerP : process (Clk_i) is
variable v_wait_cnt : unsigned(7 downto 0);
variable v_run_cnt : unsigned(7 downto 0);
begin
if (rising_edge(Clk_i)) then
if (s_register_state = SLEEP) then
v_wait_cnt := unsigned(Wait_i);
v_run_cnt := unsigned(Run_i);
s_firo_run <= '0';
s_firo_valid <= '0';
else
s_firo_valid <= '0';
if (v_wait_cnt = 0) then
s_firo_run <= '1';
else
v_wait_cnt := v_wait_cnt - 1;
end if;
if (v_run_cnt = 0) then
s_firo_run <= '0';
elsif (v_run_cnt = 1) then
s_firo_valid <= '1';
else
if (v_wait_cnt = 0) then
v_run_cnt := v_run_cnt - 1;
end if;
end if;
end if;
end if;
end process ControllerP;
extractor : if EXTRACT generate
VonNeumannP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Reset_i = '0') then
s_neumann_state <= BIT1;
else
case s_neumann_state is
when BIT1 =>
s_register_enable <= '0';
if (s_firo_valid = '1') then
s_neumann_buffer(2) <= Data_i;
s_neumann_state <= BIT2;
end if;
when BIT2 =>
if (s_firo_valid = '1') then
s_neumann_buffer(1) <= Data_i;
s_neumann_state <= BIT3;
end if;
when BIT3 =>
if (s_firo_valid = '1') then
s_neumann_buffer(0) <= Data_i;
s_neumann_state <= BIT4;
end if;
when BIT4 =>
if (s_firo_valid = '1') then
s_register_enable <= '1';
s_register_length <= 1;
s_register_din <= "00";
s_neumann_state <= BIT1;
case (s_data) is
when x"5" =>
s_register_din <= "01";
when x"1" | x"6" | x"7" =>
s_register_length <= 2;
when x"2" | x"9" | x"b" =>
s_register_din <= "01";
s_register_length <= 2;
when x"4" | x"a" | x"d" =>
s_register_din <= "10";
s_register_length <= 2;
when x"8" | x"c" | x"e" =>
s_register_din <= "11";
s_register_length <= 2;
when x"0" | x"f" =>
s_register_enable <= '0';
when others => -- incl. x"3"
null;
end case;
end if;
when others =>
null;
end case;
end if;
end if;
end process VonNeumannP;
end generate;
no_extractor : if not(EXTRACT) generate
s_register_enable <= s_firo_valid;
s_register_din(0) <= Data_i;
s_register_length <= 1;
end generate;
Data_o <= s_register_data(7 downto 0);
ShiftRegisterP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Reset_i = '0') then
s_register_counter <= (others => '1');
s_register_state <= SLEEP;
DataValid_o <= '0';
else
case s_register_state is
when SLEEP =>
DataValid_o <= '0';
if (Start_i = '1' and Run_i /= x"00") then
s_register_state <= COLLECT;
s_register_data(0) <= s_register_data(8);
end if;
when COLLECT =>
if (s_register_enable = '1') then
if (s_register_counter = 0) then
s_register_data <= s_register_din(1) & s_register_data(6 downto 0) & s_register_din(0);
DataValid_o <= '1';
s_register_state <= SLEEP;
elsif (s_register_counter = 1) then
if (s_register_length = 1) then
s_register_data(7 downto 0) <= s_register_data(6 downto 0) & s_register_din(0);
end if;
if (s_register_length = 2) then
s_register_data(7 downto 0) <= s_register_data(5 downto 0) & s_register_din;
DataValid_o <= '1';
s_register_state <= SLEEP;
end if;
else
if (s_register_length = 1) then
s_register_data(7 downto 0) <= s_register_data(6 downto 0) & s_register_din(0);
else
s_register_data(7 downto 0) <= s_register_data(5 downto 0) & s_register_din;
end if;
end if;
s_register_counter <= s_register_counter - s_register_length;
end if;
when others =>
null;
end case;
end if;
end if;
end process ShiftRegisterP;
end architecture rtl;
|
entity tb_asgn07 is
end tb_asgn07;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn07 is
signal s0 : std_logic;
signal clk : std_logic;
signal r : std_logic_vector (65 downto 0);
begin
dut: entity work.asgn07
port map (clk => clk, s0 => s0, r => r);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
s0 <= '0';
pulse;
assert r (0) = '0' severity failure;
assert r (65) = '0' severity failure;
s0 <= '1';
pulse;
assert r (0) = '1' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
assert r (65) = '1' severity failure;
s0 <= '0';
pulse;
assert r (0) = '0' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cc7c" severity failure;
assert r (65) = '0' severity failure;
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
--Top module for Headstage SerDes FPGA
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port(
clk_in : in std_logic; --input clock form oscillator
reset : in std_logic; --master system reset
pclk : out std_logic; --PCLK on the FPD chip
dout : out std_logic_vector(11 downto 0); --din on the serializer side of the FPD chip.
--LVDS outputs goes to the intan chips
cs_p : out std_logic;
cs_n : out std_logic;
sclk_p : out std_logic;
sclk_n : out std_logic;
mosi_p : out std_logic;
mosi_n : out std_logic;
--LVDS inputs for driving two 64 channel intan chips
miso_chip1_p : in std_logic;
miso_chip1_n : in std_logic;
miso_chip2_p : in std_logic;
miso_chip2_n : in std_logic;
--VS, HSYNC output - this is named as vsync and hsync just for consistency with the PCB layout
vsync_o : out std_logic; --signal one data block
hsync_o : out std_logic; --signals at only channel 0 for OE synchronization
--POT SPI interface use to config digital POT for LED driver
cs_pot_o : out std_logic; --LEDSPI2 --N5
sclk_pot_o : out std_logic; --LEDSPI0 --N4
din_pot_o :out std_logic; --LEDSPI1 --P5
--LED enable input signals
LED_GPO_0 : in std_logic;
--LED SPI interface
led_clk_o : out std_logic; --LED2
led_data_o : out std_logic; --LED0
led_latch_o : out std_logic; --LED1
--LED active output signals
LED0_active : out std_logic;
LED1_active : out std_logic
);
end top;
architecture Behavioral of top is
signal clk84M, clk42M, clk21M, clk2M, clk50M, clk10M, clk5M, clk1M, clk50K, clk500K, clk_spi, clk_pot_spi, clktest, clk2Hz, clk4Hz: std_logic;
signal count_bit : unsigned(11 downto 0);
signal cs, sclk, mosi, spi_start, data_lclk, mosi_dl : std_logic;
signal miso_chip1, miso_chip2 : std_logic;
signal miso_reg : std_logic_vector(15 downto 0);
signal command, command_dl, pot_command, led_command: std_logic_vector(15 downto 0);
signal pot_state, pot_config_enb: std_logic;
signal cs_pot, sclk_pot, din_pot : std_logic;
signal led_clk, led_data, led_latch : std_logic;
signal data_rdy_pcie : std_logic;
signal data_pcie_A, data_pcie_B, data_pcie_C, data_pcie_D : std_logic_vector(15 downto 0);
signal hsync, vsync : std_logic;
--clock divider
component clk_div is
generic (MAXD: natural:=5);
port(
clk: in std_logic;
reset: in std_logic;
div: in integer range 0 to MAXD;
div_clk: out std_logic
);
end component;
--main state machine
component main_sm
port(
clk_spi : IN std_logic;
reset : IN std_logic;
miso_reg : IN std_logic_vector(15 downto 0);
data_lclkin : IN std_logic;
spi_start_o : OUT std_logic;
command_o : OUT std_logic_vector(15 downto 0);
hsync_o : out std_logic
);
end component;
--SPI data merger unit
component data_merge is
port(
pclk : in std_logic;
reset : in std_logic;
data_rdy_pcie : in std_logic; --this is generated from the SPI interface. Here we must sample this line using 50MHz clock
vsync_o : out std_logic;
stream1 : in std_logic_vector(15 downto 0);
stream2 : in std_logic_vector(15 downto 0);
stream3 : in std_logic_vector(15 downto 0);
stream4 : in std_logic_vector(15 downto 0);
dout_o : out std_logic_vector(7 downto 0)
);
end component;
--"SPI" interface for the LED driver chip
component SPI_LEDdriver
port(
clk_spi : IN std_logic;
reset : IN std_logic;
write_start : IN std_logic;
command_in : IN std_logic_vector(15 downto 0);
led_clk_o : OUT std_logic;
led_data_o : OUT std_logic;
led_latch_o : OUT std_logic
);
end component;
--84MHz clock module
component pll
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
--SPI module
component SPI_module is
port(
clk_spi : in std_logic; --spi clock from toplevel
reset : in std_logic; --reset
spi_start : in std_logic; --spi initiate
command_in : in std_logic_vector(15 downto 0); --parallel command input vector
--SPI inputs
miso_i : in std_logic;
--SPI outputs
cs_o : out std_logic;
sclk_o : out std_logic; --sclk is always 2x slower than clk_spi
mosi_o : out std_logic;
--data latch clock
data_lclk_o : out std_logic;
data_rdy_pcie_o : out std_logic;
data_pcie_A_o : out std_logic_vector(15 downto 0);
data_pcie_B_o : out std_logic_vector(15 downto 0);
miso_reg_A_o : out std_logic_vector(15 downto 0);
miso_reg_B_o : out std_logic_vector(15 downto 0)
);
end component;
begin
--internal signal mapped to pins
pclk <= clk42M;
cs_pot_o <= cs_pot;
sclk_pot_o <= sclk_pot;
din_pot_o <= din_pot;
--debug signals sent through last 4 LSB of dout
dout(1) <= '0';
dout(3) <= sclk;
dout(2) <= miso_chip1;
dout(0) <= hsync;
--h vsync
hsync_o <= hsync;
vsync_o <= vsync;
--led control
led_clk_o <= led_clk;
led_data_o <= led_data;
led_latch_o <= led_latch;
--clock selection
clk_spi <= clk42M; --clk42M;
clk_pot_spi <= clk500K; --for the digital pot
--LVDS mapping ==============================================================
--outputs
lvds_mosi_map : OBUFDS generic map(IOSTANDARD => "LVDS_33") port map(O => mosi_p, OB => mosi_n, I => mosi);
lvds_sclk_map : OBUFDS generic map(IOSTANDARD => "LVDS_33") port map(O => sclk_p, OB => sclk_n, I => sclk);
lvds_cs_map : OBUFDS generic map(IOSTANDARD => "LVDS_33") port map(O => cs_p, OB => cs_n, I => cs);
--inputs
lvds_miso_chip1_map : IBUFGDS generic map (DIFF_TERM => FALSE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "LVDS_33") port map (O => miso_chip1, I => miso_chip1_p, IB => miso_chip1_n);
lvds_miso_chip2_map : IBUFGDS generic map (DIFF_TERM => FALSE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "LVDS_33") port map (O => miso_chip2, I => miso_chip2_p, IB => miso_chip2_n);
--clock dividers
-----------------------------------------------------------------------------
clk_div_84M: pll --from 100MHz to 84MHz
port map(CLK_IN1=>clk_in, reset=>reset,CLK_OUT1=>clk84M, LOCKED=>open);
clk_div_42M: clk_div generic map(MAXD=>2) --from 84MHz to 42MHz
port map(clk=>clk84M, reset=>reset,div=>2, div_clk=>clk42M);
clk_div_50M: clk_div generic map(MAXD=>2) --from 100MHz to 50MHz
port map(clk=>clk84M, reset=>reset,div=>2, div_clk=>clk50M);
clk_div_10M: clk_div generic map(MAXD=>5) --from 50MHz to 10MHz
port map(clk=>clk50M, reset=>reset,div=>5, div_clk=>clk10M);
clk_div_5M: clk_div generic map(MAXD=>2) --from 10MHz to 5MHz
port map(clk=>clk10M, reset=>reset,div=>2, div_clk=>clk5M);
clk_div_1M: clk_div generic map(MAXD=>5) --from 5MHz to 1MHz
port map(clk=>clk5M, reset=>reset,div=>5, div_clk=>clk1M); --not a 50% duty cycle clock
clk_div_500K: clk_div generic map(MAXD=>2) --from 1MHz to 500KHz
port map(clk=>clk1M, reset=>reset,div=>2, div_clk=>clk500K); --not a 50% duty cycle clock
clk_div_debug_only: clk_div generic map(MAXD=>40) --from 5MHz to 1MHz
port map(clk=>clk500K, reset=>reset,div=>40, div_clk=>clktest); --not a 50% duty cycle clock
-----------------------------------------------------------------------------
--map LED active to clk2Hz
LED0_active <= LED_GPO_0;
LED1_active <= LED_GPO_0;
mini_cnt_proc: process(spi_start, reset)
begin
if (reset = '1') then
count_bit <= (others=>'0');
elsif (falling_edge(spi_start)) then
count_bit <= count_bit + 1;
end if;
end process;
--generate command
--command <= "11" & std_logic_vector(to_unsigned(41,6)) & "00000000"; --read from 40 to 44 registers
--configuration sequence
-- 7654 3210
--R0 0x80DE "1101 1110"
--R1 0x8102 "0000 0010" -ADC buffer bias, 2 for >700 KS/s sampling rate.
--R2 0x8204 "0000 0100" -MUX bias 4 for >700 KS/s sampling rate
--R3 0x8302 "0000 0010" -digital out HiZ
--R4 0x845F "0101 1111" -MISO pull to highZ when CS is pulled high. twocomp. no absmode, DSP offset remove, k_freq = 0.000004857Hz
--R5 0x8500 "0000 0000" -disable impedance check
--R6 0x8600 "0000 0000" -disable impedance check DAC
--R7 0x8700 "0000 0000" -disable impedance check amplifier
--R8 0x8811 "0001 0001" -RH1 DAC1: 17 upper cutoff 10KHz
--R9 0x8980 "1000 0000" -RH1 DAC2: 0
--R10 0x8A10 "0001 0000" -RH2 DAC1: 16
--R11 0x8B80 "1000 0000" -RH2 DAC2: 0
--R12 0x8C10 "0001 0000" -RL DAC1
--R13 0x8DDC "1101 1100" -RL DAC2:28 DAC3:1 cutoff: 0.1HZ??????????????????????? confirm
--R14 0x8EFF "1111 1111"
--R15 0x8FFF "1111 1111"
--R16 0x90FF "1111 1111"
--R17 0x91FF "1111 1111"
--main statemachine
--this state machine generates command and puts those commands into the SPI module to serialize to the headstage
mainstatement: main_sm PORT MAP (
clk_spi => clk_spi,
reset => reset,
miso_reg => miso_reg,
data_lclkin => data_lclk,
spi_start_o => spi_start,
command_o => command,
hsync_o => hsync
);
--SPI data merger unit
merge: data_merge port map (
pclk => clk42M, --this gets 50MHz, should be the same as pclk frequency
reset => reset,
data_rdy_pcie => data_rdy_pcie, --this is generated from the SPI interface. Here we must sample this line using 50MHz clock
vsync_o => vsync, --link this directly to vsync_o output
stream1 => data_pcie_A,
stream2 => data_pcie_B,
stream3 => data_pcie_C,
stream4 => data_pcie_D,
dout_o => dout(11 downto 4) ---debug
);
--SPI module------------------------------------------------------
SPI_intan_chip1: SPI_module
port map(
clk_spi => clk_spi,
reset => reset,
spi_start => spi_start,
command_in => command, --read from 40 to 44 registers
--SPI inputs
miso_i => miso_chip1,
--SPI outputs
cs_o => cs,
sclk_o => sclk, --sclk is always 2x slower than clk_spi
mosi_o => mosi,
--data latch clock
data_lclk_o => data_lclk,
data_rdy_pcie_o => data_rdy_pcie,
data_pcie_A_o => data_pcie_A,
data_pcie_B_o => data_pcie_B,
miso_reg_A_o => miso_reg,
miso_reg_B_o => open
);
--SPI module------------------------------------------------------
SPI_intan_chip2: SPI_module
port map(
clk_spi => clk_spi,
reset => reset,
spi_start => spi_start,
command_in => command, --read from 40 to 44 registers
--SPI inputs
miso_i => miso_chip2,
--SPI outputs
cs_o => open,
sclk_o => open, --sclk is always 2x slower than clk_spi
mosi_o => open,
--data latch clock
data_lclk_o => open,
data_rdy_pcie_o => open,
data_pcie_A_o => data_pcie_C,
data_pcie_B_o => data_pcie_D,
miso_reg_A_o => open,
miso_reg_B_o => open
);
--LED development-------------------------------------------------------------
--generate the one shot for configuration
on_shot_pot: process(clk_pot_spi, reset)
begin
if (reset = '1') then
pot_state <= '0';
pot_config_enb <= '0';
elsif (rising_edge(clk_pot_spi)) then
if pot_state = '0' then
pot_state <= '1';
pot_config_enb <= '1';
else
pot_state <= '1';
pot_config_enb <= '0';
end if;
end if;
end process;
--pot command: write wiper information to register A and B.
--[C1 C0]="00"
--[A1 A0]="11"
pot_command <= "00" & "00" & "00" & "11" & "11011010"; --10K Ohm
--variable resistor (POT) SPI module--------------------------------------------------
SPI_imu: SPI_module
port map(
clk_spi => clk_pot_spi, --keep the frequency aroudn 1MHz or even slower
reset => reset,
spi_start => clktest, --generate a 1-shot configuration (get this from the main state_machine?)
command_in => pot_command, --read from 40 to 44 registers
--SPI inputs
miso_i => '0', --ground the miso for the pot because there is no output
--SPI outputs
cs_o => cs_pot,
sclk_o => sclk_pot, --sclk is always 2x slower than clk_spi
mosi_o => din_pot,
--data latch clock
data_lclk_o => open,
data_rdy_pcie_o => open,
data_pcie_A_o => open,
data_pcie_B_o => open,
miso_reg_A_o => open,
miso_reg_B_o => open
);
--LED configuration command
--led_command <= "1111111111111111"; --all on
led_command <= "0000000000000011";
-- Instantiate the Unit Under Test (UUT)
leddirver: SPI_LEDdriver PORT MAP (
clk_spi => clk_pot_spi,
reset => reset,
write_start => clktest,
command_in => led_command,
led_clk_o => led_clk,
led_data_o => led_data,
led_latch_o => led_latch
);
end Behavioral;
|
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
datain : in std_logic_vector;
dataout : out std_logic_vector
);
end entity sync_ram;
architecture rtl of sync_ram is
type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
signal ram : ram_type;
signal read_address : std_logic_vector(address'range);
begin
ramproc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process ramproc;
dataout <= ram(to_integer(unsigned(read_address)));
end architecture rtl;
|
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
datain : in std_logic_vector;
dataout : out std_logic_vector
);
end entity sync_ram;
architecture rtl of sync_ram is
type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
signal ram : ram_type;
signal read_address : std_logic_vector(address'range);
begin
ramproc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process ramproc;
dataout <= ram(to_integer(unsigned(read_address)));
end architecture rtl;
|
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
datain : in std_logic_vector;
dataout : out std_logic_vector
);
end entity sync_ram;
architecture rtl of sync_ram is
type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
signal ram : ram_type;
signal read_address : std_logic_vector(address'range);
begin
ramproc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process ramproc;
dataout <= ram(to_integer(unsigned(read_address)));
end architecture rtl;
|
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
datain : in std_logic_vector;
dataout : out std_logic_vector
);
end entity sync_ram;
architecture rtl of sync_ram is
type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
signal ram : ram_type;
signal read_address : std_logic_vector(address'range);
begin
ramproc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process ramproc;
dataout <= ram(to_integer(unsigned(read_address)));
end architecture rtl;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2020 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file WatchEvents.vhd when simulating
-- the core, WatchEvents. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY WatchEvents IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END WatchEvents;
ARCHITECTURE WatchEvents_a OF WatchEvents IS
-- synthesis translate_off
COMPONENT wrapped_WatchEvents
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 13,
c_default_value => "BlankString",
c_din_width => 72,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 72,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 0,
c_has_slave_ce => 0,
c_has_srst => 1,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "4kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 4095,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 4094,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 13,
c_rd_depth => 4096,
c_rd_freq => 1,
c_rd_pntr_width => 12,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 13,
c_wr_depth => 4096,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 12,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_WatchEvents
PORT MAP (
clk => clk,
srst => srst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END WatchEvents_a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end entity wbmux2;
architecture behave of wbmux2 is
signal select_zero: std_logic;
begin
select_zero<='1' when m_wbi.adr(select_line)='0' else '0';
s0_wbo.dat <= m_wbi.dat;
s0_wbo.adr <= m_wbi.adr;
s0_wbo.stb <= m_wbi.stb;
s0_wbo.we <= m_wbi.we;
s0_wbo.sel <= m_wbi.sel;
s0_wbo.tag <= m_wbi.tag;
s0_wbo.cti <= m_wbi.cti;
s0_wbo.bte <= m_wbi.bte;
s1_wbo.dat <= m_wbi.dat;
s1_wbo.adr <= m_wbi.adr;
s1_wbo.stb <= m_wbi.stb;
s1_wbo.we <= m_wbi.we;
s1_wbo.sel <= m_wbi.sel;
s1_wbo.tag <= m_wbi.tag;
s1_wbo.cti <= m_wbi.cti;
s1_wbo.bte <= m_wbi.bte;
process(m_wbi.cyc,select_zero)
begin
if m_wbi.cyc='0' then
s0_wbo.cyc<='0';
s1_wbo.cyc<='0';
else
s0_wbo.cyc<=select_zero;
s1_wbo.cyc<=not select_zero;
end if;
end process;
process(select_zero,s1_wbi.stall,s0_wbi.stall)
begin
if select_zero='0' then
m_wbo.stall<=s1_wbi.stall;
else
m_wbo.stall<=s0_wbi.stall;
end if;
end process;
-- Process responses from both slaves.
-- USE ONLY IN SIMULATION FOR NOW!!!!!
process(s0_wbi,s1_wbi)
variable sel: std_logic_vector(1 downto 0);
begin
sel := s1_wbi.ack & s0_wbi.ack;
case sel is
when "00" =>
m_wbo.ack<='0';
m_wbo.err<='0';
m_wbo.dat<=(others => 'X');
m_wbo.tag<=(others => 'X');
when "01" =>
m_wbo.ack<='1';
m_wbo.err<=s0_wbi.err;
m_wbo.dat<=s0_wbi.dat;
m_wbo.tag<=s0_wbi.tag;
when "10" =>
m_wbo.ack<='1';
m_wbo.dat<=s1_wbi.dat;
m_wbo.err<=s1_wbi.err;
m_wbo.tag<=s1_wbi.tag;
when others =>
m_wbo.ack<='1';
m_wbo.err<='1';
m_wbo.dat<=(others => 'X');
m_wbo.tag<=(others => 'X');
end case;
end process;
end behave;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
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