ALU

The ALU performs all arithmetic and logical functions on the data that the CPU is processing.

# Operations

The operations provided by the ALU in this design are:

Two Operands

* ADDition
* ADD with carry in
* SUBtraction
* SUB with borrow in
* MULtiply (has two cells output)
* AND bits
* OR bits
* XOR bits
* MAX returns higher input

One Operand

* INCrement
* DECrement
* NEGation (2's complement) - done by proper setup of the adder
* INVersion
* Logical Shift Left (same as Arithmetic Shift Left)
* Logical Shift Right
* Arithmetic Shift Right (preserves the sign bit in 2's complement)
* X^2 (has two cells output, much faster than MUL)

Zero Operand

* NOOP (output '0') no

Additional Instructions

* Clear Carry (Is a set carry useful???)
* Read CCR
* Write CCR ??? (Can this replace Clear Carry???)

## Addition

Addition is the core hardware module of the ALU. See the article on the  adder module. This ALU builds upon the final design as shown there.

## Subtraction

In order to perform subtraction, we need to define how negative numbers are represented. This design supports "2's complement" number representation in accord with the vast majority of systems. Subtraction then is performed simply:

1. NEGate the subtrahend (the 3nd number)
	1. INVert the subtrahend (the 2nd number)
	2. Add '1' to it (or the other operand, or the result). It is now the negative of the subtrahend, in 2's complement form.
2. Add it to the minuend (the 1st number)

A 'pre-processing' stage is included (on each input) to provide for these functions. This prep stage will invert the subtrahend. The carry-in signal to the adder is enabled by the control signal and this provides the +1 for the conversion.

## Multiplication and Division

Hardware multiply and divide are very complex and will not be included in this design. However, other functions are included to support multiply and divide in software. This design uses 2's complement representation and will ignore any part of a result less than '1' (to the right of the decimal point).

Software multiply and divide consist of repeatedly shifting the (partial) results left (multiply) or right (divide) and at the proper times, adding (multiply) or subtracting (divide) '1'.

## INC DEC and NEG

These are performed by the adder using the pre-processing stages for the inputs. Instead of passing NOS through to the adder the proper constant (+1 or -1) is presented to input B. This just allows for a faster increment and decrement over manually loading the constant into NOS and doing a standard ADD. For NEG, the pre-processing stage on input A (TOS) inverts the input and the +1 is performed on the result.

## Logical Operators

The 2-Operand logical function are performed on a bitwise basis between the two operators.

The 1-operand logic functions are all performed in a single block in parallel with the adder module. It has a function select input and its output may be enabled by the function code and an output buffer not needed.

The shift operations will shift in the carry bit (C) from the condition code register. This facilitates multiple cell shifts which are necessary for various functions including multiple and divide. If this bit is NOT to be included, it should be forced clear first. Additional instructions are included to provide this function.

## Condition Codes

Several system level bits are generated by the ALU in response to the result of its operations. These bits are

* C (carry out)
* V (2's complement overflow)
* N (the result is negative)
* Z (the result is zero)

All these bits are activated (set or cleared accordingly) by an ADD or SUB operations. Logical operations activate the CC bits as follows:

* The C bit is only activated by shift operations. If a '1' is shifted out of either end, this is set.
* The V bit is cleared since it is only used for 2's complement operations.
* The Z and N bits are set according to the result of the operation.

# Components

Each component takes the same single control input (ALU\_Control) and decodes it according to the function required. The various outputs of the modules are tied together in this "wired-OR" environment. When the function code does not call for a particular module, it will output a '0'.

## Adder

The core component of the ALU is the  adder module which does the arithmetic operations. The operands to the ALU in this design are the two top items on the data stack (TOS and NOS). Input A (TOS) has a pre-processing stage before being fed to the adder. This performs the INVert used to calculate subtraction. Input B (NOS) also has a pre-processing stage which may be used to force a '0' or another fixed number to the adder. The carry input to the adder may be forced to '1' by the instruction code.

## 2 Operand Logic Block

A set of logic modules for the two-operand boolean functions is the second main component. Each logic function requires a unique module and they all operate in parallel. Each function module has its own output enable which is controlled by the ALU\_Control signal.

The modules consist of a single M.Bank which performs the function and another to provide the output enable.

## 1 Operand Logic Block

The 1 operand functions are supported by a third component in the ALU. The invert function requires only a single M.Bank which is programmed with the function and acts as the output enable at the same time. The shift functions operate on the entire 16 bit cell so they are cascaded stages similar to the adder module. Three modules are included to provide the three shift functions. Each function module includes an output enable stage to provide the output enable.

The two right shifts are electrically identical. The difference is that for the arithmetic shift the highest Shift block is programmed to preserve the sign bit. Note that the final Carry Out block (CO En) has the ALU\_Control signal fed to it. This is so that block can act as an output enable for the carry out bit. This save a processing delay of 1 tic.

## Condition Code Register

This is actually a set of single bit latches which may be set, cleared or 'read' individually. They are generally activated only by internal operations but special instructions are included to manually control them. Each bit may be read individually by the system (often for 'branches'). Because each bit is uniquely defined they may also be 'wire-ORed' to form a single hex value. Thus, the CCR may also be read as a single hex value if desired.

The bits may be used to alter certain other instructions, or for additional data used by other functions. For example the carry bit may be used to support multiple-cell addition, or for software based multiplication.

## Sequencer

A single (4 bit) control input (ALU\_Control) provides the commands for the ALU system. Each component in the ALU is programmed to respond appropriately to all these commands. Every component computes in parallel so each output has its own 'enable'. This enable is inherent the ALU\_Control signal.

The ALU\_Control signal is the machine code (instruction). The ALU sequencer simply takes this instruction and passes it through to the ALU, then waits the proper time for the ALU to complete its processing. Then the sequencer latches the output in the 'accumulator register' (TOS) and signals for the next instruction.