Test and Yield Leaning

In addition to the normal sorting function, test provides
the essential feedback loop for yield-learning.  Specifically, product-based
diagnostics are increasingly vital.  The need to base diagnostics on
actual product hardware is driven by systematic defect mechanisms now being
increasingly complex functions of neighboring shapes, local pattern densities,
etc.  As a result many failure mechanisms may be visible only on product.
In addition, product-based diagnostics automatically put focus on key
yield-limiting failure mechanisms.  Volume-based diagnostics are critical
since individual occurrence of any given systematic defect mechanism may be
rare.  The pooling of data across many failing die are needed to identify
true systematic mechanisms.

== 1.1     Electrical
Test-Based Diagnosis ==

Parametric-related
feedback is needed for (1) device and interconnects parameters and (2)
design-process interactions. Measurement of device and interconnect parameters
have traditionally relied upon test structures, especially scribe line FETs and
interconnect resistance and capacitance monitors. Increasing across-chip
variation (intra-die variability) enhances the negative impact of
scribe-line-to-chip offsets. Moreover, test structures are limited by the
number of physical and electrical configurations they are able to cover. As
circuit parametrics are increasingly affected by such configurations, including
within-standard-cell and transistor-layout configurations, it becomes necessary
to base learning on product test or test of product-like layout configurations.
Embedded, distributed monitor circuits such as thermal and VDD sensors,
process-monitoring ring oscillators and critical path proxies are now standard
on microprocessor-class ICs and can be used to help diagnose parametric fails
and understand variability. Understanding variability includes unraveling the
structure of variations into spatial and cross-parameter components (variation
in transistor length, Vt, source-drain resistance, etc.)  The spatial
component includes both die-to-die and within-die components.

Cross-parameter
variations, potentially including a spatial component, are important to
analog/RF circuits, as well as digital.  Methods for
understanding/characterizing the manufacturing process and operating
environment that are sensitive enough for analog/RF are needed.  Moreover,
product test is uniquely well-suited to provide feedback on design-process
interactions, including those leading to noise-related fails, such as
power-grid-droop and crosstalk fails.

Top
challenges for test-based yield-learning include:

·
Better resolution for cell-internal
defects. Latest advances in structural testing and scan-based logic/layout-aware
diagnosis methods are adequately addressing interconnect and via defects.
Statistical approaches built into volume-based diagnostics are able to predict
interconnect-related defect modes without an over-dependence on Physical
Failure Analysis (PFA). Innovation is required, however, for
cell-internal-defect-targeted diagnostics to be able to identify systematic
fail modes inside standard cells. Observations of hardware suggest a shift
toward a larger percentage of the defect distribution being cell-internal
defects, as opposed to interconnect-related.  Current best methods for
cell-internal defect diagnostics are cell truth-table and gate-exhaustive
model-based, with the truth tables established via static SPICE simulations of
modeled cell-internal parasitics. These methods suffer from aliasing issues and
over-reliance on potentially inaccurate modeling of cell-internal defects used
in SPICE simulations. In addition, diagnosis resolution needs to be better due
to limitations in the PFA process.

·
Managing design data for yield
learning.  A tremendous amount of design data can be brought to bear for
yield learning purposes, but it is often not organized effectively for this
purpose. In addition, with hierarchical design and DFT flows, the overall
management of this data at most companies today is ad-hoc and limiting its
effective use.

·
Inadequacy of LEF/DEF as the basis
of layout-aware diagnosis. LEF/DEF suffices for the purposes of layout-aware
ATPG but is too early in the design cycle to be used effectively for
layout-aware diagnosis.  LEF/DEF is getting farther and farther away from
final mask shapes due to complex OPC, boolean and retargeting steps.

·
Yield-Learning in a
OSAT/Fabless/Foundry environment. Yield-learning capabilities must be cognizant
of the environment that has become the dominant model for our industry.
If the technology cannot deal with the security and logistical concerns of this
environment, it cannot be effective.  Factory integration issues must be

addressed.  Data capture and management capabilities must
support increasing reliance on statistical analysis and data mining of volume
production data for yield-learning. Secure mechanisms for yield-data flow for
distributed design, manufacture and test, including fabless/foundry and 3rd party
IP, are needed. Standard test data formats, such as STDF-V4-2007 scan fail
data, and infrastructure to support their transmittal, are needed to support
automation and sharing of data. Distributed design, manufacture and test also
creates an emerging role for methodologies and tools to help determine in which
area problems lie, e.g., design house, foundry or test house.

·
Test and
data-collection time increases due to longer scan chains. These increases drive
a need for focus on LBIST methodologies and scan compression for both test and
diagnosis.