Register Bank

A register bank is simply a specialized memory circuit that is very fast and tightly tied to the CPU core. It is meant to be accessed in the shortest time possible. Machine instructions will directly point to registers. In most cases the address of the register may be included in the instruction. This facilitates the higher speed access.

Registers must be R/W so the Memory Bank is used in its synchronous mode. To keepregister bank uses use a single stage of Memory Banks which will provide up to 256 registers. This is more than ample for this system. These M.Banks may be stacked to provide any needed data width.

Since the register bank is used in synchronous mode, the address inputs may fluctuate and do not need to be stable except for the single sysclock tic when the control line is activated. This R/W input is edge triggered so the addresses only need to be active at that tic. This means the address lines could be direct wired to an internal bus without the need for an "input enable" as long as the CLOCK input remains '0'. The address and CLOCK may be presented to the M.Bank at the same tic.

The memory bank contains a built in latch so its output will only change on the tic following activation of the control signal. Then it will remain present and stable regardless of the address input until the next control line activation. (The control line must return to zero before it can be activated again.) So there is a need for an output enable on the register bank if it is fed to a common bus.

# Design

## Notes

* This article assumes a register bank depth of 16 cells. This is to simplify the instruction set and the sequencer design. However it is entirely possible to use an additional dedicated register to 'page' the register bank. Paging will give 16 instances of the bank for a total of 256 accessable registers.
* Each cell may be used as an address source for indexed addressing. It is yet TBD whether indexed offset addressing will be provided directly. A dedicated ALU may be included for this case.
* The main memory is assumed to have a latch on the address input. Further analysis may reveal this latch unnecessary (but doubtful).

## Direct connect to the instruction code?

Address lines take 1 Hex. But these are Dont Care unless the CLOCK input is '4' or higher. A second Hex is fed into the CLOCK input but only the high 2 bits matter. The lower 2 bits can still be decoded by another sub-system.

In this method all register functions are accessed directly in the machine instruction and they just use 2 permanently dedicated bits plus the single Hex parameter (register address) only during accesses.

This gives a *single tic* access to the register bank!

But - to where? All register accesses are transfers to or from another location. Just use a sequencer. It only adds a minimum of 1 tic at the beginning and 1 at the end. Making small function machine code takes more time to fetch each instruction (I think). And the machine code would be bulkier and inefficient.

Rather than direct connect a sequencer lets me create machine codes to R/W data from/to different sources directly in single instructions. The fast microsequence segments can still be used in the different instructions.

## Microsequenced Control

Once a sequencer is used to control all data transfer then it is simply extended to include any controls to the register bank. Just a single tic delay is added at the start of a sequence.

Source and destination registers come direct from the IP and are dont care if there's no register instruction. An input select is added so the register bank can choose either. The controls come from the sequencer. The sequencer can read from one location in a bank and write it to another location in the same bank by microsequencing. Hardware allows the connection.

Here is the schematic for the Register bank.

The actual memory file is the block labelled "Mem". The high-order address input is not shown.

The several blocks with the AND gate symbol inside are M.Banks used as gates. They are programmed to respond only to the proper control signal values. All needed combinations of 'enabled' gates may be accomodated with a single (Hex) control line.

The block labelled "SEQ" is the microsequencer for the control lines.

[The following is taken from Instruction Sequences ]

R1->R2 (from one register to another in the same bank)

1. Enable READ (address is already present) {This will latch the M.Bank output only}, select direct data input
2. Disable READ (RTZ), Switch address\_select to "TargetRegister"
3. Enable WRITE (assuming 1 tic for above)
4. jump to WAIT, activate *DONE* output.

The WAIT state will be entered for at least 1 tic so all outputs will "RTZ".

* The address input is set to "SourceRegister".
* The memory control (CLOCK) is '0'
* The data input is set to the data bus.
* The output enable is disabled.

M[R1]->R2 (R1 is a pointer into Main memory and is used to fetch data which is then stored in R2. Transfer is over the data bus.)

1. Enable READ to register bank (address is already present) {This will latch the M.Bank output only},
2. Enable output to bus, send IDLE to register bank
3. (contents of R1 is now on bus) Latch the data memory address register. (???)
4. Disable register output to bus, select TargetRegister as register bank address input
5. NOOP for main memory decoding. (?)
6. Send READ to Main memory
7. Send IDLE to Main memory (data is now on the bus), send WRITE to register bank (data input is 'bus' as default)
8. jump to WAIT, activate *DONE* output.

* Resets register bank controls as noted previously

R1->M(R2) (R2 is a pointer into main memory and is used to store the data in R1. Transfer uses bus.)

1. Set register bank address input to "TargetRegister"
2. Send READ to register bank
3. (address is now on bus) Latch the data memory address register. (takes 2? tics)
4. Set register bank address input to "SourceRegister" (1 tic), enable main memory output to bus
5. Send READ to main memory
6. (data is now on bus) Send WRITE to register bank
7. jump to WAIT, activate *DONE* output.

* Disables main memory output to bus in addition to resetting register bank controls

M[R1]->M[R2] (Both R1 and R2 hold addresses into main memory. Transfers data from memory -to- memory, using bus.)

* Such a transfer will require the data to be temporarily stored (the address transfer uses the bus). Because of this a separate instruction is not necessary. Either a memory-to-register or memory-to-latch pair must be used.

OR? Should I add another internal bus for address transfers only???

There are 3 controls to the register bank sub-system in addition to the M.Banks's CLOCK input. These are the address\_input and data\_input selects and the output\_enable. They will all share a common (Hex) control line. So the sequencer will have 2 outputs controlling the register bank - the CLOCK control and I/O control. Other outputs are necessary but they will control other sub-systems.