Test Drivers, Challenges and Future Opportunities

This section provides a top-level view of the general challenges
facing Semiconductor test.  It is
organized into three sections

·
Key Drivers: These are the high level technical
and economic trends which will drive IC test overall

·
Difficult challenges: These difficult challenges
define areas where more development or understanding is needed in order to cost
effectively meet the semiconductor roadmap.

·
Future Opportunities: These are longer-term
areas of research and development that would address current or future
challenges in the area of semiconductor test.

== 1.1     Key
Drivers ==

=== 1.1.1    Increasing
Device Integration ===

Device integration happens in two ways:

·
SOC integration adds more functionality on the
same die

·
SIP integration integrated multiple die into the
same package.  This path is chosen
because different functions are implemented in different silicon processes or
are produced by different manufacturers, and it is more efficient to combine
them at the package level rather than moving functions to the same die.  It also allows combining purely electrical
devices with mechanical/electronics devices like sensors, MEMs, etc.

These drive two increasingly important test trends

·
Before they are shipped to customers, the device
must be validated to function in its end application.  Most manufacturing test has been migrated to
a “superposition” model, where different portions of devices are tested in
isolation through structural test, or parametric tests that are performed on
isolated analog functions.  These
techniques leave untested the ability of different portions of the device to
function with each other, typically at different operating frequencies with
random timing.  Increasing, test
insertions are being added at which the device runs in “mission mode”.   Since this adds cost to the overall
manufacturing process, techniques must be developed to provide the same test
coverage more efficiently as an existing test insertion

·
If devices are constructed from multiple die, it
is critical that the failure rate of any die be extremely low since having to
scrap the final SIP is extremely expensive.
Thus these “known” good die must be exhaustively tested before they are
integrated into the final package.  This
will require improved signal performance at probe and the need to perform
multiple probe tests without mechanical damage.

In addition, the need for non-electrical stimulus at test will
become more prevalent in the test of more highly integrated devices.  Non-electrical stimulus and responses may
include, but are not limited to:

·
Optical communications and contacting

·
Pressure including sound

·
Rotation

·
Gravity

·
Chemical, molecular, or protein sensing
including Raman spectroscopy, florescence, and other techniques

·
Temperature

·
Humidity

·
Magnetic Field

·
Acceleration including vibration and shock

·
Fluid flow

=== 1.1.2    Process
Technology and device architecture ===

Shrinking dimensions and new structures of silicon processes have
evolved to the point where being able to produce devices that function precisely
as designed cannot be relied upon.  There
are two underlying problems:

·
Every wafer has enough variations is electrical
performance that it is impossible to rely on each device to perform precisely
the same.  Most high performance devices
are designed with this in mind, so mechanism are built into the design that
allows the device performance to be adjusted after it is built.  This includes “tuning” analog parameters such
as voltage levels, frequencies and overall power consumption.  This final manufacturing step is now lumped
into the “test” process.  As a result,
the model of a known stimulus causing a known response has evolved to the point
where device stimulus must be iteratively adjusted independently on each device
based on the electrical characteristics measured at the beginning of the test
process.  This is a significant change to
the model of test as it has historically been done and will accelerate with
future fabrication technologies.  This
will require changes to the operation of test equipment in order to make that
process as efficient as possible.

·
Defects will always occur in the fabrication
process, usually measured in terms of defects per area of the wafer (N defects
per square millimeter, for example).  As
die become smaller, the chances of having some defect on a given device increases
greatly.  To compensate for this,
increasing amounts of redundant circuitry is added that can be used to replace
defective portions of the device, either when the device is manufactured or
later when the device is being used in its final application.  This has long been a technique used on memory
manufacturing, and will become more prevalent in SOC devices over time. Again,
this will drive the need for test to very efficiently adapt to the
functionality observed during initial testing.

Another artifact of new process technology is that operating
voltages are steadily decreasing.  This
will drive the need to greater accuracy in test equipment at these lower
voltages in order to optimize yield.

=== 1.1.3    Increased
device performance ===

Analog performance of devices will continue to improve.  A good example of this is the increased
performance required of RF modulation/demodulated circuitry as wireless data
rates are increased.  In concert with
cost reduction enabled by Design-For-Test features, the electrical performance
of certain test instrumentation will need to continue to match these
improvements.

=== 1.1.4    Test
Process Complexity ===

In addition to the requirements described above, the test process
has evolved in two significant ways based on the capability to better integrate
test into the overall production process.

·
Test Flows and limits are adjusted based on statistical
analysis of results either at the current test insertion or information fed
forward from earlier in the production process.

·
Test results are fed back to the design and
fabrication much more quickly to improve device yield.  This correlates to the shorter timelines
required to development new device and deploy them to high volume
manufacturing.

These developments are driving a rapid increase in the amount of
data produced by the test process, and the need to transport and analyze that
data quickly and securely.  In addition,
the collection of that data cannot reduce the throughput of the test cell.  This will drive new standards for data file
formats and transportation mechanisms to and from the test cell.

### 1.1.5    Cost

Economics are the prime driver for any high volume manufacturing
process.  Historically, test costs have
been reduced by reducing the amount of capital equipment required to produce a
given number of devices.  This has
accomplished by improving parameters such as cost per pin of test equipment,
test time and test parallelism (site count or concurrent test).

This approach will have to change for several reasons

·
The cost of test has become a very small
fraction of the overall cost of producing semiconductors.  The return on investment for new avenues of
test cost reduction is very limited as compared to investment in other aspects
of the manufacturing process such as reducing fabrication costs and improving
Time To Market

·
Site count as a test cost reduction technique is
naturally limited by handling and interface costs, as well as the volume of
devices tested.  Since the number of
devices to be produced is finite, so are the gains from increasing the
throughput of a given test cell.

·
Improvements in test time that can be achieved
are decreasing asymptotically.  Equipment
overhead has been reduced to the point where it is a very small portion of the
overall test time.  In addition, average
test times are increasing due to increased device complexity, manifested in the
form of increased scan test times and overall increases in the number of tests
required per device.

·
Improving quality of test has is much more
beneficial economically than reducing cost of test.  Any extra costs caused by test are more than
compensated for by the reduction in scrap costs that are achieved by improved
yield.  Focusing solely on test costs
ignores the much greater benefits of reducing fab costs (which are far greater)
by investing in better test equipment that would drive an increase in
yield.  See section 4 for a more detailed
discussion on this topic.

== 1.2     Difficult
Challenges ==

Listed below is selected group of technical challenges for test
that will drive new capability.

=== 1.2.1    Test
Development As A Gate To Volume Production ===

The desire to reduce the time required to start high volume
production of new, complex devices in a constant force in the semiconductor
industry.  Test development and debug is
one of the most “exposed” portions of the process given that it is gated by the
device design and fabrication and is the last step before production can
begin.  There are a number of
contributors to this process becoming more complex.

·
The sheer number of Lines of Code in test
programs is continuing to increase to implement device characterization, as
well as the requirements for variable device flows and the implementation of
tests to trim various device parameters.
In addition, the volume of pattern data continues to grow (See section 7
for a more detailed analysis).

·
Multiple test developers are deployed to
simultaneously construct different portions of the overall test program.  It must be possible to seamlessly combine the
work of these developers, and the work of one developer cannot interfere with
work of any other.  Furthermore, the
number of collaborators may be restricted by IP security or similar concerns.

·
Operation of the device during test is dependent
on embedded software and firmware which may itself be defective.

All of this combines to drive extremely complex code, typically
developed by engineers with limited software expertise.  *The*
resultant issues in the quality of the test code are the primary source of
overall test quality problems*.*

The issue of test program quality must addressed by techniques
common to the software industry overall.
For example:

·
The automated generation of pattern data from
devices simulation data is a well-controlled process.  This automated process must be extended to
the test program itself through the use of standardized code libraries and test
definitions.  While this has been a goal
of the test industry for many years, success to date is not widespread for
complex SOC devices.

·
Offline software test must be further developed
to simulate various program flows, undefined or incorrectly defined parameters,
incorrect program flow paths and binning, etc.

·
Tools for the integration and management of
multiple stand-alone test programs must be improved.

=== 1.2.2    Detecting
System Defects ===

As noted earlier, the desire to eliminate the need for
system-level test insertions to guarantee the quality of complex devices is
driven by the need to reduce overall production costs.  Finding a way to provide test coverages for these
types of faults is a continuing challenging.
See the discussion in the next section for possible paths to solve this
problem.

=== 1.2.3    Concurrent
Test ===

The adoption of concurrent test has been on ongoing challenge,
mostly owing to the inability of most devices to utilize it.

=== 1.2.4    Wafer
level Packaging ===

Wafer level packaging will continue to proliferate and will drive
the need for more efficient handling of singulated die and need for additional
wafer test insertions for temperature test or other reasons.

== 1.3     Future
Opportunities ==

Listed below are several areas with the potential to yield
significant improvements in test efficiency and effectiveness

Table TST3c-
Summary of Future Opportunities

  *Combine Multiple Test*
 Environments
 Lab, Silicon Test and System-Level Test environments to reduce costs and
  *Test Environment Simulation*
 various simulation capabilities and methodologies for device and test
  *Improved Fault Modeling*
 redundant testing with more sophisticated
 modeling to find system-level and other un-modeled faults

=== 1.3.1    Combine
Multiple Test Environments ===

There are essentially two environments for device testing.

·
The first is used for device bring-up and
silicon debug, mostly in a laboratory environment.  This environment uses tools and software
associated with the design environment and/or end-use programming.  It provides the ability to manipulate various
device functions via JTAG or some similar path and uses code that is easily
ported from EDA tools.  End-use customers
also use this environment for developing embedded software and firmware to enable
applications development for the device.

·
The second programming environment is that used
for high volume manufacturing test on traditional ATE.  The purpose of this environment is to find
manufacturing defects and assumes the design of the device has already been
validated.  The link to the design
environment is more indirect, typically just consisting of the ability to
convert device simulation data into test patterns.

As noted earlier, devices with multiple heterogeneous cores have
manufacturing defects that are only found through functional “mission mode”
test of the device, which is almost always developed as BIST functions in the
development software environment.

Device bring-up and transfer to high volume manufacturing would
be made far more efficient if these two environments were both available on
ATE.  Benefits would include:

·
The ability to easily correlate scan or
parametric tests to system-level faults

·
The ability to develop BIST functionality that
works together with the “external” test capability of the ATE to facilitate
system-level test coverage on an existing ATE insertion

·
The ability to run tests developed in the
engineering development environment on a large population of devices on the ATE
hardware utilizing the handling, temperature control and data collection
capabilities on production-oriented equipment.

·
Shortening the test feedback process to design
engineers by having test, DFT and design engineers working on the same
equipment.

=== 1.3.2    Test
Environment Simulation ===

Numerous attempts have been made over the years to provide a
single simulation environment that encompasses device simulation with
simulation of the tester environment.
Functional simulation of the tester and device has largely been
abandoned due to its complexity and the more effective solution of improving
device simulation capability, improving the EDA to test software path, and
improving and standardizing test implementation on ATE.

There are still benefits to be gained, however, by focusing on
the analog simulation of the signal transmission path from the tester to the
DUT itself, especially in the context of improving the design and fabrication
of tester interface hardware.

=== 1.3.3    Improved
Fault Modeling ===

In conjunction with the discussion in 2.2.1,
the detection of system-level faults would be facilitate by more comprehensive
device fault modeling, including the interaction of heterogeneous cores in the
device operation in their end application modes.