Test Executive Summary

The 2015 revision of the Test Technology Roadmap identifies many
significant changes to the industry as well as a number of significant
challenges which the industry is working to overcome.

1.      Notable
Changes

a.      Cost-of-Test
– Reducing the cost-of-test, while always an industry goal, has begun to suffer
from diminishing returns when looking at the traditional approach such as
capital cost reduction or site count increases.   As part complexity
increases, test times and thus cost-of-test has also been increasing and driving
up the cost-of-test.   Additionally, the cost of "consumable"
test interface material has come to play a much larger role in cost-of-test.
 Interestingly, the overall cost-of-test is becoming a lower percentage of
the overall IC manufacturing expense while at the same time test is having a
greater impact on profitability.

b.      Heterogeneous
Integration – As more and more 2.5D and 3D device integrations come on the
market it has become clear that additional testing is necessary to avoid
scrapping expensive sub-assemblies.

c.      Wafer
probing – After reporting big changes in probe pitch and counts in 2013, we
once again need to adjust the requirements in 2015.   These changes are largely in response to the
broad deployment of microbumps and pillar type interconnects which drive up the
density and down the pitch.

d.      Logic
Table – The product groupings have changes with this publication.   The new groupings are:

i.  MPU-HP (Big Data) – High Performance MPU (MPU,Servers, GPU)
ii.  MPU-CP (Mobile) – Mobile Consumer MPU (SOC, APU)
iii.  SOC-CP (Low power Devices) – Low-Power Consumer (MCU, IoT, MEMs, Analog)
2

This product grouping was chosen to provide a better alignment with the ITRS 2.0 documents.   An additional benefit of this grouping is it provides a better understanding of the challenges in the testing of low power devices
.  Areas with Significant Challenges for the Future:

a.      Thermal
– Various needs are pushing the performance envelope for high-performance
thermal solutions both at wafer probe as well as in a packaged device environment.   More sophisticated automotive electronics
demand testing to a wider temperature range.
In addition, long test times are pushing scan speeds up resulting in a
need for better device cooling during test.

a.      Adaptive
Device Testing – This technique continues to deliver significant value to the
industry.   Looking forward this
technology is challenged to broadly implement real-time feed forward and
feedback systems in an industry which has increasingly complex supply chains.
Adaptive test may prevent an increase in test cost.

b.      Parallel
Testing – The typical parallel testing site counts for most products are not
changing.  With the increased device
complexity this is one of the driving forces in an increasing cost-of-test.   Areas where the industry is working are to
increase parallel site counts are RF device testing, LCD testing, and MEMs
device testing.

c.      Logic
Device Testing – With the broad deployment of FinFET technology the complexity
of digital devices continues to increase.
Further enhancing this trend is the trend toward heterogeneous
integration.    While pattern compression
techniques help manage the challenge of test data volume it does little to help
reduce test times and hence cost of testing.

d.      Optical
Interface Testing – In 2015 we are starting to see a trend toward the use of optical
interfaces in the high-speed SerDes area.
Testing optical device brings with it big challenges for precise fiber
alignment as well as new test methods when working with light as a signal
source.

Challenges and changes in the other topic areas are less
dramatic.