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adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/csl_vcp2Aux.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ===========================================================================
* @file csl_vcp2Aux.h
*
* @path $(CSLPATH)\inc
*
* @desc API header for VCP2
*
*/
/* ============================================================================
* Revision History
* ================
* 24-March-2004 SPrasad File Created.
* 27-May-2005 SPrasad Updated with new requirements' specification.
* 03-Aug-2005 Chandra A few minor changes in documentation and to
* beautify.
* 8-dec-2005 sd changed the maxSm and minSm to be signed
* integers
* ============================================================================
*/
#ifndef _CSL_VCP2AUX_H_
#define _CSL_VCP2AUX_H_
#include <csl_vcp2.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* ============================================================================
* @n@b VCP2_ceil
*
* @b Description
* @n This function calculates the ceiling for a given value and a power of 2.
* The arguments follow the formula: ceilVal * 2^pwr2 = ceiling
* (val, pwr2).
*
* @b Arguments
@verbatim
val Value to be augmented.
pwr2 The power of two by which val must be divisible.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value The smallest number which when multiplied by 2^pwr2 is
* greater than val.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint32 numSysPar;
numSysPar = VCP2_ceil ((frameLen * rate), 4);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_ceil (
Uint32 val,
Uint32 pwr2
)
{
Uint32 value;
value = ( ((val) - ( ((val) >> (pwr2)) << (pwr2)) ) == 0) ? \
((val) >> (pwr2)) : (((val) >> (pwr2)) + 1);
return value;
}
/**
* ============================================================================
* @n@b VCP2_normalCeil
*
* @b Description
* @n Returns the value rounded to the nearest integer greater than or
* equal to (val1/val2)
*
* @b Arguments
@verbatim
val1 Value to be augmented.
val2 Value by which val1 must be divisible.
@endverbatim
*
* <b>Return Value </b> Uint32
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint32 framelen = 51200;
Uint32 numSubFrame;
...
// to calculate the number of sub frames for SP mode
numSubFrame = VCP2_normalCeil (framelen, TCP2_SUB_FRAME_SIZE_MAX);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_normalCeil (
Uint32 val1,
Uint32 val2
)
{
Uint32 value;
value = ( ((val1) % (val2)) != 0 ) ? ( ((val1) / (val2)) + 1 ) : \
((val1) / (val2));
return value;
}
/**
* ============================================================================
* @n@b VCP2_getBmEndian
*
* @b Description
* @n This function returns the value programmed into the VCPEND register for
* the branch metrics data for Big Endian mode indicating whether the data
* is in its native 8-bit format ('1') or 32-bit word packed ('0').
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Branch metric memory format.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - 32-bit word packed.
* @li 1 - Native (8 bits).
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
If (VCP2_getBmEndian ()) {
...
} // end if //
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_getBmEndian (
void
)
{
return CSL_FEXT (hVcp2->VCPEND, VCP2_VCPEND_BM);
}
/**
* ============================================================================
* @n@b VCP2_getIcConfig
*
* @b Description
* @n This function gets the current VCPIC register values and puts them in a
* structure of type VCP2_ConfigIc.
*
* @b Arguments
@verbatim
pConfigIc Pointer to the structure of type VCP2_ConfigIc to hold
the values of VCPIC registers.
@endverbatim
*
* <b>Return Value </b> Value
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The structure of type VCP2_ConfigIc passed as arguement contains the
* values of the VCP configuration registers.
*
* @b Modifies
* @n Input structure of type VCP2_ConfigIc.
*
* @b Example
* @verbatim
VCP2_ConfigIc configIc;
...
VCP2_getIcConfig (&configIc);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_getIcConfig (
VCP2_ConfigIc *configIc
)
{
register int x0, x1, x2, x3, x4, x5;
x0 = hVcp2Vbus->VCPIC0;
x1 = hVcp2Vbus->VCPIC1;
x2 = hVcp2Vbus->VCPIC2;
x3 = hVcp2Vbus->VCPIC3;
x4 = hVcp2Vbus->VCPIC4;
x5 = hVcp2Vbus->VCPIC5;
configIc->ic0 = x0;
configIc->ic1 = x1;
configIc->ic2 = x2;
configIc->ic3 = x3;
configIc->ic4 = x4;
configIc->ic5 = x5;
}
/**
* ============================================================================
* @n@b VCP2_getNumInFifo
*
* @b Description
* @n This function returns the count, number of symbols currently in the
* input FIFO.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Number of symbols in the branch metric input FIFO
* buffer.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint32 numSym;
numSym = VCP2_getNumInFifo ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_getNumInFifo (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT1, VCP2_VCPSTAT1_NSYMIF);
}
/**
* ============================================================================
* @n@b VCP2_getNumOutFifo
*
* @b Description
* @n This function returns the count, number of symbols currently in the
* output FIFO.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Number of symbols present in the output FIFO buffer.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint32 numSym;
numSym = VCP2_getNumOutFifo ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_getNumOutFifo (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT1, VCP2_VCPSTAT1_NSYMOF);
}
/**
* ============================================================================
* @n@b VCP2_getSdEndian
*
* @b Description
* @n This function returns the value programmed into the VCPEND register for
* the soft decision data for Big Endian mode indicating whether the data
* is in its native 8-bit format ('1') or 32-bit word packed ('0').
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Soft decisions memory format.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - 32-bit word packed.
* @li 1 - Native (8 bits).
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
If (VCP2_getSdEndian ()) {
...
} // end if
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_getSdEndian (
void
)
{
return CSL_FEXT (hVcp2->VCPEND, VCP2_VCPEND_SD);
}
/**
* ============================================================================
* @n@b VCP2_getStateIndex
*
* @b Description
* @n This function returns an index for the final maximum state metric.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Final maximum state metric index.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint8 index
index = VCP2_getStateIndex();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint8 VCP2_getStateIndex (
void
)
{
return CSL_FEXT (hVcp2Vbus->VCPOUT1, VCP2_VCPOUT1_FMAXI);
}
/**
* ============================================================================
* @n@b VCP2_getYamBit
*
* @b Description
* @n This function returns the value of the Yamamoto bit after the VCP
* decoding.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Yamamoto bit result. This bit is a quality indicator
* bit and is only used if the Yamamoto logic is enabled.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The return bit value indicates,
* @li 0 - at least one trellis stage had an absolute difference less than
* the Yamamoto threshold and the decoded frame has poor quality.
* @li 1 - no trellis stage had an absolute difference less than the
* Yamamoto threshold and the frame has good quality.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint8 yamBit
yamBit = VCP2_getYamBit();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint8 VCP2_getYamBit (
void
)
{
return CSL_FEXT (hVcp2Vbus->VCPOUT1, VCP2_VCPOUT1_YAM);
}
/**
* ============================================================================
* @n@b VCP2_getMaxSm
*
* @b Description
* @n This function returns the final maximum state metric after the VCP has
* completed its decoding.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Maximum state metric value for the final trellis stage.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Int16 maxSm
maxSm = VCP2_getMaxSm();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Int16 VCP2_getMaxSm (
void
)
{
return CSL_FEXT (hVcp2Vbus->VCPOUT0, VCP2_VCPOUT0_FMAXS);
}
/**
* ============================================================================
* @n@b VCP2_getMinSm
*
* @b Description
* @n This function returns the final minimum state metric after the VCP has
* completed its decoding.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Minimum state metric value for the final trellis stage.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Int16 minSm
minSm = VCP2_getMinSm();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Int16 VCP2_getMinSm (
void
)
{
return CSL_FEXT (hVcp2Vbus->VCPOUT0, VCP2_VCPOUT0_FMINS);
}
/**
* ============================================================================
* @n@b VCP2_icConfig
*
* @b Description
* @n This function programs the VCP input configuration registers with the
* values provided through the VCP2_ConfigIc structure.
*
* @b Arguments
@verbatim
pVcpConfigIc Pointer to VCP2_ConfigIc structure instance
containing the input configuration register values.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP input configuration registers.
*
* @b Example
* @verbatim
VCP2_ConfigIc configIc;
configIc.ic0 = 0xf0b07050;
configIc.ic1 = 0x10320000;
configIc.ic2 = 0x000007fa;
configIc.ic3 = 0x00000054;
configIc.ic4 = 0x00800800;
configIc.ic5 = 0x51f3000c;
...
VCP2_icConfig (&configIc);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_icConfig (
VCP2_ConfigIc *vcpConfigIc
)
{
register int x0, x1, x2, x3, x4, x5;
x0 = vcpConfigIc->ic0;
x1 = vcpConfigIc->ic1;
x2 = vcpConfigIc->ic2;
x3 = vcpConfigIc->ic3;
x4 = vcpConfigIc->ic4;
x5 = vcpConfigIc->ic5;
hVcp2Vbus->VCPIC0 = x0;
hVcp2Vbus->VCPIC1 = x1;
hVcp2Vbus->VCPIC2 = x2;
hVcp2Vbus->VCPIC3 = x3;
hVcp2Vbus->VCPIC4 = x4;
hVcp2Vbus->VCPIC5 = x5;
}
/**
* ============================================================================
* @n@b VCP2_icConfigArgs
*
* @b Description
* @n This function programs the VCP input configuration registers with the
* given values.
*
* @b Arguments
@verbatim
ic0 Value to program input configuration register 0.
ic1 Value to program input configuration register 1.
ic2 Value to program input configuration register 2.
ic3 Value to program input configuration register 3.
ic4 Value to program input configuration register 4.
ic5 Value to program input configuration register 5.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP input configuration registers.
*
* @b Example
* @verbatim
Uint32 ic0, ic1, ic2, ic3, ic4, ic5;
...
ic0 = 0xf0b07050;
ic1 = 0x10320000;
ic2 = 0x000007fa;
ic3 = 0x00000054;
ic4 = 0x00800800;
ic5 = 0x51f3000c;
...
VCP2_icConfigArgs (ic0, ic1, ic2, ic3, ic4, ic5);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_icConfigArgs (
Uint32 ic0,
Uint32 ic1,
Uint32 ic2,
Uint32 ic3,
Uint32 ic4,
Uint32 ic5
)
{
hVcp2Vbus->VCPIC0 = ic0;
hVcp2Vbus->VCPIC1 = ic1;
hVcp2Vbus->VCPIC2 = ic2;
hVcp2Vbus->VCPIC3 = ic3;
hVcp2Vbus->VCPIC4 = ic4;
hVcp2Vbus->VCPIC5 = ic5;
}
/**
* ============================================================================
* @n@b VCP2_setBmEndian
*
* @b Description
* @n This function programs the VCP to view the format of the branch metrics
* data as either native 8-bit format ('1') or values packed into 32-bit
* words in little endian format ('0').
*
* @b Arguments
@verbatim
bmEnd '1' for native 8-bit format and '0' for 32-bit word packed
format
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP endian register.
*
* @b Example
* @verbatim
Uint32 bmEnd = VCP2_END_NATIVE;
VCP2_setBmEndian (bmEnd);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_setBmEndian (
Uint32 bmEnd
)
{
CSL_FINS (hVcp2->VCPEND, VCP2_VCPEND_BM, bmEnd);
}
/**
* ============================================================================
* @n@b VCP2_setNativeEndian
*
* @b Description
* @n This function programs the VCP to view the format of all data as native
* 8-bit format.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP endian register.
*
* @b Example
* @verbatim
VCP2_setNativeEndian ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_setNativeEndian (
void
)
{
CSL_FINST (hVcp2->VCPEND, VCP2_VCPEND_BM, NATIVE);
CSL_FINST (hVcp2->VCPEND, VCP2_VCPEND_SD, NATIVE);
}
/**
* ============================================================================
* @n@b VCP2_setPacked32Endian
*
* @b Description
* @n This function programs the VCP to view the format of all data as packed
* data in 32-bit words.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP endian register.
*
* @b Example
* @verbatim
VCP2_setPacked32Endian ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_setPacked32Endian (
void
)
{
CSL_FINST (hVcp2->VCPEND, VCP2_VCPEND_BM, 32BIT);
CSL_FINST (hVcp2->VCPEND, VCP2_VCPEND_SD, 32BIT);
}
/**
* ============================================================================
* @n@b VCP2_setSdEndian
*
* @b Description
* @n This function programs the VCP to view the format of the soft decision
* data as either native 8-bit format ('1') or values packed into 32-bit
* words in little endian format ('0').
*
* @b Arguments
@verbatim
sdEnd '1' for native 8-bit format and '0' for 32-bit word packed
format
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP endian register.
*
* @b Example
* @verbatim
Uint32 sdEnd = VCP2_END_NATIVE;
VCP2_setSdEndian (sdEnd);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_setSdEndian (
Uint32 sdEnd
)
{
CSL_FINS (hVcp2->VCPEND, VCP2_VCPEND_SD, sdEnd);
}
/**
* ============================================================================
* @n@b VCP2_addPoly
*
* @b Description
* @n This function is used to add either predefined or user defined
* Polynomials to the generated VCP2_Params.
*
* @b Arguments
@verbatim
pPoly Pointer to the structure of type VCP2_Poly containing
the values of generator polynomials.
pParams Pointer to the structure of type VCP2_Params containing
the generated values for input configuration registers.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n Structure of type VCP2_Params passed as arguement to the function.
*
* @b Example
* @verbatim
VCP2_Poly poly = {VCP2_GEN_POLY_3, VCP2_GEN_POLY_1,
VCP2_GEN_POLY_2, VCP2_GEN_POLY_3};
VCP2_Params params;
VCP2_Baseparams baseParams;
...
VCP2_genParams (&baseParams, ¶ms);
VCP2_addPoly (&poly, ¶ms);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_addPoly (
VCP2_Poly *poly,
VCP2_Params *params
)
{
Uint8 x0, x1, x2, x3;
x0 = poly->poly0;
x1 = poly->poly1;
x2 = poly->poly2;
x3 = poly->poly3;
params->poly0 = x0;
params->poly1 = x1;
params->poly2 = x2;
params->poly3 = x3;
}
/**
* ============================================================================
* @n@b VCP2_statError
*
* @b Description
* @n This function returns a Boolean value indicating whether any VCP error
* has occurred.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Boolean value
* @li bitStatus ERR bit field value of VCP status register 0.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li FALSE - No error.
* @li TRUE - VCP paused due to error.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
VCP2_Error error;
// check whether an error has occurred
if (VCP2_statError ()) {
VCP2_getErrors (&error);
} // end if
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Bool VCP2_statError (
void
)
{
return (Bool) CSL_FEXT (hVcp2->VCPSTAT0, VCP2_VCPSTAT0_ERR);
}
/**
* ============================================================================
* @n@b VCP2_statInFifo
*
* @b Description
* @n This function returns the input FIFO's empty status flag. A '1'
* indicates that the input FIFO is empty and a '0' indicates it is not
* empty.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> bitStatus
* @li bitStatus IFEMP bit field value of VCP status register 0.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - Input FIFO is not empty.
* @li 1 - Input FIFO is empty.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
If (VCP2_statInFifo ()) {
...
} // end if
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_statInFifo (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT0, VCP2_VCPSTAT0_IFEMP);
}
/**
* ============================================================================
* @n@b VCP2_statOutFifo
*
* @b Description
* @n This function returns the output FIFO's full status flag. A '1'
* indicates that the output FIFO is full and a '0' indicates it is not.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> bitStatus
* @li bitStatus OFFUL bit field value of VCP status register 0.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - Output FIFO is not full.
* @li 1 - Output FIFO is full.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
If (VCP2_statOutFifo ()) {
...
} // end if
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_statOutFifo (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT0, VCP2_VCPSTAT0_OFFUL);
}
/**
* ============================================================================
* @n@b VCP2_statPause
*
* @b Description
* @n This function returns the PAUSE bit status indicating whether the VCP is
* paused or not.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> bitStatus
* @li bitStatus PAUSE bit field value of VCP status register 0.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - VCP is not paused.
* @li 1 - VCP is paused.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
// Pause the VCP.
VCP2_pause ();
// Wait for pause to take place
while (! VCP2_statPause ());
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_statPause (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT0, VCP2_VCPSTAT0_PAUSE);
}
/**
* ============================================================================
* @n@b VCP2_statRun
*
* @b Description
* @n This function returns the RUN bit status indicating whether the VCP is
* running or not.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> bitStatus
* @li bitStatus RUN bit field value of VCP status register 0.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - VCP is not running.
* @li 1 - VCP is running.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
// start the VCP
VCP2_start ();
// check that the VCP is running
while (! VCP2_statRun ());
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_statRun (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT0, VCP2_VCPSTAT0_RUN);
}
/**
* ============================================================================
* @n@b VCP2_statSymProc
*
* @b Description
* @n This function returns the number of symbols processed, NSYMPROC bitfield
* of VCP.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Number of symbols processed.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint32 numSym;
...
numSym = VCP2_statSymProc ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_statSymProc (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT0, VCP2_VCPSTAT0_NSYMPROC);
}
/**
* ============================================================================
* @n@b VCP2_statWaitIc
*
* @b Description
* @n This function returns the WIC bit status indicating whether the VCP is
* waiting to receive new input configuration values.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> bitStatus
* @li bitStatus WIC bit field value of VCP status register 0.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - VCP is not waiting for input configuration words.
* @li 1 - VCP is waiting for input configuration words.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
If (VCP2_statWaitIc ()) {
...
} // end if
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_statWaitIc (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT0, VCP2_VCPSTAT0_WIC);
}
/**
* ============================================================================
* @n@b VCP2_start
*
* @b Description
* @n This function starts the VCP by writing a start command to the VCPEXE
* register.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n VCP is started.
*
* @b Modifies
* @n VCP execution register.
*
* @b Example
* @verbatim
VCP2_start ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_start (
void
)
{
CSL_FINST (hVcp2->VCPEXE, VCP2_VCPEXE_COMMAND, START);
}
/**
* ============================================================================
* @n@b VCP2_pause
*
* @b Description
* @n This function pauses the VCP by writing a pause command to the VCPEXE
* register.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n The VCP should be operating in debug/emulation mode.
*
* <b>Post Condition </b>
* @n VCP is paused.
*
* @b Modifies
* @n VCP execution register.
*
* @b Example
* @verbatim
VCP2_pause ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_pause (
void
)
{
CSL_FINST (hVcp2->VCPEXE, VCP2_VCPEXE_COMMAND, PAUSE);
}
/**
* ============================================================================
* @n@b VCP2_unpause
*
* @b Description
* @n This function un-pauses the VCP, previously paused by VCP2_pause()
* function, by writing the un-pause command to the VCPEXE register.
* This function restarts the VCP at the beginning of current
* traceback, and VCP will run to normal completion.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n The VCP should be operating in debug/emulation mode.
*
* <b>Post Condition </b>
* @n VCP is restarted.
*
* @b Modifies
* @n VCP execution register.
*
* @b Example
* @verbatim
VCP2_unpause ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_unpause (
void
)
{
CSL_FINST (hVcp2->VCPEXE, VCP2_VCPEXE_COMMAND, RESTART);
}
/**
* ============================================================================
* @n@b VCP2_stepTraceback
*
* @b Description
* @n This function un-pauses the VCP, previously paused by VCP2_pause()
* function, by writing the un-pause command to the VCPEXE register.
* This function restarts the VCP at the beginning of current
* traceback and halts at the next traceback (i.e Step Single Traceback).
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n The VCP should be operating in debug/emulation mode.
*
* <b>Post Condition </b>
* @n VCP is restarted.
*
* @b Modifies
* @n VCP execution register.
*
* @b Example
* @verbatim
VCP2_stepTraceback ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_stepTraceback (
void
)
{
CSL_FINST (hVcp2->VCPEXE, VCP2_VCPEXE_COMMAND, RESTART_PAUSE);
}
/**
* ============================================================================
* @n@b VCP2_reset
*
* @b Description
* @n This function sets all the VCP control registers to their default
* values.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n All registers in the VCP are reset except for the execution register,
* endian register, emulation register and other internal registers.
*
* @b Modifies
* @n VCP execution register.
*
* @b Example
* @verbatim
VCP2_reset ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_reset (
void
)
{
CSL_FINST (hVcp2->VCPEXE, VCP2_VCPEXE_COMMAND, STOP);
}
/**
* ============================================================================
* @n@b VCP2_getErrors
*
* @b Description
* @n This function will acquire the VCPERR register values and fill in the
* fields of VCP2_Error structure and pass it back as the results.
*
* @b Arguments
@verbatim
pVcpErr Pointer to the VCP2_Errors structure instance.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The fields of the VCP2_Errors structure indicate the respective errors if
* occurred.
*
* @b Modifies
* @n VCPSTAT0 register, as a side effect. Clears ERR bit.
*
* @b Example
* @verbatim
VCP2_Errors error;
// check whether an error has occurred
if (VCP2_statError ()) {
VCP2_getErrors (&error);
} // end if
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_getErrors (
VCP2_Errors *pVcpErr
)
{
pVcpErr->tbnaErr = (Bool) CSL_FEXT (hVcp2->VCPERR, VCP2_VCPERR_TBNAERR);
pVcpErr->ftlErr = (Bool) CSL_FEXT (hVcp2->VCPERR, VCP2_VCPERR_FTLERR);
pVcpErr->fctlErr = (Bool) CSL_FEXT (hVcp2->VCPERR, VCP2_VCPERR_FCTLERR);
pVcpErr->maxminErr =
(Bool) CSL_FEXT (hVcp2->VCPERR, VCP2_VCPERR_MAXMINERR);
pVcpErr->symxErr = (Bool) CSL_FEXT (hVcp2->VCPERR, VCP2_VCPERR_E_SYMX);
pVcpErr->symrErr = (Bool) CSL_FEXT (hVcp2->VCPERR, VCP2_VCPERR_E_SYMR);
}
/**
* ============================================================================
* @n@b VCP2_statEmuHalt
*
* @b Description
* @n This function returns the EMUHALT bit status indicating whether the VCP
* halt is due to emulation or not.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b> bitStatus
* @li bitStatus Emuhalt bit field value of VCP status register 0.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - Not halt due to emulation.
* @li 1 - Halt due to emulation.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
If (VCP2_statEmuHalt ()) {
...
}// end if
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_statEmuHalt (
void
)
{
return CSL_FEXT (hVcp2->VCPSTAT0, VCP2_VCPSTAT0_EMUHALT);
}
/**
* ============================================================================
* @n@b VCP2_getVssSleepMode
*
* @b Description
* @n This function returns the value programmed into VCPEND register for
* sleep mode indicating if sleep mode is disabled or if internal power
* down control is enabled for SPLZVSS.
*
* @b Arguments
@verbatim
None
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Sleep mode enable/disable.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - Sleep mode disabled.
* @li 1 - Sleep mode enabled.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint32 slpMode;
slpMode = VCP2_getVssSleepMode ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_getVssSleepMode (
void
)
{
return CSL_FEXT (hVcp2->VCPEND, VCP2_VCPEND_SLPZVSS_EN);
}
/**
* ============================================================================
* @n@b VCP2_getVddSleepMode
*
* @b Description
* @n This function returns the value programmed into VCPEND register for
* sleep mode indicating if sleep mode is disabled or if internal power
* down control is enabled for SPLZVDD.
*
* @b Arguments
@verbatim
None
@endverbatim
*
* <b>Return Value </b> Value
* @li Value Sleep mode enable/disable.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n The returned value indicates
* @li 0 - Sleep mode disabled.
* @li 1 - Sleep mode enabled.
*
* @b Modifies
* @n None.
*
* @b Example
* @verbatim
Uint32 slpMode;
slpMode = VCP2_getVddSleepMode ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
Uint32 VCP2_getVddSleepMode (
void
)
{
return CSL_FEXT (hVcp2->VCPEND, VCP2_VCPEND_SLPZVDD_EN);
}
/**
* ============================================================================
* @n@b VCP2_setVssSleepMode
*
* @b Description
* @n This function either disables sleep mode or enables the internal power
* down control of SLPZVSS.
*
* @b Arguments
@verbatim
slpMode '0' to disable sleep mode and '1' to enable internal
power down control for SLPZVSS.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP endian register.
*
* @b Example
* @verbatim
VCP2_setVssSleepMode (1);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_setVssSleepMode (
Uint32 slpMode
)
{
CSL_FINS (hVcp2->VCPEND, VCP2_VCPEND_SLPZVSS_EN, slpMode);
}
/**
* ============================================================================
* @n@b VCP2_setVddSleepMode
*
* @b Description
* @n This function either disables sleep mode or enables the internal power
* down control of SLPZVDD.
*
* @b Arguments
@verbatim
slpMode '0' to disable sleep mode and '1' to enable internal
power down control for SLPZVDD.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP endian register.
*
* @b Example
* @verbatim
VCP2_setVDDSleepMode (1);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_setVddSleepMode (
Uint32 slpMode
)
{
CSL_FINS (hVcp2->VCPEND, VCP2_VCPEND_SLPZVDD_EN, slpMode);
}
/**
* ============================================================================
* @n@b VCP2_emuEnable
*
* @b Description
* @n This function enables the emulation/debug mode of VCP.
*
* @b Arguments
@verbatim
emuMode '0' to halt VCP at the end of completion of the current
window of state metric processing or at the end of a
frame. '1' to halt the VCP at the end of completion of
the processing of the frame.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n Emulation mode is enabled.
*
* @b Modifies
* @n VCP emulation control register.
*
* @b Example
* @verbatim
Uint16 emuMode = VCP2_EMUHALT_DEFAULT;
VCP2_emuEnable (emuMode);
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_emuEnable (
Uint16 emuMode
)
{
CSL_FINST (hVcp2->VCPEMU, VCP2_VCPEMU_FREE, SOFT_EN);
CSL_FINS (hVcp2->VCPEMU, VCP2_VCPEMU_SOFT, emuMode);
}
/**
* ============================================================================
* @n@b VCP2_emuDisable
*
* @b Description
* @n This function disables the emulation/debug mode of VCP.
*
* @b Arguments
@verbatim
None.
@endverbatim
*
* <b>Return Value </b>
* @n None.
*
* <b>Pre Condition </b>
* @n None.
*
* <b>Post Condition </b>
* @n None.
*
* @b Modifies
* @n VCP emulation control register.
*
* @b Example
* @verbatim
VCP2_emuDisable ();
@endverbatim
* ============================================================================
*/
CSL_IDEF_INLINE
void VCP2_emuDisable (
void
)
{
CSL_FINST (hVcp2->VCPEMU, VCP2_VCPEMU_FREE, FREE);
}
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioOpen.c | <filename>DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioOpen.c<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* provided
* ==========================================================================
*/
/** ===========================================================================
* @file csl_gpioOpen.c
*
* @path $(CSLPATH)\src\gpio
*
* @desc The CSL_gpioOpen() function definition & it's associated functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 10-jun-2004 PGR File created
* 04-Sep-2004 Nsr Updated function and documentation for CSL_gpioOpen.
* - Removed the include file, csl_resource.h.
* 11-Oct-2004 Nsr renamed the local variable "st" as "status"
* 06-Mar-2006 ds Updated the documentation
* ============================================================================
*/
#include <csl_gpio.h>
/** ============================================================================
* @n@b CSL_gpioOpen
*
* @b Description
* @n This function populates the peripheral data object for the GPIO instance
* and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of GPIO device. The device can be re-opened anytime after it has been
* normally closed if so required. The handle returned by this call is
* input as an essential argument for rest of the APIs described
* for this module.
*
* @b Arguments
* @verbatim
pGpioObj Pointer to the GPIO instance object
gpioNum Instance of the GPIO to be opened
pGpioParam Pointer to module specific parameters
pStatus pointer for returning status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_GpioHandle
* @n Valid GPIO instance handle will be returned if
status value is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n The GPIO must be successfully initialized via CSL_gpioInit() before
* calling this function.
*
* <b> Post Condition </b>
* @n 1. GPIO object structure is populated
* @n 2. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid gpio handle is returned
* @li CSL_ESYS_FAIL The gpio instance is invalid
* @li CSL_ESYS_INVPARAMS Invalid parameter
*
* @b Modifies
* @n 1. The status variable
* @n 2. GPIO object structure
*
* @b Example
* @verbatim
CSL_Status status;
CSL_GpioObj gpioObj;
CSL_GpioHandle hGpio;
...
hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO, NULL, &status);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_gpioOpen, ".text:csl_section:gpio");
CSL_GpioHandle CSL_gpioOpen (
CSL_GpioObj *pGpioObj,
CSL_InstNum gpioNum,
CSL_GpioParam *pGpioParam,
CSL_Status *pStatus
)
{
CSL_GpioHandle hGpio = (CSL_GpioHandle)NULL;
CSL_GpioBaseAddress baseAddress;
if (pStatus == NULL) {
/* do nothing : already the module is initialized to NULL */
}
else if (pGpioObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
*pStatus = CSL_gpioGetBaseAddress(gpioNum, pGpioParam, &baseAddress);
if (*pStatus == CSL_SOK) {
pGpioObj->regs = baseAddress.regs;
pGpioObj->gpioNum = (CSL_InstNum)gpioNum;
pGpioObj->numPins = CSL_GPIO_NUM_PINS;
hGpio = (CSL_GpioHandle)pGpioObj;
}
else {
pGpioObj->regs = (CSL_GpioRegsOvly)NULL;
pGpioObj->gpioNum = (CSL_InstNum)-1;
}
}
return (hGpio);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaGetHwSetup.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_emifaGetHwSetup.c
*
* @path $(CSLPATH)\src\emifa
*
* $desc File for functional layer of CSL API @a CSL_emifaGetHwSetup()
* - The @a CSL_emifaGetHwSetup() function definition & it's
* associated functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 12-May-2005 RM File Created.
*
* 09-Sep-2005 NG Updation according to coding guidelines
*
* =============================================================================
*/
#include <csl_emifa.h>
/** ============================================================================
* @n@b CSL_emifaGetHwSetup
*
* @b Description
* @n This function gets the current setup of the EMIFA. The status is
* returned through @a CSL_EmifaHwSetup. The obtaining of status
* is the reverse operation of @a CSL_emifaHwSetup() function.
*
* @b Arguments
* @verbatim
hEmifa Pointer to the object that holds reference to the
instance of EMIFA requested after the call
setup Pointer to setup structure which contains the
information to program EMIFA to a useful state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware status call is
* successful
* @li CSL_ESYS_FAIL - The external memory interface
* instance is not available.
* @li CSL_ESYS_INVPARAMS - Parameters are not valid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling @a CSL_emifaGetHwSetup().
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Second parameter setup
*
* @b Example:
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_Status status;
CSL_EmifaHwSetup hwSetup;
CSL_EmifaAsync asyncMem;
CSL_EmifaMemType value;
CSL_EmifaAsyncWait asyncWait;
value.ssel = 0;
value.async = &asyncMem;
value.sync = NULL;
hwSetup.asyncWait = &asyncWait;
hwSetup.ceCfg [0] = &value;
hwSetup.ceCfg [1] = NULL;
hwSetup.ceCfg [2] = NULL;
hwSetup.ceCfg [3] = NULL;
//Initialize the Emifa CSL
//Open Emifa Module
status = CSL_emifaGetHwSetup(hEmifa, &hwSetup);
@endverbatim
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_emifaGetHwSetup, ".text:csl_section:emifa")
CSL_Status CSL_emifaGetHwSetup (
CSL_EmifaHandle hEmifa,
CSL_EmifaHwSetup *setup
)
{
Uint8 loop;
volatile Uint32* ceCfgBaseAddr=0;
CSL_Status status = CSL_SOK;
/* invalid parameter checking */
if (setup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else if (hEmifa == NULL) {
/* bad handle checking */
status = CSL_ESYS_BADHANDLE;
}
else {
/* Get Async config */
if (setup->asyncWait != NULL) {
setup->asyncWait->asyncRdyPol =
(CSL_EmifaArdyPol)CSL_FEXT(hEmifa->regs->AWCC, EMIFA_AWCC_AP);
setup->asyncWait->turnArnd =
(Uint8)CSL_FEXT(hEmifa->regs->AWCC, EMIFA_AWCC_TA);
setup->asyncWait->maxExtWait =
(Uint8)CSL_FEXT(hEmifa->regs->AWCC, EMIFA_AWCC_MAX_EXT_WAIT);
}
ceCfgBaseAddr = &(hEmifa->regs->CE2CFG);
for (loop=0; loop < NUMCHIPENABLE; loop++) {
if (setup->ceCfg[loop] != NULL)
{
if ((setup->ceCfg[loop]->ssel == 0) &&
(setup->ceCfg[loop]->async != NULL) &&
(!((Uint8)CSL_FEXT(*(ceCfgBaseAddr + loop),
EMIFA_CE2CFG_SSEL))))
{
setup->ceCfg[loop]->async->selectStrobe = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_SS);
setup->ceCfg[loop]->async->weMode = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_BWEM);
setup->ceCfg[loop]->async->asyncRdyEn = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_AE);
setup->ceCfg[loop]->async->wSetup = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_W_SETUP);
setup->ceCfg[loop]->async->wStrobe = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_W_STROBE);
setup->ceCfg[loop]->async->wHold = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_W_HOLD);
setup->ceCfg[loop]->async->rSetup = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_R_SETUP);
setup->ceCfg[loop]->async->rStrobe = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_R_STROBE);
setup->ceCfg[loop]->async->rHold = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_R_HOLD);
setup->ceCfg[loop]->async->asize = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_ASIZE);
}
if ((setup->ceCfg[loop]->ssel == 1) &&
(setup->ceCfg[loop]->sync != NULL) &&
((Uint8)CSL_FEXT(*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_SSEL)))
{
setup->ceCfg[loop]->sync->readByteEn = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_RD_BE_EN);
setup->ceCfg[loop]->sync->chipEnExt = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_CE_EXT);
setup->ceCfg[loop]->sync->readEn = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_R_ENABLE);
setup->ceCfg[loop]->sync->w_ltncy = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_W_LTNCY);
setup->ceCfg[loop]->sync->r_ltncy = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_R_LTNCY);
setup->ceCfg[loop]->sync->sbsize = (Uint8)CSL_FEXT(
*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_SBSIZE);
}
else {
status = CSL_ESYS_FAIL;
}
}
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/cache/csl_cacheL2.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_cacheL2.c
*
* @path $(CSLPATH)\src\cache
*
* @desc File for functional layer of L2 Cache
*
*/
/* =============================================================================
* Revision History
* ===============
* 23-Mar-2004 <NAME> File Created
*
* 21-Jun-2004 <NAME> modified
*
* 24-Jan-2006 ds Updated CACHE_setL2Size() API to return Old value
* =============================================================================
*/
#include <csl_cache.h>
#include <_csl_cache.h>
/** ============================================================================
* @n@b CACHE_setL2Size
*
* @b Description
* @n Sets the L2 size.
* @n As per the specification,
* @n a. The old size is read from the L2CFG.
* @n b. The new size is programmed in L2CFG.
* @n c. L2CFG is read back to ensure it is set.
*
* @b Arguments
* @verbatim
newSize New memory size to be programmed
@endverbatim
*
* <b> Return Value </b> CACHE_L2Size
* @li Old Size set for L2
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Set L2 cache size
*
* @b Modifies
* @n L2CFG register
*
* @b Example
* @verbatim
...
CACHE_L2Size oldSize ;
oldSize = CACHE_setL2Size(CACHE_L2_32KCACHE);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_setL2Size, ".text:csl_section:cache");
CACHE_L2Size CACHE_setL2Size (
CACHE_L2Size newSize
)
{
Uint32 curL2cfg;
CACHE_L2Size returnVal;
curL2cfg = ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2CFG;
returnVal = (CACHE_L2Size) CSL_FEXT(curL2cfg, CACHE_L2CFG_MODE);
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2CFG =
CSL_FINS(curL2cfg, CACHE_L2CFG_MODE, newSize);
newSize = (CACHE_L2Size)((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2CFG;
/* End critical section */
asm(" rint");
return returnVal;
}
/** ============================================================================
* @n@b CACHE_setL2Mode
*
* @b Description
* @n Sets the L2 mode.
* @n As per the specification,
* @n a. The old mode is read from the L2CFG.
* @n b. The new mode is programmed in L2CFG.
* @n c. L2CFG is read back to ensure it is set.
*
* @b Arguments
* @verbatim
newMode New mode to be programmed
@endverbatim
*
* <b> Return Value </b> CACHE_L2Mode
* @li Old Mode set for L2
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Set L2 cache mode
*
* @b Modifies
* @n L2CFG register
*
* @b Example
* @verbatim
...
CACHE_L2Mode oldMode;
oldMode = CACHE_setL2Mode(CACHE_L2_NORMAL);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_setL2Mode, ".text:csl_section:cache");
CACHE_L2Mode CACHE_setL2Mode(
CACHE_L2Mode newMode
)
{
Uint32 oldval;
CACHE_L2Mode returnVal;
/* critical section */
asm(" dint");
oldval = ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2CFG;
returnVal = (CACHE_L2Mode)(CSL_FEXT(oldval,CACHE_L2CFG_L2CC));
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2CFG =
CSL_FINS(oldval,CACHE_L2CFG_L2CC, newMode);
oldval = ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2CFG;
/* End critical section */
asm(" rint");
return returnVal;
}
/** ============================================================================
* @n@b CACHE_wbL2
*
* @b Description
* @n Writes back range specified in L2.
* @n As per the specification,
* @n a. The start of the range that needs to be written back is programmed
* into L2WBAR.
* @n b. The byte count is programmed in L2WWC.
*
* @b Arguments
* @verbatim
blockPtr Start address of range to be written back
byteCnt Number of bytes to be written back
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed or not.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Writeback the L2 cache
*
* @b Modifies
* @n L2WWC and L2WBAR registers
*
* @b Example
* @verbatim
...
CACHE_wbL2((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wbL2, ".text:csl_section:cache");
void CACHE_wbL2 (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WBAR = (Uint32)blockPtr;
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WWC =((byteCnt+3)>>2);
_CSL_cachebusyState = CACHE_WAIT_L2WB;
_CSL_cacheEmifState =
(CACHE_emifState)(CSL_CACHE_EMIF_ISRANGE((Uint32)blockPtr) \
+ CSL_CACHE_EMIF_ISEMIFBRANGE((Uint32)blockPtr));
/* End critical section */
asm(" rint");
if(wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_invL2
*
* @b Description
* @n Invalidates range specified in L2.
* @n As per the specification,
* @n a. The start of the range that needs to be written back is programmed
* into L2IBAR
* @n b. The byte count is programmed in L2IWC.
*
* @b Arguments
* @verbatim
blockPtr Start address of range to be invalidated
byteCnt Number of bytes to be invalidated
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed or not.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Invalidate the L2 cache
*
* @b Modifies
* @n L2IBAR and L2IWC registers
*
* @b Example
* @verbatim
...
CACHE_invL2((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_invL2, ".text:csl_section:cache");
void CACHE_invL2 (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2IBAR = (Uint32)blockPtr;
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2IWC = ((byteCnt+3)>>2);
_CSL_cachebusyState = CACHE_WAIT_L2INV;
/* End critical section */
asm(" rint");
if(wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_wbInvL2
*
* @b Description
* @n Writeback invalidated range specified in L2.
* @n As per the specification,
* @n a. The start of the range that needs to be written back is programmed
* into L2WIBAR
* @n b. The byte count is programmed in L2WIWC.
*
* @b Arguments
* @verbatim
blockPtr Start address of range to be written back invalidated
byteCnt Number of bytes to be written back invalidated
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed or not.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Writeback and invalidate the L2 cache
*
* @b Modifies
* @n L2WIBAR and L2WIWC registers
*
* @b Example
* @verbatim
...
CACHE_wbInvL2((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wbInvL2, ".text:csl_section:cache");
void CACHE_wbInvL2 (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WIBAR = (Uint32)blockPtr;
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WIWC = ((byteCnt+3)>>2);
_CSL_cachebusyState = CACHE_WAIT_L2WBINV;
_CSL_cacheEmifState =
(CACHE_emifState)(CSL_CACHE_EMIF_ISRANGE((Uint32)blockPtr) \
+ CSL_CACHE_EMIF_ISEMIFBRANGE((Uint32)blockPtr));
/* End critical section */
asm(" rint");
if(wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_wbAllL2
*
* @b Description
* @n Writes back all of L2.
* @n As per the specification,
* @n a. The L2WB needs to be programmed.
*
* @b Arguments
* @verbatim
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed or not.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Writeback all L2 cache
*
* @b Modifies
* @n L2WB register
*
* @b Example
* @verbatim
...
CACHE_wbAllL2(CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wbAllL2, ".text:csl_section:cache");
void CACHE_wbAllL2 (
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WB = 1;
_CSL_cachebusyState = CACHE_WAIT_L2WBALL;
_CSL_cacheEmifState = CACHE_EMIF_AB;
/* End critical section */
asm(" rint");
if(wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_invAllL2
*
* @b Description
* @n Invalidates All of L2.
* @n As per the specification,
* @n a. The L2INV needs to be programmed.
*
* @b Arguments
* @verbatim
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed or not.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Invalidate all L2 cache
*
* @b Modifies
* @n L2INV register
*
* @b Example
* @verbatim
...
CACHE_invAllL2(CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_invAllL2, ".text:csl_section:cache");
void CACHE_invAllL2 (
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2INV = 1;
_CSL_cachebusyState = CACHE_WAIT_L2INVALL;
asm(" rint");
/* End critical section */
if(wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_wbInvAllL2
*
* @b Description
* @n Writeback invalidates All of L2.
* @n As per the specification,
* @n a. The L2WBINV needs to be programmed.
*
* @b Arguments
* @verbatim
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed or not.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Writeback and invalidate all the L2 cache
*
* @b Modifies
* @n L2WBINV register
*
* @b Example
* @verbatim
...
CACHE_wbInvAllL2(CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wbInvAllL2, ".text:csl_section:cache");
void CACHE_wbInvAllL2 (
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WBINV = 1;
_CSL_cachebusyState = CACHE_WAIT_L2WBINVALL;
_CSL_cacheEmifState = CACHE_EMIF_AB;
/* End critical section */
asm(" rint");
if(wait)
_CACHE_wait(wait);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtHwControl.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* priovided
* ============================================================================
*/
/** ===========================================================================
* @file csl_bwmngmtHwControl.c
*
* @brief File for functional layer of CSL API @a CSL_bwmngmtHwControl()
*
* @path $(CSLPATH)\bwmngmt\src
*
* Description
* - The @a CSL_bwmngmtHwControl() function definition & it's associated
* functions
*
* @date 17 Mar, 2006
* @author PSK
* =============================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 17-Mar-2006 PSK file created
* =============================================================================
*/
#include <csl_bwmngmt.h>
/** ============================================================================
* @n@b CSL_bwmngmtHwControl
*
* @b Description
* @n Takes a command of BWMNGMT with an optional argument & implements it.
* Not Implemented. For future use.
*
* @b Arguments
* @verbatim
hBwmngmt Handle to the BWMNGMT instance
cmd The command to this API indicates the action to
be taken on BWMNGMT
cmdArg An optional argument
@endverbatim
*
* <b> Return Value </b> CSL_Status
* CSL_SOK - Always returns
*
*
* <b> Pre Condition </b>
* Both CSL_bwmngmtInit() and CSL_bwmngmtOpen() must
* be called successfully in that order before this function can be called
*
* <b> Post Condition </b>
* None
* @b Modifies
* None
* @b Examples:
* @verbatim
CSL_BwmngmtHandle hBwmngmt;
CSL_bwmngmtHwControl cmd;
// Init Successfully done
...
// Open Successfully done
...
CSL_bwmngmtHwControl(hBwmngmt, cmd, NULL);
@endverbatim
*
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_bwmngmtHwControl, ".text:csl_section:bwmngmt");
CSL_Status CSL_bwmngmtHwControl (
/* pointer to the object that holds reference to the
* instance of BWMNGMT requested after the call */
CSL_BwmngmtHandle hBwmngmt,
/* pointer to setup structure which contains the
* information to program BWMNGMT to a useful state */
CSL_BwmngmtHwControlCmd cmd,
void *arg
)
{
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cGetHwStatus.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_i2cGetHwStatus.c
*
* @brief File for functional layer of CSL API CSL_i2cGetHwStatus()
*
* @path $(CSLPATH)\i2c\src
*
* Description
* - The CSL_i2cGetHwStatus() function definition & it's associated
* functions
*
* Modification 1
* - Modified on: 28/5/2004
* - Reason: created the sources
*
* @date 28th May, 2004
* @author <NAME>.
*/
/* =============================================================================
* Revision History
* ===============
* 06-Feb-2006 ds Removed CSL_I2C_QUERY_REV, CSL_I2C_QUERY_CLASS and
* CSL_I2C_QUERY_TYPE queries
*
* =============================================================================
*/
#include <csl_i2c.h>
#include <csl_i2cAux.h>
/** ============================================================================
* @n@b CSL_i2cGetHwStatus
*
* @b Description
* @n This function is used to read the current device configuration, status
* flags and the value present associated registers.Following table details
* the various status queries supported and the associated data structureto
* record the response. User should allocate memory for the said data type
* and pass its pointer as an unadorned void* argument to the status query
* call.For details about the various status queries supported and the
* associated data structure to record the response,
* refer to @a CSL_I2cHwStatusQuery
*
* @b Arguments
* @verbatim
hI2c Handle to the I2C instance
query The query to this API of I2C which indicates the
status to be returned.
response Placeholder to return the status.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVQUERY - Invalid query command
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully
* in that order before @a CSL_i2cGetHwStatus() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_I2cHandle hI2c;
CSL_I2cHwStatusQuery query;
void reponse;
status = CSL_i2cGetHwStatus(hI2c, query, &response);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_i2cGetHwStatus, ".text:csl_section:i2c")
CSL_Status CSL_i2cGetHwStatus (
CSL_I2cHandle hI2c,
CSL_I2cHwStatusQuery query,
void *response
)
{
CSL_Status status = CSL_SOK;
if (hI2c == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (query) {
case CSL_I2C_QUERY_CLOCK_SETUP:
CSL_i2cGetClockSetup(hI2c, response);
break;
case CSL_I2C_QUERY_BUS_BUSY:
CSL_i2cGetBusBusy(hI2c, response);
break;
case CSL_I2C_QUERY_RX_RDY:
CSL_i2cGetRxRdy(hI2c, response);
break;
case CSL_I2C_QUERY_TX_RDY:
CSL_i2cGetTxRdy(hI2c, response);
break;
case CSL_I2C_QUERY_ACS_RDY:
CSL_i2cGetAcsRdy(hI2c, response);
break;
case CSL_I2C_QUERY_SCD:
CSL_i2cGetScd(hI2c, response);
break;
case CSL_I2C_QUERY_AD0:
CSL_i2cGetAd0(hI2c, response);
break;
case CSL_I2C_QUERY_AAS:
CSL_i2cGetAas(hI2c, response);
break;
case CSL_I2C_QUERY_RSFULL:
CSL_i2cGetRsFull (hI2c, response);
break;
case CSL_I2C_QUERY_XSMT:
CSL_i2cGetXsmt(hI2c, response);
break;
case CSL_I2C_QUERY_AL:
CSL_i2cGetAl(hI2c, response);
break;
case CSL_I2C_QUERY_SDIR:
CSL_i2cGetSdir(hI2c, response);
break;
case CSL_I2C_QUERY_NACKSNT:
CSL_i2cGetNacksnt(hI2c, response);
break;
case CSL_I2C_QUERY_RDONE:
CSL_i2cGetRdone(hI2c, response);
break;
case CSL_I2C_QUERY_BITCOUNT:
CSL_i2cGetBitcount(hI2c, response);
break;
case CSL_I2C_QUERY_INTCODE:
CSL_i2cGetIntcode(hI2c, response);
break;
default:
status = CSL_ESYS_INVQUERY ;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/emifa/src/Emifa_ReadWrite_example.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
*
* @file Emifa_ReadWrite_example.c
*
* @path $(CSLPATH)\example\emifa\src
*
* @desc Example of EMIFA
*
* ============================================================================
* @n Target Platform: VDB
* ============================================================================
* @n <b> Example Description </b>
* @n This example,
* 1. Sets up for asynchronous and synchronous type
* 2. Initializes and opens the CSL EMFIA module.
* 3. Sets up the hardware parameter
* 4. Writes the Invalid values into EMIFA CS2 area to over write the
* previous values.
* 5. Writes valid data into CS2 area.
* 6. Does the data comparision to ensure the written data is proper or
* not and
* 7. Displays the messages based on step 6
* 8. Steps 4 to 7 is repeated to write the Data into CS4 area
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Emifa_ReadWrite_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 21-May-2005 <NAME>. created
* 20-Jul-2005 RM Module name changed from EMIF64 to EMIFA
* 30-Nov-2005 NG Updated documentation
* 06-Feb-2006 ds Async and sync start areas has changed to CE3 loaction
* =============================================================================
*/
#include <csl_emifa.h>
#include <cslr_dev.h>
#include <stdio.h>
/* Success Flag for data comparision */
#define DATA_MATCH_SUCCESS 1
/* Result - Failed */
#define DATA_MATCH_FAIL 0
/* Data count(number write/readbacks) */
#define DATA_CNT 10
/* Base address of the EMIFA CE3 */
#define EMIFA_CE3_BASE_ADDR (0xB0000000u)
#define EMIFA_MEMTYPE_ASYNC 0
#define EMIFA_MEMTYPE_SYNC 1
/* Handle for the EMIFA instance */
CSL_EmifaHandle hEmifa;
/* Locals & Forwards */
void emifaReadWrite(void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main (
void
)
{
/* Enable EMIFA */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG1, DEV_PERCFG1_EMIFACTL, \
ENABLE);
emifaReadWrite();
return;
}
/*
* =============================================================================
* @func emifaReadWrite
*
* @arg
* NONE
*
* @desc
* This function demonstrates the functionality of EMIFA with the setup
* It implements following steps
* 1. Opens the EMIFA module CSL
* 2. The CSL_emifaHwSetup is called for module configuration
* 3. It writes into CE4 area configured for synchronous memory and
* CE2 area configured for asynchronous memory reads back, to make
* sure the data is indeed written.
* 4. EMIFA module CSL is closed.
*
* @return
* NONE
*
* =============================================================================
*/
void emifaReadWrite (
void
)
{
Uint32 result, index, tempData;
CSL_EmifaObj emifaObj;
CSL_Status status;
CSL_EmifaHwSetup hwSetup ;
CSL_EmifaMemType asyncVal, syncVal;
CSL_EmifaAsyncWait asyncWait = CSL_EMIFA_ASYNCWAIT_DEFAULTS;
CSL_EmifaAsync asyncMem = CSL_EMIFA_ASYNCCFG_DEFAULTS;
CSL_EmifaSync syncMem = CSL_EMIFA_SYNCCFG_DEFAULTS;
/* Pointer that points to Async(CE3) start area */
Uint32 *pAsyncData = (Uint32 *)EMIFA_CE3_BASE_ADDR;
/* Pointer that points to Sync(CE3) start area */
Uint32 *pSyncData = (Uint32 *)EMIFA_CE3_BASE_ADDR;
/* Clear local data structures */
memset(&emifaObj, 0, sizeof(CSL_EmifaObj));
memset(&hwSetup, 0, sizeof(CSL_EmifaHwSetup));
/* setting for asynchronous type */
asyncVal.ssel = EMIFA_MEMTYPE_ASYNC;
asyncVal.async = &asyncMem;
asyncVal.sync = NULL;
/* setting for synchronous type */
syncVal.ssel = EMIFA_MEMTYPE_SYNC;
syncVal.async = NULL;
syncVal.sync = &syncMem;
/* setup the hardware parameters */
hwSetup.asyncWait = &asyncWait;
hwSetup.ceCfg[0] = &asyncVal;
hwSetup.ceCfg[1] = NULL;
hwSetup.ceCfg[2] = &syncVal;
hwSetup.ceCfg[3] = NULL;
printf("\tInfo: Read-Write operations of EMIFA \n");
/* Initialize EMIFA CSL module */
status = CSL_emifaInit(NULL);
if (status != CSL_SOK) {
printf("EMIFA: Initialization error.\n");
printf("\tReason: CSL_emifaInit [status = 0x%x].\n", status);
return;
}
else {
printf("EMIFA: Module Initialized.\n");
}
/* Opening the EMIFA instance */
hEmifa = CSL_emifaOpen(&emifaObj, CSL_EMIFA, NULL, &status);
if ((status != CSL_SOK) || (hEmifa == NULL)) {
printf("EMIFA: Error opening the instance. [status = 0x%x, hEmifa \
= 0x%x]\n", status, hEmifa);
return;
}
else {
printf("EMIFA: Module instance opened.\n");
}
/* Setting up configuration parameter using HwSetup */
status = CSL_emifaHwSetup(hEmifa, &hwSetup);
if (status != CSL_SOK) {
printf("EMIFA: Error in HW Setup.\n");
printf("Read write operation fails\n");
return;
}
else {
printf("EMIFA: Module Hardware setup is successful.\n");
}
printf("\tInfo: Async read write \n");
/* Write 'invalid' values into EMIFA CS2 area. This is to overwrite the
* previous valid values.
*/
tempData = 0xdeadbeef;
for (index = 0; index < DATA_CNT; index++) {
pAsyncData[index] = tempData;
}
/* Write **valid** values into CS2 area. */
tempData = 0x55550000;
for (index = 0; index < DATA_CNT; index++) {
pAsyncData[index] = tempData + index;
}
/* Verify that the data was indeed written */
result = DATA_MATCH_SUCCESS;
for (index = 0; index < DATA_CNT; index++) {
if (pAsyncData[index] != (tempData + index)) {
result = DATA_MATCH_FAIL;
break ;
}
}
/* Print the appropriate messages */
if (result == DATA_MATCH_SUCCESS) {
printf("\nAsynchronous Read Write is Successful\n");
}
else {
printf("\nAsynchronous Read Write is NOT Successful\n");
}
printf("\tInfo: Sync read write \n");
/* Write 'invalid' values into EMIFA CS4 area. This is to overwrite the
* previous valid values.
*/
tempData = 0xdeadbeef;
for (index = 0; index < DATA_CNT; index++) {
pSyncData[index] = tempData;
}
/* Write **valid** values into CS4 area. */
tempData = 0x56780000;
for (index = 0; index < DATA_CNT; index++) {
pSyncData[index] = tempData + index ;
}
/* Verify that the data was indeed written */
result = DATA_MATCH_SUCCESS;
for (index = 0; index < DATA_CNT; index++) {
if (pSyncData[index] != (tempData + index)) {
result = DATA_MATCH_FAIL;
break ;
}
}
/* Print the appropriate messages */
if (result == DATA_MATCH_SUCCESS) {
printf("\nSync Read Write is Successful\n");
}
else {
printf("\nSync Read Write is NOT Successful\n");
printf("\tReason:Error in data read.[status = 0x%x]\n", status);
}
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_dev.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_dev.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for DEV
*/
#ifndef _CSLR_DEV_H_
#define _CSLR_DEV_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 DEVSTAT;
volatile Uint32 PRI_ALLOC;
volatile Uint32 JTAGID;
volatile Uint8 RSVD0[262136];
volatile Uint32 PERLOCK;
volatile Uint32 PERCFG0;
volatile Uint8 RSVD1[8];
volatile Uint32 PERSTAT0;
volatile Uint32 PERSTAT1;
volatile Uint8 RSVD2[4];
volatile Uint32 EMACCFG;
volatile Uint8 RSVD3[8];
volatile Uint32 PERCFG1;
volatile Uint8 RSVD4[36];
volatile Uint32 EMUBUFPDN;
} CSL_DevRegs;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* DEVSTAT */
#define CSL_DEV_DEVSTAT_EMIFA_EN_MASK (0x00400000u)
#define CSL_DEV_DEVSTAT_EMIFA_EN_SHIFT (0x00000016u)
#define CSL_DEV_DEVSTAT_EMIFA_EN_RESETVAL (0x00000000u)
/*----EMIFA_EN Tokens----*/
#define CSL_DEV_DEVSTAT_EMIFA_EN_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_EMIFA_EN_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_DDR2_EN_MASK (0x00200000u)
#define CSL_DEV_DEVSTAT_DDR2_EN_SHIFT (0x00000015u)
#define CSL_DEV_DEVSTAT_DDR2_EN_RESETVAL (0x00000000u)
/*----DDR2_EN Tokens----*/
#define CSL_DEV_DEVSTAT_DDR2_EN_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_DDR2_EN_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_PCI_EN_MASK (0x00100000u)
#define CSL_DEV_DEVSTAT_PCI_EN_SHIFT (0x00000014u)
#define CSL_DEV_DEVSTAT_PCI_EN_RESETVAL (0x00000000u)
/*----PCI_EN Tokens----*/
#define CSL_DEV_DEVSTAT_PCI_EN_HPI (0x00000000u)
#define CSL_DEV_DEVSTAT_PCI_EN_PCI (0x00000001u)
#define CSL_DEV_DEVSTAT_CFGGP_MASK (0x000E0000u)
#define CSL_DEV_DEVSTAT_CFGGP_SHIFT (0x00000011u)
#define CSL_DEV_DEVSTAT_CFGGP_RESETVAL (0x00000000u)
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_MASK (0x00008000u)
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_SHIFT (0x0000000Fu)
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_RESETVAL (0x00000000u)
/*----SYSCLKOUT_EN Tokens----*/
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_GP1 (0x00000000u)
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_SYSCLK4 (0x00000001u)
#define CSL_DEV_DEVSTAT_MCBSP1_EN_MASK (0x00004000u)
#define CSL_DEV_DEVSTAT_MCBSP1_EN_SHIFT (0x0000000Eu)
#define CSL_DEV_DEVSTAT_MCBSP1_EN_RESETVAL (0x00000000u)
/*----MCBSP1_EN Tokens----*/
#define CSL_DEV_DEVSTAT_MCBSP1_EN_GPIO (0x00000000u)
#define CSL_DEV_DEVSTAT_MCBSP1_EN_MCBSP_1 (0x00000001u)
#define CSL_DEV_DEVSTAT_PCI66_MASK (0x00002000u)
#define CSL_DEV_DEVSTAT_PCI66_SHIFT (0x0000000Du)
#define CSL_DEV_DEVSTAT_PCI66_RESETVAL (0x00000000u)
/*----PCI66 Tokens----*/
#define CSL_DEV_DEVSTAT_PCI66_33MHZ (0x00000000u)
#define CSL_DEV_DEVSTAT_PCI66_66MHZ (0x00000001u)
#define CSL_DEV_DEVSTAT_PCI_EEAI_MASK (0x00000800u)
#define CSL_DEV_DEVSTAT_PCI_EEAI_SHIFT (0x0000000Bu)
#define CSL_DEV_DEVSTAT_PCI_EEAI_RESETVAL (0x00000000u)
/*----PCI_EEAI Tokens----*/
#define CSL_DEV_DEVSTAT_PCI_EEAI_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_PCI_EEAI_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_MACSEL_MASK (0x00000600u)
#define CSL_DEV_DEVSTAT_MACSEL_SHIFT (0x00000009u)
#define CSL_DEV_DEVSTAT_MACSEL_RESETVAL (0x00000000u)
/*----MACSEL Tokens----*/
#define CSL_DEV_DEVSTAT_MACSEL_MII (0x00000000u)
#define CSL_DEV_DEVSTAT_MACSEL_RMII (0x00000001u)
#define CSL_DEV_DEVSTAT_MACSEL_GMII (0x00000002u)
#define CSL_DEV_DEVSTAT_MACSEL_RGMII (0x00000003u)
#define CSL_DEV_DEVSTAT_UTOPIA_EN_MASK (0x00000080u)
#define CSL_DEV_DEVSTAT_UTOPIA_EN_SHIFT (0x00000007u)
#define CSL_DEV_DEVSTAT_UTOPIA_EN_RESETVAL (0x00000000u)
/*----UTOPIA_EN Tokens----*/
#define CSL_DEV_DEVSTAT_UTOPIA_EN_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_UTOPIA_EN_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_LENDIAN_MASK (0x00000040u)
#define CSL_DEV_DEVSTAT_LENDIAN_SHIFT (0x00000006u)
#define CSL_DEV_DEVSTAT_LENDIAN_RESETVAL (0x00000001u)
/*----LENDIAN Tokens----*/
#define CSL_DEV_DEVSTAT_LENDIAN_BE (0x00000000u)
#define CSL_DEV_DEVSTAT_LENDIAN_LE (0x00000001u)
#define CSL_DEV_DEVSTAT_HPI_WIDTH_MASK (0x00000020u)
#define CSL_DEV_DEVSTAT_HPI_WIDTH_SHIFT (0x00000005u)
#define CSL_DEV_DEVSTAT_HPI_WIDTH_RESETVAL (0x00000000u)
/*----HPI_WIDTH Tokens----*/
#define CSL_DEV_DEVSTAT_HPI_WIDTH_16BIT (0x00000000u)
#define CSL_DEV_DEVSTAT_HPI_WIDTH_32BIT (0x00000001u)
#define CSL_DEV_DEVSTAT_AECLKINSEL_MASK (0x00000010u)
#define CSL_DEV_DEVSTAT_AECLKINSEL_SHIFT (0x00000004u)
#define CSL_DEV_DEVSTAT_AECLKINSEL_RESETVAL (0x00000000u)
/*----AECLKINSEL Tokens----*/
#define CSL_DEV_DEVSTAT_AECLKINSEL_AECLKIN (0x00000000u)
#define CSL_DEV_DEVSTAT_AECLKINSEL_SYSCLK4 (0x00000001u)
#define CSL_DEV_DEVSTAT_BOOTMODE_MASK (0x0000000Fu)
#define CSL_DEV_DEVSTAT_BOOTMODE_SHIFT (0x00000000u)
#define CSL_DEV_DEVSTAT_BOOTMODE_RESETVAL (0x00000000u)
/*----BOOTMODE Tokens----*/
#define CSL_DEV_DEVSTAT_BOOTMODE_NONE (0x00000000u)
#define CSL_DEV_DEVSTAT_BOOTMODE_HPI (0x00000001u)
#define CSL_DEV_DEVSTAT_BOOTMODE_EMIFA8BIT (0x00000004u)
#define CSL_DEV_DEVSTAT_BOOTMODE_MASTER_I2C (0x00000005u)
#define CSL_DEV_DEVSTAT_BOOTMODE_SLAVE_I2C (0x00000006u)
#define CSL_DEV_DEVSTAT_BOOTMODE_PCI (0x00000007u)
#define CSL_DEV_DEVSTAT_BOOTMODE_SRIO (0x00000008u)
#define CSL_DEV_DEVSTAT_RESETVAL (0x00000040u)
/* PRI_ALLOC */
#define CSL_DEV_PRI_ALLOC_SRIO_MASK (0x00000E00u)
#define CSL_DEV_PRI_ALLOC_SRIO_SHIFT (0x00000009u)
#define CSL_DEV_PRI_ALLOC_SRIO_RESETVAL (0x00000000u)
#define CSL_DEV_PRI_ALLOC_HOST_MASK (0x00000038u)
#define CSL_DEV_PRI_ALLOC_HOST_SHIFT (0x00000003u)
#define CSL_DEV_PRI_ALLOC_HOST_RESETVAL (0x00000000u)
#define CSL_DEV_PRI_ALLOC_EMAC_MASK (0x00000007u)
#define CSL_DEV_PRI_ALLOC_EMAC_SHIFT (0x00000000u)
#define CSL_DEV_PRI_ALLOC_EMAC_RESETVAL (0x00000000u)
#define CSL_DEV_PRI_ALLOC_RESETVAL (0x00000000u)
/* JTAGID */
#define CSL_DEV_JTAGID_VARIANT_MASK (0xF0000000u)
#define CSL_DEV_JTAGID_VARIANT_SHIFT (0x0000001Cu)
#define CSL_DEV_JTAGID_VARIANT_RESETVAL (0x00000000u)
#define CSL_DEV_JTAGID_PARTNUMBER_MASK (0x0FFFF000u)
#define CSL_DEV_JTAGID_PARTNUMBER_SHIFT (0x0000000Cu)
#define CSL_DEV_JTAGID_PARTNUMBER_RESETVAL (0x0000008Au)
#define CSL_DEV_JTAGID_MANUFACTURER_MASK (0x00000FFEu)
#define CSL_DEV_JTAGID_MANUFACTURER_SHIFT (0x00000001u)
#define CSL_DEV_JTAGID_MANUFACTURER_RESETVAL (0x00000017u)
#define CSL_DEV_JTAGID_LSB_MASK (0x00000001u)
#define CSL_DEV_JTAGID_LSB_SHIFT (0x00000000u)
#define CSL_DEV_JTAGID_LSB_RESETVAL (0x00000001u)
#define CSL_DEV_JTAGID_RESETVAL (0x0008A02Fu)
/* PERLOCK */
#define CSL_DEV_PERLOCK_LOCKVAL_MASK (0xFFFFFFFFu)
#define CSL_DEV_PERLOCK_LOCKVAL_SHIFT (0x00000000u)
#define CSL_DEV_PERLOCK_LOCKVAL_RESETVAL (0xF0F0F0F0u)
/*----LOCKVAL Tokens----*/
#define CSL_DEV_PERLOCK_LOCKVAL_UNLOCK (0x0F0A0B00u)
#define CSL_DEV_PERLOCK_RESETVAL (0xF0F0F0F0u)
/* PERCFG0 */
#define CSL_DEV_PERCFG0_SRIOCTL_MASK (0xC0000000u)
#define CSL_DEV_PERCFG0_SRIOCTL_SHIFT (0x0000001Eu)
#define CSL_DEV_PERCFG0_SRIOCTL_RESETVAL (0x00000000u)
/*----SRIOCTL Tokens----*/
#define CSL_DEV_PERCFG0_SRIOCTL_ENABLE (0x00000003u)
#define CSL_DEV_PERCFG0_UTOPIACTL_MASK (0x00400000u)
#define CSL_DEV_PERCFG0_UTOPIACTL_SHIFT (0x00000016u)
#define CSL_DEV_PERCFG0_UTOPIACTL_RESETVAL (0x00000000u)
/*----UTOPIACTL Tokens----*/
#define CSL_DEV_PERCFG0_UTOPIACTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_PCICTL_MASK (0x00100000u)
#define CSL_DEV_PERCFG0_PCICTL_SHIFT (0x00000014u)
#define CSL_DEV_PERCFG0_PCICTL_RESETVAL (0x00000000u)
/*----PCICTL Tokens----*/
#define CSL_DEV_PERCFG0_PCICTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_HPICTL_MASK (0x00040000u)
#define CSL_DEV_PERCFG0_HPICTL_SHIFT (0x00000012u)
#define CSL_DEV_PERCFG0_HPICTL_RESETVAL (0x00000000u)
/*----HPICTL Tokens----*/
#define CSL_DEV_PERCFG0_HPICTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_MCBSP1CTL_MASK (0x00010000u)
#define CSL_DEV_PERCFG0_MCBSP1CTL_SHIFT (0x00000010u)
#define CSL_DEV_PERCFG0_MCBSP1CTL_RESETVAL (0x00000000u)
/*----MCBSP1CTL Tokens----*/
#define CSL_DEV_PERCFG0_MCBSP1CTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_MCBSP0CTL_MASK (0x00004000u)
#define CSL_DEV_PERCFG0_MCBSP0CTL_SHIFT (0x0000000Eu)
#define CSL_DEV_PERCFG0_MCBSP0CTL_RESETVAL (0x00000000u)
/*----MCBSP0CTL Tokens----*/
#define CSL_DEV_PERCFG0_MCBSP0CTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_I2CCTL_MASK (0x00001000u)
#define CSL_DEV_PERCFG0_I2CCTL_SHIFT (0x0000000Cu)
#define CSL_DEV_PERCFG0_I2CCTL_RESETVAL (0x00000000u)
/*----I2CCTL Tokens----*/
#define CSL_DEV_PERCFG0_I2CCTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_GPIOCTL_MASK (0x00000400u)
#define CSL_DEV_PERCFG0_GPIOCTL_SHIFT (0x0000000Au)
#define CSL_DEV_PERCFG0_GPIOCTL_RESETVAL (0x00000000u)
/*----GPIOCTL Tokens----*/
#define CSL_DEV_PERCFG0_GPIOCTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_TIMER1CTL_MASK (0x00000100u)
#define CSL_DEV_PERCFG0_TIMER1CTL_SHIFT (0x00000008u)
#define CSL_DEV_PERCFG0_TIMER1CTL_RESETVAL (0x00000000u)
/*----TIMER1CTL Tokens----*/
#define CSL_DEV_PERCFG0_TIMER1CTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_TIMER0CTL_MASK (0x00000040u)
#define CSL_DEV_PERCFG0_TIMER0CTL_SHIFT (0x00000006u)
#define CSL_DEV_PERCFG0_TIMER0CTL_RESETVAL (0x00000000u)
/*----TIMER0CTL Tokens----*/
#define CSL_DEV_PERCFG0_TIMER0CTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_EMACCTL_MASK (0x00000010u)
#define CSL_DEV_PERCFG0_EMACCTL_SHIFT (0x00000004u)
#define CSL_DEV_PERCFG0_EMACCTL_RESETVAL (0x00000000u)
/*----EMACCTL Tokens----*/
#define CSL_DEV_PERCFG0_EMACCTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_VCPCTL_MASK (0x00000004u)
#define CSL_DEV_PERCFG0_VCPCTL_SHIFT (0x00000002u)
#define CSL_DEV_PERCFG0_VCPCTL_RESETVAL (0x00000000u)
/*----VCPCTL Tokens----*/
#define CSL_DEV_PERCFG0_VCPCTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_TCPCTL_MASK (0x00000001u)
#define CSL_DEV_PERCFG0_TCPCTL_SHIFT (0x00000000u)
#define CSL_DEV_PERCFG0_TCPCTL_RESETVAL (0x00000000u)
/*----TCPCTL Tokens----*/
#define CSL_DEV_PERCFG0_TCPCTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_RESETVAL (0x00000000u)
/* PERSTAT0 */
#define CSL_DEV_PERSTAT0_HPISTAT_MASK (0x38000000u)
#define CSL_DEV_PERSTAT0_HPISTAT_SHIFT (0x0000001Bu)
#define CSL_DEV_PERSTAT0_HPISTAT_RESETVAL (0x00000000u)
/*----HPISTAT Tokens----*/
#define CSL_DEV_PERSTAT0_HPISTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_HPISTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_HPISTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_HPISTAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_MASK (0x07000000u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_SHIFT (0x00000018u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_RESETVAL (0x00000000u)
/*----MCBSP1STAT Tokens----*/
#define CSL_DEV_PERSTAT0_MCBSP1STAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_MASK (0x00E00000u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_SHIFT (0x00000015u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_RESETVAL (0x00000000u)
/*----MCBSP0STAT Tokens----*/
#define CSL_DEV_PERSTAT0_MCBSP0STAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_I2CSTAT_MASK (0x001C0000u)
#define CSL_DEV_PERSTAT0_I2CSTAT_SHIFT (0x00000012u)
#define CSL_DEV_PERSTAT0_I2CSTAT_RESETVAL (0x00000000u)
/*----I2CSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_I2CSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_I2CSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_I2CSTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_I2CSTAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_MASK (0x00038000u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_SHIFT (0x0000000Fu)
#define CSL_DEV_PERSTAT0_GPIOSTAT_RESETVAL (0x00000000u)
/*----GPIOSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_GPIOSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_MASK (0x00007000u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_SHIFT (0x0000000Cu)
#define CSL_DEV_PERSTAT0_TIMER1STAT_RESETVAL (0x00000000u)
/*----TIMER1STAT Tokens----*/
#define CSL_DEV_PERSTAT0_TIMER1STAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_MASK (0x00000E00u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_SHIFT (0x00000009u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_RESETVAL (0x00000000u)
/*----TIMER0STAT Tokens----*/
#define CSL_DEV_PERSTAT0_TIMER0STAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_EMACSTAT_MASK (0x000001C0u)
#define CSL_DEV_PERSTAT0_EMACSTAT_SHIFT (0x00000006u)
#define CSL_DEV_PERSTAT0_EMACSTAT_RESETVAL (0x00000000u)
/*----EMACSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_EMACSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_EMACSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_EMACSTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_EMACSTAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_VCPSTAT_MASK (0x00000038u)
#define CSL_DEV_PERSTAT0_VCPSTAT_SHIFT (0x00000003u)
#define CSL_DEV_PERSTAT0_VCPSTAT_RESETVAL (0x00000000u)
/*----VCPSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_VCPSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_VCPSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_VCPSTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_VCPSTAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_TCPSTAT_MASK (0x00000007u)
#define CSL_DEV_PERSTAT0_TCPSTAT_SHIFT (0x00000000u)
#define CSL_DEV_PERSTAT0_TCPSTAT_RESETVAL (0x00000000u)
/*----TCPSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_TCPSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_TCPSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_TCPSTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_TCPSTAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT0_RESETVAL (0x00000000u)
/* PERSTAT1 */
#define CSL_DEV_PERSTAT1_UTOPIASTAT_MASK (0x00000038u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_SHIFT (0x00000003u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_RESETVAL (0x00000000u)
/*----UTOPIASTAT Tokens----*/
#define CSL_DEV_PERSTAT1_UTOPIASTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT1_PCISTAT_MASK (0x00000007u)
#define CSL_DEV_PERSTAT1_PCISTAT_SHIFT (0x00000000u)
#define CSL_DEV_PERSTAT1_PCISTAT_RESETVAL (0x00000000u)
/*----PCISTAT Tokens----*/
#define CSL_DEV_PERSTAT1_PCISTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT1_PCISTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT1_PCISTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT1_PCISTAT_ENABLE_IN_PROGRESS (0x00000005u)
#define CSL_DEV_PERSTAT1_RESETVAL (0x00000000u)
/* EMACCFG */
#define CSL_DEV_EMACCFG_RMII_RST_MASK (0x00080000u)
#define CSL_DEV_EMACCFG_RMII_RST_SHIFT (0x00000013u)
#define CSL_DEV_EMACCFG_RMII_RST_RESETVAL (0x00000001u)
/*----RMII_RST Tokens----*/
#define CSL_DEV_EMACCFG_RMII_RST_ASSERT (0x00000000u)
#define CSL_DEV_EMACCFG_RMII_RST_RELEASE (0x00000001u)
#define CSL_DEV_EMACCFG_RESETVAL (0x00080000u)
/* PERCFG1 */
#define CSL_DEV_PERCFG1_DDR2CTL_MASK (0x00000002u)
#define CSL_DEV_PERCFG1_DDR2CTL_SHIFT (0x00000001u)
#define CSL_DEV_PERCFG1_DDR2CTL_RESETVAL (0x00000000u)
/*----DDR2CTL Tokens----*/
#define CSL_DEV_PERCFG1_DDR2CTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG1_EMIFACTL_MASK (0x00000001u)
#define CSL_DEV_PERCFG1_EMIFACTL_SHIFT (0x00000000u)
#define CSL_DEV_PERCFG1_EMIFACTL_RESETVAL (0x00000000u)
/*----EMIFACTL Tokens----*/
#define CSL_DEV_PERCFG1_EMIFACTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG1_RESETVAL (0x00000000u)
/* EMUBUFPDN */
#define CSL_DEV_EMUBUFPDN_EMUCTL_MASK (0x00000001u)
#define CSL_DEV_EMUBUFPDN_EMUCTL_SHIFT (0x00000000u)
#define CSL_DEV_EMUBUFPDN_EMUCTL_RESETVAL (0x00000000u)
/*----EMUCTL Tokens----*/
#define CSL_DEV_EMUBUFPDN_EMUCTL_ENABLE (0x00000000u)
#define CSL_DEV_EMUBUFPDN_EMUCTL_DISABLE (0x00000001u)
#define CSL_DEV_EMUBUFPDN_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/_csl_dat.h | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file _csl_dat.h
*
* @desc Header file for DAT System Service APIs
*
* @path $(CSLPATH)\inc
*
*/
/* Dat State structure */
typedef struct _CSL_DatStateStruct {
/* QDMA Channel number being requested */
Int32 qchNum;
/* Region of operation */
Int32 regionNum;
/* Transfer completion code dedicated for DAT */
Int32 tccNum;
/* Parameter Entry for this channel */
Int32 paramNum;
/* Priority/Que number on which the transfer requests are submitted */
Int32 priority;
/* Pending/Not */
Bool pending;
} CSL_DatStateStruct;
extern CSL_DatStateStruct _CSL_datStateStruct;
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcHookIsr.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/**
* @file csl_intcHookIsr.c
*
* @brief File for functional layer of CSL API CSL_intcHookIsr()
*
* PATH $(CSLPATH)\src\intc
*/
/* =============================================================================
* Revision History
* ===============
* 12-Jun-2004 <NAME> File Created
*
* 16-Mar-2005 brn modified for doxygen documentation
* =============================================================================
*/
#include <csl_intc.h>
#include <_csl_intc.h>
/** ============================================================================
* @n@b CSL_intcHookIsr
*
* @b Description
* @n Hook up an exception handler
* This API hooks up the handler to the specified exception.
* Note: In this case, it is done by inserting a B(ranch) instruction
* to the handler. Because of the restriction in the instruction
* the handler must be within 32MB of the exception vector.
* Also, the function assumes that the exception vector table is
* located at its default ("low") address.
*
* @b Arguments
* @verbatim
vectId Interrupt Vector identifier
isrAddr Pointer to the handler
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n CSL_SOK - CSL_intcHookIsr Successful
*
* @b Example:
* @verbatim
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
CSL_IntcObj intcObj20;
CSL_IntcHandle hIntc20;
CSL_IntcDropStatus drop;
CSL_IntcEventHandlerRecord recordTable[10];
CSL_IntcGlobalEnableState state;
Uint32 intrStat;
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK)
exit;
// Opening a handle for the Event 20 at vector id 4
vectId = CSL_INTC_VECTID_4;
hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId ,
NULL);
CSL_intcNmiEnable();
// Enable Global Interrupts
intStat = CSL_intcGlobalEnable(&state);
// Hook Isr appropriately
CSL_intcHookIsr(CSL_INTC_VECTID_4,&isrVect4);
...
}
interrupt void isrVect4() {
}
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_intcHookIsr, ".text:csl_section:intc");
CSL_Status CSL_intcHookIsr (
CSL_IntcVectId evtId,
void *isrAddr
)
{
Uint32 *dispPtr;
dispPtr = (Uint32*)(&_CSL_intcCpuIntrTable);
dispPtr[evtId + 1] = (Uint32)(isrAddr);
return(CSL_SOK);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example3/src/Intc_example3.c | <filename>DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example3/src/Intc_example3.c
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file Intc_example3.c
*
* @path $(CSLPATH)\example\c64xplus\intc\intc_example3\src
*
* @desc Example of INTC
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This example illustrates the opening of an event handle,
* associating a handler with it, enabling it for 124 events starting from
* 4 to 128. This example,
* 1. Initalizes the intc CSL required with proper ISR
* 2. Opens 4 to 31 events with vector line 4,
* 32 to 63 events with vector line 5, 64 to 95 events with
* vector line 6 and 96 to 127 events with vector line 7
* 3. Enables the 4 to 127 events.
* 4. Manually sets all these events
* 5. Prints the total number of events occured.
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Intc_example3.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 24-Mar-2005 BRN File Created
* 16-Dec-2005 ds Updated documentation
* 19-Dec-2005 ds Added code for clearing of all events
* ============================================================================
*/
#include <stdio.h>
#include <csl_intc.h>
#include <csl_intcAux.h>
/* Intc variables declaration */
CSL_IntcContext context;
CSL_IntcEventHandlerRecord EventHandler[30];
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
/* Function forwards */
void eventHandler(CSL_IntcEventId* event);
void intc_example (void);
/* Global variable declaration */
Uint32 evtNum = 0;
/*
* ============================================================================
*
* @func main
*
* @desc
* Application that calls example function
* ============================================================================
*/
void main (void)
{
printf ("Running Interrupt Example\n");
intc_example ();
return;
}
/*
* ============================================================================
* @func intc_example
*
* @arg
* NONE
*
* @desc
* This checks functionalities of the intc CSL.It implements following steps
* 1. Initializes the Intc module
* 2. Opens the 4 to 31 events with interrupt vector line 4
* 3. Enables the 4 to 31 events.
* 4. Sets manually all these events
* 5. Opens the 32 to 63 events with interrupt vector line 5
* 6. Enables the 32 to 63 events.
* 7. Sets manually all these events
* 8. Opens the 64 to 95 events with interrupt vector line 6
* 9. Enables the 64 to 95 events.
* 10. Sets manually all these events
* 11. Opens the 96 to 127 events with interrupt vector line 7
* 12. Enables the 96 to 127 events.
* 13. Sets manually all these events.
* 14. Prints the total number of events occured.
*
* @return
* NONE
*
* =============================================================================
*/
void intc_example (void)
{
/* Obj for combined events */
CSL_IntcObj intcObj;
CSL_IntcObj intcObj2;
CSL_IntcObj intcObj4;
CSL_IntcObj intcObj6;
/* Obj for combiner events */
CSL_IntcObj intcObj0;
CSL_IntcObj intcObj1;
CSL_IntcObj intcObj3;
CSL_IntcObj intcObj5;
CSL_IntcHandle hIntc;
CSL_IntcHandle hIntc0;
CSL_IntcHandle hIntc1;
CSL_IntcHandle hIntc2;
CSL_IntcHandle hIntc3;
CSL_IntcHandle hIntc4;
CSL_IntcHandle hIntc5;
CSL_IntcHandle hIntc6;
CSL_Status intStat;
CSL_IntcParam vectId;
CSL_BitMask32 evtEn;
Uint32 eventId;
Uint32 evtClr;
Uint32 idx;
/* Since there are only 3 events in the system table of 3 elements are
* enough
*/
CSL_IntcEventHandlerRecord Record[128];
context.numEvtEntries = 128;
context.eventhandlerRecord = Record;
/* Initializes the CPU vector table, dispatchr */
intStat = CSL_intcInit(&context);
if (intStat != CSL_SOK) {
printf ("INTR: Initialization... Failed.\n");
printf ("\tReason: CSL_intcInit failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Initialization... Passed.\n");
}
/* Enable NMIs */
intStat = CSL_intcGlobalNmiEnable();
if (intStat != CSL_SOK) {
printf ("INTR: Global NMI Enable ... Failed.\n");
printf ("\tReason: CSL_intcGlobalNmiEnable failed. [status = 0x%x]\n",
intStat);
}
else {
printf ("INTR: Global NMI Enable... Passed.\n");
}
/* Enable Global Interrupts */
intStat = CSL_intcGlobalEnable(&state);
if (intStat != CSL_SOK) {
printf ("INTR: Global Enable ... Failed.\n");
printf ("\tReason: CSL_intcGlobalEnable failed. [status = 0x%x].\n",
intStat);
}
else {
printf ("INTR: Global Enable... Passed.\n");
}
/* Opening a handle for the Combiner 0 onto CPU vector 4 */
vectId = CSL_INTC_VECTID_4;
hIntc0 = CSL_intcOpen (&intcObj0, CSL_INTC_EVENTID_EVT0, &vectId , NULL);
if ((hIntc0 == NULL) || (intStat != CSL_SOK)) {
printf ("INTR: Open... Failed.\n");
printf ("\tReason: Error opening the instance ");
printf ("[status = 0x%x, hIntc = 0x%x]\n", intStat, hIntc0);
}
else
printf ("INTR: Open... Passed.\n");
/* Opening a handle for the Combiner 1 onto CPU vector 5 */
vectId = CSL_INTC_VECTID_5;
hIntc1 = CSL_intcOpen (&intcObj1, CSL_INTC_EVENTID_EVT1, &vectId , NULL);
if ((hIntc1 == NULL) || (intStat != CSL_SOK)) {
printf ("INTR: Open... Failed.\n");
printf ("\tReason: Error opening the instance. [status = 0x%x, \
hIntc = 0x%x].\n", intStat, hIntc1);
}
else
printf ("INTR: Open... Passed.\n");
/* Opening a handle for the Combiner 2 onto CPU vector 6 */
vectId = CSL_INTC_VECTID_6;
hIntc3 = CSL_intcOpen (&intcObj3, CSL_INTC_EVENTID_EVT2, &vectId , NULL);
if ((hIntc3 == NULL) || (intStat != CSL_SOK)) {
printf ("INTR: Open... Failed.\n");
printf ("\tReason: Error opening the instance. [status = 0x%x, \
hIntc = 0x%x].\n", intStat, hIntc3);
}
else
printf ("INTR: Open... Passed.\n");
/* Opening a handle for the Combiner 3 onto CPU vector 7 */
vectId = CSL_INTC_VECTID_7;
hIntc5 = CSL_intcOpen (&intcObj5, CSL_INTC_EVENTID_EVT3, &vectId , NULL);
if ((hIntc5 == NULL) || (intStat != CSL_SOK)) {
printf ("INTR: Open... Failed.\n");
printf ("\tReason: Error opening the instance. [status = 0x%x, \
hIntc = 0x%x].\n", intStat, hIntc5);
}
else
printf ("INTR: Open... Passed.\n");
/* Clear the all events */
for (idx = 0; idx < 4; idx++) {
evtClr = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTFLAG[idx];
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[idx] = evtClr;
}
/* The event combiner divides the 124 system events in four groups.
* The first group includes events 4-31,the second group includes events
* 32-63, the third group includes events 64-95, the fourth group includes
* events 96-127. Events within each group can be combined to provide a new
* combined event. These new events are designated interrupt vector line 4,
* interrupt vector line 5, interrupt vector line 6, interrupt vector line 7
* respectively.
*/
/* For loop to check 4 to 31 interrupts with interrupt vector line 4 */
for (eventId = 4; eventId < 32; eventId++) {
/* Open and setup the handler for each eventId*/
vectId = CSL_INTC_VECTID_COMBINE;
hIntc = CSL_intcOpen (&intcObj, (CSL_IntcEventId)eventId, &vectId,
NULL);
EventRecord.handler = (CSL_IntcEventHandler)&eventHandler;
EventRecord.arg = hIntc;
CSL_intcPlugEventHandler(hIntc,&EventRecord);
evtEn = (1<<eventId);
/* Note :- Combined events along with the combiner event all can be
enabled in one API */
intStat = CSL_intcHwControl(hIntc0,CSL_INTC_CMD_EVTENABLE,&evtEn);
if(intStat != CSL_SOK) {
printf("INTR: HwControl to enable event ... Failed.\n");
}
else
printf("INTR: HwControl to enable event ... Passed.\n");
/* Set events manually */
intStat = CSL_intcHwControl(hIntc,CSL_INTC_CMD_EVTSET,NULL);
if(intStat != CSL_SOK) {
printf("INTR: HwControl to set an event ... Failed.\n");
}
else
printf("INTC: HwControl to set an event ... Passed.\n");
}
/* For loop to check 32 to 63 interrupts with interrupt vector line 5 */
for (eventId = 32; eventId <64; eventId++) {
/* Open and setup the handler for each eventId*/
vectId = CSL_INTC_VECTID_COMBINE;
hIntc2 = CSL_intcOpen (&intcObj2, (CSL_IntcEventId)eventId, &vectId,
NULL);
EventRecord.handler = (CSL_IntcEventHandler)&eventHandler;
EventRecord.arg = hIntc2;
CSL_intcPlugEventHandler(hIntc2,&EventRecord);
evtEn = (1<<(eventId-32));
/* Note :- Combined events along with the combiner event all can be
enabled in one API */
intStat = CSL_intcHwControl(hIntc1,CSL_INTC_CMD_EVTENABLE,&evtEn);
if(intStat != CSL_SOK) {
printf("INTR: HwControl to enable event ... Failed.\n");
}
else
printf("INTR: HwControl to enable event ... Passed.\n");
/* Set events manually */
intStat = CSL_intcHwControl(hIntc2,CSL_INTC_CMD_EVTSET,NULL);
if(intStat != CSL_SOK) {
printf("INTR: HwControl to set an event ... Failed.\n");
}
else
printf("INTR: HwControl to set an event ... Passed.\n");
}
/* For loop to check 64 to 95 interrupts with interrupt vector line 6 */
for (eventId = 64; eventId <96; eventId++) {
/* Open and setup the handler for each eventId*/
vectId = CSL_INTC_VECTID_COMBINE;
hIntc4 = CSL_intcOpen (&intcObj4, (CSL_IntcEventId)eventId, &vectId ,
NULL);
EventRecord.handler = (CSL_IntcEventHandler)&eventHandler;
EventRecord.arg = hIntc4;
CSL_intcPlugEventHandler(hIntc4,&EventRecord);
evtEn = (1<<(eventId-64));
/* Note :- Combined events along with the combiner event all can be
enabled in one API */
intStat = CSL_intcHwControl(hIntc3,CSL_INTC_CMD_EVTENABLE,&evtEn);
if(intStat != CSL_SOK) {
printf("INTR: HwControl to enable event ... Failed.\n");
}
else
printf("INTR: HwControl to enable event ... Passed.\n");
/* Set events manually */
intStat = CSL_intcHwControl(hIntc4,CSL_INTC_CMD_EVTSET,NULL);
if(intStat != CSL_SOK) {
printf("INTR: HwControl to set an event ... Failed.\n");
}
else
printf("INTR: HwControl to set an event ... Passed.\n");
}
/* For loop to check 96 to 128 interrupts with interrupt vector line 7 */
for (eventId = 96; eventId <128; eventId++) {
/* Open and setup the handler for each eventId*/
vectId = CSL_INTC_VECTID_COMBINE;
hIntc6 = CSL_intcOpen (&intcObj6, (CSL_IntcEventId)eventId, &vectId ,
NULL);
EventRecord.handler = (CSL_IntcEventHandler)&eventHandler;
EventRecord.arg = hIntc6;
CSL_intcPlugEventHandler(hIntc6,&EventRecord);
evtEn = (1<<(eventId-96));
/* Note :- Combined events along with the combiner event all can be
enabled in one API */
intStat = CSL_intcHwControl(hIntc5,CSL_INTC_CMD_EVTENABLE,&evtEn);
if(intStat != CSL_SOK) {
printf("INTR: HwControl to enable event ... Failed.\n");
}
else
printf("INTR: HwControl to enable event ... Passed.\n");
/* Set events manually */
intStat = CSL_intcHwControl(hIntc6,CSL_INTC_CMD_EVTSET,NULL);
if(intStat != CSL_SOK) {
printf("INTR: HwControl to set an event ... Failed.\n");
}
else
printf("INTR: HwControl to set an event ... Passed.\n");
}
printf("INTR: The Total number of Events occured are: %d\n", evtNum);
/* Closing all handles */
intStat = CSL_intcClose(hIntc);
if (intStat != CSL_SOK) {
printf ("INTR: Close ... Failed.\n");
printf ("\tReason: Intc Close failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Close ... Passed.\n");
}
intStat = CSL_intcClose(hIntc0);
if (intStat != CSL_SOK) {
printf ("INTR: Close ... Failed.\n");
printf ("\tReason: Intc Close failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Close ... Passed.\n");
}
intStat = CSL_intcClose(hIntc1);
if (intStat != CSL_SOK) {
printf ("INTR: Close ... Failed.\n");
printf ("\tReason: Intc Close failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Close ... Passed.\n");
}
intStat = CSL_intcClose(hIntc2);
if (intStat != CSL_SOK) {
printf ("INTR: Close ... Failed.\n");
printf ("\tReason: Intc Close failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Close ... Passed.\n");
}
intStat = CSL_intcClose(hIntc3);
if (intStat != CSL_SOK) {
printf ("INTR: Close ... Failed.\n");
printf ("\tReason: Intc Close failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Close ... Passed.\n");
}
intStat = CSL_intcClose(hIntc4);
if (intStat != CSL_SOK) {
printf ("INTR: Close ... Failed.\n");
printf ("\tReason: Intc Close failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Close ... Passed.\n");
}
intStat = CSL_intcClose(hIntc5);
if (intStat != CSL_SOK) {
printf ("INTR: Close ... Failed.\n");
printf ("\tReason: Intc Close failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Close ... Passed.\n");
}
intStat = CSL_intcClose(hIntc6);
if (intStat != CSL_SOK) {
printf ("INTR: Close ... Failed.\n");
printf ("\tReason: Intc Close failed. [status = 0x%x].\n", intStat);
}
else {
printf ("INTR: Close ... Passed.\n");
}
}
/*
* =============================================================================
* @func eventHandler
*
* @desc
* This is the intc event handler
*
* @arg event
* Pointer to events
*
*
* @eg
* eventHandler ();
* =============================================================================
*/
void eventHandler (
CSL_IntcEventId *event
)
{
evtNum += 1;
printf("INTR: EVENT Handler for event:%d\n",*event);
CSL_intcEventClear (*event);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/srio/srio_external_loopbk_example/src/Srio_ext_loopback_example.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ===========================================================================
* @file Srio_ext_loopback_example.c
*
* @path $(CSLPATH)\example\srio\src
*
* @desc This is a simple external lookback example of usage of CSL APIs
* of the SRIO module.
*
* ============================================================================
* @n Target Platform: EVM and Adapter board
* ============================================================================
*
* ============================================================================
* @n <b> Example Description </b>
* @n This is an example of the CSL SRIO usage for a LSU port.
* @verbatim
1. Setup SRIO module for external loop back transfer on LSU1.
2. Setup the destination and source data areas.
3. Configure LSU1 registers.
4. Start transfer.
5. Wait for completion of the transfer.
6. Verify the destination contains the expected data.
@endverbatim
*
*=============================================================================
*
* @n <b> Procedure </b>
* @verbatim
1. Configure the CCS setup
2. Please refer CCS manual for setup configuration and loading
proper GEL file
3. Launch CCS window
4. Open project Srio_ext_loopback_example.pjt
5. Build the project and load the .out file of the project.
@endverbatim
*
*
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 31-Aug-2006 NG File created
* ============================================================================
*/
#include <csl_srio.h>
#include <cslr_dev.h>
#include <soc.h>
#include <stdio.h>
/* Macros */
#define SRIO_SET_DEVICE_ID(base_dev_id, large_base_dev_id) \
CSL_FMK(SRIO_BASE_ID_BASE_DEVICEID, base_dev_id) | \
CSL_FMK(SRIO_BASE_ID_LARGE_BASE_DEVICEID, large_base_dev_id)
#define LARGE_DEV_ID 0xBEEF
#define SMALL_DEV_ID 0xAB
#define SRIO_PKT_TYPE_NWRITE 0x54
#define SELECTED_LSU 0
#define TRANSFER_SIZE 256
/* globals */
static Uint8 src[TRANSFER_SIZE];
static Uint8 dst[TRANSFER_SIZE];
static CSL_SrioHwSetup setup = CSL_SRIO_HWSETUP_DEFAULTS;
/* Function prototypes */
void srio_Create_Setup (
CSL_SrioHwSetup *pSetup,
int bootcomplete
);
/*
* ============================================================================
* @func main
*
* @desc
* This is the main routine of this program which invokes the different
* components to complete a simple LSU transfer.
* ============================================================================
*/
void main (
void
)
{
volatile Uint32 index, dummy_cnt;
Uint8 lsu_no;
CSL_SrioContext context;
CSL_Status status;
CSL_SrioHandle hSrio;
CSL_SrioObj srioObj;
CSL_InstNum srioNum = 0; /* Instance number of the SRIO */
CSL_SrioParam srioParam;
CSL_SrioDirectIO_ConfigXfr lsu_conf = {0};
CSL_SrioPortData response;
/* Unlock the powersaver control register */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the SRIO */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_SRIOCTL,
ENABLE);
/* Initialization and Open of the SRIO */
status = CSL_srioInit (&context);
hSrio = CSL_srioOpen (&srioObj, srioNum, &srioParam, &status);
if (status != CSL_SOK) {
printf("SRIO: ... Cannot open SRIO, failed\n");
return;
}
/* Create the setup structure */
srio_Create_Setup (&setup, 1);
response.index = 0;
do {
/* Setup the SRIO with the selected setup in the last step */
status = CSL_srioHwSetup (hSrio, &setup);
if (status != CSL_SOK) {
printf("SRIO: ... Hardwrae setup, failed\n");
return;
}
//Delay for PLL? need to re-clear errors?
for(index=0; index<0x10000; index++) {
dummy_cnt = index + 1;
dummy_cnt++;
}
CSL_srioGetHwStatus (hSrio, CSL_SRIO_QUERY_SP_ERR_STAT, &response);
}while(response.data & 0x1);
/* Setup the source and destination */
for(index=0; index<TRANSFER_SIZE; index++) {
src[index] = index + 1;
dst[index] = 0;
}
/* Create an LSU configuration */
lsu_conf.srcNodeAddr = (Uint32)&src[0]; /* Source address */
lsu_conf.dstNodeAddr.addressHi = 0;
lsu_conf.dstNodeAddr.addressLo = (Uint32)&dst[0]; /* Destination address */
lsu_conf.byteCnt = TRANSFER_SIZE;
lsu_conf.idSize = 1; /* 16 bit device id */
lsu_conf.priority = 2; /* PKT priority is 2 */
lsu_conf.xambs = 0; /* Not an extended
address */
lsu_conf.dstId = LARGE_DEV_ID;
lsu_conf.intrReq = 0; /* No interrupts */
lsu_conf.pktType = SRIO_PKT_TYPE_NWRITE;
/* write with no
response */
lsu_conf.hopCount = 0; /* Valid for
maintainance pkt */
lsu_conf.doorbellInfo = 0; /* Not a doorbell pkt */
lsu_conf.outPortId = 0; /* Tx on Port 0 */
for(index=0; index<0x10000; index++) {
/* Configure the LSU1 and start transmission */
lsu_no = SELECTED_LSU;
CSL_srioLsuSetup (hSrio, &lsu_conf, lsu_no);
/* Wait for the completion of transfer */
response.index = lsu_no;
do {
CSL_srioGetHwStatus (hSrio, CSL_SRIO_QUERY_LSU_BSY_STAT, &response);
}while(response.data == 1);
}
/* A delay, above checks seems to be not working
may be because, it is a write operation with
no response */
for(index=0; index<0x10000; index++) {
dummy_cnt = index + 1;
dummy_cnt++;
}
/* Verify whether data is transfered */
for(index=0; index<TRANSFER_SIZE; index++) {
if (src[index] != dst[index]) {
break;
}
}
if (index == TRANSFER_SIZE) {
printf("SRIO: ... LSU transfered %d bytes of data correctly\n",
TRANSFER_SIZE);
} else {
printf("SRIO: ... LSU failed to transfer data\n");
}
}
/*
* ============================================================================
* @func srio_Create_Setup
*
* @desc
* This routine setsup a structure with the required setup of the SRIO.
* ============================================================================
*/
void srio_Create_Setup (
CSL_SrioHwSetup *pSetup,
int bootcomplete
)
{
Uint32 index;
/* Peripheral enable */
pSetup->perEn = 1;
/* While in shutdown, put memories in sleep mode */
pSetup->periCntlSetup.swMemSleepOverride = 1;
/* Disable loopback operation
* NOTE: External lookback operation is enabled
*/
pSetup->periCntlSetup.loopback = 0;
/* Boot process is over (complete) */
pSetup->periCntlSetup.bootComplete = bootcomplete;
/* Process TX requests of priority 2, when credit is 1 or greater */
pSetup->periCntlSetup.txPriority2Wm = CSL_SRIO_TX_PRIORITY_WM_0;
/* Process TX requests of priority 1, when credit is 1 or greater */
pSetup->periCntlSetup.txPriority1Wm = CSL_SRIO_TX_PRIORITY_WM_0;
/* Process TX requests of priority 0, when credit is 1 or greater */
pSetup->periCntlSetup.txPriority0Wm = CSL_SRIO_TX_PRIORITY_WM_0;
/* Set internal bus priority to 1 (next to lowest) */
pSetup->periCntlSetup.busTransPriority = CSL_SRIO_BUS_TRANS_PRIORITY_1;
/* UDI buffers are port based not proirity based */
pSetup->periCntlSetup.bufferMode = CSL_SRIO_1X_MODE_PRIORITY;
/* VBUS clock is of 333 MHz from TPCC document section 2.3 */
pSetup->periCntlSetup.prescalar = CSL_SRIO_CLK_PRESCALE_6;
/* Enable port 0 PLL */
pSetup->periCntlSetup.pllEn = CSL_SRIO_PLL1_ENABLE;
/* Enable clocks to all domains */
pSetup->gblEn = 1;
/* Enable clock in each domain */
for (index=0; index<9; index++) { /* 9 domains */
pSetup->blkEn[index] = 1; /* Enable each of it */
}
/* 8-bit id is 0xAB and 16-bit id is 0xBEEF */
pSetup->deviceId1 = SRIO_SET_DEVICE_ID(SMALL_DEV_ID, LARGE_DEV_ID);
/* 8-bit id is 0xAB and 16-bit id is 0xBEEF for multi-cast*/
pSetup->deviceId2 = SRIO_SET_DEVICE_ID(SMALL_DEV_ID, LARGE_DEV_ID);
/* configure the SERDES registers */
/* SERDES PLL configuration for channel 0 */
pSetup->serDesPllCfg[0].pllEnable = TRUE;
pSetup->serDesPllCfg[0].pllMplyFactor = CSL_SRIO_SERDES_PLL_MPLY_BY_12_5;
/* SERDES RX channel 0 enable */
pSetup->serDesRxChannelCfg[0].enRx = TRUE;
pSetup->serDesRxChannelCfg[0].symAlign = CSL_SRIO_SERDES_SYM_ALIGN_COMMA;
pSetup->serDesRxChannelCfg[0].los = CSL_SRIO_SERDES_LOS_DET_DISABLE;
pSetup->serDesRxChannelCfg[0].clockDataRecovery = 0x00; /* first order */
pSetup->serDesRxChannelCfg[0].equalizer = 0x01;
/* SERDES TX channel 0 enable */
pSetup->serDesTxChannelCfg[0].enTx = TRUE;
pSetup->serDesTxChannelCfg[0].commonMode =
CSL_SRIO_SERDES_COMMON_MODE_RAISED;
pSetup->serDesTxChannelCfg[0].outputSwing =
CSL_SRIO_SERDES_SWING_AMPLITUDE_1000;
pSetup->serDesTxChannelCfg[0].enableFixedPhase = TRUE;
/* SERDES PLL configuration for channel 1 */
pSetup->serDesPllCfg[1].pllEnable = TRUE;
pSetup->serDesPllCfg[1].pllMplyFactor = CSL_SRIO_SERDES_PLL_MPLY_BY_6;
/* SERDES RX channel 1 enable */
pSetup->serDesRxChannelCfg[1].enRx = TRUE;
pSetup->serDesRxChannelCfg[1].symAlign = CSL_SRIO_SERDES_SYM_ALIGN_COMMA;
pSetup->serDesRxChannelCfg[1].los = CSL_SRIO_SERDES_LOS_DET_DISABLE;
pSetup->serDesRxChannelCfg[1].clockDataRecovery = 0x00; /* first order */
pSetup->serDesRxChannelCfg[1].equalizer = 0x01;
/* SERDES TX channel 1 enable */
pSetup->serDesTxChannelCfg[1].enTx = TRUE;
pSetup->serDesTxChannelCfg[1].commonMode =
CSL_SRIO_SERDES_COMMON_MODE_RAISED;
pSetup->serDesTxChannelCfg[1].outputSwing =
CSL_SRIO_SERDES_SWING_AMPLITUDE_1000;
pSetup->serDesTxChannelCfg[1].enableFixedPhase = TRUE;
/* SERDES PLL configuration for channel 2 */
pSetup->serDesPllCfg[2].pllEnable = TRUE;
pSetup->serDesPllCfg[2].pllMplyFactor = CSL_SRIO_SERDES_PLL_MPLY_BY_6;
/* SERDES RX channel 2 enable */
pSetup->serDesRxChannelCfg[2].enRx = TRUE;
pSetup->serDesRxChannelCfg[2].symAlign = CSL_SRIO_SERDES_SYM_ALIGN_COMMA;
pSetup->serDesRxChannelCfg[2].los = CSL_SRIO_SERDES_LOS_DET_DISABLE;
pSetup->serDesRxChannelCfg[2].clockDataRecovery = 0x00; /* first order */
pSetup->serDesRxChannelCfg[2].equalizer = 0x01;
/* SERDES TX channel 2 enable */
pSetup->serDesTxChannelCfg[2].enTx = TRUE;
pSetup->serDesTxChannelCfg[2].commonMode =
CSL_SRIO_SERDES_COMMON_MODE_RAISED;
pSetup->serDesTxChannelCfg[2].outputSwing =
CSL_SRIO_SERDES_SWING_AMPLITUDE_1000;
pSetup->serDesTxChannelCfg[2].enableFixedPhase = TRUE;
/* SERDES PLL configuration for channel 3 */
pSetup->serDesPllCfg[3].pllEnable = TRUE;
pSetup->serDesPllCfg[3].pllMplyFactor = CSL_SRIO_SERDES_PLL_MPLY_BY_6;
/* SERDES RX channel 3 enable */
pSetup->serDesRxChannelCfg[3].enRx = TRUE;
pSetup->serDesRxChannelCfg[3].symAlign = CSL_SRIO_SERDES_SYM_ALIGN_COMMA;
pSetup->serDesRxChannelCfg[3].los = CSL_SRIO_SERDES_LOS_DET_DISABLE;
pSetup->serDesRxChannelCfg[3].clockDataRecovery = 0x00; /* first order */
pSetup->serDesRxChannelCfg[3].equalizer = 0x01;
/* SERDES TX channel 3 enable */
pSetup->serDesTxChannelCfg[3].enTx = TRUE;
pSetup->serDesTxChannelCfg[3].commonMode =
CSL_SRIO_SERDES_COMMON_MODE_RAISED;
pSetup->serDesTxChannelCfg[3].outputSwing =
CSL_SRIO_SERDES_SWING_AMPLITUDE_1000;
pSetup->serDesTxChannelCfg[3].enableFixedPhase = TRUE;
/* Select flow control ID length 16-bit */
pSetup->flowCntlIdLen[0] = 1;
/* Destination ID of flow n, same ids as we are doing loopback */
pSetup->flowCntlId[0] = LARGE_DEV_ID;
/* Sets the number of address bits generated by the PE as a source and
* processed by the PE as the target of an operation as 34 bits
*/
pSetup->peLlAddrCtrl = CSL_SRIO_ADDR_SELECT_34BIT;
/* Base device configuration */
pSetup->devIdSetup.smallTrBaseDevId = SMALL_DEV_ID;
pSetup->devIdSetup.largeTrBaseDevId = LARGE_DEV_ID;
pSetup->devIdSetup.hostBaseDevId = LARGE_DEV_ID;
/* Port General configuration */
pSetup->portGenSetup.portLinkTimeout = 0xFFFFF; /* 215 ms */
pSetup->portGenSetup.portRespTimeout = 0xFFFFF; /* 215 ms */
pSetup->portGenSetup.hostEn = 1; /* It is a slave */
pSetup->portGenSetup.masterEn = 1; /* This device can issue requests */
/* Port control configuration */
pSetup->portCntlSetup[0].portDis = 0; /* Do not disable Port 0 */
pSetup->portCntlSetup[0].outPortEn = 1; /* Output on Port 0 enabled */
pSetup->portCntlSetup[0].inPortEn = 1; /* Input on Port 0 enabled */
pSetup->portCntlSetup[0].portWidthOverride =
CSL_SRIO_PORT_WIDTH_NO_OVERRIDE; /* 4 line port */
pSetup->portCntlSetup[0].errCheckDis = 0; /* Err check enabled */
pSetup->portCntlSetup[0].multicastRcvEn = 1; /* MltCast receive enabled */
pSetup->portCntlSetup[0].stopOnPortFailEn = 1; /* Stop on fail */
pSetup->portCntlSetup[0].dropPktEn = 1; /* Drop PKT */
pSetup->portCntlSetup[0].portLockoutEn = 0; /* Send any PKT */
/* Enable all logical/transport errors */
pSetup->lgclTransErrEn = CSL_SRIO_IO_ERR_RESP_ENABLE |
CSL_SRIO_ILL_TRANS_DECODE_ENABLE |
CSL_SRIO_ILL_TRANS_TARGET_ERR_ENABLE |
CSL_SRIO_PKT_RESP_TIMEOUT_ENABLE |
CSL_SRIO_UNSOLICITED_RESP_ENABLE |
CSL_SRIO_UNSUPPORTED_TRANS_ENABLE;
/* Enable all Port errors */
pSetup->portErrSetup[0].portErrRateEn =
CSL_SRIO_ERR_IMP_SPECIFIC_ENABLE |
CSL_SRIO_CORRUPT_CNTL_SYM_ENABLE |
CSL_SRIO_CNTL_SYM_UNEXPECTED_ACKID_ENABLE |
CSL_SRIO_RCVD_PKT_NOT_ACCPT_ENABLE |
CSL_SRIO_PKT_UNEXPECTED_ACKID_ENABLE |
CSL_SRIO_RCVD_PKT_WITH_BAD_CRC_ENABLE |
CSL_SRIO_RCVD_PKT_OVER_276B_ENABLE |
CSL_SRIO_NON_OUTSTANDING_ACKID_ENABLE |
CSL_SRIO_PROTOCOL_ERROR_ENABLE |
CSL_SRIO_UNSOLICITED_ACK_CNTL_SYM_ENABLE |
CSL_SRIO_LINK_TIMEOUT_ENABLE;
/* Decrement error rate counter every second */
pSetup->portErrSetup[0].prtErrRtBias = CSL_SRIO_ERR_RATE_BIAS_1S;
/* Allow only 2 errors after error threshold is reached */
pSetup->portErrSetup[0].portErrRtRec = CSL_SRIO_ERR_RATE_COUNT_2;
/* Port error setup */
pSetup->portErrSetup[0].portErrRtFldThresh = 10; /* Err threshold = 10 */
pSetup->portErrSetup[0].portErrRtDegrdThresh = 10; /* Err degrade
threshold = 10 */
/* This configures the SP_IP_MODE register */
/*
IDLE_ERR_DIS - 0b0; IDLE Error checking enabled
TX_FIFO_BYP ASS - 0b0; The TX_FIFO is operational
PW_DIS - 0b0; Port-Write Error reporting is enabled
TGT_ID_DIS - 0b0; packet accepted if DestID != BaseID
SELF_RST - 0b0; Self reset disabled
MLTC_EN - 0b1; Multicast-Event Interrupt Enable
RST_EN - 0b1; Reset Interrupt Enable
PW_EN - 0b1; Port-Write-In Interrupt Enable
Not writing into clear bits, assuming they are cleared on reset
*/
pSetup->portIpModeSet = 0x0000002A;
/* Configure the SP_IP_PRESCALE register assuming 333 MHz frequency */
pSetup->portIpPrescalar = 33;
/* Port-Write Timer. The timer defines a period to repeat sending an error
* reporting Port-Write request for software assistance. The timer stopped
* by software writing to the error detect registers 900 ms
*/
pSetup->pwTimer = CSL_SRIO_PW_TIME_8;
/* Port control independent error reporting enable. Macros can be ORed
* to get the value
*/
/*
TX_FLW - 0; Receive link flow control
SOFT_REC - 0; Hardware controlled error recovery
FORCE_REINIT - 0; Reinitialization process NOT forced
TRANS_MODE - 01; transfer mode - Store & Forward Mode
DEBUG - 1; Debug enable
SEND_DBG_PKT - 0; Do not force a debug packet
ILL_TRANS_EN - 1; Illegal Transfer Error reporting Enable
MAX_RETRY_EN - 1; Max_retry_error report enable
MAX_RETRY_THR - 0x01; Maximum Retry Threshold Trigger
IRQ_EN - 1; Interrupt error report Enable
*/
pSetup->portCntlIndpEn[0] = 0x01A20180;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/FB_Example/main.h | #ifndef MAIN_H_
#define MAIN_H_
#include <cslr_dev.h>
#include <cslr_gpio.h>
typedef volatile CSL_DevRegs *CSL_DevRegsOvly;
extern CSL_GpioRegsOvly gpioRegs;
void SetSegment(int Channel, int Segment);
void ClearChannel(int Channel);
void UploadSine(int Channel, int Amplitude, int Period, int Repeats, int Threshold);
void SetupTrigger();
void AddLoop(int Channel, int Vectors, int Repeats);
int AddDataPoint(int Channel, int duration, int value);
#endif /*MAIN_H_*/
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/mcbsp/mcbsp_edma/src/Mcbsp_Edma_example.c | <gh_stars>0
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
*
* @file Mcbsp_Edma_example.c
*
* @path $(CSLPATH)\example\mcbsp\mcbsp_edma\src
*
* @desc Example of MCBSP
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n In this example, the MCBSP0 is configured in digital loopback mode,
* with 32 bit data transfer, using sample rate generator to synchronize
* the frames.Edma mode of transmission is selected.
* This example,
* 1. Initializes and opens mcbsp module.
* 2. Sets up the hardware to default values and multi channel
* 32 bit data transfer i.e., CSL_mcbspHwSetup() is called for
* module configuration.
3. Sets up interrupts corresponding to EDMA and MCBSP.
* 4. Sets up EDMA for synchronizing ate MCBSP.
* 5. Enables MCBSP to Transmit/Receive Data.
* 7. Waits for the interrupt and once the transfer is done closes
* the EDMA.
* 8. Does the data comparison to ensure the validity of the data.
* 9. Displays the messages based on step 8.
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Mcbsp_Edma_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 9-Aug-2006 RR File Created.
*
* =============================================================================
*/
#include <edmaCommon.h>
#include <cslr_dev.h>
/* Define data count */
#define DATATX_COUNT 64
/* Global for mcbsp */
Uint8 srcBuff[DATATX_COUNT];
Uint8 dstBuff[DATATX_COUNT];
volatile Uint32 intFlag = 0;
volatile Uint32 rxintFlag = 0;
/* Handle for the MCBSP instance used in test */
CSL_McbspHandle hMcbsp;
/* Macro that gives 2 CLK delay cycles */
#define WAIT_FOR_1_CLK do { \
volatile int delayCnt = 1; \
while(delayCnt > 0) --delayCnt; \
}while (0)
/* Global data definition */
CSL_McbspGlobalSetup mcbspGbl = {
CSL_MCBSP_IOMODE_TXDIS_RXDIS ,
CSL_MCBSP_DLBMODE_ON,
CSL_MCBSP_CLKSTP_DISABLE
};
/** Receive Data Setup defaults */
CSL_McbspDataSetup mcbspRxData = {
CSL_MCBSP_PHASE_SINGLE,
CSL_MCBSP_WORDLEN_32,
1, //frame length
(CSL_McbspWordLen)0,
0,
CSL_MCBSP_FRMSYNC_IGNORE, //frame sinc ignore
CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
CSL_MCBSP_DATADELAY_0_BIT,
CSL_MCBSP_RJUSTDXENA_RJUST_RZF ,
CSL_MCBSP_INTMODE_ON_READY,
CSL_MCBSP_32BIT_REVERS_DISABLE
};
/** Transmit Data Setup defaults */
CSL_McbspDataSetup mcbspTxData = {
CSL_MCBSP_PHASE_SINGLE,
CSL_MCBSP_WORDLEN_32,
1,
(CSL_McbspWordLen)0,
0,
CSL_MCBSP_FRMSYNC_IGNORE,
CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
CSL_MCBSP_DATADELAY_0_BIT,
CSL_MCBSP_RJUSTDXENA_DXENA_OFF ,
CSL_MCBSP_INTMODE_ON_READY,
CSL_MCBSP_32BIT_REVERS_DISABLE
};
/** Clock Setup defaults */
CSL_McbspClkSetup mcbspClock = {
CSL_MCBSP_FSCLKMODE_INTERNAL, /* XMT Frame-sync */
CSL_MCBSP_FSCLKMODE_INTERNAL, /* RCV Frame-sync */
CSL_MCBSP_TXRXCLKMODE_INTERNAL, /* XMT clock */
CSL_MCBSP_TXRXCLKMODE_INTERNAL, /* RCV clock */
CSL_MCBSP_FSPOL_ACTIVE_HIGH, /* XMT Frame-sync Active High */
CSL_MCBSP_FSPOL_ACTIVE_HIGH, /* RCV Frame-sync Active High */
CSL_MCBSP_CLKPOL_TX_RISING_EDGE, /* XMT clock Rising Edge */
CSL_MCBSP_CLKPOL_RX_FALLING_EDGE,/* RCV clock Falling Edge */
1, /* Frame-sync pulse width = 1 bit */
0x40, /* Frame-sync pulse period */
0x1, /*clk divide by 2 */
CSL_MCBSP_SRGCLK_CLKCPU,
CSL_MCBSP_CLKPOL_TX_RISING_EDGE ,/* CLKS pin signal Rising Edge */
CSL_MCBSP_TXFSMODE_DXRCOPY,
CSL_MCBSP_CLKGSYNCMODE_OFF /* GSYNC = 0 means no clock synchronisation */
};
CSL_McbspMulChSetup mcbspMul = {
CSL_MCBSP_PARTMODE_2PARTITION, /* RX */
CSL_MCBSP_PARTMODE_2PARTITION, /* TX */
(Uint16)0, /* rxMulChSel */
(Uint16)0, /* txMulChSel */
CSL_MCBSP_PABLK_0,/* rxPartABlk */
CSL_MCBSP_PBBLK_1,/* rxPartBBlk */
CSL_MCBSP_PABLK_0,/* txPartABlk */
CSL_MCBSP_PBBLK_1 /* txPartABlk */
};
CSL_McbspHwSetup myHwSetup = {
&mcbspGbl,
&mcbspRxData,
&mcbspTxData,
&mcbspClock,
&mcbspMul,
CSL_MCBSP_EMU_FREERUN,
NULL
};
/* Global Edma Tcc handler table */
CSL_IntcEventHandlerRecord EventHandler[30];
CSL_IntcContext intcContext;
CSL_IntcGlobalEnableState state;
CSL_Status intStat,status;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcEventHandlerRecord EventRecord1;
CSL_IntcEventHandlerRecord record[2];
CSL_IntcObj intcObjEdma,intcObjEdma1;
CSL_IntcHandle hIntcEdma,hIntcEdma1;
CSL_IntcParam vectId,vectId1;
CSL_Edma3Handle hModule;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ChannelHandle hChannel1;
CSL_Edma3ChannelErr chErrClear;
/* function prototype */
void setupInterrupts(void);
void txmyIsr();
void rxmyIsr();
void mcbsp_edma_example(void);
void mcbsp_edma_setup(void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine,which invokes the test scripts
* =============================================================================
*/
void main (
void
)
{
Bool mcbsp0En;
/* Enable Mcbsp0 */
/* Unlock the PERCFG0 register */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the powersaver for the MCBSP 0 */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_MCBSP0CTL,
ENABLE);
do {
mcbsp0En = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_MCBSP0STAT);
} while (mcbsp0En != TRUE);
printf("Powersaver for MCBSP 0 is enabled\n");
/* Invoke the example */
mcbsp_edma_example ();
printf("===============================================================\n");
return;
}
/*
* ============================================================================
* @func mcbsp_edma_example
*
* @desc
* This function performs following steps:
* -# Opens one MCBSP port
* -# Resets MCBSP XMT, RCV and Enable SRGR, Frame-sync
* -# Sets up MCBSP with the initialized hwSetup function
* and waits for 1 CLK cycles
* -# After all the data is transmitted out of MCBSP, it compares
* the two buffers and prints the result to stdout
* -# In the end it closes the MCBSP instance that was opened
*
* ============================================================================
*/
void mcbsp_edma_example (void)
{
CSL_Status status = CSL_SOK;
CSL_McbspContext pContext;
CSL_McbspObj mcbspObj;
Uint16 i;
Uint16 success = 1;
CSL_BitMask16 ctrlMask;
/* Data Arrays */
for (i = 0;i < DATATX_COUNT; i++) {
srcBuff[i] = i;
dstBuff[i] = 0;
}
/* Initialize the MCBSP CSL module */
status = CSL_mcbspInit(&pContext);
/* Open the CSL module */
hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL, &status);
/* Setup hardware parameters */
status= CSL_mcbspHwSetup (hMcbsp , &myHwSetup);
/* Disable MCBSP transmit and receive */
ctrlMask = CSL_MCBSP_CTRL_SRG_ENABLE
| CSL_MCBSP_CTRL_FSYNC_ENABLE
| CSL_MCBSP_CTRL_TX_DISABLE
| CSL_MCBSP_CTRL_RX_DISABLE;
status = CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
WAIT_FOR_1_CLK;
/* setup Edma for Mcbsp */
mcbsp_edma_setup ();
/* All done now, close the port. */
CSL_mcbspClose(hMcbsp);
/* Check data to make sure transfer was successful */
for (i = 0; i < DATATX_COUNT; i++) {
if (srcBuff[i] != dstBuff[i]) {
success = 0;
break;
}
}
for (i = 0; i < DATATX_COUNT; i++) {
if (success == 1)
printf("RxData = %d\t txData=%d\n", dstBuff[i],srcBuff[i]);
else {
printf("RxData = %d\t txData=%d\n", dstBuff[i],srcBuff[i]);
return;
}
}
printf("\n%s",success?"TRANSMISSION SUCCESS\n":"TRANSMISSION: EXAMPLE FAILED\n");
return;
}
/**
* ============================================================================
* @n@b mcbsp_edma_setup
*
* @desc
* This function performs follwing steps:
* -# Set up interrupts corresponding to EDMA and MCBSP
* -# Set up EDMA for synchronising with MCBSP
* -# Enable MCBSP to Trax Data.
* -# Wait for the interrupt and once the transfer is done close the EDMA
* ============================================================================
*/
void mcbsp_edma_setup (
void
)
{
CSL_Edma3ParamHandle hParamBasic;
CSL_Edma3ParamHandle hParamBasic1;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3ParamSetup myParamSetup1;
CSL_Edma3ChannelObj ChObj,ChObj1;
CSL_Edma3ChannelAttr chParam;
CSL_Edma3Context edmaContext;
CSL_Edma3Obj edmaObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
Uint32 i, j;
CSL_BitMask16 ctrlMask;
for (i = 0, j = 1; i < DATATX_COUNT;i++,j++) {
srcBuff[i] = j;
dstBuff[i] = 0;
}
/* Intc Module Initialization */
intcContext.eventhandlerRecord = EventHandler;
intcContext.numEvtEntries = 10;
CSL_intcInit(&intcContext);
/* Enable NMIs */
CSL_intcGlobalNmiEnable();
/* Enable Global Interrupts */
intStat = CSL_intcGlobalEnable(&state);
/* Opening a handle for the Event edma */
vectId = CSL_INTC_VECTID_4;
hIntcEdma = CSL_intcOpen (&intcObjEdma, CSL_INTC_EVENTID_EDMA3CC_INT0,
&vectId , NULL);
/* Edma Module Initialization */
CSL_edma3Init(&edmaContext);
/* Edma Module Level Open */
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
/* Query Module Info */
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INFO, &info);
/********************************Setup for Tx******************************/
/* Setup the DRAE Masks */
regionAccess.region = CSL_EDMA3_REGION_0;
regionAccess.drae = 0xFFFF;
regionAccess.draeh = 0;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE,®ionAccess);
/* Open transmit channel */
chParam.regionNum = CSL_EDMA3_REGION_0;
chParam.chaNum = CSL_EDMA3_CHA_XEVT0;
hChannel = CSL_edma3ChannelOpen(&ChObj,
CSL_EDMA3,
&chParam,
&status);
/* Channel setup */
hParamBasic = CSL_edma3GetParamHandle(hChannel,CSL_EDMA3_CHA_XEVT0, &status);
/* param setup */
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
CSL_EDMA3_CHA_XEVT0, \
CSL_EDMA3_TCC_NORMAL, \
CSL_EDMA3_FIFOWIDTH_32BIT, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A,\
CSL_EDMA3_ADDRMODE_INCR,\
CSL_EDMA3_ADDRMODE_INCR \
);
myParamSetup.srcAddr = (Uint32)srcBuff;
myParamSetup.dstAddr = (Uint32)CSL_MCBSP_0_TX_EDMA_REGS;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(4,16);
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(4,0);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,1);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
myParamSetup.cCnt = 1;
CSL_edma3HwChannelSetupParam (hChannel, CSL_EDMA3_CHA_XEVT0);
CSL_edma3HwChannelSetupQue(hChannel, CSL_EDMA3_QUE_1);
CSL_edma3ParamSetup(hParamBasic,&myParamSetup);
CSL_edma3HwChannelControl(hChannel, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL);
/********************************Setup for Rx******************************/
/* Open Receive channel */
chParam.regionNum = CSL_EDMA3_REGION_0;
chParam.chaNum = CSL_EDMA3_CHA_REVT0;
hChannel1 = CSL_edma3ChannelOpen(&ChObj1,
CSL_EDMA3,
&chParam,
&status);
/* Channel Setup */
hParamBasic1 = CSL_edma3GetParamHandle(hChannel1,CSL_EDMA3_CHA_REVT0,&status);
/* Param Setup */
myParamSetup1.option = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,\
CSL_EDMA3_CHA_REVT0, \
CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_32BIT, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR \
);
myParamSetup1.srcAddr = (Uint32)CSL_MCBSP_0_RX_EDMA_REGS;
myParamSetup1.dstAddr = (Uint32)dstBuff;
myParamSetup1.aCntbCnt = CSL_EDMA3_CNT_MAKE(4,16);
myParamSetup1.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,4);
myParamSetup1.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(
CSL_EDMA3_LINK_NULL,1);
myParamSetup1.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
myParamSetup1.cCnt = 1;
CSL_edma3HwChannelSetupParam (hChannel1, CSL_EDMA3_CHA_REVT0);
CSL_edma3HwChannelSetupQue(hChannel1, CSL_EDMA3_QUE_1);
CSL_edma3ParamSetup(hParamBasic1, &myParamSetup1);
EventRecord.handler = &eventEdmaHandler;
EventRecord.arg = (void*)(hModule);
CSL_intcPlugEventHandler(hIntcEdma,&EventRecord);
/* Enabling event edma */
CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL);
/* Hook up the EDMA Event with an ISR */
EdmaEventHook(CSL_EDMA3_CHA_XEVT0, txmyIsr);
EdmaEventHook(CSL_EDMA3_CHA_REVT0, rxmyIsr);
/* Enable the interrupts */
regionIntr.region = CSL_EDMA3_REGION_0;
regionIntr.intr = 0x3000;
regionIntr.intrh = 0;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,®ionIntr);
/* Enable the receive channel */
CSL_edma3HwChannelControl(hChannel1, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL);
/* Enable MCBSP transmit and receive */
ctrlMask = CSL_MCBSP_CTRL_TX_ENABLE | CSL_MCBSP_CTRL_RX_ENABLE;
CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
WAIT_FOR_1_CLK;
/* wait for Transmit complete Interrupt */
while (!intFlag);
/* wait for Transmit complete Interrupt */
while (!rxintFlag);
/* Disable cahnnels and clear the EDMA event registers */
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
/* clear the error registers */
chErrClear.missed = TRUE;
chErrClear.secEvt = TRUE;
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear);
CSL_edma3ChannelClose(hChannel);
CSL_edma3ChannelClose(hChannel1);
CSL_edma3Close(hModule);
CSL_intcClose (hIntcEdma);
}
/*
* ============================================================================
* @func txmyIsr
*
* @desc
* This function is the interrupt service routine for transmit data
*
* @arg
* None
*
* @return
* None
* ============================================================================
*/
void txmyIsr()
{
intFlag = 1;
}
/*
* ============================================================================
* @func rxmyIsr
*
* @desc
* This function is the interrupt service routine for receive data
*
* @arg
* None
*
* @return
* None
* ============================================================================
*/
void rxmyIsr()
{
rxintFlag = 1;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_intc.h | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_intc.h
*
* @path $(CSLPATH)\inc
*
* @desc Header file for functional layer CSL of INTC
*
*/
/** @mainpage Interrupt Controller
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to detail the CSL APIs for the
* INTC Module.
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
* -# INTC: Interrupt Controller
*
* @subsection References
* -# CSL 3.x Technical Requirements Specifications Version 0.5, dated
* May 14th, 2003
* -# Inerrupt Controller Specification
*
* @subsection Assumptions
* The abbreviations INTC, Intc and intc have been used throughout this
* document to refer to Interrupt Controller
*/
/* =============================================================================
* Revision History
* ===============
* 12-Jun-2004 <NAME> File Created
* 14-Mar-2005 brn Moved the Event Ids to soc64plus.h
* 16-Mar-2005 brn modified for doxygen documentation
* =============================================================================
*/
#ifndef _CSL_INTC_H_
#define _CSL_INTC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <cslr_intc.h>
#include <soc.h>
/** Number of Events in the System */
#define CSL_INTC_EVENTID_CNT 128
/** Indicates there is no associated event-handler */
#define CSL_INTC_EVTHANDLER_NONE ((CSL_IntcEventHandler) 0)
/** Invalid handle */
#define CSL_INTC_BADHANDLE (0)
/** None mapped */
#define CSL_INTC_MAPPED_NONE (-1)
/**
* Interrupt Vector IDs
*/
typedef enum {
/** Should be used only along with CSL_intcHookIsr() */
CSL_INTC_VECTID_NMI = 1,
/** CPU Vector 4 */
CSL_INTC_VECTID_4 = 4,
/** CPU Vector 5 */
CSL_INTC_VECTID_5 = 5,
/** CPU Vector 6 */
CSL_INTC_VECTID_6 = 6,
/** CPU Vector 7 */
CSL_INTC_VECTID_7 = 7,
/** CPU Vector 8 */
CSL_INTC_VECTID_8 = 8,
/** CPU Vector 9 */
CSL_INTC_VECTID_9 = 9,
/** CPU Vector 10 */
CSL_INTC_VECTID_10 = 10,
/** CPU Vector 11 */
CSL_INTC_VECTID_11 = 11,
/** CPU Vector 12 */
CSL_INTC_VECTID_12 = 12,
/** CPU Vector 13 */
CSL_INTC_VECTID_13 = 13,
/** CPU Vector 14 */
CSL_INTC_VECTID_14 = 14,
/** CPU Vector 15 */
CSL_INTC_VECTID_15 = 15,
/** Should be used at the time of opening an Event handle
* to specify that the event needs to go to the combiner
*/
CSL_INTC_VECTID_COMBINE = 16,
/** Should be used at the time of opening an Event handle
* to specify that the event needs to go to the exception
* combiner.
*/
CSL_INTC_VECTID_EXCEP = 17
} CSL_IntcVectId;
/**
* Interrupt Event IDs
*/
typedef Int CSL_IntcEventId;
/**
* Enumeration of the control commands
*
* These are the control commands that could be used with
* CSL_intcHwControl(..). Some of the commands expect an
* argument as documented along-side the description of
* the command.
*/
typedef enum {
/**
* @brief Enables the event
* @param CSL_IntcEnableState
*/
CSL_INTC_CMD_EVTENABLE = 0,
/**
* @brief Disables the event
* @param CSL_IntcEnableState
*/
CSL_INTC_CMD_EVTDISABLE = 1,
/**
* @brief Sets the event manually
* @param None
*/
CSL_INTC_CMD_EVTSET =2,
/**
* @brief Clears the event (if pending)
* @param None
*/
CSL_INTC_CMD_EVTCLEAR =3,
/**
* @brief Enables the Drop Event detection feature for this event
* @param None
*/
CSL_INTC_CMD_EVTDROPENABLE =4,
/**
* @brief Disables the Drop Event detection feature for this event
* @param None
*/
CSL_INTC_CMD_EVTDROPDISABLE =5,
/**
* @brief To be used ONLY to invoke the associated Function handle
* with Event when the user is writing an exception handling routine.
* @param None
*/
CSL_INTC_CMD_EVTINVOKEFUNCTION = 6
} CSL_IntcHwControlCmd;
/**
* Enumeration of the queries
*
* These are the queries that could be used with CSL_intcGetHwStatus(..).
* The queries return a value through the object pointed to by the pointer
* that it takes as an argument. The argument supported by the query is
* documented along-side the description of the query.
*/
typedef enum {
/**
* @brief The Pend Status of the Event is queried
* @param Bool
*/
CSL_INTC_QUERY_PENDSTATUS
}CSL_IntcHwStatusQuery;
/**
* Enumeration of the exception mask registers
*
* These are the symbols used along with the value to be programmed
* into the Exception mask register.
*/
typedef enum {
/**
* @brief Symbol for EXPMASK[0]
* @param BitMask for EXPMASK0
*/
CSL_INTC_EXCEP_0TO31 = 0,
/**
* @brief Symbol for EXPMASK[1]
* @param BitMask for EXPMASK1
*/
CSL_INTC_EXCEP_32TO63 = 1,
/**
* @brief Symbol for EXPMASK[2]
* @param BitMask for EXPMASK2
*/
CSL_INTC_EXCEP_64TO95 = 2,
/**
* @brief Symbol for EXPMASK[3]
* @param BitMask for EXPMASK3
*/
CSL_INTC_EXCEP_96TO127 = 3
} CSL_IntcExcepEn;
/**
* Enumeration of the exception
* These are the symbols used along with the Exception Clear API
*/
typedef enum {
/**
* @brief Symbol for NMI
* @param None
*/
CSL_INTC_EXCEPTION_NMI = 31,
/**
* @brief Symbol for External Exception
* @param None
*/
CSL_INTC_EXCEPTION_EXT = 30,
/**
* @brief Symbol for Internal Exception
* @param None
*/
CSL_INTC_EXCEPTION_INT = 1,
/**
* @brief Symbol for Software Exception
* @param None
*/
CSL_INTC_EXCEPTION_SW = 0
} CSL_IntcExcep;
/**
* Event Handler pointer
*
* Event handlers ought to conform to this type
*/
typedef void (* CSL_IntcEventHandler)(void *);
/**
* Event Handler Record
*
* Used to set-up the event-handler using CSL_intcPlugEventHandler(..)
*/
typedef struct {
/** pointer to the event handler */
CSL_IntcEventHandler handler;
/** the argument to be passed to the handler when it is invoked */
void * arg;
} CSL_IntcEventHandlerRecord;
/**
* INTC Module Context.
*/
typedef struct {
/** Pointer to the event handle record */
CSL_IntcEventHandlerRecord* eventhandlerRecord;
/** Event allocation mask */
CSL_BitMask32 eventAllocMask[(CSL_INTC_EVENTID_CNT + 31) / 32];
/** Number of event entries */
Uint16 numEvtEntries;
/** Reserved */
Int8 offsetResv[128];
} CSL_IntcContext;
/**
* Event enable state
*/
typedef Uint32 CSL_IntcEventEnableState;
/**
* Global Interrupt enable state
*/
typedef Uint32 CSL_IntcGlobalEnableState;
/**
* The interrupt handle object
* This object is used by the handle to identify the event.
*/
typedef struct CSL_IntcObj {
/** The event-id */
CSL_IntcEventId eventId;
/** The vector-id */
CSL_IntcVectId vectId;
} CSL_IntcObj;
/**
* The drop status structure
*
* This object is used along with the CSL_intcQueryDropStatus()
* API.
*/
typedef struct {
/** whether dropped/not */
Bool drop;
/** The event-id */
CSL_IntcEventId eventId;
/** The vect-id */
CSL_IntcVectId vectId;
}CSL_IntcDropStatus;
/**
* INTC module parameters for open
*
* This is equivalent to the Vector Id for the event number.
*/
typedef CSL_IntcVectId CSL_IntcParam;
/**
* The interrupt handle
*
* This is returned by the CSL_intcOpen(..) API. The handle is used
* to identify the event of interest in all INTC calls.
*/
typedef struct CSL_IntcObj* CSL_IntcHandle;
/* ============================================================================
* @n@b CSL_intcInit
*
* @b Description
* @n This is the initialization function for the INTC. This function is
* idempotent in that calling it many times is same as calling it once.
* This function initializes the CSL data structures, and doesn't affect
* the H/W.
*
* @b Arguments
* @verbatim
pContext Pointer to module-context structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n This function should be called before using any of the CSL INTC APIs.
* The context should be initialized such that numEvtEntries is equal to
* the number of records capable of being held in the eventhandlerRecord
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
CSL_IntcEventHandlerRecord recordTable[10];
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK) {
exit;
}
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcInit (
CSL_IntcContext *pContext
);
/* ============================================================================
* @n@b CSL_intcOpen
*
* @b Description
* @n The API would reserve an interrupt-event for use. It returns
* a valid handle to the event only if the event is not currently
* allocated. The user could release the event after use by calling
* CSL_intcClose(..). The CSL-object ('intcObj') that the user
* passes would be used to store information pertaining handle.
*
* @b Arguments
* @verbatim
pIntcObj pointer to the CSL-object allocated by the user
eventId the event-id of the interrupt
param pointer to the Intc specific parameter
pStatus (optional) pointer for returning status of the
function call
@endverbatim
*
* <b> Return Value </b> CSL_IntcHandle
* @n Valid INTC handle identifying the event
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n 1. INTC object structure is populated
* @n 2. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid intc handle is returned
* @li CSL_ESYS_FAIL The open command failed
*
* @b Modifies
* @n 1. The status variable
* @n 2. INTC object structure
*
* @b Example:
* @verbatim
CSL_IntcObj intcObj20;
CSL_IntcGlobalEnableState state;
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
context.numEvtEntries = 0;
context.eventhandlerRecord = NULL;
// Init Module
CSL_intcInit(&context);
// NMI Enable
CSL_intcGlobalNmiEnable();
// Enable Global Interrupts
intStat = CSL_intcGlobalEnable(&state);
// Opening a handle for the Event 20 at vector id 4
vectId = CSL_INTC_VECTID_4;
hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL);
// Close handle
CSL_IntcClose(hIntc20);
@endverbatim
* =============================================================================
*/
CSL_IntcHandle CSL_intcOpen (
CSL_IntcObj *intcObj,
CSL_IntcEventId eventId,
CSL_IntcParam *params,
CSL_Status *status
);
/* =============================================================================
* @n@b CSL_intcClose
*
* @b Description
* @n This intc Handle can no longer be used to access the event. The event is
* de-allocated and further access to the event resources are possible only after
* opening the event object again.
*
* @b Arguments
* @verbatim
hIntc Handle identifying the event
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_FAIL - Close failed
*
* @b Example
* @verbatim
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
CSL_IntcObj intcObj20;
CSL_IntcHandle hIntc20;
CSL_IntcEventHandlerRecord recordTable[10];
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK) {
exit;
// Opening a handle for the Event 20 at vector id 4
vectId = CSL_INTC_VECTID_4;
hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL);
// Close handle
CSL_IntcClose(hIntc20);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcClose (
CSL_IntcHandle hIntc
);
/* ============================================================================
* @n@b CSL_intcPlugEventHandler
*
* @b Description
* @n Associate an event-handler with an event
* CSL_intcPlugEventHandler(..) ties an event-handler to an event; so
* that the occurence of the event, would result in the event-handler
* being invoked.
*
* @b Arguments
* @verbatim
hIntc Handle identying the interrupt-event
eventHandlerRecord Provides the details of the event-handler
@endverbatim
*
* <b> Return Value </b>
* @n Returns the address of the previous handler
*
* @b Example:
* @verbatim
CSL_IntcObj intcObj20;
CSL_IntcGlobalEnableState state;
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
context.numEvtEntries = 0;
context.eventhandlerRecord = NULL;
// Init Module
CSL_intcInit(&context);
// NMI Enable
CSL_intcGlobalNmiEnable();
// Enable Global Interrupts
intStat = CSL_intcGlobalEnable(&state);
// Opening a handle for the Event 20 at vector id 4
vectId = CSL_INTC_VECTID_4;
hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL);
EventRecord.handler = &event20Handler;
EventRecord.arg = hIntc20;
CSL_intcPlugEventHandler(hIntc20,&EventRecord);
// Close handle
CSL_IntcClose(hIntc20);
}
void event20Handler( CSL_IntcHandle hIntc)
{
}
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcPlugEventHandler (
CSL_IntcHandle hIntc,
CSL_IntcEventHandlerRecord *eventHandlerRecord
);
/* ============================================================================
* @n@b CSL_intcHookIsr
*
* @b Description
* @n Hook up an exception handler
* This API hooks up the handler to the specified exception.
* Note: In this case, it is done by inserting a B(ranch) instruction
* to the handler. Because of the restriction in the instruction
* th handler must be within 32MB of the exception vector.
* Also, the function assumes that the exception vector table is
* located at its default ("low") address.
*
* @b Arguments
* @verbatim
vectId Interrupt Vector identifier
isrAddr Pointer to the handler
@endverbatim
*
* @b Example:
* @verbatim
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
CSL_IntcObj intcObj20;
CSL_IntcHandle hIntc20;
CSL_IntcDropStatus drop;
CSL_IntcEventHandlerRecord recordTable[10];
CSL_IntcGlobalEnableState state;
Uint32 intrStat;
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK)
exit;
// Opening a handle for the Event 20 at vector id 4
vectId = CSL_INTC_VECTID_4;
hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL);
CSL_intcNmiEnable();
// Enable Global Interrupts
intStat = CSL_intcGlobalEnable(&state);
// Hook Isr appropriately
CSL_intcHookIsr(CSL_INTC_VECTID_4,&isrVect4);
...
}
interrupt void isrVect4()
{
}
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcHookIsr (
CSL_IntcVectId vectId,
void *isrAddr
);
/* ============================================================================
* @n@b CSL_intcHwControl
*
* @b Description
* @n Perform a control-operation. This API is used to invoke any of the
* supported control-operations supported by the module.
*
* @b Arguments
* @verbatim
hIntc Handle identifying the event
command The command to this API indicates the action to be
taken on INTC.
commandArg An optional argument.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - HwControl successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
*
* <b> Pre Condition </b>
* @n CSL_intcOpen() must be invoked before this call.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of INTC.
*
* @b Example
* @verbatim
CSL_IntcObj intcObj20;
CSL_IntcGlobalEnableState state;
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
context.numEvtEntries = 0;
context.eventhandlerRecord = NULL;
// Init Module
CSL_intcInit(&context);
// NMI Enable
CSL_intcGlobalNmiEnable();
// Enable Global Interrupts
intStat = CSL_intcGlobalEnable(&state);
// Opening a handle for the Event 20 at vector id 4
vectId = CSL_INTC_VECTID_4;
hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL);
CSL_intcHwControl(hIntc20,CSL_INTC_CMD_EVTENABLE,NULL);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcHwControl (
CSL_IntcHandle hIntc,
CSL_IntcHwControlCmd command,
void *commandArg
);
/* ============================================================================
* @n@b CSL_intcGetHwStatus
*
* @b Description
* @n Queries the peripheral for status. The CSL_intcGetHwStatus(..) API
* could be used to retrieve status or configuration information from
* the peripheral. The user must allocate an object that would hold
* the retrieved information and pass a pointer to it to the function.
* The type of the object is specific to the query-command.
*
* @b Arguments
* @verbatim
hIntc Handle identifying the event
query The query to this API of INTC which indicates the
status to be returned.
answer Placeholder to return the status.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVQUERY - Invalid query
* @li CSL_ESYS_NOTSUPPORTED - Action not supported
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
CSL_IntcObj intcObj20;
CSL_IntcHandle hIntc20;
CSL_IntcEventHandlerRecord recordTable[10];
CSL_IntcGlobalEnableState state;
Uint32 intrStat;
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK)
exit;
// Opening a handle for the Event 20 at vector id 4
vectId = CSL_INTC_VECTID_4;
hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL);
// NMI Enable
CSL_intcGlobalNmiEnable();
// Enable Global Interrupts
intStat = CSL_intcGlobalEnable(&state);
do {
CSL_intcGetHwStatus(hIntc20,CSL_INTC_QUERY_PENDSTATUS, \
(void*)&intrStat);
} while (!stat);
// Close handle
CSL_IntcClose(hIntc20);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcGetHwStatus (
CSL_IntcHandle hIntc,
CSL_IntcHwStatusQuery query,
void *response
);
/** ============================================================================
* @n@b CSL_intcGlobalEnable
*
* @b Description
* @n Globally enable interrupts.
* The API enables the global interrupt by manipulating the processor's
* global interrupt enable/disable flag. If the user wishes to restore
* the enable-state at a later point, they may store the current state
* using the parameter, which could be used with CSL_intcGlobalRestore(..).
* CSL_intcGlobalEnable(..) must be called from a privileged mode.
*
* @b Arguments
* @verbatim
prevState (Optional) Pointer to object that would store current
stateObject that contains information about previous state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_intcGlobalEnable(NULL);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcGlobalEnable (
CSL_IntcGlobalEnableState * prevState
);
/** ============================================================================
* @n@b CSL_intcGlobalDisable
*
* @b Description
* @n Globally disable interrupts.
* The API disables the global interrupt by manipulating the processor's
* global interrupt enable/disable flag. If the user wishes to restore
* the enable-state at a later point, they may store the current state
* using the parameter, which could be used with CSL_intcGlobalRestore(..).
* CSL_intcGlobalDisable(..) must be called from a privileged mode.
*
* @b Arguments
* @verbatim
prevState (Optional) Pointer to object that would store current
stateObject that contains information about previous state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_intcGlobalDisable(NULL);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcGlobalDisable (
CSL_IntcGlobalEnableState *prevState
);
/** ============================================================================
* @n@b CSL_intcGlobalRestore
*
* @b Description
* @n Restore global interrupt enable/disable to a previous state.
* The API restores the global interrupt enable/disable state to a previous
* state as recorded by the global-event-enable state passed as an argument.
* CSL_intcGlobalRestore(..) must be called from a privileged mode.
*
* @b Arguments
* @verbatim
prevState Object containing information about previous state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_IntcGlobalEnableState prevState;
CSL_intcGlobalRestore(prevState);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcGlobalRestore (
CSL_IntcGlobalEnableState prevState
);
/** ============================================================================
* @n@b CSL_intcGlobalNmiEnable
*
* @b Description
* @n This API enables global NMI
*
*
* @b Arguments
* @verbatim
None
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_intcGlobalNmiEnable();
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcGlobalNmiEnable (void);
/** ============================================================================
* @n@b CSL_intcGlobalExcepEnable
*
* @b Description
* @n This API enables global exception
*
*
* @b Arguments
* @verbatim
None
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_intcGlobalExcepEnable();
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcGlobalExcepEnable (void);
/** ============================================================================
* @n@b CSL_intcGlobalExtExcepEnable
*
* @b Description
* @n This API enables external exception
*
*
* @b Arguments
* @verbatim
None
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_intcGlobalExtExcepEnable();
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcGlobalExtExcepEnable (void);
/** ============================================================================
* @n@b CSL_intcGlobalExcepClear
*
* @b Description
* @n This API clears Global Exceptions
*
*
* @b Arguments
* @verbatim
exc Exception to be cleared NMI/SW/EXT/INT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_intcGlobalExcepClear(exc);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcGlobalExcepClear (
CSL_IntcExcep exc
);
/* ============================================================================
* @n@b CSL_intcExcepAllEnable
*
* @b Description
* @n This API enables all exceptions
*
*
* @b Arguments
* @verbatim
excepMask Exception Mask
excVal Event Value
prevState Pre state information
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_IntcExcepEn excepMask;
CSL_BitMask32 excVal;
CSL_IntcEventEnableState *prevState;
CSL_intcExcepAllEnable(excepMask, excVal, prevState);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcExcepAllEnable (
CSL_IntcExcepEn excepMask,
CSL_BitMask32 excVal,
CSL_BitMask32 *prevState
);
/* ============================================================================
* @n@b CSL_intcExcepAllDisable
*
* @b Description
* @n This API disables all exceptions
*
*
* @b Arguments
* @verbatim
excepMask Exception Mask
excVal Event Value
prevState Pre state informationT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_IntcExcepEn excepMask;
CSL_BitMask32 excVal;
CSL_IntcEventEnableState *prevState;
CSL_intcExcepAllDisable(excepMask, excVal, prevState);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcExcepAllDisable (
CSL_IntcExcepEn excepMask,
CSL_BitMask32 excVal,
CSL_BitMask32 *prevState
);
/* ============================================================================
* @n@b CSL_intcExcepAllRestore
*
* @b Description
* @n This API restores all exceptions
*
*
* @b Arguments
* @verbatim
excepMask Exception Mask 0/1/2/3
prevState BitMask to be restored
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_IntcExcepEn excepMask;
CSL_IntcEventEnableState *prevState;
CSL_intcExcepAllRestore(excepMask, prevState);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcExcepAllRestore (
CSL_IntcExcepEn excepMask,
CSL_IntcGlobalEnableState restoreVal
);
/* ============================================================================
* @n@b CSL_intcExcepAllClear
*
* @b Description
* @n This API clears all exceptions
*
*
* @b Arguments
* @verbatim
excepMask Exception Mask
excVal Holder for the event bitmask to be cleared
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_IntcExcepEn excepMask;
CSL_BitMask32 excVal;
CSL_intcExcepAllClear(excepMask, excVal);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcExcepAllClear (
CSL_IntcExcepEn excepMask,
CSL_BitMask32 excVal
);
/* ============================================================================
* @n@b CSL_intcExcepAllStatus
*
* @b Description
* @n This API is to get the exception status query
*
*
* @b Arguments
* @verbatim
excepMask Exception Mask
status status of exception
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_IntcExcepEn excepMask;
CSL_BitMask32 *status;
CSL_intcExcepAllStatus(excepMask, status);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcExcepAllStatus (
CSL_IntcExcepEn excepMask,
CSL_BitMask32 *status
);
/* ============================================================================
* @n@b CSL_intcQueryDropStatus
*
* @b Description
* @n This API is to get the exception drop status query
*
*
* @b Arguments
* @verbatim
dropStat place holder for the drop status
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK on success
*
* @b Example:
* @verbatim
CSL_IntcDropStatus *dropStat;
CSL_intcQueryDropStatus(dropStat);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_intcQueryDropStatus (
CSL_IntcDropStatus *dropStat
);
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_pci.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_pci.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for PCI
*/
#ifndef _CSLR_PCI_H_
#define _CSLR_PCI_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint8 RSVD0[16];
volatile Uint32 PCISTATSET;
volatile Uint32 PCISTATCLR;
volatile Uint8 RSVD1[8];
volatile Uint32 PCIHINTSET;
volatile Uint32 PCIHINTCLR;
volatile Uint8 RSVD2[8];
volatile Uint32 PCIBINTSET;
volatile Uint32 PCIBINTCLR;
volatile Uint8 RSVD3[200];
volatile Uint32 PCIVENDEVMIR;
volatile Uint32 PCICSRMIR;
volatile Uint32 PCICLREVMIR;
volatile Uint32 PCICLINEMIR;
volatile Uint32 PCIBAR0MSK;
volatile Uint32 PCIBAR1MSK;
volatile Uint32 PCIBAR2MSK;
volatile Uint32 PCIBAR3MSK;
volatile Uint32 PCIBAR4MSK;
volatile Uint32 PCIBAR5MSK;
volatile Uint8 RSVD4[4];
volatile Uint32 PCISUBIDMIR;
volatile Uint8 RSVD5[4];
volatile Uint32 PCICPBPTRMIR;
volatile Uint8 RSVD6[4];
volatile Uint32 PCILGINTMIR;
volatile Uint8 RSVD7[64];
volatile Uint32 PCISLVCNTL;
volatile Uint8 RSVD8[60];
volatile Uint32 PCIBAR0TRL;
volatile Uint32 PCIBAR1TRL;
volatile Uint32 PCIBAR2TRL;
volatile Uint32 PCIBAR3TRL;
volatile Uint32 PCIBAR4TRL;
volatile Uint32 PCIBAR5TRL;
volatile Uint8 RSVD9[8];
volatile Uint32 PCIBARMIR[6];
volatile Uint8 RSVD10[264];
volatile Uint32 PCIMCFGDAT;
volatile Uint32 PCIMCFGADR;
volatile Uint32 PCIMCFGCMD;
volatile Uint8 RSVD11[4];
volatile Uint32 PCIMSTCFG;
volatile Uint32 PCIADDSUB[32];
volatile Uint32 PCIVENDEVPRG;
volatile Uint32 PCICMDSTATPRG;
volatile Uint32 PCICLREVPRG;
volatile Uint32 PCISUBIDPRG;
volatile Uint32 PCIMAXLGPRG;
volatile Uint32 PCILRSTREG;
volatile Uint32 PCICFGDONE;
volatile Uint32 PCIBAR0MPRG;
volatile Uint32 PCIBAR1MPRG;
volatile Uint32 PCIBAR2MPRG;
volatile Uint32 PCIBAR3MPRG;
volatile Uint32 PCIBAR4MPRG;
volatile Uint32 PCIBAR5MPRG;
volatile Uint32 PCIBAR0PRG;
volatile Uint32 PCIBAR1PRG;
volatile Uint32 PCIBAR2PRG;
volatile Uint32 PCIBAR3PRG;
volatile Uint32 PCIBAR4PRG;
volatile Uint32 PCIBAR5PRG;
volatile Uint32 PCIBAR0TRLPRG;
volatile Uint32 PCIBAR1TRLPRG;
volatile Uint32 PCIBAR2TRLPRG;
volatile Uint32 PCIBAR3TRLPRG;
volatile Uint32 PCIBAR4TRLPRG;
volatile Uint32 PCIBAR5TRLPRG;
volatile Uint32 PCIBASENPRG;
} CSL_PciRegs;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* PCISTATSET */
#define CSL_PCI_PCISTATSET_DSPINT_MASK (0x80000000u)
#define CSL_PCI_PCISTATSET_DSPINT_SHIFT (0x0000001Fu)
#define CSL_PCI_PCISTATSET_DSPINT_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATSET_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCISTATSET_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCISTATSET_PERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATSET_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCISTATSET_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCISTATSET_SERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATSET_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCISTATSET_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCISTATSET_MS_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATSET_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCISTATSET_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCISTATSET_TGT_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATSET_RESETVAL (0x00000000u)
/* PCISTATCLR */
#define CSL_PCI_PCISTATCLR_DSPINT_MASK (0x80000000u)
#define CSL_PCI_PCISTATCLR_DSPINT_SHIFT (0x0000001Fu)
#define CSL_PCI_PCISTATCLR_DSPINT_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATCLR_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCISTATCLR_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCISTATCLR_PERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATCLR_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCISTATCLR_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCISTATCLR_SERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATCLR_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCISTATCLR_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCISTATCLR_MS_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATCLR_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCISTATCLR_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCISTATCLR_TGT_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCISTATCLR_RESETVAL (0x00000000u)
/* PCIHINTSET */
#define CSL_PCI_PCIHINTSET_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCIHINTSET_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCIHINTSET_PERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIHINTSET_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCIHINTSET_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCIHINTSET_SERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIHINTSET_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCIHINTSET_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCIHINTSET_MS_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIHINTSET_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCIHINTSET_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCIHINTSET_TGT_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIHINTSET_RESETVAL (0x00000000u)
/* PCIHINTCLR */
#define CSL_PCI_PCIHINTCLR_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCIHINTCLR_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCIHINTCLR_PERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIHINTCLR_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCIHINTCLR_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCIHINTCLR_SERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIHINTCLR_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCIHINTCLR_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCIHINTCLR_MS_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIHINTCLR_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCIHINTCLR_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCIHINTCLR_TGT_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIHINTCLR_RESETVAL (0x00000000u)
/* PCIBINTSET */
#define CSL_PCI_PCIBINTSET_DSPINT_MASK (0x80000000u)
#define CSL_PCI_PCIBINTSET_DSPINT_SHIFT (0x0000001Fu)
#define CSL_PCI_PCIBINTSET_DSPINT_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTSET_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCIBINTSET_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCIBINTSET_PERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTSET_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCIBINTSET_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCIBINTSET_SERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTSET_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCIBINTSET_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCIBINTSET_MS_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTSET_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCIBINTSET_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCIBINTSET_TGT_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTSET_RESETVAL (0x00000000u)
/* PCIBINTCLR */
#define CSL_PCI_PCIBINTCLR_DSPINT_MASK (0x80000000u)
#define CSL_PCI_PCIBINTCLR_DSPINT_SHIFT (0x0000001Fu)
#define CSL_PCI_PCIBINTCLR_DSPINT_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTCLR_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCIBINTCLR_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCIBINTCLR_PERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTCLR_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCIBINTCLR_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCIBINTCLR_SERR_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTCLR_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCIBINTCLR_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCIBINTCLR_MS_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTCLR_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCIBINTCLR_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCIBINTCLR_TGT_ABRT_DET_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBINTCLR_RESETVAL (0x00000000u)
/* PCIVENDEVMIR */
#define CSL_PCI_PCIVENDEVMIR_DEV_ID_MASK (0xFFFF0000u)
#define CSL_PCI_PCIVENDEVMIR_DEV_ID_SHIFT (0x00000010u)
#define CSL_PCI_PCIVENDEVMIR_DEV_ID_RESETVAL (0x0000B000u)
#define CSL_PCI_PCIVENDEVMIR_VEN_ID_MASK (0x0000FFFFu)
#define CSL_PCI_PCIVENDEVMIR_VEN_ID_SHIFT (0x00000000u)
#define CSL_PCI_PCIVENDEVMIR_VEN_ID_RESETVAL (0x0000104Cu)
#define CSL_PCI_PCIVENDEVMIR_RESETVAL (0xB000104Cu)
/* PCICSRMIR */
#define CSL_PCI_PCICSRMIR_DET_PAR_ERR_MASK (0x80000000u)
#define CSL_PCI_PCICSRMIR_DET_PAR_ERR_SHIFT (0x0000001Fu)
#define CSL_PCI_PCICSRMIR_DET_PAR_ERR_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_SIG_SYS_ERR_MASK (0x40000000u)
#define CSL_PCI_PCICSRMIR_SIG_SYS_ERR_SHIFT (0x0000001Eu)
#define CSL_PCI_PCICSRMIR_SIG_SYS_ERR_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_RCV_MS_ABRT_MASK (0x20000000u)
#define CSL_PCI_PCICSRMIR_RCV_MS_ABRT_SHIFT (0x0000001Du)
#define CSL_PCI_PCICSRMIR_RCV_MS_ABRT_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_RCV_TGT_ABRT_MASK (0x10000000u)
#define CSL_PCI_PCICSRMIR_RCV_TGT_ABRT_SHIFT (0x0000001Cu)
#define CSL_PCI_PCICSRMIR_RCV_TGT_ABRT_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_SIG_TGT_ABRT_MASK (0x08000000u)
#define CSL_PCI_PCICSRMIR_SIG_TGT_ABRT_SHIFT (0x0000001Bu)
#define CSL_PCI_PCICSRMIR_SIG_TGT_ABRT_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_DEVSEL_TIM_MASK (0x06000000u)
#define CSL_PCI_PCICSRMIR_DEVSEL_TIM_SHIFT (0x00000019u)
#define CSL_PCI_PCICSRMIR_DEVSEL_TIM_RESETVAL (0x00000001u)
#define CSL_PCI_PCICSRMIR_MS_DPAR_REP_MASK (0x01000000u)
#define CSL_PCI_PCICSRMIR_MS_DPAR_REP_SHIFT (0x00000018u)
#define CSL_PCI_PCICSRMIR_MS_DPAR_REP_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_CAP_MASK (0x00800000u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_CAP_SHIFT (0x00000017u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_CAP_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_66MHZ_CAP_MASK (0x00200000u)
#define CSL_PCI_PCICSRMIR_66MHZ_CAP_SHIFT (0x00000015u)
#define CSL_PCI_PCICSRMIR_66MHZ_CAP_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_CAP_LIST_IMPL_MASK (0x00100000u)
#define CSL_PCI_PCICSRMIR_CAP_LIST_IMPL_SHIFT (0x00000014u)
#define CSL_PCI_PCICSRMIR_CAP_LIST_IMPL_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_INT_STAT_MASK (0x00080000u)
#define CSL_PCI_PCICSRMIR_INT_STAT_SHIFT (0x00000013u)
#define CSL_PCI_PCICSRMIR_INT_STAT_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_INT_DIS_MASK (0x00000400u)
#define CSL_PCI_PCICSRMIR_INT_DIS_SHIFT (0x0000000Au)
#define CSL_PCI_PCICSRMIR_INT_DIS_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_EN_MASK (0x00000200u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_EN_SHIFT (0x00000009u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_EN_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_SERR_N_EN_MASK (0x00000100u)
#define CSL_PCI_PCICSRMIR_SERR_N_EN_SHIFT (0x00000008u)
#define CSL_PCI_PCICSRMIR_SERR_N_EN_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_PAR_ERR_RES_MASK (0x00000040u)
#define CSL_PCI_PCICSRMIR_PAR_ERR_RES_SHIFT (0x00000006u)
#define CSL_PCI_PCICSRMIR_PAR_ERR_RES_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_VGA_PAL_SNP_MASK (0x00000020u)
#define CSL_PCI_PCICSRMIR_VGA_PAL_SNP_SHIFT (0x00000005u)
#define CSL_PCI_PCICSRMIR_VGA_PAL_SNP_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_MEM_WRINV_EN_MASK (0x00000010u)
#define CSL_PCI_PCICSRMIR_MEM_WRINV_EN_SHIFT (0x00000004u)
#define CSL_PCI_PCICSRMIR_MEM_WRINV_EN_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_SP_CYCL_MASK (0x00000008u)
#define CSL_PCI_PCICSRMIR_SP_CYCL_SHIFT (0x00000003u)
#define CSL_PCI_PCICSRMIR_SP_CYCL_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_BUS_MS_MASK (0x00000004u)
#define CSL_PCI_PCICSRMIR_BUS_MS_SHIFT (0x00000002u)
#define CSL_PCI_PCICSRMIR_BUS_MS_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_MEM_SP_MASK (0x00000002u)
#define CSL_PCI_PCICSRMIR_MEM_SP_SHIFT (0x00000001u)
#define CSL_PCI_PCICSRMIR_MEM_SP_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_IO_SP_MASK (0x00000001u)
#define CSL_PCI_PCICSRMIR_IO_SP_SHIFT (0x00000000u)
#define CSL_PCI_PCICSRMIR_IO_SP_RESETVAL (0x00000000u)
#define CSL_PCI_PCICSRMIR_RESETVAL (0x02000000u)
/* PCICLREVMIR */
#define CSL_PCI_PCICLREVMIR_CL_CODE_MASK (0xFFFFFF00u)
#define CSL_PCI_PCICLREVMIR_CL_CODE_SHIFT (0x00000008u)
#define CSL_PCI_PCICLREVMIR_CL_CODE_RESETVAL (0x00000000u)
#define CSL_PCI_PCICLREVMIR_REV_ID_MASK (0x000000FFu)
#define CSL_PCI_PCICLREVMIR_REV_ID_SHIFT (0x00000000u)
#define CSL_PCI_PCICLREVMIR_REV_ID_RESETVAL (0x00000001u)
#define CSL_PCI_PCICLREVMIR_RESETVAL (0x00000001u)
/* PCICLINEMIR */
#define CSL_PCI_PCICLINEMIR_BIST_MASK (0xFF000000u)
#define CSL_PCI_PCICLINEMIR_BIST_SHIFT (0x00000018u)
#define CSL_PCI_PCICLINEMIR_BIST_RESETVAL (0x00000000u)
#define CSL_PCI_PCICLINEMIR_HDR_TYPE_MASK (0x00FF0000u)
#define CSL_PCI_PCICLINEMIR_HDR_TYPE_SHIFT (0x00000010u)
#define CSL_PCI_PCICLINEMIR_HDR_TYPE_RESETVAL (0x00000000u)
#define CSL_PCI_PCICLINEMIR_LAT_TMR_MASK (0x0000FF00u)
#define CSL_PCI_PCICLINEMIR_LAT_TMR_SHIFT (0x00000008u)
#define CSL_PCI_PCICLINEMIR_LAT_TMR_RESETVAL (0x00000000u)
#define CSL_PCI_PCICLINEMIR_CACHELN_SIZ_MASK (0x000000FFu)
#define CSL_PCI_PCICLINEMIR_CACHELN_SIZ_SHIFT (0x00000000u)
#define CSL_PCI_PCICLINEMIR_CACHELN_SIZ_RESETVAL (0x00000000u)
#define CSL_PCI_PCICLINEMIR_RESETVAL (0x00000000u)
/* PCIBAR0MSK */
#define CSL_PCI_PCIBAR0MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR0MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR0MSK_ADDRMASK_RESETVAL (0x0FF80000u)
#define CSL_PCI_PCIBAR0MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR0MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR0MSK_PREFETCH_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIBAR0MSK_RESETVAL (0xFF800008u)
/* PCIBAR1MSK */
#define CSL_PCI_PCIBAR1MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR1MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR1MSK_ADDRMASK_RESETVAL (0x0FFC0000u)
#define CSL_PCI_PCIBAR1MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR1MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR1MSK_PREFETCH_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIBAR1MSK_RESETVAL (0xFFC00008u)
/* PCIBAR2MSK */
#define CSL_PCI_PCIBAR2MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR2MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR2MSK_ADDRMASK_RESETVAL (0x0FF80000u)
#define CSL_PCI_PCIBAR2MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR2MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR2MSK_PREFETCH_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIBAR2MSK_RESETVAL (0xFF800008u)
/* PCIBAR3MSK */
#define CSL_PCI_PCIBAR3MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR3MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR3MSK_ADDRMASK_RESETVAL (0x0FF80000u)
#define CSL_PCI_PCIBAR3MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR3MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR3MSK_PREFETCH_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIBAR3MSK_RESETVAL (0xFF800008u)
/* PCIBAR4MSK */
#define CSL_PCI_PCIBAR4MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR4MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR4MSK_ADDRMASK_RESETVAL (0x0FF80000u)
#define CSL_PCI_PCIBAR4MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR4MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR4MSK_PREFETCH_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIBAR4MSK_RESETVAL (0xFF800008u)
/* PCIBAR5MSK */
#define CSL_PCI_PCIBAR5MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR5MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR5MSK_ADDRMASK_RESETVAL (0x0FF80000u)
#define CSL_PCI_PCIBAR5MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR5MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR5MSK_PREFETCH_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIBAR5MSK_RESETVAL (0xFF800008u)
/* PCISUBIDMIR */
#define CSL_PCI_PCISUBIDMIR_SUBSYS_ID_MASK (0xFFFF0000u)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_ID_SHIFT (0x00000010u)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_ID_RESETVAL (0x00000000u)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_VEN_ID_MASK (0x0000FFFFu)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_VEN_ID_SHIFT (0x00000000u)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_VEN_ID_RESETVAL (0x00000000u)
#define CSL_PCI_PCISUBIDMIR_RESETVAL (0x00000000u)
/* PCICPBPTRMIR */
#define CSL_PCI_PCICPBPTRMIR_CAP_MASK (0x000000FFu)
#define CSL_PCI_PCICPBPTRMIR_CAP_SHIFT (0x00000000u)
#define CSL_PCI_PCICPBPTRMIR_CAP_RESETVAL (0x00000040u)
#define CSL_PCI_PCICPBPTRMIR_RESETVAL (0x00000040u)
/* PCILGINTMIR */
#define CSL_PCI_PCILGINTMIR_MAX_LAT_MASK (0xFF000000u)
#define CSL_PCI_PCILGINTMIR_MAX_LAT_SHIFT (0x00000018u)
#define CSL_PCI_PCILGINTMIR_MAX_LAT_RESETVAL (0x00000000u)
#define CSL_PCI_PCILGINTMIR_MIN_GRNT_MASK (0x00FF0000u)
#define CSL_PCI_PCILGINTMIR_MIN_GRNT_SHIFT (0x00000010u)
#define CSL_PCI_PCILGINTMIR_MIN_GRNT_RESETVAL (0x00000000u)
#define CSL_PCI_PCILGINTMIR_INT_PIN_MASK (0x0000FF00u)
#define CSL_PCI_PCILGINTMIR_INT_PIN_SHIFT (0x00000008u)
#define CSL_PCI_PCILGINTMIR_INT_PIN_RESETVAL (0x00000001u)
#define CSL_PCI_PCILGINTMIR_INT_LINE_MASK (0x000000FFu)
#define CSL_PCI_PCILGINTMIR_INT_LINE_SHIFT (0x00000000u)
#define CSL_PCI_PCILGINTMIR_INT_LINE_RESETVAL (0x00000000u)
#define CSL_PCI_PCILGINTMIR_RESETVAL (0x00000100u)
/* PCISLVCNTL */
#define CSL_PCI_PCISLVCNTL_BASE5_EN_MASK (0x00200000u)
#define CSL_PCI_PCISLVCNTL_BASE5_EN_SHIFT (0x00000015u)
#define CSL_PCI_PCISLVCNTL_BASE5_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCISLVCNTL_BASE4_EN_MASK (0x00100000u)
#define CSL_PCI_PCISLVCNTL_BASE4_EN_SHIFT (0x00000014u)
#define CSL_PCI_PCISLVCNTL_BASE4_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCISLVCNTL_BASE3_EN_MASK (0x00080000u)
#define CSL_PCI_PCISLVCNTL_BASE3_EN_SHIFT (0x00000013u)
#define CSL_PCI_PCISLVCNTL_BASE3_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCISLVCNTL_BASE2_EN_MASK (0x00040000u)
#define CSL_PCI_PCISLVCNTL_BASE2_EN_SHIFT (0x00000012u)
#define CSL_PCI_PCISLVCNTL_BASE2_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCISLVCNTL_BASE1_EN_MASK (0x00020000u)
#define CSL_PCI_PCISLVCNTL_BASE1_EN_SHIFT (0x00000011u)
#define CSL_PCI_PCISLVCNTL_BASE1_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCISLVCNTL_BASE0_EN_MASK (0x00010000u)
#define CSL_PCI_PCISLVCNTL_BASE0_EN_SHIFT (0x00000010u)
#define CSL_PCI_PCISLVCNTL_BASE0_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_MUL_MASK (0x00000010u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_MUL_SHIFT (0x00000004u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_MUL_RESETVAL (0x00000000u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_LN_MASK (0x00000008u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_LN_SHIFT (0x00000003u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_LN_RESETVAL (0x00000000u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_MASK (0x00000004u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_SHIFT (0x00000002u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_RESETVAL (0x00000000u)
#define CSL_PCI_PCISLVCNTL_DIS_SLV_TOUT_MASK (0x00000002u)
#define CSL_PCI_PCISLVCNTL_DIS_SLV_TOUT_SHIFT (0x00000001u)
#define CSL_PCI_PCISLVCNTL_DIS_SLV_TOUT_RESETVAL (0x00000000u)
#define CSL_PCI_PCISLVCNTL_CFG_DONE_MASK (0x00000001u)
#define CSL_PCI_PCISLVCNTL_CFG_DONE_SHIFT (0x00000000u)
#define CSL_PCI_PCISLVCNTL_CFG_DONE_RESETVAL (0x00000000u)
#define CSL_PCI_PCISLVCNTL_RESETVAL (0x003F0000u)
/* PCIBAR0TRL */
#define CSL_PCI_PCIBAR0TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR0TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR0TRL_TRANS_ADDR_RESETVAL (0x00080000u)
#define CSL_PCI_PCIBAR0TRL_RESETVAL (0x00800000u)
/* PCIBAR1TRL */
#define CSL_PCI_PCIBAR1TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR1TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR1TRL_TRANS_ADDR_RESETVAL (0x00180000u)
#define CSL_PCI_PCIBAR1TRL_RESETVAL (0x01800000u)
/* PCIBAR2TRL */
#define CSL_PCI_PCIBAR2TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR2TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR2TRL_TRANS_ADDR_RESETVAL (0x00280000u)
#define CSL_PCI_PCIBAR2TRL_RESETVAL (0x02800000u)
/* PCIBAR3TRL */
#define CSL_PCI_PCIBAR3TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR3TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR3TRL_TRANS_ADDR_RESETVAL (0x08000000u)
#define CSL_PCI_PCIBAR3TRL_RESETVAL (0x80000000u)
/* PCIBAR4TRL */
#define CSL_PCI_PCIBAR4TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR4TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR4TRL_TRANS_ADDR_RESETVAL (0x0A000000u)
#define CSL_PCI_PCIBAR4TRL_RESETVAL (0xA0000000u)
/* PCIBAR5TRL */
#define CSL_PCI_PCIBAR5TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR5TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR5TRL_TRANS_ADDR_RESETVAL (0x0E000000u)
#define CSL_PCI_PCIBAR5TRL_RESETVAL (0xE0000000u)
/* PCIBARMIR */
#define CSL_PCI_PCIBARMIR_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBARMIR_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBARMIR_ADDR_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBARMIR_PREFETCH_MASK (0x00000008u)
#define CSL_PCI_PCIBARMIR_PREFETCH_SHIFT (0x00000003u)
#define CSL_PCI_PCIBARMIR_PREFETCH_RESETVAL (0x00000001u)
#define CSL_PCI_PCIBARMIR_TYPE_MASK (0x00000006u)
#define CSL_PCI_PCIBARMIR_TYPE_SHIFT (0x00000001u)
#define CSL_PCI_PCIBARMIR_TYPE_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBARMIR_IOMEM_SP_IND_MASK (0x00000001u)
#define CSL_PCI_PCIBARMIR_IOMEM_SP_IND_SHIFT (0x00000000u)
#define CSL_PCI_PCIBARMIR_IOMEM_SP_IND_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBARMIR_RESETVAL (0x00000008u)
/* PCIMCFGDAT */
#define CSL_PCI_PCIMCFGDAT_DATA_MASK (0xFFFFFFFFu)
#define CSL_PCI_PCIMCFGDAT_DATA_SHIFT (0x00000000u)
#define CSL_PCI_PCIMCFGDAT_DATA_RESETVAL (0x00000000u)
#define CSL_PCI_PCIMCFGDAT_RESETVAL (0x00000000u)
/* PCIMCFGADR */
#define CSL_PCI_PCIMCFGADR_ADDR_MASK (0xFFFFFFFFu)
#define CSL_PCI_PCIMCFGADR_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIMCFGADR_ADDR_RESETVAL (0x00000000u)
#define CSL_PCI_PCIMCFGADR_RESETVAL (0x00000000u)
/* PCIMCFGCMD */
#define CSL_PCI_PCIMCFGCMD_READY_MASK (0x80000000u)
#define CSL_PCI_PCIMCFGCMD_READY_SHIFT (0x0000001Fu)
#define CSL_PCI_PCIMCFGCMD_READY_RESETVAL (0x00000001u)
#define CSL_PCI_PCIMCFGCMD_BYTE_EN_MASK (0x000000F0u)
#define CSL_PCI_PCIMCFGCMD_BYTE_EN_SHIFT (0x00000004u)
#define CSL_PCI_PCIMCFGCMD_BYTE_EN_RESETVAL (0x00000000u)
#define CSL_PCI_PCIMCFGCMD_TYPE_MASK (0x00000004u)
#define CSL_PCI_PCIMCFGCMD_TYPE_SHIFT (0x00000002u)
#define CSL_PCI_PCIMCFGCMD_TYPE_RESETVAL (0x00000000u)
/*----TYPE Tokens----*/
#define CSL_PCI_PCIMCFGCMD_TYPE_CONFIG_SPACE (0x00000000u)
#define CSL_PCI_PCIMCFGCMD_TYPE_IO_SPACE (0x00000001u)
#define CSL_PCI_PCIMCFGCMD_RD_WR_MASK (0x00000001u)
#define CSL_PCI_PCIMCFGCMD_RD_WR_SHIFT (0x00000000u)
#define CSL_PCI_PCIMCFGCMD_RD_WR_RESETVAL (0x00000000u)
/*----RD_WR Tokens----*/
#define CSL_PCI_PCIMCFGCMD_RD_WR_WRITE (0x00000000u)
#define CSL_PCI_PCIMCFGCMD_RD_WR_READ (0x00000001u)
#define CSL_PCI_PCIMCFGCMD_RESETVAL (0x80000000u)
/* PCIMSTCFG */
#define CSL_PCI_PCIMSTCFG_CFG_FLUSH_IF_NOT_ENABLED_MASK (0x00000400u)
#define CSL_PCI_PCIMSTCFG_CFG_FLUSH_IF_NOT_ENABLED_SHIFT (0x0000000Au)
#define CSL_PCI_PCIMSTCFG_CFG_FLUSH_IF_NOT_ENABLED_RESETVAL (0x00000000u)
#define CSL_PCI_PCIMSTCFG_IO_FLUSH_IF_NOT_ENABLED_MASK (0x00000200u)
#define CSL_PCI_PCIMSTCFG_IO_FLUSH_IF_NOT_ENABLED_SHIFT (0x00000009u)
#define CSL_PCI_PCIMSTCFG_IO_FLUSH_IF_NOT_ENABLED_RESETVAL (0x00000000u)
#define CSL_PCI_PCIMSTCFG_MEM_FLUSH_IF_NOT_ENABLED_MASK (0x00000100u)
#define CSL_PCI_PCIMSTCFG_MEM_FLUSH_IF_NOT_ENABLED_SHIFT (0x00000008u)
#define CSL_PCI_PCIMSTCFG_MEM_FLUSH_IF_NOT_ENABLED_RESETVAL (0x00000000u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_MULT_EN_MASK (0x00000004u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_MULT_EN_SHIFT (0x00000002u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_MULT_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_LINE_EN_MASK (0x00000002u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_LINE_EN_SHIFT (0x00000001u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_LINE_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_WRINV_EN_MASK (0x00000001u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_WRINV_EN_SHIFT (0x00000000u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_WRINV_EN_RESETVAL (0x00000001u)
#define CSL_PCI_PCIMSTCFG_RESETVAL (0x00000007u)
/* PCIADDSUB */
#define CSL_PCI_PCIADDSUB_ADD_SUBS_MASK (0xFF800000u)
#define CSL_PCI_PCIADDSUB_ADD_SUBS_SHIFT (0x00000017u)
#define CSL_PCI_PCIADDSUB_ADD_SUBS_RESETVAL (0x00000000u)
#define CSL_PCI_PCIADDSUB_RESETVAL (0x00000000u)
/* PCIVENDEVPRG */
#define CSL_PCI_PCIVENDEVPRG_VENDOR_DEVICE_ID_PROG_MASK (0xFFFFFFFFu)
#define CSL_PCI_PCIVENDEVPRG_VENDOR_DEVICE_ID_PROG_SHIFT (0x00000000u)
#define CSL_PCI_PCIVENDEVPRG_VENDOR_DEVICE_ID_PROG_RESETVAL (0xB000104Cu)
#define CSL_PCI_PCIVENDEVPRG_RESETVAL (0xB000104Cu)
/* PCICMDSTATPRG */
#define CSL_PCI_PCICMDSTATPRG_66MHZ_CAP_MASK (0x00000002u)
#define CSL_PCI_PCICMDSTATPRG_66MHZ_CAP_SHIFT (0x00000001u)
#define CSL_PCI_PCICMDSTATPRG_66MHZ_CAP_RESETVAL (0x00000000u)
#define CSL_PCI_PCICMDSTATPRG_CAP_LIST_MASK (0x00000001u)
#define CSL_PCI_PCICMDSTATPRG_CAP_LIST_SHIFT (0x00000000u)
#define CSL_PCI_PCICMDSTATPRG_CAP_LIST_RESETVAL (0x00000000u)
#define CSL_PCI_PCICMDSTATPRG_RESETVAL (0x00000000u)
/* PCICLREVPRG */
#define CSL_PCI_PCICLREVPRG_CLASS_CODE_REV_ID_PROG_MASK (0xFFFFFFFFu)
#define CSL_PCI_PCICLREVPRG_CLASS_CODE_REV_ID_PROG_SHIFT (0x00000000u)
#define CSL_PCI_PCICLREVPRG_CLASS_CODE_REV_ID_PROG_RESETVAL (0x00000001u)
#define CSL_PCI_PCICLREVPRG_RESETVAL (0x00000001u)
/* PCISUBIDPRG */
#define CSL_PCI_PCISUBIDPRG_SUBSYS_VENDOR_ID_SUBSYS_ID_PROG_MASK (0xFFFFFFFFu)
#define CSL_PCI_PCISUBIDPRG_SUBSYS_VENDOR_ID_SUBSYS_ID_PROG_SHIFT (0x00000000u)
#define CSL_PCI_PCISUBIDPRG_SUBSYS_VENDOR_ID_SUBSYS_ID_PROG_RESETVAL (0x00000000u)
#define CSL_PCI_PCISUBIDPRG_RESETVAL (0x00000000u)
/* PCIMAXLGPRG */
#define CSL_PCI_PCIMAXLGPRG_MAX_LAT_MIN_GRANT_PROG_MASK (0x0000FFFFu)
#define CSL_PCI_PCIMAXLGPRG_MAX_LAT_MIN_GRANT_PROG_SHIFT (0x00000000u)
#define CSL_PCI_PCIMAXLGPRG_MAX_LAT_MIN_GRANT_PROG_RESETVAL (0x00000000u)
#define CSL_PCI_PCIMAXLGPRG_RESETVAL (0x00000000u)
/* PCILRSTREG */
#define CSL_PCI_PCILRSTREG_LRESET_MASK (0x00000001u)
#define CSL_PCI_PCILRSTREG_LRESET_SHIFT (0x00000000u)
#define CSL_PCI_PCILRSTREG_LRESET_RESETVAL (0x00000000u)
#define CSL_PCI_PCILRSTREG_RESETVAL (0x00000000u)
/* PCICFGDONE */
#define CSL_PCI_PCICFGDONE_CONFIG_DONE_MASK (0x00000001u)
#define CSL_PCI_PCICFGDONE_CONFIG_DONE_SHIFT (0x00000000u)
#define CSL_PCI_PCICFGDONE_CONFIG_DONE_RESETVAL (0x00000000u)
#define CSL_PCI_PCICFGDONE_RESETVAL (0x00000000u)
/* PCIBAR0MPRG */
#define CSL_PCI_PCIBAR0MPRG_MASK_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR0MPRG_MASK_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR0MPRG_MASK_RESETVAL (0x0FFC0000u)
#define CSL_PCI_PCIBAR0MPRG_RESETVAL (0x0FFC0000u)
/* PCIBAR1MPRG */
#define CSL_PCI_PCIBAR1MPRG_MASK_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR1MPRG_MASK_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR1MPRG_MASK_RESETVAL (0x0FF80000u)
#define CSL_PCI_PCIBAR1MPRG_RESETVAL (0x0FF80000u)
/* PCIBAR2MPRG */
#define CSL_PCI_PCIBAR2MPRG_MASK_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR2MPRG_MASK_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR2MPRG_MASK_RESETVAL (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR2MPRG_RESETVAL (0x0FFFFFFFu)
/* PCIBAR3MPRG */
#define CSL_PCI_PCIBAR3MPRG_MASK_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR3MPRG_MASK_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR3MPRG_MASK_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBAR3MPRG_RESETVAL (0x00000000u)
/* PCIBAR4MPRG */
#define CSL_PCI_PCIBAR4MPRG_MASK_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR4MPRG_MASK_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR4MPRG_MASK_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBAR4MPRG_RESETVAL (0x00000000u)
/* PCIBAR5MPRG */
#define CSL_PCI_PCIBAR5MPRG_MASK_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR5MPRG_MASK_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR5MPRG_MASK_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBAR5MPRG_RESETVAL (0x00000000u)
/* PCIBAR0PRG */
#define CSL_PCI_PCIBAR0PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR0PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR0PRG_PREFETCH_RESETVAL (0x00000001u)
#define CSL_PCI_PCIBAR0PRG_RESETVAL (0x00000001u)
/* PCIBAR1PRG */
#define CSL_PCI_PCIBAR1PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR1PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR1PRG_PREFETCH_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBAR1PRG_RESETVAL (0x00000000u)
/* PCIBAR2PRG */
#define CSL_PCI_PCIBAR2PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR2PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR2PRG_PREFETCH_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBAR2PRG_RESETVAL (0x00000000u)
/* PCIBAR3PRG */
#define CSL_PCI_PCIBAR3PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR3PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR3PRG_PREFETCH_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBAR3PRG_RESETVAL (0x00000000u)
/* PCIBAR4PRG */
#define CSL_PCI_PCIBAR4PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR4PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR4PRG_PREFETCH_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBAR4PRG_RESETVAL (0x00000000u)
/* PCIBAR5PRG */
#define CSL_PCI_PCIBAR5PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR5PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR5PRG_PREFETCH_RESETVAL (0x00000000u)
#define CSL_PCI_PCIBAR5PRG_RESETVAL (0x00000000u)
/* PCIBAR0TRLPRG */
#define CSL_PCI_PCIBAR0TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR0TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR0TRLPRG_TRANS_ADDR_RESETVAL (0x00080000u)
#define CSL_PCI_PCIBAR0TRLPRG_RESETVAL (0x00080000u)
/* PCIBAR1TRLPRG */
#define CSL_PCI_PCIBAR1TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR1TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR1TRLPRG_TRANS_ADDR_RESETVAL (0x00180000u)
#define CSL_PCI_PCIBAR1TRLPRG_RESETVAL (0x00180000u)
/* PCIBAR2TRLPRG */
#define CSL_PCI_PCIBAR2TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR2TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR2TRLPRG_TRANS_ADDR_RESETVAL (0x00280000u)
#define CSL_PCI_PCIBAR2TRLPRG_RESETVAL (0x00280000u)
/* PCIBAR3TRLPRG */
#define CSL_PCI_PCIBAR3TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR3TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR3TRLPRG_TRANS_ADDR_RESETVAL (0x08000000u)
#define CSL_PCI_PCIBAR3TRLPRG_RESETVAL (0x08000000u)
/* PCIBAR4TRLPRG */
#define CSL_PCI_PCIBAR4TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR4TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR4TRLPRG_TRANS_ADDR_RESETVAL (0x0A000000u)
#define CSL_PCI_PCIBAR4TRLPRG_RESETVAL (0x0A000000u)
/* PCIBAR5TRLPRG */
#define CSL_PCI_PCIBAR5TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR5TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR5TRLPRG_TRANS_ADDR_RESETVAL (0x0E000000u)
#define CSL_PCI_PCIBAR5TRLPRG_RESETVAL (0x0E000000u)
/* PCIBASENPRG */
#define CSL_PCI_PCIBASENPRG_BASE_EN_MASK (0x0000003Fu)
#define CSL_PCI_PCIBASENPRG_BASE_EN_SHIFT (0x00000000u)
#define CSL_PCI_PCIBASENPRG_BASE_EN_RESETVAL (0x0000003Fu)
#define CSL_PCI_PCIBASENPRG_RESETVAL (0x0000003Fu)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/edma/edma_ping_pong_xfer_reg5/src/Edma_ping_pong_xfer_reg5.c | <filename>DSP/TI-Header/csl_c6455/example/edma/edma_ping_pong_xfer_reg5/src/Edma_ping_pong_xfer_reg5.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
*
* @file Edma_ping_pong_xfer_reg5.c
*
* @path $(CSLPATH)\example\edma\edma_ping_pong_xfer_reg5\src
*
* @desc Example of EDMA
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This is an example of the CSL EDMA usage for the use edma Channel
* Initialization for ping pong buffer where channels are opened
* in the region 5.
* This example do the following operations
* - Initializes and Opens the edma module
* - Sets up the Module and gets the module setup values
* - Enables (Bits 0-15) the Shadow Region 0
* - Disables (Bits 12-15) the Shadow Region 0
* - Enables interrupt (Bits 0-11) for the Shadow Region 0
* - Disables interrupt (Bits 2-11) for the Shadow Region 0
* - Opens Channel 0 in context of Shadow region 0
* - Obtains a handles to parameters set 0, 1 and 2
* - Sets up the first param set (Ping buffer)
* - Sets up the Ping Entry which is loaded after the Pong entry
* gets exhausted
* - Enables Channel and Initialize the data
* - Manually triggers the Channel
* - Polls on interrupt bit 0 and clears interrupt bit 0
* - Maps Channel 0 to Event Queue 1
* - Manually triggers the Channel
* - Polls on interrupt pend bit 1 and clears interrupt bit 1
* - Compares the transfered data
* - Displays the result based on previous step
*
* ============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Edma_ping_pong_xfer_reg5.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* 16-Dec-2005 DS Minor documentation changes
* =============================================================================
*/
#include <stdio.h>
#include <csl_edma3.h>
#include <soc.h>
/* Globals */
Uint8 srcBuff1[512];
Uint8 srcBuff2[512];
Uint8 dstBuff1[512];
Uint8 dstBuff2[512];
Uint32 passStatus = 1;
/* Forward declaration */
void edma_ping_pong_xfer_region5 (void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main(void)
{
/* Invoke example */
edma_ping_pong_xfer_region5 ();
return;
}
/*
* =============================================================================
* @func edma_ping_pong_xfer_region5
*
* @arg
* NONE
*
* @desc
* This is the example routine which perform edma ping pong buffer transfer
* where channel is open in region 5.
* It implements following steps
* 1. Initializes and Opens the edma module
* 2. Sets up the Module and gets the module setup values
* 3. Enables (Bits 0-15) the Shadow Region 0
* 4. Disables (Bits 12-15) the Shadow Region 0
* 5. Enables interrupt (Bits 0-11) for the Shadow Region 0
* 6. Disables interrupt (Bits 2-11) for the Shadow Region 0
* 7. Opens Channel 0 in context of Shadow region 0
* 8. Obtains a handles to parameters set 0, 1 and 2
* 9. Sets up the first param set (Ping buffer)
* 10. Sets up the Ping Entry which is loaded after the Pong entry
* gets exhausted
* 11. Enables Channel and Initialize the data
* 12. Manually triggers the Channel
* 13. Polls on interrupt bit 0 and clears interrupt bit 0
* 14. Maps Channel 0 to Event Queue 1
* 15. Manually triggers the Channel
* 16. Polls on interrupt pend bit 1 and clears interrupt bit 1
* 17. Compares the transfered data
* 18. Close the Edma module and channel
*
* @return
* NONE
*
* =============================================================================
*/
void edma_ping_pong_xfer_region5 (void)
{
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing;
CSL_Edma3ParamHandle hParamPong;
CSL_Edma3ParamHandle hParamBasic;
CSL_Edma3ChannelObj chObj;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Status status;
CSL_Edma3HwDmaChannelSetup dmahwSetup;
volatile Uint32 loopIndex;
printf ("Running Edma Example\n");
/* Module Initialization */
status = CSL_edma3Init(&context);
if (status != CSL_SOK) {
printf ("Edma module initialization failed\n");
return;
}
/* Module level open */
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
if ( (hModule == NULL) || (status != CSL_SOK)) {
printf ("Edma module open failed\n");
return;
}
/* Module setup */
dmahwSetup.paramNum = 0;
dmahwSetup.que = CSL_EDMA3_QUE_0;
hwSetup.dmaChaSetup = &dmahwSetup;
hwSetup.qdmaChaSetup = NULL;
status = CSL_edma3HwSetup(hModule,&hwSetup);
if (status != CSL_SOK) {
printf ("Hardware setup failed\n");
CSL_edma3Close (hModule);
return;
}
/* DRAE enable(Bits 0-15) for the shadow region 5 */
regionAccess.region = CSL_EDMA3_REGION_5 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
if (status != CSL_SOK) {
printf ("Edma region enable command failed\n");
return;
}
/* DRAE disable(Bits 12-15) for the shadow region 5 */
regionAccess.region = CSL_EDMA3_REGION_5 ;
regionAccess.drae = 0xF000 ;
regionAccess.draeh = 0x0000 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_DISABLE, \
®ionAccess);
if (status != CSL_SOK) {
printf ("Edma region disable command failed\n");
return;
}
if (hModule->regs->DRA[CSL_EDMA3_REGION_5].DRAE != 0x0FFF)
passStatus = 0;
/* Interrupt enable (Bits 0-11) for the shadow region 5 */
regionIntr.region = CSL_EDMA3_REGION_5 ;
regionIntr.intr = 0x0FFF ;
regionIntr.intrh = 0x0000 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE, ®ionIntr);
if (status != CSL_SOK) {
printf ("Edma interrupts enable command failed\n");
return;
}
/* Interrupt disable (Bits 2-11) for the shadow region 5 */
regionIntr.region = CSL_EDMA3_REGION_5 ;
regionIntr.intr = 0x0FFC ;
regionIntr.intrh = 0x0000 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_DISABLE,®ionIntr);
if (status != CSL_SOK) {
printf ("Edma interrupts disable command failed\n");
return;
}
/* Check intr enable register bit */
if (hModule->regs->SHADOW[CSL_EDMA3_REGION_5].IER != 0x0003)
passStatus = 0;
/* Channel 0 open in context of shadow region 5 */
chAttr.regionNum = CSL_EDMA3_REGION_5;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status);
if ((hChannel == NULL) || (status != CSL_SOK)) {
printf ("Edma channel open failed\n");
return;
}
/* Obtain a handle to parameter set 0 */
hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status);
if (hParamBasic == NULL) {
printf ("Edma get param handle for param entry 0 failed\n");
return;
}
/* Obtain a handle to parameter set 2 */
hParamPing = CSL_edma3GetParamHandle(hChannel,2,&status);
if (hParamPing == NULL) {
printf ("Edma get param handle for param entry 2 failed\n");
return;
}
/* Obtain a handle to parameter set 1 */
hParamPong = CSL_edma3GetParamHandle(hChannel,1,&status);
if (hParamPong == NULL) {
printf ("Edma get param handle for param entry 1 failed\n");
return;
}
/* Setup the first param set (Ping buffer) */
myParamSetup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
0, CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR
);
myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(512,1);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParamPong,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1);
myParamSetup.cCnt = 1;
status = CSL_edma3ParamSetup(hParamBasic, &myParamSetup);
if (status != CSL_SOK) {
printf("Edma parameter entry setup is failed\n");
return;
}
/* Setup the Ping Entry which loaded after the Pong entry gets exhausted */
status = CSL_edma3ParamSetup(hParamPing,&myParamSetup);
if (status != CSL_SOK) {
printf("Edma ping parameter entry setup is failed\n");
return;
}
/* Setup the Pong Entry which loaded after the Ping entry gets exhausted */
myParamSetup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
1,CSL_EDMA3_TCC_NORMAL, \
CSL_EDMA3_FIFOWIDTH_NONE, \
TRUE,CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR
);
myParamSetup.srcAddr = (Uint32)srcBuff2;
myParamSetup.dstAddr = (Uint32)dstBuff2;
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParamPing,0);
status = CSL_edma3ParamSetup(hParamPong,&myParamSetup);
if (status != CSL_SOK) {
printf("Edma pong parameter entry setup is failed\n");
return;
}
/* Enable channel */
status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \
NULL);
if (status != CSL_SOK) {
printf("Edma channel enable command is failed\n");
return;
}
/* Initialize data */
for (loopIndex = 0; loopIndex < 512; loopIndex++) {
srcBuff1[loopIndex] = loopIndex;
srcBuff2[loopIndex] = loopIndex;
dstBuff1[loopIndex] = 0;
dstBuff2[loopIndex] = 0;
}
/* Manually trigger the channel */
status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
if (status != CSL_SOK) {
printf("Edma channel set command is failed\n");
return;
}
regionIntr.region = CSL_EDMA3_REGION_5;
regionIntr.intr = 0;
regionIntr.intrh = 0;
do {
/* Poll on interrupt bit 0 */
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
} while (!(regionIntr.intr & 0x1));
/* Clear interrupt bit 0 */
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \
®ionIntr);
if (status != CSL_SOK) {
printf("Edma clear interrupt bit 0 command is failed\n");
return;
}
/* Mapping channel 0 to event queue 1 */
status = CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_1);
if (status != CSL_SOK) {
printf("Edma channel setup queue is failed\n");
return;
}
/* Manually trigger the channel */
status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
if (status != CSL_SOK) {
printf("Edma channel set command is failed\n");
return;
}
regionIntr.region = CSL_EDMA3_REGION_5;
regionIntr.intr = 0;
regionIntr.intrh = 0;
/* Poll on interrupt pend bit 1 */
do {
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
} while (!(regionIntr.intr & 0x2));
/* Clear interrupt bit 1 */
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \
®ionIntr);
if (status != CSL_SOK) {
printf("Edma clear interrupt bit 1 command is failed\n");
return;
}
/* Check transfer */
if(Verify_Transfer(512, 1, 1, 0, 0, 0, 0, srcBuff1, dstBuff1,TRUE) == FALSE)
passStatus = 0;
if(Verify_Transfer(512, 1, 1, 0, 0, 0, 0, srcBuff2, dstBuff2,TRUE) == FALSE)
passStatus = 0;
if (passStatus == 1)
printf ("<<EXAMPLE PASSED>>: Edma Ping Pong Buffer Transfer Passed\n");
else {
printf ("<<EXAMPLE FAILED>>: Edma Ping Pong Buffer Transfer Failed\n");
return;
}
/* Close channel */
status = CSL_edma3ChannelClose(hChannel);
if (status != CSL_SOK) {
printf("Edma channel close failed\n");
return;
}
/* Close edma module */
status = CSL_edma3Close(hModule);
if (status != CSL_SOK) {
printf("Edma module close failed\n");
return;
}
printf ("=============================================================\n");
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/tcp2/tcp2_shared_mode/src/tcp2_extrinsic.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004 , 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file tcp2_extrinsics.c
*
* @path $(CSLPATH)\example\c6455\tcp2\tcp2_shared_mode\src
*
* @desc extrinsic reference data for the TCP2 shared mode
*
*/
#include <tistdtypes.h>
Uint32 extrinsicData [] = {
0x6a7c110d,0x077c195a,
0x7a7e7f7b,0x79100705,
0x097e0009,0x07007d7f,
0x0601037b,0x10777407,
0x7c047b78,0x00000100,
0x7f057f09,0x72027303,
0x03077b00,0x02780877,
0x06790103,0x03077e7c,
0x09797a00,0x75070400,
0x7e04730b,0x04080177,
0x7505077e,0x7f077c7f,
0x7e010001,0x05780c04,
0x79747a0c,0x75057d05,
0x0a7a750a,0x017a0c0a,
0x11021b04,0x0c716d76,
0x18272063,0x0d1d1e73,
0x720d136d,0x73186121,
0x16116c72,0x6d6b1a69,
0x000f6d0f,0x776e0873,
0x7f7d7c7d,0x790b0c75,
0x027e0405,0x780b7c7e,
0x757c7e01,0x00047b7f,
0x75017971,0x097c7603,
0x0c070d77,0x7b087905,
0x060c0600,0x0576010e,
0x040c0506,0x04090907,
0x7f030500,0x7e027c03,
0x7412030a,0x00750104,
0x097d0601,0x797e7e02,
0x007b7f7b,0x03027b7f,
0x7d790306,0x7b7a0302,
0x06080401,0x0302077e,
0x7a0b037d,0x02040702,
0x07007c01,0x7e7f0305,
0x740f0f17,0x0c780276,
0x010f7d0f,0x7e7e087a,
0x72090000,0x07760573,
0x7e7c7d04,0x000a7b74,
0x0a770879,0x7a737778,
0x75747579,0x79687173,
0x7b0c0f0f,0x10020576,
0x07057973,0x7a7d7f70,
0x78777f14,0x7404710b,
0x7c7b7e0c,0x7f787f73,
0x7f79077f,0x027d0006,
0x7c0a7f04,0x047a7d04,
0x68776c1a,0x0e0f7271,
0x6a116b6e,0x1b16676a,
0x0a0f1010,0x720a1266,
0x72757478,0x6c7c7778,
0x7b7b787e,0x077b7777,
0x0e787e7e,0x7b06027e,
0x100d7a01,0x0a71087f,
0x1a226a6f,0x12677704,
0x580e141e,0x5e627061,
0x1c5f6660,0x5f1d1f65,
0x1c686b60,0x2a19171c,
0x0010770e,0x68121e6e,
0x7d7d047f,0x7f797e7c,
0x0a7b7b09,0x7c7a7503,
0x0a770108,0x05007601,
0x03037b74,0x7f040a08,
0x00787b0a,0x06730b03,
0x07146c0e,0x010e0874,
0x740a6d1a,0x140e7479,
0x78097e79,0x07700c08,
0x79067503,0x7a040703,
0x74017d02,0x03010407,
0x757d7d70,0x0001007e,
0x7e7a7c04,0x040a7e7f,
0x0a0d7178,0x00017006,
0x77010f11,0x13196a6e,
0x7902047b,0x78010203,
0x037e0000,0x797d017e,
0x0a7e7d7e,0x78030003,
0x7b060004,0x7f7f7800,
0x710d7479,0x07080b7f,
0x700f1011,0x78790c13,
0x74150c07,0x0612710b,
0x73146d06,0x7b0b710b,
0x0b0b087d,0x146b6f6e,
0x5d171312,0x72086970,
0x10686f5b,0x0d742021,
0x73071700,0x7903020c,
0x10781103,0x7b0a797c,
0x0a7e110d,0x0a037166,
0x060a7800,0x04060c0d,
0x117d7a09,0x067e077c,
0x7c07000a,0x7d03767a,
0x000d0604,0x7a040079,
0x00010d0e,0x0d020c7c,
0x7e777f00,0x09707402,
0x7e07007c,0x0a7f7978,
0x03090d79,0x0a030501,
0x0079047e,0x047c7903,
0x12020400,0x7e6c010a,
0x73167116,0x0f066b7d,
0x6771140c,0x13720813,
0x66685a28,0x69622014,
0x6b0e0572,0x12241e5b,
0x74777e7f,0x017f107c,
0x0007077a,0x09030b77,
0x0e077803,0x7d7e050b,
0x7a080b09,0x77117f01,
0x1d656367,0x78061702,
0x6c6a646f,0x6f69150c,
0x0e787b7f,0x7d08777d,
0x0e0a0679,0x767a6d0b,
0x7872767b,0x087a7d0a,
0x747e027f,0x7d007677,
0x0e790274,0x7c6e117b,
0x0b0c6b0b,0x07040005,
0x720c737e,0x76777206,
0x07737901,0x750e7079,
0x0f71731a,0x106f6914,
0x7b0a7e7f,0x030c1905,
0x787e7a7d,0x7d7f7b01,
0x0e797b04,0x79057a07,
0x14107110,0x7f06710e,
0x6d0c1a7c,0x6b147573,
0x6e191716,0x0d7c0d79,
0x156e7363,0x1c1e1d69,
0x14107513,0x040a0d08,
0x0d096c6e,0x746c0772,
0x027b0600,0x71071074,
0x730b0407,0x761a6f05,
0x7f010901,0x0502027d,
0x6e03000a,0x09000b08,
0x0904740e,0x03767c7c,
0x12776b0f,0x116c766d,
0x7e07037f,0x7a71740c,
0x08027c0e,0x02080706,
0x017b017c,0x6c040303,
0x030a0201,0x7a7a0309,
0x7b16100e,0x79087208,
0x18716c1e,0x12100e6d,
0x0a0d060b,0x680f7973,
0x7771770f,0x7f7d7c7f,
0x70030804,0x7b7a0609,
0x170f2064,0x08120b08,
0x11710d0c,0x70766a1b,
0x737b7c7f,0x7e060775,
0x7c7c7c0d,0x7c7d7f02,
0x7b060500,0x750b7b7e,
0x79007a04,0x7d037f7f,
0x767f0401,0x0e167a7b,
0x040a040b,0x70770706,
0x6f700e0b,0x0e6e0772,
0x77780f13,0x14116e72,
0x0f01027e,0x0802067f,
0x14100f73,0x6514740f,
0x7a027d11,0x176d6f6b,
0x0307047d,0x7e017c07,
0x057b087e,0x7c717d75,
0x017d7907,0x7c020105,
0x0d7d0703,0x7a7d787d,
0x790b7d7b,0x0106067f,
0x02047a7a,0x08007d7f,
0x7a76087b,0x02000001,
0x611e6c11,0x787c740b,
0x74750575,0x0d0e7014,
0x02017d75,0x7979096a,
0x0e6d676e,0x7c0e007d,
0x7c0d6772,0x11761c17,
0x7409090c,0x0c780267,
0x13726d10,0x0e740871,
0x70070a7b,0x0a157873,
0x6f136513,0x68697970,
0x79690377,0x03751374,
0x7d74087e,0x72080c0c,
0x7d097b12,0x0c097f02,
0x72750975,0x0e79737b,
0x66696e6b,0x1170710e,
0x09020117,0x1d67201c,
0x077a760a,0x0402780b,
0x0805757e,0x7e107e77,
0x6f777908,0x120e7e75,
0x0b00770c,0x02740671,
0x0c05797c,0x7b067d03,
0x097e057f,0x7c030707,
0x037d7f01,0x02067f01,
0x097a0278,0x087c0078,
0x097b037c,0x74017e7f,
0x060e6f05,0x7b7c7d7d,
0x6b6a7111,0x12706901,
0x79751013,0x0b6d641c,
0x7d78757e,0x050e0105,
0x7c7b0500,0x02050479,
0x767f0c7f,0x01017b01,
0x767a737c,0x74790774,
0x0b6f7207,0x7a7a0c0e,
0x1a6f6b11,0x0b026272,
0x7577096d,0x15081011,
0x1c5f6865,0x2160607f,
0x0a13720b,0x19746a76,
0x63711266,0x160f1117,
0x63621573,0x601d6c6a,
0x151f1b11,0x676a1b18,
0x76136267,0x6c101d73,
0x790d1103,0x140d6775,
0x797c770d,0x73700c08,
0x6c777270,0x72720310,
0x7a7d077d,0x79777e0e,
0x7e040176,0x7c7a777b,
0x087a0278,0x01797e7d,
0x7605087d,0x097f7a0f,
0x13740501,0x0076707a,
0x787b7579,0x10787602,
0x7506007f,0x037c0000,
0x7c027207,0x020a037f,
0x7e7e7b01,0x01030e72,
0x7d05017e,0x7e7c0302,
0x7f7b7a7c,0x0100067f,
0x01017d09,0x01777b74,
0x7779117d,0x7e037701,
0x14097273,0x06760a76,
0x71140377,0x72140e70,
0x00017809,0x007f7901,
0x017a7d7d,0x02090402,
0x01777a04,0x727f0307,
0x7b780507,0x0778017c,
0x07087600,0x0a007c75,
0x77107273,0x7b77037e,
0x05780b77,0x0c72037f,
0x057a0a7a,0x0872047f,
0x03067a0e,0x03747878,
0x09080100,0x76797673,
0x79067878,0x090c7f04,
0x7d780479,0x0b766a03,
0x74707710,0x6679760c,
0x15161d70,0x126e136e,
0x77760b0c,0x75126c6e,
0x047d7e0b,0x7a077c7a,
0x02010101,0x027e077c,
0x7f7e7e7c,0x03037d7b,
0x07750278,0x01750304,
0x0c030006,0x7c7e7f7a,
0x7e04047b,0x7c090e04,
0x740f210e,0x000d7709,
0x17182211,0x216b246e,
0x120f1868,0x18611b16,
0x05087f76,0x140f090b,
0x00767e7b,0x0a7f7376,
0x78170705,0x08030674,
0x76100071,0x01797c14,
0x7a71107d,0x07720b10,
0x027a6e00,0x02027b04,
0x017a0f03,0x7d7f7702,
0x0a090005,0x7f0b027d,
0x05750b01,0x00057b02,
0x0002067f,0x7f79017f,
0x0b657002,0x7e7a097f,
0x6d6e1917,0x67171b7e,
0x0f027574,0x10741610,
0x10740c78,0x746f766e,
0x7e007774,0x08777c73,
0x08007b02,0x06767877,
0x09007901,0x037f7d75,
0x02797c7c,0x01037f02,
0x73050912,0x0b790505,
0x59602161,0x1a0a750a,
0x695a6614,0x1e206060,
0x10121014,0x636b6e62,
0x0701057b,0x0f760f72,
0x7a060b7c,0x7605047b,
0x7d087a01,0x0e7a000d,
0x06020b05,0x0c0c790b,
0x007c7c03,0x05040a08,
0x0e6e0206,0x0e7a0301,
0x097f0007,0x6f6e7e07,
0x7b7a0502,0x6f7e0e02,
0x0208787c,0x05790878,
0x04120202,0x04037e03,
0x797f0100,0x7f077e6f,
0x02787d01,0x7a7d7c02,
0x70020972,0x0602047d,
0x780c7479,0x020c0f70,
0x7d0b0c7e,0x120d0801,
0x0c7d737e,0x08797d7f,
0x7f070878,0x0b7c760c,
0x15717412,0x70700809,
0x7f6f116b,0x71741569,
0x697a7707,0x02007407,
0x7a017200,0x74057a7f,
0x01777e01,0x7b03057d,
0x01010010,0x7d7b0201,
0x7c060a06,0x74020307,
0x717c756f,0x037b7e07,
0x1207797c,0x07087c0a,
0x7805037c,0x7c050e7d,
0x097b0072,0x7b047877,
0x73747272,0x77770109,
0x7c78097b,0x726a7a10,
0x100d7006,0x6c017609,
0x0d0f7568,0x707e0a75,
0x656f6614,0x6b0e757e,
0x6c636a12,0x1766735c,
0x746c111f,0x0f136f66,
0x0300097a,0x7d020c07,
0x71010901,0x7d010b7b,
0x76010b75,0x00050305,
0x7a72120e,0x71707475,
0x12106865,0x16661470,
0x731c7671,0x69687270,
0x67776c6d,0x1016786f,
0x7a14080f,0x0d126c08,
0x09020204,0x73010575,
0x077f7b00,0x01027b7e,
0x5f6f750b,0x0d03007e,
0x171c1513,0x6b1d736d,
0x0a730f6f,0x710f1467,
0x7904027d,0x00047b7d,
0x77080c7c,0x7f7b7808,
0x0300017e,0x0401060d,
0x7f09107c,0x0204057e,
0x78000805,0x787b0707,
0x05070309,0x7f7d7b7e,
0x730c7903,0x07780579,
0x0c797579,0x05730600,
0x16060d75,0x037c0b73,
0x6f6c666d,0x15120b72,
0x756f0c07,0x04051b17,
0x7b7a086b,0x0e050302,
0x65077b06,0x74797e7c,
0x1208740f,0x77057e79,
0x0002006f,0x0106770b,
0x78027c7e,0x08027205,
0x7b7c750a,0x75777c7f,
0x0614146d,0x70716704,
0x1072067b,0x040b6f0e,
0x7c057301,0x06737c7b,
0x00087f08,0x7d080378,
0x7d7b7e00,0x75750076,
0x7f03080b,0x7f7a7d7e,
0x7d7c037c,0x7c087e78,
0x0d040578,0x76737705,
0x7071676d,0x0a6d1a77,
0x01040a06,0x02007500,
0x0401017b,0x01040474,
0x0403017e,0x01786e02,
0x00747377,0x0b017805,
0x7a000109,0x0300787d,
0x0a7b7c04,0x027b0175,
0x0e7f7507,0x7d7b7d0c,
0x7b7d7709,0x7c07780c,
0x7a7a0202,0x067a060a,
0x7e067f7e,0x09060001,
0x7e07097b,0x0a070604,
0x050f0975,0x08070102,
0x01071709,0x7d707378,
0x7c777609,0x07077d07,
0x767d0609,0x7e0a027d,
0x05730505,0x06750402,
0x0e077510,0x6e047b0a,
0x6c147170,0x6b0e6c10,
0x0d7d0404,0x0a100272,
0x7f7c7905,0x7d077f7b,
0x6d7a0102,0x0878087d,
0x70077d79,0x02080203,
0x0f1a156f,0x7f737e0a,
0x0f0b700d,0x1971151a,
0x1572076f,0x740c1073,
0x747d756f,0x166e0b6e,
0x626f786f,0x140f7572,
0x660f1760,0x63730f14,
0x05056e14,0x037a6d1f,
0x77070e05,0x127d7776,
0x07760d77,0x7e750806,
0x0c0e7778,0x017e7c0a,
0x7e780a75,0x700c670a,
0x00037506,0x09017f05,
0x057d7f05,0x7c047a00,
0x750d7612,0x7b750b08,
0x0b08110d,0x0c777270,
0x077f7b0e,0x017f0700,
0x777c7c0e,0x7a05780b,
0x10727a7a,0x757a737a,
0x7f737b7a,0x7e110b12,
0x7d0b037f,0x79040b06,
0x0c7d0605,0x00000072,
0x04040706,0x71077b7e,
0x7c080304,0x7f057d0c,
0x77760402,0x0e7e0105,
0x76097b12,0x1176790d,
0x7873107c,0x07787e00,
0x7b7c7271,0x7c08760d,
0x177c777a,0x7c02120c,
0x7b7b7a7a,0x777a0b79,
0x777d7b08,0x787f007e,
0x04070204,0x04037e75,
0x790b0f0a,0x03070702,
0x166e1711,0x706c0506,
0x7a777c79,0x72140a73,
0x73700a7c,0x7a0e7405,
0x7b050308,0x08010800,
0x087e7474,0x047d0878,
0x090e7d72,0x7d75010a,
0x706e7578,0x0c6f110e,
0x177d6d68,0x0f740476,
0x63626359,0x5b69205a,
0x057f6d76,0x0b0b7412,
0x79721404,0x787c7c0d,
0x746d1211,0x6a6d6f05,
0x6f77750c,0x120f0c0e,
0x0000760b,0x7a6f746b,
0x14136c16,0x74757b00,
0x786c6e1b,0x186c1e18,
0x016e0c01,0x04106c0f,
0x0d040a0b,0x767e0c0a,
0x7c7f0401,0x0b077c7f,
0x07017f01,0x097d0205,
0x000e7806,0x04047e03,
0x027c0001,0x03770105,
0x0a04037e,0x057c0601,
0x7a067e02,0x7c037d7f,
0x7e040079,0x007c7f00,
0x050c7f03,0x76747e7a,
0x0f13156f,0x6d107302,
0x776f6663,0x2562616e,
0x7e77050e,0x7c7c0b05,
0x04767d09,0x027b7b78,
0x03080264,0x02090905,
0x0e720a78,0x6f0a127d,
0x70166f6d,0x0c15670a,
0x0109097d,0x05001569,
0x7b030279,0x7f050306,
0x7d00017a,0x05037b00,
0x04027975,0x7a7d0304,
0x7e037a09,0x7b760a05,
0x010b0005,0x7f027d77,
0x03760702,0x7f7b777e,
0x017a7c7f,0x017b7f79,
0x7e777c7e,0x01030402,
0x7b097a08,0x037d7c79,
0x790d7300,0x7d077b00,
0x7b027f76,0x060c7d7e,
0x796b086f,0x01767201,
0x10090604,0x79700a0c,
0x6d6e0f74,0x146d7206,
0x776f7f76,0x136e140e,
0x77067f02,0x017d0606,
0x027b0603,0x79057c0b,
0x05017e05,0x7e007d7f,
0x00027373,0x7a040079,
0x790d7f06,0x027d7f03,
0x7b7a7b7d,0x7c050407,
0x07777d02,0x7b6b7f7d,
0x116d1f11,0x050a0d00,
0x1719050e,0x1015136c,
0x037c020b,0x017a7611,
0x09027b73,0x0800047e,
0x7b760a01,0x7a7d7a05,
0x7b7c7c7b,0x7b03017d,
0x017b0a02,0x78057e00,
0x7a7a0073,0x7d7e7c7c,
0x74047b0b,0x0007037b,
0x080f7509,0x7f78780a,
0x7e747d00,0x0779027a,
0x7975797d,0x01007605,
0x0e097503,0x74100a15,
0x7b0b0801,0x050e1309,
0x7e0b027f,0x7c7f7b75,
0x7e7d0201,0x78777b05,
0x780c077b,0x0308007d,
0x090c057d,0x727d7905,
0x0c020a03,0x0d020e0d,
0x7f747d02,0x0101037b,
0x78010308,0x7f060900,
0x00777d02,0x057e1106,
0x00080504,0x7d027c00,
0x7d090505,0x05047e09,
0x777d017d,0x017e017a,
0x7c017f01,0x767a7e7d,
0x067e7a77,0x01007605,
0x7b707a70,0x0773757b,
0x7e6e6d08,0x6e70687d,
0x7f060104,0x0c0f737d,
0x08720279,0x06000876,
0x7a710d75,0x6d7b0301,
0x0c037308,0x7106066e,
0x0404790a,0x047c077f,
0x780a7f7e,0x05060902,
0x756e797c,0x0b017676,
0x71790b68,0x720b7f16,
0x0c711a13,0x0d771112,
0x0b770a77,0x7a1f6f07,
0x7f7c027b,0x7e7e7e7f,
0x0005067c,0x7c7b7873,
0x79060101,0x0b7b097c,
0x0107117d,0x7d127e04,
0x790e057d,0x77060c72,
0x7203777f,0x78030179,
0x05116d6a,0x17196a18,
0x060b0e00,0x7e72006a,
0x107c7c7e,0x727b0672,
0x08797701,0x7a70057f,
0x027c0102,0x7b000b7e,
0x7a777b02,0x047f7a06,
0x07080f01,0x08060f77,
0x01780c09,0x7d7a0907,
0x0e027704,0x7e010007,
0x7d7a7c05,0x037a7c79,
0x7e770b02,0x7d797f03,
0x7e077c01,0x0a080a0a,
0x03747a05,0x7f027d01,
0x0c017708,0x7b7e060a,
0x7d02027b,0x7c067f7e,
0x0d7b797f,0x7f7c7d05,
0x030e1103,0x0b09787e,
0x77050e72,0x7b0d0379,
0x7d060a7d,0x027c027e,
0x6b77797d,0x770d0c79,
0x7d756f0e,0x190a160c,
0x73026b72,0x1278060b,
0x76020077,0x74770700,
0x03070179,0x04040302,
0x790f0202,0x027f017d,
0x7e79087f,0x7a710506,
0x727d747c,0x757b090b,
0x01090975,0x7b797b02,
0x006d7c09,0x70070570,
0x0c7a767c,0x78750301,
0x7f007e0e,0x08080a04,
0x03047505,0x07067516,
0x7c017903,0x03057a0a,
0x01017f00,0x727c050b,
0x7b6e0703,0x787f7a01,
0x760b7003,0x747a027d,
0x097b6b15,0x08077111,
0x726f1075,0x67171777,
0x137f057a,0x0e0a7574,
0x7a100002,0x79070c02,
0x16710c10,0x13177279,
0x6b201b0b,0x66212822,
0x15146314,0x6b11705d,
0x6d160a6b,0x70176c60,
0x70737069,0x72195f62,
0x7a000876,0x71090c7e,
0x6818617a,0x0c6b0c01,
0x71196167,0x196b700c,
0x79100d12,0x71186c67,
0x0208047a,0x7f790274,
0x7e030408,0x05080306,
0x03007d0b,0x09040101,
0x7f017c79,0x02767e05,
0x76030873,0x797d7a7f,
0x0e0f7701,0x73690d7e,
0x6f65256e,0x1b1e206b,
0x09061015,0x6f6a1418,
0x73030c77,0x03747379,
0x7a6e1810,0x077b710c,
0x64602321,0x0d196d0f,
0x1d216a72,0x1a1d1868,
0x746d6d0d,0x10726d12,
0x7e787e16,0x76107707,
0x0f79027b,0x7c0a0003,
0x027e7a02,0x03770200,
0x04790a08,0x04797f09,
0x7a7e7f05,0x0b00797d,
0x7d7c040a,0x06040501,
0x7e780201,0x7b000003,
0x7f05767a,0x07000304,
0x0b770102,0x007c7800,
0x78150d79,0x080e1476,
0x0b160900,0x6072140c,
0x770b190a,0x110b7173,
0x737e760c,0x0c086609,
0x670a0911,0x05771276,
0x08020c0a,0x0470060a,
0x15730f7b,0x7a7b1478,
0x0b730f1d,0x120a1967,
0x1176736e,0x6a707f0f,
0x757f0f06,0x6f057c73,
0x7e01067b,0x047c7d11,
0x7a030411,0x0602007a,
0x717d7703,0x7c010604,
0x0d770779,0x797e0801,
0x10741b0d,0x027c0875,
0x7f777776,0x030f720b,
0x797d0801,0x07017b73,
0x70010979,0x79737a7c,
0x037f7c01,0x7c047803,
0x03747d05,0x7f08787e,
0x7e790005,0x03000079,
0x6f707a09,0x77760007,
0x75797e0c,0x79767f78,
0x130e0874,0x0b03057e,
0x6e0f7a12,0x6f08100a,
0x71736500,0x0c0a0d74,
0x1510796a,0x17760e13,
0x2322191f,0x1d206510,
0x233f3759,0x59705c5e,
0x532f582e,0x2e546151,
0x707d7177,0x07675962,
0x0c740e09,0x71100f78,
0x6d0e7313,0x0d0e0d06,
0x727c7d73,0x077b7075,
0x180d7618,0x7d747a05,
0x090e1570,0x13111c0e,
0x0c730d08,0x7a090201,
0x070e0e75,0x7c78090f,
0x7f000007,0x7e75747f,
0x047f0502,0x017e7e03,
0x77117f09,0x11027b7a,
0x6c197767,0x0f0d7876,
0x72117811,0x14161c0f,
0x117f0d0f,0x78097973,
0x6f14726c,0x6d0d0f6e,
0x7f02077a,0x096e0f6f,
0x7f7d7877,0x0103777f,
0x06786e07,0x78086d0a,
0x730b017a,0x767b070a,
0x0c0b7e74,0x08767f05,
0x6a626c68,0x1466187e,
0x12667a1b,0x6b141a1c,
0x711d691c,0x0f191a6b,
0x716b076d,0x0a6c6f13,
0x0972056d,0x0b0d0e0b,
0x0b040469,0x047a780a,
0x0003047f,0x007d7c00,
0x06070406,0x04027d78,
0x08747a07,0x060e7b06,
0x05727005,0x0a080809,
0x047b7211,0x08010908,
0x040c037f,0x7d067f07,
0x7008147c,0x1604777e,
0x7a100c0d,0x780e7f0d,
0x070b0c77,0x7676780b,
0x06747e79,0x647f7076,
0x077d037f,0x7c7d7906,
0x7f797779,0x7f0e0505,
0x017d007a,0x7c7f0902,
0x027b0205,0x017e0001,
0x04037d7c,0x007a7f7f,
0x7e07767f,0x05077600,
0x01071305,0x7a7c7c73,
0x0901770b,0x13130b78,
0x06097675,0x057b7c07,
0x7c000a7b,0x76787d0b,
0x790a1002,0x01090576,
0x750b0301,0x75071304,
0x09720b78,0x0f047975,
0x086f7f7b,0x0b127c7d,
0x0c786f0f,0x6d7a0a7f,
0x75030104,0x6c706e12,
0x75790506,0x7d76717b,
0x01090100,0x79017e73,
0x0300067d,0x0001037e,
0x0e067d7c,0x7d047d05,
0x70717c06,0x74156b0f,
0x017d7778,0x780d087d,
0x77727f02,0x7e02077d,
0x73777669,0x74117600,
0x7e7a0671,0x7e01796e,
0x010c037a,0x00770d7d,
0x0800030d,0x74090002,
0x67650904,0x70740601,
0x1b6f5c17,0x1568680c,
0x6e041579,0x6e641715,
0x68736109,0x74760d69,
0x15787371,0x0779716a,
0x087f080a,0x0a777b75,
0x047e057d,0x7f7c0504,
0x7b7d7f05,0x7a7e7c7e,
0x0502017d,0x00007b00,
0x1b690a73,0x6c6f737a,
0x137b7d0b,0x6217146e,
0x767c0b09,0x7e07056e,
0x6c071002,0x7205750a,
0x0f676c0e,0x74126a6f,
0x06780477,0x1c0e166a,
0x007d7b7b,0x7a7d0801,
0x7f010002,0x00060e7e,
0x047a787f,0x7c75017f,
0x120e7378,0x7a720e7c,
0x040e086a,0x1c1e1617,
0x11057204,0x760b120d,
0x79050405,0x7f070701,
0x037c7e7e,0x7b057f00,
0x7d08737c,0x03040308,
0x077e7505,0x7a04037c,
0x057b0805,0x0a0a0679,
0x77700777,0x75760772,
0x64655e17,0x180e746b,
0x12631f6c,0x6a165f63,
0x0b7b010e,0x7d6b0f74,
0x767f077a,0x03017c07,
0x0301740d,0x057c037e,
0x0f751700,0x0f797878,
0x0c0d1711,0x13111011,
0x79010703,0x03057b04,
0x06037c07,0x717a7707,
0x7a7e7a01,0x7e7a0e03,
0x0d0c7112,0x71080a7b,
0x13146b12,0x66790368,
0x6b5a2563,0x55231f5e,
0x090c0a7c,0x14646c0f,
0x6f640c77,0x150b1309,
0x69000d18,0x61650605,
0x760b060b,0x757a0d14,
0x060d7879,0x000c097f,
0x676a036f,0x097b020b,
0x1719121b,0x10191f10,
0x166a6d1f,0x6a196b72,
0x010a7a72,0x7077716f,
0x75037201,0x067f0101,
0x0b0d0479,0x03047e7f,
0x760a7e00,0x7e7f7e7b,
0x0a087c0f,0x7c07087e,
0x76070909,0x7b757f01,
0x7a0a0502,0x7f7d7a7f,
0x6d080703,0x080c0270,
0x7b7f7e74,0x0105006c,
0x7f027a7b,0x08787b7a,
0x00737f03,0x737e0072,
0x7f087d7b,0x01067f7f,
0x7b7f7a09,0x087e787d,
0x7f03117f,0x7f036f04,
0x7603007b,0x7700767c,
0x05787c06,0x07010006,
0x7a020c03,0x01057903,
0x7d780502,0x017f0601,
0x79787e7d,0x037f767c,
0x0675107f,0x7605040f,
0x7c007f79,0x7e797106,
0x7e0b7f06,0x0b79027c,
0x7519090d,0x7d027777,
0x0707087b,0x057b0275,
0x7a077a7e,0x7076027c,
0x0002087f,0x7507017b,
0x7a7d047b,0x05000002,
0x0a76767c,0x0d00797c,
0x6d6c100d,0x77791375,
0x0c130d06,0x69666c6f,
0x0e10080b,0x0d761705,
0x02760002,0x7408067b,
0x02090002,0x060c0877,
0x7e007707,0x02020200,
0x7d757a7d,0x7505007c,
0x0673057c,0x7e017974,
0x7d78060d,0x0b077508,
0x797e0403,0x797b7d79,
0x7678010d,0x76057973,
0x717a7c12,0x04027a7f,
0x06096c0c,0x09760a0c,
0x726e0a13,0x7a0b757a,
0x09047c7b,0x070d0e02,
0x787d060a,0x117e7703,
0x05037d02,0x7703747d,
0x01050477,0x0101727f,
0x7d7d7503,0x7e010b06,
0x0b007b05,0x7f010400,
0x7b107373,0x0e080207,
0x7403010b,0x77750912,
0x767f0005,0x137f117f,
0x000b0a72,0x79780575,
0x7b04777f,0x06020803,
0x7c09787b,0x7a767e08,
0x04037f04,0x7c7e7f01,
0x7c000007,0x0004017c,
0x057e7f00,0x7c7a7d02,
0x7f7e0775,0x7e010078,
0x6f0b017e,0x0e02067c,
0x787d7c64,0x7f0e0a79,
0x03050309,0x0f7a007b,
0x7f086e7a,0x0f07770a,
0x7d710173,0x0b0a7f7f,
0x077f017a,0x7c050606,
0x7d0b0705,0x790e7b09,
0x7b00027b,0x7e7e7d7b,
0x7f7a787d,0x7d0d7f0d,
0x077b7c03,0x00027e7b,
0x7715716b,0x00740a78,
0x077c0d76,0x6b70766b,
0x7d75040d,0x07027605,
0x00010001,0x06041100,
0x6c02047d,0x03040905,
0x71090601,0x7f087e00,
0x09767d06,0x046f017e,
0x75757478,0x77710904,
0x0300007e,0x7a037a0a,
0x6f6e7a75,0x01010b0a,
0x116b1c64,0x60171615,
0x59212020,0x1e1f2116,
0x770c6871,0x1f661c61,
0x7277081a,0x611a1816,
0x780d0674,0x08791671,
0x7a080d0b,0x7d780d70,
0x070c140f,0x196a1170,
0x7305770e,0x79000274,
0x626e1570,0x721a0b73,
0x711e6362,0x19676026,
0x09721011,0x6b14106f,
0x227c7779,0x735e0075,
0x0e6a6e0e,0x746d1470,
0x00017903,0x7b7b7470,
0x7778007e,0x7d7e7800,
0x79037704,0x7d7d067a,
0x76097b7b,0x7a037704,
0x7101037d,0x79047b03,
0x65180205,0x6b6b0773,
0x76210b1c,0x6a211418,
0x6c5a212a,0x585e2468,
0x126e6d13,0x73190f1c,
0x796e7672,0x78037806,
0x77077a75,0x05737d03,
0x787a0207,0x7f7a0704,
0x7a7c7d02,0x01010779,
0x020a7c01,0x7b017d7f,
0x7a760176,0x767d0279,
0x7f03047b,0x787e7209,
0x7a7d030a,0x08037e78,
0x0000057e,0x04717b08,
0x7c057d03,0x797d7f00,
0x037d0301,0x7f00087d,
0x6919121f,0x1a0a7570,
0x62646916,0x21575b6d,
0x7d127313,0x756d6c0f,
0x7d7c7d7c,0x017a7c01,
0x7e047e79,0x7b7b0402,
0x76797d6e,0x710b7902,
0x7e060f71,0x75766b7f,
0x06736a00,0x0a720e11,
0x0104760c,0x7a031105,
0x6e166f6b,0x07047f06,
0x0678757b,0x7c126f01,
0x6c070705,0x030d7776,
0x6e770610,0x000b1277,
0x71740e05,0x6d6f1173,
0x09796f74,0x047d7877,
0x77007e7c,0x7f097e7f,
0x03007977,0x0c017e0b,
0x78000d0b,0x73790504,
0x00007e08,0x7c710b00,
0x037c020b,0x0402057e,
0x070e7b05,0x00057476,
0x1003077e,0x007b0278,
0x060f0506,0x0e757c06,
0x0a030401,0x05100678,
0x7a760106,0x047d7b7d,
0x7d7d017e,0x767a7f01,
0x77750407,0x0104017c,
0x02147713,0x6c73027c,
0x676d196b,0x7773137c,
0x0f17056a,0x0c1a0b71,
0x120e1070,0x71701964,
0x01757904,0x7f010272,
0x22665f2b,0x18215c0d,
0x0e711a18,0x0e142324,
0x7d770775,0x780b7912,
0x07040505,0x0a040c7c,
0x700d000d,0x6f060511,
0x0d080478,0x6e6c116c,
0x72766f76,0x090e0b01,
0x0878750c,0x74777910,
0x057d7b7e,0x04770a05,
0x037e0405,0x780b0309,
0x7e007d00,0x10067d7b,
0x75010902,0x7a7c007f,
0x027b7e05,0x007e017b,
0x79010002,0x7e067703,
0x030c0101,0x047f017d,
0x720f7a09,0x76790b7f,
0x7d7b0005,0x6b7b717f,
0x097b0c09,0x6e127f79,
0x1a1c1170,0x160d1316,
0x7c101013,0x1271681b,
0x7b7d7e76,0x007f0576,
0x047d0005,0x037c0373,
0x6a630c7e,0x78070c76,
0x76131a10,0x68216669,
0x710e6f0f,0x77720d67,
0x06761171,0x76750711,
0x04057806,0x6e000814,
0x14701714,0x1116070f,
0x0a061305,0x7b776869,
0x7611776d,0x090b0a74,
0x750d0a7f,0x04777a7b,
0x0879017c,0x7103030b,
0x7e7f0479,0x7d030308,
0x0b16070b,0x0a7b027c,
0x74007609,0x79777176,
0x0b747b77,0x7e0d077c,
0x7808790b,0x11017f7e,
0x71701272,0x0c0f7f0c,
0x0b61616f,0x6d1f6a7b,
0x0c76170c,0x756c1210,
0x72140c7f,0x70156d07,
0x02720975,0x7d057f04,
0x71711117,0x6d74017b,
0x03090500,0x070f7276,
0x74077407,0x08030102,
0x0b076f0a,0x72767875,
0x170f0f76,0x710a7006,
0x01106a70,0x100d0f07,
0x78020a7f,0x09091372,
0x07787f74,0x78060e06,
0x0d787c08,0x0a7b0c79,
0x727c7969,0x0a0d0871,
0x7d037e05,0x07717778,
0x7b790707,0x797d067e,
0x7b757f06,0x76080179,
0x6a121a1e,0x136d780f,
0x146c6c6d,0x1614716e,
0x5e691811,0x0a771012,
0x7671766e,0x0c757872,
0x70206c19,0x1d23127a,
0x780a050a,0x15130c17,
0x080a0701,0x76000676,
0x7c030a0c,0x087a7708,
0x0276056a,0x04000105,
0x760e7b7a,0x03770078,
0x77060509,0x11797074,
0x026b7402,0x797e7674,
0x057b017f,0x08007a00,
0x7b0b0603,0x79777906,
0x097d0100,0x7808067b,
0x01000205,0x037b7f07,
0x7d7d0578,0x7c037c7c,
0x07760703,0x757e0606,
0x7f73007e,0x01017d04,
0x7f020f7f,0x0904740d,
0x7e7a7704,0x7f007f78,
0x00757906,0x7d0c7400,
0x0a0d7d00,0x7f0b7973,
0x037b7b79,0x01047374,
0x027e7f7d,0x08067e09,
0x08017c02,0x7f00007c,
0x727f7e79,0x09700975,
0x150d6c07,0x0b057575,
0x00781079,0x7709790b,
0x7802087b,0x7309037e,
0x78767d7a,0x7f77037b,
0x7b027f76,0x0578087c,
0x7b75757d,0x787b7f76,
0x03777078,0x747f7d06,
0x73010405,0x710d7c7a,
0x78707112,0x7e037f01,
0x18091414,0x6c697674,
0x0877137e,0x090e6b0d,
0x630e756a,0x7e130b6e,
0x02756e7a,0x066e100b,
0x7a030203,0x7901730b,
0x0a7a7d7f,0x010e7772,
0x7d0d7d7d,0x06080577,
0x017c727c,0x06057f0c,
0x0b070501,0x0406057e,
0x7277680e,0x7b7b0811,
0x6e777519,0x710f7804,
0x0d736873,0x1a13070f,
0x776e6d78,0x73097d6f,
0x007b7a75,0x73070a7e,
0x01087f74,0x077e027c,
0x01010200,0x7e067c08,
0x7f7c0200,0x040a7e03,
0x7606777d,0x017c0302,
0x6e1c0d13,0x01017a02,
0x72700e0c,0x0b0c1411,
0x7f7c7f03,0x7e027d02,
0x7c08017f,0x7d7e0077,
0x7b747a7f,0x04017b03,
0x6e7a7704,0x7c7a7a7f,
0x14681422,0x76150c0c,
0x1111120f,0x6d16106e,
0x0c6e0e7c,0x11737177,
0x05050970,0x716f0774,
0x06730177,0x7b7d7b74,
0x0103060b,0x057d7a04,
0x1a0c7f7a,0x0605010a,
0x0374080b,0x76050072,
0x6f760401,0x13097915,
0x06020804,0x037a067f,
0x0877000a,0x0a050101,
0x030b077c,0x7b7c0b7f,
0x02017801,0x7b047d06,
0x017e0e00,0x067c067f,
0x770a7608,0x75080703,
0x17766f6b,0x1274106d,
0x10097413,0x1b6c661b,
0x77770a76,0x72021077,
0x7f6e7404,0x166a7372,
0x1003787f,0x0079137b,
0x7f010203,0x00010676,
0x74080200,0x7d017c7a,
0x01726c6f,0x106f1512,
0x09070202,0x7e7b0608,
0x040f787f,0x7e7d7c7c,
0x05017d7b,0x057e7d7b,
0x0e040c07,0x7e7d7f06,
0x0b777273,0x08077107,
0x717d7b69,0x07727506,
0x7d74767a,0x017d0c77,
0x7e747906,0x00067f7b,
0x0e0f6f76,0x04797d00,
0x0b110d71,0x700f1375,
0x05020a70,0x0a090775,
0x7d7e037b,0x04030708,
0x7e01067e,0x7b7b7608
};
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaOpen.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_emifaOpen.c
*
* @path $(CSLPATH)\src\emifa
*
* @desc File for functional layer of CSL API @a CSL_emifaOpen()
* - The @a CSL_emifaOpen() function definition & it's associated
* functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 10-May-2005 RM File Created.
*
* 09-Sep-2005 NG Updation according to coding guidelines
*
* =============================================================================
*/
#include <csl_emifa.h>
/** ============================================================================
* @n@b CSL_emifaOpen
*
* @b Description
* @n This function populates the peripheral data object for the EMIFA
* instance and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of EMIFA device. The device can be re-opened anytime after it has been
* normally closed if so required. The handle returned by this call is
* input as an essential argument for rest of the APIs described
* for this module.
*
* @b Arguments
* @verbatim
pEmifaObj Pointer to the EMIFA instance object
emifaNum Instance of the EMIFA to be opened.
pEmifaParam Pointer to module specific parameters
pStatus Pointer for returning status of the function call
@endverbatim
*
* <b> Return Value </b>
* @li CSL_EmifaHandle - Valid EMIFA instance handle will be
* returned if status value is equal to
* CSL_SOK.
*
* <b> Pre Condition </b>
* @n @a CSL_emifaInit() must be called successfully.
*
* <b> Post Condition </b>
* @n EMIFA object structure is populated
*
* @b Modifies
* @n 1. The status variable
* @n 2. EMIFA object structure
*
* @b Example:
* @verbatim
CSL_Status status;
CSL_EmifaObj emifaObj;
CSL_EmifaHandle hEmifa;
hI2c = CSL_emifaOpen (&emifaObj,
CSL_EMIFA,
NULL,
&status
);
@endverbatim
*
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_emifaOpen, ".text:csl_section:emifa");
CSL_EmifaHandle CSL_emifaOpen (
CSL_EmifaObj *pEmifaObj,
CSL_InstNum emifaNum,
CSL_EmifaParam *pEmifaParam,
CSL_Status *pStatus
)
{
CSL_EmifaHandle hEmifa = (CSL_EmifaHandle)NULL;
CSL_EmifaBaseAddress baseAddress;
if (pStatus == NULL) {
/* Do nothing: Module handle already initialised to NULL */
}
else if (pEmifaObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
*pStatus = CSL_emifaGetBaseAddress(emifaNum, pEmifaParam, &baseAddress);
if (*pStatus == CSL_SOK) {
pEmifaObj->regs = baseAddress.regs;
pEmifaObj->perNum = (CSL_InstNum)emifaNum;
hEmifa = (CSL_EmifaHandle)pEmifaObj;
}
else {
pEmifaObj->regs = (CSL_EmifaRegsOvly)NULL;
pEmifaObj->perNum = (CSL_InstNum)-1;
}
}
return (hEmifa);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/edma/edma_interrupt/inc/edmaCommon.h | <filename>DSP/TI-Header/csl_c6455/example/edma/edma_interrupt/inc/edmaCommon.h
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
*
* @file edmaCommon.h
*
* @path $(CSLPATH)\example\edma\edma_interrupt\inc
*
* @desc Header file for EDMA interrupt example
*
* =============================================================================
*/
#ifndef _EDMACOMMON_H_
#define _EDMACOMMON_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Macro for tcc handler */
#define InvokeHandle(num) TccHandlerTable[num]()
typedef void (*EdmaTccHandler)(void);
/* Funtion which registers individual event handlers in a table */
void EdmaEventHook(Uint16 ,EdmaTccHandler);
/* Forward declaration */
void eventEdmaHandler();
void eventGlobalEdmaHandler();
Bool Verify_Transfer(Uint16 aCnt, Uint16 bCnt, Uint16 cCnt, Uint16 srcBIdx, \
Uint16 dstBIdx, Uint16 srcCIdx, Uint16 dstCIdx, \
Uint8 *srcBuff, Uint8 *dstBuff, Bool abSync );
#ifdef __cplusplus
}
#endif
#endif /* _EDMACOMMON_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc_src/inc/tistdtypes.h | /*********************************************************************
* Copyright (C) 2005 Texas Instruments Incorporated.
* All Rights Reserved
*********************************************************************/
/*
* ======== tistdtypes.h ========
*/
/*
* These types are also defined by other TI components. They are bracketed
* with _TI_STD_TYPES to avoid warnings for duplicate definition.
*
* You may get warnings about duplicate type definitions when using this
* header file with earlier versions of DSP/BIOS and CSL.
*
* You can use the '-pds303' compiler option to suppress these warnings.
*/
#ifndef _TI_STD_TYPES
#define _TI_STD_TYPES
/*
* This '#ifndef STD_' is needed to protect from duplicate definitions
* of Int, Uns, etc. in DSP/BIOS v4.x (e.g. 4.90, 4.80) since these versions
* of DSP/BIOS did not contain the '#ifndef_TI_STD_TYPES' logic.
*/
#ifndef STD_
/*
* Aliases for standard C types
*/
typedef int Int;
typedef unsigned Uns;
typedef char Char;
/* pointer to null-terminated character sequence */
typedef char *String;
typedef void *Ptr; /* pointer to arbitrary type */
typedef unsigned short Bool; /* boolean */
#endif /* STD_ */
/*
* Uint8, Uint16, Uint32, etc are defined to be "smallest unit of
* available storage that is large enough to hold unsigned or integer
* of specified size".
*/
/* Handle the 6x ISA */
#if defined(_TMS320C6X)
/* Unsigned integer definitions (32bit, 16bit, 8bit) follow... */
typedef unsigned int Uint32;
typedef unsigned short Uint16;
typedef unsigned char Uint8;
/* Signed integer definitions (32bit, 16bit, 8bit) follow... */
typedef int Int32;
typedef short Int16;
typedef char Int8;
/* Handle the 54x, 55x and 28x ISAs */
#elif defined(_TMS320C5XX) || defined(__TMS320C55X__) || defined(_TMS320C28X)
/* Unsigned integer definitions (32bit, 16bit, 8bit) follow... */
typedef unsigned long Uint32;
typedef unsigned short Uint16;
typedef unsigned char Uint8;
/* Signed integer definitions (32bit, 16bit, 8bit) follow... */
typedef long Int32;
typedef short Int16;
typedef char Int8;
#else
/* Other ISAs not supported */
#error <tistdtypes.h> is not supported for this target
#endif /* defined(_6x_) */
#endif /* _TI_STD_TYPES */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrOpen.c | <gh_stars>0
/* =============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file csl_tmrOpen.c
*
* @brief File for functional layer of CSL API CSL_tmrOpen()
*
* @Path $(CSLPATH)\src\timer
*
* @desc The CSL_tmrOpen() function definition & it's associated
* functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 1-Sept-2004 HMM File Created.
* 29-Jul-2005 PSK Updted changes acooriding to revised timer spec. the number
* convention TIM12, TIM34 are changed to TIMLO and TIMHI.
*
* ============================================================================
*/
#include <csl_tmr.h>
/** ===========================================================================
* @b CSL_trmOpen
* @b Description
* @n This function populates the peripheral data object for the TIMER
* instance and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of TIMER device. The device can be re-opened anytime after it has been
* normally closed if so required. The handle returned by this call is
* input as an essential argument for rest of the APIs described
* for this module.
*
* @b Arguments
* @verbatim
tmrObj Pointer to timer object.
tmrNum Instance of timer CSL to be opened.
There are three instance of the timer
available. So, the value for this parameter will be
based on the instance.
pTmrParam Module specific parameters.
status Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_TmrHandle
* @n Valid timer handle will be returned if
* status value is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid timer handle is returned
* @li CSL_ESYS_FAIL The timer instance is invalid
* @li CSL_ESYS_INVPARAMS The object structure is not properly initialized
*
* 2. Timer object structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Timer object structure
*
* @b Example
* @verbatim
CSL_status status;
CSL_TmrObj tmrObj;
CSL_TmrHandle hTmr;
hTmr = CSL_tmrOpen(&tmrObj, CSL_TMR_1, NULL, &status);
...
@endverbatim
* ========================================================================== */
#pragma CODE_SECTION(CSL_tmrOpen, ".text:csl_section:tmr");
CSL_TmrHandle CSL_tmrOpen (
CSL_TmrObj *pTmrObj,
CSL_InstNum tmrNum,
CSL_TmrParam *pTmrParam,
CSL_Status *pStatus
)
{
CSL_Status st;
CSL_TmrHandle hTmr = NULL;
CSL_TmrBaseAddress baseAddress;
if (pStatus == NULL) {
/* do nothing */
}
else if (pTmrObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
st = CSL_tmrGetBaseAddress(tmrNum, pTmrParam, &baseAddress);
if (st == CSL_SOK) {
pTmrObj->regs = baseAddress.regs;
pTmrObj->perNum = (CSL_InstNum)tmrNum;
hTmr = (CSL_TmrHandle)pTmrObj;
}
else {
pTmrObj->regs = (CSL_TmrRegsOvly)NULL;
pTmrObj->perNum = (CSL_InstNum)-1;
hTmr = (CSL_TmrHandle)NULL;
}
*pStatus = st;
}
return hTmr;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/mcbsp/mcbsp_edma/src/edmaIntDispatcher.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ===========================================================================
*
* @file edmaIntDispacher.c
*
* @path $(CSLPATH)\example\mcbsp\mcbsp_edma\src
*
* @desc Edma interrupt handler for the Example of MCBSP
* ============================================================================
*/
/* ===========================================================================
* Revision History
* ===============
* 9-Aug-2006 RR File Created.
* ============================================================================
*/
#include <edmaCommon.h>
/* Global Edma Tcc handler table */
#pragma DATA_SECTION(TccHandlerTable,".testMem");
EdmaTccHandler TccHandlerTable[64];
void eventEdmaHandler(void *handle)
{
CSL_Edma3Handle hModule = (CSL_Edma3Handle)handle;
CSL_BitMask32 maskVal;
CSL_Edma3CmdIntr regionIntr;
Uint32 tcc, intr,intrh;
/* Read the IPR */
regionIntr.region = CSL_EDMA3_REGION_0;
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND, ®ionIntr);
while (regionIntr.intr || regionIntr.intrh)
{
intr = regionIntr.intr;
intrh = regionIntr.intrh;
tcc = 0;
while (intr)
{
maskVal = 1 << tcc;
if (intr & maskVal)
{
InvokeHandle(tcc);
intr &= ~maskVal;
}
tcc++;
}
tcc = 0;
while (intrh)
{
maskVal = 1 << tcc;
if (intrh & maskVal)
{
InvokeHandle((tcc+32));
intrh &= ~maskVal;
}
tcc++;
}
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,®ionIntr);
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
}
}
void EdmaEventHook(int tcc, EdmaTccHandler fxn)
{
TccHandlerTable[tcc] = (fxn);
}
void eventGlobalEdmaHandler(void *handle)
{
CSL_BitMask32 mask,maskVal;
CSL_Edma3CmdIntr regionIntr;
Uint32 tcc, intr,intrh;
Int region;
CSL_Edma3Handle hModule = (CSL_Edma3Handle)handle;
/* Read the IPR */
regionIntr.region = CSL_EDMA3_REGION_GLOBAL;
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
intr = regionIntr.intr;
intrh = regionIntr.intrh;
mask = 1;
tcc = 0;
while (intr)
{
maskVal = mask << tcc;
if (regionIntr.intr & maskVal)
{
InvokeHandle(tcc);
intr &= ~maskVal;
}
tcc++;
}
mask = 1;
tcc = 0;
while (intrh)
{
maskVal = mask << tcc;
if (intrh & maskVal)
{
InvokeHandle((tcc+32));
intrh &= ~maskVal;
}
tcc++;
}
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,®ionIntr);
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
if ((regionIntr.intr !=0)||(regionIntr.intrh !=0))
{
region = CSL_EDMA3_REGION_GLOBAL;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_EVAL,®ion);
}
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspWrite.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_mcbspWrite.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API CSL_mcbspWrite()
*
*/
/* =============================================================================
* Revision History
* ================
* Jun 29,2004 <NAME> - Created
* Mar 23, 2006 ds Added check for invalid handle
* =============================================================================
*/
#include <csl_mcbsp.h>
/** ============================================================================
* @n@b CSL_mcbspWrite
*
* @b Description
* @n Transmits the data from MCBSP. The word length for the write operation
* is specified using @a wordLen argument. According to this word length,
* the appropriate amount of data will transmitted from the data object
* (variable); the pointer to which is passed as the third argument.
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
wordLen Word length of data to be transmitted
data Pointer to data object (variable) that holds the
data to be sent out
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Write data successful
* @li CSL_EMCBSP_INVSIZE - Invalid Word length
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before CSL_mcbspWrite() can be called.
*
* <b> Post Condition </b>
* @n Data is written to DXR register
*
* @b Modifies
* @n MCBSP registers
*
* @b Example
* @verbatim
Uint16 outData;
CSL_Status status;
CSL_McbspHandle hMcbsp;
...
// MCBSP object defined and HwSetup structure defined and initialized
...
// Init, Open, HwSetup successfully done in that order
...
// MCBSP SRG, Frame sync, XMT taken out of reset in that order
...
outData = 0x1234;
status = CSL_mcbspWrite(hMcbsp, CSL_MCBSP_WORDLEN_16,&outData);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_mcbspWrite, ".text:csl_section:mcbsp");
CSL_Status CSL_mcbspWrite (
CSL_McbspHandle hMcbsp,
CSL_McbspWordLen wordLen,
void *data
)
{
CSL_Status status = CSL_SOK;
if (hMcbsp == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (data == NULL) {
status = CSL_ESYS_INVPARAMS;
}else{
switch(wordLen) {
case CSL_MCBSP_WORDLEN_8:
case CSL_MCBSP_WORDLEN_12:
case CSL_MCBSP_WORDLEN_16:
hMcbsp->regs->DXR = *((Uint16 *)data) ;
break;
case CSL_MCBSP_WORDLEN_20:
case CSL_MCBSP_WORDLEN_24:
case CSL_MCBSP_WORDLEN_32:
hMcbsp->regs->DXR = *(Uint32 *)data;
break;
default:
status = CSL_EMCBSP_INVSIZE;
}
}
return(status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/cfg/src/Cfg_example.c | /* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file Cfg_example.c
*
* @path $(CSLPATH)\example\cfg\src
*
* @desc Example for cfg module
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This example,
* 1. Initializes and opens the CSL INTC for CFG module.
* 2. Initializes and opens the CSL CFG module instance.
* 3. Clears the fault if already there
* 4. Generates the fault interrupt by writing 1000 to the reserved s
* pace of internal configuration space (0x01BE0000)
* 5. Does the fault address comparision to ensure the fault occured
* in the proper address (0x01BE0000) or not
* 6. Clears the error conditions
* 7. Displays the messages based on step 4
*
*
* ============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Cfg_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 28-July-2005 PSK File Created
*
* 16-Dec-2005 ds Updated documentation
* =============================================================================
*/
#include <csl_cfg.h>
#include <stdio.h>
#include <csl_intc.h>
#include <csl_intcAux.h>
/* Intc variable declarartions */
CSL_IntcContext intcContext;
CSL_IntcEventHandlerRecord EventHandler[30];
CSL_IntcObj intcObjEdma;
CSL_IntcHandle hIntcEdma;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
/* The data variable pointing to protected area */
Int *protData = (Int *)0x01BE0000;
/* Forward declaration */
void myIsr();
void cfg_example (void);
/* Global variables declarations */
volatile Uint32 intFlag = 0;
Uint32 cfgExampleFail = 0;
/* Handle for the CFG instance */
CSL_CfgHandle hCfg;
/*
* ============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* ============================================================================
*/
void main(void)
{
/* Invoke example */
cfg_example();
if (cfgExampleFail) {
printf("CFG Example FAILED\n");
}
else {
printf("CFG Example PASSED\n");
}
return;
}
/*
* ============================================================================
* @func cfg_example
*
* @desc
* This function invokes example that prove functionalites of fault
* occurence when something to be written to the reserved memory.
* The CSL API to retrive the fault address parameters. this is for
* config memory protection
*
* @arg
* None
*
* @expected result
* If the example passes, it displays the message "PASSED"
* If the example fails, it displays the message "FAILED"
*
* @eg
* cfg_example();
* ============================================================================
*/
void cfg_example (void)
{
CSL_CfgHandle hCfg;
CSL_Status status;
CSL_CfgObj cfgObj;
CSL_IntcParam vectId;
CSL_IntcObj intcObj;
CSL_IntcHandle hIntc;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
Uint32 faultAdd;
printf("CFG EXAMPLE DEMO\n");
/* Intc Module Initialization */
intcContext.eventhandlerRecord = EventHandler;
intcContext.numEvtEntries = 10;
CSL_intcInit(&intcContext);
/* Enable NMIs */
CSL_intcGlobalNmiEnable();
/* Enable Global Interrupts */
CSL_intcGlobalEnable(&state);
/* Opening a handle for the event */
vectId = CSL_INTC_VECTID_4;
hIntc = CSL_intcOpen (&intcObj, CSL_INTC_EVENTID_IDMA_CMPA, &vectId, NULL);
/* binding to the ISR */
EventRecord.handler = (CSL_IntcEventHandler)&myIsr;
EventRecord.arg = hIntc;
CSL_intcPlugEventHandler(hIntc, &EventRecord);
/* Enabling event */
CSL_intcHwControl(hIntc,CSL_INTC_CMD_EVTENABLE,NULL);
/* Initialize the CFG CSL module */
status = CSL_cfgInit(NULL);
if (status != CSL_SOK) {
printf ("CFG: Initialization... Failed.\n");
printf ("\tReason: CSL_cfgInit failed. [status = 0x%x].\n", status);
cfgExampleFail++;
return;
}
/* Cfg Level Open */
hCfg = CSL_cfgOpen (&cfgObj, (CSL_InstNum)CSL_MEMPROT_CONFIG, NULL,&status);
if ((hCfg == NULL) || (status != CSL_SOK)) {
printf ("CFG: Cfg Opening instance... Failed.\n");
printf ("\tReason: Error opening the instance. \
[status = 0x%x, hCfg = 0x%x]\n", status, hCfg);
cfgExampleFail++;
return;
}
/* clear the fault if already there */
status = CSL_cfgHwControl(hCfg, CSL_CFG_CMD_CLEAR, NULL);
if (status != CSL_SOK) {
printf ("CFG: The func to clear ... Failed.\n");
cfgExampleFail++;
return;
}
/* writing some value to the reserved space in internal configuration space
* to generate the fault */
*protData = 1000;
printf("The Data at location [0x%X]=>0x%X\n", protData, *protData);
/*wait for the interrupt */
while (1) {
if (intFlag == 1)
break;
}
printf("Interrupt occured \n");
/* Query to get the fault address */
status = CSL_cfgGetHwStatus(hCfg, CSL_CFG_QUERY_FAULT_ADDR, &faultAdd);
if (status != CSL_SOK) {
printf ("\nCFG: CSL_CFG_QUERY_FAULT_ADDR query command... Failed.\n");
cfgExampleFail++;
return;
}
/* Verify the fault occured address */
if ((Int *) faultAdd == protData)
printf ("CFG: Fault address = 0x%x \n", faultAdd);
else {
printf ("CFG: Fault occured in diffrent address = 0x%x \n", faultAdd);
cfgExampleFail++;
return;
}
/* Clears the error conditions stored in MPFAR and MPFSR */
status = CSL_cfgHwControl(hCfg, CSL_CFG_CMD_CLEAR, NULL);
if (status != CSL_SOK) {
printf ("CFG: The func to clear ... Failed.\n");
cfgExampleFail++;
return;
}
/*Close the CFG instance */
CSL_cfgClose(hCfg);
return;
}
/*
* ============================================================================
* @func myIsr
*
* @desc
* This is the interrupt service routine function to handle the
* CFG interrupt
*
* ============================================================================
*/
void myIsr (
CSL_IntcEventId *event
)
{
intFlag = intFlag + 1;
CSL_intcEventClear(*event);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/mcbsp/mcbsp_edma/inc/edmaCommon.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ===========================================================================
*
* @file edmaCommon.h
*
* @path $(CSLPATH)\example\mcbsp\mcbsp_edma\src
*
* @desc Header for the Example of MCBSP
* ============================================================================
*/
/* ===========================================================================
* Revision History
* ===============
* 9-Aug-2006 RR File Created.
* ============================================================================
*/
#ifndef _EDMACOMMON_H_
#define _EDMACOMMON_H_
#include <csl_edma3.h>
#include <csl_intc.h>
#include <soc.h>
#include <stdio.h>
#include <csl_mcbsp.h>
#include <cslr_dev.h>
#define InvokeHandle(num) TccHandlerTable[num]()
typedef void (* EdmaTccHandler)(void);
/* Funtion which registers individual event handlers in a table */
void eventEdmaHandler(void *);
void EdmaEventHook(int , EdmaTccHandler);
#endif /* _EDMACOMMON_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspRead.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_mcbspRead.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API CSL_mcbspRead()
*
*/
/* =============================================================================
* Revision History
* ================
* Jun 29, 2004 <NAME> - Created
* Mar 23, 2006 ds Added check for invalid handle
* =============================================================================
*/
#include <csl_mcbsp.h>
/** ============================================================================
* @n@b CSL_mcbspRead
*
* @b Description
* @n Reads the data from MCBSP. The word length for the read operation is
* specefied using @a wordLen argument. According to this word length,
* appropriate amount of data will read in the data object (variable);
* the pointer to which is passed as the third argument.
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
wordLen Word length of data to be read in
data Pointer to data object (variable) that will hold
the read data
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Read data successful
* @li CSL_EMCBSP_INVSIZE - Invalid Word length
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before CSL_mcbspRead() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n MCBSP registers
*
* @b Example
* @verbatim
Uint16 inData;
CSL_Status status;
CSL_McbspHandle hMcbsp;
...
// MCBSP object defined and HwSetup structure defined and initialized
...
// Init, Open, HwSetup successfully done in that order
...
// MCBSP SRG, Frame sync, RCV taken out of reset in that order
...
status = CSL_mcbspRead(hMcbsp, CSL_MCBSP_WORDLEN_16, &inData);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_mcbspRead, ".text:csl_section:mcbsp");
CSL_Status CSL_mcbspRead (
CSL_McbspHandle hMcbsp,
CSL_McbspWordLen wordLen,
void *data
)
{
CSL_Status status = CSL_SOK;
if (hMcbsp == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (data == NULL) {
status = CSL_ESYS_INVPARAMS;
}else {
switch(wordLen) {
case CSL_MCBSP_WORDLEN_8:
case CSL_MCBSP_WORDLEN_12:
case CSL_MCBSP_WORDLEN_16: {
*((Uint16 *)data) = (Uint16)hMcbsp->regs->DRR;
break;
}
case CSL_MCBSP_WORDLEN_20:
case CSL_MCBSP_WORDLEN_24:
case CSL_MCBSP_WORDLEN_32: {
*((Uint32 *)data) = (Uint32)hMcbsp->regs->DRR;
break;
}
default:
status = CSL_EMCBSP_INVSIZE;
}
}
return(status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/csl_utopia2.h | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_utopia2.h
*
* @path $(CSLPATH)\inc
*
* @desc This files contains the macros and inline function for UTOPIA2.
*
*/
/* ============================================================================
* Revision History
* ================
* 15-Feb-2006 ds - Added #undef IDECL and #undef IDEF
*
* ============================================================================
*/
#ifndef _CSL_UTOPIA2_H_
#define _CSL_UTOPIA2_H_
#include <cslr_utopia2.h>
#include <soc.h>
/******************************************************************************\
* scope and inline control macros
\******************************************************************************/
#ifdef __cplusplus
#define CSLAPI extern "C" far
#else
#define CSLAPI extern far
#endif
#undef IDECL
#undef IDEF
#define IDECL static inline
#define IDEF static inline
/******************************************************************************\
* global macro declarations
\******************************************************************************/
/* utopia2 interrupt numbers */
/** Interrupt for Transmit queue */
#define UTOPIA2_INT_XQ 0
/** Interrupt for Receive queue */
#define UTOPIA2_INT_RQ 16
/* utopia2 error interrupt numbers */
/** Receive queue stall interrupt enable bit. */
#define UTOPIA2_ERR_RQS 0
/** Receive clock failed interrupt enable bit. */
#define UTOPIA2_ERR_RCF 1
/** Receive clock present interrupt enable bit. */
#define UTOPIA2_ERR_RCP 2
/** Transmit queue stall interrupt enable bit. */
#define UTOPIA2_ERR_XQS 16
/** Transmit clock failed interrupt enable bit. */
#define UTOPIA2_ERR_XCF 17
/** Transmit clock present interrupt enable bit. */
#define UTOPIA2_ERR_XCP 18
/** Base address of the UTOPIA2 receive queue */
#define UTOPIA2_RCVQ_ADDR CSL_UTOPIA2_RX_EDMA_REGS
/** Base address of the UTOPIA2 transmit queue */
#define UTOPIA2_XMTQ_ADDR CSL_UTOPIA2_TX_EDMA_REGS
/** Default value of UCR */
#define UTOPIA2_UCR_DEFAULT (0x00000000u)
/** Default value of CDR */
#define UTOPIA2_CDR_DEFAULT (0x00FF00FFu)
/******************************************************************************\
* global typedef declarations
\******************************************************************************/
/* device configuration structure */
/**
* @brief The Config structure
*
* Used to configure the UTOPIA2 using utopia2_config(ucr,cdr);
*/
typedef struct {
/** UTOPIA2 Control Register */
Uint32 ucr;
/** Clock Detect Register of UTOPIA2 */
Uint32 cdr;
} UTOPIA2_Config;
/******************************************************************************\
* global variable declarations
\******************************************************************************/
extern CSL_Utopia2Regs *utopia2Regs;
/******************************************************************************\
* global function declarations
\******************************************************************************/
CSLAPI void UTOPIA2_reset();
/******************************************************************************\
* inline function definitions
\******************************************************************************/
/** ============================================================================
* @n@b UTOPIA2_getXmtAddr
*
* @b Description
* @n This function is to get the transmit address of UTOPIA2. This address
* is needed to write to the Transmit Port.
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @li val - address of transmit queue
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 utopXmtAddr;
utopXmtAddr = UTOPIA2_getXmtAddr();
@endverbatim
* =============================================================================
*/
IDEF
Uint32 UTOPIA2_getXmtAddr (
void
)
{
return (Uint32)(UTOPIA2_XMTQ_ADDR);
}
/** ============================================================================
* @n@b UTOPIA2_getRcvAddr
*
* @b Description
* @n This function is to get the receive address of UTOPIA2. This address
* is required to read from the Receiver Port.
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @li val - address of receive queue
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 utopRcvAddr;
utopRcvAddr = UTOPIA2_getRcvAddr();
@endverbatim
* =============================================================================
*/
IDEF
Uint32 UTOPIA2_getRcvAddr (
void
)
{
return (Uint32)(UTOPIA2_RCVQ_ADDR);
}
/** ============================================================================
* @n@b UTOPIA2_getEventId
*
* @b Description
* @n This function is to get the event Id associated to the
* UTOPIA2 CPU-interrupt Id.
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @li val - Event Id of UTOPIA2
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 utopEventId;
utopEventId = UTOPIA2_getEventId();
@endverbatim
* =============================================================================
*/
IDEF
Uint32 UTOPIA2_getEventId (
void
)
{
return (CSL_INTC_EVENTID_UINT);
}
/** ============================================================================
* @n@b UTOPIA2_read
*
* @b Description
* @n Reads data from the receive queue of UTOPIA2.
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @li val - Data from the receive queue.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 utopRxData;
utopRxData = UTOPIA2_read();
@endverbatim
* =============================================================================
*/
IDEF
Uint32 UTOPIA2_read (
void
)
{
return (*(volatile Uint32*)(UTOPIA2_RCVQ_ADDR));
}
/** ============================================================================
* @n@b UTOPIA2_write
*
* @b Description
* @n Writes data into the transmit queue of UTOPIA2.
*
* @b Arguments
* @verbatim
val - Value to be written into transmit queue
@endverbatim
*
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Value passed is written at transmit address of UTOPIA2 i.e.,
* UTOPIA2_XMTQ_ADDR.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 utopTxData = 0x1111FFFF;
UTOPIA2_write(utopTxData);
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_write (
Uint32 val
)
{
(*(volatile Uint32*)(UTOPIA2_XMTQ_ADDR)) = val;
}
/** ============================================================================
* @n@b UTOPIA2_enableXmt
*
* @b Description
* @n Enables transmitter port
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Modifies the UXEN bit of UCR register
*
* @b Example
* @verbatim
// Configure UTOPIA2
UTOPIA2_configArgs(0x00040004, // ucr
0x00FF00FF // cdr);
.....
.....
//Enables Transmitter port
UTOPIA2_enableXmt();
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_enableXmt (
void
)
{
CSL_FINST(utopia2Regs->UCR, UTOPIA2_UCR_UXEN, TX_PORT_ENABLE);
}
/** ============================================================================
* @n@b UTOPIA2_enableRcv
*
* @b Description
* @n Enables the reciever port
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Modifies the UREN bit of UCR register
*
* @b Example
* @verbatim
// Configure UTOPIA2
UTOPIA2_configArgs(0x00040004, // ucr
0x00FF00FF // cdr);
.....
.....
//Enables Receiver port
UTOPIA2_enableRcv();
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_enableRcv (
void
)
{
CSL_FINST(utopia2Regs->UCR, UTOPIA2_UCR_UREN, RX_PORT_ENABLE);
}
/** ============================================================================
* @n@b UTOPIA2_errDisable
*
* @b Description
* @n Disables the error interrupt event.
*
* @b Arguments
* @verbatim
errNum - Error condition ID
The following are the possible errors from EIPR
- UTOPIA2_ERR_RQS
- UTOPIA2_ERR_RCF
- UTOPIA2_ERR_RCP
- UTOPIA2_ERR_XQS
- UTOPIA2_ERR_XCF
- UTOPIA2_ERR_XCP
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Clears the transmit clock fail bit of EIER register.
*
* @b Example
* @verbatim
// disables the transmit clock fail error bit.
UTOPIA2_errDisable(UTOPIA2_ERR_XCF);
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_errDisable (
Uint32 errNum
)
{
(utopia2Regs->EIER) = ((utopia2Regs->EIER) & (~(1<<errNum)));
}
/** ============================================================================
* @n@b UTOPIA2_errEnable
*
* @b Description
* @n Enables the bit of given error condition ID of EIPR.
*
* @b Arguments
* @verbatim
errNum - Error condition ID
The following are the possible errors from EIPR
- UTOPIA2_ERR_RQS
- UTOPIA2_ERR_RCF
- UTOPIA2_ERR_RCP
- UTOPIA2_ERR_XQS
- UTOPIA2_ERR_XCF
- UTOPIA2_ERR_XCP
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Sets the transmit clock fail bit of EIER register
*
* @b Example
* @verbatim
// Enables the transmit clock fail error bit.
UTOPIA2_errEnable(UTOPIA2_ERR_XCF);
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_errEnable (
Uint32 errNum
)
{
(utopia2Regs->EIER) = ((utopia2Regs->EIER) | (1<<errNum));
}
/** ============================================================================
* @n@b UTOPIA2_errClear
*
* @b Description
* @n Clears the bit of given error condition ID of EIPR.
*
* @b Arguments
* @verbatim
errNum - Error condition ID
The following are the possible errors from EIPR
- UTOPIA2_ERR_RQS
- UTOPIA2_ERR_RCF
- UTOPIA2_ERR_RCP
- UTOPIA2_ERR_XQS
- UTOPIA2_ERR_XCF
- UTOPIA2_ERR_XCP
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Clears the transmit clock fail bit of EIPR register
*
* @b Example
* @verbatim
// clears the transmit clock fail error bit.
UTOPIA2_errClear(UTOPIA2_ERR_XCF);
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_errClear (
Uint32 errNum
)
{
(utopia2Regs->EIPR) = ((utopia2Regs->EIPR) & (~(1<<errNum)));
}
/** ============================================================================
* @n@b UTOPIA2_errTest
*
* @b Description
* @n Checks the error status of given error number.
*
* @b Arguments
* @verbatim
errNum - Error condition ID
The following are the possible errors from EIPR
- UTOPIA2_ERR_RQS
- UTOPIA2_ERR_RCF
- UTOPIA2_ERR_RCP
- UTOPIA2_ERR_XQS
- UTOPIA2_ERR_XCF
- UTOPIA2_ERR_XCP
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
// checking for the transmit clock fail error bit.
Uint32 errDetect;
UTOPIA2_errEnable(UTOPIA2_ERR_RCF);
errNum = UTOPIA2_errTest(UTOPIA2_ERR_RCF)
@endverbatim
* =============================================================================
*/
IDEF
Uint32 UTOPIA2_errTest (
Uint32 errNum
)
{
return ((utopia2Regs->EIPR & (1<<errNum)) ? 1 : 0);
}
/** ============================================================================
* @n@b UTOPIA2_errReset
*
* @b Description
* @n Disables and clears the error interrupt bit associated to the
* given error number.
*
* @b Arguments
* @verbatim
errNum - Error condition ID
The following are the possible errors from EIPR
- UTOPIA2_ERR_RQS
- UTOPIA2_ERR_RCF
- UTOPIA2_ERR_RCP
- UTOPIA2_ERR_XQS
- UTOPIA2_ERR_XCF
- UTOPIA2_ERR_XCP
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Clears the specified bit of EIPR register.
*
* @b Example
* @verbatim
// disables & clears the transmit clock fail error bit.
UTOPIA2_errReset(UTOPIA2_ERR_XCF);
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_errReset (
Uint32 errNum
)
{
UTOPIA2_errDisable(errNum);
UTOPIA2_errClear(errNum);
}
/** ============================================================================
* @n@b UTOPIA2_config
*
* @b Description
* @n Sets up configuration to use the UTOPIA2. The values are set
* to the UTOPIA2 register (UCR, CDR).
*
* @b Arguments
* @verbatim
config - Pointer to an initialized configuration structure
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n UCR and CDR registers of UTOPIA2
*
* @b Example
* @verbatim
UTOPIA2_Config utopConfig = {
0x00000000, // ucr
0x00FF00FF // cdr };
........
........
UTOPIA2_config(&utopConfig);
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_config (
UTOPIA2_Config *config
)
{
Uint32 cs;
register int ucrVal, cdrVal;
CSL_Utopia2Regs *base = (CSL_Utopia2Regs *) CSL_UTOPIA2_0_REGS;
cs = _disable_interrupts();
/* the compiler generates more efficient code if the loads */
/* and stores are grouped together rather than intermixed */
ucrVal = config->ucr;
cdrVal = config->cdr;
base->UCR = UTOPIA2_UCR_DEFAULT;
base->CDR = cdrVal;
base->UCR = ucrVal;
/* Enable interface after everything is set up */
_restore_interrupts(cs);
}
/** ============================================================================
* @n@b UTOPIA2_configArgs
*
* @b Description
* @n Sets up the UTOPIA2 mode by writing the registers which is passed in.
*
* @b Arguments
* @verbatim
ucr - Utopia2 Control Register value
cdr - Clock Detect Register value
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n UCR and CDR registers of UTOPIA2
*
* @b Example
* @verbatim
UTOPIA2_configArgs(0x00000000, // ucr
0x00FF00FF // cdr);
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_configArgs (
Uint32 ucr,
Uint32 cdr
)
{
Uint32 cs;
CSL_Utopia2Regs *base = (CSL_Utopia2Regs *) CSL_UTOPIA2_0_REGS;
cs = _disable_interrupts();
base->UCR = UTOPIA2_UCR_DEFAULT;
base->CDR = cdr;
base->UCR = ucr;
/* Enable interface after everything is set up */
_restore_interrupts(cs);
}
/** ============================================================================
* @n@b UTOPIA2_getConfig
*
* @b Description
* @n Reads the configuration values into the config structure.
*
* @b Arguments
* @verbatim
config - Pointer to a configuration structure.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
UTOPIA2_config utopConfig;
UTOPIA2_getConfig(&utopConfig);
@endverbatim
* =============================================================================
*/
IDEF
void UTOPIA2_getConfig (
UTOPIA2_Config *config
)
{
Uint32 cs;
CSL_Utopia2Regs *base = (CSL_Utopia2Regs *) CSL_UTOPIA2_0_REGS;
register int ucrVal, cdrVal;
cs = _disable_interrupts();
/* the compiler generates more efficient code if the loads */
/* and stores are grouped together rather than intermixed */
ucrVal = base->UCR;
cdrVal = base->CDR;
config->ucr = ucrVal;
config->cdr = cdrVal;
_restore_interrupts(cs);
}
#endif /* _CSL_UTOPIA2_H_ */
/******************************************************************************\
* End of csl_utopia2.h
\******************************************************************************/
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/cfg/csl_cfgInit.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_cfgInit.c
*
* @path $(CSLPATH)\src\cfg
*
* @desc File for functional layer of CSL API CSL_cfgInit()
*
*/
/* =============================================================================
* Revision History
* ===============
* 14-Apr-2005 Brn File Created
* =============================================================================
*/
#include <csl_cfg.h>
/** ============================================================================
* @n@b CSL_cfgInit
*
* @b Description
* @n This is the initialization function for the CFG CSL. The function must be
* called before calling any other API from this CSL. This function does
* not modify any registers or check status. It returns status CSL_SOK.
* It has been kept for future use
*
* @b Arguments
@verbatim
pContext Context information for the instance. Should be NULL
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_cfgInit(NULL);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_cfgInit, ".text:csl_section:cfg");
CSL_Status CSL_cfgInit(
CSL_CfgContext * pContext
)
{
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnClose.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_pwrdwnClose.c
*
* @path $(CSLPATH)\src\pwrdwn
*
* @desc File for functional layer of CSL API CSL_pwrdwnClose ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 16-Jul-2004 <NAME> File Created
* 01-Feb-2006 ds Added error checking
* =============================================================================
*/
#include <csl_pwrdwn.h>
/** ===========================================================================
* @n@b CSL_pwrdwnClose
*
* @b Description
* @n This function closes the specified instance of pwrdwn.
*
* @b Arguments
* @verbatim
hPwrdwn Handle to the PWRDWN instance
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call.
*
* <b> Post Condition </b>
* @n 1. The PWRDWN CSL APIs can not be called until the PWRDWN
* CSL is reopened again using CSL_pwrdwnOpen()
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen(&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments fof the Config structure
...
// Close
CSL_pwrdwnClose(hPwr);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_pwrdwnClose, ".text:csl_section:pwrdwn");
CSL_Status CSL_pwrdwnClose (
CSL_PwrdwnHandle hPwrdwn
)
{ CSL_Status status = CSL_SOK;
/* Indicate in the CSL global data structure that the peripheral
* has been unreserved */
if (hPwrdwn != NULL) {
hPwrdwn->l2pwrdwnRegs = (CSL_L2pwrdwnRegsOvly) NULL;
hPwrdwn->pdcRegs = (CSL_PdcRegsOvly) NULL;
hPwrdwn->instNum = (CSL_InstNum) - 1;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtClose.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* priovided
* ============================================================================
*/
/** ============================================================================
* @file csl_bwmngmtClose.c
*
* @path $(CSLPATH)\src\bwmngmt
*
* @desc File for functional layer of CSL API CSL_bwmngmtClose()
*
*/
/* =============================================================================
* Revision History
* ===============
* 03-Jun-2004 <NAME> File Created
* 11-Apr-2005 Brn Updated the file for doxygen compatibiliy
* 31-Jan-2006 ds Added error checking
* =============================================================================
*/
#include <csl_bwmngmt.h>
/** ============================================================================
* @n@b CSL_bwmngmtClose
*
* @b Description
* @n This function closes the specified instance of BWMNGMT.
*
* @b Arguments
* @verbatim
hBwmngmt Handle to the BWMNGMT instance
@endverbatim
*
* <b> Return Value </b> CSL_Status
* CSL_SOK - Close successful
* CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n Both @a CSL_bwmngmtInit() and @a CSL_bwmngmtOpen() must be called
* successfully in that order before @a CSL_bwmngmtClose() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_BwmngmtHandle hBwmngmt;
...
CSL_bwmngmtClose(hBwmngmt);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_bwmngmtClose, ".text:csl_section:bwmngmt");
CSL_Status CSL_bwmngmtClose (
CSL_BwmngmtHandle hBwmngmt
)
{
/* indicate in the CSL global data structure that the peripheral
* has been unreserved
*/
CSL_Status status = CSL_SOK;
if (hBwmngmt != NULL) {
hBwmngmt->regs = (CSL_BwmngmtRegsOvly) NULL;
hBwmngmt->bwmngmtNum = (CSL_InstNum) - 1;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_mdio.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_mdio.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for MDIO
*/
#ifndef _CSLR_MDIO_H_
#define _CSLR_MDIO_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 VERSION;
volatile Uint32 CONTROL;
volatile Uint32 ALIVE;
volatile Uint32 LINK;
volatile Uint32 LINKINTRAW;
volatile Uint32 LINKINTMASKED;
volatile Uint8 RSVD0[8];
volatile Uint32 USERINTRAW;
volatile Uint32 USERINTMASKED;
volatile Uint32 USERINTMASKSET;
volatile Uint32 USERINTMASKCLEAR;
volatile Uint8 RSVD1[80];
volatile Uint32 USERACCESS0;
volatile Uint32 USERPHYSEL0;
volatile Uint32 USERACCESS1;
volatile Uint32 USERPHYSEL1;
} CSL_MdioRegs;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* VERSION */
#define CSL_MDIO_VERSION_MODID_MASK (0xFFFF0000u)
#define CSL_MDIO_VERSION_MODID_SHIFT (0x00000010u)
#define CSL_MDIO_VERSION_MODID_RESETVAL (0x00000007u)
#define CSL_MDIO_VERSION_REVMAJ_MASK (0x0000FF00u)
#define CSL_MDIO_VERSION_REVMAJ_SHIFT (0x00000008u)
#define CSL_MDIO_VERSION_REVMAJ_RESETVAL (0x00000001u)
#define CSL_MDIO_VERSION_REVMIN_MASK (0x000000FFu)
#define CSL_MDIO_VERSION_REVMIN_SHIFT (0x00000000u)
#define CSL_MDIO_VERSION_REVMIN_RESETVAL (0x00000003u)
#define CSL_MDIO_VERSION_RESETVAL (0x00070103u)
/* CONTROL */
#define CSL_MDIO_CONTROL_IDLE_MASK (0x80000000u)
#define CSL_MDIO_CONTROL_IDLE_SHIFT (0x0000001Fu)
#define CSL_MDIO_CONTROL_IDLE_RESETVAL (0x00000001u)
/*----IDLE Tokens----*/
#define CSL_MDIO_CONTROL_IDLE_NO (0x00000000u)
#define CSL_MDIO_CONTROL_IDLE_YES (0x00000001u)
#define CSL_MDIO_CONTROL_ENABLE_MASK (0x40000000u)
#define CSL_MDIO_CONTROL_ENABLE_SHIFT (0x0000001Eu)
#define CSL_MDIO_CONTROL_ENABLE_RESETVAL (0x00000000u)
/*----ENABLE Tokens----*/
#define CSL_MDIO_CONTROL_ENABLE_NO (0x00000000u)
#define CSL_MDIO_CONTROL_ENABLE_YES (0x00000001u)
#define CSL_MDIO_CONTROL_HIGHEST_USER_CHANNEL_MASK (0x1F000000u)
#define CSL_MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT (0x00000018u)
#define CSL_MDIO_CONTROL_HIGHEST_USER_CHANNEL_RESETVAL (0x00000001u)
#define CSL_MDIO_CONTROL_PREAMBLE_MASK (0x00100000u)
#define CSL_MDIO_CONTROL_PREAMBLE_SHIFT (0x00000014u)
#define CSL_MDIO_CONTROL_PREAMBLE_RESETVAL (0x00000000u)
/*----PREAMBLE Tokens----*/
#define CSL_MDIO_CONTROL_PREAMBLE_ENABLED (0x00000000u)
#define CSL_MDIO_CONTROL_PREAMBLE_DISABLED (0x00000001u)
#define CSL_MDIO_CONTROL_FAULT_MASK (0x00080000u)
#define CSL_MDIO_CONTROL_FAULT_SHIFT (0x00000013u)
#define CSL_MDIO_CONTROL_FAULT_RESETVAL (0x00000000u)
/*----FAULT Tokens----*/
#define CSL_MDIO_CONTROL_FAULT_NO (0x00000000u)
#define CSL_MDIO_CONTROL_FAULT_YES (0x00000001u)
#define CSL_MDIO_CONTROL_FAULTENB_MASK (0x00040000u)
#define CSL_MDIO_CONTROL_FAULTENB_SHIFT (0x00000012u)
#define CSL_MDIO_CONTROL_FAULTENB_RESETVAL (0x00000000u)
/*----FAULTENB Tokens----*/
#define CSL_MDIO_CONTROL_FAULTENB_NO (0x00000000u)
#define CSL_MDIO_CONTROL_FAULTENB_YES (0x00000001u)
#define CSL_MDIO_CONTROL_CLKDIV_MASK (0x0000FFFFu)
#define CSL_MDIO_CONTROL_CLKDIV_SHIFT (0x00000000u)
#define CSL_MDIO_CONTROL_CLKDIV_RESETVAL (0x000000FFu)
#define CSL_MDIO_CONTROL_RESETVAL (0x810000FFu)
/* ALIVE */
#define CSL_MDIO_ALIVE_ALIVE_MASK (0xFFFFFFFFu)
#define CSL_MDIO_ALIVE_ALIVE_SHIFT (0x00000000u)
#define CSL_MDIO_ALIVE_ALIVE_RESETVAL (0x00000000u)
/*----ALIVE Tokens----*/
#define CSL_MDIO_ALIVE_ALIVE_DEAD (0x00000000u)
#define CSL_MDIO_ALIVE_ALIVE_ALIVE (0x00000001u)
#define CSL_MDIO_ALIVE_RESETVAL (0x00000000u)
/* LINK */
#define CSL_MDIO_LINK_LINK_MASK (0xFFFFFFFFu)
#define CSL_MDIO_LINK_LINK_SHIFT (0x00000000u)
#define CSL_MDIO_LINK_LINK_RESETVAL (0x00000000u)
/*----LINK Tokens----*/
#define CSL_MDIO_LINK_LINK_NOLINK (0x00000000u)
#define CSL_MDIO_LINK_LINK_LINK (0x00000001u)
#define CSL_MDIO_LINK_RESETVAL (0x00000000u)
/* LINKINTRAW */
#define CSL_MDIO_LINKINTRAW_LINKINTRAW_MASK (0x00000003u)
#define CSL_MDIO_LINKINTRAW_LINKINTRAW_SHIFT (0x00000000u)
#define CSL_MDIO_LINKINTRAW_LINKINTRAW_RESETVAL (0x00000000u)
#define CSL_MDIO_LINKINTRAW_RESETVAL (0x00000000u)
/* LINKINTMASKED */
#define CSL_MDIO_LINKINTMASKED_LINKINTMASKED_MASK (0x00000003u)
#define CSL_MDIO_LINKINTMASKED_LINKINTMASKED_SHIFT (0x00000000u)
#define CSL_MDIO_LINKINTMASKED_LINKINTMASKED_RESETVAL (0x00000000u)
#define CSL_MDIO_LINKINTMASKED_RESETVAL (0x00000000u)
/* USERINTRAW */
#define CSL_MDIO_USERINTRAW_USERINTRAW_MASK (0x00000003u)
#define CSL_MDIO_USERINTRAW_USERINTRAW_SHIFT (0x00000000u)
#define CSL_MDIO_USERINTRAW_USERINTRAW_RESETVAL (0x00000000u)
#define CSL_MDIO_USERINTRAW_RESETVAL (0x00000000u)
/* USERINTMASKED */
#define CSL_MDIO_USERINTMASKED_USERINTMASKED_MASK (0x00000003u)
#define CSL_MDIO_USERINTMASKED_USERINTMASKED_SHIFT (0x00000000u)
#define CSL_MDIO_USERINTMASKED_USERINTMASKED_RESETVAL (0x00000000u)
#define CSL_MDIO_USERINTMASKED_RESETVAL (0x00000000u)
/* USERINTMASKSET */
#define CSL_MDIO_USERINTMASKSET_USERINTMASKSET_MASK (0x00000003u)
#define CSL_MDIO_USERINTMASKSET_USERINTMASKSET_SHIFT (0x00000000u)
#define CSL_MDIO_USERINTMASKSET_USERINTMASKSET_RESETVAL (0x00000000u)
#define CSL_MDIO_USERINTMASKSET_RESETVAL (0x00000000u)
/* USERINTMASKCLEAR */
#define CSL_MDIO_USERINTMASKCLEAR_USERINTMASKCLEAR_MASK (0x00000003u)
#define CSL_MDIO_USERINTMASKCLEAR_USERINTMASKCLEAR_SHIFT (0x00000000u)
#define CSL_MDIO_USERINTMASKCLEAR_USERINTMASKCLEAR_RESETVAL (0x00000000u)
#define CSL_MDIO_USERINTMASKCLEAR_RESETVAL (0x00000000u)
/* USERACCESS0 */
#define CSL_MDIO_USERACCESS0_GO_MASK (0x80000000u)
#define CSL_MDIO_USERACCESS0_GO_SHIFT (0x0000001Fu)
#define CSL_MDIO_USERACCESS0_GO_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS0_WRITE_MASK (0x40000000u)
#define CSL_MDIO_USERACCESS0_WRITE_SHIFT (0x0000001Eu)
#define CSL_MDIO_USERACCESS0_WRITE_RESETVAL (0x00000000u)
/*----WRITE Tokens----*/
#define CSL_MDIO_USERACCESS0_WRITE_READ (0x00000000u)
#define CSL_MDIO_USERACCESS0_WRITE_WRITE (0x00000001u)
#define CSL_MDIO_USERACCESS0_ACK_MASK (0x20000000u)
#define CSL_MDIO_USERACCESS0_ACK_SHIFT (0x0000001Du)
#define CSL_MDIO_USERACCESS0_ACK_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS0_REGADR_MASK (0x03E00000u)
#define CSL_MDIO_USERACCESS0_REGADR_SHIFT (0x00000015u)
#define CSL_MDIO_USERACCESS0_REGADR_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS0_PHYADR_MASK (0x001F0000u)
#define CSL_MDIO_USERACCESS0_PHYADR_SHIFT (0x00000010u)
#define CSL_MDIO_USERACCESS0_PHYADR_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS0_DATA_MASK (0x0000FFFFu)
#define CSL_MDIO_USERACCESS0_DATA_SHIFT (0x00000000u)
#define CSL_MDIO_USERACCESS0_DATA_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS0_RESETVAL (0x00000000u)
/* USERPHYSEL0 */
#define CSL_MDIO_USERPHYSEL0_LINKSEL_MASK (0x00000080u)
#define CSL_MDIO_USERPHYSEL0_LINKSEL_SHIFT (0x00000007u)
#define CSL_MDIO_USERPHYSEL0_LINKSEL_RESETVAL (0x00000000u)
/*----LINKSEL Tokens----*/
#define CSL_MDIO_USERPHYSEL0_LINKSEL_MDIO (0x00000000u)
#define CSL_MDIO_USERPHYSEL0_LINKINTENB_MASK (0x00000040u)
#define CSL_MDIO_USERPHYSEL0_LINKINTENB_SHIFT (0x00000006u)
#define CSL_MDIO_USERPHYSEL0_LINKINTENB_RESETVAL (0x00000000u)
/*----LINKINTENB Tokens----*/
#define CSL_MDIO_USERPHYSEL0_LINKINTENB_DISABLE (0x00000000u)
#define CSL_MDIO_USERPHYSEL0_LINKINTENB_ENABLE (0x00000001u)
#define CSL_MDIO_USERPHYSEL0_PHYADRMON_MASK (0x0000001Fu)
#define CSL_MDIO_USERPHYSEL0_PHYADRMON_SHIFT (0x00000000u)
#define CSL_MDIO_USERPHYSEL0_PHYADRMON_RESETVAL (0x00000000u)
#define CSL_MDIO_USERPHYSEL0_RESETVAL (0x00000000u)
/* USERACCESS1 */
#define CSL_MDIO_USERACCESS1_GO_MASK (0x80000000u)
#define CSL_MDIO_USERACCESS1_GO_SHIFT (0x0000001Fu)
#define CSL_MDIO_USERACCESS1_GO_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS1_WRITE_MASK (0x40000000u)
#define CSL_MDIO_USERACCESS1_WRITE_SHIFT (0x0000001Eu)
#define CSL_MDIO_USERACCESS1_WRITE_RESETVAL (0x00000000u)
/*----WRITE Tokens----*/
#define CSL_MDIO_USERACCESS1_WRITE_READ (0x00000000u)
#define CSL_MDIO_USERACCESS1_WRITE_WRITE (0x00000001u)
#define CSL_MDIO_USERACCESS1_ACK_MASK (0x20000000u)
#define CSL_MDIO_USERACCESS1_ACK_SHIFT (0x0000001Du)
#define CSL_MDIO_USERACCESS1_ACK_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS1_REGADR_MASK (0x03E00000u)
#define CSL_MDIO_USERACCESS1_REGADR_SHIFT (0x00000015u)
#define CSL_MDIO_USERACCESS1_REGADR_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS1_PHYADR_MASK (0x001F0000u)
#define CSL_MDIO_USERACCESS1_PHYADR_SHIFT (0x00000010u)
#define CSL_MDIO_USERACCESS1_PHYADR_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS1_DATA_MASK (0x0000FFFFu)
#define CSL_MDIO_USERACCESS1_DATA_SHIFT (0x00000000u)
#define CSL_MDIO_USERACCESS1_DATA_RESETVAL (0x00000000u)
#define CSL_MDIO_USERACCESS1_RESETVAL (0x00000000u)
/* USERPHYSEL1 */
#define CSL_MDIO_USERPHYSEL1_LINKSEL_MASK (0x00000080u)
#define CSL_MDIO_USERPHYSEL1_LINKSEL_SHIFT (0x00000007u)
#define CSL_MDIO_USERPHYSEL1_LINKSEL_RESETVAL (0x00000000u)
/*----LINKSEL Tokens----*/
#define CSL_MDIO_USERPHYSEL1_LINKSEL_MDIO (0x00000000u)
#define CSL_MDIO_USERPHYSEL1_LINKINTENB_MASK (0x00000040u)
#define CSL_MDIO_USERPHYSEL1_LINKINTENB_SHIFT (0x00000006u)
#define CSL_MDIO_USERPHYSEL1_LINKINTENB_RESETVAL (0x00000000u)
/*----LINKINTENB Tokens----*/
#define CSL_MDIO_USERPHYSEL1_LINKINTENB_DISABLE (0x00000000u)
#define CSL_MDIO_USERPHYSEL1_LINKINTENB_ENABLE (0x00000001u)
#define CSL_MDIO_USERPHYSEL1_PHYADRMON_MASK (0x0000001Fu)
#define CSL_MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0x00000000u)
#define CSL_MDIO_USERPHYSEL1_PHYADRMON_RESETVAL (0x00000000u)
#define CSL_MDIO_USERPHYSEL1_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_chip.h | <filename>DSP/TI-Header/csl_c6455_src/inc/cslr_chip.h
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_chip.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for CHIP
*/
#ifndef _CSLR_CHIP_H_
#define _CSLR_CHIP_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* AMR */
#define CSL_CHIP_AMR_BK1_MASK (0x03E00000u)
#define CSL_CHIP_AMR_BK1_SHIFT (0x00000015u)
#define CSL_CHIP_AMR_BK1_RESETVAL (0x00000000u)
#define CSL_CHIP_AMR_BK0_MASK (0x001F0000u)
#define CSL_CHIP_AMR_BK0_SHIFT (0x00000010u)
#define CSL_CHIP_AMR_BK0_RESETVAL (0x00000000u)
#define CSL_CHIP_AMR_B7MODE_MASK (0x0000C000u)
#define CSL_CHIP_AMR_B7MODE_SHIFT (0x0000000Eu)
#define CSL_CHIP_AMR_B7MODE_RESETVAL (0x00000000u)
/*----B7MODE Tokens----*/
#define CSL_CHIP_AMR_B7MODE_LINEAR (0x00000000u)
#define CSL_CHIP_AMR_B7MODE_CIRCULARBK0 (0x00000001u)
#define CSL_CHIP_AMR_B7MODE_CIRCULARBK1 (0x00000002u)
#define CSL_CHIP_AMR_B7MODE_RESV (0x00000003u)
#define CSL_CHIP_AMR_B6MODE_MASK (0x00003000u)
#define CSL_CHIP_AMR_B6MODE_SHIFT (0x0000000Cu)
#define CSL_CHIP_AMR_B6MODE_RESETVAL (0x00000000u)
/*----B6MODE Tokens----*/
#define CSL_CHIP_AMR_B6MODE_LINEAR (0x00000000u)
#define CSL_CHIP_AMR_B6MODE_CIRCULARBK0 (0x00000001u)
#define CSL_CHIP_AMR_B6MODE_CIRCULARBK1 (0x00000002u)
#define CSL_CHIP_AMR_B6MODE_RESV (0x00000003u)
#define CSL_CHIP_AMR_B5MODE_MASK (0x00000C00u)
#define CSL_CHIP_AMR_B5MODE_SHIFT (0x0000000Au)
#define CSL_CHIP_AMR_B5MODE_RESETVAL (0x00000000u)
/*----B5MODE Tokens----*/
#define CSL_CHIP_AMR_B5MODE_LINEAR (0x00000000u)
#define CSL_CHIP_AMR_B5MODE_CIRCULARBK1 (0x00000001u)
#define CSL_CHIP_AMR_B5MODE_CIRCULARBK2 (0x00000002u)
#define CSL_CHIP_AMR_B5MODE_RESV (0x00000003u)
#define CSL_CHIP_AMR_B4MODE_MASK (0x00000300u)
#define CSL_CHIP_AMR_B4MODE_SHIFT (0x00000008u)
#define CSL_CHIP_AMR_B4MODE_RESETVAL (0x00000000u)
/*----B4MODE Tokens----*/
#define CSL_CHIP_AMR_B4MODE_LINEAR (0x00000000u)
#define CSL_CHIP_AMR_B4MODE_CIRCULARBK1 (0x00000001u)
#define CSL_CHIP_AMR_B4MODE_CIRCULARBK2 (0x00000002u)
#define CSL_CHIP_AMR_B4MODE_RESV (0x00000003u)
#define CSL_CHIP_AMR_A7MODE_MASK (0x000000C0u)
#define CSL_CHIP_AMR_A7MODE_SHIFT (0x00000006u)
#define CSL_CHIP_AMR_A7MODE_RESETVAL (0x00000000u)
/*----A7MODE Tokens----*/
#define CSL_CHIP_AMR_A7MODE_LINEAR (0x00000000u)
#define CSL_CHIP_AMR_A7MODE_CIRCULARBK1 (0x00000001u)
#define CSL_CHIP_AMR_A7MODE_CIRCULARBK2 (0x00000002u)
#define CSL_CHIP_AMR_A7MODE_RESV (0x00000003u)
#define CSL_CHIP_AMR_A6MODE_MASK (0x00000030u)
#define CSL_CHIP_AMR_A6MODE_SHIFT (0x00000004u)
#define CSL_CHIP_AMR_A6MODE_RESETVAL (0x00000000u)
/*----A6MODE Tokens----*/
#define CSL_CHIP_AMR_A6MODE_LINEAR (0x00000000u)
#define CSL_CHIP_AMR_A6MODE_CIRCULARBK2 (0x00000001u)
#define CSL_CHIP_AMR_A6MODE_CIRCULARBK3 (0x00000002u)
#define CSL_CHIP_AMR_A6MODE_RESV (0x00000003u)
#define CSL_CHIP_AMR_A5MODE_MASK (0x0000000Cu)
#define CSL_CHIP_AMR_A5MODE_SHIFT (0x00000002u)
#define CSL_CHIP_AMR_A5MODE_RESETVAL (0x00000000u)
/*----A5MODE Tokens----*/
#define CSL_CHIP_AMR_A5MODE_LINEAR (0x00000000u)
#define CSL_CHIP_AMR_A5MODE_CIRCULARBK3 (0x00000001u)
#define CSL_CHIP_AMR_A5MODE_CIRCULARBK4 (0x00000002u)
#define CSL_CHIP_AMR_A5MODE_RESV (0x00000003u)
#define CSL_CHIP_AMR_A4MODE_MASK (0x00000003u)
#define CSL_CHIP_AMR_A4MODE_SHIFT (0x00000000u)
#define CSL_CHIP_AMR_A4MODE_RESETVAL (0x00000000u)
/*----A4MODE Tokens----*/
#define CSL_CHIP_AMR_A4MODE_LINEAR (0x00000000u)
#define CSL_CHIP_AMR_A4MODE_CIRCULARBK4 (0x00000001u)
#define CSL_CHIP_AMR_A4MODE_CIRCULARBK5 (0x00000002u)
#define CSL_CHIP_AMR_A4MODE_RESV (0x00000003u)
#define CSL_CHIP_AMR_RESETVAL (0x00000000u)
/* CSR */
#define CSL_CHIP_CSR_CPU_ID_MASK (0xFF000000u)
#define CSL_CHIP_CSR_CPU_ID_SHIFT (0x00000018u)
#define CSL_CHIP_CSR_CPU_ID_RESETVAL (0x00000000u)
#define CSL_CHIP_CSR_REV_ID_MASK (0x00FF0000u)
#define CSL_CHIP_CSR_REV_ID_SHIFT (0x00000010u)
#define CSL_CHIP_CSR_REV_ID_RESETVAL (0x00000801u)
#define CSL_CHIP_CSR_PWRD_MASK (0x0000FC00u)
#define CSL_CHIP_CSR_PWRD_SHIFT (0x0000000Au)
#define CSL_CHIP_CSR_PWRD_RESETVAL (0x00000000u)
#define CSL_CHIP_CSR_SAT_MASK (0x00000200u)
#define CSL_CHIP_CSR_SAT_SHIFT (0x00000009u)
#define CSL_CHIP_CSR_SAT_RESETVAL (0x00000000u)
/*----SAT Tokens----*/
#define CSL_CHIP_CSR_SAT_SATURATE (0x00000001u)
#define CSL_CHIP_CSR_SAT_NONSATURATE (0x00000000u)
#define CSL_CHIP_CSR_EN_MASK (0x00000100u)
#define CSL_CHIP_CSR_EN_SHIFT (0x00000008u)
#define CSL_CHIP_CSR_EN_RESETVAL (0x00000000u)
/*----EN Tokens----*/
#define CSL_CHIP_CSR_EN_BIG (0x00000000u)
#define CSL_CHIP_CSR_EN_LITTLE (0x00000001u)
#define CSL_CHIP_CSR_PCC_MASK (0x000000E0u)
#define CSL_CHIP_CSR_PCC_SHIFT (0x00000005u)
#define CSL_CHIP_CSR_PCC_RESETVAL (0x00000000u)
#define CSL_CHIP_CSR_DCC_MASK (0x0000001Cu)
#define CSL_CHIP_CSR_DCC_SHIFT (0x00000002u)
#define CSL_CHIP_CSR_DCC_RESETVAL (0x00000000u)
#define CSL_CHIP_CSR_PGIE_MASK (0x00000002u)
#define CSL_CHIP_CSR_PGIE_SHIFT (0x00000001u)
#define CSL_CHIP_CSR_PGIE_RESETVAL (0x00000000u)
#define CSL_CHIP_CSR_GIE_MASK (0x00000001u)
#define CSL_CHIP_CSR_GIE_SHIFT (0x00000000u)
#define CSL_CHIP_CSR_GIE_RESETVAL (0x00000000u)
/*----GIE Tokens----*/
#define CSL_CHIP_CSR_GIE_ENABLE (0x00000001u)
#define CSL_CHIP_CSR_GIE_DISABLE (0x00000000u)
#define CSL_CHIP_CSR_RESETVAL (0x08010000u)
/* IFR */
#define CSL_CHIP_IFR_IF15_MASK (0x00008000u)
#define CSL_CHIP_IFR_IF15_SHIFT (0x0000000Fu)
#define CSL_CHIP_IFR_IF15_RESETVAL (0x00000000u)
/*----IF15 Tokens----*/
#define CSL_CHIP_IFR_IF15_ENABLE (0x00000001u)
#define CSL_CHIP_IFR_IF14_MASK (0x00004000u)
#define CSL_CHIP_IFR_IF14_SHIFT (0x0000000Eu)
#define CSL_CHIP_IFR_IF14_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF13_MASK (0x00002000u)
#define CSL_CHIP_IFR_IF13_SHIFT (0x0000000Du)
#define CSL_CHIP_IFR_IF13_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF12_MASK (0x00001000u)
#define CSL_CHIP_IFR_IF12_SHIFT (0x0000000Cu)
#define CSL_CHIP_IFR_IF12_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF11_MASK (0x00000800u)
#define CSL_CHIP_IFR_IF11_SHIFT (0x0000000Bu)
#define CSL_CHIP_IFR_IF11_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF10_MASK (0x00000400u)
#define CSL_CHIP_IFR_IF10_SHIFT (0x0000000Au)
#define CSL_CHIP_IFR_IF10_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF9_MASK (0x00000200u)
#define CSL_CHIP_IFR_IF9_SHIFT (0x00000009u)
#define CSL_CHIP_IFR_IF9_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF8_MASK (0x00000100u)
#define CSL_CHIP_IFR_IF8_SHIFT (0x00000008u)
#define CSL_CHIP_IFR_IF8_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF7_MASK (0x00000080u)
#define CSL_CHIP_IFR_IF7_SHIFT (0x00000007u)
#define CSL_CHIP_IFR_IF7_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF6_MASK (0x00000040u)
#define CSL_CHIP_IFR_IF6_SHIFT (0x00000006u)
#define CSL_CHIP_IFR_IF6_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF5_MASK (0x00000020u)
#define CSL_CHIP_IFR_IF5_SHIFT (0x00000005u)
#define CSL_CHIP_IFR_IF5_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_IF4_MASK (0x00000010u)
#define CSL_CHIP_IFR_IF4_SHIFT (0x00000004u)
#define CSL_CHIP_IFR_IF4_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_NMIF_MASK (0x00000002u)
#define CSL_CHIP_IFR_NMIF_SHIFT (0x00000001u)
#define CSL_CHIP_IFR_NMIF_RESETVAL (0x00000000u)
#define CSL_CHIP_IFR_RESETVAL (0x00000000u)
/* ISR */
#define CSL_CHIP_ISR_IS15_MASK (0x00008000u)
#define CSL_CHIP_ISR_IS15_SHIFT (0x0000000Fu)
#define CSL_CHIP_ISR_IS15_RESETVAL (0x00000000u)
/*----IS15 Tokens----*/
#define CSL_CHIP_ISR_IS15_SET (0x00000001u)
#define CSL_CHIP_ISR_IS14_MASK (0x00004000u)
#define CSL_CHIP_ISR_IS14_SHIFT (0x0000000Eu)
#define CSL_CHIP_ISR_IS14_RESETVAL (0x00000000u)
/*----IS14 Tokens----*/
#define CSL_CHIP_ISR_IS14_SET (0x00000001u)
#define CSL_CHIP_ISR_IS13_MASK (0x00002000u)
#define CSL_CHIP_ISR_IS13_SHIFT (0x0000000Du)
#define CSL_CHIP_ISR_IS13_RESETVAL (0x00000000u)
/*----IS13 Tokens----*/
#define CSL_CHIP_ISR_IS13_SET (0x00000001u)
#define CSL_CHIP_ISR_IS12_MASK (0x00001000u)
#define CSL_CHIP_ISR_IS12_SHIFT (0x0000000Cu)
#define CSL_CHIP_ISR_IS12_RESETVAL (0x00000000u)
/*----IS12 Tokens----*/
#define CSL_CHIP_ISR_IS12_SET (0x00000001u)
#define CSL_CHIP_ISR_IS11_MASK (0x00000800u)
#define CSL_CHIP_ISR_IS11_SHIFT (0x0000000Bu)
#define CSL_CHIP_ISR_IS11_RESETVAL (0x00000000u)
/*----IS11 Tokens----*/
#define CSL_CHIP_ISR_IS11_SET (0x00000001u)
#define CSL_CHIP_ISR_IS10_MASK (0x00000400u)
#define CSL_CHIP_ISR_IS10_SHIFT (0x0000000Au)
#define CSL_CHIP_ISR_IS10_RESETVAL (0x00000000u)
/*----IS10 Tokens----*/
#define CSL_CHIP_ISR_IS10_SET (0x00000001u)
#define CSL_CHIP_ISR_IS9_MASK (0x00000200u)
#define CSL_CHIP_ISR_IS9_SHIFT (0x00000009u)
#define CSL_CHIP_ISR_IS9_RESETVAL (0x00000000u)
/*----IS9 Tokens----*/
#define CSL_CHIP_ISR_IS9_SET (0x00000001u)
#define CSL_CHIP_ISR_IS8_MASK (0x00000100u)
#define CSL_CHIP_ISR_IS8_SHIFT (0x00000008u)
#define CSL_CHIP_ISR_IS8_RESETVAL (0x00000000u)
/*----IS8 Tokens----*/
#define CSL_CHIP_ISR_IS8_SET (0x00000001u)
#define CSL_CHIP_ISR_IS7_MASK (0x00000080u)
#define CSL_CHIP_ISR_IS7_SHIFT (0x00000007u)
#define CSL_CHIP_ISR_IS7_RESETVAL (0x00000000u)
/*----IS7 Tokens----*/
#define CSL_CHIP_ISR_IS7_SET (0x00000001u)
#define CSL_CHIP_ISR_IS6_MASK (0x00000040u)
#define CSL_CHIP_ISR_IS6_SHIFT (0x00000006u)
#define CSL_CHIP_ISR_IS6_RESETVAL (0x00000000u)
/*----IS6 Tokens----*/
#define CSL_CHIP_ISR_IS6_SET (0x00000001u)
#define CSL_CHIP_ISR_IS5_MASK (0x00000020u)
#define CSL_CHIP_ISR_IS5_SHIFT (0x00000005u)
#define CSL_CHIP_ISR_IS5_RESETVAL (0x00000000u)
/*----IS5 Tokens----*/
#define CSL_CHIP_ISR_IS5_SET (0x00000001u)
#define CSL_CHIP_ISR_IS4_MASK (0x00000010u)
#define CSL_CHIP_ISR_IS4_SHIFT (0x00000004u)
#define CSL_CHIP_ISR_IS4_RESETVAL (0x00000000u)
/*----IS4 Tokens----*/
#define CSL_CHIP_ISR_IS4_SET (0x00000001u)
#define CSL_CHIP_ISR_RESETVAL (0x00000000u)
/* ICR */
#define CSL_CHIP_ICR_IC15_MASK (0x00008000u)
#define CSL_CHIP_ICR_IC15_SHIFT (0x0000000Fu)
#define CSL_CHIP_ICR_IC15_RESETVAL (0x00000000u)
/*----IC15 Tokens----*/
#define CSL_CHIP_ICR_IC15_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC14_MASK (0x00004000u)
#define CSL_CHIP_ICR_IC14_SHIFT (0x0000000Eu)
#define CSL_CHIP_ICR_IC14_RESETVAL (0x00000000u)
/*----IC14 Tokens----*/
#define CSL_CHIP_ICR_IC14_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC13_MASK (0x00002000u)
#define CSL_CHIP_ICR_IC13_SHIFT (0x0000000Du)
#define CSL_CHIP_ICR_IC13_RESETVAL (0x00000000u)
/*----IC13 Tokens----*/
#define CSL_CHIP_ICR_IC13_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC12_MASK (0x00001000u)
#define CSL_CHIP_ICR_IC12_SHIFT (0x0000000Cu)
#define CSL_CHIP_ICR_IC12_RESETVAL (0x00000000u)
/*----IC12 Tokens----*/
#define CSL_CHIP_ICR_IC12_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC11_MASK (0x00000800u)
#define CSL_CHIP_ICR_IC11_SHIFT (0x0000000Bu)
#define CSL_CHIP_ICR_IC11_RESETVAL (0x00000000u)
/*----IC11 Tokens----*/
#define CSL_CHIP_ICR_IC11_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC10_MASK (0x00000400u)
#define CSL_CHIP_ICR_IC10_SHIFT (0x0000000Au)
#define CSL_CHIP_ICR_IC10_RESETVAL (0x00000000u)
/*----IC10 Tokens----*/
#define CSL_CHIP_ICR_IC10_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC9_MASK (0x00000200u)
#define CSL_CHIP_ICR_IC9_SHIFT (0x00000009u)
#define CSL_CHIP_ICR_IC9_RESETVAL (0x00000000u)
/*----IC9 Tokens----*/
#define CSL_CHIP_ICR_IC9_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC8_MASK (0x00000100u)
#define CSL_CHIP_ICR_IC8_SHIFT (0x00000008u)
#define CSL_CHIP_ICR_IC8_RESETVAL (0x00000000u)
/*----IC8 Tokens----*/
#define CSL_CHIP_ICR_IC8_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC7_MASK (0x00000080u)
#define CSL_CHIP_ICR_IC7_SHIFT (0x00000007u)
#define CSL_CHIP_ICR_IC7_RESETVAL (0x00000000u)
/*----IC7 Tokens----*/
#define CSL_CHIP_ICR_IC7_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC6_MASK (0x00000040u)
#define CSL_CHIP_ICR_IC6_SHIFT (0x00000006u)
#define CSL_CHIP_ICR_IC6_RESETVAL (0x00000000u)
/*----IC6 Tokens----*/
#define CSL_CHIP_ICR_IC6_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC5_MASK (0x00000020u)
#define CSL_CHIP_ICR_IC5_SHIFT (0x00000005u)
#define CSL_CHIP_ICR_IC5_RESETVAL (0x00000000u)
/*----IC5 Tokens----*/
#define CSL_CHIP_ICR_IC5_CLR (0x00000001u)
#define CSL_CHIP_ICR_IC4_MASK (0x00000010u)
#define CSL_CHIP_ICR_IC4_SHIFT (0x00000004u)
#define CSL_CHIP_ICR_IC4_RESETVAL (0x00000000u)
/*----IC4 Tokens----*/
#define CSL_CHIP_ICR_IC4_CLR (0x00000001u)
#define CSL_CHIP_ICR_RESETVAL (0x00000000u)
/* IER */
#define CSL_CHIP_IER_IE15_MASK (0x00008000u)
#define CSL_CHIP_IER_IE15_SHIFT (0x0000000Fu)
#define CSL_CHIP_IER_IE15_RESETVAL (0x00000000u)
/*----IE15 Tokens----*/
#define CSL_CHIP_IER_IE15_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE15_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE14_MASK (0x00004000u)
#define CSL_CHIP_IER_IE14_SHIFT (0x0000000Eu)
#define CSL_CHIP_IER_IE14_RESETVAL (0x00000000u)
/*----IE14 Tokens----*/
#define CSL_CHIP_IER_IE14_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE14_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE13_MASK (0x00002000u)
#define CSL_CHIP_IER_IE13_SHIFT (0x0000000Du)
#define CSL_CHIP_IER_IE13_RESETVAL (0x00000000u)
/*----IE13 Tokens----*/
#define CSL_CHIP_IER_IE13_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE13_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE12_MASK (0x00001000u)
#define CSL_CHIP_IER_IE12_SHIFT (0x0000000Cu)
#define CSL_CHIP_IER_IE12_RESETVAL (0x00000000u)
/*----IE12 Tokens----*/
#define CSL_CHIP_IER_IE12_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE12_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE11_MASK (0x00000800u)
#define CSL_CHIP_IER_IE11_SHIFT (0x0000000Bu)
#define CSL_CHIP_IER_IE11_RESETVAL (0x00000000u)
/*----IE11 Tokens----*/
#define CSL_CHIP_IER_IE11_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE11_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE10_MASK (0x00000400u)
#define CSL_CHIP_IER_IE10_SHIFT (0x0000000Au)
#define CSL_CHIP_IER_IE10_RESETVAL (0x00000000u)
/*----IE10 Tokens----*/
#define CSL_CHIP_IER_IE10_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE10_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE09_MASK (0x00000200u)
#define CSL_CHIP_IER_IE09_SHIFT (0x00000009u)
#define CSL_CHIP_IER_IE09_RESETVAL (0x00000000u)
/*----IE09 Tokens----*/
#define CSL_CHIP_IER_IE09_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE09_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE08_MASK (0x00000100u)
#define CSL_CHIP_IER_IE08_SHIFT (0x00000008u)
#define CSL_CHIP_IER_IE08_RESETVAL (0x00000000u)
/*----IE08 Tokens----*/
#define CSL_CHIP_IER_IE08_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE08_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE07_MASK (0x00000080u)
#define CSL_CHIP_IER_IE07_SHIFT (0x00000007u)
#define CSL_CHIP_IER_IE07_RESETVAL (0x00000000u)
/*----IE07 Tokens----*/
#define CSL_CHIP_IER_IE07_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE07_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE06_MASK (0x00000040u)
#define CSL_CHIP_IER_IE06_SHIFT (0x00000006u)
#define CSL_CHIP_IER_IE06_RESETVAL (0x00000000u)
/*----IE06 Tokens----*/
#define CSL_CHIP_IER_IE06_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE06_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE05_MASK (0x00000020u)
#define CSL_CHIP_IER_IE05_SHIFT (0x00000005u)
#define CSL_CHIP_IER_IE05_RESETVAL (0x00000000u)
/*----IE05 Tokens----*/
#define CSL_CHIP_IER_IE05_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE05_DISABLE (0x00000000u)
#define CSL_CHIP_IER_IE04_MASK (0x00000010u)
#define CSL_CHIP_IER_IE04_SHIFT (0x00000004u)
#define CSL_CHIP_IER_IE04_RESETVAL (0x00000000u)
/*----IE04 Tokens----*/
#define CSL_CHIP_IER_IE04_ENABLE (0x00000001u)
#define CSL_CHIP_IER_IE04_DISABLE (0x00000000u)
#define CSL_CHIP_IER_NMI_MASK (0x00000002u)
#define CSL_CHIP_IER_NMI_SHIFT (0x00000001u)
#define CSL_CHIP_IER_NMI_RESETVAL (0x00000000u)
/*----NMI Tokens----*/
#define CSL_CHIP_IER_NMI_ENABLE (0x00000001u)
#define CSL_CHIP_IER_RESET_MASK (0x00000001u)
#define CSL_CHIP_IER_RESET_SHIFT (0x00000000u)
#define CSL_CHIP_IER_RESET_RESETVAL (0x00000001u)
#define CSL_CHIP_IER_RESETVAL (0x00000001u)
/* ISTP */
#define CSL_CHIP_ISTP_ISTB_MASK (0xFFFFFC00u)
#define CSL_CHIP_ISTP_ISTB_SHIFT (0x0000000Au)
#define CSL_CHIP_ISTP_ISTB_RESETVAL (0x00000000u)
#define CSL_CHIP_ISTP_HPEINT_MASK (0x000003E0u)
#define CSL_CHIP_ISTP_HPEINT_SHIFT (0x00000005u)
#define CSL_CHIP_ISTP_HPEINT_RESETVAL (0x00000000u)
#define CSL_CHIP_ISTP_RESETVAL (0x00000000u)
/* IRP */
#define CSL_CHIP_IRP_IRP_MASK (0xFFFFFFFFu)
#define CSL_CHIP_IRP_IRP_SHIFT (0x00000000u)
#define CSL_CHIP_IRP_IRP_RESETVAL (0x00000000u)
#define CSL_CHIP_IRP_RESETVAL (0x00000000u)
/* NRP */
#define CSL_CHIP_NRP_NRP_MASK (0xFFFFFFFFu)
#define CSL_CHIP_NRP_NRP_SHIFT (0x00000000u)
#define CSL_CHIP_NRP_NRP_RESETVAL (0x00000000u)
#define CSL_CHIP_NRP_RESETVAL (0x00000000u)
/* ERP */
#define CSL_CHIP_ERP_ERP_MASK (0xFFFFFFFFu)
#define CSL_CHIP_ERP_ERP_SHIFT (0x00000000u)
#define CSL_CHIP_ERP_ERP_RESETVAL (0x00000000u)
#define CSL_CHIP_ERP_RESETVAL (0x00000000u)
/* TSCL */
#define CSL_CHIP_TSCL_TSCL_MASK (0xFFFFFFFFu)
#define CSL_CHIP_TSCL_TSCL_SHIFT (0x00000000u)
#define CSL_CHIP_TSCL_TSCL_RESETVAL (0x00000000u)
#define CSL_CHIP_TSCL_RESETVAL (0x00000000u)
/* TSCH */
#define CSL_CHIP_TSCH_TSCH_MASK (0xFFFFFFFFu)
#define CSL_CHIP_TSCH_TSCH_SHIFT (0x00000000u)
#define CSL_CHIP_TSCH_TSCH_RESETVAL (0x00000000u)
#define CSL_CHIP_TSCH_RESETVAL (0x00000000u)
/* ILC */
#define CSL_CHIP_ILC_ILC_MASK (0xFFFFFFFFu)
#define CSL_CHIP_ILC_ILC_SHIFT (0x00000000u)
#define CSL_CHIP_ILC_ILC_RESETVAL (0x00000000u)
#define CSL_CHIP_ILC_RESETVAL (0x00000000u)
/* RILC */
#define CSL_CHIP_RILC_RILC_MASK (0xFFFFFFFFu)
#define CSL_CHIP_RILC_RILC_SHIFT (0x00000000u)
#define CSL_CHIP_RILC_RILC_RESETVAL (0x00000000u)
#define CSL_CHIP_RILC_RESETVAL (0x00000000u)
/* PCE1 */
#define CSL_CHIP_PCE1_PCE1_MASK (0xFFFFFFFFu)
#define CSL_CHIP_PCE1_PCE1_SHIFT (0x00000000u)
#define CSL_CHIP_PCE1_PCE1_RESETVAL (0x00000000u)
#define CSL_CHIP_PCE1_RESETVAL (0x00000000u)
/* DNUM */
#define CSL_CHIP_DNUM_DSPNUM_MASK (0x000000FFu)
#define CSL_CHIP_DNUM_DSPNUM_SHIFT (0x00000000u)
#define CSL_CHIP_DNUM_DSPNUM_RESETVAL (0x00000000u)
#define CSL_CHIP_DNUM_RESETVAL (0x00000000u)
/* SSR */
#define CSL_CHIP_SSR_RESV_MASK (0xFFFFFFC0u)
#define CSL_CHIP_SSR_RESV_SHIFT (0x00000006u)
#define CSL_CHIP_SSR_RESV_RESETVAL (0x00000000u)
#define CSL_CHIP_SSR_M2_MASK (0x00000020u)
#define CSL_CHIP_SSR_M2_SHIFT (0x00000005u)
#define CSL_CHIP_SSR_M2_RESETVAL (0x00000000u)
#define CSL_CHIP_SSR_M1_MASK (0x00000010u)
#define CSL_CHIP_SSR_M1_SHIFT (0x00000004u)
#define CSL_CHIP_SSR_M1_RESETVAL (0x00000000u)
#define CSL_CHIP_SSR_S2_MASK (0x00000008u)
#define CSL_CHIP_SSR_S2_SHIFT (0x00000003u)
#define CSL_CHIP_SSR_S2_RESETVAL (0x00000000u)
#define CSL_CHIP_SSR_S1_MASK (0x00000004u)
#define CSL_CHIP_SSR_S1_SHIFT (0x00000002u)
#define CSL_CHIP_SSR_S1_RESETVAL (0x00000000u)
#define CSL_CHIP_SSR_L2_MASK (0x00000002u)
#define CSL_CHIP_SSR_L2_SHIFT (0x00000001u)
#define CSL_CHIP_SSR_L2_RESETVAL (0x00000000u)
#define CSL_CHIP_SSR_L1_MASK (0x00000001u)
#define CSL_CHIP_SSR_L1_SHIFT (0x00000000u)
#define CSL_CHIP_SSR_L1_RESETVAL (0x00000000u)
#define CSL_CHIP_SSR_RESETVAL (0x00000000u)
/* GPLYA */
#define CSL_CHIP_GPLYA_GPLYA_MASK (0xFFFFFFFFu)
#define CSL_CHIP_GPLYA_GPLYA_SHIFT (0x00000000u)
#define CSL_CHIP_GPLYA_GPLYA_RESETVAL (0x00000000u)
#define CSL_CHIP_GPLYA_RESETVAL (0x00000000u)
/* GPLYB */
#define CSL_CHIP_GPLYB_GPLYB_MASK (0xFFFFFFFFu)
#define CSL_CHIP_GPLYB_GPLYB_SHIFT (0x00000000u)
#define CSL_CHIP_GPLYB_GPLYB_RESETVAL (0x00000000u)
#define CSL_CHIP_GPLYB_RESETVAL (0x00000000u)
/* GFPGFR */
#define CSL_CHIP_GFPGFR_SIZE_MASK (0x07000000u)
#define CSL_CHIP_GFPGFR_SIZE_SHIFT (0x00000018u)
#define CSL_CHIP_GFPGFR_SIZE_RESETVAL (0x00000007u)
#define CSL_CHIP_GFPGFR_POLY_MASK (0x000000FFu)
#define CSL_CHIP_GFPGFR_POLY_SHIFT (0x00000000u)
#define CSL_CHIP_GFPGFR_POLY_RESETVAL (0x0000001Du)
#define CSL_CHIP_GFPGFR_RESETVAL (0x0700001Du)
/* TSR */
#define CSL_CHIP_TSR_IB_MASK (0x00008000u)
#define CSL_CHIP_TSR_IB_SHIFT (0x0000000Fu)
#define CSL_CHIP_TSR_IB_RESETVAL (0x00000000u)
/*----IB Tokens----*/
#define CSL_CHIP_TSR_IB_UNBLOCKED (0x00000000u)
#define CSL_CHIP_TSR_IB_BLOCKED (0x00000001u)
#define CSL_CHIP_TSR_SPLX_MASK (0x00004000u)
#define CSL_CHIP_TSR_SPLX_SHIFT (0x0000000Eu)
#define CSL_CHIP_TSR_SPLX_RESETVAL (0x00000000u)
/*----SPLX Tokens----*/
#define CSL_CHIP_TSR_SPLX_NOTEXEC (0x00000000u)
#define CSL_CHIP_TSR_SPLX_EXEC (0x00000001u)
#define CSL_CHIP_TSR_EXC_MASK (0x00000400u)
#define CSL_CHIP_TSR_EXC_SHIFT (0x0000000Au)
#define CSL_CHIP_TSR_EXC_RESETVAL (0x00000000u)
/*----EXC Tokens----*/
#define CSL_CHIP_TSR_EXC_NOTEXEC (0x00000000u)
#define CSL_CHIP_TSR_EXC_EXEC (0x00000001u)
#define CSL_CHIP_TSR_INT_MASK (0x00000200u)
#define CSL_CHIP_TSR_INT_SHIFT (0x00000009u)
#define CSL_CHIP_TSR_INT_RESETVAL (0x00000000u)
/*----INT Tokens----*/
#define CSL_CHIP_TSR_INT_NOTEXEC (0x00000000u)
#define CSL_CHIP_TSR_INT_EXEC (0x00000001u)
#define CSL_CHIP_TSR_CXM_MASK (0x000000C0u)
#define CSL_CHIP_TSR_CXM_SHIFT (0x00000006u)
#define CSL_CHIP_TSR_CXM_RESETVAL (0x00000000u)
/*----CXM Tokens----*/
#define CSL_CHIP_TSR_CXM_SUPERVISOR (0x00000000u)
#define CSL_CHIP_TSR_CXM_USER (0x00000001u)
#define CSL_CHIP_TSR_XEN_MASK (0x00000008u)
#define CSL_CHIP_TSR_XEN_SHIFT (0x00000003u)
#define CSL_CHIP_TSR_XEN_RESETVAL (0x00000000u)
/*----XEN Tokens----*/
#define CSL_CHIP_TSR_XEN_ENABLE (0x00000001u)
#define CSL_CHIP_TSR_XEN_DISABLE (0x00000000u)
#define CSL_CHIP_TSR_GEE_MASK (0x00000004u)
#define CSL_CHIP_TSR_GEE_SHIFT (0x00000002u)
#define CSL_CHIP_TSR_GEE_RESETVAL (0x00000000u)
/*----GEE Tokens----*/
#define CSL_CHIP_TSR_GEE_ENABLE (0x00000001u)
#define CSL_CHIP_TSR_GEE_DISABLE (0x00000000u)
#define CSL_CHIP_TSR_SGIE_MASK (0x00000002u)
#define CSL_CHIP_TSR_SGIE_SHIFT (0x00000001u)
#define CSL_CHIP_TSR_SGIE_RESETVAL (0x00000000u)
#define CSL_CHIP_TSR_GIE_MASK (0x00000001u)
#define CSL_CHIP_TSR_GIE_SHIFT (0x00000000u)
#define CSL_CHIP_TSR_GIE_RESETVAL (0x00000000u)
/*----GIE Tokens----*/
#define CSL_CHIP_TSR_GIE_ENABLE (0x00000001u)
#define CSL_CHIP_TSR_GIE_DISABLE (0x00000000u)
#define CSL_CHIP_TSR_RESETVAL (0x00000000u)
/* ITSR */
#define CSL_CHIP_ITSR_IB_MASK (0x00008000u)
#define CSL_CHIP_ITSR_IB_SHIFT (0x0000000Fu)
#define CSL_CHIP_ITSR_IB_RESETVAL (0x00000000u)
/*----IB Tokens----*/
#define CSL_CHIP_ITSR_IB_UNBLOCKED (0x00000000u)
#define CSL_CHIP_ITSR_IB_BLOCKED (0x00000001u)
#define CSL_CHIP_ITSR_SPLX_MASK (0x00004000u)
#define CSL_CHIP_ITSR_SPLX_SHIFT (0x0000000Eu)
#define CSL_CHIP_ITSR_SPLX_RESETVAL (0x00000000u)
/*----SPLX Tokens----*/
#define CSL_CHIP_ITSR_SPLX_NOTEXEC (0x00000000u)
#define CSL_CHIP_ITSR_SPLX_EXEC (0x00000001u)
#define CSL_CHIP_ITSR_EXC_MASK (0x00000400u)
#define CSL_CHIP_ITSR_EXC_SHIFT (0x0000000Au)
#define CSL_CHIP_ITSR_EXC_RESETVAL (0x00000000u)
/*----EXC Tokens----*/
#define CSL_CHIP_ITSR_EXC_NOTEXEC (0x00000000u)
#define CSL_CHIP_ITSR_EXC_EXEC (0x00000001u)
#define CSL_CHIP_ITSR_INT_MASK (0x00000200u)
#define CSL_CHIP_ITSR_INT_SHIFT (0x00000009u)
#define CSL_CHIP_ITSR_INT_RESETVAL (0x00000000u)
/*----INT Tokens----*/
#define CSL_CHIP_ITSR_INT_NOTEXEC (0x00000000u)
#define CSL_CHIP_ITSR_INT_EXEC (0x00000001u)
#define CSL_CHIP_ITSR_CXM_MASK (0x000000C0u)
#define CSL_CHIP_ITSR_CXM_SHIFT (0x00000006u)
#define CSL_CHIP_ITSR_CXM_RESETVAL (0x00000000u)
/*----CXM Tokens----*/
#define CSL_CHIP_ITSR_CXM_SUPERVISOR (0x00000000u)
#define CSL_CHIP_ITSR_CXM_USER (0x00000001u)
#define CSL_CHIP_ITSR_XEN_MASK (0x00000008u)
#define CSL_CHIP_ITSR_XEN_SHIFT (0x00000003u)
#define CSL_CHIP_ITSR_XEN_RESETVAL (0x00000000u)
/*----XEN Tokens----*/
#define CSL_CHIP_ITSR_XEN_ENABLE (0x00000001u)
#define CSL_CHIP_ITSR_XEN_DISABLE (0x00000000u)
#define CSL_CHIP_ITSR_GEE_MASK (0x00000004u)
#define CSL_CHIP_ITSR_GEE_SHIFT (0x00000002u)
#define CSL_CHIP_ITSR_GEE_RESETVAL (0x00000000u)
/*----GEE Tokens----*/
#define CSL_CHIP_ITSR_GEE_ENABLE (0x00000001u)
#define CSL_CHIP_ITSR_GEE_DISABLE (0x00000000u)
#define CSL_CHIP_ITSR_SGIE_MASK (0x00000002u)
#define CSL_CHIP_ITSR_SGIE_SHIFT (0x00000001u)
#define CSL_CHIP_ITSR_SGIE_RESETVAL (0x00000000u)
#define CSL_CHIP_ITSR_GIE_MASK (0x00000001u)
#define CSL_CHIP_ITSR_GIE_SHIFT (0x00000000u)
#define CSL_CHIP_ITSR_GIE_RESETVAL (0x00000000u)
/*----GIE Tokens----*/
#define CSL_CHIP_ITSR_GIE_ENABLE (0x00000001u)
#define CSL_CHIP_ITSR_GIE_DISABLE (0x00000000u)
#define CSL_CHIP_ITSR_RESETVAL (0x00000000u)
/* NTSR */
#define CSL_CHIP_NTSR_IB_MASK (0x00008000u)
#define CSL_CHIP_NTSR_IB_SHIFT (0x0000000Fu)
#define CSL_CHIP_NTSR_IB_RESETVAL (0x00000000u)
/*----IB Tokens----*/
#define CSL_CHIP_NTSR_IB_UNBLOCKED (0x00000000u)
#define CSL_CHIP_NTSR_IB_BLOCKED (0x00000001u)
#define CSL_CHIP_NTSR_SPLX_MASK (0x00004000u)
#define CSL_CHIP_NTSR_SPLX_SHIFT (0x0000000Eu)
#define CSL_CHIP_NTSR_SPLX_RESETVAL (0x00000000u)
/*----SPLX Tokens----*/
#define CSL_CHIP_NTSR_SPLX_NOTEXEC (0x00000000u)
#define CSL_CHIP_NTSR_SPLX_EXEC (0x00000001u)
#define CSL_CHIP_NTSR_EXC_MASK (0x00000400u)
#define CSL_CHIP_NTSR_EXC_SHIFT (0x0000000Au)
#define CSL_CHIP_NTSR_EXC_RESETVAL (0x00000000u)
/*----EXC Tokens----*/
#define CSL_CHIP_NTSR_EXC_NOTEXEC (0x00000000u)
#define CSL_CHIP_NTSR_EXC_EXEC (0x00000001u)
#define CSL_CHIP_NTSR_INT_MASK (0x00000200u)
#define CSL_CHIP_NTSR_INT_SHIFT (0x00000009u)
#define CSL_CHIP_NTSR_INT_RESETVAL (0x00000000u)
/*----INT Tokens----*/
#define CSL_CHIP_NTSR_INT_NOTEXEC (0x00000000u)
#define CSL_CHIP_NTSR_INT_EXEC (0x00000001u)
#define CSL_CHIP_NTSR_CXM_MASK (0x000000C0u)
#define CSL_CHIP_NTSR_CXM_SHIFT (0x00000006u)
#define CSL_CHIP_NTSR_CXM_RESETVAL (0x00000000u)
/*----CXM Tokens----*/
#define CSL_CHIP_NTSR_CXM_SUPERVISOR (0x00000000u)
#define CSL_CHIP_NTSR_CXM_USER (0x00000001u)
#define CSL_CHIP_NTSR_XEN_MASK (0x00000008u)
#define CSL_CHIP_NTSR_XEN_SHIFT (0x00000003u)
#define CSL_CHIP_NTSR_XEN_RESETVAL (0x00000000u)
/*----XEN Tokens----*/
#define CSL_CHIP_NTSR_XEN_ENABLE (0x00000001u)
#define CSL_CHIP_NTSR_XEN_DISABLE (0x00000000u)
#define CSL_CHIP_NTSR_GEE_MASK (0x00000004u)
#define CSL_CHIP_NTSR_GEE_SHIFT (0x00000002u)
#define CSL_CHIP_NTSR_GEE_RESETVAL (0x00000000u)
/*----GEE Tokens----*/
#define CSL_CHIP_NTSR_GEE_ENABLE (0x00000001u)
#define CSL_CHIP_NTSR_GEE_DISABLE (0x00000000u)
#define CSL_CHIP_NTSR_SGIE_MASK (0x00000002u)
#define CSL_CHIP_NTSR_SGIE_SHIFT (0x00000001u)
#define CSL_CHIP_NTSR_SGIE_RESETVAL (0x00000000u)
#define CSL_CHIP_NTSR_GIE_MASK (0x00000001u)
#define CSL_CHIP_NTSR_GIE_SHIFT (0x00000000u)
#define CSL_CHIP_NTSR_GIE_RESETVAL (0x00000000u)
/*----GIE Tokens----*/
#define CSL_CHIP_NTSR_GIE_ENABLE (0x00000001u)
#define CSL_CHIP_NTSR_GIE_DISABLE (0x00000000u)
#define CSL_CHIP_NTSR_RESETVAL (0x00000000u)
/* EFR */
#define CSL_CHIP_EFR_NXF_MASK (0x80000000u)
#define CSL_CHIP_EFR_NXF_SHIFT (0x0000001Fu)
#define CSL_CHIP_EFR_NXF_RESETVAL (0x00000000u)
#define CSL_CHIP_EFR_EXF_MASK (0x40000000u)
#define CSL_CHIP_EFR_EXF_SHIFT (0x0000001Eu)
#define CSL_CHIP_EFR_EXF_RESETVAL (0x00000000u)
#define CSL_CHIP_EFR_IXF_MASK (0x00000002u)
#define CSL_CHIP_EFR_IXF_SHIFT (0x00000001u)
#define CSL_CHIP_EFR_IXF_RESETVAL (0x00000000u)
#define CSL_CHIP_EFR_OXF_MASK (0x00000001u)
#define CSL_CHIP_EFR_OXF_SHIFT (0x00000000u)
#define CSL_CHIP_EFR_OXF_RESETVAL (0x00000000u)
#define CSL_CHIP_EFR_RESETVAL (0x00000000u)
/* ECR */
#define CSL_CHIP_ECR_NXC_MASK (0x80000000u)
#define CSL_CHIP_ECR_NXC_SHIFT (0x0000001Fu)
#define CSL_CHIP_ECR_NXC_RESETVAL (0x00000000u)
/*----NXC Tokens----*/
#define CSL_CHIP_ECR_NXC_CLEAR (0x00000001u)
#define CSL_CHIP_ECR_EXC_MASK (0x40000000u)
#define CSL_CHIP_ECR_EXC_SHIFT (0x0000001Eu)
#define CSL_CHIP_ECR_EXC_RESETVAL (0x00000000u)
/*----EXC Tokens----*/
#define CSL_CHIP_ECR_EXC_CLEAR (0x00000001u)
#define CSL_CHIP_ECR_IXC_MASK (0x00000002u)
#define CSL_CHIP_ECR_IXC_SHIFT (0x00000001u)
#define CSL_CHIP_ECR_IXC_RESETVAL (0x00000000u)
/*----IXC Tokens----*/
#define CSL_CHIP_ECR_IXC_CLEAR (0x00000001u)
#define CSL_CHIP_ECR_OXC_MASK (0x00000001u)
#define CSL_CHIP_ECR_OXC_SHIFT (0x00000000u)
#define CSL_CHIP_ECR_OXC_RESETVAL (0x00000000u)
/*----OXC Tokens----*/
#define CSL_CHIP_ECR_OXC_CLEAR (0x00000001u)
#define CSL_CHIP_ECR_RESETVAL (0x00000000u)
/* IERR */
#define CSL_CHIP_IERR_LBX_MASK (0x00000080u)
#define CSL_CHIP_IERR_LBX_SHIFT (0x00000007u)
#define CSL_CHIP_IERR_LBX_RESETVAL (0x00000000u)
#define CSL_CHIP_IERR_PRX_MASK (0x00000040u)
#define CSL_CHIP_IERR_PRX_SHIFT (0x00000006u)
#define CSL_CHIP_IERR_PRX_RESETVAL (0x00000000u)
#define CSL_CHIP_IERR_RAX_MASK (0x00000020u)
#define CSL_CHIP_IERR_RAX_SHIFT (0x00000005u)
#define CSL_CHIP_IERR_RAX_RESETVAL (0x00000000u)
#define CSL_CHIP_IERR_RCX_MASK (0x00000010u)
#define CSL_CHIP_IERR_RCX_SHIFT (0x00000004u)
#define CSL_CHIP_IERR_RCX_RESETVAL (0x00000000u)
#define CSL_CHIP_IERR_OPX_MASK (0x00000008u)
#define CSL_CHIP_IERR_OPX_SHIFT (0x00000003u)
#define CSL_CHIP_IERR_OPX_RESETVAL (0x00000000u)
#define CSL_CHIP_IERR_EPX_MASK (0x00000004u)
#define CSL_CHIP_IERR_EPX_SHIFT (0x00000002u)
#define CSL_CHIP_IERR_EPX_RESETVAL (0x00000000u)
#define CSL_CHIP_IERR_FPX_MASK (0x00000002u)
#define CSL_CHIP_IERR_FPX_SHIFT (0x00000001u)
#define CSL_CHIP_IERR_FPX_RESETVAL (0x00000000u)
#define CSL_CHIP_IERR_IFX_MASK (0x00000001u)
#define CSL_CHIP_IERR_IFX_SHIFT (0x00000000u)
#define CSL_CHIP_IERR_IFX_RESETVAL (0x00000000u)
#define CSL_CHIP_IERR_RESETVAL (0x00000000u)
/* REP */
#define CSL_CHIP_REP_REP_MASK (0xFFFFFFFFu)
#define CSL_CHIP_REP_REP_SHIFT (0x00000000u)
#define CSL_CHIP_REP_REP_RESETVAL (0x00000000u)
#define CSL_CHIP_REP_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/FB_Example/global.c | #include "MEA21_lib.h"
// the followign two lines create a variable in the external RAM
unsigned int ddr_data[1000000];
#pragma DATA_SECTION (ddr_data, ".dataddr");
Int32 adc_intern[TOTAL_ANALOG_CHANNELS];
#pragma DATA_ALIGN(adc_intern, 8);
int threshold;
int deadtime;
Uint32 StimulusEnable[2];
Uint32 DAC_select[4];
Uint32 elec_config[4];
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2HwControl.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_ddr2HwControl.c
*
* @path $(CSLPATH)\src\ddr2
*
* @desc File for functional layer of CSL API @a CSL_ddr2HwControl()
* - The @a CSL_ddr2HwControl() function definition & it's associated
* functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 11-Apr-2005 RM File Created.
*
* 05-Oct-2005 NG Updation done according to new register layer
*
* =============================================================================
*/
#include <csl_ddr2.h>
#include <csl_ddr2Aux.h>
/** ============================================================================
* @n@b CSL_ddr2HwControl
*
* @b Description
* @n Control operations for the DDR2. For a particular control operation, the
* pointer to the corresponding data type needs to be passed as argument
* HwControl function Call. All the arguments (Structure elements included)
* passed to the HwControl function are inputs. For the list of commands
* supported and argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_Ddr2HwControlCmd.
*
* @b Arguments
* @verbatim
hDdr2 Pointer to the peripheral data object of the
DDR2 external memory interface instance
cmd The command to this API indicates the action to be
taken
arg An optional argument @a void* casted
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command successful
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
* @li CSL_ESYS_INVPARAMS - The argument passed is invalid
* @li CSL_ESYS_INVCMD - The Command passed is invalid
*
* <b> Pre Condition </b>
* Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called successfully
* in order before calling @a CSL_ddr2HwControl(). For the argument type that
* can be @a void* casted & passed with a particular command refer to
* @a CSL_Ddr2HwControlCmd.
*
* <b> Post Condition </b>
* @n DDR2 registers are configured according to the command passed.
*
* @b Modifies
* @n DDR2 registers
*
* @b Example:
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Status status;
CSL_Ddr2SelfRefresh command;
command = CSL_DDR2_SELF_REFRESH_DISABLE;
...
status = CSL_ddr2HwControl(hDdr2,
CCSL_DDR2_CMD_SELF_REFRESH,
&command);
@endverbatim
*
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_ddr2HwControl, ".text:csl_section:ddr2");
CSL_Status CSL_ddr2HwControl (
CSL_Ddr2Handle hDdr2,
CSL_Ddr2HwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK;
if(hDdr2 == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if(((cmd >= 0) && (cmd <= CSL_DDR2_CMD_PRIO_RAISE)) && (arg == NULL)) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch(cmd) {
case CSL_DDR2_CMD_SELF_REFRESH:
CSL_ddr2Selfrefresh(hDdr2, (*(CSL_Ddr2SelfRefresh*)arg));
break;
case CSL_DDR2_CMD_REFRESH_RATE:
CSL_ddr2RefreshRate(hDdr2,(*(Uint16*)arg));
break;
case CSL_DDR2_CMD_PRIO_RAISE:
CSL_ddr2PrioRaise(hDdr2,(*(Uint8*)arg));
break;
default:
status = CSL_ESYS_INVCMD ;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotGetHwSetup.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_memprotGetHwSetup.c
*
* @path $(CSLPATH)\src\memprot
*
* @desc File for functional layer of CSL API CSL_memprotGetHwSetup ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 16-Jul-2004 <NAME> File Created
* 16-Nov-2005 ds Updated the documentation
* =============================================================================
*/
#include <csl_memprot.h>
/** ============================================================================
* @n@b CSL_memprotGetHwSetup
*
* @b Description
* @n This function gets the current setup of the Memory Protection registers.
* The status is returned through @a CSL_MemprotHwSetup. The obtaining of
* status is the reverse operation of @a CSL_MemprotHwSetup() function.
* Only the Memory Page attributes are read and filled into the HwSetup
* structure
*
* @b Arguments
* @verbatim
hMemprot Handle to the MEMPROT instance
setup Pointer to setup structure which contains the
setup information of MEMPROT.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Setup info load successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Usage Constraints: </b>
* Both @a CSL_memprotInit(), @a CSL_memprotOpen() and @a CSL_memprotHwSetup()
* must be called successfully in that order before @a CSL_memprotGetHwSetup()
* can be called. Ensure numpages is initialized depending on the number of
* desired attributes in the setup.Make sure to set numpages <= 32 for handles
* for L1D/L1P. Ensure numpages <= 64 for L2.
*
* <b> Post Condition </b>
* @n The registers of the specified MEMPROT instance will be setup.
*
* @b Modifies
* @n Hardware registers of the specified MEMPROT instance.
*
* @b Example
* @verbatim
#define PAGE_ATTR 0xFFF0
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
CSL_MemprotHwSetup L2MpSetup,L2MpGetSetup;
Uint16 pageAttrTable[10] = {PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,
PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR};
Uint32 key[2] = {<KEY>};
// Initializing the module
CSL_memprotInit(NULL);
// Opening the Handle for the L2
hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status);
L2MpSetup. memPageAttr = pageAttrTable;
L2MpSetup.numPages = 10;
L2MpSetup.key = key;
// Do Setup for the L2 Memory protection/
CSL_memprotHwSetup (hmpL2,&L2MpSetup);
CSL_memprotGetHwSetup(hmpL2,&L2MpGetSetup);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_memprotGetHwSetup, ".text:csl_section:memprot")
CSL_Status CSL_memprotGetHwSetup (
CSL_MemprotHandle hMemprot,
CSL_MemprotHwSetup *setup
)
{
CSL_Status status = CSL_SOK;
Uint16 i;
if (hMemprot == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (setup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
for (i = 0; i < setup->numPages; i++) {
setup->memPageAttr[i] = hMemprot->regs->MPPA[i];
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc_src/src/intc/_csl_intcDispatcher.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/*
* @file _csl_intcDispatcher.c
*
* @brief File for functional layer of CSL API _CSL_intcDispatcherInit(..)
*
* PATH $(CSLPATH)\src\intc
*/
/* =============================================================================
* Revision History
* ===============
* 12-Jun-2004 <NAME> File Created
*
* =============================================================================
*/
#include <csl_intc.h>
#include <_csl_intc.h>
#include <csl_intcAux.h>
/* ============================================================================
* @n@b _CSL_intcDispatcher
*
* @b Description
* @n Get the Event Source of the Interrupt
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @li None
*
*
* @b Example:
* @verbatim
...
_CSL_intcCpuIntrTable.isr4 = _CSL_intcDispatcher;
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (_CSL_intcDispatcher, ".text:csl_section:intc");
interrupt void _CSL_intcDispatcher (void)
{
Uint32 evtId;
Uint32 intrId = (_CSL_intcCpuIntrTable.currentVectId - \
(Uint32)(&_CSL_intcCpuIntrTable) - 4)/4;
/* Get the Event Source of the Interrupt */
if (intrId < 8)
evtId = CSL_FEXTR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTMUX1, \
(intrId-4)*8+6,(intrId-4)*8);
else {
if (intrId < 12)
evtId = CSL_FEXTR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTMUX2, \
(intrId-8)*8+6,(intrId-8)*8);
else
evtId = CSL_FEXTR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTMUX3, \
(intrId-12)*8+6,(intrId-12)*8);
}
if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE)
_CSL_intcEventHandlerRecord[_CSL_intcEventOffsetMap[evtId]].handler (
_CSL_intcEventHandlerRecord[_CSL_intcEventOffsetMap[evtId]].arg
);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_edma3cc.h | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_edma3cc.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for EDMA3CC
*/
#ifndef _CSLR_EDMA3CC_H_
#define _CSLR_EDMA3CC_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure for DRA
\**************************************************************************/
typedef struct {
volatile Uint32 DRAE;
volatile Uint32 DRAEH;
} CSL_Edma3ccDraRegs;
/**************************************************************************\
* Register Overlay Structure for SHADOW
\**************************************************************************/
typedef struct {
volatile Uint32 ER;
volatile Uint32 ERH;
volatile Uint32 ECR;
volatile Uint32 ECRH;
volatile Uint32 ESR;
volatile Uint32 ESRH;
volatile Uint32 CER;
volatile Uint32 CERH;
volatile Uint32 EER;
volatile Uint32 EERH;
volatile Uint32 EECR;
volatile Uint32 EECRH;
volatile Uint32 EESR;
volatile Uint32 EESRH;
volatile Uint32 SER;
volatile Uint32 SERH;
volatile Uint32 SECR;
volatile Uint32 SECRH;
volatile Uint8 RSVD0[8];
volatile Uint32 IER;
volatile Uint32 IERH;
volatile Uint32 IECR;
volatile Uint32 IECRH;
volatile Uint32 IESR;
volatile Uint32 IESRH;
volatile Uint32 IPR;
volatile Uint32 IPRH;
volatile Uint32 ICR;
volatile Uint32 ICRH;
volatile Uint32 IEVAL;
volatile Uint8 RSVD1[4];
volatile Uint32 QER;
volatile Uint32 QEER;
volatile Uint32 QEECR;
volatile Uint32 QEESR;
volatile Uint32 QSER;
volatile Uint32 QSECR;
volatile Uint8 RSVD2[360];
} CSL_Edma3ccShadowRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_Edma3ccShadowRegs *CSL_EdmaccShadowRegsOvly;
/**************************************************************************\
* Register Overlay Structure for PARAMSET
\**************************************************************************/
typedef struct {
volatile Uint32 OPT;
volatile Uint32 SRC;
volatile Uint32 A_B_CNT;
volatile Uint32 DST;
volatile Uint32 SRC_DST_BIDX;
volatile Uint32 LINK_BCNTRLD;
volatile Uint32 SRC_DST_CIDX;
volatile Uint32 CCNT;
} CSL_Edma3ccParamsetRegs;
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 PID;
volatile Uint32 CCCFG;
volatile Uint8 RSVD0[248];
volatile Uint32 DCHMAP[64];
volatile Uint32 QCHMAP[4];
volatile Uint8 RSVD1[48];
volatile Uint32 DMAQNUM[8];
volatile Uint32 QDMAQNUM;
volatile Uint8 RSVD2[32];
volatile Uint32 QUEPRI;
volatile Uint8 RSVD3[120];
volatile Uint32 EMR;
volatile Uint32 EMRH;
volatile Uint32 EMCR;
volatile Uint32 EMCRH;
volatile Uint32 QEMR;
volatile Uint32 QEMCR;
volatile Uint32 CCERR;
volatile Uint32 CCERRCLR;
volatile Uint32 EEVAL;
volatile Uint8 RSVD4[28];
CSL_Edma3ccDraRegs DRA[8];
volatile Uint32 QRAE[8];
volatile Uint8 RSVD5[96];
volatile Uint32 QUEEVTENTRY[4][16];
volatile Uint8 RSVD6[256];
volatile Uint32 QSTAT[4];
volatile Uint8 RSVD7[16];
volatile Uint32 QWMTHRA;
volatile Uint8 RSVD8[28];
volatile Uint32 CCSTAT;
volatile Uint8 RSVD9[444];
volatile Uint32 MPFAR;
volatile Uint32 MPFSR;
volatile Uint32 MPFCR;
volatile Uint32 MPPAG;
volatile Uint32 MPPA[8];
volatile Uint8 RSVD10[2000];
volatile Uint32 ER;
volatile Uint32 ERH;
volatile Uint32 ECR;
volatile Uint32 ECRH;
volatile Uint32 ESR;
volatile Uint32 ESRH;
volatile Uint32 CER;
volatile Uint32 CERH;
volatile Uint32 EER;
volatile Uint32 EERH;
volatile Uint32 EECR;
volatile Uint32 EECRH;
volatile Uint32 EESR;
volatile Uint32 EESRH;
volatile Uint32 SER;
volatile Uint32 SERH;
volatile Uint32 SECR;
volatile Uint32 SECRH;
volatile Uint8 RSVD11[8];
volatile Uint32 IER;
volatile Uint32 IERH;
volatile Uint32 IECR;
volatile Uint32 IECRH;
volatile Uint32 IESR;
volatile Uint32 IESRH;
volatile Uint32 IPR;
volatile Uint32 IPRH;
volatile Uint32 ICR;
volatile Uint32 ICRH;
volatile Uint32 IEVAL;
volatile Uint8 RSVD12[4];
volatile Uint32 QER;
volatile Uint32 QEER;
volatile Uint32 QEECR;
volatile Uint32 QEESR;
volatile Uint32 QSER;
volatile Uint32 QSECR;
volatile Uint8 RSVD13[3944];
CSL_Edma3ccShadowRegs SHADOW[8];
volatile Uint8 RSVD14[4096];
CSL_Edma3ccParamsetRegs PARAMSET[256];
} CSL_Edma3ccRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_Edma3ccRegs *CSL_Edma3ccRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* PID */
#define CSL_EDMA3CC_PID_PID_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_PID_PID_SHIFT (0x00000000u)
#define CSL_EDMA3CC_PID_PID_RESETVAL (0x40011B00u)
#define CSL_EDMA3CC_PID_RESETVAL (0x40011B00u)
/* CCCFG */
#define CSL_EDMA3CC_CCCFG_MP_EXIST_MASK (0x02000000u)
#define CSL_EDMA3CC_CCCFG_MP_EXIST_SHIFT (0x00000019u)
#define CSL_EDMA3CC_CCCFG_MP_EXIST_RESETVAL (0x00000001u)
/*----MP_EXIST Tokens----*/
#define CSL_EDMA3CC_CCCFG_MP_EXIST_INCLUDED (0x00000001u)
#define CSL_EDMA3CC_CCCFG_CHMAP_EXIST_MASK (0x01000000u)
#define CSL_EDMA3CC_CCCFG_CHMAP_EXIST_SHIFT (0x00000018u)
#define CSL_EDMA3CC_CCCFG_CHMAP_EXIST_RESETVAL (0x00000001u)
/*----CHMAP_EXIST Tokens----*/
#define CSL_EDMA3CC_CCCFG_CHMAP_EXIST_INCLUDED (0x00000001u)
#define CSL_EDMA3CC_CCCFG_NUM_REGN_MASK (0x00300000u)
#define CSL_EDMA3CC_CCCFG_NUM_REGN_SHIFT (0x00000014u)
#define CSL_EDMA3CC_CCCFG_NUM_REGN_RESETVAL (0x00000003u)
/*----NUM_REGN Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_REGN_8 (0x00000003u)
#define CSL_EDMA3CC_CCCFG_NUM_EVQUE_MASK (0x00070000u)
#define CSL_EDMA3CC_CCCFG_NUM_EVQUE_SHIFT (0x00000010u)
#define CSL_EDMA3CC_CCCFG_NUM_EVQUE_RESETVAL (0x00000003u)
/*----NUM_EVQUE Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_EVQUE_4 (0x00000003u)
#define CSL_EDMA3CC_CCCFG_NUM_PAENTRY_MASK (0x00007000u)
#define CSL_EDMA3CC_CCCFG_NUM_PAENTRY_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_CCCFG_NUM_PAENTRY_RESETVAL (0x00000004u)
/*----NUM_PAENTRY Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_PAENTRY_256 (0x00000004u)
#define CSL_EDMA3CC_CCCFG_NUM_INTCH_MASK (0x00000700u)
#define CSL_EDMA3CC_CCCFG_NUM_INTCH_SHIFT (0x00000008u)
#define CSL_EDMA3CC_CCCFG_NUM_INTCH_RESETVAL (0x00000004u)
/*----NUM_INTCH Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_INTCH_64 (0x00000004u)
#define CSL_EDMA3CC_CCCFG_NUM_QDMACH_MASK (0x00000070u)
#define CSL_EDMA3CC_CCCFG_NUM_QDMACH_SHIFT (0x00000004u)
#define CSL_EDMA3CC_CCCFG_NUM_QDMACH_RESETVAL (0x00000002u)
/*----NUM_QDMACH Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_QDMACH_4 (0x00000002u)
#define CSL_EDMA3CC_CCCFG_NUM_DMACH_MASK (0x00000007u)
#define CSL_EDMA3CC_CCCFG_NUM_DMACH_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CCCFG_NUM_DMACH_RESETVAL (0x00000005u)
/*----NUM_DMACH Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_DMACH_64 (0x00000005u)
#define CSL_EDMA3CC_CCCFG_RESETVAL (0x03334425u)
/* DCHMAP */
#define CSL_EDMA3CC_DCHMAP_PAENTRY_MASK (0x00003FE0u)
#define CSL_EDMA3CC_DCHMAP_PAENTRY_SHIFT (0x00000005u)
#define CSL_EDMA3CC_DCHMAP_PAENTRY_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DCHMAP_RESETVAL (0x00000000u)
/* QCHMAP */
#define CSL_EDMA3CC_QCHMAP_PAENTRY_MASK (0x00003FE0u)
#define CSL_EDMA3CC_QCHMAP_PAENTRY_SHIFT (0x00000005u)
#define CSL_EDMA3CC_QCHMAP_PAENTRY_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QCHMAP_TRWORD_MASK (0x0000001Cu)
#define CSL_EDMA3CC_QCHMAP_TRWORD_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QCHMAP_TRWORD_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QCHMAP_RESETVAL (0x00000000u)
/* DMAQNUM */
#define CSL_EDMA3CC_DMAQNUM_E7_MASK (0x70000000u)
#define CSL_EDMA3CC_DMAQNUM_E7_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_DMAQNUM_E7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E6_MASK (0x07000000u)
#define CSL_EDMA3CC_DMAQNUM_E6_SHIFT (0x00000018u)
#define CSL_EDMA3CC_DMAQNUM_E6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E5_MASK (0x00700000u)
#define CSL_EDMA3CC_DMAQNUM_E5_SHIFT (0x00000014u)
#define CSL_EDMA3CC_DMAQNUM_E5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E4_MASK (0x00070000u)
#define CSL_EDMA3CC_DMAQNUM_E4_SHIFT (0x00000010u)
#define CSL_EDMA3CC_DMAQNUM_E4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E3_MASK (0x00007000u)
#define CSL_EDMA3CC_DMAQNUM_E3_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_DMAQNUM_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E2_MASK (0x00000700u)
#define CSL_EDMA3CC_DMAQNUM_E2_SHIFT (0x00000008u)
#define CSL_EDMA3CC_DMAQNUM_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E1_MASK (0x00000070u)
#define CSL_EDMA3CC_DMAQNUM_E1_SHIFT (0x00000004u)
#define CSL_EDMA3CC_DMAQNUM_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E0_MASK (0x00000007u)
#define CSL_EDMA3CC_DMAQNUM_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_RESETVAL (0x00000000u)
/* QDMAQNUM */
#define CSL_EDMA3CC_QDMAQNUM_E3_MASK (0x00007000u)
#define CSL_EDMA3CC_QDMAQNUM_E3_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_QDMAQNUM_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_E2_MASK (0x00000700u)
#define CSL_EDMA3CC_QDMAQNUM_E2_SHIFT (0x00000008u)
#define CSL_EDMA3CC_QDMAQNUM_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_E1_MASK (0x00000070u)
#define CSL_EDMA3CC_QDMAQNUM_E1_SHIFT (0x00000004u)
#define CSL_EDMA3CC_QDMAQNUM_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_E0_MASK (0x00000007u)
#define CSL_EDMA3CC_QDMAQNUM_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_RESETVAL (0x00000000u)
/* QUEPRI */
#define CSL_EDMA3CC_QUEPRI_PRIQ3_MASK (0x00007000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ3_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_QUEPRI_PRIQ3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ2_MASK (0x00000700u)
#define CSL_EDMA3CC_QUEPRI_PRIQ2_SHIFT (0x00000008u)
#define CSL_EDMA3CC_QUEPRI_PRIQ2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ1_MASK (0x00000070u)
#define CSL_EDMA3CC_QUEPRI_PRIQ1_SHIFT (0x00000004u)
#define CSL_EDMA3CC_QUEPRI_PRIQ1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ0_MASK (0x00000007u)
#define CSL_EDMA3CC_QUEPRI_PRIQ0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_RESETVAL (0x00000000u)
/* EMR */
#define CSL_EDMA3CC_EMR_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_EMR_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EMR_E31_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_EMR_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EMR_E30_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_EMR_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EMR_E29_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_EMR_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EMR_E28_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_EMR_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EMR_E27_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_EMR_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EMR_E26_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_EMR_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EMR_E25_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_EMR_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EMR_E24_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_EMR_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EMR_E23_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_EMR_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EMR_E22_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_EMR_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EMR_E21_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_EMR_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EMR_E20_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_EMR_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EMR_E19_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_EMR_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EMR_E18_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_EMR_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EMR_E17_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_EMR_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EMR_E16_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_EMR_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EMR_E15_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_EMR_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EMR_E14_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_EMR_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EMR_E13_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_EMR_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EMR_E12_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_EMR_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EMR_E11_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_EMR_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EMR_E10_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_EMR_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EMR_E9_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_EMR_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EMR_E8_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_EMR_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EMR_E7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_EMR_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EMR_E6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_EMR_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EMR_E5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_EMR_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EMR_E4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_EMR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EMR_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_EMR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EMR_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_EMR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EMR_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_EMR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EMR_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMR_RESETVAL (0x00000000u)
/* EMRH */
#define CSL_EDMA3CC_EMRH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_EMRH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EMRH_E63_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_EMRH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EMRH_E62_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_EMRH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EMRH_E61_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_EMRH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EMRH_E60_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_EMRH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EMRH_E59_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_EMRH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EMRH_E58_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_EMRH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EMRH_E57_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_EMRH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EMRH_E56_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_EMRH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EMRH_E55_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_EMRH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EMRH_E54_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_EMRH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EMRH_E53_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_EMRH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EMRH_E52_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_EMRH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EMRH_E51_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_EMRH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EMRH_E50_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_EMRH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EMRH_E49_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_EMRH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EMRH_E48_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_EMRH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EMRH_E47_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_EMRH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EMRH_E46_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_EMRH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EMRH_E45_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_EMRH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EMRH_E44_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_EMRH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EMRH_E43_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_EMRH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EMRH_E42_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_EMRH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EMRH_E41_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_EMRH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EMRH_E40_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_EMRH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EMRH_E39_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_EMRH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EMRH_E38_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_EMRH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EMRH_E37_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_EMRH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EMRH_E36_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_EMRH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EMRH_E35_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_EMRH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EMRH_E34_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_EMRH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EMRH_E33_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_EMRH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EMRH_E32_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EMRH_RESETVAL (0x00000000u)
/* EMCR */
#define CSL_EDMA3CC_EMCR_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_EMCR_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EMCR_E31_RESETVAL (0x00000000u)
/*----E31 Tokens----*/
#define CSL_EDMA3CC_EMCR_E31_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_EMCR_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EMCR_E30_RESETVAL (0x00000000u)
/*----E30 Tokens----*/
#define CSL_EDMA3CC_EMCR_E30_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_EMCR_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EMCR_E29_RESETVAL (0x00000000u)
/*----E29 Tokens----*/
#define CSL_EDMA3CC_EMCR_E29_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_EMCR_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EMCR_E28_RESETVAL (0x00000000u)
/*----E28 Tokens----*/
#define CSL_EDMA3CC_EMCR_E28_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_EMCR_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EMCR_E27_RESETVAL (0x00000000u)
/*----E27 Tokens----*/
#define CSL_EDMA3CC_EMCR_E27_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_EMCR_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EMCR_E26_RESETVAL (0x00000000u)
/*----E26 Tokens----*/
#define CSL_EDMA3CC_EMCR_E26_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_EMCR_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EMCR_E25_RESETVAL (0x00000000u)
/*----E25 Tokens----*/
#define CSL_EDMA3CC_EMCR_E25_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_EMCR_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EMCR_E24_RESETVAL (0x00000000u)
/*----E24 Tokens----*/
#define CSL_EDMA3CC_EMCR_E24_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_EMCR_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EMCR_E23_RESETVAL (0x00000000u)
/*----E23 Tokens----*/
#define CSL_EDMA3CC_EMCR_E23_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_EMCR_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EMCR_E22_RESETVAL (0x00000000u)
/*----E22 Tokens----*/
#define CSL_EDMA3CC_EMCR_E22_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_EMCR_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EMCR_E21_RESETVAL (0x00000000u)
/*----E21 Tokens----*/
#define CSL_EDMA3CC_EMCR_E21_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_EMCR_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EMCR_E20_RESETVAL (0x00000000u)
/*----E20 Tokens----*/
#define CSL_EDMA3CC_EMCR_E20_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_EMCR_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EMCR_E19_RESETVAL (0x00000000u)
/*----E19 Tokens----*/
#define CSL_EDMA3CC_EMCR_E19_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_EMCR_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EMCR_E18_RESETVAL (0x00000000u)
/*----E18 Tokens----*/
#define CSL_EDMA3CC_EMCR_E18_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_EMCR_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EMCR_E17_RESETVAL (0x00000000u)
/*----E17 Tokens----*/
#define CSL_EDMA3CC_EMCR_E17_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_EMCR_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EMCR_E16_RESETVAL (0x00000000u)
/*----E16 Tokens----*/
#define CSL_EDMA3CC_EMCR_E16_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_EMCR_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EMCR_E15_RESETVAL (0x00000000u)
/*----E15 Tokens----*/
#define CSL_EDMA3CC_EMCR_E15_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_EMCR_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EMCR_E14_RESETVAL (0x00000000u)
/*----E14 Tokens----*/
#define CSL_EDMA3CC_EMCR_E14_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_EMCR_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EMCR_E13_RESETVAL (0x00000000u)
/*----E13 Tokens----*/
#define CSL_EDMA3CC_EMCR_E13_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_EMCR_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EMCR_E12_RESETVAL (0x00000000u)
/*----E12 Tokens----*/
#define CSL_EDMA3CC_EMCR_E12_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_EMCR_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EMCR_E11_RESETVAL (0x00000000u)
/*----E11 Tokens----*/
#define CSL_EDMA3CC_EMCR_E11_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_EMCR_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EMCR_E10_RESETVAL (0x00000000u)
/*----E10 Tokens----*/
#define CSL_EDMA3CC_EMCR_E10_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_EMCR_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EMCR_E9_RESETVAL (0x00000000u)
/*----E9 Tokens----*/
#define CSL_EDMA3CC_EMCR_E9_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_EMCR_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EMCR_E8_RESETVAL (0x00000000u)
/*----E8 Tokens----*/
#define CSL_EDMA3CC_EMCR_E8_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_EMCR_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EMCR_E7_RESETVAL (0x00000000u)
/*----E7 Tokens----*/
#define CSL_EDMA3CC_EMCR_E7_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_EMCR_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EMCR_E6_RESETVAL (0x00000000u)
/*----E6 Tokens----*/
#define CSL_EDMA3CC_EMCR_E6_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_EMCR_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EMCR_E5_RESETVAL (0x00000000u)
/*----E5 Tokens----*/
#define CSL_EDMA3CC_EMCR_E5_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_EMCR_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EMCR_E4_RESETVAL (0x00000000u)
/*----E4 Tokens----*/
#define CSL_EDMA3CC_EMCR_E4_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_EMCR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EMCR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_EMCR_E3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_EMCR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EMCR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_EMCR_E2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_EMCR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EMCR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_EMCR_E1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_EMCR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EMCR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_EMCR_E0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCR_RESETVAL (0x00000000u)
/* EMCRH */
#define CSL_EDMA3CC_EMCRH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_EMCRH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EMCRH_E63_RESETVAL (0x00000000u)
/*----E63 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E63_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_EMCRH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EMCRH_E62_RESETVAL (0x00000000u)
/*----E62 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E62_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_EMCRH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EMCRH_E61_RESETVAL (0x00000000u)
/*----E61 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E61_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_EMCRH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EMCRH_E60_RESETVAL (0x00000000u)
/*----E60 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E60_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_EMCRH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EMCRH_E59_RESETVAL (0x00000000u)
/*----E59 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E59_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_EMCRH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EMCRH_E58_RESETVAL (0x00000000u)
/*----E58 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E58_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_EMCRH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EMCRH_E57_RESETVAL (0x00000000u)
/*----E57 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E57_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_EMCRH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EMCRH_E56_RESETVAL (0x00000000u)
/*----E56 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E56_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_EMCRH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EMCRH_E55_RESETVAL (0x00000000u)
/*----E55 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E55_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_EMCRH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EMCRH_E54_RESETVAL (0x00000000u)
/*----E54 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E54_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_EMCRH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EMCRH_E53_RESETVAL (0x00000000u)
/*----E53 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E53_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_EMCRH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EMCRH_E52_RESETVAL (0x00000000u)
/*----E52 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E52_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_EMCRH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EMCRH_E51_RESETVAL (0x00000000u)
/*----E51 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E51_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_EMCRH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EMCRH_E50_RESETVAL (0x00000000u)
/*----E50 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E50_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_EMCRH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EMCRH_E49_RESETVAL (0x00000000u)
/*----E49 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E49_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_EMCRH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EMCRH_E48_RESETVAL (0x00000000u)
/*----E48 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E48_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_EMCRH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EMCRH_E47_RESETVAL (0x00000000u)
/*----E47 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E47_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_EMCRH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EMCRH_E46_RESETVAL (0x00000000u)
/*----E46 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E46_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_EMCRH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EMCRH_E45_RESETVAL (0x00000000u)
/*----E45 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E45_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_EMCRH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EMCRH_E44_RESETVAL (0x00000000u)
/*----E44 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E44_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_EMCRH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EMCRH_E43_RESETVAL (0x00000000u)
/*----E43 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E43_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_EMCRH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EMCRH_E42_RESETVAL (0x00000000u)
/*----E42 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E42_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_EMCRH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EMCRH_E41_RESETVAL (0x00000000u)
/*----E41 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E41_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_EMCRH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EMCRH_E40_RESETVAL (0x00000000u)
/*----E40 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E40_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_EMCRH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EMCRH_E39_RESETVAL (0x00000000u)
/*----E39 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E39_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_EMCRH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EMCRH_E38_RESETVAL (0x00000000u)
/*----E38 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E38_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_EMCRH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EMCRH_E37_RESETVAL (0x00000000u)
/*----E37 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E37_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_EMCRH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EMCRH_E36_RESETVAL (0x00000000u)
/*----E36 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E36_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_EMCRH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EMCRH_E35_RESETVAL (0x00000000u)
/*----E35 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E35_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_EMCRH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EMCRH_E34_RESETVAL (0x00000000u)
/*----E34 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E34_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_EMCRH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E33_RESETVAL (0x00000000u)
/*----E33 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E33_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EMCRH_E32_RESETVAL (0x00000000u)
/*----E32 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E32_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EMCRH_RESETVAL (0x00000000u)
/* QEMR */
#define CSL_EDMA3CC_QEMR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QEMR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QEMR_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEMR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QEMR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QEMR_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEMR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QEMR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QEMR_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEMR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QEMR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QEMR_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEMR_RESETVAL (0x00000000u)
/* QEMCR */
#define CSL_EDMA3CC_QEMCR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QEMCR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QEMCR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_QEMCR_E3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QEMCR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QEMCR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QEMCR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_QEMCR_E2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QEMCR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QEMCR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QEMCR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_QEMCR_E1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QEMCR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QEMCR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QEMCR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_QEMCR_E0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QEMCR_RESETVAL (0x00000000u)
/* CCERR */
#define CSL_EDMA3CC_CCERR_TCCERR_MASK (0x00010000u)
#define CSL_EDMA3CC_CCERR_TCCERR_SHIFT (0x00000010u)
#define CSL_EDMA3CC_CCERR_TCCERR_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CCERR_QTHRXCD3_MASK (0x00000008u)
#define CSL_EDMA3CC_CCERR_QTHRXCD3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_CCERR_QTHRXCD3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CCERR_QTHRXCD2_MASK (0x00000004u)
#define CSL_EDMA3CC_CCERR_QTHRXCD2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_CCERR_QTHRXCD2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CCERR_QTHRXCD1_MASK (0x00000002u)
#define CSL_EDMA3CC_CCERR_QTHRXCD1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_CCERR_QTHRXCD1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CCERR_QTHRXCD0_MASK (0x00000001u)
#define CSL_EDMA3CC_CCERR_QTHRXCD0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CCERR_QTHRXCD0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CCERR_RESETVAL (0x00000000u)
/* CCERRCLR */
#define CSL_EDMA3CC_CCERRCLR_TCCERR_MASK (0x00010000u)
#define CSL_EDMA3CC_CCERRCLR_TCCERR_SHIFT (0x00000010u)
#define CSL_EDMA3CC_CCERRCLR_TCCERR_RESETVAL (0x00000000u)
/*----TCCERR Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_TCCERR_CLEAR (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD3_MASK (0x00000008u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD3_RESETVAL (0x00000000u)
/*----QTHRXCD3 Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD2_MASK (0x00000004u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD2_RESETVAL (0x00000000u)
/*----QTHRXCD2 Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD1_MASK (0x00000002u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD1_RESETVAL (0x00000000u)
/*----QTHRXCD1 Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD0_MASK (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD0_RESETVAL (0x00000000u)
/*----QTHRXCD0 Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_RESETVAL (0x00000000u)
/* EEVAL */
#define CSL_EDMA3CC_EEVAL_EVAL_MASK (0x00000001u)
#define CSL_EDMA3CC_EEVAL_EVAL_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EEVAL_EVAL_RESETVAL (0x00000000u)
/*----EVAL Tokens----*/
#define CSL_EDMA3CC_EEVAL_EVAL_EVAL (0x00000001u)
#define CSL_EDMA3CC_EEVAL_RESETVAL (0x00000000u)
/* DRAE */
#define CSL_EDMA3CC_DRAE_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_DRAE_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_DRAE_E31_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_DRAE_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_DRAE_E30_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_DRAE_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_DRAE_E29_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_DRAE_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_DRAE_E28_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_DRAE_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_DRAE_E27_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_DRAE_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_DRAE_E26_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_DRAE_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_DRAE_E25_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_DRAE_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_DRAE_E24_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_DRAE_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_DRAE_E23_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_DRAE_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_DRAE_E22_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_DRAE_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_DRAE_E21_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_DRAE_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_DRAE_E20_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_DRAE_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_DRAE_E19_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_DRAE_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_DRAE_E18_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_DRAE_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_DRAE_E17_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_DRAE_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_DRAE_E16_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_DRAE_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_DRAE_E15_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_DRAE_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_DRAE_E14_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_DRAE_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_DRAE_E13_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_DRAE_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_DRAE_E12_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_DRAE_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_DRAE_E11_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_DRAE_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_DRAE_E10_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_DRAE_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_DRAE_E9_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_DRAE_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_DRAE_E8_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_DRAE_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_DRAE_E7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_DRAE_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_DRAE_E6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_DRAE_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_DRAE_E5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_DRAE_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_DRAE_E4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_DRAE_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_DRAE_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_DRAE_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_DRAE_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_DRAE_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_DRAE_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_DRAE_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_DRAE_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAE_RESETVAL (0x00000000u)
/* DRAEH */
#define CSL_EDMA3CC_DRAEH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_DRAEH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_DRAEH_E63_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_DRAEH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_DRAEH_E62_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_DRAEH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_DRAEH_E61_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_DRAEH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_DRAEH_E60_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_DRAEH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_DRAEH_E59_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_DRAEH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_DRAEH_E58_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_DRAEH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_DRAEH_E57_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_DRAEH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_DRAEH_E56_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_DRAEH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_DRAEH_E55_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_DRAEH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_DRAEH_E54_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_DRAEH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_DRAEH_E53_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_DRAEH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_DRAEH_E52_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_DRAEH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_DRAEH_E51_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_DRAEH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_DRAEH_E50_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_DRAEH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_DRAEH_E49_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_DRAEH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_DRAEH_E48_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_DRAEH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_DRAEH_E47_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_DRAEH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_DRAEH_E46_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_DRAEH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_DRAEH_E45_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_DRAEH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_DRAEH_E44_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_DRAEH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_DRAEH_E43_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_DRAEH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_DRAEH_E42_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_DRAEH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_DRAEH_E41_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_DRAEH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_DRAEH_E40_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_DRAEH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_DRAEH_E39_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_DRAEH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_DRAEH_E38_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_DRAEH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_DRAEH_E37_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_DRAEH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_DRAEH_E36_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_DRAEH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_DRAEH_E35_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_DRAEH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_DRAEH_E34_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_DRAEH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_DRAEH_E33_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_DRAEH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_DRAEH_E32_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DRAEH_RESETVAL (0x00000000u)
/* QRAE */
#define CSL_EDMA3CC_QRAE_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QRAE_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QRAE_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QRAE_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QRAE_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QRAE_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QRAE_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QRAE_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QRAE_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QRAE_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QRAE_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QRAE_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QRAE_RESETVAL (0x00000000u)
/* QUEEVT_ENTRY */
#define CSL_EDMA3CC_QUEEVT_ENTRY_RESV_MASK (0xFFFFFF00u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_RESV_SHIFT (0x00000008u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_RESV_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ETYPE_MASK (0x000000C0u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ETYPE_SHIFT (0x00000006u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ETYPE_RESETVAL (0x00000000u)
/*----ETYPE Tokens----*/
#define CSL_EDMA3CC_QUEEVT_ENTRY_ETYPE_EVENT (0x00000000u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ETYPE_MANUAL (0x00000001u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ETYPE_CHAIN (0x00000002u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ETYPE_AUTO (0x00000003u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ENUM_MASK (0x0000003Fu)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ENUM_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_ENUM_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEEVT_ENTRY_RESETVAL (0x00000000u)
/* QSTAT */
#define CSL_EDMA3CC_QSTAT_THRXD_MASK (0x01000000u)
#define CSL_EDMA3CC_QSTAT_THRXD_SHIFT (0x00000018u)
#define CSL_EDMA3CC_QSTAT_THRXD_RESETVAL (0x00000000u)
/*----THRXD Tokens----*/
#define CSL_EDMA3CC_QSTAT_THRXD_NOTEXCEED (0x00000000u)
#define CSL_EDMA3CC_QSTAT_THRXD_EXCEED (0x00000001u)
#define CSL_EDMA3CC_QSTAT_WM_MASK (0x001F0000u)
#define CSL_EDMA3CC_QSTAT_WM_SHIFT (0x00000010u)
#define CSL_EDMA3CC_QSTAT_WM_RESETVAL (0x00000000u)
/*----WM Tokens----*/
#define CSL_EDMA3CC_QSTAT_WM_EMPTY (0x00000000u)
#define CSL_EDMA3CC_QSTAT_WM_FULL (0x00000010u)
#define CSL_EDMA3CC_QSTAT_NUMVAL_MASK (0x00001F00u)
#define CSL_EDMA3CC_QSTAT_NUMVAL_SHIFT (0x00000008u)
#define CSL_EDMA3CC_QSTAT_NUMVAL_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QSTAT_STRTPTR_MASK (0x0000000Fu)
#define CSL_EDMA3CC_QSTAT_STRTPTR_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QSTAT_STRTPTR_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QSTAT_RESETVAL (0x00000000u)
/* QWMTHRA */
#define CSL_EDMA3CC_QWMTHRA_Q3_MASK (0x1F000000u)
#define CSL_EDMA3CC_QWMTHRA_Q3_SHIFT (0x00000018u)
#define CSL_EDMA3CC_QWMTHRA_Q3_RESETVAL (0x00000010u)
/*----Q3 Tokens----*/
#define CSL_EDMA3CC_QWMTHRA_Q3_DISABLE (0x00000011u)
#define CSL_EDMA3CC_QWMTHRA_Q2_MASK (0x001F0000u)
#define CSL_EDMA3CC_QWMTHRA_Q2_SHIFT (0x00000010u)
#define CSL_EDMA3CC_QWMTHRA_Q2_RESETVAL (0x00000010u)
/*----Q2 Tokens----*/
#define CSL_EDMA3CC_QWMTHRA_Q2_DISABLE (0x00000011u)
#define CSL_EDMA3CC_QWMTHRA_Q1_MASK (0x00001F00u)
#define CSL_EDMA3CC_QWMTHRA_Q1_SHIFT (0x00000008u)
#define CSL_EDMA3CC_QWMTHRA_Q1_RESETVAL (0x00000010u)
/*----Q1 Tokens----*/
#define CSL_EDMA3CC_QWMTHRA_Q1_DISABLE (0x00000011u)
#define CSL_EDMA3CC_QWMTHRA_Q0_MASK (0x0000001Fu)
#define CSL_EDMA3CC_QWMTHRA_Q0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QWMTHRA_Q0_RESETVAL (0x00000010u)
/*----Q0 Tokens----*/
#define CSL_EDMA3CC_QWMTHRA_Q0_DISABLE (0x00000011u)
#define CSL_EDMA3CC_QWMTHRA_RESETVAL (0x10101010u)
/* CCSTAT */
#define CSL_EDMA3CC_CCSTAT_QUEACTV3_MASK (0x00080000u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV3_SHIFT (0x00000013u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV3_RESETVAL (0x00000000u)
/*----QUEACTV3 Tokens----*/
#define CSL_EDMA3CC_CCSTAT_QUEACTV3_NONE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV3_ACTIVE (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV2_MASK (0x00040000u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV2_SHIFT (0x00000012u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV2_RESETVAL (0x00000000u)
/*----QUEACTV2 Tokens----*/
#define CSL_EDMA3CC_CCSTAT_QUEACTV2_NONE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV2_ACTIVE (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV1_MASK (0x00020000u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV1_SHIFT (0x00000011u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV1_RESETVAL (0x00000000u)
/*----QUEACTV1 Tokens----*/
#define CSL_EDMA3CC_CCSTAT_QUEACTV1_NONE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV1_ACTIVE (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV0_MASK (0x00010000u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV0_SHIFT (0x00000010u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV0_RESETVAL (0x00000000u)
/*----QUEACTV0 Tokens----*/
#define CSL_EDMA3CC_CCSTAT_QUEACTV0_NONE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_QUEACTV0_ACTIVE (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_COMPACTV_MASK (0x00003F00u)
#define CSL_EDMA3CC_CCSTAT_COMPACTV_SHIFT (0x00000008u)
#define CSL_EDMA3CC_CCSTAT_COMPACTV_RESETVAL (0x00000000u)
/*----COMPACTV Tokens----*/
#define CSL_EDMA3CC_CCSTAT_COMPACTV_NONE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_ACTV_MASK (0x00000010u)
#define CSL_EDMA3CC_CCSTAT_ACTV_SHIFT (0x00000004u)
#define CSL_EDMA3CC_CCSTAT_ACTV_RESETVAL (0x00000000u)
/*----ACTV Tokens----*/
#define CSL_EDMA3CC_CCSTAT_ACTV_IDLE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_ACTV_BUSY (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_WSTATACTV_MASK (0x00000008u)
#define CSL_EDMA3CC_CCSTAT_WSTATACTV_SHIFT (0x00000003u)
#define CSL_EDMA3CC_CCSTAT_WSTATACTV_RESETVAL (0x00000000u)
/*----WSTATACTV Tokens----*/
#define CSL_EDMA3CC_CCSTAT_WSTATACTV_IDLE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_WSTATACTV_BUSY (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_TRACTV_MASK (0x00000004u)
#define CSL_EDMA3CC_CCSTAT_TRACTV_SHIFT (0x00000002u)
#define CSL_EDMA3CC_CCSTAT_TRACTV_RESETVAL (0x00000000u)
/*----TRACTV Tokens----*/
#define CSL_EDMA3CC_CCSTAT_TRACTV_NONE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_TRACTV_ACTIVE (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_QEVTACTV_MASK (0x00000002u)
#define CSL_EDMA3CC_CCSTAT_QEVTACTV_SHIFT (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_QEVTACTV_RESETVAL (0x00000000u)
/*----QEVTACTV Tokens----*/
#define CSL_EDMA3CC_CCSTAT_QEVTACTV_NONE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_QEVTACTV_ACTIVE (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_EVTACTV_MASK (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_EVTACTV_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_EVTACTV_RESETVAL (0x00000000u)
/*----EVTACTV Tokens----*/
#define CSL_EDMA3CC_CCSTAT_EVTACTV_NONE (0x00000000u)
#define CSL_EDMA3CC_CCSTAT_EVTACTV_ACTIVE (0x00000001u)
#define CSL_EDMA3CC_CCSTAT_RESETVAL (0x00000000u)
/* MPFAR */
#define CSL_EDMA3CC_MPFAR_FADDR_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_MPFAR_FADDR_SHIFT (0x00000000u)
#define CSL_EDMA3CC_MPFAR_FADDR_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_MPFAR_RESETVAL (0x00000000u)
/* MPFSR */
#define CSL_EDMA3CC_MPFSR_FID_MASK (0x00001E00u)
#define CSL_EDMA3CC_MPFSR_FID_SHIFT (0x00000009u)
#define CSL_EDMA3CC_MPFSR_FID_RESETVAL (0x00000009u)
#define CSL_EDMA3CC_MPFSR_SRE_MASK (0x00000020u)
#define CSL_EDMA3CC_MPFSR_SRE_SHIFT (0x00000005u)
#define CSL_EDMA3CC_MPFSR_SRE_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_MPFSR_SWE_MASK (0x00000010u)
#define CSL_EDMA3CC_MPFSR_SWE_SHIFT (0x00000004u)
#define CSL_EDMA3CC_MPFSR_SWE_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_MPFSR_SXE_MASK (0x00000008u)
#define CSL_EDMA3CC_MPFSR_SXE_SHIFT (0x00000003u)
#define CSL_EDMA3CC_MPFSR_SXE_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_MPFSR_URE_MASK (0x00000004u)
#define CSL_EDMA3CC_MPFSR_URE_SHIFT (0x00000002u)
#define CSL_EDMA3CC_MPFSR_URE_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_MPFSR_UWE_MASK (0x00000002u)
#define CSL_EDMA3CC_MPFSR_UWE_SHIFT (0x00000001u)
#define CSL_EDMA3CC_MPFSR_UWE_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_MPFSR_UXE_MASK (0x00000001u)
#define CSL_EDMA3CC_MPFSR_UXE_SHIFT (0x00000000u)
#define CSL_EDMA3CC_MPFSR_UXE_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_MPFSR_RESETVAL (0x00001200u)
/* MPFCR */
#define CSL_EDMA3CC_MPFCR_MPFCLR_MASK (0x00000001u)
#define CSL_EDMA3CC_MPFCR_MPFCLR_SHIFT (0x00000000u)
#define CSL_EDMA3CC_MPFCR_MPFCLR_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_MPFCR_RESETVAL (0x00000000u)
/* MPPAG */
#define CSL_EDMA3CC_MPPAG_AID5_MASK (0x00008000u)
#define CSL_EDMA3CC_MPPAG_AID5_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_MPPAG_AID5_RESETVAL (0x00000001u)
/*----AID5 Tokens----*/
#define CSL_EDMA3CC_MPPAG_AID5_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_AID5_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_AID4_MASK (0x00004000u)
#define CSL_EDMA3CC_MPPAG_AID4_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_MPPAG_AID4_RESETVAL (0x00000001u)
/*----AID4 Tokens----*/
#define CSL_EDMA3CC_MPPAG_AID4_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_AID4_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_AID3_MASK (0x00002000u)
#define CSL_EDMA3CC_MPPAG_AID3_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_MPPAG_AID3_RESETVAL (0x00000001u)
/*----AID3 Tokens----*/
#define CSL_EDMA3CC_MPPAG_AID3_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_AID3_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_AID2_MASK (0x00001000u)
#define CSL_EDMA3CC_MPPAG_AID2_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_MPPAG_AID2_RESETVAL (0x00000001u)
/*----AID2 Tokens----*/
#define CSL_EDMA3CC_MPPAG_AID2_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_AID2_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_AID1_MASK (0x00000800u)
#define CSL_EDMA3CC_MPPAG_AID1_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_MPPAG_AID1_RESETVAL (0x00000001u)
/*----AID1 Tokens----*/
#define CSL_EDMA3CC_MPPAG_AID1_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_AID1_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_AID0_MASK (0x00000400u)
#define CSL_EDMA3CC_MPPAG_AID0_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_MPPAG_AID0_RESETVAL (0x00000001u)
/*----AID0 Tokens----*/
#define CSL_EDMA3CC_MPPAG_AID0_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_AID0_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_EXT_MASK (0x00000200u)
#define CSL_EDMA3CC_MPPAG_EXT_SHIFT (0x00000009u)
#define CSL_EDMA3CC_MPPAG_EXT_RESETVAL (0x00000001u)
/*----EXT Tokens----*/
#define CSL_EDMA3CC_MPPAG_EXT_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_EXT_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_SR_MASK (0x00000020u)
#define CSL_EDMA3CC_MPPAG_SR_SHIFT (0x00000005u)
#define CSL_EDMA3CC_MPPAG_SR_RESETVAL (0x00000001u)
/*----SR Tokens----*/
#define CSL_EDMA3CC_MPPAG_SR_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_SR_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_SW_MASK (0x00000010u)
#define CSL_EDMA3CC_MPPAG_SW_SHIFT (0x00000004u)
#define CSL_EDMA3CC_MPPAG_SW_RESETVAL (0x00000001u)
/*----SW Tokens----*/
#define CSL_EDMA3CC_MPPAG_SW_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_SW_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_SX_MASK (0x00000008u)
#define CSL_EDMA3CC_MPPAG_SX_SHIFT (0x00000003u)
#define CSL_EDMA3CC_MPPAG_SX_RESETVAL (0x00000000u)
/*----SX Tokens----*/
#define CSL_EDMA3CC_MPPAG_SX_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_SX_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_UR_MASK (0x00000004u)
#define CSL_EDMA3CC_MPPAG_UR_SHIFT (0x00000002u)
#define CSL_EDMA3CC_MPPAG_UR_RESETVAL (0x00000001u)
/*----UR Tokens----*/
#define CSL_EDMA3CC_MPPAG_UR_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_UR_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_UW_MASK (0x00000002u)
#define CSL_EDMA3CC_MPPAG_UW_SHIFT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_UW_RESETVAL (0x00000001u)
/*----UW Tokens----*/
#define CSL_EDMA3CC_MPPAG_UW_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_UW_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_UX_MASK (0x00000001u)
#define CSL_EDMA3CC_MPPAG_UX_SHIFT (0x00000000u)
#define CSL_EDMA3CC_MPPAG_UX_RESETVAL (0x00000000u)
/*----UX Tokens----*/
#define CSL_EDMA3CC_MPPAG_UX_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPAG_UX_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPAG_RESETVAL (0x0000FEF6u)
/* MPPA */
#define CSL_EDMA3CC_MPPA_AID5_MASK (0x00008000u)
#define CSL_EDMA3CC_MPPA_AID5_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_MPPA_AID5_RESETVAL (0x00000001u)
/*----AID5 Tokens----*/
#define CSL_EDMA3CC_MPPA_AID5_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_AID5_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_AID4_MASK (0x00004000u)
#define CSL_EDMA3CC_MPPA_AID4_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_MPPA_AID4_RESETVAL (0x00000001u)
/*----AID4 Tokens----*/
#define CSL_EDMA3CC_MPPA_AID4_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_AID4_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_AID3_MASK (0x00002000u)
#define CSL_EDMA3CC_MPPA_AID3_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_MPPA_AID3_RESETVAL (0x00000001u)
/*----AID3 Tokens----*/
#define CSL_EDMA3CC_MPPA_AID3_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_AID3_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_AID2_MASK (0x00001000u)
#define CSL_EDMA3CC_MPPA_AID2_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_MPPA_AID2_RESETVAL (0x00000001u)
/*----AID2 Tokens----*/
#define CSL_EDMA3CC_MPPA_AID2_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_AID2_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_AID1_MASK (0x00000800u)
#define CSL_EDMA3CC_MPPA_AID1_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_MPPA_AID1_RESETVAL (0x00000001u)
/*----AID1 Tokens----*/
#define CSL_EDMA3CC_MPPA_AID1_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_AID1_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_AID0_MASK (0x00000400u)
#define CSL_EDMA3CC_MPPA_AID0_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_MPPA_AID0_RESETVAL (0x00000001u)
/*----AID0 Tokens----*/
#define CSL_EDMA3CC_MPPA_AID0_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_AID0_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_EXT_MASK (0x00000200u)
#define CSL_EDMA3CC_MPPA_EXT_SHIFT (0x00000009u)
#define CSL_EDMA3CC_MPPA_EXT_RESETVAL (0x00000001u)
/*----EXT Tokens----*/
#define CSL_EDMA3CC_MPPA_EXT_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_EXT_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_SR_MASK (0x00000020u)
#define CSL_EDMA3CC_MPPA_SR_SHIFT (0x00000005u)
#define CSL_EDMA3CC_MPPA_SR_RESETVAL (0x00000001u)
/*----SR Tokens----*/
#define CSL_EDMA3CC_MPPA_SR_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_SR_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_SW_MASK (0x00000010u)
#define CSL_EDMA3CC_MPPA_SW_SHIFT (0x00000004u)
#define CSL_EDMA3CC_MPPA_SW_RESETVAL (0x00000001u)
/*----SW Tokens----*/
#define CSL_EDMA3CC_MPPA_SW_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_SW_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_SX_MASK (0x00000008u)
#define CSL_EDMA3CC_MPPA_SX_SHIFT (0x00000003u)
#define CSL_EDMA3CC_MPPA_SX_RESETVAL (0x00000000u)
/*----SX Tokens----*/
#define CSL_EDMA3CC_MPPA_SX_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_SX_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_UR_MASK (0x00000004u)
#define CSL_EDMA3CC_MPPA_UR_SHIFT (0x00000002u)
#define CSL_EDMA3CC_MPPA_UR_RESETVAL (0x00000001u)
/*----UR Tokens----*/
#define CSL_EDMA3CC_MPPA_UR_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_UR_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_UW_MASK (0x00000002u)
#define CSL_EDMA3CC_MPPA_UW_SHIFT (0x00000001u)
#define CSL_EDMA3CC_MPPA_UW_RESETVAL (0x00000001u)
/*----UW Tokens----*/
#define CSL_EDMA3CC_MPPA_UW_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_UW_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_UX_MASK (0x00000001u)
#define CSL_EDMA3CC_MPPA_UX_SHIFT (0x00000000u)
#define CSL_EDMA3CC_MPPA_UX_RESETVAL (0x00000000u)
/*----UX Tokens----*/
#define CSL_EDMA3CC_MPPA_UX_BLOCK (0x00000000u)
#define CSL_EDMA3CC_MPPA_UX_PERMIT (0x00000001u)
#define CSL_EDMA3CC_MPPA_RESETVAL (0x0000FEF6u)
/* ER */
#define CSL_EDMA3CC_ER_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_ER_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_ER_E31_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_ER_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_ER_E30_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_ER_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_ER_E29_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_ER_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_ER_E28_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_ER_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_ER_E27_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_ER_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_ER_E26_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_ER_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_ER_E25_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_ER_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_ER_E24_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_ER_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_ER_E23_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_ER_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_ER_E22_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_ER_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_ER_E21_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_ER_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_ER_E20_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_ER_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_ER_E19_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_ER_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_ER_E18_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_ER_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_ER_E17_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_ER_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_ER_E16_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_ER_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_ER_E15_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_ER_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_ER_E14_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_ER_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_ER_E13_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_ER_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_ER_E12_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_ER_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_ER_E11_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_ER_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_ER_E10_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_ER_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_ER_E9_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_ER_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_ER_E8_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_ER_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_ER_E7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_ER_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_ER_E6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_ER_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_ER_E5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_ER_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_ER_E4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_ER_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_ER_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_ER_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_ER_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_ER_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_ER_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_ER_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ER_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_RESETVAL (0x00000000u)
/* ERH */
#define CSL_EDMA3CC_ERH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_ERH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_ERH_E63_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_ERH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_ERH_E62_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_ERH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_ERH_E61_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_ERH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_ERH_E60_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_ERH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_ERH_E59_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_ERH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_ERH_E58_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_ERH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_ERH_E57_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_ERH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_ERH_E56_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_ERH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_ERH_E55_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_ERH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_ERH_E54_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_ERH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_ERH_E53_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_ERH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_ERH_E52_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_ERH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_ERH_E51_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_ERH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_ERH_E50_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_ERH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_ERH_E49_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_ERH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_ERH_E48_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_ERH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_ERH_E47_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_ERH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_ERH_E46_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_ERH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_ERH_E45_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_ERH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_ERH_E44_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_ERH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_ERH_E43_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_ERH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_ERH_E42_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_ERH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_ERH_E41_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_ERH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_ERH_E40_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_ERH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_ERH_E39_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_ERH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_ERH_E38_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_ERH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_ERH_E37_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_ERH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_ERH_E36_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_ERH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_ERH_E35_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_ERH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_ERH_E34_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_ERH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_ERH_E33_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_ERH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ERH_E32_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_RESETVAL (0x00000000u)
/* ECR */
#define CSL_EDMA3CC_ECR_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_ECR_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_ECR_E31_RESETVAL (0x00000000u)
/*----E31 Tokens----*/
#define CSL_EDMA3CC_ECR_E31_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_ECR_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_ECR_E30_RESETVAL (0x00000000u)
/*----E30 Tokens----*/
#define CSL_EDMA3CC_ECR_E30_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_ECR_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_ECR_E29_RESETVAL (0x00000000u)
/*----E29 Tokens----*/
#define CSL_EDMA3CC_ECR_E29_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_ECR_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_ECR_E28_RESETVAL (0x00000000u)
/*----E28 Tokens----*/
#define CSL_EDMA3CC_ECR_E28_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_ECR_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_ECR_E27_RESETVAL (0x00000000u)
/*----E27 Tokens----*/
#define CSL_EDMA3CC_ECR_E27_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_ECR_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_ECR_E26_RESETVAL (0x00000000u)
/*----E26 Tokens----*/
#define CSL_EDMA3CC_ECR_E26_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_ECR_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_ECR_E25_RESETVAL (0x00000000u)
/*----E25 Tokens----*/
#define CSL_EDMA3CC_ECR_E25_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_ECR_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_ECR_E24_RESETVAL (0x00000000u)
/*----E24 Tokens----*/
#define CSL_EDMA3CC_ECR_E24_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_ECR_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_ECR_E23_RESETVAL (0x00000000u)
/*----E23 Tokens----*/
#define CSL_EDMA3CC_ECR_E23_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_ECR_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_ECR_E22_RESETVAL (0x00000000u)
/*----E22 Tokens----*/
#define CSL_EDMA3CC_ECR_E22_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_ECR_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_ECR_E21_RESETVAL (0x00000000u)
/*----E21 Tokens----*/
#define CSL_EDMA3CC_ECR_E21_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_ECR_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_ECR_E20_RESETVAL (0x00000000u)
/*----E20 Tokens----*/
#define CSL_EDMA3CC_ECR_E20_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_ECR_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_ECR_E19_RESETVAL (0x00000000u)
/*----E19 Tokens----*/
#define CSL_EDMA3CC_ECR_E19_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_ECR_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_ECR_E18_RESETVAL (0x00000000u)
/*----E18 Tokens----*/
#define CSL_EDMA3CC_ECR_E18_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_ECR_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_ECR_E17_RESETVAL (0x00000000u)
/*----E17 Tokens----*/
#define CSL_EDMA3CC_ECR_E17_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_ECR_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_ECR_E16_RESETVAL (0x00000000u)
/*----E16 Tokens----*/
#define CSL_EDMA3CC_ECR_E16_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_ECR_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_ECR_E15_RESETVAL (0x00000000u)
/*----E15 Tokens----*/
#define CSL_EDMA3CC_ECR_E15_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_ECR_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_ECR_E14_RESETVAL (0x00000000u)
/*----E14 Tokens----*/
#define CSL_EDMA3CC_ECR_E14_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_ECR_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_ECR_E13_RESETVAL (0x00000000u)
/*----E13 Tokens----*/
#define CSL_EDMA3CC_ECR_E13_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_ECR_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_ECR_E12_RESETVAL (0x00000000u)
/*----E12 Tokens----*/
#define CSL_EDMA3CC_ECR_E12_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_ECR_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_ECR_E11_RESETVAL (0x00000000u)
/*----E11 Tokens----*/
#define CSL_EDMA3CC_ECR_E11_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_ECR_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_ECR_E10_RESETVAL (0x00000000u)
/*----E10 Tokens----*/
#define CSL_EDMA3CC_ECR_E10_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_ECR_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_ECR_E9_RESETVAL (0x00000000u)
/*----E9 Tokens----*/
#define CSL_EDMA3CC_ECR_E9_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_ECR_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_ECR_E8_RESETVAL (0x00000000u)
/*----E8 Tokens----*/
#define CSL_EDMA3CC_ECR_E8_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_ECR_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_ECR_E7_RESETVAL (0x00000000u)
/*----E7 Tokens----*/
#define CSL_EDMA3CC_ECR_E7_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_ECR_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_ECR_E6_RESETVAL (0x00000000u)
/*----E6 Tokens----*/
#define CSL_EDMA3CC_ECR_E6_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_ECR_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_ECR_E5_RESETVAL (0x00000000u)
/*----E5 Tokens----*/
#define CSL_EDMA3CC_ECR_E5_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_ECR_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_ECR_E4_RESETVAL (0x00000000u)
/*----E4 Tokens----*/
#define CSL_EDMA3CC_ECR_E4_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_ECR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_ECR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_ECR_E3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_ECR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_ECR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_ECR_E2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_ECR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_ECR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_ECR_E1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_ECR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ECR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_ECR_E0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECR_RESETVAL (0x00000000u)
/* ECRH */
#define CSL_EDMA3CC_ECRH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_ECRH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_ECRH_E63_RESETVAL (0x00000000u)
/*----E63 Tokens----*/
#define CSL_EDMA3CC_ECRH_E63_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_ECRH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_ECRH_E62_RESETVAL (0x00000000u)
/*----E62 Tokens----*/
#define CSL_EDMA3CC_ECRH_E62_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_ECRH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_ECRH_E61_RESETVAL (0x00000000u)
/*----E61 Tokens----*/
#define CSL_EDMA3CC_ECRH_E61_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_ECRH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_ECRH_E60_RESETVAL (0x00000000u)
/*----E60 Tokens----*/
#define CSL_EDMA3CC_ECRH_E60_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_ECRH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_ECRH_E59_RESETVAL (0x00000000u)
/*----E59 Tokens----*/
#define CSL_EDMA3CC_ECRH_E59_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_ECRH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_ECRH_E58_RESETVAL (0x00000000u)
/*----E58 Tokens----*/
#define CSL_EDMA3CC_ECRH_E58_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_ECRH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_ECRH_E57_RESETVAL (0x00000000u)
/*----E57 Tokens----*/
#define CSL_EDMA3CC_ECRH_E57_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_ECRH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_ECRH_E56_RESETVAL (0x00000000u)
/*----E56 Tokens----*/
#define CSL_EDMA3CC_ECRH_E56_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_ECRH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_ECRH_E55_RESETVAL (0x00000000u)
/*----E55 Tokens----*/
#define CSL_EDMA3CC_ECRH_E55_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_ECRH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_ECRH_E54_RESETVAL (0x00000000u)
/*----E54 Tokens----*/
#define CSL_EDMA3CC_ECRH_E54_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_ECRH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_ECRH_E53_RESETVAL (0x00000000u)
/*----E53 Tokens----*/
#define CSL_EDMA3CC_ECRH_E53_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_ECRH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_ECRH_E52_RESETVAL (0x00000000u)
/*----E52 Tokens----*/
#define CSL_EDMA3CC_ECRH_E52_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_ECRH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_ECRH_E51_RESETVAL (0x00000000u)
/*----E51 Tokens----*/
#define CSL_EDMA3CC_ECRH_E51_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_ECRH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_ECRH_E50_RESETVAL (0x00000000u)
/*----E50 Tokens----*/
#define CSL_EDMA3CC_ECRH_E50_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_ECRH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_ECRH_E49_RESETVAL (0x00000000u)
/*----E49 Tokens----*/
#define CSL_EDMA3CC_ECRH_E49_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_ECRH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_ECRH_E48_RESETVAL (0x00000000u)
/*----E48 Tokens----*/
#define CSL_EDMA3CC_ECRH_E48_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_ECRH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_ECRH_E47_RESETVAL (0x00000000u)
/*----E47 Tokens----*/
#define CSL_EDMA3CC_ECRH_E47_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_ECRH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_ECRH_E46_RESETVAL (0x00000000u)
/*----E46 Tokens----*/
#define CSL_EDMA3CC_ECRH_E46_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_ECRH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_ECRH_E45_RESETVAL (0x00000000u)
/*----E45 Tokens----*/
#define CSL_EDMA3CC_ECRH_E45_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_ECRH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_ECRH_E44_RESETVAL (0x00000000u)
/*----E44 Tokens----*/
#define CSL_EDMA3CC_ECRH_E44_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_ECRH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_ECRH_E43_RESETVAL (0x00000000u)
/*----E43 Tokens----*/
#define CSL_EDMA3CC_ECRH_E43_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_ECRH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_ECRH_E42_RESETVAL (0x00000000u)
/*----E42 Tokens----*/
#define CSL_EDMA3CC_ECRH_E42_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_ECRH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_ECRH_E41_RESETVAL (0x00000000u)
/*----E41 Tokens----*/
#define CSL_EDMA3CC_ECRH_E41_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_ECRH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_ECRH_E40_RESETVAL (0x00000000u)
/*----E40 Tokens----*/
#define CSL_EDMA3CC_ECRH_E40_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_ECRH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_ECRH_E39_RESETVAL (0x00000000u)
/*----E39 Tokens----*/
#define CSL_EDMA3CC_ECRH_E39_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_ECRH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_ECRH_E38_RESETVAL (0x00000000u)
/*----E38 Tokens----*/
#define CSL_EDMA3CC_ECRH_E38_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_ECRH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_ECRH_E37_RESETVAL (0x00000000u)
/*----E37 Tokens----*/
#define CSL_EDMA3CC_ECRH_E37_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_ECRH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_ECRH_E36_RESETVAL (0x00000000u)
/*----E36 Tokens----*/
#define CSL_EDMA3CC_ECRH_E36_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_ECRH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_ECRH_E35_RESETVAL (0x00000000u)
/*----E35 Tokens----*/
#define CSL_EDMA3CC_ECRH_E35_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_ECRH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_ECRH_E34_RESETVAL (0x00000000u)
/*----E34 Tokens----*/
#define CSL_EDMA3CC_ECRH_E34_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_ECRH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_ECRH_E33_RESETVAL (0x00000000u)
/*----E33 Tokens----*/
#define CSL_EDMA3CC_ECRH_E33_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_ECRH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ECRH_E32_RESETVAL (0x00000000u)
/*----E32 Tokens----*/
#define CSL_EDMA3CC_ECRH_E32_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ECRH_RESETVAL (0x00000000u)
/* ESR */
#define CSL_EDMA3CC_ESR_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_ESR_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_ESR_E31_RESETVAL (0x00000000u)
/*----E31 Tokens----*/
#define CSL_EDMA3CC_ESR_E31_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_ESR_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_ESR_E30_RESETVAL (0x00000000u)
/*----E30 Tokens----*/
#define CSL_EDMA3CC_ESR_E30_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_ESR_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_ESR_E29_RESETVAL (0x00000000u)
/*----E29 Tokens----*/
#define CSL_EDMA3CC_ESR_E29_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_ESR_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_ESR_E28_RESETVAL (0x00000000u)
/*----E28 Tokens----*/
#define CSL_EDMA3CC_ESR_E28_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_ESR_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_ESR_E27_RESETVAL (0x00000000u)
/*----E27 Tokens----*/
#define CSL_EDMA3CC_ESR_E27_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_ESR_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_ESR_E26_RESETVAL (0x00000000u)
/*----E26 Tokens----*/
#define CSL_EDMA3CC_ESR_E26_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_ESR_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_ESR_E25_RESETVAL (0x00000000u)
/*----E25 Tokens----*/
#define CSL_EDMA3CC_ESR_E25_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_ESR_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_ESR_E24_RESETVAL (0x00000000u)
/*----E24 Tokens----*/
#define CSL_EDMA3CC_ESR_E24_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_ESR_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_ESR_E23_RESETVAL (0x00000000u)
/*----E23 Tokens----*/
#define CSL_EDMA3CC_ESR_E23_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_ESR_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_ESR_E22_RESETVAL (0x00000000u)
/*----E22 Tokens----*/
#define CSL_EDMA3CC_ESR_E22_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_ESR_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_ESR_E21_RESETVAL (0x00000000u)
/*----E21 Tokens----*/
#define CSL_EDMA3CC_ESR_E21_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_ESR_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_ESR_E20_RESETVAL (0x00000000u)
/*----E20 Tokens----*/
#define CSL_EDMA3CC_ESR_E20_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_ESR_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_ESR_E19_RESETVAL (0x00000000u)
/*----E19 Tokens----*/
#define CSL_EDMA3CC_ESR_E19_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_ESR_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_ESR_E18_RESETVAL (0x00000000u)
/*----E18 Tokens----*/
#define CSL_EDMA3CC_ESR_E18_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_ESR_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_ESR_E17_RESETVAL (0x00000000u)
/*----E17 Tokens----*/
#define CSL_EDMA3CC_ESR_E17_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_ESR_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_ESR_E16_RESETVAL (0x00000000u)
/*----E16 Tokens----*/
#define CSL_EDMA3CC_ESR_E16_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_ESR_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_ESR_E15_RESETVAL (0x00000000u)
/*----E15 Tokens----*/
#define CSL_EDMA3CC_ESR_E15_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_ESR_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_ESR_E14_RESETVAL (0x00000000u)
/*----E14 Tokens----*/
#define CSL_EDMA3CC_ESR_E14_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_ESR_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_ESR_E13_RESETVAL (0x00000000u)
/*----E13 Tokens----*/
#define CSL_EDMA3CC_ESR_E13_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_ESR_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_ESR_E12_RESETVAL (0x00000000u)
/*----E12 Tokens----*/
#define CSL_EDMA3CC_ESR_E12_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_ESR_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_ESR_E11_RESETVAL (0x00000000u)
/*----E11 Tokens----*/
#define CSL_EDMA3CC_ESR_E11_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_ESR_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_ESR_E10_RESETVAL (0x00000000u)
/*----E10 Tokens----*/
#define CSL_EDMA3CC_ESR_E10_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_ESR_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_ESR_E9_RESETVAL (0x00000000u)
/*----E9 Tokens----*/
#define CSL_EDMA3CC_ESR_E9_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_ESR_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_ESR_E8_RESETVAL (0x00000000u)
/*----E8 Tokens----*/
#define CSL_EDMA3CC_ESR_E8_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_ESR_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_ESR_E7_RESETVAL (0x00000000u)
/*----E7 Tokens----*/
#define CSL_EDMA3CC_ESR_E7_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_ESR_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_ESR_E6_RESETVAL (0x00000000u)
/*----E6 Tokens----*/
#define CSL_EDMA3CC_ESR_E6_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_ESR_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_ESR_E5_RESETVAL (0x00000000u)
/*----E5 Tokens----*/
#define CSL_EDMA3CC_ESR_E5_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_ESR_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_ESR_E4_RESETVAL (0x00000000u)
/*----E4 Tokens----*/
#define CSL_EDMA3CC_ESR_E4_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_ESR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_ESR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_ESR_E3_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_ESR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_ESR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_ESR_E2_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_ESR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_ESR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_ESR_E1_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_ESR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ESR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_ESR_E0_SET (0x00000001u)
#define CSL_EDMA3CC_ESR_RESETVAL (0x00000000u)
/* ESRH */
#define CSL_EDMA3CC_ESRH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_ESRH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_ESRH_E63_RESETVAL (0x00000000u)
/*----E63 Tokens----*/
#define CSL_EDMA3CC_ESRH_E63_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_ESRH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_ESRH_E62_RESETVAL (0x00000000u)
/*----E62 Tokens----*/
#define CSL_EDMA3CC_ESRH_E62_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_ESRH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_ESRH_E61_RESETVAL (0x00000000u)
/*----E61 Tokens----*/
#define CSL_EDMA3CC_ESRH_E61_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_ESRH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_ESRH_E60_RESETVAL (0x00000000u)
/*----E60 Tokens----*/
#define CSL_EDMA3CC_ESRH_E60_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_ESRH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_ESRH_E59_RESETVAL (0x00000000u)
/*----E59 Tokens----*/
#define CSL_EDMA3CC_ESRH_E59_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_ESRH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_ESRH_E58_RESETVAL (0x00000000u)
/*----E58 Tokens----*/
#define CSL_EDMA3CC_ESRH_E58_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_ESRH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_ESRH_E57_RESETVAL (0x00000000u)
/*----E57 Tokens----*/
#define CSL_EDMA3CC_ESRH_E57_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_ESRH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_ESRH_E56_RESETVAL (0x00000000u)
/*----E56 Tokens----*/
#define CSL_EDMA3CC_ESRH_E56_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_ESRH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_ESRH_E55_RESETVAL (0x00000000u)
/*----E55 Tokens----*/
#define CSL_EDMA3CC_ESRH_E55_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_ESRH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_ESRH_E54_RESETVAL (0x00000000u)
/*----E54 Tokens----*/
#define CSL_EDMA3CC_ESRH_E54_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_ESRH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_ESRH_E53_RESETVAL (0x00000000u)
/*----E53 Tokens----*/
#define CSL_EDMA3CC_ESRH_E53_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_ESRH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_ESRH_E52_RESETVAL (0x00000000u)
/*----E52 Tokens----*/
#define CSL_EDMA3CC_ESRH_E52_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_ESRH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_ESRH_E51_RESETVAL (0x00000000u)
/*----E51 Tokens----*/
#define CSL_EDMA3CC_ESRH_E51_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_ESRH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_ESRH_E50_RESETVAL (0x00000000u)
/*----E50 Tokens----*/
#define CSL_EDMA3CC_ESRH_E50_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_ESRH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_ESRH_E49_RESETVAL (0x00000000u)
/*----E49 Tokens----*/
#define CSL_EDMA3CC_ESRH_E49_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_ESRH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_ESRH_E48_RESETVAL (0x00000000u)
/*----E48 Tokens----*/
#define CSL_EDMA3CC_ESRH_E48_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_ESRH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_ESRH_E47_RESETVAL (0x00000000u)
/*----E47 Tokens----*/
#define CSL_EDMA3CC_ESRH_E47_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_ESRH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_ESRH_E46_RESETVAL (0x00000000u)
/*----E46 Tokens----*/
#define CSL_EDMA3CC_ESRH_E46_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_ESRH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_ESRH_E45_RESETVAL (0x00000000u)
/*----E45 Tokens----*/
#define CSL_EDMA3CC_ESRH_E45_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_ESRH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_ESRH_E44_RESETVAL (0x00000000u)
/*----E44 Tokens----*/
#define CSL_EDMA3CC_ESRH_E44_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_ESRH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_ESRH_E43_RESETVAL (0x00000000u)
/*----E43 Tokens----*/
#define CSL_EDMA3CC_ESRH_E43_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_ESRH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_ESRH_E42_RESETVAL (0x00000000u)
/*----E42 Tokens----*/
#define CSL_EDMA3CC_ESRH_E42_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_ESRH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_ESRH_E41_RESETVAL (0x00000000u)
/*----E41 Tokens----*/
#define CSL_EDMA3CC_ESRH_E41_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_ESRH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_ESRH_E40_RESETVAL (0x00000000u)
/*----E40 Tokens----*/
#define CSL_EDMA3CC_ESRH_E40_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_ESRH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_ESRH_E39_RESETVAL (0x00000000u)
/*----E39 Tokens----*/
#define CSL_EDMA3CC_ESRH_E39_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_ESRH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_ESRH_E38_RESETVAL (0x00000000u)
/*----E38 Tokens----*/
#define CSL_EDMA3CC_ESRH_E38_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_ESRH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_ESRH_E37_RESETVAL (0x00000000u)
/*----E37 Tokens----*/
#define CSL_EDMA3CC_ESRH_E37_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_ESRH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_ESRH_E36_RESETVAL (0x00000000u)
/*----E36 Tokens----*/
#define CSL_EDMA3CC_ESRH_E36_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_ESRH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_ESRH_E35_RESETVAL (0x00000000u)
/*----E35 Tokens----*/
#define CSL_EDMA3CC_ESRH_E35_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_ESRH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_ESRH_E34_RESETVAL (0x00000000u)
/*----E34 Tokens----*/
#define CSL_EDMA3CC_ESRH_E34_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_ESRH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_ESRH_E33_RESETVAL (0x00000000u)
/*----E33 Tokens----*/
#define CSL_EDMA3CC_ESRH_E33_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_ESRH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ESRH_E32_RESETVAL (0x00000000u)
/*----E32 Tokens----*/
#define CSL_EDMA3CC_ESRH_E32_SET (0x00000001u)
#define CSL_EDMA3CC_ESRH_RESETVAL (0x00000000u)
/* CER */
#define CSL_EDMA3CC_CER_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_CER_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_CER_E31_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_CER_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_CER_E30_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_CER_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_CER_E29_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_CER_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_CER_E28_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_CER_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_CER_E27_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_CER_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_CER_E26_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_CER_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_CER_E25_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_CER_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_CER_E24_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_CER_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_CER_E23_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_CER_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_CER_E22_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_CER_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_CER_E21_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_CER_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_CER_E20_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_CER_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_CER_E19_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_CER_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_CER_E18_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_CER_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_CER_E17_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_CER_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_CER_E16_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_CER_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_CER_E15_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_CER_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_CER_E14_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_CER_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_CER_E13_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_CER_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_CER_E12_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_CER_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_CER_E11_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_CER_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_CER_E10_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_CER_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_CER_E9_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_CER_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_CER_E8_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_CER_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_CER_E7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_CER_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_CER_E6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_CER_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_CER_E5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_CER_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_CER_E4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_CER_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_CER_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_CER_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_CER_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_CER_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_CER_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_CER_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CER_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_RESETVAL (0x00000000u)
/* CERH */
#define CSL_EDMA3CC_CERH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_CERH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_CERH_E63_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_CERH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_CERH_E62_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_CERH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_CERH_E61_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_CERH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_CERH_E60_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_CERH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_CERH_E59_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_CERH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_CERH_E58_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_CERH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_CERH_E57_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_CERH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_CERH_E56_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_CERH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_CERH_E55_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_CERH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_CERH_E54_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_CERH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_CERH_E53_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_CERH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_CERH_E52_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_CERH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_CERH_E51_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_CERH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_CERH_E50_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_CERH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_CERH_E49_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_CERH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_CERH_E48_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_CERH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_CERH_E47_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_CERH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_CERH_E46_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_CERH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_CERH_E45_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_CERH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_CERH_E44_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_CERH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_CERH_E43_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_CERH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_CERH_E42_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_CERH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_CERH_E41_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_CERH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_CERH_E40_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_CERH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_CERH_E39_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_CERH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_CERH_E38_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_CERH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_CERH_E37_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_CERH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_CERH_E36_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_CERH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_CERH_E35_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_CERH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_CERH_E34_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_CERH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_CERH_E33_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_CERH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CERH_E32_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_RESETVAL (0x00000000u)
/* EER */
#define CSL_EDMA3CC_EER_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_EER_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EER_E31_RESETVAL (0x00000000u)
/*----E31 Tokens----*/
#define CSL_EDMA3CC_EER_E31_ (0x00000001u)
#define CSL_EDMA3CC_EER_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_EER_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EER_E30_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_EER_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EER_E29_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_EER_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EER_E28_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_EER_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EER_E27_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_EER_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EER_E26_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_EER_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EER_E25_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_EER_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EER_E24_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_EER_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EER_E23_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_EER_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EER_E22_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_EER_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EER_E21_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_EER_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EER_E20_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_EER_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EER_E19_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_EER_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EER_E18_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_EER_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EER_E17_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_EER_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EER_E16_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_EER_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EER_E15_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_EER_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EER_E14_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_EER_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EER_E13_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_EER_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EER_E12_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_EER_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EER_E11_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_EER_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EER_E10_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_EER_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EER_E9_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_EER_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EER_E8_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_EER_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EER_E7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_EER_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EER_E6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_EER_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EER_E5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_EER_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EER_E4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_EER_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EER_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_EER_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EER_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_EER_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EER_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_EER_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EER_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_RESETVAL (0x00000000u)
/* EERH */
#define CSL_EDMA3CC_EERH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_EERH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EERH_E63_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_EERH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EERH_E62_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_EERH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EERH_E61_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_EERH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EERH_E60_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_EERH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EERH_E59_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_EERH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EERH_E58_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_EERH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EERH_E57_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_EERH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EERH_E56_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_EERH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EERH_E55_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_EERH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EERH_E54_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_EERH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EERH_E53_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_EERH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EERH_E52_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_EERH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EERH_E51_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_EERH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EERH_E50_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_EERH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EERH_E49_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_EERH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EERH_E48_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_EERH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EERH_E47_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_EERH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EERH_E46_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_EERH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EERH_E45_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_EERH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EERH_E44_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_EERH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EERH_E43_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_EERH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EERH_E42_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_EERH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EERH_E41_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_EERH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EERH_E40_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_EERH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EERH_E39_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_EERH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EERH_E38_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_EERH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EERH_E37_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_EERH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EERH_E36_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_EERH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EERH_E35_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_EERH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EERH_E34_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_EERH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EERH_E33_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_EERH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EERH_E32_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_RESETVAL (0x00000000u)
/* EECR */
#define CSL_EDMA3CC_EECR_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_EECR_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EECR_E31_RESETVAL (0x00000000u)
/*----E31 Tokens----*/
#define CSL_EDMA3CC_EECR_E31_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_EECR_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EECR_E30_RESETVAL (0x00000000u)
/*----E30 Tokens----*/
#define CSL_EDMA3CC_EECR_E30_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_EECR_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EECR_E29_RESETVAL (0x00000000u)
/*----E29 Tokens----*/
#define CSL_EDMA3CC_EECR_E29_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_EECR_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EECR_E28_RESETVAL (0x00000000u)
/*----E28 Tokens----*/
#define CSL_EDMA3CC_EECR_E28_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_EECR_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EECR_E27_RESETVAL (0x00000000u)
/*----E27 Tokens----*/
#define CSL_EDMA3CC_EECR_E27_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_EECR_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EECR_E26_RESETVAL (0x00000000u)
/*----E26 Tokens----*/
#define CSL_EDMA3CC_EECR_E26_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_EECR_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EECR_E25_RESETVAL (0x00000000u)
/*----E25 Tokens----*/
#define CSL_EDMA3CC_EECR_E25_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_EECR_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EECR_E24_RESETVAL (0x00000000u)
/*----E24 Tokens----*/
#define CSL_EDMA3CC_EECR_E24_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_EECR_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EECR_E23_RESETVAL (0x00000000u)
/*----E23 Tokens----*/
#define CSL_EDMA3CC_EECR_E23_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_EECR_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EECR_E22_RESETVAL (0x00000000u)
/*----E22 Tokens----*/
#define CSL_EDMA3CC_EECR_E22_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_EECR_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EECR_E21_RESETVAL (0x00000000u)
/*----E21 Tokens----*/
#define CSL_EDMA3CC_EECR_E21_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_EECR_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EECR_E20_RESETVAL (0x00000000u)
/*----E20 Tokens----*/
#define CSL_EDMA3CC_EECR_E20_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_EECR_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EECR_E19_RESETVAL (0x00000000u)
/*----E19 Tokens----*/
#define CSL_EDMA3CC_EECR_E19_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_EECR_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EECR_E18_RESETVAL (0x00000000u)
/*----E18 Tokens----*/
#define CSL_EDMA3CC_EECR_E18_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_EECR_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EECR_E17_RESETVAL (0x00000000u)
/*----E17 Tokens----*/
#define CSL_EDMA3CC_EECR_E17_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_EECR_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EECR_E16_RESETVAL (0x00000000u)
/*----E16 Tokens----*/
#define CSL_EDMA3CC_EECR_E16_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_EECR_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EECR_E15_RESETVAL (0x00000000u)
/*----E15 Tokens----*/
#define CSL_EDMA3CC_EECR_E15_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_EECR_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EECR_E14_RESETVAL (0x00000000u)
/*----E14 Tokens----*/
#define CSL_EDMA3CC_EECR_E14_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_EECR_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EECR_E13_RESETVAL (0x00000000u)
/*----E13 Tokens----*/
#define CSL_EDMA3CC_EECR_E13_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_EECR_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EECR_E12_RESETVAL (0x00000000u)
/*----E12 Tokens----*/
#define CSL_EDMA3CC_EECR_E12_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_EECR_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EECR_E11_RESETVAL (0x00000000u)
/*----E11 Tokens----*/
#define CSL_EDMA3CC_EECR_E11_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_EECR_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EECR_E10_RESETVAL (0x00000000u)
/*----E10 Tokens----*/
#define CSL_EDMA3CC_EECR_E10_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_EECR_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EECR_E9_RESETVAL (0x00000000u)
/*----E9 Tokens----*/
#define CSL_EDMA3CC_EECR_E9_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_EECR_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EECR_E8_RESETVAL (0x00000000u)
/*----E8 Tokens----*/
#define CSL_EDMA3CC_EECR_E8_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_EECR_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EECR_E7_RESETVAL (0x00000000u)
/*----E7 Tokens----*/
#define CSL_EDMA3CC_EECR_E7_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_EECR_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EECR_E6_RESETVAL (0x00000000u)
/*----E6 Tokens----*/
#define CSL_EDMA3CC_EECR_E6_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_EECR_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EECR_E5_RESETVAL (0x00000000u)
/*----E5 Tokens----*/
#define CSL_EDMA3CC_EECR_E5_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_EECR_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EECR_E4_RESETVAL (0x00000000u)
/*----E4 Tokens----*/
#define CSL_EDMA3CC_EECR_E4_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_EECR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EECR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_EECR_E3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_EECR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EECR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_EECR_E2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_EECR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EECR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_EECR_E1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_EECR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EECR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_EECR_E0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECR_RESETVAL (0x00000000u)
/* EECRH */
#define CSL_EDMA3CC_EECRH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_EECRH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EECRH_E63_RESETVAL (0x00000000u)
/*----E63 Tokens----*/
#define CSL_EDMA3CC_EECRH_E63_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_EECRH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EECRH_E62_RESETVAL (0x00000000u)
/*----E62 Tokens----*/
#define CSL_EDMA3CC_EECRH_E62_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_EECRH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EECRH_E61_RESETVAL (0x00000000u)
/*----E61 Tokens----*/
#define CSL_EDMA3CC_EECRH_E61_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_EECRH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EECRH_E60_RESETVAL (0x00000000u)
/*----E60 Tokens----*/
#define CSL_EDMA3CC_EECRH_E60_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_EECRH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EECRH_E59_RESETVAL (0x00000000u)
/*----E59 Tokens----*/
#define CSL_EDMA3CC_EECRH_E59_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_EECRH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EECRH_E58_RESETVAL (0x00000000u)
/*----E58 Tokens----*/
#define CSL_EDMA3CC_EECRH_E58_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_EECRH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EECRH_E57_RESETVAL (0x00000000u)
/*----E57 Tokens----*/
#define CSL_EDMA3CC_EECRH_E57_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_EECRH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EECRH_E56_RESETVAL (0x00000000u)
/*----E56 Tokens----*/
#define CSL_EDMA3CC_EECRH_E56_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_EECRH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EECRH_E55_RESETVAL (0x00000000u)
/*----E55 Tokens----*/
#define CSL_EDMA3CC_EECRH_E55_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_EECRH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EECRH_E54_RESETVAL (0x00000000u)
/*----E54 Tokens----*/
#define CSL_EDMA3CC_EECRH_E54_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_EECRH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EECRH_E53_RESETVAL (0x00000000u)
/*----E53 Tokens----*/
#define CSL_EDMA3CC_EECRH_E53_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_EECRH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EECRH_E52_RESETVAL (0x00000000u)
/*----E52 Tokens----*/
#define CSL_EDMA3CC_EECRH_E52_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_EECRH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EECRH_E51_RESETVAL (0x00000000u)
/*----E51 Tokens----*/
#define CSL_EDMA3CC_EECRH_E51_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_EECRH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EECRH_E50_RESETVAL (0x00000000u)
/*----E50 Tokens----*/
#define CSL_EDMA3CC_EECRH_E50_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_EECRH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EECRH_E49_RESETVAL (0x00000000u)
/*----E49 Tokens----*/
#define CSL_EDMA3CC_EECRH_E49_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_EECRH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EECRH_E48_RESETVAL (0x00000000u)
/*----E48 Tokens----*/
#define CSL_EDMA3CC_EECRH_E48_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_EECRH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EECRH_E47_RESETVAL (0x00000000u)
/*----E47 Tokens----*/
#define CSL_EDMA3CC_EECRH_E47_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_EECRH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EECRH_E46_RESETVAL (0x00000000u)
/*----E46 Tokens----*/
#define CSL_EDMA3CC_EECRH_E46_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_EECRH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EECRH_E45_RESETVAL (0x00000000u)
/*----E45 Tokens----*/
#define CSL_EDMA3CC_EECRH_E45_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_EECRH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EECRH_E44_RESETVAL (0x00000000u)
/*----E44 Tokens----*/
#define CSL_EDMA3CC_EECRH_E44_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_EECRH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EECRH_E43_RESETVAL (0x00000000u)
/*----E43 Tokens----*/
#define CSL_EDMA3CC_EECRH_E43_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_EECRH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EECRH_E42_RESETVAL (0x00000000u)
/*----E42 Tokens----*/
#define CSL_EDMA3CC_EECRH_E42_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_EECRH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EECRH_E41_RESETVAL (0x00000000u)
/*----E41 Tokens----*/
#define CSL_EDMA3CC_EECRH_E41_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_EECRH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EECRH_E40_RESETVAL (0x00000000u)
/*----E40 Tokens----*/
#define CSL_EDMA3CC_EECRH_E40_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_EECRH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EECRH_E39_RESETVAL (0x00000000u)
/*----E39 Tokens----*/
#define CSL_EDMA3CC_EECRH_E39_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_EECRH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EECRH_E38_RESETVAL (0x00000000u)
/*----E38 Tokens----*/
#define CSL_EDMA3CC_EECRH_E38_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_EECRH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EECRH_E37_RESETVAL (0x00000000u)
/*----E37 Tokens----*/
#define CSL_EDMA3CC_EECRH_E37_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_EECRH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EECRH_E36_RESETVAL (0x00000000u)
/*----E36 Tokens----*/
#define CSL_EDMA3CC_EECRH_E36_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_EECRH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EECRH_E35_RESETVAL (0x00000000u)
/*----E35 Tokens----*/
#define CSL_EDMA3CC_EECRH_E35_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_EECRH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EECRH_E34_RESETVAL (0x00000000u)
/*----E34 Tokens----*/
#define CSL_EDMA3CC_EECRH_E34_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_EECRH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EECRH_E33_RESETVAL (0x00000000u)
/*----E33 Tokens----*/
#define CSL_EDMA3CC_EECRH_E33_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_EECRH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EECRH_E32_RESETVAL (0x00000000u)
/*----E32 Tokens----*/
#define CSL_EDMA3CC_EECRH_E32_CLEAR (0x00000001u)
#define CSL_EDMA3CC_EECRH_RESETVAL (0x00000000u)
/* EESR */
#define CSL_EDMA3CC_EESR_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_EESR_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EESR_E31_RESETVAL (0x00000000u)
/*----E31 Tokens----*/
#define CSL_EDMA3CC_EESR_E31_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_EESR_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EESR_E30_RESETVAL (0x00000000u)
/*----E30 Tokens----*/
#define CSL_EDMA3CC_EESR_E30_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_EESR_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EESR_E29_RESETVAL (0x00000000u)
/*----E29 Tokens----*/
#define CSL_EDMA3CC_EESR_E29_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_EESR_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EESR_E28_RESETVAL (0x00000000u)
/*----E28 Tokens----*/
#define CSL_EDMA3CC_EESR_E28_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_EESR_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EESR_E27_RESETVAL (0x00000000u)
/*----E27 Tokens----*/
#define CSL_EDMA3CC_EESR_E27_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_EESR_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EESR_E26_RESETVAL (0x00000000u)
/*----E26 Tokens----*/
#define CSL_EDMA3CC_EESR_E26_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_EESR_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EESR_E25_RESETVAL (0x00000000u)
/*----E25 Tokens----*/
#define CSL_EDMA3CC_EESR_E25_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_EESR_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EESR_E24_RESETVAL (0x00000000u)
/*----E24 Tokens----*/
#define CSL_EDMA3CC_EESR_E24_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_EESR_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EESR_E23_RESETVAL (0x00000000u)
/*----E23 Tokens----*/
#define CSL_EDMA3CC_EESR_E23_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_EESR_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EESR_E22_RESETVAL (0x00000000u)
/*----E22 Tokens----*/
#define CSL_EDMA3CC_EESR_E22_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_EESR_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EESR_E21_RESETVAL (0x00000000u)
/*----E21 Tokens----*/
#define CSL_EDMA3CC_EESR_E21_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_EESR_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EESR_E20_RESETVAL (0x00000000u)
/*----E20 Tokens----*/
#define CSL_EDMA3CC_EESR_E20_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_EESR_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EESR_E19_RESETVAL (0x00000000u)
/*----E19 Tokens----*/
#define CSL_EDMA3CC_EESR_E19_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_EESR_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EESR_E18_RESETVAL (0x00000000u)
/*----E18 Tokens----*/
#define CSL_EDMA3CC_EESR_E18_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_EESR_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EESR_E17_RESETVAL (0x00000000u)
/*----E17 Tokens----*/
#define CSL_EDMA3CC_EESR_E17_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_EESR_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EESR_E16_RESETVAL (0x00000000u)
/*----E16 Tokens----*/
#define CSL_EDMA3CC_EESR_E16_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_EESR_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EESR_E15_RESETVAL (0x00000000u)
/*----E15 Tokens----*/
#define CSL_EDMA3CC_EESR_E15_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_EESR_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EESR_E14_RESETVAL (0x00000000u)
/*----E14 Tokens----*/
#define CSL_EDMA3CC_EESR_E14_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_EESR_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EESR_E13_RESETVAL (0x00000000u)
/*----E13 Tokens----*/
#define CSL_EDMA3CC_EESR_E13_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_EESR_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EESR_E12_RESETVAL (0x00000000u)
/*----E12 Tokens----*/
#define CSL_EDMA3CC_EESR_E12_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_EESR_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EESR_E11_RESETVAL (0x00000000u)
/*----E11 Tokens----*/
#define CSL_EDMA3CC_EESR_E11_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_EESR_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EESR_E10_RESETVAL (0x00000000u)
/*----E10 Tokens----*/
#define CSL_EDMA3CC_EESR_E10_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_EESR_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EESR_E9_RESETVAL (0x00000000u)
/*----E9 Tokens----*/
#define CSL_EDMA3CC_EESR_E9_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_EESR_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EESR_E8_RESETVAL (0x00000000u)
/*----E8 Tokens----*/
#define CSL_EDMA3CC_EESR_E8_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_EESR_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EESR_E7_RESETVAL (0x00000000u)
/*----E7 Tokens----*/
#define CSL_EDMA3CC_EESR_E7_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_EESR_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EESR_E6_RESETVAL (0x00000000u)
/*----E6 Tokens----*/
#define CSL_EDMA3CC_EESR_E6_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_EESR_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EESR_E5_RESETVAL (0x00000000u)
/*----E5 Tokens----*/
#define CSL_EDMA3CC_EESR_E5_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_EESR_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EESR_E4_RESETVAL (0x00000000u)
/*----E4 Tokens----*/
#define CSL_EDMA3CC_EESR_E4_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_EESR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EESR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_EESR_E3_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_EESR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EESR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_EESR_E2_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_EESR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EESR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_EESR_E1_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_EESR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EESR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_EESR_E0_SET (0x00000001u)
#define CSL_EDMA3CC_EESR_RESETVAL (0x00000000u)
/* EESRH */
#define CSL_EDMA3CC_EESRH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_EESRH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_EESRH_E63_RESETVAL (0x00000000u)
/*----E63 Tokens----*/
#define CSL_EDMA3CC_EESRH_E63_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_EESRH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_EESRH_E62_RESETVAL (0x00000000u)
/*----E62 Tokens----*/
#define CSL_EDMA3CC_EESRH_E62_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_EESRH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_EESRH_E61_RESETVAL (0x00000000u)
/*----E61 Tokens----*/
#define CSL_EDMA3CC_EESRH_E61_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_EESRH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_EESRH_E60_RESETVAL (0x00000000u)
/*----E60 Tokens----*/
#define CSL_EDMA3CC_EESRH_E60_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_EESRH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_EESRH_E59_RESETVAL (0x00000000u)
/*----E59 Tokens----*/
#define CSL_EDMA3CC_EESRH_E59_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_EESRH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_EESRH_E58_RESETVAL (0x00000000u)
/*----E58 Tokens----*/
#define CSL_EDMA3CC_EESRH_E58_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_EESRH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_EESRH_E57_RESETVAL (0x00000000u)
/*----E57 Tokens----*/
#define CSL_EDMA3CC_EESRH_E57_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_EESRH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_EESRH_E56_RESETVAL (0x00000000u)
/*----E56 Tokens----*/
#define CSL_EDMA3CC_EESRH_E56_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_EESRH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_EESRH_E55_RESETVAL (0x00000000u)
/*----E55 Tokens----*/
#define CSL_EDMA3CC_EESRH_E55_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_EESRH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_EESRH_E54_RESETVAL (0x00000000u)
/*----E54 Tokens----*/
#define CSL_EDMA3CC_EESRH_E54_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_EESRH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_EESRH_E53_RESETVAL (0x00000000u)
/*----E53 Tokens----*/
#define CSL_EDMA3CC_EESRH_E53_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_EESRH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_EESRH_E52_RESETVAL (0x00000000u)
/*----E52 Tokens----*/
#define CSL_EDMA3CC_EESRH_E52_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_EESRH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_EESRH_E51_RESETVAL (0x00000000u)
/*----E51 Tokens----*/
#define CSL_EDMA3CC_EESRH_E51_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_EESRH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_EESRH_E50_RESETVAL (0x00000000u)
/*----E50 Tokens----*/
#define CSL_EDMA3CC_EESRH_E50_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_EESRH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_EESRH_E49_RESETVAL (0x00000000u)
/*----E49 Tokens----*/
#define CSL_EDMA3CC_EESRH_E49_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_EESRH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_EESRH_E48_RESETVAL (0x00000000u)
/*----E48 Tokens----*/
#define CSL_EDMA3CC_EESRH_E48_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_EESRH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_EESRH_E47_RESETVAL (0x00000000u)
/*----E47 Tokens----*/
#define CSL_EDMA3CC_EESRH_E47_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_EESRH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_EESRH_E46_RESETVAL (0x00000000u)
/*----E46 Tokens----*/
#define CSL_EDMA3CC_EESRH_E46_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_EESRH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_EESRH_E45_RESETVAL (0x00000000u)
/*----E45 Tokens----*/
#define CSL_EDMA3CC_EESRH_E45_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_EESRH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_EESRH_E44_RESETVAL (0x00000000u)
/*----E44 Tokens----*/
#define CSL_EDMA3CC_EESRH_E44_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_EESRH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_EESRH_E43_RESETVAL (0x00000000u)
/*----E43 Tokens----*/
#define CSL_EDMA3CC_EESRH_E43_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_EESRH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_EESRH_E42_RESETVAL (0x00000000u)
/*----E42 Tokens----*/
#define CSL_EDMA3CC_EESRH_E42_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_EESRH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_EESRH_E41_RESETVAL (0x00000000u)
/*----E41 Tokens----*/
#define CSL_EDMA3CC_EESRH_E41_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_EESRH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_EESRH_E40_RESETVAL (0x00000000u)
/*----E40 Tokens----*/
#define CSL_EDMA3CC_EESRH_E40_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_EESRH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_EESRH_E39_RESETVAL (0x00000000u)
/*----E39 Tokens----*/
#define CSL_EDMA3CC_EESRH_E39_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_EESRH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_EESRH_E38_RESETVAL (0x00000000u)
/*----E38 Tokens----*/
#define CSL_EDMA3CC_EESRH_E38_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_EESRH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_EESRH_E37_RESETVAL (0x00000000u)
/*----E37 Tokens----*/
#define CSL_EDMA3CC_EESRH_E37_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_EESRH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_EESRH_E36_RESETVAL (0x00000000u)
/*----E36 Tokens----*/
#define CSL_EDMA3CC_EESRH_E36_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_EESRH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_EESRH_E35_RESETVAL (0x00000000u)
/*----E35 Tokens----*/
#define CSL_EDMA3CC_EESRH_E35_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_EESRH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_EESRH_E34_RESETVAL (0x00000000u)
/*----E34 Tokens----*/
#define CSL_EDMA3CC_EESRH_E34_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_EESRH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_EESRH_E33_RESETVAL (0x00000000u)
/*----E33 Tokens----*/
#define CSL_EDMA3CC_EESRH_E33_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_EESRH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EESRH_E32_RESETVAL (0x00000000u)
/*----E32 Tokens----*/
#define CSL_EDMA3CC_EESRH_E32_SET (0x00000001u)
#define CSL_EDMA3CC_EESRH_RESETVAL (0x00000000u)
/* SER */
#define CSL_EDMA3CC_SER_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_SER_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_SER_E31_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_SER_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_SER_E30_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_SER_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_SER_E29_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_SER_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_SER_E28_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_SER_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_SER_E27_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_SER_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_SER_E26_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_SER_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_SER_E25_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_SER_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_SER_E24_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_SER_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_SER_E23_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_SER_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_SER_E22_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_SER_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_SER_E21_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_SER_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_SER_E20_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_SER_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_SER_E19_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_SER_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_SER_E18_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_SER_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_SER_E17_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_SER_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_SER_E16_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_SER_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_SER_E15_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_SER_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_SER_E14_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_SER_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_SER_E13_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_SER_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_SER_E12_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_SER_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_SER_E11_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_SER_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_SER_E10_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_SER_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_SER_E9_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_SER_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_SER_E8_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_SER_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_SER_E7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_SER_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_SER_E6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_SER_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_SER_E5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_SER_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_SER_E4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_SER_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_SER_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_SER_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_SER_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_SER_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_SER_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_SER_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SER_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_RESETVAL (0x00000000u)
/* SERH */
#define CSL_EDMA3CC_SERH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_SERH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_SERH_E63_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_SERH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_SERH_E62_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_SERH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_SERH_E61_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_SERH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_SERH_E60_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_SERH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_SERH_E59_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_SERH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_SERH_E58_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_SERH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_SERH_E57_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_SERH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_SERH_E56_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_SERH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_SERH_E55_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_SERH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_SERH_E54_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_SERH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_SERH_E53_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_SERH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_SERH_E52_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_SERH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_SERH_E51_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_SERH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_SERH_E50_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_SERH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_SERH_E49_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_SERH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_SERH_E48_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_SERH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_SERH_E47_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_SERH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_SERH_E46_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_SERH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_SERH_E45_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_SERH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_SERH_E44_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_SERH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_SERH_E43_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_SERH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_SERH_E42_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_SERH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_SERH_E41_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_SERH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_SERH_E40_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_SERH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_SERH_E39_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_SERH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_SERH_E38_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_SERH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_SERH_E37_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_SERH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_SERH_E36_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_SERH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_SERH_E35_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_SERH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_SERH_E34_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_SERH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_SERH_E33_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_SERH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SERH_E32_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_RESETVAL (0x00000000u)
/* SECR */
#define CSL_EDMA3CC_SECR_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_SECR_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_SECR_E31_RESETVAL (0x00000000u)
/*----E31 Tokens----*/
#define CSL_EDMA3CC_SECR_E31_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E30_MASK (0x40000000u)
#define CSL_EDMA3CC_SECR_E30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_SECR_E30_RESETVAL (0x00000000u)
/*----E30 Tokens----*/
#define CSL_EDMA3CC_SECR_E30_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E29_MASK (0x20000000u)
#define CSL_EDMA3CC_SECR_E29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_SECR_E29_RESETVAL (0x00000000u)
/*----E29 Tokens----*/
#define CSL_EDMA3CC_SECR_E29_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E28_MASK (0x10000000u)
#define CSL_EDMA3CC_SECR_E28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_SECR_E28_RESETVAL (0x00000000u)
/*----E28 Tokens----*/
#define CSL_EDMA3CC_SECR_E28_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E27_MASK (0x08000000u)
#define CSL_EDMA3CC_SECR_E27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_SECR_E27_RESETVAL (0x00000000u)
/*----E27 Tokens----*/
#define CSL_EDMA3CC_SECR_E27_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E26_MASK (0x04000000u)
#define CSL_EDMA3CC_SECR_E26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_SECR_E26_RESETVAL (0x00000000u)
/*----E26 Tokens----*/
#define CSL_EDMA3CC_SECR_E26_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E25_MASK (0x02000000u)
#define CSL_EDMA3CC_SECR_E25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_SECR_E25_RESETVAL (0x00000000u)
/*----E25 Tokens----*/
#define CSL_EDMA3CC_SECR_E25_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E24_MASK (0x01000000u)
#define CSL_EDMA3CC_SECR_E24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_SECR_E24_RESETVAL (0x00000000u)
/*----E24 Tokens----*/
#define CSL_EDMA3CC_SECR_E24_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E23_MASK (0x00800000u)
#define CSL_EDMA3CC_SECR_E23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_SECR_E23_RESETVAL (0x00000000u)
/*----E23 Tokens----*/
#define CSL_EDMA3CC_SECR_E23_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E22_MASK (0x00400000u)
#define CSL_EDMA3CC_SECR_E22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_SECR_E22_RESETVAL (0x00000000u)
/*----E22 Tokens----*/
#define CSL_EDMA3CC_SECR_E22_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E21_MASK (0x00200000u)
#define CSL_EDMA3CC_SECR_E21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_SECR_E21_RESETVAL (0x00000000u)
/*----E21 Tokens----*/
#define CSL_EDMA3CC_SECR_E21_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E20_MASK (0x00100000u)
#define CSL_EDMA3CC_SECR_E20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_SECR_E20_RESETVAL (0x00000000u)
/*----E20 Tokens----*/
#define CSL_EDMA3CC_SECR_E20_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E19_MASK (0x00080000u)
#define CSL_EDMA3CC_SECR_E19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_SECR_E19_RESETVAL (0x00000000u)
/*----E19 Tokens----*/
#define CSL_EDMA3CC_SECR_E19_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E18_MASK (0x00040000u)
#define CSL_EDMA3CC_SECR_E18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_SECR_E18_RESETVAL (0x00000000u)
/*----E18 Tokens----*/
#define CSL_EDMA3CC_SECR_E18_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E17_MASK (0x00020000u)
#define CSL_EDMA3CC_SECR_E17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_SECR_E17_RESETVAL (0x00000000u)
/*----E17 Tokens----*/
#define CSL_EDMA3CC_SECR_E17_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E16_MASK (0x00010000u)
#define CSL_EDMA3CC_SECR_E16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_SECR_E16_RESETVAL (0x00000000u)
/*----E16 Tokens----*/
#define CSL_EDMA3CC_SECR_E16_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E15_MASK (0x00008000u)
#define CSL_EDMA3CC_SECR_E15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_SECR_E15_RESETVAL (0x00000000u)
/*----E15 Tokens----*/
#define CSL_EDMA3CC_SECR_E15_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E14_MASK (0x00004000u)
#define CSL_EDMA3CC_SECR_E14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_SECR_E14_RESETVAL (0x00000000u)
/*----E14 Tokens----*/
#define CSL_EDMA3CC_SECR_E14_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E13_MASK (0x00002000u)
#define CSL_EDMA3CC_SECR_E13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_SECR_E13_RESETVAL (0x00000000u)
/*----E13 Tokens----*/
#define CSL_EDMA3CC_SECR_E13_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E12_MASK (0x00001000u)
#define CSL_EDMA3CC_SECR_E12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_SECR_E12_RESETVAL (0x00000000u)
/*----E12 Tokens----*/
#define CSL_EDMA3CC_SECR_E12_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E11_MASK (0x00000800u)
#define CSL_EDMA3CC_SECR_E11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_SECR_E11_RESETVAL (0x00000000u)
/*----E11 Tokens----*/
#define CSL_EDMA3CC_SECR_E11_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E10_MASK (0x00000400u)
#define CSL_EDMA3CC_SECR_E10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_SECR_E10_RESETVAL (0x00000000u)
/*----E10 Tokens----*/
#define CSL_EDMA3CC_SECR_E10_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E9_MASK (0x00000200u)
#define CSL_EDMA3CC_SECR_E9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_SECR_E9_RESETVAL (0x00000000u)
/*----E9 Tokens----*/
#define CSL_EDMA3CC_SECR_E9_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E8_MASK (0x00000100u)
#define CSL_EDMA3CC_SECR_E8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_SECR_E8_RESETVAL (0x00000000u)
/*----E8 Tokens----*/
#define CSL_EDMA3CC_SECR_E8_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E7_MASK (0x00000080u)
#define CSL_EDMA3CC_SECR_E7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_SECR_E7_RESETVAL (0x00000000u)
/*----E7 Tokens----*/
#define CSL_EDMA3CC_SECR_E7_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E6_MASK (0x00000040u)
#define CSL_EDMA3CC_SECR_E6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_SECR_E6_RESETVAL (0x00000000u)
/*----E6 Tokens----*/
#define CSL_EDMA3CC_SECR_E6_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E5_MASK (0x00000020u)
#define CSL_EDMA3CC_SECR_E5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_SECR_E5_RESETVAL (0x00000000u)
/*----E5 Tokens----*/
#define CSL_EDMA3CC_SECR_E5_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E4_MASK (0x00000010u)
#define CSL_EDMA3CC_SECR_E4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_SECR_E4_RESETVAL (0x00000000u)
/*----E4 Tokens----*/
#define CSL_EDMA3CC_SECR_E4_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_SECR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_SECR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_SECR_E3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_SECR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_SECR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_SECR_E2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_SECR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_SECR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_SECR_E1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_SECR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SECR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_SECR_E0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECR_RESETVAL (0x00000000u)
/* SECRH */
#define CSL_EDMA3CC_SECRH_E63_MASK (0x80000000u)
#define CSL_EDMA3CC_SECRH_E63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_SECRH_E63_RESETVAL (0x00000000u)
/*----E63 Tokens----*/
#define CSL_EDMA3CC_SECRH_E63_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E62_MASK (0x40000000u)
#define CSL_EDMA3CC_SECRH_E62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_SECRH_E62_RESETVAL (0x00000000u)
/*----E62 Tokens----*/
#define CSL_EDMA3CC_SECRH_E62_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E61_MASK (0x20000000u)
#define CSL_EDMA3CC_SECRH_E61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_SECRH_E61_RESETVAL (0x00000000u)
/*----E61 Tokens----*/
#define CSL_EDMA3CC_SECRH_E61_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E60_MASK (0x10000000u)
#define CSL_EDMA3CC_SECRH_E60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_SECRH_E60_RESETVAL (0x00000000u)
/*----E60 Tokens----*/
#define CSL_EDMA3CC_SECRH_E60_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E59_MASK (0x08000000u)
#define CSL_EDMA3CC_SECRH_E59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_SECRH_E59_RESETVAL (0x00000000u)
/*----E59 Tokens----*/
#define CSL_EDMA3CC_SECRH_E59_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E58_MASK (0x04000000u)
#define CSL_EDMA3CC_SECRH_E58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_SECRH_E58_RESETVAL (0x00000000u)
/*----E58 Tokens----*/
#define CSL_EDMA3CC_SECRH_E58_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E57_MASK (0x02000000u)
#define CSL_EDMA3CC_SECRH_E57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_SECRH_E57_RESETVAL (0x00000000u)
/*----E57 Tokens----*/
#define CSL_EDMA3CC_SECRH_E57_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E56_MASK (0x01000000u)
#define CSL_EDMA3CC_SECRH_E56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_SECRH_E56_RESETVAL (0x00000000u)
/*----E56 Tokens----*/
#define CSL_EDMA3CC_SECRH_E56_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E55_MASK (0x00800000u)
#define CSL_EDMA3CC_SECRH_E55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_SECRH_E55_RESETVAL (0x00000000u)
/*----E55 Tokens----*/
#define CSL_EDMA3CC_SECRH_E55_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E54_MASK (0x00400000u)
#define CSL_EDMA3CC_SECRH_E54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_SECRH_E54_RESETVAL (0x00000000u)
/*----E54 Tokens----*/
#define CSL_EDMA3CC_SECRH_E54_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E53_MASK (0x00200000u)
#define CSL_EDMA3CC_SECRH_E53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_SECRH_E53_RESETVAL (0x00000000u)
/*----E53 Tokens----*/
#define CSL_EDMA3CC_SECRH_E53_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E52_MASK (0x00100000u)
#define CSL_EDMA3CC_SECRH_E52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_SECRH_E52_RESETVAL (0x00000000u)
/*----E52 Tokens----*/
#define CSL_EDMA3CC_SECRH_E52_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E51_MASK (0x00080000u)
#define CSL_EDMA3CC_SECRH_E51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_SECRH_E51_RESETVAL (0x00000000u)
/*----E51 Tokens----*/
#define CSL_EDMA3CC_SECRH_E51_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E50_MASK (0x00040000u)
#define CSL_EDMA3CC_SECRH_E50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_SECRH_E50_RESETVAL (0x00000000u)
/*----E50 Tokens----*/
#define CSL_EDMA3CC_SECRH_E50_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E49_MASK (0x00020000u)
#define CSL_EDMA3CC_SECRH_E49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_SECRH_E49_RESETVAL (0x00000000u)
/*----E49 Tokens----*/
#define CSL_EDMA3CC_SECRH_E49_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E48_MASK (0x00010000u)
#define CSL_EDMA3CC_SECRH_E48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_SECRH_E48_RESETVAL (0x00000000u)
/*----E48 Tokens----*/
#define CSL_EDMA3CC_SECRH_E48_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E47_MASK (0x00008000u)
#define CSL_EDMA3CC_SECRH_E47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_SECRH_E47_RESETVAL (0x00000000u)
/*----E47 Tokens----*/
#define CSL_EDMA3CC_SECRH_E47_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E46_MASK (0x00004000u)
#define CSL_EDMA3CC_SECRH_E46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_SECRH_E46_RESETVAL (0x00000000u)
/*----E46 Tokens----*/
#define CSL_EDMA3CC_SECRH_E46_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E45_MASK (0x00002000u)
#define CSL_EDMA3CC_SECRH_E45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_SECRH_E45_RESETVAL (0x00000000u)
/*----E45 Tokens----*/
#define CSL_EDMA3CC_SECRH_E45_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E44_MASK (0x00001000u)
#define CSL_EDMA3CC_SECRH_E44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_SECRH_E44_RESETVAL (0x00000000u)
/*----E44 Tokens----*/
#define CSL_EDMA3CC_SECRH_E44_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E43_MASK (0x00000800u)
#define CSL_EDMA3CC_SECRH_E43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_SECRH_E43_RESETVAL (0x00000000u)
/*----E43 Tokens----*/
#define CSL_EDMA3CC_SECRH_E43_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E42_MASK (0x00000400u)
#define CSL_EDMA3CC_SECRH_E42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_SECRH_E42_RESETVAL (0x00000000u)
/*----E42 Tokens----*/
#define CSL_EDMA3CC_SECRH_E42_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E41_MASK (0x00000200u)
#define CSL_EDMA3CC_SECRH_E41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_SECRH_E41_RESETVAL (0x00000000u)
/*----E41 Tokens----*/
#define CSL_EDMA3CC_SECRH_E41_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E40_MASK (0x00000100u)
#define CSL_EDMA3CC_SECRH_E40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_SECRH_E40_RESETVAL (0x00000000u)
/*----E40 Tokens----*/
#define CSL_EDMA3CC_SECRH_E40_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E39_MASK (0x00000080u)
#define CSL_EDMA3CC_SECRH_E39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_SECRH_E39_RESETVAL (0x00000000u)
/*----E39 Tokens----*/
#define CSL_EDMA3CC_SECRH_E39_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E38_MASK (0x00000040u)
#define CSL_EDMA3CC_SECRH_E38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_SECRH_E38_RESETVAL (0x00000000u)
/*----E38 Tokens----*/
#define CSL_EDMA3CC_SECRH_E38_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E37_MASK (0x00000020u)
#define CSL_EDMA3CC_SECRH_E37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_SECRH_E37_RESETVAL (0x00000000u)
/*----E37 Tokens----*/
#define CSL_EDMA3CC_SECRH_E37_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E36_MASK (0x00000010u)
#define CSL_EDMA3CC_SECRH_E36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_SECRH_E36_RESETVAL (0x00000000u)
/*----E36 Tokens----*/
#define CSL_EDMA3CC_SECRH_E36_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E35_MASK (0x00000008u)
#define CSL_EDMA3CC_SECRH_E35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_SECRH_E35_RESETVAL (0x00000000u)
/*----E35 Tokens----*/
#define CSL_EDMA3CC_SECRH_E35_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E34_MASK (0x00000004u)
#define CSL_EDMA3CC_SECRH_E34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_SECRH_E34_RESETVAL (0x00000000u)
/*----E34 Tokens----*/
#define CSL_EDMA3CC_SECRH_E34_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E33_MASK (0x00000002u)
#define CSL_EDMA3CC_SECRH_E33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_SECRH_E33_RESETVAL (0x00000000u)
/*----E33 Tokens----*/
#define CSL_EDMA3CC_SECRH_E33_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_E32_MASK (0x00000001u)
#define CSL_EDMA3CC_SECRH_E32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SECRH_E32_RESETVAL (0x00000000u)
/*----E32 Tokens----*/
#define CSL_EDMA3CC_SECRH_E32_CLEAR (0x00000001u)
#define CSL_EDMA3CC_SECRH_RESETVAL (0x00000000u)
/* IER */
#define CSL_EDMA3CC_IER_I31_MASK (0x80000000u)
#define CSL_EDMA3CC_IER_I31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_IER_I31_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I30_MASK (0x40000000u)
#define CSL_EDMA3CC_IER_I30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_IER_I30_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I29_MASK (0x20000000u)
#define CSL_EDMA3CC_IER_I29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_IER_I29_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I28_MASK (0x10000000u)
#define CSL_EDMA3CC_IER_I28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_IER_I28_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I27_MASK (0x08000000u)
#define CSL_EDMA3CC_IER_I27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_IER_I27_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I26_MASK (0x04000000u)
#define CSL_EDMA3CC_IER_I26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_IER_I26_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I25_MASK (0x02000000u)
#define CSL_EDMA3CC_IER_I25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_IER_I25_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I24_MASK (0x01000000u)
#define CSL_EDMA3CC_IER_I24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_IER_I24_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I23_MASK (0x00800000u)
#define CSL_EDMA3CC_IER_I23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_IER_I23_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I22_MASK (0x00400000u)
#define CSL_EDMA3CC_IER_I22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_IER_I22_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I21_MASK (0x00200000u)
#define CSL_EDMA3CC_IER_I21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_IER_I21_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I20_MASK (0x00100000u)
#define CSL_EDMA3CC_IER_I20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_IER_I20_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I19_MASK (0x00080000u)
#define CSL_EDMA3CC_IER_I19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_IER_I19_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I18_MASK (0x00040000u)
#define CSL_EDMA3CC_IER_I18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_IER_I18_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I17_MASK (0x00020000u)
#define CSL_EDMA3CC_IER_I17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_IER_I17_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I16_MASK (0x00010000u)
#define CSL_EDMA3CC_IER_I16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_IER_I16_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I15_MASK (0x00008000u)
#define CSL_EDMA3CC_IER_I15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_IER_I15_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I14_MASK (0x00004000u)
#define CSL_EDMA3CC_IER_I14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_IER_I14_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I13_MASK (0x00002000u)
#define CSL_EDMA3CC_IER_I13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_IER_I13_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I12_MASK (0x00001000u)
#define CSL_EDMA3CC_IER_I12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_IER_I12_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I11_MASK (0x00000800u)
#define CSL_EDMA3CC_IER_I11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_IER_I11_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I10_MASK (0x00000400u)
#define CSL_EDMA3CC_IER_I10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_IER_I10_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I9_MASK (0x00000200u)
#define CSL_EDMA3CC_IER_I9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_IER_I9_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I8_MASK (0x00000100u)
#define CSL_EDMA3CC_IER_I8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_IER_I8_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I7_MASK (0x00000080u)
#define CSL_EDMA3CC_IER_I7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_IER_I7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I6_MASK (0x00000040u)
#define CSL_EDMA3CC_IER_I6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_IER_I6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I5_MASK (0x00000020u)
#define CSL_EDMA3CC_IER_I5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_IER_I5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I4_MASK (0x00000010u)
#define CSL_EDMA3CC_IER_I4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_IER_I4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I3_MASK (0x00000008u)
#define CSL_EDMA3CC_IER_I3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_IER_I3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I2_MASK (0x00000004u)
#define CSL_EDMA3CC_IER_I2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_IER_I2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I1_MASK (0x00000002u)
#define CSL_EDMA3CC_IER_I1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_IER_I1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_I0_MASK (0x00000001u)
#define CSL_EDMA3CC_IER_I0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IER_I0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_RESETVAL (0x00000000u)
/* IERH */
#define CSL_EDMA3CC_IERH_I63_MASK (0x80000000u)
#define CSL_EDMA3CC_IERH_I63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_IERH_I63_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I62_MASK (0x40000000u)
#define CSL_EDMA3CC_IERH_I62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_IERH_I62_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I61_MASK (0x20000000u)
#define CSL_EDMA3CC_IERH_I61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_IERH_I61_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I60_MASK (0x10000000u)
#define CSL_EDMA3CC_IERH_I60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_IERH_I60_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I59_MASK (0x08000000u)
#define CSL_EDMA3CC_IERH_I59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_IERH_I59_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I58_MASK (0x04000000u)
#define CSL_EDMA3CC_IERH_I58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_IERH_I58_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I57_MASK (0x02000000u)
#define CSL_EDMA3CC_IERH_I57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_IERH_I57_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I56_MASK (0x01000000u)
#define CSL_EDMA3CC_IERH_I56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_IERH_I56_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I55_MASK (0x00800000u)
#define CSL_EDMA3CC_IERH_I55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_IERH_I55_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I54_MASK (0x00400000u)
#define CSL_EDMA3CC_IERH_I54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_IERH_I54_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I53_MASK (0x00200000u)
#define CSL_EDMA3CC_IERH_I53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_IERH_I53_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I52_MASK (0x00100000u)
#define CSL_EDMA3CC_IERH_I52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_IERH_I52_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I51_MASK (0x00080000u)
#define CSL_EDMA3CC_IERH_I51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_IERH_I51_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I50_MASK (0x00040000u)
#define CSL_EDMA3CC_IERH_I50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_IERH_I50_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I49_MASK (0x00020000u)
#define CSL_EDMA3CC_IERH_I49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_IERH_I49_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I48_MASK (0x00010000u)
#define CSL_EDMA3CC_IERH_I48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_IERH_I48_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I47_MASK (0x00008000u)
#define CSL_EDMA3CC_IERH_I47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_IERH_I47_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I46_MASK (0x00004000u)
#define CSL_EDMA3CC_IERH_I46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_IERH_I46_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I45_MASK (0x00002000u)
#define CSL_EDMA3CC_IERH_I45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_IERH_I45_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I44_MASK (0x00001000u)
#define CSL_EDMA3CC_IERH_I44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_IERH_I44_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I43_MASK (0x00000800u)
#define CSL_EDMA3CC_IERH_I43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_IERH_I43_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I42_MASK (0x00000400u)
#define CSL_EDMA3CC_IERH_I42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_IERH_I42_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I41_MASK (0x00000200u)
#define CSL_EDMA3CC_IERH_I41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_IERH_I41_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I40_MASK (0x00000100u)
#define CSL_EDMA3CC_IERH_I40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_IERH_I40_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I39_MASK (0x00000080u)
#define CSL_EDMA3CC_IERH_I39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_IERH_I39_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I38_MASK (0x00000040u)
#define CSL_EDMA3CC_IERH_I38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_IERH_I38_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I37_MASK (0x00000020u)
#define CSL_EDMA3CC_IERH_I37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_IERH_I37_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I36_MASK (0x00000010u)
#define CSL_EDMA3CC_IERH_I36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_IERH_I36_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I35_MASK (0x00000008u)
#define CSL_EDMA3CC_IERH_I35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_IERH_I35_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I34_MASK (0x00000004u)
#define CSL_EDMA3CC_IERH_I34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_IERH_I34_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I33_MASK (0x00000002u)
#define CSL_EDMA3CC_IERH_I33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_IERH_I33_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_I32_MASK (0x00000001u)
#define CSL_EDMA3CC_IERH_I32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IERH_I32_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_RESETVAL (0x00000000u)
/* IECR */
#define CSL_EDMA3CC_IECR_I31_MASK (0x80000000u)
#define CSL_EDMA3CC_IECR_I31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_IECR_I31_RESETVAL (0x00000000u)
/*----I31 Tokens----*/
#define CSL_EDMA3CC_IECR_I31_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I30_MASK (0x40000000u)
#define CSL_EDMA3CC_IECR_I30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_IECR_I30_RESETVAL (0x00000000u)
/*----I30 Tokens----*/
#define CSL_EDMA3CC_IECR_I30_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I29_MASK (0x20000000u)
#define CSL_EDMA3CC_IECR_I29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_IECR_I29_RESETVAL (0x00000000u)
/*----I29 Tokens----*/
#define CSL_EDMA3CC_IECR_I29_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I28_MASK (0x10000000u)
#define CSL_EDMA3CC_IECR_I28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_IECR_I28_RESETVAL (0x00000000u)
/*----I28 Tokens----*/
#define CSL_EDMA3CC_IECR_I28_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I27_MASK (0x08000000u)
#define CSL_EDMA3CC_IECR_I27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_IECR_I27_RESETVAL (0x00000000u)
/*----I27 Tokens----*/
#define CSL_EDMA3CC_IECR_I27_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I26_MASK (0x04000000u)
#define CSL_EDMA3CC_IECR_I26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_IECR_I26_RESETVAL (0x00000000u)
/*----I26 Tokens----*/
#define CSL_EDMA3CC_IECR_I26_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I25_MASK (0x02000000u)
#define CSL_EDMA3CC_IECR_I25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_IECR_I25_RESETVAL (0x00000000u)
/*----I25 Tokens----*/
#define CSL_EDMA3CC_IECR_I25_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I24_MASK (0x01000000u)
#define CSL_EDMA3CC_IECR_I24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_IECR_I24_RESETVAL (0x00000000u)
/*----I24 Tokens----*/
#define CSL_EDMA3CC_IECR_I24_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I23_MASK (0x00800000u)
#define CSL_EDMA3CC_IECR_I23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_IECR_I23_RESETVAL (0x00000000u)
/*----I23 Tokens----*/
#define CSL_EDMA3CC_IECR_I23_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I22_MASK (0x00400000u)
#define CSL_EDMA3CC_IECR_I22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_IECR_I22_RESETVAL (0x00000000u)
/*----I22 Tokens----*/
#define CSL_EDMA3CC_IECR_I22_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I21_MASK (0x00200000u)
#define CSL_EDMA3CC_IECR_I21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_IECR_I21_RESETVAL (0x00000000u)
/*----I21 Tokens----*/
#define CSL_EDMA3CC_IECR_I21_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I20_MASK (0x00100000u)
#define CSL_EDMA3CC_IECR_I20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_IECR_I20_RESETVAL (0x00000000u)
/*----I20 Tokens----*/
#define CSL_EDMA3CC_IECR_I20_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I19_MASK (0x00080000u)
#define CSL_EDMA3CC_IECR_I19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_IECR_I19_RESETVAL (0x00000000u)
/*----I19 Tokens----*/
#define CSL_EDMA3CC_IECR_I19_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I18_MASK (0x00040000u)
#define CSL_EDMA3CC_IECR_I18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_IECR_I18_RESETVAL (0x00000000u)
/*----I18 Tokens----*/
#define CSL_EDMA3CC_IECR_I18_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I17_MASK (0x00020000u)
#define CSL_EDMA3CC_IECR_I17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_IECR_I17_RESETVAL (0x00000000u)
/*----I17 Tokens----*/
#define CSL_EDMA3CC_IECR_I17_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I16_MASK (0x00010000u)
#define CSL_EDMA3CC_IECR_I16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_IECR_I16_RESETVAL (0x00000000u)
/*----I16 Tokens----*/
#define CSL_EDMA3CC_IECR_I16_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I15_MASK (0x00008000u)
#define CSL_EDMA3CC_IECR_I15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_IECR_I15_RESETVAL (0x00000000u)
/*----I15 Tokens----*/
#define CSL_EDMA3CC_IECR_I15_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I14_MASK (0x00004000u)
#define CSL_EDMA3CC_IECR_I14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_IECR_I14_RESETVAL (0x00000000u)
/*----I14 Tokens----*/
#define CSL_EDMA3CC_IECR_I14_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I13_MASK (0x00002000u)
#define CSL_EDMA3CC_IECR_I13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_IECR_I13_RESETVAL (0x00000000u)
/*----I13 Tokens----*/
#define CSL_EDMA3CC_IECR_I13_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I12_MASK (0x00001000u)
#define CSL_EDMA3CC_IECR_I12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_IECR_I12_RESETVAL (0x00000000u)
/*----I12 Tokens----*/
#define CSL_EDMA3CC_IECR_I12_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I11_MASK (0x00000800u)
#define CSL_EDMA3CC_IECR_I11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_IECR_I11_RESETVAL (0x00000000u)
/*----I11 Tokens----*/
#define CSL_EDMA3CC_IECR_I11_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I10_MASK (0x00000400u)
#define CSL_EDMA3CC_IECR_I10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_IECR_I10_RESETVAL (0x00000000u)
/*----I10 Tokens----*/
#define CSL_EDMA3CC_IECR_I10_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I9_MASK (0x00000200u)
#define CSL_EDMA3CC_IECR_I9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_IECR_I9_RESETVAL (0x00000000u)
/*----I9 Tokens----*/
#define CSL_EDMA3CC_IECR_I9_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I8_MASK (0x00000100u)
#define CSL_EDMA3CC_IECR_I8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_IECR_I8_RESETVAL (0x00000000u)
/*----I8 Tokens----*/
#define CSL_EDMA3CC_IECR_I8_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I7_MASK (0x00000080u)
#define CSL_EDMA3CC_IECR_I7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_IECR_I7_RESETVAL (0x00000000u)
/*----I7 Tokens----*/
#define CSL_EDMA3CC_IECR_I7_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I6_MASK (0x00000040u)
#define CSL_EDMA3CC_IECR_I6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_IECR_I6_RESETVAL (0x00000000u)
/*----I6 Tokens----*/
#define CSL_EDMA3CC_IECR_I6_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I5_MASK (0x00000020u)
#define CSL_EDMA3CC_IECR_I5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_IECR_I5_RESETVAL (0x00000000u)
/*----I5 Tokens----*/
#define CSL_EDMA3CC_IECR_I5_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I4_MASK (0x00000010u)
#define CSL_EDMA3CC_IECR_I4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_IECR_I4_RESETVAL (0x00000000u)
/*----I4 Tokens----*/
#define CSL_EDMA3CC_IECR_I4_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I3_MASK (0x00000008u)
#define CSL_EDMA3CC_IECR_I3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_IECR_I3_RESETVAL (0x00000000u)
/*----I3 Tokens----*/
#define CSL_EDMA3CC_IECR_I3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I2_MASK (0x00000004u)
#define CSL_EDMA3CC_IECR_I2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_IECR_I2_RESETVAL (0x00000000u)
/*----I2 Tokens----*/
#define CSL_EDMA3CC_IECR_I2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I1_MASK (0x00000002u)
#define CSL_EDMA3CC_IECR_I1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_IECR_I1_RESETVAL (0x00000000u)
/*----I1 Tokens----*/
#define CSL_EDMA3CC_IECR_I1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_I0_MASK (0x00000001u)
#define CSL_EDMA3CC_IECR_I0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IECR_I0_RESETVAL (0x00000000u)
/*----I0 Tokens----*/
#define CSL_EDMA3CC_IECR_I0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECR_RESETVAL (0x00000000u)
/* IECRH */
#define CSL_EDMA3CC_IECRH_I63_MASK (0x80000000u)
#define CSL_EDMA3CC_IECRH_I63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_IECRH_I63_RESETVAL (0x00000000u)
/*----I63 Tokens----*/
#define CSL_EDMA3CC_IECRH_I63_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I62_MASK (0x40000000u)
#define CSL_EDMA3CC_IECRH_I62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_IECRH_I62_RESETVAL (0x00000000u)
/*----I62 Tokens----*/
#define CSL_EDMA3CC_IECRH_I62_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I61_MASK (0x20000000u)
#define CSL_EDMA3CC_IECRH_I61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_IECRH_I61_RESETVAL (0x00000000u)
/*----I61 Tokens----*/
#define CSL_EDMA3CC_IECRH_I61_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I60_MASK (0x10000000u)
#define CSL_EDMA3CC_IECRH_I60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_IECRH_I60_RESETVAL (0x00000000u)
/*----I60 Tokens----*/
#define CSL_EDMA3CC_IECRH_I60_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I59_MASK (0x08000000u)
#define CSL_EDMA3CC_IECRH_I59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_IECRH_I59_RESETVAL (0x00000000u)
/*----I59 Tokens----*/
#define CSL_EDMA3CC_IECRH_I59_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I58_MASK (0x04000000u)
#define CSL_EDMA3CC_IECRH_I58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_IECRH_I58_RESETVAL (0x00000000u)
/*----I58 Tokens----*/
#define CSL_EDMA3CC_IECRH_I58_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I57_MASK (0x02000000u)
#define CSL_EDMA3CC_IECRH_I57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_IECRH_I57_RESETVAL (0x00000000u)
/*----I57 Tokens----*/
#define CSL_EDMA3CC_IECRH_I57_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I56_MASK (0x01000000u)
#define CSL_EDMA3CC_IECRH_I56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_IECRH_I56_RESETVAL (0x00000000u)
/*----I56 Tokens----*/
#define CSL_EDMA3CC_IECRH_I56_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I55_MASK (0x00800000u)
#define CSL_EDMA3CC_IECRH_I55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_IECRH_I55_RESETVAL (0x00000000u)
/*----I55 Tokens----*/
#define CSL_EDMA3CC_IECRH_I55_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I54_MASK (0x00400000u)
#define CSL_EDMA3CC_IECRH_I54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_IECRH_I54_RESETVAL (0x00000000u)
/*----I54 Tokens----*/
#define CSL_EDMA3CC_IECRH_I54_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I53_MASK (0x00200000u)
#define CSL_EDMA3CC_IECRH_I53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_IECRH_I53_RESETVAL (0x00000000u)
/*----I53 Tokens----*/
#define CSL_EDMA3CC_IECRH_I53_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I52_MASK (0x00100000u)
#define CSL_EDMA3CC_IECRH_I52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_IECRH_I52_RESETVAL (0x00000000u)
/*----I52 Tokens----*/
#define CSL_EDMA3CC_IECRH_I52_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I51_MASK (0x00080000u)
#define CSL_EDMA3CC_IECRH_I51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_IECRH_I51_RESETVAL (0x00000000u)
/*----I51 Tokens----*/
#define CSL_EDMA3CC_IECRH_I51_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I50_MASK (0x00040000u)
#define CSL_EDMA3CC_IECRH_I50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_IECRH_I50_RESETVAL (0x00000000u)
/*----I50 Tokens----*/
#define CSL_EDMA3CC_IECRH_I50_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I49_MASK (0x00020000u)
#define CSL_EDMA3CC_IECRH_I49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_IECRH_I49_RESETVAL (0x00000000u)
/*----I49 Tokens----*/
#define CSL_EDMA3CC_IECRH_I49_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I48_MASK (0x00010000u)
#define CSL_EDMA3CC_IECRH_I48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_IECRH_I48_RESETVAL (0x00000000u)
/*----I48 Tokens----*/
#define CSL_EDMA3CC_IECRH_I48_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I47_MASK (0x00008000u)
#define CSL_EDMA3CC_IECRH_I47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_IECRH_I47_RESETVAL (0x00000000u)
/*----I47 Tokens----*/
#define CSL_EDMA3CC_IECRH_I47_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I46_MASK (0x00004000u)
#define CSL_EDMA3CC_IECRH_I46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_IECRH_I46_RESETVAL (0x00000000u)
/*----I46 Tokens----*/
#define CSL_EDMA3CC_IECRH_I46_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I45_MASK (0x00002000u)
#define CSL_EDMA3CC_IECRH_I45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_IECRH_I45_RESETVAL (0x00000000u)
/*----I45 Tokens----*/
#define CSL_EDMA3CC_IECRH_I45_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I44_MASK (0x00001000u)
#define CSL_EDMA3CC_IECRH_I44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_IECRH_I44_RESETVAL (0x00000000u)
/*----I44 Tokens----*/
#define CSL_EDMA3CC_IECRH_I44_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I43_MASK (0x00000800u)
#define CSL_EDMA3CC_IECRH_I43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_IECRH_I43_RESETVAL (0x00000000u)
/*----I43 Tokens----*/
#define CSL_EDMA3CC_IECRH_I43_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I42_MASK (0x00000400u)
#define CSL_EDMA3CC_IECRH_I42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_IECRH_I42_RESETVAL (0x00000000u)
/*----I42 Tokens----*/
#define CSL_EDMA3CC_IECRH_I42_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I41_MASK (0x00000200u)
#define CSL_EDMA3CC_IECRH_I41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_IECRH_I41_RESETVAL (0x00000000u)
/*----I41 Tokens----*/
#define CSL_EDMA3CC_IECRH_I41_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I40_MASK (0x00000100u)
#define CSL_EDMA3CC_IECRH_I40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_IECRH_I40_RESETVAL (0x00000000u)
/*----I40 Tokens----*/
#define CSL_EDMA3CC_IECRH_I40_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I39_MASK (0x00000080u)
#define CSL_EDMA3CC_IECRH_I39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_IECRH_I39_RESETVAL (0x00000000u)
/*----I39 Tokens----*/
#define CSL_EDMA3CC_IECRH_I39_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I38_MASK (0x00000040u)
#define CSL_EDMA3CC_IECRH_I38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_IECRH_I38_RESETVAL (0x00000000u)
/*----I38 Tokens----*/
#define CSL_EDMA3CC_IECRH_I38_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I37_MASK (0x00000020u)
#define CSL_EDMA3CC_IECRH_I37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_IECRH_I37_RESETVAL (0x00000000u)
/*----I37 Tokens----*/
#define CSL_EDMA3CC_IECRH_I37_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I36_MASK (0x00000010u)
#define CSL_EDMA3CC_IECRH_I36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_IECRH_I36_RESETVAL (0x00000000u)
/*----I36 Tokens----*/
#define CSL_EDMA3CC_IECRH_I36_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I35_MASK (0x00000008u)
#define CSL_EDMA3CC_IECRH_I35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_IECRH_I35_RESETVAL (0x00000000u)
/*----I35 Tokens----*/
#define CSL_EDMA3CC_IECRH_I35_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I34_MASK (0x00000004u)
#define CSL_EDMA3CC_IECRH_I34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_IECRH_I34_RESETVAL (0x00000000u)
/*----I34 Tokens----*/
#define CSL_EDMA3CC_IECRH_I34_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I33_MASK (0x00000002u)
#define CSL_EDMA3CC_IECRH_I33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_IECRH_I33_RESETVAL (0x00000000u)
/*----I33 Tokens----*/
#define CSL_EDMA3CC_IECRH_I33_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_I32_MASK (0x00000001u)
#define CSL_EDMA3CC_IECRH_I32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IECRH_I32_RESETVAL (0x00000000u)
/*----I32 Tokens----*/
#define CSL_EDMA3CC_IECRH_I32_CLEAR (0x00000001u)
#define CSL_EDMA3CC_IECRH_RESETVAL (0x00000000u)
/* IESR */
#define CSL_EDMA3CC_IESR_I31_MASK (0x80000000u)
#define CSL_EDMA3CC_IESR_I31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_IESR_I31_RESETVAL (0x00000000u)
/*----I31 Tokens----*/
#define CSL_EDMA3CC_IESR_I31_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I30_MASK (0x40000000u)
#define CSL_EDMA3CC_IESR_I30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_IESR_I30_RESETVAL (0x00000000u)
/*----I30 Tokens----*/
#define CSL_EDMA3CC_IESR_I30_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I29_MASK (0x20000000u)
#define CSL_EDMA3CC_IESR_I29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_IESR_I29_RESETVAL (0x00000000u)
/*----I29 Tokens----*/
#define CSL_EDMA3CC_IESR_I29_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I28_MASK (0x10000000u)
#define CSL_EDMA3CC_IESR_I28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_IESR_I28_RESETVAL (0x00000000u)
/*----I28 Tokens----*/
#define CSL_EDMA3CC_IESR_I28_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I27_MASK (0x08000000u)
#define CSL_EDMA3CC_IESR_I27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_IESR_I27_RESETVAL (0x00000000u)
/*----I27 Tokens----*/
#define CSL_EDMA3CC_IESR_I27_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I26_MASK (0x04000000u)
#define CSL_EDMA3CC_IESR_I26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_IESR_I26_RESETVAL (0x00000000u)
/*----I26 Tokens----*/
#define CSL_EDMA3CC_IESR_I26_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I25_MASK (0x02000000u)
#define CSL_EDMA3CC_IESR_I25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_IESR_I25_RESETVAL (0x00000000u)
/*----I25 Tokens----*/
#define CSL_EDMA3CC_IESR_I25_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I24_MASK (0x01000000u)
#define CSL_EDMA3CC_IESR_I24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_IESR_I24_RESETVAL (0x00000000u)
/*----I24 Tokens----*/
#define CSL_EDMA3CC_IESR_I24_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I23_MASK (0x00800000u)
#define CSL_EDMA3CC_IESR_I23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_IESR_I23_RESETVAL (0x00000000u)
/*----I23 Tokens----*/
#define CSL_EDMA3CC_IESR_I23_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I22_MASK (0x00400000u)
#define CSL_EDMA3CC_IESR_I22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_IESR_I22_RESETVAL (0x00000000u)
/*----I22 Tokens----*/
#define CSL_EDMA3CC_IESR_I22_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I21_MASK (0x00200000u)
#define CSL_EDMA3CC_IESR_I21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_IESR_I21_RESETVAL (0x00000000u)
/*----I21 Tokens----*/
#define CSL_EDMA3CC_IESR_I21_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I20_MASK (0x00100000u)
#define CSL_EDMA3CC_IESR_I20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_IESR_I20_RESETVAL (0x00000000u)
/*----I20 Tokens----*/
#define CSL_EDMA3CC_IESR_I20_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I19_MASK (0x00080000u)
#define CSL_EDMA3CC_IESR_I19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_IESR_I19_RESETVAL (0x00000000u)
/*----I19 Tokens----*/
#define CSL_EDMA3CC_IESR_I19_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I18_MASK (0x00040000u)
#define CSL_EDMA3CC_IESR_I18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_IESR_I18_RESETVAL (0x00000000u)
/*----I18 Tokens----*/
#define CSL_EDMA3CC_IESR_I18_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I17_MASK (0x00020000u)
#define CSL_EDMA3CC_IESR_I17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_IESR_I17_RESETVAL (0x00000000u)
/*----I17 Tokens----*/
#define CSL_EDMA3CC_IESR_I17_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I16_MASK (0x00010000u)
#define CSL_EDMA3CC_IESR_I16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_IESR_I16_RESETVAL (0x00000000u)
/*----I16 Tokens----*/
#define CSL_EDMA3CC_IESR_I16_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I15_MASK (0x00008000u)
#define CSL_EDMA3CC_IESR_I15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_IESR_I15_RESETVAL (0x00000000u)
/*----I15 Tokens----*/
#define CSL_EDMA3CC_IESR_I15_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I14_MASK (0x00004000u)
#define CSL_EDMA3CC_IESR_I14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_IESR_I14_RESETVAL (0x00000000u)
/*----I14 Tokens----*/
#define CSL_EDMA3CC_IESR_I14_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I13_MASK (0x00002000u)
#define CSL_EDMA3CC_IESR_I13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_IESR_I13_RESETVAL (0x00000000u)
/*----I13 Tokens----*/
#define CSL_EDMA3CC_IESR_I13_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I12_MASK (0x00001000u)
#define CSL_EDMA3CC_IESR_I12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_IESR_I12_RESETVAL (0x00000000u)
/*----I12 Tokens----*/
#define CSL_EDMA3CC_IESR_I12_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I11_MASK (0x00000800u)
#define CSL_EDMA3CC_IESR_I11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_IESR_I11_RESETVAL (0x00000000u)
/*----I11 Tokens----*/
#define CSL_EDMA3CC_IESR_I11_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I10_MASK (0x00000400u)
#define CSL_EDMA3CC_IESR_I10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_IESR_I10_RESETVAL (0x00000000u)
/*----I10 Tokens----*/
#define CSL_EDMA3CC_IESR_I10_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I9_MASK (0x00000200u)
#define CSL_EDMA3CC_IESR_I9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_IESR_I9_RESETVAL (0x00000000u)
/*----I9 Tokens----*/
#define CSL_EDMA3CC_IESR_I9_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I8_MASK (0x00000100u)
#define CSL_EDMA3CC_IESR_I8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_IESR_I8_RESETVAL (0x00000000u)
/*----I8 Tokens----*/
#define CSL_EDMA3CC_IESR_I8_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I7_MASK (0x00000080u)
#define CSL_EDMA3CC_IESR_I7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_IESR_I7_RESETVAL (0x00000000u)
/*----I7 Tokens----*/
#define CSL_EDMA3CC_IESR_I7_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I6_MASK (0x00000040u)
#define CSL_EDMA3CC_IESR_I6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_IESR_I6_RESETVAL (0x00000000u)
/*----I6 Tokens----*/
#define CSL_EDMA3CC_IESR_I6_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I5_MASK (0x00000020u)
#define CSL_EDMA3CC_IESR_I5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_IESR_I5_RESETVAL (0x00000000u)
/*----I5 Tokens----*/
#define CSL_EDMA3CC_IESR_I5_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I4_MASK (0x00000010u)
#define CSL_EDMA3CC_IESR_I4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_IESR_I4_RESETVAL (0x00000000u)
/*----I4 Tokens----*/
#define CSL_EDMA3CC_IESR_I4_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I3_MASK (0x00000008u)
#define CSL_EDMA3CC_IESR_I3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_IESR_I3_RESETVAL (0x00000000u)
/*----I3 Tokens----*/
#define CSL_EDMA3CC_IESR_I3_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I2_MASK (0x00000004u)
#define CSL_EDMA3CC_IESR_I2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_IESR_I2_RESETVAL (0x00000000u)
/*----I2 Tokens----*/
#define CSL_EDMA3CC_IESR_I2_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I1_MASK (0x00000002u)
#define CSL_EDMA3CC_IESR_I1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_IESR_I1_RESETVAL (0x00000000u)
/*----I1 Tokens----*/
#define CSL_EDMA3CC_IESR_I1_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_I0_MASK (0x00000001u)
#define CSL_EDMA3CC_IESR_I0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IESR_I0_RESETVAL (0x00000000u)
/*----I0 Tokens----*/
#define CSL_EDMA3CC_IESR_I0_SET (0x00000001u)
#define CSL_EDMA3CC_IESR_RESETVAL (0x00000000u)
/* IESRH */
#define CSL_EDMA3CC_IESRH_I63_MASK (0x80000000u)
#define CSL_EDMA3CC_IESRH_I63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_IESRH_I63_RESETVAL (0x00000000u)
/*----I63 Tokens----*/
#define CSL_EDMA3CC_IESRH_I63_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I62_MASK (0x40000000u)
#define CSL_EDMA3CC_IESRH_I62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_IESRH_I62_RESETVAL (0x00000000u)
/*----I62 Tokens----*/
#define CSL_EDMA3CC_IESRH_I62_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I61_MASK (0x20000000u)
#define CSL_EDMA3CC_IESRH_I61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_IESRH_I61_RESETVAL (0x00000000u)
/*----I61 Tokens----*/
#define CSL_EDMA3CC_IESRH_I61_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I60_MASK (0x10000000u)
#define CSL_EDMA3CC_IESRH_I60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_IESRH_I60_RESETVAL (0x00000000u)
/*----I60 Tokens----*/
#define CSL_EDMA3CC_IESRH_I60_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I59_MASK (0x08000000u)
#define CSL_EDMA3CC_IESRH_I59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_IESRH_I59_RESETVAL (0x00000000u)
/*----I59 Tokens----*/
#define CSL_EDMA3CC_IESRH_I59_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I58_MASK (0x04000000u)
#define CSL_EDMA3CC_IESRH_I58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_IESRH_I58_RESETVAL (0x00000000u)
/*----I58 Tokens----*/
#define CSL_EDMA3CC_IESRH_I58_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I57_MASK (0x02000000u)
#define CSL_EDMA3CC_IESRH_I57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_IESRH_I57_RESETVAL (0x00000000u)
/*----I57 Tokens----*/
#define CSL_EDMA3CC_IESRH_I57_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I56_MASK (0x01000000u)
#define CSL_EDMA3CC_IESRH_I56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_IESRH_I56_RESETVAL (0x00000000u)
/*----I56 Tokens----*/
#define CSL_EDMA3CC_IESRH_I56_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I55_MASK (0x00800000u)
#define CSL_EDMA3CC_IESRH_I55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_IESRH_I55_RESETVAL (0x00000000u)
/*----I55 Tokens----*/
#define CSL_EDMA3CC_IESRH_I55_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I54_MASK (0x00400000u)
#define CSL_EDMA3CC_IESRH_I54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_IESRH_I54_RESETVAL (0x00000000u)
/*----I54 Tokens----*/
#define CSL_EDMA3CC_IESRH_I54_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I53_MASK (0x00200000u)
#define CSL_EDMA3CC_IESRH_I53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_IESRH_I53_RESETVAL (0x00000000u)
/*----I53 Tokens----*/
#define CSL_EDMA3CC_IESRH_I53_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I52_MASK (0x00100000u)
#define CSL_EDMA3CC_IESRH_I52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_IESRH_I52_RESETVAL (0x00000000u)
/*----I52 Tokens----*/
#define CSL_EDMA3CC_IESRH_I52_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I51_MASK (0x00080000u)
#define CSL_EDMA3CC_IESRH_I51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_IESRH_I51_RESETVAL (0x00000000u)
/*----I51 Tokens----*/
#define CSL_EDMA3CC_IESRH_I51_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I50_MASK (0x00040000u)
#define CSL_EDMA3CC_IESRH_I50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_IESRH_I50_RESETVAL (0x00000000u)
/*----I50 Tokens----*/
#define CSL_EDMA3CC_IESRH_I50_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I49_MASK (0x00020000u)
#define CSL_EDMA3CC_IESRH_I49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_IESRH_I49_RESETVAL (0x00000000u)
/*----I49 Tokens----*/
#define CSL_EDMA3CC_IESRH_I49_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I48_MASK (0x00010000u)
#define CSL_EDMA3CC_IESRH_I48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_IESRH_I48_RESETVAL (0x00000000u)
/*----I48 Tokens----*/
#define CSL_EDMA3CC_IESRH_I48_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I47_MASK (0x00008000u)
#define CSL_EDMA3CC_IESRH_I47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_IESRH_I47_RESETVAL (0x00000000u)
/*----I47 Tokens----*/
#define CSL_EDMA3CC_IESRH_I47_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I46_MASK (0x00004000u)
#define CSL_EDMA3CC_IESRH_I46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_IESRH_I46_RESETVAL (0x00000000u)
/*----I46 Tokens----*/
#define CSL_EDMA3CC_IESRH_I46_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I45_MASK (0x00002000u)
#define CSL_EDMA3CC_IESRH_I45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_IESRH_I45_RESETVAL (0x00000000u)
/*----I45 Tokens----*/
#define CSL_EDMA3CC_IESRH_I45_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I44_MASK (0x00001000u)
#define CSL_EDMA3CC_IESRH_I44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_IESRH_I44_RESETVAL (0x00000000u)
/*----I44 Tokens----*/
#define CSL_EDMA3CC_IESRH_I44_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I43_MASK (0x00000800u)
#define CSL_EDMA3CC_IESRH_I43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_IESRH_I43_RESETVAL (0x00000000u)
/*----I43 Tokens----*/
#define CSL_EDMA3CC_IESRH_I43_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I42_MASK (0x00000400u)
#define CSL_EDMA3CC_IESRH_I42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_IESRH_I42_RESETVAL (0x00000000u)
/*----I42 Tokens----*/
#define CSL_EDMA3CC_IESRH_I42_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I41_MASK (0x00000200u)
#define CSL_EDMA3CC_IESRH_I41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_IESRH_I41_RESETVAL (0x00000000u)
/*----I41 Tokens----*/
#define CSL_EDMA3CC_IESRH_I41_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I40_MASK (0x00000100u)
#define CSL_EDMA3CC_IESRH_I40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_IESRH_I40_RESETVAL (0x00000000u)
/*----I40 Tokens----*/
#define CSL_EDMA3CC_IESRH_I40_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I39_MASK (0x00000080u)
#define CSL_EDMA3CC_IESRH_I39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_IESRH_I39_RESETVAL (0x00000000u)
/*----I39 Tokens----*/
#define CSL_EDMA3CC_IESRH_I39_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I38_MASK (0x00000040u)
#define CSL_EDMA3CC_IESRH_I38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_IESRH_I38_RESETVAL (0x00000000u)
/*----I38 Tokens----*/
#define CSL_EDMA3CC_IESRH_I38_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I37_MASK (0x00000020u)
#define CSL_EDMA3CC_IESRH_I37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_IESRH_I37_RESETVAL (0x00000000u)
/*----I37 Tokens----*/
#define CSL_EDMA3CC_IESRH_I37_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I36_MASK (0x00000010u)
#define CSL_EDMA3CC_IESRH_I36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_IESRH_I36_RESETVAL (0x00000000u)
/*----I36 Tokens----*/
#define CSL_EDMA3CC_IESRH_I36_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I35_MASK (0x00000008u)
#define CSL_EDMA3CC_IESRH_I35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_IESRH_I35_RESETVAL (0x00000000u)
/*----I35 Tokens----*/
#define CSL_EDMA3CC_IESRH_I35_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I34_MASK (0x00000004u)
#define CSL_EDMA3CC_IESRH_I34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_IESRH_I34_RESETVAL (0x00000000u)
/*----I34 Tokens----*/
#define CSL_EDMA3CC_IESRH_I34_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I33_MASK (0x00000002u)
#define CSL_EDMA3CC_IESRH_I33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_IESRH_I33_RESETVAL (0x00000000u)
/*----I33 Tokens----*/
#define CSL_EDMA3CC_IESRH_I33_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_I32_MASK (0x00000001u)
#define CSL_EDMA3CC_IESRH_I32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IESRH_I32_RESETVAL (0x00000000u)
/*----I32 Tokens----*/
#define CSL_EDMA3CC_IESRH_I32_SET (0x00000001u)
#define CSL_EDMA3CC_IESRH_RESETVAL (0x00000000u)
/* IPR */
#define CSL_EDMA3CC_IPR_I31_MASK (0x80000000u)
#define CSL_EDMA3CC_IPR_I31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_IPR_I31_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I30_MASK (0x40000000u)
#define CSL_EDMA3CC_IPR_I30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_IPR_I30_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I29_MASK (0x20000000u)
#define CSL_EDMA3CC_IPR_I29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_IPR_I29_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I28_MASK (0x10000000u)
#define CSL_EDMA3CC_IPR_I28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_IPR_I28_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I27_MASK (0x08000000u)
#define CSL_EDMA3CC_IPR_I27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_IPR_I27_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I26_MASK (0x04000000u)
#define CSL_EDMA3CC_IPR_I26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_IPR_I26_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I25_MASK (0x02000000u)
#define CSL_EDMA3CC_IPR_I25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_IPR_I25_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I24_MASK (0x01000000u)
#define CSL_EDMA3CC_IPR_I24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_IPR_I24_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I23_MASK (0x00800000u)
#define CSL_EDMA3CC_IPR_I23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_IPR_I23_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I22_MASK (0x00400000u)
#define CSL_EDMA3CC_IPR_I22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_IPR_I22_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I21_MASK (0x00200000u)
#define CSL_EDMA3CC_IPR_I21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_IPR_I21_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I20_MASK (0x00100000u)
#define CSL_EDMA3CC_IPR_I20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_IPR_I20_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I19_MASK (0x00080000u)
#define CSL_EDMA3CC_IPR_I19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_IPR_I19_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I18_MASK (0x00040000u)
#define CSL_EDMA3CC_IPR_I18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_IPR_I18_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I17_MASK (0x00020000u)
#define CSL_EDMA3CC_IPR_I17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_IPR_I17_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I16_MASK (0x00010000u)
#define CSL_EDMA3CC_IPR_I16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_IPR_I16_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I15_MASK (0x00008000u)
#define CSL_EDMA3CC_IPR_I15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_IPR_I15_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I14_MASK (0x00004000u)
#define CSL_EDMA3CC_IPR_I14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_IPR_I14_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I13_MASK (0x00002000u)
#define CSL_EDMA3CC_IPR_I13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_IPR_I13_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I12_MASK (0x00001000u)
#define CSL_EDMA3CC_IPR_I12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_IPR_I12_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I11_MASK (0x00000800u)
#define CSL_EDMA3CC_IPR_I11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_IPR_I11_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I10_MASK (0x00000400u)
#define CSL_EDMA3CC_IPR_I10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_IPR_I10_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I9_MASK (0x00000200u)
#define CSL_EDMA3CC_IPR_I9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_IPR_I9_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I8_MASK (0x00000100u)
#define CSL_EDMA3CC_IPR_I8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_IPR_I8_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I7_MASK (0x00000080u)
#define CSL_EDMA3CC_IPR_I7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_IPR_I7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I6_MASK (0x00000040u)
#define CSL_EDMA3CC_IPR_I6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_IPR_I6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I5_MASK (0x00000020u)
#define CSL_EDMA3CC_IPR_I5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_IPR_I5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I4_MASK (0x00000010u)
#define CSL_EDMA3CC_IPR_I4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_IPR_I4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I3_MASK (0x00000008u)
#define CSL_EDMA3CC_IPR_I3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_IPR_I3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I2_MASK (0x00000004u)
#define CSL_EDMA3CC_IPR_I2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_IPR_I2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I1_MASK (0x00000002u)
#define CSL_EDMA3CC_IPR_I1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_IPR_I1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_I0_MASK (0x00000001u)
#define CSL_EDMA3CC_IPR_I0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IPR_I0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_RESETVAL (0x00000000u)
/* IPRH */
#define CSL_EDMA3CC_IPRH_I63_MASK (0x80000000u)
#define CSL_EDMA3CC_IPRH_I63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_IPRH_I63_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I62_MASK (0x40000000u)
#define CSL_EDMA3CC_IPRH_I62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_IPRH_I62_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I61_MASK (0x20000000u)
#define CSL_EDMA3CC_IPRH_I61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_IPRH_I61_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I60_MASK (0x10000000u)
#define CSL_EDMA3CC_IPRH_I60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_IPRH_I60_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I59_MASK (0x08000000u)
#define CSL_EDMA3CC_IPRH_I59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_IPRH_I59_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I58_MASK (0x04000000u)
#define CSL_EDMA3CC_IPRH_I58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_IPRH_I58_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I57_MASK (0x02000000u)
#define CSL_EDMA3CC_IPRH_I57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_IPRH_I57_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I56_MASK (0x01000000u)
#define CSL_EDMA3CC_IPRH_I56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_IPRH_I56_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I55_MASK (0x00800000u)
#define CSL_EDMA3CC_IPRH_I55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_IPRH_I55_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I54_MASK (0x00400000u)
#define CSL_EDMA3CC_IPRH_I54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_IPRH_I54_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I53_MASK (0x00200000u)
#define CSL_EDMA3CC_IPRH_I53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_IPRH_I53_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I52_MASK (0x00100000u)
#define CSL_EDMA3CC_IPRH_I52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_IPRH_I52_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I51_MASK (0x00080000u)
#define CSL_EDMA3CC_IPRH_I51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_IPRH_I51_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I50_MASK (0x00040000u)
#define CSL_EDMA3CC_IPRH_I50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_IPRH_I50_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I49_MASK (0x00020000u)
#define CSL_EDMA3CC_IPRH_I49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_IPRH_I49_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I48_MASK (0x00010000u)
#define CSL_EDMA3CC_IPRH_I48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_IPRH_I48_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I47_MASK (0x00008000u)
#define CSL_EDMA3CC_IPRH_I47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_IPRH_I47_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I46_MASK (0x00004000u)
#define CSL_EDMA3CC_IPRH_I46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_IPRH_I46_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I45_MASK (0x00002000u)
#define CSL_EDMA3CC_IPRH_I45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_IPRH_I45_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I44_MASK (0x00001000u)
#define CSL_EDMA3CC_IPRH_I44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_IPRH_I44_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I43_MASK (0x00000800u)
#define CSL_EDMA3CC_IPRH_I43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_IPRH_I43_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I42_MASK (0x00000400u)
#define CSL_EDMA3CC_IPRH_I42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_IPRH_I42_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I41_MASK (0x00000200u)
#define CSL_EDMA3CC_IPRH_I41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_IPRH_I41_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I40_MASK (0x00000100u)
#define CSL_EDMA3CC_IPRH_I40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_IPRH_I40_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I39_MASK (0x00000080u)
#define CSL_EDMA3CC_IPRH_I39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_IPRH_I39_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I38_MASK (0x00000040u)
#define CSL_EDMA3CC_IPRH_I38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_IPRH_I38_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I37_MASK (0x00000020u)
#define CSL_EDMA3CC_IPRH_I37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_IPRH_I37_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I36_MASK (0x00000010u)
#define CSL_EDMA3CC_IPRH_I36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_IPRH_I36_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I35_MASK (0x00000008u)
#define CSL_EDMA3CC_IPRH_I35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_IPRH_I35_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I34_MASK (0x00000004u)
#define CSL_EDMA3CC_IPRH_I34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_IPRH_I34_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I33_MASK (0x00000002u)
#define CSL_EDMA3CC_IPRH_I33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_IPRH_I33_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_I32_MASK (0x00000001u)
#define CSL_EDMA3CC_IPRH_I32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IPRH_I32_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_RESETVAL (0x00000000u)
/* ICR */
#define CSL_EDMA3CC_ICR_I31_MASK (0x80000000u)
#define CSL_EDMA3CC_ICR_I31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_ICR_I31_RESETVAL (0x00000000u)
/*----I31 Tokens----*/
#define CSL_EDMA3CC_ICR_I31_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I30_MASK (0x40000000u)
#define CSL_EDMA3CC_ICR_I30_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_ICR_I30_RESETVAL (0x00000000u)
/*----I30 Tokens----*/
#define CSL_EDMA3CC_ICR_I30_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I29_MASK (0x20000000u)
#define CSL_EDMA3CC_ICR_I29_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_ICR_I29_RESETVAL (0x00000000u)
/*----I29 Tokens----*/
#define CSL_EDMA3CC_ICR_I29_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I28_MASK (0x10000000u)
#define CSL_EDMA3CC_ICR_I28_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_ICR_I28_RESETVAL (0x00000000u)
/*----I28 Tokens----*/
#define CSL_EDMA3CC_ICR_I28_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I27_MASK (0x08000000u)
#define CSL_EDMA3CC_ICR_I27_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_ICR_I27_RESETVAL (0x00000000u)
/*----I27 Tokens----*/
#define CSL_EDMA3CC_ICR_I27_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I26_MASK (0x04000000u)
#define CSL_EDMA3CC_ICR_I26_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_ICR_I26_RESETVAL (0x00000000u)
/*----I26 Tokens----*/
#define CSL_EDMA3CC_ICR_I26_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I25_MASK (0x02000000u)
#define CSL_EDMA3CC_ICR_I25_SHIFT (0x00000019u)
#define CSL_EDMA3CC_ICR_I25_RESETVAL (0x00000000u)
/*----I25 Tokens----*/
#define CSL_EDMA3CC_ICR_I25_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I24_MASK (0x01000000u)
#define CSL_EDMA3CC_ICR_I24_SHIFT (0x00000018u)
#define CSL_EDMA3CC_ICR_I24_RESETVAL (0x00000000u)
/*----I24 Tokens----*/
#define CSL_EDMA3CC_ICR_I24_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I23_MASK (0x00800000u)
#define CSL_EDMA3CC_ICR_I23_SHIFT (0x00000017u)
#define CSL_EDMA3CC_ICR_I23_RESETVAL (0x00000000u)
/*----I23 Tokens----*/
#define CSL_EDMA3CC_ICR_I23_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I22_MASK (0x00400000u)
#define CSL_EDMA3CC_ICR_I22_SHIFT (0x00000016u)
#define CSL_EDMA3CC_ICR_I22_RESETVAL (0x00000000u)
/*----I22 Tokens----*/
#define CSL_EDMA3CC_ICR_I22_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I21_MASK (0x00200000u)
#define CSL_EDMA3CC_ICR_I21_SHIFT (0x00000015u)
#define CSL_EDMA3CC_ICR_I21_RESETVAL (0x00000000u)
/*----I21 Tokens----*/
#define CSL_EDMA3CC_ICR_I21_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I20_MASK (0x00100000u)
#define CSL_EDMA3CC_ICR_I20_SHIFT (0x00000014u)
#define CSL_EDMA3CC_ICR_I20_RESETVAL (0x00000000u)
/*----I20 Tokens----*/
#define CSL_EDMA3CC_ICR_I20_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I19_MASK (0x00080000u)
#define CSL_EDMA3CC_ICR_I19_SHIFT (0x00000013u)
#define CSL_EDMA3CC_ICR_I19_RESETVAL (0x00000000u)
/*----I19 Tokens----*/
#define CSL_EDMA3CC_ICR_I19_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I18_MASK (0x00040000u)
#define CSL_EDMA3CC_ICR_I18_SHIFT (0x00000012u)
#define CSL_EDMA3CC_ICR_I18_RESETVAL (0x00000000u)
/*----I18 Tokens----*/
#define CSL_EDMA3CC_ICR_I18_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I17_MASK (0x00020000u)
#define CSL_EDMA3CC_ICR_I17_SHIFT (0x00000011u)
#define CSL_EDMA3CC_ICR_I17_RESETVAL (0x00000000u)
/*----I17 Tokens----*/
#define CSL_EDMA3CC_ICR_I17_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I16_MASK (0x00010000u)
#define CSL_EDMA3CC_ICR_I16_SHIFT (0x00000010u)
#define CSL_EDMA3CC_ICR_I16_RESETVAL (0x00000000u)
/*----I16 Tokens----*/
#define CSL_EDMA3CC_ICR_I16_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I15_MASK (0x00008000u)
#define CSL_EDMA3CC_ICR_I15_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_ICR_I15_RESETVAL (0x00000000u)
/*----I15 Tokens----*/
#define CSL_EDMA3CC_ICR_I15_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I14_MASK (0x00004000u)
#define CSL_EDMA3CC_ICR_I14_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_ICR_I14_RESETVAL (0x00000000u)
/*----I14 Tokens----*/
#define CSL_EDMA3CC_ICR_I14_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I13_MASK (0x00002000u)
#define CSL_EDMA3CC_ICR_I13_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_ICR_I13_RESETVAL (0x00000000u)
/*----I13 Tokens----*/
#define CSL_EDMA3CC_ICR_I13_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I12_MASK (0x00001000u)
#define CSL_EDMA3CC_ICR_I12_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_ICR_I12_RESETVAL (0x00000000u)
/*----I12 Tokens----*/
#define CSL_EDMA3CC_ICR_I12_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I11_MASK (0x00000800u)
#define CSL_EDMA3CC_ICR_I11_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_ICR_I11_RESETVAL (0x00000000u)
/*----I11 Tokens----*/
#define CSL_EDMA3CC_ICR_I11_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I10_MASK (0x00000400u)
#define CSL_EDMA3CC_ICR_I10_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_ICR_I10_RESETVAL (0x00000000u)
/*----I10 Tokens----*/
#define CSL_EDMA3CC_ICR_I10_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I9_MASK (0x00000200u)
#define CSL_EDMA3CC_ICR_I9_SHIFT (0x00000009u)
#define CSL_EDMA3CC_ICR_I9_RESETVAL (0x00000000u)
/*----I9 Tokens----*/
#define CSL_EDMA3CC_ICR_I9_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I8_MASK (0x00000100u)
#define CSL_EDMA3CC_ICR_I8_SHIFT (0x00000008u)
#define CSL_EDMA3CC_ICR_I8_RESETVAL (0x00000000u)
/*----I8 Tokens----*/
#define CSL_EDMA3CC_ICR_I8_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I7_MASK (0x00000080u)
#define CSL_EDMA3CC_ICR_I7_SHIFT (0x00000007u)
#define CSL_EDMA3CC_ICR_I7_RESETVAL (0x00000000u)
/*----I7 Tokens----*/
#define CSL_EDMA3CC_ICR_I7_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I6_MASK (0x00000040u)
#define CSL_EDMA3CC_ICR_I6_SHIFT (0x00000006u)
#define CSL_EDMA3CC_ICR_I6_RESETVAL (0x00000000u)
/*----I6 Tokens----*/
#define CSL_EDMA3CC_ICR_I6_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I5_MASK (0x00000020u)
#define CSL_EDMA3CC_ICR_I5_SHIFT (0x00000005u)
#define CSL_EDMA3CC_ICR_I5_RESETVAL (0x00000000u)
/*----I5 Tokens----*/
#define CSL_EDMA3CC_ICR_I5_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I4_MASK (0x00000010u)
#define CSL_EDMA3CC_ICR_I4_SHIFT (0x00000004u)
#define CSL_EDMA3CC_ICR_I4_RESETVAL (0x00000000u)
/*----I4 Tokens----*/
#define CSL_EDMA3CC_ICR_I4_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I3_MASK (0x00000008u)
#define CSL_EDMA3CC_ICR_I3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_ICR_I3_RESETVAL (0x00000000u)
/*----I3 Tokens----*/
#define CSL_EDMA3CC_ICR_I3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I2_MASK (0x00000004u)
#define CSL_EDMA3CC_ICR_I2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_ICR_I2_RESETVAL (0x00000000u)
/*----I2 Tokens----*/
#define CSL_EDMA3CC_ICR_I2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I1_MASK (0x00000002u)
#define CSL_EDMA3CC_ICR_I1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_ICR_I1_RESETVAL (0x00000000u)
/*----I1 Tokens----*/
#define CSL_EDMA3CC_ICR_I1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_I0_MASK (0x00000001u)
#define CSL_EDMA3CC_ICR_I0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ICR_I0_RESETVAL (0x00000000u)
/*----I0 Tokens----*/
#define CSL_EDMA3CC_ICR_I0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICR_RESETVAL (0x00000000u)
/* ICRH */
#define CSL_EDMA3CC_ICRH_I63_MASK (0x80000000u)
#define CSL_EDMA3CC_ICRH_I63_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_ICRH_I63_RESETVAL (0x00000000u)
/*----I63 Tokens----*/
#define CSL_EDMA3CC_ICRH_I63_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I62_MASK (0x40000000u)
#define CSL_EDMA3CC_ICRH_I62_SHIFT (0x0000001Eu)
#define CSL_EDMA3CC_ICRH_I62_RESETVAL (0x00000000u)
/*----I62 Tokens----*/
#define CSL_EDMA3CC_ICRH_I62_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I61_MASK (0x20000000u)
#define CSL_EDMA3CC_ICRH_I61_SHIFT (0x0000001Du)
#define CSL_EDMA3CC_ICRH_I61_RESETVAL (0x00000000u)
/*----I61 Tokens----*/
#define CSL_EDMA3CC_ICRH_I61_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I60_MASK (0x10000000u)
#define CSL_EDMA3CC_ICRH_I60_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_ICRH_I60_RESETVAL (0x00000000u)
/*----I60 Tokens----*/
#define CSL_EDMA3CC_ICRH_I60_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I59_MASK (0x08000000u)
#define CSL_EDMA3CC_ICRH_I59_SHIFT (0x0000001Bu)
#define CSL_EDMA3CC_ICRH_I59_RESETVAL (0x00000000u)
/*----I59 Tokens----*/
#define CSL_EDMA3CC_ICRH_I59_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I58_MASK (0x04000000u)
#define CSL_EDMA3CC_ICRH_I58_SHIFT (0x0000001Au)
#define CSL_EDMA3CC_ICRH_I58_RESETVAL (0x00000000u)
/*----I58 Tokens----*/
#define CSL_EDMA3CC_ICRH_I58_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I57_MASK (0x02000000u)
#define CSL_EDMA3CC_ICRH_I57_SHIFT (0x00000019u)
#define CSL_EDMA3CC_ICRH_I57_RESETVAL (0x00000000u)
/*----I57 Tokens----*/
#define CSL_EDMA3CC_ICRH_I57_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I56_MASK (0x01000000u)
#define CSL_EDMA3CC_ICRH_I56_SHIFT (0x00000018u)
#define CSL_EDMA3CC_ICRH_I56_RESETVAL (0x00000000u)
/*----I56 Tokens----*/
#define CSL_EDMA3CC_ICRH_I56_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I55_MASK (0x00800000u)
#define CSL_EDMA3CC_ICRH_I55_SHIFT (0x00000017u)
#define CSL_EDMA3CC_ICRH_I55_RESETVAL (0x00000000u)
/*----I55 Tokens----*/
#define CSL_EDMA3CC_ICRH_I55_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I54_MASK (0x00400000u)
#define CSL_EDMA3CC_ICRH_I54_SHIFT (0x00000016u)
#define CSL_EDMA3CC_ICRH_I54_RESETVAL (0x00000000u)
/*----I54 Tokens----*/
#define CSL_EDMA3CC_ICRH_I54_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I53_MASK (0x00200000u)
#define CSL_EDMA3CC_ICRH_I53_SHIFT (0x00000015u)
#define CSL_EDMA3CC_ICRH_I53_RESETVAL (0x00000000u)
/*----I53 Tokens----*/
#define CSL_EDMA3CC_ICRH_I53_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I52_MASK (0x00100000u)
#define CSL_EDMA3CC_ICRH_I52_SHIFT (0x00000014u)
#define CSL_EDMA3CC_ICRH_I52_RESETVAL (0x00000000u)
/*----I52 Tokens----*/
#define CSL_EDMA3CC_ICRH_I52_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I51_MASK (0x00080000u)
#define CSL_EDMA3CC_ICRH_I51_SHIFT (0x00000013u)
#define CSL_EDMA3CC_ICRH_I51_RESETVAL (0x00000000u)
/*----I51 Tokens----*/
#define CSL_EDMA3CC_ICRH_I51_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I50_MASK (0x00040000u)
#define CSL_EDMA3CC_ICRH_I50_SHIFT (0x00000012u)
#define CSL_EDMA3CC_ICRH_I50_RESETVAL (0x00000000u)
/*----I50 Tokens----*/
#define CSL_EDMA3CC_ICRH_I50_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I49_MASK (0x00020000u)
#define CSL_EDMA3CC_ICRH_I49_SHIFT (0x00000011u)
#define CSL_EDMA3CC_ICRH_I49_RESETVAL (0x00000000u)
/*----I49 Tokens----*/
#define CSL_EDMA3CC_ICRH_I49_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I48_MASK (0x00010000u)
#define CSL_EDMA3CC_ICRH_I48_SHIFT (0x00000010u)
#define CSL_EDMA3CC_ICRH_I48_RESETVAL (0x00000000u)
/*----I48 Tokens----*/
#define CSL_EDMA3CC_ICRH_I48_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I47_MASK (0x00008000u)
#define CSL_EDMA3CC_ICRH_I47_SHIFT (0x0000000Fu)
#define CSL_EDMA3CC_ICRH_I47_RESETVAL (0x00000000u)
/*----I47 Tokens----*/
#define CSL_EDMA3CC_ICRH_I47_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I46_MASK (0x00004000u)
#define CSL_EDMA3CC_ICRH_I46_SHIFT (0x0000000Eu)
#define CSL_EDMA3CC_ICRH_I46_RESETVAL (0x00000000u)
/*----I46 Tokens----*/
#define CSL_EDMA3CC_ICRH_I46_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I45_MASK (0x00002000u)
#define CSL_EDMA3CC_ICRH_I45_SHIFT (0x0000000Du)
#define CSL_EDMA3CC_ICRH_I45_RESETVAL (0x00000000u)
/*----I45 Tokens----*/
#define CSL_EDMA3CC_ICRH_I45_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I44_MASK (0x00001000u)
#define CSL_EDMA3CC_ICRH_I44_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_ICRH_I44_RESETVAL (0x00000000u)
/*----I44 Tokens----*/
#define CSL_EDMA3CC_ICRH_I44_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I43_MASK (0x00000800u)
#define CSL_EDMA3CC_ICRH_I43_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_ICRH_I43_RESETVAL (0x00000000u)
/*----I43 Tokens----*/
#define CSL_EDMA3CC_ICRH_I43_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I42_MASK (0x00000400u)
#define CSL_EDMA3CC_ICRH_I42_SHIFT (0x0000000Au)
#define CSL_EDMA3CC_ICRH_I42_RESETVAL (0x00000000u)
/*----I42 Tokens----*/
#define CSL_EDMA3CC_ICRH_I42_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I41_MASK (0x00000200u)
#define CSL_EDMA3CC_ICRH_I41_SHIFT (0x00000009u)
#define CSL_EDMA3CC_ICRH_I41_RESETVAL (0x00000000u)
/*----I41 Tokens----*/
#define CSL_EDMA3CC_ICRH_I41_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I40_MASK (0x00000100u)
#define CSL_EDMA3CC_ICRH_I40_SHIFT (0x00000008u)
#define CSL_EDMA3CC_ICRH_I40_RESETVAL (0x00000000u)
/*----I40 Tokens----*/
#define CSL_EDMA3CC_ICRH_I40_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I39_MASK (0x00000080u)
#define CSL_EDMA3CC_ICRH_I39_SHIFT (0x00000007u)
#define CSL_EDMA3CC_ICRH_I39_RESETVAL (0x00000000u)
/*----I39 Tokens----*/
#define CSL_EDMA3CC_ICRH_I39_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I38_MASK (0x00000040u)
#define CSL_EDMA3CC_ICRH_I38_SHIFT (0x00000006u)
#define CSL_EDMA3CC_ICRH_I38_RESETVAL (0x00000000u)
/*----I38 Tokens----*/
#define CSL_EDMA3CC_ICRH_I38_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I37_MASK (0x00000020u)
#define CSL_EDMA3CC_ICRH_I37_SHIFT (0x00000005u)
#define CSL_EDMA3CC_ICRH_I37_RESETVAL (0x00000000u)
/*----I37 Tokens----*/
#define CSL_EDMA3CC_ICRH_I37_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I36_MASK (0x00000010u)
#define CSL_EDMA3CC_ICRH_I36_SHIFT (0x00000004u)
#define CSL_EDMA3CC_ICRH_I36_RESETVAL (0x00000000u)
/*----I36 Tokens----*/
#define CSL_EDMA3CC_ICRH_I36_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I35_MASK (0x00000008u)
#define CSL_EDMA3CC_ICRH_I35_SHIFT (0x00000003u)
#define CSL_EDMA3CC_ICRH_I35_RESETVAL (0x00000000u)
/*----I35 Tokens----*/
#define CSL_EDMA3CC_ICRH_I35_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I34_MASK (0x00000004u)
#define CSL_EDMA3CC_ICRH_I34_SHIFT (0x00000002u)
#define CSL_EDMA3CC_ICRH_I34_RESETVAL (0x00000000u)
/*----I34 Tokens----*/
#define CSL_EDMA3CC_ICRH_I34_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I33_MASK (0x00000002u)
#define CSL_EDMA3CC_ICRH_I33_SHIFT (0x00000001u)
#define CSL_EDMA3CC_ICRH_I33_RESETVAL (0x00000000u)
/*----I33 Tokens----*/
#define CSL_EDMA3CC_ICRH_I33_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_I32_MASK (0x00000001u)
#define CSL_EDMA3CC_ICRH_I32_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ICRH_I32_RESETVAL (0x00000000u)
/*----I32 Tokens----*/
#define CSL_EDMA3CC_ICRH_I32_CLEAR (0x00000001u)
#define CSL_EDMA3CC_ICRH_RESETVAL (0x00000000u)
/* IEVAL */
#define CSL_EDMA3CC_IEVAL_EVAL_MASK (0x00000001u)
#define CSL_EDMA3CC_IEVAL_EVAL_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IEVAL_EVAL_RESETVAL (0x00000000u)
/*----EVAL Tokens----*/
#define CSL_EDMA3CC_IEVAL_EVAL_EVAL (0x00000001u)
#define CSL_EDMA3CC_IEVAL_RESETVAL (0x00000000u)
/* QER */
#define CSL_EDMA3CC_QER_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QER_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QER_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QER_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QER_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QER_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QER_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QER_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QER_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QER_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QER_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QER_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QER_RESETVAL (0x00000000u)
/* QEER */
#define CSL_EDMA3CC_QEER_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QEER_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QEER_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEER_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QEER_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QEER_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEER_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QEER_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QEER_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEER_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QEER_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QEER_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEER_RESETVAL (0x00000000u)
/* QEECR */
#define CSL_EDMA3CC_QEECR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QEECR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QEECR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_QEECR_E3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QEECR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QEECR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QEECR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_QEECR_E2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QEECR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QEECR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QEECR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_QEECR_E1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QEECR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QEECR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QEECR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_QEECR_E0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QEECR_RESETVAL (0x00000000u)
/* QEESR */
#define CSL_EDMA3CC_QEESR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QEESR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QEESR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_QEESR_E3_SET (0x00000001u)
#define CSL_EDMA3CC_QEESR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QEESR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QEESR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_QEESR_E2_SET (0x00000001u)
#define CSL_EDMA3CC_QEESR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QEESR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QEESR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_QEESR_E1_SET (0x00000001u)
#define CSL_EDMA3CC_QEESR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QEESR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QEESR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_QEESR_E0_SET (0x00000001u)
#define CSL_EDMA3CC_QEESR_RESETVAL (0x00000000u)
/* QSER */
#define CSL_EDMA3CC_QSER_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QSER_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QSER_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QSER_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QSER_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QSER_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QSER_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QSER_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QSER_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QSER_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QSER_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QSER_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QSER_RESETVAL (0x00000000u)
/* QSECR */
#define CSL_EDMA3CC_QSECR_E3_MASK (0x00000008u)
#define CSL_EDMA3CC_QSECR_E3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_QSECR_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_QSECR_E3_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QSECR_E2_MASK (0x00000004u)
#define CSL_EDMA3CC_QSECR_E2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QSECR_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_QSECR_E2_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QSECR_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_QSECR_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_QSECR_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_QSECR_E1_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QSECR_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_QSECR_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QSECR_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_QSECR_E0_CLEAR (0x00000001u)
#define CSL_EDMA3CC_QSECR_RESETVAL (0x00000000u)
/* OPT */
#define CSL_EDMA3CC_OPT_PRIV_MASK (0x80000000u)
#define CSL_EDMA3CC_OPT_PRIV_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_OPT_PRIV_RESETVAL (0x00000000u)
/*----PRIV Tokens----*/
#define CSL_EDMA3CC_OPT_PRIV_USER (0x00000000u)
#define CSL_EDMA3CC_OPT_PRIV_SUPERVISOR (0x00000001u)
#define CSL_EDMA3CC_OPT_PRIVID_MASK (0x0F000000u)
#define CSL_EDMA3CC_OPT_PRIVID_SHIFT (0x00000018u)
#define CSL_EDMA3CC_OPT_PRIVID_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_OPT_ITCCHEN_MASK (0x00800000u)
#define CSL_EDMA3CC_OPT_ITCCHEN_SHIFT (0x00000017u)
#define CSL_EDMA3CC_OPT_ITCCHEN_RESETVAL (0x00000000u)
/*----ITCCHEN Tokens----*/
#define CSL_EDMA3CC_OPT_ITCCHEN_DISABLE (0x00000000u)
#define CSL_EDMA3CC_OPT_ITCCHEN_ENABLE (0x00000001u)
#define CSL_EDMA3CC_OPT_TCCHEN_MASK (0x00400000u)
#define CSL_EDMA3CC_OPT_TCCHEN_SHIFT (0x00000016u)
#define CSL_EDMA3CC_OPT_TCCHEN_RESETVAL (0x00000000u)
/*----TCCHEN Tokens----*/
#define CSL_EDMA3CC_OPT_TCCHEN_DISABLE (0x00000000u)
#define CSL_EDMA3CC_OPT_TCCHEN_ENABLE (0x00000001u)
#define CSL_EDMA3CC_OPT_ITCINTEN_MASK (0x00200000u)
#define CSL_EDMA3CC_OPT_ITCINTEN_SHIFT (0x00000015u)
#define CSL_EDMA3CC_OPT_ITCINTEN_RESETVAL (0x00000000u)
/*----ITCINTEN Tokens----*/
#define CSL_EDMA3CC_OPT_ITCINTEN_DISABLE (0x00000000u)
#define CSL_EDMA3CC_OPT_ITCINTEN_ENABLE (0x00000001u)
#define CSL_EDMA3CC_OPT_TCINTEN_MASK (0x00100000u)
#define CSL_EDMA3CC_OPT_TCINTEN_SHIFT (0x00000014u)
#define CSL_EDMA3CC_OPT_TCINTEN_RESETVAL (0x00000000u)
/*----TCINTEN Tokens----*/
#define CSL_EDMA3CC_OPT_TCINTEN_DISABLE (0x00000000u)
#define CSL_EDMA3CC_OPT_TCINTEN_ENABLE (0x00000001u)
#define CSL_EDMA3CC_OPT_TCC_MASK (0x0003F000u)
#define CSL_EDMA3CC_OPT_TCC_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_OPT_TCC_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_OPT_TCCMODE_MASK (0x00000800u)
#define CSL_EDMA3CC_OPT_TCCMODE_SHIFT (0x0000000Bu)
#define CSL_EDMA3CC_OPT_TCCMODE_RESETVAL (0x00000000u)
/*----TCCMODE Tokens----*/
#define CSL_EDMA3CC_OPT_TCCMODE_NORMAL (0x00000000u)
#define CSL_EDMA3CC_OPT_TCCMODE_EARLY (0x00000001u)
#define CSL_EDMA3CC_OPT_FWID_MASK (0x00000700u)
#define CSL_EDMA3CC_OPT_FWID_SHIFT (0x00000008u)
#define CSL_EDMA3CC_OPT_FWID_RESETVAL (0x00000000u)
/*----FWID Tokens----*/
#define CSL_EDMA3CC_OPT_FWID_8 (0x00000000u)
#define CSL_EDMA3CC_OPT_FWID_16 (0x00000001u)
#define CSL_EDMA3CC_OPT_FWID_32 (0x00000002u)
#define CSL_EDMA3CC_OPT_FWID_64 (0x00000003u)
#define CSL_EDMA3CC_OPT_FWID_128 (0x00000004u)
#define CSL_EDMA3CC_OPT_FWID_256 (0x00000005u)
#define CSL_EDMA3CC_OPT_STATIC_MASK (0x00000008u)
#define CSL_EDMA3CC_OPT_STATIC_SHIFT (0x00000003u)
#define CSL_EDMA3CC_OPT_STATIC_RESETVAL (0x00000000u)
/*----STATIC Tokens----*/
#define CSL_EDMA3CC_OPT_STATIC_NORMAL (0x00000000u)
#define CSL_EDMA3CC_OPT_STATIC_STATIC (0x00000001u)
#define CSL_EDMA3CC_OPT_SYNCDIM_MASK (0x00000004u)
#define CSL_EDMA3CC_OPT_SYNCDIM_SHIFT (0x00000002u)
#define CSL_EDMA3CC_OPT_SYNCDIM_RESETVAL (0x00000000u)
/*----SYNCDIM Tokens----*/
#define CSL_EDMA3CC_OPT_SYNCDIM_ASYNC (0x00000000u)
#define CSL_EDMA3CC_OPT_SYNCDIM_ABSYNC (0x00000001u)
#define CSL_EDMA3CC_OPT_DAM_MASK (0x00000002u)
#define CSL_EDMA3CC_OPT_DAM_SHIFT (0x00000001u)
#define CSL_EDMA3CC_OPT_DAM_RESETVAL (0x00000000u)
/*----DAM Tokens----*/
#define CSL_EDMA3CC_OPT_DAM_INCR (0x00000000u)
#define CSL_EDMA3CC_OPT_DAM_CONST (0x00000001u)
#define CSL_EDMA3CC_OPT_SAM_MASK (0x00000001u)
#define CSL_EDMA3CC_OPT_SAM_SHIFT (0x00000000u)
#define CSL_EDMA3CC_OPT_SAM_RESETVAL (0x00000000u)
/*----SAM Tokens----*/
#define CSL_EDMA3CC_OPT_SAM_INCR (0x00000000u)
#define CSL_EDMA3CC_OPT_SAM_CONST (0x00000001u)
#define CSL_EDMA3CC_OPT_RESETVAL (0x00000000u)
/* SRC */
#define CSL_EDMA3CC_SRC_SRC_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_SRC_SRC_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SRC_SRC_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SRC_RESETVAL (0x00000000u)
/* A_B_CNT */
#define CSL_EDMA3CC_A_B_CNT_BCNT_MASK (0xFFFF0000u)
#define CSL_EDMA3CC_A_B_CNT_BCNT_SHIFT (0x00000010u)
#define CSL_EDMA3CC_A_B_CNT_BCNT_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_A_B_CNT_ACNT_MASK (0x0000FFFFu)
#define CSL_EDMA3CC_A_B_CNT_ACNT_SHIFT (0x00000000u)
#define CSL_EDMA3CC_A_B_CNT_ACNT_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_A_B_CNT_RESETVAL (0x00000000u)
/* DST */
#define CSL_EDMA3CC_DST_DST_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_DST_DST_SHIFT (0x00000000u)
#define CSL_EDMA3CC_DST_DST_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DST_RESETVAL (0x00000000u)
/* SRC_DST_BIDX */
#define CSL_EDMA3CC_SRC_DST_BIDX_DSTBIDX_MASK (0xFFFF0000u)
#define CSL_EDMA3CC_SRC_DST_BIDX_DSTBIDX_SHIFT (0x00000010u)
#define CSL_EDMA3CC_SRC_DST_BIDX_DSTBIDX_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SRC_DST_BIDX_SRCBIDX_MASK (0x0000FFFFu)
#define CSL_EDMA3CC_SRC_DST_BIDX_SRCBIDX_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SRC_DST_BIDX_SRCBIDX_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SRC_DST_BIDX_RESETVAL (0x00000000u)
/* LINK_BCNTRLD */
#define CSL_EDMA3CC_LINK_BCNTRLD_BCNTRLD_MASK (0xFFFF0000u)
#define CSL_EDMA3CC_LINK_BCNTRLD_BCNTRLD_SHIFT (0x00000010u)
#define CSL_EDMA3CC_LINK_BCNTRLD_BCNTRLD_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_LINK_BCNTRLD_LINK_MASK (0x0000FFFFu)
#define CSL_EDMA3CC_LINK_BCNTRLD_LINK_SHIFT (0x00000000u)
#define CSL_EDMA3CC_LINK_BCNTRLD_LINK_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_LINK_BCNTRLD_RESETVAL (0x00000000u)
/* SRC_DST_CIDX */
#define CSL_EDMA3CC_SRC_DST_CIDX_DSTCIDX_MASK (0xFFFF0000u)
#define CSL_EDMA3CC_SRC_DST_CIDX_DSTCIDX_SHIFT (0x00000010u)
#define CSL_EDMA3CC_SRC_DST_CIDX_DSTCIDX_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SRC_DST_CIDX_SRCCIDX_MASK (0x0000FFFFu)
#define CSL_EDMA3CC_SRC_DST_CIDX_SRCCIDX_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SRC_DST_CIDX_SRCCIDX_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SRC_DST_CIDX_RESETVAL (0x00000000u)
/* CCNT */
#define CSL_EDMA3CC_CCNT_CCNT_MASK (0x0000FFFFu)
#define CSL_EDMA3CC_CCNT_CCNT_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CCNT_CCNT_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CCNT_RESETVAL (0x00000000u)
/* ER */
#define CSL_EDMA3CC_ER_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_ER_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ER_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ER_RESETVAL (0x00000000u)
/* ERH */
#define CSL_EDMA3CC_ERH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_ERH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ERH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ERH_RESETVAL (0x00000000u)
/* ECR */
#define CSL_EDMA3CC_ECR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_ECR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ECR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ECR_RESETVAL (0x00000000u)
/* ECRH */
#define CSL_EDMA3CC_ECRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_ECRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ECRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ECRH_RESETVAL (0x00000000u)
/* ESR */
#define CSL_EDMA3CC_ESR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_ESR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ESR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ESR_RESETVAL (0x00000000u)
/* ESRH */
#define CSL_EDMA3CC_ESRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_ESRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ESRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ESRH_RESETVAL (0x00000000u)
/* CER */
#define CSL_EDMA3CC_CER_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_CER_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CER_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CER_RESETVAL (0x00000000u)
/* CERH */
#define CSL_EDMA3CC_CERH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_CERH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CERH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_CERH_RESETVAL (0x00000000u)
/* EER */
#define CSL_EDMA3CC_EER_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_EER_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EER_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EER_RESETVAL (0x00000000u)
/* EERH */
#define CSL_EDMA3CC_EERH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_EERH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EERH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EERH_RESETVAL (0x00000000u)
/* EECR */
#define CSL_EDMA3CC_EECR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_EECR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EECR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EECR_RESETVAL (0x00000000u)
/* EECRH */
#define CSL_EDMA3CC_EECRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_EECRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EECRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EECRH_RESETVAL (0x00000000u)
/* EESR */
#define CSL_EDMA3CC_EESR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_EESR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EESR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EESR_RESETVAL (0x00000000u)
/* EESRH */
#define CSL_EDMA3CC_EESRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_EESRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_EESRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_EESRH_RESETVAL (0x00000000u)
/* SER */
#define CSL_EDMA3CC_SER_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_SER_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SER_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SER_RESETVAL (0x00000000u)
/* SERH */
#define CSL_EDMA3CC_SERH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_SERH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SERH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SERH_RESETVAL (0x00000000u)
/* SECR */
#define CSL_EDMA3CC_SECR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_SECR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SECR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SECR_RESETVAL (0x00000000u)
/* SECRH */
#define CSL_EDMA3CC_SECRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_SECRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_SECRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_SECRH_RESETVAL (0x00000000u)
/* IER */
#define CSL_EDMA3CC_IER_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_IER_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IER_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IER_RESETVAL (0x00000000u)
/* IERH */
#define CSL_EDMA3CC_IERH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_IERH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IERH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IERH_RESETVAL (0x00000000u)
/* IECR */
#define CSL_EDMA3CC_IECR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_IECR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IECR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IECR_RESETVAL (0x00000000u)
/* IECRH */
#define CSL_EDMA3CC_IECRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_IECRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IECRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IECRH_RESETVAL (0x00000000u)
/* IESR */
#define CSL_EDMA3CC_IESR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_IESR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IESR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IESR_RESETVAL (0x00000000u)
/* IESRH */
#define CSL_EDMA3CC_IESRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_IESRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IESRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IESRH_RESETVAL (0x00000000u)
/* IPR */
#define CSL_EDMA3CC_IPR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_IPR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IPR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPR_RESETVAL (0x00000000u)
/* IPRH */
#define CSL_EDMA3CC_IPRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_IPRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IPRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_IPRH_RESETVAL (0x00000000u)
/* ICR */
#define CSL_EDMA3CC_ICR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_ICR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ICR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ICR_RESETVAL (0x00000000u)
/* ICRH */
#define CSL_EDMA3CC_ICRH_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_ICRH_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_ICRH_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_ICRH_RESETVAL (0x00000000u)
/* IEVAL */
#define CSL_EDMA3CC_IEVAL_EVAL_MASK (0x00000001u)
#define CSL_EDMA3CC_IEVAL_EVAL_SHIFT (0x00000000u)
#define CSL_EDMA3CC_IEVAL_EVAL_RESETVAL (0x00000000u)
/*----EVAL Tokens----*/
#define CSL_EDMA3CC_IEVAL_EVAL_EVAL (0x00000001u)
#define CSL_EDMA3CC_IEVAL_RESETVAL (0x00000000u)
/* QER */
#define CSL_EDMA3CC_QER_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_QER_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QER_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QER_RESETVAL (0x00000000u)
/* QEER */
#define CSL_EDMA3CC_QEER_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_QEER_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QEER_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEER_RESETVAL (0x00000000u)
/* QEECR */
#define CSL_EDMA3CC_QEECR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_QEECR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QEECR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEECR_RESETVAL (0x00000000u)
/* QEESR */
#define CSL_EDMA3CC_QEESR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_QEESR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QEESR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QEESR_RESETVAL (0x00000000u)
/* QSER */
#define CSL_EDMA3CC_QSER_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_QSER_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QSER_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QSER_RESETVAL (0x00000000u)
/* QSECR */
#define CSL_EDMA3CC_QSECR_REG_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_QSECR_REG_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QSECR_REG_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QSECR_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/cache/csl_cacheL1.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_cacheL1.c
*
* @path $(CSLPATH)\src\cache
*
* @desc File for functional layer of L1 Cache
*
*/
/* =============================================================================
* Revision History
* ===============
* 23-Mar-2004 <NAME> File Created
*
* 21-Jun-2004 <NAME> modified.
*
* 24-Jan-2006 ds Updated CACHE_setL1pSize() API to return Old value
* =============================================================================
*/
#include <csl_cache.h>
#include <_csl_cache.h>
/** ============================================================================
* @n@b CACHE_freezeL1
*
* @b Description
* @n Freezes the L1P and L1D.
* @n As per the specification,
* @n a. The new freeze state is programmed in L1DCC, L1PCC.
* @n b. The old state is read from the L1DCC, L1PCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new state
* is programmed as well as reading the old programmed value.
*
* @b Arguments
* @n None
*
* <b> Return Value </b> CACHE_L1_Freeze
* @li CACHE_L1_FREEZE - Old Freeze State of L1 Cache
* @li CACHE_L1P_FREEZE - Old Freeze State of L1P Cache
* @li CACHE_L1D_FREEZE - Old Freeze State of L1D Cache
* @li CACHE_L1_NORMAL - Normal State of L1 Cache
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Freeze L1 cache
*
* @b Modifies
* @n L1DCC and L1PCC registers
*
* @b Example
* @verbatim
...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_freezeL1();
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_freezeL1, ".text:csl_section:cache");
CACHE_L1_Freeze CACHE_freezeL1(void)
{
Uint32 oldL1DFrz;
Uint32 oldL1PFrz;
/* Critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCC = \
CSL_FMK(CACHE_L1DCC_OPER, CSL_CACHE_L1DCC_OPER_FREEZE);
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCC = \
CSL_FMK(CACHE_L1PCC_OPER, CSL_CACHE_L1PCC_OPER_FREEZE);
oldL1DFrz = CSL_FEXT(((CSL_CacheRegsOvly) \
CSL_CACHE_0_REGS)->L1DCC, CACHE_L1DCC_POPER);
oldL1PFrz = CSL_FEXT(((CSL_CacheRegsOvly) \
CSL_CACHE_0_REGS)->L1PCC, CACHE_L1PCC_POPER);
asm(" rint");
/* End Critical section */
/* return cache state if a single freeze is returned then the other */
if (oldL1DFrz == CSL_CACHE_L1DCC_OPER_FREEZE) {
if (oldL1PFrz == CSL_CACHE_L1PCC_OPER_FREEZE)
return CACHE_L1_FREEZE;
else
return CACHE_L1D_FREEZE;
}
else {
if (oldL1PFrz == CSL_CACHE_L1PCC_OPER_FREEZE)
return CACHE_L1P_FREEZE;
else
return CACHE_L1_NORMAL;
}
}
/** ============================================================================
* @n@b CACHE_unfreezeL1
*
* @b Description
* @n Unfreezes the L1P and L1D.
* @n As per the specification,
* @n a. The new unfreeze state is programmed in L1DCC, L1PCC.
* @n b. The old state is read from the L1DCC, L1PCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new state
* is programmed as well as reading the old programmed value.
*
*
* @b Arguments
* @n None
*
* <b> Return Value </b> CACHE_L1_Freeze
* @li CACHE_L1_FREEZE - Old Freeze State of L1 Cache
* @li CACHE_L1P_FREEZE - Old Freeze State of L1P Cache
* @li CACHE_L1D_FREEZE - Old Freeze State of L1D Cache
* @li CACHE_L1_NORMAL - Normal State of L1 Cache
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Unfreeze L1 cache
*
* @b Modifies
* @n L1DCC and L1PCC registers
*
* @b Example
* @verbatim
...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_unfreezeL1();
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_unfreezeL1, ".text:csl_section:cache");
CACHE_L1_Freeze CACHE_unfreezeL1 (void)
{
Uint32 oldL1DFrz;
Uint32 oldL1PFrz;
/* Critical Section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCC = \
CSL_FMK(CACHE_L1DCC_OPER, CSL_CACHE_L1DCC_OPER_NORM);
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCC = \
CSL_FMK(CACHE_L1PCC_OPER, CSL_CACHE_L1PCC_OPER_NORM);
oldL1DFrz = CSL_FEXT(((CSL_CacheRegsOvly) \
CSL_CACHE_0_REGS)->L1DCC, CACHE_L1DCC_POPER);
oldL1PFrz = CSL_FEXT(((CSL_CacheRegsOvly) \
CSL_CACHE_0_REGS)->L1PCC, CACHE_L1PCC_POPER);
/* End Critical section */
asm(" rint");
/* return cache state if a single freeze is returned then the other
* cache is in normal mode
*/
if (oldL1DFrz == CSL_CACHE_L1DCC_OPER_FREEZE) {
if (oldL1PFrz == CSL_CACHE_L1PCC_OPER_FREEZE)
return CACHE_L1_FREEZE;
else
return CACHE_L1D_FREEZE;
}
else {
if (oldL1PFrz == CSL_CACHE_L1PCC_OPER_FREEZE)
return CACHE_L1P_FREEZE;
else
return CACHE_L1_NORMAL;
}
}
/** ============================================================================
* @n@b CACHE_setL1pSize
*
* @b Description
* @n Sets the L1P size.
* @n As per the specification,
* @n a. The new size is programmed in L1PCFG.
* @n b. L1PCFG is read back to ensure it is set.
*
* @b Arguments
* @verbatim
newSize New size to be programmed
@endverbatim
*
* <b> Return Value </b> CACHE_L1Size
* @li Old size of L1 Cache
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Set L1P cache size
*
* @b Modifies
* @n L1PCFG register
*
* @b Example
* @verbatim
...
CACHE_L1Size oldSize ;
oldSize = CACHE_setL1pSize(CACHE_L1_32KCACHE);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_setL1pSize, ".text:csl_section:cache");
CACHE_L1Size CACHE_setL1pSize (
CACHE_L1Size newSize
)
{
Uint32 curSize;
curSize = ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCFG;
/* Critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCFG = newSize;
newSize = (CACHE_L1Size)((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCFG;
/* End Critical section */
asm(" rint");
return (CACHE_L1Size) (curSize);
}
/** ============================================================================
* @n@b CACHE_freezeL1p
*
* @b Description
* @n Freezes L1P.
* @n As per the specification,
* @n a. The new freeze state is programmed in L1PCC.
* @n b. The old state is read from the L1PCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new state
* is programmed as well as reading the old programmed value.
*
* @b Arguments
* @n None
*
* <b> Return Value </b> CACHE_L1_Freeze
* @li CACHE_L1P_FREEZE - Old Freeze State of L1P Cache
* @li CACHE_L1P_NORMAL - Normal State of L1P Cache
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Freeze L1P cache
*
* @b Modifies
* @n L1PCC register
*
* @b Example
* @verbatim
...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_freezeL1p();
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_freezeL1p, ".text:csl_section:cache");
CACHE_L1_Freeze CACHE_freezeL1p (void)
{
Uint32 oldL1PFrz;
/* Critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCC = \
CSL_FMK(CACHE_L1PCC_OPER, CSL_CACHE_L1PCC_OPER_FREEZE);
oldL1PFrz =
CSL_FEXT(((CSL_CacheRegsOvly) \
CSL_CACHE_0_REGS)->L1PCC, CACHE_L1PCC_POPER);
/* End Critical Section */
asm(" rint");
if(oldL1PFrz == CSL_CACHE_L1PCC_OPER_FREEZE)
return CACHE_L1P_FREEZE;
else
return CACHE_L1P_NORMAL;
}
/** ============================================================================
* @n@b CACHE_unfreezeL1p
*
* @b Description
* @n Unfreezes L1P.
* @n As per the specification,
* @n a. The normal state is programmed in L1PCC
* @n b. The old state is read from the L1PCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new state
* is programmed as well as reading the old programmed value.
*
* @b Arguments
* @n None
*
* <b> Return Value </b> CACHE_L1_Freeze
* @li CACHE_L1P_FREEZE - Old Freeze State of L1P Cache
* @li CACHE_L1P_NORMAL - Normal State of L1P Cache
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Unreeze L1P cache
*
* @b Modifies
* @n L1PCC register
*
* @b Example
* @verbatim
...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_unfreezeL1p();
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_unfreezeL1p, ".text:csl_section:cache");
CACHE_L1_Freeze CACHE_unfreezeL1p (void)
{
Uint32 temp;
/* Critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCC =
CSL_FMK(CACHE_L1PCC_OPER, CSL_CACHE_L1PCC_OPER_NORM);
temp = CSL_FEXT(((CSL_CacheRegsOvly) \
CSL_CACHE_0_REGS)->L1PCC, CACHE_L1PCC_POPER);
/* End Critical Section */
asm(" rint");
if(temp == CSL_CACHE_L1PCC_OPER_NORM)
return CACHE_L1P_NORMAL;
else
return CACHE_L1P_FREEZE;
}
/** ============================================================================
* @n@b CACHE_invL1p
*
* @b Description
* @n Invalidates range specified in L1P.
* @n As per the specification,
* @n a. The start of the range that needs to be invalidated is written
* into L1PIBAR
* @n b. The byte count is programmed in L1PIWC.
*
* @b Arguments
* @verbatim
blockPtr Start address of range to be invalidated
byteCnt Number of bytes to be invalidated
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Invalidate L1P cache
*
* @b Modifies
* @n L1PIBAR and L1PIWC registers
*
* @b Example
* @verbatim
...
CACHE_invL1p ((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_invL1p, ".text:csl_section:cache");
void CACHE_invL1p (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* treat BAR/WC as crit section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PIBAR = (Uint32)blockPtr;
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PIWC = ((byteCnt+3)>>2);
_CSL_cachebusyState = CACHE_WAIT_L1PINV;
/* End Critical section */
asm(" rint");
if (wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_invAllL1p
*
* @b Description
* @n Invalidates all of L1P.
* @n As per the specification,
* @n a. The L1PINV is programmed.
*
* @b Arguments
* @verbatim
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Invalidate all L1P cache
*
* @b Modifies
* @n L1PINV register
*
* @b Example
* @verbatim
...
CACHE_invAllL1p (CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_invAllL1p, ".text:csl_section:cache");
void CACHE_invAllL1p (
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* Critical Section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PINV = 1;
_CSL_cachebusyState = CACHE_WAIT_L1PINVALL;
/* End Critical Section */
asm(" rint");
if (wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_setL1dSize
*
* @b Description
* @n Sets the L1D size.
* @n As per the specification,
* @n a. The new size is programmed in L1DCFG
* @n b. L1DCFG is read back to ensure it is set.
*
* @b Arguments
* @verbatim
newSize New size to be programmed
@endverbatim
*
* <b> Return Value </b> CACHE_L1Size
* @li Old Size set for L1D
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Set L1D cache size
*
* @b Modifies
* @n L1DCFG register
*
* @b Example
* @verbatim
...
CACHE_L1Size oldSize ;
oldSize = CACHE_setL1dSize(CACHE_L1_32KCACHE);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_setL1dSize, ".text:csl_section:cache");
CACHE_L1Size CACHE_setL1dSize (
CACHE_L1Size newSize
)
{
Uint32 curSize;
curSize = ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCFG;
/* Critical Section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCFG = newSize;
newSize = (CACHE_L1Size)((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCFG;
/* End critical section */
asm(" rint");
return (CACHE_L1Size) (curSize);
}
/** ============================================================================
* @n@b CACHE_freezeL1d
*
* @b Description
* @n Freezes L1D.
* @n As per the specification,
* @n a. The new freeze state is programmed in L1DCC.
* @n b. The old state is read from the L1DCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new state
* is programmed as well as reading the old programmed value.
*
* @b Arguments
* @n None
*
* <b> Return Value </b> CACHE_L1_Freeze
* @li CACHE_L1D_FREEZE - Old Freeze State of L1D Cache
* @li CACHE_L1D_NORMAL - Normal State of L1D Cache
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Freeze L1D cache
*
* @b Modifies
* @n L1DCC register
*
* @b Example
* @verbatim
...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_freezeL1d();
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_freezeL1d, ".text:csl_section:cache");
CACHE_L1_Freeze CACHE_freezeL1d (void)
{
Uint32 temp;
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCC =
CSL_FMK(CACHE_L1DCC_OPER, CSL_CACHE_L1DCC_OPER_FREEZE);
temp = CSL_FEXT(((CSL_CacheRegsOvly) \
CSL_CACHE_0_REGS)->L1DCC, CACHE_L1DCC_POPER);
/* End critical section */
asm(" rint");
if(temp == CSL_CACHE_L1DCC_OPER_FREEZE)
return CACHE_L1D_FREEZE;
else
return CACHE_L1D_NORMAL;
}
/** ============================================================================
* @n@b CACHE_unfreezeL1d
*
* @b Description
* @n Unfreezes L1D.
* @n As per the specification,
* @n a. The normal state is programmed in L1DCC
* @n b. The old state is read from the L1DCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new state
* is programmed as well as reading the old programmed value.
*
* @b Arguments
* @n None
*
* <b> Return Value </b> CACHE_L1_Freeze
* @li CACHE_L1D_FREEZE - Old Freeze State of L1D Cache
* @li CACHE_L1D_NORMAL - Normal State of L1D Cache
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Unfreeze L1D cache
*
* @b Modifies
* @n L1DCC register
*
* @b Example
* @verbatim
...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_unfreezeL1d();
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_unfreezeL1d, ".text:csl_section:cache");
CACHE_L1_Freeze CACHE_unfreezeL1d (void)
{
Uint32 temp;
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCC =
CSL_FMK(CACHE_L1DCC_OPER, CSL_CACHE_L1DCC_OPER_NORM);
temp = CSL_FEXT(((CSL_CacheRegsOvly) \
CSL_CACHE_0_REGS)->L1DCC, CACHE_L1DCC_POPER);
/* End critical section */
asm(" rint");
if(temp == CSL_CACHE_L1DCC_OPER_NORM)
return CACHE_L1D_NORMAL;
else
return CACHE_L1D_FREEZE;
}
/** ============================================================================
* @n@b CACHE_wbL1d
*
* @b Description
* @n Writes back range specified in L1D.
* @n As per the specification,
* @n a. The start of the range that needs to be written back is programmed
* into L1DWBAR.
* @n b. The byte count is programmed in L1DWWC.
*
* @b Arguments
* @verbatim
blockPtr Start address of range to be written back
byteCnt Number of bytes to be written back
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed or not.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Writeback L1D cache
*
* @b Modifies
* @n L1DWWC and L1DWBAR registers
*
* @b Example
* @verbatim
...
CACHE_wbL1d((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wbL1d, ".text:csl_section:cache");
void CACHE_wbL1d (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* Critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWBAR = (Uint32)blockPtr;
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWWC =((byteCnt+3)>>2);
_CSL_cachebusyState = CACHE_WAIT_L1DWB;
_CSL_cacheEmifState = (CACHE_emifState) \
(CSL_CACHE_EMIF_ISRANGE((Uint32)blockPtr)
+ CSL_CACHE_EMIF_ISEMIFBRANGE((Uint32)blockPtr));
/* End critical section */
asm(" rint");
if (wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_invL1d
*
* @b Description
* @n Invalidates range specified in L1D.
* @n As per the specification,
* @n a. The start of the range that needs to be invalidated is written
* into L1DIBAR.
* @n b. The byte count is programmed in L1DIWC.
*
* @b Arguments
* @verbatim
blockPtr Start address of range to be invalidated
byteCnt Number of bytes to be invalidated
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Invalidate the L1D cache
*
* @b Modifies
* @n L1DIWC and L1DIBAR registers
*
* @b Example
* @verbatim
...
CACHE_invL1d ((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_invL1d, ".text:csl_section:cache");
void CACHE_invL1d (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DIBAR = (Uint32)blockPtr;
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DIWC = ((byteCnt+3)>>2);
_CSL_cachebusyState = CACHE_WAIT_L1DINV;
/* End critical section */
asm(" rint");
if (wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_wbInvL1d
*
* @b Description
* @n Writeback invalidates range specified in L1D.
* @n As per the specification,
* @n a. The start of the range that needs to be writeback invalidated is
* programmed into L1DWIBAR.
* @n b. The byte count is programmed in L1DWIWC.
*
* @b Arguments
* @verbatim
blockPtr Start address of range to be written back invalidated
byteCnt Number of bytes to be written back invalidated
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Witebacvk and invalidate the L1D cache
*
* @b Modifies
* @n L1DWIWC and L1DWIBAR registers
*
* @b Example
* @verbatim
...
CACHE_wbInvL1d ((Uint32*)(0x1000),200,CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wbInvL1d, ".text:csl_section:cache");
void CACHE_wbInvL1d (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWIBAR = (Uint32)blockPtr;
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWIWC = ((byteCnt+3)>>2);
_CSL_cachebusyState = CACHE_WAIT_L1DWBINV;
_CSL_cacheEmifState = (CACHE_emifState) \
(CSL_CACHE_EMIF_ISRANGE((Uint32)blockPtr) \
+ CSL_CACHE_EMIF_ISEMIFBRANGE((Uint32)blockPtr));
/* End critical section */
asm(" rint");
if (wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_wbAllL1d
*
* @b Description
* @n Writeback All of L1D.
* @n As per the specification,
* @n a. The L1DWB is programmed.
*
* @b Arguments
* @verbatim
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Writeback all the L1D cache
*
* @b Modifies
* @n L1DWB register
*
* @b Example
* @verbatim
...
CACHE_wbAllL1d (CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wbAllL1d, ".text:csl_section:cache");
void CACHE_wbAllL1d (
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWB = 1;
_CSL_cachebusyState = CACHE_WAIT_L1DWBALL;
_CSL_cacheEmifState = CACHE_EMIF_AB;
/* End critical section */
asm(" rint");
if (wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_invAllL1d
*
* @b Description
* @n Invalidates All of L1D.
* @n As per the specification,
* @n a. The L1DINV is programmed.
*
* @b Arguments
* @verbatim
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Invalidate the all L1D cache
*
* @b Modifies
* @n L1DINV register
*
* @b Example
* @verbatim
...
CACHE_invAllL1d (CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_invAllL1d, ".text:csl_section:cache");
void CACHE_invAllL1d (
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DINV = 1;
_CSL_cachebusyState = CACHE_WAIT_L1DINVALL;
/* End critical section */
asm(" rint");
if (wait)
_CACHE_wait(wait);
}
/** ============================================================================
* @n@b CACHE_wbInvAllL1d
*
* @b Description
* @n Writeback invalidates All of L1D.
* @n As per the specification,
* @n a. The L1DWBINV is programmed.
*
* @b Arguments
* @verbatim
wait Whether the call is blocking (and the extent of wait)
till the issued operation is completed.
Whether the function must exit on completion/or not.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The CACHE must be succesfully enabled via CACHE_enableCaching() before
* calling this function.
*
* <b> Post Condition </b>
* @n Writeback and invalidate all L1D cache
*
* @b Modifies
* @n L1DWBINV register
*
* @b Example
* @verbatim
...
CACHE_wbInvAllL1d (CACHE_NOWAIT);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wbInvAllL1d, ".text:csl_section:cache");
void CACHE_wbInvAllL1d (
CACHE_Wait wait
)
{
CACHE_waitInternal();
/* critical section */
asm(" dint");
((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWBINV = 1;
_CSL_cachebusyState = CACHE_WAIT_L1DWBINVALL;
_CSL_cacheEmifState = CACHE_EMIF_AB;
/* End of critical section */
asm(" rint");
if (wait)
_CACHE_wait(wait);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/csl_srioAux.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* =========================================================================
*/
/** ===========================================================================
* @file csl_srioAux.h
*
* @brief API Auxilary header file for SRIO CSL
*
* @path $(CSLPATH)\srio\inc
*
* @desc It gives the definitions of the status query and control functions.
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 26-Aug-2005 PSK File Created.
* ============================================================================
*/
#ifndef _CSL_SRIOAUX_H_
#define _CSL_SRIOAUX_H_
#include <csl_srio.h>
#ifdef __cplusplus
extern "C" {
#endif
/** ============================================================================
* @n@b CSL_SrioDoorbellIntrClear
*
* @b Description
* @n This function Clears doorbell interrupts. Macros can be OR'ed to get
* the value
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
clearData pointer to the clear value
@endverbatim
*
* <b> Return Value </b> None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData clearData;
clearData.data = CSL_SRIO_DOORBELL_INTR0 |
CSL_SRIO_DOORBELL_INTR1 |
CSL_SRIO_DOORBELL_INTR2;
clearData.index = 1;
...
CSL_SrioDoorbellIntrClear(hSrio, &clearData);
...
@endverbatim
* ============================================================================
*/
static inline
void CSL_SrioDoorbellIntrClear (
CSL_SrioHandle hSrio,
CSL_SrioPortData *clearData
)
{
hSrio->regs->DOORBELL_INTR[clearData->index].DOORBELL_ICCR =
clearData->data;
}
/** ===========================================================================
* @n@b CSL_SrioSrcAddrSet
*
* @b Description
* @n This function Sets 32-bit DSP byte source address
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg contains the source address and index
@endverbatim
*
* <b> Return Value </b> None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.data = 0x050;
arg.index = 1; //index to the LSU BLOCKs
...
CSL_SrioSrcAddrSet(hSrio, &arg);
...
@endverbatim
* ============================================================================
*/
static inline
void CSL_SrioSrcAddrSet (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
hSrio->regs->LSU[arg->index].LSU_REG2 = arg->data;
}
/** ===========================================================================
* @n@b CSL_SrioDstAddrMsbSet
*
* @b Description
* @n This function Sets the rapid IO destination MSB address
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg pointer to the structure that contains destination MSB
address and index to LSU registers set
@endverbatim
*
* <b> Return Value </b> None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 2;
arg.data = 0x02e00000; // destination address
...
CSL_SrioDstAddrMsbSet(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioDstAddrMsbSet (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
hSrio->regs->LSU[arg->index].LSU_REG0 = arg->data;
}
/** ===========================================================================
* @n@b CSL_SrioDstAddrLsbSet
*
* @b Description
* @n This function Sets the rapid IO destination LSB address
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg pointer to the structure that contains destination LSB
address and index to LSU registers set
@endverbatim
*
* <b> Return Value </b> None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 2;
arg.data = 0x02e00000; // destination address
...
CSL_SrioDstAddrLsbSet(hSrio, &arg);
...
@endverbatim
* ============================================================================
*/
static inline
void CSL_SrioDstAddrLsbSet (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
hSrio->regs->LSU[arg->index].LSU_REG1 = arg->data;
}
/** ===========================================================================
* @n@b CSL_SrioLsuXfrByteCntSet
*
* @b Description
* @n This function sets the Number of data bytes to Read/Write - up to 4KB
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg pointer to the structure that contains Number of data bytes
to Read/Write and index to LSU registers set
@endverbatim
*
* <b> Return Value </b> None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 2;
arg.data = 0x0f;
...
CSL_SrioLsuXfrByteCntSet(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioLsuXfrByteCntSet (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
CSL_FINS(hSrio->regs->LSU[arg->index].LSU_REG3,
SRIO_LSU_REG3_BYTE_COUNT, arg->data);
}
/** ============================================================================
* @n@b CSL_SrioLsuXfrTypeSet
*
* @b Description
* Sets 4 MSBs to 4-bit ftype field for all packets
* and 4 LSBs to 4-bit trans field for Packet types 2,5 and 8
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg pointer to the structure that contains transfer type
and index to LSU registers set
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 2;
arg.data = 2; //packet type
...
CSL_SrioLsuXfrTypeSet(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioLsuXfrTypeSet (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
CSL_FINS(hSrio->regs->LSU[arg->index].LSU_REG5,
SRIO_LSU_REG5_PACKET_TYPE, arg->data);
}
/** ============================================================================
* @n@b CSL_SrioDoorbellXfrTypeSet
*
* @b Description
* Sets RapidIO doorbell info field for type 10 packets and sets the
* packet type to 10.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg pointer to the structure that contains doorbell info
and index to LSU registers set
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None.
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 2;
arg.data = 0; //doorbell info for type 10 packets
...
CSL_SrioDoorbellXfrTypeSet(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioDoorbellXfrTypeSet (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
Uint32 val = hSrio->regs->LSU[arg->index].LSU_REG5;
CSL_FINS (val, SRIO_LSU_REG5_DRBLL_INFO, arg->data);
CSL_FINS (val, SRIO_LSU_REG5_PACKET_TYPE, 10); /* Doorbell packet type */
hSrio->regs->LSU[arg->index].LSU_REG5 = val;
}
/** ============================================================================
* @n@b CSL_SrioLsuFlowMaskSet
*
* @b Description
* Sets LSU flow masks.Port number is passed as input.
* Macros can be OR'ed to get the value for argument
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg pointer to the structure that contains flowmask value
and index to LSU registers set
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None.
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 1;
arg.data = 0x0;
...
CSL_SrioLsuFlowMaskSet(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioLsuFlowMaskSet (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
hSrio->regs->LSU[arg->index].LSU_FLOW_MASKS = arg->data;
}
/** ============================================================================
* @n@b CSL_SrioPortCmdSet
*
* @b Description
* Sets the command to be sent in the link-request control symbol
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg pointer to structure that contains the command value and
index to ports
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 2;
arg.data = 0x0;
...
CSL_SrioPortCmdSet(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioPortCmdSet (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
CSL_FINS(hSrio->regs->PORT[arg->index].SP_LM_REQ,
SRIO_SP_LM_REQ_COMMAND, arg->data);
}
/** ============================================================================
* @n@b CSL_SrioSpErrStatClear
*
* @b Description
* Clear port errors status. Macros can be OR'ed to get the value to
* pass the argument
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to a structure containing the error status
clear value and index to the port
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 0;
arg.data = CSL_SRIO_ERR_OUTPUT_PKT_DROP |
CSL_SRIO_ERR_OUTPUT_FLD_ENC |
CSL_SRIO_ERR_OUTPUT_DEGRD_ENC |
...
CSL_SRIO_INPUT_ERROR_ENC;
CSL_SrioSpErrStatClear(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioSpErrStatClear (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
hSrio->regs->PORT[arg->index].SP_ERR_STAT = arg->data;
}
/** ============================================================================
* @n@b CSL_SrioSpErrDetStatClear
*
* @b Description
* Clear port error detect status. Macros can be OR'ed to get the value
* to pass the argument
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 3;
arg.data = CSL_SRIO_ERR_IMP_SPECIFIC |
CSL_SRIO_CORRUPT_CNTL_SYM
...
CSL_SRIO_RCVD_PKT_WITH_BAD_CRC;
CSL_SrioSpErrDetStatClear(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioSpErrDetStatClear (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
hSrio->regs->PORT_ERROR[arg->index].SP_ERR_DET = arg->data;
}
/** ============================================================================
* @n@b CSL_SrioCntlSymSet
*
* @b Description
* Sets up the registers for sending a control symbol
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the control symbol structure
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioCntlSym arg;
...
CSL_SrioCntlSymSet(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioCntlSymSet (
CSL_SrioHandle hSrio,
CSL_SrioCntlSym *arg
)
{
hSrio->regs->PORT_OPTION[arg->portNum].SP_CS_TX =
CSL_FMK(SRIO_SP_CS_TX_STYPE_0, arg->stype0) |
CSL_FMK(SRIO_SP_CS_TX_PAR_0, arg->par0) |
CSL_FMK(SRIO_SP_CS_TX_PAR_1, arg->par1) |
CSL_FMK(SRIO_SP_CS_TX_STYPE_1, arg->stype1) |
CSL_FMK(SRIO_SP_CS_TX_CMD, arg->cmd) |
CSL_FMK(SRIO_SP_CS_TX_CS_EMB, arg->emb);
}
/** ============================================================================
* @n@b CSL_SrioSpCtlIndepErrStatClear
*
* @b Description
* Clears port control independent status register bits.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
arg.index = 1;
arg.data = 0x10040; //clears corresponding error status
...
CSL_SrioSpCtlIndepErrStatClear(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioSpCtlIndepErrStatClear (
CSL_SrioHandle hSrio,
CSL_SrioPortData *arg
)
{
hSrio->regs->PORT_OPTION[arg->index].SP_CTL_INDEP = arg->data;
}
/** ============================================================================
* @n@b CSL_SrioPerEn
*
* @b Description
* Enables/disables the peripheral.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg value to be configured
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Bool arg = 0x0;
...
CSL_SrioPerEn(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioPerEn (
CSL_SrioHandle hSrio,
Bool arg
)
{
CSL_FINS(hSrio->regs->PCR, SRIO_PCR_PEREN, arg);
}
/** ============================================================================
* @n@b CSL_SrioPllCntlSet
*
* @b Description
* Enables/disables the PLL.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Value to enable/disable the 4 PLL
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint8 arg = CSL_SRIO_PLL1_ENABLE |
CSL_SRIO_PLL2_ENABLE |
...
CSL_SRIO_PLL4_ENABLE;
...
CSL_SrioPllCntlSet(hSrio, arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioPllCntlSet (
CSL_SrioHandle hSrio,
Uint8 arg
)
{
CSL_FINSR(hSrio->regs->PER_SET_CNTL, 3, 0, arg);
}
/** ============================================================================
* @n@b CSL_SrioLsuIntrClear
*
* @b Description
* Clears LSU interrupt status bits corresponding to the bits set .
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Mask cotaining the status bits to be cleared
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 arg;
arg = CSL_SRIO_LSU_INTR0 |
CSL_SRIO_LSU_INTR1 |
CSL_SRIO_LSU_INTR2;
...
CSL_SrioLsuIntrClear(hSrio, arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioLsuIntrClear (
CSL_SrioHandle hSrio,
Uint32 arg
)
{
hSrio->regs->LSU_ICCR = arg;
}
/** ============================================================================
* @n@b CSL_SrioErrRstIntrClear
*
* @b Description
* Clears error interrupt status bits corresponding to the bits set .
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Mask cotaining the status bits to be cleared
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 arg;
arg = CSL_SRIO_ERR_DEV_RST_INTR |
CSL_SRIO_ERR_PORT3_INTR |
...
CSL_SRIO_ERR_LGCL_INTR;
...
CSL_SrioErrRstIntrClear(hSrio, arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioErrRstIntrClear (
CSL_SrioHandle hSrio,
Uint32 arg
)
{
hSrio->regs->ERR_RST_EVNT_ICCR = arg;
}
/** ============================================================================
* @n@b CSL_SrioLgclTrnsErrStatClear
*
* @b Description
* Clears logical ransport layer error status bits corresponding to
* the bits set .
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Mask cotaining the status bits to be cleared
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 arg;
arg = CSL_SRIO_IO_ERR_RSPNS |
CSL_SRIO_ILL_TRANS_DECODE |
...
CSL_SRIO_UNSOLICITED_RSPNS;
...
CSL_SrioLgclTrnsErrStatClear(hSrio, arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioLgclTrnsErrStatClear (
CSL_SrioHandle hSrio,
Uint32 arg
)
{
hSrio->regs->ERR_DET = arg;
}
/** ============================================================================
* @n@b CSL_SrioSetIntdstRateCntl
*
* @b Description
* Sets interrupt rate control counter
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Mask cotaining the status bits to be cleared
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 arg;
arg = 0x100;
...
CSL_SrioSetIntdstRateCntl(hSrio, arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioSetIntdstRateCntl (
CSL_SrioHandle hSrio,
Uint32 arg
)
{
hSrio->regs->INTDST_RATE_CNTL[0] = arg;
}
/** ============================================================================
* @n@b CSL_srioGetPid
*
* @b Description
* Quries the peripheral identification details.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure to return the peripheral details
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPidNumber arg;
...
CSL_srioGetPid(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetPid (
CSL_SrioHandle hSrio,
CSL_SrioPidNumber *response
)
{
response->srioType = CSL_FEXT(hSrio->regs->PID, SRIO_PID_TYPE);
response->srioClass = CSL_FEXT(hSrio->regs->PID, SRIO_PID_CLASS);
response->srioRevision = CSL_FEXT(hSrio->regs->PID, SRIO_PID_REV);
}
/** ============================================================================
* @n@b CSL_srioGetBlkEnStat
*
* @b Description
* Quries the enabled blocks of the peripheral.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure to return the status of different blocks
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioBlkEn arg;
...
CSL_srioGetBlkEnStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetBlkEnStat (
CSL_SrioHandle hSrio,
CSL_SrioBlkEn *response
)
{
response->block0 = (Bool)hSrio->regs->BLK_ENABLE[0].BLK_EN_STAT;
response->block1 = (Bool)hSrio->regs->BLK_ENABLE[1].BLK_EN_STAT;
response->block2 = (Bool)hSrio->regs->BLK_ENABLE[2].BLK_EN_STAT;
response->block3 = (Bool)hSrio->regs->BLK_ENABLE[3].BLK_EN_STAT;
response->block4 = (Bool)hSrio->regs->BLK_ENABLE[4].BLK_EN_STAT;
response->block5 = (Bool)hSrio->regs->BLK_ENABLE[5].BLK_EN_STAT;
response->block6 = (Bool)hSrio->regs->BLK_ENABLE[6].BLK_EN_STAT;
response->block7 = (Bool)hSrio->regs->BLK_ENABLE[7].BLK_EN_STAT;
response->block8 = (Bool)hSrio->regs->BLK_ENABLE[8].BLK_EN_STAT;
}
/** ============================================================================
* @n@b CSL_srioGetDoorbellIntrStat
*
* @b Description
* Quries the doorbell interrupts status.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioGetDoorbellIntrStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetDoorbellIntrStat (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data = hSrio->regs->DOORBELL_INTR[response->index].DOORBELL_ICSR;
}
/** ============================================================================
* @n@b CSL_srioLsuCompCodeStat
*
* @b Description
* Quries the completion code status of LSU.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
LSU completion code
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioLsuCompStat arg;
...
CSL_srioLsuCompCodeStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioLsuCompCodeStat(
CSL_SrioHandle hSrio,
CSL_SrioLsuCompStat *response
)
{
response->lsuCompCode = (CSL_SrioCompCode)CSL_FEXT(
hSrio->regs->LSU[response->portNum].LSU_REG6,
SRIO_LSU_REG6_COMPLETION_CODE);
}
/** ============================================================================
* @n@b CSL_srioLsuBsyStat
*
* @b Description
* Quries the LSU busy status.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioLsuBsyStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioLsuBsyStat (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data = CSL_FEXT(hSrio->regs->LSU[response->index].LSU_REG6,
SRIO_LSU_REG6_BSY);
}
/** ============================================================================
* @n@b CSL_srioGetDevIdInfo
*
* @b Description
* Quries the device identity.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, device info
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioDevInfo arg;
...
CSL_srioGetDevIdInfo(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetDevIdInfo (
CSL_SrioHandle hSrio,
CSL_SrioDevInfo *response
)
{
response->devId = CSL_FEXT(hSrio->regs->DEV_ID, SRIO_DEV_ID_DEVICEIDENTITY);
response->devVendorId = CSL_FEXT(hSrio->regs->DEV_ID,
SRIO_DEV_ID_DEVICE_VENDORIDENTITY);
response->devRevision = CSL_FEXT(hSrio->regs->DEV_INFO,
SRIO_DEV_INFO_DEVICEREV);
}
/** ============================================================================
* @n@b CSL_srioGetAssyIdInfo
*
* @b Description
* Quries the device assembly identity.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, assembly info of
the peripheral
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioAssyInfo arg;
...
CSL_srioGetAssyIdInfo(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetAssyIdInfo (
CSL_SrioHandle hSrio,
CSL_SrioAssyInfo *response
)
{
response->assyId = CSL_FEXT(hSrio->regs->ASBLY_ID,
SRIO_ASBLY_ID_ASSY_IDENTITY);
response->assyVendorId = CSL_FEXT(hSrio->regs->ASBLY_ID,
SRIO_ASBLY_ID_ASSY_VENDORIDENTITY);
response->assyRevision = CSL_FEXT(hSrio->regs->ASBLY_INFO,
SRIO_ASBLY_INFO_ASSYREV);
}
/** ============================================================================
* @n@b CSL_srioGetLclCfgBar
*
* @b Description
* Quries long address of programmed for the LSU
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify the long address
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioLongAddress arg;
...
CSL_srioGetLclCfgBar(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetLclCfgBar(
CSL_SrioHandle hSrio,
CSL_SrioLongAddress *response
)
{
response->addressHi = hSrio->regs->LCL_CFG_HBAR;
response->addressLo = hSrio->regs->LCL_CFG_BAR;
}
/** ============================================================================
* @n@b CSL_srioGetSpLmRespStat
*
* @b Description
* Quries the link maintainance response status.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioGetSpLmRespStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetSpLmRespStat (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data = hSrio->regs->PORT[response->index].SP_LM_RESP;
}
/** ============================================================================
* @n@b CSL_srioGetSpAckIdStat
*
* @b Description
* Quries port ACK ID status.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioGetSpAckIdStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetSpAckIdStat (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data = hSrio->regs->PORT[response->index].SP_ACKID_STAT;
}
/** ============================================================================
* @n@b CSL_srioGetSpErrStat
*
* @b Description
* Quries the port error status.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioGetSpErrStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetSpErrStat (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data = hSrio->regs->PORT[response->index].SP_ERR_STAT;
}
/** ============================================================================
* @n@b CSL_srioGetSpCtlStat
*
* @b Description
* Quries the port control status.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioGetSpCtlStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetSpCtlStat (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data = hSrio->regs->PORT[response->index].SP_CTL;
}
/** ============================================================================
* @n@b CSL_srioGetLgclTransErrCapt
*
* @b Description
* Quries captured error information of
* logical/transport layer status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, captured error
information of logical/transport layer
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioLogTrErrInfo arg;
...
CSL_srioGetLgclTransErrCapt(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetLgclTransErrCapt (
CSL_SrioHandle hSrio,
CSL_SrioLogTrErrInfo *response
)
{
response->errAddrHi = hSrio->regs->H_ADDR_CAPT;
response->errAddrLo = CSL_FEXT(hSrio->regs->ADDR_CAPT,
SRIO_ADDR_CAPT_ADDRESS_31_3);
response->xambs = CSL_FEXT(hSrio->regs->ADDR_CAPT,
SRIO_ADDR_CAPT_XAMSBS);
response->destId = CSL_FEXTR(hSrio->regs->ID_CAPT, 31, 16);
response->srcId = CSL_FEXTR(hSrio->regs->ID_CAPT, 15, 0);
response->ftype = CSL_FEXT(hSrio->regs->CTRL_CAPT, SRIO_CTRL_CAPT_FTYPE);
response->tType = CSL_FEXT(hSrio->regs->CTRL_CAPT, SRIO_CTRL_CAPT_TTYPE);
//response->msgInfo = CSL_FEXT(hSrio->regs->CTRL_CAPT, SRIO_CTRL_CAPT_MSGINFO);
response->impSpecific = CSL_FEXT(hSrio->regs->CTRL_CAPT,
SRIO_CTRL_CAPT_IMP_SPECIFIC);
}
/** ============================================================================
* @n@b CSL_srioGetSpErrDetStat
*
* @b Description
* Quries the port error detect status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioGetSpErrDetStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetSpErrDetStat (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data = hSrio->regs->PORT_ERROR[response->index].SP_ERR_DET;
}
/** ============================================================================
* @n@b CSL_srioGetPortErrCapt
*
* @b Description
* Quries the port error capture status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port error capture
details
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioGetPortErrCapt(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetPortErrCapt (
CSL_SrioHandle hSrio,
CSL_SrioPortErrCapt *response
)
{
response->portErrCaptType = (CSL_SrioPortCaptType)CSL_FEXT(
hSrio->regs->PORT_ERROR[response->portNum].SP_ERR_ATTR_CAPT_DBG0, \
SRIO_SP_ERR_ATTR_CAPT_DBG0_INFO_TYPE);
response->errorType = CSL_FEXT(
hSrio->regs->PORT_ERROR[response->portNum].SP_ERR_ATTR_CAPT_DBG0, \
SRIO_SP_ERR_ATTR_CAPT_DBG0_ERROR_TYPE);
response->impSpecData = CSL_FEXT(
hSrio->regs->PORT_ERROR[response->portNum].SP_ERR_ATTR_CAPT_DBG0, \
SRIO_SP_ERR_ATTR_CAPT_DBG0_IMP_SPECIFIC);
response->capture0 =
hSrio->regs->PORT_ERROR[response->portNum].SP_ERR_CAPT_DBG[0];
response->capture1 =
hSrio->regs->PORT_ERROR[response->portNum].SP_ERR_CAPT_DBG[1];
response->capture2 =
hSrio->regs->PORT_ERROR[response->portNum].SP_ERR_CAPT_DBG[2];
response->capture3 =
hSrio->regs->PORT_ERROR[response->portNum].SP_ERR_CAPT_DBG[3];
}
/** ============================================================================
* @n@b CSL_srioGetSpCtlIndepStat
*
* @b Description
* Quries the port control independent status.
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port number and the
argument
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioGetSpCtlIndepStat(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetSpCtlIndepStat (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data = hSrio->regs->PORT_OPTION[response->index].SP_CTL_INDEP;
}
/** ============================================================================
* @n@b CSL_srioGetPwCapt
*
* @b Description
* Quries the port error capture status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, port write capture
details
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortWriteCapt arg;
...
CSL_srioGetPwCapt(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetPwCapt (
CSL_SrioHandle hSrio,
CSL_SrioPortWriteCapt *response
)
{
response->capture0 = hSrio->regs->SP_IP_PW_IN_CAPT[0];
response->capture1 = hSrio->regs->SP_IP_PW_IN_CAPT[1];
response->capture2 = hSrio->regs->SP_IP_PW_IN_CAPT[2];
response->capture3 = hSrio->regs->SP_IP_PW_IN_CAPT[3];
}
/** ============================================================================
* @n@b CSL_srioErrRateCounterRead
*
* @b Description
* Quries the port error rate counter value
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, output parameter
for error rate counter and index to the ports
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioErrRateCounterRead(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioErrRateCounterRead (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data =
CSL_FEXT(hSrio->regs->PORT_ERROR[response->index].SP_ERR_RATE,\
SRIO_SP_ERR_RATE_ERROR_RATE_COUNTER);
}
/** ============================================================================
* @n@b CSL_srioErrRatePeakRead
*
* @b Description
* Quries the port Error Rate Peak value
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
arg Pointer to the structure that specify, output parameter for
Error Rate Peak value and index
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData arg;
...
CSL_srioErrRatePeakRead(hSrio, &arg);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioErrRatePeakRead (
CSL_SrioHandle hSrio,
CSL_SrioPortData *response
)
{
response->data =
CSL_FEXT(hSrio->regs->PORT_ERROR[response->index].SP_ERR_RATE, \
SRIO_SP_ERR_RATE_PEAK_ERROR_RATE);
}
/** ============================================================================
* @n@b CSL_srioGetGblEnStat
*
* @b Description
* Queries the Global enable status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the status
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_srioGetGblEnStat(hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetGblEnStat (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = hSrio->regs->GBL_EN_STAT;
}
/** ============================================================================
* @n@b CSL_srioGetLsuIntrStat
*
* @b Description
* Queries the LSU interrupt status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the status
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_srioGetLsuIntrStat(hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetLsuIntrStat (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = hSrio->regs->LSU_ICSR;
}
/** ============================================================================
* @n@b CSL_srioGetErrRstIntrStat
*
* @b Description
* Queries the error and reset interrupt status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the status
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_srioGetErrRstIntrStat (hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetErrRstIntrStat (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = hSrio->regs->ERR_RST_EVNT_ICSR;
}
/** ============================================================================
* @n@b CSL_srioGetLsuIntrDecodeStat
*
* @b Description
* Queries the LSU interrupt decode status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the status
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_srioGetLsuIntrDecodeStat (hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetLsuIntrDecodeStat (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = CSL_FEXT(hSrio->regs->INTDST_DECODE[0],
SRIO_INTDST_DECODE_ISDR31);
}
/** ============================================================================
* @n@b CSL_srioGetErrIntrDecodeStat
*
* @b Description
* Queries the error interrupt decode status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the status
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_srioGetErrIntrDecodeStat(hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetErrIntrDecodeStat (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = CSL_FEXT(hSrio->regs->INTDST_DECODE[0],
SRIO_INTDST_DECODE_ISDR30);
}
/** ============================================================================
* @n@b CSL_srioGetPeFeature
*
* @b Description
* Queries the PE features register
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the value
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_srioGetPeFeature(hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetPeFeature (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = hSrio->regs->PE_FEAT;
}
/** ============================================================================
* @n@b CSL_srioGetSrcOpernSuppStat
*
* @b Description
* Queries the sorce operations supported register
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the value
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_srioGetSrcOpernSuppStat(hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetSrcOpernSuppStat (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = hSrio->regs->SRC_OP;
}
/** ============================================================================
* @n@b CSL_srioGetDstOpernSuppStat
*
* @b Description
* Queries the destination operation support register
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the value
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_srioGetDstOpernSuppStat(hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_srioGetDstOpernSuppStat (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = hSrio->regs->DEST_OP;
}
/** ============================================================================
* @n@b CSL_SrioGetLgclTrnsErrStat
*
* @b Description
* Queries the logical transport layer error status
*
* @b Arguments
* @verbatim
hSrio Pointer to the object that holds reference to the
instance of SRIO
response output parameter to return the status
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
Uint32 resp;
...
CSL_SrioGetLgclTrnsErrStat(hSrio, &resp);
...
@endverbatim
* ===========================================================================
*/
static inline
void CSL_SrioGetLgclTrnsErrStat (
CSL_SrioHandle hSrio,
Uint32* response
)
{
*(Uint32 *)response = hSrio->regs->ERR_DET;
}
#ifdef __cplusplus
extern "C" {
#endif
#endif /* CSL_SRIOAUX_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/csl_emifa.h | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_emifa.h
*
* @path $(CSLPATH)\inc
*
* @desc Header file for functional layer of CSL
* - The different enumerations, structure definitions
* and function declarations
*
*/
/**
* @mainpage EMIFA CSL 3.x
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to identify a set of common CSL APIs for
* the EMIFA module across various devices. The CSL developer is expected to
* refer to this document while designing APIs for these modules. Some of the
* cases listed APIs may not be applicable to a given EMIFA module. While
* other in this list of APIs may not be sufficient to cover all the features of
* a particular EMIFA Module. The CSL developer should use his discretion
* designing new APIs or extending the existing ones to cover these.
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
*
* @subsection References
* -# EMIF_SPEC, EMIF Module Specifications Document; Version 3.16.1
* Jan 18,2005
*
*/
/* =============================================================================
* Revision History
* ===============
* 12-May-2005 RM File Created.
*
* 07-Jul-2005 RM - Changed the module name from EMIF64 to EMIFA
* - Changes made in accordance to the change in cslr_emifa.h
*
* 09-Sep-2005 NG Updation according to coding guidelines
*
* =============================================================================
*/
#ifndef _CSL_EMIFA_H_
#define _CSL_EMIFA_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <cslr.h>
#include <soc.h>
#include <csl_error.h>
#include <csl_types.h>
#include <cslr_emifa.h>
/*****************************************************************************
EMIFA global typedef declarations
*****************************************************************************
*/
/** Total number of Chip Enables for Async/Sync memories */
#define NUMCHIPENABLE 0x4
/** The default values of EMIFA Async Wait structure */
#define CSL_EMIFA_ASYNCWAIT_MAXEXTWAIT_DEFAULT 0x80
#define CSL_EMIFA_ASYNCWAIT_TURNARND_DEFAULT 0x03
/** The default values of EMIFA CEConfig for Async structure */
#define CSL_EMIFA_ASYNCCFG_SELECTSTROBE_DEFAULT 0x00
#define CSL_EMIFA_ASYNCCFG_WEMODE_DEFAULT 0x00
#define CSL_EMIFA_ASYNCCFG_ASYNCRDYEN_DEFAULT 0x00
#define CSL_EMIFA_ASYNCCFG_WSETUP_DEFAULT 0x0F
#define CSL_EMIFA_ASYNCCFG_SSTROBE_DEFAULT 0x3F
#define CSL_EMIFA_ASYNCCFG_WHOLD_DEFAULT 0x07
#define CSL_EMIFA_ASYNCCFG_RSETUP_DEFAULT 0x0F
#define CSL_EMIFA_ASYNCCFG_RSTROBE_DEFAULT 0x3F
#define CSL_EMIFA_ASYNCCFG_RHOLD_DEFAULT 0x07
#define CSL_EMIFA_ASYNCCFG_ASIZE_DEFAULT 0x00
/** The default values of EMIFA CEConfig for Sync structure */
#define CSL_EMIFA_SYNCCFG_READBYTEEN_DEFAULT 0x00
#define CSL_EMIFA_SYNCCFG_CHIPENEXT_DEFAULT 0x00
#define CSL_EMIFA_SYNCCFG_READEN_DEFAULT 0x00
#define CSL_EMIFA_SYNCCFG_WLTNCY_DEFAULT 0x00
#define CSL_EMIFA_SYNCCFG_RLTNCY_DEFAULT 0x00
#define CSL_EMIFA_SYNCCFG_SBSIZE_DEFAULT 0x00
/** @brief Enumeration for bit field AP of Asynchronous Wait Cycle Configuration
* Register
*/
typedef enum {
/** strobe period extended when ARDY is low */
CSL_EMIFA_ARDYPOL_LOW = 0,
/** strobe period extended when ARDY is high */
CSL_EMIFA_ARDYPOL_HIGH = 1
} CSL_EmifaArdyPol;
/** @brief Enumeration for bit field for memory type
*/
typedef enum {
/** Asynchronous memory type */
CSL_EMIFA_MEMTYPE_ASYNC = 0,
/** Synchronous memory type */
CSL_EMIFA_MEMTYPE_SYNC = 1
} CSL_EmifaMemoryType;
/** @brief Module specific context information. */
typedef struct {
/** Context information of EMIFA external memory interface CSL passed as an
* argument to CSL_emifaInit().Present implementation of EMIFA CSL doesn't
* have any context information; hence assigned NULL.
* The below declaration is just a place-holder for future implementation.
*/
Uint16 contextInfo;
} CSL_EmifaContext;
/** @brief This structure contains the base-address information for the EMIFA
* instance
*/
typedef struct {
/** Base-address of the configuration registers of the peripheral */
CSL_EmifaRegsOvly regs;
} CSL_EmifaBaseAddress;
/** @brief This Object contains the reference to the instance of EMIFA opened
* using the @a CSL_emifaOpen().
* The pointer to this, is passed to all EMIFA CSL APIs.
*/
typedef struct CSL_EmifaObj {
/** This is a pointer to the registers of the instance of EMIFA
* referred to by this object
*/
CSL_EmifaRegsOvly regs;
/** This is the instance of EMIFA being referred to by this object */
CSL_InstNum perNum;
} CSL_EmifaObj;
/** @brief This is a pointer to @a CSL_EmifaObj and is passed as the first
* parameter to all EMIFA CSL APIs
*/
typedef struct CSL_EmifaObj *CSL_EmifaHandle;
/**
* @brief Module specific parameters. Present implementation of EMIFA CSL
* doesn't have any module specific parameters.
*/
typedef struct {
/** Bit mask to be used for module specific parameters. The below
* declaration is just a place-holder for future implementation. Passed as
* an argument to CSL_emifaOpen().
*/
CSL_BitMask16 flags;
} CSL_EmifaParam;
/** @brief EMIFA Async structure.
*
* All fields needed for EMIFA Async configuration are present in this
* structure. The pointer to this structure is a member to the structure
* CSL_EmifaMemType. CSL_EmifaAsync structure holds the value to be programmed
* into CE Configuration register when ssel=0 (i.e., asynchronous).
*/
typedef struct {
/** Select Strobe Mode Enable */
Uint8 selectStrobe;
/** Select WE Strobe Mode Enable */
Uint8 weMode;
/** Asynchronous Ready Input Enable */
Uint8 asyncRdyEn;
/** Write Setup Width */
Uint8 wSetup;
/** Write Strobe Width */
Uint8 wStrobe;
/** Write Hold Width */
Uint8 wHold;
/** Read Setup Width */
Uint8 rSetup;
/** Read Strobe Width */
Uint8 rStrobe;
/** Read Hold Width */
Uint8 rHold;
/** Asynchronous Memory Size */
Uint8 asize;
} CSL_EmifaAsync;
/**
* @brief EMIFA Sync structure.
*
* All fields needed for EMIFA Sync configuration are present in this structure.
* The pointer to this structure is a member to the structure CSL_EmifaMemType.
* CSL_EmifaSync structure holds the value to be programmed into CE
* Configuration register when ssel=1 (i.e. synchronous).
*/
typedef struct {
/** Read Byte Enable enable */
Uint8 readByteEn;
/** Synchronous Memory Chip Enable Extend */
Uint8 chipEnExt;
/** Synchronous Memory Read Enable Mode */
Uint8 readEn;
/** Synchronous Memory Write Latency */
Uint8 w_ltncy;
/** Synchronous Memory Read Latency */
Uint8 r_ltncy;
/** Synchronous Memory Device Size */
Uint8 sbsize;
} CSL_EmifaSync;
/**
* @brief EMIFA MemType structure.
*
* This structure defines the memory type of a particular chip enable.
* If a particular chip enable e.g., CE2 is to be configured as asynchronous
* memory, ssel must be 0, sync must be NULL and async must be a pointer to
* CSL_EmifaAsync structure with the proper values configured.
*/
typedef struct {
/** Synchronous/asynchronous memory select. Asynchronous memory mode
* when ssel is set to 0 and synchronous when ssel is 1.
*/
Uint8 ssel;
/** Pointer to structure of asynchronous type. The pointer
* value should be NULL if the chip select value is synchronous.
*/
CSL_EmifaAsync *async;
/** Pointer to structure of synchronous type. The pointer value
* should be NULL if the chip select value is asynchronous.
*/
CSL_EmifaSync *sync;
} CSL_EmifaMemType;
/**
* @brief EMIFA AsyncWait structure.
*
* This structure is a structure member of CSL_EmifaHwSetup. It holds
* the value to be programmed into Asynchronous Wait Cycle Configuration
* register. This is valid only for asynchronous (ssel=0) memories.
*/
typedef struct {
/** Asynchronous Ready Pin Polarity */
CSL_EmifaArdyPol asyncRdyPol;
/** Maximum Extended Wait cycles */
Uint8 maxExtWait;
/** Turn Around cycles */
Uint8 turnArnd;
} CSL_EmifaAsyncWait;
/** @brief This has all the fields required to configure EMIFA at Power Up
* (After a Hardware Reset) or a Soft Reset
*
* This structure is used to setup or obtain existing setup of
* EMIFA using @a CSL_emifaHwSetup() & @a CSL_emifaGetHwSetup() functions
* respectively.
*/
typedef struct {
/** Pointer to structure for configuring the Asynchronous Wait Cycle
* Configuration register
*/
CSL_EmifaAsyncWait *asyncWait;
/** Array of CSL_EmifaMemType* for configuring the Chip enables
* as Async or Sync memory type.
*/
CSL_EmifaMemType *ceCfg[NUMCHIPENABLE];
} CSL_EmifaHwSetup;
/** @brief EMIFA Module ID and Revision structure
*
* This structure is used for querying the EMIFA module ID and revision
*/
typedef struct {
/** EMIFA Module ID */
Uint16 modId;
/** EMIFA Major Revision */
Uint8 majRev;
/** EMIFA Minor Revision */
Uint8 minRev;
} CSL_EmifaModIdRev;
/**
* @brief EMIFA config structure which is used in CSL_emifaHwSetupRaw function.
* This is a structure of register values, rather than a structure of
* register field values like CSL_EmifaHwSetup.
*/
typedef struct {
/** Chip Enable2 Configuration register */
volatile Uint32 CE2CFG;
/** Chip Enable3 Configuration register */
volatile Uint32 CE3CFG;
/** Chip Enable4 Configuration register */
volatile Uint32 CE4CFG;
/** Chip Enable5 Configuration register */
volatile Uint32 CE5CFG;
/** Asynchronous Wait Cycle Configuration register */
volatile Uint32 AWCC;
/** Interrupt Raw Register */
volatile Uint32 INTRAW;
/** Interrupt Masked Register */
volatile Uint32 INTMSK;
/** Interrupt Mask Set Register */
volatile Uint32 INTMSKSET;
/** Interrupt Mask Clear Register */
volatile Uint32 INTMSKCLR;
/** Burst Priority Register */
volatile Uint32 BPRIO;
} CSL_EmifaConfig;
/** @brief Enumeration for queries passed to @a CSL_emifaGetHwStatus()
* This is used to get the status of different operations
*/
typedef enum {
/**
* @brief Get the EMIFA module ID and revision numbers
*
* @param (CSL_EmifaModIdRev *)
*/
CSL_EMIFA_QUERY_REV_ID = 0,
/**
* @brief Get Asynchronous Timeout status ie enabled or not
*
* @param (Uint8 *)
*/
CSL_EMIFA_QUERY_ASYNC_TIMEOUT_EN,
/**
* @brief Get Asynchronous Timeout status in Interrupt Raw register
*
* @param (Uint8 *)
*/
CSL_EMIFA_QUERY_ASYNC_TIMEOUT_STATUS,
/**
* @brief Gets the EMIFA EMIF Endianness
*
* @param (Uint8 *)
*/
CSL_EMIFA_QUERY_ENDIAN
} CSL_EmifaHwStatusQuery;
/**
* @brief Enumeration for commands passed to @a CSL_emifaHwControl()
*
* This is used to select the commands to control the operations
* existing setup of EMIFA. The arguments to be passed with each
* enumeration if any are specified next to the enumeration.
*/
typedef enum {
/**
* @brief Clears Asyn Timeout interrupt
*
* @param (None)
*/
CSL_EMIFA_CMD_ASYNC_TIMEOUT_CLEAR = 0,
/**
* @brief Disables Asyn Timeout interrupt
*
* @param (None)
*/
CSL_EMIFA_CMD_ASYNC_TIMEOUT_DISABLE,
/**
* @brief Enables Asyn Timeout interrupt
*
* @param (None)
*/
CSL_EMIFA_CMD_ASYNC_TIMEOUT_ENABLE,
/**
* @brief Number of memory transfers after which the EMIFA
* momentarily raises the priority of old commands in the VBUSM
* Command FIFO
* @param (Uint8 *)
*/
CSL_EMIFA_CMD_PRIO_RAISE
} CSL_EmifaHwControlCmd;
/** @brief The defaults of EMIFA Async Wait structure */
#define CSL_EMIFA_ASYNCWAIT_DEFAULTS {\
(CSL_EmifaArdyPol)CSL_EMIFA_ARDYPOL_HIGH, \
(Uint8)CSL_EMIFA_ASYNCWAIT_MAXEXTWAIT_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCWAIT_TURNARND_DEFAULT \
}
/** @brief The defaults of EMIFA CEConfig for Async structure */
#define CSL_EMIFA_ASYNCCFG_DEFAULTS {\
(Uint8)CSL_EMIFA_ASYNCCFG_SELECTSTROBE_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCCFG_WEMODE_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCCFG_ASYNCRDYEN_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCCFG_WSETUP_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCCFG_SSTROBE_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCCFG_WHOLD_DEFAULT,\
(Uint8)CSL_EMIFA_ASYNCCFG_RSETUP_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCCFG_RSTROBE_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCCFG_RHOLD_DEFAULT, \
(Uint8)CSL_EMIFA_ASYNCCFG_ASIZE_DEFAULT \
}
/** @brief The defaults of EMIFA CEConfig for Sync structure */
#define CSL_EMIFA_SYNCCFG_DEFAULTS {\
(Uint8)CSL_EMIFA_SYNCCFG_READBYTEEN_DEFAULT, \
(Uint8)CSL_EMIFA_SYNCCFG_CHIPENEXT_DEFAULT, \
(Uint8)CSL_EMIFA_SYNCCFG_READEN_DEFAULT, \
(Uint8)CSL_EMIFA_SYNCCFG_WLTNCY_DEFAULT, \
(Uint8)CSL_EMIFA_SYNCCFG_RLTNCY_DEFAULT, \
(Uint8)CSL_EMIFA_SYNCCFG_SBSIZE_DEFAULT \
}
/** @brief The default Config structure */
#define CSL_EMIFA_CONFIG_DEFAULTS { \
(Uint32)CSL_EMIFA_CE2CFG_SSEL0_RESETVAL, \
(Uint32)CSL_EMIFA_CE3CFG_SSEL0_RESETVAL, \
(Uint32)CSL_EMIFA_CE4CFG_SSEL0_RESETVAL, \
(Uint32)CSL_EMIFA_CE5CFG_SSEL0_RESETVAL, \
(Uint32)CSL_EMIFA_AWCC_RESETVAL, \
(Uint32)CSL_EMIFA_INTRAW_RESETVAL, \
(Uint32)CSL_EMIFA_INTMSK_RESETVAL, \
(Uint32)CSL_EMIFA_INTMSKSET_RESETVAL, \
(Uint32)CSL_EMIFA_INTMSKCLR_RESETVAL, \
(Uint32)CSL_EMIFA_BPRIO_RESETVAL \
}
/******************************************************************************
EMIFA global function declarations
******************************************************************************
*/
/** ============================================================================
* @n@b CSL_emifaInit
*
* @b Description
* @n This function is idempotent i.e. calling it many times is same as calling
* it once. This function presently does nothing.
*
* @b Arguments
@verbatim
pContext Context information for the instance. Should be NULL
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n This function should be called before using any of the CSL APIs
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CSL_emifaInit( NULL );
...
}
@endverbatim
*
* =============================================================================
*/
CSL_Status CSL_emifaInit (
CSL_EmifaContext *pContext
);
/** ============================================================================
* @n@b CSL_emifaOpen
*
* @b Description
* @n This function populates the peripheral data object for the EMIFA
* instance and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of EMIFA device. The device can be re-opened anytime after it has been
* normally closed if so required. The handle returned by this call is
* input as an essential argument for rest of the APIs described
* for this module.
*
* @b Arguments
* @verbatim
pEmifaObj Pointer to the EMIFA instance object
emifaNum Instance of the EMIFA to be opened.
pEmifaParam Pointer to module specific parameters
pStatus Pointer for returning status of the function call
@endverbatim
*
* <b> Return Value </b>
* @li CSL_EmifaHandle - Valid EMIFA instance handle will be
* returned if status value is equal to
* CSL_SOK.
*
* <b> Pre Condition </b>
* @n @a CSL_emifaInit() must be called successfully.
*
* <b> Post Condition </b>
* @n EMIFA object structure is populated
*
* @b Modifies
* @n 1. The status variable
* @n 2. EMIFA object structure
*
* @b Example:
* @verbatim
CSL_Status status;
CSL_EmifaObj emifaObj;
CSL_EmifaHandle hEmifa;
hI2c = CSL_emifaOpen (&emifaObj,
CSL_EMIFA,
NULL,
&status
);
@endverbatim
*
* =============================================================================
*/
CSL_EmifaHandle CSL_emifaOpen (
CSL_EmifaObj *hEmifaObj,
CSL_InstNum emifaNum,
CSL_EmifaParam *pEmifaParam,
CSL_Status *status
);
/** ============================================================================
* @n@b csl_emifaClose.c
*
* @b Description
* @n This function marks that CSL for the external memory interface instance
* needsto be reopened before using any external memory interface CSL APIs.
*
* @b Arguments
* @verbatim
hEmifa Handle to the external memory interface instance
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - external memory interface is
* closed successfully
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling @a CSL_emifaClose().
*
* <b> Post Condition </b>
* @n 1. The external memory interface CSL APIs cannot be called until the
* external memory interface CSL is reopened again using
* CSL_emifaOpen().
*
* @b Modifies
* @n hEmifa structure
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
...
CSL_emifaClose(hEmifa);
...
@endverbatim
* =============================================================================
*/
CSL_Status CSL_emifaClose (
CSL_EmifaHandle hEmifa
);
/** ============================================================================
* @n@b CSL_emifaGetBaseAddress
*
* @b Description
* @n The getbaseaddress call will give the External memory interface current
* instance base address
*
* @b Arguments
* @verbatim
emifaNum Specifies the instance of the EMIFA external memory
interface for which the base address is requested
pEmifaParam Module specific parameters.
pBaseAddress Pointer to the base address structure to return the
base address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Open call is successful
* @li CSL_ESYS_FAIL The external memory interface
* instance is not available.
*
* <b> Pre Condition </b>
* @n @a CSL_emifaInit() and CSL_emifaOpen () must be called successfully.
*
* <b> Post Condition </b>
* @n Base address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_EmifaBaseAddress baseAddress;
...
status = CSL_emifaGetBaseAddress(CSL_EMIFA, NULL, &baseAddress);
@endverbatim
*
* =============================================================================
*/
CSL_Status CSL_emifaGetBaseAddress (
CSL_InstNum emifaNum,
CSL_EmifaParam *pEmifaParam,
CSL_EmifaBaseAddress *pBaseAddress
);
/** ============================================================================
* @n@b CSL_emifaHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the Config data structure.
*
* @b Arguments
* @verbatim
hEmifa Handle to the EMIFA external memory interface instance
config Pointer to the config structure containing the
device register values
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration structure
* pointer is not properly
* initialized
*
* <b> Pre Condition </b>
* @n Both CSL_ emifaInit () and CSL_emifaOpen() must be called successfully
* in order before calling this function
*
* <b> Post Condition </b>
* @n The registers of the specified EMIFA instance will be
* setup according to the values passed through the Config structure
*
* @b Modifies
* @n Hardware registers of the EMIFA
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_EmifaConfig config = CSL_EMIFA_CONFIG_DEFAULTS;
CSL_Status status;
..
status = CSL_emifaHwSetupRaw(hEmifa, &config);
...
@endverbatim
* =============================================================================
*/
CSL_Status CSL_emifaHwSetupRaw (
CSL_EmifaHandle hEmifa,
CSL_EmifaConfig *config
);
/** ============================================================================
* @n@b CSL_emifaHwSetup
*
* @b Description
* @n This function initializes the device registers with the appropriate values
* provided through the HwSetup data structure. For information passed through
* the HwSetup data structure refer @a CSL_EmifaHwSetup.
*
* @b Arguments
* @verbatim
hEmifa Pointer to the object that holds reference to the
instance of EMIFA requested after the call
setup Pointer to setup structure which contains the
information to program EMIFA to a useful state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK - configuration successful
* @li CSL_ESYS_FAIL - The external memory interface
* instance is not available.
* @li CSL_ESYS_INVPARAMS - Parameters are not valid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling this function. The user has to
* allocate space for & fill in the main setup structure appropriately
* before calling this function.
*
* <b> Post Condition </b>
* @n EMIFA registers are configured according to the hardware setup parameters
*
* @b Modifies
* @n EMIFA registers
*
* @b Example:
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_EmifaAsync asyncMem = CSL_EMIFA_ASYNCCFG_DEFAULTS;
CSL_EmifaAsyncWait asyncWait = CSL_EMIFA_ASYNCWAIT_DEFAULTS;
CSL_EmifaMemType value;
CSL_EmifaHwSetup hwSetup ;
value.ssel = 0;
value.async = &asyncMem;
value.sync = NULL;
hwSetup.asyncWait = &asyncMem;
hwSetup.cefg [0] = &value;
hwSetup.ceCfg [1] = NULL;
hwSetup.ceCfg [2] = NULL;
hwSetup.ceCfg [3] = NULL;
CSL_emifaHwSetup(hEmifa, &hwSetup);
@endverbatim
*
* =============================================================================
*/
CSL_Status CSL_emifaHwSetup (
CSL_EmifaHandle hEmifa,
CSL_EmifaHwSetup *setup
);
/** ============================================================================
* @n@b CSL_emifaGetHwSetup
*
* @b Description
* @n This function gets the current setup of the EMIFA. The status is
* returned through @a CSL_EmifaHwSetup. The obtaining of status
* is the reverse operation of @a CSL_emifaHwSetup() function.
*
* @b Arguments
* @verbatim
hEmifa Pointer to the object that holds reference to the
instance of EMIFA requested after the call
setup Pointer to setup structure which contains the
information to program EMIFA to a useful state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK - Hardware status call is
* successful
* @li CSL_ESYS_FAIL - The external memory interface
* instance is not available.
* @li CSL_ESYS_INVPARAMS - Parameters are not valid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling @a CSL_emifaGetHwSetup().
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Second parameter setup
*
* @b Example:
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_Status status;
CSL_EmifaHwSetup hwSetup;
CSL_EmifaAsync asyncMem;
CSL_EmifaMemType value;
CSL_EmifaAsyncWait asyncWait;
value.ssel = 0;
value.async = &asyncMem;
value.sync = NULL;
hwSetup.asyncWait = &asyncWait;
hwSetup.ceCfg [0] = &value;
hwSetup.ceCfg [1] = NULL;
hwSetup.ceCfg [2] = NULL;
hwSetup.ceCfg [3] = NULL;
status = CSL_emifaGetHwSetup(hEmifa, &hwSetup);
@endverbatim
*
* =============================================================================
*/
CSL_Status CSL_emifaGetHwSetup (
CSL_EmifaHandle hEmifa,
CSL_EmifaHwSetup *setup
);
/** ============================================================================
* @n@b CSL_emifaHwControl
*
* @b Description
* @n Control operations for the EMIFA. For a particular control operation, the
* pointer to the corresponding data type needs to be passed as argument
* HwControl function Call. All the arguments (structure elements included)
* passed to the HwControl function are inputs. For the list of commands
* supported and argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_EmifaHwControlCmd.
*
* @b Arguments
* @verbatim
hEmifa Pointer to the object that holds reference to the
instance of EMIFA requested after the call
cmd The command to this API indicates the action to be
taken
arg An optional argument @a void* casted
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK - Hardware control call is
* successful
* @li CSL_ESYS_INVCMD - command is not valid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling @a CSL_emifaHwControl().
* For the argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_EmifaHwControlCmd
*
* <b> Post Condition </b>
* @n EMIFA registers are configured according to the command passed
*
* @b Modifies
* @n EMIFA registers
*
* @b Example:
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_Status status;
Uint8 * command;
...
status = CSL_emifaHwControl(hEmifa,
CSL_EMIFA_CMD_PRIO_RAISE,
&command);
@endverbatim
*
* =============================================================================
*/
CSL_Status CSL_emifaHwControl (
CSL_EmifaHandle hEmifa,
CSL_EmifaHwControlCmd cmd,
void *arg
);
/** ============================================================================
* @n@b CSL_emifaGetHwStatus
*
* @b Description
* @n This function is used to read the current device configuration, status
* flags and the value present associated registers. User should allocate
* memory for the said data type and pass its pointer as an unadorned void*
* argument to the status query call. For details about the various status
* queries supported & the associated data structure to record the response,
* refer to @a CSL_EmifaHwStatusQuery.
*
* @b Arguments
* @verbatim
hEmifa Pointer to the object that holds reference to the
instance of EMIFA requested after the call
query The query to this API which indicates the status
to be returned
response Placeholder to return the status. @a void* casted
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK - successful on getting hardware
* status
* @li CSL_ESYS_INVQUERY - Query is not valid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling @a CSL_emifaGetHwStatus().
* For the argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_EmifaHwStatusQuery
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Third parameter response vlaue
*
* @b Example:
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_Status status;
Uint8 *response;
...
status = CSL_emifaGetHwStatus(hEmifa,
CSL_EMIFA_QUERY_ENDIAN,
&response);
@endverbatim
*
*
* =============================================================================
*/
CSL_Status CSL_emifaGetHwStatus (
CSL_EmifaHandle hEmifa,
CSL_EmifaHwStatusQuery query,
void *response
);
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiHwSetupRaw.c | <filename>DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiHwSetupRaw.c<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ===========================================================================
*/
/**
* @file csl_hpiHwSetupRaw.c
*
* @path $(CSLPATH)\src\hpi
*
* @brief File for functional layer of CSL API @a CSL_hpiHwSetupRaw()
*
*/
#include <csl_hpi.h>
/** ============================================================================
* @n@b CSL_hpiHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the Config Data structure.
*
* @b Arguments
* @verbatim
hHpi Handle to the HPI instance
config Pointer to Config structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration is not
properly initialized
* <b> Pre Condition </b>
* @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in
* order before calling CSL_hpiGetHwSetupRaw().
*
* <b> Post Condition </b>
* @n The registers of the specified HPI instance will be setup
* according to input configuration structure values.
*
* @b Modifies
* @n Hardware registers of the specified HPI instance.
*
* @b Example
* @verbatim
CSL_HpiHandle hHpi;
CSL_HpiConfig config = CSL_HPI_CONFIG_DEFAULTS;
CSL_Status status;
status = CSL_hpiHwSetupRaw(hHpi, &config);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_hpiHwSetupRaw, ".text:csl_section:hpi");
CSL_Status CSL_hpiHwSetupRaw (
CSL_HpiHandle hHpi,
CSL_HpiConfig *config
)
{
CSL_Status status = CSL_SOK;
if (hHpi == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (config == NULL ) {
status = CSL_ESYS_INVPARAMS;
}
else {
hHpi->regs->PWREMU_MGMT = config->PWREMU_MGMT;
hHpi->regs->HPIC = config->HPIC;
hHpi->regs->HPIAW = config->HPIAW;
hHpi->regs->HPIAR = config->HPIAR;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/cfg/csl_cfgGetHwStatus.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_cfgGetHwStatus.c
*
* @path $(CSLPATH)\src\cfg
*
* @desc File for functional layer of CSL API CSL_cfgGetHwStatus()
*
*/
/* ============================================================================
* Revision History
* ===============
* 14-Apr-2005 Brn File Created
* ============================================================================
*/
#include <csl_cfg.h>
#include <csl_cfgAux.h>
/** ============================================================================
* @n@b CSL_cfgGetHwStatus
*
* @b Description
* @n Gets the status of the different operations of CFG.
*
* @b Arguments
* @verbatim
hCfg Handle to the CFG instance
query The query to this API of CFG which indicates the
status to be returned.
response Placeholder to return the status.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful
* @li CSL_ESYS_INVQUERY - Invalid query command
* @li CSL_ESYS_INVPARAMS - Invalid parameter
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n Both CSL_cfgInit() and CSL_cfgOpen() must be called successfully in
* that order before CSL_cgfGetHwStatus () can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_CfgHandle hCfg;
Uint32 reponse;
CSL_Status status;
...
status = CSL_GetcfgHwStatus(hCfg, CSL_CFG_QUERY_FAULT_ADDR, &response);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_cfgGetHwStatus, ".text:csl_section:cfg")
CSL_Status CSL_cfgGetHwStatus (
CSL_CfgHandle hCfg,
CSL_CfgHwStatusQuery query,
void *response
)
{
CSL_Status status = CSL_SOK;
if (hCfg == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (query) {
case CSL_CFG_QUERY_FAULT_ADDR:
CSL_cfgGetFaultAddr(hCfg, (Uint32 *)response);
break;
case CSL_CFG_QUERY_FAULT_STATUS:
CSL_cfgGetFaultStat(hCfg, (CSL_CfgFaultStatus *)response);
break;
default:
status = CSL_ESYS_INVQUERY ;
break;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioGetHwStatus.c | /* ==========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* provided
* ==========================================================================
*/
/** ==========================================================================
* @file csl_gpioGetHwStatus.c
*
* @Path $(CSLPATH)\src\gpio
*
* @desc File for functional layer of CSL API CSL_gpioGetHwStatus()
* ============================================================================
*/
/* ===========================================================================
* Revision History
* ===============
* 11-Jun-2004 PGR file created
* 04-Sep-2004 Nsr Updated the source csl_gpioGetHwStatus.c for the new CSL
* format.
* ============================================================================
*/
#include <csl_gpio.h>
#include <csl_gpioAux.h>
/** ============================================================================
* @n@b CSL_gpioGetHwStatus
*
* @b Description
* @n Gets the status of the different operations of GPIO.
*
* @b Arguments
* @verbatim
hGpio Handle to the GPIO instance
query The query to this API of GPIO which indicates the
status to be returned.
response Placeholder to return the status.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVQUERY - Invalid Query
* @li CSL_ESYS_INVPARAMS - Invalid Parameters
*
* <b> Pre Condition </b>
* @n Both CSL_gpioInit() and CSL_gpioOpen() must be called successfully in
* order before this function
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Third parameter, response value
*
* @b Example
* @verbatim
CSL_GpioHandle hGpio;
CSL_GpioHwStatusQuery query = CSL_GPIO_QUERY_BINTEN_STAT;
Uint32 reponse;
status = CSL_gpioGetHwStatus(hGpio, query, &response);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_gpioGetHwStatus, ".text:csl_section:gpio");
CSL_Status CSL_gpioGetHwStatus (
CSL_GpioHandle hGpio,
CSL_GpioHwStatusQuery query,
void *response
)
{
CSL_Status status = CSL_SOK;
if (hGpio == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (query) {
case CSL_GPIO_QUERY_BINTEN_STAT:
CSL_gpioGetBintenStat(hGpio, response);
break;
default:
status = CSL_ESYS_INVQUERY;
break;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3HwChannelControl.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3HwChannelControl.c
*
* @path $(CSLPATH)\src\edma
*
* @desc File for functional layer of CSL API CSL_edma3HwChannelControl()
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* =============================================================================
*/
#include <csl_edma3.h>
#include <csl_edma3Aux.h>
/** ============================================================================
* @n@b CSL_edma3HwChannelControl
*
* @b Description
* @n Takes a command with an optional argument & implements it. This function
* is used to carry out the different operations performed by EDMA.
*
* @b Arguments
* @verbatim
hCh Channel Handle
cmd The command to this API which indicates the
action to be taken
cmdArg Pointer arguement specific to the command
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command execution successful
* @li CSL_ESYS_BADHANDLE - The handle passed is
* invalid
* @li CSL_ESYS_INVCMD - The command passed is invalid
*
*
* <b> Pre Condition </b>
* @n Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen()
* must be called successfully in that order before this API can be
* invoked.If a Shadow region is used then care of the DRAE settings
* must be taken
*
* <b> Post Condition </b>
* @n Edma registers are configured according to the command and
* the command arguements. The command determines which registers are
* modified.
*
* @b Modifies
* @n Edma registers determined by the command
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelObj chObj;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Status status;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// DRAE Enable(Bits 0-15) for the Shadow Region 0.
regionAccess.region = CSL_EDMA3_REGION_0 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
// Interrupt Enable (Bits 0-11) for the Shadow Region 0.
regionIntr.region = CSL_EDMA3_REGION_0 ;
regionIntr.intr = 0x0FFF ;
regionIntr.intrh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE, ®ionIntr);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj,
CSL_EDMA3,
&chAttr,
&status);
// Enable Channel(if the channel is meant for external event)
// This step is not required if the channel is chained to or manually
triggered.
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3HwChannelControl, ".text:csl_section:edma3");
CSL_Status CSL_edma3HwChannelControl (
CSL_Edma3ChannelHandle hCh,
CSL_Edma3HwChannelControlCmd cmd,
void *cmdArg
)
{
CSL_Status status = CSL_SOK;
if (hCh == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if ((cmd == CSL_EDMA3_CMD_CHANNEL_CLEARERR) && (cmdArg == NULL)) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch(cmd) {
case CSL_EDMA3_CMD_CHANNEL_ENABLE:
status = CSL_edma3ChannelEnable(hCh);
break;
case CSL_EDMA3_CMD_CHANNEL_DISABLE:
status = CSL_edma3ChannelDisable(hCh);
break;
case CSL_EDMA3_CMD_CHANNEL_SET:
status = CSL_edma3ChannelEventSet(hCh);
break;
case CSL_EDMA3_CMD_CHANNEL_CLEAR:
status = CSL_edma3ChannelEventClear(hCh);
break;
case CSL_EDMA3_CMD_CHANNEL_CLEARERR:
status = CSL_Edma3ChannelErrorClear(hCh,
(CSL_Edma3ChannelErr*)cmdArg);
break;
default:
status = CSL_ESYS_INVCMD;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrInit.c | <filename>DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrInit.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file csl_tmrInit.c
*
* @brief File for functional layer of CSL API CSL_tmrInit()
*
* @path $(CSLPATH)\src\timer
*
* @desc The CSL_tmrInit() function definition & it's associated
* functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 1-Sept-2004 HMM File Created.
* 29-Jul-2005 PSK Updated changes acooriding to revised timer spec. The number
* convention TIM12, TIM34 are changed to TIMLO and TIMHI.
* ============================================================================
*/
#include <csl_tmr.h>
/** ============================================================================
* @n@b CSL_tmrInit
*
* @b Description
* @n This is the initialization function for the Timer CSL.The function
* must be called before calling any other API from this CSL.
* This function is idem-potent. Currently, the function just return
* status CSL_SOK, without doing anything.
*
* @b Arguments
* @verbatim
pContext Pointer to module-context. As timer doesn't have any context
based information user is expected to pass NULL.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The CSL for Timer is initialized
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_tmrInit();
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION(CSL_tmrInit, ".text:csl_section:tmr");
CSL_Status CSL_tmrInit (
CSL_TmrContext *pContext
)
{
CSL_Status st = CSL_SOK;
return st;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3GetHwChannelStatus.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3GetHwChannelStatus.c
*
* @path $(CSLPATH)\src\edma
*
* @desc File for functional layer of CSL API CSL_edma3GetHwChannelStatus()
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* =============================================================================
*/
#include <csl_edma3.h>
#include <csl_edma3Aux.h>
/** ============================================================================
* @n@b CSL_edma3GetHwChannelStatus
*
* @b Description
* @n Gets the status of the different operations or the current setup of EDMA
* module.
*
* @b Arguments
* @verbatim
hEdma Channel Handle
myQuery Query to be performed
response Pointer to buffer to return the data requested by
the query passed
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Get the edma channel status
* @li CSL_ESYS_BADHANDLE - The handle passed is
* invalid
* @li CSL_ESYS_INVQUERY - The query passed is invalid
*
*
* <b> Pre Condition </b>
* @n Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen()
* must be called successfully in that order before this API can be
* invoked.If a Shadow region is used then care of the DRAE settings
* must be taken
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The input arguement "response" is modified
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelObj chObj;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Status status;
Bool errStat;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj,
CSL_EDMA3,
&chAttr,
&status);
// Enable Channel( .. )
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
// Obtain Channel Error Status
CSL_edma3GetHwChannelStatus(hChannel,CSL_EDMA3_QUERY_CHANNEL_ERR, \
errStat);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3GetHwChannelStatus, ".text:csl_section:edma3");
CSL_Status CSL_edma3GetHwChannelStatus (
CSL_Edma3ChannelHandle hEdma,
CSL_Edma3HwChannelStatusQuery myQuery,
void *response
)
{
CSL_Status status = CSL_SOK;
if (hEdma == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch(myQuery) {
case CSL_EDMA3_QUERY_CHANNEL_STATUS:
status = CSL_Edma3GetChannelStatus(hEdma,(Bool*)response);
break;
case CSL_EDMA3_QUERY_CHANNEL_ERR:
status = CSL_Edma3GetChannelErrStatus(hEdma, \
(CSL_Edma3ChannelErr*)response);
break;
default:
status = CSL_ESYS_INVQUERY;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiGetHwSetup.c | <filename>DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiGetHwSetup.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ===========================================================================
*/
/**
* @file csl_hpiGetHwSetup.c
*
* @path $(CSLPATH)\src\hpi
*
* @brief File for functional layer of CSL API @a CSL_hpiGetHwSetup()
*
*/
#include <csl_hpi.h>
/** ============================================================================
* @n@b CSL_hpiGetHwSetup
*
* @b Description
* @n It retrives the hardware setup parameters of the hpi
* specified by the given handle.
*
* @b Arguments
* @verbatim
hHpi Handle to the hpi
hwSetup Pointer to the harware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Retrieving the hardware setup
* parameters is successful
* @li CSL_ESYS_BADHANDLE - The handle is passed is
* invalid
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order
* before calling CSL_hpiGetHwSetup().
*
* <b> Post Condition </b>
* @n The hardware setup structure is populated with the hardware setup
* parameters
*
* @b Modifies
* @n hwSetup variable
*
* @b Example
* @verbatim
CSL_HpiHandle hHpi;
CSL_HpiHwSetup hwSetup;
...
status = CSL_hpiGetHwSetup(hHpi, &hwSetup);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_hpiGetHwSetup, ".text:csl_section:hpi");
CSL_Status CSL_hpiGetHwSetup (
CSL_HpiHandle hHpi,
CSL_HpiHwSetup *hwSetup
)
{
CSL_Status status = CSL_SOK;
CSL_HpiRegsOvly hpiRegs = hHpi->regs;
if (hHpi == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (hwSetup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
hwSetup->hpiCtrl = (CSL_HpiCtrl)hpiRegs->HPIC;
hwSetup->hpiAddr.hpiaWrtAddr = hpiRegs->HPIAW;
hwSetup->hpiAddr.hpiaReadAddr = hpiRegs->HPIAR;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/csl_memprotAux.h | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ===========================================================================
* @file csl_memprotAux.h
*
* @brief API Auxilary header file for MEMPROT CSL.
*
* @path $(CSLPATH)\inc
*
* Description
* - The different control command and status query functions definations
*
* Modification : 30th Aug 2004
* Modified function
* Added documentation
*
* @author <NAME>
* ===========================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 15-Dec-2005 ds Removed Read access to Write only MPLKCMD register
* =============================================================================
*/
#ifndef _CSL_MEMPROTAUX_H
#define _CSL_MEMPROTAUX_H
#ifdef __cplusplus
extern "C" {
#endif
#define CSL_IDEF_INLINE static inline
/** @addtogroup CSL_MEMPROT_FUNCTION_INTERNAL
@{ */
/** ===========================================================================
* @n@b CSL_memprotLock
*
* @b Description
* @n Locks access to the memory protection registers
*
* @b Arguments
* @verbatim
hMemprot Handle to the MEMPROT instance
key Key used to lock the memory module registers
@endverbatim
*
* <b> Return Value </b> Status(CSL_SOK/CSL_ESYS_FAIL)
*
* <b> Pre Condition </b>
* @n All @a CSL_memprotInit(), @a CSL_memprotOpen() must be
* invoked successfully in that order before this API can
* be invoked.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
Uint32 key[2] = {<KEY>};
// Initializing the module
CSL_memprotInit(NULL);
// Opening the Handle for the L2
hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status);
CSL_memprotLock(hmpL2,key);
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
CSL_Status CSL_memprotLock (
CSL_MemprotHandle hMemprot,
Uint32* key
)
{
if (CSL_FEXT(hMemprot->regs->MPLKSTAT,MEMPROTL1D_MPLKSTAT_LK)) {
return CSL_ESYS_FAIL;
}
hMemprot->regs->MPLKCMD = CSL_FMKT(MEMPROTL1D_MPLKCMD_KEYR, YES);
/* Since the L2, L1D, LIP all implement only 64 bit
keys this is sufficient */
hMemprot->regs->MPLK0 = key[0];
hMemprot->regs->MPLK1 = key[1];
hMemprot->regs->MPLK2 = 0;
hMemprot->regs->MPLK3 = 0;
hMemprot->regs->MPLKCMD = CSL_FMKT(MEMPROTL1D_MPLKCMD_LOCK, YES);
return CSL_SOK;
}
/** ===========================================================================
* @n@b CSL_memprotUnLock
*
* @b Description
* @n Unlocks access to the memory protection registers
*
* @b Arguments
* @verbatim
hMemprot Handle to the MEMPROT instance
key Key used to lock the memory module registers
@endverbatim
*
* <b> Return Value </b> Status(CSL_SOK/CSL_ESYS_FAIL)
*
* <b> Pre Condition </b>
* @n All @a CSL_memprotInit(), @a CSL_memprotOpen() must be
* invoked successfully in that order before this API can
* be invoked.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
Uint32 key[2] = {<KEY>};
// Initializing the module
CSL_memprotInit(NULL);
// Opening the Handle for the L2
hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status);
CSL_memprotUnLock(hmpL2,key);
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
CSL_Status CSL_memprotUnLock (
CSL_MemprotHandle hMemprot,
Uint32* key
)
{
if (!CSL_FEXT(hMemprot->regs->MPLKSTAT,MEMPROTL1D_MPLKSTAT_LK)) {
return CSL_ESYS_FAIL;
}
hMemprot->regs->MPLKCMD = CSL_FMKT(MEMPROTL1D_MPLKCMD_KEYR, YES);
/* Since the L2, L1D, LIP all implement only 64 bit
keys this is sufficient */
hMemprot->regs->MPLK0 = key[0];
hMemprot->regs->MPLK1 = key[1];
hMemprot->regs->MPLK2 = 0;
hMemprot->regs->MPLK3 = 0;
hMemprot->regs->MPLKCMD = CSL_FMKT(MEMPROTL1D_MPLKCMD_UNLOCK, YES);
return CSL_SOK;
}
/** ===========================================================================
* @n@b CSL_memprotSetPageAttr
*
* @b Description
* @n Sets the page access attributes.
*
* @b Arguments
* @verbatim
hMemprot Handle to the memory protection unit
page Page number
attr Attributes
@endverbatim
*
* <b> Return Value </b> None
*
* <b> Pre Condition </b>
* @n All @a CSL_memprotInit(), @a CSL_memprotOpen() must be
* invoked successfully in that order before this API can
* be invoked.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
// Initializing the module
CSL_memprotInit(NULL);
// Opening the Handle for the L2
hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status);
CSL_memprotSetPageAttr(hmpL2,12,PAGE_ATTR|CSL_MEMPROT_MEMACCESS_UR);
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
void CSL_memprotSetPageAttr (
CSL_MemprotHandle hMemprot,
Uint32 page,
Uint32 attr
)
{
hMemprot->regs->MPPA[page] = attr;
}
/** ===========================================================================
* @n@b CSL_memprotGetPageAttr
*
* @b Description
* @n Queries the page access attributes.
*
* @b Arguments
* @verbatim
hMemprot Handle to the memory protection unit
page Page number
attr Attributes
@endverbatim
*
* <b> Return Value </b> Page Attributes
*
* <b> Pre Condition </b>
* @n All @a CSL_memprotInit(), @a CSL_memprotOpen() must be
* invoked successfully in that order before this API can
* be invoked.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
CSL_BitMask32 pageAttr;
// Initializing the module
CSL_memprotInit(NULL);
// Opening the Handle for the L2
hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status);
pageAttr = CSL_memprotGetPageAttr(hmpL2,12);
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
CSL_BitMask32 CSL_memprotGetPageAttr (
CSL_MemprotHandle hMemprot,
Uint16 page
)
{
return hMemprot->regs->MPPA[page];
}
/** ===========================================================================
* @n@b CSL_memprotGetFaultStatus
*
* @b Description
* @n Queries the fault id of the defaulter access
*
* @b Arguments
* @verbatim
hMemprot Handle to the memory protection unit
faultStatus fault Status
@endverbatim
*
* <b> Return Value </b> None
*
* <b> Pre Condition </b>
* @n All @a CSL_memprotInit(), @a CSL_memprotOpen() must be
* invoked successfully in that order before this API can
* be invoked.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
CSL_BitMask32 pageAttr;
CSL_MemprotFaultStatus faultStat;
// Initializing the module
CSL_memprotInit(NULL);
// Opening the Handle for the L2
hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status);
CSL_memprotGetFaultStatus(hmpL2,&faultStat);
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
void CSL_memprotGetFaultStatus (
CSL_MemprotHandle hMemprot,
CSL_MemprotFaultStatus *faultStatus
)
{
Uint32 stat;
faultStatus->addr = hMemprot->regs->MPFAR ;
stat = hMemprot->regs->MPFSR ;
faultStatus->errorMask = CSL_FEXTR(stat,8,0);
faultStatus->fid = CSL_FEXTR(stat,15,9);
/* Clearing the Memory Fault Error */
hMemprot->regs->MPFCR = 1;
}
/** ===========================================================================
* @n@b CSL_memprotGetLockStat
*
* @b Description
* @n Queries the lock status of the registers.
*
* @b Arguments
* @verbatim
hMemprot Handle to the memory protection unit
@endverbatim
*
* <b> Return Value </b> Lock Status
*
* <b> Pre Condition </b>
* @n All @a CSL_memprotInit(), @a CSL_memprotOpen() must be
* invoked successfully in that order before this API can
* be invoked.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
CSL_MemprotLockStatus lockAttr;
// Initializing the module
CSL_memprotInit(NULL);
// Opening the Handle for the L2
hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status);
lockAttr = CSL_memprotGetLockStat(hmpL2);
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
CSL_MemprotLockStatus CSL_memprotGetLockStat (
CSL_MemprotHandle hMemprot
)
{
return ((CSL_MemprotLockStatus)(CSL_FEXTR(hMemprot->regs->MPLKSTAT,0,0)));
}
#ifdef __cplusplus
}
#endif
#endif
/**
@}
*/
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc_src/src/common/csl_version.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
#include <tistdtypes.h>
#include <csl_version.h>
#pragma DATA_SECTION(CSL_versionStr, ".const:csl_section:version");
const
char CSL_versionStr[ ] =
CSL_VERSION_STR ":" CSL_CHIP_STR ":" __DATE__ ":" __TIME__;
#pragma CODE_SECTION(CSL_versionGetID, ".text:csl_section:version");
Uint32
CSL_versionGetID (
void
)
{
return CSL_VERSION_ID;
}
#pragma CODE_SECTION(CSL_versionGetStr, ".text:csl_section:version");
const char *
CSL_versionGetStr (
void
)
{
return (const char *)CSL_versionStr;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_intcAux.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* @file csl_intcAux.h
*
* @brief Header file for functional layer of CSL
*
* PATH $(CSLPATH)\\inc
*/
/* =============================================================================
* Revision History
* ===============
* 12-Jun-2004 <NAME> File Created
* 16-Mar-2005 brn modified for doxygen documentation and removed redundant
CSL_intcInterruptEnable, CSL_intcInterruptDisable and
CSL_intcInterruptRestore functions.
27-Mar-2006 ds Removed Read access to Write only EVTSET[3] and EVTCLR[3]
registers
* =============================================================================
*/
#ifndef _CSL_INTCAUX_H
#define _CSL_INTCAUX_H
#include <csl_intc.h>
/* External definition for _CSL_intcEventOffsetMap */
extern Int8 *_CSL_intcEventOffsetMap;
/* External definition for _CSL_intcAllocMask */
extern CSL_BitMask32* _CSL_intcAllocMask;
/* External definition for _CSL_intcEventHandlerRecord */
extern CSL_IntcEventHandlerRecord* _CSL_intcEventHandlerRecord;
/* External definition for _CSL_intcNumEvents */
extern Uint16 _CSL_intcNumEvents;
/* ============================================================================
* @n@b CSL_intcMapEventVector
*
* @b Description
* This API Maps the event to the given CPU vector
*
* @b Arguments
* @verbatim
eventId Intc event Identifier
vectId Intc vector identifier
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n CSL_intcInit() must be invoked before this call.
*
* <b> Post Condition </b>
* @n Maps the event to the given CPU vector
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcVectId vectId;
CSL_IntcEventId eventId;
...
CSL_intcMapEventVector(eventId, vectId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcMapEventVector (
CSL_IntcEventId eventId,
CSL_IntcVectId vectId
)
{
Int bitLow;
if (vectId < CSL_INTC_VECTID_8) {
bitLow = (vectId - 4) * 8;
CSL_FINSR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTMUX1, \
bitLow+6,bitLow,eventId);
}
else {
if (vectId < CSL_INTC_VECTID_12) {
bitLow = (vectId - 8) * 8;
CSL_FINSR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTMUX2, \
bitLow+6,bitLow,eventId);
}
else {
bitLow = (vectId - 12) * 8;
CSL_FINSR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTMUX3, \
bitLow+6,bitLow,eventId);
}
}
}
/* ============================================================================
* @n@b CSL_intcEventEnable
*
* @b Description
* This API enables particular event (EVTMASK0/1/2/3 bit programmation)
*
* @b Arguments
* @verbatim
eventId Intc event Identifier
@endverbatim
*
* <b> Return Value </b>
* CSL_IntcEventEnableState - Previous state
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Particular event will be enabled
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_IntcEventEnableState prevState;
...
prevState = CSL_intcEventEnable(eventId);
...
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_IntcEventEnableState CSL_intcEventEnable (
CSL_IntcEventId eventId
)
{
Int _x;
Int _y;
Int _regVal;
CSL_IntcEventEnableState _oldState;
_y = eventId >> 5;
_x = eventId & 0x1f;
_regVal = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[_y];
_oldState = CSL_FEXTR(_regVal,_x,_x);
CSL_FINSR(_regVal,_x,_x,0);
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[_y] = _regVal;
return _oldState;
}
/* ============================================================================
* @n@b CSL_intcEventDisable
*
* @b Description
* This API disables particular event (EVTMASK0/1/2/3 bit programmation)
*
* @b Arguments
* @verbatim
eventId Intc event Identifier
@endverbatim
*
* <b> Return Value </b>
* CSL_IntcEventEnableState - Previous state
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Particular event will be disabled
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_IntcEventEnableState eventStat;
...
eventStat = CSL_intcEventDisable(eventId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_IntcEventEnableState CSL_intcEventDisable (
CSL_IntcEventId eventId
)
{
Int _x;
Int _y;
Int _regVal;
CSL_IntcEventEnableState oldState;
_y = eventId >> 5;
_x = eventId & 0x1f;
_regVal = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[_y];
oldState = CSL_FEXTR(_regVal,_x,_x);
CSL_FINSR(_regVal,_x,_x,1);
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[_y] = _regVal;
return oldState;
}
/* ============================================================================
* @n@b CSL_intcEventRestore
*
* @b Description
* This API restores particular event (EVTMASK0/1/2/3 bit programmation)
*
* @b Arguments
* @verbatim
eventId Intc event Identifier
restoreVal Restore value
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n particular event will be restored
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_IntcEventEnableState restoreVal;
CSL_IntcEventEnableState eventStat;
...
eventStat = CSL_intcEventResore(eventId, restoreVal);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcEventRestore(
CSL_IntcEventId eventId,
CSL_IntcEventEnableState restoreVal
)
{
Int _x;
Int _y;
_y = eventId >> 5;
_x = eventId & 0x1F;
CSL_FINSR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[_y], _x, _x, \
restoreVal);
}
/* ============================================================================
* @n@b CSL_intcEventSet
*
* @b Description
* This API sets Event (EVTMASK0/1/2/3 bit programmation)
*
* @b Arguments
* @verbatim
eventId Intc event identifier
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Particular event will set
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
...
CSL_intcEventSet(eventId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcEventSet(
CSL_IntcEventId eventId
)
{
Int _x;
Int _y;
_y = eventId >> 5;
_x = eventId & 0x1F;
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTSET[_y] = CSL_FMKR(_x,_x,1);
}
/* ============================================================================
* @n@b CSL_intcEventClear
*
* @b Description
* This API clears particular event (EVTMASK0/1/2/3 bit programmation)
*
* @b Arguments
* @verbatim
eventId Intc event identifier
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Particular event will be cleared
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
...
CSL_intcEventClear(eventId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcEventClear (
CSL_IntcEventId eventId
)
{
Int _x;
Int _y;
_y = eventId >> 5;
_x = eventId & 0x1F;
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[_y] = CSL_FMKR(_x,_x,1);
}
/* ============================================================================
* @n@b CSL_intcCombinedEventClear
*
* @b Description
* This API clears particular combined events
* (EVTMASK0/1/2/3 bit programmation)
*
* @b Arguments
* @verbatim
eventId Intc event identifier
clearMask Bit Mask of events to be cleared
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Particular combined event will be cleared
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_BitMask32 clearMask;
...
CSL_intcEventClear(eventId, clearMask);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcCombinedEventClear(
CSL_IntcEventId eventId,
CSL_BitMask32 clearMask
)
{
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[eventId] = clearMask;
}
/* ============================================================================
* @n@b CSL_intcCombinedEventGet
*
* @b Description
* This API gets particular combined events
* (EVTMASK0/1/2/3 bit programmation)
*
* @b Arguments
* @verbatim
eventId Intc event identifier
@endverbatim
*
* <b> Return Value </b>
* CSL_BitMask32 - The combined events information
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_BitMask32 combEvtStat;
...
combEvtStat = CSL_intcEventClear(eventId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_BitMask32 CSL_intcCombinedEventGet(
CSL_IntcEventId eventId
)
{
return (((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[eventId]);
}
/* ============================================================================
* @n@b CSL_intcCombinedEventEnable
*
* @b Description
* This API enables particular combined events
*
* @b Arguments
* @verbatim
eventId event identifier
enableMask BitMask of events to be enabled
@endverbatim
*
* <b> Return Value </b>
* CSL_BitMask32 - previous state
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_BitMask32 enableMask;
CSL_BitMask32 combEvtStat;
...
combEvtStat = CSL_intCombinedEventEnable(eventId, enableMask);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_BitMask32 CSL_intcCombinedEventEnable(
CSL_IntcEventId eventId,
CSL_BitMask32 enableMask
)
{
CSL_BitMask32 evtMask =
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[eventId];
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[eventId] = ~enableMask;
return evtMask;
}
/** ============================================================================
* @n@b CSL_intcCombinedEventDisable
*
* @b Description
* This API disables particular combined events
*
* @b Arguments
* @verbatim
eventId Intc event identifier
enableMask Bit Mask of events to be disabled
@endverbatim
*
* <b> Return Value </b>
* CSL_BitMask32 - previous state
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_BitMask32 disableMask;
CSL_BitMask32 combEvtStat;
...
combEvtStat=CSL_intCombinedEventDisable(eventId, disableMask);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_BitMask32 CSL_intcCombinedEventDisable (
CSL_IntcEventId eventId,
CSL_BitMask32 enableMask
)
{
CSL_BitMask32 evtMask =
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[eventId];
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[eventId] = enableMask;
return evtMask ;
}
/* ============================================================================
* @n@b CSL_intcCombinedEventRestore
*
* @b Description
* This API restores particular combined events
*
* @b Arguments
* @verbatim
eventId Intc event identifier
restoreMask Bit Mask of events to be restored
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_BitMask32 restoreMask;
CSL_BitMask32 combEvtStat;
...
combEvtStat=CSL_intCombinedEventRestore(eventId, restoreMask);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcCombinedEventRestore(
CSL_IntcEventId eventId,
CSL_BitMask32 restoreMask
)
{
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTMASK[eventId] = restoreMask;
}
/* ============================================================================
* @n@b CSL_intcInterruptDropEnable
*
* @b Description
* This API enables interrupts for which drop detection
*
* @b Arguments
* @verbatim
dropMask Vector id mask
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_BitMask32 dropMask;
...
CSL_intcInterruptDropEnable(dropMask );
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcInterruptDropEnable (
CSL_BitMask32 dropMask
)
{
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTDMASK &= ~dropMask;
}
/* ============================================================================
* @n@b CSL_intcInterruptDropDisable
*
* @b Description
* This API disables interrupts for which drop detection
*
* @b Arguments
* @verbatim
dropMask Vector id mask
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_BitMask32 dropMask;
...
CSL_intcInterruptDropEnable(dropMask);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcInterruptDropDisable (
CSL_BitMask32 dropMask
)
{
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTDMASK |= dropMask;
}
/* ============================================================================
* @n@b CSL_intcInvokeEventHandle
*
* @b Description
* This API is for the purpose of excption handler which will need to be
* written by the user. This API invokes the event handler regisered by
* the user at the time of event Open and event handler registration
*
* @b Arguments
* @verbatim
evtId Intc event identifier
@endverbatim
*
* <b> Return Value </b>
* CSL_SOK - success.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Status status;
CSL_IntcEventId evtId;
...
status = CSL_intcInvokeEventHandle(evtId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_intcInvokeEventHandle (
CSL_IntcEventId evtId
)
{
if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE)
_CSL_intcEventHandlerRecord[_CSL_intcEventOffsetMap[evtId]].handler (
_CSL_intcEventHandlerRecord[_CSL_intcEventOffsetMap[evtId]].arg );
return CSL_SOK;
}
/* ============================================================================
* @n@b CSL_intcQueryEventStatus
*
* @b Description
* This API is to check whether a specified event is enabled or not
*
* @b Arguments
* @verbatim
eventId - Intc event identifier.
@endverbatim
*
* <b> Return Value </b>
* Bool
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
Bool returnVal;
...
returnVal = CSL_intcQueryEventStatus(eventId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE Bool CSL_intcQueryEventStatus(CSL_IntcEventId eventId)
{
Int _x;
Int _y;
_y = eventId >> 5;
_x = eventId & 0x1F;
return ((Bool)(CSL_FEXTR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTFLAG[_y], \
_x,_x)));
}
/* CPU Interrupt Handling routines */
/* ============================================================================
* @n@b CSL_intcInterruptEnable
*
* @b Description
* This API is enables the Interrupt
*
* @b Arguments
* @verbatim
vectId vector id to enable.
@endverbatim
*
* <b> Return Value </b>
* Uint32 - previous state
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcVectId vectId;
Uint32 returnVal;
...
returnVal = CSL_intcInterruptEnable(vectId);
...
@endverbatim
* ===========================================================================
*/
Uint32 CSL_intcInterruptEnable (
CSL_IntcVectId vectId
);
/* ============================================================================
* @n@b CSL_intcInterruptDisable
*
* @b Description
* This API is used to disable the interrupt
*
* @b Arguments
* @verbatim
vectId Vector Id to disable.
@endverbatim
*
* <b> Return Value </b>
* Uint32 - previous state
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcVectId vectId;
Uint32 returnVal;
...
returnVal = CSL_intcInterruptDisable(vectID);
...
@endverbatim
* ===========================================================================
*/
Uint32 CSL_intcInterruptDisable (
CSL_IntcVectId vectId
);
/* ============================================================================
* @n@b CSL_intcInterruptRestore
*
* @b Description
* This API restores the Interrupt
*
* @b Arguments
* @verbatim
vectId vector id to restore.
restoreVal Value to be restored
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcVectId vectId;
Uint32 restoreVal;
...
CSL_intcInterruptDisable(vectId, restoreVal);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcInterruptRestore (
CSL_IntcVectId vectId,
Uint32 restoreVal
);
/* ============================================================================
* @n@b CSL_intcInterruptSet
*
* @b Description
* This API is sets interrupt.
*
* @b Arguments
* @verbatim
vectId Vector id to set
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcVectId vectId;
...
CSL_intcInterruptSet(vectId);
...
@endverbatim
* ===========================================================================
*/
void CSL_intcInterruptSet (
CSL_IntcVectId vectId
);
/* ============================================================================
* @n@b CSL_intcInterruptClear
*
* @b Description
* This API is clears specified interrupt
*
* @b Arguments
* @verbatim
vectId Vector id to cleared
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcVectId vectId;
...
CSL_intcInterruptClear (vectId);
...
@endverbatim
* ===========================================================================
*/
void CSL_intcInterruptClear (
CSL_IntcVectId vectId
);
/* ============================================================================
* @n@b CSL_intcQueryInterruptStatus
*
* @b Description
* This API is to check whether a specified CPU interrupt is pending or not
*
* @b Arguments
* @verbatim
vectId Vector id
@endverbatim
*
* <b> Return Value </b>
* Bool
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_IntcVectId vectId;
Bool returnVal;
...
returnVal = CSL_intcInterruptSet(vectId);
...
@endverbatim
* ===========================================================================
*/
Bool CSL_intcQueryInterruptStatus (
CSL_IntcVectId vectId
);
/* Exception handling routines */
/* ============================================================================
* @n@b CSL_intcExcepEnable
*
* @b Description
* This API enables the specific exception event
*
* @b Arguments
* @verbatim
eventId exception event id to be enabled
@endverbatim
*
* <b> Return Value </b>
* CSL_IntcEventEnableState - old state.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_IntcEventEnableState returnVal;
...
returnVal = CSL_intcExcepEnable(eventId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_IntcEventEnableState CSL_intcExcepEnable (
CSL_IntcEventId eventId
)
{
Int _x;
Int _y;
Int _regVal;
CSL_IntcEventEnableState _oldState;
_y = eventId >> 5;
_x = eventId & 0x1f;
_regVal = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[_y];
_oldState = CSL_FEXTR(_regVal,_x,_x);
CSL_FINSR(_regVal,_x,_x,0);
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[_y] = _regVal;
return _oldState;
}
/* ============================================================================
* @n@b CSL_intcExcepDisable
*
* @b Description
* This API is disables the specific exception event
*
* @b Arguments
* @verbatim
eventId exception event id to be disabled
@endverbatim
*
* <b> Return Value </b>
* CSL_IntcEventEnableState - old state
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
CSL_IntcEventEnableState returnVal;
...
returnVal = CSL_intcExcepDisable(eventId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_IntcEventEnableState CSL_intcExcepDisable (
CSL_IntcEventId eventId
)
{
Int _x;
Int _y;
Int _regVal;
CSL_IntcEventEnableState oldState;
_y = eventId >> 5;
_x = eventId & 0x1f;
_regVal = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[_y];
oldState = CSL_FEXTR(_regVal,_x,_x);
CSL_FINSR(_regVal,_x,_x,1);
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[_y] = _regVal;
return oldState;
}
/* ============================================================================
* @n@b CSL_intcExcepRestore
*
* @b Description
* This API restores the specific exception event
*
* @b Arguments
* @verbatim
eventId exception event id to be restored.
restoreVal restore value
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
Uint32 restoreVal;
...
CSL_intcExcepRestore(eventId, restoreVal);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcExcepRestore (
CSL_IntcEventId eventId,
Uint32 restoreVal
)
{
Int _x;
Int _y;
_y = eventId >> 5;
_x = eventId & 0x1F;
CSL_FINSR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[_y],_x,_x, \
restoreVal);
}
/* ============================================================================
* @n@b CSL_intcExcepClear
*
* @b Description
* This API clears the specific exception event
*
* @b Arguments
* @verbatim
eventId exception event id to be cleared
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n INTC hardware registers
*
* @b Example
* @verbatim
CSL_IntcEventId eventId;
...
CSL_intcExcepClear(eventId);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE void CSL_intcExcepClear (
CSL_IntcEventId eventId
)
{
Int _x;
Int _y;
_y = eventId >> 5;
_x = eventId & 0x1F;
CSL_FINSR(((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[_y],_x,_x,1);
}
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/common/csl_srioGetBaseAddress.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_srioGetBaseAddress.c
*
* @path $(CSLPATH)\src\common
*
* @desc CSL Implementation of CSL_srioGetBaseAddress
*
*/
/* =============================================================================
* Revision History
* ===============
* 25-Aug-2005 PSK File Created.
* =============================================================================
*/
#include <soc.h>
#include <csl_srio.h>
/** ============================================================================
* @n@b CSL_SrioGetBaseAddress
*
* @b Description
* @n This function gets the base address of the given SRIOinstance.
This function is used for getting the base address of the peripheral
* instance. This function will be called inside the CSL_srioOpen()
* function call. This function is open for re-implementing if the user
* wants to modify the base address of the peripheral object to point to
* a different location and there by allow CSL initiated write/reads into
* peripheral. MMR's go to an alternate location.
*
* @b Arguments
* @verbatim
srioNum Specifies the instance of the SRIO to be opened
pSrioParam SRIO module specific parameters
pBaseAddress Pointer to base address structure containing base
address details
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Successful on getting the base
* address of srio
* @li CSL_ESYS_FAIL SRIO instance is not
* available.
* @li CSL_ESYS_INVPARAMS Invalid Parameters
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure is modified.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_SrioBaseAddress baseAddress;
...
status = CSL_SrioGetBaseAddress(CSL_SRIO, NULL, &baseAddress);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_srioGetBaseAddress, ".text:csl_section:srio");
CSL_Status CSL_srioGetBaseAddress (
CSL_InstNum srioNum,
CSL_SrioParam *pSrioParam,
CSL_SrioBaseAddress *pBaseAddress
)
{
CSL_Status status = CSL_SOK;
if (pBaseAddress == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (srioNum) {
case CSL_SRIO:
pBaseAddress->regs = (CSL_SrioRegsOvly)CSL_SRIO_0_REGS;
break;
default:
pBaseAddress->regs = (CSL_SrioRegsOvly)NULL;
status = CSL_ESYS_FAIL;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioHwSetup.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ==========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* provided
* ==========================================================================
*/
/** ===========================================================================
* @file csl_gpioHwSetup.c
*
* @path $(CSLPATH)\src\gpio
*
* @Desc File for functional layer of CSL API CSL_gpioHwSetup()
* ============================================================================
*/
/* ============================================================================
* Revision History
* =================
* 10-Jun-2004 PGR file created
* 06-Mar-2006 ds Updated the documentation
* ============================================================================
*/
#include <csl_gpio.h>
/** ============================================================================
* @n@b CSL_gpioHwSetup
*
* @b Description
* @n It configures the gpio registers as per the values passed
* in the hardware setup structure.This is a dummy API .
* Its is left for future implementation.
*
* @b Arguments
* @verbatim
hGpio Handle to the GPIO instance
hwSetup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n Both CSL_gpioInit() and CSL_gpioOpen() must be called successfully in
* order before this function.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_GpioHandle hGpio;
CSL_GpioObj gpioObj;
CSL_GpioHwSetup hwSetup;
CSL_Status status;
hwSetup.extendSetup = NULL;
...
hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO, NULL, &status);
status = CSL_gpioHwSetup(hGpio, &hwSetup);
* @endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_gpioHwSetup, ".text:csl_section:gpio");
CSL_Status CSL_gpioHwSetup (
CSL_GpioHandle hGpio,
CSL_GpioHwSetup *setup
)
{
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/common/csl_ddr2GetBaseAddress.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_ddr2GetBaseAddress.c
*
* @path $(CSLPATH)\src\common
*
* @desc CSL Implementation of CSL_ddr2GetBaseAddress
*
*/
/* ============================================================================
* Revision History
* ===============
* 12-April-2005 <NAME> File Created.
* 25-Jan-2006 SD Modified the code section start address
* 09-Aug-2006 NG Added condition to check the invalid parameter
* ============================================================================
*/
#include <soc.h>
#include <csl_ddr2.h>
/** ============================================================================
* @n@b CSL_ddr2GetBaseAddress
*
* @b Description
* @n The get base address call will give the External memory interface current
* current instance base address
*
* @b Arguments
* @verbatim
ddr2Num Specifies the instance of the DDR2 external memory
interface for which the base address is requested
pDdr2Param Module specific parameters.
pBaseAddress Pointer to the base address structure to return the
base address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Successful on getting the base
* address of ddr2
* @li CSL_ESYS_FAIL The external memory interface
* instance is not available.
* @li CSL_ESYS_INVPARAMS Invalid parameter
*
* <b> Pre Condition </b>
* @n @a CSL_ddr2Init() and CSL_ddr2Open () must be called successfully.
*
* <b> Post Condition </b>
* @n Base address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_Ddr2BaseAddress baseAddress;
...
status = CSL_ddr2GetBaseAddress(CSL_DDR2, NULL, &baseAddress);
@endverbatim
* @return Returns the status of the get base address operation
*
* ============================================================================
*/
#pragma CODE_SECTION (CSL_ddr2GetBaseAddress, ".text:csl_section:ddr2");
CSL_Status
CSL_ddr2GetBaseAddress (
CSL_InstNum ddr2Num,
CSL_Ddr2Param *pDdr2Param,
CSL_Ddr2BaseAddress *pBaseAddress
)
{
CSL_Status status = CSL_SOK;
if (pBaseAddress == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (ddr2Num) {
case CSL_DDR2:
pBaseAddress->regs = (CSL_Ddr2RegsOvly)CSL_DDR2_0_REGS;
break;
default:
pBaseAddress->regs = (CSL_Ddr2RegsOvly)NULL;
status = CSL_ESYS_FAIL;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/FB_W2100_SCU_MEA256/Device_lib.h | #ifndef DEVICE_LIB_H_
#define DEVICE_LIB_H_
#include <csl_types.h>
#include "global.h"
#define READ_REGISTER(reg) DEVICE_REGISTER(reg)
#define WRITE_REGISTER(reg, value) {DEVICE_REGISTER(reg) = value; (*(volatile Uint32 *)(0x70000000)) = 0; (*(volatile Uint32 *)(0x70000000)); }
extern Uint32 MeaData[MAX_DATAPOINTS_PER_FRAME];
extern Uint32 MonitorData[MONITOR_ARRAY];
extern Uint32 ChannelsPerSweepConfigured;
#define IFB_LED_CONFIG 0x002c
#define IFB_AUX_OUT 0x04b0
#define IFB_AUX_IN 0x04b4
#define IFB_AUX_DIR 0x04b8
#define DSP_INDATA_CTRL0 0x0b00
#define DSPINDATACTRL0_INT_ENABLE 0x0100 // Enable IRQ
#define DSPINDATACTRL0_CLEAR_FIFO 0x0002
#define DSPINDATACTRL0_RESET_FIFO 0x0001
#define DSP_OUTDATA_CTRL 0x0b04
#define DSP_OUTDATA_THR 0x0b14
#define DSP_INDATA_CHANNELS 0x0b18
#define FEEDBACK_REGISTER 0x0480
#define MAILBOX_CTRL 0x0b24
#define DIGITAL_MUX 0x0540 // Digital MUX
#define DSP_INDATA_CONFIG0 0xb80
#define DSP_INDATA_CONFIG1 0xb81
#define DSP_INDATA_CONFIG2 0xb82
#define DSP_INDATA_CONFIG3 0xb83
#define DSP_INDATA_CONFIG4 0xb84
#define DSP_INDATA_CONFIG5 0xb85
#define DSP_INDATA_CONFIG6 0xb86
#define DSP_INDATA_CONFIG7 0xb87
#define DSP_INDATA_CONFIG8 0xb88
#define DSP_INDATA_CONFIG9 0xb89
#define DSP_INDATA_CONFIGa 0xb8a
#define DSP_INDATA_CONFIGb 0xb8b
#define DSP_INDATA_CONFIGc 0xb8c
#define DSP_INDATA_CONFIGd 0xb8d
#define DSP_INDATA_CONFIGe 0xb8e
#define DSP_INDATA_CONFIGf 0xb8f
#define MAILBOX_LASTWRITTEN 0xb28 /// was 0x428 MEA2100
#define MAILBOX_BASE 0x1000
#define MAILBOX_THRSHOLD 0x00
#define MAILBOX_DEADTIME 0x04
#define MAILBOX_AMPLITUDE 0x08
#define MAILBOX_DURATION 0x0c
#define MAILBOX_REPEATS 0x10
#define MAILBOX_STEPSIZE 0x14
void MEA21_init();
void MEA21_enableData();
void SetMonitorSize(int datapoints);
void timer_setperiod(int period);
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3HwSetup.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3HwSetup.c
*
* @path $(CSLPATH)\src\edma
*
* @desc File for functional layer of CSL API CSL_edma3HwSetup()
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* =============================================================================
*/
#include <csl_edma3.h>
#include <csl_edma3Aux.h>
/** ============================================================================
* @n@b CSL_edma3HwSetup
*
* @b Description
* @n This function initializes the device registers with the appropriate
* values provided through the HwSetup Data structure. After the Setup is
* completed, the device is ready for operation. For information passed
* through the HwSetup Data structure, refer CSL_Edma3HwSetup.This does
* the setup for all dma/qdma channels viz. the parameter entry mapping,
* the trigger word setting (if QDMA channels) and the event queue mapping
* of the channel.
*
* @b Arguments
* @verbatim
hMod Edma module Handle
setup Pointer to the setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hwsetup successful
* @li CSL_ESYS_BADHANDLE - The handle passed is
* invalid
* @li CSL_ESYS_INVPARAMS - The parameter passed is invalid
*
* <b> Pre Condition </b>
* @n CSL_edma3Init(), CSL_edma3Open() must be called successfully in that
* order before this API can be invoked
*
* <b> Post Condition </b>
* @n Edma registers are configured according to the hardware setup
* parameters
*
* @b Modifies
* @n Edma registers
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] =
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] =
CSL_EDMA3_QDMACHANNELSETUP_DEFAULT;
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = &qdmaSetup[0];
CSL_edma3HwSetup(hModule,&hwSetup);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3HwSetup, ".text:csl_section:edma3");
CSL_Status CSL_edma3HwSetup(
CSL_Edma3Handle hMod,
CSL_Edma3HwSetup *setup
)
{
Uint32 numCha;
Uint32 tempQnum = 0;
Uint32 tempChmap = 0;
Uint32 ii;
CSL_Status status = CSL_SOK;
if (hMod == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (setup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
if (setup->dmaChaSetup != NULL) {
for (numCha = 0 ; numCha < CSL_EDMA3_NUM_DMACH; numCha++) {
#ifdef CSL_EDMA3_CHMAPEXIST
hMod->regs->DCHMAP[numCha] =
CSL_FMK(EDMA3CC_DCHMAP_PAENTRY, \
setup->dmaChaSetup[numCha].paramNum);
#endif
ii = numCha % 8;
CSL_FINSR(tempQnum,(ii * 4) + 2,(ii * 4), \
setup->dmaChaSetup[numCha].que);
if (((ii + 1) % 8) == 0) {
hMod->regs->DMAQNUM[numCha/8] = tempQnum;
tempQnum = 0;
}
}
}
if (setup->qdmaChaSetup != NULL) {
for (numCha = 0 ; numCha < CSL_EDMA3_NUM_QDMACH; numCha++) {
tempChmap = CSL_FMK(EDMA3CC_QCHMAP_PAENTRY, \
setup->qdmaChaSetup[numCha].paramNum)| \
CSL_FMK(EDMA3CC_QCHMAP_TRWORD, \
setup->qdmaChaSetup[numCha].triggerWord);
hMod->regs->QCHMAP[numCha] = tempChmap;
CSL_FINSR(tempQnum, (numCha * 4) + 2,(numCha * 4), \
setup->qdmaChaSetup[numCha].que);
}
hMod->regs->QDMAQNUM = tempQnum;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_emac.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_emac.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for EMAC
*/
#ifndef _CSLR_EMAC_H_
#define _CSLR_EMAC_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 TXIDVER;
volatile Uint32 TXCONTROL;
volatile Uint32 TXTEARDOWN;
volatile Uint8 RSVD0[4];
volatile Uint32 RXIDVER;
volatile Uint32 RXCONTROL;
volatile Uint32 RXTEARDOWN;
volatile Uint8 RSVD1[100];
volatile Uint32 TXINTSTATRAW;
volatile Uint32 TXINTSTATMASKED;
volatile Uint32 TXINTMASKSET;
volatile Uint32 TXINTMASKCLEAR;
volatile Uint32 MACINVECTOR;
volatile Uint8 RSVD2[12];
volatile Uint32 RXINTSTATRAW;
volatile Uint32 RXINTSTATMASKED;
volatile Uint32 RXINTMASKSET;
volatile Uint32 RXINTMASKCLEAR;
volatile Uint32 MACINTSTATRAW;
volatile Uint32 MACINTSTATMASKED;
volatile Uint32 MACINTMASKSET;
volatile Uint32 MACINTMASKCLEAR;
volatile Uint8 RSVD3[64];
volatile Uint32 RXMBPENABLE;
volatile Uint32 RXUNICASTSET;
volatile Uint32 RXUNICASTCLEAR;
volatile Uint32 RXMAXLEN;
volatile Uint32 RXBUFFEROFFSET;
volatile Uint32 RXFILTERLOWTHRESH;
volatile Uint8 RSVD4[8];
volatile Uint32 RX0FLOWTHRESH;
volatile Uint32 RX1FLOWTHRESH;
volatile Uint32 RX2FLOWTHRESH;
volatile Uint32 RX3FLOWTHRESH;
volatile Uint32 RX4FLOWTHRESH;
volatile Uint32 RX5FLOWTHRESH;
volatile Uint32 RX6FLOWTHRESH;
volatile Uint32 RX7FLOWTHRESH;
volatile Uint32 RX0FREEBUFFER;
volatile Uint32 RX1FREEBUFFER;
volatile Uint32 RX2FREEBUFFER;
volatile Uint32 RX3FREEBUFFER;
volatile Uint32 RX4FREEBUFFER;
volatile Uint32 RX5FREEBUFFER;
volatile Uint32 RX6FREEBUFFER;
volatile Uint32 RX7FREEBUFFER;
volatile Uint32 MACCONTROL;
volatile Uint32 MACSTATUS;
volatile Uint32 EMCONTROL;
volatile Uint32 FIFOCONTROL;
volatile Uint32 MACCONFIG;
volatile Uint32 SOFTRESET;
volatile Uint8 RSVD5[88];
volatile Uint32 MACSRCADDRLO;
volatile Uint32 MACSRCADDRHI;
volatile Uint32 MACHASH1;
volatile Uint32 MACHASH2;
volatile Uint32 BOFFTEST;
volatile Uint32 TPACETEST;
volatile Uint32 RXPAUSE;
volatile Uint32 TXPAUSE;
volatile Uint8 RSVD6[16];
volatile Uint32 RXGOODFRAMES;
volatile Uint32 RXBCASTFRAMES;
volatile Uint32 RXMCASTFRAMES;
volatile Uint32 RXPAUSEFRAMES;
volatile Uint32 RXCRCERRORS;
volatile Uint32 RXALIGNCODEERRORS;
volatile Uint32 RXOVERSIZED;
volatile Uint32 RXJABBER;
volatile Uint32 RXUNDERSIZED;
volatile Uint32 RXFRAGMENTS;
volatile Uint32 RXFILTERED;
volatile Uint32 RXQOSFILTERED;
volatile Uint32 RXOCTETS;
volatile Uint32 TXGOODFRAMES;
volatile Uint32 TXBCASTFRAMES;
volatile Uint32 TXMCASTFRAMES;
volatile Uint32 TXPAUSEFRAMES;
volatile Uint32 TXDEFERRED;
volatile Uint32 TXCOLLISION;
volatile Uint32 TXSINGLECOLL;
volatile Uint32 TXMULTICOLL;
volatile Uint32 TXEXCESSIVECOLL;
volatile Uint32 TXLATECOLL;
volatile Uint32 TXUNDERRUN;
volatile Uint32 TXCARRIERSENSE;
volatile Uint32 TXOCTETS;
volatile Uint32 FRAME64;
volatile Uint32 FRAME65T127;
volatile Uint32 FRAME128T255;
volatile Uint32 FRAME256T511;
volatile Uint32 FRAME512T1023;
volatile Uint32 FRAME1024TUP;
volatile Uint32 NETOCTETS;
volatile Uint32 RXSOFOVERRUNS;
volatile Uint32 RXMOFOVERRUNS;
volatile Uint32 RXDMAOVERRUNS;
volatile Uint8 RSVD7[624];
volatile Uint32 MACADDRLO;
volatile Uint32 MACADDRHI;
volatile Uint32 MACINDEX;
volatile Uint8 RSVD8[244];
volatile Uint32 TX0HDP;
volatile Uint32 TX1HDP;
volatile Uint32 TX2HDP;
volatile Uint32 TX3HDP;
volatile Uint32 TX4HDP;
volatile Uint32 TX5HDP;
volatile Uint32 TX6HDP;
volatile Uint32 TX7HDP;
volatile Uint32 RX0HDP;
volatile Uint32 RX1HDP;
volatile Uint32 RX2HDP;
volatile Uint32 RX3HDP;
volatile Uint32 RX4HDP;
volatile Uint32 RX5HDP;
volatile Uint32 RX6HDP;
volatile Uint32 RX7HDP;
volatile Uint32 TX0CP;
volatile Uint32 TX1CP;
volatile Uint32 TX2CP;
volatile Uint32 TX3CP;
volatile Uint32 TX4CP;
volatile Uint32 TX5CP;
volatile Uint32 TX6CP;
volatile Uint32 TX7CP;
volatile Uint32 RX0CP;
volatile Uint32 RX1CP;
volatile Uint32 RX2CP;
volatile Uint32 RX3CP;
volatile Uint32 RX4CP;
volatile Uint32 RX5CP;
volatile Uint32 RX6CP;
volatile Uint32 RX7CP;
} CSL_EmacRegs;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* TXIDVER */
#define CSL_EMAC_TXIDVER_TXIDENT_MASK (0xFFFF0000u)
#define CSL_EMAC_TXIDVER_TXIDENT_SHIFT (0x00000010u)
#define CSL_EMAC_TXIDVER_TXIDENT_RESETVAL (0x0000000Cu)
#define CSL_EMAC_TXIDVER_TXMAJORVER_MASK (0x0000FF00u)
#define CSL_EMAC_TXIDVER_TXMAJORVER_SHIFT (0x00000008u)
#define CSL_EMAC_TXIDVER_TXMAJORVER_RESETVAL (0x0000000Au)
#define CSL_EMAC_TXIDVER_TXMINORVER_MASK (0x000000FFu)
#define CSL_EMAC_TXIDVER_TXMINORVER_SHIFT (0x00000000u)
#define CSL_EMAC_TXIDVER_TXMINORVER_RESETVAL (0x00000007u)
#define CSL_EMAC_TXIDVER_RESETVAL (0x000C0A07u)
/* TXCONTROL */
#define CSL_EMAC_TXCONTROL_TXEN_MASK (0x00000001u)
#define CSL_EMAC_TXCONTROL_TXEN_SHIFT (0x00000000u)
#define CSL_EMAC_TXCONTROL_TXEN_RESETVAL (0x00000000u)
/*----TXEN Tokens----*/
#define CSL_EMAC_TXCONTROL_TXEN_DISABLE (0x00000000u)
#define CSL_EMAC_TXCONTROL_TXEN_ENABLE (0x00000001u)
#define CSL_EMAC_TXCONTROL_RESETVAL (0x00000000u)
/* TXTEARDOWN */
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_MASK (0x00000007u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_SHIFT (0x00000000u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_RESETVAL (0x00000000u)
/*----TXTDNCH Tokens----*/
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_CHA0 (0x00000000u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_CHA1 (0x00000001u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_CHA2 (0x00000002u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_CHA3 (0x00000003u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_CHA4 (0x00000004u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_CHA5 (0x00000005u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_CHA6 (0x00000006u)
#define CSL_EMAC_TXTEARDOWN_TXTDNCH_CHA7 (0x00000007u)
#define CSL_EMAC_TXTEARDOWN_RESETVAL (0x00000000u)
/* RXIDVER */
#define CSL_EMAC_RXIDVER_RXIDENT_MASK (0xFFFF0000u)
#define CSL_EMAC_RXIDVER_RXIDENT_SHIFT (0x00000010u)
#define CSL_EMAC_RXIDVER_RXIDENT_RESETVAL (0x0000000Cu)
#define CSL_EMAC_RXIDVER_RXMAJORVER_MASK (0x0000FF00u)
#define CSL_EMAC_RXIDVER_RXMAJORVER_SHIFT (0x00000008u)
#define CSL_EMAC_RXIDVER_RXMAJORVER_RESETVAL (0x0000000Au)
#define CSL_EMAC_RXIDVER_RXMINORVER_MASK (0x000000FFu)
#define CSL_EMAC_RXIDVER_RXMINORVER_SHIFT (0x00000000u)
#define CSL_EMAC_RXIDVER_RXMINORVER_RESETVAL (0x00000007u)
#define CSL_EMAC_RXIDVER_RESETVAL (0x000C0A07u)
/* RXCONTROL */
#define CSL_EMAC_RXCONTROL_RXEN_MASK (0x00000001u)
#define CSL_EMAC_RXCONTROL_RXEN_SHIFT (0x00000000u)
#define CSL_EMAC_RXCONTROL_RXEN_RESETVAL (0x00000000u)
/*----RXEN Tokens----*/
#define CSL_EMAC_RXCONTROL_RXEN_DISABLE (0x00000000u)
#define CSL_EMAC_RXCONTROL_RXEN_ENABLE (0x00000001u)
#define CSL_EMAC_RXCONTROL_RESETVAL (0x00000000u)
/* RXTEARDOWN */
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_MASK (0x00000007u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_SHIFT (0x00000000u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_RESETVAL (0x00000000u)
/*----RXTDNCH Tokens----*/
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_CHA0 (0x00000000u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_CHA1 (0x00000001u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_CHA2 (0x00000002u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_CHA3 (0x00000003u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_CHA4 (0x00000004u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_CHA5 (0x00000005u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_CHA6 (0x00000006u)
#define CSL_EMAC_RXTEARDOWN_RXTDNCH_CHA7 (0x00000007u)
#define CSL_EMAC_RXTEARDOWN_RESETVAL (0x00000000u)
/* TXINTSTATRAW */
#define CSL_EMAC_TXINTSTATRAW_TX7PEND_MASK (0x00000080u)
#define CSL_EMAC_TXINTSTATRAW_TX7PEND_SHIFT (0x00000007u)
#define CSL_EMAC_TXINTSTATRAW_TX7PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_TX6PEND_MASK (0x00000040u)
#define CSL_EMAC_TXINTSTATRAW_TX6PEND_SHIFT (0x00000006u)
#define CSL_EMAC_TXINTSTATRAW_TX6PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_TX5PEND_MASK (0x00000020u)
#define CSL_EMAC_TXINTSTATRAW_TX5PEND_SHIFT (0x00000005u)
#define CSL_EMAC_TXINTSTATRAW_TX5PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_TX4PEND_MASK (0x00000010u)
#define CSL_EMAC_TXINTSTATRAW_TX4PEND_SHIFT (0x00000004u)
#define CSL_EMAC_TXINTSTATRAW_TX4PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_TX3PEND_MASK (0x00000008u)
#define CSL_EMAC_TXINTSTATRAW_TX3PEND_SHIFT (0x00000003u)
#define CSL_EMAC_TXINTSTATRAW_TX3PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_TX2PEND_MASK (0x00000004u)
#define CSL_EMAC_TXINTSTATRAW_TX2PEND_SHIFT (0x00000002u)
#define CSL_EMAC_TXINTSTATRAW_TX2PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_TX1PEND_MASK (0x00000002u)
#define CSL_EMAC_TXINTSTATRAW_TX1PEND_SHIFT (0x00000001u)
#define CSL_EMAC_TXINTSTATRAW_TX1PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_TX0PEND_MASK (0x00000001u)
#define CSL_EMAC_TXINTSTATRAW_TX0PEND_SHIFT (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_TX0PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATRAW_RESETVAL (0x00000000u)
/* TXINTSTATMASKED */
#define CSL_EMAC_TXINTSTATMASKED_TX7PEND_MASK (0x00000080u)
#define CSL_EMAC_TXINTSTATMASKED_TX7PEND_SHIFT (0x00000007u)
#define CSL_EMAC_TXINTSTATMASKED_TX7PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_TX6PEND_MASK (0x00000040u)
#define CSL_EMAC_TXINTSTATMASKED_TX6PEND_SHIFT (0x00000006u)
#define CSL_EMAC_TXINTSTATMASKED_TX6PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_TX5PEND_MASK (0x00000020u)
#define CSL_EMAC_TXINTSTATMASKED_TX5PEND_SHIFT (0x00000005u)
#define CSL_EMAC_TXINTSTATMASKED_TX5PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_TX4PEND_MASK (0x00000010u)
#define CSL_EMAC_TXINTSTATMASKED_TX4PEND_SHIFT (0x00000004u)
#define CSL_EMAC_TXINTSTATMASKED_TX4PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_TX3PEND_MASK (0x00000008u)
#define CSL_EMAC_TXINTSTATMASKED_TX3PEND_SHIFT (0x00000003u)
#define CSL_EMAC_TXINTSTATMASKED_TX3PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_TX2PEND_MASK (0x00000004u)
#define CSL_EMAC_TXINTSTATMASKED_TX2PEND_SHIFT (0x00000002u)
#define CSL_EMAC_TXINTSTATMASKED_TX2PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_TX1PEND_MASK (0x00000002u)
#define CSL_EMAC_TXINTSTATMASKED_TX1PEND_SHIFT (0x00000001u)
#define CSL_EMAC_TXINTSTATMASKED_TX1PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_TX0PEND_MASK (0x00000001u)
#define CSL_EMAC_TXINTSTATMASKED_TX0PEND_SHIFT (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_TX0PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTSTATMASKED_RESETVAL (0x00000000u)
/* TXINTMASKSET */
#define CSL_EMAC_TXINTMASKSET_TX7MASK_MASK (0x00000080u)
#define CSL_EMAC_TXINTMASKSET_TX7MASK_SHIFT (0x00000007u)
#define CSL_EMAC_TXINTMASKSET_TX7MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_TX6MASK_MASK (0x00000040u)
#define CSL_EMAC_TXINTMASKSET_TX6MASK_SHIFT (0x00000006u)
#define CSL_EMAC_TXINTMASKSET_TX6MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_TX5MASK_MASK (0x00000020u)
#define CSL_EMAC_TXINTMASKSET_TX5MASK_SHIFT (0x00000005u)
#define CSL_EMAC_TXINTMASKSET_TX5MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_TX4MASK_MASK (0x00000010u)
#define CSL_EMAC_TXINTMASKSET_TX4MASK_SHIFT (0x00000004u)
#define CSL_EMAC_TXINTMASKSET_TX4MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_TX3MASK_MASK (0x00000008u)
#define CSL_EMAC_TXINTMASKSET_TX3MASK_SHIFT (0x00000003u)
#define CSL_EMAC_TXINTMASKSET_TX3MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_TX2MASK_MASK (0x00000004u)
#define CSL_EMAC_TXINTMASKSET_TX2MASK_SHIFT (0x00000002u)
#define CSL_EMAC_TXINTMASKSET_TX2MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_TX1MASK_MASK (0x00000002u)
#define CSL_EMAC_TXINTMASKSET_TX1MASK_SHIFT (0x00000001u)
#define CSL_EMAC_TXINTMASKSET_TX1MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_TX0MASK_MASK (0x00000001u)
#define CSL_EMAC_TXINTMASKSET_TX0MASK_SHIFT (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_TX0MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKSET_RESETVAL (0x00000000u)
/* TXINTMASKCLEAR */
#define CSL_EMAC_TXINTMASKCLEAR_TX7MASK_MASK (0x00000080u)
#define CSL_EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT (0x00000007u)
#define CSL_EMAC_TXINTMASKCLEAR_TX7MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_TX6MASK_MASK (0x00000040u)
#define CSL_EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT (0x00000006u)
#define CSL_EMAC_TXINTMASKCLEAR_TX6MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_TX5MASK_MASK (0x00000020u)
#define CSL_EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT (0x00000005u)
#define CSL_EMAC_TXINTMASKCLEAR_TX5MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_TX4MASK_MASK (0x00000010u)
#define CSL_EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT (0x00000004u)
#define CSL_EMAC_TXINTMASKCLEAR_TX4MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_TX3MASK_MASK (0x00000008u)
#define CSL_EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT (0x00000003u)
#define CSL_EMAC_TXINTMASKCLEAR_TX3MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_TX2MASK_MASK (0x00000004u)
#define CSL_EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT (0x00000002u)
#define CSL_EMAC_TXINTMASKCLEAR_TX2MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_TX1MASK_MASK (0x00000002u)
#define CSL_EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT (0x00000001u)
#define CSL_EMAC_TXINTMASKCLEAR_TX1MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_TX0MASK_MASK (0x00000001u)
#define CSL_EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_TX0MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_TXINTMASKCLEAR_RESETVAL (0x00000000u)
/* MACINVECTOR */
#define CSL_EMAC_MACINVECTOR_USERINT_MASK (0x80000000u)
#define CSL_EMAC_MACINVECTOR_USERINT_SHIFT (0x0000001Fu)
#define CSL_EMAC_MACINVECTOR_USERINT_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINVECTOR_LINKINT_MASK (0x40000000u)
#define CSL_EMAC_MACINVECTOR_LINKINT_SHIFT (0x0000001Eu)
#define CSL_EMAC_MACINVECTOR_LINKINT_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINVECTOR_HOSTPEND_MASK (0x00020000u)
#define CSL_EMAC_MACINVECTOR_HOSTPEND_SHIFT (0x00000011u)
#define CSL_EMAC_MACINVECTOR_HOSTPEND_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINVECTOR_STATPEND_MASK (0x00010000u)
#define CSL_EMAC_MACINVECTOR_STATPEND_SHIFT (0x00000010u)
#define CSL_EMAC_MACINVECTOR_STATPEND_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINVECTOR_RXPEND_MASK (0x0000FF00u)
#define CSL_EMAC_MACINVECTOR_RXPEND_SHIFT (0x00000008u)
#define CSL_EMAC_MACINVECTOR_RXPEND_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINVECTOR_TXPEND_MASK (0x000000FFu)
#define CSL_EMAC_MACINVECTOR_TXPEND_SHIFT (0x00000000u)
#define CSL_EMAC_MACINVECTOR_TXPEND_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINVECTOR_RESETVAL (0x00000000u)
/* RXINTSTATRAW */
#define CSL_EMAC_RXINTSTATRAW_RX7PEND_MASK (0x00000080u)
#define CSL_EMAC_RXINTSTATRAW_RX7PEND_SHIFT (0x00000007u)
#define CSL_EMAC_RXINTSTATRAW_RX7PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RX6PEND_MASK (0x00000040u)
#define CSL_EMAC_RXINTSTATRAW_RX6PEND_SHIFT (0x00000006u)
#define CSL_EMAC_RXINTSTATRAW_RX6PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RX5PEND_MASK (0x00000020u)
#define CSL_EMAC_RXINTSTATRAW_RX5PEND_SHIFT (0x00000005u)
#define CSL_EMAC_RXINTSTATRAW_RX5PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RX4PEND_MASK (0x00000010u)
#define CSL_EMAC_RXINTSTATRAW_RX4PEND_SHIFT (0x00000004u)
#define CSL_EMAC_RXINTSTATRAW_RX4PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RX3PEND_MASK (0x00000008u)
#define CSL_EMAC_RXINTSTATRAW_RX3PEND_SHIFT (0x00000003u)
#define CSL_EMAC_RXINTSTATRAW_RX3PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RX2PEND_MASK (0x00000004u)
#define CSL_EMAC_RXINTSTATRAW_RX2PEND_SHIFT (0x00000002u)
#define CSL_EMAC_RXINTSTATRAW_RX2PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RX1PEND_MASK (0x00000002u)
#define CSL_EMAC_RXINTSTATRAW_RX1PEND_SHIFT (0x00000001u)
#define CSL_EMAC_RXINTSTATRAW_RX1PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RX0PEND_MASK (0x00000001u)
#define CSL_EMAC_RXINTSTATRAW_RX0PEND_SHIFT (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RX0PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATRAW_RESETVAL (0x00000000u)
/* RXINTSTATMASKED */
#define CSL_EMAC_RXINTSTATMASKED_RX7PEND_MASK (0x00000080u)
#define CSL_EMAC_RXINTSTATMASKED_RX7PEND_SHIFT (0x00000007u)
#define CSL_EMAC_RXINTSTATMASKED_RX7PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RX6PEND_MASK (0x00000040u)
#define CSL_EMAC_RXINTSTATMASKED_RX6PEND_SHIFT (0x00000006u)
#define CSL_EMAC_RXINTSTATMASKED_RX6PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RX5PEND_MASK (0x00000020u)
#define CSL_EMAC_RXINTSTATMASKED_RX5PEND_SHIFT (0x00000005u)
#define CSL_EMAC_RXINTSTATMASKED_RX5PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RX4PEND_MASK (0x00000010u)
#define CSL_EMAC_RXINTSTATMASKED_RX4PEND_SHIFT (0x00000004u)
#define CSL_EMAC_RXINTSTATMASKED_RX4PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RX3PEND_MASK (0x00000008u)
#define CSL_EMAC_RXINTSTATMASKED_RX3PEND_SHIFT (0x00000003u)
#define CSL_EMAC_RXINTSTATMASKED_RX3PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RX2PEND_MASK (0x00000004u)
#define CSL_EMAC_RXINTSTATMASKED_RX2PEND_SHIFT (0x00000002u)
#define CSL_EMAC_RXINTSTATMASKED_RX2PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RX1PEND_MASK (0x00000002u)
#define CSL_EMAC_RXINTSTATMASKED_RX1PEND_SHIFT (0x00000001u)
#define CSL_EMAC_RXINTSTATMASKED_RX1PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RX0PEND_MASK (0x00000001u)
#define CSL_EMAC_RXINTSTATMASKED_RX0PEND_SHIFT (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RX0PEND_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTSTATMASKED_RESETVAL (0x00000000u)
/* RXINTMASKSET */
#define CSL_EMAC_RXINTMASKSET_RX7MASK_MASK (0x00000080u)
#define CSL_EMAC_RXINTMASKSET_RX7MASK_SHIFT (0x00000007u)
#define CSL_EMAC_RXINTMASKSET_RX7MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RX6MASK_MASK (0x00000040u)
#define CSL_EMAC_RXINTMASKSET_RX6MASK_SHIFT (0x00000006u)
#define CSL_EMAC_RXINTMASKSET_RX6MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RX5MASK_MASK (0x00000020u)
#define CSL_EMAC_RXINTMASKSET_RX5MASK_SHIFT (0x00000005u)
#define CSL_EMAC_RXINTMASKSET_RX5MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RX4MASK_MASK (0x00000010u)
#define CSL_EMAC_RXINTMASKSET_RX4MASK_SHIFT (0x00000004u)
#define CSL_EMAC_RXINTMASKSET_RX4MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RX3MASK_MASK (0x00000008u)
#define CSL_EMAC_RXINTMASKSET_RX3MASK_SHIFT (0x00000003u)
#define CSL_EMAC_RXINTMASKSET_RX3MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RX2MASK_MASK (0x00000004u)
#define CSL_EMAC_RXINTMASKSET_RX2MASK_SHIFT (0x00000002u)
#define CSL_EMAC_RXINTMASKSET_RX2MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RX1MASK_MASK (0x00000002u)
#define CSL_EMAC_RXINTMASKSET_RX1MASK_SHIFT (0x00000001u)
#define CSL_EMAC_RXINTMASKSET_RX1MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RX0MASK_MASK (0x00000001u)
#define CSL_EMAC_RXINTMASKSET_RX0MASK_SHIFT (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RX0MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKSET_RESETVAL (0x00000000u)
/* RXINTMASKCLEAR */
#define CSL_EMAC_RXINTMASKCLEAR_RX7MASK_MASK (0x00000080u)
#define CSL_EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT (0x00000007u)
#define CSL_EMAC_RXINTMASKCLEAR_RX7MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RX6MASK_MASK (0x00000040u)
#define CSL_EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT (0x00000006u)
#define CSL_EMAC_RXINTMASKCLEAR_RX6MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RX5MASK_MASK (0x00000020u)
#define CSL_EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT (0x00000005u)
#define CSL_EMAC_RXINTMASKCLEAR_RX5MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RX4MASK_MASK (0x00000010u)
#define CSL_EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT (0x00000004u)
#define CSL_EMAC_RXINTMASKCLEAR_RX4MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RX3MASK_MASK (0x00000008u)
#define CSL_EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT (0x00000003u)
#define CSL_EMAC_RXINTMASKCLEAR_RX3MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RX2MASK_MASK (0x00000004u)
#define CSL_EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT (0x00000002u)
#define CSL_EMAC_RXINTMASKCLEAR_RX2MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RX1MASK_MASK (0x00000002u)
#define CSL_EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT (0x00000001u)
#define CSL_EMAC_RXINTMASKCLEAR_RX1MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RX0MASK_MASK (0x00000001u)
#define CSL_EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RX0MASK_RESETVAL (0x00000000u)
#define CSL_EMAC_RXINTMASKCLEAR_RESETVAL (0x00000000u)
/* MACINTSTATRAW */
#define CSL_EMAC_MACINTSTATRAW_HOSTPEND_MASK (0x00000002u)
#define CSL_EMAC_MACINTSTATRAW_HOSTPEND_SHIFT (0x00000001u)
#define CSL_EMAC_MACINTSTATRAW_HOSTPEND_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINTSTATRAW_STATPEND_MASK (0x00000001u)
#define CSL_EMAC_MACINTSTATRAW_STATPEND_SHIFT (0x00000000u)
#define CSL_EMAC_MACINTSTATRAW_STATPEND_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINTSTATRAW_RESETVAL (0x00000000u)
/* MACINTSTATMASKED */
#define CSL_EMAC_MACINTSTATMASKED_HOSTPEND_MASK (0x00000002u)
#define CSL_EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT (0x00000001u)
#define CSL_EMAC_MACINTSTATMASKED_HOSTPEND_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINTSTATMASKED_STATPEND_MASK (0x00000001u)
#define CSL_EMAC_MACINTSTATMASKED_STATPEND_SHIFT (0x00000000u)
#define CSL_EMAC_MACINTSTATMASKED_STATPEND_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINTSTATMASKED_RESETVAL (0x00000000u)
/* MACINTMASKSET */
#define CSL_EMAC_MACINTMASKSET_HOSTMASK_MASK (0x00000002u)
#define CSL_EMAC_MACINTMASKSET_HOSTMASK_SHIFT (0x00000001u)
#define CSL_EMAC_MACINTMASKSET_HOSTMASK_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINTMASKSET_STATMASK_MASK (0x00000001u)
#define CSL_EMAC_MACINTMASKSET_STATMASK_SHIFT (0x00000000u)
#define CSL_EMAC_MACINTMASKSET_STATMASK_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINTMASKSET_RESETVAL (0x00000000u)
/* MACINTMASKCLEAR */
#define CSL_EMAC_MACINTMASKCLEAR_HOSTMASK_MASK (0x00000002u)
#define CSL_EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT (0x00000001u)
#define CSL_EMAC_MACINTMASKCLEAR_HOSTMASK_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINTMASKCLEAR_STATMASK_MASK (0x00000001u)
#define CSL_EMAC_MACINTMASKCLEAR_STATMASK_SHIFT (0x00000000u)
#define CSL_EMAC_MACINTMASKCLEAR_STATMASK_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINTMASKCLEAR_RESETVAL (0x00000000u)
/* RXMBPENABLE */
#define CSL_EMAC_RXMBPENABLE_RXPASSCRC_MASK (0x40000000u)
#define CSL_EMAC_RXMBPENABLE_RXPASSCRC_SHIFT (0x0000001Eu)
#define CSL_EMAC_RXMBPENABLE_RXPASSCRC_RESETVAL (0x00000000u)
/*----RXPASSCRC Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXPASSCRC_DISCARD (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXPASSCRC_INCLUDE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXQOSEN_MASK (0x20000000u)
#define CSL_EMAC_RXMBPENABLE_RXQOSEN_SHIFT (0x0000001Du)
#define CSL_EMAC_RXMBPENABLE_RXQOSEN_RESETVAL (0x00000000u)
/*----RXQOSEN Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXQOSEN_DISABLE (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXQOSEN_ENABLE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXNOCHAIN_MASK (0x10000000u)
#define CSL_EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT (0x0000001Cu)
#define CSL_EMAC_RXMBPENABLE_RXNOCHAIN_RESETVAL (0x00000000u)
/*----RXNOCHAIN Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXNOCHAIN_DISABLE (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXNOCHAIN_ENABLE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXCMFEN_MASK (0x01000000u)
#define CSL_EMAC_RXMBPENABLE_RXCMFEN_SHIFT (0x00000018u)
#define CSL_EMAC_RXMBPENABLE_RXCMFEN_RESETVAL (0x00000000u)
/*----RXCMFEN Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXCMFEN_DISABLE (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXCMFEN_ENABLE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXCSFEN_MASK (0x00800000u)
#define CSL_EMAC_RXMBPENABLE_RXCSFEN_SHIFT (0x00000017u)
#define CSL_EMAC_RXMBPENABLE_RXCSFEN_RESETVAL (0x00000000u)
/*----RXCSFEN Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXCSFEN_DISABLE (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXCSFEN_ENABLE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXCEFEN_MASK (0x00400000u)
#define CSL_EMAC_RXMBPENABLE_RXCEFEN_SHIFT (0x00000016u)
#define CSL_EMAC_RXMBPENABLE_RXCEFEN_RESETVAL (0x00000000u)
/*----RXCEFEN Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXCEFEN_DISABLE (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXCEFEN_ENABLE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXCAFEN_MASK (0x00200000u)
#define CSL_EMAC_RXMBPENABLE_RXCAFEN_SHIFT (0x00000015u)
#define CSL_EMAC_RXMBPENABLE_RXCAFEN_RESETVAL (0x00000000u)
/*----RXCAFEN Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXCAFEN_DISABLE (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_MASK (0x00070000u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_SHIFT (0x00000010u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_RESETVAL (0x00000000u)
/*----RXPROMCH Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_CHA0 (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_CHA1 (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_CHA2 (0x00000002u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_CHA3 (0x00000003u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_CHA4 (0x00000004u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_CHA5 (0x00000005u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_CHA6 (0x00000006u)
#define CSL_EMAC_RXMBPENABLE_RXPROMCH_CHA7 (0x00000007u)
#define CSL_EMAC_RXMBPENABLE_RXBROADEN_MASK (0x00002000u)
#define CSL_EMAC_RXMBPENABLE_RXBROADEN_SHIFT (0x0000000Du)
#define CSL_EMAC_RXMBPENABLE_RXBROADEN_RESETVAL (0x00000000u)
/*----RXBROADEN Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXBROADEN_DISABLE (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXBROADEN_ENABLE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_MASK (0x00000700u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_SHIFT (0x00000008u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_RESETVAL (0x00000000u)
/*----RXBROADCH Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_CHA0 (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_CHA1 (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_CHA2 (0x00000002u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_CHA3 (0x00000003u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_CHA4 (0x00000004u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_CHA5 (0x00000005u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_CHA6 (0x00000006u)
#define CSL_EMAC_RXMBPENABLE_RXBROADCH_CHA7 (0x00000007u)
#define CSL_EMAC_RXMBPENABLE_RXMULTEN_MASK (0x00000020u)
#define CSL_EMAC_RXMBPENABLE_RXMULTEN_SHIFT (0x00000005u)
#define CSL_EMAC_RXMBPENABLE_RXMULTEN_RESETVAL (0x00000000u)
/*----RXMULTEN Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXMULTEN_DISABLE (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXMULTEN_ENABLE (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_MASK (0x00000007u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_SHIFT (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_RESETVAL (0x00000000u)
/*----RXMULTCH Tokens----*/
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_CHA0 (0x00000000u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_CHA1 (0x00000001u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_CHA2 (0x00000002u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_CHA3 (0x00000003u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_CHA4 (0x00000004u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_CHA5 (0x00000005u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_CHA6 (0x00000006u)
#define CSL_EMAC_RXMBPENABLE_RXMULTCH_CHA7 (0x00000007u)
#define CSL_EMAC_RXMBPENABLE_RESETVAL (0x00000000u)
/* RXUNICASTSET */
#define CSL_EMAC_RXUNICASTSET_RXCH7EN_MASK (0x00000080u)
#define CSL_EMAC_RXUNICASTSET_RXCH7EN_SHIFT (0x00000007u)
#define CSL_EMAC_RXUNICASTSET_RXCH7EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RXCH6EN_MASK (0x00000040u)
#define CSL_EMAC_RXUNICASTSET_RXCH6EN_SHIFT (0x00000006u)
#define CSL_EMAC_RXUNICASTSET_RXCH6EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RXCH5EN_MASK (0x00000020u)
#define CSL_EMAC_RXUNICASTSET_RXCH5EN_SHIFT (0x00000005u)
#define CSL_EMAC_RXUNICASTSET_RXCH5EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RXCH4EN_MASK (0x00000010u)
#define CSL_EMAC_RXUNICASTSET_RXCH4EN_SHIFT (0x00000004u)
#define CSL_EMAC_RXUNICASTSET_RXCH4EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RXCH3EN_MASK (0x00000008u)
#define CSL_EMAC_RXUNICASTSET_RXCH3EN_SHIFT (0x00000003u)
#define CSL_EMAC_RXUNICASTSET_RXCH3EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RXCH2EN_MASK (0x00000004u)
#define CSL_EMAC_RXUNICASTSET_RXCH2EN_SHIFT (0x00000002u)
#define CSL_EMAC_RXUNICASTSET_RXCH2EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RXCH1EN_MASK (0x00000002u)
#define CSL_EMAC_RXUNICASTSET_RXCH1EN_SHIFT (0x00000001u)
#define CSL_EMAC_RXUNICASTSET_RXCH1EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RXCH0EN_MASK (0x00000001u)
#define CSL_EMAC_RXUNICASTSET_RXCH0EN_SHIFT (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RXCH0EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTSET_RESETVAL (0x00000000u)
/* RXUNICASTCLEAR */
#define CSL_EMAC_RXUNICASTCLEAR_RXCH7EN_MASK (0x00000080u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT (0x00000007u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH7EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH6EN_MASK (0x00000040u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT (0x00000006u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH6EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH5EN_MASK (0x00000020u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT (0x00000005u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH5EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH4EN_MASK (0x00000010u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT (0x00000004u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH4EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH3EN_MASK (0x00000008u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT (0x00000003u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH3EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH2EN_MASK (0x00000004u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT (0x00000002u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH2EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH1EN_MASK (0x00000002u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT (0x00000001u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH1EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH0EN_MASK (0x00000001u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RXCH0EN_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNICASTCLEAR_RESETVAL (0x00000000u)
/* RXMAXLEN */
#define CSL_EMAC_RXMAXLEN_RXMAXLEN_MASK (0x0000FFFFu)
#define CSL_EMAC_RXMAXLEN_RXMAXLEN_SHIFT (0x00000000u)
#define CSL_EMAC_RXMAXLEN_RXMAXLEN_RESETVAL (0x000005EEu)
#define CSL_EMAC_RXMAXLEN_RESETVAL (0x000005EEu)
/* RXBUFFEROFFSET */
#define CSL_EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_MASK (0x0000FFFFu)
#define CSL_EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT (0x00000000u)
#define CSL_EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_RESETVAL (0x00000000u)
#define CSL_EMAC_RXBUFFEROFFSET_RESETVAL (0x00000000u)
/* RXFILTERLOWTHRESH */
#define CSL_EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RXFILTERLOWTHRESH_RESETVAL (0x00000000u)
/* RX0FLOWTHRESH */
#define CSL_EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RX0FLOWTHRESH_RESETVAL (0x00000000u)
/* RX1FLOWTHRESH */
#define CSL_EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RX1FLOWTHRESH_RESETVAL (0x00000000u)
/* RX2FLOWTHRESH */
#define CSL_EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RX2FLOWTHRESH_RESETVAL (0x00000000u)
/* RX3FLOWTHRESH */
#define CSL_EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RX3FLOWTHRESH_RESETVAL (0x00000000u)
/* RX4FLOWTHRESH */
#define CSL_EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RX4FLOWTHRESH_RESETVAL (0x00000000u)
/* RX5FLOWTHRESH */
#define CSL_EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RX5FLOWTHRESH_RESETVAL (0x00000000u)
/* RX6FLOWTHRESH */
#define CSL_EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RX6FLOWTHRESH_RESETVAL (0x00000000u)
/* RX7FLOWTHRESH */
#define CSL_EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_MASK (0x000000FFu)
#define CSL_EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_RESETVAL (0x00000000u)
#define CSL_EMAC_RX7FLOWTHRESH_RESETVAL (0x00000000u)
/* RX0FREEBUFFER */
#define CSL_EMAC_RX0FREEBUFFER_RX0FREEBUF_MASK (0x0000FFFFu)
#define CSL_EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT (0x00000000u)
#define CSL_EMAC_RX0FREEBUFFER_RX0FREEBUF_RESETVAL (0x00000000u)
#define CSL_EMAC_RX0FREEBUFFER_RESETVAL (0x00000000u)
/* RX1FREEBUFFER */
#define CSL_EMAC_RX1FREEBUFFER_RX1FREEBUF_MASK (0x0000FFFFu)
#define CSL_EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT (0x00000000u)
#define CSL_EMAC_RX1FREEBUFFER_RX1FREEBUF_RESETVAL (0x00000000u)
#define CSL_EMAC_RX1FREEBUFFER_RESETVAL (0x00000000u)
/* RX2FREEBUFFER */
#define CSL_EMAC_RX2FREEBUFFER_RX2FREEBUF_MASK (0x0000FFFFu)
#define CSL_EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT (0x00000000u)
#define CSL_EMAC_RX2FREEBUFFER_RX2FREEBUF_RESETVAL (0x00000000u)
#define CSL_EMAC_RX2FREEBUFFER_RESETVAL (0x00000000u)
/* RX3FREEBUFFER */
#define CSL_EMAC_RX3FREEBUFFER_RX3FREEBUF_MASK (0x0000FFFFu)
#define CSL_EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT (0x00000000u)
#define CSL_EMAC_RX3FREEBUFFER_RX3FREEBUF_RESETVAL (0x00000000u)
#define CSL_EMAC_RX3FREEBUFFER_RESETVAL (0x00000000u)
/* RX4FREEBUFFER */
#define CSL_EMAC_RX4FREEBUFFER_RX4FREEBUF_MASK (0x0000FFFFu)
#define CSL_EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT (0x00000000u)
#define CSL_EMAC_RX4FREEBUFFER_RX4FREEBUF_RESETVAL (0x00000000u)
#define CSL_EMAC_RX4FREEBUFFER_RESETVAL (0x00000000u)
/* RX5FREEBUFFER */
#define CSL_EMAC_RX5FREEBUFFER_RX5FREEBUF_MASK (0x0000FFFFu)
#define CSL_EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT (0x00000000u)
#define CSL_EMAC_RX5FREEBUFFER_RX5FREEBUF_RESETVAL (0x00000000u)
#define CSL_EMAC_RX5FREEBUFFER_RESETVAL (0x00000000u)
/* RX6FREEBUFFER */
#define CSL_EMAC_RX6FREEBUFFER_RX6FREEBUF_MASK (0x0000FFFFu)
#define CSL_EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT (0x00000000u)
#define CSL_EMAC_RX6FREEBUFFER_RX6FREEBUF_RESETVAL (0x00000000u)
#define CSL_EMAC_RX6FREEBUFFER_RESETVAL (0x00000000u)
/* RX7FREEBUFFER */
#define CSL_EMAC_RX7FREEBUFFER_RX7FREEBUF_MASK (0x0000FFFFu)
#define CSL_EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT (0x00000000u)
#define CSL_EMAC_RX7FREEBUFFER_RX7FREEBUF_RESETVAL (0x00000000u)
#define CSL_EMAC_RX7FREEBUFFER_RESETVAL (0x00000000u)
/* MACCONTROL */
#define CSL_EMAC_MACCONTROL_RGMIIEN_MASK (0x00040000u)
#define CSL_EMAC_MACCONTROL_RGMIIEN_SHIFT (0x00000012u)
#define CSL_EMAC_MACCONTROL_RGMIIEN_RESETVAL (0x00000000u)
/*----RGMIIEN Tokens----*/
#define CSL_EMAC_MACCONTROL_RGMIIEN_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_RGMIIEN_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_GIGFORCE_MASK (0x00020000u)
#define CSL_EMAC_MACCONTROL_GIGFORCE_SHIFT (0x00000011u)
#define CSL_EMAC_MACCONTROL_GIGFORCE_RESETVAL (0x00000000u)
#define CSL_EMAC_MACCONTROL_RMIIDUPLEXMODE_MASK (0x00010000u)
#define CSL_EMAC_MACCONTROL_RMIIDUPLEXMODE_SHIFT (0x00000010u)
#define CSL_EMAC_MACCONTROL_RMIIDUPLEXMODE_RESETVAL (0x00000000u)
/*----RMIIDUPLEXMODE Tokens----*/
#define CSL_EMAC_MACCONTROL_RMIIDUPLEXMODE_HALFDUPLEX (0x00000000u)
#define CSL_EMAC_MACCONTROL_RMIIDUPLEXMODE_FULLDUPLEX (0x00000001u)
#define CSL_EMAC_MACCONTROL_RMIISPEED_MASK (0x00008000u)
#define CSL_EMAC_MACCONTROL_RMIISPEED_SHIFT (0x0000000Fu)
#define CSL_EMAC_MACCONTROL_RMIISPEED_RESETVAL (0x00000000u)
/*----RMIISPEED Tokens----*/
#define CSL_EMAC_MACCONTROL_RMIISPEED_2_5MHZ (0x00000000u)
#define CSL_EMAC_MACCONTROL_RMIISPEED_25MHZ (0x00000001u)
#define CSL_EMAC_MACCONTROL_RXOFFLENBLOCK_MASK (0x00004000u)
#define CSL_EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT (0x0000000Eu)
#define CSL_EMAC_MACCONTROL_RXOFFLENBLOCK_RESETVAL (0x00000000u)
/*----RXOFFLENBLOCK Tokens----*/
#define CSL_EMAC_MACCONTROL_RXOFFLENBLOCK_NOBLOCK (0x00000000u)
#define CSL_EMAC_MACCONTROL_RXOFFLENBLOCK_BLOCK (0x00000001u)
#define CSL_EMAC_MACCONTROL_RXOWNERSHIP_MASK (0x00002000u)
#define CSL_EMAC_MACCONTROL_RXOWNERSHIP_SHIFT (0x0000000Du)
#define CSL_EMAC_MACCONTROL_RXOWNERSHIP_RESETVAL (0x00000000u)
/*----RXOWNERSHIP Tokens----*/
#define CSL_EMAC_MACCONTROL_RXOWNERSHIP_ZERO (0x00000000u)
#define CSL_EMAC_MACCONTROL_RXOWNERSHIP_ONE (0x00000001u)
#define CSL_EMAC_MACCONTROL_RXFIFOFLOWEN_MASK (0x00001000u)
#define CSL_EMAC_MACCONTROL_RXFIFOFLOWEN_SHIFT (0x0000000Cu)
#define CSL_EMAC_MACCONTROL_RXFIFOFLOWEN_RESETVAL (0x00000000u)
/*----RXFIFOFLOWEN Tokens----*/
#define CSL_EMAC_MACCONTROL_RXFIFOFLOWEN_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_RXFIFOFLOWEN_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_CMDIDLE_MASK (0x00000800u)
#define CSL_EMAC_MACCONTROL_CMDIDLE_SHIFT (0x0000000Bu)
#define CSL_EMAC_MACCONTROL_CMDIDLE_RESETVAL (0x00000000u)
/*----CMDIDLE Tokens----*/
#define CSL_EMAC_MACCONTROL_CMDIDLE_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_CMDIDLE_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_TXPTYPE_MASK (0x00000200u)
#define CSL_EMAC_MACCONTROL_TXPTYPE_SHIFT (0x00000009u)
#define CSL_EMAC_MACCONTROL_TXPTYPE_RESETVAL (0x00000000u)
#define CSL_EMAC_MACCONTROL_TXSHORTGAPEN_MASK (0x00000400u)
#define CSL_EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT (0x0000000Au)
#define CSL_EMAC_MACCONTROL_TXSHORTGAPEN_RESETVAL (0x00000000u)
/*----SHORTGAP Tokens----*/
#define CSL_EMAC_MACCONTROL_TXSHORTGAPEN_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_TXSHORTGAPEN_ENABLE (0x00000001u)
/*----TXPTYPE Tokens----*/
#define CSL_EMAC_MACCONTROL_TXPTYPE_RROBIN (0x00000000u)
#define CSL_EMAC_MACCONTROL_TXPTYPE_CHANNELPRI (0x00000001u)
#define CSL_EMAC_MACCONTROL_GIG_MASK (0x00000080u)
#define CSL_EMAC_MACCONTROL_GIG_SHIFT (0x00000007u)
#define CSL_EMAC_MACCONTROL_GIG_RESETVAL (0x00000000u)
/*----GIG Tokens----*/
#define CSL_EMAC_MACCONTROL_GIG_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_GIG_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_TXPACE_MASK (0x00000040u)
#define CSL_EMAC_MACCONTROL_TXPACE_SHIFT (0x00000006u)
#define CSL_EMAC_MACCONTROL_TXPACE_RESETVAL (0x00000000u)
/*----TXPACE Tokens----*/
#define CSL_EMAC_MACCONTROL_TXPACE_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_TXPACE_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_GMIIEN_MASK (0x00000020u)
#define CSL_EMAC_MACCONTROL_GMIIEN_SHIFT (0x00000005u)
#define CSL_EMAC_MACCONTROL_GMIIEN_RESETVAL (0x00000000u)
/*----GMIIEN Tokens----*/
#define CSL_EMAC_MACCONTROL_GMIIEN_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_GMIIEN_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_TXFLOWEN_MASK (0x00000010u)
#define CSL_EMAC_MACCONTROL_TXFLOWEN_SHIFT (0x00000004u)
#define CSL_EMAC_MACCONTROL_TXFLOWEN_RESETVAL (0x00000000u)
/*----TXFLOWEN Tokens----*/
#define CSL_EMAC_MACCONTROL_TXFLOWEN_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_TXFLOWEN_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_RXBUFFERFLOWEN_MASK (0x00000008u)
#define CSL_EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT (0x00000003u)
#define CSL_EMAC_MACCONTROL_RXBUFFERFLOWEN_RESETVAL (0x00000000u)
/*----RXBUFFERFLOWEN Tokens----*/
#define CSL_EMAC_MACCONTROL_RXBUFFERFLOWEN_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_RXBUFFERFLOWEN_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_LOOPBACK_MASK (0x00000002u)
#define CSL_EMAC_MACCONTROL_LOOPBACK_SHIFT (0x00000001u)
#define CSL_EMAC_MACCONTROL_LOOPBACK_RESETVAL (0x00000000u)
/*----LOOPBACK Tokens----*/
#define CSL_EMAC_MACCONTROL_LOOPBACK_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_LOOPBACK_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_FULLDUPLEX_MASK (0x00000001u)
#define CSL_EMAC_MACCONTROL_FULLDUPLEX_SHIFT (0x00000000u)
#define CSL_EMAC_MACCONTROL_FULLDUPLEX_RESETVAL (0x00000000u)
/*----FULLDUPLEX Tokens----*/
#define CSL_EMAC_MACCONTROL_FULLDUPLEX_DISABLE (0x00000000u)
#define CSL_EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x00000001u)
#define CSL_EMAC_MACCONTROL_RESETVAL (0x00000000u)
/* MACSTATUS */
#define CSL_EMAC_MACSTATUS_IDLE_MASK (0x80000000u)
#define CSL_EMAC_MACSTATUS_IDLE_SHIFT (0x0000001Fu)
#define CSL_EMAC_MACSTATUS_IDLE_RESETVAL (0x00000000u)
/*----IDLE Tokens----*/
#define CSL_EMAC_MACSTATUS_IDLE_NOIDLE (0x00000000u)
#define CSL_EMAC_MACSTATUS_IDLE_IDLE (0x00000001u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_MASK (0x00F00000u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_SHIFT (0x00000014u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_RESETVAL (0x00000000u)
/*----TXERRCODE Tokens----*/
#define CSL_EMAC_MACSTATUS_TXERRCODE_NOERROR (0x00000000u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_SOPERROR (0x00000001u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_OWNERSHIP (0x00000002u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_NOEOP (0x00000003u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_NULLPTR (0x00000004u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_NULLEN (0x00000005u)
#define CSL_EMAC_MACSTATUS_TXERRCODE_LENRRROR (0x00000006u)
#define CSL_EMAC_MACSTATUS_TXERRCH_MASK (0x00070000u)
#define CSL_EMAC_MACSTATUS_TXERRCH_SHIFT (0x00000010u)
#define CSL_EMAC_MACSTATUS_TXERRCH_RESETVAL (0x00000000u)
/*----TXERRCH Tokens----*/
#define CSL_EMAC_MACSTATUS_TXERRCH_CHA0 (0x00000000u)
#define CSL_EMAC_MACSTATUS_TXERRCH_CHA1 (0x00000001u)
#define CSL_EMAC_MACSTATUS_TXERRCH_CHA2 (0x00000002u)
#define CSL_EMAC_MACSTATUS_TXERRCH_CHA3 (0x00000003u)
#define CSL_EMAC_MACSTATUS_TXERRCH_CHA4 (0x00000004u)
#define CSL_EMAC_MACSTATUS_TXERRCH_CHA5 (0x00000005u)
#define CSL_EMAC_MACSTATUS_TXERRCH_CHA6 (0x00000006u)
#define CSL_EMAC_MACSTATUS_TXERRCH_CHA7 (0x00000007u)
#define CSL_EMAC_MACSTATUS_RXERRCODE_MASK (0x0000F000u)
#define CSL_EMAC_MACSTATUS_RXERRCODE_SHIFT (0x0000000Cu)
#define CSL_EMAC_MACSTATUS_RXERRCODE_RESETVAL (0x00000000u)
/*----RXERRCODE Tokens----*/
#define CSL_EMAC_MACSTATUS_RXERRCODE_NOERROR (0x00000000u)
#define CSL_EMAC_MACSTATUS_RXERRCODE_OWNERSHIP (0x00000002u)
#define CSL_EMAC_MACSTATUS_RXERRCODE_NULLPTR (0x00000004u)
#define CSL_EMAC_MACSTATUS_RXERRCH_MASK (0x00000700u)
#define CSL_EMAC_MACSTATUS_RXERRCH_SHIFT (0x00000008u)
#define CSL_EMAC_MACSTATUS_RXERRCH_RESETVAL (0x00000000u)
/*----RXERRCH Tokens----*/
#define CSL_EMAC_MACSTATUS_RXERRCH_CHA0 (0x00000000u)
#define CSL_EMAC_MACSTATUS_RXERRCH_CHA1 (0x00000001u)
#define CSL_EMAC_MACSTATUS_RXERRCH_CHA2 (0x00000002u)
#define CSL_EMAC_MACSTATUS_RXERRCH_CHA3 (0x00000003u)
#define CSL_EMAC_MACSTATUS_RXERRCH_CHA4 (0x00000004u)
#define CSL_EMAC_MACSTATUS_RXERRCH_CHA5 (0x00000005u)
#define CSL_EMAC_MACSTATUS_RXERRCH_CHA6 (0x00000006u)
#define CSL_EMAC_MACSTATUS_RXERRCH_CHA7 (0x00000007u)
#define CSL_EMAC_MACSTATUS_RGMIIGIG_MASK (0x00000010u)
#define CSL_EMAC_MACSTATUS_RGMIIGIG_SHIFT (0x00000004u)
#define CSL_EMAC_MACSTATUS_RGMIIGIG_RESETVAL (0x00000000u)
#define CSL_EMAC_MACSTATUS_RGMIIFULLDUPLEX_MASK (0x00000008u)
#define CSL_EMAC_MACSTATUS_RGMIIFULLDUPLEX_SHIFT (0x00000003u)
#define CSL_EMAC_MACSTATUS_RGMIIFULLDUPLEX_RESETVAL (0x00000000u)
#define CSL_EMAC_MACSTATUS_RXQOSACT_MASK (0x00000004u)
#define CSL_EMAC_MACSTATUS_RXQOSACT_SHIFT (0x00000002u)
#define CSL_EMAC_MACSTATUS_RXQOSACT_RESETVAL (0x00000000u)
/*----RXQOSACT Tokens----*/
#define CSL_EMAC_MACSTATUS_RXQOSACT_DISABLE (0x00000000u)
#define CSL_EMAC_MACSTATUS_RXQOSACT_ENABLE (0x00000001u)
#define CSL_EMAC_MACSTATUS_RXFLOWACT_MASK (0x00000002u)
#define CSL_EMAC_MACSTATUS_RXFLOWACT_SHIFT (0x00000001u)
#define CSL_EMAC_MACSTATUS_RXFLOWACT_RESETVAL (0x00000000u)
/*----RXFLOWACT Tokens----*/
#define CSL_EMAC_MACSTATUS_RXFLOWACT_INACTIVE (0x00000000u)
#define CSL_EMAC_MACSTATUS_RXFLOWACT_ACTIVE (0x00000001u)
#define CSL_EMAC_MACSTATUS_TXFLOWACT_MASK (0x00000001u)
#define CSL_EMAC_MACSTATUS_TXFLOWACT_SHIFT (0x00000000u)
#define CSL_EMAC_MACSTATUS_TXFLOWACT_RESETVAL (0x00000000u)
/*----TXFLOWACT Tokens----*/
#define CSL_EMAC_MACSTATUS_TXFLOWACT_INACTIVE (0x00000000u)
#define CSL_EMAC_MACSTATUS_TXFLOWACT_ACTIVE (0x00000001u)
#define CSL_EMAC_MACSTATUS_RESETVAL (0x00000000u)
/* EMCONTROL */
#define CSL_EMAC_EMCONTROL_SOFT_MASK (0x00000002u)
#define CSL_EMAC_EMCONTROL_SOFT_SHIFT (0x00000001u)
#define CSL_EMAC_EMCONTROL_SOFT_RESETVAL (0x00000000u)
#define CSL_EMAC_EMCONTROL_FREE_MASK (0x00000001u)
#define CSL_EMAC_EMCONTROL_FREE_SHIFT (0x00000000u)
#define CSL_EMAC_EMCONTROL_FREE_RESETVAL (0x00000000u)
#define CSL_EMAC_EMCONTROL_RESETVAL (0x00000000u)
/* FIFOCONTROL */
#define CSL_EMAC_FIFOCONTROL_RXFIFOFLOWTHRESH_MASK (0x007F0000u)
#define CSL_EMAC_FIFOCONTROL_RXFIFOFLOWTHRESH_SHIFT (0x00000010u)
#define CSL_EMAC_FIFOCONTROL_RXFIFOFLOWTHRESH_RESETVAL (0x00000002u)
#define CSL_EMAC_FIFOCONTROL_TXCELLTHRESH_MASK (0x0000001Fu)
#define CSL_EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT (0x00000000u)
#define CSL_EMAC_FIFOCONTROL_TXCELLTHRESH_RESETVAL (0x00000018u)
#define CSL_EMAC_FIFOCONTROL_RESETVAL (0x00020018u)
/* MACCONFIG */
#define CSL_EMAC_MACCONFIG_TXCELLDEPTH_MASK (0xFF000000u)
#define CSL_EMAC_MACCONFIG_TXCELLDEPTH_SHIFT (0x00000018u)
#define CSL_EMAC_MACCONFIG_TXCELLDEPTH_RESETVAL (0x00000018u)
#define CSL_EMAC_MACCONFIG_RXCELLDEPTH_MASK (0x00FF0000u)
#define CSL_EMAC_MACCONFIG_RXCELLDEPTH_SHIFT (0x00000010u)
#define CSL_EMAC_MACCONFIG_RXCELLDEPTH_RESETVAL (0x00000044u)
#define CSL_EMAC_MACCONFIG_ADDRESSTYPE_MASK (0x0000FF00u)
#define CSL_EMAC_MACCONFIG_ADDRESSTYPE_SHIFT (0x00000008u)
#define CSL_EMAC_MACCONFIG_ADDRESSTYPE_RESETVAL (0x00000002u)
#define CSL_EMAC_MACCONFIG_MACCFIG_MASK (0x000000FFu)
#define CSL_EMAC_MACCONFIG_MACCFIG_SHIFT (0x00000000u)
#define CSL_EMAC_MACCONFIG_MACCFIG_RESETVAL (0x00000003u)
#define CSL_EMAC_MACCONFIG_RESETVAL (0x18440203u)
/* SOFTRESET */
#define CSL_EMAC_SOFTRESET_SOFTRESET_MASK (0x00000001u)
#define CSL_EMAC_SOFTRESET_SOFTRESET_SHIFT (0x00000000u)
#define CSL_EMAC_SOFTRESET_SOFTRESET_RESETVAL (0x00000000u)
/*----SOFTRESET Tokens----*/
#define CSL_EMAC_SOFTRESET_SOFTRESET_NORESET (0x00000000u)
#define CSL_EMAC_SOFTRESET_SOFTRESET_RESET (0x00000001u)
#define CSL_EMAC_SOFTRESET_RESETVAL (0x00000000u)
/* MACSRCADDRLO */
#define CSL_EMAC_MACSRCADDRLO_MACSRCADDR0_MASK (0x0000FF00u)
#define CSL_EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT (0x00000008u)
#define CSL_EMAC_MACSRCADDRLO_MACSRCADDR0_RESETVAL (0x00000000u)
#define CSL_EMAC_MACSRCADDRLO_MACSRCADDR1_MASK (0x000000FFu)
#define CSL_EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT (0x00000000u)
#define CSL_EMAC_MACSRCADDRLO_MACSRCADDR1_RESETVAL (0x00000000u)
#define CSL_EMAC_MACSRCADDRLO_RESETVAL (0x00000000u)
/* MACSRCADDRHI */
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR2_MASK (0xFF000000u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT (0x00000018u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR2_RESETVAL (0x00000000u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR3_MASK (0x00FF0000u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT (0x00000010u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR3_RESETVAL (0x00000000u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR4_MASK (0x0000FF00u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT (0x00000008u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR4_RESETVAL (0x00000000u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR5_MASK (0x000000FFu)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT (0x00000000u)
#define CSL_EMAC_MACSRCADDRHI_MACSRCADDR5_RESETVAL (0x00000000u)
#define CSL_EMAC_MACSRCADDRHI_RESETVAL (0x00000000u)
/* MACHASH1 */
#define CSL_EMAC_MACHASH1_MACHASH1_MASK (0xFFFFFFFFu)
#define CSL_EMAC_MACHASH1_MACHASH1_SHIFT (0x00000000u)
#define CSL_EMAC_MACHASH1_MACHASH1_RESETVAL (0x00000000u)
#define CSL_EMAC_MACHASH1_RESETVAL (0x00000000u)
/* MACHASH2 */
#define CSL_EMAC_MACHASH2_MACHASH2_MASK (0xFFFFFFFFu)
#define CSL_EMAC_MACHASH2_MACHASH2_SHIFT (0x00000000u)
#define CSL_EMAC_MACHASH2_MACHASH2_RESETVAL (0x00000000u)
#define CSL_EMAC_MACHASH2_RESETVAL (0x00000000u)
/* BOFFTEST */
#define CSL_EMAC_BOFFTEST_RNDNUM_MASK (0x03FF0000u)
#define CSL_EMAC_BOFFTEST_RNDNUM_SHIFT (0x00000010u)
#define CSL_EMAC_BOFFTEST_RNDNUM_RESETVAL (0x00000000u)
#define CSL_EMAC_BOFFTEST_COLLCOUNT_MASK (0x0000F000u)
#define CSL_EMAC_BOFFTEST_COLLCOUNT_SHIFT (0x0000000Cu)
#define CSL_EMAC_BOFFTEST_COLLCOUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_BOFFTEST_TXBACKOFF_MASK (0x000003FFu)
#define CSL_EMAC_BOFFTEST_TXBACKOFF_SHIFT (0x00000000u)
#define CSL_EMAC_BOFFTEST_TXBACKOFF_RESETVAL (0x00000000u)
#define CSL_EMAC_BOFFTEST_RESETVAL (0x00000000u)
/* TPACETEST */
#define CSL_EMAC_TPACETEST_PACEVAL_MASK (0x0000001Fu)
#define CSL_EMAC_TPACETEST_PACEVAL_SHIFT (0x00000000u)
#define CSL_EMAC_TPACETEST_PACEVAL_RESETVAL (0x00000000u)
#define CSL_EMAC_TPACETEST_RESETVAL (0x00000000u)
/* RXPAUSE */
#define CSL_EMAC_RXPAUSE_PAUSETIMER_MASK (0x0000FFFFu)
#define CSL_EMAC_RXPAUSE_PAUSETIMER_SHIFT (0x00000000u)
#define CSL_EMAC_RXPAUSE_PAUSETIMER_RESETVAL (0x00000000u)
#define CSL_EMAC_RXPAUSE_RESETVAL (0x00000000u)
/* TXPAUSE */
#define CSL_EMAC_TXPAUSE_PAUSETIMER_MASK (0x0000FFFFu)
#define CSL_EMAC_TXPAUSE_PAUSETIMER_SHIFT (0x00000000u)
#define CSL_EMAC_TXPAUSE_PAUSETIMER_RESETVAL (0x00000000u)
#define CSL_EMAC_TXPAUSE_RESETVAL (0x00000000u)
/* RXGOODFRAMES */
#define CSL_EMAC_RXGOODFRAMES_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXGOODFRAMES_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXGOODFRAMES_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXGOODFRAMES_RESETVAL (0x00000000u)
/* RXBCASTFRAMES */
#define CSL_EMAC_RXBCASTFRAMES_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXBCASTFRAMES_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXBCASTFRAMES_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXBCASTFRAMES_RESETVAL (0x00000000u)
/* RXMCASTFRAMES */
#define CSL_EMAC_RXMCASTFRAMES_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXMCASTFRAMES_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXMCASTFRAMES_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXMCASTFRAMES_RESETVAL (0x00000000u)
/* RXPAUSEFRAMES */
#define CSL_EMAC_RXPAUSEFRAMES_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXPAUSEFRAMES_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXPAUSEFRAMES_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXPAUSEFRAMES_RESETVAL (0x00000000u)
/* RXCRCERRORS */
#define CSL_EMAC_RXCRCERRORS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXCRCERRORS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXCRCERRORS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXCRCERRORS_RESETVAL (0x00000000u)
/* RXALIGNCODEERRORS */
#define CSL_EMAC_RXALIGNCODEERRORS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXALIGNCODEERRORS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXALIGNCODEERRORS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXALIGNCODEERRORS_RESETVAL (0x00000000u)
/* RXOVERSIZED */
#define CSL_EMAC_RXOVERSIZED_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXOVERSIZED_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXOVERSIZED_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXOVERSIZED_RESETVAL (0x00000000u)
/* RXJABBER */
#define CSL_EMAC_RXJABBER_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXJABBER_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXJABBER_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXJABBER_RESETVAL (0x00000000u)
/* RXUNDERSIZED */
#define CSL_EMAC_RXUNDERSIZED_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXUNDERSIZED_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXUNDERSIZED_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXUNDERSIZED_RESETVAL (0x00000000u)
/* RXFRAGMENTS */
#define CSL_EMAC_RXFRAGMENTS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXFRAGMENTS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXFRAGMENTS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXFRAGMENTS_RESETVAL (0x00000000u)
/* RXFILTERED */
#define CSL_EMAC_RXFILTERED_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXFILTERED_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXFILTERED_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXFILTERED_RESETVAL (0x00000000u)
/* RXQOSFILTERED */
#define CSL_EMAC_RXQOSFILTERED_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXQOSFILTERED_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXQOSFILTERED_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXQOSFILTERED_RESETVAL (0x00000000u)
/* RXOCTETS */
#define CSL_EMAC_RXOCTETS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXOCTETS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXOCTETS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXOCTETS_RESETVAL (0x00000000u)
/* TXGOODFRAMES */
#define CSL_EMAC_TXGOODFRAMES_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXGOODFRAMES_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXGOODFRAMES_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXGOODFRAMES_RESETVAL (0x00000000u)
/* TXBCASTFRAMES */
#define CSL_EMAC_TXBCASTFRAMES_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXBCASTFRAMES_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXBCASTFRAMES_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXBCASTFRAMES_RESETVAL (0x00000000u)
/* TXMCASTFRAMES */
#define CSL_EMAC_TXMCASTFRAMES_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXMCASTFRAMES_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXMCASTFRAMES_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXMCASTFRAMES_RESETVAL (0x00000000u)
/* TXPAUSEFRAMES */
#define CSL_EMAC_TXPAUSEFRAMES_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXPAUSEFRAMES_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXPAUSEFRAMES_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXPAUSEFRAMES_RESETVAL (0x00000000u)
/* TXDEFERRED */
#define CSL_EMAC_TXDEFERRED_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXDEFERRED_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXDEFERRED_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXDEFERRED_RESETVAL (0x00000000u)
/* TXCOLLISION */
#define CSL_EMAC_TXCOLLISION_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXCOLLISION_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXCOLLISION_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXCOLLISION_RESETVAL (0x00000000u)
/* TXSINGLECOLL */
#define CSL_EMAC_TXSINGLECOLL_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXSINGLECOLL_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXSINGLECOLL_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXSINGLECOLL_RESETVAL (0x00000000u)
/* TXMULTICOLL */
#define CSL_EMAC_TXMULTICOLL_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXMULTICOLL_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXMULTICOLL_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXMULTICOLL_RESETVAL (0x00000000u)
/* TXEXCESSIVECOLL */
#define CSL_EMAC_TXEXCESSIVECOLL_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXEXCESSIVECOLL_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXEXCESSIVECOLL_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXEXCESSIVECOLL_RESETVAL (0x00000000u)
/* TXLATECOLL */
#define CSL_EMAC_TXLATECOLL_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXLATECOLL_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXLATECOLL_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXLATECOLL_RESETVAL (0x00000000u)
/* TXUNDERRUN */
#define CSL_EMAC_TXUNDERRUN_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXUNDERRUN_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXUNDERRUN_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXUNDERRUN_RESETVAL (0x00000000u)
/* TXCARRIERSENSE */
#define CSL_EMAC_TXCARRIERSENSE_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXCARRIERSENSE_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXCARRIERSENSE_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXCARRIERSENSE_RESETVAL (0x00000000u)
/* TXOCTETS */
#define CSL_EMAC_TXOCTETS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TXOCTETS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_TXOCTETS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_TXOCTETS_RESETVAL (0x00000000u)
/* FRAME64 */
#define CSL_EMAC_FRAME64_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_FRAME64_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_FRAME64_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_FRAME64_RESETVAL (0x00000000u)
/* FRAME65T127 */
#define CSL_EMAC_FRAME65T127_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_FRAME65T127_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_FRAME65T127_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_FRAME65T127_RESETVAL (0x00000000u)
/* FRAME128T255 */
#define CSL_EMAC_FRAME128T255_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_FRAME128T255_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_FRAME128T255_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_FRAME128T255_RESETVAL (0x00000000u)
/* FRAME256T511 */
#define CSL_EMAC_FRAME256T511_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_FRAME256T511_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_FRAME256T511_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_FRAME256T511_RESETVAL (0x00000000u)
/* FRAME512T1023 */
#define CSL_EMAC_FRAME512T1023_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_FRAME512T1023_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_FRAME512T1023_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_FRAME512T1023_RESETVAL (0x00000000u)
/* FRAME1024TUP */
#define CSL_EMAC_FRAME1024TUP_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_FRAME1024TUP_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_FRAME1024TUP_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_FRAME1024TUP_RESETVAL (0x00000000u)
/* NETOCTETS */
#define CSL_EMAC_NETOCTETS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_NETOCTETS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_NETOCTETS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_NETOCTETS_RESETVAL (0x00000000u)
/* RXSOFOVERRUNS */
#define CSL_EMAC_RXSOFOVERRUNS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXSOFOVERRUNS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXSOFOVERRUNS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXSOFOVERRUNS_RESETVAL (0x00000000u)
/* RXMOFOVERRUNS */
#define CSL_EMAC_RXMOFOVERRUNS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXMOFOVERRUNS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXMOFOVERRUNS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXMOFOVERRUNS_RESETVAL (0x00000000u)
/* RXDMAOVERRUNS */
#define CSL_EMAC_RXDMAOVERRUNS_COUNT_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RXDMAOVERRUNS_COUNT_SHIFT (0x00000000u)
#define CSL_EMAC_RXDMAOVERRUNS_COUNT_RESETVAL (0x00000000u)
#define CSL_EMAC_RXDMAOVERRUNS_RESETVAL (0x00000000u)
/* MACADDRLO */
#define CSL_EMAC_MACADDRLO_VALID_MASK (0x00100000u)
#define CSL_EMAC_MACADDRLO_VALID_SHIFT (0x00000014u)
#define CSL_EMAC_MACADDRLO_VALID_RESETVAL (0x00000000u)
/*----VALID Tokens----*/
#define CSL_EMAC_MACADDRLO_VALID_INVALID (0x00000000u)
#define CSL_EMAC_MACADDRLO_VALID_VALID (0x00000001u)
#define CSL_EMAC_MACADDRLO_MATCHFILT_MASK (0x00080000u)
#define CSL_EMAC_MACADDRLO_MATCHFILT_SHIFT (0x00000013u)
#define CSL_EMAC_MACADDRLO_MATCHFILT_RESETVAL (0x00000000u)
/*----MATCHFILT Tokens----*/
#define CSL_EMAC_MACADDRLO_MATCHFILT_FILTER (0x00000000u)
#define CSL_EMAC_MACADDRLO_MATCHFILT_MATCH (0x00000001u)
#define CSL_EMAC_MACADDRLO_CHANNEL_MASK (0x00070000u)
#define CSL_EMAC_MACADDRLO_CHANNEL_SHIFT (0x00000010u)
#define CSL_EMAC_MACADDRLO_CHANNEL_RESETVAL (0x00000000u)
#define CSL_EMAC_MACADDRLO_MACADDR0_MASK (0x0000FF00u)
#define CSL_EMAC_MACADDRLO_MACADDR0_SHIFT (0x00000008u)
#define CSL_EMAC_MACADDRLO_MACADDR0_RESETVAL (0x00000000u)
#define CSL_EMAC_MACADDRLO_MACADDR1_MASK (0x000000FFu)
#define CSL_EMAC_MACADDRLO_MACADDR1_SHIFT (0x00000000u)
#define CSL_EMAC_MACADDRLO_MACADDR1_RESETVAL (0x00000000u)
#define CSL_EMAC_MACADDRLO_RESETVAL (0x00000000u)
/* MACADDRHI */
#define CSL_EMAC_MACADDRHI_MACADDR2_MASK (0xFF000000u)
#define CSL_EMAC_MACADDRHI_MACADDR2_SHIFT (0x00000018u)
#define CSL_EMAC_MACADDRHI_MACADDR2_RESETVAL (0x00000000u)
#define CSL_EMAC_MACADDRHI_MACADDR3_MASK (0x00FF0000u)
#define CSL_EMAC_MACADDRHI_MACADDR3_SHIFT (0x00000010u)
#define CSL_EMAC_MACADDRHI_MACADDR3_RESETVAL (0x00000000u)
#define CSL_EMAC_MACADDRHI_MACADDR4_MASK (0x0000FF00u)
#define CSL_EMAC_MACADDRHI_MACADDR4_SHIFT (0x00000008u)
#define CSL_EMAC_MACADDRHI_MACADDR4_RESETVAL (0x00000000u)
#define CSL_EMAC_MACADDRHI_MACADDR5_MASK (0x000000FFu)
#define CSL_EMAC_MACADDRHI_MACADDR5_SHIFT (0x00000000u)
#define CSL_EMAC_MACADDRHI_MACADDR5_RESETVAL (0x00000000u)
#define CSL_EMAC_MACADDRHI_RESETVAL (0x00000000u)
/* MACINDEX */
#define CSL_EMAC_MACINDEX_MACINDEX_MASK (0x0000001Fu)
#define CSL_EMAC_MACINDEX_MACINDEX_SHIFT (0x00000000u)
#define CSL_EMAC_MACINDEX_MACINDEX_RESETVAL (0x00000000u)
#define CSL_EMAC_MACINDEX_RESETVAL (0x00000000u)
/* TX0HDP */
#define CSL_EMAC_TX0HDP_TX0HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX0HDP_TX0HDP_SHIFT (0x00000000u)
#define CSL_EMAC_TX0HDP_TX0HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX0HDP_RESETVAL (0x00000000u)
/* TX1HDP */
#define CSL_EMAC_TX1HDP_TX1HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX1HDP_TX1HDP_SHIFT (0x00000000u)
#define CSL_EMAC_TX1HDP_TX1HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX1HDP_RESETVAL (0x00000000u)
/* TX2HDP */
#define CSL_EMAC_TX2HDP_TX2HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX2HDP_TX2HDP_SHIFT (0x00000000u)
#define CSL_EMAC_TX2HDP_TX2HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX2HDP_RESETVAL (0x00000000u)
/* TX3HDP */
#define CSL_EMAC_TX3HDP_TX3HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX3HDP_TX3HDP_SHIFT (0x00000000u)
#define CSL_EMAC_TX3HDP_TX3HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX3HDP_RESETVAL (0x00000000u)
/* TX4HDP */
#define CSL_EMAC_TX4HDP_TX4HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX4HDP_TX4HDP_SHIFT (0x00000000u)
#define CSL_EMAC_TX4HDP_TX4HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX4HDP_RESETVAL (0x00000000u)
/* TX5HDP */
#define CSL_EMAC_TX5HDP_TX5HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX5HDP_TX5HDP_SHIFT (0x00000000u)
#define CSL_EMAC_TX5HDP_TX5HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX5HDP_RESETVAL (0x00000000u)
/* TX6HDP */
#define CSL_EMAC_TX6HDP_TX6HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX6HDP_TX6HDP_SHIFT (0x00000000u)
#define CSL_EMAC_TX6HDP_TX6HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX6HDP_RESETVAL (0x00000000u)
/* TX7HDP */
#define CSL_EMAC_TX7HDP_TX7HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX7HDP_TX7HDP_SHIFT (0x00000000u)
#define CSL_EMAC_TX7HDP_TX7HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX7HDP_RESETVAL (0x00000000u)
/* RX0HDP */
#define CSL_EMAC_RX0HDP_RX0HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX0HDP_RX0HDP_SHIFT (0x00000000u)
#define CSL_EMAC_RX0HDP_RX0HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX0HDP_RESETVAL (0x00000000u)
/* RX1HDP */
#define CSL_EMAC_RX1HDP_RX1HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX1HDP_RX1HDP_SHIFT (0x00000000u)
#define CSL_EMAC_RX1HDP_RX1HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX1HDP_RESETVAL (0x00000000u)
/* RX2HDP */
#define CSL_EMAC_RX2HDP_RX2HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX2HDP_RX2HDP_SHIFT (0x00000000u)
#define CSL_EMAC_RX2HDP_RX2HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX2HDP_RESETVAL (0x00000000u)
/* RX3HDP */
#define CSL_EMAC_RX3HDP_RX3HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX3HDP_RX3HDP_SHIFT (0x00000000u)
#define CSL_EMAC_RX3HDP_RX3HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX3HDP_RESETVAL (0x00000000u)
/* RX4HDP */
#define CSL_EMAC_RX4HDP_RX4HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX4HDP_RX4HDP_SHIFT (0x00000000u)
#define CSL_EMAC_RX4HDP_RX4HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX4HDP_RESETVAL (0x00000000u)
/* RX5HDP */
#define CSL_EMAC_RX5HDP_RX5HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX5HDP_RX5HDP_SHIFT (0x00000000u)
#define CSL_EMAC_RX5HDP_RX5HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX5HDP_RESETVAL (0x00000000u)
/* RX6HDP */
#define CSL_EMAC_RX6HDP_RX6HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX6HDP_RX6HDP_SHIFT (0x00000000u)
#define CSL_EMAC_RX6HDP_RX6HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX6HDP_RESETVAL (0x00000000u)
/* RX7HDP */
#define CSL_EMAC_RX7HDP_RX7HDP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX7HDP_RX7HDP_SHIFT (0x00000000u)
#define CSL_EMAC_RX7HDP_RX7HDP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX7HDP_RESETVAL (0x00000000u)
/* TX0CP */
#define CSL_EMAC_TX0CP_TX0CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX0CP_TX0CP_SHIFT (0x00000000u)
#define CSL_EMAC_TX0CP_TX0CP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX0CP_RESETVAL (0x00000000u)
/* TX1CP */
#define CSL_EMAC_TX1CP_TX1CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX1CP_TX1CP_SHIFT (0x00000000u)
#define CSL_EMAC_TX1CP_TX1CP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX1CP_RESETVAL (0x00000000u)
/* TX2CP */
#define CSL_EMAC_TX2CP_TX2CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX2CP_TX2CP_SHIFT (0x00000000u)
#define CSL_EMAC_TX2CP_TX2CP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX2CP_RESETVAL (0x00000000u)
/* TX3CP */
#define CSL_EMAC_TX3CP_TX3CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX3CP_TX3CP_SHIFT (0x00000000u)
#define CSL_EMAC_TX3CP_TX3CP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX3CP_RESETVAL (0x00000000u)
/* TX4CP */
#define CSL_EMAC_TX4CP_TX4CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX4CP_TX4CP_SHIFT (0x00000000u)
#define CSL_EMAC_TX4CP_TX4CP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX4CP_RESETVAL (0x00000000u)
/* TX5CP */
#define CSL_EMAC_TX5CP_TX5CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX5CP_TX5CP_SHIFT (0x00000000u)
#define CSL_EMAC_TX5CP_TX5CP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX5CP_RESETVAL (0x00000000u)
/* TX6CP */
#define CSL_EMAC_TX6CP_TX6CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX6CP_TX6CP_SHIFT (0x00000000u)
#define CSL_EMAC_TX6CP_TX6CP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX6CP_RESETVAL (0x00000000u)
/* TX7CP */
#define CSL_EMAC_TX7CP_TX7CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_TX7CP_TX7CP_SHIFT (0x00000000u)
#define CSL_EMAC_TX7CP_TX7CP_RESETVAL (0x00000000u)
#define CSL_EMAC_TX7CP_RESETVAL (0x00000000u)
/* RX0CP */
#define CSL_EMAC_RX0CP_RX0CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX0CP_RX0CP_SHIFT (0x00000000u)
#define CSL_EMAC_RX0CP_RX0CP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX0CP_RESETVAL (0x00000000u)
/* RX1CP */
#define CSL_EMAC_RX1CP_RX1CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX1CP_RX1CP_SHIFT (0x00000000u)
#define CSL_EMAC_RX1CP_RX1CP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX1CP_RESETVAL (0x00000000u)
/* RX2CP */
#define CSL_EMAC_RX2CP_RX2CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX2CP_RX2CP_SHIFT (0x00000000u)
#define CSL_EMAC_RX2CP_RX2CP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX2CP_RESETVAL (0x00000000u)
/* RX3CP */
#define CSL_EMAC_RX3CP_RX3CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX3CP_RX3CP_SHIFT (0x00000000u)
#define CSL_EMAC_RX3CP_RX3CP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX3CP_RESETVAL (0x00000000u)
/* RX4CP */
#define CSL_EMAC_RX4CP_RX4CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX4CP_RX4CP_SHIFT (0x00000000u)
#define CSL_EMAC_RX4CP_RX4CP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX4CP_RESETVAL (0x00000000u)
/* RX5CP */
#define CSL_EMAC_RX5CP_RX5CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX5CP_RX5CP_SHIFT (0x00000000u)
#define CSL_EMAC_RX5CP_RX5CP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX5CP_RESETVAL (0x00000000u)
/* RX6CP */
#define CSL_EMAC_RX6CP_RX6CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX6CP_RX6CP_SHIFT (0x00000000u)
#define CSL_EMAC_RX6CP_RX6CP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX6CP_RESETVAL (0x00000000u)
/* RX7CP */
#define CSL_EMAC_RX7CP_RX7CP_MASK (0xFFFFFFFFu)
#define CSL_EMAC_RX7CP_RX7CP_SHIFT (0x00000000u)
#define CSL_EMAC_RX7CP_RX7CP_RESETVAL (0x00000000u)
#define CSL_EMAC_RX7CP_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_tmr.h | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_tmr.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for TIMER
*/
#ifndef _CSLR_TMR_H_
#define _CSLR_TMR_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint8 RSVD0[4];
volatile Uint32 EMUMGT_CLKSPD;
volatile Uint8 RSVD1[8];
volatile Uint32 TIMLO;
volatile Uint32 TIMHI;
volatile Uint32 PRDLO;
volatile Uint32 PRDHI;
volatile Uint32 TCR;
volatile Uint32 TGCR;
volatile Uint32 WDTCR;
} CSL_TmrRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_TmrRegs *CSL_TmrRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* EMUMGT_CLKSPD */
#define CSL_TMR_EMUMGT_CLKSPD_CLKDIV_MASK (0x000F0000u)
#define CSL_TMR_EMUMGT_CLKSPD_CLKDIV_SHIFT (0x00000010u)
#define CSL_TMR_EMUMGT_CLKSPD_CLKDIV_RESETVAL (0x00000006u)
/*----CLKDIV Tokens----*/
#define CSL_TMR_EMUMGT_CLKSPD_CLKDIV_DIV0 (0x00000000u)
#define CSL_TMR_EMUMGT_CLKSPD_CLKDIV_DIV1 (0x00000001u)
#define CSL_TMR_EMUMGT_CLKSPD_CLKDIV_DIV2 (0x00000002u)
#define CSL_TMR_EMUMGT_CLKSPD_CLKDIV_DIV4 (0x00000004u)
#define CSL_TMR_EMUMGT_CLKSPD_CLKDIV_DIV8 (0x00000008u)
#define CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK (0x00000002u)
#define CSL_TMR_EMUMGT_CLKSPD_SOFT_SHIFT (0x00000001u)
#define CSL_TMR_EMUMGT_CLKSPD_SOFT_RESETVAL (0x00000000u)
#define CSL_TMR_EMUMGT_CLKSPD_FREE_MASK (0x00000001u)
#define CSL_TMR_EMUMGT_CLKSPD_FREE_SHIFT (0x00000000u)
#define CSL_TMR_EMUMGT_CLKSPD_FREE_RESETVAL (0x00000000u)
#define CSL_TMR_EMUMGT_CLKSPD_RESETVAL (0x00060000u)
/* TIMLO */
#define CSL_TMR_TIMLO_TIMLO_MASK (0xFFFFFFFFu)
#define CSL_TMR_TIMLO_TIMLO_SHIFT (0x00000000u)
#define CSL_TMR_TIMLO_TIMLO_RESETVAL (0x00000000u)
#define CSL_TMR_TIMLO_RESETVAL (0x00000000u)
/* TIMHI */
#define CSL_TMR_TIMHI_TIMHI_MASK (0xFFFFFFFFu)
#define CSL_TMR_TIMHI_TIMHI_SHIFT (0x00000000u)
#define CSL_TMR_TIMHI_TIMHI_RESETVAL (0x00000000u)
#define CSL_TMR_TIMHI_RESETVAL (0x00000000u)
/* PRDLO */
#define CSL_TMR_PRDLO_PRDLO_MASK (0xFFFFFFFFu)
#define CSL_TMR_PRDLO_PRDLO_SHIFT (0x00000000u)
#define CSL_TMR_PRDLO_PRDLO_RESETVAL (0x00000000u)
#define CSL_TMR_PRDLO_RESETVAL (0x00000000u)
/* PRDHI */
#define CSL_TMR_PRDHI_PRDHI_MASK (0xFFFFFFFFu)
#define CSL_TMR_PRDHI_PRDHI_SHIFT (0x00000000u)
#define CSL_TMR_PRDHI_PRDHI_RESETVAL (0x00000000u)
#define CSL_TMR_PRDHI_RESETVAL (0x00000000u)
/* TCR */
#define CSL_TMR_TCR_ENAMODE_HI_MASK (0x00C00000u)
#define CSL_TMR_TCR_ENAMODE_HI_SHIFT (0x00000016u)
#define CSL_TMR_TCR_ENAMODE_HI_RESETVAL (0x00000000u)
/*----ENAMODE_HI Tokens----*/
#define CSL_TMR_TCR_ENAMODE_HI_DISABLE (0x00000000u)
#define CSL_TMR_TCR_PWID_HI_MASK (0x00300000u)
#define CSL_TMR_TCR_PWID_HI_SHIFT (0x00000014u)
#define CSL_TMR_TCR_PWID_HI_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_CP_HI_MASK (0x00080000u)
#define CSL_TMR_TCR_CP_HI_SHIFT (0x00000013u)
#define CSL_TMR_TCR_CP_HI_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_INVOUTP_HI_MASK (0x00020000u)
#define CSL_TMR_TCR_INVOUTP_HI_SHIFT (0x00000011u)
#define CSL_TMR_TCR_INVOUTP_HI_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_TSTAT_HI_MASK (0x00010000u)
#define CSL_TMR_TCR_TSTAT_HI_SHIFT (0x00000010u)
#define CSL_TMR_TCR_TSTAT_HI_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_TIEN_LO_MASK (0x00000200u)
#define CSL_TMR_TCR_TIEN_LO_SHIFT (0x00000009u)
#define CSL_TMR_TCR_TIEN_LO_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_CLKSRC_LO_MASK (0x00000100u)
#define CSL_TMR_TCR_CLKSRC_LO_SHIFT (0x00000008u)
#define CSL_TMR_TCR_CLKSRC_LO_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_ENAMODE_LO_MASK (0x000000C0u)
#define CSL_TMR_TCR_ENAMODE_LO_SHIFT (0x00000006u)
#define CSL_TMR_TCR_ENAMODE_LO_RESETVAL (0x00000000u)
/*----ENAMODE_LO Tokens----*/
#define CSL_TMR_TCR_ENAMODE_LO_DISABLE (0x00000000u)
#define CSL_TMR_TCR_PWID_LO_MASK (0x00000030u)
#define CSL_TMR_TCR_PWID_LO_SHIFT (0x00000004u)
#define CSL_TMR_TCR_PWID_LO_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_CP_LO_MASK (0x00000008u)
#define CSL_TMR_TCR_CP_LO_SHIFT (0x00000003u)
#define CSL_TMR_TCR_CP_LO_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_INVINP_LO_MASK (0x00000004u)
#define CSL_TMR_TCR_INVINP_LO_SHIFT (0x00000002u)
#define CSL_TMR_TCR_INVINP_LO_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_INVOUTP_LO_MASK (0x00000002u)
#define CSL_TMR_TCR_INVOUTP_LO_SHIFT (0x00000001u)
#define CSL_TMR_TCR_INVOUTP_LO_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_TSTAT_LO_MASK (0x00000001u)
#define CSL_TMR_TCR_TSTAT_LO_SHIFT (0x00000000u)
#define CSL_TMR_TCR_TSTAT_LO_RESETVAL (0x00000000u)
#define CSL_TMR_TCR_RESETVAL (0x00000000u)
/* TGCR */
#define CSL_TMR_TGCR_TDDRHI_MASK (0x0000F000u)
#define CSL_TMR_TGCR_TDDRHI_SHIFT (0x0000000Cu)
#define CSL_TMR_TGCR_TDDRHI_RESETVAL (0x00000000u)
#define CSL_TMR_TGCR_PSCHI_MASK (0x00000F00u)
#define CSL_TMR_TGCR_PSCHI_SHIFT (0x00000008u)
#define CSL_TMR_TGCR_PSCHI_RESETVAL (0x00000000u)
#define CSL_TMR_TGCR_TIMMODE_MASK (0x0000000Cu)
#define CSL_TMR_TGCR_TIMMODE_SHIFT (0x00000002u)
#define CSL_TMR_TGCR_TIMMODE_RESETVAL (0x00000000u)
#define CSL_TMR_TGCR_TIMHIRS_MASK (0x00000002u)
#define CSL_TMR_TGCR_TIMHIRS_SHIFT (0x00000001u)
#define CSL_TMR_TGCR_TIMHIRS_RESETVAL (0x00000000u)
/*----TIMHIRS Tokens----*/
#define CSL_TMR_TGCR_TIMHIRS_RESET_ON (0x00000000u)
#define CSL_TMR_TGCR_TIMHIRS_RESET_OFF (0x00000001u)
#define CSL_TMR_TGCR_TIMLORS_MASK (0x00000001u)
#define CSL_TMR_TGCR_TIMLORS_SHIFT (0x00000000u)
#define CSL_TMR_TGCR_TIMLORS_RESETVAL (0x00000000u)
/*----TIMLORS Tokens----*/
#define CSL_TMR_TGCR_TIMLORS_RESET_ON (0x00000000u)
#define CSL_TMR_TGCR_TIMLORS_RESET_OFF (0x00000001u)
#define CSL_TMR_TGCR_RESETVAL (0x00000000u)
/* WDTCR */
#define CSL_TMR_WDTCR_WDKEY_MASK (0xFFFF0000u)
#define CSL_TMR_WDTCR_WDKEY_SHIFT (0x00000010u)
#define CSL_TMR_WDTCR_WDKEY_RESETVAL (0x00000000u)
/*----WDKEY Tokens----*/
#define CSL_TMR_WDTCR_WDKEY_CMD1 (0x0000A5C6u)
#define CSL_TMR_WDTCR_WDKEY_CMD2 (0x0000DA7Eu)
#define CSL_TMR_WDTCR_WDFLAG_MASK (0x00008000u)
#define CSL_TMR_WDTCR_WDFLAG_SHIFT (0x0000000Fu)
#define CSL_TMR_WDTCR_WDFLAG_RESETVAL (0x00000000u)
#define CSL_TMR_WDTCR_WDEN_MASK (0x00004000u)
#define CSL_TMR_WDTCR_WDEN_SHIFT (0x0000000Eu)
#define CSL_TMR_WDTCR_WDEN_RESETVAL (0x00000000u)
/*----WDEN Tokens----*/
#define CSL_TMR_WDTCR_WDEN_DISABLE (0x00000000u)
#define CSL_TMR_WDTCR_WDEN_ENABLE (0x00000001u)
#define CSL_TMR_WDTCR_WDIKEY_MASK (0x00003000u)
#define CSL_TMR_WDTCR_WDIKEY_SHIFT (0x0000000Cu)
#define CSL_TMR_WDTCR_WDIKEY_RESETVAL (0x00000000u)
#define CSL_TMR_WDTCR_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3Open.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3Open.c
*
* @path $(CSLPATH)\src\edma
*
* @desc File for functional layer of CSL API CSL_edma3Open ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* =============================================================================
*/
#include <csl_edma3.h>
/** ============================================================================
* @n@b CSL_edma3Open
*
* @b Description
* @n This function returns the handle to the edma instance. This handle is
* passed to all other CSL APIs.
*
* @b Arguments
* @verbatim
pEdmaObj EDMA Module Object pointer
edmaNum Instance of EDMA
pAttr EDMA Attribute pointer
pStatus Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_Edma3Handle
* @li Valid Edma handle will be returned if status value
* is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n The EDMA must be succesfully initialized via CSL_edma3Init() before
* calling this function.
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid EDMA handle is returned
* @li CSL_ESYS_FAIL The EDMA instance is invalid
* @li CSL_ESYS_INVPARAMS The Parameter passed is invalid
*
* 2. Edma object structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Edma object structure
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3Obj edmaObj;
CSL_Status status;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3Open, ".text:csl_section:edma3");
CSL_Edma3Handle CSL_edma3Open (
CSL_Edma3Obj *pEdmaObj,
CSL_InstNum edmaNum,
CSL_Edma3ModuleAttr *pAttr,
CSL_Status *pStatus
)
{
CSL_Edma3ModuleBaseAddress baseAddress;
CSL_Edma3Handle hEdma = (CSL_Edma3Handle)NULL;
if (pStatus == NULL) {
/* Do nothing : Module handle already initialised to NULL */
}
else if (pEdmaObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
*pStatus = CSL_edma3ccGetModuleBaseAddr(edmaNum, pAttr, &baseAddress);
if (*pStatus == CSL_SOK) {
pEdmaObj->regs = baseAddress.regs;
pEdmaObj->instNum = (CSL_InstNum)edmaNum;
hEdma = (CSL_Edma3Handle)pEdmaObj;
}
else {
pEdmaObj->regs = (CSL_Edma3ccRegsOvly)NULL;
pEdmaObj->instNum = (CSL_InstNum) -1;
}
}
return (hEdma);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/ddr2/ddr2_narrow_mode_read_write_example/src/Ddr2_narrow_mode_read_write_example.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
*
* @file Ddr2_narrow_mode_read_write_example.c
*
* @path $(CSLPATH)\example\ddr2\Ddr2_narrow_mode_read_write_example\src
*
* @desc Read write example of DDR2 in Narrow Mode.
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This example,
* 1. Enables clock to the DDR2 module
* 2. Initializes and opens the CSL DDR2 module instance.
* 3. Sets up the hardware to default values and narrow mode i.e.,
* CSL_ddr2HwSetup() is called for module configuration.
* 4. Writes the invalid values into DDR2 SDRAM area to over write the
* previous values.
* 5. Writes valid data
* 6. Does the data comparision to ensure the written data is proper or
* not and
* 7. Displays the messages based on step 6
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Ddr2_narrow_mode_read_write_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 21-May-2005 <NAME>. created
*
* 30-Nov-2005 NG Updated documentation
* =============================================================================
*/
#include <csl_ddr2.h>
#include <cslr_dev.h>
#include <stdio.h>
/* Success Flag for data comparision */
#define DATA_MATCH_SUCCESS 1
/* Fail Flag for data comparision */
#define DATA_MATCH_FAIL 0
/* Data count(number write/readbacks) */
#define DATA_CNT 10
#define EMIFB_CE0_BASE_ADDR (0xE0000000u)
#define SDRAM_REFRESH_RATE_DEFAULT (0x0000073Bu)
/* Handle for the DDR2 instance */
CSL_Ddr2Handle hDdr2;
void ddr2_readWrite(void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main (
void
)
{
/* Enable the ddr2 */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG1, DEV_PERCFG1_DDR2CTL,
ENABLE);
printf("Powersaver clock for DDR2 is enabled\n");
/* read_write functionality of DDR2 */
ddr2_readWrite();
return;
}
/*
* =============================================================================
* @func ddr2_readWrite
*
* @arg
* NONE
*
* @desc
* This function demonstrates the functionality of DDR2 EMIF with the setup
* It implements following steps
* 1. It opens the DDR2 module CSL
* 2. The CSL_ddr2HwSetup is called for module configuration
* 3. Enable 16 bit DDR2 SDRAM using CSL_ddr2HwSetup
* 4. It writes into SDRAM area and reads back, to make sure the data
* is indeed written.
* 5. Closes CSL DDR2 module.
*
* @return
* NONE
*
* =============================================================================
*/
void ddr2_readWrite (
void
)
{
volatile Uint32 result, index ;
Uint16 tempData;
CSL_Ddr2Obj ddr2Obj;
CSL_Status status;
CSL_Ddr2HwSetup hwSetup ;
CSL_Ddr2Timing1 tim1 = {0x23, 0x4,0x4, 0x4, 0x0B, 0x0F, 0x2,0x2};
CSL_Ddr2Timing2 tim2 = {0x2, 0x25, 0xDC, 0x2, 0x04};
CSL_Ddr2Settings set = CSL_DDR2_SETTING_DEFAULTS;
/* Pointer that points to SDRAM start area */
Uint16 *pDdr2Data = (Uint16 *)EMIFB_CE0_BASE_ADDR ;
/* Clear local data structures */
memset(&ddr2Obj, 0, sizeof(CSL_Ddr2Obj));
memset(&hwSetup, 0, sizeof(CSL_Ddr2HwSetup));
/* setup the hardware parameters */
hwSetup.refreshRate = SDRAM_REFRESH_RATE_DEFAULT;
hwSetup.timing1Param = &tim1;
hwSetup.timing2Param = &tim2;
set.narrowMode = CSL_DDR2_NARROW_MODE;
hwSetup.setParam = &set;
/* Initialize DDR2 CSL module */
status = CSL_ddr2Init(NULL);
if (status != CSL_SOK) {
printf("DDR2 EMIF: Initialization error.\n");
printf("\tReason: CSL_ddr2Init [status = 0x%x].\n", status);
return;
}
else {
printf("DDR2 EMIF: Module Initialized.\n");
}
/* Opening the DDR2 instance */
hDdr2 = CSL_ddr2Open(&ddr2Obj, CSL_DDR2, NULL, &status);
if ((status != CSL_SOK) || (hDdr2 == NULL)) {
printf("DDR2 EMIF: Error opening the instance. [status = 0x%x, hDdr2 = \
0x%x]\n", status, hDdr2);
return;
}
else {
printf("DDR2 EMIF: Module instance opened.\n");
}
/* Setting up configuration parameter using HwSetup */
status = CSL_ddr2HwSetup(hDdr2, &hwSetup);
if (status != CSL_SOK) {
printf("DDR2 EMIF: Error in HW Setup.\n");
printf("Read write operation fails\n");
return;
}
else {
printf("DDR2 EMIF: Module Hardware setup is successful.\n");
}
/* Write 'invalid' values into DDR2 SDRAM area. This is to overwrite the
* previous valid values
*/
tempData = 0xdead;
for (index = 0; index < DATA_CNT; index++) {
pDdr2Data[index] = tempData;
}
/* Write **valid** values into SDRAM area. */
tempData = 0x5678;
for (index = 0; index < DATA_CNT; index++) {
pDdr2Data[index] = tempData;
}
/* Verify that the data was indeed written */
result = DATA_MATCH_SUCCESS;
for (index = 0; index < DATA_CNT; index++) {
if (pDdr2Data[index] != tempData) {
result = DATA_MATCH_FAIL;
break ;
}
}
/* Print the appropriate message based on result */
if (result == DATA_MATCH_SUCCESS) {
printf("\nWrite to and Read from DDR2 SDRAM is Successful\n");
}
else {
printf("\nWrite to and Read from DDR2 SDRAM is NOT Successful\n");
printf("\tError in data read.[status = 0x%x]\n", status);
}
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiClose.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ===========================================================================
*/
/**
* @file csl_hpiClose.c
*
* @path $(CSLPATH)\src\hpi
*
* @brief File for functional layer of CSL API @a CSL_hpiClose()
*
*/
#include <csl_hpi.h>
/** ============================================================================
* @n@b CSL_hpiClose
*
* @b Description
* @n This function closes the specified instance of HPI.
*
* @b Arguments
* @verbatim
hHpi Handle to the HPI
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n The HPI instance should be opened before this close operation.
*
* <b> Post Condition </b>
* @n The HPI CSL APIs can not be called until the HPI CSL is reopened
* again using CSL_hpiOpen().
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_HpiHandle hHpi;
CSL_Status status;
...
status = CSL_hpiClose(hHpi);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_hpiClose, ".text:csl_section:hpi");
CSL_Status CSL_hpiClose (
CSL_HpiHandle hHpi
)
{
CSL_Status status = CSL_SOK;
if (hHpi != NULL) {
hHpi->regs = (CSL_HpiRegsOvly)NULL;
hHpi->hpiNum = (CSL_InstNum)-1;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/tcp2/csl_tcp2.c | <filename>DSP/TI-Header/csl_c6455_src/src/tcp2/csl_tcp2.c<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_tcp2.c
*
* @path $(CSLPATH)\src\tcp2
*
* @desc File for functional layer of CSL API of TCP2
*
*/
/* =============================================================================
* Revision History
* ===============
* 15-Mar-2005 sd File Created.
* 03-Aug-2005 sd Modifications for the requirements change.
* 15-Sep-2005 sd Changed TCP to TCP2 in all the names
* 07-Oct-2005 sd Changes during testing
* =============================================================================
*/
#include <csl_tcp2.h>
#include <csl_tcp2Aux.h>
/* defines */
/* TCP number of extrinsic factors */
#define NUM_EXTRINSIC_FACTORS 16
/* TCP data width */
#define DATA_WIDTH 6
/* forward declarations */
static void TCP2_calcSubBlocks (TCP2_Params *configParms);
/** ============================================================================
* @n@b TCP2_setParams
*
* @b Description
* @n This function sets up the TCP2 input configuration parameters in the
* TCP2_ConfigIc structure. The configuration values are passed in the
* configParms input argument.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
configIc Pointer to the TCP2_ConfigIc structure to be filled.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
TCP2_ConfigIc *configIc;
...
TCP2_setParams(configParms, configIc);
@endverbatim
* ===========================================================================
*/
void TCP2_setParams (
TCP2_Params *restrict configParms,
TCP2_ConfigIc *restrict configIc
)
{
/* IC0 parameters */
TCP2_Mode mode = configParms->mode;
TCP2_NumSW numSw = configParms->numSlideWin;
TCP2_Rate rate = configParms->rate;
Uint32 intFlag = configParms->intFlag;
Uint32 outParmFlag = configParms->outParmFlag;
Uint32 frameLen = configParms->frameLen;
/* IC1 parameters */
Uint32 relLen = configParms->relLen;
/* IC2 parameters */
Uint32 prologSize = configParms->prologSize;
Uint32 numSubBlock = configParms->numSubBlock;
Uint32 maxIter = configParms->maxIter;
Uint32 snr = configParms->snr;
/* IC3 parameters */
Bool maxStarEn = configParms->maxStarEn;
Bool prologRedEn = configParms->prologRedEn;
Uint8 minIter = configParms->minIter;
TCP2_InputSign inputSign = configParms->inputSign;
TCP2_OutputOrder outputOrder = configParms->outputOrder;
/* IC4 parameters */
Uint8 numCrcPass = configParms->numCrcPass;
Uint8 crcLen = configParms->crcLen;
/* IC5 parameters */
Uint32 crcPoly = configParms->crcPoly;
Uint32 ic0=0, ic1=0, ic2=0, ic3=0, ic4=0, ic5=0,
ic12=0, ic13=0, ic14=0, ic15=0;
Uint32 gie;
gie = _disable_interrupts ();
/* set the values for the TCPIC0 register */
CSL_FINS (ic0, TCP2_TCPIC0_FL, frameLen);
CSL_FINS (ic0, TCP2_TCPIC0_NUMSW, numSw);
CSL_FINS (ic0, TCP2_TCPIC0_OUTF, outParmFlag);
CSL_FINS (ic0, TCP2_TCPIC0_INTER, intFlag);
CSL_FINS (ic0, TCP2_TCPIC0_RATE, rate);
CSL_FINS (ic0, TCP2_TCPIC0_OPMOD, mode);
/* set the values for the TCPIC1 register */
CSL_FINS (ic1, TCP2_TCPIC1_R, relLen);
/* set the values for the TCPIC2 register */
CSL_FINS (ic2, TCP2_TCPIC2_SNR, snr);
CSL_FINS (ic2, TCP2_TCPIC2_MAXIT, maxIter);
CSL_FINS (ic2, TCP2_TCPIC2_NSB, numSubBlock);
CSL_FINS (ic2, TCP2_TCPIC2_P, prologSize);
/* set the values for the TCPIC3 register */
CSL_FINS (ic3, TCP2_TCPIC3_OUTORDER, outputOrder);
CSL_FINS (ic3, TCP2_TCPIC3_INPUTSIGN, inputSign);
CSL_FINS (ic3, TCP2_TCPIC3_MINITER, minIter);
CSL_FINS (ic3, TCP2_TCPIC3_EPRORED, prologRedEn);
CSL_FINS (ic3, TCP2_TCPIC3_EMAXSTR, maxStarEn);
/* set the values for the TCPIC4 register */
CSL_FINS (ic4, TCP2_TCPIC4_CRCITERPASS, numCrcPass);
CSL_FINS (ic4, TCP2_TCPIC4_CRCLEN, crcLen);
/* set the values for the TCPIC5 register */
CSL_FINS (ic5, TCP2_TCPIC5_CRCPOLY, crcPoly);
/* set the values for TCPIC12 to TCPIC15 */
/* Form the value for the register TCPIC12 */
ic12 = TCP2_setExtScaling (configParms->extrScaling [0],
configParms->extrScaling [1],
configParms->extrScaling [2],
configParms->extrScaling [3]);
/* Form the value for the register TCPIC13 */
ic13 = TCP2_setExtScaling (configParms->extrScaling [4],
configParms->extrScaling [5],
configParms->extrScaling [6],
configParms->extrScaling [7]);
/* Form the value for the register TCPIC14 */
ic14 = TCP2_setExtScaling (configParms->extrScaling [8],
configParms->extrScaling [9],
configParms->extrScaling [10],
configParms->extrScaling [11]);
/* Form the value for the register TCPIC15 */
ic15 = TCP2_setExtScaling (configParms->extrScaling [12],
configParms->extrScaling [13],
configParms->extrScaling [14],
configParms->extrScaling [15]);
/* Assign the configIc values */
configIc->ic0 = ic0;
configIc->ic1 = ic1;
configIc->ic2 = ic2;
configIc->ic3 = ic3;
configIc->ic4 = ic4;
configIc->ic5 = ic5;
configIc->ic12 = ic12;
configIc->ic13 = ic13;
configIc->ic14 = ic14;
configIc->ic15 = ic15;
_restore_interrupts (gie);
return;
} /* end TCP2_setParams */
/** ============================================================================
* @n@b TCP2_tailConfig
*
* @b Description
* @n This function generates the input control values IC6-IC11 based on the
* processing to be performed by the TCP. These values consist of the tail
* data following the systematics and parities data. This function
* calls specific tail generation functions depending on the
* standard followed.
*
* @b Arguments
@verbatim
standard 3G standard to be decoded.
mode TCP processing mode (SA or SP)
map TCP shared processing MAP
rate Code rate of the TCP
tailData Pointer to the tail data
configIc Pointer to the TCP_ConfigIc structure to be filled.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
TCP2_ConfigIc *configIc;
TCP2_UserData *xabData = &userData[frameLen];
...
TCP2_tailConfig (configParms->standard, configParms->mode,
configParms->map, configParms->rate,
userData, configIc);
@endverbatim
* ===========================================================================
*/
void TCP2_tailConfig (
TCP2_Standard standard,
TCP2_Mode mode,
TCP2_Map map,
TCP2_Rate rate,
TCP2_TailData *restrict tailData,
TCP2_ConfigIc *restrict configIc
)
{
/* Call the specific tail generation function */
if (standard == TCP2_STANDARD_3GPP)
TCP2_tailConfig3GPP ( mode, map, rate, tailData, configIc);
else
TCP2_tailConfigIs2000 (mode, map, rate, tailData, configIc);
return;
} /* end TCP2_tailConfig() */
/** ============================================================================
* @n@b TCP2_genIc
*
* @b Description
* @n This function sets up the TCP2 input configuration parameters in the
* TCP2_ConfigIc structure. The configuration values are passed in the
* configParms input argument.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
tailData Tail data
configIc Pointer to the TCP2_ConfigIc structure to be filled.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
extern TCP2_UserData *userData;
TCP2_BaseParams configBase;
TCP2_Params configParams;
TCP2_TailData *xabData;
Uint32 frameLen = 40;
xabData = &userData [frameLen];
// assign the configuration parameters
configBase.frameLen = frameLen;
configBase.inputSign = TCP2_INPUT_SIGN_POSITIVE;
configBase.intFlag = 1;
configBase.maxIter = 8;
configBase.maxStarEn = TRUE;
configBase.standard = TCP2_STANDARD_3GPP;
configBase.crcLen = 0;
configBase.crcPoly = 0;
configBase.minIter = 1;
configBase.numCrcPass = 1;
configBase.outParmFlag = 0;
configBase.outputOrder = TCP2_OUT_ORDER_0_31;
configBase.prologRedEn = FALSE;
configBase.prologSize = 24;
configBase.rate = TCP2_RATE_1_3;
configBase.snr = 0;
for (cnt = 0; cnt < 16; cnt++)
configBase.extrScaling [cnt] = 32;
// setup the TCP configuration registers parameters
TCP2_genParams (&configBase, &configParams);
// generate the configuration register values
TCP2_genIc (&configParams, xabData, &configIc);
@endverbatim
* ===========================================================================
*/
void TCP2_genIc (
TCP2_Params *restrict configParms,
TCP2_TailData *restrict tailData,
TCP2_ConfigIc *restrict configIc
)
{
TCP2_Standard standard = configParms->standard;
TCP2_Rate rate = configParms->rate;
TCP2_Mode mode = configParms->mode;
TCP2_Map map = configParms->map;
/* configuration parameters configuration */
TCP2_setParams (configParms, configIc);
/* TCP tail parameter configuration */
TCP2_tailConfig(standard, mode, map, rate, tailData, configIc);
return;
} /* end TCP2_genIc */
/** ============================================================================
* @n@b TCP2_genParams
*
* @b Description
* @n This function copies the basic parameters, to the configParams
* parameters structure.
*
* @b Arguments
@verbatim
configBase Pointer to the TCP2_BaseParams structure
configParams Pointer to the TCP configuration parameters
structure.
@endverbatim
*
* <b> Return Value </b> Uint32
* @n The number of sub frames for shared processing mode
*
* <b> Pre Condition </b>
* @n configBase is populated with all the configurtaion parameters
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configParams argument passed.
*
* @b Example
* @verbatim
extern TCP2_UserData *userData;
TCP2_BaseParams configBase;
TCP2_Params configParams;
TCP2_TailData *xabData;
Uint32 frameLen = 40;
xabData = &userData [frameLen];
// assign the configuration parameters
configBase.frameLen = frameLen;
configBase.inputSign = TCP2_INPUT_SIGN_POSITIVE;
configBase.intFlag = 1;
configBase.maxIter = 8;
configBase.maxStarEn = TRUE;
configBase.standard = TCP2_STANDARD_3GPP;
configBase.crcLen = 0;
configBase.crcPoly = 0;
configBase.minIter = 1;
configBase.numCrcPass = 1;
configBase.outParmFlag = 0;
configBase.outputOrder = TCP2_OUT_ORDER_0_31;
configBase.prologRedEn = FALSE;
configBase.prologSize = 24;
configBase.rate = TCP2_RATE_1_3;
configBase.snr = 0;
for (cnt = 0; cnt < 16; cnt++)
configBase.extrScaling [cnt] = 32;
// setup the TCP configuration registers parameters
TCP2_genParams (&configBase, &configParams);
@endverbatim
* ===========================================================================
*/
Uint32 TCP2_genParams (
TCP2_BaseParams *restrict configBase,
TCP2_Params *restrict configParams
)
{
Uint8 cnt;
Uint32 numSubFrames = 0;
Uint32 frameLen = configBase->frameLen;
/* Assign the configuration parameters */
configParams->standard = configBase->standard;
configParams->rate = configBase->rate;
configParams->intFlag = configBase->intFlag;
configParams->outParmFlag = configBase->outParmFlag;
configParams->prologSize = configBase->prologSize;
configParams->maxIter = configBase->maxIter;
configParams->snr = configBase->snr;
configParams->maxStarEn = configBase->maxStarEn;
configParams->prologRedEn = configBase->prologRedEn;
configParams->minIter = configBase->minIter;
configParams->inputSign = configBase->inputSign;
configParams->outputOrder = configBase->outputOrder;
configParams->numCrcPass = configBase->numCrcPass;
configParams->crcLen = configBase->crcLen;
configParams->crcPoly = configBase->crcPoly;
configParams->map = configBase->map;
for (cnt = 0; cnt < NUM_EXTRINSIC_FACTORS; cnt++)
configParams->extrScaling [cnt] = configBase->extrScaling [cnt];
/* calculate the sub blocks */
configParams->frameLen = frameLen;
if (frameLen <= TCP2_FLEN_MAX) {
/* Configure for Standalone processing */
/* to assign the frame length and mode */
configParams->mode = TCP2_MODE_SA;
/* Calculate the sub blocks, reliabilty length and
* num of sliding windows
*/
TCP2_calcSubBlocksSA (configParams);
}
else { /* Configure for Shared processing */
/*for shared processing assign the paramemters for the second
* configuration structure
*/
TCP2_Params *configParms2 = &configParams [1];
/* Assign the configuration parameters */
configParms2->standard = configBase->standard;
configParms2->rate = configBase->rate;
configParms2->intFlag = configBase->intFlag;
configParms2->outParmFlag = configBase->outParmFlag;
configParms2->prologSize = configBase->prologSize;
configParms2->maxIter = configBase->maxIter;
configParms2->snr = configBase->snr;
configParms2->maxStarEn = configBase->maxStarEn;
configParms2->prologRedEn = configBase->prologRedEn;
configParms2->minIter = configBase->minIter;
configParms2->inputSign = configBase->inputSign;
configParms2->outputOrder = configBase->outputOrder;
configParms2->numCrcPass = configBase->numCrcPass;
configParms2->crcLen = configBase->crcLen;
configParms2->crcPoly = configBase->crcPoly;
configParms2->map = configBase->map;
for (cnt = 0; cnt < NUM_EXTRINSIC_FACTORS; cnt++)
configParms2->extrScaling [cnt] = configBase->extrScaling [cnt];
/* Calculate the number of sub frames, sub blocks, reliabilty length
* and num of sliding windows
*/
numSubFrames = TCP2_calcSubBlocksSP (configParams);
}
return numSubFrames;
} /* end TCP2_genParams */
/** ============================================================================
* @n@b TCP2_calcSubBlocksSA
*
* @b Description
* @n This function calculates the number of sub blocks for the TCP
* standalone processing. The reliability length is also calculated and the
* configParms structure is populated.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configParms argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
...
TCP2_calcSubBlocksSA (configParms);
@endverbatim
* ===========================================================================
*/
void TCP2_calcSubBlocksSA (
TCP2_Params *configParms
)
{
/* calculate the sub blocks and other parameters */
TCP2_calcSubBlocks (configParms);
return;
} /* end TCP2_calcSubBlocksSA () */
/** ============================================================================
* @n@b TCP2_calcSubBlocksSP
*
* @b Description
* @n This function calculates the number of sub blocks for the TCP
* shared processing. The reliability length is also calculated and the
* configParms structure is populated.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
@endverbatim
*
* <b> Return Value </b> Uint32
* @n Number of sub frames the frame is divided into
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configParms argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
...
TCP2_calcSubBlocksSP (configParms);
@endverbatim
* ===========================================================================
*/
Uint32 TCP2_calcSubBlocksSP (
TCP2_Params *configParms
)
{
Uint16 numSubFrame;
Uint16 subFrameLen;
Uint16 subFrameLenLast;
TCP2_Params *configParams1 = &configParms [0];
TCP2_Params *configParams2 = &configParms [1];
Uint16 frameLen = configParms->frameLen;
/* calculate the number of sub frames and their lengths */
numSubFrame = TCP2_normalCeil (frameLen, TCP2_SUB_FRAME_SIZE_MAX);
subFrameLen = (TCP2_normalCeil (frameLen, (numSubFrame * 256))) * 256;
/* calculate the last sub frame length */
while (frameLen > TCP2_SUB_FRAME_SIZE_MAX)
frameLen = frameLen - subFrameLen;
if (frameLen > 128)
subFrameLenLast = frameLen;
else {
numSubFrame--;
subFrameLenLast = frameLen + TCP2_SUB_FRAME_SIZE_MAX;
}
/* Assign the config parameters for the first and the middle subframes */
configParams1->mode = TCP2_FIRST_SF;
configParams1->frameLen = subFrameLen;
TCP2_calcSubBlocks (configParams1);
/* Assign the config parameters for the first and the middle subframes */
configParams2->mode = TCP2_LAST_SF;
configParams2->frameLen = subFrameLenLast;
TCP2_calcSubBlocks (configParams2);
return numSubFrame;
} /* end TCP2_calcSubBlocksSP () */
/* ============================================================================
* @n@b TCP2_calcSubBlocks
*
* @b Description
* @n This function calculates the number of sub blocks for the TCP
* processing. The reliability length is also calculated and the
* configParms structure is populated.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configParms argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
...
TCP2_calcSubBlocks (configParms);
@endverbatim
* ===========================================================================
*/
void TCP2_calcSubBlocks (
TCP2_Params *configParms
)
{
Uint16 frameLen = configParms->frameLen;
Uint16 winSize;
Uint16 numSlidingWindow;
Uint16 relLen;
Uint16 numSubBlock = 1;
Uint16 relLenMax = TCP2_RLEN_MAX;
/* calculate the number of sliding windows */
if (frameLen <= 128) {
numSlidingWindow = 1;
relLen = frameLen;
}
else
numSlidingWindow = 2;
/* Calculate the reliability length and number of sub blocks */
if (2 == numSlidingWindow) {
winSize = TCP2_normalCeil (frameLen, numSlidingWindow);
do {
numSubBlock = TCP2_normalCeil (winSize, relLenMax);
relLen = winSize / numSubBlock;
if ((relLen * numSubBlock) < winSize)
relLen++;
relLenMax--;
} while (((numSubBlock * relLen * numSlidingWindow) - frameLen) >=
(relLen - (configParms->prologSize)));
}
configParms->relLen = relLen - 1;
configParms->numSubBlock = numSubBlock;
configParms->numSlideWin = numSlidingWindow - 1;
return;
} /* end TCP2_calcSubBlocks () */
/** ============================================================================
* @n@b TCP2_tailConfig3GPP
*
* @b Description
* @n This function generates the input control values IC6-IC11 for 3GPP
* channels. These values consist of the tail data following the
* systematics and parities data. This function is called from the generic
* TCP2_tailConfig function.
*
* @b Arguments
@verbatim
mode TCP processing mode (SA or SP)
map TCP shared processing MAP
rate TCP data code rate
tailData Pointer to the tail data
configIc Pointer to the IC values structure
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The configIc structure is assigned the tail configuration values
* based on the tailData.
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
TCP2_ConfigIc *configIc;
TCP2_UserData *xabData = &userData[frameLen];
...
TCP2_tailConfig3GPP (configParms->mode, configParms->map,
configParms->rate,
userData, configIc);
@endverbatim
* ===========================================================================
*/
void TCP2_tailConfig3GPP (
TCP2_Mode mode,
TCP2_Map map,
TCP2_Rate rate,
TCP2_TailData *restrict tailData,
TCP2_ConfigIc *restrict configIc
)
{
Uint32 tail1 = 0, tail2 = 0, tail3 = 0, tail4 = 0, tail5 = 0, tail6 = 0;
Uint32 gie;
if (TCP2_MODE_SA == mode) { /* set the tail bits for SA mode */
switch (rate) {
case TCP2_RATE_1_2:
case TCP2_RATE_1_3:
case TCP2_RATE_3_4: {
/* tail1 = x10(2), x10(1), x10(0) */
/* tail2 = p10(2), p10(1), p10(0) */
/* tail3 = 0, 0, 0 */
/* tail4 = x20(2), x20(1), x20(0) */
/* tail5 = p20(2), p20(1), p20(0) */
/* tail6 = 0, 0, 0 */
tail1 = TCP2_makeTailArgs(tailData [4], tailData [2],
tailData [0]);
tail2 = TCP2_makeTailArgs(tailData [5], tailData [3],
tailData [1]);
tail3 = 0;
tail4 = TCP2_makeTailArgs(tailData [10], tailData [8],
tailData [6]);
tail5 = TCP2_makeTailArgs(tailData [11], tailData [9],
tailData [7]);
tail6 = 0;
break;
}
case TCP2_RATE_1_4:
case TCP2_RATE_1_5: {
/* tail1 = x10(2), x10(1), x10(0) */
/* tail2 = p10(2), p10(1), p10(0) */
/* tail3 = p11(2), p11(1), p11(0) */
/* tail4 = x20(2), x20(1), x20(0) */
/* tail5 = p20(2), p20(1), p20(0) */
/* tail6 = p21(2), p21(1), p21(0) */
tail1 = TCP2_makeTailArgs(tailData [6], tailData [3],
tailData [0]);
tail2 = TCP2_makeTailArgs(tailData [7], tailData [4],
tailData [1]);
tail3 = TCP2_makeTailArgs(tailData [8], tailData [5],
tailData [2]);
tail4 = TCP2_makeTailArgs(tailData [15], tailData [12],
tailData [9]);
tail5 = TCP2_makeTailArgs(tailData [16], tailData [13],
tailData [10]);
tail6 = TCP2_makeTailArgs(tailData [17], tailData [14],
tailData [11]);
break;
}
default:
break;
} /* end of switch */
} /* end of if (TCP2_MODE_SA == mode) */
if (TCP2_LAST_SF == mode) { /* set the tail bits for SP last sub frame */
switch (rate) {
case TCP2_RATE_1_2:
case TCP2_RATE_1_3:
case TCP2_RATE_3_4: {
/* SP MAP1 - non interleaved tail bits */
/* tail1 = x10(2), x10(1), x10(0) */
/* tail2 = p10(2), p10(1), p10(0) */
/* tail3 = 0, 0, 0 */
/* SP MAP2 - interleaved tail bits */
/* tail1 = x20(2), x20(1), x20(0) */
/* tail2 = p20(2), p20(1), p20(0) */
/* tail3 = 0, 0, 0 */
if (TCP2_MAP_MAP1 == map) {
tail1 = TCP2_makeTailArgs(tailData [4], tailData [2],
tailData [0]);
tail2 = TCP2_makeTailArgs(tailData [5], tailData [3],
tailData [1]);
tail3 = 0;
}
else {
tail1 = TCP2_makeTailArgs(tailData [10], tailData [8],
tailData [6]);
tail2 = TCP2_makeTailArgs(tailData [11], tailData [9],
tailData [7]);
tail3 = 0;
}
tail4 = 0;
tail5 = 0;
tail6 = 0;
break;
}
case TCP2_RATE_1_4:
case TCP2_RATE_1_5: {
/* SP MAP1 - non interleaved tail bits */
/* tail1 = x10(2), x10(1), x10(0) */
/* tail2 = p10(2), p10(1), p10(0) */
/* tail3 = p11(2), p11(1), p11(0) */
/* SP MAP2 - interleaved tail bits */
/* tail1 = x20(2), x20(1), x20(0) */
/* tail2 = p20(2), p20(1), p20(0) */
/* tail3 = p21(2), p21(1), p21(0) */
if (TCP2_MAP_MAP1 == map) {
tail1 = TCP2_makeTailArgs(tailData [6], tailData [3],
tailData [0]);
tail2 = TCP2_makeTailArgs(tailData [7], tailData [4],
tailData [1]);
tail3 = TCP2_makeTailArgs(tailData [8], tailData [5],
tailData [2]);
}
else {
tail1 = TCP2_makeTailArgs(tailData [15], tailData [12],
tailData [9]);
tail2 = TCP2_makeTailArgs(tailData [16], tailData [13],
tailData [10]);
tail3 = TCP2_makeTailArgs(tailData [17], tailData [14],
tailData [11]);
}
tail4 = 0;
tail5 = 0;
tail6 = 0;
break;
}
default:
break;
} /* end of switch */
} /* end of if (TCP2_LAST_SF == mode) */
gie = _disable_interrupts ();
/* Assign the tail data values */
configIc->ic6 = tail1;
configIc->ic7 = tail2;
configIc->ic8 = tail3;
configIc->ic9 = tail4;
configIc->ic10 = tail5;
configIc->ic11 = tail6;
_restore_interrupts (gie);
return;
} /* end TCP2_tailConfig3GPP */
/** ============================================================================
* @n@b TCP2_tailConfigIs2000
*
* @b Description
* @n This function generates the input control values IC6-IC11 for IS2000
* channels. These values consist of the tail data following the
* systematics and parities data. This function is called from the generic
* TCP2_tailConfig function.
*
* @b Arguments
@verbatim
mode TCP processing mode (SA or SP)
map TCP shared processing MAP
rate TCP data code rate
tailData Pointer to the tail data
configIc Pointer to the IC values structure
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The configIc structure is assigned the tail configuration values
* based on the taildata.
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
TCP2_ConfigIc *configIc;
TCP2_UserData *xabData = &userData[frameLen];
...
TCP2_tailConfigIs2000 (configParms->mode, configParms->map,
configParms->rate,
userData, configIc);
@endverbatim
* ===========================================================================
*/
void TCP2_tailConfigIs2000 (
TCP2_Mode mode,
TCP2_Map map,
TCP2_Rate rate,
TCP2_TailData *restrict tailData,
TCP2_ConfigIc *restrict configIc
)
{
Uint32 tail1 = 0, tail2 = 0, tail3 = 0, tail4 = 0, tail5 = 0, tail6 = 0;
Uint32 gie;
if (TCP2_MODE_SA == mode) { /* set the tail bits for SA mode */
switch (rate) {
case TCP2_RATE_1_2: {
/* tail1 = x10(2), x10(1), x10(0) */
/* tail2 = p10 (2), p10 (1), p10 (0) */
/* tail3 = 0, 0, 0 */
/* tail4 = x20 (2), x20 (1), x20 (0) */
/* tail5 = p20 (2), p20 (1), p20 (0) */
/* tail6 = 0, 0, 0 */
tail1 = TCP2_makeTailArgs(tailData [4], tailData [2],
tailData [0]);
tail2 = TCP2_makeTailArgs(tailData [5], tailData [3],
tailData [1]);
tail3 = 0;
tail4 = TCP2_makeTailArgs(tailData [10], tailData [8],
tailData [6]);
tail5 = TCP2_makeTailArgs(tailData [11], tailData [9],
tailData [7]);
tail6 = 0;
break;
}
case TCP2_RATE_3_4: {
/* tail1 = x10 (2), x10 (1), x10 (0) */
/* tail2 = 0, 0, p10 (0) */
/* tail3 = 0, 0, 0 */
/* tail4 = x20 (2), x20 (1), x20 (0) */
/* tail5 = 0, 0, p20 (0) */
/* tail6 = 0, 0, 0 */
tail1 = TCP2_makeTailArgs(tailData [4], tailData [2],
tailData [0]);
tail2 = TCP2_makeTailArgs( 0, 0, tailData [1]);
tail3 = 0;
tail4 = TCP2_makeTailArgs(tailData [10], tailData [8],
tailData [6]);
tail5 = TCP2_makeTailArgs( 0, 0, tailData [7]);
tail6 = 0;
break;
}
case TCP2_RATE_1_3: {
/* tail1 = (x10 + x10)/2, (x10 + x10)/2, (x10 + x10)/2 */
/* tail2 = p10, p10, p10 */
/* tail3 = 0, 0, 0 */
/* tail4 = (x20 + x20)/2, (x20 + x20)/2, (x20 + x20)/2 */
/* tail5 = p20, p20, p20 */
/* tail6 = 0, 0, 0 */
tail1 = TCP2_makeTailArgs((tailData [7] + tailData [6]) / 2,
(tailData [4] + tailData [3]) / 2,
(tailData [1] + tailData [0]) / 2);
tail2 = TCP2_makeTailArgs(tailData [8], tailData [5],
tailData [2]);
tail3 = 0;
tail4 = TCP2_makeTailArgs((tailData [15] + tailData [16]) / 2,
(tailData [12] + tailData [13]) / 2,
(tailData [9] + tailData [10]) / 2);
tail5 = TCP2_makeTailArgs(tailData [17], tailData [14],
tailData [11]);
tail6 = 0;
break;
}
case TCP2_RATE_1_4: {
/* tail1 = (x10 + x10)/2, (x10 + x10)/2, (x10 + x10)/2 */
/* tail2 = p10, p10, p10 */
/* tail3 = p11, p11, p11 */
/* tail4 = (x20 + x20)/2, (x20 + x20)/2, (x20 + x20)/2 */
/* tail5 = p20, p20, p20 */
/* tail6 = p21, p21, p21 */
tail1 = TCP2_makeTailArgs((tailData [8] + tailData [9]) / 2,
(tailData [4] + tailData [5]) / 2,
(tailData [0] + tailData [1]) / 2);
tail2 = TCP2_makeTailArgs(tailData [10], tailData [6],
tailData [2]);
tail3 = TCP2_makeTailArgs(tailData [11], tailData [7],
tailData [3]);
tail4 = TCP2_makeTailArgs((tailData [20] + tailData [21]) / 2,
(tailData [17] + tailData [16]) / 2,
(tailData [12] + tailData [13]) / 2);
tail5 = TCP2_makeTailArgs(tailData [22], tailData [18],
tailData [14]);
tail6 = TCP2_makeTailArgs(tailData [23], tailData [19],
tailData [15]);
break;
}
case TCP2_RATE_1_5: {
/* tail1 = (x10 + x10 + x10)/3, (x10 + x10 + x10)/3,
(x10 + x10 + x10)/3 */
/* tail2 = p10, p10, p10 */
/* tail3 = p11, p11, p11 */
/* tail4 = (x20 + x20 + x20)/3, (x20 + x20 + x20)/3,
(x20 + x20 + x20)/3 */
/* tail5 = p20, p20, p20 */
/* tail6 = p21, p21, p21 */
tail1 = TCP2_makeTailArgs(
(tailData [10] + tailData [11] + tailData [12]) / 3,
(tailData [5] + tailData [6] + tailData [7]) / 3,
(tailData [0] + tailData [1] + tailData [2]) / 3
);
tail2 = TCP2_makeTailArgs(tailData [13], tailData [8],
tailData [3]);
tail3 = TCP2_makeTailArgs(tailData [14], tailData [9],
tailData [4]);
tail4 = TCP2_makeTailArgs(
(tailData [25] + tailData [26] + tailData [27]) / 3,
(tailData [20] + tailData [21] + tailData [22]) / 3,
(tailData [15] + tailData [16] + tailData [17]) / 3
);
tail5 = TCP2_makeTailArgs(tailData [28], tailData [23],
tailData [18]);
tail6 = TCP2_makeTailArgs(tailData [29], tailData [24],
tailData [19]);
break;
}
default:
break;
}
} /* end of if (TCP2_MODE_SA == mode) */
if (TCP2_LAST_SF == mode) { /* set the tail bits for SP last sub frame */
switch (rate) {
case TCP2_RATE_1_2: {
/* SP MAP1 non interleaved data */
/* tail1 = x10(2), x10(1), x10(0) */
/* tail2 = p10 (2), p10 (1), p10 (0) */
/* tail3 = 0, 0, 0 */
/* SP MAP2 interleaved data */
/* tail1 = x20 (2), x20 (1), x20 (0) */
/* tail2 = p20 (2), p20 (1), p20 (0) */
/* tail3 = 0, 0, 0 */
if (TCP2_MAP_MAP1 == map) {
tail1 = TCP2_makeTailArgs(tailData [4], tailData [2],
tailData [0]);
tail2 = TCP2_makeTailArgs(tailData [5], tailData [3],
tailData [1]);
tail3 = 0;
}
else {
tail1 = TCP2_makeTailArgs(tailData [10], tailData [8],
tailData [6]);
tail2 = TCP2_makeTailArgs(tailData [11], tailData [9],
tailData [7]);
tail3 = 0;
}
tail4 = 0;
tail5 = 0;
tail6 = 0;
break;
}
case TCP2_RATE_3_4: {
/* SP MAP1 non interleaved data */
/* tail1 = x10 (2), x10 (1), x10 (0) */
/* tail2 = 0, 0, p10 (0) */
/* tail3 = 0, 0, 0 */
/* SP MAP2 interleaved data */
/* tail1 = x20 (2), x20 (1), x20 (0) */
/* tail2 = 0, 0, p20 (0) */
/* tail3 = 0, 0, 0 */
if (TCP2_MAP_MAP1 == map) {
tail1 = TCP2_makeTailArgs(tailData [4], tailData [2],
tailData [0]);
tail2 = TCP2_makeTailArgs( 0, 0, tailData [1]);
tail3 = 0;
}
else {
tail1 = TCP2_makeTailArgs(tailData [10], tailData [8],
tailData [6]);
tail2 = TCP2_makeTailArgs( 0, 0, tailData [7]);
tail3 = 0;
}
tail4 = 0;
tail5 = 0;
tail6 = 0;
break;
}
case TCP2_RATE_1_3: {
/* SP MAP1 non interleaved data */
/* tail1 = (x10 + x10)/2, (x10 + x10)/2, (x10 + x10)/2 */
/* tail2 = p10, p10, p10 */
/* tail3 = 0, 0, 0 */
/* SP MAP2 interleaved data */
/* tail1 = (x20 + x20)/2, (x20 + x20)/2, (x20 + x20)/2 */
/* tail2 = p20, p20, p20 */
/* tail3 = 0, 0, 0 */
if (TCP2_MAP_MAP1 == map) {
tail1 = TCP2_makeTailArgs((tailData [7] + tailData [6]) / 2,
(tailData [4] + tailData [3]) / 2,
(tailData [1] + tailData [0]) / 2);
tail2 = TCP2_makeTailArgs(tailData [8], tailData [5],
tailData [2]);
tail3 = 0;
}
else {
tail1 = TCP2_makeTailArgs(
(tailData [15] + tailData [16]) / 2,
(tailData [12] + tailData [13]) / 2,
(tailData [9] + tailData [10]) / 2
);
tail2 = TCP2_makeTailArgs(tailData [17], tailData [14],
tailData [11]);
tail3 = 0;
}
tail4 = 0;
tail5 = 0;
tail6 = 0;
break;
}
case TCP2_RATE_1_4: {
/* SP MAP1 non interleaved data */
/* tail1 = (x10 + x10)/2, (x10 + x10)/2, (x10 + x10)/2 */
/* tail2 = p10, p10, p10 */
/* tail3 = p11, p11, p11 */
/* SP MAP2 interleaved data */
/* tail1 = (x20 + x20)/2, (x20 + x20)/2, (x20 + x20)/2 */
/* tail2 = p20, p20, p20 */
/* tail3 = p21, p21, p21 */
if (TCP2_MAP_MAP1 == map) {
tail1 = TCP2_makeTailArgs((tailData [8] + tailData [9]) / 2,
(tailData [4] + tailData [5]) / 2,
(tailData [0] + tailData [1]) / 2);
tail2 = TCP2_makeTailArgs(tailData [10], tailData [6],
tailData [2]);
tail3 = TCP2_makeTailArgs(tailData [11], tailData [7],
tailData [3]);
}
else {
tail1 = TCP2_makeTailArgs(
(tailData [20] + tailData [21]) / 2,
(tailData [17] + tailData [16]) / 2,
(tailData [12] + tailData [13]) / 2
);
tail2 = TCP2_makeTailArgs(tailData [22], tailData [18],
tailData [14]);
tail3 = TCP2_makeTailArgs(tailData [23], tailData [19],
tailData [15]);
}
tail4 = 0;
tail5 = 0;
tail6 = 0;
break;
}
case TCP2_RATE_1_5: {
/* SP MAP1 non interleaved data */
/* tail1 = (x10 + x10 + x10)/3, (x10 + x10 + x10)/3,
(x10 + x10 + x10)/3 */
/* tail2 = p10, p10, p10 */
/* tail3 = p11, p11, p11 */
/* SP MAP2 interleaved data */
/* tail4 = (x20 + x20 + x20)/3, (x20 + x20 + x20)/3,
(x20 + x20 + x20)/3 */
/* tail5 = p20, p20, p20 */
/* tail6 = p21, p21, p21 */
if (TCP2_MAP_MAP1 == map) {
tail1 = TCP2_makeTailArgs(
(tailData [10] + tailData [11] + tailData [12]) / 3,
(tailData [5] + tailData [6] + tailData [7]) / 3,
(tailData [0] + tailData [1] + tailData [2]) / 3
);
tail2 = TCP2_makeTailArgs(tailData [13], tailData [8],
tailData [3]);
tail3 = TCP2_makeTailArgs(tailData [14], tailData [9],
tailData [4]);
}
else {
tail1 = TCP2_makeTailArgs(
(tailData [25] + tailData [26] + tailData [27]) / 3,
(tailData [20] + tailData [21] + tailData [22]) / 3,
(tailData [15] + tailData [16] + tailData [17]) / 3
);
tail2 = TCP2_makeTailArgs(tailData [28], tailData [23],
tailData [18]);
tail3 = TCP2_makeTailArgs(tailData [29], tailData [24],
tailData [19]);
}
tail4 = 0;
tail5 = 0;
tail6 = 0;
break;
}
default:
break;
}
} /* end of else */
/* Assign the tail data values */
gie = _disable_interrupts ();
configIc->ic6 = tail1;
configIc->ic7 = tail2;
configIc->ic8 = tail3;
configIc->ic9 = tail4;
configIc->ic10 = tail5;
configIc->ic11 = tail6;
_restore_interrupts (gie);
return;
} /* end TCP2_tailConfigIs2000 */
/** ============================================================================
* @n@b TCP2_calculateHd
*
* @b Description
* @n This function calculates the hard decisions following multiple MAP
* decodings in shared processing mode.
*
* @b Arguments
@verbatim
extrinsicsMap1 Extrinsics data following MAP1 decode
apriori Apriori data following MAP2 decode
channelData Input channel data
hardDecisions Hard decisions
numExt Number of extrinsics
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The hardDecisions will contain the calculated hard decisions.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
void TCP2_calculateHd(extrinsicsMap1, apriori,
channelData, hardDecisions, numExt);
@endverbatim
* ===========================================================================
*/
void TCP2_calculateHd (
const TCP2_ExtrinsicData *extrinsicsMap1,
const TCP2_ExtrinsicData *apriori,
const TCP2_UserData *channelData,
Uint32 *hardDecisions,
Uint16 numExt
)
{
Uint32 i;
Int32 extInt;
Int32 apInt;
Int32 inputInt;
Int32 softDecision;
Uint32 wordCount = 0;
Uint32 hdCount = 0;
hardDecisions[0] = 0;
for (i = 0; i < numExt; i++) {
if((extrinsicsMap1[i]<<1)&0x80)
extInt = (extrinsicsMap1[i]<<1) | 0xffffff00;
else
extInt = (Int32)(extrinsicsMap1[i]<<1);
if((apriori[i]<<1)&0x80)
apInt = (apriori[i]<<1) | 0xffffff00;
else
apInt = (Int32)(apriori[i]<<1);
inputInt = (Int32)channelData[i / 5]; /* i * rate( = 1/5) */
if(inputInt & 0x80) inputInt |= 0xFFFFFF00;
softDecision = inputInt + extInt + apInt;
if(hdCount == 32) {
hdCount = 0;
wordCount++;
hardDecisions[wordCount] = 0;
}
if((softDecision & 0x200) == 0)
hardDecisions[wordCount] |= 1 << hdCount;
hdCount++;
}
return;
}
/** ============================================================================
* @n@b TCP2_deinterleaveExt
*
* @b Description
* @n This function de-interleaves the MAP2 extrinsics data to generate
* apriori data for the MAP1 decode. This function is for use in
* performing shared processing.
*
* @b Arguments
@verbatim
aprioriMap1 Apriori data for MAP1 decode
extrinsicsMap2 Extrinsics data
interleaverTable Interleaver data table
numExt Number of Extrinsics
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The aprioriMap1 will contain the deinterleaved data.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
<...MAP 2 decode...>
TCP2_deinterleaveExt(aprioriMap1, extrinsicsMap2,
interleaverTable, numExt);
<...MAP 1 decode...>
@endverbatim
* ===========================================================================
*/
void TCP2_deinterleaveExt (
TCP2_ExtrinsicData *aprioriMap1,
const TCP2_ExtrinsicData *extrinsicsMap2,
const Uint16 *interleaverTable,
Uint32 numExt
)
{
Uint32 cnt;
/* deinterleave extrinsics */
for (cnt = 0; cnt < numExt; cnt++) {
aprioriMap1[interleaverTable[cnt]] = *(extrinsicsMap2 + cnt);
}
return;
}
/** ============================================================================
* @n@b TCP2_interleaveExt
*
* @b Description
* @n This function interleaves the MAP1 extrinsics data to generate
* apriori data for the MAP2 decode. This function is for used in
* performing shared processing.
*
* @b Arguments
@verbatim
aprioriMap2 Apriori data for MAP2 decode
extrinsicsMap1 Extrinsics data
interleaverTable Interleaver data table
numExt Number of Extrinsics
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The aprioriMap2 will contain the interleaved data.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
<...MAP 1 decode...>
TCP2_interleaveExt(aprioriMap2, extrinsicsMap1,
interleaverTable, numExt);
<...MAP 2 decode...>
@endverbatim
* ===========================================================================
*/
void TCP2_interleaveExt (
TCP2_ExtrinsicData *aprioriMap2,
const TCP2_ExtrinsicData *extrinsicsMap1,
const Uint16 *interleaverTable,
Uint32 numExt
)
{
Uint32 cnt;
/* interleaving extrinsics */
for (cnt=0; cnt < numExt; cnt++) {
aprioriMap2[cnt] = *(extrinsicsMap1 + interleaverTable[cnt]);
}
return;
}
/** ============================================================================
* @n@b TCP2_demuxInput
*
* @b Description
* @n This function splits the input data into two working sets. One set
* contains the non-interleaved input data and is used with the MAP 1
* decoding. The other contains the interleaved input data and is used
* with the MAP2 decoding. This function is used in shared processing mode.
*
* @b Arguments
@verbatim
rate TCP data code rate
frameLen Frame length
input Input channel data
interleaver Interleaver data table
nonInterleaved Non Interleaved data for SP MAP0
interleaved Interleaved data for SP MAP1
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The nonInterleaved will contain the non-interleaved
* data and the interleaved will contain the interleaved data.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
TCP2_demuxInput (frameLen, input,
interleaver, interleaved, nonInterleaved);
@endverbatim
* ===========================================================================
*/
void TCP2_demuxInput (
Uint32 rate,
Uint32 frameLen,
const TCP2_UserData *input,
const Uint16 *interleaver,
TCP2_ExtrinsicData *nonInterleaved,
TCP2_ExtrinsicData *interleaved
)
{
Uint32 inCnt;
Uint32 outCnt;
Uint32 cnt;
Uint16 iter;
Uint32 *output0 = (Uint32 *)nonInterleaved;
Uint32 *output1 = (Uint32 *)interleaved;
Uint16 *deInterleaveTbl;
Uint16 dataIndex;
Uint16 tableIndex;
Uint16 numPar;
/* allocate memory for deinterleave table */
deInterleaveTbl = (Uint16*) malloc (sizeof (Uint16) * frameLen);
/*
'interleaver' is a buffer of frameLen 16-bit indices
'input' is a buffer of frameLen * rate 8-bit elements
'output[2]' is the 2 de-multiplexed buffers :
.out[0] buffer which is the TCP input buffer for LOG-MAP 1 decoding
.out[1] buffer which is the TCP input buffer for LOG-MAP 2 decoding
*/
/* For shared processing, TCP2 only executes the non-interleaved MAP
* decoder. Therefore, p20 and p21 are not used in the input data. When
* processing a non-interleaved MAP(as MAP1 in SA mode) x10, p10, and
* p11 must be non-interleaved data. And when processing the interleaved
* MAP (As MAP2 in SA mode) x10, p10, and p11 must be the interleaved data
* that has been deinterleaved.
*/
/* Form the de-interleave table */
for (cnt = 0; cnt < frameLen; cnt++)
deInterleaveTbl [ interleaver [cnt] ] = cnt;
/* Form the output for MAP1 and MAP2 */
switch (rate) {
case TCP2_RATE_1_5: {
/* for code rate = 1/5 */
/* Set of 5 symbols are processed at once */
/* input (Uint8):
* x0a0b0a0'b0'x1a1b1a1'b1'
*
* output (Uint32)
* non interleaved:
* b0 a0 x0
* b1 a1 x1
*
* interleaved:
* b0' a0' x0
* b1' a1' x1
*/
outCnt = 0;
for (inCnt = 0; inCnt < frameLen * rate; inCnt += rate) {
/* Form the non interleaved data */
output0 [outCnt] = input [inCnt + 2] << 12 |
input [inCnt + 1] << 6 |
input [inCnt];
/* Form the interleaved data */
tableIndex = inCnt / rate;
dataIndex = deInterleaveTbl [tableIndex] * rate;
output1 [outCnt] = input [dataIndex + 4] << 12 |
input [dataIndex + 3] << 6 |
input [inCnt];
/* Fill the next Uint32 value */
outCnt++;
}
break;
}/* TCP2_RATE_1_5 */
case TCP2_RATE_1_4: {
/* for code rate = 1/4 */
/* Set of 4 symbols are processed at once */
/* input (Uint8):
* x0a0b0b0'x1a1a1'b1'
*
* output (Uint32)
* non interleaved:
* b0 a0 x0 (even)
* 0 a1 x1 (odd)
*
* interleaved:
* b0' 0 x0
* b1' a1' x1
*/
outCnt = 0;
/* Used to handle the difference in the input data symbols for
* 2 consecutive set of 4 symbols
*/
iter = 0;
for (inCnt = 0; inCnt < frameLen * rate; inCnt += rate) {
if (0 == iter) {
/* Form the non interleaved data */
output0 [outCnt] = input [inCnt + 2] << 12 |
input [inCnt + 1] << 6 |
input [inCnt];
/* Form the interleaved data */
tableIndex = inCnt / rate;
dataIndex = deInterleaveTbl [tableIndex] * rate;
if ((deInterleaveTbl [tableIndex] % 2) == 0) {
output1 [outCnt] = input [dataIndex + 3] << 12 |
input [inCnt];
}
else {
output1 [outCnt] = input [dataIndex + 3] << 12 |
input [dataIndex + 2] << 6 |
input [inCnt];
}
iter = 1;
} /* end of if (0 == iter) */
else {
/* Form the non interleaved data */
output0 [outCnt] = input [inCnt + 1] << 6 |
input [inCnt];
/* Form the interleaved data */
tableIndex = inCnt / rate;
dataIndex = deInterleaveTbl [tableIndex] * rate;
if ((deInterleaveTbl [tableIndex] % 2) == 0) {
output1 [outCnt] = input [dataIndex + 3] << 12 |
input [inCnt];
}
else {
output1 [outCnt] = input [dataIndex + 3] << 12 |
input [dataIndex + 2] << 6 |
input [inCnt];
}
iter = 0;
} /* end of else of if (0 == iter) */
/* Fill the next Uint32 value */
outCnt++;
}
break;
}/* TCP2_RATE_1_4 */
case TCP2_RATE_1_3: {
/* for code rate = 1/3 */
/* Set of 3 symbols are processed at once */
/* input (Uint8):
* x0a0a0'x1a1a1'
*
* output (Uint32)
* non interleaved:
* a0 x0
* a1 x1
*
* interleaved:
* a0' x0
* a1' x1
*/
outCnt = 0;
for (inCnt = 0; inCnt < frameLen * rate; inCnt += rate) {
/* Form the non interleaved data */
output0 [outCnt] = input [inCnt + 1] << 6 |
input [inCnt];
/* Form the interleaved data */
tableIndex = inCnt / rate;
dataIndex = deInterleaveTbl [tableIndex] * rate;
output1 [outCnt] = input [dataIndex + 2] << 6 |
input [inCnt];
/* Fill the next Uint32 value */
outCnt++;
}
break;
}/* TCP2_RATE_1_3 */
case TCP2_RATE_1_2: {
/* for code rate = 1/2 */
/* Set of 2 symbols are processed at once */
/* input (Uint8):
* x0a0x1a1'x2a2x3a3'
*
* output (Uint32)
* non interleaved:
* a0 x0 (even)
* 0 x1 (odd)
*
* interleaved:
* 0 x0
* a1' x1
*/
outCnt = 0;
/* Used to handle the difference in the input data symbols for
* 2 consecutive set of 2 symbols
*/
iter = 0;
for (inCnt = 0; inCnt < frameLen * rate; inCnt += rate) {
if (0 == iter) {
/* Form the non interleaved data */
output0 [outCnt] = input [inCnt + 1] << 6 |
input [inCnt];
/* Form the interleaved data */
tableIndex = inCnt / rate;
dataIndex = deInterleaveTbl [tableIndex] * rate;
if ((deInterleaveTbl [tableIndex] % 2) == 0) {
output1 [outCnt] = input [inCnt];
}
else {
output1 [outCnt] = input [dataIndex + 1] << 6 |
input [inCnt];
}
iter = 1;
} /* end of if (0 == iter) */
else {
/* Form the non interleaved data */
output0 [outCnt] = input [inCnt];
/* Form the interleaved data */
tableIndex = inCnt / rate;
dataIndex = deInterleaveTbl [tableIndex] * rate;
if ((deInterleaveTbl [tableIndex] % 2) == 0) {
output1 [outCnt] = input [inCnt];
}
else {
output1 [outCnt] = input [dataIndex + 1] << 6 |
input [inCnt];
}
iter = 0;
} /* end of else of if (0 == iter) */
/* Fill the next Uint32 value */
outCnt++;
}
break;
}/* TCP2_RATE_1_2 */
case TCP2_RATE_3_4: {
/* for code rate = 3/4 */
/* input (Uint8):
* x0a0x1x2x3a3'x4x5
*
* output (Uint32)
* non interleaved:
* a0 x0 (even)
* 0 x1 (odd)
* 0 x2
*
* interleaved:
* 0 x0
* 0 x1
* 0 x2
* a3' x3
*/
/* Set of 4 symbols are processed at once to get 3 output data */
outCnt = 0;
/* Used to handle the difference in the input data symbols for
* 2 consecutive set of 4 symbols
*/
iter = 0;
/* to calculate the symbols added for rate 3/4 */
for (inCnt = 0; inCnt < frameLen; inCnt += 1) {
/* Shift the data and convert to the 32 bit TCP input
* data format
*/
if (((inCnt % 2) == 0) && ((inCnt % 3) == 0)) {
/* Form the non interleaved data - 3 */
output0 [outCnt] = (
(input [inCnt + numPar + 1] << 6) |
(input [inCnt + numPar] << 0)
);
}
else {
output0 [outCnt ] = input [inCnt + numPar];
}
/* Form the interleaved data */
dataIndex = deInterleaveTbl [inCnt] + numPar;
if (((deInterleaveTbl [inCnt] % 2) != 0) &&
((deInterleaveTbl [inCnt] % 3) == 0)) {
output1 [outCnt] = input [dataIndex + 1] << 6 |
input [inCnt + numPar];
}
else {
output1 [outCnt] = input [inCnt + numPar];
}
/* adjust for the parity data, required as the inCnt is
* incremented by 1 and not rate
*/
if ((inCnt % 3) == 0) {
numPar++; /* offset to get the data index */
}
outCnt += 1;
} /* end of for */
break;
}/* TCP2_RATE_3_4 */
default:
break;
}/* end of switch */
/* Free the memory allocated for de interleave table */
free (deInterleaveTbl);
return;
} /* end TCP2_demuxInput() */
/** ============================================================================
* @n@b TCP2_depunctInputs
*
* @b Description
* @n This function scales and sorts input data into a code rate 1/5 format.
*
* @b Arguments
@verbatim
frameLen Input data length in bytes
inputData Input data
rate Input data code rate
scalingFact Scaling factor
depunctData Depunctured data
@endverbatim
*
* <b> Return Value </b> None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The depunctData will contain the data depunctured to rate 1/5.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
TCP2_depunctInputs (length, inputData, rate
scalingFact, depunctData);
@endverbatim
* ===========================================================================
*/
void TCP2_depunctInputs (
Uint32 frameLen,
TCP2_UserData* inputData,
TCP2_Rate rate,
Uint32 scalingFact,
TCP2_InputData* depunctData
)
{
Uint32 inCnt;
Uint32 outCnt;
Uint32 cnt;
Uint32 modLen;
Uint16 iter;
switch (rate) {
case TCP2_RATE_1_5: {
/* for code rate = 1/5 */
/* Set of 5 symbols are processed at once */
/* input (Uint8):
* x0a0b0a0'b0'x1a1b1a1'b1'
*
* output (Uint32)
* b0' a0' b0 a0 x0
* b1' a1' b1 a1 x1
*/
outCnt = 0;
for (inCnt = 0; inCnt < frameLen * rate; inCnt += rate) {
/* Shift the data and convert to the 32 bit TCP input
* data format
*/
for (cnt = 0; cnt < rate; cnt++) {
depunctData [outCnt] |= (
(inputData [inCnt + cnt] * scalingFact ) <<
DATA_WIDTH * cnt);
}
/* Fill the next Uint32 value */
outCnt++;
}
break;
}/* TCP2_RATE_1_5 */
case TCP2_RATE_1_4: {
/* for code rate = 1/4 */
/* input (Uint8):
* x0a0b0b0'x1a1a1'b1'
*
* output (Uint32)
* b0' 0 b0 a0 x0
* b1' a1' 0 a0 x1
*/
/* Set of 4 symbols are processed at once */
outCnt = 0;
/* Used to handle the difference in the input data symbols for
* 2 consecutive set of 4 symbols
*/
iter = 0;
for (inCnt = 0; inCnt < frameLen * rate; inCnt += rate) {
/* Shift the data and convert to the 32 bit TCP input
* data format
*/
if (0 == iter) {
depunctData [outCnt] = (
((inputData [inCnt + 3] * scalingFact) << 24) |
((inputData [inCnt + 2] * scalingFact) << 12) |
((inputData [inCnt + 1] * scalingFact) << 6) |
((inputData [inCnt] * scalingFact))
);
iter = 1;
}
else {
depunctData [outCnt] = (
((inputData [inCnt + 3] * scalingFact) << 24) |
((inputData [inCnt + 2] * scalingFact) << 18) |
((inputData [inCnt + 1] * scalingFact) << 6) |
((inputData [inCnt] * scalingFact))
);
iter = 0;
}
/* Fill the next Uint32 value */
outCnt++;
} /* end of for */
break;
}/* TCP2_RATE_1_4 */
case TCP2_RATE_1_3: {
/* for code rate = 1/3 */
/* Set of 4 symbols are processed at once */
/* input (Uint8):
* x0a0a0'x1a1a1'
*
* output (Uint32)
* 0 a0' 0 a0 x0
* 0 a1' 0 a1 x1
*/
outCnt = 0;
for (inCnt = 0; inCnt < frameLen * rate; inCnt += rate) {
/* Shift the data and convert to the 32 bit TCP input
* data format
*/
depunctData [outCnt] = (
((inputData [inCnt + 2] * scalingFact) << 18) |
((inputData [inCnt + 1] * scalingFact) << 6) |
((inputData [inCnt] * scalingFact))
);
/* Fill the next Uint32 value */
outCnt++;
}
break;
}/* TCP2_RATE_1_3 */
case TCP2_RATE_1_2: {
/* for code rate = 1/2 */
/* input (Uint8):
* x0a0x1a1'
*
* output (Uint32)
* b0' 0 b0 a0 x0
* b1' a1' 0 a1 x1
*/
/* Set of 2 symbols are processed at once */
outCnt = 0;
/* Used to handle the difference in the input data symbols for
* 2 consecutive set of 2 symbols
*/
iter = 0;
for (inCnt = 0; inCnt < frameLen * rate; inCnt += rate) {
/* Shift the data and convert to the 32 bit TCP input
* data format
*/
if (0 == iter) {
depunctData [outCnt] = (
((inputData [inCnt + 1] * scalingFact) << 6) |
((inputData [inCnt] * scalingFact))
);
iter = 1;
}
else {
depunctData [outCnt] = (
((inputData [inCnt + 1] * scalingFact) << 18) |
((inputData [inCnt] * scalingFact))
);
iter = 0;
}
/* Fill the next Uint32 value */
outCnt++;
}
break;
}/* TCP2_RATE_1_2 */
case TCP2_RATE_3_4: {
/* for code rate = 3/4 */
/* input (Uint8):
* x0a0x1x2x3a3'x4x5
*
* output (Uint32)
* b0' 0 b0 a0 x0
* b1' a1' 0 a1 x1
*/
/* Set of 4 symbols are processed at once to get 3 output data */
outCnt = 0;
/* Used to handle the difference in the input data symbols for
* 2 consecutive set of 4 symbols
*/
iter = 0;
/* to calculate the symbols added for rate 3/4 */
modLen = (frameLen * 4) / 3;
for (inCnt = 0; inCnt < modLen; inCnt += 4) {
/* Shift the data and convert to the 32 bit TCP input
* data format
*/
if (0 == iter) {
/* 3 output data are got */
depunctData [outCnt++] = (
((inputData [inCnt + 1] * scalingFact) << 6) |
((inputData [inCnt] * scalingFact))
);
depunctData [outCnt++] = (inputData [inCnt + 2] * scalingFact);
depunctData [outCnt++] = (inputData [inCnt + 3] * scalingFact);
iter = 1;
}
else {
/* 3 output data are got */
depunctData [outCnt++] = (
((inputData [inCnt + 1] * scalingFact) << 18) |
((inputData [inCnt] * scalingFact))
);
depunctData [outCnt++] = (inputData [inCnt + 2] * scalingFact);
depunctData [outCnt++] = (inputData [inCnt + 3] * scalingFact);
iter = 0;
}
} /* end of for */
break;
}/* TCP2_RATE_3_4 */
default:
break;
}/* end of switch (rate)*/
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_i2c.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_i2c.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for I2C
*/
#ifndef _CSLR_I2C_H_
#define _CSLR_I2C_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 ICOAR;
volatile Uint32 ICIMR;
volatile Uint32 ICSTR;
volatile Uint32 ICCLKL;
volatile Uint32 ICCLKH;
volatile Uint32 ICCNT;
volatile Uint32 ICDRR;
volatile Uint32 ICSAR;
volatile Uint32 ICDXR;
volatile Uint32 ICMDR;
volatile Uint32 ICIVR;
volatile Uint32 ICEMDR;
volatile Uint32 ICPSC;
} CSL_I2cRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_I2cRegs *CSL_I2cRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* ICOAR */
#define CSL_I2C_ICOAR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICOAR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICOAR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICOAR_OADDR_MASK (0x000003FFu)
#define CSL_I2C_ICOAR_OADDR_SHIFT (0x00000000u)
#define CSL_I2C_ICOAR_OADDR_RESETVAL (0x00000000u)
#define CSL_I2C_ICOAR_RESETVAL (0x00000000u)
/* ICIMR */
#define CSL_I2C_ICIMR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICIMR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICIMR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICIMR_AAS_MASK (0x00000040u)
#define CSL_I2C_ICIMR_AAS_SHIFT (0x00000006u)
#define CSL_I2C_ICIMR_AAS_RESETVAL (0x00000000u)
/*----AAS Tokens----*/
#define CSL_I2C_ICIMR_AAS_DISABLE (0x00000000u)
#define CSL_I2C_ICIMR_AAS_ENABLE (0x00000001u)
#define CSL_I2C_ICIMR_SCD_MASK (0x00000020u)
#define CSL_I2C_ICIMR_SCD_SHIFT (0x00000005u)
#define CSL_I2C_ICIMR_SCD_RESETVAL (0x00000000u)
/*----SCD Tokens----*/
#define CSL_I2C_ICIMR_SCD_DISABLE (0x00000000u)
#define CSL_I2C_ICIMR_SCD_ENABLE (0x00000001u)
#define CSL_I2C_ICIMR_ICXRDY_MASK (0x00000010u)
#define CSL_I2C_ICIMR_ICXRDY_SHIFT (0x00000004u)
#define CSL_I2C_ICIMR_ICXRDY_RESETVAL (0x00000000u)
/*----ICXRDY Tokens----*/
#define CSL_I2C_ICIMR_ICXRDY_DISABLE (0x00000000u)
#define CSL_I2C_ICIMR_ICXRDY_ENABLE (0x00000001u)
#define CSL_I2C_ICIMR_ICRRDY_MASK (0x00000008u)
#define CSL_I2C_ICIMR_ICRRDY_SHIFT (0x00000003u)
#define CSL_I2C_ICIMR_ICRRDY_RESETVAL (0x00000000u)
/*----ICRRDY Tokens----*/
#define CSL_I2C_ICIMR_ICRRDY_DISABLE (0x00000000u)
#define CSL_I2C_ICIMR_ICRRDY_ENABLE (0x00000001u)
#define CSL_I2C_ICIMR_ARDY_MASK (0x00000004u)
#define CSL_I2C_ICIMR_ARDY_SHIFT (0x00000002u)
#define CSL_I2C_ICIMR_ARDY_RESETVAL (0x00000000u)
/*----ARDY Tokens----*/
#define CSL_I2C_ICIMR_ARDY_DISABLE (0x00000000u)
#define CSL_I2C_ICIMR_ARDY_ENABLE (0x00000001u)
#define CSL_I2C_ICIMR_NACK_MASK (0x00000002u)
#define CSL_I2C_ICIMR_NACK_SHIFT (0x00000001u)
#define CSL_I2C_ICIMR_NACK_RESETVAL (0x00000000u)
/*----NACK Tokens----*/
#define CSL_I2C_ICIMR_NACK_DISABLE (0x00000000u)
#define CSL_I2C_ICIMR_NACK_ENABLE (0x00000001u)
#define CSL_I2C_ICIMR_AL_MASK (0x00000001u)
#define CSL_I2C_ICIMR_AL_SHIFT (0x00000000u)
#define CSL_I2C_ICIMR_AL_RESETVAL (0x00000000u)
/*----AL Tokens----*/
#define CSL_I2C_ICIMR_AL_DISABLE (0x00000000u)
#define CSL_I2C_ICIMR_AL_ENABLE (0x00000001u)
#define CSL_I2C_ICIMR_RESETVAL (0x00000000u)
/* ICSTR */
#define CSL_I2C_ICSTR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICSTR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICSTR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_SDIR_MASK (0x00004000u)
#define CSL_I2C_ICSTR_SDIR_SHIFT (0x0000000Eu)
#define CSL_I2C_ICSTR_SDIR_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_NACKSNT_MASK (0x00002000u)
#define CSL_I2C_ICSTR_NACKSNT_SHIFT (0x0000000Du)
#define CSL_I2C_ICSTR_NACKSNT_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_BB_MASK (0x00001000u)
#define CSL_I2C_ICSTR_BB_SHIFT (0x0000000Cu)
#define CSL_I2C_ICSTR_BB_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_RSFULL_MASK (0x00000800u)
#define CSL_I2C_ICSTR_RSFULL_SHIFT (0x0000000Bu)
#define CSL_I2C_ICSTR_RSFULL_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_XSMT_MASK (0x00000400u)
#define CSL_I2C_ICSTR_XSMT_SHIFT (0x0000000Au)
#define CSL_I2C_ICSTR_XSMT_RESETVAL (0x00000001u)
#define CSL_I2C_ICSTR_AAS_MASK (0x00000200u)
#define CSL_I2C_ICSTR_AAS_SHIFT (0x00000009u)
#define CSL_I2C_ICSTR_AAS_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_AD0_MASK (0x00000100u)
#define CSL_I2C_ICSTR_AD0_SHIFT (0x00000008u)
#define CSL_I2C_ICSTR_AD0_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_SCD_MASK (0x00000020u)
#define CSL_I2C_ICSTR_SCD_SHIFT (0x00000005u)
#define CSL_I2C_ICSTR_SCD_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_ICXRDY_MASK (0x00000010u)
#define CSL_I2C_ICSTR_ICXRDY_SHIFT (0x00000004u)
#define CSL_I2C_ICSTR_ICXRDY_RESETVAL (0x00000001u)
#define CSL_I2C_ICSTR_ICRRDY_MASK (0x00000008u)
#define CSL_I2C_ICSTR_ICRRDY_SHIFT (0x00000003u)
#define CSL_I2C_ICSTR_ICRRDY_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_ARDY_MASK (0x00000004u)
#define CSL_I2C_ICSTR_ARDY_SHIFT (0x00000002u)
#define CSL_I2C_ICSTR_ARDY_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_NACK_MASK (0x00000002u)
#define CSL_I2C_ICSTR_NACK_SHIFT (0x00000001u)
#define CSL_I2C_ICSTR_NACK_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_AL_MASK (0x00000001u)
#define CSL_I2C_ICSTR_AL_SHIFT (0x00000000u)
#define CSL_I2C_ICSTR_AL_RESETVAL (0x00000000u)
#define CSL_I2C_ICSTR_RESETVAL (0x00000410u)
/* ICCLKL */
#define CSL_I2C_ICCLKL_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICCLKL_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICCLKL_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICCLKL_ICCL_MASK (0x0000FFFFu)
#define CSL_I2C_ICCLKL_ICCL_SHIFT (0x00000000u)
#define CSL_I2C_ICCLKL_ICCL_RESETVAL (0x00000000u)
#define CSL_I2C_ICCLKL_RESETVAL (0x00000000u)
/* ICCLKH */
#define CSL_I2C_ICCLKH_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICCLKH_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICCLKH_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICCLKH_ICCH_MASK (0x0000FFFFu)
#define CSL_I2C_ICCLKH_ICCH_SHIFT (0x00000000u)
#define CSL_I2C_ICCLKH_ICCH_RESETVAL (0x00000000u)
#define CSL_I2C_ICCLKH_RESETVAL (0x00000000u)
/* ICCNT */
#define CSL_I2C_ICCNT_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICCNT_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICCNT_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICCNT_ICDC_MASK (0x0000FFFFu)
#define CSL_I2C_ICCNT_ICDC_SHIFT (0x00000000u)
#define CSL_I2C_ICCNT_ICDC_RESETVAL (0x00000000u)
#define CSL_I2C_ICCNT_RESETVAL (0x00000000u)
/* ICDRR */
#define CSL_I2C_ICDRR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICDRR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICDRR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICDRR_D_MASK (0x000000FFu)
#define CSL_I2C_ICDRR_D_SHIFT (0x00000000u)
#define CSL_I2C_ICDRR_D_RESETVAL (0x00000000u)
#define CSL_I2C_ICDRR_RESETVAL (0x00000000u)
/* ICSAR */
#define CSL_I2C_ICSAR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICSAR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICSAR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICSAR_SADDR_MASK (0x000003FFu)
#define CSL_I2C_ICSAR_SADDR_SHIFT (0x00000000u)
#define CSL_I2C_ICSAR_SADDR_RESETVAL (0x000003FFu)
#define CSL_I2C_ICSAR_RESETVAL (0x000003FFu)
/* ICDXR */
#define CSL_I2C_ICDXR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICDXR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICDXR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICDXR_D_MASK (0x000000FFu)
#define CSL_I2C_ICDXR_D_SHIFT (0x00000000u)
#define CSL_I2C_ICDXR_D_RESETVAL (0x00000000u)
#define CSL_I2C_ICDXR_RESETVAL (0x00000000u)
/* ICMDR */
#define CSL_I2C_ICMDR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICMDR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICMDR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_NACKMOD_MASK (0x00008000u)
#define CSL_I2C_ICMDR_NACKMOD_SHIFT (0x0000000Fu)
#define CSL_I2C_ICMDR_NACKMOD_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_FREE_MASK (0x00004000u)
#define CSL_I2C_ICMDR_FREE_SHIFT (0x0000000Eu)
#define CSL_I2C_ICMDR_FREE_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_STT_MASK (0x00002000u)
#define CSL_I2C_ICMDR_STT_SHIFT (0x0000000Du)
#define CSL_I2C_ICMDR_STT_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_STP_MASK (0x00000800u)
#define CSL_I2C_ICMDR_STP_SHIFT (0x0000000Bu)
#define CSL_I2C_ICMDR_STP_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_MST_MASK (0x00000400u)
#define CSL_I2C_ICMDR_MST_SHIFT (0x0000000Au)
#define CSL_I2C_ICMDR_MST_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_TRX_MASK (0x00000200u)
#define CSL_I2C_ICMDR_TRX_SHIFT (0x00000009u)
#define CSL_I2C_ICMDR_TRX_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_XA_MASK (0x00000100u)
#define CSL_I2C_ICMDR_XA_SHIFT (0x00000008u)
#define CSL_I2C_ICMDR_XA_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_RM_MASK (0x00000080u)
#define CSL_I2C_ICMDR_RM_SHIFT (0x00000007u)
#define CSL_I2C_ICMDR_RM_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_DLB_MASK (0x00000040u)
#define CSL_I2C_ICMDR_DLB_SHIFT (0x00000006u)
#define CSL_I2C_ICMDR_DLB_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_IRS_MASK (0x00000020u)
#define CSL_I2C_ICMDR_IRS_SHIFT (0x00000005u)
#define CSL_I2C_ICMDR_IRS_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_STB_MASK (0x00000010u)
#define CSL_I2C_ICMDR_STB_SHIFT (0x00000004u)
#define CSL_I2C_ICMDR_STB_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_FDF_MASK (0x00000008u)
#define CSL_I2C_ICMDR_FDF_SHIFT (0x00000003u)
#define CSL_I2C_ICMDR_FDF_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_BC_MASK (0x00000007u)
#define CSL_I2C_ICMDR_BC_SHIFT (0x00000000u)
#define CSL_I2C_ICMDR_BC_RESETVAL (0x00000000u)
#define CSL_I2C_ICMDR_RESETVAL (0x00000000u)
/* ICIVR */
#define CSL_I2C_ICIVR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICIVR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICIVR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICIVR_TESTMD_MASK (0x00000F00u)
#define CSL_I2C_ICIVR_TESTMD_SHIFT (0x00000008u)
#define CSL_I2C_ICIVR_TESTMD_RESETVAL (0x00000000u)
#define CSL_I2C_ICIVR_INTCODE_MASK (0x00000007u)
#define CSL_I2C_ICIVR_INTCODE_SHIFT (0x00000000u)
#define CSL_I2C_ICIVR_INTCODE_RESETVAL (0x00000000u)
/*----INTCODE Tokens----*/
#define CSL_I2C_ICIVR_INTCODE_NONE (0x00000000u)
#define CSL_I2C_ICIVR_INTCODE_AL (0x00000001u)
#define CSL_I2C_ICIVR_INTCODE_NACK (0x00000002u)
#define CSL_I2C_ICIVR_INTCODE_RAR (0x00000003u)
#define CSL_I2C_ICIVR_INTCODE_RDR (0x00000004u)
#define CSL_I2C_ICIVR_INTCODE_TDR (0x00000005u)
#define CSL_I2C_ICIVR_INTCODE_SCD (0x00000006u)
#define CSL_I2C_ICIVR_INTCODE_AAS (0x00000007u)
#define CSL_I2C_ICIVR_RESETVAL (0x00000000u)
/* ICEMDR */
#define CSL_I2C_ICEMDR_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICEMDR_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICEMDR_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICEMDR_BCM_MASK (0x00000001u)
#define CSL_I2C_ICEMDR_BCM_SHIFT (0x00000000u)
#define CSL_I2C_ICEMDR_BCM_RESETVAL (0x00000001u)
#define CSL_I2C_ICEMDR_RESETVAL (0x00000001u)
/* ICPSC */
#define CSL_I2C_ICPSC_RESERVED_MASK (0xFFFF0000u)
#define CSL_I2C_ICPSC_RESERVED_SHIFT (0x00000010u)
#define CSL_I2C_ICPSC_RESERVED_RESETVAL (0x00000000u)
#define CSL_I2C_ICPSC_IPSC_MASK (0x000000FFu)
#define CSL_I2C_ICPSC_IPSC_SHIFT (0x00000000u)
#define CSL_I2C_ICPSC_IPSC_RESETVAL (0x00000000u)
#define CSL_I2C_ICPSC_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiInit.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ===========================================================================
*/
/**
* @file csl_hpiInit.c
*
* @path $(CSLPATH)\src\hpi
*
* @brief File for functional layer of CSL API @a CSL_hpiInit()
*
*/
#include <csl_hpi.h>
/** ============================================================================
* @n@b CSL_hpiInit
*
* @b Description
* @n This is the initialization function for the hpi CSL. The function
* must be called before calling any other API from this CSL. This
* function is idem-potent. Currently, the function just return status
* CSL_SOK, without doing anything.
*
* @b Arguments
* @verbatim
pContext Pointer to module-context. As HPI doesn't have
any context based information user is expected to pass NULL.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Status status;
...
status = CSL_hpiInit(NULL);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_hpiInit, ".text:csl_section:hpi");
CSL_Status CSL_hpiInit (
CSL_HpiContext *pContext
)
{
pContext = pContext;
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotHwControl.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_memprotHwControl.c
*
* @path $(CSLPATH)\src\memprot
*
* @desc File for functional layer of CSL API CSL_memprotHwControl ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 16-Jul-2004 <NAME> File Created
*
* 16-Nov-2005 ds Updated the documentation
* =============================================================================
*/
#include <csl_memprot.h>
#include <csl_memprotAux.h>
/** ===========================================================================
* @n@b CSL_memprotHwControl
*
* @b Description
* @n Control operations for the Memory protection registers.
* For a particular control operation, the pointer to the corresponding
* data type needs to be passed as argument HwControl function Call.
* All the arguments (Structure elements included) passed to the
* HwControl function are inputs. For the list of commands supported and
* argument type that can be @a void* casted & passed with a particular
* command refer to @a CSL_MemprotHwControlCmd.
*
* @b Arguments
* @verbatim
hMemprot Handle to the MEMPROT instance
cmd The command to this API indicates the action to be
taken on MEMPROT.
arg An optional argument.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_ESYS_FAIL - Invalid instance number
* @li CSL_ESYS_INVPARAMS - Invalid Parameter
*
* <b> Pre Condition </b>
* @n Both @a CSL_memprotInit() and @a CSL_memprotOpen() must be called
* successfully in that order before @a CSL_memprotHwControl() can be
* called. For the argument type that can be @a void* casted & passed
* with a particular command refer to @a CSL_MemprotHwControlCmd
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of MEMPROT.
*
* @b Example
* @verbatim
#define PAGE_ATTR 0xFFF0
Uint16 pageAttrTable[10] = {PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,
PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR};
Uint32 key[2] = {<KEY>};
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
CSL_MemprotHwSetup L2MpSetup,L2MpGetSetup;
CSL_MemprotLockStatus lockStat;
CSL_MemprotPageAttr pageAttr;
CSL_MemprotFaultStatus queryFaultStatus;
// Initializing the module
CSL_memprotInit(NULL);
// Opening the Handle for the L2
hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status);
L2MpSetup. memPageAttr = pageAttrTable;
L2MpSetup.numPages = 10;
L2MpSetup.key = key;
// Do Setup for the L2 Memory protection/
CSL_memprotHwSetup (hmpL2,&L2MpSetup);
// Query Lock Status
CSL_memprotGetHwStatus(hmpL2,CSL_MEMPROT_QUERY_LOCKSTAT,&lockStat);
// Unlock the Unit if Locked
if ((lockStat == CSL_MEMPROT_LOCKSTAT_LOCK)
|| (lockStat == CSL_MEMPROT_LOCKSTAT_UNLOCK)) {
CSL_memprotHwControl(hmpL2,CSL_MEMPROT_CMD_UNLOCK,key);
}
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_memprotHwControl, ".text:csl_section:memprot");
CSL_Status CSL_memprotHwControl (
CSL_MemprotHandle hMemprot,
CSL_MemprotHwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK;
if (hMemprot == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if ((arg == NULL) && ((cmd >= 0) && \
(cmd <= CSL_MEMPROT_CMD_PAGEATTR))){
status = CSL_ESYS_INVPARAMS;
}
else {
switch (cmd) {
case CSL_MEMPROT_CMD_LOCK:
status = CSL_memprotLock(hMemprot, (Uint32 *)(arg));
break;
case CSL_MEMPROT_CMD_UNLOCK:
status = CSL_memprotUnLock(hMemprot, (Uint32 *)(arg));
break;
case CSL_MEMPROT_CMD_PAGEATTR:
CSL_memprotSetPageAttr(hMemprot,
((CSL_MemprotPageAttr *)arg)->page,
((CSL_MemprotPageAttr *)arg)->attr);
break;
default:
status = CSL_ESYS_INVCMD;
break;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/vcp2/vcp2_hard_decisions/src/Vcp2_hard_decisions_example.c | /* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file Vcp2_hard_decisions_example.c
*
* @path $(CSLPATH)\example\vcp2\vcp2_hard_decisions\src
*
* @desc Example of usage of CSL of VCP2
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Description </b>
* This is an example for the VCP2 CSL usage for computing hard decision
* against the given branch metric values.
*
* @n The branch metrics are transferred to the VCP and hard decisions are
* read from the VCP using EDMA.
* @verbatim
1. Configure the 2 EDMA channels
2. Configure the input configuration registers of VCP
3. Enable EDMA channels
4. Start VCP
5. Wait until VCP run is complete
@endverbatim
*=============================================================================
*
* @n <b> Procedure to run the example </b>
* @verbatim
1. Configure the CCS setup
2. Please refer CCS manual for setup configuration and loading
proper GEL file
3. Launch CCS window
4. Open project Vcp2_hard_decisions_example.pjt
5. Build the project and load the .out file of the project.
@endverbatim
*
*
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 20-May-2005 SPrasad File Created.
* 25-Jul-2005 Chandra Updated to a new version of EDMA 3.x
* 01-Aug-2005 Chandra Beautified
* 11-Aug-2005 Chandra Minor format changes.
* 14-Sep-2005 Chandra Changes after review.
* 19-Dec-2005 SD Added clearing the EDMA error registers before
* enabling the channel
* 06-Feb-2006 SD Changes according to spec changes
* 24-Feb-2006 DS Added clearing of EDMA channel error registers at
* the end of example
* ============================================================================
*/
#include <csl_vcp2.h>
#include <csl_vcp2Aux.h>
#include <csl_edma3.h>
#include <soc.h>
#include <stdio.h>
#include <string.h>
#include <Vcp2_example.h>
#include <cslr_dev.h>
#define BITS_IN_A_BYTE 8
/* Constraint length */
#define CONSTRAINT_LEN 5
/* Frame length */
#define FRAME_LENGTH 300
/* EDMA frame size */
#define DMA_BURST_SIZE 128
/* VCP input configuration transfer size */
#define VCPIC_DMA_SIZE 24
/* VCP out register transfer size */
#define VCPOUT_DMA_SIZE 8
/* Forward declarations */
Uint16 vcp2_configEdma (Uint32 inputBM, Uint32 outputHD
);
/* EDMA global declarations */
CSL_Edma3Context context;
CSL_Edma3ChannelObj ChObj, ChObj1;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelHandle hChannel, hChannel1;
CSL_Edma3ParamHandle hParam[4]; /* Example uses 4 PaRAMs */
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3ChannelAttr chParam, chParam1;
CSL_Edma3ChannelErr chErrClear;
/* Globals */
VCP2_ConfigIc vcpConfig;
Uint32 ouputParams[2];
VCP2_ConfigIc vcpConfigRead;
/**
* ============================================================================
* @func main
* @desc
* Shows the usage of VCP2 CSL API for computing the hard decisions.
* @n Various parameters of the input data (Branch metrics) provided
* are as follows.
* @verbatim
Frame length...................................300
rate...........................................1/3
constraint length..............................5
Decision mode..................................Hard
Traceback Mode.................................Convergent
Index of the initial max state metric(IMAXI)...0
output parameters read flag....................0
Yamamoto bit enable............................False
Yamamote threshold.............................N/A
Traceback state enable.........................False
Traceback state index..........................N/A
DSP endian.....................................Little
Endian Register................................bm_endian
Output order...................................0
@endverbatim
* @expected result
* Appropriate message will be logged depending on
* the result
*
* ============================================================================
*/
void
main (
)
{
Uint32 numSymProc, inputBM, outputHD, outputHD_bytes, outputHD_words;
VCP2_Params vcpParams;
VCP2_BaseParams vcpBaseParams;
volatile Uint32 runStat;
int index;
/* Enable the VCP2 in power saver */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK);
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_VCPCTL, ENABLE);
while (CSL_DEV_PERSTAT0_VCPSTAT_ENABLE !=
CSL_FEXT (((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_VCPSTAT));
/* VCP configuration */
vcpBaseParams.rate = VCP2_RATE_1_3;
vcpBaseParams.constLen = CONSTRAINT_LEN;
vcpBaseParams.frameLen = FRAME_LENGTH;
vcpBaseParams.yamTh = 0;
vcpBaseParams.stateNum = 0;
vcpBaseParams.tbConvrgMode = TRUE;
vcpBaseParams.decision = VCP2_DECISION_HARD;
vcpBaseParams.readFlag = 1;
vcpBaseParams.tailBitEnable = FALSE;
vcpBaseParams.traceBackIndex = 0;
vcpBaseParams.outOrder = 0;
/* VCP configuration */
VCP2_genParams (&vcpBaseParams, &vcpParams);
VCP2_genIc (&vcpParams, &vcpConfig);
/* Number of EDMA frames (transfers) for the branch metrics */
inputBM = vcpParams.numBmFrames;
/* Output hard decisions in terms of bytes rounded to upper byte */
outputHD_bytes =
VCP2_normalCeil (vcpBaseParams.frameLen + vcpBaseParams.constLen - 1,
BITS_IN_A_BYTE);
/* Output hard decisions in terms of words rounded to upper words */
outputHD_words = VCP2_normalCeil (outputHD_bytes, sizeof (Uint32));
/* Total number of bytes required to be transfered for the hard decisions */
outputHD = outputHD_words * sizeof (Uint32);
/* Configure EDMA */
if (!(vcp2_configEdma (inputBM, outputHD))) {
printf ("\nError in configuring EDMA\n");
return;
}
/* clear the EDMA error registers */
chErrClear.missed = TRUE;
chErrClear.secEvt = TRUE;
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
/* Enable Channel */
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL);
/* Enable Channel */
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL);
/* write to the endian register */
VCP2_setPacked32Endian ();
/* Reset and Start VCP2 */
VCP2_reset ();
VCP2_emuDisable ();
VCP2_start ();
/* Wait till processing is over */
do {
runStat = VCP2_statRun ();
} while (runStat == 1);
printf ("VCP2 processing of data over\n");
printf ("\nRESULT\n");
printf ("~~~~~~\n");
/* Get the number of symbols processed */
numSymProc = VCP2_statSymProc ();
printf ("Number of symbols processed = %d \n", numSymProc);
/* Verify the hard decisions output */
for (index = 0; index < ((vcpParams.frameLen / BITS_IN_A_BYTE)/4); index++) {
if (hard_decision [index] != hard_decisionRef [index]) {
break;
}
}
if (index == ((vcpParams.frameLen / BITS_IN_A_BYTE)/4)) {
printf ("\nHard decisions are computed properly\n");
}
else {
printf ("\nHard decisions are not computed properly %d\n", index);
}
/* clear the EDMA error registers */
chErrClear.missed = TRUE;
chErrClear.secEvt = TRUE;
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
/* Close EDMA channel */
CSL_edma3ChannelClose (hChannel);
CSL_edma3ChannelClose (hChannel1);
}
/*
* ============================================================================
* @func vcp2_configEdma
* @desc
* Configures EDMA channels 28 and 29.
* @n For channel 29 there are 2 param entries(0 &1) which are linked.
* @n - Link 0 transfers the VCP2 input configuration register values.
* @n - Link 1 transfers Branch metrics.
* @n
* @n For channel 28 there 2 param entry (2 & 3).
* @n - Link 2 transfers the Hard decisions.
* @n - Link 3 transfers the VCPOUT values
*
* @expected result
* Appropriate message will be logged depending on
* the result
*
* @eg
* vcp2_configEdma(inputBm, ouputHD);
* ============================================================================
*/
Uint16
vcp2_configEdma (
Uint32 inputBM,
Uint32 outputHD
)
{
CSL_Status chStatus, chStatus1;
Uint32 receive_link_offset, transmit_link_offset;
/* EDMA Initialization */
CSL_edma3Init (&context);
CSL_edma3Open (&edmaObj, CSL_EDMA3, NULL, &chStatus);
/* Channel Configuration for VCPXEVT event */
/* Channel Open */
chParam.regionNum = CSL_EDMA3_REGION_GLOBAL;
chParam.chaNum = CSL_EDMA3_CHA_VCP2XEVT;
hChannel = CSL_edma3ChannelOpen (&ChObj, CSL_EDMA3, &chParam, &chStatus);
if ((chStatus != CSL_SOK) || (hChannel == NULL)) {
printf ("Error in EDMA channel open function\n");
return 0;
}
/* Channel Setup */
if (CSL_SOK != CSL_edma3HwChannelSetupParam (hChannel,
0 /* PaRAM entry */ )) {
printf ("Error in Tx EDMA channel setup\n");
return 0;
}
if (CSL_SOK != CSL_edma3HwChannelSetupQue (hChannel,
CSL_EDMA3_QUE_0)) {
printf ("Error in Tx EDMA channel setup\n");
return 0;
}
/* Channel Configuration for VCPREVT event */
/* Channel Open */
chParam1.regionNum = CSL_EDMA3_REGION_GLOBAL;
chParam1.chaNum = CSL_EDMA3_CHA_VCP2REVT;
hChannel1 =
CSL_edma3ChannelOpen (&ChObj1, CSL_EDMA3, &chParam1, &chStatus1);
if ((chStatus1 != CSL_SOK) | (hChannel1 == NULL)) {
printf ("Error in EDMA channel open function\n");
return 0;
}
/* Channel Setup */
if (CSL_SOK != CSL_edma3HwChannelSetupParam (hChannel1,
2 /* PaRAM entry */ )) {
printf ("Error in Rx EDMA channel setup\n");
return 0;
}
if (CSL_SOK != CSL_edma3HwChannelSetupQue (hChannel1,
CSL_EDMA3_QUE_0)) {
printf ("Error in Rx EDMA channel setup\n");
return 0;
}
/* Using PaRAMs 0, 1, 2, 3 */
/* 0 and 1 are to transmit */
/* 2 and 3 are to receive */
hParam[0] = CSL_edma3GetParamHandle (hChannel, 0, &chStatus);
hParam[1] = CSL_edma3GetParamHandle (hChannel, 1, &chStatus);
hParam[2] = CSL_edma3GetParamHandle (hChannel1, 2, &chStatus);
hParam[3] = CSL_edma3GetParamHandle (hChannel1, 3, &chStatus);
/* Lower 4 nibbles of the PaRAM address forms the link offset */
/* PaRAMs 0 and 1 are linked */
transmit_link_offset = (Uint32)hParam[1] & 0x0000FFFF;
/* PaRAMs 2 and 3 are linked */
receive_link_offset = (Uint32)hParam[3] & 0x0000FFFF;
/*
* itcchEn - False
* tcchEn - False
* itcintEn - False
* tcintEn - False
* tcc - 0
* tccMode - Normal completion (interrupt after transfer completion)
* fwid - SAM, DAM are to increment, so fwid = none
* stat - 0, linking allowed
* syncDim - A - synchronization
* dam - Destination address increment
* sam - Source address increment
*/
myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0,
CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,
CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_INCR); /* Options */
myParamSetup.srcAddr = (Uint32) & vcpConfig; /* Source address */
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (VCPIC_DMA_SIZE, 1);
/* Single transfer of VCPIC_DMA_SIZE bytes */
myParamSetup.dstAddr = (Uint32) &hVcp2Vbus->VCPIC0; /* Destination address */
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE (0, 0);
/* Index do not care */
myParamSetup.linkBcntrld =
CSL_EDMA3_LINKBCNTRLD_MAKE (transmit_link_offset, 0); /* linking */
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE (0, 0);
/* Index do not care */
myParamSetup.cCnt = 1; /* CCount is 1 */
if (CSL_SOK != CSL_edma3ParamSetup (hParam[0], &myParamSetup)) {
printf ("Error in EDMA paRam setup for VCP IC register transfer\n");
return 0;
}
transmit_link_offset = (Uint32)hParam[2] & 0x0000FFFF;
/* Setup link to transmit branch metrics */
/*
* itcchEn - False
* tcchEn - False
* itcintEn - False
* tcintEn - False
* tcc - 0
* tccMode - Normal completion (interrupt after transfer completion)
* fwid - 64-bit
* stat - 0, linking allowed
* syncDim - A - synchronization
* dam - Destination is a FIFO
* sam - Source address increment
*/
myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0,
CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_64BIT, FALSE,
CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_CONST,
CSL_EDMA3_ADDRMODE_INCR); /* Options */
myParamSetup.srcAddr = (Uint32) branch_metric; /* Source address */
/* Source address increment */
myParamSetup.dstAddr = (Uint32) & (hVcp2Vbus->VCPWBM);
/* Destination address */
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (DMA_BURST_SIZE, inputBM);
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE (DMA_BURST_SIZE, 0);
myParamSetup.linkBcntrld =
CSL_EDMA3_LINKBCNTRLD_MAKE (CSL_EDMA3_LINK_NULL, 0);
/* No linking */
/* inputBM transfers of DMA_BURST_SIZE bytes */
myParamSetup.cCnt = 1; /* CCount is 1 */
if (CSL_SOK != CSL_edma3ParamSetup (hParam[1], &myParamSetup)) {
printf ("Error in EDMA paRam setup for branch metrics transfer\n");
return 0;
}
/*
* itcchEn - False
* tcchEn - False
* itcintEn - False
* tcintEn - False
* tcc - 0
* tccMode - Normal completion (interrupt after transfer completion)
* fwid - 64-bit
* stat - 0, linking allowed
* syncDim - A - synchronization
* dam - Destination to increment
* sam - Source is a FIFO
*/
myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0,
CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_64BIT, FALSE,
CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_CONST); /* Options */
myParamSetup.srcAddr = (Uint32)&(hVcp2Vbus->VCPRDECS); /* Source */
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (outputHD, 1);
/* outputHD bytes in a transfer */
myParamSetup.dstAddr = (Uint32) hard_decision; /* Destination */
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE (0, outputHD);
myParamSetup.linkBcntrld =
CSL_EDMA3_LINKBCNTRLD_MAKE (receive_link_offset, 0); /* linking */
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE (0, 0);
/* Index do not care */
myParamSetup.cCnt = 1; /* CCount */
if (CSL_SOK != CSL_edma3ParamSetup (hParam[2], &myParamSetup)) {
printf ("Error in EDMA paRam setup for decisions read\n");
return 0;
}
/*
* itcchEn - False
* tcchEn - False
* itcintEn - False
* tcintEn - False
* tcc - 0
* tccMode - Normal completion (interrupt after transfer completion)
* fwid - SAM, DAM are to increment, so fwid = none
* stat - 0, linking allowed
* syncDim - A - synchronization
* dam - Destination address increment
* sam - Source address increment
*/
myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0,
CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,
CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_INCR); /* Options */
myParamSetup.srcAddr = (Uint32) & (hVcp2Vbus->VCPOUT1); /* Source */
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (VCPOUT_DMA_SIZE, 1);
/* Transfer of VCPOUT_DMA_SIZE bytes 1 time */
myParamSetup.dstAddr = (Uint32) & ouputParams[0]; /* Destination */
myParamSetup.linkBcntrld =
CSL_EDMA3_LINKBCNTRLD_MAKE (CSL_EDMA3_LINK_NULL, 0);
/* No linking */
if (CSL_SOK != CSL_edma3ParamSetup (hParam[3], &myParamSetup)) {
printf ("Error in EDMA paRam setup for output registers read\n");
return 0;
}
return 1;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3HwControl.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3HwControl.c
*
* @path $(CSLPATH)\src\edma
*
* @desc File for functional layer of CSL API CSL_edma3HwControl()
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* =============================================================================
*/
#include <csl_edma3.h>
#include <csl_edma3Aux.h>
/** ============================================================================
* @n@b CSL_edma3HwControl
*
* @b Description
* @n Takes a command with an optional argument & implements it. This function
* is used to carry out the different operations performed by EDMA.
*
* @b Arguments
* @verbatim
hMod Edma module Handle
cmd The command to this API which indicates the
action to be taken
cmdArg Pointer arguement specific to the command
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command execution successful
* @li CSL_ESYS_BADHANDLE - The handle passed is
* invalid
* @li CSL_ESYS_INVCMD - The command passed is invalid
*
* <b> Pre Condition </b>
* @n Functions CSL_edma3Init(), CSL_edma3Open() must be called successfully
* in that order before this API can be invoked
*
* <b> Post Condition </b>
* @n Edma registers are configured according to the command and
* the command arguments. The command determines which registers are
* modified.
*
* @b Modifies
* @n Edma registers determined by the command
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i,passStatus = 1;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Query Module Info
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INFO,&info);
// DRAE Enable(Bits 0-15) for the Shadow Region 0.
regionAccess.region = CSL_EDMA3_REGION_0 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3HwControl, ".text:csl_section:edma3");
CSL_Status CSL_edma3HwControl (
CSL_Edma3Handle hMod,
CSL_Edma3HwControlCmd cmd,
void *cmdArg
)
{
CSL_Status status = CSL_SOK;
if (hMod == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (((cmd >= 0) && (cmd <= CSL_EDMA3_CMD_EVENTMISSED_CLEAR)) &&
((cmd != CSL_EDMA3_CMD_MEMFAULT_CLEAR) &&
(cmd != CSL_EDMA3_CMD_ERROR_EVAL)) && (cmdArg == NULL)) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch(cmd) {
#if CSL_EDMA3_MEMPROTECT
case CSL_EDMA3_CMD_MEMPROTECT_SET:
status = CSL_edma3SetMemoryProtectionAttrib(hMod, \
((CSL_Edma3CmdRegion*)cmdArg)->region,\
((CSL_Edma3CmdRegion*)cmdArg)->regionVal);
break;
case CSL_EDMA3_CMD_MEMFAULT_CLEAR:
status = CSL_edma3MemFaultClear(hMod);
break;
#endif
case CSL_EDMA3_CMD_DMAREGION_ENABLE:
status = CSL_edma3DmaRegionAccessEnable(hMod, \
((CSL_Edma3CmdDrae*)cmdArg)->region, \
((CSL_Edma3CmdDrae*)cmdArg)->drae, \
((CSL_Edma3CmdDrae*)cmdArg)->draeh);
break;
case CSL_EDMA3_CMD_DMAREGION_DISABLE:
status = CSL_edma3DmaRegionAccessDisable(hMod, \
((CSL_Edma3CmdDrae*)cmdArg)->region, \
((CSL_Edma3CmdDrae*)cmdArg)->drae, \
((CSL_Edma3CmdDrae*)cmdArg)->draeh);
break;
case CSL_EDMA3_CMD_QDMAREGION_ENABLE:
status = CSL_edma3QdmaRegionAccessEnable(hMod, \
((CSL_Edma3CmdQrae*)cmdArg)->region,\
((CSL_Edma3CmdQrae*)cmdArg)->qrae);
break;
case CSL_EDMA3_CMD_QDMAREGION_DISABLE:
status = CSL_edma3QdmaRegionAccessDisable(hMod, \
((CSL_Edma3CmdQrae*)cmdArg)->region, \
((CSL_Edma3CmdQrae*)cmdArg)->qrae);
break;
case CSL_EDMA3_CMD_QUEPRIORITY_SET:
status = CSL_edma3EventQueuePrioritySet(hMod, \
((CSL_Edma3CmdQuePri*)cmdArg)->que, \
((CSL_Edma3CmdQuePri*)cmdArg)->pri);
break;
case CSL_EDMA3_CMD_QUETHRESHOLD_SET:
status = CSL_edma3EventQueueThresholdSet(hMod,\
((CSL_Edma3CmdQueThr*)cmdArg)->que, \
((CSL_Edma3CmdQueThr*)cmdArg)->threshold);
break;
case CSL_EDMA3_CMD_ERROR_EVAL:
status = CSL_edma3ErrorEval(hMod);
break;
case CSL_EDMA3_CMD_INTRPEND_CLEAR:
status = CSL_edma3InterruptClear(hMod, \
((CSL_Edma3CmdIntr*)(cmdArg))->region, \
((CSL_Edma3CmdIntr*)(cmdArg))->intr,\
((CSL_Edma3CmdIntr*)(cmdArg))->intrh);
break;
case CSL_EDMA3_CMD_INTR_ENABLE:
status = CSL_edma3InterruptEnable(hMod, \
((CSL_Edma3CmdIntr*)(cmdArg))->region, \
((CSL_Edma3CmdIntr*)(cmdArg))->intr, \
((CSL_Edma3CmdIntr*)(cmdArg))->intrh);
break;
case CSL_EDMA3_CMD_INTR_DISABLE:
status = CSL_edma3InterruptDisable(hMod, \
((CSL_Edma3CmdIntr*)(cmdArg))->region, \
((CSL_Edma3CmdIntr*)(cmdArg))->intr, \
((CSL_Edma3CmdIntr*)(cmdArg))->intrh);
break;
case CSL_EDMA3_CMD_INTR_EVAL:
status = CSL_edma3InterruptEval(hMod,*((Int*)(cmdArg)));
break;
case CSL_EDMA3_CMD_CTRLERROR_CLEAR:
status = CSL_edma3ControllerErrorClear(hMod, \
((CSL_Edma3CtrlErrStat*)(cmdArg)));
break;
case CSL_EDMA3_CMD_EVENTMISSED_CLEAR:
status = \
CSL_edma3EventsMissedClear(hMod,((CSL_BitMask32*)cmdArg)[0], \
((CSL_BitMask32*)cmdArg)[1],((CSL_BitMask32*)cmdArg)[2]);
break;
default:
status = CSL_ESYS_INVCMD;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/edma/edma2x_example/src/edma_csl2x_example.c | <gh_stars>0
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file edma_csl2x_example.c
*
* @path $(CSLPATH)\example\edma\src
*
* @desc This is an example program for EDMA of CSL 2x
*
* =============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This example Performs EDMA transfers in different modes.
* 1. Sets up the INTC module for use by the EDMA
* 2. Performs a simple memory to memory transfer using EDMA
* 3. Performs a simple memory to memory transfer using QDMA
* 4. Performs a memory to memory transfer that involves linking
* 5. Performs a memory to memory transfer that involves chaining
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Edma_Csl2x_Example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ================
* 28-Jul-2005 Chandra File created.
* 11-Aug-2005 Chandra Minor format changes.
* 16-Dec-2005 DS Updated documentation
* ============================================================================
*/
#include <csl_edma2.h>
#include <stdio.h>
#include <csl_intc.h>
#include <edma_int_dispatcher.h>
/* Macros for buffer sizes */
#define SIMPLE_TRANSFER_SIZE (16)
#define LINK_BUF_SIZE (16)
#define CHAIN_BUF_SIZE (16)
/* Macros to manipulate the TCC and TCCM fields */
#define TCC_SHIFT (16)
#define TCCM_SHIFT (9)
#define TCC_MASK (0x0000000F)
#define TCCM_MASK (0x00000030)
/* LINK and Reload default */
#define NO_RELOAD_AND_LINK (0xFFFF)
/* OPT word value for different transfers */
/*
Simple transfer
Priority - 2
Esize - 3 (1 byte)
2DS - 0 (1 dimensional source)
SUM - 1 (increment source)
2DD - 0 (1 dimensional destination)
DUM - 1 (increment destination)
TCINT - 1 (transfer complete interrupt ON)
TCC, TCCM - ?, 0 (transfer completion code is ?)
A value for TCC is selected in the function.
ATCINT - 0 (alternate transfer completion interrupt OFF)
ATTC - 0 (alternate transfer completion code is 0)
PDTS - 0 (source peripheral device transfer is OFF)
PDTD - 0 (destination peripheral device transfer is OFF)
LINK - 0 (linking is OFF)
FS - 1 (frame synchronization ON)
*/
#define SIMPLE_TRANSFER_OPTIONS (0x51300001)
/*
First of the link transfers
Priority - 2
Esize - 3 (1 byte)
2DS - 0 (1 dimensional source)
SUM - 1 (increment source)
2DD - 0 (1 dimensional destination)
DUM - 1 (increment destination)
TCINT - 0 (transfer complete interrupt ON)
TCC, TCCM - ?, 0 (transfer completion code is ?)
ATCINT - 0 (alternate transfer completion interrupt OFF)
ATTC - 0 (alternate transfer completion code is 0)
PDTS - 0 (source peripheral device transfer is OFF)
PDTD - 0 (destination peripheral device transfer is OFF)
LINK - 1 (linking is ON)
FS - 1 (frame synchronization ON)
*/
#define LINK_OPTIONS_WITH_LINK (0x45300003)
/*
Last transfer of the link transfers
Priority - 2
Esize - 3 (1 byte)
2DS - 0 (1 dimensional source)
SUM - 1 (increment source)
2DD - 0 (1 dimensional destination)
DUM - 1 (increment destination)
TCINT - 0 (transfer complete interrupt ON)
TCC, TCCM - ?, 0 (transfer completion code is ?)
ATCINT - 0 (alternate transfer completion interrupt OFF)
ATTC - 0 (alternate transfer completion code is 0)
PDTS - 0 (source peripheral device transfer is OFF)
PDTD - 0 (destination peripheral device transfer is OFF)
LINK - 0 (linking is OFF)
FS - 1 (frame synchronization ON)
*/
#define LINK_OPTIONS_WITH_OUT_LINK (0x45300001)
/*
Chained Transfer
Priority - 2
Esize - 3 (1 byte)
2DS - 0 (1 dimensional source)
SUM - 1 (increment source)
2DD - 0 (1 dimensional destination)
DUM - 1 (increment destination)
TCINT - 0 (transfer complete interrupt ON)
TCC, TCCM - ?, 0 (transfer completion code is ?)
ATCINT - 0 (alternate transfer completion interrupt OFF)
ATTC - 0 (alternate transfer completion code is 0)
PDTS - 0 (source peripheral device transfer is OFF)
PDTD - 0 (destination peripheral device transfer is OFF)
LINK - 0 (linking is OFF)
FS - 1 (frame synchronization ON)
*/
#define CHAIN_OPTIONS (0x45300001)
/*
QDMA transfer
PRI - 2
ESIZE - 0 : 4 byte transfers
2DS - 0 : 1-d source
SUM - 1 : Increment source address
2DD - 0 : 1-d destination
DUM - 1 : Increment destination address
FS - 1 : Transfer is frame synchronized
CNT = No. of elements to be transferred = Buffer size / size of tx element
See section 1.16.1 of 'spru234.pdf'
*/
#define QDMA_OPTIONS (0x41300001)
/* forward declarations */
void transfer_example (void);
static void isr (int tccNum);
static void isr2 (int tccNum);
void eventEdmaHandler (void *handle);
void configure_intc (void);
void link_example (void);
void chain_example (void);
void qdma_example (void);
void configure_intc (void);
/* Global */
/* Flags used in the ISRs */
volatile Uint32 isr_cnt = 0;
volatile Uint32 parent_isr_cnt = 0;
/* Data structures for INTC configuration */
CSL_IntcContext intcContext;
CSL_IntcEventHandlerRecord EventHandler[1];
/* Allocation of buffers to use in the transfers */
static Uint8 src[SIMPLE_TRANSFER_SIZE];
static Uint8 dst[SIMPLE_TRANSFER_SIZE];
static Uint8 link_src1[LINK_BUF_SIZE];
static Uint8 link_src2[LINK_BUF_SIZE];
static Uint8 link_dst1[LINK_BUF_SIZE];
static Uint8 link_dst2[LINK_BUF_SIZE];
static Uint8 chain_src1[CHAIN_BUF_SIZE];
static Uint8 chain_src2[CHAIN_BUF_SIZE];
static Uint8 chain_dst1[CHAIN_BUF_SIZE];
static Uint8 chain_dst2[CHAIN_BUF_SIZE];
/**
* ============================================================================
* @func main
*
* @desc
* This is the main routine of this file that invokes the individual
* example routines
* ============================================================================
*/
void main (void)
{
/* First configure the interupts */
configure_intc ();
/* Simple transfer example */
transfer_example ();
/* Transfer example using the QDMA */
qdma_example ();
/* Transfer example using link feature */
link_example ();
/* Transfer example using chain feature */
chain_example ();
/* Clean up */
EDMA_resetAll ();
EDMA_intResetAll ();
}
/* ISR to handle TCC interrupt */
static void isr (
Int tccNum
)
{
isr_cnt++;
}
/* Another ISR to handle TCC interrupt */
static void isr2 (
Int tccNum
)
{
parent_isr_cnt++;
}
/**
* ============================================================================
* @func transfer_example
*
* @desc
* This performs a simple EDMA memory to memory transfer.
*
* @n <b> Procedure </b>
* @verbatim
1. Enables a channel
2. Configures it
3. Allocates and configures an EDMA channel interrupt
4. Sets up the interrupt and ISR
4. Initiates the transfer
5. Waits for completion of ISR
6. Verifies the transfer
7. Cleans up
@endverbatim
* ============================================================================
*/
void transfer_example (void)
{
EDMA_Handle handle;
Uint32 chan_no;
EDMA_Config conf = { 0 };
Uint32 index;
Uint32 tcc;
/* Setup the source and destination memory areas */
for (index = 0; index < SIMPLE_TRANSFER_SIZE; index++) {
src[index] = index;
dst[index] = 0;
}
/* Reset all interrupts of all channels of EDMA */
EDMA_intResetAll ();
/* Consider the channel 4 of EDMA */
chan_no = 4;
handle = EDMA_open (chan_no, EDMA_OPEN_RESET);
/* Choose the same TCC as the channel */
tcc = EDMA_intAlloc (chan_no);
if (tcc != chan_no) {
printf ("Error in allocating TCC\n");
return;
}
/* Setup the config structure */
conf.opt =
SIMPLE_TRANSFER_OPTIONS | ((tcc & TCC_MASK) << TCC_SHIFT) | ((tcc &
TCCM_MASK) << TCCM_SHIFT);
conf.cnt = SIMPLE_TRANSFER_SIZE;
conf.idx = 0; /* 1-d source, 1-d destination, address
increment for both, so
FRMIDX = ELEIDX = don't care */
conf.rld = NO_RELOAD_AND_LINK;
conf.dst = (Uint32) & dst[0];
conf.src = (Uint32) & src[0];
printf
("EDMA: Example ... Config. a memory to memory transfer of %d bytes\n",
SIMPLE_TRANSFER_SIZE);
EDMA_config (handle, &conf);
/* Setup the ISR */
edmaEventHook (chan_no, isr);
/* Enable EDMA interrupt for the selected channel */
EDMA_intEnable (chan_no);
printf ("EDMA: Example ... Initiating the transfer\n");
EDMA_setChannel (handle); /* Set event register, this should result in
interrupt */
/* Wait for the ISR to run */
while (1) {
if (isr_cnt > 0) {
isr_cnt = 0;
break;
}
}
printf ("EDMA: Example ... Data transfer is complete\n");
/* Verify the transferred data */
for (index = 0; index < SIMPLE_TRANSFER_SIZE; index++) {
if (src[index] != dst[index]) {
break;
}
}
if (index == SIMPLE_TRANSFER_SIZE) {
printf ("EDMA: Example ... Data transferred correctly\n");
}
else {
printf ("EDMA: Example ... Data not transferred correctly\n");
return;
}
/* Clean up */
EDMA_intReset (tcc);
EDMA_intFree (tcc);
EDMA_close (handle);
printf ("EDMA: Simple Example ... DONE\n");
}
/**
* ============================================================================
* @func link_example
*
* @desc
* This performs a EDMA memory to memory transfer in two stages, by link.
*
* @n <b> Procedure </b>
* @verbatim
1. Setup the data destinations and sources for 2 transfers
2. Enable a channel
3. Allocate and configure an interrupt
4. Configure the PaRAM of the channel
5. Allocate and configure another PaRAM for link transfer
6. Link the second PaRAM with the first
7. Start transfer on the channel
8. Verify the data transfer
9. Start the second transfer on the same channel
10. Verify the data transfer
11. Clean up
@endverbatim
* ============================================================================
*/
void link_example (void)
{
EDMA_Handle handle;
EDMA_Handle link_handle;
Uint32 chan_no;
Uint32 tcc;
EDMA_Config conf = { 0 };
Int index;
/* Setup the data area */
for (index = 0; index < LINK_BUF_SIZE; index++) {
link_src1[index] = index;
link_dst1[index] = 0;
link_src2[index] = LINK_BUF_SIZE - index;
link_dst2[index] = 0;
}
/* Reset all interrupts of all channels of EDMA */
EDMA_intResetAll ();
/* Open a channel and allocate a PaRAM for linking */
chan_no = 3; /* Use channel 3 of EDMA */
handle = EDMA_open (chan_no, EDMA_OPEN_RESET);
/* Allocate and enable interrupt of same number as channel */
tcc = EDMA_intAlloc (chan_no);
if (tcc != chan_no) {
printf ("Error in allocating TCC\n");
return;
}
EDMA_intEnable (chan_no);
printf
("EDMA: Link Example ... Config. a 2 stage mem. to mem. transfer\n");
printf ("EDMA: Link Example ... Each transfer of %d bytes\n",
LINK_BUF_SIZE);
printf ("EDMA: Link Example ... Configuring stage 1\n");
conf.opt =
LINK_OPTIONS_WITH_LINK | ((tcc & TCC_MASK) << TCC_SHIFT) | ((tcc &
TCCM_MASK) << TCCM_SHIFT);
conf.cnt = (LINK_BUF_SIZE);
conf.idx = 0; /* 1-d source, 1-d destination, address
increment for both, so
FRMIDX = ELEIDX = don't care */
conf.rld = NO_RELOAD_AND_LINK; /* Linking is done latter in the example */
conf.dst = (Uint32) & link_dst1[0];
conf.src = (Uint32) & link_src1[0];
EDMA_config (handle, &conf);
printf
("EDMA: Link Example ... Alloc. a PaRAM for stage 2 configuration\n");
link_handle = EDMA_allocTable (EDMA_ALLOC_ANY);
printf ("EDMA: Link Example ... Configuring stage 2\n");
conf.opt =
LINK_OPTIONS_WITH_OUT_LINK | ((tcc & TCC_MASK) << TCC_SHIFT) | ((tcc &
TCCM_MASK) << TCCM_SHIFT); /* Same as stage 1 without linking */
conf.cnt = (LINK_BUF_SIZE);
conf.idx = 0; /* 1-d source, 1-d destination, address
increment for both, so
FRMIDX = ELEIDX = don't care */
conf.rld = NO_RELOAD_AND_LINK;
conf.dst = (Uint32) & link_dst2[0];
conf.src = (Uint32) & link_src2[0];
EDMA_config (link_handle, &conf);
printf ("EDMA: Link Example ... Linking the two transfers\n");
EDMA_link (handle, link_handle);
printf ("EDMA: Link Example ... Initiating the transfer 1\n");
/* Setup the ISR for the transfer */
edmaEventHook (chan_no, isr);
EDMA_setChannel (handle); /* Set event register, this should result in
interrupt */
/* Wait for the first transfer */
while (1) {
if (isr_cnt > 0) {
isr_cnt = 0;
break;
}
}
printf
("EDMA: Link Example ... Data transfer of first stage is complete\n");
/* Verify the first data transfer */
for (index = 0; index < LINK_BUF_SIZE; index++) {
if (link_dst1[index] != link_src1[index]) {
break;
}
}
if (index == LINK_BUF_SIZE) {
printf
("EDMA: Link Example ... 1st stage data transferred correctly\n");
}
else {
printf
("EDMA: Link Example ... 1st stage data not transferred correctly\n");
return;
}
printf ("EDMA: Link Example ... Initiating the transfer 2\n");
EDMA_setChannel (handle); /* Set event register, this should result in
interrupt */
/* Wait for the 2nd transfer completion */
while (1) {
if (isr_cnt > 0) {
isr_cnt = 0;
break;
}
}
printf
("EDMA: Link Example ... Data transfer of second stage is complete\n");
/* Verify the 2nd data transfer */
for (index = 0; index < LINK_BUF_SIZE; index++) {
if (link_dst2[index] != link_src2[index]) {
break;
}
}
if (index == LINK_BUF_SIZE) {
printf
("EDMA: Link Example ... 2nd stage data transferred correctly\n");
}
else {
printf
("EDMA: Link Example ... 2nd stage data not transferred correctly\n");
return;
}
/* Clean up */
EDMA_intReset (chan_no);
printf ("EDMA: Link Example ... DONE\n");
EDMA_close (handle);
EDMA_freeTable (link_handle);
EDMA_intFree (tcc);
}
/**
* ============================================================================
* @func chain_example
*
* @desc
* This performs a EDMA memory to memory transfer in two stages, by
* chaining.
*
* @n <b> Procedure </b>
* @verbatim
1. Setup the data destinations and sources for 2 transfers
2. Enable 2 channels
3. Allocate and configure interrupts, such that first channel transfer
is chained to the second channel
4. Configure the PaRAMs of the channels
5. Setup chaining
6. Start transfer on the first channel
7. Wait for the completion of both the tranfers
8. Verify the data transfers
9. Clean up
@endverbatim
* ============================================================================
*/
void chain_example (void)
{
EDMA_Handle handle;
EDMA_Handle chain_handle;
Uint32 chan_no;
Uint32 chain_chan_no;
Uint32 tcc1;
Uint32 tcc2;
EDMA_Config conf = { 0 };
Uint32 index;
/* Setup the data area */
for (index = 0; index < CHAIN_BUF_SIZE; index++) {
chain_src1[index] = index;
chain_dst1[index] = 0;
chain_src2[index] = CHAIN_BUF_SIZE - index;
chain_dst2[index] = 0;
}
/* Reset all interrupts of all channels of EDMA */
EDMA_intResetAll ();
chan_no = 4; /* Consider channel 4 as primary channel */
chain_chan_no = 5; /* Consider channel 5 as second channel in the chain */
/* TCC field of the first channel = second channel number, allocate it */
tcc1 = EDMA_intAlloc (chain_chan_no);
if (tcc1 != chain_chan_no) {
return;
}
/* Enable interrupt and open channel for the first transfer */
EDMA_intEnable (chain_chan_no);
handle = EDMA_open (chan_no, EDMA_OPEN_RESET);
printf
("EDMA: Chain Example ... Config. a 2 stage mem to mem transfer\n");
printf ("EDMA: Chain Example ... Each transfer of %d bytes\n",
CHAIN_BUF_SIZE);
printf ("EDMA: Chain Example ... Configuring stage 1\n");
conf.opt = CHAIN_OPTIONS; /* EDMA_chian will set the TCC */
conf.cnt = (CHAIN_BUF_SIZE); /* Frame Count is 0 */
conf.idx = 0; /* 1-d source, 1-d destination, address
increment for both, so
FRMIDX = ELEIDX = don't care */
conf.rld = NO_RELOAD_AND_LINK;
conf.dst = (Uint32) & chain_dst1[0];
conf.src = (Uint32) & chain_src1[0];
EDMA_config (handle, &conf);
/* Open the channel for the second transfer */
chain_handle = EDMA_open (chain_chan_no, EDMA_OPEN_RESET);
tcc2 = EDMA_intAlloc (6); /* Allocate EDMA interrupt 6 for the 2nd
transfer completion */
if (tcc2 != 6) {
return;
}
printf ("EDMA: Chain Example ... Configuring stage 2\n");
conf.opt =
CHAIN_OPTIONS | ((tcc2 & TCC_MASK) << TCC_SHIFT) | ((tcc2 &
TCCM_MASK) << TCCM_SHIFT); /* TCC is 6 */
conf.cnt = (CHAIN_BUF_SIZE); /* Frame Count is 0 */
conf.idx = 0; /* 1-d source, 1-d destination, address
increment for both, so
FRMIDX = ELEIDX = don't care */
conf.rld = NO_RELOAD_AND_LINK;
conf.dst = (Uint32) & chain_dst2[0];
conf.src = (Uint32) & chain_src2[0];
EDMA_config (chain_handle, &conf);
printf ("EDMA: Chain Example ... Chaining the two transfers\n");
EDMA_chain (handle, chain_handle, EDMA_TCC_SET, EDMA_ATCC_CLEAR);
printf ("EDMA: Chain Example ... Initiating the transfer\n");
EDMA_intEnable (tcc2);
/* Setup the ISRs for both the transfers */
edmaEventHook (chain_chan_no, isr2);
edmaEventHook (tcc2, isr);
/* Inititate transfer */
EDMA_setChannel (handle); /* Set event register, this should
result in interrupt */
/* Wait for the first stage of the chain */
while (1) {
if (parent_isr_cnt > 0) {
parent_isr_cnt = 0;
break;
}
}
/* Wait for the second stage of the chain */
while (1) {
if (isr_cnt > 0) {
isr_cnt = 0;
break;
}
}
printf ("EDMA: Chain Example ... Data transfer is complete\n");
/* Verify the first stage data transfer */
for (index = 0; index < CHAIN_BUF_SIZE; index++) {
if (chain_dst1[index] != chain_src1[index]) {
break;
}
}
if (index == CHAIN_BUF_SIZE) {
printf
("EDMA: Chain Example ... 1st stage data transferred correctly\n");
}
else {
printf
("EDMA: Chain Example ... 1st stage data not transferred correctly\n");
return;
}
/* Verify the second stage data transfer */
for (index = 0; index < CHAIN_BUF_SIZE; index++) {
if (chain_dst2[index] != chain_src2[index]) {
break;
}
}
if (index == CHAIN_BUF_SIZE) {
printf
("EDMA: Chain Example ... 2nd stage data transferred correctly\n");
}
else {
printf
("EDMA: Chain Example ... 2nd stage data not transferred correctly\n");
return;
}
printf ("EDMA: Chain Example ... DONE\n");
/* Clean up */
EDMA_close (handle);
EDMA_close (chain_handle);
EDMA_intReset (tcc2);
EDMA_intReset (chain_chan_no);
EDMA_intFree (tcc2);
EDMA_intFree (chain_chan_no);
}
/**
* ============================================================================
* @func qdma_example
*
* @desc
* This performs a QDMA memory to memory transfer.
*
* @n <b> Procedure </b>
* @verbatim
1. Setup the data destination and source
2. Allocate and configure interrupt
3. Configure the QDMA
4. Wait for the completion of the transfer
5. Verify the data transfer
6. Clean up
@endverbatim
* ============================================================================
*/
void qdma_example (void)
{
EDMA_Config conf = { 0 };
Int index;
Int tcc;
printf
("EDMA: QDMA Example ... config. to transfer a 1 dimensional array \n");
for (index = 0; index < SIMPLE_TRANSFER_SIZE; index++) {
src[index] = index;
dst[index] = 0;
}
/* Allocate the interrupt */
tcc = EDMA_intAlloc (EDMA_ALLOC_ANY);
conf.opt =
QDMA_OPTIONS | ((tcc & TCC_MASK) << TCC_SHIFT) | ((tcc & TCCM_MASK) <<
TCCM_SHIFT);
conf.src = (Uint32) (&src[0]);
conf.cnt = ((SIMPLE_TRANSFER_SIZE) / sizeof (Uint32)); /* Element Count */
conf.dst = (Uint32) (&dst[0]);
/* Setup the ISR */
edmaEventHook (tcc, isr);
EDMA_intEnable (tcc);
printf ("EDMA: QDMA Example ... Configuring and starting the transfer\n");
EDMA_qdmaConfig (&conf);
/* Wait for until transfer is over */
while (1) {
if (isr_cnt > 0) {
isr_cnt = 0;
break;
}
}
/* Verify the transferred data */
for (index = 0; index < SIMPLE_TRANSFER_SIZE; index++) {
if (src[index] != dst[index]) {
break;
}
}
if (index == SIMPLE_TRANSFER_SIZE) {
printf
("EDMA: QDMA Example ... transferred 1 dimensional array of %d bytes\n",
SIMPLE_TRANSFER_SIZE);
}
else {
printf ("EDMA: qdmaConfig ... Failed, while transfering an array\n");
return;
}
EDMA_intFree (tcc);
EDMA_intReset (tcc);
printf ("EDMA: QDMA Example ... DONE\n");
}
/* Configuration of INTC module */
void configure_intc (void)
{
CSL_IntcObj intcObjEdma;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcHandle hIntcEdma;
CSL_Status intStat;
CSL_IntcParam vectId;
/* Intc Module Initialization */
intcContext.eventhandlerRecord = EventHandler;
intcContext.numEvtEntries = 1;
CSL_intcInit (&intcContext);
/* Enable NMIs */
CSL_intcGlobalNmiEnable ();
/* Enable Global Interrupts */
intStat = CSL_intcGlobalEnable (&state);
if (intStat != CSL_SOK) {
printf ("Initiallization of INTC failed\n");
}
/* Opening a handle for the Event edma */
vectId = CSL_INTC_VECTID_12;
hIntcEdma = CSL_intcOpen (&intcObjEdma, CSL_INTC_EVENTID_EDMA3CC_GINT, \
&vectId, NULL);
EventRecord.handler = &eventEdmaHandler;
EventRecord.arg = 0;
CSL_intcPlugEventHandler (hIntcEdma, &EventRecord);
/* Enabling event edma */
CSL_intcHwControl (hIntcEdma, CSL_INTC_CMD_EVTENABLE, NULL);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/csl_chip.h | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_chip.h
*
* @path $(CSLPATH)\inc
*
* @desc API header file for CHIP module CSL
*
* =============================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 07-Mar-2006 ds To fix bug PSG00001004, Added a dummy code chipReadNone2,
* before ILC read in CSL_chipReadReg () API
* To fix bug PSG00001012, Added dummy code chipWriteNone2,
* before ILC write in CSL_chipWriteReg () API
* 19-May-2006 NG Updated the enum CSL_ChipReg ie., from AMR to CSL_CHIP_AMR
* according to coding guidelines.
* REP value changed from 32 to 15
* =============================================================================
*/
#ifndef _CSL_CHIP_H_
#define _CSL_CHIP_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <cslr_chip.h>
/* CHIP global macro declarations */
/* CHIP global typedef declarations */
/** Enum for the CHIP registers */
typedef enum {
/** Addressing Mode Register */
CSL_CHIP_AMR = 0,
/** Control Status Register */
CSL_CHIP_CSR = 1,
/** Interrupt Flag Register */
CSL_CHIP_IFR = 2,
/** Interrupt Set Register */
CSL_CHIP_ISR = 2,
/** Interrupt Clear Register */
CSL_CHIP_ICR = 3,
/** Interrupt Enable Register */
CSL_CHIP_IER = 4,
/** Interrupt Service Table Pointer Register */
CSL_CHIP_ISTP= 5,
/** Interrupt Return Pointer Register */
CSL_CHIP_IRP= 6,
/** Nonmaskable Interrupt (NMI) Return Pointer Register */
CSL_CHIP_NRP= 7,
/** Exception Return Pointer Register */
CSL_CHIP_ERP= 7,
/** Time Stamp Counter Register - Low */
CSL_CHIP_TSCL= 10,
/** Time Stamp Counter Registers - High */
CSL_CHIP_TSCH= 11,
/** SPLOOP Inner Loop Count Register */
CSL_CHIP_ILC= 13,
/** SPLOOP Reload Inner Loop Count Register */
CSL_CHIP_RILC= 14,
/** Restricted Entry Point Address Register */
CSL_CHIP_REP= 15,
/** E1 Phase Program Counter */
CSL_CHIP_PCE1= 16,
/** DSP Core Number Register */
CSL_CHIP_DNUM= 17,
/** Saturation Status Register */
CSL_CHIP_SSR= 21,
/** GMPY Polynomial.A Side Register */
CSL_CHIP_GPLYA= 22,
/** GMPY Polynomial.B Side Register */
CSL_CHIP_GPLYB= 23,
/** Galois Field Polynomial Generator Function Register */
CSL_CHIP_GFPGFR= 24,
/** Task State Register */
CSL_CHIP_TSR= 26,
/** Interrupt Task State Register */
CSL_CHIP_ITSR= 27,
/** NMI/Exception Task State Register */
CSL_CHIP_NTSR= 28,
/** Exception Flag Register */
CSL_CHIP_EFR= 29,
/** Exception Clear Register */
CSL_CHIP_ECR= 29,
/** Internal Exception Report Register */
CSL_CHIP_IERR= 31
} CSL_ChipReg;
/* CHIP global function declarations */
/** ============================================================================
* @n@b CSL_chipWriteReg
*
* @b Description
* @n This API writes specified control register with the specified
* value 'val'.
*
* @b Arguments
* @verbatim
reg Specifies the control register to be written to
val Value to be written.
@endverbatim
*
*
* <b> Return Value Uint32
* @li Old programmed value
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The reg control register is written with the value passed
*
* @b Modifies
* @n None
*
* <b> Usage Constraints: </b>
* @n Please refer to the C64x+ user guide for constraints while accessing
* registers in different privilege levels.
*
* @b Example
* @verbatim
Uint32 oldamr;
oldamr = CSL_chipWriteReg (AMR, 56);
@endverbatim
* ===========================================================================
*/
Uint32 CSL_chipWriteReg (
CSL_ChipReg reg,
CSL_Reg32 val
);
/** ============================================================================
* @n@b CSL_chipReadReg
*
* @b Description
* @n This API reads the specified control register.
*
* @b Arguments
* @verbatim
reg Specifies the control register to be read
@endverbatim
*
*
* <b> Return Value Uint32
* @li The control register value read
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* <b> Usage Constraints: </b>
* @n Please refer to the C64x+ user guide for constraints while accessing
* registers in different privilege levels.
*
* @b Example
* @verbatim
Uint32 amr;
amr = CSL_chipReadReg (AMR);
@endverbatim
* ===========================================================================
*/
Uint32 CSL_chipReadReg(
CSL_ChipReg reg
);
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/common/csl_cfgGetBaseAddress.c | <filename>DSP/TI-Header/csl_c6455_src/src/common/csl_cfgGetBaseAddress.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_cfgGetBaseAddress.c
*
* @path $(CSLPATH)\src\common
*
* @desc CSL Implementation of CSL_cfgGetBaseAddress
*
*/
/* ============================================================================
* Revision History
* ===============
* 31-Jan-2006 ds File Created.
* 09-Aug-2006 NG Added condition to check the invalid parameter
*
* ============================================================================
*/
#include <soc.h>
#include <csl_cfg.h>
/** ============================================================================
* @n@b CSL_cfgGetBaseAddress
*
* @b Description
* @n Function to get the base address of the peripheral instance.
* This function is used for getting the base address of the peripheral
* instance. This function will be called inside the CSL_cfgOpen()
* function call. This function is open for re-implementing if the user
* wants to modify the base address of the peripheral object to point to
* a different location and there by allow CSL initiated write/reads into
* peripheral. MMR's go to an alternate location.
*
* @b Arguments
* @verbatim
cfgNum Specifies the instance of the CFG to be opened.
pCfgParam Module specific parameters.
pBaseAddress Pointer to baseaddress structure containing base
address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Successful on getting the base
* address of CFG
* @li CSL_ESYS_FAIL The instance number is invalid.
* @li CSL_ESYS_INVPARAMS Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base Address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure is modified.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_CfgBaseAddress baseAddress;
...
status = CSL_cfgGetBaseAddress(CSL_MEMPROT_CONFIG, NULL, &baseAddress);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_cfgGetBaseAddress, ".text:csl_section:cfg");
CSL_Status CSL_cfgGetBaseAddress (
CSL_InstNum cfgNum,
CSL_CfgParam *pCfgParam,
CSL_CfgBaseAddress *pBaseAddress
)
{
CSL_Status status = CSL_SOK;
if (pBaseAddress == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (cfgNum) {
case CSL_MEMPROT_CONFIG:
pBaseAddress->regs = (CSL_CfgRegsOvly)CSL_MEMPROT_CONFIG_REGS;
break;
default:
pBaseAddress->regs = (CSL_CfgRegsOvly)NULL;
status = CSL_ESYS_FAIL;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc_src/inc/csl.h | /*****************************************************\
* Copyright 2005 Texas Instruments Incorporated. *
* All rights reserved. *
* Restricted rights to use, duplicate or disclose *
* this code are granted through contract. *
* *
* "@(#) PSP/CSL 3.0.0.0 (2003-09-30) *
\*****************************************************/
#ifndef _CSL_H_
#define _CSL_H_
#include <csl_types.h>
#include <csl_error.h>
void
CSL_sysInit (
void
);
#endif /* _CSL_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnHwControl.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_pwrdwnHwControl.c
*
* @path $(CSLPATH)\src\pwrdwn
*
* @desc File for functional layer of CSL API CSL_pwrdwnHwControl ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 16-Jul-2004 <NAME> File Created
* =============================================================================
*/
#include <csl_pwrdwn.h>
#include <csl_pwrdwnAux.h>
/** ===========================================================================
* @n@b CSL_pwrdwnHwControl
*
* @b Description
* @n This function performs various control operations on the PWRDWN
* instance based on the command passed.
*
* @b Arguments
* @verbatim
hPwrdwn Handle to the PWRDWN instance
cmd Operation to be performed on the PWRDWN
cmdArg Arguement specific to the command
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command execution successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_ESYS_INVPARAMS - Invalid Parameter
*
* <b> Pre Condition </b>
* CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call
*
* <b> Post Condition </b>
* @n Registers of the PWRDWN instance are configured according to the
* command and the command arguments. The command determines which
* registers are modified.
*
* @b Modifies
* @n Registers determined by the command
*
* @b Example:
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnHwSetup pwrSetup;
CSL_PwrdwnHandle hPwr;
CSL_PwrdwnPortData pageSleep;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Setup structure
...
// Setup
CSL_pwrdwnHwSetup(hPwr,&pwrSetup);
// Hw Control
pageSleep.portNum = 0x1;
pageSleep.data = 0x0;
CSL_pwrdwnHwControl(hPwr,CSL_PWRDWN_CMD_PAGE0_SLEEP,&pageSleep);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbtim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pwrdwnHwControl, ".text:csl_section:pwrdwn");
CSL_Status CSL_pwrdwnHwControl (
CSL_PwrdwnHandle hPwrdwn,
CSL_PwrdwnHwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK;
if (hPwrdwn == NULL) {
return CSL_ESYS_BADHANDLE;
}
else if ((arg == NULL) && ((cmd >= 0) && \
(cmd <= CSL_PWRDWN_CMD_PAGE1_WAKE))) {
return CSL_ESYS_INVPARAMS;
}
else {
switch (cmd) {
case CSL_PWRDWN_CMD_PAGE0_SLEEP:
status = CSL_pwrdwnPage0Sleep(hPwrdwn, (CSL_PwrdwnPortData *)arg);
break;
case CSL_PWRDWN_CMD_PAGE1_SLEEP:
status = CSL_pwrdwnPage1Sleep(hPwrdwn, (CSL_PwrdwnPortData *)arg);
break;
case CSL_PWRDWN_CMD_PAGE0_WAKE:
status = CSL_pwrdwnPage0Wake(hPwrdwn, (CSL_PwrdwnPortData *)arg);
break;
case CSL_PWRDWN_CMD_PAGE1_WAKE:
status = CSL_pwrdwnPage1Wake(hPwrdwn, (CSL_PwrdwnPortData *)arg);
break;
default:
status = CSL_ESYS_INVCMD ;
break;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/vcp2/vcp2_hard_decisions/src/Vcp2_data.c | /* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file Vcp2_data.c
*
* @path $(CSLPATH)\example\c6455\vcp2\vcp2_hard_decisions\src
*
* @desc Data definition file for the example of VCP2
*
*/
/* ============================================================================
* Revision History
* ===============
* 20-May-2005 SPrasad File Created.
* 01-Aug-2005 Chandra Beautified
* 11-Aug-2005 Chandra Minor format chagnes.
* ============================================================================
*/
#include <csl_vcp2.h>
#include <Vcp2_example.h>
#pragma DATA_SECTION(branch_metric, ".channelBmData")
#pragma DATA_SECTION(hard_decision, ".channelHdData")
#pragma DATA_SECTION(hard_decisionRef, ".channelHdrefData")
/* The banch metrics data */
Uint32 branch_metric[] = {
0x29d7d583,
0x83d7d72b,
0xd42a82d8,
0xd52983d7,
0x7e2c2ad8,
0x81d7d52b,
0x297fd52b,
0x28d6d684,
0x29d77d2b,
0x2bd77f2b,
0xd62a2a7e,
0x29d57f2b,
0x29d77d2b,
0x2ad8d684,
0xd6842ad8,
0xd52b297f,
0x2a7fd62c,
0x7f2b2bd7,
0x2bd7d783,
0x2ad6d682,
0x7d292bd7,
0x2a7ed82c,
0x2ad8d684,
0xd62a84d8,
0x2a7fd62c,
0x2a7ed82c,
0x2ad67f2c,
0x81d7d72d,
0xd62a2a7e,
0x7e2a2cd8,
0xd5832bd9,
0x81d5d72b,
0x83d7d72b,
0xd58329d7,
0x7e2a2cd8,
0x2ad8d684,
0x29d7d785,
0x81d5d72b,
0x29d77d2b,
0xd58329d7,
0x2ad87e2c,
0x7e2c2ad8,
0x81d6d62c,
0xd58329d7,
0x81d7d72d,
0x7d292bd7,
0xd62a84d8,
0x29d77d2b,
0x29d7d785,
0x287ed62c,
0x7e2c2ad8,
0x2ad6d682,
0x2ad6d682,
0x7f2b2bd7,
0xd6822cd8,
0x81d6d62c,
0x7f2b2bd7,
0xd52b81d7,
0x29d77d2b,
0xd62a2c7f,
0xd72b83d7,
0x2a7ed82c,
0xd6822ad6,
0xd7832bd7,
0xd6822ad6,
0x297dd72b,
0x2ad87e2c,
0x7d292bd7,
0x81d6d62c,
0x2b7fd72b,
0xd5292b7f,
0x297fd52b,
0x81d7d72d,
0x7d292bd7,
0x29d77f2d,
0x2a7ed82c,
0x287ed62c,
0xd52b83d9,
0x29d7d785,
0xd6822ad6,
0xd42a2a7f,
0xd6842ad8,
0x2ad8d684,
0x29d77d2b,
0x29d57f2b,
0x2ad8d684,
0xd58329d7,
0xd5292b7f,
0x297fd72d,
0x81d5d72b,
0x7c2a2ad8,
0xd72b83d7,
0x29d77f2d,
0xd42a2a7f,
0xd42a82d8,
0x2a7ed82c,
0xd6842ad8,
0x2a7ed82c,
0x28d67e2c,
0x81d6d62c,
0xd52b297f,
0x81d5d72b,
0xd62a84d8,
0x29d57f2b,
0xd62c2a7f,
0xd62a84d8,
0x2a7fd62c,
0x2a7fd62c,
0x29d57f2b,
0x82d6d82c,
0xd52b2b7f,
0x7f2b2bd7,
0x2b7fd72b,
0x2ad8d684,
0xd62a82d6,
0x297fd52b,
0x297dd72b,
0x28d67e2c,
0x81d7d72d,
0x29d7d785,
0x2bd7d783,
0x81d7d72d,
0xd52983d7,
0xd62a84d8,
0x7e2a2cd8,
0x82d6d62a,
0xd6822cd8,
0x7e2c2ad8,
0x2ad8d684,
0x29d7d583,
0x7d292bd7,
0xd6822cd8,
0x81d7d52b,
0x7f2b2bd7,
0x29d77d2b,
0x297dd72b,
0xd6822ad6,
0xd6822ad6,
0x287ed62c,
0xd62a82d6,
0xd62a2c7f,
0x29d77d2b,
0xd52983d7,
0x81d7d72d,
0xd62a2a7e,
0x7c2a2ad8,
0xd58329d7,
0x7c2a2ad8,
0xd62c2a7f,
0x82d6d62a,
0x2ad67f2c,
0xd5812bd7,
0x29d77f2d,
0x7e2c2ad8,
0x82d8d62c,
0xd4822ad8,
0x7d2b29d7,
0x28d6d684,
0xd42a2a7f,
0x29d7d785,
0x7d2b2bd9,
0xd5832bd9,
0x7d292bd7,
0xd42a2a7f,
0x81d7d52b,
0xd52983d7,
0xd62a84d8,
0x7d2b2bd9,
0x7d2b29d7,
0x2ad67f2c,
0xd4822ad8,
0x2ad87e2c,
0x81d5d72b,
0xd62a2a7e,
0x82d6d82c,
0x29d57f2b,
0xd58329d7,
0x28d67e2c,
0x81d7d72d,
0x2ad6d884,
0xd62c2a7f,
0x28d6d684,
0x7e2a2ad6,
0xd7832bd7,
0x81d7d72d,
0x83d7d72b,
0xd6822cd8,
0x82d8d62c,
0x7d292bd7,
0xd72b83d7,
0xd42a82d8,
0x7e2a2cd8,
0x81d5d72b,
0x297dd72b,
0xd52b2b7f,
0xd6822cd8,
0x28d6d684,
0xd52b81d7,
0x297dd72b,
0xd5812bd7,
0x2a7fd62c,
0xd52983d7,
0xd52b297f,
0x2ad67f2c,
0x29d57f2b,
0x29d7d785,
0xd6822ad6,
0xd62a2c7f,
0x297fd72d,
0x7d292bd7,
0xd72b2b7f,
0x82d6d62a,
0x2bd77f2b,
0x2b7fd72b,
0x297fd72d,
0xd42a82d8,
0x29d7d583,
0xd5812bd7,
0x29d7d583,
0x2ad67e2a,
0xd52b83d9,
0x82d6d82c,
0xd52b2b7f,
0x7e2c2ad8,
0x2a7ed82c,
0xd62c2a7f,
0x2b7fd72b,
0x81d7d52b,
0x81d5d72b,
0xd5812bd7,
0x81d7d52b,
0x82d6d82c,
0xd6822ad6,
0x7e2c2ad8,
0x2ad8d684,
0x2bd7d783,
0x7e2a2cd8,
0xd5812bd7,
0x81d7d72d,
0x82d8d62c,
0x297fd72d,
0x2ad8d684,
0xd62a84d8,
0x297fd72d,
0x287ed62c,
0xd52b83d9,
0x29d5d783,
0xd6822cd8,
0x28d6d684,
0x2ad67e2a,
0xd52b83d9,
0x7d2b29d7,
0x7e2a2ad6,
0xd52983d7,
0x29d77d2b,
0x2bd7d783,
0x2a7fd62c,
0x81d6d62c,
0x7e2a2ad6,
0x29d77f2d,
0xd58329d7,
0x29d77f2d,
0x82d8d62c,
0x28d6d684,
0xd5292b7f,
0xd52b297f,
0x2ad8d684,
0x82d8d62c,
0x29d77f2d,
0x297dd72b,
0xd5832bd9,
0xd58329d7,
0xd7832bd7,
0x2b7fd72b,
0xd62a82d6,
0x29d5d783,
0x287ed62c,
0x82d6d62a,
0x7f2b2bd7,
0xd42a82d8,
0x29d77d2b,
0x29d7d583,
0x287ed62c,
0x7e2c2ad8,
0x29d7d583,
0xd62a2c7f,
0x29d7d583,
0x7e2c2ad8,
0x2b7fd72b,
0xd62a2c7f,
0xd6842ad8,
0x2ad6d682,
0xd52983d7,
0x2b7fd72b,
0x297fd52b,
0x28d67e2c,
0x82d8d62c,
0x29d7d583,
0xd72b2b7f,
0x2bd7d783,
0x83d7d72b,
0x2ad87e2c,
0xd5832bd9,
0xd52b83d9,
0x28d6d684,
0xd4822ad8,
0xd52b297f,
0xd58329d7,
0xd72b2b7f,
0xd4822ad8,
0x2bd7d783,
0xd72b83d7,
0xd5812bd7,
0x28d67e2c,
0x81d5d72b,
0xd62a2c7f,
0x7e2c2ad8,
0xd6822cd8,
0x83d7d72b,
0x7d292bd7,
0xd62a84d8,
0xd62c82d8,
0x83d7d72b,
0x2ad6d884,
0x29d7d785,
0x82d6d62a,
0xd52983d7,
0xd42a82d8,
0x81d5d72b,
0xd5292b7f,
0x7e2c2ad8,
0xd6822ad6,
0x82d8d62c,
0x81d7d52b,
0x2b7fd72b,
0xd62a2a7e,
0xd5812bd7,
0xd62c2a7f,
0xd58329d7,
0x28d6d684,
0x29d77d2b,
0x29d57f2b,
0xd62a2c7f,
0xd62a84d8,
0xd4822ad8,
0x29d77d2b,
0x81d6d62c,
0x2bd7d783,
0xd62a2c7f,
0x28d6d684,
0x7d2b2bd9,
0xd5832bd9,
0x81d7d72d,
0x81d7d52b,
0x2a7ed62a,
0xd62a2c7f,
0xd6842ad8,
0xd62a2a7e,
0x2a7ed82c,
0x82d6d62a,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
/* Space for the hard decisions, filled with all 1s*/
Uint32 hard_decision[] = {
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF
};
/* Pre-computed hard decisions */
Uint32 hard_decisionRef[] = {
0x91E856D3,
0xFD90B270,
0xF656AF29,
0x130F47B1,
0x82711BF2,
0x9920E398,
0x46BC56FA,
0x59AF4849,
0x4165FC0E,
0xC8EAB83D,
0x20ED5230,
0x00000095
};
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrGetHwSetup.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* =============================================================================
*/
/** ===========================================================================
* @file csl_tmrGetHwSetup.c
*
* @brief File for functional layer of CSL API CSL_tmrGetHwSetup()
*
* @path $(CSLPATH)\src\timer
*
* @desc The CSL_tmrGetHwSetup() function definition & it's associated functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 1-Sept-2004 HMM File Created.
*
* 29-Jul-2005 PSK updted changes acooriding to revised timer spec. the number
* convention TIM12, TIM34 are changed to TIMLO and TIMHI.
*
* 01-Feb-2006 ds Updated according to TCI6482/C6455 UserGuide
* ============================================================================
*/
#include <csl_tmr.h>
/** ============================================================================
* @n@b CSL_tmrGetHwSetup
*
* @b Description
* @n It retrives the hardware setup parameters
*
* @b Arguments
* @verbatim
hTmr Handle to the timer instance
hwSetup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup retrived
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - setup structure is not
* properly initialized
*
* <b> Pre Condition </b>
* @n Module should be initialised and opened
*
* <b> Post Condition </b>
* @n The hardware set up structure will be populated with values from
* the registers
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_TmrHwSetup hwSetup;
...
hwsetup->tmrTimerPeriodLo = 0x100;
hwsetup->tmrTimerPeriodLo = 0x100;
...
status = CSL_tmrGetHwsetup(hTmr, &hwSetup);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_tmrGetHwSetup, ".text:csl_section:tmr");
CSL_Status CSL_tmrGetHwSetup (
CSL_TmrHandle hTmr,
CSL_TmrHwSetup *hwSetup
)
{
CSL_Status status = CSL_SOK;
if (hTmr == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (hwSetup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
/* Get the Period register's values */
hwSetup->tmrTimerPeriodLo = hTmr->regs->PRDLO;
hwSetup->tmrTimerPeriodHi = hTmr->regs->PRDHI;
/* Get the counter register's values*/
hwSetup->tmrTimerCounterLo = hTmr->regs->TIMLO;
hwSetup->tmrTimerCounterHi = hTmr->regs->TIMHI;
hwSetup->tmrPulseWidthHi =
(CSL_TmrPulseWidth)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_PWID_HI);
hwSetup->tmrClockPulseHi =
(CSL_TmrClockPulse)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_CP_HI);
hwSetup->tmrInvOutpHi =
(CSL_TmrInvOutp)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_INVOUTP_HI);
/* Get the TCR register configurations */
hwSetup->tmrIpGateLo =
(CSL_TmrIpGate)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_TIEN_LO);
hwSetup->tmrClksrcLo =
(CSL_TmrClksrc)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_CLKSRC_LO);
hwSetup->tmrPulseWidthLo =
(CSL_TmrPulseWidth)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_PWID_LO);
hwSetup->tmrClockPulseLo =
(CSL_TmrClockPulse)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_CP_LO);
hwSetup->tmrInvInpLo =
(CSL_TmrInvInp)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_INVINP_LO);
hwSetup->tmrInvOutpLo =
(CSL_TmrInvOutp)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_INVOUTP_LO);
/* Get the TGCR register configurations */
hwSetup->tmrPreScalarCounterHi =
(Uint8)CSL_FEXT(hTmr->regs->TGCR, TMR_TGCR_PSCHI);
/* Get the operation mode */
hwSetup->tmrTimerMode =
(CSL_TmrMode)CSL_FEXT(hTmr->regs->TGCR, TMR_TGCR_TIMMODE);
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/FB_W2100_SCU_MEA256/irq.c | #include <csl.h>
#include <cslr_tmr.h>
#include <cslr_gpio.h>
#include <cslr_chip.h>
#include <cslr_edma3cc.h>
#include <soc.h>
#include <c6x.h>
#include "main.h"
#include "irq.h"
#include "Device_lib.h"
#include "Common/MCS_USB_commands.h"
int num_tr_cross[HS1_CHANNELS/2];
int last_tr_cross[HS1_CHANNELS/2];
Uint32 aux_value = 0;
#define DATA_HEADER_SIZE 1
void toggleLED()
{
static int led = 0;
CSL_GpioRegsOvly gpioRegs = (CSL_GpioRegsOvly)CSL_GPIO_0_REGS;
CSL_FINS(gpioRegs->OUT_DATA, GPIO_OUT_DATA_OUT2, led); // LED
led = 1 - led;
}
void W2100Usb(Uint32 direction, Uint32 request, Uint32 value, Uint32 index, Uint32 data, Uint32 length)
{
Uint32 setup0 = direction + (request << 8) + (value << 16);
Uint32 setup1 = index + (length << 16);
WRITE_REGISTER(0x0c10, setup0);
WRITE_REGISTER(0x0c11, setup1);
WRITE_REGISTER(0x0c12, data);
WRITE_REGISTER(0x0c13, 0);
Uint32 ready = 0;
Uint32 repeat = 50000; // 2.5s
while (!ready && repeat > 0)
{
repeat--;
ready = READ_REGISTER(0x0c13);
}
}
// Mailbox write interrupt
// use "#define USE_MAILBOX_IRQ" in global.h to enable this interrupt
interrupt void interrupt8(void)
{
int update_waveform = 0;
Uint32 reg_written;
Uint32 reg_value;
// a write to a mailbox register occurred
reg_written = READ_REGISTER(MAILBOX_LASTWRITTEN);
reg_value = READ_REGISTER(MAILBOX_BASE + reg_written);
switch(reg_written)
{
case MAILBOX_THRSHOLD:
threshold = reg_value;
break;
case MAILBOX_DEADTIME:
deadtime = reg_value;
break;
case MAILBOX_AMPLITUDE:
if (StimAmplitude != reg_value)
{
StimAmplitude = reg_value;
update_waveform = 1;
}
break;
case MAILBOX_DURATION:
if (StimDuration != reg_value)
{
StimDuration = reg_value;
update_waveform = 1;
}
break;
case MAILBOX_REPEATS:
if (StimRepeats != reg_value)
{
StimRepeats = reg_value;
update_waveform = 1;
}
break;
case MAILBOX_STEPSIZE:
if (StimStepsize != reg_value)
{
StimStepsize = reg_value;
update_waveform = 1;
}
break;
}
if (update_waveform)
{
UploadBiphaseRect(0, 0, StimAmplitude, StimDuration, StimRepeats);
}
}
// DMA finished Interrupt
interrupt void interrupt6(void)
{
static int timestamp = 0; // exists only in this function but is created only once on the first function call (i.e. static)
static int segment = 0;
static int crossing_detected = 0;
static int stg_electrode = 0;
static int seg = 0;
int i;
CSL_Edma3ccRegsOvly edma3ccRegs = (CSL_Edma3ccRegsOvly)CSL_EDMA3CC_0_REGS;
// search start of data segments
Int32 HS_data_header[NUM_SEGMENTS];
// command information decoding
// bits 31:28 Data Source/Group
// bits 27:21 reserved for future use
// bit 20:19 data format '00': 2x16 bit, '01': 1x32 bit, '10': 64 bit in 2 DWords
// bit 18 '0': Analog data, '1': Digital data / don't alow data manipulation (no filter, no sign/unsign change)
// bit 17 last Frame/Segment of sweep
// bit 16 first Frame/Segment of sweep
#ifdef _W2100
// bits 15:8 segment number / sub group
// bits 7:0 length of this packet excluding token counter/CRC
#else
// bits 15:9 segment number / sub group
// bits 8:0 length of this packet excluding token counter/CRC
#endif
// Data Source/Group decoding:
// 0: Header
#ifdef _W2100
// 1: Receiver 0 Data (up to 32 segments, each segment has up to 255 32-bit words)
// 2: Receiver 1 Data (up to 32 segments, each segment has up to 255 32-bit words)
// 3: IFB Analog Data
// 4: DSP Data (up to 128 segments, each segment has up to 256 32-bit words)
// 7: Digital Data
#else
// 1,2,3,4: Extender Unit 0 Data (up to 4*16 segments, each segment has up to 511 32-bit words)
// 5,6,7,8: Extender Unit 1 Data (up to 4*16 segments, each segment has up to 511 32-bit words)
// 9: IFB Analog Data
// A: Analog data
// B: DAC data
// C: DSP Data (up to 128 segments, each segment has up to 256 32-bit words)
// D: Digital Data
#endif
// E: reserved
// F: Fooder/Tail
Int32* restrict HS_Data_p[NUM_SEGMENTS];
Int32* restrict IF_Data_p = 0;
int index = 0;
for(i = 0;i < NUM_SEGMENTS;i++)
{
HS_data_header[i] = MeaData[index];
HS_Data_p[i] = (Int32 *)&MeaData[index + 1];
#ifdef _W2100
if ((HS_data_header[i] & 0xF0000000) == 0x30000000) // IF Analog
#else
if ((HS_data_header[i]& 0xF0000000) == 0x90000000) // IF Analog
#endif
{
IF_Data_p = (Int32 *)&MeaData[index + 1];
}
// debug
// MonitorData[i] = MeaData[index];
#ifdef _W2100
index += (HS_data_header[i] & 0xFF) + 1;
#else
index += (HS_data_header[i] & 0x1FF) + 1;
#endif
}
// Prepare DMA for next data transfer DO NOT CHANGE THE FOLLOWING LINE
CSL_FINST(edma3ccRegs->ICRH, EDMA3CC_ICRH_I52, CLEAR); // Clear pending interrupt for event 52
//
// Write to AUX register to see how long interrupt takes (set output to high, at the end set output to low)
//if (timestamp == 9999)
{
aux_value |= 1;
}
//else
{
// aux_value &= ~1;
}
WRITE_REGISTER(IFB_AUX_OUT, aux_value); // set AUX 1 to value one
#ifndef _W2100
// Monitor Analog in
if (IF_Data_p[0] > threshold)
{
aux_value |= 2;
WRITE_REGISTER(0x002C, 0x404); //switch on HS2 LED
if (crossing_detected == 0)
{
crossing_detected = 1;
WRITE_REGISTER(TRIGGER_ID_HS1, segment << 16); // select segment for trigger 1
WRITE_REGISTER(TRIGGER_SET_EVENT_HS1, 0x01); // Start Trigger 1
}
}
else
{
crossing_detected = 0;
aux_value &= ~2;
WRITE_REGISTER(0x002C, 0x400); //switch on HS2 LED
}
// once per second
if (timestamp == 49999)
{
int enable;
int mux;
int config;
int iMeanActivity = 0;
for (i = 0; i < HS1_CHANNELS; i++)
{
iMeanActivity = iMeanActivity + num_tr_cross[i];
}
iMeanActivity = iMeanActivity /(HS1_CHANNELS);
for (i = 0; i < HS1_CHANNELS / ELECTRODES_PER_REGISTER; i++)
{
StimulusEnable[i] = 0;
elec_config[i] = 0;
}
for (i = 0; i < HS1_CHANNELS / (ELECTRODES_PER_REGISTER/2); i++)
{
DAC_select[i] = 0;
}
for (i = 0; i < HS1_CHANNELS; i++)
{
// if (num_tr_cross[i] <= iMeanActivity) {
// if (num_tr_cross[i] > 0)
if (i == stg_electrode)
{
enable = 1;
mux = 1; // Stimulation Source is DAC 1
config = 0; // Use Sidestream 1 for Stimulation Switch
}
else
{
enable = 0;
mux = 0; // Keep MUX at ground
config = 1; // Keep Switches static, manual mode
}
// 1 bit per channel
StimulusEnable[i/ELECTRODES_PER_REGISTER] |= (enable << (i % ELECTRODES_PER_REGISTER));
elec_config[i/ELECTRODES_PER_REGISTER] |= (config << (i % ELECTRODES_PER_REGISTER));
// 2 bit per channel
DAC_select[i/(ELECTRODES_PER_REGISTER/2)] |= (mux << 2 * (i % (ELECTRODES_PER_REGISTER/2)));
}
for (i = 0; i < HS1_CHANNELS / ELECTRODES_PER_REGISTER; i++)
{
WRITE_REGISTER(STG_ELECTRODE_ENABLE + i*REGISTER_OFFSET, StimulusEnable[i]); // Enable Stimulation on STG
// WRITE_REGISTER(0x8140+i*REGISTER_OFFSET, StimulusEnable[i]); // Enable hard blanking for Stimulation Electrodes
WRITE_REGISTER(STG_ELECTRODE_MODE + (i*REGISTER_OFFSET), elec_config[i]); // Configure Stimulation Electrodes to Listen to Sideband 1
}
for (i = 0; i < HS1_CHANNELS / (ELECTRODES_PER_REGISTER/2); i++)
{
WRITE_REGISTER(STG_ELECTRODE_MUX + (i*REGISTER_OFFSET), DAC_select[i]); // Select DAC 1 for Stimulation Electrodes
}
// WRITE_REGISTER(TRIGGER_ID_HS1, segment << 16); // select segment for trigger 1
// WRITE_REGISTER(TRIGGER_SET_EVENT_HS1, 0x01); // Start Trigger 1
// segment = 1 - segment; // alternate between segment 0 and 1
// analyze data
// configure stim signal
}
if (++timestamp == 50000)
{
timestamp = 0;
toggleLED();
if (stg_electrode < 256)
{
stg_electrode++;
}
else
{
stg_electrode = 0;
}
}
#else
#if 1
#define PERIOD 200
int nextsegment[16] =
{
0, 1, 2, 3,
2, 1, 0, 2,
4, 8, 7, 6,
5, 4, 3, 2,
};
static int j = 0;
if (timestamp == PERIOD - 50)
{
WRITE_REGISTER(0x9A80, 0x1000 * nextsegment[j] + 0x100); // Trigger Channel 1
j++;
}
if (timestamp > 0 && timestamp < PERIOD * 16 - 100)
{
if (timestamp % PERIOD == 0)
{
WRITE_REGISTER(0x9A80, 0x1000 * nextsegment[j] + 0x100); // Trigger Channel 1
j++;
}
}
if (timestamp == PERIOD * 16 + 50)
{
WRITE_REGISTER(0x9A80, 0); // Stop Trigger
}
++timestamp;
#else
if (timestamp == 5000)
{
//WRITE_REGISTER(0x0480, 0); // Feedback
}
aux_value &= ~2;
MonitorData[3] = 0;
if (++timestamp == 20000)
{
timestamp = 0;
toggleLED();
//WRITE_REGISTER(0x0480, 1); // Feedback
seg++;
if (seg >= 16)
{
seg = 0;
}
WRITE_REGISTER(0x9A80, 0x1000 * seg + 0x100); // Trigger Channel 1
aux_value |= 2;
MonitorData[3] = 5;
}
#endif
#endif
//int f = HS_Data_p[0][0] > 0;
//WRITE_REGISTER(0x0480, f); // Feedback
/*
MonitorData[0] = (timestamp >> 4) & 0xFF;
MonitorData[1] = HS_Data_p[0][4] + 80;
MonitorData[2] = (IF_Data_p[0][0] - 1190000) >> 15;
//MonitorData[3] = HS_Data_p[0][6] + 30;
MonitorData[4] = HS_Data_p[0][0] >> 10;
MonitorData[5] = HS_Data_p[0][8] + 30;
MonitorData[6] = HS_Data_p[0][9] + 30;
*/
for(i = 0; i < 64; i++)
{
//MonitorData[i] = HS_Data_p[0][i];
}
for(i = 32; i < 64; i++)
{
//MonitorData[i] = IF_Data_p[0][i];
}
CSL_FINST(edma3ccRegs->ESRH, EDMA3CC_ESRH_E53, SET); // Manual Trigger Event 53
aux_value &= ~1;
WRITE_REGISTER(IFB_AUX_OUT, aux_value); // set AUX 1 to value zero
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtHwSetup.c | <filename>DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtHwSetup.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* priovided
* ============================================================================
*/
/** ============================================================================
* @file csl_bwmngmtHwSetup.c
*
* @path $(CSLPATH)\src\bwmngmt
*
* @desc File for functional layer of CSL API CSL_bwmngmtHwSetup()
*
*/
/* =============================================================================
* Revision History
* ===============
* 03-Jun-2004 <NAME> File Created
*
* 11-Apr-2005 Brn updated the file for doxygen compatibiliy
*
* 16-Nov-2005 ds updated the documentation
* =============================================================================
*/
#include <csl_bwmngmt.h>
/** ============================================================================
* @n@b CSL_bwmngmtHwSetup
*
* @b Description
* @n Configures the BWMNGMT using the values passed in through the
* setup structure.
*
* @b Arguments
* @verbatim
hBwmngmt Handle to the BWMNGMT instance
setup Setup structure for BWMNGMT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* CSL_SOK - Close successful
* CSL_ESYS_BADHANDLE - Invalid handle
* CSL_ESYS_INVPARAMS - If setup is NULL
*
* <b> Pre Condition </b>
* @n Both @a CSL_bwmngmtInit() and @a CSL_bwmngmtOpen() must be called
* successfully in that order before this function can be called. The
* main setup structure consists of fields used for the configuration at
* start up. The user must allocate space for it and fill in the main
* setup structure fields appropriately before a call to this function
* is made. \n
*
* <b> Post Condition </b>
* @n BWMNGMT registers are configured according to the hardware setup
* parameters
*
* @b Modifies
* @n The following registers and fields are programmed by this API \n
* 1. CPU Arbitration Parameters \n
* - PRI field set in L1D, L2 and/or EXT \n
* - MAXWAIT field set in L1D, L2 and/or EXT \n
*
* 2. IDMA Arbitration Parameter \n
* - MAXWAIT field set in L1D, L2 and/or EXT \n
*
* 3. SLAP Arbitration Parameter \n
* - MAXWAIT field set in L1D, L2 and/or EXT \n
*
* 4. MAP Arbitration Parameter \n
* - PRI field set in EXT \n
*
* 5. UC Arbitration Parameter \n
* - MAXWAIT field set in L1D and/or L2 \n
*
* The @b control: bitmask indicates which of the three control blocks
* (L1D, L2 and EXT) will be set with the associated PRI and MAXWAIT values
* Note: That if associated control block is not programmable for given
* requestor then it will not ignored but no error will be provide. This
* allows the user to set control to CSL_BWMNGMT_BLOCK_ALL which is the
* default value. This will set all programmed arbitration values for a given
* requestor to the same value across \n the blocks which is recommended.
* If PRI is set to CSL_BWMNGMT_PRI_NULL (-1) then no change will be made
* for the corresponding requestors priority level.
* If MAXWAIT is set to CSL_BWMNGMT_MAXWAIT_NULL (-1) then no change will be
* made for the corresponding requestors maxwait setting.
* @b Examples:
* @verbatim
Example 1: Sets Priorities and Maxwaits to default values
CSL_BwmngmtHandle hBwmngmt;
CSL_BwmngmtHwSetup hwSetup;
hwSetup = CSL_BWMNGMT_HWSETUP_DEFAULTS;
...
// Init Successfully done
...
// Open Successfully done
...
CSL_bwmngmtHwSetup(hBwmngmt, &hwSetup);
Example 2: Sets CPU Priority to 1, CPU Maxwait to 8, MAP Priority to 6 for
all blocks (L1D, L2 and EXT)
CSL_BwmngmtHandle hBwmngmt;
CSL_BwmngmtHwSetup hwSetup;
hwSetup.cpuPriority = CSL_BWMNGMT_PRI_1;
hwSetup.cpuMaxwait = CSL_BWMNGMT_MAXWAIT_8;
hwSetup.idmaMaxwait = CSL_BWMNGMT_MAXWAIT_NULL;
hwSetup.slapMaxwait = CSL_BWMNGMT_MAXWAIT_NULL;
hwSetup.mapPriority = CSL_BWMNGMT_PRI_6;
hwSetup.ucMaxwait = CSL_BWMNGMT_MAXWAIT_NULL;
hwSetup.control = CSL_BWMNGMT_BLOCK_ALL;
...
// Init Successfully done
...
// Open Successfully done
...
CSL_bwmngmtHwSetup(hBwmngmt, &hwSetup);
@endverbatim
*
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_bwmngmtHwSetup, ".text:csl_section:bwmngmt");
CSL_Status CSL_bwmngmtHwSetup (
CSL_BwmngmtHandle hBwmngmt,
CSL_BwmngmtHwSetup *setup
)
{
CSL_Status status = CSL_SOK;
Uint32 _tempControl;
if (hBwmngmt == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (setup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
_tempControl = setup->control;
if (setup->cpuPriority != CSL_BWMNGMT_PRI_NULL) {
if (_tempControl & CSL_BWMNGMT_BLOCK_L1D) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBL1D,
BWMNGMT_CPUARBL1D_PRI, setup->cpuPriority);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_L2) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBL2,
BWMNGMT_CPUARBL2_PRI, setup->cpuPriority);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_EXT) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBEXT,
BWMNGMT_CPUARBEXT_PRI, setup->cpuPriority);
}
}
if (setup->cpuMaxwait != CSL_BWMNGMT_MAXWAIT_NULL) {
if (_tempControl & CSL_BWMNGMT_BLOCK_L1D) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBL1D,
BWMNGMT_CPUARBL1D_MAXWAIT, setup->cpuMaxwait);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_L2) {
CSL_FINS(((CSL_BwmngmtRegs*)CSL_BWMNGMT_0_REGS)->CPUARBL2,
BWMNGMT_CPUARBL2_MAXWAIT, setup->cpuMaxwait);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_EXT) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBEXT,
BWMNGMT_CPUARBEXT_MAXWAIT, setup->cpuMaxwait);
}
}
if (setup->idmaMaxwait != CSL_BWMNGMT_MAXWAIT_NULL) {
if (_tempControl & CSL_BWMNGMT_BLOCK_L1D) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->IDMAARBL1D,
BWMNGMT_IDMAARBL1D_MAXWAIT, setup->idmaMaxwait);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_L2) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->IDMAARBL2,
BWMNGMT_IDMAARBL2_MAXWAIT, setup->idmaMaxwait);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_EXT) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->IDMAARBEXT,
BWMNGMT_IDMAARBEXT_MAXWAIT, setup->idmaMaxwait);
}
}
if (setup->slapMaxwait != CSL_BWMNGMT_MAXWAIT_NULL) {
if (_tempControl & CSL_BWMNGMT_BLOCK_L1D) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->SLAPARBL1D,
BWMNGMT_SLAPARBL1D_MAXWAIT, setup->slapMaxwait);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_L2) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->SLAPARBL2,
BWMNGMT_SLAPARBL2_MAXWAIT, setup->slapMaxwait);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_EXT) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->SLAPARBEXT,
BWMNGMT_SLAPARBEXT_MAXWAIT, setup->slapMaxwait);
}
}
if (setup->mapPriority != CSL_BWMNGMT_PRI_NULL) {
if (_tempControl & CSL_BWMNGMT_BLOCK_EXT) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->MAPARBEXT,
BWMNGMT_MAPARBEXT_PRI, setup->mapPriority);
}
}
if (setup->ucMaxwait != CSL_BWMNGMT_MAXWAIT_NULL) {
if (_tempControl & CSL_BWMNGMT_BLOCK_L1D) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->UCARBL1D,
BWMNGMT_UCARBL1D_MAXWAIT, setup->ucMaxwait);
}
if (_tempControl & CSL_BWMNGMT_BLOCK_L2) {
CSL_FINS(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->UCARBL2,
BWMNGMT_UCARBL2_MAXWAIT, setup->ucMaxwait);
}
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example6/src/Intc_example6.c | <filename>DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example6/src/Intc_example6.c
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file Intc_example6.c
*
* @path $(CSLPATH)\example\c64xplus\intc\intc_example6\src
*
* @desc Example of INTC
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This example demonstrating usage of the exception handling. Timer 0,1
* are treated as exceptions and they are cleared accordingly.
* Some additional CSL APIs are tested here compared to intc_exampl5.
* This example,
* 1. Intializes Intc module and the CPU vector table, dispatcher
* 2. Enables the external exceptions
* 3. Hook up the NMI Isr
* 4. Opens a handle for the Timer 0 and Timer1 Event as an
* exception event
* 5. Plugs timers event handler
* 6. Enabls timers exception and Disables exceptions
* 7. Again restores the exceptions
* 8. Intializes and opens the timer module
* 9. Sets up the timer modules
* 10. starts the timers
* 11. Wait for exceptions to occur
* 12. print the result
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Intc_example6.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 2-July-2004 <NAME> File Created.
*
* 14-Nov-2005 ds changed to support timer CSL
*
* ============================================================================
*/
#include <csl_intc.h>
#include <cslr_chip.h>
#include <csl_intcAux.h>
#include <cslr_dev.h>
#include <csl_tmr.h>
#include <soc.h>
#include <stdio.h>
/* Forward declarations */
void eventTimer0Handler(void *handle);
void eventTimer1Handler(void *handle);
void NMI_handler();
void intc_example (void);
/* Global variables declarations */
volatile Int timer0Cnt = 0;
volatile Int timer1Cnt = 0;
volatile Int passed = 0;
volatile Int failed = 0;
extern cregister volatile Uint32 CSR;
extern cregister volatile Uint32 TSR;
extern cregister volatile Uint32 EFR;
/* Intc Variable declarations */
CSL_IntcContext context;
CSL_IntcEventHandlerRecord Record[3];
CSL_IntcEventHandlerRecord EventHandler[30];
/* ============================================================================
*
* @func main
*
* @desc
* This is the main routine,which invokes the example
* ============================================================================
*/
void main()
{
Bool timerEn;
Bool timerEn1;
printf ("Demonstrating the exception handling \n");
/* Unlock the control register */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the timer0 */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER0CTL,
ENABLE);
do {
timerEn = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_TIMER0STAT);
} while (timerEn != TRUE);
/* Enable the timer1 */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER1CTL,
ENABLE);
do {
timerEn1 = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_TIMER1STAT);
} while (timerEn1 != TRUE);
printf("Power saver clock for TIMER0 and TIMER1 Enabled\n");
/* Invoke example */
intc_example ();
return;
}
/*
* =============================================================================
* @func intc_example
*
* @arg None
*
* @desc
* Demonstrating usage of the exception handling. Timer 0,1 are treated
* as exceptions and they are cleared accordingly
* It implements following steps
* 1. Intializes Intc module and the CPU vector table, dispatcher
* 2. Enables the external exceptions
* 3. Hook up the NMI Isr
* 4. Opens a handle for the Timer 0 and Timer1 Event as an
* exception event
* 5. Plugs timers event handler
* 6. Enabls timers exception and Disables exceptions
* 7. Again restores the exceptions
* 8. Intializes and opens the timer module
* 9. Sets up the timer modules
* 10. starts the timers
* 11. Wait for exceptions to occur
* 12. print the result
* 13. Close intc and timer module
*
* @return
* None
*
* @eg
* intc_example ();
* =============================================================================
*/
void intc_example (void)
{
CSL_IntcObj intcTimerObj0;
CSL_IntcObj intcTimerObj1;
CSL_IntcHandle hIntcTimer0;
CSL_IntcHandle hIntcTimer1;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord eventRecord;
CSL_IntcParam vectId;
CSL_TmrHandle hTmr;
CSL_TmrHandle hTmr1;
CSL_TmrObj tmrObj;
CSL_TmrObj tmrObj1;
CSL_Status status;
CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
CSL_TmrHwSetup hwSetup1 = CSL_TMR_HWSETUP_DEFAULTS;
CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;
Uint32 loadValue = 100;
Uint32 prevState;
volatile Uint16 delay;
/* Init the Interrupt Controller
* Initializes the CPU vector table, dispatcher
*/
context.numEvtEntries = 3;
context.eventhandlerRecord = Record;
status = CSL_intcInit(&context);
if (status != CSL_SOK) {
printf("Intc initialization failed\n");
return;
}
/* Enable NMIs */
status = CSL_intcGlobalNmiEnable();
if (status != CSL_SOK) {
printf("Intc global NMI enable failed\n");
return;
}
/* Enabling Global interrupts */
status = CSL_intcGlobalEnable(&state);
if (status != CSL_SOK) {
printf ("Intc global enable failed\n");
return;
}
/* Global Exceptions enable */
status = CSL_intcGlobalExcepEnable ();
if (status != CSL_SOK) {
printf ("Intc global exceptions enable failed\n");
return;
}
/* Global External Exceptions enable */
status = CSL_intcGlobalExtExcepEnable ();
if (status != CSL_SOK) {
printf ("Intc global external exceptions enable failed\n");
return;
}
/* Disabling Global interrupts */
status = CSL_intcGlobalDisable(&state);
if (status != CSL_SOK) {
printf ("Intc global disable failed\n");
return;
}
/* Restore Global interrupts */
status = CSL_intcGlobalRestore(state);
if (status != CSL_SOK) {
printf ("Intc global restore failed\n");
return;
}
/* Check for all interrupt are enable are not */
if (CSL_FEXT(CSR,CHIP_CSR_GIE) != CSL_CHIP_CSR_GIE_ENABLE)
failed++;
/* Hook up the NMI Isr */
status = CSL_intcHookIsr(CSL_INTC_VECTID_NMI,NMI_handler);
if (status != CSL_SOK) {
printf ("Intc hook up NMI Isr failed\n");
return;
}
/* Opening a handle for the Timer 0 Event as an exception event */
vectId = CSL_INTC_VECTID_EXCEP;
hIntcTimer0 = CSL_intcOpen (&intcTimerObj0, CSL_INTC_EVENTID_TINTLO0,
&vectId , NULL);
if (hIntcTimer0 == NULL) {
printf("Intc open failed for timer0 event \n");
return;
}
/* Plug timer0 event handler */
eventRecord.handler = &eventTimer0Handler;
eventRecord.arg = hIntcTimer0;
status = CSL_intcPlugEventHandler(hIntcTimer0,&eventRecord);
if (status != CSL_SOK) {
printf("Intc plug event handler for timer0 event failed\n");
return;
}
/* Opening a handle for the Timer 1 Event as an exception event */
vectId = CSL_INTC_VECTID_EXCEP;
hIntcTimer1 = CSL_intcOpen (&intcTimerObj1, CSL_INTC_EVENTID_TINTLO1,
&vectId , NULL);
if (hIntcTimer1 == NULL) {
printf("Intc open failed for timer1 event \n");
return;
}
/* Plug timer1 event handler */
eventRecord.handler = &eventTimer1Handler;
eventRecord.arg = hIntcTimer1;
status = CSL_intcPlugEventHandler(hIntcTimer1,&eventRecord);
if (status != CSL_SOK) {
printf("Intc plug event handler for timer1 event failed\n");
return;
}
/* Enable timer Exceptions */
status = CSL_intcExcepAllEnable (CSL_INTC_EXCEP_64TO95,
(1 << (67 - 64))|(1 << (69 - 64)), &prevState);
if (status != CSL_SOK) {
printf("Intc enabling timer exceptions failed\n");
return;
}
/* Disable timer Exceptions */
status = CSL_intcExcepAllDisable (CSL_INTC_EXCEP_64TO95,
(1 << (67 - 64)) | (1 << (69 - 64)),
&prevState);
if (status != CSL_SOK) {
printf("Intc disabling timer exceptions failed\n");
return;
}
/* Restore timer Exceptions */
status = CSL_intcExcepAllRestore(CSL_INTC_EXCEP_64TO95,prevState);
if (status != CSL_SOK) {
printf("Intc restore timer exceptions failed\n");
return;
}
/* Disabling these exceptions for a while */
if (((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[2] != prevState)
failed++;
/* Check leftover Exception routines */
if (CSL_FEXT(TSR,CHIP_TSR_GEE) != CSL_CHIP_TSR_GEE_ENABLE)
failed ++;
/* Initialize timer CSL module */
CSL_tmrInit(NULL);
/* Open timer 0 and Timer 1 */
hTmr = CSL_tmrOpen(&tmrObj, CSL_TMR_0, NULL, &status);
hTmr1 = CSL_tmrOpen(&tmrObj1, CSL_TMR_1, NULL, &status);
/* Stop the Timer */
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL);
/* Stop the Timer */
status = CSL_tmrHwControl(hTmr1, CSL_TMR_CMD_RESET_TIMLO, NULL);
/* Set the timer mode to unchained dual mode */
hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED;
/* Set the timer mode to unchained dual mode */
hwSetup1.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED;
/* Setup the timer */
CSL_tmrHwSetup(hTmr, &hwSetup);
CSL_tmrHwSetup(hTmr1, &hwSetup1);
/* Load the timer0 period register */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void *)&loadValue);
/* Load the timer1 period register */
CSL_tmrHwControl(hTmr1, CSL_TMR_CMD_LOAD_PRDLO, (void *)&loadValue);
/* Start the timer0 with one shot*/
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, (void *)&TimeCountMode);
/* Start the timer1 with one shot*/
CSL_tmrHwControl(hTmr1, CSL_TMR_CMD_START_TIMLO, (void *)&TimeCountMode);
/* Waits for exception to generate */
while (!passed);
/* Wait for some time */
for (delay = 0; delay < 10000; delay++);
printf ("Demonstrating the exception handling Done\n");
}
/*
* =============================================================================
* @func NMI_handler
*
* @desc
* This is the interrupt exception handler
*
* @arg
* None
*
*
* @eg
* NMI_handler ();
* =============================================================================
*/
volatile Uint32 temp;
#pragma NMI_INTERRUPT(NMI_handler);
void NMI_handler()
{
Uint32 excepStatus1,rcvExcep64to95,evtMask;
int evtId;
Uint32 prevState;
CSL_intcExcepAllStatus(CSL_INTC_EXCEP_64TO95,&excepStatus1);
temp = EFR;
while (excepStatus1) {
rcvExcep64to95 = excepStatus1;
CSL_intcExcepAllClear(CSL_INTC_EXCEP_64TO95,excepStatus1);
evtMask = 1;
evtId = 64;
do {
if (rcvExcep64to95 & evtMask) {
CSL_intcInvokeEventHandle(evtId);
rcvExcep64to95 &= ~evtMask;
}
evtMask = evtMask << 1;
evtId++;
} while (rcvExcep64to95);
CSL_intcExcepAllStatus(CSL_INTC_EXCEP_64TO95,&excepStatus1);
}
CSL_intcExcepAllDisable(CSL_INTC_EXCEP_64TO95,(1<<3)|(1<< 5), &prevState);
passed++;
}
/*
* =============================================================================
* @func eventTimer0Handler
*
* @desc
* This is the interrupt handler for timer 0
*
* @arg
* None
*
*
* @eg
* eventTimer0Handler ();
* =============================================================================
*/
void eventTimer0Handler (
void *handle
)
{
timer0Cnt++;
}
/*
* =============================================================================
* @func eventTimer0Handler
*
* @desc
* This is the interrupt handler for timer 1
*
* @arg
* None
*
*
* @eg
* eventTimer0Handler ();
* =============================================================================
*/
void eventTimer1Handler (
void *handle
)
{
timer1Cnt++;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnGetHwStatus.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_pwrdwnGetHwStatus.c
*
* @path $(CSLPATH)\src\pwrdwn
*
* @desc File for functional layer of CSL API CSL_pwrdwnGetHwStatus ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 16-Jul-2004 <NAME> File Created
* =============================================================================
*/
#include <csl_pwrdwn.h>
#include <csl_pwrdwnAux.h>
/** ===========================================================================
* @n@b CSL_pwrdwnGetHwStatus
*
* @b Description
* @n This function is used to get the value of various parameters of the
* PWRDWN instance. The value returned depends on the query passed.
*
* @b Arguments
* @verbatim
hPwr Handle to the PWRDWN instance
query Query to be performed
response Pointer to buffer to return the data requested by
the query passed
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Successful completion of the
* query
*
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* @li CSL_ESYS_INVQUERY - Query command not supported
*
* @li CSL_ESYS_INVPARAMS - Invalid Parameters.
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call
*
* <b> Post Condition </b>
* Data requested by the query is returned through the variable "response"
*
* @b Modifies
* @n The input arguement "response" is modified
*
* @b Example:
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnHwSetup pwrSetup;
CSL_PwrdwnHandle hPwr;
CSL_PwrdwnPortData pageSleep;
pageSleep.portNum = 0x0;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Setup structure
...
// Setup
CSL_pwrdwnHwSetup(hPwr,&pwrSetup);
// Hw Status Query
CSL_pwrdwnGetHwStatus(hPwr,CSL_PWRDWN_QUERY_PAGE0_STATUS,
&pageSleep);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pwrdwnGetHwStatus, ".text:csl_section:pwrdwn");
CSL_Status CSL_pwrdwnGetHwStatus (
CSL_PwrdwnHandle hPwrdwn,
CSL_PwrdwnHwStatusQuery query,
void *response
)
{
CSL_Status status = CSL_SOK;
if (hPwrdwn == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (query) {
case CSL_PWRDWN_QUERY_PAGE0_STATUS:
CSL_pwrdwnGetPage0SleepStatus(hPwrdwn, \
(CSL_PwrdwnPortData *)response);
break;
case CSL_PWRDWN_QUERY_PAGE1_STATUS:
CSL_pwrdwnGetPage1SleepStatus(hPwrdwn, \
(CSL_PwrdwnPortData *)response);
break;
default:
status = CSL_ESYS_INVQUERY ;
break;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnHwSetup.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnHwSetup.c<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_pwrdwnHwSetup.c
*
* @path $(CSLPATH)\src\pwrdwn
*
* @desc File for functional layer of CSL API CSL_pwrdwnHwSetup ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 16-Jul-2004 <NAME> File Created
* =============================================================================
*/
#include <csl_pwrdwn.h>
/** ===========================================================================
* @n@b CSL_pwrdwnHwSetup
*
* @b Description
* @n It configures the PWRDWN instance registers as per the values passed
* in the hardware setup structure.
*
* @b Arguments
* @verbatim
hPwrdwn Handle to the pwrdwn instance
setup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Hardware structure is not
* properly initialized
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call
*
* <b> Post Condition </b>
* @n The specified instance will be setup according to value passed
*
* @b Modifies
* @n Hardware registers for the specified instance
*
* @b Example:
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnHwSetup pwrSetup;
CSL_PwrdwnHandle hPwr;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Setup structure
...
// Setup
CSL_pwrdwnHwSetup(hPwr,&pwrSetup);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pwrdwnHwSetup, ".text:csl_section:pwrdwn");
CSL_Status CSL_pwrdwnHwSetup (
CSL_PwrdwnHandle hPwrdwn,
CSL_PwrdwnHwSetup *setup
)
{
/* This is a pointer to the registers of the instance of L2 PWRDWN
* referred to by this object
*/
CSL_Status status = CSL_SOK;
if (hPwrdwn == NULL) {
return CSL_ESYS_BADHANDLE;
}
else if (setup == NULL) {
return CSL_ESYS_INVPARAMS;
}
else {
CSL_FINS(hPwrdwn->pdcRegs->PDCCMD, PDC_PDCCMD_MEGPD, setup->idlePwrdwn);
if (setup->manualPwrdwn) {
hPwrdwn->l2pwrdwnRegs->L2PDWAKE[0] =
setup->manualPwrdwn->port0PageWake;
hPwrdwn->l2pwrdwnRegs->L2PDWAKE[1] =
setup->manualPwrdwn->port1PageWake;
hPwrdwn->l2pwrdwnRegs->L2PDSLEEP[0] =
setup->manualPwrdwn->port0PageSleep;
hPwrdwn->l2pwrdwnRegs->L2PDSLEEP[1] =
setup->manualPwrdwn->port1PageSleep;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cHwControl.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_i2cHwControl.c
*
* @brief File for functional layer of CSL API CSL_i2cHwControl()
*
* @path $(CSLPATH)\i2c\src
*
* Description
* - The CSL_i2cHwControl() function definition & it's associated
* functions
*
* Modification 1
* - Modified on: 28/5/2004
* - Reason: created the sources
*
* @date 28th May, 2004
* @author <NAME>.
*/
/** ============================================================================
* Revision History
* ===============
* 31-aug-2004 Hs Updated the CSL_i2cHwControl to call respective functions.
* 11-oct-2004 Hs updated code according to code review comments.
* =============================================================================
*/
#include <csl_i2c.h>
#include <csl_i2cAux.h>
/** ============================================================================
* @n@b CSL_i2cHwControl
*
* @b Description
* @n Control operations for the I2C. For a particular control operation,
* the pointer to the corresponding data type need to be passed as argument
* to HwControl function Call.All the arguments(Structure element included)
* passed to the HwControl function are inputs. For the list of commands
* supported and argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_I2cHwControlCmd.
* @b Arguments
* @verbatim
hI2c Handle to the I2C instance
cmd The command to this API indicates the action to be
taken on I2C.
arg An optional argument.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully
* in that order before @a CSL_i2cHwControl() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of I2C.
*
* @b Example
* @verbatim
CSL_I2cHandle hI2c;
CSL_I2cHwControlCmd cmd = CSL_I2C_CMD_RESET;
void arg;
CSL_Status status;
...
status = CSL_i2cHwControl (hI2c, cmd, &arg);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_i2cHwControl, ".text:csl_section:i2c");
CSL_Status CSL_i2cHwControl(
CSL_I2cHandle hI2c,
CSL_I2cHwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK;
if (hI2c == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else {
switch (cmd) {
case CSL_I2C_CMD_ENABLE:
CSL_i2cEnable(hI2c);
break;
case CSL_I2C_CMD_RESET:
CSL_i2cReset(hI2c);
break;
case CSL_I2C_CMD_OUTOFRESET:
CSL_i2cOutOfReset(hI2c);
break;
case CSL_I2C_CMD_CLEAR_STATUS:
CSL_i2cClearStatus(hI2c);
break;
case CSL_I2C_CMD_SET_SLAVE_ADDR:
if (arg == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
CSL_i2cSetSlaveAddr(hI2c, arg);
}
break;
case CSL_I2C_CMD_SET_DATA_COUNT:
if (arg == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
CSL_i2cSetDataCount(hI2c, arg);
}
break;
case CSL_I2C_CMD_START:
CSL_i2cStart(hI2c);
break;
case CSL_I2C_CMD_STOP:
CSL_i2cStop(hI2c);
break;
case CSL_I2C_CMD_DIR_TRANSMIT:
CSL_i2cDirTransmit(hI2c);
break;
case CSL_I2C_CMD_DIR_RECEIVE:
CSL_i2cDirReceive(hI2c);
break;
case CSL_I2C_CMD_RM_ENABLE:
CSL_i2cRmEnable(hI2c);
break;
case CSL_I2C_CMD_RM_DISABLE:
CSL_i2cRmDisable(hI2c);
break;
case CSL_I2C_CMD_DLB_ENABLE:
CSL_i2cDlbEnable(hI2c);
break;
case CSL_I2C_CMD_DLB_DISABLE:
CSL_i2cDlbDisable(hI2c);
break;
default:
status = CSL_ESYS_INVCMD;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrHwControl.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* =============================================================================
*/
/** ===========================================================================
* @file csl_tmrHwControl.c
*
* @brief File for functional layer of CSL API CSL_tmrHwControl()
*
* @path $(CSLPATH)\src\timer
*
* @desc The CSL_tmrHwControl() function definition & it's associated
* functions
*
*/
/* ============================================================================
* Revision History
* ===============
* 1-Sept-2004 HMM File Created.
* 29-Jul-2005 PSK updted changes acooriding to revised timer spec. The number
* convention TIM12, TIM34 are changed to TIMLO and TIMHI.
* ============================================================================
*/
#include <csl_tmr.h>
#include <csl_tmrAux.h>
/** ============================================================================
* @n@b CSL_tmrHwControl
*
* @b Description
* @n This function performs various control operations on the timer instance,
* based on the command passed.
*
* @b Arguments
* @verbatim
hTmr Handle to the timer instance
cmd Operation to be performed on the timer
cmdArg Arguement specific to the command
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command execution successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_ESYS_INVPARAMS - Invalid Parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Registers of the timer instance are configured according to the command
* and the command arguments. The command determines which registers are
* modified.
*
* @b Modifies
* @n Registers determined by the command
*
* @b Example
* @verbatim
CSL_Status status;
...
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, NULL);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_tmrHwControl, ".text:csl_section:tmr");
CSL_Status CSL_tmrHwControl (
CSL_TmrHandle hTmr,
CSL_TmrHwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK ;
if (hTmr == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (\
(cmd <= CSL_TMR_CMD_LOAD_WDKEY) && (cmd != CSL_TMR_CMD_STOP_TIMLO) &&\
(cmd != CSL_TMR_CMD_STOP_TIMHI) && (cmd != CSL_TMR_CMD_RESET_TIMLO)&&\
(cmd != CSL_TMR_CMD_RESET_TIMHI)&& (cmd != CSL_TMR_CMD_STOP64) &&\
(cmd != CSL_TMR_CMD_RESET64) && (arg == NULL)\
) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (cmd) {
/* Load PRDLO */
case CSL_TMR_CMD_LOAD_PRDLO:
CSL_TmrLoadPrdLo(hTmr, (Uint32 *)arg);
break;
/* Load PRDHI */
case CSL_TMR_CMD_LOAD_PRDHI:
CSL_TmrLoadPrdHi(hTmr, (Uint32 *)arg);
break;
/* Load PSCHI */
case CSL_TMR_CMD_LOAD_PSCHI:
CSL_TmrLoadPrescalarHi(hTmr, (Uint8 *)arg);
break;
/* start the timer Low */
case CSL_TMR_CMD_START_TIMLO:
CSL_TmrStartLo(hTmr, *((CSL_TmrEnamode *)arg));
break;
/* start the timer Low */
case CSL_TMR_CMD_START_TIMHI:
CSL_TmrStartHi(hTmr, *((CSL_TmrEnamode *)arg));
break;
/* Stop the Timer Low */
case CSL_TMR_CMD_STOP_TIMLO:
CSL_TmrStopLo(hTmr);
break;
/* Stop the TimerHi */
case CSL_TMR_CMD_STOP_TIMHI:
CSL_TmrStopHi(hTmr);
break;
/* Reset the Timer Low */
case CSL_TMR_CMD_RESET_TIMLO:
CSL_TmrResetLo(hTmr);
break;
/* Reset the TimerHi */
case CSL_TMR_CMD_RESET_TIMHI:
CSL_TmrResetHi(hTmr);
break;
/* Start the timer in GPtimer64 OR Chained mode */
case CSL_TMR_CMD_START64:
CSL_TmrStart64(hTmr, *((CSL_TmrEnamode *)arg));
break;
/*Stop the timer of GPtimer64 OR Chained */
case CSL_TMR_CMD_STOP64:
CSL_TmrStop64(hTmr);
break;
/*Reset the timer of GPtimer64 OR Chained */
case CSL_TMR_CMD_RESET64:
CSL_TmrReset64(hTmr);
break;
/*Starts the timer in watchdog mode */
case CSL_TMR_CMD_START_WDT:
CSL_TmrStartWdt(hTmr, *(CSL_TmrEnamode *)arg);
break;
/*loads the watchdog key */
case CSL_TMR_CMD_LOAD_WDKEY:
CSL_TmrLoadWdkey(hTmr, *((Uint16 *)arg));
break;
default:
status = CSL_ESYS_INVCMD;
break;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioGetHwSetup.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* provided
* ============================================================================
*/
/** ==========================================================================
* @file csl_gpioGetHwSetup.c
*
* @path $(CSLPATH)\src\gpio
*
* @desc File for functional layer of CSL API CSL_gpioGetHwSetup()
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 10-Jun-2004 PGR File created
* 11-Oct-2004 Nsr Changed this file according to review commnets.
* 06-Mar-2006 ds Updated the documentation
* ============================================================================
*/
#include <csl_gpio.h>
/** ============================================================================
* @n@b CSL_gpioGetHwSetup
*
* @b Description
* @n Gets the current setup of GPIO. This is a dummy API .
* Its is left for future implementation.
*
* @b Arguments
* @verbatim
hGpio Handle to the GPIO instance
setup Pointer to setup structure to hold the
setup information of GPIO.
@endverbatim
*
* <b> Return Value </b> Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n Both CSL_gpioInit() and CSL_gpioOpen() must be called successfully in
* order before this function.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_GpioHandle hGpio;
CSL_GpioHwSetup setup;
CSL_Status status;
status = CSL_gpioGetHwSetup(hGpio, &setup);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_gpioGetHwSetup, ".text:csl_section:gpio");
CSL_Status CSL_gpioGetHwSetup (
CSL_GpioHandle hGpio,
CSL_GpioHwSetup *setup
)
{
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspGetHwStatus.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_mcbspGetHwStatus.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API CSL_mcbspGetHwStatus()
*
*/
/* =============================================================================
* Revision History
* ================
* June 29,2004 <NAME> - Created
* Oct 27, 2005 ds - Removed CSL_MCBSP_QUERY_PID query
* Feb 02, 2006 ds - Removed CSL_MCBSP_QUERY_TX_INT_MODE and
* CSL_MCBSP_QUERY_TX_INT_MODE queries
* =============================================================================
*/
#include <csl_mcbsp.h>
#include <_csl_mcbsp.h>
#include <csl_mcbspAux.h>
/** ============================================================================
* @n@b CSL_mcbspGetHwStatus
*
* @b Description
* @n Gets the status of different operations or some setup-parameters of
* MCBSP.The status is returned through the third parameter.
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
myQuery Query command
response Response from the query. Pointer to appropriate
object corresponding to the query command needs
to be passed here
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Query successful
* @li CSL_ESYS_INVQUERY - The Query passed is invalid
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
* @li CSL_ESYS_INVPARAMS - Invalid Parameter
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before CSL_mcbspGetHwStatus() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Third parameter response vlaue
*
* @b Example
* @verbatim
CSL_McbspHandle hMcbsp;
CSL_Status status;
Uint16 response;
...
status = CSL_mcbspGetHwStatus(hMcbsp,
CSL_MCBSP_QUERY_DEV_STATUS,
&response);
if (response & CSL_MCBSP_RRDY)
{
// Receiver is ready to with new data
...
}
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_mcbspGetHwStatus, ".text:csl_section:mcbsp");
CSL_Status CSL_mcbspGetHwStatus (
CSL_McbspHandle hMcbsp,
CSL_McbspHwStatusQuery myQuery,
void *response
)
{
CSL_Status status = CSL_SOK;
if (hMcbsp == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if(response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch(myQuery) {
case CSL_MCBSP_QUERY_CUR_RX_BLK:
CSL_mcbspGetCurRxBlk (hMcbsp, response);
break;
case CSL_MCBSP_QUERY_CUR_TX_BLK:
CSL_mcbspGetCurTxBlk (hMcbsp, (CSL_BitMask16 *)response);
break;
case CSL_MCBSP_QUERY_DEV_STATUS:
CSL_mcbspGetDevStatus (hMcbsp, (CSL_BitMask16 *)response);
break;
case CSL_MCBSP_QUERY_TX_RST_STAT:
CSL_mcbspGetTxRstStat (hMcbsp, response);
break;
case CSL_MCBSP_QUERY_RX_RST_STAT:
CSL_mcbspGetRxRstStat (hMcbsp, response);
break;
default:
status = CSL_ESYS_INVQUERY;
break;
}
}
return(status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/mcbsp/mcbsp_multi_channel/src/Mcbsp_MulChannel_example.c | /* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
*
* @file Mcbsp_mulChannel_example.c
*
* @path $(CSLPATH)\example\mcbsp\mcbsp_multi_channel\src
*
* @desc Example of MCBSP
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n In this example, the MCBSP0 is configured in digital loopback mode,
* with 32 bit data transfer, using sample rate generator to synchronise
* the frames.Multi channel mode of transmission is selected.
* This example,
* 1. Intializes and opens mcbsp module
* 2. Sets up the hardware to default values and multi channel
* 32 bit data transfe i.e., CSL_mcbspHwSetup() is called for
* module configuration.
* 3. Brings MCBSP XMT and RCV out of reset
* 4. For every element to be trasmitted out of MCBSP, it first waits
* for XRDY signal to be ON and then writes that element
* 6. Since MCBSP is configured in loopback, this value also comes at
* the receiver, which comes in RCV data register
* 7. For every such element to be received, it waits for RRDY signal
* to be ON and then copies that element from RCV data register to
* a buffer
* 8. Does the data comparision to ensure the written data is proper or
* not and
* 9. Displays the messages based on step 8
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Mcbsp_mulChannel_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 25-April-2005 <NAME>. created
*
* 14-Nov-2005 ds Changed the CLKGDV value during testing
* 16-Dec-2005 ds Updated documentation
* 06-Feb-2006 ds Added "intEvent" configuration to rcvDataCfg and
* xmtDataCfg
* 21-Feb-2006 ds Alocated Memory for readHwsetup structure variable which
* is used in CSL_mcbspGetHwSetup() API call.
* Cleared local data structures
* Added Code to compare the Hwsetup and read Hwsetup
* parameters
* ============================================================================
*/
#include <csl_mcbsp.h>
#include <cslr_dev.h>
#include <soc.h>
#include <stdio.h>
/* Macro that gives 2 CLK delay cycles */
#define WAIT_FOR_2_CLK do { \
volatile int delayCnt = 2; \
while(delayCnt > 0) --delayCnt; \
}while (0)
/* Global constants */
/* Number of words to be transmitted*/
#define NumOfWords 25
/* Handle for the MCBSP instance */
CSL_McbspHandle hMcbsp;
/* Create data buffers for transfer */
Uint32 xmt[NumOfWords];
Uint32 rcv[NumOfWords];
/* Function forwards */
void mcbsp_multichannel_example (void);
CSL_Status hwSetupVerify (CSL_McbspHwSetup *,
CSL_McbspHwSetup *
);
/* Global data definition */
CSL_McbspGlobalSetup gblCfg = {
CSL_MCBSP_IOMODE_TXDIS_RXDIS,
CSL_MCBSP_DLBMODE_ON,
CSL_MCBSP_CLKSTP_DISABLE
};
/* Receive data setup */
CSL_McbspDataSetup rcvDataCfg = {
CSL_MCBSP_PHASE_SINGLE,
CSL_MCBSP_WORDLEN_32,
32, /* FRMLEN1 */
CSL_MCBSP_WORDLEN_8, /* Default value for phase2*/
2, /* FRMLEN2 */
CSL_MCBSP_FRMSYNC_DETECT,
CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
CSL_MCBSP_DATADELAY_0_BIT,
CSL_MCBSP_RJUSTDXENA_RJUST_RZF,
CSL_MCBSP_INTMODE_ON_READY,
CSL_MCBSP_32BIT_REVERS_DISABLE
};
/* Transmit data setup */
CSL_McbspDataSetup xmtDataCfg = {
CSL_MCBSP_PHASE_SINGLE,
CSL_MCBSP_WORDLEN_32,
32, /* FRMLEN1 */
CSL_MCBSP_WORDLEN_8, /* Default value */
2, /* FRMLEN2 */
CSL_MCBSP_FRMSYNC_DETECT,
CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
CSL_MCBSP_DATADELAY_0_BIT,
CSL_MCBSP_RJUSTDXENA_DXENA_OFF,
CSL_MCBSP_INTMODE_ON_READY,
CSL_MCBSP_32BIT_REVERS_DISABLE
};
/* Mcbsp clock setup */
CSL_McbspClkSetup clkCfg = {
CSL_MCBSP_FSCLKMODE_INTERNAL, /* XMT Frame-sync */
CSL_MCBSP_FSCLKMODE_INTERNAL, /* RCV Frame-sync */
CSL_MCBSP_TXRXCLKMODE_INTERNAL, /* XMT clock */
CSL_MCBSP_TXRXCLKMODE_INTERNAL, /* RCV clock */
CSL_MCBSP_FSPOL_ACTIVE_HIGH, /* XMT Frame-sync Active High */
CSL_MCBSP_FSPOL_ACTIVE_HIGH, /* RCV Frame-sync Active High */
CSL_MCBSP_CLKPOL_TX_RISING_EDGE, /* XMT clock Rising Edge */
CSL_MCBSP_CLKPOL_RX_FALLING_EDGE,/* RCV clock Falling Edge */
2, /* Frame-sync pulse width=2 CLKG periods */
1024, /* Frame-sync pulse period = 1024 CLKG periods */
1, /* CLKGDIV = 1 means divide by input clock by 2 */
CSL_MCBSP_SRGCLK_CLKCPU, /* SCLKME = 0, CLKSM = 1 */
CSL_MCBSP_CLKPOL_SRG_RISING_EDGE, /* CLKS pin signal Rising Edge */
CSL_MCBSP_TXFSMODE_DXRCOPY, /* If FSGM = 1, XMT Frame-sync driven by
sample rate generater, FSG signal */
CSL_MCBSP_CLKGSYNCMODE_OFF /* GSYNC = 0 means no clock synchronisation */
};
/* Multichannel setup */
CSL_McbspMulChSetup mulChCfg = {
(CSL_McbspPartMode)CSL_MCBSP_PARTMODE_2PARTITION,
(CSL_McbspPartMode)CSL_MCBSP_PARTMODE_2PARTITION,
(Uint16)1, /* Receive multichannel selection enable */
(Uint16)2, /* Transmit multichannel selection enable */
(CSL_McbspPABlk)CSL_MCBSP_PABLK_0,
(CSL_McbspPBBlk)CSL_MCBSP_PBBLK_1,
(CSL_McbspPABlk)CSL_MCBSP_PABLK_0,
(CSL_McbspPBBlk)CSL_MCBSP_PBBLK_1
};
/* Mcbsp hwsetup */
CSL_McbspHwSetup myHwSetup = {
&gblCfg,
&rcvDataCfg,
&xmtDataCfg,
&clkCfg,
&mulChCfg,
CSL_MCBSP_EMU_STOP,
NULL
};
/*
* ============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* ============================================================================
*/
void main (void)
{
Bool mcbsp0En;
/* Unlock the control register */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the Powersavr for MCBSP 0 */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_MCBSP0CTL,
ENABLE);
do {
mcbsp0En = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_MCBSP0STAT);
} while (mcbsp0En != TRUE);
printf("Power saver clock for McBSP0 Enabled\n");
/* Invoke the example */
mcbsp_multichannel_example();
return;
}
/*
* ============================================================================
* @func mcbsp_multichannel_example
*
* @desc
* This function performs follwing steps:
* -# Opens one MCBSP port
* -# Resets MCBSP SRGR, XMT, RCV and Frame-sync
* -# Sets up MCBSP with the initialised hwSetup function
* and waits for 2 CLK cycles
* -# Brings MCBSP SRGR and Frame sync out of reset and waits for 2 CLK
* cycles
* -# Brings MCBSP XMT and RCV out of reset
* -# For every element to be trasmitted out of MCBSP, it first waits for
* XRDY signal to be ON and then writes that element
* -# Since MCBSP is configured in loopback, this value also comes at the
* receiver, which comes in RCV data register
* -# For every such element to be received, it waits for RRDY signal to
* be ON and then copies that element from RCV data register to
* a buffer
* -# After all the data is transmitted out of MCBSP, it compares
* the two buffers and prints the result to stdout
* -# In the end it closes the MCBSP instance that was opened
*
* ============================================================================
*/
void mcbsp_multichannel_example (void)
{
CSL_Status status = CSL_SOK;
CSL_McbspContext pContext;
CSL_McbspObj mcbspObj;
Uint16 loopIndex;
CSL_BitMask16 ctrlMask;
CSL_BitMask16 response;
Uint32 err = 0;
CSL_McbspHwSetup readHwSetup;
CSL_McbspChanControl channel;
CSL_McbspGlobalSetup globalSetup;
CSL_McbspDataSetup rxDataSetup;
CSL_McbspDataSetup txDataSetup;
CSL_McbspClkSetup clkSetup;
CSL_McbspMulChSetup mulChSetup;
/* Clear local data structures */
memset(&mcbspObj, 0, sizeof(CSL_McbspObj));
memset(&readHwSetup, 0, sizeof(CSL_McbspHwSetup));
printf("MCBSP Multichannel Example\n");
/* Allocated memory for variable */
readHwSetup.global = &globalSetup;
readHwSetup.rxdataset = &rxDataSetup;
readHwSetup.txdataset = &txDataSetup;
readHwSetup.clkset = &clkSetup;
readHwSetup.mulCh = &mulChSetup;
/* Initilize data buffers. xmt will be 32 bit value
* with element number in lower 16 bits and 2 * element
* in upper 16 bits. i.e. 0x00020001, 0x00040002, etc. */
for(loopIndex = 0; loopIndex <= NumOfWords - 1; loopIndex++) {
xmt[loopIndex] = (((Uint32) (loopIndex + 1) << 17) + (loopIndex + 1));
rcv[loopIndex] = 0;
}
/* Initialize the MCBSP CSL module */
status = CSL_mcbspInit(&pContext);
if (status != CSL_SOK) {
printf("Mcbsp initialization failed\n");
return;
}
/* Open the CSL module */
hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL, &status);
if ((hMcbsp == NULL) || (status != CSL_SOK)) {
printf ("MCBSP: Opening instance... Failed.\n");
printf ("\tReason: Error opening the instance. \
[status = 0x%x, hMcbsp = 0x%x]\n", status, hMcbsp);
exit(1);
}
/* Put SRG, Frame-sync, XMT and RCV in reset */
ctrlMask = CSL_MCBSP_CTRL_SRG_DISABLE
| CSL_MCBSP_CTRL_FSYNC_DISABLE
| CSL_MCBSP_CTRL_TX_DISABLE
| CSL_MCBSP_CTRL_RX_DISABLE;
status = CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
if (status != CSL_SOK) {
printf("Mcbsp CSL_MCBSP_CMD_RESET_CONTROL command failed\n");
return;
}
/* Program MCBSP control registers */
status = CSL_mcbspHwSetup(hMcbsp, &myHwSetup);
if (status != CSL_SOK) {
printf ("MCBSP: Hardware setup... Failed.\n");
exit(1);
}
/* Get the mcbsp control register values */
status = CSL_mcbspGetHwSetup (hMcbsp , &readHwSetup);
if (status != CSL_SOK) {
printf ("MCBSP: Get Hardware setup... Failed.\n");
exit(1);
}
/* Compare the hardware setup parameter values passed in the
* "hwSetup" structure by comparing them with the actual values read from
* the Mcbsp registers
*/
status = hwSetupVerify (&myHwSetup, &readHwSetup);
if (status != CSL_SOK){
printf ("MCBSP: Hardware setup and Read Hardware setup parameter ");
printf ("comparision ... Failed.\n");
exit(1);
}
/* Enabling the channels- 0 & 31 */
channel.channelNo = 0;
channel.operation = CSL_MCBSP_CHCTRL_RX_ENABLE;
CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_CHANNEL_CONTROL, &channel);
channel.channelNo = 31;
channel.operation = CSL_MCBSP_CHCTRL_RX_ENABLE;
CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_CHANNEL_CONTROL, &channel);
channel.channelNo = 0;
channel.operation = CSL_MCBSP_CHCTRL_TX_ENABLE;
CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_CHANNEL_CONTROL, &channel);
channel.channelNo = 31;
channel.operation = CSL_MCBSP_CHCTRL_TX_ENABLE;
CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_CHANNEL_CONTROL, &channel);
/* Start sample rate generator and wait for 2 clock cycles */
ctrlMask = CSL_MCBSP_CTRL_SRG_ENABLE | CSL_MCBSP_CTRL_FSYNC_ENABLE;
CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
/* Give small delay to start sample rate generator */
WAIT_FOR_2_CLK;
/* Enable MCBSP transmit and receive */
ctrlMask = CSL_MCBSP_CTRL_TX_ENABLE | CSL_MCBSP_CTRL_RX_ENABLE;
CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
/* Give small delay to enable transmit and receive */
WAIT_FOR_2_CLK;
printf("Waiting for transmission to Complete\n");
/* Begin data transfer loop. We will loop through to transmit
* and receive the data.
*/
for (loopIndex = 0; loopIndex <= NumOfWords - 1; loopIndex++) {
/* Wait for XRDY signal before writing data to DXR */
response = 0;
while (!(response & CSL_MCBSP_XRDY)) {
CSL_mcbspGetHwStatus(hMcbsp, CSL_MCBSP_QUERY_DEV_STATUS, &response);
}
/* Write 32 bit data value to DXR */
CSL_mcbspWrite (hMcbsp, CSL_MCBSP_WORDLEN_32, &xmt[loopIndex]);
/* Wait for RRDY signal to read data from DRR */
response = 0;
while (!(response & CSL_MCBSP_RRDY)) {
CSL_mcbspGetHwStatus(hMcbsp, CSL_MCBSP_QUERY_DEV_STATUS, &response);
}
/* Read 32 bit value from DRR */
CSL_mcbspRead (hMcbsp, CSL_MCBSP_WORDLEN_32, &rcv[loopIndex]);
}
/* Check data to make sure transfer was successful */
for(loopIndex = 0; loopIndex <= NumOfWords - 1; loopIndex++) {
if (xmt[loopIndex] != rcv[loopIndex]) {
printf("xmt[%d] != rcv[%d]\n", loopIndex, loopIndex);
++err;
}
else {
printf("xmt[%d] == rcv[%d]\n",loopIndex, loopIndex);
}
}
printf("\n%s",err?"TRANSMISSION: EXAMPLE FAILED\n":"TRANSMISSION SUCCESS\n");
/* We are done with MCBSP, so close it */
CSL_mcbspClose(hMcbsp);
return;
}
/*
* ============================================================================
* @func hwSetupVerify
*
* @desc
* This function compare the hardware setup parameter values passed in the
* "hwSetup" structure by comparing them with the actual values read from
* the Mcbsp registers.
*
* @arg hwSetup
* Pointer to the buffer containing the hardware setup parameters that
* are needed to be compare
* @arg hwSetupRead
* Pointer to the buffer containing the get hardware setup parameters that
* are needed to be compared with setup parameters
*
* ============================================================================
*/
CSL_Status hwSetupVerify (
CSL_McbspHwSetup *hwSetup,
CSL_McbspHwSetup *hwSetupRead
)
{
CSL_Status status = CSL_SOK;
/* Check the mcbsp global setup parameters */
if (hwSetupRead->global != NULL) {
if(!((hwSetup->global->dlbMode == hwSetupRead->global->dlbMode)
&&(hwSetup->global->clkStopMode == \
hwSetupRead->global->clkStopMode)
&&(hwSetup->global->ioEnableMode == \
hwSetupRead->global->ioEnableMode))) {
status = CSL_ESYS_FAIL;
}
}
/* Check the mcbsp receive data setup parameters */
if (hwSetupRead->rxdataset != NULL) {
if (!((hwSetup->rxdataset->numPhases == \
hwSetupRead->rxdataset->numPhases)
&&(hwSetup->rxdataset->wordLength1 == \
hwSetupRead->rxdataset->wordLength1)
&&(hwSetup->rxdataset->wordLength2 == \
hwSetupRead->rxdataset->wordLength2)
&&(hwSetup->rxdataset->frmLength1 == \
hwSetupRead->rxdataset->frmLength1)
&&(hwSetup->rxdataset->frmSyncIgn == \
hwSetupRead->rxdataset->frmSyncIgn)
&&(hwSetup->rxdataset->compand == \
hwSetupRead->rxdataset->compand)
&& (hwSetup->rxdataset->dataDelay == \
hwSetupRead->rxdataset->dataDelay)
&&(hwSetup->rxdataset->rjust_dxenable == \
hwSetupRead->rxdataset->rjust_dxenable)
&&(hwSetup->rxdataset->intEvent == \
hwSetupRead->rxdataset->intEvent)
&&(hwSetup->rxdataset->wordReverse == \
hwSetupRead->rxdataset->wordReverse))) {
status = CSL_ESYS_FAIL;
}
}
/* Check the mcbsp transmit data setup parameters */
if (hwSetupRead->txdataset != NULL) {
if (!((hwSetup->txdataset->numPhases == \
hwSetupRead->txdataset->numPhases)
&&(hwSetup->txdataset->wordLength1 == \
hwSetupRead->txdataset->wordLength1)
&&(hwSetup->txdataset->wordLength2 == \
hwSetupRead->txdataset->wordLength2)
&&(hwSetup->txdataset->frmLength1 == \
hwSetupRead->txdataset->frmLength1)
&&(hwSetup->txdataset->frmSyncIgn == \
hwSetupRead->txdataset->frmSyncIgn)
&&(hwSetup->txdataset->compand == \
hwSetupRead->txdataset->compand)
&&(hwSetup->txdataset->dataDelay == \
hwSetupRead->txdataset->dataDelay)
&&(hwSetup->txdataset->rjust_dxenable == \
hwSetupRead->txdataset->rjust_dxenable)
&&(hwSetup->txdataset->intEvent == \
hwSetupRead->txdataset->intEvent)
&&(hwSetup->txdataset->wordReverse == \
hwSetupRead->txdataset->wordReverse))) {
status = CSL_ESYS_FAIL;
}
}
/* Check the mcbsp clock setup parameters */
if (hwSetupRead->clkset != NULL) {
if (!((hwSetup->clkset->frmSyncRxMode == \
hwSetupRead->clkset->frmSyncRxMode)
&&(hwSetup->clkset->frmSyncTxMode == \
hwSetupRead->clkset->frmSyncTxMode)
&&(hwSetup->clkset->frmSyncRxPolarity == \
hwSetupRead->clkset->frmSyncRxPolarity)
&&(hwSetup->clkset->frmSyncTxPolarity == \
hwSetupRead->clkset->frmSyncTxPolarity)
&&(hwSetup->clkset->clkRxMode == \
hwSetupRead->clkset->clkRxMode)
&&(hwSetup->clkset->clkTxMode == \
hwSetupRead->clkset->clkTxMode)
&&(hwSetup->clkset->clkRxPolarity == \
hwSetupRead->clkset->clkRxPolarity)
&&(hwSetup->clkset->clkTxPolarity == \
hwSetupRead->clkset->clkTxPolarity)
&&(hwSetup->clkset->srgFrmPulseWidth == \
hwSetupRead->clkset->srgFrmPulseWidth)
&&(hwSetup->clkset->srgFrmPeriod == \
hwSetupRead->clkset->srgFrmPeriod)
&&(hwSetup->clkset->srgClkDivide == \
hwSetupRead->clkset->srgClkDivide)
&&(hwSetup->clkset->srgClkSync == \
hwSetupRead->clkset->srgClkSync)
&&(hwSetup->clkset->srgInputClkMode == \
hwSetupRead->clkset->srgInputClkMode)
&&(hwSetup->clkset->srgClkPolarity == \
hwSetupRead->clkset->srgClkPolarity)
&&(hwSetup->clkset->srgTxFrmSyncMode == \
hwSetupRead->clkset->srgTxFrmSyncMode))) {
status = CSL_ESYS_FAIL;
}
}
/* Check the mcbsp multichannel setup parameters */
if (hwSetupRead->mulCh != NULL) {
if(!((hwSetup->mulCh->rxMulChSel == hwSetupRead->mulCh->rxMulChSel)
&&(hwSetup->mulCh->txMulChSel == hwSetupRead->mulCh->txMulChSel)
&&(hwSetup->mulCh->rxPartition == hwSetupRead->mulCh->rxPartition)
&&(hwSetup->mulCh->rxPartABlk == hwSetupRead->mulCh->rxPartABlk)
&&(hwSetup->mulCh->rxPartBBlk == hwSetupRead->mulCh->rxPartBBlk)
&&(hwSetup->mulCh->txPartition == hwSetupRead->mulCh->txPartition)
&&(hwSetup->mulCh->txPartABlk == hwSetupRead->mulCh->txPartABlk)
&&(hwSetup->mulCh->txPartBBlk == \
hwSetupRead->mulCh->txPartBBlk))) {
status = !CSL_SOK;
}
}
/* Check the mcbsp emulation mode setup parameters */
if(!((hwSetup->emumode == hwSetupRead->emumode ) &&
(hwSetup->extendSetup == hwSetupRead->extendSetup))) {
status = CSL_ESYS_FAIL;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455/example/mcbsp/mcbsp_single_channel/src/Mcbsp_SinChannel_example.c | /* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
*
* @file Mcbsp_sinChannel_example.c
*
* @path $(CSLPATH)\example\mcbsp\mcbsp_single_channel\src
*
* @desc Example of MCBSP
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n In this example, the MCBSP0 is configured in digital loopback mode,
* with 16 bit data transfer, using sample rate generator
* to synchronise the frames. Normal mode(Single channel) of transmission
* is selected.
* This example,
* 1. Intializes and opens mcbsp module
* 2. Sets up the hardware to default values and single channel
* 16 bit data transfe i.e., CSL_mcbspHwSetup() is called for
* module configuration.
* 3. Brings MCBSP XMT and RCV out of reset
* 4. For every element to be trasmitted out of MCBSP, it first waits
* for XRDY signal to be ON and then writes that element
* 6. Since MCBSP is configured in loopback, this value also comes at
* the receiver, which comes in RCV data register
* 7. For every such element to be received, it waits for RRDY signal
* to be ON and then copies that element from RCV data register to
* a buffer
* 8. Does the data comparision to ensure the written data is proper or
* not and
* 9. Displays the messages based on step 8
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Mcbsp_sinChannel_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 25-April-2005 <NAME>. created
*
* 16-Dec-2005 ds Updated documentation
* 07-Feb-2006 ds Added "intEvent" configuration to rcvDataCfg and
* xmtDataCfg and Changed to use DEV functional layer
* 21-Feb-2006 ds Alocated Memory for readHwsetup structure variable which
* is used in CSL_mcbspGetHwSetup() API call.
* Cleared local data structures
* Added Code to compare the Hwsetup and read Hwsetup
* parameters
* ============================================================================
*/
#include <csl_mcbsp.h>
#include <cslr_dev.h>
#include <soc.h>
#include <stdio.h>
/* Macro that gives 2 CLK delay cycles */
#define WAIT_FOR_2_CLK do { \
volatile int delayCnt = 2; \
while(delayCnt > 0) --delayCnt; \
}while (0)
/* Global constants- Number of words to transfer */
#define NumOfWords 100
/* Function declarations */
void singleChannelTransmission(void);
CSL_Status hwSetupVerify (CSL_McbspHwSetup *,
CSL_McbspHwSetup *
);
/* Handle for the MCBSP instance */
CSL_McbspHandle hMcbsp;
/* Create data buffers for transfer */
Uint16 xmt[NumOfWords];
Uint16 rcv[NumOfWords];
/* Global data definition */
CSL_McbspGlobalSetup mcbspGbl = {
CSL_MCBSP_IOMODE_TXDIS_RXDIS ,
CSL_MCBSP_DLBMODE_ON,
CSL_MCBSP_CLKSTP_DISABLE
};
/* Receive data setup */
CSL_McbspDataSetup mcbspRxData = {
CSL_MCBSP_PHASE_SINGLE,
CSL_MCBSP_WORDLEN_16,
1, //frame length
(CSL_McbspWordLen)0,
0,
CSL_MCBSP_FRMSYNC_IGNORE, //frame sinc ignore
CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
CSL_MCBSP_DATADELAY_0_BIT,
CSL_MCBSP_RJUSTDXENA_RJUST_RZF ,
CSL_MCBSP_INTMODE_ON_READY,
CSL_MCBSP_32BIT_REVERS_DISABLE
};
/* Transmit data setup */
CSL_McbspDataSetup mcbspTxData = {
CSL_MCBSP_PHASE_SINGLE,
CSL_MCBSP_WORDLEN_16,
1,
(CSL_McbspWordLen)0,
0,
CSL_MCBSP_FRMSYNC_IGNORE,
CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
CSL_MCBSP_DATADELAY_0_BIT,
CSL_MCBSP_RJUSTDXENA_DXENA_OFF ,
CSL_MCBSP_INTMODE_ON_READY,
CSL_MCBSP_32BIT_REVERS_DISABLE
};
/* Clock setup defaults */
CSL_McbspClkSetup mcbspClock = {
CSL_MCBSP_FSCLKMODE_INTERNAL, /* XMT Frame-sync */
CSL_MCBSP_FSCLKMODE_INTERNAL, /* RCV Frame-sync */
CSL_MCBSP_TXRXCLKMODE_INTERNAL, /* XMT clock */
CSL_MCBSP_TXRXCLKMODE_INTERNAL, /* RCV clock */
CSL_MCBSP_FSPOL_ACTIVE_HIGH, /* XMT Frame-sync active high */
CSL_MCBSP_FSPOL_ACTIVE_HIGH, /* RCV Frame-sync active high */
CSL_MCBSP_CLKPOL_TX_RISING_EDGE, /* XMT clock rising edge */
CSL_MCBSP_CLKPOL_RX_FALLING_EDGE,/* RCV clock falling edge */
1, /* Frame-sync pulse width = 1 bit */
0x40, /* Frame-sync pulse period */
0x1, /*clk divide by 2 */
CSL_MCBSP_SRGCLK_CLKCPU,
CSL_MCBSP_CLKPOL_TX_RISING_EDGE ,/* CLKS pin signal rising edge */
CSL_MCBSP_TXFSMODE_DXRCOPY,
CSL_MCBSP_CLKGSYNCMODE_OFF /* GSYNC = 0 means no clock synchronisation */
};
/* Multichannel setup */
CSL_McbspMulChSetup mcbspMul = {
CSL_MCBSP_PARTMODE_2PARTITION, /* RX */
CSL_MCBSP_PARTMODE_2PARTITION, /* TX */
(Uint16)0, /* rxMulChSel */
(Uint16)0, /* txMulChSel */
CSL_MCBSP_PABLK_0,/* rxPartABlk */
CSL_MCBSP_PBBLK_1,/* rxPartBBlk */
CSL_MCBSP_PABLK_0,/* txPartABlk */
CSL_MCBSP_PBBLK_1 /* txPartABlk */
};
/* Mcbsp hwsetup */
CSL_McbspHwSetup myHwSetup = {
&mcbspGbl,
&mcbspRxData,
&mcbspTxData,
&mcbspClock,
&mcbspMul,
CSL_MCBSP_EMU_FREERUN,
NULL
};
/*
* ============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* ============================================================================
*/
void main (void)
{
Bool mcbsp0En;
/* Unlock the PERCFG0 register */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the powersaver for the MCBSP 0 */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_MCBSP0CTL,
ENABLE);
do {
mcbsp0En = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_MCBSP0STAT);
} while (mcbsp0En != TRUE);
printf("Powersaver for MCBSP 0 is enabled\n");
/* Invoke example */
singleChannelTransmission();
return;
}
/*
* ============================================================================
* @func singleChannelTransmission()
*
* @desc
* This function performs following steps:
* -# Opens one MCBSP port
* -# Resets MCBSP SRGR, XMT, RCV and Frame-sync
* -# Brings MCBSP XMT and RCV out of reset
* -# For every element to be transmitted out of MCBSP, it first waits for
* XRDY signal to be ON and then writes that element
* -# Since MCBSP is configured in loopback, this value also comes at the
* receiver, which comes in RCV data register
* -# For every such element to be received, it waits for RRDY signal to
* be ON and then copies that element from RCV data register to
* a buffer
* -# After all the data is transmitted out of MCBSP, it compares
* the two buffers and prints the result to stdout
* -# In the end it closes the MCBSP instance that was opened
*
* ============================================================================
*/
void singleChannelTransmission(void)
{
CSL_Status status = CSL_SOK;
CSL_McbspContext pContext;
CSL_McbspObj mcbspObj;
Uint16 loopIndex;
CSL_BitMask16 ctrlMask;
CSL_BitMask16 response;
CSL_McbspHwSetup readHwSetup;
Uint16 maxTimeout = 1000;
Uint16 timeout = 0;
Uint16 errCount = 0;
CSL_McbspGlobalSetup globalSetup;
CSL_McbspDataSetup rxDataSetup;
CSL_McbspDataSetup txDataSetup;
CSL_McbspClkSetup clkSetup;
/* Clear local data structures */
memset (&readHwSetup, 0, sizeof(CSL_McbspHwSetup));
memset (&mcbspObj, 0, sizeof(CSL_McbspObj));
/* Allocated memory for variable */
readHwSetup.global = &globalSetup;
readHwSetup.rxdataset = &rxDataSetup;
readHwSetup.txdataset = &txDataSetup;
readHwSetup.clkset = &clkSetup;
/* Data Arrays */
for (loopIndex = 0; loopIndex < NumOfWords; loopIndex++) {
xmt[loopIndex] = loopIndex;
rcv[loopIndex] = 0;
}
printf("\n***singleChannelTransmission***\n");
/* Initialize the MCBSP CSL module */
status = CSL_mcbspInit(&pContext);
if (status != CSL_SOK) {
printf("Mcbsp initialization failed\n");
return;
}
/* Open the CSL module */
hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL, &status);
if ((hMcbsp == NULL) || (status != CSL_SOK)) {
printf ("MCBSP: Opening instance... Failed.\n");
printf ("\tReason: Error opening the instance. \
[status = 0x%x, hMcbsp = 0x%x]\n", status, hMcbsp);
exit(1);
}
/* Disable MCBSP transmit and receive */
ctrlMask = CSL_MCBSP_CTRL_RX_DISABLE
| CSL_MCBSP_CTRL_TX_DISABLE
| CSL_MCBSP_CTRL_FSYNC_DISABLE
| CSL_MCBSP_CTRL_SRG_DISABLE;
CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
/* Setup hardware parameters */
status= CSL_mcbspHwSetup (hMcbsp , &myHwSetup);
if (status != CSL_SOK){
printf ("MCBSP: Hardware setup... Failed.\n");
exit(1);
}
/* Get Hw setup Parameters */
status = CSL_mcbspGetHwSetup (hMcbsp , &readHwSetup);
if (status != CSL_SOK){
printf ("MCBSP: Get Hardware setup... Failed.\n");
exit(1);
}
/* Compare the hardware setup parameter values passed in the
* "hwSetup" structure by comparing them with the actual values read from
* the Mcbsp registers
*/
status = hwSetupVerify (&myHwSetup, &readHwSetup);
if (status != CSL_SOK){
printf ("MCBSP: Hardware setup and Read Hardware setup parameter ");
printf ("comparision ... Failed.\n");
exit(1);
}
/* Start sample rate generator and wait for 2 clock cycles */
ctrlMask = CSL_MCBSP_CTRL_SRG_ENABLE | CSL_MCBSP_CTRL_FSYNC_ENABLE;
CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
WAIT_FOR_2_CLK;
/* Enable MCBSP transmit and receive and wait for 2 clock cycles */
ctrlMask = CSL_MCBSP_CTRL_TX_ENABLE | CSL_MCBSP_CTRL_RX_ENABLE;
CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);
WAIT_FOR_2_CLK;
for(loopIndex = 0; loopIndex < NumOfWords; loopIndex++) {
timeout = 0;
/* Wait for XRDY signal before writing data to DXR */
response = 0;
while ((timeout++ < maxTimeout) && !(response & CSL_MCBSP_XRDY)) {
CSL_mcbspGetHwStatus(hMcbsp, CSL_MCBSP_QUERY_DEV_STATUS, &response);
}
if(timeout >= maxTimeout) {
printf("MCBSP: Example Failed\n");
printf("\tReason: Failed to make the transmitter ready\n");
exit(1);
}
/* Write 16 bit data value to DXR */
CSL_mcbspWrite (hMcbsp, CSL_MCBSP_WORDLEN_16, &xmt[loopIndex]);
timeout = 0;
/* Read 16 bit value from DRR and check the data */
response = 0;
while ((timeout++ < maxTimeout) && !(response & CSL_MCBSP_RRDY)) {
CSL_mcbspGetHwStatus(hMcbsp, CSL_MCBSP_QUERY_DEV_STATUS, &response);
}
/* Read 16 bit value from DRR */
CSL_mcbspRead (hMcbsp, CSL_MCBSP_WORDLEN_16, &rcv[loopIndex]);
if(xmt[loopIndex] != rcv[loopIndex])
errCount++;
}
/* Check the data to make sure transfer was successful and print data */
for(loopIndex = 0; loopIndex <= NumOfWords - 1; loopIndex++) {
if (xmt[loopIndex] != rcv[loopIndex]) {
printf("xmt[%d] != rcv[%d]\n", loopIndex, loopIndex);
}
else {
printf("xmt[%d] == rcv[%d]\n", loopIndex, loopIndex);
}
}
/* Check for error count to display example result */
if (errCount > 0) {
printf("MCBSP: Single Channel Transmission Example... Failed.\n");
}
else {
printf("MCBSP: Single Channel Transmission Example... Success.\n");
}
}
/*
* ============================================================================
* @func hwSetupVerify
*
* @desc
* This function compare the hardware setup parameter values passed in the
* "hwSetup" structure by comparing them with the actual values read from
* the Mcbsp registers.
*
* @arg hwSetup
* Pointer to the buffer containing the hardware setup parameters that
* are needed to be compare
* @arg hwSetupRead
* Pointer to the buffer containing the get hardware setup parameters that
* are needed to be compared with setup parameters
*
* ============================================================================
*/
CSL_Status hwSetupVerify (
CSL_McbspHwSetup *hwSetup,
CSL_McbspHwSetup *hwSetupRead
)
{
CSL_Status status = CSL_SOK;
/* Check the mcbsp global setup parameters */
if (hwSetupRead->global != NULL) {
if(!((hwSetup->global->dlbMode == hwSetupRead->global->dlbMode)
&&(hwSetup->global->clkStopMode == \
hwSetupRead->global->clkStopMode)
&&(hwSetup->global->ioEnableMode == \
hwSetupRead->global->ioEnableMode))) {
status = CSL_ESYS_FAIL;
}
}
/* Check the mcbsp receive data setup parameters */
if (hwSetupRead->rxdataset != NULL) {
if (!((hwSetup->rxdataset->numPhases == \
hwSetupRead->rxdataset->numPhases)
&&(hwSetup->rxdataset->wordLength1 == \
hwSetupRead->rxdataset->wordLength1)
&&(hwSetup->rxdataset->wordLength2 == \
hwSetupRead->rxdataset->wordLength2)
&&(hwSetup->rxdataset->frmLength1 == \
hwSetupRead->rxdataset->frmLength1)
&&(hwSetup->rxdataset->frmSyncIgn == \
hwSetupRead->rxdataset->frmSyncIgn)
&&(hwSetup->rxdataset->compand == \
hwSetupRead->rxdataset->compand)
&& (hwSetup->rxdataset->dataDelay == \
hwSetupRead->rxdataset->dataDelay)
&&(hwSetup->rxdataset->rjust_dxenable == \
hwSetupRead->rxdataset->rjust_dxenable)
&&(hwSetup->rxdataset->intEvent == \
hwSetupRead->rxdataset->intEvent)
&&(hwSetup->rxdataset->wordReverse == \
hwSetupRead->rxdataset->wordReverse))) {
status = CSL_ESYS_FAIL;
}
}
/* Check the mcbsp transmit data setup parameters */
if (hwSetupRead->txdataset != NULL) {
if (!((hwSetup->txdataset->numPhases == \
hwSetupRead->txdataset->numPhases)
&&(hwSetup->txdataset->wordLength1 == \
hwSetupRead->txdataset->wordLength1)
&&(hwSetup->txdataset->wordLength2 == \
hwSetupRead->txdataset->wordLength2)
&&(hwSetup->txdataset->frmLength1 == \
hwSetupRead->txdataset->frmLength1)
&&(hwSetup->txdataset->frmSyncIgn == \
hwSetupRead->txdataset->frmSyncIgn)
&&(hwSetup->txdataset->compand == \
hwSetupRead->txdataset->compand)
&&(hwSetup->txdataset->dataDelay == \
hwSetupRead->txdataset->dataDelay)
&&(hwSetup->txdataset->rjust_dxenable == \
hwSetupRead->txdataset->rjust_dxenable)
&&(hwSetup->txdataset->intEvent == \
hwSetupRead->txdataset->intEvent)
&&(hwSetup->txdataset->wordReverse == \
hwSetupRead->txdataset->wordReverse))) {
status = CSL_ESYS_FAIL;
}
}
/* Check the mcbsp clock setup parameters */
if (hwSetupRead->clkset != NULL) {
if (!((hwSetup->clkset->frmSyncRxMode == \
hwSetupRead->clkset->frmSyncRxMode)
&&(hwSetup->clkset->frmSyncTxMode == \
hwSetupRead->clkset->frmSyncTxMode)
&&(hwSetup->clkset->frmSyncRxPolarity == \
hwSetupRead->clkset->frmSyncRxPolarity)
&&(hwSetup->clkset->frmSyncTxPolarity == \
hwSetupRead->clkset->frmSyncTxPolarity)
&&(hwSetup->clkset->clkRxMode == \
hwSetupRead->clkset->clkRxMode)
&&(hwSetup->clkset->clkTxMode == \
hwSetupRead->clkset->clkTxMode)
&&(hwSetup->clkset->clkRxPolarity == \
hwSetupRead->clkset->clkRxPolarity)
&&(hwSetup->clkset->clkTxPolarity == \
hwSetupRead->clkset->clkTxPolarity)
&&(hwSetup->clkset->srgFrmPulseWidth == \
hwSetupRead->clkset->srgFrmPulseWidth)
&&(hwSetup->clkset->srgFrmPeriod == \
hwSetupRead->clkset->srgFrmPeriod)
&&(hwSetup->clkset->srgClkDivide == \
hwSetupRead->clkset->srgClkDivide)
&&(hwSetup->clkset->srgClkSync == \
hwSetupRead->clkset->srgClkSync)
&&(hwSetup->clkset->srgInputClkMode == \
hwSetupRead->clkset->srgInputClkMode)
&&(hwSetup->clkset->srgClkPolarity == \
hwSetupRead->clkset->srgClkPolarity)
&&(hwSetup->clkset->srgTxFrmSyncMode == \
hwSetupRead->clkset->srgTxFrmSyncMode))) {
status = CSL_ESYS_FAIL;
}
}
/* Check the mcbsp emulation mode setup parameters */
if(!((hwSetup->emumode == hwSetupRead->emumode ) &&
(hwSetup->extendSetup == hwSetupRead->extendSetup))) {
status = CSL_ESYS_FAIL;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnOpen.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_pwrdwnOpen.c
*
* @path $(CSLPATH)\src\pwrdwn
*
* @desc File for functional layer of CSL API CSL_pwrdwnOpen ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 16-Jul-2004 <NAME> File Created
* =============================================================================
*/
#include <csl_pwrdwn.h>
/** ============================================================================
* @b CSL_ pwrdwnOpen
*
* @b Description
* @n This function populates the peripheral data object for the PWRDWN
* instance and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of PWRDWN device. The device can be re-opened anytime after it has been
* normally closed if so required. The handle returned by this call is
* input as an essential argument for rest of the APIs described
* for this module.
*
* @b Arguments
* @verbatim
pwrdwnObj Pointer to PWRDWN object.
pwrdwnNum Instance of pwrdwn CSL to be opened.
There are three instance of the PWRDWN
available. So, the value for this parameter will be
based on the instance.
pPwrdwnParam Module specific parameters.
status Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_pwrdwnHandle
* @n Valid pwrdwn handle will be returned if
* status value is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen()must be opened prior to this call
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid pwrdwn handle is returned
* @li CSL_ESYS_FAIL The pwrdwn instance is invalid
* @li CSL_ESYS_INVPARAMS Invalid Parameters
*
* 2. pwrdwn object structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. pwrdwn object structure
*
* @b Example
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments fof the Config structure
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pwrdwnOpen, ".text:csl_section:pwrdwn");
CSL_PwrdwnHandle CSL_pwrdwnOpen (
CSL_PwrdwnObj *pPwrdwnObj,
CSL_InstNum pwrdwnNum,
CSL_PwrdwnParam *pPwrdwnParam,
CSL_Status *pStatus
)
{
CSL_PwrdwnBaseAddress baseAddress;
CSL_PwrdwnHandle hPwrdwn = (CSL_PwrdwnHandle)NULL;
if (pStatus == NULL) {
/* do nothing : already the module is initialized to NULL */
}
else if (pPwrdwnObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
*pStatus = CSL_pwrdwnGetBaseAddress(pwrdwnNum, pPwrdwnParam, &baseAddress);
if (*pStatus == CSL_SOK) {
pPwrdwnObj->pdcRegs = baseAddress.regs;
pPwrdwnObj->l2pwrdwnRegs = baseAddress.l2pwrdwnRegs;
pPwrdwnObj->instNum = (CSL_InstNum)pwrdwnNum;
hPwrdwn = (CSL_PwrdwnHandle)pPwrdwnObj;
}
else {
pPwrdwnObj->pdcRegs = (CSL_PdcRegsOvly)NULL;
pPwrdwnObj->l2pwrdwnRegs = NULL;
pPwrdwnObj->instNum = (CSL_InstNum)-1;
}
}
return (hPwrdwn);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcGetHwSetup.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** @file csl_pllcGetHwSetup.c
*
* @brief File for functional layer of CSL API @a CSL_pllcGetHwSetup()
*
* Path: \(CSLPATH)\src\pllc
*/
/* ============================================================================
* Revision History
* ===============
* 26-Aug-2005 Tej File created.
* 27-oct-2005 sd changes for multiplier configuration
* 18-Jan-2006 sd Changes according to spec changes
* ============================================================================
*/
#include <csl_pllc.h>
/** ============================================================================
* @n@b CSL_pllcGetHwSetup
*
* @b Description
* @n It retrives the hardware setup parameters of the pllc
* specified by the given handle.
*
* @b Arguments
* @verbatim
hPllc Handle to the pllc
hwSetup Pointer to the hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Retrieving the hardware setup
* parameters is successful
* @li CSL_ESYS_BADHANDLE - The handle is passed is
* invalid
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The hardware setup structure is populated with the hardware setup
* parameters
*
* @b Modifies
* @n hwSetup variable
*
* @b Example
* @verbatim
CSL_PllcHandle hPllc;
CSL_PllcHwSetup hwSetup;
...
status = CSL_pllcGetHwSetup(hPllc, &hwSetup);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pllcGetHwSetup, ".text:csl_section:pllc");
CSL_Status CSL_pllcGetHwSetup (
CSL_PllcHandle hPllc,
CSL_PllcHwSetup *hwSetup
)
{
CSL_Status status = CSL_SOK;
CSL_PllcRegsOvly pllcRegs = hPllc->regs;
if (hPllc == NULL ) {
status = CSL_ESYS_BADHANDLE;
}
else if (hwSetup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
hwSetup->divEnable = 0;
if (hPllc->pllcNum == CSL_PLLC_1) {
hwSetup->pllMode = (CSL_FEXT( pllcRegs->PLLCTL, PLLC_PLLCTL_PLLEN)) ||
(CSL_FEXT( pllcRegs->PLLCTL, PLLC_PLLCTL_PLLENSRC))||
(CSL_FEXT( pllcRegs->PLLCTL, PLLC_PLLCTL_PLLRST)) ||
(CSL_FEXT( pllcRegs->PLLCTL, PLLC_PLLCTL_PLLPWRDN));
if (CSL_FEXT (pllcRegs->PREDIV, PLLC_PREDIV_PREDEN)) {
hwSetup->divEnable |= CSL_PLLC_DIVEN_PREDIV;
hwSetup->preDiv = CSL_FEXT (pllcRegs->PREDIV, PLLC_PREDIV_RATIO) + 1;
}
hwSetup->pllM = CSL_FEXT (pllcRegs->PLLM, PLLC_PLLM_PLLM) + 1;
if (CSL_FEXT (pllcRegs->PLLDIV4, PLLC_PLLDIV4_D4EN)) {
hwSetup->divEnable |= CSL_PLLC_DIVEN_PLLDIV4;
hwSetup->pllDiv4 = CSL_FEXT (pllcRegs->PLLDIV4, PLLC_PLLDIV4_RATIO) + 1;
}
if (CSL_FEXT (pllcRegs->PLLDIV5, PLLC_PLLDIV5_D5EN)) {
hwSetup->divEnable |= CSL_PLLC_DIVEN_PLLDIV5;
hwSetup->pllDiv5 = CSL_FEXT (pllcRegs->PLLDIV5, PLLC_PLLDIV5_RATIO) + 1;
}
}
if (hPllc->pllcNum == CSL_PLLC_2) {
if (CSL_FEXT (pllcRegs->PLLDIV1, PLLC_PLLDIV1_D1EN)) {
hwSetup->divEnable |= CSL_PLLC_DIVEN_PLLDIV1;
hwSetup->pllDiv1 = CSL_FEXT (pllcRegs->PLLDIV1, PLLC_PLLDIV1_RATIO) + 1;
}
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c64xplus_intc_src/inc/cslr.h | /*****************************************************\
* Copyright 2003-2005 Texas Instruments Incorporated. *
* All rights reserved. *
* Restricted rights to use, duplicate or disclose *
* this code are granted through contract. *
* *
* "@(#) PSP/CSL 3.0.0.0 (2003-09-30) *
\*****************************************************/
/* Register layer central -- contains field-manipulation macro definitions */
#ifndef _CSLR_H_
#define _CSLR_H_
/* the "expression" macros */
/* the Field MaKe macro */
#define CSL_FMK(PER_REG_FIELD, val) \
(((val) << CSL_##PER_REG_FIELD##_SHIFT) & CSL_##PER_REG_FIELD##_MASK)
/* the Field EXTract macro */
#define CSL_FEXT(reg, PER_REG_FIELD) \
(((reg) & CSL_##PER_REG_FIELD##_MASK) >> CSL_##PER_REG_FIELD##_SHIFT)
/* the Field INSert macro */
#define CSL_FINS(reg, PER_REG_FIELD, val) \
((reg) = ((reg) & ~CSL_##PER_REG_FIELD##_MASK) \
| CSL_FMK(PER_REG_FIELD, val))
/* the "token" macros */
/* the Field MaKe (Token) macro */
#define CSL_FMKT(PER_REG_FIELD, TOKEN) \
CSL_FMK(PER_REG_FIELD, CSL_##PER_REG_FIELD##_##TOKEN)
/* the Field INSert (Token) macro */
#define CSL_FINST(reg, PER_REG_FIELD, TOKEN) \
CSL_FINS((reg), PER_REG_FIELD, CSL_##PER_REG_FIELD##_##TOKEN)
/* the "raw" macros */
/* the Field MaKe (Raw) macro */
#define CSL_FMKR(msb, lsb, val) \
(((val) & ((1 << ((msb) - (lsb) + 1)) - 1)) << (lsb))
/* the Field EXTract (Raw) macro */
#define CSL_FEXTR(reg, msb, lsb) \
(((reg) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
/* the Field INSert (Raw) macro */
#define CSL_FINSR(reg, msb, lsb, val) \
((reg) = ((reg) &~ (((1 << ((msb) - (lsb) + 1)) - 1) << (lsb))) \
| CSL_FMKR(msb, lsb, val))
#endif /* _CSLR_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspInit.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_mcbspInit.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API CSL_mcbspInit()
*
*/
/* =============================================================================
* Revision History
* ================
* June 29,2004 <NAME> - Created
*
* =============================================================================
*/
#include <csl_mcbsp.h>
/** ============================================================================
* @n@b CSL_mcbspInit
*
* @b Description
* @n This function is idempotent i.e. calling it many times is same as
* calling it once. This function is only for book-keeping purpose
* and it doesn't touch the hardware (read/write registers) in any manner.
*
* @b Arguments
@verbatim
pContext Pointer to module-context. As mcbsp doesn't have
any context based information user is expected
to pass NULL.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CSL_mcbspInit();
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_mcbspInit, ".text:csl_section:mcbsp");
CSL_Status CSL_mcbspInit (
CSL_McbspContext *pContext
)
{
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/inc/cslr_pwrdwnPdc.h | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_pdc.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for PDC
*/
#ifndef _CSLR_PDC_H_
#define _CSLR_PDC_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 PDCCMD;
} CSL_PdcRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_PdcRegs *CSL_PdcRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* PDCCMD */
#define CSL_PDC_PDCCMD_MEGPD_MASK (0x00010000u)
#define CSL_PDC_PDCCMD_MEGPD_SHIFT (0x00000010u)
#define CSL_PDC_PDCCMD_MEGPD_RESETVAL (0x00000000u)
/*----MEGPD Tokens----*/
#define CSL_PDC_PDCCMD_MEGPD_NORMAL (0x00000000u)
#define CSL_PDC_PDCCMD_MEGPD_SLEEP (0x00000001u)
#define CSL_PDC_PDCCMD_RESETVAL (0x0000FFFFu)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspOpen.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_mcbspOpen.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API CSL_mcbspOpen()
*
*/
/* =============================================================================
* Revision History
* ================
* 15-Feb-2005 NSR - Updated function and documentation for CSL_mcbspOpen.
* - Removed the include file, csl_resource.h.
* 15-Nov-2005 ds - Removed *pMcbspParam = *pMcbspParam
*
* =============================================================================
*/
#include <csl_mcbsp.h>
/** ============================================================================
* @n@b CSL_mcbspOpen
*
* @b Description
* @n Reserves the specified MCBSP for use. The device can be re-opened
* anytime after it has been normally closed, if so required.
* The MCBSP handle returned by this call is input as an essential argument
* for the rest of the APIs in MCBSP module.
*
* @b Arguments
* @verbatim
mcbspObj Mcbsp Module Object pointer
mcbspNum Instance of Mcbsp
pMcbspParam Parameter for McBSP
status Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_McbspHandle
* @li Valid Mcbsp handle will be returned if status value
* is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n The MCbsp must be succesfully initialized via CSL_mcbspInit() before
* calling this function.
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid MCBSP handle is returned
* @li CSL_ESYS_FAIL The MCBSP instance is invalid
* @li CSL_ESYS_INVPARAMS The Parameter passed is invalid
*
* 2. Mcbsp object structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Mcbsp object structure
*
* @b Example
* @verbatim
CSL_McbspHandle hMcbsp;
CSL_McbspObj mcbspObj;
CSL_McbspHwSetup mcbspSetup;
CSL_Status status;
...
hMcbsp = CSL_mcbspOpen(&mcbspObj, CSL_MCBSP_0, NULL, &status);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_mcbspOpen, ".text:csl_section:mcbsp");
CSL_McbspHandle CSL_mcbspOpen (
CSL_McbspObj *pMcbspObj,
CSL_InstNum mcbspNum,
CSL_McbspParam *pMcbspParam,
CSL_Status *pStatus
)
{
CSL_Status status;
CSL_McbspHandle hMcbsp = NULL;
CSL_McbspBaseAddress baseAddress;
if (pStatus == NULL) {
/* do nothing */
}
else if (pMcbspObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else{
status = CSL_mcbspGetBaseAddress(mcbspNum, pMcbspParam, &baseAddress);
if (status == CSL_SOK) {
pMcbspObj->regs = baseAddress.regs;
pMcbspObj->perNum = (CSL_InstNum)mcbspNum;
hMcbsp = (CSL_McbspHandle)pMcbspObj;
}
else {
pMcbspObj->regs = (CSL_McbspRegsOvly)NULL;
pMcbspObj->perNum = (CSL_InstNum)-1;
hMcbsp = (CSL_McbspHandle)NULL;
}
*pStatus = status;
}
return hMcbsp;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtGetHwSetup.c | /* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* priovided
* ============================================================================
*/
/** ============================================================================
* @file csl_bwmngmtGetHwSetup.c
*
* @path $(CSLPATH)\src\bwmngmt
*
* @desc File for functional layer of CSL API CSL_bwmngmtGetHwSetup()
*
*/
/* =============================================================================
* Revision History
* ===============
* 04-Jun-2004 <NAME> File Created
*
* 11-Apr-2005 Brn updated the file for doxygen compatibiliy
*
* 16-Nov-2005 ds updated the documentation
* =============================================================================
*/
#include <csl_bwmngmt.h>
/** ============================================================================
* @n@b CSL_bwmngmtGetHwSetup
*
* @b Description
* @n Gets the current set up of BWMNGMT
*
* @b Arguments
* @verbatim
hBwmngmt Handle to the BWMNGMT instance
setup Setup structure for BWMNGMT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* CSL_SOK - Close successful
* CSL_ESYS_BADHANDLE - Invalid handle
* CSL_ESYS_INVPARAMS - IF setup is NULL
*
* <b> Pre Condition </b>
* @n Both CSL_bwmngmtInit() and CSL_bwmngmtOpen() must be called
* successfully in that order before this function can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n
* 1. CPU Arbitration Parameters
* - PRI field set in Control Block Specified by "control" \n
* - MAXWAIT field set in Control Block Specified by "control" \n
*
* 2. IDMA Arbitration Parameter \n
* - MAXWAIT field set in Control Block Specified by "control" \n
*
* 3. SLAP Arbitration Parameter \n
* - MAXWAIT field set in Control Block Specified by "control" \n
*
* 4. MAP Arbitration Parameter \n
* - PRI field set in Control Block Specified by "control" \n
* if not EXT then returns CSL_BWMNGMT_PRI_NULL \n
*
* 5. UC Arbitration Parameter \n
* - MAXWAIT field set in Control Block Specified by "control" \n
* if not L1D or L2 then returns CSL_BWMNGMT_MAXWAIT_NULL \n
*
* @b Example:
* @verbatim
CSL_BwmngmtHandle hBwmngmt;
CSL_BwmngmtHwSetup hwSetup;
hwSetup.control = CSL_BWMNGMT_BLOCK_L1D;
// only CSL_BWMNGMT_BLOCK_L1D, CSL_BWMNGMT_BLOCK_L2, or
// CSL_BWMNGMT_BLOCK_EXT are valid
...
// Init Successfully done
...
// Open Successfully done
...
CSL_bwmngmtGetHwSetup(hBwmngmt, &hwSetup);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_bwmngmtGetHwSetup, ".text:csl_section:bwmngmt");
CSL_Status CSL_bwmngmtGetHwSetup (
CSL_BwmngmtHandle hBwmngmt,
CSL_BwmngmtHwSetup *hwSetup
)
{
CSL_Status status = CSL_SOK;
Uint32 ControlBlock;
if (hBwmngmt == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (hwSetup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
ControlBlock = hwSetup->control;
if (ControlBlock == CSL_BWMNGMT_BLOCK_L1D) {
hwSetup->cpuPriority = (CSL_BwmngmtPriority)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBL1D,
BWMNGMT_CPUARBL1D_PRI);
hwSetup->cpuMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBL1D,
BWMNGMT_CPUARBL1D_MAXWAIT);
hwSetup->idmaMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->IDMAARBL1D,
BWMNGMT_IDMAARBL1D_MAXWAIT);
hwSetup->slapMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->SLAPARBL1D,
BWMNGMT_SLAPARBL1D_MAXWAIT);
hwSetup->ucMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->UCARBL1D,
BWMNGMT_UCARBL1D_MAXWAIT);
}
else if (ControlBlock == CSL_BWMNGMT_BLOCK_L2) {
hwSetup->cpuPriority = (CSL_BwmngmtPriority)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBL2,
BWMNGMT_CPUARBL2_PRI);
hwSetup->cpuMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBL2,
BWMNGMT_CPUARBL2_MAXWAIT);
hwSetup->idmaMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->IDMAARBL2,
BWMNGMT_IDMAARBL2_MAXWAIT);
hwSetup->slapMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->SLAPARBL2,
BWMNGMT_SLAPARBL2_MAXWAIT);
hwSetup->ucMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->UCARBL2,
BWMNGMT_UCARBL2_MAXWAIT);
}
else if (ControlBlock == CSL_BWMNGMT_BLOCK_EXT) {
hwSetup->cpuPriority = (CSL_BwmngmtPriority)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBEXT,
BWMNGMT_CPUARBEXT_PRI);
hwSetup->cpuMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->CPUARBEXT,
BWMNGMT_CPUARBEXT_MAXWAIT);
hwSetup->idmaMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->IDMAARBEXT,
BWMNGMT_IDMAARBEXT_MAXWAIT);
hwSetup->slapMaxwait = (CSL_BwmngmtMaxwait)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->SLAPARBEXT,
BWMNGMT_SLAPARBEXT_MAXWAIT);
hwSetup->mapPriority = (CSL_BwmngmtPriority)
CSL_FEXT(((CSL_BwmngmtRegs *)CSL_BWMNGMT_0_REGS)->MAPARBEXT,
BWMNGMT_MAPARBEXT_PRI);
}
else {
status = CSL_ESYS_INVPARAMS;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2Open.c | <gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_ddr2Open.c
*
* @path: $(CSLPATH)\src\ddr2
*
* @desc File for functional layer of CSL API @a CSL_ddr2Open()
* - The @a CSL_ddr2Open() function definition & it's associated
* functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 10-Apr-2005 RM File Created.
*
* 05-Oct-2005 NG Updation done according to new register layer
*
* =============================================================================
*/
#include <csl_ddr2.h>
/** ============================================================================
* @n@b CSL_ddr2Open
*
* @b Description
* @n This function returns the handle to the DDR2 instance. This
* handle is passed to all other CSL APIs.
*
* @b Arguments
* @verbatim
pDdr2Obj Pointer to the object that holds reference to the
instance of DDR2 requested after the call
ddr2Num Instance of DDR2 to which a handle is requested
pDdr2Param Pointer to module specific parameters
pStatus pointer for returning status of the function call
@endverbatim
*
* <b> Return Value </b>
* CSL_Ddr2Handle - Valid DDR2 instance handle will be returned if status
* @li value is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n @a The DDR2 must be successfully initialized via CSL_ ddr2Init()
* before calling this function.
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status returned is
* CSL_SOK - Valid DDR2 handle is returned.
* CSL_ESYS_FAIL - The DDR2 instance is invalid.
CSL_ESYS_INVPARAMS - The Obj structure passed is invalid
* 2. DDR2 object structure is populated.
*
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_Status status;
CSL_Ddr2Obj ddr2Obj;
CSL_Ddr2Handle hDdr2;
hDdr2 = CSL_Ddr2Open(&ddr2Obj,
CSL_DDR2,
NULL,
&status
);
@endverbatim
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_ddr2Open, ".text:csl_section:ddr2");
CSL_Ddr2Handle CSL_ddr2Open (
CSL_Ddr2Obj *pDdr2Obj,
CSL_InstNum ddr2Num,
CSL_Ddr2Param *pDdr2Param,
CSL_Status *pStatus
)
{
CSL_Ddr2Handle hDdr2 = (CSL_Ddr2Handle)NULL;
CSL_Ddr2BaseAddress baseAddress;
if (pStatus == NULL) {
/* Do nothing : Module handle already initialised to NULL */
}
else if (pDdr2Obj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
*pStatus = CSL_ddr2GetBaseAddress(ddr2Num, pDdr2Param, &baseAddress);
if (*pStatus == CSL_SOK) {
pDdr2Obj->regs = baseAddress.regs;
pDdr2Obj->perNum = (CSL_InstNum)ddr2Num;
hDdr2 = (CSL_Ddr2Handle)pDdr2Obj;
}
else {
pDdr2Obj->regs = (CSL_Ddr2RegsOvly)NULL;
pDdr2Obj->perNum = (CSL_InstNum)-1;
}
}
return (hDdr2);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/FB_W2100_SCU_MEA256/irq.h | #ifndef IRQ_H_
#define IRQ_H_
#endif /*IRQ_H_*/
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback | DSP/TI-Header/csl_c6455_src/src/common/csl_memprotGetBaseAddress.c | <reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/src/common/csl_memprotGetBaseAddress.c<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* ============================================================================
*/
/** ============================================================================
* @file csl_memprotGetBaseAddress.c
*
* @path $(CSLPATH)\src\common
*
* @desc CSL Implementation of CSL_memprotGetBaseAddress
*
* Note: This function is open for re-implementing if the user wants to modify
* the base address of the peripheral object to point to a different location
* there by allow CSL initiated write/reads into peripheral MMR's go to an
* alternate location. Please refer documentation for more details.
*
* @author <NAME>.
*/
/* =============================================================================
* Revision History
* ================
* 22-sep-2005 PSK updated according to code review comments.
* 09-Aug-2006 NG Added condition to check the invalid parameter
* =============================================================================
*/
#include <soc.h>
#include <csl_memprot.h>
/** ===========================================================================
* @n@b CSL_memprotGetBaseAddress
*
* @b Description
* @n This function gets the base address of the given memprot
* instance.
*
* @b Arguments
* @verbatim
memprotNum Module instance number
pMemprotParam Module specific parameters
pBaseAddress Pointer to base address structure containing base
address details
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Successful on getting the base
* address of memprot
* @li CSL_ESYS_FAIL memprot instance is not
* available.
* @li CSL_ESYS_INVPARAMS Invalid Parameters
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure is modified.
*
* @b Example:
* @verbatim
CSL_Status status;
CSL_MemprotBaseAddress baseAddress;
...
status = CSL_memprotGetBaseAddress(CSL_MEMPROT_L2, NULL, &baseAddress);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_memprotGetBaseAddress, ".text:csl_section:memprot");
CSL_Status CSL_memprotGetBaseAddress (
CSL_InstNum memprotNum,
CSL_MemprotParam *pMemprotParam,
CSL_MemprotBaseAddress *pBaseAddress
)
{
CSL_Status status = CSL_SOK;
if (pBaseAddress == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (memprotNum) {
case CSL_MEMPROT_L2:
pBaseAddress->regs = (CSL_MemprotRegsOvly)CSL_MEMPROT_L2_REGS;
break;
case CSL_MEMPROT_L1D:
pBaseAddress->regs = (CSL_MemprotRegsOvly)CSL_MEMPROT_L1D_REGS;
break;
case CSL_MEMPROT_L1P:
pBaseAddress->regs = (CSL_MemprotRegsOvly)CSL_MEMPROT_L1P_REGS;
break;
default:
pBaseAddress->regs = (CSL_MemprotRegsOvly)NULL;
status = CSL_ESYS_FAIL;
break;
}
}
return (status);
}
|
Yunori/Fridge-menu | functions/my_strdup.c | <reponame>Yunori/Fridge-menu<gh_stars>0
#include <stdlib.h>
int my_strlen(char *str);
char *my_strdup(char *str)
{
int len;
char *copy;
len = my_strlen(str) + 1;
if (!(copy = malloc(len)))
return (NULL);
if (str < copy)
for (str += len, copy += len; len; --len)
*--copy = *--str;
else if (str != copy)
for (; len; --len)
*copy++ = *str++;
return (copy);
}
|
Yunori/Fridge-menu | controller/readline.c | <filename>controller/readline.c<gh_stars>0
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <unistd.h>
char *readLine()
{
ssize_t ret;
char *buff;
if ((buff = malloc(sizeof(*buff) * (50 + 1))) == NULL)
return (NULL);
if ((ret = read(0, buff, 50)) > 1)
{
buff[ret - 1] = '\0';
return (buff);
}
buff[0] = '\0';
return (buff);
}
|
Yunori/Fridge-menu | functions/my_strcpy.c | char *my_strcpy(char *dest, char *src)
{
char *adrr;
for (adrr = dest; *src; *dest++ = *src++);
*dest++ = '\0';
return (adrr);
}
|
Yunori/Fridge-menu | controller/random.c | #include <time.h>
#include "../game.h"
int alea()
{
int min;
int max;
int a;
int b;
min = 0;
max = 10;
a = min;
b = max+1;
return rand()%(b-a) +a;
}
|
Yunori/Fridge-menu | my.h | <filename>my.h
#ifndef MY_H_
# define MY_H_
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <time.h>
void my_putchar(char c);
int my_isneg(int n);
int my_put_nbr(int nb);
void my_swap(int *a, int *b);
void my_putstr(char *str);
int my_strlen(char *str);
int my_getnbr(char *str);
void my_aff_tab(int tab[], int len);
char *my_strcpy(char *dest, char *src);
char *my_strncpy(char *dest, char *src, int n);
int my_strcmp(char *s1, char *s2);
int my_strncmp(char *s1, char *s2, int n);
char *my_strcat(char *str1, char *str2);
char *my_strncat(char *str1, char *str2, int n);
char *my_strstr(char *str, char *to_find);
#endif
|
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