codecomplete/starcoderdata_0.003 · Datasets at Hugging Face

repo_name stringlengths 6 97	path stringlengths 3 341	text stringlengths 8 1.02M
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/tcp2/tcp2_shared_mode/src/tcp2_syst_parities.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004 , 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file tcp2_syst_parities.c * * @path $(CSLPATH)\example\c6455\tcp2\tcp2_shared_mode\src * * @desc Systematics and parity data for the TCP2 shared mode * */ #include <tistdtypes.h> Uint32 sysParData [] = { 0x00000d7f,0x0000058b, 0x00000ff6,0x000000cd, 0x00000241,0x00000285, 0x00000336,0x000005c6, 0x00000d91,0x00000d87, 0x00000136,0x00000f01, 0x000004d4,0x00000c8a, 0x0000030f,0x0000017d, 0x00000ed1,0x000003cb, 0x00000f3f,0x00000133, 0x000001f6,0x00000586, 0x00000001,0x00000278, 0x00000e78,0x00000f0d, 0x000001c8,0x00000524, 0x00000d06,0x000000fe, 0x00000bfe,0x000005b9, 0x00000001,0x00000036, 0x0000037f,0x0000007d, 0x000002f0,0x00000075, 0x00000147,0x0000007b, 0x000007fc,0x00000bfe, 0x00000c7f,0x00000b6a, 0x0000021d,0x00000f3a, 0x000000bb,0x00000bc1, 0x00000378,0x00000138, 0x000001cb,0x00000fc7, 0x00000c07,0x00000785, 0x00000a7c,0x00000075, 0x00000f84,0x00000c82, 0x00000179,0x000000bd, 0x00000f3a,0x000001f6, 0x00000e95,0x00000dc0, 0x00000d72,0x00000000, 0x0000013d,0x0000043b, 0x00000dae,0x000001b6, 0x00000675,0x00000f82, 0x00000485,0x00000fcc, 0x00000bbc,0x0000019a, 0x000006c5,0x00000ddb, 0x000000f4,0x00000f64, 0x0000023c,0x00000d05, 0x00000d38,0x0000003c, 0x00000bfe,0x00000f47, 0x00000d4b,0x0000014c, 0x00000237,0x000005dd, 0x00000d8e,0x00000efc, 0x000002d2,0x00000d84, 0x00000172,0x00000e87, 0x00000fc9,0x0000007f, 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0x00000282,0x00000fed, 0x00000476,0x0000038c, 0x00000e2b,0x00000cc0, 0x00000145,0x00000076, 0x00000340,0x00000276, 0x00000288,0x000000f4, 0x000001c4,0x00000109, 0x00000e46,0x00000039, 0x000001f1,0x000009cc, 0x0000017f,0x00000eb9, 0x00000fb0,0x00000c8b, 0x00000fb8,0x00000e7e, 0x000004bd,0x0000028f, 0x000002b2,0x000003b4, 0x00000177,0x0000027c, 0x000004fa,0x00000e42, 0x0000033e,0x000001fe, 0x00000dfd,0x0000022e, 0x00000e33,0x00000c83, 0x00000307,0x0000053d, 0x00000042,0x00000358, 0x00000115,0x000000be, 0x00000d44,0x00000402, 0x00000f39,0x0000017f, 0x000001fe,0x0000035f, 0x00000fc5,0x0000000c, 0x00000c30,0x000002d9, 0x00000ec9,0x00000bfc, 0x00000bbe,0x00000c54, 0x00000389,0x00000fff, 0x00000103,0x00000d3b, 0x00000d88,0x00000d8b, 0x00000573,0x00000dcb, 0x00000c0a,0x000002c1, 0x00000db6,0x000004c2, 0x0000032e,0x00000079, 0x00000ec0,0x00000c4b, 0x00000ef4,0x000001f5, 0x00000d07,0x0000037f, 0x000000c3,0x00000006, 0x00000d7e,0x00000ec4, 0x00000ffd,0x0000068a, 0x00000c38,0x00000f3f }; Int8 tailData [] = {0x09, 0x2a, 0x03, 0x3e, 0x2c, 0x36, 0x3c, 0x32, 0x3c, 0x3d, 0x0d, 0x15};
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/srio/csl_srioHwSetup.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* =========================================================================== * @file csl_srioHwSetup.c * * @brief File for functional layer of CSL API CSL_srioHwSetup() * * @path $(CSLPATH)\src\srio * * @desc The CSL_srioHwSetup() function definition and it's associated * functions * ============================================================================ / / ============================================================================ * Revision History * =============== * 25-Aug-2005 PSK File Created. * 15-Dec-2005 SD Updated the SERDES configuration. * 09-Aug-2006 NG Moved the GBL_EN & BLK_ENABLE before setting PER_SET_CNTL. * ============================================================================ / #include <csl_srio.h> #include <csl_srioAux.h> /* ============================================================================ * @n@b CSL_srioHwSetup * * @b Description * @n It configures the SRIO instance registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim hSrio Handle to the SRIO instance setup Pointer to hardware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The specified instance will be setup according to value passed * * @b Modifies * @n Hardware registers for the specified instance * * @b Example * @verbatim CSL_SrioHandle hSrio; CSL_SrioObj srioObj; CSL_SrioHwSetup hwSetup; CSL_Status status; CSL_SrioControlSetup periSetup; CSL_SrioBlkEn blockSetup; CSL_SrioPktFwdCntl pktFwdSetup; hwSetup.perEn = TRUE; periSetup.swMemSleepOverride = FALSE; periSetup.loopback = FALSE; . . . periSetup.prescalar = CSL_SRIO_CLK_PRESCALE_0; hwSetup.periCntlSetup = &periSetup; hwSetup.blkEn = &blockSetup; hwSetup.pktFwdCntl = &pktfwdSetup; ... hSrio = CSL_srioOpen (&srioObj, CSL_SRIO, NULL, &status); ... status = CSL_srioHwSetup(hSrio, &hwSetup); ... @endverbatim * =========================================================================== / #pragma CODE_SECTION(CSL_srioHwSetup, ".text:csl_section:srio"); CSL_Status CSL_srioHwSetup ( CSL_SrioHandle hSrio, CSL_SrioHwSetup hwSetup ) { Uint32 i; CSL_Status status = CSL_SOK; if (hSrio == NULL) { status = CSL_ESYS_BADHANDLE; } else if (hwSetup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* global enable setup / CSL_FINS(hSrio->regs->GBL_EN, SRIO_GBL_EN_EN, hwSetup->gblEn); / block enable setup / for (i = 0; i < CSL_SRIO_BLOCKS_MAX; i++) { CSL_FINS(hSrio->regs->BLK_ENABLE[i].BLK_EN, SRIO_BLK_EN_EN, hwSetup->blkEn[i]); } / sets up the PER_SET_CNTL register / hSrio->regs->PER_SET_CNTL = CSL_FMK(SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE, \ hwSetup->periCntlSetup.swMemSleepOverride) \| CSL_FMK( SRIO_PER_SET_CNTL_LOOPBACK, \ hwSetup->periCntlSetup.loopback) \| CSL_FMK(SRIO_PER_SET_CNTL_BOOT_COMPLETE, \ hwSetup->periCntlSetup.bootComplete) \| CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI2_WM, \ hwSetup->periCntlSetup.txPriority2Wm) \| CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI1_WM, \ hwSetup->periCntlSetup.txPriority1Wm) \| CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI0_WM, \ hwSetup->periCntlSetup.txPriority0Wm) \| CSL_FMK(SRIO_PER_SET_CNTL_CBA_TRANS_PRI, \ hwSetup->periCntlSetup.busTransPriority) \| CSL_FMK(SRIO_PER_SET_CNTL_1X_MODE, \ hwSetup->periCntlSetup.bufferMode) \| CSL_FMK(SRIO_PER_SET_CNTL_PRESCALER_SELECT, \ hwSetup->periCntlSetup.prescalar) \| CSL_FMKR(3, 0, hwSetup->periCntlSetup.pllEn); / the device ids setup / hSrio->regs->DEVICEID_REG1 = hwSetup->deviceId1; hSrio->regs->DEVICEID_REG2 = hwSetup->deviceId2; / hardware packet forwading registers setup / for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL, SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND, hwSetup->pktFwdCntl[i].largeUpBoundDevId); CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL, SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND, hwSetup->pktFwdCntl[i].largeLowBoundDevId); CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT, hwSetup->pktFwdCntl[i].outBoundPort); CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND, hwSetup->pktFwdCntl[i].smallUpBoundDevId); CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND, hwSetup->pktFwdCntl[i].smallLowBoundDevId); } / SERDES PLL configuration setup / for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { if (hwSetup->serDesPllCfg[i].pllEnable) { / Configure the loop bandwidth / CSL_FINS (hSrio->regs->SERDES_CFG_CNTL[i], SRIO_SERDES_CFG_CNTL_LB, hwSetup->serDesPllCfg[i].loopBandwidth); / Configure the multiplication factor / CSL_FINS (hSrio->regs->SERDES_CFG_CNTL[i], SRIO_SERDES_CFG_CNTL_MPY, hwSetup->serDesPllCfg[i].pllMplyFactor); / Enable the internal PLL/ CSL_FINST (hSrio->regs->SERDES_CFG_CNTL[i], SRIO_SERDES_CFG_CNTL_ENPLL, ENABLE); } } / SERDES RX channel enable setup / for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { if (hwSetup->serDesRxChannelCfg [i].enRx) { / Configure the bus width / CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_BUSWIDTH, hwSetup->serDesRxChannelCfg [i].busWidth); / Configure the operating rate / CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_RATE, hwSetup->serDesRxChannelCfg [i].rate); / Configure the polarity / CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_INVPAIR, hwSetup->serDesRxChannelCfg [i].invertedPolarity); / Configure the termination / CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_TERM, hwSetup->serDesRxChannelCfg [i].termination); / Configure the symbol alignment / CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_ALIGN, hwSetup->serDesRxChannelCfg [i].symAlign); / Configure the loss of signal detection / CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_LOS, hwSetup->serDesRxChannelCfg [i].los); / Configure the clock and data recovery algorithm / CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_CDR, hwSetup->serDesRxChannelCfg [i].clockDataRecovery); / Configure the adaptive equalizer / CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_EQ, hwSetup->serDesRxChannelCfg [i].equalizer); / Enable the receiver / CSL_FINST(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_ENRX, ENABLE); } } / SERDES TX channel enable setup / for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { if (hwSetup->serDesTxChannelCfg [i].enTx) { / Configure the bus width / CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_BUSWIDTH, hwSetup->serDesTxChannelCfg [i].busWidth); / Configure the operating rate / CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_RATE, hwSetup->serDesTxChannelCfg [i].rate); / Configure the polarity / CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_INVPAIR, hwSetup->serDesTxChannelCfg [i].invertedPolarity); / Configure the common mode / CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_CM, hwSetup->serDesTxChannelCfg [i].commonMode); / Configure the output swing / CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_SWING, hwSetup->serDesTxChannelCfg [i].outputSwing); / Configure the output de-emphasis / CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_DE, hwSetup->serDesTxChannelCfg [i].outputDeEmphasis); / Enable/disable the fixed phase / CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_ENFTP, hwSetup->serDesTxChannelCfg [i].enableFixedPhase); / Enable the transmitter / CSL_FINST (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_ENTX, ENABLE); } } / flow control setup / for (i = 0; i < CSL_SRIO_FLOW_CONTROL_REG_MAX; i++) { CSL_FINS(hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_TT, hwSetup->flowCntlIdLen[i]); CSL_FINS(hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_FLOW_CNTL_ID, hwSetup->flowCntlId[i]); } / the processing element address bits setup / hSrio->regs->PE_LL_CTL = hwSetup->peLlAddrCtrl; / Base device configuration / CSL_FINS(hSrio->regs->BASE_ID, SRIO_BASE_ID_BASE_DEVICEID, hwSetup->devIdSetup.smallTrBaseDevId); CSL_FINS(hSrio->regs->BASE_ID, SRIO_BASE_ID_LARGE_BASE_DEVICEID, hwSetup->devIdSetup.largeTrBaseDevId); CSL_FINS(hSrio->regs->HOST_BASE_ID_LOCK, SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID, hwSetup->devIdSetup.hostBaseDevId); / Software defined component Tag for PE (processing element) setup / hSrio->regs->COMP_TAG = hwSetup->componentTag; / Port General configuration / CSL_FINS(hSrio->regs->SP_LT_CTL, SRIO_SP_LT_CTL_TIMEOUT_VALUE, hwSetup->portGenSetup.portLinkTimeout); CSL_FINS(hSrio->regs->SP_RT_CTL, SRIO_SP_RT_CTL_TIMEOUT_VALUE, hwSetup->portGenSetup.portRespTimeout); CSL_FINS(hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_HOST, hwSetup->portGenSetup.hostEn); CSL_FINS(hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_MASTER_ENABLE, hwSetup->portGenSetup.masterEn); / port control configuration / for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_DISABLE, hwSetup->portCntlSetup[i].portDis); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_OUTPUT_PORT_ENABLE, hwSetup->portCntlSetup[i].outPortEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_INPUT_PORT_ENABLE, hwSetup->portCntlSetup[i].inPortEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_WIDTH_OVERRIDE, hwSetup->portCntlSetup[i].portWidthOverride); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_ERROR_CHECK_DISABLE, hwSetup->portCntlSetup[i].errCheckDis); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_MULTICAST_PARTICIPANT, hwSetup->portCntlSetup[i].multicastRcvEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE, hwSetup->portCntlSetup[i].stopOnPortFailEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_DROP_PACKET_ENABLE, hwSetup->portCntlSetup[i].dropPktEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_LOCKOUT, hwSetup->portCntlSetup[i].portLockoutEn); } / logical/transport layer errors setup / hSrio->regs->ERR_EN = hwSetup->lgclTransErrEn; / port error configuration / for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { hSrio->regs->PORT_ERROR[i].SP_RATE_EN = hwSetup->portErrSetup[i].portErrRateEn; CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_RATE, SRIO_SP_ERR_RATE_ERROR_RATE_BIAS, hwSetup->portErrSetup[i].prtErrRtBias); CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_RATE, SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY, hwSetup->portErrSetup[i].portErrRtRec); CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH, SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD, hwSetup->portErrSetup[i].portErrRtFldThresh); CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH, SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES, hwSetup->portErrSetup[i].portErrRtDegrdThresh); } / the discovery timer value setup / CSL_FINS(hSrio->regs->SP_IP_DISCOVERY_TIMER, SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER, hwSetup->discoveryTimer); / port write timer value setup / CSL_FINS(hSrio->regs->SP_IP_DISCOVERY_TIMER, SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER, hwSetup->pwTimer); / configuration of SP_IP_MODE register / hSrio->regs->SP_IP_MODE = hwSetup->portIpModeSet; / configuration of SP_IP_PRESCALE register / CSL_FINS(hSrio->regs->IP_PRESCAL, SRIO_IP_PRESCAL_PRESCALE, hwSetup->portIpPrescalar); / setups for silence timer and Port control independent error * register / for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { CSL_FINS(hSrio->regs->PORT_OPTION[i].SP_SILENCE_TIMER, SRIO_SP_SILENCE_TIMER_SILENCE_TIMER, hwSetup->silenceTimer[i]); hSrio->regs->PORT_OPTION[i].SP_CTL_INDEP = hwSetup->portCntlIndpEn[i]; } / Enable the peripheral */ CSL_FINS(hSrio->regs->PCR, SRIO_PCR_PEREN, hwSetup->perEn); } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_cfgAux.h	<filename>DSP/TI-Header/csl_c6455_src/inc/csl_cfgAux.h<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* =========================================================================== * @file csl_cfgAux.h * * @brief Header file for functional layer of CSL * * @path $(CSLPATH)\inc * * Description * - The defines inline function definitions * ============================================================================ / / ============================================================================ * Revision History * =============== * 14-Apr-2005 Brn File Created * ============================================================================ / #ifndef _CSL_CFGAUX_H_ #define _CSL_CFGAUX_H_ #include <csl_cfg.h> #ifdef __cplusplus extern "C" { #endif /* * Control Functions of cfg. / /* ============================================================================ * @n@b CSL_cfgClear * * @b Description * @n This function clears the CFG module. * * @b Arguments * @verbatim hCfg Handle to CFG instance @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n Clears the status and flag values * * @b Example * @verbatim CSL_cfgEnable(hCfg); @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_cfgCmdClear ( / Handle to CFG instance / CSL_CfgHandle hCfg ) { CSL_FINS(((CSL_CfgRegs )CSL_MEMPROT_CONFIG_REGS)-> MPFCR, CFG_MPFCR_MPFCLR, 1); } /** Status query functions / /* ============================================================================ * @n@b CSL_cfgGetFaultAddr * * @b Description * @n This function returns the Fault Adrress. * * @b Arguments * @verbatim hCfg Handle to CFG instance faultAddr Place holder to get the Fault Address @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_cfgGetFaultAddr(hCfg); @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_cfgGetFaultAddr ( / Handle to CFG instance / CSL_CfgHandle hCfg, / Pointer which holds the fault address / Uint32 faultAddr ) { faultAddr = ((CSL_CfgRegs)CSL_MEMPROT_CONFIG_REGS)->MPFAR; } /** ============================================================================ * @n@b CSL_cfgGetCfgStat * * @b Description * @n This function gets the CFG status information. * * @b Arguments * @verbatim hCfg Handle to CFG instance cfgStatus Placeholder to return status. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_cfgGetCfgStat(hCfg, &cfgStatus); @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_cfgGetFaultStat ( / Handle to CFG instance / CSL_CfgHandle hCfg, / Placeholder to return the status. @a void* casted / CSL_CfgFaultStatus faultStatus ) { faultStatus->errorMask = CSL_FEXTR(((CSL_CfgRegs)CSL_MEMPROT_CONFIG_REGS)->MPFSR, 8, 0); faultStatus->faultId = CSL_FEXTR(((CSL_CfgRegs)CSL_MEMPROT_CONFIG_REGS)->MPFSR, 15, 9); } #ifdef __cplusplus } #endif #endif /* CSL_CFGAUX_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_srio.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_srio.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for SRIO / #ifndef _CSLR_SRIO_H_ #define _CSLR_SRIO_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure for the Buffer Descriptors \************************************************************************/ typedef struct buffDesc { Uint32 nextDescPtr; Uint32 buffPtr; Uint32 opt1; Uint32 opt2; } CSL_SrioBuffDesc; /***********************************************************************\ Register Overlay Structure for BLK_ENABLE \************************************************************************/ typedef struct { volatile Uint32 BLK_EN; volatile Uint32 BLK_EN_STAT; } CSL_SrioBlk_enableRegs; /***********************************************************************\ Register Overlay Structure for HW_PKT_FWD \************************************************************************/ typedef struct { volatile Uint32 PF_16BIT_CNTL; volatile Uint32 PF_8BIT_CNTL; } CSL_SrioHw_pkt_fwdRegs; /***********************************************************************\ Register Overlay Structure for DOORBELL_INTR \************************************************************************/ typedef struct { volatile Uint32 DOORBELL_ICSR; volatile Uint8 RSVD0[4]; volatile Uint32 DOORBELL_ICCR; volatile Uint8 RSVD1[4]; } CSL_SrioDoorbell_intrRegs; /***********************************************************************\ Register Overlay Structure for DOORBELL_INTR_ROUTE \************************************************************************/ typedef struct { volatile Uint32 DOORBELL_ICRR; volatile Uint32 DOORBELL_ICRR2; volatile Uint8 RSVD0[8]; } CSL_SrioDoorbell_intr_routeRegs; /***********************************************************************\ Register Overlay Structure for LSU \************************************************************************/ typedef struct { volatile Uint32 LSU_REG0; volatile Uint32 LSU_REG1; volatile Uint32 LSU_REG2; volatile Uint32 LSU_REG3; volatile Uint32 LSU_REG4; volatile Uint32 LSU_REG5; volatile Uint32 LSU_REG6; volatile Uint32 LSU_FLOW_MASKS; } CSL_SrioLsuRegs; /***********************************************************************\ Register Overlay Structure for MAP \************************************************************************/ typedef struct { volatile Uint32 RXU_MAP_L; volatile Uint32 RXU_MAP_H; } CSL_SrioMapRegs; /***********************************************************************\ Register Overlay Structure for PORT \************************************************************************/ typedef struct { volatile Uint32 SP_LM_REQ; volatile Uint32 SP_LM_RESP; volatile Uint32 SP_ACKID_STAT; volatile Uint8 RSVD0[12]; volatile Uint32 SP_ERR_STAT; volatile Uint32 SP_CTL; } CSL_SrioPortRegs; /***********************************************************************\ Register Overlay Structure for PORT_ERROR \************************************************************************/ typedef struct { volatile Uint32 SP_ERR_DET; volatile Uint32 SP_RATE_EN; volatile Uint32 SP_ERR_ATTR_CAPT_DBG0; volatile Uint32 SP_ERR_CAPT_DBG[4]; volatile Uint8 RSVD0[12]; volatile Uint32 SP_ERR_RATE; volatile Uint32 SP_ERR_THRESH; volatile Uint8 RSVD1[16]; } CSL_SrioPort_errorRegs; /***********************************************************************\ Register Overlay Structure for PORT_OPTION \************************************************************************/ typedef struct { volatile Uint32 SP_RST_OPT; volatile Uint32 SP_CTL_INDEP; volatile Uint32 SP_SILENCE_TIMER; volatile Uint32 SP_MULT_EVNT_CS; volatile Uint8 RSVD0[4]; volatile Uint32 SP_CS_TX; volatile Uint8 RSVD1[232]; } CSL_SrioPort_optionRegs; /***********************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint32 PID; volatile Uint32 PCR; volatile Uint8 RSVD0[24]; volatile Uint32 PER_SET_CNTL; volatile Uint8 RSVD1[12]; volatile Uint32 GBL_EN; volatile Uint32 GBL_EN_STAT; CSL_SrioBlk_enableRegs BLK_ENABLE[9]; volatile Uint32 DEVICEID_REG1; volatile Uint32 DEVICEID_REG2; volatile Uint8 RSVD3[8]; CSL_SrioHw_pkt_fwdRegs HW_PKT_FWD[4]; volatile Uint8 RSVD4[80]; volatile Uint32 SERDES_CFGRX_CNTL[4]; volatile Uint32 SERDES_CFGTX_CNTL[4]; volatile Uint32 SERDES_CFG_CNTL[4]; volatile Uint8 RSVD5[208]; CSL_SrioDoorbell_intrRegs DOORBELL_INTR[4]; volatile Uint32 RX_CPPI_ICSR; volatile Uint8 RSVD6[4]; volatile Uint32 RX_CPPI_ICCR; volatile Uint8 RSVD7[4]; volatile Uint32 TX_CPPI_ICSR; volatile Uint8 RSVD8[4]; volatile Uint32 TX_CPPI_ICCR; volatile Uint8 RSVD9[4]; volatile Uint32 LSU_ICSR; volatile Uint8 RSVD10[4]; volatile Uint32 LSU_ICCR; volatile Uint8 RSVD11[4]; volatile Uint32 ERR_RST_EVNT_ICSR; volatile Uint8 RSVD12[4]; volatile Uint32 ERR_RST_EVNT_ICCR; volatile Uint8 RSVD13[4]; CSL_SrioDoorbell_intr_routeRegs DOORBELL_INTR_ROUTE[4]; volatile Uint32 RX_CPPI_ICRR; volatile Uint32 RX_CPPI_ICRR2; volatile Uint8 RSVD14[8]; volatile Uint32 TX_CPPI_ICRR; volatile Uint32 TX_CPPI_ICRR2; volatile Uint8 RSVD15[8]; volatile Uint32 LSU_ICRR[4]; volatile Uint32 ERR_RST_EVNT_ICRR; volatile Uint32 ERR_RST_EVNT_ICRR2; volatile Uint32 ERR_RST_EVNT_ICRR3; volatile Uint8 RSVD16[4]; volatile Uint32 INTDST_DECODE[8]; volatile Uint32 INTDST_RATE_CNTL[8]; volatile Uint8 RSVD17[192]; CSL_SrioLsuRegs LSU[4]; volatile Uint8 RSVD18[128]; volatile Uint32 QUEUE_TXDMA_HDP[16]; volatile Uint8 RSVD19[64]; volatile Uint32 QUEUE_TXDMA_CP[16]; volatile Uint8 RSVD20[64]; volatile Uint32 QUEUE_RXDMA_HDP[16]; volatile Uint8 RSVD21[64]; volatile Uint32 QUEUE_RXDMA_CP[16]; volatile Uint8 RSVD22[64]; volatile Uint32 TX_QUEUE_TEAR_DOWN; volatile Uint32 TX_CPPI_FLOW_MASKS[8]; volatile Uint8 RSVD23[28]; volatile Uint32 RX_QUEUE_TEAR_DOWN; volatile Uint32 RX_CPPI_CNTL; volatile Uint8 RSVD24[152]; volatile Uint32 TX_QUEUE_CNTL0; volatile Uint32 TX_QUEUE_CNTL1; volatile Uint32 TX_QUEUE_CNTL2; volatile Uint32 TX_QUEUE_CNTL3; volatile Uint8 RSVD25[16]; CSL_SrioMapRegs MAP[32]; volatile Uint32 FLOW_CNTL[16]; volatile Uint8 RSVD27[1728]; volatile Uint32 DEV_ID; volatile Uint32 DEV_INFO; volatile Uint32 ASBLY_ID; volatile Uint32 ASBLY_INFO; volatile Uint32 PE_FEAT; volatile Uint8 RSVD28[4]; volatile Uint32 SRC_OP; volatile Uint32 DEST_OP; volatile Uint8 RSVD29[44]; volatile Uint32 PE_LL_CTL; volatile Uint8 RSVD30[8]; volatile Uint32 LCL_CFG_HBAR; volatile Uint32 LCL_CFG_BAR; volatile Uint32 BASE_ID; volatile Uint8 RSVD31[4]; volatile Uint32 HOST_BASE_ID_LOCK; volatile Uint32 COMP_TAG; volatile Uint8 RSVD32[144]; volatile Uint32 SP_MB_HEAD; volatile Uint8 RSVD33[28]; volatile Uint32 SP_LT_CTL; volatile Uint32 SP_RT_CTL; volatile Uint8 RSVD34[20]; volatile Uint32 SP_GEN_CTL; CSL_SrioPortRegs PORT[4]; volatile Uint8 RSVD35[3648]; volatile Uint32 ERR_RPT_BH; volatile Uint8 RSVD36[4]; volatile Uint32 ERR_DET; volatile Uint32 ERR_EN; volatile Uint32 H_ADDR_CAPT; volatile Uint32 ADDR_CAPT; volatile Uint32 ID_CAPT; volatile Uint32 CTRL_CAPT; volatile Uint8 RSVD37[8]; volatile Uint32 PW_TGT_ID; volatile Uint8 RSVD38[20]; CSL_SrioPort_errorRegs PORT_ERROR[4]; volatile Uint8 RSVD39[65216]; volatile Uint32 SP_IP_DISCOVERY_TIMER; volatile Uint32 SP_IP_MODE; volatile Uint32 IP_PRESCAL; volatile Uint8 RSVD40[4]; volatile Uint32 SP_IP_PW_IN_CAPT[4]; volatile Uint8 RSVD41[8160]; CSL_SrioPort_optionRegs PORT_OPTION[4]; volatile Uint8 RSVD42[965864]; CSL_SrioBuffDesc txBuffDesc[32]; CSL_SrioBuffDesc rxBuffDesc[32]; } CSL_SrioRegs; /***********************************************************************\ Overlay structure typedef definition \*************************************************************************/ typedef volatile CSL_SrioRegs CSL_SrioRegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / PID / #define CSL_SRIO_PID_TYPE_MASK (0x00FF0000u) #define CSL_SRIO_PID_TYPE_SHIFT (0x00000010u) #define CSL_SRIO_PID_TYPE_RESETVAL (0x00000001u) #define CSL_SRIO_PID_CLASS_MASK (0x0000FF00u) #define CSL_SRIO_PID_CLASS_SHIFT (0x00000008u) #define CSL_SRIO_PID_CLASS_RESETVAL (0x0000000Au) #define CSL_SRIO_PID_REV_MASK (0x000000FFu) #define CSL_SRIO_PID_REV_SHIFT (0x00000000u) #define CSL_SRIO_PID_REV_RESETVAL (0x00000001u) #define CSL_SRIO_PID_RESETVAL (0x00010A01u) / PCR / #define CSL_SRIO_PCR_PEREN_MASK (0x00000004u) #define CSL_SRIO_PCR_PEREN_SHIFT (0x00000002u) #define CSL_SRIO_PCR_PEREN_RESETVAL (0x00000000u) /----PEREN Tokens----/ #define CSL_SRIO_PCR_PEREN_DISABLE (0x00000000u) #define CSL_SRIO_PCR_PEREN_ENABLE (0x00000001u) #define CSL_SRIO_PCR_SOFT_MASK (0x00000002u) #define CSL_SRIO_PCR_SOFT_SHIFT (0x00000001u) #define CSL_SRIO_PCR_SOFT_RESETVAL (0x00000000u) #define CSL_SRIO_PCR_FREE_MASK (0x00000001u) #define CSL_SRIO_PCR_FREE_SHIFT (0x00000000u) #define CSL_SRIO_PCR_FREE_RESETVAL (0x00000001u) #define CSL_SRIO_PCR_RESETVAL (0x00000001u) / PER_SET_CNTL / #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_MASK (0x04000000u) #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_SHIFT (0x0000001Au) #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_RESETVAL (0x00000001u) /----SW_MEM_SLEEP_OVERRIDE Tokens----/ #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_MASK (0x02000000u) #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_SHIFT (0x00000019u) #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_RESETVAL (0x00000000u) /----LOOPBACK Tokens----/ #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_NORMAL (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_LOOPBACK (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_MASK (0x01000000u) #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_SHIFT (0x00000018u) #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_RESETVAL (0x00000000u) /----BOOT_COMPLETE Tokens----/ #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_WRITE_ENABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_WRITE_DISABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI2_WM_MASK (0x001C0000u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI2_WM_SHIFT (0x00000012u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI2_WM_RESETVAL (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI1_WM_MASK (0x00038000u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI1_WM_SHIFT (0x0000000Fu) #define CSL_SRIO_PER_SET_CNTL_TX_PRI1_WM_RESETVAL (0x00000002u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI0_WM_MASK (0x00007000u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI0_WM_SHIFT (0x0000000Cu) #define CSL_SRIO_PER_SET_CNTL_TX_PRI0_WM_RESETVAL (0x00000003u) #define CSL_SRIO_PER_SET_CNTL_CBA_TRANS_PRI_MASK (0x00000E00u) #define CSL_SRIO_PER_SET_CNTL_CBA_TRANS_PRI_SHIFT (0x00000009u) #define CSL_SRIO_PER_SET_CNTL_CBA_TRANS_PRI_RESETVAL (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_1X_MODE_MASK (0x00000100u) #define CSL_SRIO_PER_SET_CNTL_1X_MODE_SHIFT (0x00000008u) #define CSL_SRIO_PER_SET_CNTL_1X_MODE_RESETVAL (0x00000000u) /----1X_MODE Tokens----/ #define CSL_SRIO_PER_SET_CNTL_1X_MODE_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_1X_MODE_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_MASK (0x000000F0u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_SHIFT (0x00000004u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_RESETVAL (0x00000000u) /----PRESCALER_SELECT Tokens----/ #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_1 (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_2 (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_3 (0x00000002u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_4 (0x00000003u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_5 (0x00000004u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_6 (0x00000005u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_7 (0x00000006u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_8 (0x00000007u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_9 (0x00000008u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_10 (0x00000009u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_11 (0x0000000Au) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_12 (0x0000000Bu) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_13 (0x0000000Cu) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_14 (0x0000000Du) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_15 (0x0000000Eu) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_16 (0x0000000Fu) #define CSL_SRIO_PER_SET_CNTL_ENPLL4_MASK (0x00000008u) #define CSL_SRIO_PER_SET_CNTL_ENPLL4_SHIFT (0x00000003u) #define CSL_SRIO_PER_SET_CNTL_ENPLL4_RESETVAL (0x00000000u) /----ENPLL4 Tokens----/ #define CSL_SRIO_PER_SET_CNTL_ENPLL4_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL4_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL3_MASK (0x00000004u) #define CSL_SRIO_PER_SET_CNTL_ENPLL3_SHIFT (0x00000002u) #define CSL_SRIO_PER_SET_CNTL_ENPLL3_RESETVAL (0x00000000u) /----ENPLL3 Tokens----/ #define CSL_SRIO_PER_SET_CNTL_ENPLL3_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL3_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL2_MASK (0x00000002u) #define CSL_SRIO_PER_SET_CNTL_ENPLL2_SHIFT (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL2_RESETVAL (0x00000000u) /----ENPLL2 Tokens----/ #define CSL_SRIO_PER_SET_CNTL_ENPLL2_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL2_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL1_MASK (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL1_SHIFT (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL1_RESETVAL (0x00000000u) /----ENPLL1 Tokens----/ #define CSL_SRIO_PER_SET_CNTL_ENPLL1_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL1_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_RESETVAL (0x04053000u) / GBL_EN / #define CSL_SRIO_GBL_EN_EN_MASK (0x00000001u) #define CSL_SRIO_GBL_EN_EN_SHIFT (0x00000000u) #define CSL_SRIO_GBL_EN_EN_RESETVAL (0x00000000u) /----EN Tokens----/ #define CSL_SRIO_GBL_EN_EN_DISABLE (0x00000000u) #define CSL_SRIO_GBL_EN_EN_ENABLE (0x00000001u) #define CSL_SRIO_GBL_EN_RESETVAL (0x00000000u) / GBL_EN_STAT / #define CSL_SRIO_GBL_EN_STAT_GBL_EN_STAT_MASK (0x00000001u) #define CSL_SRIO_GBL_EN_STAT_GBL_EN_STAT_SHIFT (0x00000000u) #define CSL_SRIO_GBL_EN_STAT_GBL_EN_STAT_RESETVAL (0x00000000u) #define CSL_SRIO_GBL_EN_STAT_RESETVAL (0x00000000u) / BLK_EN / #define CSL_SRIO_BLK_EN_EN_MASK (0x00000001u) #define CSL_SRIO_BLK_EN_EN_SHIFT (0x00000000u) #define CSL_SRIO_BLK_EN_EN_RESETVAL (0x00000000u) /----EN Tokens----/ #define CSL_SRIO_BLK_EN_EN_DISABLE (0x00000000u) #define CSL_SRIO_BLK_EN_EN_ENABLE (0x00000001u) #define CSL_SRIO_BLK_EN_RESETVAL (0x00000000u) / BLK_EN_STAT / #define CSL_SRIO_BLK_EN_STAT_EN_STAT_MASK (0x00000001u) #define CSL_SRIO_BLK_EN_STAT_EN_STAT_SHIFT (0x00000000u) #define CSL_SRIO_BLK_EN_STAT_EN_STAT_RESETVAL (0x00000000u) #define CSL_SRIO_BLK_EN_STAT_RESETVAL (0x00000000u) / DEVICEID_REG1 / #define CSL_SRIO_DEVICEID_REG1_8BNODEID_MASK (0x00FF0000u) #define CSL_SRIO_DEVICEID_REG1_8BNODEID_SHIFT (0x00000010u) #define CSL_SRIO_DEVICEID_REG1_8BNODEID_RESETVAL (0x000000FFu) #define CSL_SRIO_DEVICEID_REG1_16BNODEID_MASK (0x0000FFFFu) #define CSL_SRIO_DEVICEID_REG1_16BNODEID_SHIFT (0x00000000u) #define CSL_SRIO_DEVICEID_REG1_16BNODEID_RESETVAL (0x0000FFFFu) #define CSL_SRIO_DEVICEID_REG1_RESETVAL (0x00FFFFFFu) / DEVICEID_REG2 / #define CSL_SRIO_DEVICEID_REG2_8BNODEID_MASK (0x00FF0000u) #define CSL_SRIO_DEVICEID_REG2_8BNODEID_SHIFT (0x00000010u) #define CSL_SRIO_DEVICEID_REG2_8BNODEID_RESETVAL (0x000000FFu) #define CSL_SRIO_DEVICEID_REG2_16BNODEID_MASK (0x0000FFFFu) #define CSL_SRIO_DEVICEID_REG2_16BNODEID_SHIFT (0x00000000u) #define CSL_SRIO_DEVICEID_REG2_16BNODEID_RESETVAL (0x0000FFFFu) #define CSL_SRIO_DEVICEID_REG2_RESETVAL (0x00FFFFFFu) / PF_16BIT_CNTL / #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND_MASK (0xFFFF0000u) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND_SHIFT (0x00000010u) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND_RESETVAL (0x0000FFFFu) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND_MASK (0x0000FFFFu) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND_SHIFT (0x00000000u) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND_RESETVAL (0x0000FFFFu) #define CSL_SRIO_PF_16BIT_CNTL_RESETVAL (0xFFFFFFFFu) / PF_8BIT_CNTL / #define CSL_SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT_MASK (0x00030000u) #define CSL_SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT_SHIFT (0x00000010u) #define CSL_SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT_RESETVAL (0x00000003u) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND_MASK (0x0000FF00u) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND_SHIFT (0x00000008u) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND_RESETVAL (0x000000FFu) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND_MASK (0x000000FFu) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND_SHIFT (0x00000000u) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND_RESETVAL (0x000000FFu) #define CSL_SRIO_PF_8BIT_CNTL_RESETVAL (0x0003FFFFu) / SERDES_CFGRX_CNTL / #define CSL_SRIO_SERDES_CFGRX_CNTL_EQ_MASK (0x00780000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_EQ_SHIFT (0x00000013u) #define CSL_SRIO_SERDES_CFGRX_CNTL_EQ_RESETVAL (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_CDR_MASK (0x00070000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_CDR_SHIFT (0x00000010u) #define CSL_SRIO_SERDES_CFGRX_CNTL_CDR_RESETVAL (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_MASK (0x0000C000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_SHIFT (0x0000000Eu) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_RESETVAL (0x00000000u) /----LOS Tokens----/ #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_DISABLED (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_HIGH_THRESHOLD (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_LOW_THRESHOLD (0x00000002u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_MASK (0x00003000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_SHIFT (0x0000000Cu) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_RESETVAL (0x00000000u) /----ALIGN Tokens----/ #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_DISABLE (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_COMMA (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_JOG (0x00000002u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_MASK (0x00000700u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_SHIFT (0x00000008u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_RESETVAL (0x00000000u) /----TERM Tokens----/ #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_VDDT (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_0_8_VDDT (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_FLOATING (0x00000003u) #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_MASK (0x00000080u) #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_SHIFT (0x00000007u) #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_RESETVAL (0x00000000u) /----INVPAIR Tokens----/ #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_NORMAL (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_INVERTED (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_MASK (0x00000060u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_SHIFT (0x00000005u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_RESETVAL (0x00000000u) /----RATE Tokens----/ #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_FULL (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_HALF (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_QUARTER (0x00000002u) #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_MASK (0x0000001Cu) #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_SHIFT (0x00000002u) #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_RESETVAL (0x00000000u) /----BUSWIDTH Tokens----/ #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_10BIT (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_8BIT (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_MASK (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_SHIFT (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_RESETVAL (0x00000000u) /----ENRX Tokens----/ #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_DISABLE (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_ENABLE (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RESETVAL (0x00000000u) / SERDES_CFGTX_CNTL / #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_MASK (0x00010000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_SHIFT (0x00000010u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_RESETVAL (0x00000000u) /----ENFTP Tokens----/ #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_ARBITRARY (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_FIXED (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_MASK (0x0000F000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_SHIFT (0x0000000Cu) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_RESETVAL (0x00000000u) /----DE Tokens----/ #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_4_76 (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_9_52 (0x00000002u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_14_28 (0x00000003u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_19_04 (0x00000004u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_23_80 (0x00000005u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_28_56 (0x00000006u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_33_32 (0x00000007u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_38_08 (0x00000008u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_42_85 (0x00000009u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_47_61 (0x0000000Au) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_52_38 (0x0000000Bu) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_57_14 (0x0000000Cu) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_61_90 (0x0000000Du) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_66_66 (0x0000000Eu) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_71_42 (0x0000000Fu) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_MASK (0x00000E00u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_SHIFT (0x00000009u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_RESETVAL (0x00000000u) /----SWING Tokens----/ #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_125 (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_250 (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_500 (0x00000002u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_625 (0x00000003u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_750 (0x00000004u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_1000 (0x00000005u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_1125 (0x00000006u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_1250 (0x00000007u) #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_MASK (0x00000100u) #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_SHIFT (0x00000008u) #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_RESETVAL (0x00000000u) /----CM Tokens----/ #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_NORMAL (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_RAISED (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_MASK (0x00000080u) #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_SHIFT (0x00000007u) #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_RESETVAL (0x00000000u) /----INVPAIR Tokens----/ #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_NORMAL (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_INVERTED (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_MASK (0x00000060u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_SHIFT (0x00000005u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_RESETVAL (0x00000000u) /----RATE Tokens----/ #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_FULL (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_HALF (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_QUARTER (0x00000002u) #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_MASK (0x0000001Cu) #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_SHIFT (0x00000002u) #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_RESETVAL (0x00000000u) /----BUSWIDTH Tokens----/ #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_10BIT (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_8BIT (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_MASK (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_SHIFT (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_RESETVAL (0x00000000u) /----ENTX Tokens----/ #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_DISABLE (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_ENABLE (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RESETVAL (0x00000000u) / SERDES_CFG_CNTL / #define CSL_SRIO_SERDES_CFG_CNTL_LB_MASK (0x00000300u) #define CSL_SRIO_SERDES_CFG_CNTL_LB_SHIFT (0x00000008u) #define CSL_SRIO_SERDES_CFG_CNTL_LB_RESETVAL (0x00000000u) /----LB Tokens----/ #define CSL_SRIO_SERDES_CFG_CNTL_LB_FREQ_DEP (0x00000000u) #define CSL_SRIO_SERDES_CFG_CNTL_LB_LOW (0x00000002u) #define CSL_SRIO_SERDES_CFG_CNTL_LB_HIGH (0x00000003u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_MASK (0x0000003Eu) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_SHIFT (0x00000001u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_RESETVAL (0x00000000u) /----MPY Tokens----/ #define CSL_SRIO_SERDES_CFG_CNTL_MPY_4 (0x00000000u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_5 (0x00000001u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_6 (0x00000002u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_8 (0x00000004u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_10 (0x00000005u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_12 (0x00000006u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_12_5 (0x00000007u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_15 (0x00000008u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_20 (0x00000009u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_25 (0x0000000Au) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_50 (0x0000000Du) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_60 (0x0000000Eu) #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_MASK (0x00000001u) #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_SHIFT (0x00000000u) #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_RESETVAL (0x00000000u) /----ENPLL Tokens----/ #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_DISABLE (0x00000000u) #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_ENABLE (0x00000001u) #define CSL_SRIO_SERDES_CFG_CNTL_RESETVAL (0x00000000u) / DOORBELL_ICSR / #define CSL_SRIO_DOORBELL_ICSR_ICS15_MASK (0x00008000u) #define CSL_SRIO_DOORBELL_ICSR_ICS15_SHIFT (0x0000000Fu) #define CSL_SRIO_DOORBELL_ICSR_ICS15_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS14_MASK (0x00004000u) #define CSL_SRIO_DOORBELL_ICSR_ICS14_SHIFT (0x0000000Eu) #define CSL_SRIO_DOORBELL_ICSR_ICS14_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS13_MASK (0x00002000u) #define CSL_SRIO_DOORBELL_ICSR_ICS13_SHIFT (0x0000000Du) #define CSL_SRIO_DOORBELL_ICSR_ICS13_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS12_MASK (0x00001000u) #define CSL_SRIO_DOORBELL_ICSR_ICS12_SHIFT (0x0000000Cu) #define CSL_SRIO_DOORBELL_ICSR_ICS12_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_DOORBELL_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_DOORBELL_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_DOORBELL_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_DOORBELL_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_DOORBELL_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_DOORBELL_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_DOORBELL_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_DOORBELL_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS7_MASK (0x00000080u) #define CSL_SRIO_DOORBELL_ICSR_ICS7_SHIFT (0x00000007u) #define CSL_SRIO_DOORBELL_ICSR_ICS7_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS6_MASK (0x00000040u) #define CSL_SRIO_DOORBELL_ICSR_ICS6_SHIFT (0x00000006u) #define CSL_SRIO_DOORBELL_ICSR_ICS6_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS5_MASK (0x00000020u) #define CSL_SRIO_DOORBELL_ICSR_ICS5_SHIFT (0x00000005u) #define CSL_SRIO_DOORBELL_ICSR_ICS5_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS4_MASK (0x00000010u) #define CSL_SRIO_DOORBELL_ICSR_ICS4_SHIFT (0x00000004u) #define CSL_SRIO_DOORBELL_ICSR_ICS4_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS3_MASK (0x00000008u) #define CSL_SRIO_DOORBELL_ICSR_ICS3_SHIFT (0x00000003u) #define CSL_SRIO_DOORBELL_ICSR_ICS3_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_DOORBELL_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_DOORBELL_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_DOORBELL_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_DOORBELL_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_DOORBELL_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_RESETVAL (0x00000000u) / DOORBELL_ICCR / #define CSL_SRIO_DOORBELL_ICCR_ICC15_MASK (0x00008000u) #define CSL_SRIO_DOORBELL_ICCR_ICC15_SHIFT (0x0000000Fu) #define CSL_SRIO_DOORBELL_ICCR_ICC15_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC14_MASK (0x00004000u) #define CSL_SRIO_DOORBELL_ICCR_ICC14_SHIFT (0x0000000Eu) #define CSL_SRIO_DOORBELL_ICCR_ICC14_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC13_MASK (0x00002000u) #define CSL_SRIO_DOORBELL_ICCR_ICC13_SHIFT (0x0000000Du) #define CSL_SRIO_DOORBELL_ICCR_ICC13_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC12_MASK (0x00001000u) #define CSL_SRIO_DOORBELL_ICCR_ICC12_SHIFT (0x0000000Cu) #define CSL_SRIO_DOORBELL_ICCR_ICC12_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_DOORBELL_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_DOORBELL_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_DOORBELL_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_DOORBELL_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_DOORBELL_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_DOORBELL_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_DOORBELL_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_DOORBELL_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC7_MASK (0x00000080u) #define CSL_SRIO_DOORBELL_ICCR_ICC7_SHIFT (0x00000007u) #define CSL_SRIO_DOORBELL_ICCR_ICC7_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC6_MASK (0x00000040u) #define CSL_SRIO_DOORBELL_ICCR_ICC6_SHIFT (0x00000006u) #define CSL_SRIO_DOORBELL_ICCR_ICC6_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC5_MASK (0x00000020u) #define CSL_SRIO_DOORBELL_ICCR_ICC5_SHIFT (0x00000005u) #define CSL_SRIO_DOORBELL_ICCR_ICC5_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC4_MASK (0x00000010u) #define CSL_SRIO_DOORBELL_ICCR_ICC4_SHIFT (0x00000004u) #define CSL_SRIO_DOORBELL_ICCR_ICC4_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC3_MASK (0x00000008u) #define CSL_SRIO_DOORBELL_ICCR_ICC3_SHIFT (0x00000003u) #define CSL_SRIO_DOORBELL_ICCR_ICC3_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_DOORBELL_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_DOORBELL_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_DOORBELL_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_DOORBELL_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_DOORBELL_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_RESETVAL (0x00000000u) / RX_CPPI_ICSR / #define CSL_SRIO_RX_CPPI_ICSR_ICS15_MASK (0x00008000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS15_SHIFT (0x0000000Fu) #define CSL_SRIO_RX_CPPI_ICSR_ICS15_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS14_MASK (0x00004000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS14_SHIFT (0x0000000Eu) #define CSL_SRIO_RX_CPPI_ICSR_ICS14_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS13_MASK (0x00002000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS13_SHIFT (0x0000000Du) #define CSL_SRIO_RX_CPPI_ICSR_ICS13_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS12_MASK (0x00001000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS12_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_ICSR_ICS12_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_RX_CPPI_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_RX_CPPI_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_RX_CPPI_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_RX_CPPI_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_RX_CPPI_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_RX_CPPI_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_RX_CPPI_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS7_MASK (0x00000080u) #define CSL_SRIO_RX_CPPI_ICSR_ICS7_SHIFT (0x00000007u) #define CSL_SRIO_RX_CPPI_ICSR_ICS7_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS6_MASK (0x00000040u) #define CSL_SRIO_RX_CPPI_ICSR_ICS6_SHIFT (0x00000006u) #define CSL_SRIO_RX_CPPI_ICSR_ICS6_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS5_MASK (0x00000020u) #define CSL_SRIO_RX_CPPI_ICSR_ICS5_SHIFT (0x00000005u) #define CSL_SRIO_RX_CPPI_ICSR_ICS5_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS4_MASK (0x00000010u) #define CSL_SRIO_RX_CPPI_ICSR_ICS4_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_ICSR_ICS4_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS3_MASK (0x00000008u) #define CSL_SRIO_RX_CPPI_ICSR_ICS3_SHIFT (0x00000003u) #define CSL_SRIO_RX_CPPI_ICSR_ICS3_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_RX_CPPI_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_RX_CPPI_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_RX_CPPI_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_RX_CPPI_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_RX_CPPI_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_RESETVAL (0x00000000u) / RX_CPPI_ICCR / #define CSL_SRIO_RX_CPPI_ICCR_ICC15_MASK (0x00008000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC15_SHIFT (0x0000000Fu) #define CSL_SRIO_RX_CPPI_ICCR_ICC15_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC14_MASK (0x00004000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC14_SHIFT (0x0000000Eu) #define CSL_SRIO_RX_CPPI_ICCR_ICC14_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC13_MASK (0x00002000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC13_SHIFT (0x0000000Du) #define CSL_SRIO_RX_CPPI_ICCR_ICC13_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC12_MASK (0x00001000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC12_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_ICCR_ICC12_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_RX_CPPI_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_RX_CPPI_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_RX_CPPI_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_RX_CPPI_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_RX_CPPI_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_RX_CPPI_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_RX_CPPI_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC7_MASK (0x00000080u) #define CSL_SRIO_RX_CPPI_ICCR_ICC7_SHIFT (0x00000007u) #define CSL_SRIO_RX_CPPI_ICCR_ICC7_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC6_MASK (0x00000040u) #define CSL_SRIO_RX_CPPI_ICCR_ICC6_SHIFT (0x00000006u) #define CSL_SRIO_RX_CPPI_ICCR_ICC6_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC5_MASK (0x00000020u) #define CSL_SRIO_RX_CPPI_ICCR_ICC5_SHIFT (0x00000005u) #define CSL_SRIO_RX_CPPI_ICCR_ICC5_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC4_MASK (0x00000010u) #define CSL_SRIO_RX_CPPI_ICCR_ICC4_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_ICCR_ICC4_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC3_MASK (0x00000008u) #define CSL_SRIO_RX_CPPI_ICCR_ICC3_SHIFT (0x00000003u) #define CSL_SRIO_RX_CPPI_ICCR_ICC3_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_RX_CPPI_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_RX_CPPI_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_RX_CPPI_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_RX_CPPI_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_RX_CPPI_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_RESETVAL (0x00000000u) / TX_CPPI_ICSR / #define CSL_SRIO_TX_CPPI_ICSR_ICS15_MASK (0x00008000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS15_SHIFT (0x0000000Fu) #define CSL_SRIO_TX_CPPI_ICSR_ICS15_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS14_MASK (0x00004000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS14_SHIFT (0x0000000Eu) #define CSL_SRIO_TX_CPPI_ICSR_ICS14_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS13_MASK (0x00002000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS13_SHIFT (0x0000000Du) #define CSL_SRIO_TX_CPPI_ICSR_ICS13_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS12_MASK (0x00001000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS12_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_ICSR_ICS12_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_TX_CPPI_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_TX_CPPI_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_TX_CPPI_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_TX_CPPI_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_TX_CPPI_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_TX_CPPI_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_TX_CPPI_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS7_MASK (0x00000080u) #define CSL_SRIO_TX_CPPI_ICSR_ICS7_SHIFT (0x00000007u) #define CSL_SRIO_TX_CPPI_ICSR_ICS7_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS6_MASK (0x00000040u) #define CSL_SRIO_TX_CPPI_ICSR_ICS6_SHIFT (0x00000006u) #define CSL_SRIO_TX_CPPI_ICSR_ICS6_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS5_MASK (0x00000020u) #define CSL_SRIO_TX_CPPI_ICSR_ICS5_SHIFT (0x00000005u) #define CSL_SRIO_TX_CPPI_ICSR_ICS5_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS4_MASK (0x00000010u) #define CSL_SRIO_TX_CPPI_ICSR_ICS4_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_ICSR_ICS4_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS3_MASK (0x00000008u) #define CSL_SRIO_TX_CPPI_ICSR_ICS3_SHIFT (0x00000003u) #define CSL_SRIO_TX_CPPI_ICSR_ICS3_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_TX_CPPI_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_TX_CPPI_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_TX_CPPI_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_TX_CPPI_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_TX_CPPI_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_RESETVAL (0x00000000u) / TX_CPPI_ICCR / #define CSL_SRIO_TX_CPPI_ICCR_ICC15_MASK (0x00008000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC15_SHIFT (0x0000000Fu) #define CSL_SRIO_TX_CPPI_ICCR_ICC15_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC14_MASK (0x00004000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC14_SHIFT (0x0000000Eu) #define CSL_SRIO_TX_CPPI_ICCR_ICC14_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC13_MASK (0x00002000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC13_SHIFT (0x0000000Du) #define CSL_SRIO_TX_CPPI_ICCR_ICC13_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC12_MASK (0x00001000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC12_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_ICCR_ICC12_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_TX_CPPI_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_TX_CPPI_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_TX_CPPI_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_TX_CPPI_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_TX_CPPI_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_TX_CPPI_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_TX_CPPI_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC7_MASK (0x00000080u) #define CSL_SRIO_TX_CPPI_ICCR_ICC7_SHIFT (0x00000007u) #define CSL_SRIO_TX_CPPI_ICCR_ICC7_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC6_MASK (0x00000040u) #define CSL_SRIO_TX_CPPI_ICCR_ICC6_SHIFT (0x00000006u) #define CSL_SRIO_TX_CPPI_ICCR_ICC6_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC5_MASK (0x00000020u) #define CSL_SRIO_TX_CPPI_ICCR_ICC5_SHIFT (0x00000005u) #define CSL_SRIO_TX_CPPI_ICCR_ICC5_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC4_MASK (0x00000010u) #define CSL_SRIO_TX_CPPI_ICCR_ICC4_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_ICCR_ICC4_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC3_MASK (0x00000008u) #define CSL_SRIO_TX_CPPI_ICCR_ICC3_SHIFT (0x00000003u) #define CSL_SRIO_TX_CPPI_ICCR_ICC3_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_TX_CPPI_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_TX_CPPI_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_TX_CPPI_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_TX_CPPI_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_TX_CPPI_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_RESETVAL (0x00000000u) / LSU_ICSR / #define CSL_SRIO_LSU_ICSR_ICS31_MASK (0x80000000u) #define CSL_SRIO_LSU_ICSR_ICS31_SHIFT (0x0000001Fu) #define CSL_SRIO_LSU_ICSR_ICS31_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS30_MASK (0x40000000u) #define CSL_SRIO_LSU_ICSR_ICS30_SHIFT (0x0000001Eu) #define CSL_SRIO_LSU_ICSR_ICS30_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS29_MASK (0x20000000u) #define CSL_SRIO_LSU_ICSR_ICS29_SHIFT (0x0000001Du) #define CSL_SRIO_LSU_ICSR_ICS29_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS28_MASK (0x10000000u) #define CSL_SRIO_LSU_ICSR_ICS28_SHIFT (0x0000001Cu) #define CSL_SRIO_LSU_ICSR_ICS28_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS27_MASK (0x08000000u) #define CSL_SRIO_LSU_ICSR_ICS27_SHIFT (0x0000001Bu) #define CSL_SRIO_LSU_ICSR_ICS27_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS26_MASK (0x04000000u) #define CSL_SRIO_LSU_ICSR_ICS26_SHIFT (0x0000001Au) #define CSL_SRIO_LSU_ICSR_ICS26_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS25_MASK (0x02000000u) #define CSL_SRIO_LSU_ICSR_ICS25_SHIFT (0x00000019u) #define CSL_SRIO_LSU_ICSR_ICS25_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS24_MASK (0x01000000u) #define CSL_SRIO_LSU_ICSR_ICS24_SHIFT (0x00000018u) #define CSL_SRIO_LSU_ICSR_ICS24_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS23_MASK (0x00800000u) #define CSL_SRIO_LSU_ICSR_ICS23_SHIFT (0x00000017u) #define CSL_SRIO_LSU_ICSR_ICS23_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS22_MASK (0x00400000u) #define CSL_SRIO_LSU_ICSR_ICS22_SHIFT (0x00000016u) #define CSL_SRIO_LSU_ICSR_ICS22_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS21_MASK (0x00200000u) #define CSL_SRIO_LSU_ICSR_ICS21_SHIFT (0x00000015u) #define CSL_SRIO_LSU_ICSR_ICS21_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS20_MASK (0x00100000u) #define CSL_SRIO_LSU_ICSR_ICS20_SHIFT (0x00000014u) #define CSL_SRIO_LSU_ICSR_ICS20_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS19_MASK (0x00080000u) #define CSL_SRIO_LSU_ICSR_ICS19_SHIFT (0x00000013u) #define CSL_SRIO_LSU_ICSR_ICS19_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS18_MASK (0x00040000u) #define CSL_SRIO_LSU_ICSR_ICS18_SHIFT (0x00000012u) #define CSL_SRIO_LSU_ICSR_ICS18_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS17_MASK (0x00020000u) #define CSL_SRIO_LSU_ICSR_ICS17_SHIFT (0x00000011u) #define CSL_SRIO_LSU_ICSR_ICS17_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS16_MASK (0x00010000u) #define CSL_SRIO_LSU_ICSR_ICS16_SHIFT (0x00000010u) #define CSL_SRIO_LSU_ICSR_ICS16_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS15_MASK (0x00008000u) #define CSL_SRIO_LSU_ICSR_ICS15_SHIFT (0x0000000Fu) #define CSL_SRIO_LSU_ICSR_ICS15_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS14_MASK (0x00004000u) #define CSL_SRIO_LSU_ICSR_ICS14_SHIFT (0x0000000Eu) #define CSL_SRIO_LSU_ICSR_ICS14_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS13_MASK (0x00002000u) #define CSL_SRIO_LSU_ICSR_ICS13_SHIFT (0x0000000Du) #define CSL_SRIO_LSU_ICSR_ICS13_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS12_MASK (0x00001000u) #define CSL_SRIO_LSU_ICSR_ICS12_SHIFT (0x0000000Cu) #define CSL_SRIO_LSU_ICSR_ICS12_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_LSU_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_LSU_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_LSU_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_LSU_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_LSU_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_LSU_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_LSU_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_LSU_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS7_MASK (0x00000080u) #define CSL_SRIO_LSU_ICSR_ICS7_SHIFT (0x00000007u) #define CSL_SRIO_LSU_ICSR_ICS7_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS6_MASK (0x00000040u) #define CSL_SRIO_LSU_ICSR_ICS6_SHIFT (0x00000006u) #define CSL_SRIO_LSU_ICSR_ICS6_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS5_MASK (0x00000020u) #define CSL_SRIO_LSU_ICSR_ICS5_SHIFT (0x00000005u) #define CSL_SRIO_LSU_ICSR_ICS5_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS4_MASK (0x00000010u) #define CSL_SRIO_LSU_ICSR_ICS4_SHIFT (0x00000004u) #define CSL_SRIO_LSU_ICSR_ICS4_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS3_MASK (0x00000008u) #define CSL_SRIO_LSU_ICSR_ICS3_SHIFT (0x00000003u) #define CSL_SRIO_LSU_ICSR_ICS3_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_LSU_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_LSU_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_LSU_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_LSU_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_LSU_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_RESETVAL (0x00000000u) / LSU_ICCR / #define CSL_SRIO_LSU_ICCR_ICC31_MASK (0x80000000u) #define CSL_SRIO_LSU_ICCR_ICC31_SHIFT (0x0000001Fu) #define CSL_SRIO_LSU_ICCR_ICC31_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC30_MASK (0x40000000u) #define CSL_SRIO_LSU_ICCR_ICC30_SHIFT (0x0000001Eu) #define CSL_SRIO_LSU_ICCR_ICC30_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC29_MASK (0x20000000u) #define CSL_SRIO_LSU_ICCR_ICC29_SHIFT (0x0000001Du) #define CSL_SRIO_LSU_ICCR_ICC29_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC28_MASK (0x10000000u) #define CSL_SRIO_LSU_ICCR_ICC28_SHIFT (0x0000001Cu) #define CSL_SRIO_LSU_ICCR_ICC28_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC27_MASK (0x08000000u) #define CSL_SRIO_LSU_ICCR_ICC27_SHIFT (0x0000001Bu) #define CSL_SRIO_LSU_ICCR_ICC27_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC26_MASK (0x04000000u) #define CSL_SRIO_LSU_ICCR_ICC26_SHIFT (0x0000001Au) #define CSL_SRIO_LSU_ICCR_ICC26_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC25_MASK (0x02000000u) #define CSL_SRIO_LSU_ICCR_ICC25_SHIFT (0x00000019u) #define CSL_SRIO_LSU_ICCR_ICC25_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC24_MASK (0x01000000u) #define CSL_SRIO_LSU_ICCR_ICC24_SHIFT (0x00000018u) #define CSL_SRIO_LSU_ICCR_ICC24_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC23_MASK (0x00800000u) #define CSL_SRIO_LSU_ICCR_ICC23_SHIFT (0x00000017u) #define CSL_SRIO_LSU_ICCR_ICC23_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC22_MASK (0x00400000u) #define CSL_SRIO_LSU_ICCR_ICC22_SHIFT (0x00000016u) #define CSL_SRIO_LSU_ICCR_ICC22_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC21_MASK (0x00200000u) #define CSL_SRIO_LSU_ICCR_ICC21_SHIFT (0x00000015u) #define CSL_SRIO_LSU_ICCR_ICC21_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC20_MASK (0x00100000u) #define CSL_SRIO_LSU_ICCR_ICC20_SHIFT (0x00000014u) #define CSL_SRIO_LSU_ICCR_ICC20_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC19_MASK (0x00080000u) #define CSL_SRIO_LSU_ICCR_ICC19_SHIFT (0x00000013u) #define CSL_SRIO_LSU_ICCR_ICC19_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC18_MASK (0x00040000u) #define CSL_SRIO_LSU_ICCR_ICC18_SHIFT (0x00000012u) #define CSL_SRIO_LSU_ICCR_ICC18_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC17_MASK (0x00020000u) #define CSL_SRIO_LSU_ICCR_ICC17_SHIFT (0x00000011u) #define CSL_SRIO_LSU_ICCR_ICC17_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC16_MASK (0x00010000u) #define CSL_SRIO_LSU_ICCR_ICC16_SHIFT (0x00000010u) #define CSL_SRIO_LSU_ICCR_ICC16_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC15_MASK (0x00008000u) #define CSL_SRIO_LSU_ICCR_ICC15_SHIFT (0x0000000Fu) #define CSL_SRIO_LSU_ICCR_ICC15_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC14_MASK (0x00004000u) #define CSL_SRIO_LSU_ICCR_ICC14_SHIFT (0x0000000Eu) #define CSL_SRIO_LSU_ICCR_ICC14_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC13_MASK (0x00002000u) #define CSL_SRIO_LSU_ICCR_ICC13_SHIFT (0x0000000Du) #define CSL_SRIO_LSU_ICCR_ICC13_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC12_MASK (0x00001000u) #define CSL_SRIO_LSU_ICCR_ICC12_SHIFT (0x0000000Cu) #define CSL_SRIO_LSU_ICCR_ICC12_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_LSU_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_LSU_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_LSU_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_LSU_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_LSU_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_LSU_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_LSU_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_LSU_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC7_MASK (0x00000080u) #define CSL_SRIO_LSU_ICCR_ICC7_SHIFT (0x00000007u) #define CSL_SRIO_LSU_ICCR_ICC7_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC6_MASK (0x00000040u) #define CSL_SRIO_LSU_ICCR_ICC6_SHIFT (0x00000006u) #define CSL_SRIO_LSU_ICCR_ICC6_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC5_MASK (0x00000020u) #define CSL_SRIO_LSU_ICCR_ICC5_SHIFT (0x00000005u) #define CSL_SRIO_LSU_ICCR_ICC5_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC4_MASK (0x00000010u) #define CSL_SRIO_LSU_ICCR_ICC4_SHIFT (0x00000004u) #define CSL_SRIO_LSU_ICCR_ICC4_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC3_MASK (0x00000008u) #define CSL_SRIO_LSU_ICCR_ICC3_SHIFT (0x00000003u) #define CSL_SRIO_LSU_ICCR_ICC3_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_LSU_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_LSU_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_LSU_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_LSU_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_LSU_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_RESETVAL (0x00000000u) / ERR_RST_EVNT_ICSR / #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS16_MASK (0x00010000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS16_SHIFT (0x00000010u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS16_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_RESETVAL (0x00000000u) / ERR_RST_EVNT_ICCR / #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC16_MASK (0x00010000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC16_SHIFT (0x00000010u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC16_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_RESETVAL (0x00000000u) / DOORBELL_ICRR / #define CSL_SRIO_DOORBELL_ICRR_ICR7_MASK (0xF0000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_DOORBELL_ICRR_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR6_MASK (0x0F000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_DOORBELL_ICRR_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR5_MASK (0x00F00000u) #define CSL_SRIO_DOORBELL_ICRR_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_DOORBELL_ICRR_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR4_MASK (0x000F0000u) #define CSL_SRIO_DOORBELL_ICRR_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_DOORBELL_ICRR_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR3_MASK (0x0000F000u) #define CSL_SRIO_DOORBELL_ICRR_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_DOORBELL_ICRR_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_DOORBELL_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_DOORBELL_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_DOORBELL_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_DOORBELL_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_DOORBELL_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_RESETVAL (0x00000000u) / DOORBELL_ICRR2 / #define CSL_SRIO_DOORBELL_ICRR2_ICR7_MASK (0xF0000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_DOORBELL_ICRR2_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR6_MASK (0x0F000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_DOORBELL_ICRR2_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR5_MASK (0x00F00000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_DOORBELL_ICRR2_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR4_MASK (0x000F0000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_DOORBELL_ICRR2_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR3_MASK (0x0000F000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_DOORBELL_ICRR2_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR2_MASK (0x00000F00u) #define CSL_SRIO_DOORBELL_ICRR2_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_DOORBELL_ICRR2_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR1_MASK (0x000000F0u) #define CSL_SRIO_DOORBELL_ICRR2_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_DOORBELL_ICRR2_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_DOORBELL_ICRR2_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_RESETVAL (0x00000000u) / RX_CPPI_ICRR / #define CSL_SRIO_RX_CPPI_ICRR_ICR7_MASK (0xF0000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_RX_CPPI_ICRR_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR6_MASK (0x0F000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_RX_CPPI_ICRR_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR5_MASK (0x00F00000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_RX_CPPI_ICRR_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR4_MASK (0x000F0000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_RX_CPPI_ICRR_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR3_MASK (0x0000F000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_ICRR_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_RX_CPPI_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_RX_CPPI_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_RX_CPPI_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_RESETVAL (0x00000000u) / RX_CPPI_ICRR2 / #define CSL_SRIO_RX_CPPI_ICRR2_ICR7_MASK (0xF0000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_RX_CPPI_ICRR2_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR6_MASK (0x0F000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR5_MASK (0x00F00000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR4_MASK (0x000F0000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR3_MASK (0x0000F000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_ICRR2_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR2_MASK (0x00000F00u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR1_MASK (0x000000F0u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_RX_CPPI_ICRR2_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_RESETVAL (0x00000000u) / TX_CPPI_ICRR / #define CSL_SRIO_TX_CPPI_ICRR_ICR7_MASK (0xF0000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_CPPI_ICRR_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR6_MASK (0x0F000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_TX_CPPI_ICRR_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR5_MASK (0x00F00000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_TX_CPPI_ICRR_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR4_MASK (0x000F0000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_TX_CPPI_ICRR_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR3_MASK (0x0000F000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_ICRR_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_TX_CPPI_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_TX_CPPI_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_TX_CPPI_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_RESETVAL (0x00000000u) / TX_CPPI_ICRR2 / #define CSL_SRIO_TX_CPPI_ICRR2_ICR7_MASK (0xF0000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_CPPI_ICRR2_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR6_MASK (0x0F000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR5_MASK (0x00F00000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR4_MASK (0x000F0000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR3_MASK (0x0000F000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_ICRR2_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR2_MASK (0x00000F00u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR1_MASK (0x000000F0u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_TX_CPPI_ICRR2_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_RESETVAL (0x00000000u) / LSU_ICRR / #define CSL_SRIO_LSU_ICRR_ICR7_MASK (0xF0000000u) #define CSL_SRIO_LSU_ICRR_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_LSU_ICRR_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR6_MASK (0x0F000000u) #define CSL_SRIO_LSU_ICRR_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_LSU_ICRR_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR5_MASK (0x00F00000u) #define CSL_SRIO_LSU_ICRR_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_LSU_ICRR_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR4_MASK (0x000F0000u) #define CSL_SRIO_LSU_ICRR_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_LSU_ICRR_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR3_MASK (0x0000F000u) #define CSL_SRIO_LSU_ICRR_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_LSU_ICRR_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_LSU_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_LSU_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_LSU_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_LSU_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_LSU_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_RESETVAL (0x00000000u) / ERR_RST_EVNT_ICRR / #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_RESETVAL (0x00000000u) / ERR_RST_EVNT_ICRR2 / #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR11_MASK (0x0000F000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR11_SHIFT (0x0000000Cu) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR11_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR10_MASK (0x00000F00u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR10_SHIFT (0x00000008u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR10_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR9_MASK (0x000000F0u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR9_SHIFT (0x00000004u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR9_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR8_MASK (0x0000000Fu) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR8_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR8_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_RESETVAL (0x00000000u) / ERR_RST_EVNT_ICRR3 / #define CSL_SRIO_ERR_RST_EVNT_ICRR3_ICR16_MASK (0x0000000Fu) #define CSL_SRIO_ERR_RST_EVNT_ICRR3_ICR16_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR3_ICR16_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR3_RESETVAL (0x00000000u) / INTDST_DECODE / #define CSL_SRIO_INTDST_DECODE_ISDR31_MASK (0x80000000u) #define CSL_SRIO_INTDST_DECODE_ISDR31_SHIFT (0x0000001Fu) #define CSL_SRIO_INTDST_DECODE_ISDR31_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR30_MASK (0x40000000u) #define CSL_SRIO_INTDST_DECODE_ISDR30_SHIFT (0x0000001Eu) #define CSL_SRIO_INTDST_DECODE_ISDR30_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR29_MASK (0x20000000u) #define CSL_SRIO_INTDST_DECODE_ISDR29_SHIFT (0x0000001Du) #define CSL_SRIO_INTDST_DECODE_ISDR29_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR28_MASK (0x10000000u) #define CSL_SRIO_INTDST_DECODE_ISDR28_SHIFT (0x0000001Cu) #define CSL_SRIO_INTDST_DECODE_ISDR28_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR27_MASK (0x08000000u) #define CSL_SRIO_INTDST_DECODE_ISDR27_SHIFT (0x0000001Bu) #define CSL_SRIO_INTDST_DECODE_ISDR27_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR26_MASK (0x04000000u) #define CSL_SRIO_INTDST_DECODE_ISDR26_SHIFT (0x0000001Au) #define CSL_SRIO_INTDST_DECODE_ISDR26_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR25_MASK (0x02000000u) #define CSL_SRIO_INTDST_DECODE_ISDR25_SHIFT (0x00000019u) #define CSL_SRIO_INTDST_DECODE_ISDR25_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR24_MASK (0x01000000u) #define CSL_SRIO_INTDST_DECODE_ISDR24_SHIFT (0x00000018u) #define CSL_SRIO_INTDST_DECODE_ISDR24_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR23_MASK (0x00800000u) #define CSL_SRIO_INTDST_DECODE_ISDR23_SHIFT (0x00000017u) #define CSL_SRIO_INTDST_DECODE_ISDR23_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR22_MASK (0x00400000u) #define CSL_SRIO_INTDST_DECODE_ISDR22_SHIFT (0x00000016u) #define CSL_SRIO_INTDST_DECODE_ISDR22_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR21_MASK (0x00200000u) #define CSL_SRIO_INTDST_DECODE_ISDR21_SHIFT (0x00000015u) #define CSL_SRIO_INTDST_DECODE_ISDR21_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR20_MASK (0x00100000u) #define CSL_SRIO_INTDST_DECODE_ISDR20_SHIFT (0x00000014u) #define CSL_SRIO_INTDST_DECODE_ISDR20_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR19_MASK (0x00080000u) #define CSL_SRIO_INTDST_DECODE_ISDR19_SHIFT (0x00000013u) #define CSL_SRIO_INTDST_DECODE_ISDR19_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR18_MASK (0x00040000u) #define CSL_SRIO_INTDST_DECODE_ISDR18_SHIFT (0x00000012u) #define CSL_SRIO_INTDST_DECODE_ISDR18_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR17_MASK (0x00020000u) #define CSL_SRIO_INTDST_DECODE_ISDR17_SHIFT (0x00000011u) #define CSL_SRIO_INTDST_DECODE_ISDR17_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR16_MASK (0x00010000u) #define CSL_SRIO_INTDST_DECODE_ISDR16_SHIFT (0x00000010u) #define CSL_SRIO_INTDST_DECODE_ISDR16_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR15_MASK (0x00008000u) #define CSL_SRIO_INTDST_DECODE_ISDR15_SHIFT (0x0000000Fu) #define CSL_SRIO_INTDST_DECODE_ISDR15_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR14_MASK (0x00004000u) #define CSL_SRIO_INTDST_DECODE_ISDR14_SHIFT (0x0000000Eu) #define CSL_SRIO_INTDST_DECODE_ISDR14_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR13_MASK (0x00002000u) #define CSL_SRIO_INTDST_DECODE_ISDR13_SHIFT (0x0000000Du) #define CSL_SRIO_INTDST_DECODE_ISDR13_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR12_MASK (0x00001000u) #define CSL_SRIO_INTDST_DECODE_ISDR12_SHIFT (0x0000000Cu) #define CSL_SRIO_INTDST_DECODE_ISDR12_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR11_MASK (0x00000800u) #define CSL_SRIO_INTDST_DECODE_ISDR11_SHIFT (0x0000000Bu) #define CSL_SRIO_INTDST_DECODE_ISDR11_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR10_MASK (0x00000400u) #define CSL_SRIO_INTDST_DECODE_ISDR10_SHIFT (0x0000000Au) #define CSL_SRIO_INTDST_DECODE_ISDR10_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR9_MASK (0x00000200u) #define CSL_SRIO_INTDST_DECODE_ISDR9_SHIFT (0x00000009u) #define CSL_SRIO_INTDST_DECODE_ISDR9_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR8_MASK (0x00000100u) #define CSL_SRIO_INTDST_DECODE_ISDR8_SHIFT (0x00000008u) #define CSL_SRIO_INTDST_DECODE_ISDR8_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR7_MASK (0x00000080u) #define CSL_SRIO_INTDST_DECODE_ISDR7_SHIFT (0x00000007u) #define CSL_SRIO_INTDST_DECODE_ISDR7_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR6_MASK (0x00000040u) #define CSL_SRIO_INTDST_DECODE_ISDR6_SHIFT (0x00000006u) #define CSL_SRIO_INTDST_DECODE_ISDR6_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR5_MASK (0x00000020u) #define CSL_SRIO_INTDST_DECODE_ISDR5_SHIFT (0x00000005u) #define CSL_SRIO_INTDST_DECODE_ISDR5_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR4_MASK (0x00000010u) #define CSL_SRIO_INTDST_DECODE_ISDR4_SHIFT (0x00000004u) #define CSL_SRIO_INTDST_DECODE_ISDR4_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR3_MASK (0x00000008u) #define CSL_SRIO_INTDST_DECODE_ISDR3_SHIFT (0x00000003u) #define CSL_SRIO_INTDST_DECODE_ISDR3_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR2_MASK (0x00000004u) #define CSL_SRIO_INTDST_DECODE_ISDR2_SHIFT (0x00000002u) #define CSL_SRIO_INTDST_DECODE_ISDR2_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR1_MASK (0x00000002u) #define CSL_SRIO_INTDST_DECODE_ISDR1_SHIFT (0x00000001u) #define CSL_SRIO_INTDST_DECODE_ISDR1_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR0_MASK (0x00000001u) #define CSL_SRIO_INTDST_DECODE_ISDR0_SHIFT (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR0_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_RESETVAL (0x00000000u) / INTDST_RATE_CNTL / #define CSL_SRIO_INTDST_RATE_CNTL_COUNT_DOWN_VALUE_MASK (0xFFFFFFFFu) #define CSL_SRIO_INTDST_RATE_CNTL_COUNT_DOWN_VALUE_SHIFT (0x00000000u) #define CSL_SRIO_INTDST_RATE_CNTL_COUNT_DOWN_VALUE_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_RATE_CNTL_RESETVAL (0x00000000u) / LSU_REG0 / #define CSL_SRIO_LSU_REG0_ADDRESS_MSB_MASK (0xFFFFFFFFu) #define CSL_SRIO_LSU_REG0_ADDRESS_MSB_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG0_ADDRESS_MSB_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG0_RESETVAL (0x00000000u) / LSU_REG1 / #define CSL_SRIO_LSU_REG1_ADDRESS_LSB_CONFIG_OFFSET_MASK (0xFFFFFFFFu) #define CSL_SRIO_LSU_REG1_ADDRESS_LSB_CONFIG_OFFSET_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG1_ADDRESS_LSB_CONFIG_OFFSET_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG1_RESETVAL (0x00000000u) / LSU_REG2 / #define CSL_SRIO_LSU_REG2_DSP_ADDRESS_MASK (0xFFFFFFFFu) #define CSL_SRIO_LSU_REG2_DSP_ADDRESS_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG2_DSP_ADDRESS_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG2_RESETVAL (0x00000000u) / LSU_REG3 / #define CSL_SRIO_LSU_REG3_BYTE_COUNT_MASK (0x00000FFFu) #define CSL_SRIO_LSU_REG3_BYTE_COUNT_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG3_BYTE_COUNT_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG3_RESETVAL (0x00000000u) / LSU_REG4 / #define CSL_SRIO_LSU_REG4_OUTPORTID_MASK (0xC0000000u) #define CSL_SRIO_LSU_REG4_OUTPORTID_SHIFT (0x0000001Eu) #define CSL_SRIO_LSU_REG4_OUTPORTID_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG4_PRIORITY_MASK (0x30000000u) #define CSL_SRIO_LSU_REG4_PRIORITY_SHIFT (0x0000001Cu) #define CSL_SRIO_LSU_REG4_PRIORITY_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG4_XAMBS_MASK (0x0C000000u) #define CSL_SRIO_LSU_REG4_XAMBS_SHIFT (0x0000001Au) #define CSL_SRIO_LSU_REG4_XAMBS_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG4_ID_SIZE_MASK (0x03000000u) #define CSL_SRIO_LSU_REG4_ID_SIZE_SHIFT (0x00000018u) #define CSL_SRIO_LSU_REG4_ID_SIZE_RESETVAL (0x00000000u) /----ID_SIZE Tokens----/ #define CSL_SRIO_LSU_REG4_ID_SIZE_8BIT (0x00000000u) #define CSL_SRIO_LSU_REG4_ID_SIZE_16BIT (0x00000001u) #define CSL_SRIO_LSU_REG4_DESTID_MASK (0x00FFFF00u) #define CSL_SRIO_LSU_REG4_DESTID_SHIFT (0x00000008u) #define CSL_SRIO_LSU_REG4_DESTID_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_MASK (0x00000001u) #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_RESETVAL (0x00000000u) /----INTERRUPT_REQ Tokens----/ #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_DISABLE (0x00000000u) #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_ENABLE (0x00000001u) #define CSL_SRIO_LSU_REG4_RESETVAL (0x00000000u) / LSU_REG5 / #define CSL_SRIO_LSU_REG5_DRBLL_INFO_MASK (0xFFFF0000u) #define CSL_SRIO_LSU_REG5_DRBLL_INFO_SHIFT (0x00000010u) #define CSL_SRIO_LSU_REG5_DRBLL_INFO_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG5_HOP_COUNT_MASK (0x0000FF00u) #define CSL_SRIO_LSU_REG5_HOP_COUNT_SHIFT (0x00000008u) #define CSL_SRIO_LSU_REG5_HOP_COUNT_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG5_PACKET_TYPE_MASK (0x000000FFu) #define CSL_SRIO_LSU_REG5_PACKET_TYPE_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG5_PACKET_TYPE_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG5_RESETVAL (0x00000000u) / LSU_REG6 / #define CSL_SRIO_LSU_REG6_COMPLETION_CODE_MASK (0x0000001Eu) #define CSL_SRIO_LSU_REG6_COMPLETION_CODE_SHIFT (0x00000001u) #define CSL_SRIO_LSU_REG6_COMPLETION_CODE_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG6_BSY_MASK (0x00000001u) #define CSL_SRIO_LSU_REG6_BSY_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG6_BSY_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG6_RESETVAL (0x00000000u) / LSU_FLOW_MASKS / #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK15_MASK (0x00008000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK15_SHIFT (0x0000000Fu) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK15_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK14_MASK (0x00004000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK14_SHIFT (0x0000000Eu) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK14_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK13_MASK (0x00002000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK13_SHIFT (0x0000000Du) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK13_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK12_MASK (0x00001000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK12_SHIFT (0x0000000Cu) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK12_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK11_MASK (0x00000800u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK11_SHIFT (0x0000000Bu) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK11_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK10_MASK (0x00000400u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK10_SHIFT (0x0000000Au) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK10_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK9_MASK (0x00000200u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK9_SHIFT (0x00000009u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK9_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK8_MASK (0x00000100u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK8_SHIFT (0x00000008u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK8_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK7_MASK (0x00000080u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK7_SHIFT (0x00000007u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK7_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK6_MASK (0x00000040u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK6_SHIFT (0x00000006u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK6_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK5_MASK (0x00000020u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK5_SHIFT (0x00000005u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK5_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK4_MASK (0x00000010u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK4_SHIFT (0x00000004u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK4_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK3_MASK (0x00000008u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK3_SHIFT (0x00000003u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK3_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK2_MASK (0x00000004u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK2_SHIFT (0x00000002u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK2_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK1_MASK (0x00000002u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK1_SHIFT (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK1_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK0_MASK (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK0_SHIFT (0x00000000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK0_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_RESETVAL (0x0000FFFFu) / QUEUE_TXDMA_HDP / #define CSL_SRIO_QUEUE_TXDMA_HDP_TX_HDP_MASK (0xFFFFFFFFu) #define CSL_SRIO_QUEUE_TXDMA_HDP_TX_HDP_SHIFT (0x00000000u) #define CSL_SRIO_QUEUE_TXDMA_HDP_TX_HDP_RESETVAL (0x00000000u) #define CSL_SRIO_QUEUE_TXDMA_HDP_RESETVAL (0x00000000u) / QUEUE_TXDMA_CP / #define CSL_SRIO_QUEUE_TXDMA_CP_TX_CP_MASK (0xFFFFFFFFu) #define CSL_SRIO_QUEUE_TXDMA_CP_TX_CP_SHIFT (0x00000000u) #define CSL_SRIO_QUEUE_TXDMA_CP_TX_CP_RESETVAL (0x00000000u) #define CSL_SRIO_QUEUE_TXDMA_CP_RESETVAL (0x00000000u) / QUEUE_RXDMA_HDP / #define CSL_SRIO_QUEUE_RXDMA_HDP_RX_HDP_MASK (0xFFFFFFFFu) #define CSL_SRIO_QUEUE_RXDMA_HDP_RX_HDP_SHIFT (0x00000000u) #define CSL_SRIO_QUEUE_RXDMA_HDP_RX_HDP_RESETVAL (0x00000000u) #define CSL_SRIO_QUEUE_RXDMA_HDP_RESETVAL (0x00000000u) / QUEUE_RXDMA_CP / #define CSL_SRIO_QUEUE_RXDMA_CP_RX_CP_MASK (0xFFFFFFFFu) #define CSL_SRIO_QUEUE_RXDMA_CP_RX_CP_SHIFT (0x00000000u) #define CSL_SRIO_QUEUE_RXDMA_CP_RX_CP_RESETVAL (0x00000000u) #define CSL_SRIO_QUEUE_RXDMA_CP_RESETVAL (0x00000000u) / TX_QUEUE_TEAR_DOWN / #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_MASK (0x00008000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_SHIFT (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_MASK (0x00004000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_SHIFT (0x0000000Eu) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_MASK (0x00002000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_SHIFT (0x0000000Du) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_MASK (0x00001000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_MASK (0x00000800u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_SHIFT (0x0000000Bu) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_MASK (0x00000400u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_SHIFT (0x0000000Au) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_MASK (0x00000200u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_SHIFT (0x00000009u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_MASK (0x00000100u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_MASK (0x00000080u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_SHIFT (0x00000007u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_MASK (0x00000040u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_SHIFT (0x00000006u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_MASK (0x00000020u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_SHIFT (0x00000005u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_MASK (0x00000010u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_MASK (0x00000008u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_SHIFT (0x00000003u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_MASK (0x00000004u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_SHIFT (0x00000002u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_MASK (0x00000002u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_SHIFT (0x00000001u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_MASK (0x00000001u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_RESETVAL (0x00000000u) /----QUEUE Tokens----/ #define CSL_SRIO_QUEUE_TEAR_DOWN (0x00000001u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_RESETVAL (0x00000000u) / TX_CPPI_FLOW_MASKS / #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK15_MASK (0x80000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK15_SHIFT (0x0000001Fu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK15_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK14_MASK (0x40000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK14_SHIFT (0x0000001Eu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK14_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK13_MASK (0x20000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK13_SHIFT (0x0000001Du) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK13_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK12_MASK (0x10000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK12_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK12_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK11_MASK (0x08000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK11_SHIFT (0x0000001Bu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK11_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK10_MASK (0x04000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK10_SHIFT (0x0000001Au) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK10_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK9_MASK (0x02000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK9_SHIFT (0x00000019u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK9_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK8_MASK (0x01000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK8_SHIFT (0x00000018u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK8_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK7_MASK (0x00800000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK7_SHIFT (0x00000017u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK7_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK6_MASK (0x00400000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK6_SHIFT (0x00000016u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK6_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK5_MASK (0x00200000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK5_SHIFT (0x00000015u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK5_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK4_MASK (0x00100000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK4_SHIFT (0x00000014u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK4_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK3_MASK (0x00080000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK3_SHIFT (0x00000013u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK3_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK2_MASK (0x00040000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK2_SHIFT (0x00000012u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK2_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK1_MASK (0x00020000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK1_SHIFT (0x00000011u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK1_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK0_MASK (0x00010000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK0_SHIFT (0x000000010u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK0_RESETVAL (0x00000001u) /----QUEUE1_FLOW_MASK Tokens----/ #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK_DISABLE (0x00000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK_ENABLE (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK15_MASK (0x00008000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK15_SHIFT (0x0000000Fu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK15_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK14_MASK (0x00004000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK14_SHIFT (0x0000000Eu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK14_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK13_MASK (0x00002000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK13_SHIFT (0x0000000Du) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK13_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK12_MASK (0x00001000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK12_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK12_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK11_MASK (0x00000800u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK11_SHIFT (0x0000000Bu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK11_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK10_MASK (0x00000400u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK10_SHIFT (0x0000000Au) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK10_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK9_MASK (0x00000200u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK9_SHIFT (0x00000009u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK9_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK8_MASK (0x00000100u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK8_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK8_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK7_MASK (0x00000080u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK7_SHIFT (0x00000007u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK7_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK6_MASK (0x00000040u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK6_SHIFT (0x00000006u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK6_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK5_MASK (0x00000020u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK5_SHIFT (0x00000005u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK5_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK4_MASK (0x00000010u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK4_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK4_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK3_MASK (0x00000008u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK3_SHIFT (0x00000003u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK3_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK2_MASK (0x00000004u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK2_SHIFT (0x00000002u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK2_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK1_MASK (0x00000002u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK1_SHIFT (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK1_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK0_MASK (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK0_RESETVAL (0x00000001u) /----QUEUE0_FLOW_MASK Tokens----/ #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK_DISABLE (0x00000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK_ENABLE (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_RESETVAL (0xFFFFFFFFu) / RX_QUEUE_TEAR_DOWN / #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_MASK (0x00008000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_SHIFT (0x0000000Fu) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_MASK (0x00004000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_SHIFT (0x0000000Eu) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_MASK (0x00002000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_SHIFT (0x0000000Du) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_MASK (0x00001000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_MASK (0x00000800u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_SHIFT (0x0000000Bu) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_MASK (0x00000400u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_SHIFT (0x0000000Au) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_MASK (0x00000200u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_SHIFT (0x00000009u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_MASK (0x00000100u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_SHIFT (0x00000008u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_MASK (0x00000080u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_SHIFT (0x00000007u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_MASK (0x00000040u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_SHIFT (0x00000006u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_MASK (0x00000020u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_SHIFT (0x00000005u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_MASK (0x00000010u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_SHIFT (0x00000004u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_MASK (0x00000008u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_SHIFT (0x00000003u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_MASK (0x00000004u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_SHIFT (0x00000002u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_MASK (0x00000002u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_SHIFT (0x00000001u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_MASK (0x00000001u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_SHIFT (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_RESETVAL (0x00000000u) / RX_CPPI_CNTL / #define CSL_SRIO_RX_CPPI_CNTL_QUEUE15_IN_ORDER_MASK (0x00008000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE15_IN_ORDER_SHIFT (0x0000000Fu) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE15_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE14_IN_ORDER_MASK (0x00004000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE14_IN_ORDER_SHIFT (0x0000000Eu) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE14_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE13_IN_ORDER_MASK (0x00002000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE13_IN_ORDER_SHIFT (0x0000000Du) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE13_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE12_IN_ORDER_MASK (0x00001000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE12_IN_ORDER_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE12_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE11_IN_ORDER_MASK (0x00000800u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE11_IN_ORDER_SHIFT (0x0000000Bu) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE11_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE10_IN_ORDER_MASK (0x00000400u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE10_IN_ORDER_SHIFT (0x0000000Au) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE10_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE9_IN_ORDER_MASK (0x00000200u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE9_IN_ORDER_SHIFT (0x00000009u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE9_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE8_IN_ORDER_MASK (0x00000100u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE8_IN_ORDER_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE8_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE7_IN_ORDER_MASK (0x00000080u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE7_IN_ORDER_SHIFT (0x00000007u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE7_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE6_IN_ORDER_MASK (0x00000040u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE6_IN_ORDER_SHIFT (0x00000006u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE6_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE5_IN_ORDER_MASK (0x00000020u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE5_IN_ORDER_SHIFT (0x00000005u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE5_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE4_IN_ORDER_MASK (0x00000010u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE4_IN_ORDER_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE4_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE3_IN_ORDER_MASK (0x00000008u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE3_IN_ORDER_SHIFT (0x00000003u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE3_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE2_IN_ORDER_MASK (0x00000004u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE2_IN_ORDER_SHIFT (0x00000002u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE2_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE1_IN_ORDER_MASK (0x00000002u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE1_IN_ORDER_SHIFT (0x00000001u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE1_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE0_IN_ORDER_MASK (0x00000001u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE0_IN_ORDER_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE0_IN_ORDER_RESETVAL (0x00000000u) /----QUEUE Tokens----/ #define CSL_SRIO_RX_CPPI_CNTL_QUEUE_IN_ORDER_DISABLE (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE_IN_ORDER_ENABLE (0x00000001u) #define CSL_SRIO_RX_CPPI_CNTL_RESETVAL (0x00000000u) / TX_QUEUE_CNTL0 / #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_NUM_MSGS_MASK (0xF0000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_NUM_MSGS_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_QUEUE_PTR_MASK (0x0F000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_QUEUE_PTR_SHIFT (0x00000018u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_QUEUE_PTR_RESETVAL (0x00000003u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_NUM_MSGS_MASK (0x00F00000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_NUM_MSGS_SHIFT (0x00000014u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_QUEUE_PTR_MASK (0x000F0000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_QUEUE_PTR_SHIFT (0x00000010u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_QUEUE_PTR_RESETVAL (0x00000002u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_NUM_MSGS_MASK (0x0000F000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_NUM_MSGS_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_QUEUE_PTR_MASK (0x00000F00u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_QUEUE_PTR_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_QUEUE_PTR_RESETVAL (0x00000001u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_NUM_MSGS_MASK (0x000000F0u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_NUM_MSGS_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_QUEUE_PTR_MASK (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_QUEUE_PTR_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_QUEUE_PTR_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_RESETVAL (0x03020100u) / TX_QUEUE_CNTL1 / #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_NUM_MSGS_MASK (0xF0000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_NUM_MSGS_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_QUEUE_PTR_MASK (0x0F000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_QUEUE_PTR_SHIFT (0x00000018u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_QUEUE_PTR_RESETVAL (0x00000007u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_NUM_MSGS_MASK (0x00F00000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_NUM_MSGS_SHIFT (0x00000014u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_QUEUE_PTR_MASK (0x000F0000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_QUEUE_PTR_SHIFT (0x00000010u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_QUEUE_PTR_RESETVAL (0x00000006u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_NUM_MSGS_MASK (0x0000F000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_NUM_MSGS_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_QUEUE_PTR_MASK (0x00000F00u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_QUEUE_PTR_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_QUEUE_PTR_RESETVAL (0x00000005u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_NUM_MSGS_MASK (0x000000F0u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_NUM_MSGS_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_QUEUE_PTR_MASK (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_QUEUE_PTR_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_QUEUE_PTR_RESETVAL (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL1_RESETVAL (0x07060504u) / TX_QUEUE_CNTL2 / #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_NUM_MSGS_MASK (0xF0000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_NUM_MSGS_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_QUEUE_PTR_MASK (0x0F000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_QUEUE_PTR_SHIFT (0x00000018u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_QUEUE_PTR_RESETVAL (0x0000000Bu) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_NUM_MSGS_MASK (0x00F00000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_NUM_MSGS_SHIFT (0x00000014u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_QUEUE_PTR_MASK (0x000F0000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_QUEUE_PTR_SHIFT (0x00000010u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_QUEUE_PTR_RESETVAL (0x0000000Au) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_NUM_MSGS_MASK (0x0000F000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_NUM_MSGS_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_QUEUE_PTR_MASK (0x00000F00u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_QUEUE_PTR_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_QUEUE_PTR_RESETVAL (0x00000009u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_NUM_MSGS_MASK (0x000000F0u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_NUM_MSGS_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_QUEUE_PTR_MASK (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_QUEUE_PTR_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_QUEUE_PTR_RESETVAL (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL2_RESETVAL (0x0B0A0908u) / TX_QUEUE_CNTL3 / #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_NUM_MSGS_MASK (0xF0000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_NUM_MSGS_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_QUEUE_PTR_MASK (0x0F000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_QUEUE_PTR_SHIFT (0x00000018u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_QUEUE_PTR_RESETVAL (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_NUM_MSGS_MASK (0x00F00000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_NUM_MSGS_SHIFT (0x00000014u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_QUEUE_PTR_MASK (0x000F0000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_QUEUE_PTR_SHIFT (0x00000010u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_QUEUE_PTR_RESETVAL (0x0000000Eu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_NUM_MSGS_MASK (0x0000F000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_NUM_MSGS_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_QUEUE_PTR_MASK (0x00000F00u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_QUEUE_PTR_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_QUEUE_PTR_RESETVAL (0x0000000Du) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_NUM_MSGS_MASK (0x000000F0u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_NUM_MSGS_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_QUEUE_PTR_MASK (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_QUEUE_PTR_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_QUEUE_PTR_RESETVAL (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL3_RESETVAL (0x0F0E0D0Cu) / RXU_MAP_L / #define CSL_SRIO_RXU_MAP_L_LETTER_MASK_MASK (0xC0000000u) #define CSL_SRIO_RXU_MAP_L_LETTER_MASK_SHIFT (0x0000001Eu) #define CSL_SRIO_RXU_MAP_L_LETTER_MASK_RESETVAL (0x00000003u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_MASK_MASK (0x3F000000u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_MASK_SHIFT (0x00000018u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_MASK_RESETVAL (0x0000003Fu) #define CSL_SRIO_RXU_MAP_L_LETTER_MASK (0x00C00000u) #define CSL_SRIO_RXU_MAP_L_LETTER_SHIFT (0x00000016u) #define CSL_SRIO_RXU_MAP_L_LETTER_RESETVAL (0x00000000u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_MASK (0x003F0000u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_SHIFT (0x00000010u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_RESETVAL (0x00000000u) #define CSL_SRIO_RXU_MAP_L_SOURCEID_MASK (0x0000FFFFu) #define CSL_SRIO_RXU_MAP_L_SOURCEID_SHIFT (0x00000000u) #define CSL_SRIO_RXU_MAP_L_SOURCEID_RESETVAL (0x00000000u) #define CSL_SRIO_RXU_MAP_L_RESETVAL (0xFF000000u) / RXU_MAP_H / #define CSL_SRIO_RXU_MAP_H_TT_MASK (0x00000300u) #define CSL_SRIO_RXU_MAP_H_TT_SHIFT (0x00000008u) #define CSL_SRIO_RXU_MAP_H_TT_RESETVAL (0x00000001u) /----TT Tokens----/ #define CSL_SRIO_RXU_MAP_H_TT_MATCH_8BIT_SRCID (0x00000000u) #define CSL_SRIO_RXU_MAP_H_TT_MATCH_16BIT_SRCID (0x00000001u) #define CSL_SRIO_RXU_MAP_H_QUEUE_ID_MASK (0x0000003Cu) #define CSL_SRIO_RXU_MAP_H_QUEUE_ID_SHIFT (0x00000002u) #define CSL_SRIO_RXU_MAP_H_QUEUE_ID_RESETVAL (0x00000000u) #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_MASK (0x00000002u) #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_SHIFT (0x00000001u) #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_RESETVAL (0x00000000u) /----PROMISCUOUS Tokens----/ #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_DISABLE (0x00000000u) #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_ENABLE (0x00000001u) #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_MASK (0x00000001u) #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_SHIFT (0x00000000u) #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_RESETVAL (0x00000000u) /----SEGMENT_MAPPING Tokens----/ #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_SINGLE_SEGMENT (0x00000000u) #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_MULTI_SEGMENT (0x00000001u) #define CSL_SRIO_RXU_MAP_H_RESETVAL (0x00000100u) / FLOW_CNTL / #define CSL_SRIO_FLOW_CNTL_TT_MASK (0x00030000u) #define CSL_SRIO_FLOW_CNTL_TT_SHIFT (0x00000010u) #define CSL_SRIO_FLOW_CNTL_TT_RESETVAL (0x00000001u) /----TT Tokens----/ #define CSL_SRIO_FLOW_CNTL_TT_8BIT_ID (0x00000000u) #define CSL_SRIO_FLOW_CNTL_TT_16BIT_ID (0x00000001u) #define CSL_SRIO_FLOW_CNTL_FLOW_CNTL_ID_MASK (0x0000FFFFu) #define CSL_SRIO_FLOW_CNTL_FLOW_CNTL_ID_SHIFT (0x00000000u) #define CSL_SRIO_FLOW_CNTL_FLOW_CNTL_ID_RESETVAL (0x00000000u) #define CSL_SRIO_FLOW_CNTL_RESETVAL (0x00010000u) / DEV_ID / #define CSL_SRIO_DEV_ID_DEVICEIDENTITY_MASK (0xFFFF0000u) #define CSL_SRIO_DEV_ID_DEVICEIDENTITY_SHIFT (0x00000010u) #define CSL_SRIO_DEV_ID_DEVICEIDENTITY_RESETVAL (0x00000000u) #define CSL_SRIO_DEV_ID_DEVICE_VENDORIDENTITY_MASK (0x0000FFFFu) #define CSL_SRIO_DEV_ID_DEVICE_VENDORIDENTITY_SHIFT (0x00000000u) #define CSL_SRIO_DEV_ID_DEVICE_VENDORIDENTITY_RESETVAL (0x00000030u) #define CSL_SRIO_DEV_ID_RESETVAL (0x00000030u) / DEV_INFO / #define CSL_SRIO_DEV_INFO_DEVICEREV_MASK (0xFFFFFFFFu) #define CSL_SRIO_DEV_INFO_DEVICEREV_SHIFT (0x00000000u) #define CSL_SRIO_DEV_INFO_DEVICEREV_RESETVAL (0x00000000u) #define CSL_SRIO_DEV_INFO_RESETVAL (0x00000000u) / ASBLY_ID / #define CSL_SRIO_ASBLY_ID_ASSY_IDENTITY_MASK (0xFFFF0000u) #define CSL_SRIO_ASBLY_ID_ASSY_IDENTITY_SHIFT (0x00000010u) #define CSL_SRIO_ASBLY_ID_ASSY_IDENTITY_RESETVAL (0x00000000u) #define CSL_SRIO_ASBLY_ID_ASSY_VENDORIDENTITY_MASK (0x0000FFFFu) #define CSL_SRIO_ASBLY_ID_ASSY_VENDORIDENTITY_SHIFT (0x00000000u) #define CSL_SRIO_ASBLY_ID_ASSY_VENDORIDENTITY_RESETVAL (0x00000030u) #define CSL_SRIO_ASBLY_ID_RESETVAL (0x00000030u) / ASBLY_INFO / #define CSL_SRIO_ASBLY_INFO_ASSYREV_MASK (0xFFFF0000u) #define CSL_SRIO_ASBLY_INFO_ASSYREV_SHIFT (0x00000010u) #define CSL_SRIO_ASBLY_INFO_ASSYREV_RESETVAL (0x00000000u) #define CSL_SRIO_ASBLY_INFO_EXTENDEDFEATURESPTR_MASK (0x0000FFFFu) #define CSL_SRIO_ASBLY_INFO_EXTENDEDFEATURESPTR_SHIFT (0x00000000u) #define CSL_SRIO_ASBLY_INFO_EXTENDEDFEATURESPTR_RESETVAL (0x00000100u) #define CSL_SRIO_ASBLY_INFO_RESETVAL (0x00000100u) / PE_FEAT / #define CSL_SRIO_PE_FEAT_BRIDGE_MASK (0x80000000u) #define CSL_SRIO_PE_FEAT_BRIDGE_SHIFT (0x0000001Fu) #define CSL_SRIO_PE_FEAT_BRIDGE_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_MEMORY_MASK (0x40000000u) #define CSL_SRIO_PE_FEAT_MEMORY_SHIFT (0x0000001Eu) #define CSL_SRIO_PE_FEAT_MEMORY_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_PROCESSOR_MASK (0x20000000u) #define CSL_SRIO_PE_FEAT_PROCESSOR_SHIFT (0x0000001Du) #define CSL_SRIO_PE_FEAT_PROCESSOR_RESETVAL (0x00000001u) #define CSL_SRIO_PE_FEAT_SWITCH_MASK (0x10000000u) #define CSL_SRIO_PE_FEAT_SWITCH_SHIFT (0x0000001Cu) #define CSL_SRIO_PE_FEAT_SWITCH_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_FLOW_CONTROL_SUPPORT_MASK (0x00000080u) #define CSL_SRIO_PE_FEAT_FLOW_CONTROL_SUPPORT_SHIFT (0x00000007u) #define CSL_SRIO_PE_FEAT_FLOW_CONTROL_SUPPORT_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_RETRANSMIT_SUPPRESS_MASK (0x00000040u) #define CSL_SRIO_PE_FEAT_RETRANSMIT_SUPPRESS_SHIFT (0x00000006u) #define CSL_SRIO_PE_FEAT_RETRANSMIT_SUPPRESS_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_CRF_SUPPORT_MASK (0x00000020u) #define CSL_SRIO_PE_FEAT_CRF_SUPPORT_SHIFT (0x00000005u) #define CSL_SRIO_PE_FEAT_CRF_SUPPORT_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_LARGE_SUPPORT_MASK (0x00000010u) #define CSL_SRIO_PE_FEAT_LARGE_SUPPORT_SHIFT (0x00000004u) #define CSL_SRIO_PE_FEAT_LARGE_SUPPORT_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_EXTENDED_FEATURES_MASK (0x00000008u) #define CSL_SRIO_PE_FEAT_EXTENDED_FEATURES_SHIFT (0x00000003u) #define CSL_SRIO_PE_FEAT_EXTENDED_FEATURES_RESETVAL (0x00000001u) #define CSL_SRIO_PE_FEAT_EXTENDED_ADDRESSING_SUPPORT_MASK (0x00000007u) #define CSL_SRIO_PE_FEAT_EXTENDED_ADDRESSING_SUPPORT_SHIFT (0x00000000u) #define CSL_SRIO_PE_FEAT_EXTENDED_ADDRESSING_SUPPORT_RESETVAL (0x00000001u) #define CSL_SRIO_PE_FEAT_RESETVAL (0x20000009u) / SRC_OP / #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_2_MASK (0x00030000u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_2_SHIFT (0x00000010u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_2_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_READ_MASK (0x00008000u) #define CSL_SRIO_SRC_OP_READ_SHIFT (0x0000000Fu) #define CSL_SRIO_SRC_OP_READ_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_WRITE_MASK (0x00004000u) #define CSL_SRIO_SRC_OP_WRITE_SHIFT (0x0000000Eu) #define CSL_SRIO_SRC_OP_WRITE_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_STREAM_WRITE_MASK (0x00002000u) #define CSL_SRIO_SRC_OP_STREAM_WRITE_SHIFT (0x0000000Du) #define CSL_SRIO_SRC_OP_STREAM_WRITE_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_WRITE_WITH_RESP_MASK (0x00001000u) #define CSL_SRIO_SRC_OP_WRITE_WITH_RESP_SHIFT (0x0000000Cu) #define CSL_SRIO_SRC_OP_WRITE_WITH_RESP_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_DATA_MESS_MASK (0x00000800u) #define CSL_SRIO_SRC_OP_DATA_MESS_SHIFT (0x0000000Bu) #define CSL_SRIO_SRC_OP_DATA_MESS_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_DOORBELL_MASK (0x00000400u) #define CSL_SRIO_SRC_OP_DOORBELL_SHIFT (0x0000000Au) #define CSL_SRIO_SRC_OP_DOORBELL_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_TEST_AND_SWAP_MASK (0x00000100u) #define CSL_SRIO_SRC_OP_ATOMIC_TEST_AND_SWAP_SHIFT (0x00000008u) #define CSL_SRIO_SRC_OP_ATOMIC_TEST_AND_SWAP_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_INCRMNT_MASK (0x00000080u) #define CSL_SRIO_SRC_OP_ATOMIC_INCRMNT_SHIFT (0x00000007u) #define CSL_SRIO_SRC_OP_ATOMIC_INCRMNT_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_DCRMNT_MASK (0x00000040u) #define CSL_SRIO_SRC_OP_ATOMIC_DCRMNT_SHIFT (0x00000006u) #define CSL_SRIO_SRC_OP_ATOMIC_DCRMNT_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_SET_MASK (0x00000020u) #define CSL_SRIO_SRC_OP_ATOMIC_SET_SHIFT (0x00000005u) #define CSL_SRIO_SRC_OP_ATOMIC_SET_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_CLEAR_MASK (0x00000010u) #define CSL_SRIO_SRC_OP_ATOMIC_CLEAR_SHIFT (0x00000004u) #define CSL_SRIO_SRC_OP_ATOMIC_CLEAR_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_PORT_WRITE_MASK (0x00000004u) #define CSL_SRIO_SRC_OP_PORT_WRITE_SHIFT (0x00000002u) #define CSL_SRIO_SRC_OP_PORT_WRITE_RESETVAL (0x00000001u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_1_MASK (0x00000003u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_1_SHIFT (0x00000000u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_1_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_RESETVAL (0x00000004u) / DEST_OP / #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_2_MASK (0x00030000u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_2_SHIFT (0x00000010u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_2_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_READ_MASK (0x00008000u) #define CSL_SRIO_DEST_OP_READ_SHIFT (0x0000000Fu) #define CSL_SRIO_DEST_OP_READ_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_WRITE_MASK (0x00004000u) #define CSL_SRIO_DEST_OP_WRITE_SHIFT (0x0000000Eu) #define CSL_SRIO_DEST_OP_WRITE_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_STREAM_WRITE_MASK (0x00002000u) #define CSL_SRIO_DEST_OP_STREAM_WRITE_SHIFT (0x0000000Du) #define CSL_SRIO_DEST_OP_STREAM_WRITE_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_WRITE_WITH_RESP_MASK (0x00001000u) #define CSL_SRIO_DEST_OP_WRITE_WITH_RESP_SHIFT (0x0000000Cu) #define CSL_SRIO_DEST_OP_WRITE_WITH_RESP_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_DATA_MESS_MASK (0x00000800u) #define CSL_SRIO_DEST_OP_DATA_MESS_SHIFT (0x0000000Bu) #define CSL_SRIO_DEST_OP_DATA_MESS_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_DOORBELL_MASK (0x00000400u) #define CSL_SRIO_DEST_OP_DOORBELL_SHIFT (0x0000000Au) #define CSL_SRIO_DEST_OP_DOORBELL_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_TEST_AND_SWAP_MASK (0x00000100u) #define CSL_SRIO_DEST_OP_ATOMIC_TEST_AND_SWAP_SHIFT (0x00000008u) #define CSL_SRIO_DEST_OP_ATOMIC_TEST_AND_SWAP_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_INCRMNT_MASK (0x00000080u) #define CSL_SRIO_DEST_OP_ATOMIC_INCRMNT_SHIFT (0x00000007u) #define CSL_SRIO_DEST_OP_ATOMIC_INCRMNT_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_DCRMNT_MASK (0x00000040u) #define CSL_SRIO_DEST_OP_ATOMIC_DCRMNT_SHIFT (0x00000006u) #define CSL_SRIO_DEST_OP_ATOMIC_DCRMNT_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_SET_MASK (0x00000020u) #define CSL_SRIO_DEST_OP_ATOMIC_SET_SHIFT (0x00000005u) #define CSL_SRIO_DEST_OP_ATOMIC_SET_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_CLEAR_MASK (0x00000010u) #define CSL_SRIO_DEST_OP_ATOMIC_CLEAR_SHIFT (0x00000004u) #define CSL_SRIO_DEST_OP_ATOMIC_CLEAR_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_PORT_WRITE_MASK (0x00000004u) #define CSL_SRIO_DEST_OP_PORT_WRITE_SHIFT (0x00000002u) #define CSL_SRIO_DEST_OP_PORT_WRITE_RESETVAL (0x00000001u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_1_MASK (0x00000003u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_1_SHIFT (0x00000000u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_1_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_RESETVAL (0x00000004u) / PE_LL_CTL / #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_MASK (0x00000007u) #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_SHIFT (0x00000000u) #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_RESETVAL (0x00000001u) /----EXTENDED_ADDRESSING_CONTROL Tokens----/ #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_66BIT (0x00000004u) #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_50BIT (0x00000002u) #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_34BIT (0x00000001u) #define CSL_SRIO_PE_LL_CTL_RESETVAL (0x00000001u) / LCL_CFG_HBAR / #define CSL_SRIO_LCL_CFG_HBAR_LCSBA_MASK (0x7FFFFFFFu) #define CSL_SRIO_LCL_CFG_HBAR_LCSBA_SHIFT (0x00000000u) #define CSL_SRIO_LCL_CFG_HBAR_LCSBA_RESETVAL (0x00000000u) #define CSL_SRIO_LCL_CFG_HBAR_RESETVAL (0x00000000u) / LCL_CFG_BAR / #define CSL_SRIO_LCL_CFG_BAR_LCSBA_MASK (0xFFFFFFFFu) #define CSL_SRIO_LCL_CFG_BAR_LCSBA_SHIFT (0x00000000u) #define CSL_SRIO_LCL_CFG_BAR_LCSBA_RESETVAL (0x00000000u) #define CSL_SRIO_LCL_CFG_BAR_RESETVAL (0x00000000u) / BASE_ID / #define CSL_SRIO_BASE_ID_BASE_DEVICEID_MASK (0x00FF0000u) #define CSL_SRIO_BASE_ID_BASE_DEVICEID_SHIFT (0x00000010u) #define CSL_SRIO_BASE_ID_BASE_DEVICEID_RESETVAL (0x000000FFu) #define CSL_SRIO_BASE_ID_LARGE_BASE_DEVICEID_MASK (0x0000FFFFu) #define CSL_SRIO_BASE_ID_LARGE_BASE_DEVICEID_SHIFT (0x00000000u) #define CSL_SRIO_BASE_ID_LARGE_BASE_DEVICEID_RESETVAL (0x0000FFFFu) #define CSL_SRIO_BASE_ID_RESETVAL (0x00FFFFFFu) / HOST_BASE_ID_LOCK / #define CSL_SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID_MASK (0x0000FFFFu) #define CSL_SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID_SHIFT (0x00000000u) #define CSL_SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID_RESETVAL (0x0000FFFFu) #define CSL_SRIO_HOST_BASE_ID_LOCK_RESETVAL (0x0000FFFFu) / COMP_TAG / #define CSL_SRIO_COMP_TAG_COMPONENT_TAG_MASK (0xFFFFFFFFu) #define CSL_SRIO_COMP_TAG_COMPONENT_TAG_SHIFT (0x00000000u) #define CSL_SRIO_COMP_TAG_COMPONENT_TAG_RESETVAL (0x00000000u) #define CSL_SRIO_COMP_TAG_RESETVAL (0x00000000u) / SP_MB_HEAD / #define CSL_SRIO_SP_MB_HEAD_EF_PTR_MASK (0xFFFF0000u) #define CSL_SRIO_SP_MB_HEAD_EF_PTR_SHIFT (0x00000010u) #define CSL_SRIO_SP_MB_HEAD_EF_PTR_RESETVAL (0x00001000u) #define CSL_SRIO_SP_MB_HEAD_EF_ID_MASK (0x0000FFFFu) #define CSL_SRIO_SP_MB_HEAD_EF_ID_SHIFT (0x00000000u) #define CSL_SRIO_SP_MB_HEAD_EF_ID_RESETVAL (0x00000001u) #define CSL_SRIO_SP_MB_HEAD_RESETVAL (0x10000001u) / SP_LT_CTL / #define CSL_SRIO_SP_LT_CTL_TIMEOUT_VALUE_MASK (0xFFFFFF00u) #define CSL_SRIO_SP_LT_CTL_TIMEOUT_VALUE_SHIFT (0x00000008u) #define CSL_SRIO_SP_LT_CTL_TIMEOUT_VALUE_RESETVAL (0x00FFFFFFu) #define CSL_SRIO_SP_LT_CTL_RESETVAL (0xFFFFFF00u) / SP_RT_CTL / #define CSL_SRIO_SP_RT_CTL_TIMEOUT_VALUE_MASK (0xFFFFFF00u) #define CSL_SRIO_SP_RT_CTL_TIMEOUT_VALUE_SHIFT (0x00000008u) #define CSL_SRIO_SP_RT_CTL_TIMEOUT_VALUE_RESETVAL (0x00FFFFFFu) #define CSL_SRIO_SP_RT_CTL_RESETVAL (0xFFFFFF00u) / SP_GEN_CTL / #define CSL_SRIO_SP_GEN_CTL_HOST_MASK (0x80000000u) #define CSL_SRIO_SP_GEN_CTL_HOST_SHIFT (0x0000001Fu) #define CSL_SRIO_SP_GEN_CTL_HOST_RESETVAL (0x00000000u) /----HOST Tokens----/ #define CSL_SRIO_SP_GEN_CTL_HOST_DISABLE (0x00000000u) #define CSL_SRIO_SP_GEN_CTL_HOST_ENABLE (0x00000001u) #define CSL_SRIO_SP_GEN_CTL_MASTER_ENABLE_MASK (0x40000000u) #define CSL_SRIO_SP_GEN_CTL_MASTER_ENABLE_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_GEN_CTL_MASTER_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_GEN_CTL_DISCOVERED_MASK (0x20000000u) #define CSL_SRIO_SP_GEN_CTL_DISCOVERED_SHIFT (0x0000001Du) #define CSL_SRIO_SP_GEN_CTL_DISCOVERED_RESETVAL (0x00000000u) #define CSL_SRIO_SP_GEN_CTL_RESETVAL (0x00000000u) / SP_LM_REQ / #define CSL_SRIO_SP_LM_REQ_COMMAND_MASK (0x00000007u) #define CSL_SRIO_SP_LM_REQ_COMMAND_SHIFT (0x00000000u) #define CSL_SRIO_SP_LM_REQ_COMMAND_RESETVAL (0x00000000u) #define CSL_SRIO_SP_LM_REQ_RESETVAL (0x00000000u) / SP_LM_RESP / #define CSL_SRIO_SP_LM_RESP_RESPONSE_VALID_MASK (0x80000000u) #define CSL_SRIO_SP_LM_RESP_RESPONSE_VALID_SHIFT (0x0000001Fu) #define CSL_SRIO_SP_LM_RESP_RESPONSE_VALID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_LM_RESP_ACKID_STATUS_MASK (0x000003E0u) #define CSL_SRIO_SP_LM_RESP_ACKID_STATUS_SHIFT (0x00000005u) #define CSL_SRIO_SP_LM_RESP_ACKID_STATUS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_LM_RESP_LINK_STATUS_MASK (0x0000001Fu) #define CSL_SRIO_SP_LM_RESP_LINK_STATUS_SHIFT (0x00000000u) #define CSL_SRIO_SP_LM_RESP_LINK_STATUS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_LM_RESP_RESETVAL (0x00000000u) / SP_ACKID_STAT / #define CSL_SRIO_SP_ACKID_STAT_INBOUND_ACKID_MASK (0x1F000000u) #define CSL_SRIO_SP_ACKID_STAT_INBOUND_ACKID_SHIFT (0x00000018u) #define CSL_SRIO_SP_ACKID_STAT_INBOUND_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ACKID_STAT_OUTSTANDING_ACKID_MASK (0x00001F00u) #define CSL_SRIO_SP_ACKID_STAT_OUTSTANDING_ACKID_SHIFT (0x00000008u) #define CSL_SRIO_SP_ACKID_STAT_OUTSTANDING_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ACKID_STAT_OUTBOUND_ACKID_MASK (0x0000001Fu) #define CSL_SRIO_SP_ACKID_STAT_OUTBOUND_ACKID_SHIFT (0x00000000u) #define CSL_SRIO_SP_ACKID_STAT_OUTBOUND_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ACKID_STAT_RESETVAL (0x00000000u) / SP_ERR_STAT / #define CSL_SRIO_SP_ERR_STAT_OUTPUT_PKT_DROP_MASK (0x04000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_PKT_DROP_SHIFT (0x0000001Au) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_PKT_DROP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_FLD_ENC_MASK (0x02000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_FLD_ENC_SHIFT (0x00000019u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_FLD_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_DEGRD_ENC_MASK (0x01000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_DEGRD_ENC_SHIFT (0x00000018u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_DEGRD_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_ENC_MASK (0x00100000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_ENC_SHIFT (0x00000014u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRIED_MASK (0x00080000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRIED_SHIFT (0x00000013u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRIED_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_STP_MASK (0x00040000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_STP_SHIFT (0x00000012u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_STP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_ENC_MASK (0x00020000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_ENC_SHIFT (0x00000011u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_STP_MASK (0x00010000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_STP_SHIFT (0x00000010u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_STP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_INPUT_RETRY_STP_MASK (0x00000400u) #define CSL_SRIO_SP_ERR_STAT_INPUT_RETRY_STP_SHIFT (0x0000000Au) #define CSL_SRIO_SP_ERR_STAT_INPUT_RETRY_STP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_ENC_MASK (0x00000200u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_ENC_SHIFT (0x00000009u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_STP_MASK (0x00000100u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_STP_SHIFT (0x00000008u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_STP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_WRITE_PND_MASK (0x00000010u) #define CSL_SRIO_SP_ERR_STAT_PORT_WRITE_PND_SHIFT (0x00000004u) #define CSL_SRIO_SP_ERR_STAT_PORT_WRITE_PND_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_ERROR_MASK (0x00000004u) #define CSL_SRIO_SP_ERR_STAT_PORT_ERROR_SHIFT (0x00000002u) #define CSL_SRIO_SP_ERR_STAT_PORT_ERROR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_OK_MASK (0x00000002u) #define CSL_SRIO_SP_ERR_STAT_PORT_OK_SHIFT (0x00000001u) #define CSL_SRIO_SP_ERR_STAT_PORT_OK_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_UNINITIALIZED_MASK (0x00000001u) #define CSL_SRIO_SP_ERR_STAT_PORT_UNINITIALIZED_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_UNINITIALIZED_RESETVAL (0x00000001u) #define CSL_SRIO_SP_ERR_STAT_RESETVAL (0x00000001u) / SP_CTL / #define CSL_SRIO_SP_CTL_PORT_WIDTH_MASK (0xC0000000u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_CTL_PORT_WIDTH_RESETVAL (0x00000001u) #define CSL_SRIO_SP_CTL_INITIALIZED_PORT_WIDTH_MASK (0x38000000u) #define CSL_SRIO_SP_CTL_INITIALIZED_PORT_WIDTH_SHIFT (0x0000001Bu) #define CSL_SRIO_SP_CTL_INITIALIZED_PORT_WIDTH_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_MASK (0x07000000u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_SHIFT (0x00000018u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_RESETVAL (0x00000000u) /----PORT_WIDTH_OVERRIDE Tokens----/ #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_NO_OVERRIDE (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_SINGLE_LANE_0 (0x00000002u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_SINGLE_LANE_2 (0x00000003u) #define CSL_SRIO_SP_CTL_PORT_DISABLE_MASK (0x00800000u) #define CSL_SRIO_SP_CTL_PORT_DISABLE_SHIFT (0x00000017u) #define CSL_SRIO_SP_CTL_PORT_DISABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_OUTPUT_PORT_ENABLE_MASK (0x00400000u) #define CSL_SRIO_SP_CTL_OUTPUT_PORT_ENABLE_SHIFT (0x00000016u) #define CSL_SRIO_SP_CTL_OUTPUT_PORT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INPUT_PORT_ENABLE_MASK (0x00200000u) #define CSL_SRIO_SP_CTL_INPUT_PORT_ENABLE_SHIFT (0x00000015u) #define CSL_SRIO_SP_CTL_INPUT_PORT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_ERROR_CHECK_DISABLE_MASK (0x00100000u) #define CSL_SRIO_SP_CTL_ERROR_CHECK_DISABLE_SHIFT (0x00000014u) #define CSL_SRIO_SP_CTL_ERROR_CHECK_DISABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_MULTICAST_PARTICIPANT_MASK (0x00080000u) #define CSL_SRIO_SP_CTL_MULTICAST_PARTICIPANT_SHIFT (0x00000013u) #define CSL_SRIO_SP_CTL_MULTICAST_PARTICIPANT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE_MASK (0x00000008u) #define CSL_SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE_SHIFT (0x00000003u) #define CSL_SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_DROP_PACKET_ENABLE_MASK (0x00000004u) #define CSL_SRIO_SP_CTL_DROP_PACKET_ENABLE_SHIFT (0x00000002u) #define CSL_SRIO_SP_CTL_DROP_PACKET_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_LOCKOUT_MASK (0x00000002u) #define CSL_SRIO_SP_CTL_PORT_LOCKOUT_SHIFT (0x00000001u) #define CSL_SRIO_SP_CTL_PORT_LOCKOUT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_TYPE_MASK (0x00000001u) #define CSL_SRIO_SP_CTL_PORT_TYPE_SHIFT (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_TYPE_RESETVAL (0x00000001u) #define CSL_SRIO_SP_CTL_RESETVAL (0x40000001u) / ERR_RPT_BH / #define CSL_SRIO_ERR_RPT_BH_EF_PTR_MASK (0xFFFF0000u) #define CSL_SRIO_ERR_RPT_BH_EF_PTR_SHIFT (0x00000010u) #define CSL_SRIO_ERR_RPT_BH_EF_PTR_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RPT_BH_EF_ID_MASK (0x0000FFFFu) #define CSL_SRIO_ERR_RPT_BH_EF_ID_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RPT_BH_EF_ID_RESETVAL (0x00000007u) #define CSL_SRIO_ERR_RPT_BH_RESETVAL (0x00000007u) / ERR_DET / #define CSL_SRIO_ERR_DET_IO_ERR_RSPNS_MASK (0x80000000u) #define CSL_SRIO_ERR_DET_IO_ERR_RSPNS_SHIFT (0x0000001Fu) #define CSL_SRIO_ERR_DET_IO_ERR_RSPNS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_MSG_ERR_RSPNS_MASK (0x40000000u) #define CSL_SRIO_ERR_DET_MSG_ERR_RSPNS_SHIFT (0x0000001Eu) #define CSL_SRIO_ERR_DET_MSG_ERR_RSPNS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_GSM_ERR_RSPNS_MASK (0x20000000u) #define CSL_SRIO_ERR_DET_GSM_ERR_RSPNS_SHIFT (0x0000001Du) #define CSL_SRIO_ERR_DET_GSM_ERR_RSPNS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_ERR_MSG_FORMAT_MASK (0x10000000u) #define CSL_SRIO_ERR_DET_ERR_MSG_FORMAT_SHIFT (0x0000001Cu) #define CSL_SRIO_ERR_DET_ERR_MSG_FORMAT_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_ILL_TRANS_DECODE_MASK (0x08000000u) #define CSL_SRIO_ERR_DET_ILL_TRANS_DECODE_SHIFT (0x0000001Bu) #define CSL_SRIO_ERR_DET_ILL_TRANS_DECODE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_ILL_TRANS_TRGT_ERR_MASK (0x04000000u) #define CSL_SRIO_ERR_DET_ILL_TRANS_TRGT_ERR_SHIFT (0x0000001Au) #define CSL_SRIO_ERR_DET_ILL_TRANS_TRGT_ERR_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_MSG_REQ_TIMEOUT_MASK (0x02000000u) #define CSL_SRIO_ERR_DET_MSG_REQ_TIMEOUT_SHIFT (0x00000019u) #define CSL_SRIO_ERR_DET_MSG_REQ_TIMEOUT_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_PKT_RSPNS_TIMEOUT_MASK (0x01000000u) #define CSL_SRIO_ERR_DET_PKT_RSPNS_TIMEOUT_SHIFT (0x00000018u) #define CSL_SRIO_ERR_DET_PKT_RSPNS_TIMEOUT_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_UNSOLICITED_RSPNS_MASK (0x00800000u) #define CSL_SRIO_ERR_DET_UNSOLICITED_RSPNS_SHIFT (0x00000017u) #define CSL_SRIO_ERR_DET_UNSOLICITED_RSPNS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_UNSUPPORTED_TRANS_MASK (0x00400000u) #define CSL_SRIO_ERR_DET_UNSUPPORTED_TRANS_SHIFT (0x00000016u) #define CSL_SRIO_ERR_DET_UNSUPPORTED_TRANS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_RX_CPPI_SECURITY_MASK (0x00000080u) #define CSL_SRIO_ERR_DET_RX_CPPI_SECURITY_SHIFT (0x00000007u) #define CSL_SRIO_ERR_DET_RX_CPPI_SECURITY_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_RX_IO_DMA_ACCESS_MASK (0x00000040u) #define CSL_SRIO_ERR_DET_RX_IO_DMA_ACCESS_SHIFT (0x00000006u) #define CSL_SRIO_ERR_DET_RX_IO_DMA_ACCESS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_RESETVAL (0x00000000u) / ERR_EN / #define CSL_SRIO_ERR_EN_IO_ERR_RESP_ENABLE_MASK (0x80000000u) #define CSL_SRIO_ERR_EN_IO_ERR_RESP_ENABLE_SHIFT (0x0000001Fu) #define CSL_SRIO_ERR_EN_IO_ERR_RESP_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_MSG_ERR_RESP_ENABLE_MASK (0x40000000u) #define CSL_SRIO_ERR_EN_MSG_ERR_RESP_ENABLE_SHIFT (0x0000001Eu) #define CSL_SRIO_ERR_EN_MSG_ERR_RESP_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_GSM_ERR_RESP_ENABLE_MASK (0x20000000u) #define CSL_SRIO_ERR_EN_GSM_ERR_RESP_ENABLE_SHIFT (0x0000001Du) #define CSL_SRIO_ERR_EN_GSM_ERR_RESP_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_ERR_MSG_FORMAT_ENABLE_MASK (0x10000000u) #define CSL_SRIO_ERR_EN_ERR_MSG_FORMAT_ENABLE_SHIFT (0x0000001Cu) #define CSL_SRIO_ERR_EN_ERR_MSG_FORMAT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_ILL_TRANS_DECODE_ENABLE_MASK (0x08000000u) #define CSL_SRIO_ERR_EN_ILL_TRANS_DECODE_ENABLE_SHIFT (0x0000001Bu) #define CSL_SRIO_ERR_EN_ILL_TRANS_DECODE_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_ILL_TRANS_TARGET_ERR_ENABLE_MASK (0x04000000u) #define CSL_SRIO_ERR_EN_ILL_TRANS_TARGET_ERR_ENABLE_SHIFT (0x0000001Au) #define CSL_SRIO_ERR_EN_ILL_TRANS_TARGET_ERR_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_MSG_REQ_TIMEOUT_ENABLE_MASK (0x02000000u) #define CSL_SRIO_ERR_EN_MSG_REQ_TIMEOUT_ENABLE_SHIFT (0x00000019u) #define CSL_SRIO_ERR_EN_MSG_REQ_TIMEOUT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_PKT_RESP_TIMEOUT_ENABLE_MASK (0x01000000u) #define CSL_SRIO_ERR_EN_PKT_RESP_TIMEOUT_ENABLE_SHIFT (0x00000018u) #define CSL_SRIO_ERR_EN_PKT_RESP_TIMEOUT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_UNSOLICITED_RESP_ENABLE_MASK (0x00800000u) #define CSL_SRIO_ERR_EN_UNSOLICITED_RESP_ENABLE_SHIFT (0x00000017u) #define CSL_SRIO_ERR_EN_UNSOLICITED_RESP_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_UNSUPPORTED_TRANS_ENABLE_MASK (0x00400000u) #define CSL_SRIO_ERR_EN_UNSUPPORTED_TRANS_ENABLE_SHIFT (0x00000016u) #define CSL_SRIO_ERR_EN_UNSUPPORTED_TRANS_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_RX_CPPI_SECURITY_MASK (0x00000080u) #define CSL_SRIO_ERR_EN_RX_CPPI_SECURITY_SHIFT (0x00000007u) #define CSL_SRIO_ERR_EN_RX_CPPI_SECURITY_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_RX_IO_SECURITY_MASK (0x00000040u) #define CSL_SRIO_ERR_EN_RX_IO_SECURITY_SHIFT (0x00000006u) #define CSL_SRIO_ERR_EN_RX_IO_SECURITY_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_RESETVAL (0x00000000u) / H_ADDR_CAPT / #define CSL_SRIO_H_ADDR_CAPT_ADDRESS_63_32_MASK (0xFFFFFFFFu) #define CSL_SRIO_H_ADDR_CAPT_ADDRESS_63_32_SHIFT (0x00000000u) #define CSL_SRIO_H_ADDR_CAPT_ADDRESS_63_32_RESETVAL (0x00000000u) #define CSL_SRIO_H_ADDR_CAPT_RESETVAL (0x00000000u) / ADDR_CAPT / #define CSL_SRIO_ADDR_CAPT_ADDRESS_31_3_MASK (0xFFFFFFF8u) #define CSL_SRIO_ADDR_CAPT_ADDRESS_31_3_SHIFT (0x00000003u) #define CSL_SRIO_ADDR_CAPT_ADDRESS_31_3_RESETVAL (0x00000000u) #define CSL_SRIO_ADDR_CAPT_XAMSBS_MASK (0x00000003u) #define CSL_SRIO_ADDR_CAPT_XAMSBS_SHIFT (0x00000000u) #define CSL_SRIO_ADDR_CAPT_XAMSBS_RESETVAL (0x00000000u) #define CSL_SRIO_ADDR_CAPT_RESETVAL (0x00000000u) / ID_CAPT / #define CSL_SRIO_ID_CAPT_MSB_DESTID_MASK (0xFF000000u) #define CSL_SRIO_ID_CAPT_MSB_DESTID_SHIFT (0x00000018u) #define CSL_SRIO_ID_CAPT_MSB_DESTID_RESETVAL (0x00000000u) #define CSL_SRIO_ID_CAPT_DESTID_MASK (0x00FF0000u) #define CSL_SRIO_ID_CAPT_DESTID_SHIFT (0x00000010u) #define CSL_SRIO_ID_CAPT_DESTID_RESETVAL (0x00000000u) #define CSL_SRIO_ID_CAPT_MSB_SOURCEID_MASK (0x0000FF00u) #define CSL_SRIO_ID_CAPT_MSB_SOURCEID_SHIFT (0x00000008u) #define CSL_SRIO_ID_CAPT_MSB_SOURCEID_RESETVAL (0x00000000u) #define CSL_SRIO_ID_CAPT_SOURCEID_MASK (0x000000FFu) #define CSL_SRIO_ID_CAPT_SOURCEID_SHIFT (0x00000000u) #define CSL_SRIO_ID_CAPT_SOURCEID_RESETVAL (0x00000000u) #define CSL_SRIO_ID_CAPT_RESETVAL (0x00000000u) / CTRL_CAPT / #define CSL_SRIO_CTRL_CAPT_FTYPE_MASK (0xF0000000u) #define CSL_SRIO_CTRL_CAPT_FTYPE_SHIFT (0x0000001Cu) #define CSL_SRIO_CTRL_CAPT_FTYPE_RESETVAL (0x00000000u) #define CSL_SRIO_CTRL_CAPT_TTYPE_MASK (0x0F000000u) #define CSL_SRIO_CTRL_CAPT_TTYPE_SHIFT (0x00000018u) #define CSL_SRIO_CTRL_CAPT_TTYPE_RESETVAL (0x00000000u) #define CSL_SRIO_CTRL_CAPT_MSGINFO_MASK (0x00FF0000u) #define CSL_SRIO_CTRL_CAPT_MSGINFO_SHIFT (0x00000010u) #define CSL_SRIO_CTRL_CAPT_MSGINFO_RESETVAL (0x00000000u) #define CSL_SRIO_CTRL_CAPT_IMP_SPECIFIC_MASK (0x0000FFFFu) #define CSL_SRIO_CTRL_CAPT_IMP_SPECIFIC_SHIFT (0x00000000u) #define CSL_SRIO_CTRL_CAPT_IMP_SPECIFIC_RESETVAL (0x00000000u) #define CSL_SRIO_CTRL_CAPT_RESETVAL (0x00000000u) / PW_TGT_ID / #define CSL_SRIO_PW_TGT_ID_DEVICEID_MSB_MASK (0xFF000000u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_MSB_SHIFT (0x00000018u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_MSB_RESETVAL (0x00000000u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_MASK (0x00FF0000u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_SHIFT (0x00000010u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_RESETVAL (0x00000000u) #define CSL_SRIO_PW_TGT_ID_RESETVAL (0x00000000u) / SP_ERR_DET / #define CSL_SRIO_SP_ERR_DET_ERR_IMP_SPECIFIC_MASK (0x80000000u) #define CSL_SRIO_SP_ERR_DET_ERR_IMP_SPECIFIC_SHIFT (0x0000001Fu) #define CSL_SRIO_SP_ERR_DET_ERR_IMP_SPECIFIC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_CORRUPT_CNTL_SYM_MASK (0x00400000u) #define CSL_SRIO_SP_ERR_DET_CORRUPT_CNTL_SYM_SHIFT (0x00000016u) #define CSL_SRIO_SP_ERR_DET_CORRUPT_CNTL_SYM_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_CNTL_SYM_UNEXPECTED_ACKID_MASK (0x00200000u) #define CSL_SRIO_SP_ERR_DET_CNTL_SYM_UNEXPECTED_ACKID_SHIFT (0x00000015u) #define CSL_SRIO_SP_ERR_DET_CNTL_SYM_UNEXPECTED_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_NOT_ACCPT_MASK (0x00100000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_NOT_ACCPT_SHIFT (0x00000014u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_NOT_ACCPT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_PKT_UNEXPECTED_ACKID_MASK (0x00080000u) #define CSL_SRIO_SP_ERR_DET_PKT_UNEXPECTED_ACKID_SHIFT (0x00000013u) #define CSL_SRIO_SP_ERR_DET_PKT_UNEXPECTED_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_WITH_BAD_CRC_MASK (0x00040000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_WITH_BAD_CRC_SHIFT (0x00000012u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_WITH_BAD_CRC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_OVER_276B_MASK (0x00020000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_OVER_276B_SHIFT (0x00000011u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_OVER_276B_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_NON_OUTSTANDING_ACKID_MASK (0x00000020u) #define CSL_SRIO_SP_ERR_DET_NON_OUTSTANDING_ACKID_SHIFT (0x00000005u) #define CSL_SRIO_SP_ERR_DET_NON_OUTSTANDING_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_PROTOCOL_ERROR_MASK (0x00000010u) #define CSL_SRIO_SP_ERR_DET_PROTOCOL_ERROR_SHIFT (0x00000004u) #define CSL_SRIO_SP_ERR_DET_PROTOCOL_ERROR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_DELINEATION_ERROR_MASK (0x00000004u) #define CSL_SRIO_SP_ERR_DET_DELINEATION_ERROR_SHIFT (0x00000002u) #define CSL_SRIO_SP_ERR_DET_DELINEATION_ERROR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_UNSOLICITED_ACK_CNTL_SYM_MASK (0x00000002u) #define CSL_SRIO_SP_ERR_DET_UNSOLICITED_ACK_CNTL_SYM_SHIFT (0x00000001u) #define CSL_SRIO_SP_ERR_DET_UNSOLICITED_ACK_CNTL_SYM_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_LINK_TIMEOUT_MASK (0x00000001u) #define CSL_SRIO_SP_ERR_DET_LINK_TIMEOUT_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_DET_LINK_TIMEOUT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_RESETVAL (0x00000000u) / SP_RATE_EN / #define CSL_SRIO_SP_RATE_EN_EN_IMP_SPECIFIC_MASK (0x80000000u) #define CSL_SRIO_SP_RATE_EN_EN_IMP_SPECIFIC_SHIFT (0x0000001Fu) #define CSL_SRIO_SP_RATE_EN_EN_IMP_SPECIFIC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_CORRUPT_CNTL_SYM_ENABLE_MASK (0x00400000u) #define CSL_SRIO_SP_RATE_EN_CORRUPT_CNTL_SYM_ENABLE_SHIFT (0x00000016u) #define CSL_SRIO_SP_RATE_EN_CORRUPT_CNTL_SYM_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_CNTL_SYM_UNEXPECTED_ACKID_EN_MASK (0x00200000u) #define CSL_SRIO_SP_RATE_EN_CNTL_SYM_UNEXPECTED_ACKID_EN_SHIFT (0x00000015u) #define CSL_SRIO_SP_RATE_EN_CNTL_SYM_UNEXPECTED_ACKID_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_NOT_ACCPT_EN_MASK (0x00100000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_NOT_ACCPT_EN_SHIFT (0x00000014u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_NOT_ACCPT_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_PKT_UNEXPECTED_ACKID_EN_MASK (0x00080000u) #define CSL_SRIO_SP_RATE_EN_PKT_UNEXPECTED_ACKID_EN_SHIFT (0x00000013u) #define CSL_SRIO_SP_RATE_EN_PKT_UNEXPECTED_ACKID_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_WITH_BAD_CRC_EN_MASK (0x00040000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_WITH_BAD_CRC_EN_SHIFT (0x00000012u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_WITH_BAD_CRC_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_OVER_276B_EN_MASK (0x00020000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_OVER_276B_EN_SHIFT (0x00000011u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_OVER_276B_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_NON_OUTSTANDING_ACKID_EN_MASK (0x00000020u) #define CSL_SRIO_SP_RATE_EN_NON_OUTSTANDING_ACKID_EN_SHIFT (0x00000005u) #define CSL_SRIO_SP_RATE_EN_NON_OUTSTANDING_ACKID_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_PROTOCOL_ERROR_EN_MASK (0x00000010u) #define CSL_SRIO_SP_RATE_EN_PROTOCOL_ERROR_EN_SHIFT (0x00000004u) #define CSL_SRIO_SP_RATE_EN_PROTOCOL_ERROR_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_DELINEATION_ERROR_EN_MASK (0x00000004u) #define CSL_SRIO_SP_RATE_EN_DELINEATION_ERROR_EN_SHIFT (0x00000002u) #define CSL_SRIO_SP_RATE_EN_DELINEATION_ERROR_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_UNSOLICITED_ACK_CNTL_SYM_EN_MASK (0x00000002u) #define CSL_SRIO_SP_RATE_EN_UNSOLICITED_ACK_CNTL_SYM_EN_SHIFT (0x00000001u) #define CSL_SRIO_SP_RATE_EN_UNSOLICITED_ACK_CNTL_SYM_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_LINK_TIMEOUT_EN_MASK (0x00000001u) #define CSL_SRIO_SP_RATE_EN_LINK_TIMEOUT_EN_SHIFT (0x00000000u) #define CSL_SRIO_SP_RATE_EN_LINK_TIMEOUT_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_RESETVAL (0x00000000u) / SP_ERR_ATTR_CAPT_DBG0 / #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_INFO_TYPE_MASK (0xC0000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_INFO_TYPE_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_INFO_TYPE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_ERROR_TYPE_MASK (0x1F000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_ERROR_TYPE_SHIFT (0x00000018u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_ERROR_TYPE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_IMP_SPECIFIC_MASK (0x00FFFFF0u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_IMP_SPECIFIC_SHIFT (0x00000004u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_IMP_SPECIFIC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_CAPTURE_VALID_INFO_MASK (0x00000001u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_CAPTURE_VALID_INFO_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_CAPTURE_VALID_INFO_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_RESETVAL (0x00000000u) / SP_ERR_CAPT_DBG / #define CSL_SRIO_SP_ERR_CAPT_DBG_CAPTURE_MASK (0xFFFFFFFFu) #define CSL_SRIO_SP_ERR_CAPT_DBG_CAPTURE_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_CAPT_DBG_CAPTURE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_CAPT_DBG_RESETVAL (0x00000000u) / SP_ERR_RATE / #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_BIAS_MASK (0xFF000000u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_BIAS_SHIFT (0x00000018u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_BIAS_RESETVAL (0x000000FFu) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY_MASK (0x00030000u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY_SHIFT (0x00000010u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_RATE_PEAK_ERROR_RATE_MASK (0x0000FF00u) #define CSL_SRIO_SP_ERR_RATE_PEAK_ERROR_RATE_SHIFT (0x00000008u) #define CSL_SRIO_SP_ERR_RATE_PEAK_ERROR_RATE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_COUNTER_MASK (0x000000FFu) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_COUNTER_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_COUNTER_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_RATE_RESETVAL (0xFF000000u) / SP_ERR_THRESH / #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD_MASK (0xFF000000u) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD_SHIFT (0x00000018u) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD_RESETVAL (0x000000FFu) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES_MASK (0x00FF0000u) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES_SHIFT (0x00000010u) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES_RESETVAL (0x000000FFu) #define CSL_SRIO_SP_ERR_THRESH_RESETVAL (0xFFFF0000u) / SP_IP_DISCOVERY_TIMER / #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER_MASK (0xF0000000u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER_SHIFT (0x0000001Cu) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER_RESETVAL (0x00000009u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER_MASK (0x00F00000u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER_SHIFT (0x00000014u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER_RESETVAL (0x00000008u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_RESETVAL (0x90800000u) / SP_IP_MODE / #define CSL_SRIO_SP_IP_MODE_SP_MODE_MASK (0xC0000000u) #define CSL_SRIO_SP_IP_MODE_SP_MODE_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_IP_MODE_SP_MODE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_MASK (0x20000000u) #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_SHIFT (0x0000001Du) #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_RESETVAL (0x00000000u) /----IDLE_ERR_DIS Tokens----/ #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_DISABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_ENABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_MASK (0x10000000u) #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_SHIFT (0x0000001Cu) #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_RESETVAL (0x00000000u) /----TX_FIFO_BYPASS Tokens----/ #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_DIS_MASK (0x08000000u) #define CSL_SRIO_SP_IP_MODE_PW_DIS_SHIFT (0x0000001Bu) #define CSL_SRIO_SP_IP_MODE_PW_DIS_RESETVAL (0x00000000u) /----PW_DIS Tokens----/ #define CSL_SRIO_SP_IP_MODE_PW_DIS_DISABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_DIS_ENABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_TGT_ID_DIS_MASK (0x04000000u) #define CSL_SRIO_SP_IP_MODE_TGT_ID_DIS_SHIFT (0x0000001Au) #define CSL_SRIO_SP_IP_MODE_TGT_ID_DIS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_SELF_RST_MASK (0x02000000u) #define CSL_SRIO_SP_IP_MODE_SELF_RST_SHIFT (0x00000019u) #define CSL_SRIO_SP_IP_MODE_SELF_RST_RESETVAL (0x00000000u) /----SELF_RST Tokens----/ #define CSL_SRIO_SP_IP_MODE_SELF_RST_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_SELF_RST_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_MLTC_EN_MASK (0x00000020u) #define CSL_SRIO_SP_IP_MODE_MLTC_EN_SHIFT (0x00000005u) #define CSL_SRIO_SP_IP_MODE_MLTC_EN_RESETVAL (0x00000000u) /----MLTC_EN Tokens----/ #define CSL_SRIO_SP_IP_MODE_MLTC_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_MLTC_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_MLTC_IRQ_MASK (0x00000010u) #define CSL_SRIO_SP_IP_MODE_MLTC_IRQ_SHIFT (0x00000004u) #define CSL_SRIO_SP_IP_MODE_MLTC_IRQ_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_RST_EN_MASK (0x00000008u) #define CSL_SRIO_SP_IP_MODE_RST_EN_SHIFT (0x00000003u) #define CSL_SRIO_SP_IP_MODE_RST_EN_RESETVAL (0x00000000u) /----RST_EN Tokens----/ #define CSL_SRIO_SP_IP_MODE_RST_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_RST_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_RST_CS_MASK (0x00000004u) #define CSL_SRIO_SP_IP_MODE_RST_CS_SHIFT (0x00000002u) #define CSL_SRIO_SP_IP_MODE_RST_CS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_PW_EN_MASK (0x00000002u) #define CSL_SRIO_SP_IP_MODE_PW_EN_SHIFT (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_EN_RESETVAL (0x00000000u) /----PW_EN Tokens----/ #define CSL_SRIO_SP_IP_MODE_PW_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_PW_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_IRQ_MASK (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_IRQ_SHIFT (0x00000000u) #define CSL_SRIO_SP_IP_MODE_PW_IRQ_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_RESETVAL (0x00000000u) / IP_PRESCAL / #define CSL_SRIO_IP_PRESCAL_PRESCALE_MASK (0x000000FFu) #define CSL_SRIO_IP_PRESCAL_PRESCALE_SHIFT (0x00000000u) #define CSL_SRIO_IP_PRESCAL_PRESCALE_RESETVAL (0x0000000Fu) #define CSL_SRIO_IP_PRESCAL_RESETVAL (0x0000000Fu) / SP_IP_PW_IN_CAPT / #define CSL_SRIO_SP_IP_PW_IN_CAPT_PW_CAPT_MASK (0xFFFFFFFFu) #define CSL_SRIO_SP_IP_PW_IN_CAPT_PW_CAPT_SHIFT (0x00000000u) #define CSL_SRIO_SP_IP_PW_IN_CAPT_PW_CAPT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_PW_IN_CAPT_RESETVAL (0x00000000u) / SP_RST_OPT / #define CSL_SRIO_SP_RST_OPT_PORT_ID_MASK (0x000000FFu) #define CSL_SRIO_SP_RST_OPT_PORT_ID_SHIFT (0x00000000u) #define CSL_SRIO_SP_RST_OPT_PORT_ID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RST_OPT_RESETVAL (0x00000000u) / SP_CTL_INDEP / #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_MASK (0x40000000u) #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_RESETVAL (0x00000000u) /----TX_FLW Tokens----/ #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_ENABLE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_MASK (0x20000000u) #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_SHIFT (0x0000001Du) #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_RESETVAL (0x00000000u) /----SOFT_REC Tokens----/ #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_BYHARDWARE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_BYSOFTWARE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_FORCE_REINIT_MASK (0x04000000u) #define CSL_SRIO_SP_CTL_INDEP_FORCE_REINIT_SHIFT (0x0000001Au) #define CSL_SRIO_SP_CTL_INDEP_FORCE_REINIT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_TRANS_MODE_MASK (0x03000000u) #define CSL_SRIO_SP_CTL_INDEP_TRANS_MODE_SHIFT (0x00000018u) #define CSL_SRIO_SP_CTL_INDEP_TRANS_MODE_RESETVAL (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_DEBUG_MASK (0x00800000u) #define CSL_SRIO_SP_CTL_INDEP_DEBUG_SHIFT (0x00000017u) #define CSL_SRIO_SP_CTL_INDEP_DEBUG_RESETVAL (0x00000000u) /----DEBUG Tokens----/ #define CSL_SRIO_SP_CTL_INDEP_DEBUG_NORMAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_DEBUG_DEBUG (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_SEND_DBG_PKT_MASK (0x00400000u) #define CSL_SRIO_SP_CTL_INDEP_SEND_DBG_PKT_SHIFT (0x00000016u) #define CSL_SRIO_SP_CTL_INDEP_SEND_DBG_PKT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_MASK (0x00200000u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_SHIFT (0x00000015u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_RESETVAL (0x00000000u) /----ILL_TRANS_EN Tokens----/ #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_ERR_MASK (0x00100000u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_ERR_SHIFT (0x00000014u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_ERR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_MASK (0x00020000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_SHIFT (0x00000011u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_RESETVAL (0x00000000u) /----MAX_RETRY_EN Tokens----/ #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_ERR_MASK (0x00010000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_ERR_SHIFT (0x00000010u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_ERR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_THR_MASK (0x0000FF00u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_THR_SHIFT (0x00000008u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_THR_RESETVAL (0x00000000u) /----MAX_RETRY_THR Tokens----/ #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_THR_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_MASK (0x00000080u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_SHIFT (0x00000007u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_RESETVAL (0x00000000u) /----IRQ_EN Tokens----/ #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_ERR_MASK (0x00000040u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_ERR_SHIFT (0x00000006u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_ERR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_RESETVAL (0x01000000u) / SP_SILENCE_TIMER / #define CSL_SRIO_SP_SILENCE_TIMER_SILENCE_TIMER_MASK (0xF0000000u) #define CSL_SRIO_SP_SILENCE_TIMER_SILENCE_TIMER_SHIFT (0x0000001Cu) #define CSL_SRIO_SP_SILENCE_TIMER_SILENCE_TIMER_RESETVAL (0x0000000Bu) #define CSL_SRIO_SP_SILENCE_TIMER_RESETVAL (0xB0000000u) / SP_MULT_EVNT_CS / #define CSL_SRIO_SP_MULT_EVNT_CS_MULT_EVNT_CS_MASK (0xFFFFFFFFu) #define CSL_SRIO_SP_MULT_EVNT_CS_MULT_EVNT_CS_SHIFT (0x00000000u) #define CSL_SRIO_SP_MULT_EVNT_CS_MULT_EVNT_CS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_MULT_EVNT_CS_RESETVAL (0x00000000u) / SP_CS_TX / #define CSL_SRIO_SP_CS_TX_STYPE_0_MASK (0xE0000000u) #define CSL_SRIO_SP_CS_TX_STYPE_0_SHIFT (0x0000001Du) #define CSL_SRIO_SP_CS_TX_STYPE_0_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_PAR_0_MASK (0x1F000000u) #define CSL_SRIO_SP_CS_TX_PAR_0_SHIFT (0x00000018u) #define CSL_SRIO_SP_CS_TX_PAR_0_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_PAR_1_MASK (0x00F80000u) #define CSL_SRIO_SP_CS_TX_PAR_1_SHIFT (0x00000013u) #define CSL_SRIO_SP_CS_TX_PAR_1_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_STYPE_1_MASK (0x00070000u) #define CSL_SRIO_SP_CS_TX_STYPE_1_SHIFT (0x00000010u) #define CSL_SRIO_SP_CS_TX_STYPE_1_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_CMD_MASK (0x0000E000u) #define CSL_SRIO_SP_CS_TX_CMD_SHIFT (0x0000000Du) #define CSL_SRIO_SP_CS_TX_CMD_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_CS_EMB_MASK (0x00001000u) #define CSL_SRIO_SP_CS_TX_CS_EMB_SHIFT (0x0000000Cu) #define CSL_SRIO_SP_CS_TX_CS_EMB_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_RESETVAL (0x00000000u) /************************************************************************\ Field Definition Macros for Tx Buffer Descriptor \*************************************************************************/ / TXBUFFDESC (for opt1) / #define CSL_SRIO_TXBUFFDESC_DEST_ID_MASK (0xFFFF0000u) #define CSL_SRIO_TXBUFFDESC_DEST_ID_SHIFT (0x00000010u) #define CSL_SRIO_TXBUFFDESC_DEST_ID_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_PRI_MASK (0x0000C000u) #define CSL_SRIO_TXBUFFDESC_PRI_SHIFT (0x0000000Eu) #define CSL_SRIO_TXBUFFDESC_PRI_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_TT_MASK (0x00003000u) #define CSL_SRIO_TXBUFFDESC_TT_SHIFT (0x0000000Cu) #define CSL_SRIO_TXBUFFDESC_TT_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_PORT_ID_MASK (0x00000C00u) #define CSL_SRIO_TXBUFFDESC_PORT_ID_SHIFT (0x0000000Au) #define CSL_SRIO_TXBUFFDESC_PORT_ID_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_SSIZE_MASK (0x000003C0u) #define CSL_SRIO_TXBUFFDESC_SSIZE_SHIFT (0x00000006u) #define CSL_SRIO_TXBUFFDESC_SSIZE_RESETVAL (0x00000000u) /----SSIZE Tokens----/ #define CSL_SRIO_TXBUFFDESC_SSIZE_128B (0x00000009u) #define CSL_SRIO_TXBUFFDESC_SSIZE_256B (0x0000000Au) #define CSL_SRIO_TXBUFFDESC_SSIZE_512B (0x0000000Bu) #define CSL_SRIO_TXBUFFDESC_SSIZE_1024B (0x0000000Cu) #define CSL_SRIO_TXBUFFDESC_SSIZE_2048B (0x0000000Du) #define CSL_SRIO_TXBUFFDESC_SSIZE_4096B (0x0000000Eu) #define CSL_SRIO_TXBUFFDESC_MAILBOX_MASK (0x0000003Fu) #define CSL_SRIO_TXBUFFDESC_MAILBOX_SHIFT (0x00000000u) #define CSL_SRIO_TXBUFFDESC_MAILBOX_RESETVAL (0x00000000u) / TXBUFFDESC (for opt2) / #define CSL_SRIO_TXBUFFDESC_SOP_MASK (0x80000000u) #define CSL_SRIO_TXBUFFDESC_SOP_SHIFT (0x0000001Fu) #define CSL_SRIO_TXBUFFDESC_SOP_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_EOP_MASK (0x40000000u) #define CSL_SRIO_TXBUFFDESC_EOP_SHIFT (0x0000001Eu) #define CSL_SRIO_TXBUFFDESC_EOP_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_MASK (0x20000000u) #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_SHIFT (0x0000001Du) #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_RESETVAL (0x00000000u) /----OWNERSHIP Tokens----/ #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_HOST (0x00000000u) #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_PORT (0x00000001u) #define CSL_SRIO_TXBUFFDESC_EOQ_MASK (0x10000000u) #define CSL_SRIO_TXBUFFDESC_EOQ_SHIFT (0x0000001Cu) #define CSL_SRIO_TXBUFFDESC_EOQ_RESETVAL (0x00000000u) /----EOQ Tokens----/ #define CSL_SRIO_TXBUFFDESC_EOQ_TRUE (0x00000001u) #define CSL_SRIO_TXBUFFDESC_EOQ_FALSE (0x00000000u) #define CSL_SRIO_TXBUFFDESC_TEARDOWN_MASK (0x08000000u) #define CSL_SRIO_TXBUFFDESC_TEARDOWN_SHIFT (0x0000001Bu) #define CSL_SRIO_TXBUFFDESC_TEARDOWN_RESETVAL (0x00000000u) /----TEARDOWN Tokens----/ #define CSL_SRIO_TXBUFFDESC_TEARDOWN_NOT_COMPLETE (0x00000000u) #define CSL_SRIO_TXBUFFDESC_TEARDOWN_COMPLETE (0x00000001u) #define CSL_SRIO_TXBUFFDESC_RESERVED_MASK (0x07FC0000u) #define CSL_SRIO_TXBUFFDESC_RESERVED_SHIFT (0x00000012u) #define CSL_SRIO_TXBUFFDESC_RESERVED_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_RETRY_COUNT_MASK (0x0003F000u) #define CSL_SRIO_TXBUFFDESC_RETRY_COUNT_SHIFT (0x0000000Cu) #define CSL_SRIO_TXBUFFDESC_RETRY_COUNT_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_CC_MASK (0x00000E00u) #define CSL_SRIO_TXBUFFDESC_CC_SHIFT (0x00000009u) #define CSL_SRIO_TXBUFFDESC_CC_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_MESSAGE_LENGTH_MASK (0x000001FFu) #define CSL_SRIO_TXBUFFDESC_MESSAGE_LENGTH_SHIFT (0x00000000u) #define CSL_SRIO_TXBUFFDESC_MESSAGE_LENGTH_RESETVAL (0x00000000u) /************************************************************************\ Field Definition Macros for Rx Buffer Descriptor \*************************************************************************/ / RXBUFFDESC (for opt1) / #define CSL_SRIO_RXBUFFDESC_SRC_ID_MASK (0xFFFF0000u) #define CSL_SRIO_RXBUFFDESC_SRC_ID_SHIFT (0x00000010u) #define CSL_SRIO_RXBUFFDESC_SRC_ID_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_PRI_MASK (0x0000C000u) #define CSL_SRIO_RXBUFFDESC_PRI_SHIFT (0x0000000Eu) #define CSL_SRIO_RXBUFFDESC_PRI_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_TT_MASK (0x00003000u) #define CSL_SRIO_RXBUFFDESC_TT_SHIFT (0x0000000Cu) #define CSL_SRIO_RXBUFFDESC_TT_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_MAILBOX_MASK (0x0000003Fu) #define CSL_SRIO_RXBUFFDESC_MAILBOX_SHIFT (0x00000000u) #define CSL_SRIO_RXBUFFDESC_MAILBOX_RESETVAL (0x00000000u) / RXBUFFDESC (option 2) / #define CSL_SRIO_RXBUFFDESC_SOP_MASK (0x80000000u) #define CSL_SRIO_RXBUFFDESC_SOP_SHIFT (0x0000001Fu) #define CSL_SRIO_RXBUFFDESC_SOP_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_EOP_MASK (0x40000000u) #define CSL_SRIO_RXBUFFDESC_EOP_SHIFT (0x0000001Eu) #define CSL_SRIO_RXBUFFDESC_EOP_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_MASK (0x20000000u) #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_SHIFT (0x0000001Du) #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_RESETVAL (0x00000000u) /----OWNERSHIP Tokens----/ #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_HOST (0x00000000u) #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_PORT (0x00000001u) #define CSL_SRIO_RXBUFFDESC_EOQ_MASK (0x10000000u) #define CSL_SRIO_RXBUFFDESC_EOQ_SHIFT (0x0000001Cu) #define CSL_SRIO_RXBUFFDESC_EOQ_RESETVAL (0x00000000u) /----EOQ Tokens----/ #define CSL_SRIO_RXBUFFDESC_EOQ_TRUE (0x00000001u) #define CSL_SRIO_RXBUFFDESC_EOQ_FALSE (0x00000000u) #define CSL_SRIO_RXBUFFDESC_TEARDOWN_MASK (0x08000000u) #define CSL_SRIO_RXBUFFDESC_TEARDOWN_SHIFT (0x0000001Bu) #define CSL_SRIO_RXBUFFDESC_TEARDOWN_RESETVAL (0x00000000u) /----TEARDOWN Tokens----*/ #define CSL_SRIO_RXBUFFDESC_TEARDOWN_NOT_COMPLETE (0x00000000u) #define CSL_SRIO_RXBUFFDESC_TEARDOWN_COMPLETE (0x00000001u) #define CSL_SRIO_RXBUFFDESC_CC_MASK (0x00000E00u) #define CSL_SRIO_RXBUFFDESC_CC_SHIFT (0x00000009u) #define CSL_SRIO_RXBUFFDESC_CC_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_MESSAGE_LENGTH_MASK (0x000001FFu) #define CSL_SRIO_RXBUFFDESC_MESSAGE_LENGTH_SHIFT (0x00000000u) #define CSL_SRIO_RXBUFFDESC_MESSAGE_LENGTH_RESETVAL (0x00000000u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/src/intc/_csl_intcCombEventDispatcher.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / / * @file _csl_intcCombEventDispatcher.c * * @brief File for functional layer of CSL API _CSL_intcEvent0Dispatcher() * * PATH $(CSLPATH)\src\intc / / ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * ============================================================================= / #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> / ============================================================================ * @n@b _CSL_intcEvent0Dispatcher * * @b Description * @n Get the event source of the combiner interrupt0 * * @b Arguments * @n None * * <b> Return Value </b> * @li None * * * @b Example: * @verbatim CSL_IntcParam param; ... CSL_intcHookIsr(((CSL_IntcVectId)param),_CSL_intcEvent0Dispatcher); ... @endverbatim ============================================================================= / #pragma CODE_SECTION (_CSL_intcEvent0Dispatcher, ".text:csl_section:intc"); interrupt void _CSL_intcEvent0Dispatcher (void) { volatile CSL_BitMask32 evtRcv; Uint32 evtId; Uint32 evtMask ; evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[0]; while (evtRcv) { / Clear the events / ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[0] = evtRcv ; evtMask = 1 << 4; evtId = 4; evtRcv &= ~(0xF); do { if (evtRcv & evtMask) { if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE) _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].handler ( _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].arg ); evtRcv &= ~evtMask; } evtMask = evtMask << 1; evtId++; } while (evtRcv); / Read the MEVTFLAG[0] register / evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[0]; } } / ============================================================================ * @n@b _CSL_intcEvent1Dispatcher * * @b Description * @n Get the event source of the combiner interrupt1 * * @b Arguments * @n None * * <b> Return Value </b> * @li None * * * @b Example: * @verbatim CSL_IntcParam param; ... CSL_intcHookIsr(((CSL_IntcVectId)param),_CSL_intcEvent1Dispatcher); ... @endverbatim ============================================================================= / #pragma CODE_SECTION (_CSL_intcEvent1Dispatcher, ".text:csl_section:intc"); interrupt void _CSL_intcEvent1Dispatcher (void) { volatile CSL_BitMask32 evtRcv; Uint32 evtId; Uint32 evtMask ; / Read the MEVTFLAG[1] register / evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[1]; while (evtRcv) { / Clear the events / ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[1] = evtRcv ; evtId = 32; evtMask = 1; do { if (evtRcv & evtMask) { if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE) _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].handler ( _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].arg ); evtRcv &= ~evtMask; } evtMask = evtMask << 1; evtId++; } while (evtRcv); / Read the MEVTFLAG[1] register / evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[1]; } } / ============================================================================ * @n@b _CSL_intcEvent2Dispatcher * * @b Description * @n Get the event source of the combiner interrupt2 * * @b Arguments * @n None * * <b> Return Value </b> * @li None * * * @b Example: * @verbatim CSL_IntcParam param; ... CSL_intcHookIsr(((CSL_IntcVectId)param),_CSL_intcEvent2Dispatcher); ... @endverbatim ============================================================================= / #pragma CODE_SECTION (_CSL_intcEvent2Dispatcher, ".text:csl_section:intc"); interrupt void _CSL_intcEvent2Dispatcher (void) { volatile CSL_BitMask32 evtRcv; Uint32 evtId; Uint32 evtMask ; / Read the MEVTFLAG[2] register / evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[2]; while (evtRcv) { / Clear the events / ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[2] = evtRcv ; evtId = 64; evtMask = 1; do { if (evtRcv & evtMask) { if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE) _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].handler ( _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].arg ); evtRcv &= ~evtMask; } evtMask = evtMask << 1; evtId++; } while (evtRcv); / Read the MEVTFLAG[2] register / evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[2]; } } / ============================================================================ * @n@b _CSL_intcEvent3Dispatcher * * @b Description * @n Get the event source of the combiner interrupt3 * * @b Arguments * @n None * * <b> Return Value </b> * @li None * * * @b Example: * @verbatim CSL_IntcParam param; ... CSL_intcHookIsr(((CSL_IntcVectId)param),_CSL_intcEvent3Dispatcher); ... @endverbatim ============================================================================= / #pragma CODE_SECTION (_CSL_intcEvent3Dispatcher, ".text:csl_section:intc"); interrupt void _CSL_intcEvent3Dispatcher (void) { volatile CSL_BitMask32 evtRcv; Uint32 evtId; Uint32 evtMask ; / Read the MEVTFLAG[3] register / evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[3]; while (evtRcv) { / Clear the events / ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[3] = evtRcv ; evtId = 96; evtMask = 1; do { if (evtRcv & evtMask) { if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE) _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].handler ( _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].arg ); evtRcv &= ~evtMask; } evtMask = evtMask << 1; evtId++; } while (evtRcv); / Read the MEVTFLAG[3] register */ evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[3]; } }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_vcp2.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_vcp2.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for VCP2 / / ============================================================================= * Revision History * ================ * 23-March-2005 SPrasad File created. * * ============================================================================= / #ifndef _CSLR_VCP2_H_ #define _CSLR_VCP2_H_ #include <cslr.h> #include <tistdtypes.h> /* * Register Overlay Structure for registers accessible through Config bus / typedef struct { volatile Uint8 RSVD0[24]; volatile Uint32 VCPEXE; volatile Uint8 RSVD1[4]; volatile Uint32 VCPEND; volatile Uint8 RSVD2[28]; volatile Uint32 VCPSTAT0; volatile Uint32 VCPSTAT1; volatile Uint8 RSVD3[8]; volatile Uint32 VCPERR; volatile Uint8 RSVD4[12]; volatile Uint32 VCPEMU; } CSL_Vcp2ConfigRegs; /* * Register Overlay Structure for registers accessible through EDMA bus / typedef struct { volatile Uint32 VCPIC0; volatile Uint32 VCPIC1; volatile Uint32 VCPIC2; volatile Uint32 VCPIC3; volatile Uint32 VCPIC4; volatile Uint32 VCPIC5; volatile Uint8 RSVD0[48]; volatile Uint32 VCPOUT0; volatile Uint32 VCPOUT1; volatile Uint8 RSVD1[48]; volatile Uint32 VCPWBM; volatile Uint8 RSVD2[60]; volatile Uint32 VCPRDECS; } CSL_Vcp2EdmaRegs; /************************************************************************\ Field Definition Macros for registers accessible through config bus \*************************************************************************/ / VCPEXE / #define CSL_VCP2_VCPEXE_COMMAND_MASK (0x0000000Fu) #define CSL_VCP2_VCPEXE_COMMAND_SHIFT (0x00000000u) #define CSL_VCP2_VCPEXE_COMMAND_RESETVAL (0x00000000u) /----COMMAND Tokens----/ #define CSL_VCP2_VCPEXE_COMMAND_NOCMD (0x00000000u) #define CSL_VCP2_VCPEXE_COMMAND_START (0x00000001u) #define CSL_VCP2_VCPEXE_COMMAND_PAUSE (0x00000002u) #define CSL_VCP2_VCPEXE_COMMAND_RESTART_PAUSE (0x00000003u) #define CSL_VCP2_VCPEXE_COMMAND_RESTART (0x00000004u) #define CSL_VCP2_VCPEXE_COMMAND_STOP (0x00000005u) #define CSL_VCP2_VCPEXE_RESETVAL (0x00000000u) / VCPEND / #define CSL_VCP2_VCPEND_SLPZVSS_EN_MASK (0x00000200u) #define CSL_VCP2_VCPEND_SLPZVSS_EN_SHIFT (0x00000009u) #define CSL_VCP2_VCPEND_SLPZVSS_EN_RESETVAL (0x00000001u) /----SLPZVSS_EN Tokens----/ #define CSL_VCP2_VCPEND_SLPZVSS_EN_SLEEP_DIS (0x00000000u) #define CSL_VCP2_VCPEND_SLPZVSS_EN_SLPVSS_EN (0x00000001u) #define CSL_VCP2_VCPEND_SLPZVDD_EN_MASK (0x00000100u) #define CSL_VCP2_VCPEND_SLPZVDD_EN_SHIFT (0x00000008u) #define CSL_VCP2_VCPEND_SLPZVDD_EN_RESETVAL (0x00000001u) /----SLPZVDD_EN Tokens----/ #define CSL_VCP2_VCPEND_SLPZVDD_EN_SLEEP_DIS (0x00000000u) #define CSL_VCP2_VCPEND_SLPZVDD_EN_SLPVDD_EN (0x00000001u) #define CSL_VCP2_VCPEND_SD_MASK (0x00000002u) #define CSL_VCP2_VCPEND_SD_SHIFT (0x00000001u) #define CSL_VCP2_VCPEND_SD_RESETVAL (0x00000000u) /----SD Tokens----/ #define CSL_VCP2_VCPEND_SD_32BIT (0x00000000u) #define CSL_VCP2_VCPEND_SD_NATIVE (0x00000001u) #define CSL_VCP2_VCPEND_BM_MASK (0x00000001u) #define CSL_VCP2_VCPEND_BM_SHIFT (0x00000000u) #define CSL_VCP2_VCPEND_BM_RESETVAL (0x00000000u) /----BM Tokens----/ #define CSL_VCP2_VCPEND_BM_32BIT (0x00000000u) #define CSL_VCP2_VCPEND_BM_NATIVE (0x00000001u) #define CSL_VCP2_VCPEND_RESETVAL (0x00000300u) / VCPSTAT0 / #define CSL_VCP2_VCPSTAT0_NSYMPROC_MASK (0x1FFFF000u) #define CSL_VCP2_VCPSTAT0_NSYMPROC_SHIFT (0x0000000Cu) #define CSL_VCP2_VCPSTAT0_NSYMPROC_RESETVAL (0x00000000u) #define CSL_VCP2_VCPSTAT0_EMUHALT_MASK (0x00000040u) #define CSL_VCP2_VCPSTAT0_EMUHALT_SHIFT (0x00000006u) #define CSL_VCP2_VCPSTAT0_EMUHALT_RESETVAL (0x00000000u) /----EMUHALT Tokens----/ #define CSL_VCP2_VCPSTAT0_EMUHALT_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_EMUHALT_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_OFFUL_MASK (0x00000020u) #define CSL_VCP2_VCPSTAT0_OFFUL_SHIFT (0x00000005u) #define CSL_VCP2_VCPSTAT0_OFFUL_RESETVAL (0x00000000u) /----OFFUL Tokens----/ #define CSL_VCP2_VCPSTAT0_OFFUL_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_OFFUL_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_IFEMP_MASK (0x00000010u) #define CSL_VCP2_VCPSTAT0_IFEMP_SHIFT (0x00000004u) #define CSL_VCP2_VCPSTAT0_IFEMP_RESETVAL (0x00000000u) /----IFEMP Tokens----/ #define CSL_VCP2_VCPSTAT0_IFEMP_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_IFEMP_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_WIC_MASK (0x00000008u) #define CSL_VCP2_VCPSTAT0_WIC_SHIFT (0x00000003u) #define CSL_VCP2_VCPSTAT0_WIC_RESETVAL (0x00000000u) /----WIC Tokens----/ #define CSL_VCP2_VCPSTAT0_WIC_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_WIC_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_ERR_MASK (0x00000004u) #define CSL_VCP2_VCPSTAT0_ERR_SHIFT (0x00000002u) #define CSL_VCP2_VCPSTAT0_ERR_RESETVAL (0x00000000u) /----ERR Tokens----/ #define CSL_VCP2_VCPSTAT0_ERR_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_ERR_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_RUN_MASK (0x00000002u) #define CSL_VCP2_VCPSTAT0_RUN_SHIFT (0x00000001u) #define CSL_VCP2_VCPSTAT0_RUN_RESETVAL (0x00000000u) /----RUN Tokens----/ #define CSL_VCP2_VCPSTAT0_RUN_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_RUN_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_PAUSE_MASK (0x00000001u) #define CSL_VCP2_VCPSTAT0_PAUSE_SHIFT (0x00000000u) #define CSL_VCP2_VCPSTAT0_PAUSE_RESETVAL (0x00000000u) /----PAUSE Tokens----/ #define CSL_VCP2_VCPSTAT0_PAUSE_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_PAUSE_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_RESETVAL (0x00000000u) / VCPSTAT1 / #define CSL_VCP2_VCPSTAT1_NSYMOF_MASK (0xFFFF0000u) #define CSL_VCP2_VCPSTAT1_NSYMOF_SHIFT (0x00000010u) #define CSL_VCP2_VCPSTAT1_NSYMOF_RESETVAL (0x00000000u) #define CSL_VCP2_VCPSTAT1_NSYMIF_MASK (0x0000FFFFu) #define CSL_VCP2_VCPSTAT1_NSYMIF_SHIFT (0x00000000u) #define CSL_VCP2_VCPSTAT1_NSYMIF_RESETVAL (0x00000000u) #define CSL_VCP2_VCPSTAT1_RESETVAL (0x00000000u) / VCPERR / #define CSL_VCP2_VCPERR_E_SYMR_MASK (0x00000040u) #define CSL_VCP2_VCPERR_E_SYMR_SHIFT (0x00000006u) #define CSL_VCP2_VCPERR_E_SYMR_RESETVAL (0x00000000u) /----E_SYMR Tokens----/ #define CSL_VCP2_VCPERR_E_SYMR_NO (0x00000000u) #define CSL_VCP2_VCPERR_E_SYMR_YES (0x00000001u) #define CSL_VCP2_VCPERR_E_SYMX_MASK (0x00000020u) #define CSL_VCP2_VCPERR_E_SYMX_SHIFT (0x00000005u) #define CSL_VCP2_VCPERR_E_SYMX_RESETVAL (0x00000000u) /----E_SYMX Tokens----/ #define CSL_VCP2_VCPERR_E_SYMX_NO (0x00000000u) #define CSL_VCP2_VCPERR_E_SYMX_YES (0x00000001u) #define CSL_VCP2_VCPERR_MAXMINERR_MASK (0x00000010u) #define CSL_VCP2_VCPERR_MAXMINERR_SHIFT (0x00000004u) #define CSL_VCP2_VCPERR_MAXMINERR_RESETVAL (0x00000000u) /----MAXMINERR Tokens----/ #define CSL_VCP2_VCPERR_MAXMINERR_NO (0x00000000u) #define CSL_VCP2_VCPERR_MAXMINERR_YES (0x00000001u) #define CSL_VCP2_VCPERR_FCTLERR_MASK (0x00000008u) #define CSL_VCP2_VCPERR_FCTLERR_SHIFT (0x00000003u) #define CSL_VCP2_VCPERR_FCTLERR_RESETVAL (0x00000000u) /----FCTLERR Tokens----/ #define CSL_VCP2_VCPERR_FCTLERR_NO (0x00000000u) #define CSL_VCP2_VCPERR_FCTLERR_YES (0x00000001u) #define CSL_VCP2_VCPERR_FTLERR_MASK (0x00000004u) #define CSL_VCP2_VCPERR_FTLERR_SHIFT (0x00000002u) #define CSL_VCP2_VCPERR_FTLERR_RESETVAL (0x00000000u) /----FTLERR Tokens----/ #define CSL_VCP2_VCPERR_FTLERR_NO (0x00000000u) #define CSL_VCP2_VCPERR_FTLERR_YES (0x00000001u) #define CSL_VCP2_VCPERR_TBNAERR_MASK (0x00000002u) #define CSL_VCP2_VCPERR_TBNAERR_SHIFT (0x00000001u) #define CSL_VCP2_VCPERR_TBNAERR_RESETVAL (0x00000000u) /----TBNAERR Tokens----/ #define CSL_VCP2_VCPERR_TBNAERR_NO (0x00000000u) #define CSL_VCP2_VCPERR_TBNAERR_YES (0x00000001u) #define CSL_VCP2_VCPERR_ERROR_MASK (0x00000001u) #define CSL_VCP2_VCPERR_ERROR_SHIFT (0x00000000u) #define CSL_VCP2_VCPERR_ERROR_RESETVAL (0x00000000u) /----ERROR Tokens----/ #define CSL_VCP2_VCPERR_ERROR_NO (0x00000000u) #define CSL_VCP2_VCPERR_ERROR_YES (0x00000001u) #define CSL_VCP2_VCPERR_RESETVAL (0x00000000u) / VCPEMU / #define CSL_VCP2_VCPEMU_SOFT_MASK (0x00000002u) #define CSL_VCP2_VCPEMU_SOFT_SHIFT (0x00000001u) #define CSL_VCP2_VCPEMU_SOFT_RESETVAL (0x00000000u) /----SOFT Tokens----/ #define CSL_VCP2_VCPEMU_SOFT_HALT_DEFAULT (0x00000000u) #define CSL_VCP2_VCPEMU_SOFT_HALT_FRAMEEND (0x00000001u) #define CSL_VCP2_VCPEMU_FREE_MASK (0x00000001u) #define CSL_VCP2_VCPEMU_FREE_SHIFT (0x00000000u) #define CSL_VCP2_VCPEMU_FREE_RESETVAL (0x00000000u) /----FREE Tokens----/ #define CSL_VCP2_VCPEMU_FREE_SOFT_EN (0x00000000u) #define CSL_VCP2_VCPEMU_FREE_FREE (0x00000001u) #define CSL_VCP2_VCPEMU_RESETVAL (0x00000000u) /************************************************************************\ Field Definition Macros for registers accessible through EDMA bus \*************************************************************************/ / VCPIC0 / #define CSL_VCP2_VCPIC0_POLY3_MASK (0xFF000000u) #define CSL_VCP2_VCPIC0_POLY3_SHIFT (0x00000018u) #define CSL_VCP2_VCPIC0_POLY3_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC0_POLY2_MASK (0x00FF0000u) #define CSL_VCP2_VCPIC0_POLY2_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC0_POLY2_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC0_POLY1_MASK (0x0000FF00u) #define CSL_VCP2_VCPIC0_POLY1_SHIFT (0x00000008u) #define CSL_VCP2_VCPIC0_POLY1_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC0_POLY0_MASK (0x000000FFu) #define CSL_VCP2_VCPIC0_POLY0_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC0_POLY0_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC0_RESETVAL (0x00000000u) / VCPIC1 / #define CSL_VCP2_VCPIC1_YAMEN_MASK (0x10000000u) #define CSL_VCP2_VCPIC1_YAMEN_SHIFT (0x0000001Cu) #define CSL_VCP2_VCPIC1_YAMEN_RESETVAL (0x00000000u) /----YAMEN Tokens----/ #define CSL_VCP2_VCPIC1_YAMEN_DISABLE (0x00000000u) #define CSL_VCP2_VCPIC1_YAMEN_ENABLE (0x00000001u) #define CSL_VCP2_VCPIC1_YAMT_MASK (0x0FFF0000u) #define CSL_VCP2_VCPIC1_YAMT_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC1_YAMT_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC1_RESETVAL (0x00000000u) / VCPIC2 / #define CSL_VCP2_VCPIC2_R_MASK (0xFFFF0000u) #define CSL_VCP2_VCPIC2_R_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC2_R_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC2_FL_MASK (0x0000FFFFu) #define CSL_VCP2_VCPIC2_FL_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC2_FL_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC2_RESETVAL (0x00000000u) / VCPIC3 / #define CSL_VCP2_VCPIC3_OUT_ORDER_MASK (0x10000000u) #define CSL_VCP2_VCPIC3_OUT_ORDER_SHIFT (0x0000001Cu) #define CSL_VCP2_VCPIC3_OUT_ORDER_RESETVAL (0x00000000u) /----OUT_ORDER Tokens----/ #define CSL_VCP2_VCPIC3_OUT_ORDER_LSB (0x00000000u) #define CSL_VCP2_VCPIC3_OUT_ORDER_MSB (0x00000001u) #define CSL_VCP2_VCPIC3_ITBEN_MASK (0x01000000u) #define CSL_VCP2_VCPIC3_ITBEN_SHIFT (0x00000018u) #define CSL_VCP2_VCPIC3_ITBEN_RESETVAL (0x00000000u) /----ITBEN Tokens----/ #define CSL_VCP2_VCPIC3_ITBEN_DISABLE (0x00000000u) #define CSL_VCP2_VCPIC3_ITBEN_ENABLE (0x00000001u) #define CSL_VCP2_VCPIC3_ITBI_MASK (0x00FF0000u) #define CSL_VCP2_VCPIC3_ITBI_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC3_ITBI_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC3_C_MASK (0x0000FFFFu) #define CSL_VCP2_VCPIC3_C_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC3_C_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC3_RESETVAL (0x00000000u) / VCPIC4 / #define CSL_VCP2_VCPIC4_IMINS_MASK (0x1FFF0000u) #define CSL_VCP2_VCPIC4_IMINS_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC4_IMINS_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC4_IMAXS_MASK (0x00001FFFu) #define CSL_VCP2_VCPIC4_IMAXS_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC4_IMAXS_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC4_RESETVAL (0x00000000u) / VCPIC5 / #define CSL_VCP2_VCPIC5_SDHD_MASK (0x80000000u) #define CSL_VCP2_VCPIC5_SDHD_SHIFT (0x0000001Fu) #define CSL_VCP2_VCPIC5_SDHD_RESETVAL (0x00000000u) /----SDHD Tokens----/ #define CSL_VCP2_VCPIC5_SDHD_HARD (0x00000000u) #define CSL_VCP2_VCPIC5_SDHD_SOFT (0x00000001u) #define CSL_VCP2_VCPIC5_OUTF_MASK (0x40000000u) #define CSL_VCP2_VCPIC5_OUTF_SHIFT (0x0000001Eu) #define CSL_VCP2_VCPIC5_OUTF_RESETVAL (0x00000000u) /----OUTF Tokens----/ #define CSL_VCP2_VCPIC5_OUTF_NO (0x00000000u) #define CSL_VCP2_VCPIC5_OUTF_YES (0x00000001u) #define CSL_VCP2_VCPIC5_TB_MASK (0x30000000u) #define CSL_VCP2_VCPIC5_TB_SHIFT (0x0000001Cu) #define CSL_VCP2_VCPIC5_TB_RESETVAL (0x00000000u) /----TB Tokens----/ #define CSL_VCP2_VCPIC5_TB_NO (0x00000000u) #define CSL_VCP2_VCPIC5_TB_TAIL (0x00000001u) #define CSL_VCP2_VCPIC5_TB_CONV (0x00000002u) #define CSL_VCP2_VCPIC5_TB_MIX (0x00000003u) #define CSL_VCP2_VCPIC5_SYMR_MASK (0x01F00000u) #define CSL_VCP2_VCPIC5_SYMR_SHIFT (0x00000014u) #define CSL_VCP2_VCPIC5_SYMR_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC5_SYMX_MASK (0x000F0000u) #define CSL_VCP2_VCPIC5_SYMX_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC5_SYMX_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC5_IMAXI_MASK (0x000000FFu) #define CSL_VCP2_VCPIC5_IMAXI_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC5_IMAXI_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC5_RESETVAL (0x00000000u) / VCPOUT0 / #define CSL_VCP2_VCPOUT0_FMINS_MASK (0x1FFF0000u) #define CSL_VCP2_VCPOUT0_FMINS_SHIFT (0x00000010u) #define CSL_VCP2_VCPOUT0_FMINS_RESETVAL (0x00000000u) #define CSL_VCP2_VCPOUT0_FMAXS_MASK (0x00001FFFu) #define CSL_VCP2_VCPOUT0_FMAXS_SHIFT (0x00000000u) #define CSL_VCP2_VCPOUT0_FMAXS_RESETVAL (0x00000000u) #define CSL_VCP2_VCPOUT0_RESETVAL (0x00000000u) / VCPOUT1 / #define CSL_VCP2_VCPOUT1_YAM_MASK (0x00010000u) #define CSL_VCP2_VCPOUT1_YAM_SHIFT (0x00000010u) #define CSL_VCP2_VCPOUT1_YAM_RESETVAL (0x00000000u) /----YAM Tokens----/ #define CSL_VCP2_VCPOUT1_YAM_NO (0x00000000u) #define CSL_VCP2_VCPOUT1_YAM_YES (0x00000001u) #define CSL_VCP2_VCPOUT1_FMAXI_MASK (0x000000FFu) #define CSL_VCP2_VCPOUT1_FMAXI_SHIFT (0x00000000u) #define CSL_VCP2_VCPOUT1_FMAXI_RESETVAL (0x00000000u) #define CSL_VCP2_VCPOUT1_RESETVAL (0x00000000u) / VCPWBM / #define CSL_VCP2_VCPWBM_WRITE_MASK (0xFFFFFFFFu) #define CSL_VCP2_VCPWBM_WRITE_SHIFT (0x00000000u) #define CSL_VCP2_VCPWBM_WRITE_RESETVAL (0x00000000u) #define CSL_VCP2_VCPWBM_RESETVAL (0x00000000u) / VCPRDECS */ #define CSL_VCP2_VCPRDECS_READ_MASK (0xFFFFFFFFu) #define CSL_VCP2_VCPRDECS_READ_SHIFT (0x00000000u) #define CSL_VCP2_VCPRDECS_READ_RESETVAL (0x00000000u) #define CSL_VCP2_VCPRDECS_RESETVAL (0x00000000u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcGetHwStatus.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* @file csl_pllcGetHwStatus.c * * @brief File for functional layer of CSL API @a CSL_pllcGetHwStatus() * * Path: \(CSLPATH)\src\pllc / / ============================================================================ * Revision History * =============== * 25-Aug-2005 Tej File Created. * 27-oct-2005 sd changes for multiplier configuration * 18-Jan-2006 sd Changes according to spec changes * ============================================================================ / #include <csl_pllc.h> #include <csl_pllcAux.h> /* ============================================================================ * @n@b CSL_pllcGetHwStatus * * @b Description * @n Gets the status of the different operations of PLLC. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance query The query to this API of PLLC which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVQUERY - Invalid query command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcHwStatusQuery query = CSL_PLLC_QUERY_STATUS; CSL_BitMask32 reponse; ... status = CSL_pllcGetHwStatus (hPllc, query, &response); @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_pllcGetHwStatus, ".text:csl_section:pllc"); CSL_Status CSL_pllcGetHwStatus ( CSL_PllcHandle hPllc, CSL_PllcHwStatusQuery query, void response ) { CSL_Status status = CSL_SOK; if (hPllc == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (query) { /* Query for GOSTAT bit in PLLSTAT register/ case CSL_PLLC_QUERY_STATUS: (CSL_BitMask32) response = CSL_pllcGetStatus (hPllc); break; / Query for SYSnOn bits SYSSTAT register/ case CSL_PLLC_QUERY_SYSCLKSTAT: (CSL_BitMask32) response = CSL_pllcGetSysClkStatus (hPllc); break; / Query for status of RSTYPE register/ case CSL_PLLC_QUERY_RESETSTAT: if (hPllc->pllcNum == CSL_PLLC_1) (CSL_BitMask32*) response = CSL_pllcGetResetStatus (hPllc); else status = CSL_ESYS_INVPARAMS; break; default: status = CSL_ESYS_INVQUERY; break; } } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrGetHwStatus.c	<filename>DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrGetHwStatus.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* =========================================================================== * @file csl_tmrGetHwStatus.c * * @brief File for functional layer of CSL API CSL_tmrGetHwStatus() * * @path $(CSLPATH)\src\timer * * @desc The CSL_tmrGetHwStatus() function definition & it's associated * functions * ============================================================================ / / ============================================================================ * Revision History * =============== * 1-Sept-2004 HMM File Created. * 29-Jul-2005 PSK updted changes acooriding to revised timer spec. the number * convention TIM12, TIM34 are changed to TIMLO and TIMHI. * ============================================================================ / #include <csl_tmr.h> #include <csl_tmrAux.h> /* =========================================================================== * @n@b CSL_tmrGetHwStatus * * @b Description * @n This function is used to get the value of various parameters of the * timer instance. The value returned depends on the query passed. * * @b Arguments * @verbatim hTmr Handle to the timer instance query Query to be performed response Pointer to buffer to return the data requested by the query passed @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Successful completion of the * query * * @li CSL_ESYS_BADHANDLE - Invalid handle * * @li CSL_ESYS_INVQUERY - Query command not supported * * @li CSL_ESYS_INVPARAMS - Invalid Parameter * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * Data requested by the query is returned through the variable "response" * * @b Modifies * @n The input arguement "response" is modified * * @b Example * @verbatim CSL_status status; Uint8 hwRevId; ... status = CSL_tmrGetHwStatus(hGptimer, CSL_TMR_QUERY_COUNT_LO, &hwRevId); ... @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_tmrGetHwStatus, ".text:csl_section:tmr"); CSL_Status CSL_tmrGetHwStatus ( CSL_TmrHandle hTmr, CSL_TmrHwStatusQuery query, void response ) { CSL_Status status = CSL_SOK; if (hTmr == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (query) { case CSL_TMR_QUERY_COUNT_LO: CSL_tmrGetTimLoCount(hTmr, (Uint32 )response); break; case CSL_TMR_QUERY_COUNT_HI: CSL_tmrGetTimHiCount(hTmr, (Uint32 )response); break; case CSL_TMR_QUERY_TSTAT_LO: ((CSL_TmrTstat )response) = CSL_tmrGetTstatLoStatus(hTmr); break; case CSL_TMR_QUERY_TSTAT_HI: ((CSL_TmrTstat )response) = CSL_tmrGetTstatHiStatus(hTmr); break; case CSL_TMR_QUERY_WDFLAG_STATUS: ((CSL_TmrWdflagBitStatus)response) = CSL_tmrGetWdflagStatus(hTmr); break; default: status = CSL_ESYS_INVQUERY; break; } } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/srio/csl_srioInit.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ========================================================================== / /* =========================================================================== * @file csl_srioInit.c * * @brief File for functional layer of CSL API CSL_srioInit() * * @path $(CSLPATH)\srio\src * * @desc The CSL_srioInit() function definition and it's associated * functions * ============================================================================ / / ============================================================================ * Revision History * =============== * 20-Aug-2005 PSK File Created. * ============================================================================ / #include <csl_srio.h> /* ============================================================================ * @n@b CSL_srioInit * * @b Description * @n This is the initialization function for the SRIO CSL. * The function must be called before calling any other API from this CSL. * This function is idem-potent. Currently, the function just return * status CSL_SOK, without doing anything. * * @b Arguments * @verbatim pContext Pointer to module-context. As SRIO doesn't have any context based information user is expected to pass NULL. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The CSL for SRIO is initialized * * @b Modifies * @n None * * @b Example * @verbatim CSL_Status status; ... status = CSL_srioInit(NULL); ... @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_srioInit, ".text:csl_section:srio"); CSL_Status CSL_srioInit ( CSL_SrioContext pContext ) { return (CSL_SOK); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3Init.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_edma3Init.c * * @path $(CSLPATH)\src\edma * * @desc File for functional layer of CSL API CSL_edma3Init () * / / ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= / #include <csl_edma3.h> /* ============================================================================ * @n@b CSL_edma3Init * * @b Description * @n This is the initialization function for the edma CSL. The function must * be called before calling any other API from this CSL.This function is * idem-potent. Currently, the function just return status CSL_SOK, * without doing anything. * * @b Arguments @verbatim pContext Pointer to module-context. As edma doesn't have any context based information user is expected to pass NULL. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The CSL for EDMA is initialized * * @b Modifies * @n None * * @b Example * @verbatim ... if (CSL_edma3Init(NULL) != CSL_SOK) { exit; } @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_edma3Init, ".text:csl_section:edma3"); CSL_Status CSL_edma3Init ( CSL_Edma3Context pContext ) { return CSL_SOK; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcPlugEventHandler.c	<filename>DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcPlugEventHandler.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_intcPlugEventHandler.c * * @brief File for functional layer of CSL API @a CSL_intcPlugEventHandler() * * PATH $(CSLPATH)\src\intc * / / ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= / #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /* ============================================================================ * @n@b CSL_intcPlugEventHandler * * @b Description * @n Associate an event-handler with an event * CSL_intcPlugEventHandler(..) ties an event-handler to an event; so * that the occurence of the event, would result in the event-handler * being invoked. * * @b Arguments * @verbatim hIntc Intc handle identifies the interrupt-event eventHandlerRecord Provides the details of the event-handler @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Succussful completion of PlugEventHandler * @li CSL_ESYS_FAIL - Non completion of PlugEventHandler * * @b Example: * @verbatim CSL_IntcObj intcObj20; CSL_IntcGlobalEnableState state; CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; context.numEvtEntries = 0; context.eventhandlerRecord = NULL; // Init Module CSL_intcInit(&context); // NMI Enable CSL_intcGlobalNmiEnable(); // Enable Global Interrupts intStat = CSL_intcGlobalEnable(&state); // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL); EventRecord.handler = &event20Handler; EventRecord.arg = hIntc20; CSL_intcPlugEventHandler(hIntc20,&EventRecord); // Close handle CSL_IntcClose(hIntc20); } void event20Handler( CSL_IntcHandle hIntc) { } @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_intcPlugEventHandler, ".text:csl_section:intc"); CSL_Status CSL_intcPlugEventHandler ( CSL_IntcHandle hIntc, CSL_IntcEventHandlerRecord eventHandlerRecord ) { volatile Uint16 i; CSL_Status status = CSL_ESYS_FAIL; asm(" dint"); /* Search for free entry and plug in handler / for (i = 0; i < _CSL_intcNumEvents; i++) { if (_CSL_intcEventHandlerRecord[i].handler == CSL_INTC_EVTHANDLER_NONE){ / Plug in Handler / _CSL_intcEventHandlerRecord[i].handler = eventHandlerRecord->handler; _CSL_intcEventHandlerRecord[i].arg = eventHandlerRecord->arg; / Establish mapping */ _CSL_intcEventOffsetMap[hIntc->eventId] = i; status = CSL_SOK; break; } } asm(" rint"); return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcHwControl.c	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* @file csl_pllcHwControl.c * * @brief File for functional layer of CSL API @a CSL_pllcHwControl() * * Path: \(CSLPATH)\src\pllc / / ============================================================================ * Revision History * =============== * 25-Aug-2005 Tej File Created. * 18-Jan-2006 sd Changes according to spec changes * ============================================================================ / #include <csl_pllc.h> #include <csl_pllcAux.h> /* ============================================================================ * @n@b CSL_pllcHwControl * * @b Description * @n Takes a command of PLLC with an optional argument & implements it. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance cmd The command to this API indicates the action to be taken on PLLC. arg An optional argument. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n To change PLLM, PREDIV & PLLDIVn, PLLCTL_PLLEN bit must be in BYPASS * * <b> Post Condition </b> * @n None * * @b Modifies * @n The hardware registers of PLLC. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcHwControlCmd cmd = CSL_PLLC_CMD_SET_PLLM; void arg = 0x7; ... status = CSL_pllcHwControl (hPllc, cmd, &arg); @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_pllcHwControl, ".text:csl_section:pllc"); CSL_Status CSL_pllcHwControl ( CSL_PllcHandle hPllc, CSL_PllcHwControlCmd cmd, void arg ) { CSL_Status status = CSL_SOK; if (hPllc == NULL) { status = CSL_ESYS_BADHANDLE; } else if (arg == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (cmd) { /* cmd to change PLLCTL and PLLCMD register of PLL controller / case CSL_PLLC_CMD_PLLCONTROL: CSL_pllcCommandCtrl (hPllc, (CSL_BitMask32)arg, &status); break; / cmd to change PLLM register of PLL controller / case CSL_PLLC_CMD_SET_PLLM: CSL_pllcMultiplierCtrl (hPllc, (Uint32)arg, &status); break; / cmd to change PLLDIVn_RATIO of PLLDIVn register / case CSL_PLLC_CMD_SET_PLLRATIO: CSL_pllcSetPLLDivRatio (hPllc, (CSL_PllcDivRatio) arg, &status); break; / cmd to change PLLDIVn_DnEN of PLLDIVn register / case CSL_PLLC_CMD_PLLDIV_CONTROL: CSL_pllcPLLDivCtrl (hPllc, (CSL_PllcDivideControl*) arg, &status); break; default: status = CSL_ESYS_INVCMD; break; } } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_gpio.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * provided * ============================================================================ / /* =========================================================================== * @file csl_gpio.h * * @path $(CSLPATH)\inc * * @desc GPIO functional layer APIs header file. The different enumerations, * structure definitions and function declarations * ============================================================================ * @mainpage GPIO CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the GPIO module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given GPIO module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular GPIO Module.The CSL developer should use his discretion designing * new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 ============================================================================= / /* ============================================================================ * Revision History * =============== * 11-Jun-2004 PGR file created * 04-sep-2004 Nsr - Updated CSL_GpioObj and added CSL_GpioBaseAddress, * CSL_GpioParam, SL_GpioContext, CSL_GpioConfig structures. * - Updated comments for H/W control cmd and status query * enums. * - Added prototypes for CSL_gpioGetBaseAdddress and * CSL_gpioHwSetupRaw. * - Changed prototypes of CSL_gpioInit, CSL_gpioOpen. * - Updated respective comments along with that of * CSL_gpioClose. * 11-Oct-2004 Nsr - Removed the extern keyword before function declaration and * - Changed this file according to review. * 22-Feb-2005 Nsr - Added control command CSL_GPIO_CMD_GET_BIT according to * TI issue PSG00000310. * 28-Jul-2005 PSK - Updated the CSL source to support only one BANK * * 11-Jan-2006 NG - Added CSL_GPIO_CMD_SET_OUT_BIT Control Command * 06-Mar-2006 ds - Rename CSL_GPIO_CMD_SET_OUT_BIT to * CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT * - Moved CSL_GpioPinNum Enumeration from the cslr_gpio.h * ============================================================================ / #ifndef _CSL_GPIO_H_ #define _CSL_GPIO_H_ #ifdef __cplusplus extern "C" { #endif #include <soc.h> #include <csl.h> #include <cslr_gpio.h> /< Invalid argument / #define CSL_EGPIO_INVPARAM CSL_EGPIO_FIRST /***************************************************************************\ GPIO global typedef declarations \*************************************************************************/ / * \brief Base-address of the Configuration registers of GPIO. / typedef struct { /* Base-address of the configuration registers of the peripheral / CSL_GpioRegsOvly regs; } CSL_GpioBaseAddress; /* * \brief GPIO specific parameters. Present implementation doesn't have * any specific parameters. / typedef struct { /* Bit mask to be used for module specific parameters. * The below declaration is just a place-holder for future * implementation. / CSL_BitMask16 flags; } CSL_GpioParam; /* \brief GPIO specific context information. Present implementation doesn't * have any Context information. / typedef struct { /* Context information of GPIO. * The below declaration is just a place-holder for future * implementation. / Uint16 contextInfo; } CSL_GpioContext; /* * @brief Config structure of GPIO. This is used to configure GPIO * using CSL_HwSetupRaw function / typedef struct { /* GPIO Interrupt Per-Bank Enable Register / volatile Uint32 BINTEN; /* GPIO Direction Register / volatile Uint32 DIR; /* GPIO Output Data Register / volatile Uint32 OUT_DATA; /* GPIO Set Data Register / volatile Uint32 SET_DATA; /* GPIO Clear Data Register / volatile Uint32 CLR_DATA; /* GPIO Set Rising Edge Interrupt Register / volatile Uint32 SET_RIS_TRIG; /* GPIO Clear Rising Edge Interrupt Register / volatile Uint32 CLR_RIS_TRIG; /* GPIO Set Falling Edge Interrupt Register / volatile Uint32 SET_FAL_TRIG; /* GPIO Clear Falling Edge Interrupt Register / volatile Uint32 CLR_FAL_TRIG; } CSL_GpioConfig; /* @brief Default Values for GPIO Config structure / #define CSL_GPIO_CONFIG_DEFAULTS { \ CSL_GPIO_BINTEN_RESETVAL , \ CSL_GPIO_DIR_RESETVAL, \ CSL_GPIO_OUT_DATA_RESETVAL, \ CSL_GPIO_SET_DATA_RESETVAL, \ CSL_GPIO_CLR_DATA_RESETVAL, \ CSL_GPIO_SET_RIS_TRIG_RESETVAL, \ CSL_GPIO_CLR_RIS_TRIG_RESETVAL, \ CSL_GPIO_SET_FAL_TRIG_RESETVAL, \ CSL_GPIO_CLR_FAL_TRIG_RESETVAL, \ } /* Enumeration used for specifying the GPIO pin numbers / typedef enum { /* Gpio pin 0 / CSL_GPIO_PIN0, /* Gpio pin 1 / CSL_GPIO_PIN1, /* Gpio pin 2 / CSL_GPIO_PIN2, /* Gpio pin 3 / CSL_GPIO_PIN3, /* Gpio pin 4 / CSL_GPIO_PIN4, /* Gpio pin 5 / CSL_GPIO_PIN5, /* Gpio pin 6 / CSL_GPIO_PIN6, /* Gpio pin 7 / CSL_GPIO_PIN7, /* Gpio pin 8 / CSL_GPIO_PIN8, /* Gpio pin 0 / CSL_GPIO_PIN9, /* Gpio pin 10 / CSL_GPIO_PIN10, /* Gpio pin 11 / CSL_GPIO_PIN11, /* Gpio pin 12 / CSL_GPIO_PIN12, /* Gpio pin 13 / CSL_GPIO_PIN13, /* Gpio pin 14 / CSL_GPIO_PIN14, /* Gpio pin 15 / CSL_GPIO_PIN15 } CSL_GpioPinNum; /\brief Enums for configuring GPIO pin direction / typedef enum { CSL_GPIO_DIR_OUTPUT,/<<b>: Output pin</b>/ CSL_GPIO_DIR_INPUT /*<<b>: Input pin</b>/ } CSL_GpioDirection; /** \brief Enums for configuring GPIO pin edge detection * / typedef enum { /<<b>: No edge detection </b>/ CSL_GPIO_TRIG_CLEAR_EDGE, /*<<b>: Rising edge detection </b>/ CSL_GPIO_TRIG_RISING_EDGE, /*<<b>: Falling edge detection </b>/ CSL_GPIO_TRIG_FALLING_EDGE, /*<<b>: Dual edge detection </b>/ CSL_GPIO_TRIG_DUAL_EDGE } CSL_GpioTriggerType; /** \brief Enumeration for control commands passed to \a CSL_gpioHwControl() * * This is the set of commands that are passed to the \a CSL_gpioHwControl() * with an optional argument type-casted to \a void* . * The arguments to be passed with each enumeration (if any) are specified * next to the enumeration / typedef enum { /* * @brief Enables interrupt on bank * @param ( None ) / CSL_GPIO_CMD_BANK_INT_ENABLE = 0, /* * @brief Disables interrupt on bank * @param ( None ) / CSL_GPIO_CMD_BANK_INT_DISABLE = 1, /* * @brief Configures GPIO pin direction and edge detection properties * @param ( CSL_GpioPinConfig ) / CSL_GPIO_CMD_CONFIG_BIT = 2, /* * @brief Changes output state of GPIO pin to logic-1 * @param ( CSL_GpioPinNum ) / CSL_GPIO_CMD_SET_BIT = 3, /* * @brief Changes output state of GPIO pin to logic-0 * @param ( CSL_GpioPinNum ) / CSL_GPIO_CMD_CLEAR_BIT = 4, /* * @brief Gets the state of input pins on bank * The "data" field act as output parameter reporting * the input state of the GPIO pins on the bank. * @param ( CSL_BitMask16) / CSL_GPIO_CMD_GET_INPUTBIT = 5, /** * @brief Gets the state of output pins on bank. * The "data" field act as output parameter reporting the * output drive state of the GPIO pins on the bank * @param ( CSL_BitMask16* ) / CSL_GPIO_CMD_GET_OUTDRVSTATE = 6, /* * @brief Gets the state of input pin on bank. * @param ( CSL_GpioPinData * ) / CSL_GPIO_CMD_GET_BIT = 7, /* * @brief Changes output state of GPIO pin to logic-1 * @param ( CSL_GpioPinData ) / CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT = 8 } CSL_GpioHwControlCmd; /** \brief Enumeration for queries passed to \a CSL_GpioGetHwStatus() * * This is used to get the status of different operations.The arguments * to be passed with each enumeration if any are specified next to * the enumeration / typedef enum { /* * @brief Queries GPIO bank interrupt enable status * @param ( CSL_BitMask16* ) / CSL_GPIO_QUERY_BINTEN_STAT = 2 } CSL_GpioHwStatusQuery; /* \brief Input parameters for configuring a GPIO pin * This is used to configure the direction and edge detection / typedef struct { /< Pin number for GPIO bank / CSL_GpioPinNum pinNum; /*< Direction for GPIO Pin / CSL_GpioDirection direction; /*< GPIO pin edge detection / CSL_GpioTriggerType trigger; } CSL_GpioPinConfig; /*\brief this is used for getting a specific pin staus / typedef struct { /*< Pin number for GPIO bank / CSL_GpioPinNum pinNum; /** pin value / Int16 pinVal; } CSL_GpioPinData; /* \brief Input parameters for setting up GPIO during startup * * This is just a placeholder as GPIO is a simple module, which doesn't * require any setup / typedef struct { /* The extendSetup is just a place-holder for future * implementation. / void extendSetup; } CSL_GpioHwSetup; /** \brief This object contains the reference to the instance of GPIO * opened using the @a CSL_gpioOpen() * * The pointer to this is passed to all GPIO CSL APIs * This structure has the fields required to configure GPIO for any test * case/application. It should be initialized as per requirements of a * test case/application and passed on to the setup function / typedef struct CSL_GpioObj { /< This is a pointer to the registers of the instance of GPIO referred to by this object / CSL_GpioRegsOvly regs; /< This is the instance of GPIO being referred to by this object / CSL_InstNum gpioNum; /< This is the maximum number of pins supported by this instance of GPIO / Uint8 numPins; } CSL_GpioObj; /* \brief this is a pointer to @a CSL_GpioObj and is passed as the first * parameter to all GPIO CSL APIs / typedef CSL_GpioObj CSL_GpioHandle; /***************************************************************************\ CSL3.x mandatory function prototype definitions \*************************************************************************/ / =========================================================================== * @n@b CSL_gpioInit * * @b Description * @n This is the initialization function for the GPIO. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. * * @b Arguments * @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... CSL_gpioInit(); @endverbatim * =========================================================================== / CSL_Status CSL_gpioInit( CSL_GpioContext pContext ); /** ============================================================================ * @n@b CSL_gpioOpen * * @b Description * @n This function populates the peripheral dgpio object for the GPIO instance * and returns a handle to the instance. * The open call sets up the dgpio structures for the particular instance * of GPIO device. The device can be re-opened anytime after it has been * normally closed if so required. The handle returned by this call is * input as an essential argument for rest of the APIs described * for this module. * * @b Arguments * @verbatim pGpioObj Pointer to the GPIO instance object gpioNum Instance of the GPIO to be opened pGpioParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * <b> Return Value </b> CSL_GpioHandle * @n Valid GPIO instance handle will be returned if status value is equal to CSL_SOK. * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n 1. GPIO object structure is populated * @n 2. The status is returned in the status variable. If status * returned is * @li CSL_SOK Valid gpio handle is returned * @li CSL_ESYS_FAIL The gpio instance is invalid * @li CSL_ESYS_INVPARAMS Invalid parameter * * @b Modifies * @n 1. The status variable * @n 2. GPIO object structure * * @b Example * @verbatim CSL_status status; CSL_GpioObj gpioObj; CSL_GpioHandle hGpio; ... hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO_PER_CNT, NULL, &status); ... @endverbatim * ============================================================================= / CSL_GpioHandle CSL_gpioOpen ( CSL_GpioObj hGpioObj, CSL_InstNum gpioNum, CSL_GpioParam pGpioParam, CSL_Status status ); /** ============================================================================ * @n@b CSL_gpioClose * * @b Description * @n This function closes the specified instance of GPIO. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Close successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_status status; ... status = CSL_gpioClose(hGpio); @endverbatim * ============================================================================= / CSL_Status CSL_gpioClose ( CSL_GpioHandle hGpio ); /* ============================================================================ * @n@b CSL_gpioHwSetup * * @b Description * @n It configures the gpio registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance hwSetup Pointer to harware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @b Modifies * @n The hardware registers of GPIO. * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioObj gpioObj; CSL_GpioHwSetup hwSetup; CSL_status status; ... hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO_PRIMARY, NULL, &status); status = CSL_gpioHwSetup(hGpio, &hwSetup); @endverbatim * ============================================================================= / CSL_Status CSL_gpioHwSetup ( CSL_GpioHandle hGpio, CSL_GpioHwSetup setup ); /** =========================================================================== * @n@b CSL_gpioHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hGpio Handle to the Gpio instance config Pointer to config structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not * properly initialized * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The registers of the specified GPIO instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified GPIO instance. * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioConfig config = CSL_GPIO_CONFIG_DEFAULTS; CSL_Status status; status = CSL_gpioHwSetupRaw(hGpio, &config); @endverbatim * =========================================================================== / CSL_Status CSL_gpioHwSetupRaw ( CSL_GpioHandle hGpio, CSL_GpioConfig config ); /** ============================================================================ * @n@b CSL_gpioGetHwSetup * * @b Description * @n Gets the current setup of GPIO. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance setup Pointer to setup structure which contains the setup information of GPIO. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Setup info load successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The registers of the specified GPIO instance will be setup. * * @b Modifies * @n Hardware registers of the specified GPIO instance. * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioHwSetup setup; CSL_Status status; status = CSL_gpioGetHwSetup(hGpio, &setup); @endverbatim * ============================================================================= / CSL_Status CSL_gpioGetHwSetup ( CSL_GpioHandle hGpio, CSL_GpioHwSetup setup ); /** ============================================================================ * @n@b CSL_gpioHwControl * * @b Description * @n Takes a command of GPIO with an optional argument & implements it. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance cmd The command to this API indicates the action to be taken on GPIO. arg An optional argument. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_FAIL - Invalid instance number * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n The hardware registers of GPIO. * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioHwControlCmd cmd; void arg; status = CSL_gpioHwControl(hGpio, cmd, &arg); @endverbatim * ============================================================================= / CSL_Status CSL_gpioHwControl ( CSL_GpioHandle hGpio, CSL_GpioHwControlCmd cmd, void arg ); /** ============================================================================ * @n@b CSL_gpioGetHwStatus * * @b Description * @n Gets the status of the different operations of GPIO. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance query The query to this API of GPIO which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioHwStatusQuery query; void reponse; status = CSL_gpioGetHwStatus(hGpio, query, &response); @endverbatim * ============================================================================= / CSL_Status CSL_gpioGetHwStatus( CSL_GpioHandle hGpio, CSL_GpioHwStatusQuery query, void response ); /** =========================================================================== * @n@b CSL_gpioGetBaseAddress * * @b Description * @n Function to get the base address of the peripheral instance. * This function is used for getting the base address of the peripheral * instance. This function will be called inside the CSL_gpioOpen() * function call. This function is open for re-implementing if the user * wants to modify the base address of the peripheral object to point to * a different location and there by allow CSL initiated write/reads into * peripheral MMR's go to an alternate location. * * @b Arguments * @verbatim gpioNum Specifies the instance of GPIO to be opened. pGpioParam Module specific parameters. pBaseAddress Pointer to baseaddress structure containing base address details. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_OK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Base Address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_GpioBaseAddress baseAddress; ... status = CSL_gpioGetBaseAddress(CSL_GPIO_PER_CNT, NULL, &baseAddress); @endverbatim * =========================================================================== / CSL_Status CSL_gpioGetBaseAddress ( CSL_InstNum gpioNum, CSL_GpioParam pGpioParam, CSL_GpioBaseAddress pBaseAddress ); #ifdef __cplusplus } #endif #endif /_CSL_GPIO_H_*/
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtOpen.c	<filename>DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtOpen.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * priovided * ============================================================================ / /* ============================================================================ * @file csl_bwmngmtOpen.c * * @path $(CSLPATH)\src\bwmngmt * * @desc File for functional layer of CSL API CSL_bwmngmtOpen() * / / ============================================================================= * Revision History * =============== * 03-Jun-2004 <NAME> File Created * 11-Apr-2005 Brn Updated the file for doxygen compatibiliy * 16-Nov-2005 ds Updated the documentation * 31-Jan-2006 ds Supported to use the CSL_bwmngmtGetBaseAddress() API * ============================================================================= / #include <csl_bwmngmt.h> /* =========================================================================== * @n@b CSL_bwmngmtOpen * * @b Description * This function populates the peripheral data object for the instance * and returns a handle to the BWMNGMT instance. * The open call sets up the data structures for the particular instance * of BWMNGMT device. The device can be re-opened anytime after it has * been normally closed, if so required.The handle returned by this call * is input as an essential argument for rest of the APIs described for * this module. * * @b Arguments * @verbatim pBwmngmtObj Pointer to the BWMNGMT instance object bwmngmtNum Instance of the BWMNGMT to be opened. pBwmngmtParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * <b> Return Value </b> CSL_BwmngmtHandle * Valid BWMNGMT instance handle will be returned if status value is * equal to CSL_SOK. * * <b> Pre Condition </b> * @n The BWMNGMT module must be successfully initialized via * CSL_bwmngmtInit() before calling this function. * * <b> Post Condition </b> * @n 1. The status is returned in the status variable. If status returned is * CSL_SOK - Valid BWMNGMT handle is returned. * CSL_ESYS_FAIL - The BWMNGMT instance is invalid. CSL_ESYS_INVPARAMS - The Obj structure passed is invalid * 2. BWMNGMT object structure is populated. * * * @b Modifies * @n 1. The status variable * 2. BWMNGMT object structure * * @b Example * @verbatim CSL_status status; CSL_BwmngmtObj bwmngmtObj; CSL_BwmngmtHandle hBwmngmt; hBwmngmt = CSL_bwmngmtOpen (&bwmngmtObj, CSL_BWMNGMT, NULL, &status ); @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_bwmngmtOpen, ".text:csl_section:bwmngmt"); CSL_BwmngmtHandle CSL_bwmngmtOpen ( CSL_BwmngmtObj pBwmngmtObj, CSL_InstNum bwmngmtNum, CSL_BwmngmtParam pBwmmngmtParam, CSL_Status pStatus ) { CSL_BwmngmtHandle hBwmngmt = (CSL_BwmngmtHandle)NULL; CSL_BwmngmtBaseAddress baseAddress; if (pStatus == NULL) { /* do nothing : already the module is initialized to NULL / } else if (pBwmngmtObj == NULL) { pStatus = CSL_ESYS_INVPARAMS; } else { pStatus = CSL_bwmngmtGetBaseAddress(bwmngmtNum, pBwmmngmtParam, &baseAddress); if (pStatus == CSL_SOK) { pBwmngmtObj->regs = baseAddress.regs; pBwmngmtObj->bwmngmtNum = (CSL_InstNum)bwmngmtNum; hBwmngmt = (CSL_BwmngmtHandle)pBwmngmtObj; } else { pBwmngmtObj->regs = (CSL_BwmngmtRegsOvly)NULL; pBwmngmtObj->bwmngmtNum = (CSL_InstNum)-1; } } return (hBwmngmt); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiHwSetup.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_hpiHwSetup.c * * @path $(CSLPATH)\src\hpi * * @brief File for functional layer of CSL API @a CSL_hpiHwSetup() * / #include <csl_hpi.h> /* ============================================================================ * @n@b CSL_hpiHwSetup * * @b Description * @n It configures the hpi registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim hHpi Handle to the hpi hwSetup Pointer to harware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup successful * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVPARAMS - The parameter passed is * invalid * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n HPI registers are configured according to the hardware setup * parameters. * * @b Modifies * @n HPI registers * * @b Example * @verbatim CSL_status status; CSL_HpiHwSetup myHwSetup; CSL_HpiHandle hHpi; myHwSetup.HPIC = hwSetup->hpiCtrl; ..... status = CSL_hpiHwSetup(hHpi, &hwSetup); @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_hpiHwSetup, ".text:csl_section:hpi"); CSL_Status CSL_hpiHwSetup ( CSL_HpiHandle hHpi, CSL_HpiHwSetup hwSetup ) { CSL_Status status = CSL_SOK; CSL_HpiRegsOvly hpiRegs = hHpi->regs; if (hHpi == NULL) { status = CSL_ESYS_BADHANDLE; } else if (hwSetup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Configure the Control Register */ hpiRegs->HPIC = hwSetup->hpiCtrl; } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_gpioAux.h	<filename>DSP/TI-Header/csl_c6455_src/inc/csl_gpioAux.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ============================================================================ / /* =========================================================================== * @file csl_gpioAux.h * * @brief APIs Auxilary header file for GPIO CSL * * @Path $(CSLPATH)\inc * * @desc Control command and status query Functions of gpio * ============================================================================ / / ============================================================================ * Revision History * =============== * 04-Sep-2004 Nsr File Created from CSL_gpioHwControl.c And * CSL_gpioGetHwStatus.c. * 04-Sep-2004 Nsr Added inline functions for query commands also. * 11-Oct-2004 Nsr Changed this file according to review commnets. * 22-Feb-2005 Nsr Added CSL_gpioGetBit API according to TI Issue PSG00000310. * 03-Mar-2005 Nsr Updated changes (PSG00000289) in CSL_gpioSetBit and * CSL_gpioClearBit. * 28-Jul-2005 PSK updated CSL source to support only ONE BANK. * bank "index" is removed. * 11-Jan-2006 NG Added CSL_GPIO_CMD_SET_OUT_BIT Control Command * 06-Mar-2006 ds Changed CSL_GPIO_CMD_SET_OUT_BIT cmd to clear and set the * outbit and Renamed CSL_GPIO_CMD_SET_OUT_BIT to * CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT * ============================================================================ / #ifndef _CSL_GPIOAUX_H_ #define _CSL_GPIOAUX_H_ #include <csl_gpio.h> #ifdef __cplusplus extern "C" { #endif / Control command and status query Functions of gpio. / /* =========================================================================== * @n@b CSL_gpioBankIntEnable * * @b Description * @n This function enables the GPIO bank interrupt . * * @b Arguments * @verbatim hGpio Handle to GPIO instance. @endverbatim * * <b> Return Value </b> * @n CSL_SOK * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Bank interrupt will be enabled * * @b Modifies * @n BINTEN register * * @b Example * @verbatim CSL_gpioBankIntEnable(hGpio); @endverbatim * ============================================================================ / static inline CSL_Status CSL_gpioBankIntEnable ( CSL_GpioHandle hGpio ) { CSL_FINSR(hGpio->regs->BINTEN, 0, 0, TRUE); return CSL_SOK; } /* =========================================================================== * @n@b CSL_gpioBankIntDisable * * @b Description * @n This function disables the GPIO bank interrupt . * * @b Arguments * @verbatim hGpio Handle to GPIO instance. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Bank interrupt will be disabled * * @b Modifies * @n BINTEN register * * @b Example * @verbatim CSL_gpioBankIntDisable(hGpio); @endverbatim * ============================================================================ / static inline CSL_Status CSL_gpioBankIntDisable ( CSL_GpioHandle hGpio ) { CSL_FINSR(hGpio->regs->BINTEN, 0, 0, FALSE); return CSL_SOK; } /* =========================================================================== * @n@b CSL_gpioConfigBit * * @b Description * @n This function used to configure the direction and rising and falling edge trigger registers. * * @b Arguments * @verbatim hGpio Handle to GPIO instance config Pointer to the CSL_GpioPinConfig structure. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Configures any of the 16 GPIO signals * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioConfigBit (hGpio, &config); @endverbatim * ============================================================================ / static inline CSL_Status CSL_gpioConfigBit ( CSL_GpioHandle hGpio, CSL_GpioPinConfig config ) { CSL_Status status = CSL_SOK; CSL_GpioPinNum pinNum; CSL_GpioTriggerType trigger; CSL_GpioRegsOvly gpioRegs = hGpio->regs; pinNum = config->pinNum; if (pinNum < hGpio->numPins) { pinNum = (CSL_GpioPinNum)(pinNum & 0x1f); trigger = config->trigger; CSL_FINSR(gpioRegs->DIR, pinNum, pinNum, config->direction); if (trigger & CSL_GPIO_TRIG_RISING_EDGE) { CSL_FINSR(gpioRegs->SET_RIS_TRIG, pinNum, pinNum, TRUE); } else { CSL_FINSR(gpioRegs->CLR_RIS_TRIG, pinNum, pinNum, TRUE); } if (trigger & CSL_GPIO_TRIG_FALLING_EDGE) { CSL_FINSR(gpioRegs->SET_FAL_TRIG, pinNum, pinNum, TRUE); } else { CSL_FINSR (gpioRegs->CLR_FAL_TRIG, pinNum, pinNum, TRUE); } } else { status = CSL_EGPIO_INVPARAM; } return status; } /** =========================================================================== * @n@b CSL_gpioSetBit * * @b Description * @n This function sets the bit value of SET_DATA register in the GPIO * module. * * @b Arguments * @verbatim hGpio Handle to GPIO instance pinNum This variable holds the GPIO pin number. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioSetBit(hGpio,pinNum); @endverbatim * ============================================================================ / static inline CSL_Status CSL_gpioSetBit ( CSL_GpioHandle hGpio, CSL_GpioPinNum pinNum ) { CSL_Status status = CSL_SOK; CSL_GpioRegsOvly gpioRegs = hGpio->regs; if (pinNum < hGpio->numPins) { pinNum = (CSL_GpioPinNum)(pinNum & 0x1f); gpioRegs->SET_DATA = (1<<pinNum); } else { status = CSL_EGPIO_INVPARAM; } return status; } /* =========================================================================== * @n@b CSL_gpioEnDisOutBit * * @b Description * @n This function sets and clear the bit value of OUT_DATA register in the * GPIO * module. * * @b Arguments * @verbatim hGpio Handle to GPIO instance pinData Pointer to Gpio PinData structure @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioSetOutBit(hGpio,pinNum); @endverbatim * ============================================================================ / static inline CSL_Status CSL_gpioEnDisOutBit ( CSL_GpioHandle hGpio, CSL_GpioPinData pinData ) { CSL_Status status = CSL_SOK; CSL_GpioRegsOvly gpioRegs = hGpio->regs; if (pinData->pinNum < hGpio->numPins) { pinData->pinNum = (CSL_GpioPinNum)(pinData->pinNum & 0x1f); CSL_FINSR(gpioRegs->OUT_DATA, pinData->pinNum, pinData->pinNum, \ pinData->pinVal); } else { status = CSL_EGPIO_INVPARAM; } return status; } /** =========================================================================== * @n@b CSL_gpioClearBit * * @b Description * @n This function sets the bit value of CLR_DATA register. * * @b Arguments * @verbatim hGpio Handle to GPIO instance pinNum This variable holds the GPIO pin number. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioClearBit(hGpio,pinNum); @endverbatim * ============================================================================ / static inline CSL_Status CSL_gpioClearBit ( CSL_GpioHandle hGpio, CSL_GpioPinNum pinNum ) { CSL_Status status = CSL_SOK; CSL_GpioRegsOvly gpioRegs = hGpio->regs; if (pinNum < hGpio->numPins) { pinNum = (CSL_GpioPinNum)(pinNum & 0x1f); gpioRegs->CLR_DATA = (1<<pinNum); } else { status = CSL_EGPIO_INVPARAM; } return status; } /* =========================================================================== * @n@b CSL_gpioGetInputBit * * @b Description * @n This function gets the IN_DATA register value of the GPIO bank. * * @b Arguments * @verbatim hGpio Handle to GPIO instance value Read IN_DATA register value. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioGetInputBit(hGpio,&value); @endverbatim * ============================================================================ / static inline CSL_Status CSL_gpioGetInputBit ( CSL_GpioHandle hGpio, CSL_BitMask16 value ) { (CSL_BitMask16 )value = hGpio->regs->IN_DATA; return CSL_SOK; } /** =========================================================================== * @n@b CSL_gpioGetBit * * @b Description * @n This function gets the Pin number status of GPIO module. * @b Arguments * @verbatim hGpio Handle to GPIO instance pinNum pin number to get the status. @endverbatim * * <b> Return Value </b> * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioGetBit(hGpio,pinNum); @endverbatim * =========================================================================== / static inline CSL_Status CSL_gpioGetBit ( CSL_GpioHandle hGpio, CSL_GpioPinData pinData ) { CSL_Status status = CSL_SOK; CSL_GpioRegsOvly gpioRegs = hGpio->regs; if (pinData->pinNum < hGpio->numPins) { pinData->pinNum = (CSL_GpioPinNum)(pinData->pinNum & 0x1f); pinData->pinVal = CSL_FEXTR(gpioRegs->IN_DATA, pinData->pinNum, pinData->pinNum); } else { pinData->pinVal = CSL_ESYS_FAIL; status = CSL_EGPIO_INVPARAM; } return status; } /** =========================================================================== * @n@b CSL_gpioGetOutDrvState * * @b Description * @n This function gets the OUT_DATA value of the GPIO bank. * * @b Arguments * @verbatim hGpio Handle to GPIO instance value Read OUT_DATA register value. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioGetOutDrvState(hGpio,&value); @endverbatim * =========================================================================== / static inline CSL_Status CSL_gpioGetOutDrvState ( CSL_GpioHandle hGpio, void value ) { (CSL_BitMask16 )value = hGpio->regs->OUT_DATA; return CSL_SOK; } /** =========================================================================== * @n@b CSL_gpioGetBintenStat * * @b Description * @n This function gets the interrupt capabilities of all banks in GPIO. * * @b Arguments * @verbatim hGpio Handle to GPIO instance response Placeholder to return status. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioGetBintenStat(hGpio, &response); @endverbatim * =========================================================================== / static inline void CSL_gpioGetBintenStat ( CSL_GpioHandle hGpio, void response ) { (CSL_BitMask16 )response = hGpio->regs->BINTEN; } #ifdef __cplusplus extern "C" { #endif #endif /* CSL_GPIOAUX_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtInit.c	<filename>DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtInit.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * priovided * ============================================================================ / /* ============================================================================ * @file csl_bwmngmtInit.c * * @path $(CSLPATH)\src\bwmngmt * * @desc File for functional layer of CSL API CSL_bwmngmtInit() * / / ============================================================================= * Revision History * =============== * 03-Jun-2004 <NAME> File Created * * 11-Apr-2005 Brn updated the file for doxygen compatibiliy * * 16-Nov-2005 ds updated the documentation * ============================================================================= / #include <csl_bwmngmt.h> /* ============================================================================ * @n@b CSL_bwmngmtInit * * @b Description * @n This is the initialization function for the BWMNGMT. This function must * be called before calling any other API from this CSL.This function is * idem-potent. Currently, the function just returns status CSL_SOK, * without doing anything. * * @b Arguments @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... CSL_bwmngmtInit(); @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_bwmngmtInit, ".text:csl_section:bwmngmt"); CSL_Status CSL_bwmngmtInit ( CSL_BwmngmtContext pContext ) { return CSL_SOK; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspIoRead.c	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_mcbspIoRead.c * * @path $(CSLPATH)\src\mcbsp * * @desc File for functional layer of CSL API CSL_mcbspIoRead() * / / ============================================================================= * Revision History * ================ * June 29,2004 <NAME> - Created * * ============================================================================= / #include <csl_mcbsp.h> /* ============================================================================ * @n@b CSL_mcbspIoRead * * @b Description * @n Reads the data from MCBSP pin which is configured as general purpose * input.The 16-bit data read from this pin is returned by this API. MCBSP * pin to use in this read operation is identified by the second argument. * * @b Arguments * @verbatim hMcbsp MCBSP handle returned by successful 'open' inputSel MCBSP pin to be used as general purpose input @endverbatim * * <b> Return Value </b> Uint16 * @li Data read from the pin * * <b> Pre Condition </b> * @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully * in that order before CSL_mcbspIoRead() can be called. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint16 inData; Uint16 clkx_data; Uint16 clkr_data; CSL_Status status; CSL_BitMask16 inMask; CSL_McbspHandle hMcbsp; ... // MCBSP object defined and HwSetup structure defined and initialized ... // Init, Open, HwSetup successfully done in that order ... inMask = CSL_MCBSP_IO_CLKX \| CSL_MCBSP_IO_CLKR; inData = CSL_mcbspIoRead(hMcbsp, inMask); if ((inData & CSL_MCBSP_IO_CLKX) != 0) clkx_data = 1; else clkx_data = 0; if ((inData & CSL_MCBSP_IO_CLKR) != 0) clkr_data = 1; else clkr_data = 0; ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_mcbspIoRead, ".text:csl_section:mcbsp"); Uint16 CSL_mcbspIoRead ( CSL_McbspHandle hMcbsp, CSL_BitMask16 inputSel ) { Uint16 ret_value = 0; if(inputSel & CSL_MCBSP_IO_CLKX) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_CLKXP)) ret_value \|= CSL_MCBSP_IO_CLKX; } if(inputSel & CSL_MCBSP_IO_FSX) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_FSXP)) ret_value \|= CSL_MCBSP_IO_FSX; } if(inputSel & CSL_MCBSP_IO_CLKR) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_CLKRP)) ret_value \|= CSL_MCBSP_IO_CLKR; } if(inputSel & CSL_MCBSP_IO_FSR) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_FSRP)) ret_value \|= CSL_MCBSP_IO_FSR; } if(inputSel & CSL_MCBSP_IO_DR) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_DRSTAT)) ret_value \|= CSL_MCBSP_IO_DR; } if(inputSel & CSL_MCBSP_IO_CLKS) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_CLKSSTAT)) ret_value \|= CSL_MCBSP_IO_CLKS; } return( ret_value ); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiHwControl.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_hpiHwControl.c * * @path $(CSLPATH)\src\hpi * * @brief File for functional layer of CSL API @a CSL_hpiHwControl() * / / ============================================================================ * Revision History * =============== * 06-Mar-2006 sd Removed the invalid parameter check * ============================================================================ / #include <csl_hpi.h> #include <csl_hpiAux.h> /* ============================================================================ * @n@b CSL_hpiHwControl * * @b Description * @n This function takes an input control command with an optional argument * and accordingly controls the operation/configuration of HPI. * * @b Arguments * @verbatim hHpi Handle to the HPI instance cmd The command to this API indicates the action to be taken on HPI. arg An optional argument. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Command successful. * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order * before calling CSL_hpiHwControl(). * * <b> Post Condition </b> * @n HPI registers are configured according to the command passed. * * @b Modifies * @n The hardware registers of HPI. * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_Status status; CSL_HpiHwControlCmd cmd = CSL_HPI_CMD_SET_DSP_INT; status = CSL_hpiHwControl(hHpi, cmd, NULL); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_hpiHwControl, ".text:csl_section:hpi"); CSL_Status CSL_hpiHwControl ( CSL_HpiHandle hHpi, CSL_HpiHwControlCmd cmd, void arg ) { CSL_Status status = CSL_SOK; if (hHpi == NULL) { status = CSL_ESYS_BADHANDLE; } else { switch (cmd) { /* Set the Host-to-DSP Interrupt / case CSL_HPI_CMD_SET_DSP_INT: CSL_hpiSetDspInt(hHpi); break; / Reset the Host-to-DSP Interrupt / case CSL_HPI_CMD_RESET_DSP_INT: CSL_hpiResetDspInt(hHpi); break; / Set the HPIC Host Interrupt / case CSL_HPI_CMD_SET_HINT: CSL_hpiSetHint(hHpi); break; / Rest the HPIC Host Interrupt */ case CSL_HPI_CMD_RESET_HINT: CSL_hpiResetHint(hHpi); break; default: status = CSL_ESYS_INVCMD; } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotHwSetupRaw.c	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_memprotHwSetupRaw.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotHwSetupRaw () * / / ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * * ============================================================================= / #include <csl_memprot.h> /* @brief Configures the Memory protection using the register-values passed in * through the config structure. For this module this API is a dummy. / #pragma CODE_SECTION (CSL_memprotHwSetupRaw, ".text:csl_section:memprot"); CSL_Status CSL_memprotHwSetupRaw ( / Pointer to the object that holds reference to the * instance of memory protection unit. / CSL_MemprotHandle hMemprot, / Pointer to setup structure which contains the * information to program the memory protection unit to a useful state / CSL_MemprotConfig config ) { return CSL_SOK; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3GetHwStatus.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_edma3GetHwStatus.c * * @path $(CSLPATH)\src\edma * * @desc File for functional layer of CSL API @a CSL_edma3GetHwStatus() * / / ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= / #include <csl_edma3.h> #include <csl_edma3Aux.h> /* ============================================================================ * @n@b CSL_edma3GetHwStatus * * @b Description * @n Gets the status of the different operations or the current setup of EDMA * module. * * @b Arguments * @verbatim hMod Edma module handle myQuery Query to be performed response Pointer to buffer to return the data requested by the query passed @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Get the status of edma * @li CSL_ESYS_BADHANDLE - The handle passed is * invalid * @li CSL_ESYS_INVQUERY - The query passed is invalid * @li CSL_ESYS_INVPARAMS - The parameter passed is * invalid * * <b> Pre Condition </b> * @n Functions CSL_edma3Init(), CSL_edma3Open() must be called successfully * in that order before this API can be invoked.argument type that can be * void* casted & passed with a particular command refer to * CSL_Edma3HwStatusQuery * * <b> Post Condition </b> * @n None * * @b Modifies * @n The input arguement "response" is modified * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3QueryInfo info; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Query Module Info CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INFO,&info); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_edma3GetHwStatus, ".text:csl_section:edma3"); CSL_Status CSL_edma3GetHwStatus ( CSL_Edma3Handle hMod, CSL_Edma3HwStatusQuery myQuery, void response ) { CSL_Status status = CSL_SOK; if (hMod == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch(myQuery) { #if CSL_EDMA3_MEMPROTECT case CSL_EDMA3_QUERY_MEMFAULT: status = CSL_edma3GetMemoryFaultError(hMod, \ (CSL_Edma3MemFaultStat)response); break; case CSL_EDMA3_QUERY_MEMPROTECT: ((CSL_Edma3CmdRegion)response)->regionVal = \ CSL_edma3GetMemoryProtectionAttrib(hMod, \ ((CSL_Edma3CmdRegion)response)->region); break; #endif case CSL_EDMA3_QUERY_CTRLERROR: status = CSL_edma3GetControllerError(hMod, \ (CSL_Edma3CtrlErrStat)response); break; case CSL_EDMA3_QUERY_INTRPEND: status = CSL_edma3GetIntrPendStatus(hMod, \ ((CSL_Edma3CmdIntr)response)->region, \ &((CSL_Edma3CmdIntr)response)->intr, \ &((CSL_Edma3CmdIntr)response)->intrh ); break; case CSL_EDMA3_QUERY_EVENTMISSED: status = \ CSL_edma3GetEventMissed(hMod,&((CSL_BitMask32)response)[0],\ &((CSL_BitMask32)response)[1], \ &((CSL_BitMask32)response)[2]); break; case CSL_EDMA3_QUERY_QUESTATUS: status = \ CSL_edma3GetQueStatus(hMod,((CSL_Edma3QueStat)response)->que,\ ((CSL_Edma3QueStat)response)); break; case CSL_EDMA3_QUERY_ACTIVITY: status = \ CSL_edma3GetActivityStatus(hMod,\ ((CSL_Edma3ActivityStat)response)); break; case CSL_EDMA3_QUERY_INFO: status = CSL_edma3GetInfo(hMod,((CSL_Edma3QueryInfo)response)); break; default: status = CSL_ESYS_INVQUERY; break; } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/FB_Example/global.h	#ifndef GLOBAL_H_ #define GLOBAL_H_ // #define USE_SIMULATOR #define INIT_IRQ #define USE_MAILBOX_IRQ #include <csl.h> #define I2C_BUFFER_SIZE 512 #define MONITOR_ARRAY 256 #define STIMULUS_VECTOR_SIZE 10 #define SENDDATA_PER_FRAME 64 #define DOWNSAMPLE 1 #define FRAMES_PER_LOOP 1 #define INCLUDE_HS1_DATA //#define INCLUDE_HS2_DATA #define INCLUDE_IF_DATA #define INCLUDE_HS1_FILTER_DATA //#define INCLUDE_HS2_FILTER_DATA //#define INCLUDE_DIGIO_DATA //#define INCLUDE_STATUS_DATA #define TOTAL_ANALOG_CHANNELS 256 extern Int32 adc_intern[TOTAL_ANALOG_CHANNELS]; extern unsigned int ddr_data[1000000]; // this makes the variable visible to all .c files that include global.h extern int threshold; extern int deadtime; extern Uint32 StimulusEnable[2]; extern Uint32 DAC_select[4]; extern Uint32 elec_config[4]; #endif /GLOBAL_H_/
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/bwmngmt/src/Bwmngmt_example.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / / ============================================================================ * @file Bwmngmt_example.c * * @path $(CSLPATH)\example\bwmngmt\src * * @desc Example for BWMNGMT CSL * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @n This example, * 1. Initializes and opens the CSL BWMNGMT module instance. * 2. Sets up the hardware to default values and mapPriority, * ControlBlocks i.e., CSL_bwmngmtHwSetup() is called for * module configuration. * 3. Read back the hardware setup parameters * 4. Does the comparision of configured setup parameters and red * hardware setup parameters * 5. Displays the messages based on step 4 * * ============================================================================= * * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Bwmngmt_example.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================= * Revision History * =============== * 23-sept-2005 PSK File Created * * 16-Dec-2005 ds Updated documentation * ============================================================================= / #include <csl_bwmngmt.h> #include <soc.h> #include <stdio.h> / Forward declarations / void bwmngmt_example (void); CSL_Status bwmngmtHwSetupVerify(CSL_BwmngmtHwSetup, CSL_BwmngmtHwSetup); / Handle for the BWMNGMT instance / CSL_BwmngmtHandle hBwmngmt; / Global variable used to log the error / Uint32 bwmngmtExampleFailed = 0; / * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= / void main (void) { bwmngmt_example(); return; } / * ============================================================================= * @func bwmngmt_example * * @desc * This function invokes example that prove functionalites of hardware * setup function with different value for the setup parameters. * The CSL API to retrive hardware setup parameters is also verified * * @arg * None * * @expected result * If the example passes, it displays the message "PASSED" * If the example fails, it displays the messae "FAILED" * * @eg * bwmngmt_example(); * ============================================================================= / void bwmngmt_example ( void ) { CSL_BwmngmtObj bwmngmtObj; CSL_Status status; CSL_BwmngmtHwSetup hwSetupRead; CSL_BwmngmtHwSetup hwSetup = CSL_BWMNGMT_HWSETUP_DEFAULTS; / Clear local data structures / memset(&bwmngmtObj, 0, sizeof(CSL_BwmngmtObj)); memset(&hwSetupRead, 0, sizeof(CSL_BwmngmtHwSetup)); / Setup parameters for Bwmngmt / hwSetupRead.control = (CSL_BwmngmtControlBlocks)2; hwSetup.mapPriority = (CSL_BwmngmtPriority)0x0; / Initialize BWMNGMT module / status = CSL_bwmngmtInit(NULL); if (status != CSL_SOK) { printf("BWMNGMT: Initialization... Failed.\n"); bwmngmtExampleFailed++; return; } / open the module / hBwmngmt = CSL_bwmngmtOpen(&bwmngmtObj, CSL_BWMNGMT, NULL, &status); if (status != CSL_SOK \|\| hBwmngmt == NULL) { printf ("BWMNGMT: Opening instance... Failed.\n"); bwmngmtExampleFailed++; return; } / hardware setup / status = CSL_bwmngmtHwSetup(hBwmngmt, &hwSetup); if (status != CSL_SOK) { printf ("BWMNGMT: HW Setup... Failed.\n"); bwmngmtExampleFailed++; return; } / Read back and verify setup / status = CSL_bwmngmtGetHwSetup(hBwmngmt, &hwSetupRead); if (status != CSL_SOK) { printf ("BWMNGMT: Get HW Setup... Failed.\n"); bwmngmtExampleFailed++; return; } / Verify the setup parameter with red parameters / status = bwmngmtHwSetupVerify(&hwSetup, &hwSetupRead); if (status != CSL_SOK) { printf ("BWMNGMT: Example FAILED.\n"); return; } else { printf ("BWMNGMT: Example PASSED.\n"); } return; } / * ============================================================================= * @func bwmngmtHwSetupVerify * * @desc * This function compares the hw setup that was configured and that was * returned by CSL_bwmngmtGetHwSetup() of BWMNGMT. * * @arg Pointer to the original configuration * Pointer to the configuration that was returned by * bwmngmtGetHwSetup() * * @eg * CSL_BwmngmtHwSetup hwSetup; * CSL_BwmngmtHwSetup hwSetupRead; * * ...... ; * * bwmngmtHwSetupVerify (hwSetup, hwSetupRead); * ============================================================================= / CSL_Status bwmngmtHwSetupVerify ( CSL_BwmngmtHwSetup hwSetup, CSL_BwmngmtHwSetup hwSetupRead ) { CSL_Status status = CSL_SOK; / Compare each and every filed of hw setup structure and * print the read values. / / Cpu Priority value / if (hwSetup->cpuPriority != hwSetupRead->cpuPriority) { bwmngmtExampleFailed++; } / Cpu Maxwait value / if (hwSetup->cpuMaxwait != hwSetupRead->cpuMaxwait) { bwmngmtExampleFailed++; } / Internal DMA max wait value / if (hwSetup->idmaMaxwait != hwSetupRead->idmaMaxwait) { bwmngmtExampleFailed++; } / Slave Port Max Wait value / if (hwSetup->slapMaxwait != hwSetupRead->slapMaxwait) { bwmngmtExampleFailed++; } / Master Port Priority value / if (hwSetup->mapPriority != hwSetupRead->mapPriority) { bwmngmtExampleFailed++; } / User Coherance Max Wait value */ if (hwSetup->ucMaxwait != hwSetupRead->ucMaxwait) { bwmngmtExampleFailed++; } if (bwmngmtExampleFailed > 0) { status = CSL_ESYS_FAIL; } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/FB_W2100_SCU_MEA256/global.c	#include "global.h" int threshold; int deadtime; int StimAmplitude; int StimDuration; int StimRepeats; int StimStepsize; Uint32 StimulusEnable[HS1_CHANNELS / ELECTRODES_PER_REGISTER]; Uint32 elec_config[HS1_CHANNELS / ELECTRODES_PER_REGISTER]; Uint32 DAC_select[HS1_CHANNELS / (ELECTRODES_PER_REGISTER/2)];
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/common/csl_timerGetBaseAddress.c	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_tmrGetBaseAddress.c * * @path $(CSLPATH)\src\common * * @desc CSL Implementation of CSL_tmrGetBaseAddress * / / ============================================================================= * Revision History * =============== * 1-Sept-2004 HMM File Created. * ============================================================================= / #include <soc.h> #include <csl_tmr.h> /* ============================================================================ * @n@b CSL_tmrGetBaseAddress * * @b Description * @n This function gets the base address of the given gptimer * instance. * * @b Arguments * @verbatim tmrNum Specifies the instance of the gptimer to be opened pTmrParam Gptimer module specific parameters pBaseAddress Pointer to base address structure containing base address details @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_OK Successful on getting the base * address of timer * @li CSL_ESYS_FAIL gptimer instance is not * available. * @li CSL_ESYS_INVPARAMS Invalid Parameters * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Base address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_TmrBaseAddress baseAddress; ... status = CSL_tmrGetBaseAddress(CSL_TMR_1, NULL, &baseAddress); ... @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_tmrGetBaseAddress, ".text:csl_section:tmr"); CSL_Status CSL_tmrGetBaseAddress ( CSL_InstNum tmrNum, CSL_TmrParam pTmrParam, CSL_TmrBaseAddress *pBaseAddress ) { CSL_Status status = CSL_SOK; if (pBaseAddress == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (tmrNum) { case CSL_TMR_0: pBaseAddress->regs = (CSL_TmrRegsOvly)CSL_TMR_0_REGS; break; case CSL_TMR_1: pBaseAddress->regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; break; default: pBaseAddress->regs = (CSL_TmrRegsOvly)NULL; status = CSL_ESYS_FAIL; break; } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/vcp2/vcp2_soft_decisions/src/vcp2_data.c	/* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ========================================================================== / /* =========================================================================== * @file vcp2_data.c * * @path $(CSLPATH)\example\c6455\vcp2\vcp2_soft_decisions\src * * @desc reference VCP2 soft decisions data * * ============================================================================ / #include <csl_vcp2.h> #pragma DATA_SECTION(branch_metric, ".channelBmData") Uint32 branch_metric[] = { 0xfdf92507, 0xf224dd0f, 0x1612ddcb, 0xf22c0816, 0xf8163301, 0xe1efe3f5, 0x2a0005fd, 0xebeb07df, 0xefe701e3, 0x14c8de10, 0xf2eaf927, 0xd3fdee3a, 0xf341e307, 0x0606f2da, 0x1ad20f27, 0x48cce014, 0xf40e061c, 0xe5f1f83c, 0x1b1118ec, 0x1ff30a3e, 0xf23605d9, 0xbc20f6e4, 0xfd23fc12, 0x08eaf539, 0xf0e2d8dc, 0xf9ed01e9, 0xd7f5d7cd, 0x0de11ded, 0xf838d4da, 0x1428eed0, 0xe8ea1002, 0xe5050cdc, 0xfd0d13d5, 0x1cea2917, 0xedbb4509, 0x57053519, 0xea36dffd, 0x2c248100, 0x261cf416, 0xdc2cf808, 0x22ec01eb, 0xf2262202, 0x101406fe, 0xf7fd0d07, 0x0d091517, 0xf4dcdbe1, 0x08f216f0, 0x13fb1f33, 0x02b8f60a, 0xf31fca08, 0x200cd5fd, 0xfbc7dcd8, 0xf2063218, 0xcbfbe129, 0x13fd041c, 0x0fe1e8f8, 0x30ee04f6, 0xd7e918be, 0x18f81d0b, 0xf9130def, 0x06061e2c, 0xefdd04ee, 0xeeeeeae4, 0xd919ffd9, 0xf21a091d, 0xf20229c9, 0xe3f5102c, 0xeded01dd, 0x17f1e804, 0x10f612e0, 0xeb412a08, 0xfe0a0be9, 0x0802edc9, 0x1ed6f21c, 0xe537f10d, 0xeaf21ad4, 0xf9350131, 0x330f1509, 0xdc18eeb6, 0xf8f2f331, 0xdb0b0ce4, 0x02debc30, 0x0cdee6fc, 0x19c926da, 0x4a22210b, 0x1d271412, 0xfae6fdff, 0xfde73218, 0x15c9070b, 0x2905270f, 0x32fac408, 0xdbd71b03, 0x3cf00a04, 0x00f81fe7, 0xf9cde30b, 0x27e902fe, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; / End of branch metrics / Uint32 soft_decisionRef[] = { 0x8080807f, 0x7fc68086, 0x80807e7f, 0x94807f80, 0x8080807f, 0x7f7f807f, 0x7f7f807f, 0x7f807f80, 0x807f7f80, 0x80807f80, 0x807f7f80, 0x807f7f7f, 0x7f7f807f, 0x807f7f80, 0x967f7f80, 0x807f64e4, 0x7f807f7f, 0x7f7f807f, 0x803f7f4c, 0xb8c28080, 0x51975c4a, 0x224e6e6c, 0x7f305480, 0x807f6e80, 0x7f7f8080, 0x807f7f80, 0x7f92907f, 0x7f807f80, 0x327f787f, 0xee3e4ce7, 0x7fc48056, 0x7c7fb87f, 0x7f80607f, 0x807f5480, 0x6a80547f, 0x80ce7678, 0x7f7f7080, 0x7f807f80, 0x7f7a7f80, 0x80807f7f, 0x7f808080, 0x7f807880, 0x80807f7f, 0x8080807f, 0x7f7f7f7f, 0x80808080, 0x0000807f, 0x00000000 }; / End of soft decision reference data / Uint32 soft_decision[] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; / End of soft decisions area */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotGetHwStatus.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_memprotGetHwStatus.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotGetHwStatus () * / / ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * * 16-Nov-2005 ds Updated the documentation * ============================================================================= / #include <csl_memprot.h> #include <csl_memprotAux.h> /* =========================================================================== * @n@b CSL_memprotGetHwStatus * * @b Description * @n This function is used to read the current module configuration, status * flags and the value present associated registers. User should allocate * memory for the said data type and pass its pointer as an unadorned * void* argument to the status query call. For details about the various * status queries supported and the associated data structure to record * the response refer to @a CSL_MemprotHwStatusQuery * * @b Arguments * @verbatim hMemprot Handle to the MEMPROT instance query The query to this API of MEMPROT which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * @li CSL_ESYS_INVQUERY - Invalid Query * * <b> Pre Condition </b> * Both @a CSL_memprotInit() and @a CSL_memprotOpen() must be called * successfully in that order before @a CSL_memprotGetHwStatus() can be * called. For the argument type that can be @a void* casted & passed * with a particular command refer to @a CSL_MemprotHwStatusQuery * * <b> Post Condition </b> * @n None * * @b Modifies * @n Third parameter "response" value * * @b Example * @verbatim #define PAGE_ATTR 0xFFF0 Uint16 pageAttrTable[10] = {PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR, PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR}; Uint32 key[2] = {<KEY>}; CSL_MemprotObj mpL2Obj; CSL_MemprotHandle hmpL2; CSL_Status status; CSL_MemprotHwSetup L2MpSetup,L2MpGetSetup; CSL_MemprotLockStatus lockStat; CSL_MemprotPageAttr pageAttr; CSL_MemprotFaultStatus queryFaultStatus; // Initializing the module CSL_memprotInit(NULL); // Opening the Handle for the L2 hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status); L2MpSetup. memPageAttr = pageAttrTable; L2MpSetup.numPages = 10; L2MpSetup.key = key; // Do Setup for the L2 Memory protection/ CSL_memprotHwSetup (hmpL2,&L2MpSetup); // Query Lock Status CSL_memprotGetHwStatus(hmpL2,CSL_MEMPROT_QUERY_LOCKSTAT,&lockStat); @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_memprotGetHwStatus, ".text:csl_section:memprot") CSL_Status CSL_memprotGetHwStatus ( CSL_MemprotHandle hMemprot, CSL_MemprotHwStatusQuery query, void response ) { CSL_Status status = CSL_SOK; if (hMemprot == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (query) { case CSL_MEMPROT_QUERY_FAULT: CSL_memprotGetFaultStatus(hMemprot, (CSL_MemprotFaultStatus )response); break; case CSL_MEMPROT_QUERY_PAGEATTR: ((CSL_MemprotPageAttr )response)->attr = CSL_memprotGetPageAttr(hMemprot, ((CSL_MemprotPageAttr)response)->page); break; case CSL_MEMPROT_QUERY_LOCKSTAT: ((CSL_MemprotLockStatus *)response) = CSL_memprotGetLockStat(hMemprot); break; default: status = CSL_ESYS_INVQUERY ; } } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcGetHwStatus.c	<filename>DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcGetHwStatus.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_intcGetHwStatus.c * * @brief File for functional layer of CSL API @a CSL_intcGetHwStatus() * * PATH $(CSLPATH)\src\intc / / ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= / #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /* ============================================================================ * @n@b CSL_intcGetHwStatus * * @b Description * @n Queries the peripheral for status. The CSL_intcGetHwStatus(..) API * could be used to retrieve status or configuration information from * the peripheral. The user must allocate an object that would hold * the retrieved information and pass a pointer to it to the function. * The type of the object is specific to the query-command. * * @b Arguments * @verbatim hIntc Handle identifying the event query The query to this API of INTC which indicates the status to be returned. answer Placeholder to return the status. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful * @li CSL_ESYS_INVQUERY - Invalid query * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example: * @verbatim CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; CSL_IntcObj intcObj20; CSL_IntcHandle hIntc20; CSL_IntcEventHandlerRecord recordTable[10]; CSL_IntcGlobalEnableState state; Uint32 intrStat; context.numEvtEntries = 10; context.eventhandlerRecord = &recordTable; // Init Module ... if (CSL_intcInit(&context) != CSL_SOK) exit; // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL); // NMI Enable CSL_intcGlobalNmiEnable(); // Enable Global Interrupts intStat = CSL_intcGlobalEnable(&state); do { CSL_intcGetHwStatus(hIntc20,CSL_INTC_QUERY_PENDSTATUS, \ (void)&intrStat); } while (!stat); // Close handle CSL_IntcClose(hIntc20); @endverbatim ============================================================================= / #pragma CODE_SECTION (CSL_intcGetHwStatus, ".text:csl_section:intc"); CSL_Status CSL_intcGetHwStatus ( CSL_IntcHandle hIntc, CSL_IntcHwStatusQuery myQuery, void answer ) { CSL_Status status = CSL_SOK; if (hIntc && answer) { switch (myQuery) { case CSL_INTC_QUERY_PENDSTATUS: if (hIntc->vectId < CSL_INTC_VECTID_EXCEP) { if (hIntc->eventId < 4) ((Uint32)answer) = \ (Uint32)(CSL_intcCombinedEventGet(hIntc->eventId)); else ((Bool)answer) = \ (Bool)(CSL_intcQueryEventStatus(hIntc->eventId)); } break; default: status = CSL_ESYS_INVQUERY; break; } } else status = CSL_ESYS_INVPARAMS; return status; } /** ============================================================================ * @n@b CSL_intcQueryDropStatus * * @b Description * @n Queries the peripheral for Drop status. The CSL_intcQueryDropStatus(..) * API could be used to retrieve drop status * * @b Arguments * @verbatim drop Pointer to drop status structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful * @li CSL_ESYS_INVPARAMS - Invalid handle * * <b> Pre Condition </b> * @n CSL_intcInit(), CSL_intcOpen() must be invoked before this call * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example: * @verbatim CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; CSL_IntcObj intcObj20; CSL_IntcHandle hIntc20; CSL_IntcDropStatus drop; CSL_IntcEventHandlerRecord recordTable[10]; CSL_IntcGlobalEnableState state; Uint32 intrStat; context.numEvtEntries = 10; context.eventhandlerRecord = &recordTable; // Init Module ... if (CSL_intcInit(&context) != CSL_SOK) exit; // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL); // Drop Enable CSL_intHwControl(hIntc20,CSL_INTC_CMD_EVTDROPENABLE,NULL); // Query Drop status CSL_intcQueryDropStatus(&drop); // Close handle CSL_IntcClose(hIntc20); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_intcQueryDropStatus, ".text:csl_section:intc"); CSL_Status CSL_intcQueryDropStatus ( CSL_IntcDropStatus drop ) { Uint32 dropVal; CSL_Status status = CSL_ESYS_INVPARAMS ; if (drop) { dropVal = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTXSTAT; drop->drop = (Bool)(CSL_FEXT(dropVal,INTC_INTXSTAT_DROP)); drop->eventId = (CSL_IntcEventId)(CSL_FEXT(dropVal,INTC_INTXSTAT_SYSINT)); drop->vectId = (CSL_IntcVectId)(CSL_FEXT(dropVal,INTC_INTXSTAT_CPUINT)); /* Clear the drop condition */ ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTXCLR = 1; status = CSL_SOK; } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotInit.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_memprotInit.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotInit () * / / ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * * 16-Nov-2005 ds Updated the documentation * ============================================================================= / #include <csl_memprot.h> /* =========================================================================== * @n@b CSL_memprotInit * * @b Description * @n This is the initialization function for the MEMPROT. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. The function must be called before calling any other API from * this CSL. * * @b Arguments @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * This function should be called before using any of the CSL APIs * in the Memory Protection module. * * Note: As Memory Protection doesn't have any context based information, * the function just returns CSL_SOK. User is expected to pass NULL. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... CSL_memprotInit(); @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_memprotInit, ".text:csl_section:memprot"); CSL_Status CSL_memprotInit ( CSL_MemprotContext pContext ) { /* If the module is already initialized, then error is * returned as init done(CSL_EINITDONE). If the user * needs to force init more than once, then set the * global Context pointer to NULL and invoke CSL_memprotInit() */ return CSL_SOK; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_pwrdwnL2.h	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_pwrdwnL2.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for L2PWRDWN / #ifndef _CSLR_PWRDWNL2_H_ #define _CSLR_PWRDWNL2_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint8 RSVD0[64]; volatile Uint32 L2PDWAKE[2]; volatile Uint8 RSVD1[8]; volatile Uint32 L2PDSLEEP[2]; volatile Uint8 RSVD2[8]; volatile Uint32 L2PDSTAT[2]; } CSL_L2pwrdwnRegs; /***********************************************************************\ Overlay structure typedef definition \*************************************************************************/ typedef volatile CSL_L2pwrdwnRegs CSL_L2pwrdwnRegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / L2PDWAKE / #define CSL_L2PWRDWN_L2PDWAKE_P1_MASK (0x00000002u) #define CSL_L2PWRDWN_L2PDWAKE_P1_SHIFT (0x00000001u) #define CSL_L2PWRDWN_L2PDWAKE_P1_RESETVAL (0x00000000u) /----P1 Tokens----/ #define CSL_L2PWRDWN_L2PDWAKE_P1_DISABLE (0x00000000u) #define CSL_L2PWRDWN_L2PDWAKE_P1_ENABLE (0x00000001u) #define CSL_L2PWRDWN_L2PDWAKE_P0_MASK (0x00000001u) #define CSL_L2PWRDWN_L2PDWAKE_P0_SHIFT (0x00000000u) #define CSL_L2PWRDWN_L2PDWAKE_P0_RESETVAL (0x00000000u) /----P0 Tokens----/ #define CSL_L2PWRDWN_L2PDWAKE_P0_DISABLE (0x00000000u) #define CSL_L2PWRDWN_L2PDWAKE_P0_ENABLE (0x00000001u) #define CSL_L2PWRDWN_L2PDWAKE_RESETVAL (0x00000000u) / L2PDSLEEP / #define CSL_L2PWRDWN_L2PDSLEEP_P1_MASK (0x00000002u) #define CSL_L2PWRDWN_L2PDSLEEP_P1_SHIFT (0x00000001u) #define CSL_L2PWRDWN_L2PDSLEEP_P1_RESETVAL (0x00000000u) /----P1 Tokens----/ #define CSL_L2PWRDWN_L2PDSLEEP_P1_DISABLE (0x00000000u) #define CSL_L2PWRDWN_L2PDSLEEP_P1_ENABLE (0x00000001u) #define CSL_L2PWRDWN_L2PDSLEEP_P0_MASK (0x00000001u) #define CSL_L2PWRDWN_L2PDSLEEP_P0_SHIFT (0x00000000u) #define CSL_L2PWRDWN_L2PDSLEEP_P0_RESETVAL (0x00000000u) /----P0 Tokens----/ #define CSL_L2PWRDWN_L2PDSLEEP_P0_DISABLE (0x00000000u) #define CSL_L2PWRDWN_L2PDSLEEP_P0_ENABLE (0x00000001u) #define CSL_L2PWRDWN_L2PDSLEEP_RESETVAL (0x00000000u) / L2PDSTAT */ #define CSL_L2PWRDWN_L2PDSTAT_P1_MASK (0x00000002u) #define CSL_L2PWRDWN_L2PDSTAT_P1_SHIFT (0x00000001u) #define CSL_L2PWRDWN_L2PDSTAT_P1_RESETVAL (0x00000000u) #define CSL_L2PWRDWN_L2PDSTAT_P0_MASK (0x00000001u) #define CSL_L2PWRDWN_L2PDSTAT_P0_SHIFT (0x00000000u) #define CSL_L2PWRDWN_L2PDSTAT_P0_RESETVAL (0x00000000u) #define CSL_L2PWRDWN_L2PDSTAT_RESETVAL (0x00000000u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/dat/csl_dat.c	<filename>DSP/TI-Header/csl_c6455_src/src/dat/csl_dat.c /** =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_dat.c * * @desc This file defines the functions in the DAT module. * * @path $(CSLPATH)\src\dat / / ============================================================================= * Revision History * =============== * 14-Nov-2005 ds File modified - In the APIs DAT_copy(), DAT_copy2d(), * DAT_fill() added macro to set the STATIC when * OPT is programmed. * ============================================================================= / #include <csl_dat.h> #include <_csl_dat.h> /* ============================================================================ * @n@b DAT_open * * @b Description * @n This API * a. Sets up the channel to Parameter set mapping \n * b. Sets up the priority. This is essentially done by specifying the * queue to which the channel is submitted to viz Queue0- Queue7. * Queue 0 being the highest priority. \n * c. Enables the region access bit for the channel if a region is * specified. * * @b Arguments @verbatim setup Pointer to the DAT setup structure @endverbatim * * <b> Return Value </b> CSL_SOK * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The EDMA registers are configured with the setup values passed. * * @b Modifies * @n None * * @b Example * @verbatim DAT_Setup datSetup; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); @endverbatim * =========================================================================== / #pragma CODE_SECTION (DAT_open, ".text:csl_section:dat"); Int16 DAT_open ( DAT_Setup setup ) { Uint32 cs; /* Enter critical section / cs = _disable_interrupts (); _CSL_datStateStruct.qchNum = setup->qchNum; _CSL_datStateStruct.regionNum = setup->regionNum; _CSL_datStateStruct.tccNum = setup->tccNum; _CSL_datStateStruct.priority = setup->priority; _CSL_datStateStruct.paramNum = setup->paramNum; _CSL_datStateStruct.pending = FALSE; / the que entry number mapping / CSL_FINSR (((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QDMAQNUM, setup->qchNum 4 + 2, setup->qchNum * 4, setup->priority); /* The parameter set mapping / ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QCHMAP[setup->qchNum] = CSL_FMK (EDMA3CC_QCHMAP_PAENTRY, setup->paramNum) \| CSL_FMK (EDMA3CC_QCHMAP_TRWORD, 7); / Enable the DRAE Bit / if (setup->regionNum != CSL_DAT_REGION_GLOBAL) { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QRAE[setup->regionNum] \|= (1 << setup->qchNum); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[setup->regionNum].QEESR = (1 << setup->qchNum); } else { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QEESR = (1 << setup->qchNum); } / Leave critical section / _restore_interrupts (cs); return CSL_SOK; } /* ============================================================================ * @n@b DAT_close * * @b Description * @n This API * a. Disables the region access bit if specified. * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n DAT_open() must be successfully invoked prior to this call. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim DAT_Setup datSetup; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... DAT_close(); @endverbatim * =========================================================================== / #pragma CODE_SECTION (DAT_close, ".text:csl_section:dat"); void DAT_close (void) { Uint32 cs; if (_CSL_datStateStruct.regionNum != CSL_DAT_REGION_GLOBAL) { cs = _disable_interrupts (); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QRAE[_CSL_datStateStruct.regionNum] &= ~(1 << _CSL_datStateStruct.qchNum); _restore_interrupts (cs); } } /* ============================================================================ * @n@b DAT_copy * * @b Description * @n This API copies data from source to destination for one dimension * transfer. * * @b Arguments @verbatim src Source memory address for the data transfer dst Destination memory address of the data transfer byteCnt Number of bytes to be transferred @endverbatim * * <b> Return Value </b> tccNum * * <b> Pre Condition </b> * @n DAT_open() must be successfully invoked prior to this call. * * <b> Post Condition </b> * @n The EDMA registers are configured to transfer byteCnt bytes from the * source memory address to the destination memory address * * @b Modifies * @n EDMA registers * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst1d[816]; Uint8 src1d[816]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... DAT_copy(&src1d,&dst1d,256); ... DAT_close(); @endverbatim * =========================================================================== / #pragma CODE_SECTION (DAT_copy, ".text:csl_section:dat"); Uint32 DAT_copy ( void src, void dst, Uint16 byteCnt ) { volatile CSL_Edma3ccParamsetRegs param; Uint32 cs; cs = _disable_interrupts (); param = &((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->PARAMSET[_CSL_datStateStruct.paramNum]; if (_CSL_datStateStruct.pending) DAT_wait (_CSL_datStateStruct.tccNum); /* The options in the param set programmed need to have STATIC = 1. * If STATIC != 1 then when QDMA links to NULL SER will get set causing * further issue of Transfer requests / param->OPT = CSL_FMKT (EDMA3CC_OPT_TCINTEN, ENABLE) \| CSL_FMK (EDMA3CC_OPT_TCC, _CSL_datStateStruct.tccNum) \| CSL_FMKT (EDMA3CC_OPT_STATIC, STATIC); param->SRC = (Uint32) (src); param->A_B_CNT = CSL_FMK (EDMA3CC_A_B_CNT_ACNT, byteCnt) \| CSL_FMK (EDMA3CC_A_B_CNT_BCNT, 1); param->DST = (Uint32) (dst); param->LINK_BCNTRLD = CSL_FMK (EDMA3CC_LINK_BCNTRLD_LINK, 0xFFFF); param->CCNT = 0x00000001; _CSL_datStateStruct.pending = TRUE; _restore_interrupts (cs); return _CSL_datStateStruct.tccNum; } /* ============================================================================ * @n@b DAT_fill * * @b Description * @n This API fill destination by given fill value. * * @b Arguments @verbatim dst Destination memory address to be filled byteCnt Number of bytes to be filled value Value to be filled @endverbatim * * <b> Return Value </b> tccNum * * <b> Pre Condition </b> * @n DAT_open() must be successfully invoked prior to this call. * * <b> Post Condition </b> * @n The EDMA registers are configured to transfer a value to byteCnt bytes * of the destination memory address * * @b Modifies * @n EDMA registers * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst[816]; Uint8 fillVal; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... fillVal = 0x5a; DAT_fill(&dst,256,&fillval); ... DAT_close(); @endverbatim =========================================================================== / #pragma CODE_SECTION (DAT_fill, ".text:csl_section:dat"); Uint32 DAT_fill ( void dst, Uint16 byteCnt, Uint32 value ) { volatile CSL_Edma3ccParamsetRegs param; Uint32 cs; cs = _disable_interrupts (); param = &((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->PARAMSET[_CSL_datStateStruct.paramNum]; if (_CSL_datStateStruct.pending) DAT_wait (_CSL_datStateStruct.tccNum); /* The options in the param set programmed need to have STATIC = 1. * If STATIC != 1 then when QDMA links to NULL SER will get set causing * further issue of Transfer requests / param->OPT = CSL_FMKT (EDMA3CC_OPT_TCINTEN, ENABLE) \| CSL_FMK (EDMA3CC_OPT_TCC, _CSL_datStateStruct.tccNum) \| CSL_FMKT (EDMA3CC_OPT_SYNCDIM, ABSYNC) \| CSL_FMKT (EDMA3CC_OPT_STATIC, STATIC); param->SRC = (Uint32) (value); param->A_B_CNT = CSL_FMK (EDMA3CC_A_B_CNT_ACNT, 1) \| CSL_FMK (EDMA3CC_A_B_CNT_BCNT, byteCnt); param->DST = (Uint32) (dst); param->SRC_DST_BIDX = CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, 1) \| CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0); param->LINK_BCNTRLD = CSL_FMK (EDMA3CC_LINK_BCNTRLD_LINK, 0xFFFF); param->CCNT = 0x00000001; _CSL_datStateStruct.pending = TRUE; _restore_interrupts (cs); return _CSL_datStateStruct.tccNum; } /* ============================================================================ * @n@b DAT_wait * * @b Description * @n This API Waits for completion of the ongoing transfer. * * @b Arguments @verbatim id Channel number of the previous transfer @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n DAT_copy()/DAT_fill must be successfully invoked prior to this call. * * <b> Post Condition </b> * @n Indicates that the transfer ongoing is complete * * @b Modifies * @n None * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst1d[816]; Uint8 src1d[816]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... id = DAT_copy(&src1d,&dst1d,256); DAT_wait(id); ... DAT_close(); @endverbatim * =========================================================================== / #pragma CODE_SECTION (DAT_wait, ".text:csl_section:dat"); void DAT_wait ( Uint32 id ) { Uint32 cs; cs = _disable_interrupts (); if (_CSL_datStateStruct.regionNum != CSL_DAT_REGION_GLOBAL) { if (_CSL_datStateStruct.tccNum < 32) { while (!(((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct. regionNum].IPR & (1 << _CSL_datStateStruct.tccNum))); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum].ICR = (1 << _CSL_datStateStruct.tccNum); } else { while (!(((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct. regionNum].IPRH & (1 << (_CSL_datStateStruct.tccNum - 32)))); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum]. ICRH = (1 << _CSL_datStateStruct.tccNum - 32); } } else { if (_CSL_datStateStruct.tccNum < 32) { while (!(((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->IPR & (1 << _CSL_datStateStruct.tccNum))); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ICR = (1 << _CSL_datStateStruct.tccNum); } else { while (!(((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->IPRH & (1 << (_CSL_datStateStruct.tccNum - 32)))); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ICRH = (1 << _CSL_datStateStruct.tccNum - 32); } } _CSL_datStateStruct.pending = FALSE; _restore_interrupts (cs); } /* ============================================================================ * @n@b DAT_busy * * @b Description * @n This API polls for transfer completion. * * @b Arguments @verbatim id Channel number of the previous transfer @endverbatim * * <b> Return Value </b> Int16 * TRUE/FALSE * * <b> Pre Condition </b> * @n DAT_copy()/DAT_fill must be successfully invoked prior to this call. * * <b> Post Condition </b> * @n Indicates that the transfer ongoing is complete * * @b Modifies * @n None * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst1d[816]; Uint8 src1d[816]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... id = DAT_copy(&src1d,&dst1d,256); do { ... }while (DAT_busy(id)); ... DAT_close(); @endverbatim * ============================================================================ / #pragma CODE_SECTION (DAT_busy, ".text:csl_section:dat"); Int16 DAT_busy ( Uint32 id ) { Bool status = TRUE; Uint32 temp; Uint32 cs; cs = _disable_interrupts (); / The number 32 signifies lower 32 channels / if (_CSL_datStateStruct.regionNum != CSL_DAT_REGION_GLOBAL) { if (_CSL_datStateStruct.tccNum < 32) { temp = ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum].IPR & (1 << _CSL_datStateStruct.tccNum); } else { temp = ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum]. IPRH & (1 << (_CSL_datStateStruct.tccNum - 32)); } } else { if (_CSL_datStateStruct.tccNum < 32) { temp = ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->IPR & (1 << _CSL_datStateStruct.tccNum); } else { temp = ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->IPRH & (1 << (_CSL_datStateStruct.tccNum - 32)); } } if (temp) { if (_CSL_datStateStruct.regionNum != CSL_DAT_REGION_GLOBAL) { if (_CSL_datStateStruct.tccNum < 32) { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum]. ICR = (1 << _CSL_datStateStruct.tccNum); } else { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum]. ICRH = (1 << (_CSL_datStateStruct.tccNum - 32)); } } else { if (_CSL_datStateStruct.tccNum < 32) { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ICR = (1 << _CSL_datStateStruct.tccNum); } else { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ICRH = (1 << (_CSL_datStateStruct.tccNum - 32)); } } _CSL_datStateStruct.pending = FALSE; status = FALSE; } _restore_interrupts (cs); return status; } /* ============================================================================ * @n@b DAT_copy2d * * @b Description * @n This API copies data from source to destination for two dimension * transfer. * * @b Arguments @verbatim type Indicates the type of the transfer DAT_1D2D - 1 dimension to 2 dimension DAT_2D1D - 2 dimension to 1 dimension DAT_2D2D - 2 dimension to 2 dimension src Source memory address for the data transfer dst Destination memory address of the data transfer lineLen Number of bytes per line lineCnt Number of lines linePitch Number of bytes between start of one line to start of next line @endverbatim * * <b> Return Value </b> tccNum * * <b> Pre Condition </b> * @n DAT_open() must be successfully invoked prior to this call. * * <b> Post Condition </b> * @n The EDMA registers are configured for the transfer * * @b Modifies * @n EDMA registers * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst2d[8][20]; Uint8 src1d[816]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... id = DAT_copy2d(DAT_1D2D,src1d,dst2d,16,8,20); do { ... }while (DAT_busy(id)); ... DAT_close(); @endverbatim =========================================================================== / #pragma CODE_SECTION (DAT_copy2d, ".text:csl_section:dat"); Uint32 DAT_copy2d ( Uint32 type, void src, void dst, Uint16 lineLen, Uint16 lineCnt, Uint16 linePitch ) { volatile CSL_Edma3ccParamsetRegs param; Uint32 cs; cs = _disable_interrupts (); param = &((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->PARAMSET[_CSL_datStateStruct.paramNum]; if (_CSL_datStateStruct.pending) DAT_wait (_CSL_datStateStruct.tccNum); /* The options in the param set programmed need to have STATIC = 1. * If STATIC != 1 then when QDMA links to NULL SER will get set causing * further issue of Transfer requests / param->OPT = CSL_FMKT (EDMA3CC_OPT_TCINTEN, ENABLE) \| CSL_FMK (EDMA3CC_OPT_TCC, _CSL_datStateStruct.tccNum) \| CSL_FMKT (EDMA3CC_OPT_SYNCDIM, ABSYNC) \| CSL_FMKT (EDMA3CC_OPT_STATIC, STATIC); param->SRC = (Uint32) (src); param->A_B_CNT = CSL_FMK (EDMA3CC_A_B_CNT_ACNT, lineLen) \| CSL_FMK (EDMA3CC_A_B_CNT_BCNT, lineCnt); param->DST = (Uint32) (dst); if (type == DAT_2D2D) { param->SRC_DST_BIDX = CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, linePitch) \| CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, linePitch); } else { if (type == DAT_1D2D) { param->SRC_DST_BIDX = CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, linePitch) \| CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, lineLen); } else { if (type == DAT_2D1D) { param->SRC_DST_BIDX = CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, lineLen) \| CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, linePitch); } } } param->LINK_BCNTRLD = CSL_FMK (EDMA3CC_LINK_BCNTRLD_LINK, 0xFFFF); param->CCNT = 0x00000001; _CSL_datStateStruct.pending = TRUE; _restore_interrupts (cs); return _CSL_datStateStruct.tccNum; } /* ============================================================================ * @n@b DAT_setPriority * * @b Description * @n Sets the priority bit value PRI of OPT register. The priority value * can be set by using the type CSL_DatPriority. * * @b Arguments @verbatim priority priority value @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n DAT_open must be successfully invoked prior to this call. * * <b> Post Condition </b> * @n OPT register is set for the priority value * * @b Modifies * @n OPT register * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst2d[8][20]; Uint8 src1d[816]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... DAT_setPriority(CSL_DAT_PRI_3); @endverbatim ============================================================================ / #pragma CODE_SECTION (DAT_setPriority, ".text:csl_section:dat"); void DAT_setPriority ( Int priority ) { Uint32 cs; if (_CSL_datStateStruct.pending) DAT_wait (_CSL_datStateStruct.tccNum); cs = _disable_interrupts (); / The que entry number mapping / / The numbers 4 and 2 used to calculate the MSB and LSB of qdma Qnumber / CSL_FINSR (((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QDMAQNUM, _CSL_datStateStruct.qchNum 4 + 2, _CSL_datStateStruct.qchNum * 4, priority); _CSL_datStateStruct.priority = priority; _restore_interrupts (cs); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnGetHwSetup.c	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_pwrdwnGetHwSetup.c * * @path $(CSLPATH)\src\pwrdwn * * @desc File for functional layer of CSL API CSL_pwrdwnGetHwSetup () * / / ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * ============================================================================= / #include <csl_pwrdwn.h> /* =========================================================================== * @n@b CSL_pwrdwnGetHwSetup * * @b Description * @n It retrives the hardware setup parameters * * @b Arguments * @verbatim hPwr Handle to the PWRDWN instance hwSetup Pointer to hardware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup retrived * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @b CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call. * * <b> Post Condition </b> * @n The hardware set up structure will be populated with values from * the registers * * @b Modifies * @n None * * @b Example @verbatim CSL_PwrdwnObj pwrObj; CSL_PwrdwnHwSetup pwrSetup, querySetup; CSL_PwrdwnHandle hPwr; // Init Module ... if (CSL_pwrdwnInit(NULL) != CSL_SOK) exit; // Opening a handle for the Module hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL); // Setup the arguments for the Setup structure ... // Setup CSL_pwrdwnHwSetup(hPwr,&pwrSetup); // Query Setup CSL_pwrdwnGetHwSetup(hPwr,&querySetup); // Close handle CSL_pwrdwnClose(hPwr); @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_pwrdwnGetHwSetup, ".text:csl_section:pwrdwn"); CSL_Status CSL_pwrdwnGetHwSetup ( CSL_PwrdwnHandle hPwrdwn, CSL_PwrdwnHwSetup setup ) { CSL_Status status = CSL_SOK; /* This is a pointer to the registers of the instance of L2 PWRDWN * referred to by this object */ if (hPwrdwn == NULL) { status = CSL_ESYS_BADHANDLE; } else if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else { setup->idlePwrdwn = (Bool)CSL_FEXT(hPwrdwn->pdcRegs->PDCCMD, \ PDC_PDCCMD_MEGPD); if (setup->manualPwrdwn) { setup->manualPwrdwn->port0PageWake = CSL_FEXTR(hPwrdwn->l2pwrdwnRegs->L2PDWAKE[0], 2, 0); setup->manualPwrdwn->port1PageWake = CSL_FEXTR(hPwrdwn->l2pwrdwnRegs->L2PDWAKE[1], 2, 0); setup->manualPwrdwn->port0PageSleep = CSL_FEXTR(hPwrdwn->l2pwrdwnRegs->L2PDSLEEP[0], 2, 0); setup->manualPwrdwn->port1PageSleep = CSL_FEXTR(hPwrdwn->l2pwrdwnRegs->L2PDSLEEP[1], 2, 0); } } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_pllc.h	<filename>DSP/TI-Header/csl_c6455_src/inc/cslr_pllc.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_pllc.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for PLLC / #ifndef _CSLR_PLLC_H_ #define _CSLR_PLLC_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint8 RSVD0[228]; volatile Uint32 RSTYPE; volatile Uint8 RSVD1[24]; volatile Uint32 PLLCTL; volatile Uint8 RSVD2[12]; volatile Uint32 PLLM; volatile Uint32 PREDIV; volatile Uint32 PLLDIV1; volatile Uint8 RSVD3[28]; volatile Uint32 PLLCMD; volatile Uint32 PLLSTAT; volatile Uint32 ALNCTL; volatile Uint32 DCHANGE; volatile Uint8 RSVD4[8]; volatile Uint32 SYSTAT; volatile Uint8 RSVD5[12]; volatile Uint32 PLLDIV4; volatile Uint32 PLLDIV5; } CSL_PllcRegs; /***********************************************************************\ Overlay structure typedef definition \*************************************************************************/ typedef volatile CSL_PllcRegs CSL_PllcRegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / RSTYPE / #define CSL_PLLC_RSTYPE_SRST_MASK (0x00000008u) #define CSL_PLLC_RSTYPE_SRST_SHIFT (0x00000003u) #define CSL_PLLC_RSTYPE_SRST_RESETVAL (0x00000000u) /----SRST Tokens----/ #define CSL_PLLC_RSTYPE_SRST_NO (0x00000000u) #define CSL_PLLC_RSTYPE_SRST_YES (0x00000001u) #define CSL_PLLC_RSTYPE_MRST_MASK (0x00000004u) #define CSL_PLLC_RSTYPE_MRST_SHIFT (0x00000002u) #define CSL_PLLC_RSTYPE_MRST_RESETVAL (0x00000000u) /----MRST Tokens----/ #define CSL_PLLC_RSTYPE_MRST_NO (0x00000000u) #define CSL_PLLC_RSTYPE_MRST_YES (0x00000001u) #define CSL_PLLC_RSTYPE_WRST_MASK (0x00000002u) #define CSL_PLLC_RSTYPE_WRST_SHIFT (0x00000001u) #define CSL_PLLC_RSTYPE_WRST_RESETVAL (0x00000000u) /----WRST Tokens----/ #define CSL_PLLC_RSTYPE_WRST_NO (0x00000000u) #define CSL_PLLC_RSTYPE_WRST_YES (0x00000001u) #define CSL_PLLC_RSTYPE_POR_MASK (0x00000001u) #define CSL_PLLC_RSTYPE_POR_SHIFT (0x00000000u) #define CSL_PLLC_RSTYPE_POR_RESETVAL (0x00000000u) /----POR Tokens----/ #define CSL_PLLC_RSTYPE_POR_NO (0x00000000u) #define CSL_PLLC_RSTYPE_POR_YES (0x00000001u) #define CSL_PLLC_RSTYPE_RESETVAL (0x00000000u) / PLLCTL / #define CSL_PLLC_PLLCTL_PLLENSRC_MASK (0x00000020u) #define CSL_PLLC_PLLCTL_PLLENSRC_SHIFT (0x00000005u) #define CSL_PLLC_PLLCTL_PLLENSRC_RESETVAL (0x00000000u) /----PLLENSRC Tokens----/ #define CSL_PLLC_PLLCTL_PLLENSRC_REGBIT (0x00000000u) #define CSL_PLLC_PLLCTL_PLLENSRC_NONREGBIT (0x00000001u) #define CSL_PLLC_PLLCTL_PLLRST_MASK (0x00000008u) #define CSL_PLLC_PLLCTL_PLLRST_SHIFT (0x00000003u) #define CSL_PLLC_PLLCTL_PLLRST_RESETVAL (0x00000001u) /----PLLRST Tokens----/ #define CSL_PLLC_PLLCTL_PLLRST_NO (0x00000000u) #define CSL_PLLC_PLLCTL_PLLRST_YES (0x00000001u) #define CSL_PLLC_PLLCTL_PLLPWRDN_MASK (0x00000002u) #define CSL_PLLC_PLLCTL_PLLPWRDN_SHIFT (0x00000001u) #define CSL_PLLC_PLLCTL_PLLPWRDN_RESETVAL (0x00000000u) /----PLLPWRDN Tokens----/ #define CSL_PLLC_PLLCTL_PLLPWRDN_NO (0x00000000u) #define CSL_PLLC_PLLCTL_PLLPWRDN_YES (0x00000001u) #define CSL_PLLC_PLLCTL_PLLEN_MASK (0x00000001u) #define CSL_PLLC_PLLCTL_PLLEN_SHIFT (0x00000000u) #define CSL_PLLC_PLLCTL_PLLEN_RESETVAL (0x00000000u) /----PLLEN Tokens----/ #define CSL_PLLC_PLLCTL_PLLEN_BYPASS (0x00000000u) #define CSL_PLLC_PLLCTL_PLLEN_PLL (0x00000001u) #define CSL_PLLC_PLLCTL_RESETVAL (0x00000048u) / PLLM / #define CSL_PLLC_PLLM_PLLM_MASK (0x0000003Fu) #define CSL_PLLC_PLLM_PLLM_SHIFT (0x00000000u) #define CSL_PLLC_PLLM_PLLM_RESETVAL (0x00000000u) #define CSL_PLLC_PLLM_RESETVAL (0x00000000u) / PREDIV / #define CSL_PLLC_PREDIV_PREDEN_MASK (0x00008000u) #define CSL_PLLC_PREDIV_PREDEN_SHIFT (0x0000000Fu) #define CSL_PLLC_PREDIV_PREDEN_RESETVAL (0x00000001u) /----PREDEN Tokens----/ #define CSL_PLLC_PREDIV_PREDEN_DISABLE (0x00000000u) #define CSL_PLLC_PREDIV_PREDEN_ENABLE (0x00000001u) #define CSL_PLLC_PREDIV_RATIO_MASK (0x0000001Fu) #define CSL_PLLC_PREDIV_RATIO_SHIFT (0x00000000u) #define CSL_PLLC_PREDIV_RATIO_RESETVAL (0x00000002u) #define CSL_PLLC_PREDIV_RESETVAL (0x00008002u) / PLLDIV1 / #define CSL_PLLC_PLLDIV1_D1EN_MASK (0x00008000u) #define CSL_PLLC_PLLDIV1_D1EN_SHIFT (0x0000000Fu) #define CSL_PLLC_PLLDIV1_D1EN_RESETVAL (0x00000001u) /----D1EN Tokens----/ #define CSL_PLLC_PLLDIV1_D1EN_DISABLE (0x00000000u) #define CSL_PLLC_PLLDIV1_D1EN_ENABLE (0x00000001u) #define CSL_PLLC_PLLDIV1_RATIO_MASK (0x0000001Fu) #define CSL_PLLC_PLLDIV1_RATIO_SHIFT (0x00000000u) #define CSL_PLLC_PLLDIV1_RATIO_RESETVAL (0x00000001u) /----RATIO Tokens----/ #define CSL_PLLC_PLLDIV1_RATIO_DIV2 (0x00000001u) #define CSL_PLLC_PLLDIV1_RATIO_DIV5 (0x00000004u) #define CSL_PLLC_PLLDIV1_RESETVAL (0x00008001u) / PLLCMD / #define CSL_PLLC_PLLCMD_GOSET_MASK (0x00000001u) #define CSL_PLLC_PLLCMD_GOSET_SHIFT (0x00000000u) #define CSL_PLLC_PLLCMD_GOSET_RESETVAL (0x00000000u) /----GOSET Tokens----/ #define CSL_PLLC_PLLCMD_GOSET_CLRBIT (0x00000000u) #define CSL_PLLC_PLLCMD_GOSET_SET (0x00000001u) #define CSL_PLLC_PLLCMD_RESETVAL (0x00000000u) / PLLSTAT / #define CSL_PLLC_PLLSTAT_GOSTAT_MASK (0x00000001u) #define CSL_PLLC_PLLSTAT_GOSTAT_SHIFT (0x00000000u) #define CSL_PLLC_PLLSTAT_GOSTAT_RESETVAL (0x00000000u) /----GOSTAT Tokens----/ #define CSL_PLLC_PLLSTAT_GOSTAT_NONE (0x00000000u) #define CSL_PLLC_PLLSTAT_GOSTAT_INPROG (0x00000001u) #define CSL_PLLC_PLLSTAT_RESETVAL (0x00000000u) / ALNCTL / #define CSL_PLLC_ALNCTL_ALN5_MASK (0x00000010u) #define CSL_PLLC_ALNCTL_ALN5_SHIFT (0x00000004u) #define CSL_PLLC_ALNCTL_ALN5_RESETVAL (0x00000001u) /----ALN5 Tokens----/ #define CSL_PLLC_ALNCTL_ALN5_NO (0x00000000u) #define CSL_PLLC_ALNCTL_ALN5_YES (0x00000001u) #define CSL_PLLC_ALNCTL_ALN4_MASK (0x00000008u) #define CSL_PLLC_ALNCTL_ALN4_SHIFT (0x00000003u) #define CSL_PLLC_ALNCTL_ALN4_RESETVAL (0x00000001u) /----ALN4 Tokens----/ #define CSL_PLLC_ALNCTL_ALN4_NO (0x00000000u) #define CSL_PLLC_ALNCTL_ALN4_YES (0x00000001u) #define CSL_PLLC_ALNCTL_ALN1_MASK (0x00000001u) #define CSL_PLLC_ALNCTL_ALN1_SHIFT (0x00000000u) #define CSL_PLLC_ALNCTL_ALN1_RESETVAL (0x00000001u) /----ALN1 Tokens----/ #define CSL_PLLC_ALNCTL_ALN1_NO (0x00000000u) #define CSL_PLLC_ALNCTL_ALN1_YES (0x00000001u) #define CSL_PLLC_ALNCTL_RESETVAL (0x00000019u) / DCHANGE / #define CSL_PLLC_DCHANGE_SYS5_MASK (0x00000010u) #define CSL_PLLC_DCHANGE_SYS5_SHIFT (0x00000004u) #define CSL_PLLC_DCHANGE_SYS5_RESETVAL (0x00000000u) /----SYS5 Tokens----/ #define CSL_PLLC_DCHANGE_SYS5_NO (0x00000000u) #define CSL_PLLC_DCHANGE_SYS5_YES (0x00000001u) #define CSL_PLLC_DCHANGE_SYS4_MASK (0x00000008u) #define CSL_PLLC_DCHANGE_SYS4_SHIFT (0x00000003u) #define CSL_PLLC_DCHANGE_SYS4_RESETVAL (0x00000000u) /----SYS4 Tokens----/ #define CSL_PLLC_DCHANGE_SYS4_NO (0x00000000u) #define CSL_PLLC_DCHANGE_SYS4_YES (0x00000001u) #define CSL_PLLC_DCHANGE_SYS1_MASK (0x00000001u) #define CSL_PLLC_DCHANGE_SYS1_SHIFT (0x00000000u) #define CSL_PLLC_DCHANGE_SYS1_RESETVAL (0x00000000u) /----SYS1 Tokens----/ #define CSL_PLLC_DCHANGE_SYS1_NO (0x00000000u) #define CSL_PLLC_DCHANGE_SYS1_YES (0x00000001u) #define CSL_PLLC_DCHANGE_RESETVAL (0x00000000u) / SYSTAT / #define CSL_PLLC_SYSTAT_SYS5ON_MASK (0x00000010u) #define CSL_PLLC_SYSTAT_SYS5ON_SHIFT (0x00000004u) #define CSL_PLLC_SYSTAT_SYS5ON_RESETVAL (0x00000001u) /----SYS5ON Tokens----/ #define CSL_PLLC_SYSTAT_SYS5ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS5ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_SYS4ON_MASK (0x00000008u) #define CSL_PLLC_SYSTAT_SYS4ON_SHIFT (0x00000003u) #define CSL_PLLC_SYSTAT_SYS4ON_RESETVAL (0x00000001u) /----SYS4ON Tokens----/ #define CSL_PLLC_SYSTAT_SYS4ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS4ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_SYS3ON_MASK (0x00000004u) #define CSL_PLLC_SYSTAT_SYS3ON_SHIFT (0x00000002u) #define CSL_PLLC_SYSTAT_SYS3ON_RESETVAL (0x00000001u) /----SYS3ON Tokens----/ #define CSL_PLLC_SYSTAT_SYS3ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS3ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_SYS2ON_MASK (0x00000002u) #define CSL_PLLC_SYSTAT_SYS2ON_SHIFT (0x00000001u) #define CSL_PLLC_SYSTAT_SYS2ON_RESETVAL (0x00000001u) /----SYS2ON Tokens----/ #define CSL_PLLC_SYSTAT_SYS2ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS2ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_SYS1ON_MASK (0x00000001u) #define CSL_PLLC_SYSTAT_SYS1ON_SHIFT (0x00000000u) #define CSL_PLLC_SYSTAT_SYS1ON_RESETVAL (0x00000001u) /----SYS1ON Tokens----/ #define CSL_PLLC_SYSTAT_SYS1ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS1ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_RESETVAL (0x0000001Fu) / PLLDIV4 / #define CSL_PLLC_PLLDIV4_D4EN_MASK (0x00008000u) #define CSL_PLLC_PLLDIV4_D4EN_SHIFT (0x0000000Fu) #define CSL_PLLC_PLLDIV4_D4EN_RESETVAL (0x00000001u) /----D4EN Tokens----/ #define CSL_PLLC_PLLDIV4_D4EN_DISABLE (0x00000000u) #define CSL_PLLC_PLLDIV4_D4EN_ENABLE (0x00000001u) #define CSL_PLLC_PLLDIV4_RATIO_MASK (0x0000001Fu) #define CSL_PLLC_PLLDIV4_RATIO_SHIFT (0x00000000u) #define CSL_PLLC_PLLDIV4_RATIO_RESETVAL (0x00000007u) #define CSL_PLLC_PLLDIV4_RESETVAL (0x00008007u) / PLLDIV5 / #define CSL_PLLC_PLLDIV5_D5EN_MASK (0x00008000u) #define CSL_PLLC_PLLDIV5_D5EN_SHIFT (0x0000000Fu) #define CSL_PLLC_PLLDIV5_D5EN_RESETVAL (0x00000001u) /----D5EN Tokens----*/ #define CSL_PLLC_PLLDIV5_D5EN_DISABLE (0x00000000u) #define CSL_PLLC_PLLDIV5_D5EN_ENABLE (0x00000001u) #define CSL_PLLC_PLLDIV5_RATIO_MASK (0x0000001Fu) #define CSL_PLLC_PLLDIV5_RATIO_SHIFT (0x00000000u) #define CSL_PLLC_PLLDIV5_RATIO_RESETVAL (0x00000002u) #define CSL_PLLC_PLLDIV5_RESETVAL (0x00008002u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/vcp2/vcp2_hard_decisions/inc/Vcp2_example.h	<gh_stars>0 /* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ========================================================================== / /* =========================================================================== * @file Vcp2_example.h * * @path $(CSLPATH)\example\c6455\vcp2\vcp2_hard_decisions\inc * * @desc Example header file for VCP. * * ============================================================================ / / ============================================================================ * Revision History * =============== * 20-May-2005 SPrasad File Created. * 01-Aug-2005 Chandra Beautified * 11-Aug-2005 Chandra Minor format chagnes. * ============================================================================ / #ifndef _VCP2_EXAMPLE_H_ #define _VCP2_EXAMPLE_H_ #ifdef __cplusplus extern "C" { #endif / Space for the banch metrics / extern Uint32 branch_metric[]; / Space for the hard decisions / extern Uint32 hard_decision[]; / Space for the pre-computed hard decisions / extern Uint32 hard_decisionRef[]; #ifdef __cplusplus } #endif #endif /_VCP2_EXAMPLE_H_*/
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3GetHwChannelSetup.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_edma3GetHwChannelSetup.c * * @path $(CSLPATH)\src\edma * * @desc EDMA3 CSL Implementation on DSP side * / / ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= / #include <csl_edma3.h> #include <csl_edma3Aux.h> /* ============================================================================ * @n@b CSL_edma3GetHwChannelSetupParam * * @b Description * @n Obtains the Channel to Parameter Set mapping.This reads the * DCHMAP/QCHMAP appropriately. * * @b Arguments * @verbatim hEdma Channel Handle paramNum Pointer to parameter entry @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Retrieving the parameter entry * number to which a channel is * mapped * @li CSL_ESYS_BADHANDLE - The handle is passed is * invalid * @li CSL_ESYS_INVPARAMS - Invalid Parameter entry * * * <b> Pre Condition </b> * @n Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() * must be called successfully in that order before * CSL_edma3GetHwChannelSetupParam() can be invoked. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; Uint16 paramNum; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the parameter entry number to which a channel is mapped to CSL_edma3GetHwChannelSetupParam(hChannel,&paramNum); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_edma3GetHwChannelSetupParam, ".text:csl_section:edma3"); CSL_Status CSL_edma3GetHwChannelSetupParam ( CSL_Edma3ChannelHandle hEdma, Uint16 paramNum ) { CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else if (paramNum == NULL) { status = CSL_ESYS_INVPARAMS; } else { if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH) { #if CSL_EDMA3_CHMAPEXIST paramNum = CSL_FEXT(hEdma->regs->DCHMAP[hEdma->chaNum], \ EDMA3CC_DCHMAP_PAENTRY); #endif } else paramNum = CSL_FEXT(hEdma->regs->QCHMAP[hEdma->chaNum-CSL_EDMA3_NUM_DMACH],\ EDMA3CC_QCHMAP_PAENTRY); } return (status); } /** ============================================================================ * @n@b CSL_edma3GetHwChannelSetupTriggerWord * * @b Description * @n Reads the QDMA channel triggerword.This reads the QCHMAP to obtain the * trigger word appropriately. * * @b Arguments * @verbatim hEdma Channel Handle triggerWord Pointer to Trigger word @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Retrieving the parameter entry * number to which a channel is * mapped * @li CSL_ESYS_BADHANDLE - The handle is passed is * invalid * @li CSL_ESYS_INVPARAMS - Invalid Parameter entry * * * <b> Pre Condition </b> * @n Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() * must be called successfully in that order before * CSL_edma3GetHwChannelSetupTriggerWord() can be called. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; Uint8 triggerWord; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the trigger word programmed for a channel CSL_edma3GetHwChannelSetupTriggerWord(hChannel,&triggerWord); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_edma3GetHwChannelSetupTriggerWord, ".text:csl_section:edma3"); CSL_Status CSL_edma3GetHwChannelSetupTriggerWord ( CSL_Edma3ChannelHandle hEdma, Uint8 triggerWord ) { CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else { if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH) { status = CSL_ESYS_INVPARAMS; } else triggerWord = \ CSL_FEXT(hEdma->regs->QCHMAP[hEdma->chaNum-CSL_EDMA3_NUM_DMACH], \ EDMA3CC_QCHMAP_TRWORD); } return (status); } /* ============================================================================ * @n@b CSL_edma3GetHwChannelSetupQue * * @b Description * @n Obtains the Channel to Queue map for the channel.This reads the * DMAQNUM/QDAMQNUM appropriately. * * @b Arguments * @verbatim hEdma Channel Handle evtQue Pointer to Queue setup @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Retrieving the que to which a * channel is mapped * @li CSL_ESYS_BADHANDLE - The handle is passed is * invalid * @li CSL_ESYS_INVPARAMS - Invalid Parameter entry * * * <b> Pre Condition </b> * @n Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() * must be called successfully in that order before * CSL_edma3GetHwChannelSetupQue() can be called. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3Que evtQue; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); // Get the que to which a channel is mapped CSL_edma3GetHwChannelSetupQue(hChannel,&evtQue); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_edma3GetHwChannelSetupQue, ".text:csl_section:edma3"); CSL_Status CSL_edma3GetHwChannelSetupQue ( CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que evtQue ) { Uint32 _cha; Uint32 _qNumIndex; Uint32 _qchMap; CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else if (evtQue == NULL) { status = CSL_ESYS_INVPARAMS; } else { if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH) { /* Extracting the Channel Number in case of QDMA / _cha = hEdma->chaNum - CSL_EDMA3_NUM_DMACH; / Channel to Event Queue mapping / evtQue = (CSL_Edma3Que)CSL_FEXTR(hEdma->regs->QDMAQNUM, _cha * 4 + 2, \ _cha * 4); } else { /* Finding out the relevant DMAQNUM register and the correct bit * positions to write into / _qNumIndex = hEdma->chaNum >> 3; _qchMap = hEdma->chaNum - (_qNumIndex 8); evtQue = (CSL_Edma3Que)CSL_FEXTR(hEdma->regs->DMAQNUM[_qNumIndex], \ _qchMap 4 + 2, _qchMap * 4); } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_i2c.h	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @mainpage I2C CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the I2C module across various devices. The CSL developer is expected to * refer to this document while designing APIs for this module. Some of the * listed APIs may not be applicable to a given I2C module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular I2C Module. The CSL developer should use his discretion designing * new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 * -# i2c_fs_25.pdf, I2C Peripheral Module * Design Requirement/Specification V2.5 / /* ============================================================================ * @file csl_i2c.h * * @brief Header file for functional layer of CSL * * @path $(CSLPATH)\inc * * Description * - The different enumerations, structure definitions * and function declarations * * * Modification 1 * - modified on: 28/5/2004 * - reason: Created the sources * * @date 28th May, 2004 * @author <NAME>. * =========================================================================== / / ============================================================================= * Revision History * =============== * 30-aug-2004 Hs updated CSL_I2cObj and added CSL_I2cBaseAddress, CSL_i2cParam, * CSL_i2cContext, CSL_i2cConfig structures. * - Updated comments for H/W control cmd and status query enums. * - Added prototypes for CSL_i2cGetBaseAdddress and * CSL_I2cHwSetupRaw. * - Changed prototypes of CSL_i2cInit, CSL_i2cOpen. * - Updated respective comments along with that of * CSL_i2cClose. * 11-oct-2004 Hs updated according to code review comments. * 28-jul-2005 sv removed gpio support * 06-Feb-2006 ds removed CSL_I2C_QUERY_REV, CSL_I2C_QUERY_CLASS and * CSL_I2C_QUERY_TYPE queries from the CSL_I2cHwStatusQuery * =========================================================================== / #ifndef _CSL_I2C_H_ #define _CSL_I2C_H_ #ifdef __cplusplus extern "C" { #endif #include <csl.h> #include <soc.h> #include <cslr_i2c.h> /************************************************************************\ I2C global macro declarations \************************************************************************/ / Constants for passing parameters to the I2C Hardware Setup function / /* For setting the SLAVE Mode for I2C / #define CSL_I2C_MODE_SLAVE (0) /* For setting the MASTER Mode for I2C / #define CSL_I2C_MODE_MASTER (1) /* For setting the RECEIVER Mode for I2C / #define CSL_I2C_DIR_RECEIVE (0) /* For setting the TRANSMITTER Mode for I2C / #define CSL_I2C_DIR_TRANSMIT (1) /* For setting the 7-bit Addressing Mode for I2C / #define CSL_I2C_ADDRSZ_SEVEN (0) /* For setting the 10-bit Addressing Mode / #define CSL_I2C_ADDRSZ_TEN (1) /* For Disabling the Start Byte Mode for I2C(Normal Mode) / #define CSL_I2C_STB_DISABLE (0) /* For Enabling the Start Byte Mode for I2C / #define CSL_I2C_STB_ENABLE (1) /* For enabling the tx of a ACK to the TX-ER, while in the RECEIVER mode / #define CSL_I2C_ACK_ENABLE (0) /* For enabling the tx of a NACK to the TX-ER, while in the RECEIVER mode / #define CSL_I2C_ACK_DISABLE (1) /* For enabling the free run mode of the I2C / #define CSL_I2C_FREE_MODE_ENABLE (1) /* For disabling the free run mode of the I2C / #define CSL_I2C_FREE_MODE_DISABLE (0) /* For enabling the Repeat Mode of the I2C / #define CSL_I2C_REPEAT_MODE_ENABLE (1) /* For disabling the Repeat Mode of the I2C / #define CSL_I2C_REPEAT_MODE_DISABLE (0) /* For enabling DLB mode of I2C (applicable only in case of MASTER TX-ER) / #define CSL_I2C_DLB_ENABLE (1) /* For disabling DLB mode of I2C (applicable only in case of MASTER TX-ER) / #define CSL_I2C_DLB_DISABLE (0) /* For putting the I2C in Reset / #define CSL_I2C_IRS_ENABLE (0) /* For taking the I2C out of Reset / #define CSL_I2C_IRS_DISABLE (1) /* For enabling the Free Data Format of I2C / #define CSL_I2C_FDF_ENABLE (1) /* For disabling the Free Data Format of I2C / #define CSL_I2C_FDF_DISABLE (0) /* For enabling the Backward Compatibility mode of I2C / #define CSL_I2C_BCM_ENABLE (1) /* For disabling the Backward Compatibility mode of I2C / #define CSL_I2C_BCM_DISABLE (0) /* Constants for passing parameters to the I2C Status Query function / /* For indicating the non-completion of Reset / #define CSL_I2C_RESET_NOT_DONE (0) /* For indicating the completion of Reset / #define CSL_I2C_RESET_DONE (1) /* For indicating that the bus is not busy / #define CSL_I2C_BUS_NOT_BUSY (0) /* For indicating that the bus is busy / #define CSL_I2C_BUS_BUSY (1) /* For indicating that the Receive ready signal is low / #define CSL_I2C_RX_NOT_READY (0) /* For indicating that the Receive ready signal is high / #define CSL_I2C_RX_READY (1) /* For indicating that the Transmit ready signal is low / #define CSL_I2C_TX_NOT_READY (0) /* For indicating that the Transmit ready signal is high / #define CSL_I2C_TX_READY (1) /* For indicating that the Access ready signal is low / #define CSL_I2C_ACS_NOT_READY (0) /* For indicating that the Access ready signal is high / #define CSL_I2C_ACS_READY (1) /* For indicating Single Byte Data signal is set / #define CSL_I2C_SINGLE_BYTE_DATA (1) /* For indicating Receive overflow signal is set / #define CSL_I2C_RECEIVE_OVERFLOW (1) /* For indicating Transmit underflow signal is set / #define CSL_I2C_TRANSMIT_UNDERFLOW (1) /* For indicating Arbitration Lost signal is set / #define CSL_I2C_ARBITRATION_LOST (1) /* Constants for status bit clear / /* Clear the Arbitration Lost status bit / #define CSL_I2C_CLEAR_AL 0x1 /* Clear the No acknowledge status bit / #define CSL_I2C_CLEAR_NACK 0x2 /* Clear the Register access ready status bit / #define CSL_I2C_CLEAR_ARDY 0x4 /* Clear the Receive ready status bit / #define CSL_I2C_CLEAR_RRDY 0x8 /* Clear the Transmit ready status bit / #define CSL_I2C_CLEAR_XRDY 0x10 /* Clear the Stop Condition Detect status bit / #define CSL_I2C_CLEAR_SCD 0x20 /************************************************************************\ I2C global typedef declarations \************************************************************************/ / @brief This object contains the reference to the instance of I2C opened * using the @a CSL_i2cOpen(). * * The pointer to this, is passed to all I2C CSL APIs. / typedef struct CSL_I2cObj { /* The register overlay structure of I2C. / CSL_I2cRegsOvly regs; /* This is the instance of I2C being referred to by this object / CSL_InstNum perNum; } CSL_I2cObj; /* @brief Holds the base-address information for I2C peripheral * instance / typedef struct { /* Base-address of the Configuration registers of I2C. / CSL_I2cRegsOvly regs; } CSL_I2cBaseAddress; /* @brief I2C specific parameters. Present implementation doesn't have * any specific parameters. / typedef struct { /* Bit mask to be used for module specific parameters. * The below declaration is just a place-holder for future * implementation. / CSL_BitMask16 flags; } CSL_I2cParam; /* @brief I2C specific context information. Present implementation doesn't * have any Context information. / typedef struct { /* Context information of I2C. * The below declaration is just a place-holder for future * implementation. / Uint16 contextInfo; } CSL_I2cContext; /* @brief I2C Configuration Structure, is used to configure I2C * using CSL_HwSetupRaw function. / typedef struct { volatile Uint32 ICOAR; /< I2C Own address register / volatile Uint32 ICIMR; /*< I2C Interrupt Mask register / volatile Uint32 ICSTR; /*< I2C Status register / volatile Uint32 ICCLKL; /*< I2C Clock low register / volatile Uint32 ICCLKH; /*< I2C clock high register / volatile Uint32 ICCNT; /*< I2C Data Count register / volatile Uint32 ICSAR; /*< I2C Slave address register / volatile Uint32 ICDXR; /*< I2C Data Transmit register / volatile Uint32 ICMDR; /*< I2C Mode register / volatile Uint32 ICIVR; /*< I2C Interrupt vector register / volatile Uint32 ICEMDR; /*< I2C Extended mode register / volatile Uint32 ICPSC; /*< I2C Prescalar register / } CSL_I2cConfig; /** Default Values for Config structure / #define CSL_I2C_CONFIG_DEFAULTS { \ CSL_I2C_ICOAR_RESETVAL, \ CSL_I2C_ICIMR_RESETVAL, \ CSL_I2C_ICSTR_RESETVAL, \ CSL_I2C_ICCLKL_RESETVAL, \ CSL_I2C_ICCLKH_RESETVAL, \ CSL_I2C_ICCNT_RESETVAL, \ CSL_I2C_ICSAR_RESETVAL, \ CSL_I2C_ICDXR_RESETVAL, \ CSL_I2C_ICMDR_RESETVAL, \ CSL_I2C_ICIVR_RESETVAL, \ CSL_I2C_ICEMDR_RESETVAL, \ CSL_I2C_ICPSC_RESETVAL, \ } /* @brief Handle to the I2C object * Handle is used in all accesses to the device parameters. / typedef struct CSL_I2cObj CSL_I2cHandle; /** @brief The clock setup structure has all the fields required to configure * the I2C clock. / typedef struct { /* Prescalar to the input clock / Uint32 prescalar; /* Low time period of the clock / Uint32 clklowdiv; /* High time period of the clock / Uint32 clkhighdiv; } CSL_I2cClkSetup; /* @brief This has all the fields required to configure I2C at Power Up * (After a Hardware Reset) or a Soft Reset * * This structure is used to setup or obtain existing setup of * I2C using @a CSL_i2cHwSetup() & @a CSL_i2cGetHwSetup() functions * respectively. / typedef struct { /* Master or Slave Mode : 1==> Master Mode, 0==> Slave Mode / Uint32 mode; /* Transmitter Mode or Receiver Mode: 1==> Transmitter Mode, * 0 ==> Receiver Mode / Uint32 dir; /* Addressing Mode :0==> 7-bit Mode, 1==> 10-bit Mode / Uint32 addrMode; /* Start Byte Mode : 1 ==> Start Byte Mode, 0 ==> Normal Mode / Uint32 sttbyteen; /* Address of the own device / Uint32 ownaddr; /* ACK mode while receiver: 0==> ACK Mode, 1==> NACK Mode / Uint32 ackMode; /* Run mode of I2C: 0==> No Free Run, 1==> Free Run mode / Uint32 runMode; /* Repeat Mode of I2C: 0==> No repeat mode 1==> Repeat mode / Uint32 repeatMode; /* DLBack mode of I2C (master tx-er only): * 0 ==> No loopback, * 1 ==> Loopback Mode / Uint32 loopBackMode; /* Free Data Format of I2C: * 0 ==>Free data format disable, * 1 ==> Free data format enable / Uint32 freeDataFormat; /* I2C Reset Mode: 0==> Reset, 1==> Out of reset / Uint32 resetMode; /* I2C Backward Compatibility Mode : * 0 ==> Not compatible, * 1 ==> Compatible / Uint32 bcm; /* Interrupt Enable mask The mask can be for one interrupt or * OR of multiple interrupts. / Uint32 inten; /* Prescalar, Clock Low and Clock High for Clock Setup / CSL_I2cClkSetup clksetup; } CSL_I2cHwSetup; /** @brief Enumeration for queries passed to @a CSL_i2cGetHwStatus() * * This is used to get the status of different operations or to get the * existing setup of I2C. / typedef enum { /* * @brief Get current clock setup parameters * @param (CSL_I2cClkSetup ) / CSL_I2C_QUERY_CLOCK_SETUP = 1, /** * @brief Get the Bus Busy status information * @param (Uint16) / CSL_I2C_QUERY_BUS_BUSY = 2, /** * @brief Get the Receive Ready status information * @param (Uint16) / CSL_I2C_QUERY_RX_RDY = 3, /** * @brief Get the Transmit Ready status information * @param (Uint16) / CSL_I2C_QUERY_TX_RDY = 4, /** * @brief Get the Register Ready status information * @param (Uint16) / CSL_I2C_QUERY_ACS_RDY = 5, /** * @brief Get the Stop Condition Data bit information * @param (Uint16) / CSL_I2C_QUERY_SCD = 6, /** * @brief Get the Address Zero (General Call) detection status * @param (Uint16) / CSL_I2C_QUERY_AD0 = 7, /** * @brief Get the Receive overflow status information * @param (Uint16) / CSL_I2C_QUERY_RSFULL = 8, /** * @brief Get the Transmit underflow status information * @param (Uint16) / CSL_I2C_QUERY_XSMT = 9, /** * @brief Get the Address as Slave bit information * @param (Uint16) / CSL_I2C_QUERY_AAS = 10, /** * @brief Get the Arbitration Lost status information * @param (Uint16) / CSL_I2C_QUERY_AL = 11, /** * @brief Get the Reset Done status bit information * @param (Uint16) / CSL_I2C_QUERY_RDONE = 12, /** * @brief Get no of bits of next byte to be received or transmitted * @param (Uint16) / CSL_I2C_QUERY_BITCOUNT = 13, /** * @brief Get the interrupt code for the interrupt that occured * @param (Uint16) / CSL_I2C_QUERY_INTCODE = 14, /** * @brief Get the slave direction * @param (Uint16) / CSL_I2C_QUERY_SDIR = 15, /** * @brief Get the acknowledgement status * @param (Uint16) / CSL_I2C_QUERY_NACKSNT = 16 } CSL_I2cHwStatusQuery; /** @brief Enumeration for queries passed to @a CSL_i2cHwControl() * * This is used to select the commands to control the operations * existing setup of I2C. The arguments to be passed with each * enumeration if any are specified next to the enumeration. / typedef enum { /* * @brief Enable the I2C * @param (None) / CSL_I2C_CMD_ENABLE = 1, /* * @brief Reset command to the I2C * @param (None) / CSL_I2C_CMD_RESET = 2, /* * @brief Bring the I2C out of reset * @param (None) / CSL_I2C_CMD_OUTOFRESET = 3, /* * @brief Clear the status bits. The argument next to the command * specifies the status bit to be cleared. The status bit * can be : * CSL_I2C_CLEAR_AL, * CSL_I2C_CLEAR_NACK, * CSL_I2C_CLEAR_ARDY, * CSL_I2C_CLEAR_RRDY, * CSL_I2C_CLEAR_XRDY, * CSL_I2C_CLEAR_GC * @param (None) / CSL_I2C_CMD_CLEAR_STATUS = 4, /* * @brief Set the address of the Slave device * @param (Uint16 ) / CSL_I2C_CMD_SET_SLAVE_ADDR = 5, /** * @brief Set the Data Count * @param (Uint16 ) / CSL_I2C_CMD_SET_DATA_COUNT = 6, /** * @brief Set the start condition * @param (None) / CSL_I2C_CMD_START = 7, /* * @brief Set the stop condition * @param (None) / CSL_I2C_CMD_STOP = 8, /* * @brief Set the transmission mode * @param (None) / CSL_I2C_CMD_DIR_TRANSMIT = 9, /* * @brief Set the receiver mode * @param (None) / CSL_I2C_CMD_DIR_RECEIVE = 10, /* * @brief Set the Repeat Mode * @param (None) / CSL_I2C_CMD_RM_ENABLE = 11, /* * @brief Disable the Repeat Mode * @param (None) / CSL_I2C_CMD_RM_DISABLE = 12, /* * @brief Set the loop back mode * @param (None) / CSL_I2C_CMD_DLB_ENABLE = 13, /* * @brief Disable the loop back mode * @param (None) / CSL_I2C_CMD_DLB_DISABLE = 14 } CSL_I2cHwControlCmd; /************************************************************************\ I2C global function declarations \************************************************************************/ / ============================================================================ * @n@b CSL_i2cInit * * @b Description * @n This is the initialization function for the I2C. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. * * @b Arguments @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Status status; ... status = CSL_i2cInit(); ... @endverbatim * =========================================================================== / CSL_Status CSL_i2cInit ( CSL_I2cContext pContext ); /** ============================================================================ * @n@b CSL_i2cOpen * * @b Description * @n This function populates the peripheral data object for the instance * and returns a handle to the instance. * The open call sets up the data structures for the particular instance * of I2C device. The device can be re-opened anytime after it has been * normally closed if so required. The handle returned by this call is * input as an essential argument for rest of the APIs described for * this module. * * @b Arguments * @verbatim pI2cObj Pointer to the I2C instance object i2cNum Instance of the I2C to be opened. pI2cParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * <b> Return Value </b> * CSL_I2cHandle * Valid I2C instance handle will be returned if status value is * equal to CSL_SOK. * * <b> Pre Condition </b> * @n @a CSL_i2cInit() must be called successfully. * * <b> Post Condition </b> * @n i2c instance will be opened * * @b Modifies * @n None * * @b Example: * @verbatim CSL_status status; CSL_I2cObj i2cObj; CSL_I2cHandle hI2c; ... hI2c = CSL_I2cOpen (&i2cObj, CSL_I2C, NULL, &status ); ... @endverbatim * * =========================================================================== / CSL_I2cHandle CSL_i2cOpen ( CSL_I2cObj hI2cObj, CSL_InstNum i2cNum, CSL_I2cParam pI2cParam, CSL_Status status ); /** ============================================================================ * @n@b CSL_i2cClose * * @b Description * @n This function closes the specified instance of I2C. * * @b Arguments * @verbatim hI2c Handle to the I2C @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Close Successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * <b> Pre Condition </b> * @n The device should be successfully opened. * * <b> Post Condition </b> * @n None * * @b Modifies * @n I2C Handle * * @b Example * @verbatim CSL_I2cHandle hI2c; ... status = CSL_i2cClose(hI2c); ... @endverbatim * ============================================================================ / CSL_Status CSL_i2cClose ( CSL_I2cHandle hI2c ); /* ============================================================================ * @n@b CSL_i2cHwSetup * * @b Description * @n This function initializes the device registers with the appropriate * values provided through the HwSetup Data structure. This function needs * to be called only if the HwSetup Structure was not previously passed * through the Open call. After the Setup is completed, the device is ready * for operation.For information passed through the HwSetup Data structure * refer @a CSL_i2cHwSetup. * @b Arguments * @verbatim hI2c Handle to the I2C setup Pointer to setup structure which contains the information to program I2C to a useful state @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup Successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before this function can be called. The user has to * allocate space for & fill in the main setup structure appropriately * before calling this function. * * <b> Post Condition </b> * @n The registers of the specified I2C instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified I2C instance. * * @b Example * @verbatim CSL_i2cHandle hI2c; CSL_i2cHwSetup hwSetup = CSL_I2C_HWSETUP_DEFAULTS; ... CSL_i2cHwSetup(hI2c, &hwSetup); ... @endverbatim * =========================================================================== / CSL_Status CSL_i2cHwSetup ( CSL_I2cHandle hI2c, CSL_I2cHwSetup setup ); /** ============================================================================ * @n@b CSL_i2cGetHwSetup * * @b Description * @n This function gets the current setup of the I2C. The status is * returned through @a CSL_I2cHwSetup. The obtaining of status * is the reverse operation of @a CSL_i2cHwSetup() function. * * @b Arguments * @verbatim hI2c Handle to the I2C hwSetup Pointer to the hardware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Retrieving the hardware setup * parameters is successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cGetHwSetup() can be called. * * <b> Post Condition </b> * @n The hardware setup structure is populated with the hardware setup * parameters * * @b Modifies * @n hwSetup variable * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cHwSetup hwSetup; ... status = CSL_i2cGetHwSetup(hI2c, &hwSetup); ... @endverbatim * =========================================================================== / CSL_Status CSL_i2cGetHwSetup ( CSL_I2cHandle hI2c, CSL_I2cHwSetup setup ); /** ============================================================================ * @n@b CSL_i2cHwControl * * @b Description * @n Control operations for the I2C. For a particular control operation, * the pointer to the corresponding data type need to be passed as argument * to HwControl function Call.All the arguments(Structure element included) * passed to the HwControl function are inputs. For the list of commands * supported and argument type that can be @a void* casted & passed with a * particular command refer to @a CSL_I2cHwControlCmd. * @b Arguments * @verbatim hI2c Handle to the I2C instance cmd The command to this API indicates the action to be taken on I2C. arg An optional argument. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cHwControl() can be called. * * <b> Post Condition </b> * @n None * * @b Modifies * @n The hardware registers of I2C. * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cHwControlCmd cmd = CSL_I2C_CMD_RESET; void arg; CSL_Status status; ... status = CSL_i2cHwControl (hI2c, cmd, &arg); ... @endverbatim * ============================================================================= / CSL_Status CSL_i2cHwControl ( CSL_I2cHandle hI2c, CSL_I2cHwControlCmd cmd, void arg ); /** ============================================================================ * @n@b CSL_i2cRead * * @b Description * @n This function reads I2C data. * * @b Arguments * @verbatim hI2c Handle to I2C instance buf Buffer to store the data read @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Operation Successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cRead() can be called. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example: * @verbatim Uint16 outData; CSL_Status status; CSL_I2cHandle hI2c; ... // I2C object defined and HwSetup structure defined and initialized ... // Init, Open, HwSetup successfully done in that order ... status = CSL_i2cRead(hI2c, &outData); @endverbatim * =========================================================================== / CSL_Status CSL_i2cRead ( CSL_I2cHandle hI2c, void buf ); /** ============================================================================ * @n@b CSL_i2cWrite * * @b Description * @n This function writes the specified data into I2C data register. * * @b Arguments * @verbatim hI2c Handle to I2C instance buf data to be written @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Success (doesnot verify written data) * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cWrite() can be called. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example: * @verbatim Uint16 inData; CSL_Status status; CSL_I2cHandle hI2c; ... // I2C object defined and HwSetup structure defined and initialized ... // Init, Open, HwSetup successfully done in that order ... status = CSL_i2cWrite(hi2c, &inData); @endverbatim * =========================================================================== / CSL_Status CSL_i2cWrite ( CSL_I2cHandle hI2c, void buf ); /** ============================================================================ * @n@b CSL_i2cHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hI2c Handle to the I2C config Pointer to config structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not * properly initialized * * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cHwSetupRaw() can be called. * * <b> Post Condition </b> * @n The registers of the specified I2C instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified I2C instance. * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cConfig config = CSL_I2C_CONFIG_DEFAULTS; CSL_Status status; ... status = CSL_i2cHwSetupRaw(hI2c, &config); ... @endverbatim * =========================================================================== / CSL_Status CSL_i2cHwSetupRaw ( CSL_I2cHandle hI2c, CSL_I2cConfig config ); /** ============================================================================ * @n@b CSL_i2cGetHwStatus * * @b Description * @n This function is used to read the current device configuration, status * flags and the value present associated registers.Following table details * the various status queries supported and the associated data structureto * record the response. User should allocate memory for the said data type * and pass its pointer as an unadorned void* argument to the status query * call.For details about the various status queries supported and the * associated data structure to record the response, * refer to @a CSL_I2cHwStatusQuery * * @b Arguments * @verbatim hI2c Handle to the I2C instance query The query to this API of I2C which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Status info return successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVQUERY - Invalid query command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cGetHwStatus() can be called. * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cHwStatusQuery query; void reponse; status = CSL_i2cGetHwStatus(hI2c, query, &response); @endverbatim * ============================================================================= / CSL_Status CSL_i2cGetHwStatus ( CSL_I2cHandle hI2c, CSL_I2cHwStatusQuery query, void response ); /** ============================================================================ * @n@b CSL_i2cGetBaseAddress * * @b Description * @n Function to get the base address of the peripheral instance. * This function is used for getting the base address of the peripheral * instance. This function will be called inside the CSL_i2cOpen() * function call. This function is open for re-implementing if the user * wants to modify the base address of the peripheral object to point to * a different location and there by allow CSL initiated write/reads into * peripheral MMR's go to an alternate location. * * @b Arguments * @verbatim i2cNum Specifies the instance of I2C to be opened. pI2cParam Module specific parameters. pBaseAddress Pointer to baseaddress structure containing base address details. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_OK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Base Address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_I2cBaseAddress baseAddress; ... status = CSL_i2cGetBaseAddress(CSL_I2C, NULL, &baseAddress); @endverbatim * =========================================================================== / CSL_Status CSL_i2cGetBaseAddress ( CSL_InstNum i2cNum, CSL_I2cParam pI2cParam, CSL_I2cBaseAddress *pBaseAddress ); #ifdef __cplusplus } #endif #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/cache/_csl_cache.c	<filename>DSP/TI-Header/csl_c6455_src/src/cache/_csl_cache.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / / ============================================================================ * @file _csl_cache.c * * @path $(CSLPATH)\src\cache * * @desc File for functional layer of CSL API _CSL_cacheApplyPatch() and * _CACHE_wait () * / / ============================================================================= * Revision History * =============== * 23-Mar-2004 <NAME> File Created * * 21-Jun-2004 <NAME> modified. * * ============================================================================= / #include <csl_cache.h> #include <_csl_cache.h> #pragma DATA_SECTION (_CSL_cachebusyState, ".bss:csl_section:cache"); volatile CACHE_waitState _CSL_cachebusyState = CACHE_WAIT_NONE; #pragma DATA_SECTION (_CSL_cacheEmifState, ".bss:csl_section:cache"); volatile CACHE_emifState _CSL_cacheEmifState = CACHE_EMIF_NONE; / ============================================================================ * @n@b _CSL_cacheApplyPatch * * @b Description * @n This API used to set the cacheability of the specified EMIF range. * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... _CSL_cacheApplyPatch (); ... @endverbatim * ============================================================================ / #pragma CODE_SECTION (_CSL_cacheApplyPatch, ".text:csl_section:cache"); void _CSL_cacheApplyPatch(void) { switch (_CSL_cacheEmifState) { case CACHE_EMIF_NONE: break; case CACHE_EMIF_A: CSL_CACHE_EMIFA_PATCH(); break; case CACHE_EMIF_B: CSL_CACHE_EMIFB_PATCH(); break; case CACHE_EMIF_AB: CSL_CACHE_EMIFA_PATCH(); CSL_CACHE_EMIFB_PATCH(); break; } _CSL_cacheEmifState = CACHE_EMIF_NONE; } / ============================================================================ * @n@b _CACHE_wait * * @b Description * @n This API call the CACHE_waitInternal() and CACHE_wait() APIs. * * @b Arguments * @n wait - Specifies whether the cache operations should block * till the desired operation is complete * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... _CACHE_wait(CACHE_NOWAIT); ... @endverbatim * ============================================================================ */ #pragma CODE_SECTION (_CACHE_wait, ".text:csl_section:cache"); void _CACHE_wait ( CACHE_Wait wait ) { if (wait == CACHE_WAITINTERNAL) CACHE_waitInternal(); else CACHE_wait(); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/gpio/src/Gpio_example.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * * @file gpioExample.c * * @path $(CSLPATH)\example\gpio\src * * @desc example for GPIO. * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @verbatim This Example, 1. Initializes INTC, enables NMIs, enables event 2. Initializes and opens GPIO CSL module 3. Configures pin 5 to generate an interrupt on rising edge and configures the pin as an output. 4. Enables the bank interrupt. 5. Sets data high. 6. Waits for interrupt to be generated 7. Sets the data low and closes the GPIO instance. * * ============================================================================= * * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project gpioExample.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================= * Revision History * =============== * 23-Sep-2005 PSK File Created * * 07-Nov-2005 NG Updated documentation * * ============================================================================= / #include <csl_gpio.h> #include <csl_intc.h> #include <stdio.h> #include <string.h> #include <csl_intcAux.h> #include <cslr_dev.h> / Locals & Forwards / void gpioInternalLoopbackDemo(void); / Globals / CSL_GpioHandle hGpio; volatile Uint8 intrCnt; int demoFail = 0; / Interrupt module Declarations / CSL_IntcObj gpioIntcObj; CSL_IntcHandle gpioIntcHandle; CSL_IntcContext context; CSL_IntcEventHandlerRecord isr_gpio; CSL_IntcEventHandlerRecord record[1]; / * ============================================================================= * @func HandleGPIO_INT * * @arg * NONE * * @desc * This function is Handler for Interrupt. * * @return * NONE * * ============================================================================= / void HandleGPIO_INT ( void arg ) { intrCnt++; return; } /* * ============================================================================= * @func main * * @desc * This is the main routine, which invokes the example script. * * ============================================================================= / void main ( void ) { Bool gpioEn; / Unlock the control register / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the GPIO / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_GPIOCTL, ENABLE); do { gpioEn = (Bool) CSL_FEXT(((CSL_DevRegs)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_GPIOSTAT); } while (gpioEn != TRUE); printf("Powersaver clock for GPIO is enabled\n"); / Invoking example script / gpioInternalLoopbackDemo(); if (demoFail) { printf("\nGPIO: EXAMPLE fails. \n"); } else { printf("\nGPIO: EXAMPLE completed\n"); } return; } / * ============================================================================= * @func gpioInternalLoopbackDemo * * @arg * NONE * * @desc * Gives demo for the internal loopback mechanism for the interrupt path; * the value sent on a output pin can trigger a Rising or Falling edge * interrupt. * * @return * NONE * * ============================================================================= / void gpioInternalLoopbackDemo ( void ) { CSL_Status intStat; CSL_GpioPinConfig config; CSL_GpioPinNum pinNum; CSL_Status status; CSL_GpioContext pContext; CSL_GpioObj gpioObj; CSL_GpioHwSetup hwSetup; CSL_IntcGlobalEnableState state; CSL_IntcParam vectId; / Initialize INTC / context.numEvtEntries = 1; context.eventhandlerRecord = record; intStat = CSL_intcInit(&context); if (intStat != CSL_SOK) { printf("INTR: Initialization error.\n"); demoFail++; return; } / Enable NMIs / intStat = CSL_intcGlobalNmiEnable(); if (intStat != CSL_SOK) { printf("INTR: Error while enabling NMI.\n"); demoFail++; return; } / Enable all interrupts / intStat = CSL_intcGlobalEnable(&state); if (intStat != CSL_SOK) { printf("INTR: Error while enabling interrupt.\n"); demoFail++; return; } / Open interrupt module / vectId = CSL_INTC_VECTID_12; gpioIntcHandle = CSL_intcOpen(&gpioIntcObj, CSL_INTC_EVENTID_GPINT5, &vectId, &intStat); if ((gpioIntcHandle == NULL) \|\| (intStat != CSL_SOK)) { printf("INTR: Error opening the instance.\n"); demoFail++; return; } / Bind ISR to Interrupt / isr_gpio.handler = (CSL_IntcEventHandler)&HandleGPIO_INT; isr_gpio.arg = gpioIntcHandle; CSL_intcPlugEventHandler(gpioIntcHandle, &isr_gpio); / Event Enable / CSL_intcHwControl(gpioIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL); if (intStat != CSL_SOK) { printf("INTR: Error in enabling event.\n"); demoFail++; return; } / Initialize the GPIO CSL module / status = CSL_gpioInit(&pContext); if (status != CSL_SOK) { printf("GPIO: Initialization error.\n"); demoFail++; return; } / Open the CSL module / hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO, NULL, &status); if ((hGpio == NULL) \|\| (status != CSL_SOK)) { printf("GPIO: Error opening the instance.\n"); demoFail++; return; } intrCnt = 0; / Setup hardware parameters / hwSetup.extendSetup = NULL; / Setup the General Purpose IO / status = CSL_gpioHwSetup(hGpio, &hwSetup); / Configure pin 5 to generate an interrupt on Rising Edge, and * configure it as an output, then set the data High (Low->High). * Set Trigger: / config.pinNum = CSL_GPIO_PIN5; config.trigger = CSL_GPIO_TRIG_RISING_EDGE; config.direction = CSL_GPIO_DIR_OUTPUT; / Enable the bank interrupt / status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_BANK_INT_ENABLE, NULL); if (status != CSL_SOK) { printf("GPIO: Command to enable bank interrupt... Failed.\n"); demoFail++; } / configure the gpio pin 5 / status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_CONFIG_BIT, &config); if (status != CSL_SOK) { printf("GPIO: GPIO pin configuration error.\n"); demoFail++; return; } / Set Data High: / pinNum = CSL_GPIO_PIN5; status = CSL_gpioHwControl (hGpio, CSL_GPIO_CMD_SET_BIT, &pinNum); if (status != CSL_SOK) { printf("GPIO: Command to set bit... Failed.\n"); demoFail++; return; } / Wait for interrupt to be generated. / while (1) { if (intrCnt == 1) break; } printf("\n GPIO: Interrupt Occurred.\n"); / Set Data Low again: */ pinNum = CSL_GPIO_PIN5; status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_CLEAR_BIT, &pinNum); if (status != CSL_SOK) { printf("GPIO: Command to clear bit... Failed.\n"); demoFail++; return; } status = CSL_gpioClose(hGpio); if (status != CSL_SOK) { printf("GPIO: Unable to Close the instance.[status = 0x%x].\n", status); demoFail++; return; } }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/mcbsp/_csl_mcbspBlockAssign.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / / ============================================================================ * @file _csl_mcbspBlockAssign.c * * @path $(CSLPATH)\src\mcbsp * * @desc File for functional layer of CSL API _CSL_mcbspBlockAssign() * / / ============================================================================= * Revision History * ================ * June 29,2004 <NAME> - Created * * ============================================================================= / #include <csl_mcbsp.h> #include <_csl_mcbsp.h> / ============================================================================ * @n@b _CSL_mcbspBlockAssign * * @b Description * @n The funtion is used to assign block to a particular partition * This is an Internal function and is used by the CSL_mcbspHwControl * function * * @b Arguments * @verbatim hMcbsp Handle to MCBSP Obj used partition Partition to which the block is to be assigned block Identifies the block @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Successful completion * @li CSL_ESYS_FAIL - Operation could not the done * @li CSL_ESYS_BADHANDLE - Invalid Handle * * <b> Pre Condition </b> * @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully * in that order before _CSL_mcbspBlockAssign() can be called. * * <b> Post Condition </b> * @n Assign block to a specified partition * * @b Modifies * @n None * * @b Example * @verbatim CSL_McbspHandle hMcbsp; ... CSL_mcbspBlockAssign(hMcbsp, CSL_MCBSP_PARTITION_ATX, \ CSL_MCBSP_BLOCK0); ... @endverbatim * ============================================================================= / #pragma CODE_SECTION (_CSL_mcbspBlockAssign, ".text:csl_section:mcbsp"); CSL_Status _CSL_mcbspBlockAssign ( CSL_McbspHandle hMcbsp, CSL_McbspPartition partition, CSL_McbspBlock block ) { CSL_Status status = CSL_SOK; if (partition & 0x01) { if ((CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_RMCME) == 0) && (CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_RMCM) == 1)) { if ((block & 0x01) && partition == 3) { / Odd blocks can be assinged to only partition B / CSL_FINS( hMcbsp->regs->MCR, MCBSP_MCR_RPBBLK, block ); } else { if ((!(block & 0x01)) && partition == 1) { / Even blocks can be assinged to only partition A / CSL_FINS( hMcbsp->regs->MCR, MCBSP_MCR_RPABLK, block ); } else status = CSL_EMCBSP_INVPARAMS; } } else status = CSL_EMCBSP_INVMODE; } else { if ((CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_XMCME) == 0) && (CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_XMCM) != 0)) { if ((block & 0x01) && partition == 2) { / Odd blocks can be assinged to only partition B / CSL_FINS( hMcbsp->regs->MCR, MCBSP_MCR_XPBBLK, block ); } else { if ((!(block & 0x01)) && partition == 0) { / Even blocks can be assinged to only partition A */ CSL_FINS( hMcbsp->regs->MCR, MCBSP_MCR_XPABLK, block ); } else status = CSL_EMCBSP_INVPARAMS; } } else status = CSL_EMCBSP_INVMODE; } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_vcp2.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * =========================================================================== / /* =========================================================================== * @file csl_vcp2.h * * @path $(CSLPATH)\inc * * @desc API header for VCP2 * / /* @mainpage VCP2 CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the VCP2 module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given VCP2 module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular VCP2 Module. The CSL developer should use his discretion * designing new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# VCP2 FUNCTIONAL SPEC 2.00.W.12 * / / ============================================================================ * Revision History * ================ * 24-March-2005 SPrasad File Created. * 27-May-2005 SPrasad Updated with new requirements' specification. * 03-Aug-2005 Chandra Minor changes to beautify the file. * 08-dec-2005 sd changed the maxSm and minSm to be signed * integers * 07-mar-2006 ds Rename of Out order tokens according to register * header file. * - CSL_VCP2_VCPIC3_OUT_ORDER_0_31 to * CSL_VCP2_VCPIC3_OUT_ORDER_LSB and * - CSL_VCP2_VCPIC3_OUT_ORDER_31_0 to * CSL_VCP2_VCPIC3_OUT_ORDER_MSB * * ============================================================================ / #ifndef _CSL_VCP2_H_ #define _CSL_VCP2_H_ #include <csl.h> #include <cslr_vcp2.h> #include <soc.h> #ifdef __cplusplus extern "C" { #endif /***************************************************************************** * VCP Macros ***************************************************************************/ / Code rate = 2 / #define VCP2_RATE_1_2 2 /* Code rate = 3 / #define VCP2_RATE_1_3 3 /* Code rate = 4 / #define VCP2_RATE_1_4 4 /* Speed critical / #define VCP2_SPEED_CRITICAL 0 /* Speed most critical / #define VCP2_SPEED_MOST_CRITICAL 1 /* Performance critical / #define VCP2_PERF_CRITICAL 2 /* Performance most critical / #define VCP2_PERF_MOST_CRITICAL 3 /* Default value / #define VCP2_PERF_DEFAULT VCP2_SPEED_CRITICAL /* Out order of VCP output for decoded data : 0 to 31 / #define VCP2_OUTORDER_0_31 CSL_VCP2_VCPIC3_OUT_ORDER_LSB /* Out order of VCP output for decoded data : 31 to 0 / #define VCP2_OUTORDER_31_0 CSL_VCP2_VCPIC3_OUT_ORDER_MSB /* Output decision type : Hard decisions / #define VCP2_DECISION_HARD CSL_VCP2_VCPIC5_SDHD_HARD /* Output decision type : Soft decisions / #define VCP2_DECISION_SOFT CSL_VCP2_VCPIC5_SDHD_SOFT /* Output parameters read flag : VCP read event is not generated / #define VCP2_OUTF_NO CSL_VCP2_VCPIC5_OUTF_NO /* Output parameters read flag : VCP read event is generated / #define VCP2_OUTF_YES CSL_VCP2_VCPIC5_OUTF_YES /* No trace back allowed / #define VCP2_TRACEBACK_NONE CSL_VCP2_VCPIC5_TB_NO /* Traceback mode : Tailed / #define VCP2_TRACEBACK_TAILED CSL_VCP2_VCPIC5_TB_TAIL /* Traceback mode : Convergent / #define VCP2_TRACEBACK_CONVERGENT CSL_VCP2_VCPIC5_TB_CONV /* Traceback mode : Mixed / #define VCP2_TRACEBACK_MIXED CSL_VCP2_VCPIC5_TB_MIX /* * VCP unpause type : VCP restarts and processes one sliding window before * pausing again / #define VCP2_UNPAUSE_ONESW CSL_VCP2_VCPEXE_COMMAND_RESTART_PAUSE /* VCP unpause type : VCP restarts / #define VCP2_UNPAUSE_NORMAL CSL_VCP2_VCPEXE_COMMAND_RESTART /* Soft decisions memory format : 32-bit word packed / #define VCP2_END_PACKED32 CSL_VCP2_VCPEND_SD_32BIT /* Soft decisions memory format : Native (8 bits) / #define VCP2_END_NATIVE CSL_VCP2_VCPEND_SD_NATIVE /* EMU mode : VCP halts at the end of completion of the current window of * state metric processing or at the end of a frame / #define VCP2_EMUHALT_DEFAULT CSL_VCP2_VCPEMU_SOFT_HALT_DEFAULT /* * EMU mode : VCP halts at the end of completion of the processing of the * frame / #define VCP2_EMUHALT_FRAMEEND CSL_VCP2_VCPEMU_SOFT_HALT_FRAMEEND /************************************************************************** * Following are Polynomials used in GSM/Edge/GPRS ************************************************************************/ / * GSM/Edge/GPRS generator polynomial 0 / #define VCP2_GEN_POLY_0 0x30 /* * GSM/Edge/GPRS generator polynomial 1 / #define VCP2_GEN_POLY_1 0xB0 /* * GSM/Edge/GPRS generator polynomial 2 / #define VCP2_GEN_POLY_2 0x50 /* * GSM/Edge/GPRS generator polynomial 3 / #define VCP2_GEN_POLY_3 0xF0 /* * GSM/Edge/GPRS generator polynomial 4 / #define VCP2_GEN_POLY_4 0x6C /* * GSM/Edge/GPRS generator polynomial 5 / #define VCP2_GEN_POLY_5 0x94 /* * GSM/Edge/GPRS generator polynomial 6 / #define VCP2_GEN_POLY_6 0xF4 /* * GSM/Edge/GPRS generator polynomial 7 / #define VCP2_GEN_POLY_7 0xE4 /* * NULL generator polynomial for GSM/Edge/GPRS / #define VCP2_GEN_POLY_GNULL 0x00 /***************************************************************************** * VCP global typedef declarations ***************************************************************************/ / * Handle to access VCP2 registers accessible through config bus. / #define hVcp2 ((CSL_Vcp2ConfigRegs)CSL_VCP2_0_REGS) /** * Handle to access VCP2 registers accessible through EDMA bus. / #define hVcp2Vbus ((CSL_Vcp2EdmaRegs )CSL_VCP2_EDMA_REGS) /** * VCP code rate type / typedef Uint32 VCP2_Rate; /* * VCP input configuration structure that holds all of the configuration * values that are to be transferred to the VCP via the EDMA. / typedef struct { /* Value of VCP input configuration register 0 / Uint32 ic0; /* Value of VCP input configuration register 1 / Uint32 ic1; /* Value of VCP input configuration register 2 / Uint32 ic2; /* Value of VCP input configuration register 3 / Uint32 ic3; /* Value of VCP input configuration register 4 / Uint32 ic4; /* Value of VCP input configuration register 5 / Uint32 ic5; } VCP2_ConfigIc; /* * VCP channel parameters structure that holds all of the information * concerning the user channel. These values are used to generate the * appropriate input configuration values for the VCP and to program * the EDMA. / typedef struct { /* Code rate / VCP2_Rate rate; /* Constraint length / Uint8 constLen; /* Polynomial 0 / Uint8 poly0; /* Polynomial 1 / Uint8 poly1; /* Polynomial 2 / Uint8 poly2; /* Polynomial 3 / Uint8 poly3; /* Yamamoto threshold value/ Uint16 yamTh; /* Frame length i.e. number of symbols in a frame/ Uint16 frameLen; /* Reliability length / Uint16 relLen; /* Convergence distance / Uint16 convDist; /* Traceback state index / Uint16 traceBackIndex; /* Traceback state index enable/disable / Bool traceBackEn; /* Hard decision output ordering / Uint16 outOrder; /* Maximum initial state metric / Int16 maxSm; /* Minimum initial state metric / Int16 minSm; /* State index set to the maximum initial state metric/ Uint8 stateNum; /* Branch metrics buffer length in input FIFO / Uint8 bmBuffLen; /* Decisions buffer length in output FIFO / Uint8 decBuffLen; /* Traceback mode / Uint8 traceBack; /* Output parameters read flag / Uint8 readFlag; /* Decision selection: hard or soft / Uint8 decision; /* Number of branch metric frames/ Uint16 numBmFrames; /* Number of decision frames / Uint16 numDecFrames; } VCP2_Params; /* * VCP base parameter structure that is used to configure the VCP parameters * structure with the given values using VCP2_genParams() function. / typedef struct { /* Code rate / VCP2_Rate rate; /* Constraint length / Uint8 constLen; /* Frame length / Uint16 frameLen; /* Yamamoto threshold value / Uint16 yamTh; /* Maximum initial state metric value / Uint8 stateNum; /* Traceback convergement mode / Bool tbConvrgMode; /* Output decision type / Uint8 decision; /* Output parameters read flag / Uint8 readFlag; /* Enable/Disable tail biting / Bool tailBitEnable; /* Tailbiting traceback index mode / Uint16 traceBackIndex; /* Hard decision output ordering / Uint8 outOrder; /* Performance and speed / Uint8 perf; } VCP2_BaseParams; /* VCP Error structure / typedef struct { /* Traceback mode error / Bool tbnaErr; /* Frame length error / Bool ftlErr; /* Reliability + convergence distance error / Bool fctlErr; /* Max-Min error / Bool maxminErr; /* SYMX error / Bool symxErr; /* SYMR error / Bool symrErr; } VCP2_Errors; /* VCP generator polynomials structure / typedef struct { /* Generator polynomial 0 / Uint8 poly0; /* Generator polynomial 1 / Uint8 poly1; /* Generator polynomial 2 / Uint8 poly2; /* Generator polynomial 3 / Uint8 poly3; } VCP2_Poly; /***************************************************************************** * VCP2 global function declarations ****************************************************************************/ / * ============================================================================ * @func VCP2_genParams * * @desc * This function calculates the VCP parameters based on the input * VCP2_BaseParams object values and set the values to the output * VCP2_Params parameters structure. * * @arg pConfigBase * Pointer to VCP base parameters structure. * * @arg pConfigParams * Pointer to output VCP channel parameters structure. * * @ret None * * @eg * VCP2_Params vcpParam; * VCP2_BaseParams vcpBaseParam; * ... * vcpBaseParam.rate = VCP2_RATE_1_4; * vcpBaseParam.constLen = 5; * vcpBaseParam.frameLen = 2042; * vcpBaseParam.yamTh = 50; * vcpBaseParam.stateNum = 2048; * vcpBaseParam.tbConvrgMode = FALSE; * vcpBaseParam.decision = VCP2_DECISION_HARD; * vcpBaseParam.readFlag = VCP2_OUTF_YES; * vcpBaseParam.tailBitEnable = FALSE; * vcpBaseParam.traceBackIndex = 0x0; * vcpBaseParam.outOrder = VCP2_OUTORDER_0_31; * vcpBaseParam.perf = VCP2_SPEED_CRITICAL; * ... * VCP2_genParams (&vcpBaseParam, &vcpParam); * * ============================================================================ / extern void VCP2_genParams ( VCP2_BaseParams pConfigBase, VCP2_Params * pConfigParams ); /* * ============================================================================ * @func VCP2_genIc * * @desc * This function generates the required input configuration registers' * values needed to program the VCP based on the parameters provided by * VCP2_Params object values. * * @arg pConfigParams * Pointer to channel parameters structure. * * @arg pConfigIc * Pointer to input configuration structure. * * @ret None * * @eg * VCP2_Params vcpParam; * VCP2_ConfigIc vcpConfig; * VCP2_BaseParams vcpBaseParam; * ... * vcpBaseParam.rate = VCP2_RATE_1_4; * vcpBaseParam.constLen = 5; * vcpBaseParam.frameLen = 2042; * vcpBaseParam.yamTh = 50; * vcpBaseParam.stateNum = 2048; * vcpBaseParam.tbConvrgMode = FALSE; * vcpBaseParam.decision = VCP2_DECISION_HARD; * vcpBaseParam.readFlag = VCP2_OUTF_YES; * vcpBaseParam.tailBitEnable = FALSE; * vcpBaseParam.traceBackIndex = 0x0; * vcpBaseParam.outOrder = VCP2_OUTORDER_0_31; * vcpBaseParam.perf = VCP2_SPEED_CRITICAL; * ... * VCP2_genParams (&vcpBaseParam, &vcpParam); * * VCP2_genIc (&vcpParam, &vcpConfig); * * ============================================================================ / extern void VCP2_genIc ( VCP2_Params pConfigParams, VCP2_ConfigIc * pConfigIc ); #ifdef __cplusplus } #endif #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_ectl.h	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_ectl.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for ECTL / #ifndef _CSLR_ECTL_H_ #define _CSLR_ECTL_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint8 RSVD0[4]; volatile Uint32 EWCTL; volatile Uint32 EWINTTCNT; } CSL_EctlRegs; /***********************************************************************\ Field Definition Macros \*************************************************************************/ / EWCTL / #define CSL_ECTL_EWCTL_INTEN_MASK (0x00000001u) #define CSL_ECTL_EWCTL_INTEN_SHIFT (0x00000000u) #define CSL_ECTL_EWCTL_INTEN_RESETVAL (0x00000000u) /----INTEN Tokens----/ #define CSL_ECTL_EWCTL_INTEN_DISABLE (0x00000000u) #define CSL_ECTL_EWCTL_INTEN_ENABLE (0x00000001u) #define CSL_ECTL_EWCTL_RESETVAL (0x00000000u) / EWINTTCNT */ #define CSL_ECTL_EWINTTCNT_EWINTTCNT_MASK (0x0001FFFFu) #define CSL_ECTL_EWINTTCNT_EWINTTCNT_SHIFT (0x00000000u) #define CSL_ECTL_EWINTTCNT_EWINTTCNT_RESETVAL (0x00000000u) #define CSL_ECTL_EWINTTCNT_RESETVAL (0x00000000u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/FB_Example/MEA21_lib.h	#include <csl_types.h> #include "global.h" #define MEA21_REGISTER(reg) ((volatile Uint32 )(0xa0000000+reg)) #define READ_REGISTER(reg) MEA21_REGISTER(reg) #define WRITE_REGISTER(reg, value) {MEA21_REGISTER(reg) = value; ((volatile Uint32 )(0x70000000)) = 0; ((volatile Uint32 )(0x70000000));} #ifdef INCLUDE_HS1_DATA #define HS1_CHANNELS 120 #define HS1_DATA_WORDS (HS1_CHANNELS+2) #define HS1_DATA_ENABLE 0x0200 #else #define HS1_CHANNELS 0 #define HS1_DATA_WORDS 0 #define HS1_DATA_ENABLE 0 #endif #ifdef INCLUDE_HS2_DATA #define HS2_CHANNELS 120 #define HS2_DATA_WORDS (HS2_CHANNELS+2) #define HS2_DATA_ENABLE 0x0400 #else #define HS2_CHANNELS 0 #define HS2_DATA_WORDS 0 #define HS2_DATA_ENABLE 0 #endif #ifdef INCLUDE_IF_DATA #define IF_CHANNELS 8 #define IF_DATA_WORDS (IF_CHANNELS+1) #define IF_DATA_ENABLE 0x0800 #else #define IF_CHANNELS 0 #define IF_DATA_WORDS 0 #define IF_DATA_ENABLE 0 #endif #ifdef INCLUDE_HS1_FILTER_DATA #define HF1_CHANNELS 120 #define HF1_DATA_WORDS (HF1_CHANNELS+2) #define HF1_DATA_ENABLE 0x4000 #else #define HF1_CHANNELS 0 #define HF1_DATA_WORDS 0 #define HF1_DATA_ENABLE 0 #endif #ifdef INCLUDE_HS2_FILTER_DATA #define HF2_CHANNELS 120 #define HF2_DATA_WORDS (HF2_CHANNELS+2) #define HF2_DATA_ENABLE 0x8000 #else #define HF2_CHANNELS 0 #define HF2_DATA_WORDS 0 #define HF2_DATA_ENABLE 0 #endif #ifdef INCLUDE_DIGITAL_DATA #define DIGITAL_CHANNELS 31 #define DIGITAL_DATA_WORDS (DIGITAL_CHANNELS+1) #define DIGITAL_DATA_ENABLE 0x1000 #else #define DIGITAL_CHANNELS 0 #define DIGITAL_DATA_WORDS 0 #define DIGITAL_DATA_ENABLE 0 #endif #ifdef INCLUDE_TIMESTAMP_DATA #define TIMESTAMP_CHANNELS 2 #define TIMESTAMP_DATA_WORDS (TIMESTAMP_CHANNELS+1) #define TIMESTAMP_DATA_ENABLE 0x2000 #else #define TIMESTAMP_CHANNELS 0 #define TIMESTAMP_DATA_WORDS 0 #define TIMESTAMP_DATA_ENABLE 0 #endif #define HS1_DATA_OFFSET (1) #define HS2_DATA_OFFSET (HS1_DATA_OFFSET + HS1_DATA_WORDS) #define IF_DATA_OFFSET (HS2_DATA_OFFSET + HS2_DATA_WORDS) #define HF1_DATA_OFFSET (IF_DATA_OFFSET + IF_DATA_WORDS) #define HF2_DATA_OFFSET (HF1_DATA_OFFSET + HF1_DATA_WORDS) #define DIGITAL_DATA_OFFSET (HF2_DATA_OFFSET + HF2_DATA_WORDS) #define TIMESTAMP_DATA_OFFSET (DIGITAL_DATA_OFFSET + DIGITAL_DATA_WORDS) #define CHANNELS_PER_FRAME (HS1_DATA_WORDS+HS2_DATA_WORDS+IF_DATA_WORDS+HF1_DATA_WORDS+HF2_DATA_WORDS+DIGITAL_DATA_WORDS+TIMESTAMP_DATA_WORDS) #define DSPINDATACTRL_VALUE (0x0100\| HS1_DATA_ENABLE \| HS2_DATA_ENABLE \| IF_DATA_ENABLE \| DIGITAL_DATA_ENABLE \| TIMESTAMP_DATA_ENABLE \| HF1_DATA_ENABLE \| HF2_DATA_ENABLE ) // Enable IRQ and selected data streams extern Uint32 MeaData[CHANNELS_PER_FRAME*FRAMES_PER_LOOP]; extern Uint32 MonitorData[MONITOR_ARRAY]; #define DSP_INDATA_CTRL 0x0400 #define DSP_OUTDATA_CTRL 0x0404 #define DSP_OUTDATA_THR 0x0414 #define FEEDBACK_REGISTER 0x0780 #define MAILBOX_CTRL 0x0424 void MEA21_init(); void SetMonitorSize(int datapoints);
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_mcbsp.h	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_mcbsp.h * * @path $(CSLPATH)\inc * * @desc Header file for functional layer of McBSP CSL * / /* @mainpage MCBSP CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the MCBSP module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given MCBSP module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular MCBSP Module. The CSL developer should use his discretion * designing new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 * / / ============================================================================= * Revision History * ================ * June 29,2004 <NAME> - Created * * May 17,2005 <NAME> - Removed support for 512 channel mode * - Removed support for Super synchronization * - IntEvent removed from CSL_McbspHwSetup and * added commands and queries for interrupt mode * - CSL_MCBSP_CMD_REG_RESET changed to * CSL_MCBSP_CMD_RESET * * July 04, 2005 ds - Removed support for DX Mode.Hence removed * dxState from CSL_McbspHwSetup * - Removed support for enhanced sample clock * mode. * - Register Naming convention used for * Multichannel registers are changed according * the changes in cslr_mcbsp.h * * July 26, 2005 ds - Removed control cmd * CSL_MCBSP_CMD_IO_MODE_CONTROL. * * Sept 21, 2005 ds - Removed the DXR and DRR register from the * config data structure * * Oct 27, 2005 ds - Removed CSL_MCBSP_QUERY_PID query from * CSL_McbspHwStatusQuery * * Feb 02 , 2006 ds - IntEvent added to CSL_McbspHwSetup and * removed interrupt mode commands and queries * ============================================================================= / #ifndef _CSL_MCBSP_H_ #define _CSL_MCBSP_H_ #ifdef __cplusplus extern "C" { #endif #include <soc.h> #include <csl.h> #include <cslr_mcbsp.h> /************************************************************************\ MCBSP global macro declarations \************************************************************************/ / * Use this symbol as pin mask for @a CSL_mcbspIoRead() and * CSL_mcbspIoWrite() functions / /* I/O Pin Input/Output configuration for CLKX Pin / #define CSL_MCBSP_IO_CLKX (1) /* I/O Pin Input/Output configuration for FSX Pin / #define CSL_MCBSP_IO_FSX (2) /* Not Configurable. Always Output. / #define CSL_MCBSP_IO_DX (4) /* I/O Pin Input/Output configuration for CLKR Pin / #define CSL_MCBSP_IO_CLKR (8) /* I/O Pin Input/Output configuration for FSR Pin / #define CSL_MCBSP_IO_FSR (16) /* Not Configurable. Always Input. / #define CSL_MCBSP_IO_DR (32) /* Not Configurable. Always Input. / #define CSL_MCBSP_IO_CLKS (64) /* * Use this symbol as enable/disable control bitmask for * CSL_mcbspHwControl() function / /* To enable Receiver in resetControl Function / #define CSL_MCBSP_CTRL_RX_ENABLE (1) /* To enable Transmitter in resetControl Function / #define CSL_MCBSP_CTRL_TX_ENABLE (2) /* To disable Receiver in resetControl Function / #define CSL_MCBSP_CTRL_RX_DISABLE (4) /* To disable Transmitter in resetControl Function / #define CSL_MCBSP_CTRL_TX_DISABLE (8) /* To enable Frame Sync Generation in resetControl Function / #define CSL_MCBSP_CTRL_FSYNC_ENABLE (16) /* To enable Sample Rate Generator in resetControl Function / #define CSL_MCBSP_CTRL_SRG_ENABLE (32) /* To disable Frame Sync Generation in resetControl Function / #define CSL_MCBSP_CTRL_FSYNC_DISABLE (64) /* To disable Sample Rate Generator in resetControl Function / #define CSL_MCBSP_CTRL_SRG_DISABLE (128) /* * Use this symbol to compare the return value of @a CSL_mcbspGetHwStatus() * function for @a CSL_MCBSP_QUERY_DEV_STATUS query * \n For eg:- On RFULL event, (response & CSL_MCBSP_RFULL) == 0x0004 / /* RCV ready status / #define CSL_MCBSP_RRDY 0x0001 /* XMT ready status / #define CSL_MCBSP_XRDY 0x0002 /* RCV full status / #define CSL_MCBSP_RFULL 0x0004 /* XMT empty status / #define CSL_MCBSP_XEMPTY 0x0008 /* RCV frame sync error status / #define CSL_MCBSP_RSYNCERR 0x0010 /* XMT frame sync error status / #define CSL_MCBSP_XSYNCERR 0x0020 /* CSL_EMCBSP_SYMBOL Error codes / /* Invalid Control Command / #define CSL_EMCBSP_INVCNTLCMD (CSL_EMCBSP_FIRST - 0) /* Invalid Query / #define CSL_EMCBSP_INVQUERY (CSL_EMCBSP_FIRST - 1) /* Invalid Parameter / #define CSL_EMCBSP_INVPARAMS (CSL_EMCBSP_FIRST - 2) /* Invalid Size / #define CSL_EMCBSP_INVSIZE (CSL_EMCBSP_FIRST - 3) /* 'Does not exist' / #define CSL_EMCBSP_NOTEXIST (CSL_EMCBSP_FIRST - 4) /* Invalid mode to conduct operation / #define CSL_EMCBSP_INVMODE (CSL_EMCBSP_FIRST - 5) /* CSL_MCBSP_DEFAULT_SYMBOL MCBSP CSL Defaults / /* Data Setup defaults / #define CSL_MCBSP_DATASETUP_DEFAULTS { \ (CSL_McbspPhase)CSL_MCBSP_PHASE_SINGLE, \ (CSL_McbspWordLen)CSL_MCBSP_WORDLEN_16, \ 1, \ (CSL_McbspWordLen)0, \ 0, \ (CSL_McbspFrmSync)CSL_MCBSP_FRMSYNC_DETECT, \ (CSL_McbspCompand)CSL_MCBSP_COMPAND_OFF_MSB_FIRST, \ (CSL_McbspDataDelay)CSL_MCBSP_DATADELAY_0_BIT, \ (CSL_McbspRjustDxena)0, \ (CSL_McbspIntMode)CSL_MCBSP_INTMODE_ON_READY, \ (CSL_McbspBitReversal)CSL_MCBSP_32BIT_REVERS_DISABLE }\ /* Clock Setup defaults / #define CSL_MCBSP_CLOCKSETUP_DEFAULTS { \ (CSL_McbspFsClkMode)CSL_MCBSP_FSCLKMODE_EXTERNAL, \ (CSL_McbspFsClkMode)CSL_MCBSP_FSCLKMODE_EXTERNAL, \ (CSL_McbspTxRxClkMode)CSL_MCBSP_TXRXCLKMODE_INTERNAL, \ (CSL_McbspTxRxClkMode)CSL_MCBSP_TXRXCLKMODE_EXTERNAL, \ (CSL_McbspFsPol)0, \ (CSL_McbspFsPol)0, \ (CSL_McbspClkPol)0, \ (CSL_McbspClkPol)0, \ 1, \ 0x40, \ 0xFF, \ (CSL_McbspSrgClk)0, \ (CSL_McbspClkPol)0, \ (CSL_McbspTxFsMode)CSL_MCBSP_TXFSMODE_SRG, \ (CSL_McbspClkgSyncMode)CSL_MCBSP_CLKGSYNCMODE_OFF }\ /* Multichannel Setup defaults / #define CSL_MCBSP_MULTICHAN_DEFAULTS { \ (CSL_McbspPartMode)CSL_MCBSP_PARTMODE_2PARTITION, \ (CSL_McbspPartMode)CSL_MCBSP_PARTMODE_2PARTITION, \ (Uint16)0, \ (Uint16)0, \ (CSL_McbspPABlk)CSL_MCBSP_PABLK_0, \ (CSL_McbspPBBlk)CSL_MCBSP_PBBLK_1, \ (CSL_McbspPABlk)CSL_MCBSP_PABLK_0, \ (CSL_McbspPBBlk)CSL_MCBSP_PBBLK_1, \ }\ /* Global parameters Setup defaults / #define CSL_MCBSP_GLOBALSETUP_DEFAULTS { \ (CSL_McbspIOMode)CSL_MCBSP_IOMODE_TXDIS_RXDIS, \ (CSL_McbspDlbMode)CSL_MCBSP_DLBMODE_OFF, \ (CSL_McbspClkStp)CSL_MCBSP_CLKSTP_DISABLE } \ /* Default Emulation mode - Stop / #define CSL_MCBSP_EMUMODE_DEFAULT CSL_MCBSP_EMU_STOP /* Extend Setup default - NULL / #define CSL_MCBSP_EXTENDSETUP_DEFAULT NULL /************************************************************************\ MCBSP global typedef declarations \************************************************************************/ / * Word lengths supported on MCBSP.Use this symbol for setting Word * Length in each Phase for every Frame / typedef enum { /* Word Length for Frame is 8 / CSL_MCBSP_WORDLEN_8 = 0, /* Word Length for Frame is 12 / CSL_MCBSP_WORDLEN_12 = 1, /* Word Length for Frame is 16 / CSL_MCBSP_WORDLEN_16 = 2, /* Word Length for Frame is 20 / CSL_MCBSP_WORDLEN_20 = 3, /* Word Length for Frame is 24 / CSL_MCBSP_WORDLEN_24 = 4, /* Word Length for Frame is 32 / CSL_MCBSP_WORDLEN_32 = 5 } CSL_McbspWordLen; /* * MCBSP companding options - Use this symbol to set Companding related options / typedef enum { /* no companding for msb / CSL_MCBSP_COMPAND_OFF_MSB_FIRST = 0, /* no companding for lsb / CSL_MCBSP_COMPAND_OFF_LSB_FIRST = 1, /* mu-law comapanding enable for channel / CSL_MCBSP_COMPAND_MULAW = 2, /* A-law comapanding enable for channel / CSL_MCBSP_COMPAND_ALAW = 3 } CSL_McbspCompand; /* * Data delay in bits - Use this symbol to set XMT/RCV Data Delay (in bits) / typedef enum { /* sets XMT/RCV Data Delay is 0 / CSL_MCBSP_DATADELAY_0_BIT = 0, /* sets XMT/RCV Data Delay is 1 / CSL_MCBSP_DATADELAY_1_BIT = 1, /* sets XMT/RCV Data Delay is 2 / CSL_MCBSP_DATADELAY_2_BITS = 2 } CSL_McbspDataDelay; /* * MCBSP Interrupt mode - * Use this symbol to set Interrupt mode (i.e. source of interrupt generation). * This symbol is used on both RCV and XMT for RINT and XINT generation mode. / typedef enum { /* Interrupt generated on RRDY of RCV or XRDY of XMT / CSL_MCBSP_INTMODE_ON_READY = 0, /* Interrupt generated on end of 16-channel block transfer * in multichannel mode / CSL_MCBSP_INTMODE_ON_EOB = 1, /* Interrupt generated on frame sync / CSL_MCBSP_INTMODE_ON_FSYNC = 2, /* Interrupt generated on synchronisation error / CSL_MCBSP_INTMODE_ON_SYNCERR = 3 } CSL_McbspIntMode; /* * Frame sync clock source - Use this symbol to set the frame sync clock * source as internal or external / typedef enum { /* frame sync clock source as external / CSL_MCBSP_FSCLKMODE_EXTERNAL = 0, /* frame sync clock source as internal / CSL_MCBSP_FSCLKMODE_INTERNAL = 1 } CSL_McbspFsClkMode; /* * Clock source - Use this symbol to set the clock source as * internal or external / typedef enum { /* clock source as external / CSL_MCBSP_TXRXCLKMODE_EXTERNAL = 0, /* clock source as internal / CSL_MCBSP_TXRXCLKMODE_INTERNAL = 1 } CSL_McbspTxRxClkMode; /* * Frame sync polarity - Use this symbol to set frame sync polarity as * active-high or active-low / typedef enum { /* frame sync polarity is active-high / CSL_MCBSP_FSPOL_ACTIVE_HIGH = 0, /* frame sync polarity is active-low / CSL_MCBSP_FSPOL_ACTIVE_LOW = 1 } CSL_McbspFsPol; /* * Clock polarity - Use this symbol to set XMT or RCV clock polarity as * rising or falling edge / typedef enum { /* XMT clock polarity is rising edge / CSL_MCBSP_CLKPOL_TX_RISING_EDGE = 0, /* RCV clock polarity is falling edge / CSL_MCBSP_CLKPOL_RX_FALLING_EDGE = 0, /* SRG clock polarity is rising edge / CSL_MCBSP_CLKPOL_SRG_RISING_EDGE = 0, /* XMT clock polarity is falling edge / CSL_MCBSP_CLKPOL_TX_FALLING_EDGE = 1, /* RCV clock polarity is rising edge / CSL_MCBSP_CLKPOL_RX_RISING_EDGE = 1, /* SRG clock polarity Is falling edge / CSL_MCBSP_CLKPOL_SRG_FALLING_EDGE = 1 } CSL_McbspClkPol; /* * SRG clock source - Use this symbol to select input clock source * for Sample Rate Generator / typedef enum { /* input clock source for Sample Rate Generator is CLKS pin / CSL_MCBSP_SRGCLK_CLKS = 0, /* input clock source for Sample Rate Generator is CPU / CSL_MCBSP_SRGCLK_CLKCPU = 1 } CSL_McbspSrgClk; /* * XMT Frame Sync generation mode - Use this symbol to set XMT Frame Sync * generation mode / typedef enum { /* Disables the frame sync generation mode / CSL_MCBSP_TXFSMODE_DXRCOPY = 0, /* Enables the frame sync generation mode / CSL_MCBSP_TXFSMODE_SRG = 1 } CSL_McbspTxFsMode; /* * XMT and RCV IO Mode - Use this symbol to Enable/Disable IO Mode * for XMT and RCV / typedef enum { /* Disable the both XMT and RCV IO mode / CSL_MCBSP_IOMODE_TXDIS_RXDIS = 0, /* Disable XMT and enable RCV IO mode / CSL_MCBSP_IOMODE_TXDIS_RXEN = 1, /* Enable XMT and Disble RCV IO mode / CSL_MCBSP_IOMODE_TXEN_RXDIS = 2, /* Enable XMT and enable RCV IO mode / CSL_MCBSP_IOMODE_TXEN_RXEN = 3 } CSL_McbspIOMode; /* * Clock Stop Mode - Use this symbol to Enable/Disable Clock Stop Mode / typedef enum { /* Disable the clock stop mode / CSL_MCBSP_CLKSTP_DISABLE = 0, /* Emable the clock stop mode with out delay / CSL_MCBSP_CLKSTP_WITHOUT_DELAY = 2, /* Emable the clock stop mode with delay / CSL_MCBSP_CLKSTP_WITH_DELAY = 3 } CSL_McbspClkStp; /* * Multichannel mode Partition type - Use this symbol to select the partition * type in multichannel mode / typedef enum { /* two partition mode / CSL_MCBSP_PARTMODE_2PARTITION = 0, /* Eight partition multichannel mode / CSL_MCBSP_PARTMODE_8PARTITION = 1 } CSL_McbspPartMode; /* * Multichannel mode PartitionA block - Use this symbol to assign Blocks to * Partition-A in multichannel mode / typedef enum { /* Block 0 for partition A / CSL_MCBSP_PABLK_0 = 0, /* Block 2 for partition A / CSL_MCBSP_PABLK_2 = 1, /* Block 4 for partition A / CSL_MCBSP_PABLK_4 = 2, /* Block 6 for partition A / CSL_MCBSP_PABLK_6 = 3 } CSL_McbspPABlk; /* * Multichannel mode PartitionB block - Use this symbol to assign Blocks to * Partition-B in multichannel mode / typedef enum { /* Block 1 for partition B / CSL_MCBSP_PBBLK_1 = 0, /* Block 3 for partition B / CSL_MCBSP_PBBLK_3 = 1, /* Block 5 for partition B / CSL_MCBSP_PBBLK_5 = 2, /* Block 7 for partition B / CSL_MCBSP_PBBLK_7 = 3 } CSL_McbspPBBlk; /* * Emulation mode setting - Use this symbol to set the Emulation Mode / typedef enum { /* Emulation mode stop / CSL_MCBSP_EMU_STOP = 0, /* Emulation mode TX stop / CSL_MCBSP_EMU_TX_STOP = 1, /* Emulation free run mode / CSL_MCBSP_EMU_FREERUN = 2 } CSL_McbspEmu; /* * Multichannel mode Partition select - Use this symbol in multichannel mode to * select the Partition for assigning a block to / typedef enum { /* TX partition for A / CSL_MCBSP_PARTITION_ATX = 0, /* RX partition for A / CSL_MCBSP_PARTITION_ARX = 1, /* TX partition for B / CSL_MCBSP_PARTITION_BTX = 2, /* RX partition for B / CSL_MCBSP_PARTITION_BRX = 3 } CSL_McbspPartition; /* * Multichannel mode Block select - Use this symbol in multichannel mode to * select block on which the operation is to be performed / typedef enum { /* Block 0 for multichannel mode / CSL_MCBSP_BLOCK_0 = 0, /* Block 1 for multichannel mode / CSL_MCBSP_BLOCK_1 = 1, /* Block 2 for multichannel mode / CSL_MCBSP_BLOCK_2 = 2, /* Block 3 for multichannel mode / CSL_MCBSP_BLOCK_3 = 3, /* Block 4 for multichannel mode / CSL_MCBSP_BLOCK_4 = 4, /* Block 5 for multichannel mode / CSL_MCBSP_BLOCK_5 = 5, /* Block 6 for multichannel mode / CSL_MCBSP_BLOCK_6 = 6, /* Block 7 for multichannel mode / CSL_MCBSP_BLOCK_7 = 7 } CSL_McbspBlock; /* * Channel control in multichannel mode * Use this symbol to enable/disable a channel in multichannel mode. * This is a member of CSL_McbspChanControl structure, which is input to * CSL_mcbspHwControl() function for CSL_MCBSP_CMD_CHANNEL_CONTROL command / typedef enum { /* TX enable for multichannel mode / CSL_MCBSP_CHCTRL_TX_ENABLE = 0, /* TX disable for multichannel mode / CSL_MCBSP_CHCTRL_TX_DISABLE = 1, /* RX enable for multichannel mode / CSL_MCBSP_CHCTRL_RX_ENABLE = 2, /* RX disable for multichannel mode / CSL_MCBSP_CHCTRL_RX_DISABLE = 3 } CSL_McbspChCtrl; /* * Channel type: TX, RX or both - Use this symbol to select the channel type for * CSL_mcbspHwControl() / typedef enum { /* Channel type is RX / CSL_MCBSP_CHTYPE_RX = 1, /* Channel type is TX / CSL_MCBSP_CHTYPE_TX = 2, /* Channel type is TXRX / CSL_MCBSP_CHTYPE_TXRX = 4 } CSL_McbspChType; /* * Digital Loopback mode selection - Use this symbol to enable/disable digital * loopback mode / typedef enum { /* disable digital loopback mode / CSL_MCBSP_DLBMODE_OFF = 0, /* enable digital loopback mode / CSL_MCBSP_DLBMODE_ON = 1 } CSL_McbspDlbMode; /* * Phase count selection - Use this symbol to select number of phases per frame / typedef enum { /* Single phase for frame / CSL_MCBSP_PHASE_SINGLE = 0, /* Dual phase for frame / CSL_MCBSP_PHASE_DUAL = 1 } CSL_McbspPhase; /* * Frame sync ignore status - Use this symbol to detect or ignore * frame synchronisation / typedef enum { /* detect frame synchronisation / CSL_MCBSP_FRMSYNC_DETECT = 0, /* ignore frame synchronisation / CSL_MCBSP_FRMSYNC_IGNORE = 1 } CSL_McbspFrmSync; /* * RJUST or DXENA settings - Use this symbol for setting up RCV sign-extension * and justification mode or enabling/disabling XMT DX pin delay / typedef enum { /* RCV setting - right justify, fill MSBs with zeros / CSL_MCBSP_RJUSTDXENA_RJUST_RZF = 0, /* XMT setting - Delay at DX pin disabled / CSL_MCBSP_RJUSTDXENA_DXENA_OFF = 0, /* RCV setting - right justify, sign-extend the data into MSBs / CSL_MCBSP_RJUSTDXENA_RJUST_RSE = 1, /* XMT setting - Delay at DX pin enabled / CSL_MCBSP_RJUSTDXENA_DXENA_ON = 1, /* RCV setting - left justify, fill LSBs with zeros / CSL_MCBSP_RJUSTDXENA_RJUST_LZF = 2 } CSL_McbspRjustDxena; /* * CLKG sync mode selection - Use this symbol to enable/disable CLKG * synchronisation when input CLK source for SRGR is external / typedef enum { /* disable CLKG synchronisation / CSL_MCBSP_CLKGSYNCMODE_OFF = 0, /* enable CLKG synchronisation / CSL_MCBSP_CLKGSYNCMODE_ON = 1 } CSL_McbspClkgSyncMode; /* * Tx/Rx reset status - Use this symbol to compare the output of * CSL_mcbspGetHwStatus() for CSL_MCBSP_QUERY_TX_RST_STAT and * CSL_MCBSP_QUERY_RX_RST_STAT queries / typedef enum { /* disable the XRST bit / CSL_MCBSP_RSTSTAT_TX_IN_RESET = 0, /* disable the RRST bit / CSL_MCBSP_RSTSTAT_RX_IN_RESET = 0, /* enable the XRST bit / CSL_MCBSP_RSTSTAT_TX_OUTOF_RESET = 1, /* enable the RRST bit / CSL_MCBSP_RSTSTAT_RX_OUTOF_RESET = 1 } CSL_McbspRstStat; /* McBSP 32-bit reversal feature / typedef enum { /* 32-bit reversal disabled / CSL_MCBSP_32BIT_REVERS_DISABLE = 0, /* 32-bit reversal enabled. 32-bit data is received LSB first. Word length * should be set for 32-bit operation; else operation undefined / CSL_MCBSP_32BIT_REVERS_ENABLE = 1 } CSL_McbspBitReversal; /* * This is the set of control commands that are passed to * CSL_mcbspHwControl(), with an optional argument type-casted to void* * The arguments, if any, to be passed with each command are specified * next to that command. / typedef enum { /* * @brief Assigns a block to a particular partition in multichannel * mode * @param (CSL_McbspBlkAssign ) / CSL_MCBSP_CMD_ASSIGN_BLOCK = 0, /** * @brief Enables or disables a channel in multichannel mode * @param (CSL_McbspChanControl ) / CSL_MCBSP_CMD_CHANNEL_CONTROL = 1, /** * @brief Clears frame sync error for XMT or RCV * @param (CSL_McbspChType ) / CSL_MCBSP_CMD_CLEAR_FRAME_SYNC = 2, /** * @brief Resets all the registers to their power-on default values * @param None / CSL_MCBSP_CMD_RESET = 3, /* * @brief Enable/Disable - Frame Sync, Sample Rate Generator and * XMT/RCV Operation * @param (CSL_BitMask16 ) / CSL_MCBSP_CMD_RESET_CONTROL = 4 } CSL_McbspControlCmd; /** * This is the set of query commands to get the status of various * operations in MCBSP * The arguments, if any, to be passed with each command are specified * next to that command / typedef enum { /* * @brief Queries the current XMT block * @param (CSL_McbspBlock ) / CSL_MCBSP_QUERY_CUR_TX_BLK = 1, /** * @brief Queries the current RCV block * @param (CSL_McbspBlock ) / CSL_MCBSP_QUERY_CUR_RX_BLK = 2, /** * @brief Queries the status of RRDY, XRDY, RFULL, XEMPTY, RSYNCERR * and XSYNCERR events and returns them in supplied * CSL_BitMask16 argument * @param (CSL_BitMask16 ) / CSL_MCBSP_QUERY_DEV_STATUS = 3, /** * @brief Queries XMT reset status * @param (CSL_McbspRstStat ) @return CSL_SOK / CSL_MCBSP_QUERY_TX_RST_STAT = 4, /* * @brief Queries RCV reset status * @param (CSL_McbspRstStat ) / CSL_MCBSP_QUERY_RX_RST_STAT = 5 } CSL_McbspHwStatusQuery; /** * This will have the base-address information for the peripheral instance / typedef struct { /* Base-address of the Configuration registers of MCBSP / CSL_McbspRegsOvly regs; } CSL_McbspBaseAddress; /* * MCBSP specific parameters. Present implementation doesn't have * any specific parameters. / typedef struct { /* Bit mask to be used for module specific parameters. * The below declaration is just a place-holder for future * implementation. / CSL_BitMask16 flags; } CSL_McbspParam; /* * MCBSP specific context information. Present implementation doesn't * have any Context information. / typedef struct { /* Context information of MCBSP. * The below declaration is just a place-holder for future * implementation. / Uint16 contextInfo; } CSL_McbspContext; /* * Pointer to this structure is used as the third argument in * CSL_mcbspHwControl() for block assignment in multichannel mode / typedef struct CSL_McbspBlkAssign { /* Partition to choose / CSL_McbspPartition partition; /* Block to choose / CSL_McbspBlock block; } CSL_McbspBlkAssign; /* * Pointer to this structure is used as the third argument in * CSL_mcbspHwControl() for channel control operations (Enable/Disable TX/RX) * in multichannel mode. / typedef struct CSL_McbspChanControl { /* Channel number to control / Uint16 channelNo; /* Control operation / CSL_McbspChCtrl operation; } CSL_McbspChanControl; /* * This is a sub-structure in @ CSL_McbspHwSetup. This structure is used for * configuring input/output data related parameters. / typedef struct CSL_McbspDataSetup { /* Number of phases in a frame / CSL_McbspPhase numPhases; /* Number of bits per word in phase 1 / CSL_McbspWordLen wordLength1; /* Number of words per frame in phase 1 / Uint16 frmLength1; /* Number of bits per word in phase 2 / CSL_McbspWordLen wordLength2; /* Number of words per frame in phase 2 / Uint16 frmLength2; /* Frame Sync ignore / CSL_McbspFrmSync frmSyncIgn; /* Companding options / CSL_McbspCompand compand; /* Data delay in number of bits / CSL_McbspDataDelay dataDelay; /* Controls DX delay for XMT or sign-extension and justification for RCV / CSL_McbspRjustDxena rjust_dxenable; /* Interrupt event mask / CSL_McbspIntMode intEvent; /* 32-bit reversal feature / CSL_McbspBitReversal wordReverse; } CSL_McbspDataSetup; /* * This is a sub-structure in @a CSL_McbspHwSetup. This structure is used for * configuring Clock and Frame Sync generation parameters. / typedef struct CSL_McbspClkSetup { /* XMT frame sync mode / CSL_McbspFsClkMode frmSyncTxMode; /* RCV frame sync mode / CSL_McbspFsClkMode frmSyncRxMode; /* XMT clock mode / CSL_McbspTxRxClkMode clkTxMode; /* RCV clock mode / CSL_McbspTxRxClkMode clkRxMode; /* XMT frame sync polarity / CSL_McbspFsPol frmSyncTxPolarity; /* RCV frame sync polarty / CSL_McbspFsPol frmSyncRxPolarity; /* XMT clock polarity / CSL_McbspClkPol clkTxPolarity; /* RCV clock polarity / CSL_McbspClkPol clkRxPolarity; /* SRG frame sync pulse width / Uint16 srgFrmPulseWidth; /* SRG frame sync period / Uint16 srgFrmPeriod; /* SRG divide-down ratio / Uint16 srgClkDivide; /* SRG input clock mode / CSL_McbspSrgClk srgInputClkMode; /* SRG clock polarity / CSL_McbspClkPol srgClkPolarity; /* SRG XMT frame-synchronisatoin mode / CSL_McbspTxFsMode srgTxFrmSyncMode; /* SRG clock synchronisation mode / CSL_McbspClkgSyncMode srgClkSync; } CSL_McbspClkSetup; /* * This is a sub-structure in @a CSL_McbspHwSetup. This structure is used * for configuring the parameters global to MCBSP / typedef struct CSL_McbspGlobalSetup { /* XMT and RCV IO enable bit / CSL_McbspIOMode ioEnableMode; /* Digital Loopback mode / CSL_McbspDlbMode dlbMode; /* Clock stop mode / CSL_McbspClkStp clkStopMode; } CSL_McbspGlobalSetup; /* * This is a sub-structure in @a CSL_McbspHwSetup. This structure is used * for configuring Multichannel mode parameters / typedef struct CSL_McbspMulChSetup { /* RCV partition / CSL_McbspPartMode rxPartition; /* XMT partition / CSL_McbspPartMode txPartition; /* RCV multichannel selection mode / Uint16 rxMulChSel; /* XMT multichannel selection mode / Uint16 txMulChSel; /* RCV partition A block / CSL_McbspPABlk rxPartABlk; /* RCV partition B block / CSL_McbspPBBlk rxPartBBlk; /* XMT partition A block / CSL_McbspPABlk txPartABlk; /* XMT partition B block / CSL_McbspPBBlk txPartBBlk; } CSL_McbspMulChSetup; /* * This is the Setup structure for configuring MCBSP using CSL_mcbspHwSetup() * function. / typedef struct CSL_McbspHwSetup { /* Global configuration parameters / CSL_McbspGlobalSetup global; /** RCV data setup related parameters / CSL_McbspDataSetup rxdataset; /** XMT data setup related parameters / CSL_McbspDataSetup txdataset; /** Clock configuration parameters / CSL_McbspClkSetup clkset; /** Multichannel mode configuration parameters / CSL_McbspMulChSetup mulCh; /** Emulation mode parameters / CSL_McbspEmu emumode ; /* Any extra parameters, for future use / void extendSetup; } CSL_McbspHwSetup; /** * This structure/object holds the context of the instance of MCBSP * opened using CSL_mcbspOpen() function. * * Pointer to this object is passed as MCBSP Handle to all MCBSP CSL APIs. * CSL_mcbspOpen() function intializes this structure based on the parameters * passed / typedef struct CSL_McbspObj { /* Pointer to the register overlay structure of the MCBSP / CSL_McbspRegsOvly regs; /* Instance of MCBSP being referred by this object / CSL_InstNum perNum; } CSL_McbspObj; /* This is a pointer to @a CSL_McbspObj and is passed as the first * parameter to all MCBSP CSL APIs / typedef struct CSL_McbspObj CSL_McbspHandle; /*************************************************************************\ Register Configuration Structure of MCBSP \************************************************************************/ / @brief Config structure of MCBSP. * * This is used to configure MCBSP using CSL_HwSetupRaw function / typedef struct { /* Config structure of MCBSP. This is used to configure MCBSP * using CSL_HwSetupRaw function / /* Serial Port Control Register / volatile Uint32 SPCR; /* Receive Control Register / volatile Uint32 RCR; /* Transmit Control Register / volatile Uint32 XCR; /* Sample Rate Generator Register / volatile Uint32 SRGR; /* Multichannel Control Register / volatile Uint32 MCR; /* Receive Channel Enable Register for Partition A and B / volatile Uint32 RCERE0; /* Transmit Channel Enable Register for Partition A and B / volatile Uint32 XCERE0; /* Pin Control Register / volatile Uint32 PCR; /* Receive Channel Enable Register for Partition C and D / volatile Uint32 RCERE1; /* Transmit Channel Enable Register for Partition C and D / volatile Uint32 XCERE1; /* Receive Channel Enable Register for Partition E and F / volatile Uint32 RCERE2; /* Transmit Channel Enable Register for Partition E and F / volatile Uint32 XCERE2; /* Receive Channel Enable Register for Partition G and H / volatile Uint32 RCERE3; /* Transmit Channel Enable Register for Partition G and H / volatile Uint32 XCERE3; } CSL_McbspConfig; /* Default Values for Config structure / #define CSL_MCBSP_CONFIG_DEFAULTS { \ CSL_MCBSP_SPCR_RESETVAL, \ CSL_MCBSP_RCR_RESETVAL, \ CSL_MCBSP_XCR_RESETVAL, \ CSL_MCBSP_SRGR_RESETVAL, \ CSL_MCBSP_MCR_RESETVAL, \ CSL_MCBSP_RCERE0_RESETVAL, \ CSL_MCBSP_XCERE0_RESETVAL, \ CSL_MCBSP_PCR_RESETVAL, \ CSL_MCBSP_RCERE1_RESETVAL, \ CSL_MCBSP_XCERE1_RESETVAL, \ CSL_MCBSP_RCERE2_RESETVAL, \ CSL_MCBSP_XCERE2_RESETVAL, \ CSL_MCBSP_RCERE3_RESETVAL, \ CSL_MCBSP_XCERE3_RESETVAL \ } / ***********************************************************************\ MCBSP global function declarations \* ***********************************************************************/ / * ============================================================================= * @func CSL_mcbspInit * * @desc * This function is idempotent i.e. calling it many times is same as * calling it once. This function is only for book-keeping purpose * and it doesn't touch the hardware (read/write registers) in any manner. * * @arg pContext * Context information for mcbsp * * @ret CSL_Status * CSL_SOK - Always returns * * @eg * CSL_mcbspInit (NULL); * ============================================================================= / extern CSL_Status CSL_mcbspInit ( CSL_McbspContext pContext ); /* ============================================================================ @func CSL_mcbspOpen * * @desc * Reserves the specified MCBSP for use. The device can be re-opened * anytime after it has been normally closed, if so required. The MCBSP * handle returned by this call is input as an essential argument for * the rest of the APIs in MCBSP module. * * @arg pMcbspObj * Pointer to the object that holds reference to the instance of MCBSP * requested after the call * * @arg mcbspNum * Instance of mcbsp CSL to be opened. * * @arg pMcbspParam * Pointer to module specific parameters * * @arg pStatus * pointer for returning status of the function call * * @ret CSL_McbspHandle * Valid mcbsp instance handle will be returned * if status value is equal to CSL_SOK. * * @eg * CSL_McbspHandle hMcbsp; * CSL_McbspObj mcbspObj; * CSL_McbspHwSetup mcbspSetup; * CSL_Status status; * ... * hMcbsp = CSL_mcbspOpen(&mcbspObj, CSL_MCBSP_0, NULL, &status); * ... * =========================================================================== / extern CSL_McbspHandle CSL_mcbspOpen ( CSL_McbspObj pMcbspObj, CSL_InstNum mcbspNum, CSL_McbspParam pMcbspParam, CSL_Status pStatus ); /* ============================================================================ @func CSL_mcbspClose * * @desc * Unreserves the MCBSP identified by the handle passed. * * @arg hMcbsp * Mcbsp handle * * @ret CSL_Status * CSL_SOK - Close successful * CSL_ESYS_BADHANDLE - Invalid handle * * @eg * CSL_McbspHandle hMcbsp; * CSL_McbspObj mcbspObj; * CSL_McbspHwSetup mcbspSetup; * CSL_Status status; * ... * hMcbsp = CSL_mcbspOpen(&mcbspObj, CSL_MCBSP_0, NULL, &status); * ... * CSL_mcbspClose(hMcbsp); * =========================================================================== / extern CSL_Status CSL_mcbspClose ( CSL_McbspHandle hMcbsp ); / * ============================================================================= * @func CSL_mcbspHwSetup * * @desc * Configures the MCBSP using the values passed in the setup structure. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg hwSetup * Pointer to hardware setup structure * * @ret CSL_Status * CSL_SOK - Hardware setup successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @eg * CSL_mcbspHandle hMcbsp; * CSL_McbspHwSetup hwSetup = CSL_MCBSP_HWSETUP_DEFAULTS; * ... * * // Init Successfully done * ... * // Open Successfully done * ... * CSL_mcbspHwSetup(hMcbsp, &hwSetup); * ... * =========================================================================== / extern CSL_Status CSL_mcbspHwSetup ( CSL_McbspHandle hMcbsp, CSL_McbspHwSetup setup ); /* * ============================================================================= * @func CSL_mcbspHwSetupRaw * * @desc * This function initializes the device registers with the register-values * provided through the Config Data structure. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg config * Pointer to config structure * * @ret CSL_Status * CSL_SOK - Configuration successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Config structure is not * properly initialized * * @eg * CSL_mcbspHandle hMcbsp; * CSL_McbspConfig config = CSL_MCBSP_CONFIG_DEFAULTS; * CSL_Status status; * ... * status = CSL_mcbspHwSetupRaw (hMcbsp, &config); * ... * =========================================================================== / extern CSL_Status CSL_mcbspHwSetupRaw ( CSL_McbspHandle hMcbsp, CSL_McbspConfig config ); /* * ============================================================================= * @func CSL_mcbspRead * * @desc * Reads the data from MCBSP. The word length for the read operation is * specefied using wordLen argument. According to this word length, * appropriate amount of data will read in the data object (variable); * the pointer to which is passed as the third argument. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg wordLen * Word length of data to be read in * * @arg data * Pointer to data object (variable) that will hold the input data * * @ret CSL_Status * CSL_SOK - Read successful * CSL_EMCBSP_INVSIZE - Invalid word length * CSL_ESYS_INVPARAMS - Invalid data pointer * * @eg * CSL_mcbspHandle hMcbsp; * Uint16 inData; * CSL_Status status; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init, Open, HwSetup successfully done in that order * ... * // MCBSP SRG, Frame sync, RCV taken out of reset in that order * ... * status = CSL_mcbspRead(hMcbsp, CSL_MCBSP_WORDLEN_16, &inData); * ... * =========================================================================== / extern CSL_Status CSL_mcbspRead ( CSL_McbspHandle hMcbsp, CSL_McbspWordLen wordLen, void data ); /* * ============================================================================= * @func CSL_mcbspWrite * * @desc * Transmits the data from MCBSP. The word length for the write operation is * specefied using wordLen argument. According to this word length, the * appropriate amount of data will transmitted from the data object (variable); * the pointer to which is passed as the third argument. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg wordLen * Word length of data to be write * * @arg data * Pointer to data object (variable) that holds the data to be sent out * * @ret CSL_Status * CSL_SOK - Read successful * CSL_EMCBSP_INVSIZE - Invalid word length * CSL_ESYS_INVPARAMS - Invalid data pointer * * @eg * CSL_mcbspHandle hMcbsp; * Uint16 outData; * CSL_Status status; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init, Open, HwSetup successfully done in that order * ... * // MCBSP SRG, Frame sync, RCV taken out of reset in that order * ... * outData = 0x1234; * status = CSL_mcbspWrite(hMcbsp,CSL_MCBSP_WORDLEN_16,&outData); * ... * =========================================================================== / extern CSL_Status CSL_mcbspWrite ( CSL_McbspHandle hMcbsp, CSL_McbspWordLen wordLen, void data ); /* * ============================================================================= * @func CSL_mcbspIoWrite * * @desc * Sends the data using MCBSP pin which is configured as general purpose * output.The 16-bit data trasnmitted is specified by 'outputData' argument. * MCBSP pin to use in this write operation is identified by the second * argument. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg outputSel * MCBSP pin to be used as general purpose output * * @arg outputData * 1 bit output data to be transmitted * * @ret * None * * @eg * Uint16 outData; * CSL_Status status; * CSL_McbspHandle hMcbsp; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init, Open, HwSetup successfully done in that order * ... * outData = 1; * inData = CSL_mcbspIoWrite(hMcbsp, CSL_MCBSP_IO_CLKX, outData); * ... * =========================================================================== / extern void CSL_mcbspIoWrite ( CSL_McbspHandle hMcbsp, CSL_BitMask16 outputSel, Uint16 outputData ); / * ============================================================================= * @func CSL_mcbspIoWrite * * @desc * Reads the data from MCBSP pin which is configured as general purpose * input.The 16-bit data read from this pin is returned by this API. MCBSP * pin to use in this read operation is identified by the second argument. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg inputSel * MCBSP pin to be used as general purpose input * * @ret Uint16 * data read from the pin(s) * * @eg * Uint16 inData, clkx_data, clkr_data; * CSL_Status status; * CSL_BitMask16 inMask; * CSL_McbspHandle hMcbsp; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init, Open, HwSetup successfully done in that order * ... * inMask = CSL_MCBSP_IO_CLKX \| CSL_MCBSP_IO_CLKR; * inData = CSL_mcbspIoRead(hMcbsp, inMask); * * if ((inData & CSL_MCBSP_IO_CLKX) != 0) * clkx_data = 1; * else * clkx_data = 0; * if ((inData & CSL_MCBSP_IO_CLKR) != 0) * clkr_data = 1; * else * clkr_data = 0; * ... * =========================================================================== / extern Uint16 CSL_mcbspIoRead ( CSL_McbspHandle hMcbsp, CSL_BitMask16 inputSel ); /* ============================================================================ * @func CSL_mcbspHwControl * * @desc * This function takes an input control command with an optional argument * and accordingly controls the operation/configuration of MCBSP. * * @arg hMcbsp * Handle to the Mcbsp instance * * @arg cmd * Operation to be performed on the mcbsp instance * * @arg cmdArg * Arguement specific to the command * * @ret CSL_Status * CSL_SOK - Command execution successful. * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVCMD - Invalid command * CSL_ESYS_INVPARAMS - The parameter is invalid * * @eg * CSL_Status status; * CSL_BitMask16 ctrlMask; * CSL_McbspHandle hMcbsp; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init successfully done * ... * // Open successfully done * ... * // HwSetup sucessfully done * ... * // MCBSP SRG and Frame sync taken out of reset * ... * * ctrlMask = CSL_MCBSP_CTRL_RX_ENABLE \| CSL_MCBSP_CTRL_TX_ENABLE; * status = CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, * &ctrlMask); * ... * =========================================================================== / extern CSL_Status CSL_mcbspHwControl ( CSL_McbspHandle hMcbsp, CSL_McbspControlCmd cmd, void arg ); /** ============================================================================ * @func CSL_mcbspGetHwStatus * * @desc * Gets the status of different operations or some setup-parameters of MCBSP. * The status is returned through the third parameter. * * @arg hMcbsp * Handle to the Mcbsp instance * * @arg myQuery * Query to be performed * * @arg response * Pointer to buffer to return the data requested by the query passed * * @ret CSL_Status * CSL_SOK - Query execution successful. * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVQUERY - Invalid Query * CSL_ESYS_INVPARAMS - The parameter is invalid * * @eg * CSL_Status status; * CSL_BitMask16 ctrlMask; * CSL_McbspHandle hMcbsp; * Uint16 response; * ... * status = CSL_mcbspGetHwStatus(hMcbsp,CSL_MCBSP_QUERY_DEV_STATUS, * &response); * * if (response & CSL_MCBSP_RRDY) { * // Receiver is ready to with new data * ... * } * ... * =========================================================================== / extern CSL_Status CSL_mcbspGetHwStatus ( CSL_McbspHandle hMcbsp, CSL_McbspHwStatusQuery myQuery, void response ); /* * ============================================================================ * @func CSL_mcbspGetHwSetup * * @desc * Gets the status of some or all of the setup-parameters of MCBSP. * To get the status of complete MCBSP h/w setup, all the sub-structure * pointers inside the main HwSetup structure, should be non-NULL. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg hwSetup * Pointer to hardware setup structure * * @ret CSL_Status * CSL_SOK - Hardware setup successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @eg * CSL_status status; * CSL_McbspGlobalSetup gblSetup; * CSL_McbspClkSetup clkSetup; * CSL_McbspEmu emuMode; * * CSL_McbspHwSetup readSetup = { &gblSetup, NULL, // RX Data-setup structure if not required NULL, // TX Data-setup structure if not required &clkSetup, NULL, // Multichannel-setup structure if not required emuMode }; * * status = CSL_mcbspGetHwSetup (hMcbs, &hwSetup); * * =========================================================================== / extern CSL_Status CSL_mcbspGetHwSetup ( CSL_McbspHandle hMcbsp, CSL_McbspHwSetup myHwSetup ); /** ============================================================================ * @n@b CSL_mcbspGetBaseAddress * * @b Description * @n Function to get the base address of the peripheral instance. * This function is used for getting the base address of the peripheral * instance. This function will be called inside the CSL_mcbspOpen() * function call. This function is open for re-implementing if the user * wants to modify the base address of the peripheral object to point to * a different location and there by allow CSL initiated write/reads into * peripheral. MMR's go to an alternate location. * * @b Arguments * @verbatim mcbspNum Specifies the instance of the MCBSP to be opened. pMcbspParam Module specific parameters. pBaseAddress Pointer to baseaddress structure. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_OK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Base Address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_McbspBaseAddress baseAddress; ... status = CSL_mcbspGetBaseAddress(CSL_MCBSP_PER_CNT, NULL, &baseAddress); @endverbatim * =========================================================================== / CSL_Status CSL_mcbspGetBaseAddress ( CSL_InstNum mcbspNum, CSL_McbspParam pMcbspParam, CSL_McbspBaseAddress *pBaseAddress ); #ifdef __cplusplus } #endif #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cHwSetupRaw.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_i2cHwSetupRaw.c * * @brief File for functional layer of CSL API @a CSL_i2cHwSetupRaw() * * @path $(CSLPATH)\i2c\src * * Description * - The @a CSL_i2cHwSetupRaw() function definition & it's associated * functions * * Modification 1 * - Modified on: 28/5/2004 * - Reason: created the sources * * @date 28th May, 2004 * @author <NAME>. / / ============================================================================= * Revision History * =============== * 01-Sep-2004 Hs File Created. * 11-oct-2004 Hs updated code according to code review comments. * ============================================================================= / #include <csl_i2c.h> /* ============================================================================ * @n@b CSL_i2cHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hI2c Handle to the I2C config Pointer to config structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not * properly initialized * * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cHwSetupRaw() can be called. * * <b> Post Condition </b> * @n The registers of the specified I2C instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified I2C instance. * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cConfig config = CSL_I2C_CONFIG_DEFAULTS; CSL_Status status; ... status = CSL_i2cHwSetupRaw(hI2c, &config); ... @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_i2cHwSetupRaw, ".text:csl_section:i2c"); CSL_Status CSL_i2cHwSetupRaw ( CSL_I2cHandle hI2c, CSL_I2cConfig config ) { CSL_Status status = CSL_SOK; if (hI2c == NULL) { status = CSL_ESYS_BADHANDLE; } else if (config == NULL ) { status = CSL_ESYS_INVPARAMS; } else { hI2c->regs->ICOAR = config->ICOAR; hI2c->regs->ICIMR = config->ICIMR; hI2c->regs->ICSTR = config->ICSTR; hI2c->regs->ICCLKL = config->ICCLKL; hI2c->regs->ICCLKH = config->ICCLKH; hI2c->regs->ICCNT = config->ICCNT; hI2c->regs->ICSAR = config->ICSAR; hI2c->regs->ICDXR = config->ICDXR; hI2c->regs->ICMDR = config->ICMDR; hI2c->regs->ICIVR = config->ICIVR; hI2c->regs->ICEMDR = config->ICEMDR; hI2c->regs->ICPSC = config->ICPSC; } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_types.h	<filename>DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_types.h<gh_stars>0 /****************************************************\ Copyright 2003, 2005 Texas Instruments Incorporated. * * All rights reserved. * * Restricted rights to use, duplicate or disclose * * this code are granted through contract. * * * * "@(#) PSP/CSL 3.0.0.0 (2003-09-30) * \****************************************************/ #ifndef _CSL_TYPES_H_ #define _CSL_TYPES_H_ #include <tistdtypes.h> #ifndef TRUE #define TRUE ((Bool) 1) #define FALSE ((Bool) 0) #endif typedef Int16 CSL_Uid; typedef Int16 CSL_ModuleId; typedef Uint32 CSL_Xio; typedef Uint8 CSL_BitMask8; typedef Uint16 CSL_BitMask16; typedef Uint32 CSL_BitMask32; typedef volatile Uint8 CSL_Reg8; typedef volatile Uint16 CSL_Reg16; typedef volatile Uint32 CSL_Reg32; typedef Int16 CSL_Status; typedef Int16 CSL_InstNum; typedef Int16 CSL_ChaNum; typedef unsigned long long int CSL_Uint64; typedef enum { CSL_EXCLUSIVE = 0, CSL_SHARED = 1 } CSL_OpenMode; typedef enum { CSL_FAIL = 0, CSL_PASS = 1 } CSL_Test; #ifndef NULL #define NULL ((void)0) #endif #endif /* _CSL_TYPES_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cOpen.c	<filename>DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cOpen.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_i2cOpen.c * * @brief File for functional layer of CSL API @a CSL_i2cOpen() * * @path $(CSLPATH)\i2c\src * * Description * - The @a CSL_i2cOpen() function definition & it's associated functions * Modification 1 * - Created on: 28/05/2004 * * @date 28th May, 2004 * @author <NAME>. / / ============================================================================= * Revision History * =============== * 31-aug-2004 Hs Updated function and documentation for CSL_i2cOpen. * - Removed the include file, csl_resource.h. * 11-oct-2004 Hs updated code according to code review comments. * 15-nov-2005 Hs Removed the assignment of pI2cParam and redundant pStatus check * * ============================================================================= / #include <csl_i2c.h> /* ============================================================================ * @n@b CSL_i2cOpen * * @b Description * @n This function populates the peripheral data object for the instance * and returns a handle to the instance. * The open call sets up the data structures for the particular instance * of I2C device. The device can be re-opened anytime after it has been * normally closed if so required. The handle returned by this call is * input as an essential argument for rest of the APIs described for * this module. * * @b Arguments * @verbatim pI2cObj Pointer to the I2C instance object i2cNum Instance of the I2C to be opened. pI2cParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * <b> Return Value </b> * CSL_I2cHandle * Valid I2C instance handle will be returned if status value is * equal to CSL_SOK. * * <b> Pre Condition </b> * @n @a CSL_i2cInit() must be called successfully. * * <b> Post Condition </b> * @n i2c instance will be opened * * @b Modifies * @n None * * @b Example: * @verbatim CSL_status status; CSL_I2cObj i2cObj; CSL_I2cHandle hI2c; ... hI2c = CSL_I2cOpen (&i2cObj, CSL_I2C, NULL, &status ); ... @endverbatim * * =========================================================================== / #pragma CODE_SECTION (CSL_i2cOpen, ".text:csl_section:i2c"); CSL_I2cHandle CSL_i2cOpen ( CSL_I2cObj pI2cObj, CSL_InstNum i2cNum, CSL_I2cParam pI2cParam, CSL_Status pStatus ) { CSL_I2cHandle hI2c = (CSL_I2cHandle)NULL; CSL_I2cBaseAddress baseAddress; /* Added according to review comment 1. / if (pStatus == NULL) { / do nothing : module handle is already initialized to NULL / } else if (pI2cObj == NULL) { pStatus = CSL_ESYS_INVPARAMS; } else { pStatus = CSL_i2cGetBaseAddress(i2cNum, pI2cParam, &baseAddress); if (pStatus == CSL_SOK) { pI2cObj->regs = baseAddress.regs; pI2cObj->perNum = (CSL_InstNum)i2cNum; hI2c = (CSL_I2cHandle)pI2cObj; } else { pI2cObj->regs = (CSL_I2cRegsOvly)NULL; pI2cObj->perNum = (CSL_InstNum)-1; } } return (hI2c); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2HwSetupRaw.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_ddr2HwSetupRaw.c * * @path: $(CSLPATH)\src\ddr2 * * @desc File for functional layer of CSL API @a CSL_ddr2HwSetupRaw() * - The @a CSL_ddr2HwSetupRaw() function definition & it's associated * functions * / / ============================================================================= * Revision History * =============== * 12-Apr-2005 RM File Created. * * 05-Oct-2005 NG Updation done according to new register layer * * 03-Feb-2006 ds Updated configuration of SDCFG register * ============================================================================= / #include <csl_ddr2.h> /* ============================================================================ * @n@b CSL_ddr2HwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the config data structure. * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 external memory interface instance config Pointer to the config structure containing the device register values @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration structure * pointer is not properly * initialized * * <b> Pre Condition </b> * @n @a CSL_ddr2Init() and @a CSL_ddr2Open () must be called successfully. * before calling this function. * * <b> Post Condition </b> * @n The registers of the specified DDR2 EMIF instance will be * setup according to the values passed through the config structure * * @b Modifies * @n Hardware registers of the DDR2 EMIF * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; CSL_Ddr2Config config = CSL_DDR2_CONFIG_DEFAULTS; CSL_Status status; ... status = CSL_ddr2HwSetupRaw (hDdr2, &config); .. @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_ddr2HwSetupRaw, ".text:csl_section:ddr2"); CSL_Status CSL_ddr2HwSetupRaw ( CSL_Ddr2Handle hDdr2, CSL_Ddr2Config config ) { CSL_Status status = CSL_SOK; Uint32 mask = 0; if(hDdr2 == NULL) { status = CSL_ESYS_BADHANDLE; } else if(config == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Disabling the Initialization sequence. / / setting the SDRAM Config Register / / The mask is used to leave the reserved fields at their default * values / mask = CSL_DDR2_SDCFG_BOOT_UNLOCK_MASK \| CSL_DDR2_SDCFG_DDR_DRIVE_MASK \| CSL_DDR2_SDCFG_TIMUNLOCK_MASK \| CSL_DDR2_SDCFG_NM_MASK \| CSL_DDR2_SDCFG_CL_MASK \| CSL_DDR2_SDCFG_IBANK_MASK \| CSL_DDR2_SDCFG_PAGESIZE_MASK; hDdr2->regs->SDCFG = (hDdr2->regs->SDCFG & ~mask) \| (config->SDCFG & mask); / setting SDRAM Timing1 Register / hDdr2->regs->SDTIM1 = config->SDTIM1; / setting the SDRAM Timing2 Register / hDdr2->regs->SDTIM2 = config->SDTIM2; / Clearing the timing unlock bit to prevent further changes/ CSL_FINS(hDdr2->regs->SDCFG,DDR2_SDCFG_TIMUNLOCK, CSL_DDR2_SDCFG_TIMUNLOCK_CLEAR ); / setting the SDRAM Refresh Control Register / / The mask is used to leave the reserved fields at their default * values / mask = CSL_DDR2_SDRFC_SR_MASK \| CSL_DDR2_SDRFC_REFRESH_RATE_MASK; hDdr2->regs->SDRFC = (hDdr2->regs->SDRFC & ~mask) \| (config->SDRFC & mask); / setting the VBUSM Burst Priority Register */ hDdr2->regs->BPRIO = config->BPRIO; } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_tmrAux.h	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ========================================================================= / /* =========================================================================== * @file csl_tmrAux.h * * @brief API Auxilary header file for TIMER CSL * * @Path $(CSLPATH)\inc * * @desc It gives the definitions of the status query & control functions. * ============================================================================ / / ============================================================================ * Revision History * =============== * 1-Sept-2004 HMM File Created. * 29-Jul-2005 PSK updted changes acooriding to revised timer spec. the number * convention TIM12, TIM34 are changed to TIMLO and TIMHI. * ============================================================================ / #ifndef _CSL_TMRAUX_H_ #define _CSL_TMRAUX_H_ #include <csl_tmr.h> #ifdef __cplusplus extern "C" { #endif / Status Query Functions of General purpose timer / /* ============================================================================ * @n@b CSL_tmrGetTimHiCount * * @b Description * @n This function gets the value of the TIMHI counter * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call countHi output parameter to get the TIMHI value @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n Timer should be set to GPTimer OR Unchained mode OR Chained mode * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; Unit32 countHi; ... CSL_tmrGetTimHiCount(hTmr, &countHi); ... @endverbatim ============================================================================ / static inline void CSL_tmrGetTimHiCount ( CSL_TmrHandle hTmr, Uint32 countHi ) { countHi = hTmr->regs->TIMHI; } /* =========================================================================== * @n@b CSL_tmrGetTimLoCount * * @b Description * @n This function gets the value of the TIMLO counter * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call countLo output parameter to get the TIMHI value @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n Timer should be set to GPTimer OR Unchained mode OR Chained mode * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; Unit32 countLo; ... CSL_tmrGetTimLoCount(hTmr, &countLo); ... @endverbatim ============================================================================ / static inline void CSL_tmrGetTimLoCount ( CSL_TmrHandle hTmr, Uint32 countLo ) { countLo = hTmr->regs->TIMLO; } /* =========================================================================== * @n@b CSL_tmrGetTstatLoStatus * * @b Description * @n This function gets the status of the TINTLO * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call @endverbatim * * <b> Return Value </b> CSL_TmrTstatLo - TINTLO status value * * @li CSL_TMR_TSTAT_LO_LOW - Data low * @li CSL_TMR_TSTAT_LO_HIGH - Data High * * <b> Pre Condition </b> * @n Timer should be set to GPTimer OR Unchained mode OR Chained mode * * <b> Post Condition </b> * @n TINTLO status value * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrTstatLo statusLo; ... statusLo = CSL_tmrGetTstatLoStatus(hTmr); ... @endverbatim * =========================================================================== / static inline CSL_TmrTstat CSL_tmrGetTstatLoStatus ( CSL_TmrHandle hTmr ) { return (CSL_TmrTstat)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_TSTAT_LO); } /* =========================================================================== * @n@b CSL_tmrGetTstatHiStatus * * @b Description * @n This function gets the status of the TINTHI * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call @endverbatim * * <b> Return Value </b> CSL_TmrTstatHi - TINTHI status value * * @li CSL_TMR_TSTATHI_LOW - Data low * @li CSL_TMR_TSTATHI_HIGH - Data High * * <b> Pre Condition </b> * @n Timer should be set to GPTimer OR Unchained mode OR Chained mode * * <b> Post Condition </b> * @n TINTHI status value * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrTstatHi statusHi; ... statusHi = CSL_tmrGetTstatHiStatus(hTmr); ... @endverbatim * ============================================================================ / static inline CSL_TmrTstat CSL_tmrGetTstatHiStatus ( CSL_TmrHandle hTmr ) { return (CSL_TmrTstat)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_TSTAT_HI); } /* =========================================================================== * @n@b CSL_tmrGetWdflagStatus * * @b Description * @n This function gets the status of the WDFLAG * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call @endverbatim * * <b> Return Value </b> CSL_TmrFlagBitStatus - WDFLAG status value * * @li CSL_TMR_WDFLAG_NOTIMEOUT - no watchdog timeout occured * @li CSL_TMR_WDFLAG_TIMEOUT - watchdog timeout occured * * <b> Pre Condition </b> * @n Timer should be set to WATCHDOG mode * * <b> Post Condition </b> * @n WDFLAG status value * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrWdflagBitStatus status; ... status = CSL_tmrGetWdflagStatus(hTmr); ... @endverbatim * =========================================================================== / static inline CSL_TmrWdflagBitStatus CSL_tmrGetWdflagStatus ( CSL_TmrHandle hTmr ) { return (CSL_TmrWdflagBitStatus)CSL_FEXT(hTmr->regs->WDTCR, TMR_WDTCR_WDFLAG); } /* ============================================================================ * @n@b CSL_TmrLoadPrdLo * * @b Description * Loads the General purpose timer period register Low * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance loadVal Value to be loaded to the Gptimer period register Low @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to timer mode * * <b> Post Condition </b> * @n Gptimer period register is loaded with the given value. * * * @b Modifies * @n Gptimer period register Low * * @b Example * @verbatim CSL_TmrHandle hTmr; Uint32 loadVal; ... CSL_TmrLoadPrdLo(hWdt, &loadVal); ... @endverbatim =========================================================================== / static inline void CSL_TmrLoadPrdLo ( CSL_TmrHandle hTmr, Uint32 loadVal ) { hTmr->regs->PRDLO = (loadVal); } /* ============================================================================ * @n@b CSL_TmrLoadPrdHi * * @b Description * Loads the General purpose timer period register High * * @b Arguments * @verbatim hTmr Handle to the GPtimer instance loadVal Value to be loaded to the Gptimer period register High @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to timer mode * * <b> Post Condition </b> * @n Gptimer period register is loaded with the given value. * * * @b Modifies * @n Gptimer period register High * * @b Example * @verbatim CSL_TmrHandle hTmr; Uint32 loadVal; ... CSL_TmrLoadPrdHi(hWdt, &loadVal); ... @endverbatim =========================================================================== / static inline void CSL_TmrLoadPrdHi ( CSL_TmrHandle hTmr, Uint32 loadVal ) { hTmr->regs->PRDHI = (loadVal); } /* ============================================================================ * @n@b CSL_TmrLoadPrescalarHi * * @b Description * Loads the General purpose timer prescalr register High * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance loadVal Value to be loaded to the Gptimer prescalar register High @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to unchained mode * * <b> Post Condition </b> * @n Gptimer prescalar register is loaded with the given value. * * * @b Modifies * @n Gptimer prescalar register High * * @b Example * @verbatim CSL_TmrHandle hTmr; Uint8 loadVal; ... CSL_TmrLoadPrescalarHi(hWdt, &loadVal); ... @endverbatim =========================================================================== / static inline void CSL_TmrLoadPrescalarHi ( CSL_TmrHandle hTmr, Uint8 loadVal ) { CSL_FINS(hTmr->regs->TGCR, TMR_TGCR_PSCHI, ((Uint8 )loadVal)); } /** ============================================================================ * @n@b CSL_TmrStartHi * * @b Description * sets the timer counting mode and timer reset * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance countMode specifies the timer counting mode @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any GPtimer mode * * <b> Post Condition </b> * @n Set the GP Timer counting mode and timer High reset. * * @b Modifies * @n Gptimer TCR and TGCR register of timer High * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrEnamode countMode; ... CSL_TmrStartHi(hWdt, countMode); ... @endverbatim * =========================================================================== / static inline void CSL_TmrStartHi ( CSL_TmrHandle hTmr, CSL_TmrEnamode countMode ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_OFF); CSL_FINS(hTmr->regs->TCR, TMR_TCR_ENAMODE_HI, countMode); } /* ============================================================================ * @n@b CSL_TmrStartLo * * @b Description * sets the timer counting mode and timer reset * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance countMode specifies the timer counting mode @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any GPtimer mode * * <b> Post Condition </b> * @n Set the GP Timer counting mode and timer Low reset. * * * @b Modifies * @n Gptimer TCR and TGCR register of timer Low * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrEnamode countMode; ... CSL_TmrStartLo(hWdt, countMode); ... @endverbatim * =========================================================================== / static inline void CSL_TmrStartLo ( CSL_TmrHandle hTmr, CSL_TmrEnamode countMode ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); CSL_FINS(hTmr->regs->TCR, TMR_TCR_ENAMODE_LO, countMode); } /* =========================================================================== * @n@b CSL_TmrStart64 * * @b Description * sets the timer counting mode and timer reset of GP OR chained timer * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance countMode specifies the timer counting mode @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any GPtimer mode * * <b> Post Condition </b> * @n Set the GP OR chained timer counting mode and timer Low and High reset register. * * * @b Modifies * @n Gptimer TCR and TGCR register of timer Low AND High * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrEnamode countMode; ... CSL_TmrStart64(hWdt, countMode); ... @endverbatim * =========================================================================== / static inline void CSL_TmrStart64 ( CSL_TmrHandle hTmr, CSL_TmrEnamode countMode ) { Uint32 temp; CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_OFF); / enable TIML0 and TIMHI simultaneously by making 32 bit write to TGCR / temp = CSL_FMK(TMR_TCR_ENAMODE_LO, countMode) \| CSL_FMK(TMR_TCR_ENAMODE_HI, countMode); / do read, modify write operation for mode bits for TIMLO, TIMHI / hTmr->regs->TCR = (hTmr->regs->TCR & ~temp) \| temp; } /* =========================================================================== * @n@b CSL_TmrStopLo * * @b Description * sets the timer counting mode to stop the timer. * The timer maintains the current value * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any GPtimer mode * * <b> Post Condition </b> * @n Set the GP Timer counting mode to stop the counting. * * * @b Modifies * @n Gptimer TCR of timer Low * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrStopLo(hWdt); ... @endverbatim * =========================================================================== / static inline void CSL_TmrStopLo ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TCR, TMR_TCR_ENAMODE_LO, DISABLE); } /* =========================================================================== * @n@b CSL_TmrStopHi * * @b Description * sets the timer counting mode to stop the timer. * The timer maintains the current value * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any GPtimer mode * * <b> Post Condition </b> * @n Set the GP Timer counting mode to stop the counting. * * * @b Modifies * @n Gptimer TCR of timer High * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrStopHi(hWdt); ... @endverbatim * =========================================================================== / static inline void CSL_TmrStopHi ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TCR, TMR_TCR_ENAMODE_HI, DISABLE); } /* =========================================================================== * @n@b CSL_TmrStop64 * * @b Description * sets the timer counting mode to stop the timer. * The timer maintains the current value * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to GPtimer or Chained mode * * <b> Post Condition </b> * @n Set the GP Timer counting mode to stop the counting. * * * @b Modifies * @n Gptimer TCR of timer Low and High * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrStop64(hWdt); ... @endverbatim * =========================================================================== / static inline void CSL_TmrStop64 ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TCR, TMR_TCR_ENAMODE_LO, DISABLE); CSL_FINST(hTmr->regs->TCR, TMR_TCR_ENAMODE_HI, DISABLE); } /* =========================================================================== * @n@b CSL_TmrResetHi * * @b Description * TSTAT_HI is set to reset state * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any unchained mode * * <b> Post Condition </b> * @n TTSTAT_HI is set to reset state * * * @b Modifies * @n Gptimer TCR of timer High * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrResetHi(hWdt); ... @endverbatim * =========================================================================== / static inline void CSL_TmrResetHi ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_ON); } /* =========================================================================== * @n@b CSL_TmrResetLo * * @b Description * TSTAT_LO is set to reset state * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any unchained mode * * <b> Post Condition </b> * @n TSTAT_LO is set to reset state * * * @b Modifies * @n Gptimer TCR of timer Low * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrResetLo(hWdt); ... @endverbatim * =========================================================================== / static inline void CSL_TmrResetLo ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_ON); } /* =========================================================================== * @n@b CSL_TmrReset64 * * @b Description * TSTAT_LO and TSTAT_HI is set to reset state. * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to GPtimer or chained mode * * <b> Post Condition </b> * @n TSTAT_LO and TSTAT_HI is set to reset state * * * @b Modifies * @n Gptimer TCR of timer Low and High * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrReset64(hWdt); ... @endverbatim * =========================================================================== / static inline void CSL_TmrReset64 ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_ON); CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_ON); } /* =========================================================================== * @n@b CSL_TmrStartWdt * * @b Description * sets the timer in watchdog mode and counting mode for it * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance countMode specifies the timer counting mode @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any GPtimer mode * * <b> Post Condition </b> * @n Set the watchdog timer counting mode and timer Low and High reset register and WDEN bit and WDKEY. * * * @b Modifies * @n Gptimer TCR and TGCR register of timer Low AND High and WDTCR rgister * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrEnamode countMode; ... CSL_TmrStartWdt(hWdt, countMode); ... @endverbatim * =========================================================================== / static inline void CSL_TmrStartWdt ( CSL_TmrHandle hTmr, CSL_TmrEnamode countMode ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_OFF); CSL_FINST(hTmr->regs->WDTCR, TMR_WDTCR_WDEN, ENABLE); CSL_FINS(hTmr->regs->TCR, TMR_TCR_ENAMODE_LO, countMode); CSL_FINS(hTmr->regs->TCR, TMR_TCR_ENAMODE_HI, countMode); } /* =========================================================================== * @n@b CSL_TmrLoadtWdkey * * @b Description * sets the watchdog key * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance cmd specifies the key @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any GPtimer mode * * <b> Post Condition </b> * @n Loads the WDKEY in WDTCR register. * * * @b Modifies * @n WDTCR rgister * * @b Example * @verbatim CSL_TmrHandle hTmr; Uint16 cmd; ... CSL_TmrStartWdt(hTmr, cmd); ... @endverbatim * =========================================================================== / static inline void CSL_TmrLoadWdkey ( CSL_TmrHandle hTmr, Uint16 cmd ) { CSL_FINS(hTmr->regs->WDTCR, TMR_WDTCR_WDKEY, cmd); } /* =========================================================================== * @n@b CSL_TmrDisableWdt * * @b Description * disables the timer in watchdog mode and counting mode for it * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n Timer should be set it to any GPtimer mode * * <b> Post Condition </b> * @n Set the watchdog timer counting mode and timer Low and High reset register and WDEN bit and WDKEY. * * * @b Modifies * @n Gptimer TCR and TGCR register of timer Low AND High and WDTCR rgister * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrStartWdt(hTmr); ... @endverbatim * =========================================================================== / static inline void CSL_TmrDisableWdt ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->WDTCR, TMR_WDTCR_WDEN, DISABLE); } #ifdef __cplusplus extern "C" { #endif #endif / CSL_TMRAUX_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cInit.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_i2cInit.c * * @brief File for functional layer of CSL API @a CSL_i2cInit() * * @path $(CSLPATH)\i2c\src * * Description * - The @a CSL_i2cInit() function definition & it's associated functions * * Modification 1 * - Modified on: 28/5/2004 * - Reason: created the sources * * @date 28th May, 2004 * @author <NAME>. / / ============================================================================= * Revision History * =============== * 31-aug-2004 Hs Updated the function and documentation for CSL_i2cInit. * 11-oct-2004 Hs updated code according to code review comments. * ============================================================================= / #include <csl_i2c.h> /* ============================================================================ * @n@b CSL_i2cInit * * @b Description * @n This is the initialization function for the I2C. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. * * @b Arguments @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Status status; ... status = CSL_i2cInit(); ... @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_i2cInit, ".text:csl_section:i2c"); CSL_Status CSL_i2cInit ( CSL_I2cContext pContext ) { /* Added according to review comment 1. / pContext = pContext; / To remove compiler warning/remarks */ return CSL_SOK; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/tcp2/tcp2_standalone_mode/src/Tcp2_standalone_mode_example.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file Tcp2_standalone_mode_example.c * * @path $(CSLPATH)\example\tcp2\tcp2_standalone_mode\src * * @desc Example file for the TCP2 CSL * ============================================================================ * @n Target Platform: EVM * ============================================================================ * The example demonstrates the usage of the TCP2 CSL API for decoding the * input data in stand alone mode. * * ============================================================================ * @n <b> Description </b> * This is an example for the usage of the TCP2 CSL API in the standalone * mode. * * @b Procedure * 1 - Sets up the TCP2 input configuration parameters * 2 - Configures the EDMA to transfer the input paramters, * systematics and parity data, interleaver data on successful TCPXEVT * 3 - Configures the EDMA for the hard decisions transfer on TCPREVT. * 4 - Starts the turbo coprocessor and waits for the completion of the * processing * 5 - After the state indicates the hard decisions are read, they are * displayed. ============================================================================= * The steps to run this example are as follows: * 1 - Open the Tcp2_standalone_mode_example.pjt in the CCS studio * 2 - Build the example * 3 - Execute the .out file * / / ============================================================================= * Revision History * =============== * 23-May-2005 sd File Created. * 05-Aug-2005 sd Changes for EDMA CSL * 17-Dec-2005 sd Adding EDMA error registers clearing before enabling * the channel * 05-Feb-2006 sd Changes according to the spec changes * 21-Feb-2006 ds Added clearing the EDMA error registers at end of the * example * 22-Mar-2006 ds Removed "mode" bit from TCP2_BaseParams structure * ============================================================================= / #include <csl_tcp2.h> #include <csl_tcp2Aux.h> #include <csl_edma3.h> #include <stdio.h> #include <cslr_dev.h> / defines / / To load the interleaver RAM/ #define INTERLEAVER_LOAD_FLAG TRUE / Maximum iterations of the TCP / #define MAX_TCP_ITERATIONS 8 / Maximum iterations of the TCP / #define MIN_TCP_ITERATIONS 1 / Output paramters read flag / #define OUT_PARAM_READ_FLAG TRUE / prolog size / #define PROLOG_SIZE 24 / externs / / systematic and parity data to be input to TCP / extern Uint32 sysParData []; / Interleaver table to be input to TCP / extern Uint32 interleaverTbl []; / tail data for TCP configuration / extern Int8 tailData []; / Hard decisions expected / extern Uint32 hdRefBuff []; / Frame length of the TCP input data / extern Uint32 frameLength; / globals / / TCP input configuration structure / TCP2_ConfigIc configIc; / EDMA CSL configuration structures / CSL_Edma3Context context; CSL_Edma3ChannelObj ChObj, ChObj1; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelHandle hChannel, hChannel1; CSL_Edma3ParamHandle hParam[4]; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3ChannelAttr chParam, chParam1; CSL_Edma3ChannelErr chErrClear; / forward declarations / Uint16 tcp2_configEdma ( Uint32 hdDecisionBuffer ); /* * ============================================================================ * @func main () * * @desc * Example to show the usage of the TCP2 CSL API for standalone mode * processing * * @b Arguments * @verbatim None @endverbatim * * <b> Return Value </b> None * * @b Procedure * 1 - Sets up the TCP2 input configuration parameters * 2 - Configures the EDMA to transfer the input paramters, * systematics and parity data, interleaver data on successful TCPXEVT * 3 - Configures the EDMA for the hard decision transfer on TCPREVT. * 4 - Starts the turbo coprocessor and waits for the completion of the * processing * 5 - After the state indicates the hard decisions are read, they are * displayed. * * * ============================================================================ / void main ( void ) { TCP2_BaseParams configBase; / base params to configure TCP2 / TCP2_Params configParams; / holds all the input configuration parameters for TCP/ Uint32 frameLen = frameLength; Uint32 cnt; Uint32 numHd; / number of hard decisions / Uint32 hdDecisionBuffer; /* to hold the hard decisions / / Enable the TCP2 in power saver / CSL_FINST (((CSL_DevRegs)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); CSL_FINST (((CSL_DevRegs)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TCPCTL, ENABLE); while (CSL_DEV_PERSTAT0_TCPSTAT_ENABLE != CSL_FEXT (((CSL_DevRegs)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TCPSTAT)); /* calculate the number of hard decision 32 bit words expected / numHd = frameLen / 32; / for 32 bits / /* account for the hard decision data if the frame len is not * 32 bit aligned / if (0 != (frameLen % 32)) numHd++; / Allocate memory for the hard decisions / hdDecisionBuffer = (Uint32) malloc ( sizeof (Uint32) * numHd); /* setup the base params / configBase.frameLen = frameLen; configBase.inputSign = TCP2_INPUT_SIGN_POSITIVE; configBase.intFlag = INTERLEAVER_LOAD_FLAG; configBase.maxIter = MAX_TCP_ITERATIONS; configBase.maxStarEn = TRUE; configBase.standard = TCP2_STANDARD_3GPP; configBase.crcLen = 0; / Disable CRC / configBase.crcPoly = 0; / not used / configBase.minIter = MIN_TCP_ITERATIONS; configBase.numCrcPass = 0; / default value / configBase.outParmFlag = OUT_PARAM_READ_FLAG; configBase.outputOrder = TCP2_OUT_ORDER_0_31; configBase.prologRedEn = FALSE; configBase.prologSize = PROLOG_SIZE; configBase.rate = TCP2_RATE_1_3; configBase.snr = 0; / disable SNR threshold checking / / assign the extrinsic scaling factors / for (cnt = 0; cnt < 16; cnt++) configBase.extrScaling [cnt] = 32; / setup the TCP configuration registers parmeters / TCP2_genParams (&configBase, &configParams); / generate the configuration register values / TCP2_genIc (&configParams, tailData, &configIc); / configure the Endian register / TCP2_setInterEndian (CSL_TCP2_TCPEND_ENDIAN_INTR_32BITS); TCP2_setExtEndian (CSL_TCP2_TCPEND_ENDIAN_EXTR_32BITS); / configure the sleep modes / TCP2_setSlpzvdd (CSL_TCP2_TCPEND_SLPZVDD_EN_ENABLE); TCP2_setSlpzvss (CSL_TCP2_TCPEND_SLPZVSS_EN_ENABLE); / Configure EDMA to write/read TCP data on app. events / tcp2_configEdma (hdDecisionBuffer); / Disable cahnnels and clear the EDMA event registers / CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); / Enable Channel / CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL); / reset and start the TCP / TCP2_reset (); TCP2_start (); / wait for the status to indicate hard decisions are read / while (0xA != TCP2_statTcpState ()); / compare the hard decisions and check if they are as expected / for (cnt = 0; cnt < numHd; cnt++) { printf ("Hard decisions : 0x%x \n", hdDecisionBuffer [cnt]); } / end of for / / free the allocated memory / free (hdDecisionBuffer); / Disable cahnnels and clear the EDMA event registers / CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); / clear the EDMA error registers / chErrClear.missed = TRUE; chErrClear.secEvt = TRUE; CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear); printf ("Example complete \n"); } / * ============================================================================= * @func tcp2_configEdma * @desc * Configures EDMA channels 30 and 31. * For channel 31 there are 3 param entries(0, 1 and 2) which are linked. * Link 0 transfers the TCP2 input configuration register values. * Link 1 transfer the systematics and parity data. * Link 2 transfers the interleaver data * For channel 30 there is 1 param entry (3). * Link 3 transfers the Hard decisions. * * * @eg * tcp2_configEdma(); * ============================================================================= / Uint16 tcp2_configEdma ( Uint32 hdDecisionBuffer ) { volatile Uint16 count; CSL_Status chStatus, chStatus1; CSL_edma3Init(&context); CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&chStatus); /* Channel Configuration for TCPXEVT event / / Channel Open / chParam.regionNum = CSL_EDMA3_REGION_GLOBAL; chParam.chaNum = CSL_EDMA3_CHA_TCP2XEVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chParam, &chStatus); if ((chStatus != CSL_SOK) \|\| (hChannel == NULL)) { printf("Error in EDMA channel open function\n"); return 0; } / Channel Setup for PARAM entry 0 / if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel, 0 )){ printf("Error is EDMA channel setup for channel #31\n"); return 0; } if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel, CSL_EDMA3_QUE_0)) { printf("Error is EDMA channel setup for channel #31\n"); return 0; } / Setup EDMA to transmit the input configuration parameters / hParam[0] = CSL_edma3GetParamHandle (hChannel, 0, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)&configIc; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1, 1); myParamSetup.dstAddr = (Uint32)CSL_TCP2_CFG_REGS; myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(0x20, 0); / offset to the next PARAM entry / myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(sizeof (configIc), 1); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[0], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #0\n"); return 0; } / Setup link to transmit systematics and parity data using param 1/ hParam[1] = CSL_edma3GetParamHandle (hChannel, 1, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)sysParData; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1, 1); myParamSetup.dstAddr = (Uint32)CSL_TCP2_X0_MEM; / linking to the offset to the next PARAM entry / myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(0x40, 0); / length of the systematic and parity data to be transferred / myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(frameLength 4, 1); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[1], &myParamSetup)) { printf("Error in EDMA paRam setup for entry #1\n"); return 0; } /* Setup link to transmit interleaver data / hParam[2] = CSL_edma3GetParamHandle (hChannel, 2, &chStatus); / param entry 2 / myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)interleaverTbl; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1, 1); myParamSetup.dstAddr = (Uint32)CSL_TCP2_I0_MEM; myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( CSL_EDMA3_LINK_NULL, 0); myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(88, 1); / number of bytes of interleaver data / myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[2], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #2\n"); return 0; } / Receive Channel Open / chParam1.regionNum = CSL_EDMA3_REGION_GLOBAL; chParam1.chaNum = CSL_EDMA3_CHA_TCP2REVT; hChannel1 = CSL_edma3ChannelOpen (&ChObj1, CSL_EDMA3, &chParam1, &chStatus1); if ((chStatus1 != CSL_SOK) \| (hChannel1 == NULL)) { printf("Error in EDMA channel open function\n"); return 0; } / Channel Setup / if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel1, 3 / PaRAM entry 3/)) { printf("Error is EDMA channel setup for channel #30\n"); return 0; } if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel1, CSL_EDMA3_QUE_0)) { printf("Error is EDMA channel setup for channel #30\n"); return 0; } / Channel Setup / / configure param entry 3 to read the hard decisions / hParam[3] = CSL_edma3GetParamHandle (hChannel1, 3, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)CSL_TCP2_O0_MEM; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (8, 1); / number of bytes of hard decision data to be read */ myParamSetup.dstAddr = (Uint32)hdDecisionBuffer; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE (1, 1); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( CSL_EDMA3_LINK_NULL, 0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE (1, 1); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[3], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #3\n"); return 0; } return 1; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example4/src/Intc_example4.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ========================================================================== / /* =========================================================================== * @file Intc_example4.c * * @path $(CSLPATH)\example\c64xplus\intc\intc_example4\src * * @desc Example of INTC * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @n Demonstraing the usage and occurence of the dropped event. * 1. Initalizes the intc CSL required with proper ISR * 2. Opens the INTERR/DROP and timer events * 3. Enables the timer event drop * 4. Intializes and setup timer module * 5. Poll for the event to be set * 6. Closes the Intc module * * ============================================================================= * * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Intc_example4.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================ * Revision History * =============== * 29-Jun-2004 <NAME> File Created. * * 04-Aug-2005 ds Changed to support timer CSL * 11-Nov-2005 ds Changed to add powersaver for timer * 16-Dec-2005 ds Updated documentation * ============================================================================ / #include <stdio.h> #include <csl_intc.h> #include <csl_intcAux.h> #include <csl_tmr.h> #include <cslr_dev.h> / Intc variables declarations / CSL_IntcEventHandlerRecord EventHandler[30]; CSL_IntcGlobalEnableState state; CSL_IntcEventHandlerRecord EventRecord; CSL_IntcEventHandlerRecord Record[2]; / Suficient Entries / CSL_IntcDropStatus drop; CSL_IntcContext context; CSL_IntcHandle hIntcTimer; CSL_IntcHandle hDrop; / Function forwards / interrupt void eventTimerHandler(); void eventDropHandler(void handle); void intc_example (void); /* Global variables declarations / volatile Uint32 intrCnt = 0; volatile Uint32 passed = 0; volatile Uint32 intrDrop = 0; / ============================================================================ * * @func main * * @desc * This is the main routine,which invokes the example * ============================================================================ / void main(void) { Bool timer0En; printf ("Running Interrupt Example\n"); / Unlock the control register / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the Powersaver clock for TIMER 0 / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER0CTL, ENABLE); do { timer0En = (Bool) CSL_FEXT(((CSL_DevRegs)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TIMER0STAT); } while (timer0En != TRUE); printf("Powersaver clock for TIMER 0 is enabled\n"); intc_example (); return; } / * ============================================================================= * @func intc_example * * @arg None * * @desc * This is the usage and occurence of the dropped event. * It implements following steps * 1. Initalizes the intc CSL required with proper ISR * 2. Opens the INTERR/DROP and timer events * 3. Enables the timer event drop * 4. Intializes and setup timer module * 5. Poll for the event to be set * 6. Closes the Intc module * * @return * None * * @eg * intc_example (); * ============================================================================= / void intc_example (void) { CSL_IntcObj intcTimerObj; CSL_IntcObj intcDropObj; CSL_IntcParam vectId; volatile Uint32 dropStat; volatile Uint32 timerStat; CSL_TmrHandle hTmr; CSL_TmrObj TmrObj; CSL_Status status; CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS; CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_CONT; Uint32 LoadValue = 100; printf ("Demonstraing the usage and occurence of the dropped event\n"); / Initialize Intc / context.numEvtEntries = 2; context.eventhandlerRecord = Record; CSL_intcInit(&context); / Enable NMIs / CSL_intcGlobalNmiEnable(); / Enable Global Interrupts / CSL_intcGlobalEnable(&state); / Open the INTERR/DROP EVENT Object / vectId = CSL_INTC_VECTID_4; hDrop = CSL_intcOpen (&intcDropObj, CSL_INTC_EVENTID_INTERR, &vectId , NULL); EventRecord.handler = &eventDropHandler; EventRecord.arg = hDrop; CSL_intcPlugEventHandler(hDrop,&EventRecord); CSL_intcQueryDropStatus(&drop); / Opening a handle for the Timer 0 Event onto CPU vector 13 / vectId = CSL_INTC_VECTID_13; hIntcTimer = CSL_intcOpen (&intcTimerObj, CSL_INTC_EVENTID_TINTLO0, &vectId, NULL); / Enabling timer event / CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDROPENABLE,NULL); CSL_intcHwControl(hDrop,CSL_INTC_CMD_EVTENABLE,NULL); / Initialize timer CSL module / CSL_tmrInit(NULL); hTmr = CSL_tmrOpen(&TmrObj, CSL_TMR_0, NULL, &status); CSL_tmrHwSetup(hTmr, &hwSetup); / Stop the Timer / status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL); / set the timer mode to unchained dual mode / hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED; CSL_tmrHwSetup(hTmr, &hwSetup); / Load the period register / CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void )&LoadValue); /* Start the timer with one shot/ CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, (void )&TimeCountMode); /* Poll mode, query for the event to be set / do { CSL_intcGetHwStatus(hIntcTimer,CSL_INTC_QUERY_PENDSTATUS, \ (void)&timerStat); if (timerStat) intrCnt++; if (intrDrop) break; } while (1); printf ("Example Passed for usage and occurence of the dropped event\n"); } /* * ============================================================================= * @func eventDropHandler * * @desc * This is the interrupt event drop handler * * @arg handle * Pointer to timer handle * * * @eg * eventDropHandler (); * ============================================================================= / void eventDropHandler(void handle) { intrDrop++; CSL_intcQueryDropStatus(&drop); /* Want only one drop */ CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDROPDISABLE,NULL); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cGetHwSetup.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_i2cGetHwSetup.c * * @brief File for functional layer of CSL API CSL_i2cGetHwSetup() * * @path $(CSLPATH)\i2c\src * * Description * - The CSL_i2cGetHwSetup() function definition & it's associated * functions * * Modification 1 * - Modified on: 28/5/2004 * - Reason: created the sources * * @date 28th May, 2004 * @author <NAME>. / #include <csl_i2c.h> /* ============================================================================ * @n@b CSL_i2cGetHwSetup * * @b Description * @n This function gets the current setup of the I2C. The status is * returned through @a CSL_I2cHwSetup. The obtaining of status * is the reverse operation of @a CSL_i2cHwSetup() function. * * @b Arguments * @verbatim hI2c Handle to the I2C hwSetup Pointer to the hardware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Retrieving the hardware setup * parameters is successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cGetHwSetup() can be called. * * <b> Post Condition </b> * @n The hardware setup structure is populated with the hardware setup * parameters * * @b Modifies * @n hwSetup variable * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cHwSetup hwSetup; ... status = CSL_i2cGetHwSetup(hI2c, &hwSetup); ... @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_i2cGetHwSetup, ".text:csl_section:i2c") CSL_Status CSL_i2cGetHwSetup ( CSL_I2cHandle hI2c, CSL_I2cHwSetup setup ) { CSL_Status status = CSL_SOK; CSL_I2cClkSetup clkSetup; if (hI2c == NULL) { status = CSL_ESYS_BADHANDLE; } else if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else { setup->mode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_MST); setup->dir = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_TRX); setup->addrMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_XA); setup->ownaddr = CSL_FEXT(hI2c->regs->ICOAR, I2C_ICOAR_OADDR); setup->sttbyteen = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_STB); setup->ackMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_NACKMOD); setup ->runMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_FREE); setup ->repeatMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_RM); setup->loopBackMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_DLB); setup->freeDataFormat = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_FDF); setup->resetMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_IRS); setup->bcm = CSL_FEXT(hI2c->regs->ICEMDR, I2C_ICEMDR_BCM); setup->inten = hI2c->regs->ICIMR ; clkSetup.prescalar = CSL_FEXT(hI2c->regs->ICPSC, I2C_ICPSC_IPSC); clkSetup.clklowdiv = CSL_FEXT(hI2c->regs->ICCLKL, I2C_ICCLKL_ICCL); clkSetup.clkhighdiv= CSL_FEXT(hI2c->regs->ICCLKH, I2C_ICCLKH_ICCH); setup->clksetup->prescalar = clkSetup.prescalar; setup->clksetup->clklowdiv = clkSetup.clklowdiv; setup->clksetup->clkhighdiv = clkSetup.clkhighdiv; } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_cfg.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_cfg.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for CFG / #ifndef _CSLR_CFG_H_ #define _CSLR_CFG_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint32 MPFAR; volatile Uint32 MPFSR; volatile Uint32 MPFCR; } CSL_CfgRegs; /***********************************************************************\ Overlay structure typedef definition \*************************************************************************/ typedef volatile CSL_CfgRegs CSL_CfgRegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / MPFAR / #define CSL_CFG_MPFAR_ADDR_MASK (0xFFFFFFFFu) #define CSL_CFG_MPFAR_ADDR_SHIFT (0x00000000u) #define CSL_CFG_MPFAR_ADDR_RESETVAL (0x00000000u) #define CSL_CFG_MPFAR_RESETVAL (0x00000000u) / MPFSR / #define CSL_CFG_MPFSR_FID_MASK (0x0000FE00u) #define CSL_CFG_MPFSR_FID_SHIFT (0x00000009u) #define CSL_CFG_MPFSR_FID_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_LOCAL_MASK (0x00000100u) #define CSL_CFG_MPFSR_LOCAL_SHIFT (0x00000008u) #define CSL_CFG_MPFSR_LOCAL_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_SR_MASK (0x00000020u) #define CSL_CFG_MPFSR_SR_SHIFT (0x00000005u) #define CSL_CFG_MPFSR_SR_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_SW_MASK (0x00000010u) #define CSL_CFG_MPFSR_SW_SHIFT (0x00000004u) #define CSL_CFG_MPFSR_SW_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_SX_MASK (0x00000008u) #define CSL_CFG_MPFSR_SX_SHIFT (0x00000003u) #define CSL_CFG_MPFSR_SX_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_UR_MASK (0x00000004u) #define CSL_CFG_MPFSR_UR_SHIFT (0x00000002u) #define CSL_CFG_MPFSR_UR_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_UW_MASK (0x00000002u) #define CSL_CFG_MPFSR_UW_SHIFT (0x00000001u) #define CSL_CFG_MPFSR_UW_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_UX_MASK (0x00000001u) #define CSL_CFG_MPFSR_UX_SHIFT (0x00000000u) #define CSL_CFG_MPFSR_UX_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_RESETVAL (0x00000000u) / MPFCR / #define CSL_CFG_MPFCR_MPFCLR_MASK (0x00000001u) #define CSL_CFG_MPFCR_MPFCLR_SHIFT (0x00000000u) #define CSL_CFG_MPFCR_MPFCLR_RESETVAL (0x00000000u) /----MPFCLR Tokens----*/ #define CSL_CFG_MPFCR_MPFCLR_CLEAR (0x00000001u) #define CSL_CFG_MPFCR_RESETVAL (0x00000000u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3Close.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_edma3Close.c * * @path $(CSLPATH)\src\edma * * @desc EDMA3 CSL Implementation on DSP side * / / ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= / #include <csl_edma3.h> /* ============================================================================ * @n@b CSL_edma3Close.c * * @b Description * @n This is a module level close require to invalidate the module handle. * The module handle must not be used after this API call. * * @b Arguments * @verbatim hEdma Handle to the Edma Instance @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Edma is closed successfully. * * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * * <b> Pre Condition </b> * @n Functions CSL_edma3Init() and CSL_edma3Open() have to be called in that * order successfully before calling this function. * * <b> Post Condition </b> * @n The edma CSL APIs can not be called until the edma CSL is reopened * again using CSL_edma3Open() * * @b Modifies * @n CSL_edma3Obj structure values * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule, &hwSetup); // Open Channels, setup transfers etc // Close Module CSL_edma3Close(hModule); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3Close, ".text:csl_section:edma3"); CSL_Status CSL_edma3Close ( CSL_Edma3Handle hEdma ) { CSL_Status status = CSL_SOK; if (hEdma != NULL) { hEdma->regs = (CSL_Edma3ccRegsOvly) NULL; hEdma->instNum = (CSL_InstNum)-1; } else { status = CSL_ESYS_BADHANDLE; } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_mcbsp.h	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/inc/cslr_mcbsp.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_mcbsp.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for MCBSP * / #ifndef _CSLR_MCBSP_H_ #define _CSLR_MCBSP_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint32 DRR; volatile Uint32 DXR; volatile Uint32 SPCR; volatile Uint32 RCR; volatile Uint32 XCR; volatile Uint32 SRGR; volatile Uint32 MCR; volatile Uint32 RCERE0; volatile Uint32 XCERE0; volatile Uint32 PCR; volatile Uint32 RCERE1; volatile Uint32 XCERE1; volatile Uint32 RCERE2; volatile Uint32 XCERE2; volatile Uint32 RCERE3; volatile Uint32 XCERE3; } CSL_McbspRegs; /***********************************************************************\ Overlay structure typedef definition \*************************************************************************/ typedef volatile CSL_McbspRegs CSL_McbspRegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / DRR / #define CSL_MCBSP_DRR_DRR_MASK (0xFFFFFFFFu) #define CSL_MCBSP_DRR_DRR_SHIFT (0x00000000u) #define CSL_MCBSP_DRR_DRR_RESETVAL (0x00000000u) #define CSL_MCBSP_DRR_RESETVAL (0x00000000u) / DXR / #define CSL_MCBSP_DXR_DXR_MASK (0xFFFFFFFFu) #define CSL_MCBSP_DXR_DXR_SHIFT (0x00000000u) #define CSL_MCBSP_DXR_DXR_RESETVAL (0x00000000u) #define CSL_MCBSP_DXR_RESETVAL (0x00000000u) / SPCR / #define CSL_MCBSP_SPCR_FREE_MASK (0x02000000u) #define CSL_MCBSP_SPCR_FREE_SHIFT (0x00000019u) #define CSL_MCBSP_SPCR_FREE_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_SOFT_MASK (0x01000000u) #define CSL_MCBSP_SPCR_SOFT_SHIFT (0x00000018u) #define CSL_MCBSP_SPCR_SOFT_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_FRST_MASK (0x00800000u) #define CSL_MCBSP_SPCR_FRST_SHIFT (0x00000017u) #define CSL_MCBSP_SPCR_FRST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_GRST_MASK (0x00400000u) #define CSL_MCBSP_SPCR_GRST_SHIFT (0x00000016u) #define CSL_MCBSP_SPCR_GRST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_XINTM_MASK (0x00300000u) #define CSL_MCBSP_SPCR_XINTM_SHIFT (0x00000014u) #define CSL_MCBSP_SPCR_XINTM_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_XSYNCERR_MASK (0x00080000u) #define CSL_MCBSP_SPCR_XSYNCERR_SHIFT (0x00000013u) #define CSL_MCBSP_SPCR_XSYNCERR_RESETVAL (0x00000000u) /----XSYNCERR Tokens----/ #define CSL_MCBSP_SPCR_XSYNCERR_CLEAR (0x00000000u) #define CSL_MCBSP_SPCR_XEMPTY_MASK (0x00040000u) #define CSL_MCBSP_SPCR_XEMPTY_SHIFT (0x00000012u) #define CSL_MCBSP_SPCR_XEMPTY_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_XRDY_MASK (0x00020000u) #define CSL_MCBSP_SPCR_XRDY_SHIFT (0x00000011u) #define CSL_MCBSP_SPCR_XRDY_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_XRST_MASK (0x00010000u) #define CSL_MCBSP_SPCR_XRST_SHIFT (0x00000010u) #define CSL_MCBSP_SPCR_XRST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_DLB_MASK (0x00008000u) #define CSL_MCBSP_SPCR_DLB_SHIFT (0x0000000Fu) #define CSL_MCBSP_SPCR_DLB_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RJUST_MASK (0x00006000u) #define CSL_MCBSP_SPCR_RJUST_SHIFT (0x0000000Du) #define CSL_MCBSP_SPCR_RJUST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_CLKSTP_MASK (0x00001800u) #define CSL_MCBSP_SPCR_CLKSTP_SHIFT (0x0000000Bu) #define CSL_MCBSP_SPCR_CLKSTP_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_DXENA_MASK (0x00000080u) #define CSL_MCBSP_SPCR_DXENA_SHIFT (0x00000007u) #define CSL_MCBSP_SPCR_DXENA_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RINTM_MASK (0x00000030u) #define CSL_MCBSP_SPCR_RINTM_SHIFT (0x00000004u) #define CSL_MCBSP_SPCR_RINTM_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RSYNCERR_MASK (0x00000008u) #define CSL_MCBSP_SPCR_RSYNCERR_SHIFT (0x00000003u) #define CSL_MCBSP_SPCR_RSYNCERR_RESETVAL (0x00000000u) /----RSYNCERR Tokens----/ #define CSL_MCBSP_SPCR_RSYNCERR_CLEAR (0x00000000u) #define CSL_MCBSP_SPCR_RFULL_MASK (0x00000004u) #define CSL_MCBSP_SPCR_RFULL_SHIFT (0x00000002u) #define CSL_MCBSP_SPCR_RFULL_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RRDY_MASK (0x00000002u) #define CSL_MCBSP_SPCR_RRDY_SHIFT (0x00000001u) #define CSL_MCBSP_SPCR_RRDY_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RRST_MASK (0x00000001u) #define CSL_MCBSP_SPCR_RRST_SHIFT (0x00000000u) #define CSL_MCBSP_SPCR_RRST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RESETVAL (0x00000000u) / RCR / #define CSL_MCBSP_RCR_RPHASE_MASK (0x80000000u) #define CSL_MCBSP_RCR_RPHASE_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCR_RPHASE_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RFRLEN2_MASK (0x7F000000u) #define CSL_MCBSP_RCR_RFRLEN2_SHIFT (0x00000018u) #define CSL_MCBSP_RCR_RFRLEN2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RWDLEN2_MASK (0x00E00000u) #define CSL_MCBSP_RCR_RWDLEN2_SHIFT (0x00000015u) #define CSL_MCBSP_RCR_RWDLEN2_RESETVAL (0x00000000u) /----RWDLEN2 Tokens----/ #define CSL_MCBSP_RCR_RWDLEN2_8BITS (0x00000000u) #define CSL_MCBSP_RCR_RWDLEN2_12BITS (0x00000001u) #define CSL_MCBSP_RCR_RWDLEN2_16BITS (0x00000002u) #define CSL_MCBSP_RCR_RWDLEN2_20BITS (0x00000003u) #define CSL_MCBSP_RCR_RWDLEN2_24BITS (0x00000004u) #define CSL_MCBSP_RCR_RWDLEN2_32BITS (0x00000005u) #define CSL_MCBSP_RCR_RCOMPAND_MASK (0x00180000u) #define CSL_MCBSP_RCR_RCOMPAND_SHIFT (0x00000013u) #define CSL_MCBSP_RCR_RCOMPAND_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RFIG_MASK (0x00040000u) #define CSL_MCBSP_RCR_RFIG_SHIFT (0x00000012u) #define CSL_MCBSP_RCR_RFIG_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RDATDLY_MASK (0x00030000u) #define CSL_MCBSP_RCR_RDATDLY_SHIFT (0x00000010u) #define CSL_MCBSP_RCR_RDATDLY_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RFRLEN1_MASK (0x00007F00u) #define CSL_MCBSP_RCR_RFRLEN1_SHIFT (0x00000008u) #define CSL_MCBSP_RCR_RFRLEN1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RWDLEN1_MASK (0x000000E0u) #define CSL_MCBSP_RCR_RWDLEN1_SHIFT (0x00000005u) #define CSL_MCBSP_RCR_RWDLEN1_RESETVAL (0x00000000u) /----RWDLEN1 Tokens----/ #define CSL_MCBSP_RCR_RWDLEN1_8BITS (0x00000000u) #define CSL_MCBSP_RCR_RWDLEN1_12BITS (0x00000001u) #define CSL_MCBSP_RCR_RWDLEN1_16BITS (0x00000002u) #define CSL_MCBSP_RCR_RWDLEN1_20BITS (0x00000003u) #define CSL_MCBSP_RCR_RWDLEN1_24BITS (0x00000004u) #define CSL_MCBSP_RCR_RWDLEN1_32BITS (0x00000005u) #define CSL_MCBSP_RCR_RWDREVRS_MASK (0x00000010u) #define CSL_MCBSP_RCR_RWDREVRS_SHIFT (0x00000004u) #define CSL_MCBSP_RCR_RWDREVRS_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RESETVAL (0x00000000u) / XCR / #define CSL_MCBSP_XCR_XPHASE_MASK (0x80000000u) #define CSL_MCBSP_XCR_XPHASE_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCR_XPHASE_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XFRLEN2_MASK (0x7F000000u) #define CSL_MCBSP_XCR_XFRLEN2_SHIFT (0x00000018u) #define CSL_MCBSP_XCR_XFRLEN2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XWDLEN2_MASK (0x00E00000u) #define CSL_MCBSP_XCR_XWDLEN2_SHIFT (0x00000015u) #define CSL_MCBSP_XCR_XWDLEN2_RESETVAL (0x00000000u) /----XWDLEN2 Tokens----/ #define CSL_MCBSP_XCR_XWDLEN2_8BITS (0x00000000u) #define CSL_MCBSP_XCR_XWDLEN2_12BITS (0x00000001u) #define CSL_MCBSP_XCR_XWDLEN2_16BITS (0x00000002u) #define CSL_MCBSP_XCR_XWDLEN2_20BITS (0x00000003u) #define CSL_MCBSP_XCR_XWDLEN2_24BITS (0x00000004u) #define CSL_MCBSP_XCR_XWDLEN2_32BITS (0x00000005u) #define CSL_MCBSP_XCR_XCOMPAND_MASK (0x00180000u) #define CSL_MCBSP_XCR_XCOMPAND_SHIFT (0x00000013u) #define CSL_MCBSP_XCR_XCOMPAND_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XFIG_MASK (0x00040000u) #define CSL_MCBSP_XCR_XFIG_SHIFT (0x00000012u) #define CSL_MCBSP_XCR_XFIG_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XDATDLY_MASK (0x00030000u) #define CSL_MCBSP_XCR_XDATDLY_SHIFT (0x00000010u) #define CSL_MCBSP_XCR_XDATDLY_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XFRLEN1_MASK (0x00007F00u) #define CSL_MCBSP_XCR_XFRLEN1_SHIFT (0x00000008u) #define CSL_MCBSP_XCR_XFRLEN1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XWDLEN1_MASK (0x000000E0u) #define CSL_MCBSP_XCR_XWDLEN1_SHIFT (0x00000005u) #define CSL_MCBSP_XCR_XWDLEN1_RESETVAL (0x00000000u) /----XWDLEN1 Tokens----/ #define CSL_MCBSP_XCR_XWDLEN1_8BITS (0x00000000u) #define CSL_MCBSP_XCR_XWDLEN1_12BITS (0x00000001u) #define CSL_MCBSP_XCR_XWDLEN1_16BITS (0x00000002u) #define CSL_MCBSP_XCR_XWDLEN1_20BITS (0x00000003u) #define CSL_MCBSP_XCR_XWDLEN1_24BITS (0x00000004u) #define CSL_MCBSP_XCR_XWDLEN1_32BITS (0x00000005u) #define CSL_MCBSP_XCR_XWDREVRS_MASK (0x00000010u) #define CSL_MCBSP_XCR_XWDREVRS_SHIFT (0x00000004u) #define CSL_MCBSP_XCR_XWDREVRS_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_RESETVAL (0x00000000u) / SRGR / #define CSL_MCBSP_SRGR_GSYNC_MASK (0x80000000u) #define CSL_MCBSP_SRGR_GSYNC_SHIFT (0x0000001Fu) #define CSL_MCBSP_SRGR_GSYNC_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_CLKSP_MASK (0x40000000u) #define CSL_MCBSP_SRGR_CLKSP_SHIFT (0x0000001Eu) #define CSL_MCBSP_SRGR_CLKSP_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_CLKSM_MASK (0x20000000u) #define CSL_MCBSP_SRGR_CLKSM_SHIFT (0x0000001Du) #define CSL_MCBSP_SRGR_CLKSM_RESETVAL (0x00000001u) #define CSL_MCBSP_SRGR_FSGM_MASK (0x10000000u) #define CSL_MCBSP_SRGR_FSGM_SHIFT (0x0000001Cu) #define CSL_MCBSP_SRGR_FSGM_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_FPER_MASK (0x0FFF0000u) #define CSL_MCBSP_SRGR_FPER_SHIFT (0x00000010u) #define CSL_MCBSP_SRGR_FPER_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_FWID_MASK (0x0000FF00u) #define CSL_MCBSP_SRGR_FWID_SHIFT (0x00000008u) #define CSL_MCBSP_SRGR_FWID_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_CLKGDV_MASK (0x000000FFu) #define CSL_MCBSP_SRGR_CLKGDV_SHIFT (0x00000000u) #define CSL_MCBSP_SRGR_CLKGDV_RESETVAL (0x00000001u) #define CSL_MCBSP_SRGR_RESETVAL (0x20000001u) / MCR / #define CSL_MCBSP_MCR_XMCME_MASK (0x02000000u) #define CSL_MCBSP_MCR_XMCME_SHIFT (0x00000019u) #define CSL_MCBSP_MCR_XMCME_RESETVAL (0x00000000u) /----XMCME Tokens----/ #define CSL_MCBSP_MCR_XMCME_PARTITIONS2 (0x00000000u) #define CSL_MCBSP_MCR_XPBBLK_MASK (0x01800000u) #define CSL_MCBSP_MCR_XPBBLK_SHIFT (0x00000017u) #define CSL_MCBSP_MCR_XPBBLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_XPABLK_MASK (0x00600000u) #define CSL_MCBSP_MCR_XPABLK_SHIFT (0x00000015u) #define CSL_MCBSP_MCR_XPABLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_XCBLK_MASK (0x001C0000u) #define CSL_MCBSP_MCR_XCBLK_SHIFT (0x00000012u) #define CSL_MCBSP_MCR_XCBLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_XMCM_MASK (0x00030000u) #define CSL_MCBSP_MCR_XMCM_SHIFT (0x00000010u) #define CSL_MCBSP_MCR_XMCM_RESETVAL (0x00000000u) /----XMCM Tokens----/ #define CSL_MCBSP_MCR_XMCM_ENABLE (0x00000000u) #define CSL_MCBSP_MCR_XMCM_DISABLE (0x00000001u) #define CSL_MCBSP_MCR_XMCM_ENABLE_MASK (0x00000002u) #define CSL_MCBSP_MCR_XMCM_SYMMETRIC (0x00000003u) #define CSL_MCBSP_MCR_RMCME_MASK (0x00000200u) #define CSL_MCBSP_MCR_RMCME_SHIFT (0x00000009u) #define CSL_MCBSP_MCR_RMCME_RESETVAL (0x00000000u) /----RMCME Tokens----/ #define CSL_MCBSP_MCR_RMCME_PARTITIONS2 (0x00000000u) #define CSL_MCBSP_MCR_RMCME_PARTITIONS8 (0x00000001u) #define CSL_MCBSP_MCR_RPBBLK_MASK (0x00000180u) #define CSL_MCBSP_MCR_RPBBLK_SHIFT (0x00000007u) #define CSL_MCBSP_MCR_RPBBLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_RPABLK_MASK (0x00000060u) #define CSL_MCBSP_MCR_RPABLK_SHIFT (0x00000005u) #define CSL_MCBSP_MCR_RPABLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_RCBLK_MASK (0x0000001Cu) #define CSL_MCBSP_MCR_RCBLK_SHIFT (0x00000002u) #define CSL_MCBSP_MCR_RCBLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_RMCM_MASK (0x00000001u) #define CSL_MCBSP_MCR_RMCM_SHIFT (0x00000000u) #define CSL_MCBSP_MCR_RMCM_RESETVAL (0x00000000u) /----RMCM Tokens----/ #define CSL_MCBSP_MCR_RMCM_ENABLE (0x00000000u) #define CSL_MCBSP_MCR_RMCM_DISABLE (0x00000001u) #define CSL_MCBSP_MCR_RESETVAL (0x00000000u) / RCERE0 / #define CSL_MCBSP_RCERE0_RCE31_MASK (0x80000000u) #define CSL_MCBSP_RCERE0_RCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCERE0_RCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE30_MASK (0x40000000u) #define CSL_MCBSP_RCERE0_RCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_RCERE0_RCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE29_MASK (0x20000000u) #define CSL_MCBSP_RCERE0_RCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_RCERE0_RCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE28_MASK (0x10000000u) #define CSL_MCBSP_RCERE0_RCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_RCERE0_RCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE27_MASK (0x08000000u) #define CSL_MCBSP_RCERE0_RCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_RCERE0_RCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE26_MASK (0x04000000u) #define CSL_MCBSP_RCERE0_RCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_RCERE0_RCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE25_MASK (0x02000000u) #define CSL_MCBSP_RCERE0_RCE25_SHIFT (0x00000019u) #define CSL_MCBSP_RCERE0_RCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE24_MASK (0x01000000u) #define CSL_MCBSP_RCERE0_RCE24_SHIFT (0x00000018u) #define CSL_MCBSP_RCERE0_RCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE23_MASK (0x00800000u) #define CSL_MCBSP_RCERE0_RCE23_SHIFT (0x00000017u) #define CSL_MCBSP_RCERE0_RCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE22_MASK (0x00400000u) #define CSL_MCBSP_RCERE0_RCE22_SHIFT (0x00000016u) #define CSL_MCBSP_RCERE0_RCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE21_MASK (0x00200000u) #define CSL_MCBSP_RCERE0_RCE21_SHIFT (0x00000015u) #define CSL_MCBSP_RCERE0_RCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE20_MASK (0x00100000u) #define CSL_MCBSP_RCERE0_RCE20_SHIFT (0x00000014u) #define CSL_MCBSP_RCERE0_RCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE19_MASK (0x00080000u) #define CSL_MCBSP_RCERE0_RCE19_SHIFT (0x00000013u) #define CSL_MCBSP_RCERE0_RCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE18_MASK (0x00040000u) #define CSL_MCBSP_RCERE0_RCE18_SHIFT (0x00000012u) #define CSL_MCBSP_RCERE0_RCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE17_MASK (0x00020000u) #define CSL_MCBSP_RCERE0_RCE17_SHIFT (0x00000011u) #define CSL_MCBSP_RCERE0_RCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE16_MASK (0x00010000u) #define CSL_MCBSP_RCERE0_RCE16_SHIFT (0x00000010u) #define CSL_MCBSP_RCERE0_RCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE15_MASK (0x00008000u) #define CSL_MCBSP_RCERE0_RCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_RCERE0_RCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE14_MASK (0x00004000u) #define CSL_MCBSP_RCERE0_RCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_RCERE0_RCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE13_MASK (0x00002000u) #define CSL_MCBSP_RCERE0_RCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_RCERE0_RCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE12_MASK (0x00001000u) #define CSL_MCBSP_RCERE0_RCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_RCERE0_RCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE11_MASK (0x00000800u) #define CSL_MCBSP_RCERE0_RCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_RCERE0_RCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE10_MASK (0x00000400u) #define CSL_MCBSP_RCERE0_RCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_RCERE0_RCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE9_MASK (0x00000200u) #define CSL_MCBSP_RCERE0_RCE9_SHIFT (0x00000009u) #define CSL_MCBSP_RCERE0_RCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE8_MASK (0x00000100u) #define CSL_MCBSP_RCERE0_RCE8_SHIFT (0x00000008u) #define CSL_MCBSP_RCERE0_RCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE7_MASK (0x00000080u) #define CSL_MCBSP_RCERE0_RCE7_SHIFT (0x00000007u) #define CSL_MCBSP_RCERE0_RCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE6_MASK (0x00000040u) #define CSL_MCBSP_RCERE0_RCE6_SHIFT (0x00000006u) #define CSL_MCBSP_RCERE0_RCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE5_MASK (0x00000020u) #define CSL_MCBSP_RCERE0_RCE5_SHIFT (0x00000005u) #define CSL_MCBSP_RCERE0_RCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE4_MASK (0x00000010u) #define CSL_MCBSP_RCERE0_RCE4_SHIFT (0x00000004u) #define CSL_MCBSP_RCERE0_RCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE3_MASK (0x00000008u) #define CSL_MCBSP_RCERE0_RCE3_SHIFT (0x00000003u) #define CSL_MCBSP_RCERE0_RCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE2_MASK (0x00000004u) #define CSL_MCBSP_RCERE0_RCE2_SHIFT (0x00000002u) #define CSL_MCBSP_RCERE0_RCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE1_MASK (0x00000002u) #define CSL_MCBSP_RCERE0_RCE1_SHIFT (0x00000001u) #define CSL_MCBSP_RCERE0_RCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE0_MASK (0x00000001u) #define CSL_MCBSP_RCERE0_RCE0_SHIFT (0x00000000u) #define CSL_MCBSP_RCERE0_RCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RESETVAL (0x00000000u) / XCERE0 / #define CSL_MCBSP_XCERE0_XCE31_MASK (0x80000000u) #define CSL_MCBSP_XCERE0_XCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCERE0_XCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE30_MASK (0x40000000u) #define CSL_MCBSP_XCERE0_XCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_XCERE0_XCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE29_MASK (0x20000000u) #define CSL_MCBSP_XCERE0_XCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_XCERE0_XCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE28_MASK (0x10000000u) #define CSL_MCBSP_XCERE0_XCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_XCERE0_XCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE27_MASK (0x08000000u) #define CSL_MCBSP_XCERE0_XCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_XCERE0_XCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE26_MASK (0x04000000u) #define CSL_MCBSP_XCERE0_XCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_XCERE0_XCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE25_MASK (0x02000000u) #define CSL_MCBSP_XCERE0_XCE25_SHIFT (0x00000019u) #define CSL_MCBSP_XCERE0_XCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE24_MASK (0x01000000u) #define CSL_MCBSP_XCERE0_XCE24_SHIFT (0x00000018u) #define CSL_MCBSP_XCERE0_XCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE23_MASK (0x00800000u) #define CSL_MCBSP_XCERE0_XCE23_SHIFT (0x00000017u) #define CSL_MCBSP_XCERE0_XCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE22_MASK (0x00400000u) #define CSL_MCBSP_XCERE0_XCE22_SHIFT (0x00000016u) #define CSL_MCBSP_XCERE0_XCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE21_MASK (0x00200000u) #define CSL_MCBSP_XCERE0_XCE21_SHIFT (0x00000015u) #define CSL_MCBSP_XCERE0_XCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE20_MASK (0x00100000u) #define CSL_MCBSP_XCERE0_XCE20_SHIFT (0x00000014u) #define CSL_MCBSP_XCERE0_XCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE19_MASK (0x00080000u) #define CSL_MCBSP_XCERE0_XCE19_SHIFT (0x00000013u) #define CSL_MCBSP_XCERE0_XCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE18_MASK (0x00040000u) #define CSL_MCBSP_XCERE0_XCE18_SHIFT (0x00000012u) #define CSL_MCBSP_XCERE0_XCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE17_MASK (0x00020000u) #define CSL_MCBSP_XCERE0_XCE17_SHIFT (0x00000011u) #define CSL_MCBSP_XCERE0_XCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE16_MASK (0x00010000u) #define CSL_MCBSP_XCERE0_XCE16_SHIFT (0x00000010u) #define CSL_MCBSP_XCERE0_XCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE15_MASK (0x00008000u) #define CSL_MCBSP_XCERE0_XCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_XCERE0_XCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE14_MASK (0x00004000u) #define CSL_MCBSP_XCERE0_XCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_XCERE0_XCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE13_MASK (0x00002000u) #define CSL_MCBSP_XCERE0_XCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_XCERE0_XCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE12_MASK (0x00001000u) #define CSL_MCBSP_XCERE0_XCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_XCERE0_XCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE11_MASK (0x00000800u) #define CSL_MCBSP_XCERE0_XCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_XCERE0_XCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE10_MASK (0x00000400u) #define CSL_MCBSP_XCERE0_XCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_XCERE0_XCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE9_MASK (0x00000200u) #define CSL_MCBSP_XCERE0_XCE9_SHIFT (0x00000009u) #define CSL_MCBSP_XCERE0_XCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE8_MASK (0x00000100u) #define CSL_MCBSP_XCERE0_XCE8_SHIFT (0x00000008u) #define CSL_MCBSP_XCERE0_XCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE7_MASK (0x00000080u) #define CSL_MCBSP_XCERE0_XCE7_SHIFT (0x00000007u) #define CSL_MCBSP_XCERE0_XCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE6_MASK (0x00000040u) #define CSL_MCBSP_XCERE0_XCE6_SHIFT (0x00000006u) #define CSL_MCBSP_XCERE0_XCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE5_MASK (0x00000020u) #define CSL_MCBSP_XCERE0_XCE5_SHIFT (0x00000005u) #define CSL_MCBSP_XCERE0_XCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE4_MASK (0x00000010u) #define CSL_MCBSP_XCERE0_XCE4_SHIFT (0x00000004u) #define CSL_MCBSP_XCERE0_XCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE3_MASK (0x00000008u) #define CSL_MCBSP_XCERE0_XCE3_SHIFT (0x00000003u) #define CSL_MCBSP_XCERE0_XCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE2_MASK (0x00000004u) #define CSL_MCBSP_XCERE0_XCE2_SHIFT (0x00000002u) #define CSL_MCBSP_XCERE0_XCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE1_MASK (0x00000002u) #define CSL_MCBSP_XCERE0_XCE1_SHIFT (0x00000001u) #define CSL_MCBSP_XCERE0_XCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE0_MASK (0x00000001u) #define CSL_MCBSP_XCERE0_XCE0_SHIFT (0x00000000u) #define CSL_MCBSP_XCERE0_XCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_RESETVAL (0x00000000u) / PCR / #define CSL_MCBSP_PCR_XIOEN_MASK (0x00002000u) #define CSL_MCBSP_PCR_XIOEN_SHIFT (0x0000000Du) #define CSL_MCBSP_PCR_XIOEN_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_RIOEN_MASK (0x00001000u) #define CSL_MCBSP_PCR_RIOEN_SHIFT (0x0000000Cu) #define CSL_MCBSP_PCR_RIOEN_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_FSXM_MASK (0x00000800u) #define CSL_MCBSP_PCR_FSXM_SHIFT (0x0000000Bu) #define CSL_MCBSP_PCR_FSXM_RESETVAL (0x00000000u) /----FSXM Tokens----/ #define CSL_MCBSP_PCR_FSXM_INPUT (0x00000000u) #define CSL_MCBSP_PCR_FSXM_OUTPUT (0x00000001u) #define CSL_MCBSP_PCR_FSRM_MASK (0x00000400u) #define CSL_MCBSP_PCR_FSRM_SHIFT (0x0000000Au) #define CSL_MCBSP_PCR_FSRM_RESETVAL (0x00000000u) /----FSRM Tokens----/ #define CSL_MCBSP_PCR_FSRM_INPUT (0x00000000u) #define CSL_MCBSP_PCR_FSRM_OUTPUT (0x00000001u) #define CSL_MCBSP_PCR_CLKXM_MASK (0x00000200u) #define CSL_MCBSP_PCR_CLKXM_SHIFT (0x00000009u) #define CSL_MCBSP_PCR_CLKXM_RESETVAL (0x00000000u) /----CLKXM Tokens----/ #define CSL_MCBSP_PCR_CLKXM_INPUT (0x00000000u) #define CSL_MCBSP_PCR_CLKXM_OUTPUT (0x00000001u) #define CSL_MCBSP_PCR_CLKRM_MASK (0x00000100u) #define CSL_MCBSP_PCR_CLKRM_SHIFT (0x00000008u) #define CSL_MCBSP_PCR_CLKRM_RESETVAL (0x00000000u) /----CLKRM Tokens----/ #define CSL_MCBSP_PCR_CLKRM_INPUT (0x00000000u) #define CSL_MCBSP_PCR_CLKRM_OUTPUT (0x00000001u) #define CSL_MCBSP_PCR_CLKSSTAT_MASK (0x00000040u) #define CSL_MCBSP_PCR_CLKSSTAT_SHIFT (0x00000006u) #define CSL_MCBSP_PCR_CLKSSTAT_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_DXSTAT_MASK (0x00000020u) #define CSL_MCBSP_PCR_DXSTAT_SHIFT (0x00000005u) #define CSL_MCBSP_PCR_DXSTAT_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_DRSTAT_MASK (0x00000010u) #define CSL_MCBSP_PCR_DRSTAT_SHIFT (0x00000004u) #define CSL_MCBSP_PCR_DRSTAT_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_FSXP_MASK (0x00000008u) #define CSL_MCBSP_PCR_FSXP_SHIFT (0x00000003u) #define CSL_MCBSP_PCR_FSXP_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_FSRP_MASK (0x00000004u) #define CSL_MCBSP_PCR_FSRP_SHIFT (0x00000002u) #define CSL_MCBSP_PCR_FSRP_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_CLKXP_MASK (0x00000002u) #define CSL_MCBSP_PCR_CLKXP_SHIFT (0x00000001u) #define CSL_MCBSP_PCR_CLKXP_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_CLKRP_MASK (0x00000001u) #define CSL_MCBSP_PCR_CLKRP_SHIFT (0x00000000u) #define CSL_MCBSP_PCR_CLKRP_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_RESETVAL (0x00000000u) / RCERE1 / #define CSL_MCBSP_RCERE1_RCE31_MASK (0x80000000u) #define CSL_MCBSP_RCERE1_RCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCERE1_RCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE30_MASK (0x40000000u) #define CSL_MCBSP_RCERE1_RCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_RCERE1_RCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE29_MASK (0x20000000u) #define CSL_MCBSP_RCERE1_RCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_RCERE1_RCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE28_MASK (0x10000000u) #define CSL_MCBSP_RCERE1_RCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_RCERE1_RCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE27_MASK (0x08000000u) #define CSL_MCBSP_RCERE1_RCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_RCERE1_RCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE26_MASK (0x04000000u) #define CSL_MCBSP_RCERE1_RCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_RCERE1_RCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE25_MASK (0x02000000u) #define CSL_MCBSP_RCERE1_RCE25_SHIFT (0x00000019u) #define CSL_MCBSP_RCERE1_RCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE24_MASK (0x01000000u) #define CSL_MCBSP_RCERE1_RCE24_SHIFT (0x00000018u) #define CSL_MCBSP_RCERE1_RCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE23_MASK (0x00800000u) #define CSL_MCBSP_RCERE1_RCE23_SHIFT (0x00000017u) #define CSL_MCBSP_RCERE1_RCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE22_MASK (0x00400000u) #define CSL_MCBSP_RCERE1_RCE22_SHIFT (0x00000016u) #define CSL_MCBSP_RCERE1_RCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE21_MASK (0x00200000u) #define CSL_MCBSP_RCERE1_RCE21_SHIFT (0x00000015u) #define CSL_MCBSP_RCERE1_RCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE20_MASK (0x00100000u) #define CSL_MCBSP_RCERE1_RCE20_SHIFT (0x00000014u) #define CSL_MCBSP_RCERE1_RCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE19_MASK (0x00080000u) #define CSL_MCBSP_RCERE1_RCE19_SHIFT (0x00000013u) #define CSL_MCBSP_RCERE1_RCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE18_MASK (0x00040000u) #define CSL_MCBSP_RCERE1_RCE18_SHIFT (0x00000012u) #define CSL_MCBSP_RCERE1_RCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE17_MASK (0x00020000u) #define CSL_MCBSP_RCERE1_RCE17_SHIFT (0x00000011u) #define CSL_MCBSP_RCERE1_RCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE16_MASK (0x00010000u) #define CSL_MCBSP_RCERE1_RCE16_SHIFT (0x00000010u) #define CSL_MCBSP_RCERE1_RCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE15_MASK (0x00008000u) #define CSL_MCBSP_RCERE1_RCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_RCERE1_RCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE14_MASK (0x00004000u) #define CSL_MCBSP_RCERE1_RCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_RCERE1_RCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE13_MASK (0x00002000u) #define CSL_MCBSP_RCERE1_RCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_RCERE1_RCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE12_MASK (0x00001000u) #define CSL_MCBSP_RCERE1_RCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_RCERE1_RCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE11_MASK (0x00000800u) #define CSL_MCBSP_RCERE1_RCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_RCERE1_RCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE10_MASK (0x00000400u) #define CSL_MCBSP_RCERE1_RCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_RCERE1_RCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE9_MASK (0x00000200u) #define CSL_MCBSP_RCERE1_RCE9_SHIFT (0x00000009u) #define CSL_MCBSP_RCERE1_RCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE8_MASK (0x00000100u) #define CSL_MCBSP_RCERE1_RCE8_SHIFT (0x00000008u) #define CSL_MCBSP_RCERE1_RCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE7_MASK (0x00000080u) #define CSL_MCBSP_RCERE1_RCE7_SHIFT (0x00000007u) #define CSL_MCBSP_RCERE1_RCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE6_MASK (0x00000040u) #define CSL_MCBSP_RCERE1_RCE6_SHIFT (0x00000006u) #define CSL_MCBSP_RCERE1_RCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE5_MASK (0x00000020u) #define CSL_MCBSP_RCERE1_RCE5_SHIFT (0x00000005u) #define CSL_MCBSP_RCERE1_RCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE4_MASK (0x00000010u) #define CSL_MCBSP_RCERE1_RCE4_SHIFT (0x00000004u) #define CSL_MCBSP_RCERE1_RCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE3_MASK (0x00000008u) #define CSL_MCBSP_RCERE1_RCE3_SHIFT (0x00000003u) #define CSL_MCBSP_RCERE1_RCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE2_MASK (0x00000004u) #define CSL_MCBSP_RCERE1_RCE2_SHIFT (0x00000002u) #define CSL_MCBSP_RCERE1_RCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE1_MASK (0x00000002u) #define CSL_MCBSP_RCERE1_RCE1_SHIFT (0x00000001u) #define CSL_MCBSP_RCERE1_RCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE0_MASK (0x00000001u) #define CSL_MCBSP_RCERE1_RCE0_SHIFT (0x00000000u) #define CSL_MCBSP_RCERE1_RCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RESETVAL (0x00000000u) / XCERE1 / #define CSL_MCBSP_XCERE1_XCE31_MASK (0x80000000u) #define CSL_MCBSP_XCERE1_XCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCERE1_XCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE30_MASK (0x40000000u) #define CSL_MCBSP_XCERE1_XCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_XCERE1_XCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE29_MASK (0x20000000u) #define CSL_MCBSP_XCERE1_XCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_XCERE1_XCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE28_MASK (0x10000000u) #define CSL_MCBSP_XCERE1_XCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_XCERE1_XCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE27_MASK (0x08000000u) #define CSL_MCBSP_XCERE1_XCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_XCERE1_XCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE26_MASK (0x04000000u) #define CSL_MCBSP_XCERE1_XCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_XCERE1_XCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE25_MASK (0x02000000u) #define CSL_MCBSP_XCERE1_XCE25_SHIFT (0x00000019u) #define CSL_MCBSP_XCERE1_XCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE24_MASK (0x01000000u) #define CSL_MCBSP_XCERE1_XCE24_SHIFT (0x00000018u) #define CSL_MCBSP_XCERE1_XCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE23_MASK (0x00800000u) #define CSL_MCBSP_XCERE1_XCE23_SHIFT (0x00000017u) #define CSL_MCBSP_XCERE1_XCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE22_MASK (0x00400000u) #define CSL_MCBSP_XCERE1_XCE22_SHIFT (0x00000016u) #define CSL_MCBSP_XCERE1_XCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE21_MASK (0x00200000u) #define CSL_MCBSP_XCERE1_XCE21_SHIFT (0x00000015u) #define CSL_MCBSP_XCERE1_XCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE20_MASK (0x00100000u) #define CSL_MCBSP_XCERE1_XCE20_SHIFT (0x00000014u) #define CSL_MCBSP_XCERE1_XCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE19_MASK (0x00080000u) #define CSL_MCBSP_XCERE1_XCE19_SHIFT (0x00000013u) #define CSL_MCBSP_XCERE1_XCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE18_MASK (0x00040000u) #define CSL_MCBSP_XCERE1_XCE18_SHIFT (0x00000012u) #define CSL_MCBSP_XCERE1_XCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE17_MASK (0x00020000u) #define CSL_MCBSP_XCERE1_XCE17_SHIFT (0x00000011u) #define CSL_MCBSP_XCERE1_XCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE16_MASK (0x00010000u) #define CSL_MCBSP_XCERE1_XCE16_SHIFT (0x00000010u) #define CSL_MCBSP_XCERE1_XCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE15_MASK (0x00008000u) #define CSL_MCBSP_XCERE1_XCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_XCERE1_XCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE14_MASK (0x00004000u) #define CSL_MCBSP_XCERE1_XCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_XCERE1_XCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE13_MASK (0x00002000u) #define CSL_MCBSP_XCERE1_XCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_XCERE1_XCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE12_MASK (0x00001000u) #define CSL_MCBSP_XCERE1_XCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_XCERE1_XCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE11_MASK (0x00000800u) #define CSL_MCBSP_XCERE1_XCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_XCERE1_XCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE10_MASK (0x00000400u) #define CSL_MCBSP_XCERE1_XCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_XCERE1_XCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE9_MASK (0x00000200u) #define CSL_MCBSP_XCERE1_XCE9_SHIFT (0x00000009u) #define CSL_MCBSP_XCERE1_XCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE8_MASK (0x00000100u) #define CSL_MCBSP_XCERE1_XCE8_SHIFT (0x00000008u) #define CSL_MCBSP_XCERE1_XCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE7_MASK (0x00000080u) #define CSL_MCBSP_XCERE1_XCE7_SHIFT (0x00000007u) #define CSL_MCBSP_XCERE1_XCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE6_MASK (0x00000040u) #define CSL_MCBSP_XCERE1_XCE6_SHIFT (0x00000006u) #define CSL_MCBSP_XCERE1_XCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE5_MASK (0x00000020u) #define CSL_MCBSP_XCERE1_XCE5_SHIFT (0x00000005u) #define CSL_MCBSP_XCERE1_XCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE4_MASK (0x00000010u) #define CSL_MCBSP_XCERE1_XCE4_SHIFT (0x00000004u) #define CSL_MCBSP_XCERE1_XCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE3_MASK (0x00000008u) #define CSL_MCBSP_XCERE1_XCE3_SHIFT (0x00000003u) #define CSL_MCBSP_XCERE1_XCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE2_MASK (0x00000004u) #define CSL_MCBSP_XCERE1_XCE2_SHIFT (0x00000002u) #define CSL_MCBSP_XCERE1_XCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE1_MASK (0x00000002u) #define CSL_MCBSP_XCERE1_XCE1_SHIFT (0x00000001u) #define CSL_MCBSP_XCERE1_XCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE0_MASK (0x00000001u) #define CSL_MCBSP_XCERE1_XCE0_SHIFT (0x00000000u) #define CSL_MCBSP_XCERE1_XCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_RESETVAL (0x00000000u) / RCERE2 / #define CSL_MCBSP_RCERE2_RCE31_MASK (0x80000000u) #define CSL_MCBSP_RCERE2_RCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCERE2_RCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE30_MASK (0x40000000u) #define CSL_MCBSP_RCERE2_RCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_RCERE2_RCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE29_MASK (0x20000000u) #define CSL_MCBSP_RCERE2_RCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_RCERE2_RCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE28_MASK (0x10000000u) #define CSL_MCBSP_RCERE2_RCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_RCERE2_RCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE27_MASK (0x08000000u) #define CSL_MCBSP_RCERE2_RCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_RCERE2_RCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE26_MASK (0x04000000u) #define CSL_MCBSP_RCERE2_RCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_RCERE2_RCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE25_MASK (0x02000000u) #define CSL_MCBSP_RCERE2_RCE25_SHIFT (0x00000019u) #define CSL_MCBSP_RCERE2_RCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE24_MASK (0x01000000u) #define CSL_MCBSP_RCERE2_RCE24_SHIFT (0x00000018u) #define CSL_MCBSP_RCERE2_RCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE23_MASK (0x00800000u) #define CSL_MCBSP_RCERE2_RCE23_SHIFT (0x00000017u) #define CSL_MCBSP_RCERE2_RCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE22_MASK (0x00400000u) #define CSL_MCBSP_RCERE2_RCE22_SHIFT (0x00000016u) #define CSL_MCBSP_RCERE2_RCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE21_MASK (0x00200000u) #define CSL_MCBSP_RCERE2_RCE21_SHIFT (0x00000015u) #define CSL_MCBSP_RCERE2_RCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE20_MASK (0x00100000u) #define CSL_MCBSP_RCERE2_RCE20_SHIFT (0x00000014u) #define CSL_MCBSP_RCERE2_RCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE19_MASK (0x00080000u) #define CSL_MCBSP_RCERE2_RCE19_SHIFT (0x00000013u) #define CSL_MCBSP_RCERE2_RCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE18_MASK (0x00040000u) #define CSL_MCBSP_RCERE2_RCE18_SHIFT (0x00000012u) #define CSL_MCBSP_RCERE2_RCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE17_MASK (0x00020000u) #define CSL_MCBSP_RCERE2_RCE17_SHIFT (0x00000011u) #define CSL_MCBSP_RCERE2_RCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE16_MASK (0x00010000u) #define CSL_MCBSP_RCERE2_RCE16_SHIFT (0x00000010u) #define CSL_MCBSP_RCERE2_RCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE15_MASK (0x00008000u) #define CSL_MCBSP_RCERE2_RCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_RCERE2_RCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE14_MASK (0x00004000u) #define CSL_MCBSP_RCERE2_RCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_RCERE2_RCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE13_MASK (0x00002000u) #define CSL_MCBSP_RCERE2_RCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_RCERE2_RCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE12_MASK (0x00001000u) #define CSL_MCBSP_RCERE2_RCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_RCERE2_RCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE11_MASK (0x00000800u) #define CSL_MCBSP_RCERE2_RCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_RCERE2_RCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE10_MASK (0x00000400u) #define CSL_MCBSP_RCERE2_RCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_RCERE2_RCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE9_MASK (0x00000200u) #define CSL_MCBSP_RCERE2_RCE9_SHIFT (0x00000009u) #define CSL_MCBSP_RCERE2_RCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE8_MASK (0x00000100u) #define CSL_MCBSP_RCERE2_RCE8_SHIFT (0x00000008u) #define CSL_MCBSP_RCERE2_RCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE7_MASK (0x00000080u) #define CSL_MCBSP_RCERE2_RCE7_SHIFT (0x00000007u) #define CSL_MCBSP_RCERE2_RCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE6_MASK (0x00000040u) #define CSL_MCBSP_RCERE2_RCE6_SHIFT (0x00000006u) #define CSL_MCBSP_RCERE2_RCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE5_MASK (0x00000020u) #define CSL_MCBSP_RCERE2_RCE5_SHIFT (0x00000005u) #define CSL_MCBSP_RCERE2_RCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE4_MASK (0x00000010u) #define CSL_MCBSP_RCERE2_RCE4_SHIFT (0x00000004u) #define CSL_MCBSP_RCERE2_RCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE3_MASK (0x00000008u) #define CSL_MCBSP_RCERE2_RCE3_SHIFT (0x00000003u) #define CSL_MCBSP_RCERE2_RCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE2_MASK (0x00000004u) #define CSL_MCBSP_RCERE2_RCE2_SHIFT (0x00000002u) #define CSL_MCBSP_RCERE2_RCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE1_MASK (0x00000002u) #define CSL_MCBSP_RCERE2_RCE1_SHIFT (0x00000001u) #define CSL_MCBSP_RCERE2_RCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE0_MASK (0x00000001u) #define CSL_MCBSP_RCERE2_RCE0_SHIFT (0x00000000u) #define CSL_MCBSP_RCERE2_RCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RESETVAL (0x00000000u) / XCERE2 / #define CSL_MCBSP_XCERE2_XCE31_MASK (0x80000000u) #define CSL_MCBSP_XCERE2_XCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCERE2_XCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE30_MASK (0x40000000u) #define CSL_MCBSP_XCERE2_XCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_XCERE2_XCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE29_MASK (0x20000000u) #define CSL_MCBSP_XCERE2_XCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_XCERE2_XCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE28_MASK (0x10000000u) #define CSL_MCBSP_XCERE2_XCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_XCERE2_XCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE27_MASK (0x08000000u) #define CSL_MCBSP_XCERE2_XCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_XCERE2_XCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE26_MASK (0x04000000u) #define CSL_MCBSP_XCERE2_XCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_XCERE2_XCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE25_MASK (0x02000000u) #define CSL_MCBSP_XCERE2_XCE25_SHIFT (0x00000019u) #define CSL_MCBSP_XCERE2_XCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE24_MASK (0x01000000u) #define CSL_MCBSP_XCERE2_XCE24_SHIFT (0x00000018u) #define CSL_MCBSP_XCERE2_XCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE23_MASK (0x00800000u) #define CSL_MCBSP_XCERE2_XCE23_SHIFT (0x00000017u) #define CSL_MCBSP_XCERE2_XCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE22_MASK (0x00400000u) #define CSL_MCBSP_XCERE2_XCE22_SHIFT (0x00000016u) #define CSL_MCBSP_XCERE2_XCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE21_MASK (0x00200000u) #define CSL_MCBSP_XCERE2_XCE21_SHIFT (0x00000015u) #define CSL_MCBSP_XCERE2_XCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE20_MASK (0x00100000u) #define CSL_MCBSP_XCERE2_XCE20_SHIFT (0x00000014u) #define CSL_MCBSP_XCERE2_XCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE19_MASK (0x00080000u) #define CSL_MCBSP_XCERE2_XCE19_SHIFT (0x00000013u) #define CSL_MCBSP_XCERE2_XCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE18_MASK (0x00040000u) #define CSL_MCBSP_XCERE2_XCE18_SHIFT (0x00000012u) #define CSL_MCBSP_XCERE2_XCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE17_MASK (0x00020000u) #define CSL_MCBSP_XCERE2_XCE17_SHIFT (0x00000011u) #define CSL_MCBSP_XCERE2_XCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE16_MASK (0x00010000u) #define CSL_MCBSP_XCERE2_XCE16_SHIFT (0x00000010u) #define CSL_MCBSP_XCERE2_XCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE15_MASK (0x00008000u) #define CSL_MCBSP_XCERE2_XCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_XCERE2_XCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE14_MASK (0x00004000u) #define CSL_MCBSP_XCERE2_XCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_XCERE2_XCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE13_MASK (0x00002000u) #define CSL_MCBSP_XCERE2_XCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_XCERE2_XCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE12_MASK (0x00001000u) #define CSL_MCBSP_XCERE2_XCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_XCERE2_XCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE11_MASK (0x00000800u) #define CSL_MCBSP_XCERE2_XCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_XCERE2_XCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE10_MASK (0x00000400u) #define CSL_MCBSP_XCERE2_XCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_XCERE2_XCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE9_MASK (0x00000200u) #define CSL_MCBSP_XCERE2_XCE9_SHIFT (0x00000009u) #define CSL_MCBSP_XCERE2_XCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE8_MASK (0x00000100u) #define CSL_MCBSP_XCERE2_XCE8_SHIFT (0x00000008u) #define CSL_MCBSP_XCERE2_XCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE7_MASK (0x00000080u) #define CSL_MCBSP_XCERE2_XCE7_SHIFT (0x00000007u) #define CSL_MCBSP_XCERE2_XCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE6_MASK (0x00000040u) #define CSL_MCBSP_XCERE2_XCE6_SHIFT (0x00000006u) #define CSL_MCBSP_XCERE2_XCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE5_MASK (0x00000020u) #define CSL_MCBSP_XCERE2_XCE5_SHIFT (0x00000005u) #define CSL_MCBSP_XCERE2_XCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE4_MASK (0x00000010u) #define CSL_MCBSP_XCERE2_XCE4_SHIFT (0x00000004u) #define CSL_MCBSP_XCERE2_XCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE3_MASK (0x00000008u) #define CSL_MCBSP_XCERE2_XCE3_SHIFT (0x00000003u) #define CSL_MCBSP_XCERE2_XCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE2_MASK (0x00000004u) #define CSL_MCBSP_XCERE2_XCE2_SHIFT (0x00000002u) #define CSL_MCBSP_XCERE2_XCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE1_MASK (0x00000002u) #define CSL_MCBSP_XCERE2_XCE1_SHIFT (0x00000001u) #define CSL_MCBSP_XCERE2_XCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE0_MASK (0x00000001u) #define CSL_MCBSP_XCERE2_XCE0_SHIFT (0x00000000u) #define CSL_MCBSP_XCERE2_XCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_RESETVAL (0x00000000u) / RCERE3 / #define CSL_MCBSP_RCERE3_RCE31_MASK (0x80000000u) #define CSL_MCBSP_RCERE3_RCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCERE3_RCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE30_MASK (0x40000000u) #define CSL_MCBSP_RCERE3_RCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_RCERE3_RCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE29_MASK (0x20000000u) #define CSL_MCBSP_RCERE3_RCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_RCERE3_RCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE28_MASK (0x10000000u) #define CSL_MCBSP_RCERE3_RCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_RCERE3_RCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE27_MASK (0x08000000u) #define CSL_MCBSP_RCERE3_RCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_RCERE3_RCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE26_MASK (0x04000000u) #define CSL_MCBSP_RCERE3_RCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_RCERE3_RCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE25_MASK (0x02000000u) #define CSL_MCBSP_RCERE3_RCE25_SHIFT (0x00000019u) #define CSL_MCBSP_RCERE3_RCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE24_MASK (0x01000000u) #define CSL_MCBSP_RCERE3_RCE24_SHIFT (0x00000018u) #define CSL_MCBSP_RCERE3_RCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE23_MASK (0x00800000u) #define CSL_MCBSP_RCERE3_RCE23_SHIFT (0x00000017u) #define CSL_MCBSP_RCERE3_RCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE22_MASK (0x00400000u) #define CSL_MCBSP_RCERE3_RCE22_SHIFT (0x00000016u) #define CSL_MCBSP_RCERE3_RCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE21_MASK (0x00200000u) #define CSL_MCBSP_RCERE3_RCE21_SHIFT (0x00000015u) #define CSL_MCBSP_RCERE3_RCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE20_MASK (0x00100000u) #define CSL_MCBSP_RCERE3_RCE20_SHIFT (0x00000014u) #define CSL_MCBSP_RCERE3_RCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE19_MASK (0x00080000u) #define CSL_MCBSP_RCERE3_RCE19_SHIFT (0x00000013u) #define CSL_MCBSP_RCERE3_RCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE18_MASK (0x00040000u) #define CSL_MCBSP_RCERE3_RCE18_SHIFT (0x00000012u) #define CSL_MCBSP_RCERE3_RCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE17_MASK (0x00020000u) #define CSL_MCBSP_RCERE3_RCE17_SHIFT (0x00000011u) #define CSL_MCBSP_RCERE3_RCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE16_MASK (0x00010000u) #define CSL_MCBSP_RCERE3_RCE16_SHIFT (0x00000010u) #define CSL_MCBSP_RCERE3_RCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE15_MASK (0x00008000u) #define CSL_MCBSP_RCERE3_RCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_RCERE3_RCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE14_MASK (0x00004000u) #define CSL_MCBSP_RCERE3_RCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_RCERE3_RCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE13_MASK (0x00002000u) #define CSL_MCBSP_RCERE3_RCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_RCERE3_RCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE12_MASK (0x00001000u) #define CSL_MCBSP_RCERE3_RCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_RCERE3_RCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE11_MASK (0x00000800u) #define CSL_MCBSP_RCERE3_RCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_RCERE3_RCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE10_MASK (0x00000400u) #define CSL_MCBSP_RCERE3_RCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_RCERE3_RCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE9_MASK (0x00000200u) #define CSL_MCBSP_RCERE3_RCE9_SHIFT (0x00000009u) #define CSL_MCBSP_RCERE3_RCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE8_MASK (0x00000100u) #define CSL_MCBSP_RCERE3_RCE8_SHIFT (0x00000008u) #define CSL_MCBSP_RCERE3_RCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE7_MASK (0x00000080u) #define CSL_MCBSP_RCERE3_RCE7_SHIFT (0x00000007u) #define CSL_MCBSP_RCERE3_RCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE6_MASK (0x00000040u) #define CSL_MCBSP_RCERE3_RCE6_SHIFT (0x00000006u) #define CSL_MCBSP_RCERE3_RCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE5_MASK (0x00000020u) #define CSL_MCBSP_RCERE3_RCE5_SHIFT (0x00000005u) #define CSL_MCBSP_RCERE3_RCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE4_MASK (0x00000010u) #define CSL_MCBSP_RCERE3_RCE4_SHIFT (0x00000004u) #define CSL_MCBSP_RCERE3_RCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE3_MASK (0x00000008u) #define CSL_MCBSP_RCERE3_RCE3_SHIFT (0x00000003u) #define CSL_MCBSP_RCERE3_RCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE2_MASK (0x00000004u) #define CSL_MCBSP_RCERE3_RCE2_SHIFT (0x00000002u) #define CSL_MCBSP_RCERE3_RCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE1_MASK (0x00000002u) #define CSL_MCBSP_RCERE3_RCE1_SHIFT (0x00000001u) #define CSL_MCBSP_RCERE3_RCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE0_MASK (0x00000001u) #define CSL_MCBSP_RCERE3_RCE0_SHIFT (0x00000000u) #define CSL_MCBSP_RCERE3_RCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RESETVAL (0x00000000u) / XCERE3 */ #define CSL_MCBSP_XCERE3_XCE31_MASK (0x80000000u) #define CSL_MCBSP_XCERE3_XCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCERE3_XCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE30_MASK (0x40000000u) #define CSL_MCBSP_XCERE3_XCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_XCERE3_XCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE29_MASK (0x20000000u) #define CSL_MCBSP_XCERE3_XCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_XCERE3_XCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE28_MASK (0x10000000u) #define CSL_MCBSP_XCERE3_XCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_XCERE3_XCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE27_MASK (0x08000000u) #define CSL_MCBSP_XCERE3_XCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_XCERE3_XCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE26_MASK (0x04000000u) #define CSL_MCBSP_XCERE3_XCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_XCERE3_XCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE25_MASK (0x02000000u) #define CSL_MCBSP_XCERE3_XCE25_SHIFT (0x00000019u) #define CSL_MCBSP_XCERE3_XCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE24_MASK (0x01000000u) #define CSL_MCBSP_XCERE3_XCE24_SHIFT (0x00000018u) #define CSL_MCBSP_XCERE3_XCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE23_MASK (0x00800000u) #define CSL_MCBSP_XCERE3_XCE23_SHIFT (0x00000017u) #define CSL_MCBSP_XCERE3_XCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE22_MASK (0x00400000u) #define CSL_MCBSP_XCERE3_XCE22_SHIFT (0x00000016u) #define CSL_MCBSP_XCERE3_XCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE21_MASK (0x00200000u) #define CSL_MCBSP_XCERE3_XCE21_SHIFT (0x00000015u) #define CSL_MCBSP_XCERE3_XCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE20_MASK (0x00100000u) #define CSL_MCBSP_XCERE3_XCE20_SHIFT (0x00000014u) #define CSL_MCBSP_XCERE3_XCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE19_MASK (0x00080000u) #define CSL_MCBSP_XCERE3_XCE19_SHIFT (0x00000013u) #define CSL_MCBSP_XCERE3_XCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE18_MASK (0x00040000u) #define CSL_MCBSP_XCERE3_XCE18_SHIFT (0x00000012u) #define CSL_MCBSP_XCERE3_XCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE17_MASK (0x00020000u) #define CSL_MCBSP_XCERE3_XCE17_SHIFT (0x00000011u) #define CSL_MCBSP_XCERE3_XCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE16_MASK (0x00010000u) #define CSL_MCBSP_XCERE3_XCE16_SHIFT (0x00000010u) #define CSL_MCBSP_XCERE3_XCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE15_MASK (0x00008000u) #define CSL_MCBSP_XCERE3_XCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_XCERE3_XCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE14_MASK (0x00004000u) #define CSL_MCBSP_XCERE3_XCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_XCERE3_XCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE13_MASK (0x00002000u) #define CSL_MCBSP_XCERE3_XCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_XCERE3_XCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE12_MASK (0x00001000u) #define CSL_MCBSP_XCERE3_XCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_XCERE3_XCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE11_MASK (0x00000800u) #define CSL_MCBSP_XCERE3_XCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_XCERE3_XCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE10_MASK (0x00000400u) #define CSL_MCBSP_XCERE3_XCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_XCERE3_XCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE9_MASK (0x00000200u) #define CSL_MCBSP_XCERE3_XCE9_SHIFT (0x00000009u) #define CSL_MCBSP_XCERE3_XCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE8_MASK (0x00000100u) #define CSL_MCBSP_XCERE3_XCE8_SHIFT (0x00000008u) #define CSL_MCBSP_XCERE3_XCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE7_MASK (0x00000080u) #define CSL_MCBSP_XCERE3_XCE7_SHIFT (0x00000007u) #define CSL_MCBSP_XCERE3_XCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE6_MASK (0x00000040u) #define CSL_MCBSP_XCERE3_XCE6_SHIFT (0x00000006u) #define CSL_MCBSP_XCERE3_XCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE5_MASK (0x00000020u) #define CSL_MCBSP_XCERE3_XCE5_SHIFT (0x00000005u) #define CSL_MCBSP_XCERE3_XCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE4_MASK (0x00000010u) #define CSL_MCBSP_XCERE3_XCE4_SHIFT (0x00000004u) #define CSL_MCBSP_XCERE3_XCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE3_MASK (0x00000008u) #define CSL_MCBSP_XCERE3_XCE3_SHIFT (0x00000003u) #define CSL_MCBSP_XCERE3_XCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE2_MASK (0x00000004u) #define CSL_MCBSP_XCERE3_XCE2_SHIFT (0x00000002u) #define CSL_MCBSP_XCERE3_XCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE1_MASK (0x00000002u) #define CSL_MCBSP_XCERE3_XCE1_SHIFT (0x00000001u) #define CSL_MCBSP_XCERE3_XCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE0_MASK (0x00000001u) #define CSL_MCBSP_XCERE3_XCE0_SHIFT (0x00000000u) #define CSL_MCBSP_XCERE3_XCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_RESETVAL (0x00000000u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotHwSetup.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_memprotHwSetup.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotHwSetup () * / / ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * * 16-Nov-2005 ds Updated the documentation * ============================================================================= / #include <csl_memprot.h> #include <csl_memprotAux.h> /* ============================================================================ * @n@b CSL_memprotHwSetup * * @b Description * @n This function initializes the module registers with the appropriate * values provided through the HwSetup Data structure. * For information passed through the HwSetup Data structure refer * @a CSL_memprotHwSetup. * * @b Arguments * @verbatim hMemprot Handle to the memprot instance setup Pointer to harware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Hardware structure is not properly initialized * * <b> Pre Condition </b> * Both @a CSL_memprotInit() and @a CSL_memprotOpen() must be called * successfully in that order before this function can be called. The user * has to allocate space for & fill in the main setup structure appropriately * before calling this function. Ensure numpages is not set to > 32 for handles * for L1D/L1P. Ensure numpages is not > 64 for L2. * * <b> Post Condition </b> * @n 1. MEMPROT object structure is populated * @n 2. The status is returned in the status variable. If status * returned is * @li CSL_SOK Valid MEMPORT handle is returned * @li CSL_ESYS_INVPARAMS Invalid parameter * @li CSL_ESYS_BADHANDLE Invalid Handle * * @b Modifies * @n The hardware registers of MEMPORT. * * @b Example * @verbatim #define PAGE_ATTR 0xFFF0 CSL_MemprotObj mpL2Obj; CSL_MemprotHandle hmpL2; CSL_Status status; CSL_MemprotHwSetup L2MpSetup; Uint16 pageAttrTable[10] = {PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR, PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR}; Uint32 key[2] = {<KEY>}; // Initializing the module CSL_memprotInit(NULL); // Opening the Handle for the L2 hmpL2 = CSL_memprotOpen(&mpL2Obj, CSL_MEMPROT_L2, NULL, &status); L2MpSetup. memPageAttr = pageAttrTable; L2MpSetup.numPages = 10; L2MpSetup.key = key; // Do Setup for the L2 Memory protection/ CSL_memprotHwSetup (hmpL2, &L2MpSetup); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_memprotHwSetup, ".text:csl_section:memprot"); CSL_Status CSL_memprotHwSetup ( / Handle to the memprot instance / CSL_MemprotHandle hMemprot, / Pointer to setup structure which contains the * information to program the memory protection module to a useful state. / CSL_MemprotHwSetup setup ) { CSL_Status status = CSL_SOK; Uint16 i; if (hMemprot == NULL) { status = CSL_ESYS_BADHANDLE; } else if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Unlock the module. This call anyways checks if the module is already locked/not / if (setup->key != NULL) { CSL_memprotUnLock(hMemprot,setup->key); } / Program memory page attribute registers / for (i = 0;i < setup->numPages ;i++) { hMemprot->regs->MPPA[i] = setup->memPageAttr[i]; } / Lock Module */ if (setup->key != NULL) { status = CSL_memprotLock(hMemprot,setup->key); } } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaHwSetup.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaHwSetup.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_emifaHwSetup.c * * @path $(CSLPATH)\src\emifa * * @desc File for functional layer of CSL API @a CSL_emifaHwSetup() * - The @a CSL_emifaHwSetup() function definition & it's associated * functions * / / ============================================================================= * Revision History * =============== * 12-May-2005 RM File Created. * * 08-Jul-2005 RM Changes made in accordance to the change in cslr_emifa.h * * 09-Sep-2005 NG Updation according to coding guidelines * * ============================================================================= / #include <csl_emifa.h> /* ============================================================================ * @n@b CSL_emifaHwSetup * * @b Description * @n This function initializes the device registers with the appropriate values * provided through the HwSetup data structure. For information passed through * the HwSetup data structure refer @a CSL_EmifaHwSetup. * * @b Arguments * @verbatim hEmifa Pointer to the object that holds reference to the instance of EMIFA requested after the call setup Pointer to setup structure which contains the information to program EMIFA to a useful state @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - configuration successful * @li CSL_ESYS_FAIL - The external memory interface * instance is not available. * @li CSL_ESYS_INVPARAMS - Parameters are not valid * @li CSL_ESYS_BADHANDLE - Handle is not valid * * <b> Pre Condition </b> * @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called * successfully in order before calling this function. The user has to * allocate space for & fill in the main setup structure appropriately * before calling this function. * * <b> Post Condition </b> * @n EMIFA registers are configured according to the hardware setup parameters * * @b Modifies * @n EMIFA registers * * @b Example: * @verbatim CSL_EmifaHandle hEmifa; CSL_EmifaAsync asyncMem = CSL_EMIFA_ASYNCCFG_DEFAULTS; CSL_EmifaAsyncWait asyncWait = CSL_EMIFA_ASYNCWAIT_DEFAULTS; CSL_EmifaMemType value; CSL_EmifaHwSetup hwSetup ; value.ssel = 0; value.async = &asyncMem; value.sync = NULL; hwSetup.asyncWait = &asyncMem; hwSetup.cefg [0] = &value; hwSetup.ceCfg [1] = NULL; hwSetup.ceCfg [2] = NULL; hwSetup.ceCfg [3] = NULL; //Initialize the Emifa CSL //Open Emifa Module CSL_emifaHwSetup(hEmifa, &hwSetup); @endverbatim * * ============================================================================ / #pragma CODE_SECTION (CSL_emifaHwSetup, ".text:csl_section:emifa"); CSL_Status CSL_emifaHwSetup( CSL_EmifaHandle hEmifa, CSL_EmifaHwSetup setup ) { CSL_Status status = CSL_SOK; Uint32 mask, mask1, mask2; Uint8 loop; volatile Uint32 ceCfgBaseAddr = 0; / invalid parameter checking / if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else if (hEmifa == NULL) { / bad handle checking / status = CSL_ESYS_BADHANDLE; } else { if (setup->asyncWait != NULL) { mask = ~((CSL_EMIFA_AWCC_AP_MASK) \|(CSL_EMIFA_AWCC_TA_MASK) \| (CSL_EMIFA_AWCC_MAX_EXT_WAIT_MASK)); hEmifa->regs->AWCC = (hEmifa->regs->AWCC & mask) \| (CSL_FMK(EMIFA_AWCC_AP, setup->asyncWait->asyncRdyPol)) \| (CSL_FMK(EMIFA_AWCC_TA, setup->asyncWait->turnArnd)) \| (CSL_FMK(EMIFA_AWCC_MAX_EXT_WAIT, setup->asyncWait->maxExtWait)); } / Configuring chip selects for synchronous or Asynchronous memory / ceCfgBaseAddr = &(hEmifa->regs->CE2CFG); mask1 = ~((CSL_EMIFA_CE2CFG_SS_MASK) \| (CSL_EMIFA_CE2CFG_BWEM_MASK) \| (CSL_EMIFA_CE2CFG_AE_MASK) \| (CSL_EMIFA_CE2CFG_W_SETUP_MASK) \| (CSL_EMIFA_CE2CFG_W_STROBE_MASK) \| (CSL_EMIFA_CE2CFG_W_HOLD_MASK) \| (CSL_EMIFA_CE2CFG_R_SETUP_MASK) \| (CSL_EMIFA_CE2CFG_R_STROBE_MASK) \| (CSL_EMIFA_CE2CFG_R_HOLD_MASK) \| (CSL_EMIFA_CE2CFG_ASIZE_MASK)); mask2 = ~((CSL_EMIFA_CE2CFG_RD_BE_EN_MASK) \| (CSL_EMIFA_CE2CFG_CE_EXT_MASK) \| (CSL_EMIFA_CE2CFG_R_ENABLE_MASK) \| (CSL_EMIFA_CE2CFG_W_LTNCY_MASK) \| (CSL_EMIFA_CE2CFG_R_LTNCY_MASK) \| (CSL_EMIFA_CE2CFG_SBSIZE_MASK)); for (loop = 0; loop < NUMCHIPENABLE; loop++) { if (setup->ceCfg[loop] != NULL) { if ((setup->ceCfg[loop]->ssel == 0) && (setup->ceCfg[loop]->async != NULL)) { CSL_FINS((ceCfgBaseAddr + loop), EMIFA_CE2CFG_SSEL, CSL_EMIFA_CE2CFG_SSEL_ASYNCMEM); (ceCfgBaseAddr + loop) = ((ceCfgBaseAddr + loop) & mask1) \| (CSL_FMK(EMIFA_CE2CFG_SS, setup->ceCfg[loop]->async->selectStrobe)) \| (CSL_FMK(EMIFA_CE2CFG_BWEM, setup->ceCfg[loop]->async->weMode)) \| (CSL_FMK(EMIFA_CE2CFG_AE, setup->ceCfg[loop]->async->asyncRdyEn)) \| (CSL_FMK(EMIFA_CE2CFG_W_SETUP, setup->ceCfg[loop]->async->wSetup)) \| (CSL_FMK(EMIFA_CE2CFG_W_STROBE, setup->ceCfg[loop]->async->wStrobe)) \| (CSL_FMK(EMIFA_CE2CFG_W_HOLD, setup->ceCfg[loop]->async->wHold)) \| (CSL_FMK(EMIFA_CE2CFG_R_SETUP, setup->ceCfg[loop]->async->rSetup)) \| (CSL_FMK(EMIFA_CE2CFG_R_STROBE, setup->ceCfg[loop]->async->rStrobe)) \| (CSL_FMK(EMIFA_CE2CFG_R_HOLD, setup->ceCfg[loop]->async->rHold)) \| (CSL_FMK(EMIFA_CE2CFG_ASIZE, setup->ceCfg[loop]->async->asize)); } else { if ((setup->ceCfg[loop]->ssel == 1) && (setup->ceCfg[loop]->sync != NULL)) { CSL_FINS((ceCfgBaseAddr + loop), EMIFA_CE2CFG_SSEL, CSL_EMIFA_CE2CFG_SSEL_SYNCMEM); (ceCfgBaseAddr + loop) = (*(ceCfgBaseAddr + loop) & mask2)\| (CSL_FMK(EMIFA_CE2CFG_RD_BE_EN, setup->ceCfg[loop]->sync->readByteEn)) \| (CSL_FMK(EMIFA_CE2CFG_CE_EXT, setup->ceCfg[loop]->sync->chipEnExt)) \| (CSL_FMK(EMIFA_CE2CFG_R_ENABLE, setup->ceCfg[loop]->sync->readEn)) \| (CSL_FMK(EMIFA_CE2CFG_W_LTNCY, setup->ceCfg[loop]->sync->w_ltncy)) \| (CSL_FMK(EMIFA_CE2CFG_R_LTNCY, setup->ceCfg[loop]->sync->r_ltncy)) \| (CSL_FMK(EMIFA_CE2CFG_SBSIZE, setup->ceCfg[loop]->sync->sbsize)); } else { status = CSL_ESYS_FAIL; } } } } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_hpi.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_hpi.h * * @path $(CSLPATH)\inc * * @brief HPI functional layer API header file * / /* * @mainpage HPI CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the HPI module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given HPI module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular HPI Module. The CSL developer should use his discretion designing * new APIs or extending the existing ones to cover these. * * @subsection Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 * / / ============================================================================= * Revision History * =============== * 06-Feb-2006 ds Removed CSL_HPI_QUERY_PID_REV, CSL_HPI_QUERY_PID_TYPE and * CSL_HPI_QUERY_PID_CLASS from the CSL_HpiHwStatusQuery * * ============================================================================= / #ifndef _CSL_HPI_H_ #define _CSL_HPI_H_ #ifdef __cplusplus extern "C" { #endif #include <cslr.h> #include <soc.h> #include <csl_error.h> #include <csl_types.h> #include <csl.h> #include <cslr_hpi.h> /* * @brief Enumeration for queries passed to @a CSL_hpiGetHwStatus() * * This is used to get the status of different operations / typedef enum { CSL_HPI_QUERY_HRDY = 1, /< @brief Query the current value of Host Fetch * @param (Uint32 ) / CSL_HPI_QUERY_FETCH = 2, /*< @brief Query the current value of HPI Reset * @param (Uint32 ) / CSL_HPI_QUERY_HPI_RST = 3, /*< @brief Query the current value of Half-word ordering status * @param (Uint32 ) / CSL_HPI_QUERY_HWOB_STAT = 4 } CSL_HpiHwStatusQuery; /** * @brief Enumeration for commands passed to @a CSL_hpiHwControl() * * This is used to select the commands to control the operations * existing setup of HPI. The arguments to be passed with each * enumeration if any are specified next to the enumeration. / typedef enum { /< @brief Sets the HPIC Host-to-DSP Interrupt. * @param (None) / CSL_HPI_CMD_SET_DSP_INT = 0, /< @brief Reset the HPIC Host-to-DSP Interrupt. * @param (None) / CSL_HPI_CMD_RESET_DSP_INT = 1, /< @brief Set the HPIC DSP-to-Host Interrupt. * @param (None) / CSL_HPI_CMD_SET_HINT = 2, /< @brief Reset the HPIC DSP-to-Host Interrupt. * @param (None) / CSL_HPI_CMD_RESET_HINT = 3 } CSL_HpiHwControlCmd; /* @brief Structure configures Host Port Interface Write & Read Address / typedef struct { /* Host Port Interface Write Address / Uint32 hpiaWrtAddr; /* Host Port Interface Read Address / Uint32 hpiaReadAddr; } CSL_HpiAddrCfg; /* @brief Enumation for the control commands of HPI. / typedef enum { /* Half-word Ordering Bit / CSL_HPI_HWOB = 0x1, /* Host-to-DSP Interrupt / CSL_HPI_DSP_INT = 0x2, /* DSP-to-Host Interrupt / CSL_HPI_HINT = 0x4, /* Host Ready / CSL_HPI_HRDY = 0x8, /* Host Fetch / CSL_HPI_FETCH = 0x10, /* CPU Core Reset / CSL_HPI_RESET = 0x40, /* HPI Reset / CSL_HPI_HPI_RST = 0x80, /* Half-word ordering bit status / CSL_HPI_HWOB_STAT = 0x100, /* Dual HPIA mode configuration bit / CSL_HPI_DUAL_HPIA = 0x200, /* HPIA register select bit / CSL_HPI_HPIA_RW_SEL = 0x800 } CSL_HpiCtrl; /* @brief The structure contains the HPI hardware setup / typedef struct { /* Host port Interface control Register / CSL_HpiCtrl hpiCtrl; /* Host port Interface Read & Write Address Register / CSL_HpiAddrCfg hpiAddr; /* Emulation Mode parameter / Uint32 emu; } CSL_HpiHwSetup; /* @brief The configuration structure which is to configure HPI. / typedef struct { /* Power and Emulation Management Register / volatile Uint32 PWREMU_MGMT; /* Host Port Interface Control Register / volatile Uint32 HPIC; /* Host Port Interface Write Address Register / volatile Uint32 HPIAW; /* Host Port Interface Read Address Register / volatile Uint32 HPIAR; } CSL_HpiConfig; /* Default Values for Config structure / #define CSL_HPI_CONFIG_DEFAULTS { \ CSL_HPI_PWREMU_MGMT_RESETVAL, \ CSL_HPI_HPIC_RESETVAL, \ CSL_HPI_HPIAW_RESETVAL, \ CSL_HPI_HPIAR_RESETVAL \ } /* @brief HPI specific context information. Present implementation of HPI * CSL doesn't have any context information. / typedef struct { /* Context information of HPI CSL. * The below declaration is just a place-holder for future implementation. / Uint32 contextInfo; } CSL_HpiContext; /* @brief HPI specific parameters. Present implementation of HPI CSL * doesn't have any module specific parameters. / typedef struct { /* Bit mask to be used for module specific parameters. The below * declaration is just a place-holder for future implementation. / CSL_BitMask32 flags; } CSL_HpiParam; /* @brief This structure contains the base-address information for the * peripheral instance of the HPI / typedef struct { /* Base-address of the configuration registers of the peripheral / CSL_HpiRegsOvly regs; } CSL_HpiBaseAddress; /* @brief This structure/object holds the context of the instance of HPI * opened using CSL_hpiOpen() function. Pointer to this object is * passed as HPI Handle to all HPI CSL APIs. CSL_hpiOpen() function * initializes this structure based on the parameters passed / typedef struct CSL_HpiObj{ /* Pointer to the register overlay structure of the hpi / CSL_HpiRegsOvly regs; /* Instance of hpi being referred by this object / CSL_InstNum hpiNum; } CSL_HpiObj; /* @brief This data type is used to return the handle to the CSL of the HPI / typedef struct CSL_HpiObj CSL_HpiHandle; /******************************************************************************* * DSP HPI controller function declarations ****************************************************************************/ / ============================================================================ * @n@b CSL_hpiInit * * @b Description * @n This is the initialization function for the hpi CSL. The function * must be called before calling any other API from this CSL. This * function is idem-potent. Currently, the function just return status * CSL_SOK, without doing anything. * * @b Arguments * @verbatim pContext Pointer to module-context. As HPI doesn't have any context based information user is expected to pass NULL. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Status status; ... status = CSL_hpiInit(NULL); ... @endverbatim * ============================================================================= / extern CSL_Status CSL_hpiInit ( CSL_HpiContext pContext ); /** ============================================================================ * @n@b CSL_hpiOpen * * @b Description * @n This function returns the handle to the HPI controller * instance. This handle is passed to all other CSL APIs. * * @b Arguments * @verbatim hpiObj Pointer to the object that holds reference to the instance of HPI requested after the call. hpiNum Instance of HPI to which a handle is requested. There is only one instance of the hpi available. So, the value for this parameter will be CSL_HPI always. pHpiParam Module specific parameters. status Status of the function call @endverbatim * * <b> Return Value </b> CSL_HpiHandle * @n Valid HPI handle will be returned if * status value is equal to CSL_SOK. * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n 1. The status is returned in the status variable. If status * returned is * @li CSL_SOK - Valid HPI handle is returned * @li CSL_ESYS_FAIL - The HPI instance is invalid * @li CSL_ESYS_INVPARAMS - Invalid parameter * * 2. HPI object structure is populated * * @b Modifies * @n 1. The status variable * * 2. HPI object structure * * @b Example * @verbatim CSL_status status; CSL_HpiObj hpiObj; CSL_HpiHandle hHpi; ... hHpi = CSL_hpiOpen(&hpiObj, CSL_HPI, NULL, &status); ... @endverbatim * ============================================================================= / extern CSL_HpiHandle CSL_hpiOpen ( CSL_HpiObj hpiObj, CSL_InstNum hpiNum, CSL_HpiParam pHpiParam, CSL_Status status ); /** ============================================================================ * @n@b CSL_hpiGetBaseAddress * * @b Description * @n Function to get the base address of the peripheral instance. * This function is used for getting the base address of the peripheral * instance. This function will be called inside the CSL_hpiOpen() * function call. This function is open for re-implementing if the user * wants to modify the base address of the peripheral object to point to * a different location and there by allow CSL initiated write/reads into * peripheral. MMR's go to an alternate location. * * @b Arguments * @verbatim hpiNum Specifies the instance of the hpi to be opened. pHpiParam Module specific parameters. pBaseAddress Pointer to base address structure containing base address details. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_OK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * @li CSL_ESYS_INVPARAMS Invalid parameter * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Base address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_HpiBaseAddress baseAddress; ... status = CSL_hpiGetBaseAddress(CSL_HPI, NULL, &baseAddress); ... @endverbatim * =========================================================================== / extern CSL_Status CSL_hpiGetBaseAddress ( CSL_InstNum hpiNum, CSL_HpiParam pHpiParam, CSL_HpiBaseAddress pBaseAddress ); /* ============================================================================ * @n@b CSL_hpiClose * * @b Description * @n This function closes the specified instance of HPI. * * @b Arguments * @verbatim hHpi Handle to the HPI @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Close successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * <b> Pre Condition </b> * @n The HPI instance should be opened before this close operation. * * <b> Post Condition </b> * @n The HPI CSL APIs can not be called until the HPI CSL is reopened * again using CSL_hpiOpen(). * * @b Modifies * @n None * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_Status status; ... status = CSL_hpiClose(hHpi); @endverbatim * =========================================================================== / extern CSL_Status CSL_hpiClose ( CSL_HpiHandle hHpi ); /* ============================================================================ * @n@b CSL_hpiHwSetup * * @b Description * @n It configures the hpi registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim hHpi Handle to the hpi hwSetup Pointer to harware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup successful * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVPARAMS - The parameter passed is * invalid * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n HPI registers are configured according to the hardware setup * parameters. * * @b Modifies * @n HPI registers * * @b Example * @verbatim CSL_status status; CSL_HpiHwSetup myHwSetup; CSL_HpiHandle hHpi; myHwSetup.HPIC = hwSetup->hpiCtrl; ..... status = CSL_hpiHwSetup(hHpi, &hwSetup); @endverbatim * =========================================================================== / extern CSL_Status CSL_hpiHwSetup ( CSL_HpiHandle hHpi, CSL_HpiHwSetup hwSetup ); /** ============================================================================ * @n@b CSL_hpiHwControl * * @b Description * @n This function takes an input control command with an optional argument * and accordingly controls the operation/configuration of HPI. * * @b Arguments * @verbatim hHpi Handle to the HPI instance cmd The command to this API indicates the action to be taken on HPI. arg An optional argument. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Command successful. * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order * before calling CSL_hpiHwControl(). * * <b> Post Condition </b> * @n HPI registers are configured according to the command passed. * * @b Modifies * @n The hardware registers of HPI. * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_HpiHwControlCmd cmd; void arg; status = CSL_hpiHwControl(hHpi, cmd, &arg); @endverbatim * ============================================================================= / extern CSL_Status CSL_hpiHwControl ( CSL_HpiHandle hHpi, CSL_HpiHwControlCmd cmd, void arg ); /** ============================================================================ * @n@b CSL_hpiGetHwStatus * * @b Description * @n Gets the status of the different operations of HPI. * * @b Arguments * @verbatim hHpi Handle to the HPI instance query The query to this API of HPI which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Query successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVQUERY - The Query passed is invalid * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order * before calling CSL_hpiGetHwStatus(). * * <b> Post Condition </b> * @n None * * @b Modifies * @n Third parameter response vlaue * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_HpiHwStatusQuery query; void reponse; status = CSL_hpiGetHwStatus(hHpi, query, &response); @endverbatim * ============================================================================= / extern CSL_Status CSL_hpiGetHwStatus ( CSL_HpiHandle hHpi, CSL_HpiHwStatusQuery query, void response ); /** ============================================================================ * @n@b CSL_hpiHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hHpi Handle to the HPI instance config Pointer to Config structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not properly initialized * <b> Pre Condition </b> * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in * order before calling CSL_hpiGetHwSetupRaw(). * * <b> Post Condition </b> * @n The registers of the specified HPI instance will be setup * according to input configuration structure values. * * @b Modifies * @n Hardware registers of the specified HPI instance. * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_HpiConfig config = CSL_HPI_CONFIG_DEFAULTS; CSL_Status status; status = CSL_hpiHwSetupRaw(hHpi, &config); @endverbatim * ============================================================================= / extern CSL_Status CSL_hpiHwSetupRaw ( CSL_HpiHandle hHpi, CSL_HpiConfig config ); /** ============================================================================ * @n@b CSL_hpiGetHwSetup * * @b Description * @n It retrives the hardware setup parameters of the hpi * specified by the given handle. * * @b Arguments * @verbatim hHpi Handle to the hpi hwSetup Pointer to the harware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Retrieving the hardware setup * parameters is successful * @li CSL_ESYS_BADHANDLE - The handle is passed is * invalid * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order * before calling CSL_hpiGetHwSetup(). * * <b> Post Condition </b> * @n The hardware setup structure is populated with the hardware setup * parameters * * @b Modifies * @n hwSetup variable * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_HpiHwSetup hwSetup; ... status = CSL_hpiGetHwSetup(hHpi, &hwSetup); ... @endverbatim * =========================================================================== / extern CSL_Status CSL_hpiGetHwSetup( CSL_HpiHandle hHpi, CSL_HpiHwSetup hwSetup ); #ifdef __cplusplus } #endif #endif /* _CSL_HPI_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_hpi.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_hpi.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for HPI / #ifndef _CSLR_HPI_H_ #define _CSLR_HPI_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint8 RSVD0[4]; volatile Uint32 PWREMU_MGMT; volatile Uint8 RSVD1[40]; volatile Uint32 HPIC; volatile Uint32 HPIAW; volatile Uint32 HPIAR; } CSL_HpiRegs; /***********************************************************************\ Overlay structure typedef definition \*************************************************************************/ typedef volatile CSL_HpiRegs CSL_HpiRegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / PWREMU_MGMT / #define CSL_HPI_PWREMU_MGMT_SOFT_MASK (0x00000002u) #define CSL_HPI_PWREMU_MGMT_SOFT_SHIFT (0x00000001u) #define CSL_HPI_PWREMU_MGMT_SOFT_RESETVAL (0x00000000u) /----SOFT Tokens----/ #define CSL_HPI_PWREMU_MGMT_SOFT_OFF (0x00000000u) #define CSL_HPI_PWREMU_MGMT_SOFT_ON (0x00000001u) #define CSL_HPI_PWREMU_MGMT_FREE_MASK (0x00000001u) #define CSL_HPI_PWREMU_MGMT_FREE_SHIFT (0x00000000u) #define CSL_HPI_PWREMU_MGMT_FREE_RESETVAL (0x00000000u) /----FREE Tokens----/ #define CSL_HPI_PWREMU_MGMT_FREE_OFF (0x00000000u) #define CSL_HPI_PWREMU_MGMT_FREE_ON (0x00000001u) #define CSL_HPI_PWREMU_MGMT_RESETVAL (0x00000000u) / HPIC / #define CSL_HPI_HPIC_HPIARWSEL_MASK (0x00000800u) #define CSL_HPI_HPIC_HPIARWSEL_SHIFT (0x0000000Bu) #define CSL_HPI_HPIC_HPIARWSEL_RESETVAL (0x00000000u) /----HPIARWSEL Tokens----/ #define CSL_HPI_HPIC_HPIARWSEL_HPIA_R (0x00000000u) #define CSL_HPI_HPIC_HPIARWSEL_HPIA_W (0x00000001u) #define CSL_HPI_HPIC_DUALHPIA_MASK (0x00000200u) #define CSL_HPI_HPIC_DUALHPIA_SHIFT (0x00000009u) #define CSL_HPI_HPIC_DUALHPIA_RESETVAL (0x00000000u) /----DUALHPIA Tokens----/ #define CSL_HPI_HPIC_DUALHPIA_DISABLE (0x00000000u) #define CSL_HPI_HPIC_DUALHPIA_ENABLE (0x00000001u) #define CSL_HPI_HPIC_HWOBSTAT_MASK (0x00000100u) #define CSL_HPI_HPIC_HWOBSTAT_SHIFT (0x00000008u) #define CSL_HPI_HPIC_HWOBSTAT_RESETVAL (0x00000000u) #define CSL_HPI_HPIC_HPIRST_MASK (0x00000080u) #define CSL_HPI_HPIC_HPIRST_SHIFT (0x00000007u) #define CSL_HPI_HPIC_HPIRST_RESETVAL (0x00000001u) #define CSL_HPI_HPIC_FETCH_MASK (0x00000010u) #define CSL_HPI_HPIC_FETCH_SHIFT (0x00000004u) #define CSL_HPI_HPIC_FETCH_RESETVAL (0x00000000u) #define CSL_HPI_HPIC_HRDY_MASK (0x00000008u) #define CSL_HPI_HPIC_HRDY_SHIFT (0x00000003u) #define CSL_HPI_HPIC_HRDY_RESETVAL (0x00000000u) #define CSL_HPI_HPIC_HINT_MASK (0x00000004u) #define CSL_HPI_HPIC_HINT_SHIFT (0x00000002u) #define CSL_HPI_HPIC_HINT_RESETVAL (0x00000000u) /----HINT Tokens----/ #define CSL_HPI_HPIC_HINT_DISABLE (0x00000001u) #define CSL_HPI_HPIC_HINT_ENABLE (0x00000001u) #define CSL_HPI_HPIC_DSPINT_MASK (0x00000002u) #define CSL_HPI_HPIC_DSPINT_SHIFT (0x00000001u) #define CSL_HPI_HPIC_DSPINT_RESETVAL (0x00000000u) /----DSPINT Tokens----/ #define CSL_HPI_HPIC_DSPINT_DISABLE (0x00000000u) #define CSL_HPI_HPIC_DSPINT_ENABLE (0x00000001u) #define CSL_HPI_HPIC_HWOB_MASK (0x00000001u) #define CSL_HPI_HPIC_HWOB_SHIFT (0x00000000u) #define CSL_HPI_HPIC_HWOB_RESETVAL (0x00000000u) /----HWOB Tokens----/ #define CSL_HPI_HPIC_HWOB_DISABLE (0x00000000u) #define CSL_HPI_HPIC_HWOB_ENABLE (0x00000001u) #define CSL_HPI_HPIC_RESETVAL (0x00000080u) / HPIAW / #define CSL_HPI_HPIAW_HPIAW_MASK (0xFFFFFFFFu) #define CSL_HPI_HPIAW_HPIAW_SHIFT (0x00000000u) #define CSL_HPI_HPIAW_HPIAW_RESETVAL (0x00000000u) #define CSL_HPI_HPIAW_RESETVAL (0x00000000u) / HPIAR */ #define CSL_HPI_HPIAR_HPIAR_MASK (0xFFFFFFFFu) #define CSL_HPI_HPIAR_HPIAR_SHIFT (0x00000000u) #define CSL_HPI_HPIAR_HPIAR_RESETVAL (0x00000000u) #define CSL_HPI_HPIAR_RESETVAL (0x00000000u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcClose.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* @file csl_pllcClose.c * * @brief File for functional layer of CSL API @a CSL_pllcClose() * * @path \(CSLPATH)\src\pllc * / / ============================================================================ * Revision History * =============== * 10-Feb-2004 kpn CSL3X Upgradation. * ============================================================================ / #include <csl_pllc.h> /* ============================================================================ * @n@b CSL_pllcClose * * @b Description * @n This function closes the specified instance of PLLC. * * @b Arguments * @verbatim hPllc Handle to the pllc @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Close successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n 1. PLLC instance is closed and its usage is * illegal until next open * * * @b Modifies * @n 1. PLLC object structure * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_status status; ... status = CSL_pllcClose(hPllc); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_pllcClose, ".text:csl_section:pllc"); CSL_Status CSL_pllcClose ( CSL_PllcHandle hPllc ) { CSL_Status status; if (hPllc != NULL) { hPllc->regs = (CSL_PllcRegsOvly)NULL; hPllc->pllcNum = (CSL_InstNum)-1; status = CSL_SOK; } else { status = CSL_ESYS_BADHANDLE; } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/edma/edma_sub_frame_xfer/src/Edma_sub_frame_xfer.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * * @file Edma_sub_frame_xfer.c * * @path $(CSLPATH)\example\edma\edma_sub_frame_xfer\src * * @desc Example of EDMA * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @n This illustrates Edma Sub frame transfer * This example do the following operations * - Initializes and Opens the edma module * - Sets up the Module * - Enables (Bits 0-15) the Shadow Region 0 * - Opens Channel 0 in context of Shadow region 0 * - Obtains a handles to parameters set 0 * - Sets up the param set * - Enables Channel and Initialize the data * - Manually triggers the Channel * - Polls on interrupt bit 0 and clears interrupt bit 0 * - Compares the transfered data * - Displays the result based on previous step * * ============================================================================= * * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Edma_sub_frame_xfer.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================= * Revision History * =============== * 08-Feb-2006 ds File Created. * * ============================================================================= / #include <stdio.h> #include <csl_edma3.h> #include <soc.h> / Number of bytes to transfer / #define NOF_BYTES_XFR 512 / Globals / Uint8 srcBuff1[NOF_BYTES_XFR]; Uint8 dstBuff1[NOF_BYTES_XFR]; Uint32 passStatus = 1; / Forward declaration / void edma_sub_frame_xfer (void); / * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= / void main(void) { / Invoke example / edma_sub_frame_xfer (); return; } / * ============================================================================= * @func edma_sub_frame_xfer * * @arg * NONE * * @desc * This is the example routine which perform edma sub frame transfer * It implements following steps * - Initializes and Opens the edma module * - Sets up the Module * - Enables (Bits 0-15) the Shadow Region 0 * - Opens Channel 0 in context of Shadow region 0 * - Obtains a handles to parameters set 0 * - Sets up the param set * - Enables Channel and Initialize the data * - Manually triggers the Channel * - Polls on interrupt bit 0 and clears interrupt bit 0 * - Compares the transfered data * - Displays the result based on previous step * * @return * NONE * * ============================================================================= / void edma_sub_frame_xfer (void) { CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ChannelObj chObj; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Status status; CSL_Edma3HwDmaChannelSetup dmahwSetup; volatile Uint32 loopIndex; printf ("Running Edma Example\n"); / Module Initialization / status = CSL_edma3Init(&context); if (status != CSL_SOK) { printf ("Edma module initialization failed\n"); return; } / Module level open / hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); if ( (hModule == NULL) \|\| (status != CSL_SOK)) { printf ("Edma module open failed\n"); return; } / Module setup / dmahwSetup.paramNum = 0; dmahwSetup.que = CSL_EDMA3_QUE_0; hwSetup.dmaChaSetup = &dmahwSetup; hwSetup.qdmaChaSetup = NULL; status = CSL_edma3HwSetup(hModule,&hwSetup); if (status != CSL_SOK) { printf ("Hardware setup failed\n"); CSL_edma3Close (hModule); return; } / DRAE enable(Bits 0-15) for the shadow region 5 / regionAccess.region = CSL_EDMA3_REGION_5 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); if (status != CSL_SOK) { printf ("Edma region enable command failed\n"); return; } / Channel 0 open in context of shadow region 5 / chAttr.regionNum = CSL_EDMA3_REGION_5; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); if ((hChannel == NULL) \|\| (status != CSL_SOK)) { printf ("Edma channel open failed\n"); return; } / Obtain a handle to parameter set 0 / hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); if (hParamBasic == NULL) { printf ("Edma get param handle for param entry 0 failed\n"); return; } / Setup the first param set / myParamSetup.option = CSL_EDMA3_OPT_MAKE (CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 0, CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_EN, \ CSL_EDMA3_SYNC_AB, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR ); myParamSetup.srcAddr = (Uint32)srcBuff1; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(20,12); myParamSetup.dstAddr = (Uint32)dstBuff1; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(40,20); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, 1); myParamSetup.cCnt = 1; status = CSL_edma3ParamSetup(hParamBasic, &myParamSetup); if (status != CSL_SOK) { printf("Edma parameter entry setup is failed\n"); return; } / Enable channel / status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \ NULL); if (status != CSL_SOK) { printf("Edma channel enable command is failed\n"); return; } / Initialize data / for (loopIndex = 0; loopIndex < 41; loopIndex++) { srcBuff1[loopIndex] = loopIndex; dstBuff1[loopIndex] = 0; } for (loopIndex = 41; loopIndex < NOF_BYTES_XFR; loopIndex++) { srcBuff1[loopIndex] = loopIndex + 12; dstBuff1[loopIndex] = 0; } / Manually trigger the channel / status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL); if (status != CSL_SOK) { printf("Edma channel set command is failed\n"); return; } regionIntr.region = CSL_EDMA3_REGION_5; regionIntr.intr = 0; regionIntr.intrh = 0; do { / Poll on interrupt bit 0 / CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr); } while (!(regionIntr.intr & 0x1)); / Clear interrupt bit 0 / status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \ &regionIntr); if (status != CSL_SOK) { printf("Edma clear interrupt bit 0 command is failed\n"); return; } / Check transfer / if(Verify_Transfer(20, 12, 1, 40, 20, 0, 0, srcBuff1, dstBuff1,TRUE) == FALSE) { passStatus = 0; } if (passStatus == 1) printf ("<<EXAMPLE PASSED>>: Edma Sub Frame Transfer Passed\n"); else { printf ("<<EXAMPLE FAILED>>: Edma Sub Frame Buffer Transfer Failed\n"); return; } / Close channel / status = CSL_edma3ChannelClose(hChannel); if (status != CSL_SOK) { printf("Edma channel close failed\n"); return; } / Close edma module */ status = CSL_edma3Close(hModule); if (status != CSL_SOK) { printf("Edma module close failed\n"); return; } printf ("=============================================================\n"); return; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example2/src/Intc_example2.c	<filename>DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example2/src/Intc_example2.c /* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ========================================================================== / /* =========================================================================== * @file Intc_example2.c * * @path $(CSLPATH)\c64plus\example\intc * * @desc Example of INTC * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @n This example demonstrating usage of the combiners in the Interrupt * controller with the help of the the timers. This example, * 1. Intializes Intc module * 2. Opens a handle for the Timer 0 onto CPU vector 12 * 3. Plugs timer event handler and enables the event * 4. Intializes and opens the timer module * 5. Sets up and starts the timer * 6. Wait for interrupt genaration, (count to become 20) * 7. Disables the timer event * 8. Close the Intc module * 9. Opens the combined event on CPU vector 12 * 10. Opens the timer event on the combiner vector * CSL_INTC_VECTID_COMBINE * 11. Enables the combined and timer events * 12. Waits for interrupt genaration, (count to become 20) * 13. Disables the timer and combined events * 14. Enable the timer and combined events * 15. Wait for interrupt genaration, (count to become 20) * 16. Displays the message * * ============================================================================= * * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Intc_example2.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================ * Revision History * =============== * 29-Jun-2004 <NAME> File Created. * * 04-Aug-2005 ds Changed to support timer CSL * 11-Nov-2005 ds Changed to add powersaver clock for timer * 16-Dec-2005 ds Updated documentation * 28-Mar-2006 ds Added code to clear all the evnts * ============================================================================ / #include <csl_intc.h> #include <csl_intcAux.h> #include <csl_tmr.h> #include <cslr_dev.h> #include <stdio.h> / Intc variables decalarations / CSL_IntcObj intcTimerObj; CSL_IntcObj intcCombObj; CSL_IntcHandle hIntcTimer; CSL_IntcHandle hIntcComb; CSL_IntcGlobalEnableState state; CSL_IntcEventHandlerRecord EventRecord; CSL_IntcParam vectId; CSL_IntcContext context; CSL_IntcEventHandlerRecord Record[1]; CSL_IntcEventHandlerRecord EventHandler[30]; / Function forwards / void eventTimerHandler(void handle); void intc_example (void); /* Global variable declarations / volatile int intrCnt=0; / * ============================================================================ * @func main * * @desc * This is the main routine, which invokes the example * ============================================================================ / void main(void) { Bool timer0En; printf ("Running Interrupt Example\n"); / Unlock the control register / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the Powersaver clock for TIMER 0 / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER0CTL, ENABLE); do { timer0En = (Bool) CSL_FEXT(((CSL_DevRegs)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TIMER0STAT); } while (timer0En != TRUE); printf("Powersaver clock for TIMER 0 is enabled\n"); intc_example (); return; } / * ============================================================================= * @func intc_example * * @arg None * * @desc * This is the example for combiners in the interrupt comtroller. * It implements following steps * 1. Initalizes the intc CSL required with proper ISR * 2. Intializes Timer. * 3. Enables the timer event * 4. Waits for timer interrupt generate. * 5. Disables the timer event * 6. Closes the Intc module * 7. Opens the combined event on CPU vector 12 * 8. Opens the timer event on the combiner vector * CSL_INTC_VECTID_COMBINE * 9. Enables the combined and timer events * 10. Waits for interrupt genaration, (count to become 20) * 11. Disables the timer and combined events * 12. Enables the timer and combined events * 13. Waits for interrupt genaration, (count to become 20) * 14. Closes the timer module * 15. Closes the Intc module * * @return * None * * @eg * intc_example (); * ============================================================================= / void intc_example (void) { CSL_TmrHandle hTmr; CSL_TmrObj TmrObj; CSL_Status status, intStat; CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS; CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_CONT; volatile Uint32 delay; Uint32 LoadValue = 100; Uint32 evtClr; Uint32 idx; CSL_BitMask32 evtEn; printf ("Demonstrating usage of the combiners in the Intc\n"); / Init the interrupt controller initializes the CPU vector table, * dispatcher / context.numEvtEntries = 1; context.eventhandlerRecord = Record; status = CSL_intcInit(&context); if (status != CSL_SOK) { printf("Intc initialization failed\n"); return; } / Enable NMIs / status = CSL_intcGlobalNmiEnable(); if (status != CSL_SOK) { printf("Intc global NMI enable failed\n"); return; } / Enable global interrupts / intStat = CSL_intcGlobalEnable(&state); if (intStat != CSL_SOK) { printf ("Intc global enable failed\n"); return; } / Opening a handle for the Timer 0 onto CPU vector 12 / vectId = CSL_INTC_VECTID_12; hIntcTimer = CSL_intcOpen (&intcTimerObj, CSL_INTC_EVENTID_TINTLO0, \ &vectId , NULL); if (hIntcTimer == NULL) { printf("Intc open failed\n"); return; } / Plug Event handler / EventRecord.handler = &eventTimerHandler; EventRecord.arg = hIntcTimer; status = CSL_intcPlugEventHandler(hIntcTimer,&EventRecord); if (status != CSL_SOK) { printf("Intc plug event handler failed\n"); return; } / Checking the CSL_INTC_CMD_EVTENABLE, by enabling timer event / status = CSL_intcHwControl(hIntcTimer, CSL_INTC_CMD_EVTENABLE,NULL); if (status != CSL_SOK) { printf("Intc CSL_INTC_CMD_EVTENABLE command failed\n"); return; } / Initialize and Setup timer CSL module / CSL_tmrInit(NULL); hTmr = CSL_tmrOpen(&TmrObj, CSL_TMR_0, NULL, &status); / Setup timer / CSL_tmrHwSetup(hTmr, &hwSetup); / Stop the timer / status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL); / set the timer mode to unchained dual mode / hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED; / Setup timer / CSL_tmrHwSetup(hTmr, &hwSetup); / Load the period register / CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void )&LoadValue); /* Start the timer with auto reload / CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, (void )&TimeCountMode); /* Wait for interrupt genaration, (count to become 20) / while (intrCnt < 20); intrCnt = 0; / Checking the CSL_INTC_CMD_EVTDISABLE, by disabling timer event / status = CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDISABLE,NULL); if (status != CSL_SOK) { printf("Intc CSL_INTC_CMD_EVTDISABLE command failed\n"); return; } / Wait for long time, to check timer stop / for (delay =0 ; delay < 10000; delay++); / Check for timer counter value / if (intrCnt != 0) while(1); / Failed / / Close Intc CSL / CSL_intcClose(hIntcTimer); / Do the same stuff with an event that is on a combined with others. * Opening a handle for the Combiner 0 onto CPU vector 12 / / Open the combined event on CPU vector 12 / vectId = CSL_INTC_VECTID_12; hIntcComb = CSL_intcOpen(&intcCombObj,CSL_INTC_EVENTID_EVT2, &vectId,NULL); if (hIntcComb == NULL) { printf("Intc combined event open failed \n"); return; } vectId = CSL_INTC_VECTID_COMBINE; hIntcTimer = CSL_intcOpen (&intcTimerObj, CSL_INTC_EVENTID_TINTLO0, \ &vectId , NULL); if (hIntcTimer == NULL) { printf("Intc open failed\n"); return; } / Plug event handler / EventRecord.handler = &eventTimerHandler; EventRecord.arg = hIntcTimer; status = CSL_intcPlugEventHandler(hIntcTimer, &EventRecord); if (status != CSL_SOK) { printf("Intc plug event handler failed\n"); return; } / Enabling the combined event / evtEn = CSL_INTC_EVENTID_TINTLO0; status = CSL_intcHwControl(hIntcComb,CSL_INTC_CMD_EVTENABLE, &evtEn); if (status != CSL_SOK) { printf("Enabling the combined event failed\n"); return; } / Enabling timer event / status = CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTENABLE,NULL); if (status != CSL_SOK) { printf("Enabling timer event failed\n"); return; } / Wait for interrupt genaration, (count to become 20) / while (intrCnt < 20); intrCnt = 0; / Checking the CSL_INTC_CMD_EVTDISABLE by disabling timer event / status = CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDISABLE,NULL); if (status != CSL_SOK) { printf("Disabling the combined event failed\n"); return; } / Wait for a long time / for (delay =0 ; delay < 10000; delay++); / Check for timer counter value / if (intrCnt != 0) while(1); / Failed / / Now doing the same test with the Combined Event disabled/enabled / intrCnt = 0; CSL_intcHwControl(hIntcComb,CSL_INTC_CMD_EVTDISABLE,NULL); / Enabling timer event / CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTENABLE,NULL); / Wait for a long time, to check timer stop / for (delay =0 ; delay < 10000; delay++); / Check for timer counter value / if (intrCnt != 0) while(1); / Failed / / Enable the combined event / CSL_intcHwControl(hIntcComb,CSL_INTC_CMD_EVTENABLE,NULL); / Wait for interrupt genaration, (count to become 20) / while (intrCnt < 20); printf ("Intc Example Done \n"); / Clear the all events / for (idx = 0; idx < 4; idx++) { evtClr = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTFLAG[idx]; ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[idx] = evtClr; } / Close Intc / CSL_tmrClose (hTmr); CSL_intcClose(hIntcTimer); CSL_intcClose(hIntcComb); } / * ============================================================================= * @func eventTimerHandler * * @desc * This is the interrupt event handler for timer * * @arg handle * Pointer to timer handle * * * @eg * eventTimerHandler (); * ============================================================================= / void eventTimerHandler ( void handle ) { intrCnt++; if (intrCnt == 20) CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDISABLE,NULL); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnInit.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_pwrdwnInit.c * * @path $(CSLPATH)\src\pwrdwn * * @desc File for functional layer of CSL API CSL_pwrdwnInit () * / / ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * ============================================================================= / #include <csl_pwrdwn.h> /* * ============================================================================ * @brief Initializes the module * * CSL_pwrdwnInit(..) initializes the PWRDWN module. * This function is idempotent -- calling it several times would * have the same effect as calling it the first time. * This function initializes the CSL data structures, and doesn't * touches the hardware. * * @b Arguments * @verbatim pContext Pointer to module-context. As PWRDWN doesn't have any context based information user is expected to pass NULL. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The CSL for PWRDWN is initialized * * @b Modifies * @n None * * Note: As PWRDWN doesn't have any context based information, the function * just returns CSL_SOK. User is expected to pass NULL. * * @b Example * @verbatim ... if (CSL_SOK != CSL_pwrdwnInit(NULL)) { return; } @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_pwrdwnInit, ".text:csl_section:pwrdwn"); CSL_Status CSL_pwrdwnInit ( CSL_PwrdwnContext pContext ) { /* If the module is already initialized, then error is * returned as init done(CSL_EINITDONE). If the user * needs to force init more than once, then set the * global Context pointer to NULL and invoke CSL_pwrdwnInit() */ return CSL_SOK; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/common/csl_pwrdwnGetBaseAddress.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * provided * ============================================================================ / /* ============================================================================ * @file csl_pwrdwnGetBaseAddress.c * * @path $(CSLPATH)\src\common * * @desc CSL Implementation of CSL_pwrdwnGetBaseAddress * * Note: This function is open for re-implementing if the user wants to modify * the base address of the peripheral object to point to a different location * there by allow CSL initiated write/reads into peripheral MMR's go to an * alternate location. Please refer documentation for more details. * * @author <NAME>. / / ============================================================================= * Revision History * ================ * 22-sep-2005 PSK updated according to code review comments. * 09-Aug-2006 NG Added condition to check the invalid parameter * ============================================================================= / #include <soc.h> #include <csl_pwrdwn.h> /* =========================================================================== * @n@b CSL_pwrdwnGetBaseAddress * * @b Description * @n This function gets the base address of the given pwrdwn * instance. * * @b Arguments * @verbatim pwrdwnNum Peripheral instance numberd pPwrdwnParam Module specific parameters pBaseAddress Pointer to base address structure containing base address details @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK Successful on getting the base * address of pwrdwn * @li CSL_ESYS_FAIL pwrdwn instance is not * available. * @li CSL_ESYS_INVPARAMS Invalid parameter * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Base address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example: @verbatim CSL_PwrdwnHandle hPwrdwn; CSL_PwrdwnBaseAddress baseAddress; CSL_PwrdwnParam params; CSL_pwrdwnGetBaseAddress(CSL_PWRDWN, &params, &baseAddress) ; @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_pwrdwnGetBaseAddress, ".text:csl_section:pwrdwn"); CSL_Status CSL_pwrdwnGetBaseAddress ( CSL_InstNum pwrdwnNum, CSL_PwrdwnParam pPwrdwnParam, CSL_PwrdwnBaseAddress *pBaseAddress ) { CSL_Status status = CSL_SOK; if (pBaseAddress == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (pwrdwnNum) { case CSL_PWRDWN: pBaseAddress->regs = (CSL_PdcRegsOvly)CSL_PWRDWN_PDC_REGS; pBaseAddress->l2pwrdwnRegs = (CSL_L2pwrdwnRegsOvly)CSL_PWRDWN_L2_REGS; break; default: pBaseAddress->regs = (CSL_PdcRegsOvly)NULL; pBaseAddress->l2pwrdwnRegs = (CSL_L2pwrdwnRegsOvly)NULL; status = CSL_ESYS_FAIL; } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrHwSetup.c	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* =========================================================================== * @file csl_tmrHwSetup.c * * @brief File for functional layer of CSL API CSL_tmrHwSetup() * * @path $(CSLPATH)\src\timer * * @desc The CSL_tmrHwSetup() function definition & it's associated * functions * ============================================================================ / / ============================================================================ * Revision History * =============== * 1-Sept-2004 HMM File Created. * 29-Jul-2005 PSK Updted changes acooriding to revised timer spec. The number * convention TIM12, TIM34 are changed to TIMLO and TIMHI. * 01-Feb-2006 ds Updated According to TCI6482/C6455 UserGuide * ============================================================================ / #include <csl_tmr.h> #include <csl_tmrAux.h> /* ============================================================================ * @n@b CSL_tmrHwSetup * * @b Description * @n It configures the timer instance registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim htmr Handle to the timer instance setup Pointer to hardware setup structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The specified instance will be setup according to value passed * * @b Modifies * @n Hardware registers for the specified instance * * @b Example * @verbatim CSL_status status; CSL_tmrHwSetup hwSetup; ... status = CSL_tmrHwSetup(htmr, &hwSetup); ... @endverbatim * =========================================================================== / #pragma CODE_SECTION(CSL_tmrHwSetup, ".text:csl_section:tmr"); CSL_Status CSL_tmrHwSetup ( CSL_TmrHandle hTmr, CSL_TmrHwSetup hwSetup ) { CSL_Status status = CSL_SOK ; if (hTmr == NULL) { status = CSL_ESYS_BADHANDLE; } else if (hwSetup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Load the Period register's / hTmr->regs->PRDLO = hwSetup->tmrTimerPeriodLo; hTmr->regs->PRDHI = hwSetup->tmrTimerPeriodHi; / Load the counter register's / hTmr->regs->TIMLO = hwSetup->tmrTimerCounterLo; hTmr->regs->TIMHI = hwSetup->tmrTimerCounterHi; / Setup the TCR register configurations / CSL_FINS(hTmr->regs->TCR, TMR_TCR_PWID_HI, hwSetup->tmrPulseWidthHi); CSL_FINS(hTmr->regs->TCR, TMR_TCR_CP_HI, hwSetup->tmrClockPulseHi); CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVOUTP_HI, hwSetup->tmrInvOutpHi); / Setup the TCR register configurations / CSL_FINS(hTmr->regs->TCR, TMR_TCR_TIEN_LO, hwSetup->tmrIpGateLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_CLKSRC_LO, hwSetup->tmrClksrcLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_PWID_LO, hwSetup->tmrPulseWidthLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_CP_LO, hwSetup->tmrClockPulseLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVINP_LO, hwSetup->tmrInvInpLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVOUTP_LO, hwSetup->tmrInvOutpLo); / Setup the TGCR register configurations / CSL_FINS(hTmr->regs->TGCR, TMR_TGCR_PSCHI, hwSetup->tmrPreScalarCounterHi); / set the operation mode */ CSL_FINS(hTmr->regs->TGCR, TMR_TGCR_TIMMODE, hwSetup->tmrTimerMode); } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/srio/csl_srioGetHwStatus.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* =========================================================================== * @file csl_srioGetHwStatus.c * * @brief File for functional layer of CSL API CSL_srioGetHwStatus() * * @path $(CSLPATH)\srio\src * * @desc The CSL_srioGetHwStatus() function definition and it's associated * functions * ============================================================================ / / ============================================================================ * Revision History * =============== * 24-Aug-2005 PSK File Created. * ============================================================================ / #include <csl_srio.h> #include <csl_srioAux.h> /* =========================================================================== * @n@b CSL_srioGetHwStatus * * @b Description * @n This function is used to get the value of various parameters of the * SRIO instance. The value returned depends on the query passed. * * @b Arguments * @verbatim hSrio Handle to the SRIO instance query Query to be performed response Pointer to buffer to return the data requested by the query passed @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Successful completion of the * query * * @li CSL_ESYS_BADHANDLE - Invalid handle * * @li CSL_ESYS_INVQUERY - Query command not supported * * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * Data requested by the query is returned through the variable * "response" * * @b Modifies * @n The input arguement "response" is modified * * @b Example * @verbatim CSL_Status status; CSL_SrioHandle hSrio; CSL_SrioPidNumber response; ... Status=CSL_srioGetHwStatus(hSrio, CSL_SRIO_QUERY_PID_NUMBER, &response); ... @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_srioGetHwStatus, ".text:csl_section:srio"); CSL_Status CSL_srioGetHwStatus ( CSL_SrioHandle hSrio, CSL_SrioHwStatusQuery query, void response ) { CSL_Status status = CSL_SOK; if (hSrio == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (query) { /* queries SRIO Peripheral Identification number / case CSL_SRIO_QUERY_PID_NUMBER: CSL_srioGetPid(hSrio, (CSL_SrioPidNumber )response); break; /* Gets global enable status / case CSL_SRIO_QUERY_GBL_EN_STAT: CSL_srioGetGblEnStat(hSrio, (Uint32 )response); break; /* Gets block enable status for all the blocks / case CSL_SRIO_QUERY_BLK_EN_STAT: CSL_srioGetBlkEnStat(hSrio, (CSL_SrioBlkEn )response); break; /* Get doorbell interrupts status / case CSL_SRIO_QUERY_DOORBELL_INTR_STAT: CSL_srioGetDoorbellIntrStat(hSrio, (CSL_SrioPortData )response); break; /* Get the LSU interrupts status / case CSL_SRIO_QUERY_LSU_INTR_STAT: CSL_srioGetLsuIntrStat(hSrio, (Uint32 )response); break; /* Gets Error, Reset, and Special Event interrupts status / case CSL_SRIO_QUERY_ERR_RST_INTR_STAT: CSL_srioGetErrRstIntrStat(hSrio, (Uint32 )response); break; /* Get status of LSU interrupts decode for DST 0 / case CSL_SRIO_QUERY_LSU_INTR_DECODE_STAT: CSL_srioGetLsuIntrDecodeStat(hSrio, (Uint32 )response); break; /* Get Error, Reset, and Special Event interrupts decode * status for DST 0 / case CSL_SRIO_QUERY_ERR_INTR_DECODE_STAT: CSL_srioGetErrIntrDecodeStat(hSrio, (Uint32 )response); break; /* Gets the status of the pending command of LSU * registers for a particular port / case CSL_SRIO_QUERY_LSU_COMP_CODE_STAT: CSL_srioLsuCompCodeStat(hSrio, (CSL_SrioLsuCompStat )response); break; /* Gets status of the command registers of LSU module * for a particular port / case CSL_SRIO_QUERY_LSU_BSY_STAT: CSL_srioLsuBsyStat(hSrio, (CSL_SrioPortData )response); break; /* Gets the type of device (Vendor specific) / case CSL_SRIO_QUERY_DEV_ID_INFO: CSL_srioGetDevIdInfo(hSrio, (CSL_SrioDevInfo )response); break; /* Gets vendor specific assembly information / case CSL_SRIO_QUERY_ASSY_ID_INFO: CSL_srioGetAssyIdInfo(hSrio, (CSL_SrioAssyInfo )response); break; /* Gets processing element features / case CSL_SRIO_QUERY_PE_FEATURE: CSL_srioGetPeFeature(hSrio, (Uint32 )response); break; /* Get source operations CAR status / case CSL_SRIO_QUERY_SRC_OPERN_SUPPORT: CSL_srioGetSrcOpernSuppStat(hSrio, (Uint32 )response); break; /* Get destination operations CAR status / case CSL_SRIO_QUERY_DST_OPERN_SUPPORT: CSL_srioGetDstOpernSuppStat(hSrio, (Uint32 )response); break; /* Get local configuration space base addresses / case CSL_SRIO_QUERY_LCL_CFG_BAR: CSL_srioGetLclCfgBar(hSrio, (CSL_SrioLongAddress )response); break; /* Get status of SP_LM_RESP register fields / case CSL_SRIO_QUERY_SP_LM_RESP_STAT: CSL_srioGetSpLmRespStat(hSrio, (CSL_SrioPortData )response); break; /* Get status of SP_ACKID_STAT register fields / case CSL_SRIO_QUERY_SP_ACKID_STAT: CSL_srioGetSpAckIdStat(hSrio, (CSL_SrioPortData )response); break; /* Get status of SP_ERR_STAT register fields / case CSL_SRIO_QUERY_SP_ERR_STAT: CSL_srioGetSpErrStat(hSrio, (CSL_SrioPortData )response); break; /* Gets SP_CTL register status fields / case CSL_SRIO_QUERY_SP_CTL: CSL_srioGetSpCtlStat(hSrio, (CSL_SrioPortData )response); break; /* Get the status of logical/transport layer errors / case CSL_SRIO_QUERY_LGCL_TRNS_ERR_STAT: CSL_SrioGetLgclTrnsErrStat(hSrio, (Uint32 )response); break; /* Get captured error info of logical/transport layer / case CSL_SRIO_QUERY_LGCL_TRNS_ERR_CAPT: CSL_srioGetLgclTransErrCapt(hSrio, (CSL_SrioLogTrErrInfo )response); break; /* Get status of port error detect CSR fields / case CSL_SRIO_QUERY_SP_ERR_DET_STAT: CSL_srioGetSpErrDetStat(hSrio, (CSL_SrioPortData )response); break; /* Get the port error captured information / case CSL_SRIO_QUERY_PORT_ERR_CAPT: CSL_srioGetPortErrCapt(hSrio, (CSL_SrioPortErrCapt )response); break; /* Get port control independent register fields status / case CSL_SRIO_QUERY_SP_CTL_INDEP: CSL_srioGetSpCtlIndepStat(hSrio, (CSL_SrioPortData )response); break; /* Get the port write capture information / case CSL_SRIO_QUERY_PW_CAPTURE: CSL_srioGetPwCapt(hSrio, (CSL_SrioPortWriteCapt )response); break; /* Reads the count of the number of transmission * errors that have occurred / case CSL_SRIO_QUERY_ERR_RATE_CNTR_READ: CSL_srioErrRateCounterRead(hSrio, (CSL_SrioPortData )response); break; /* Reads the peak value of the error rate counter / case CSL_SRIO_QUERY_PEAK_ERR_RATE_READ: CSL_srioErrRatePeakRead(hSrio, (CSL_SrioPortData )response); break; default: status = CSL_ESYS_INVQUERY; break; } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotOpen.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_memprotOpen.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotOpen () * / / ============================================================================= * Revision History * =============== * 16-Nov-2005 ds updated the documentation * ============================================================================= / #include <csl_memprot.h> /* =========================================================================== * @n@b CSL_memprotOpen * * @b Description * @n This function populates the peripheral data object for the instance * and returns a handle to the instance. * The open call sets up the data structures for the particular instance * of MEMPROT device.The device can be re-opened anytime after it has been * normally closed, if so required. The handle returned by this call is * input as an essential argument for rest of the APIs described * for this module. * * @b Arguments * @verbatim pMemprotObj Pointer to the MEMPROT instance object memprotNum Instance of the MEMPROT to be opened pMemprotParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * <b> Return Value </b> CSL_MemprotHandle * @n Valid MEMPROT instance handle will be returned if status value is equal to CSL_SOK. * * <b> Pre Condition </b> * Memory protection must be successfully initialized via @a CSL_memprotInit() * before calling this function. Memory for the @a CSL_MemprotObj must be * allocated outside this call. This object must be retained while usage of * this module.Depending on the module opened some inherant constraints need * to be kept in mind. When a handle for the Config block is opened the only * operation possible is a query for the fault Status. No other control * command/ query/ setup must be used. * When a handle for L1D/L1P is opened then too constraints wrt the number of * Memory pages must be kept in mind. * * <b> Post Condition </b> * @n 1. MEMPROT object structure is populated * @n 2. The status is returned in the status variable. If status * returned is * @li CSL_SOK Valid MEMPORT handle is returned * @li CSL_ESYS_FAIL The MEMPORT instance is invalid * @li CSL_ESYS_INVPARAMS Invalid parameter * * @b Modifies * @n 1. The status variable * @n 2. MEMPROT object structure * * @b Example * @verbatim CSL_MemprotObj mpL2Obj; CSL_MemprotHandle hmpL2; CSL_Status status; // Initializing the module CSL_memprotInit(NULL); // Opening the Handle for the L2 hmpL2 = CSL_memprotOpen(&mpL2Obj, CSL_MEMPROT_L2, NULL, &status); @endverbatim * ============================================================================ / #pragma CODE_SECTION (CSL_memprotOpen, ".text:csl_section:memprot"); CSL_MemprotHandle CSL_memprotOpen ( CSL_MemprotObj pMemprotObj, CSL_InstNum memprotNum, CSL_MemprotParam pMemprotParam, CSL_Status pStatus ) { CSL_MemprotHandle hMemprot = (CSL_MemprotHandle)NULL; CSL_MemprotBaseAddress baseAddress; if (pStatus == NULL) { /* do nothing : already the module is initialized to NULL / } else if (pMemprotObj == NULL) { pStatus = CSL_ESYS_INVPARAMS; } else { pStatus = CSL_memprotGetBaseAddress(memprotNum, pMemprotParam, &baseAddress); if (pStatus == CSL_SOK) { pMemprotObj->regs = baseAddress.regs; pMemprotObj->modNum = (CSL_InstNum)memprotNum; hMemprot = (CSL_MemprotHandle)pMemprotObj; } else { pMemprotObj->regs = (CSL_MemprotRegsOvly)NULL; pMemprotObj->modNum = (CSL_InstNum)-1; } } return (hMemprot); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/cache/csl_cacheEnable.c	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_cacheEnable.c * * @path $(CSLPATH)\src\cache * * @desc File for functional layer of CSL API CACHE_enableCaching () * / / ============================================================================= * Revision History * =============== * 23-Mar-2004 <NAME> File Created * * ============================================================================= / #include <csl_cache.h> #include <_csl_cache.h> /* ============================================================================ * @n@b CACHE_enableCaching * * @b Description * @n Enables caching for the specified memory range. * * @b Arguments * @verbatim mar EMIF range @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Caching for the specified memory range is enabled * * @b Modifies * @n MAR register * * @b Example * @verbatim ... CACHE_enableCaching (CACHE_EMIFB_CE00); ... @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CACHE_enableCaching, ".text:csl_section:cache"); void CACHE_enableCaching ( CE_MAR mar ) { ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->MAR[mar] = 1; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioClose.c	/* ========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * provided * ========================================================================== / /* =========================================================================== * @file csl_gpioClose.c * * @path $(CSLPATH)\src\gpio * * @desc File for functional layer of CSL API CSL_gpioClose() * ============================================================================ / / ============================================================================ * Revision History * =============== * 10-Jun_2004 PGR file created * 07-Sep-2004 Nsr Updated function and documentation for CSL_gpioclose. * - Removed the include file, csl_resource.h. * 11-Oct-2004 Nsr renamed the local variable "st" as "status" * 28-Jul-2005 PSK Updated CSL source to support only ONE BANK. * bank "index" is removed. * 06-Mar-2006 ds Updated the documentation * ============================================================================ / #include <csl_gpio.h> /* ============================================================================ * @n@b CSL_gpioClose * * @b Description * @n This function closes the specified instance of GPIO. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Close successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * <b> Pre Condition </b> * @n Both CSL_gpioInit() and CSL_gpioOpen() must be called successfully in * order before calling CSL_gpioClose(). * * <b> Post Condition </b> * @n The GPIO CSL APIs can not be called until the GPIO CSL is reopened * again using CSL_gpioOpen(). * * @b Modifies * @n Obj structure values * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_Status status; ... status = CSL_gpioClose(hGpio); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_gpioClose, ".text:csl_section:gpio"); CSL_Status CSL_gpioClose ( CSL_GpioHandle hGpio ) { / Indicate in the CSL global hGpio structure that the peripheral * has been unreserved */ CSL_Status status = CSL_SOK; if (hGpio != NULL) { hGpio->regs = (CSL_GpioRegsOvly)NULL; hGpio->gpioNum = (CSL_InstNum)-1; } else { status = CSL_ESYS_BADHANDLE; } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3HwChannelSetup.c	<filename>DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3HwChannelSetup.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_edma3HwChannelSetup.c * * @path $(CSLPATH)\src\edma * * @desc File for functional layer of CSL API CSL_edma3HwChannelSetup() * / / ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= / #include <csl_edma3.h> #include <csl_edma3Aux.h> /* ============================================================================ * @n@b CSL_edma3HwChannelSetupParam * * @b Description * @n Sets up the channel to parameter entry mapping.This writes the * DCHMAP[]/QCHMAP appropriately. * * @b Arguments * @verbatim hEdma Channel Handle paramNum Parameter Entry @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Channel setup param successful * @li CSL_ESYS_BADHANDLE - The handle passed is * invalid * @li CSL_ESYS_INVPARAMS - The paameters passed is invalid * * <b> Pre Condition </b> * @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be * called successfully in that order before this API can be invoked * * <b> Post Condition </b> * @n Channel to parameter entry is configured * * @b Modifies * @n Edma registers * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; Uint16 paramNum; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); // Set the parameter entry number to channel paramNum = 100; CSL_edma3HwChannelSetupParam(hChannel,paramNum); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_edma3HwChannelSetupParam, ".text:csl_section:edma3"); CSL_Status CSL_edma3HwChannelSetupParam ( CSL_Edma3ChannelHandle hEdma, Uint16 paramNum ) { CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else if (paramNum >= CSL_EDMA3_NUM_PARAMSETS) { status = CSL_ESYS_INVPARAMS; } else { / CSL_edma3ChannelSetEvtQue(hCh,setup->que); / if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH) { #if CSL_EDMA3_CHMAPEXIST CSL_FINS(hEdma->regs->DCHMAP[hEdma->chaNum], EDMA3CC_DCHMAP_PAENTRY, \ paramNum); #endif } else CSL_FINS(hEdma->regs->QCHMAP[hEdma->chaNum-CSL_EDMA3_NUM_DMACH], \ EDMA3CC_QCHMAP_PAENTRY,paramNum); } return (status); } /* ============================================================================ * @n@b CSL_edma3HwChannelSetupTriggerWord * * @b Description * @n Programs the QDMA channel triggerword.This writes the QCHMAP[] * appropriately. * * @b Arguments * @verbatim hEdma Channel Handle triggerWord Trigger Word @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Channel setup triggerword * successful * @li CSL_ESYS_BADHANDLE - The handle passed is * invalid * @li CSL_ESYS_INVPARAMS - The paameters passed is invalid * * <b> Pre Condition </b> * @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be * called successfully in that order before this API can be invoked * * <b> Post Condition </b> * @n Sets up the QDMA Channel to trigger Word * * @b Modifies * @n Edma registers * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_QCHA_0; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Sets up the QDMA Channel 0 trigger Word to the 3rd trigger word. CSL_edma3HwChannelSetupTriggerWord(hChannel,3); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_edma3HwChannelSetupTriggerWord, ".text:csl_section:edma3"); CSL_Status CSL_edma3HwChannelSetupTriggerWord ( CSL_Edma3ChannelHandle hEdma, Uint8 triggerWord ) { CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else if (triggerWord > 7) { status = CSL_ESYS_INVPARAMS; } else if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH) { / CSL_edma3ChannelSetEvtQue(hEdma,setup->que); / status = CSL_ESYS_INVPARAMS; } else CSL_FINS(hEdma->regs->QCHMAP[hEdma->chaNum-CSL_EDMA3_NUM_DMACH], \ EDMA3CC_QCHMAP_TRWORD,triggerWord); return (status); } /* ============================================================================ * @n@b CSL_edma3HwChannelSetupQue * * @b Description * @n Programs the Channel to Queue mapping.This writes the DMAQNUM/QDAMQNUM * appropriately. * * @b Arguments * @verbatim hEdma Channel Handle evtQue Queue Setup @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Channel setup queue * successful * @li CSL_ESYS_BADHANDLE - The handle passed is * invalid * * <b> Pre Condition </b> * @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be * called successfully in that order before this API can be invoked * * <b> Post Condition </b> * @n Sets up the channel to Queue mapping * * @b Modifies * @n Edma registers * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Set up the channel to que mapping CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_3); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_edma3HwChannelSetupQue, ".text:csl_section:edma3"); CSL_Status CSL_edma3HwChannelSetupQue ( CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que evtQue ) { Uint32 _cha; Uint32 _qNumIndex; Uint32 _qchMap; CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else { if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH) { / Extracting the Channel Number in case of QDMA / _cha = hEdma->chaNum - CSL_EDMA3_NUM_DMACH; / Channel to Event Queue mapping / CSL_FINSR(hEdma->regs->QDMAQNUM,_cha 4 + 2,_cha * 4,evtQue); } else { /* Finding out the relevant DMAQNUM register and the correct bit positions to write into / _qNumIndex = hEdma->chaNum >> 3; _qchMap = hEdma->chaNum - (_qNumIndex 8); CSL_FINSR(hEdma->regs->DMAQNUM[_qNumIndex], _qchMap * 4 + 2, \ _qchMap * 4, evtQue); } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/tcp2/tcp2_shared_mode/src/Tcp2_shared_mode_example.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file Tcp2_shared_mode_example.c * * @path $(CSLPATH)\example\tcp2\tcp2_shared_mode\src * * @desc Example file for the TCP2 CSL * ============================================================================ * @n Target Platform: EVM * ============================================================================ * * The example demonstrates the usage of the TCP2 CSL API for decoding the * input data in shared mode. * * ============================================================================ * @n <b> Description </b> * This is an example for the usage of the TCP2 CSL API in the shared * mode. * * @b Procedure * 1 - Sets up the TCP2 input configuration parameters * 2 - Configures the EDMA to transfer the input paramters, * systematics and parity data, apriori data on successful TCPXEVT * 3 - Configures the EDMA for the extrinsics transfer on TCPREVT. * 4 - Starts the turbo coprocessor and waits for the completion of the * processing * 5 - After the state indicates the extrinsics are read, the example exits * 6 - This demonstrates the usage only for the first sub frame of * a frame length = 51200 ============================================================================= * The steps to run this example are as follows: * 1 - Open the Tcp2_shared_mode_example.pjt in the CCS studio * 2 - Build the example * 3 - Execute the .out file * / / ============================================================================= * Revision History * =============== * 23-May-2005 sd File Created. * 05-Aug-2005 sd Changes for EDMA CSL * 17-Dec-2005 sd Added clearing the EDMA error registers before enabling the * channel. * 05-Feb-2006 sd Changes according to the spec changes * 21-Feb-2006 ds Added clearing the EDMA error registers at end of the * example * 22-Mar-2006 ds Removed "mode" bit from TCP2_BaseParams structure * ============================================================================= / #include <csl_tcp2.h> #include <csl_tcp2Aux.h> #include <csl_edma3.h> #include <stdio.h> #include <cslr_dev.h> / defines / / To load the interleaver RAM/ #define INTERLEAVER_LOAD_FLAG FALSE / Maximum iterations of the TCP / #define MAX_TCP_ITERATIONS 8 / Maximum iterations of the TCP / #define MIN_TCP_ITERATIONS 1 / Output paramters read flag / #define OUT_PARAM_READ_FLAG FALSE / prolog size / #define PROLOG_SIZE 32 / CRC Polynomial / #define CRC_POLY 0 / CRC length / #define CRC_LEN 0 / EDMA PARAM size / #define EDMA_PARAM_SIZE 0x20 / Frame length of the TCP input data / Uint32 frameLength = 51200; / externs / extern TCP2_TailData tailData []; extern TCP2_UserData sysParData []; extern TCP2_ExtrinsicData aprioriData []; extern TCP2_ExtrinsicData extrinsicData []; / globals / Uint8 extrinsicBuffer1 [51200]; Uint8 extrinsicBuffer2 [51200]; / TCP input configuration structure / TCP2_ConfigIc configIc [3]; / EDMA CSL configuration structures / CSL_Edma3Context context; CSL_Edma3ChannelObj ChObj, ChObj1; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelHandle hChannel, hChannel1; CSL_Edma3ParamHandle hParam[24]; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3ChannelAttr chParam, chParam1; CSL_Edma3ChannelErr chErrClear; / EDMA PARAM indexes / Uint32 txParamIndex = 0; Uint32 rxParamIndex = 20; / forward declarations / Uint16 tcp2_configEdma ( Uint32 inputRegs, Uint8* aprioriData, Uint8* extrinsicBuffer, Uint32 txDataLen, Uint32 aprioriTxlen, Uint32 rxDataLen, Bool endConfig ); /* * ============================================================================ * @func main () * * @desc * Example to show the usage of the TCP2 CSL API for shared mode * processing * * @b Arguments * @verbatim None @endverbatim * * <b> Return Value </b> None * * @b Procedure * 1 - Sets up the TCP2 input configuration parameters * 2 - Configures the EDMA to transfer the input paramters, * systematics and parity data, apriori data on successful TCPXEVT * 3 - Configures the EDMA for the extrinsics transfer on TCPREVT. * 4 - Starts the turbo coprocessor and waits for the completion of the * processing * 5 - After the state indicates the extrinsics are read, the example exits * * ============================================================================ / void main ( void ) { TCP2_BaseParams configBase; / base params to configure TCP2 / TCP2_Params configParams [2]; / holds all the input configuration parameters for TCP/ TCP2_Params tempParams; Uint32 frameLen = frameLength; Uint32 cnt; Uint32 txDataLen = 0, rxDataLen = 0, aprioriTxLen = 0; Uint32 extIndex, aprIndex; /* Enable the TCP2 in power saver / CSL_FINST (((CSL_DevRegs)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); CSL_FINST (((CSL_DevRegs)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TCPCTL, ENABLE); while (CSL_DEV_PERSTAT0_TCPSTAT_ENABLE != CSL_FEXT (((CSL_DevRegs)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TCPSTAT)); /* setup the base params / configBase.frameLen = frameLen; configBase.inputSign = TCP2_INPUT_SIGN_POSITIVE; configBase.intFlag = INTERLEAVER_LOAD_FLAG; configBase.maxIter = MAX_TCP_ITERATIONS; configBase.maxStarEn = FALSE; configBase.standard = TCP2_STANDARD_3GPP; configBase.crcLen = 0; / Disable CRC / configBase.crcPoly = 0; / not used / configBase.minIter = MIN_TCP_ITERATIONS; configBase.numCrcPass = 0; / default value / configBase.outParmFlag = OUT_PARAM_READ_FLAG; configBase.outputOrder = TCP2_OUT_ORDER_0_31; configBase.prologRedEn = FALSE; configBase.prologSize = PROLOG_SIZE; configBase.rate = TCP2_RATE_1_3; configBase.snr = 0; / disable SNR threshold checking / configBase.map = TCP2_MAP_MAP1; / assign the extrinsic scaling factors / for (cnt = 0; cnt < 16; cnt++) configBase.extrScaling [cnt] = 0; / setup the TCP configuration registers parmeters / TCP2_genParams (&configBase, configParams); / generate the configuration register values / / For the first sub frame / TCP2_genIc (&configParams [0], tailData, &configIc [0]); / for the middle sub frame / tempParams = &configParams [0]; tempParams->mode = TCP2_MIDDLE_SF; TCP2_genIc (tempParams, tailData, &configIc [1]); / For the last sub frame / TCP2_genIc (&configParams [1], tailData, &configIc [2]); / configure the Endian register / TCP2_setInterEndian (CSL_TCP2_TCPEND_ENDIAN_INTR_32BITS); TCP2_setExtEndian (CSL_TCP2_TCPEND_ENDIAN_EXTR_32BITS); / configure the sleep modes / TCP2_setSlpzvdd (CSL_TCP2_TCPEND_SLPZVDD_EN_ENABLE); TCP2_setSlpzvss (CSL_TCP2_TCPEND_SLPZVSS_EN_ENABLE); / Configure EDMA to write/read TCP data on app. events / / MAP 1 configuration / / set the index for extrinsics / extIndex = 0; aprIndex = 0; / for the first sub frame / tempParams = &configParams [0]; txDataLen = tempParams->frameLen + tempParams->prologSize; if ((txDataLen % 2) !=0) txDataLen++; aprioriTxLen = tempParams->frameLen + tempParams->prologSize; if ((aprioriTxLen % 2) !=0) aprioriTxLen++; rxDataLen = tempParams->frameLen; if ((rxDataLen % 2) !=0) rxDataLen++; tcp2_configEdma ((Uint32)&configIc [0], &aprioriData [aprIndex], &extrinsicBuffer1 [extIndex], txDataLen, aprioriTxLen, rxDataLen, TRUE); /* Enable Channel / CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL); / Enable Channel / CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL); / reset and start the TCP / TCP2_reset (); TCP2_start (); / wait for the status to indicate extrinsics to be read / while (0x0B != TCP2_statTcpState ()); printf ("Reading the extrinsics \n"); / wait for the status to indicate the extrinsics read complete / while (0x01 == TCP2_statWaitExt ()); printf ("Reading the extrinsics complete \n"); / Disable cahnnels and clear the EDMA event registers / CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); / clear the EDMA error registers / chErrClear.missed = TRUE; chErrClear.secEvt = TRUE; CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear); printf ("Example complete \n"); } / * ============================================================================= * @func tcp2_configEdma * @desc * Configures EDMA channels 30 and 31. * For channel 31 there are 3 param entries(0, 1 and 2) which are linked. * Link 0 transfers the TCP2 input configuration register values. * Link 1 transfer the systematics and parity data. * Link 2 transfers the apriori data * For channel 30 there is 1 param entry (3). * Link 3 transfers the extrinsic data. * * @expected result * * * @eg * tcp2_configEdma(); * ============================================================================= / Uint16 tcp2_configEdma ( Uint32 inputRegs, Uint8 aprioriData, Uint8 extrinsicBuffer, Uint32 txDataLen, Uint32 aprioriTxlen, Uint32 rxDataLen, Bool endConfig ) { volatile Uint16 count; CSL_Status chStatus, chStatus1; CSL_edma3Init(&context); CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&chStatus); /* Channel Configuration for TCPXEVT event / / Channel Open / if (txParamIndex == 0){ / open it only the first time / chParam.regionNum = CSL_EDMA3_REGION_GLOBAL; chParam.chaNum = CSL_EDMA3_CHA_TCP2XEVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chParam, &chStatus); if ((chStatus != CSL_SOK) \|\| (hChannel == NULL)) { printf("Error in EDMA channel open function\n"); return 0; } / Channel Setup for PaRAM entry 0 / if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel, txParamIndex )){ printf("Error is EDMA channel setup for channel #31\n"); return 0; } if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel, CSL_EDMA3_QUE_0)) { printf("Error is EDMA channel setup for channel #31\n"); return 0; } } / Setup EDMA to transmit the input configuration parameters / hParam[txParamIndex] = CSL_edma3GetParamHandle (hChannel, txParamIndex, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)inputRegs; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, 0); myParamSetup.dstAddr = (Uint32)CSL_TCP2_CFG_REGS; myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE( ((txParamIndex+1) EDMA_PARAM_SIZE), 0); /* offset to the next PARAM entry / myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(sizeof (TCP2_ConfigIc), 1); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[txParamIndex], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #0\n"); return 0; } / Setup link to transmit systematics and parity data using param / txParamIndex++; hParam[txParamIndex] = CSL_edma3GetParamHandle (hChannel, txParamIndex, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_AB, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)sysParData; myParamSetup.dstAddr = (Uint32)CSL_TCP2_X0_MEM; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(8, 8); / length of the systematic and parity data to be transferred / myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(8, (txDataLen/2)); //txDataLen / linking to the offset to the next PARAM entry / myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE( ((txParamIndex+1) EDMA_PARAM_SIZE), 0); myParamSetup.cCnt = 1; myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, 0); if (CSL_SOK != CSL_edma3ParamSetup (hParam[txParamIndex], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #1\n"); return 0; } txParamIndex++; /* Setup link to transmit apriori data using param / hParam[txParamIndex] = CSL_edma3GetParamHandle (hChannel, txParamIndex, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)aprioriData; myParamSetup.dstAddr = (Uint32)CSL_TCP2_W1_MEM; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, 0); / length of the apriori data to be transferred / myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(aprioriTxlen, 1); myParamSetup.cCnt = 1; if (!endConfig) { myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( ((txParamIndex+1) EDMA_PARAM_SIZE), 0); } else { myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( CSL_EDMA3_LINK_NULL, 0); } if (CSL_SOK != CSL_edma3ParamSetup (hParam[txParamIndex], &myParamSetup)) { /* * link this with the next transfer to be configured unless this * is the last iteration / printf("Error in EDMA PARAM setup for entry #2\n"); return 0; } / increment to the next PARAM index / txParamIndex++; / Receive Channel Open / if (rxParamIndex == 20) { / open the channel only once / chParam1.regionNum = CSL_EDMA3_REGION_GLOBAL; chParam1.chaNum = CSL_EDMA3_CHA_TCP2REVT; hChannel1 = CSL_edma3ChannelOpen (&ChObj1, CSL_EDMA3, &chParam1, &chStatus1); if ((chStatus1 != CSL_SOK) \| (hChannel1 == NULL)) { printf("Error in EDMA channel open function\n"); return 0; } / Channel Setup / if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel1, rxParamIndex)) { printf("Error is EDMA channel setup for channel #30\n"); return 0; } if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel1, CSL_EDMA3_QUE_0)) { printf("Error is EDMA channel setup for channel #30\n"); return 0; } } / Channel Setup / / configure param entry 3 to read the extrinsics data / hParam[rxParamIndex] = CSL_edma3GetParamHandle (hChannel1, rxParamIndex, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)CSL_TCP2_W0_MEM; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (rxDataLen, 1); / number of bytes of apriori data to be read / myParamSetup.dstAddr = (Uint32)extrinsicBuffer; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE (0, 0); / * link this with the next transfer to be configured unless this * is the last iteration / if (!endConfig) { myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( ((rxParamIndex+1) EDMA_PARAM_SIZE), 0); } else { myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( CSL_EDMA3_LINK_NULL, 0); } myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE (0, 0); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[rxParamIndex], &myParamSetup)) { printf("Error in EDMA paRam setup for entry #3\n"); return 0; } /* increment to the next PARAM index */ rxParamIndex++; return 1; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_version.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_version.h * * @path $(CSLPATH)\inc * * @desc This file contains the version number of different chips * / / ============================================================================= * Revision History * =============== * 25-Aug-2006 NG Updated for new chip c6454 for the release v03_00_10_02 * ============================================================================= / #ifndef _CSL_VERSION_H_ #define _CSL_VERSION_H_ #ifdef __cplusplus extern "C" { #endif #include <tistdtypes.h> / 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) / #define CSL_VERSION_ID (0x03001002) #define CSL_VERSION_STR "@(#) CSL Revision: 3.00.10.02;" #ifdef c6482 #define CSL_CHIP_ID (0x6482) #define CSL_CHIP_STR "TMS320C6482 PG 1.0 (C6482)" #endif #ifdef c6455 #define CSL_CHIP_ID (0x6455) #define CSL_CHIP_STR "TMS320C6455 PG 1.0 (C6455)" #endif #ifdef c6454 #define CSL_CHIP_ID (0x6454) #define CSL_CHIP_STR "TMS320C6454 PG 1.0 (C6454)" #endif #ifdef c64xplus_intc #define CSL_CHIP_ID (0x64A) #define CSL_CHIP_STR "C64X PLUS" #endif /* @brief Retrieves the version ID / Uint32 CSL_versionGetID ( void ); /* @brief Retrieves the version string / const char CSL_versionGetStr ( void ); #ifdef __cplusplus } #endif #endif /* _CSL_VERSION_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/edma/qdma_idma_link_xfer_gbl_reg/src/Qdma_idma_link_xfer_gbl_reg.c	/* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ========================================================================== / /* =========================================================================== * * @file Qdma_link_xfer_gbl_reg.c * * @path $(CSLPATH)\example\edma\qdma_idma_link_xfer_gbl_reg\src * * @desc Example of EDMA * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @n This is an example of the CSL EDMA usage for the QDMA Channel * Initialization for a linked transfer. * This example do the following operations * 1. Initializes and Opens the edma module * 2. Sets up the Module and gets the module setup values * 3. Opens qdma channel0 in the global region. * 4. Maps channel to parameter entry 67 * 5. Gets param handle for 64, 65, 66 * 6. Links the param sets * - Parameter set 67 is linked 66 * - Parameter set 66 is linked 65 * - Parameter set 65 is linked 64 * 7. Initializes the parameter entries using IDMA and * 8. IDMA trigger the transfer * 9. Polls for IPR bit and clears the bit * 10. Compares the transfered data * 11. Displays the result based on step 10 * Note:- Parameter Set 64 is marked as static * * ============================================================================= * * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Qdma_idma_link_xfer_gbl_reg.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================ * Revision History * =============== * 08-July-2005 <NAME> File Created. * 16-Dec-2005 ds Updated documentation * 27-Mar-2006 ds Added disable edma chhnel command * ============================================================================ / #include <stdio.h> #include <csl_edma3.h> #include <soc.h> #include <csl_idma.h> / Globals / Uint8 srcBuff0[64]; Uint8 srcBuff1[64]; Uint8 srcBuff2[64]; Uint8 srcBuff3[64]; Uint8 dstBuff0[64]; Uint8 dstBuff1[64]; Uint8 dstBuff2[64]; Uint8 dstBuff3[64]; Uint32 passStatus = 1; #pragma DATA_ALIGN(myParamSetup, 32); CSL_Edma3ParamSetup myParamSetup[4]; / Forward declarations / void qdma_link_xfer_gbl_region (void); / * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= / void main(void) { / Invoke example / qdma_link_xfer_gbl_region (); return; } / * ============================================================================= * @func qdma_link_xfer_gbl_region * * @arg * NONE * * @desc * This is the example routine which perform qdma link transfer where * channel is open in global region * It implements following steps * 1. Initializes and Opens the edma module * 2. Sets up the Module and gets the module setup values * 3. Opens qdma channel0 in the global region. * 4. Maps channel to parameter entry 67 * 5. Gets param handle for 64, 65, 66 * 6. Links the param sets * - Parameter set 67 is linked 66 * - Parameter set 66 is linked 65 * - Parameter set 65 is linked 64 * 7. Initializes the parameter entries using IDMA and * 8. IDMA trigger the transfer * 9. Polls for IPR bit and clears the bit * 10. Compares the transfered data * 11. Closes edma module and channel * * @return * NONE * * ============================================================================= / void qdma_link_xfer_gbl_region (void) { CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParam64; CSL_Edma3ParamHandle hParam65; CSL_Edma3ParamHandle hParam66; CSL_Edma3ChannelObj ChObj; CSL_Edma3CmdIntr regionIntr; CSL_Edma3ChannelHandle hChannel; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Status status; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = \ CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; Uint32 loopIndex; / Initialize data / for (loopIndex = 0; loopIndex < 64; loopIndex++) { srcBuff0[loopIndex] = loopIndex; srcBuff1[loopIndex] = loopIndex; srcBuff2[loopIndex] = loopIndex; srcBuff3[loopIndex] = loopIndex; dstBuff0[loopIndex] = 0; dstBuff1[loopIndex] = 0; dstBuff2[loopIndex] = 0; dstBuff3[loopIndex] = 0; } / Module Initialization / status = CSL_edma3Init(&context); if (status != CSL_SOK) { printf ("Edma module initialization failed\n"); return; } / Module Level Open / hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); if ( (hModule == NULL) \|\| (status != CSL_SOK)) { printf ("Edma module open failed\n"); return; } / Module setup / hwSetup.dmaChaSetup = NULL; hwSetup.qdmaChaSetup = &qdmahwSetup[0]; status = CSL_edma3HwSetup(hModule, &hwSetup); if (status != CSL_SOK) { printf ("Hardware setup failed\n"); CSL_edma3Close (hModule); return; } / Channel open / chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL; chAttr.chaNum = CSL_EDMA3_QCHA_0; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); if ((hChannel == NULL) \|\| (status != CSL_SOK)) { printf ("Edma channel open failed\n"); return; } / Change channel to parameter entry mapping / status = CSL_edma3HwChannelSetupParam(hChannel, 67); if (status != CSL_SOK) { printf ("Edma channel to parameter entry mapping is failed\n"); return; } / Obtain a handle to parameter set 66 / hParam66 = CSL_edma3GetParamHandle(hChannel,66,&status); if (hParam66 == NULL) { printf ("Edma get param handle for param entry 66 failed\n"); return; } / Obtain a handle to parameter set 65 / hParam65 = CSL_edma3GetParamHandle(hChannel,65,&status); if (hParam65 == NULL) { printf ("Edma get param handle for param entry 65 failed\n"); return; } / Obtain a handle to parameter set 64 / hParam64 = CSL_edma3GetParamHandle(hChannel,64,&status); if (hParam64 == NULL) { printf ("Edma get param handle for param entry 64 failed\n"); return; } / Parameter setup for 64, 65, 66 param entries / myParamSetup[0].option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 3,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_EN, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup[0].srcAddr = (Uint32)srcBuff3; myParamSetup[0].aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1); myParamSetup[0].dstAddr = (Uint32)dstBuff3; myParamSetup[0] .srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup[0].linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE( CSL_EDMA3_LINK_NULL, \ 0); myParamSetup[0].srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup[0].cCnt = 1; myParamSetup[1].option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_DIS,\ 2,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup[1].srcAddr = (Uint32)srcBuff2; myParamSetup[1].aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1); myParamSetup[1].dstAddr = (Uint32)dstBuff2; myParamSetup[1] .srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup[1].linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParam64,0); myParamSetup[1].srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup[1].cCnt = 1; myParamSetup[2].option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_DIS,\ 1,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup[2].srcAddr = (Uint32)srcBuff1; myParamSetup[2].aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1); myParamSetup[2].dstAddr = (Uint32)dstBuff1; myParamSetup[2] .srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup[2].linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParam65,0); myParamSetup[2].srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup[2].cCnt = 1; myParamSetup[3].option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_DIS,\ 0,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup[3].srcAddr = (Uint32)srcBuff0; myParamSetup[3].aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1); myParamSetup[3].dstAddr = (Uint32)dstBuff0; myParamSetup[3].srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup[3].linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParam66,0); myParamSetup[3].srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup[3].cCnt = 1; / Enable channel / status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \ NULL); if (status != CSL_SOK) { printf("Edma channel enable command failed\n"); return; } / Initialize the parameter entries using IDMA. Parameter entries are writtn * linearly start with parameter entry 64. As soon as the last word in * entry 67 is written the transfer gets triggered. / IDMA0_init(IDMA_INT_EN); IDMA0_configArgs(0x00000000, (Uint32)myParamSetup,(Uint32)hParam64, 0); IDMA0_wait(); regionIntr.region = CSL_EDMA3_REGION_GLOBAL; / Poll on IPR bit / do { CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr); } while (!(regionIntr.intr & 0x8)); / Clear interrupt / status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \ &regionIntr); if (status != CSL_SOK) { printf("Edma interrrupt clear command failed\n"); return; } / Check transfer by comparing the source and destination buffers / if(Verify_Transfer( 64, 1, 1, 0, 0, 0, 0, srcBuff0, dstBuff0,TRUE) == FALSE) passStatus = 0; if(Verify_Transfer( 64, 1, 1, 0, 0, 0, 0, srcBuff1, dstBuff1,TRUE) == FALSE) passStatus = 0; if(Verify_Transfer( 64, 1, 1, 0, 0, 0, 0, srcBuff2, dstBuff2,TRUE) == FALSE) passStatus = 0; if(Verify_Transfer( 64, 1, 1, 0, 0, 0, 0, srcBuff3, dstBuff3,TRUE) == FALSE) passStatus = 0; if (passStatus == 1) printf ("<<EXAMPLE PASSED>>: Qdma Link Transfer Passed\n"); else { printf ("<<EXAMPLE FAILED>>: Qdma Link Transfer Failed\n"); return; } / Disable the channel / status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_DISABLE, \ NULL); / Close channel / status = CSL_edma3ChannelClose(hChannel); if (status != CSL_SOK) { printf("Edma channel close failed\n"); return; } / Close edma module */ status = CSL_edma3Close(hModule); if (status != CSL_SOK) { printf("Edma module close failed\n"); return; } printf ("=============================================================\n"); return; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcOpen.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_intcOpen.c * * @brief File for functional layer of CSL API CSL_intcOpen() * * PATH $(CSLPATH)\src\intc / / ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= / #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /* ============================================================================ * @n@b CSL_intcOpen * * @b Description * @n The API would reserve an interrupt-event for use. It returns * a valid handle to the event only if the event is not currently * allocated. The user could release the event after use by calling * CSL_intcClose(..) * * @b Arguments * @verbatim pIntcObj Pointer to the CSL-object allocated by the user eventId The event-id of the interrupt param Pointer to the Intc specific parameter pStatus Pointer for returning status of the function call @endverbatim * * <b> Return Value </b> CSL_IntcHandle * @n Valid INTC handle identifying the event * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n 1. INTC object structure is populated * @n 2. The status is returned in the status variable. If status * returned is * @li CSL_SOK Valid intc handle is returned * @li CSL_ESYS_FAIL The open command failed * * @b Modifies * @n 1. The status variable * @n 2. INTC object structure * * @b Example: * @verbatim CSL_IntcObj intcObj20; CSL_IntcGlobalEnableState state; CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; context.numEvtEntries = 0; context.eventhandlerRecord = NULL; // Init Module CSL_intcInit(&context); // NMI Enable CSL_intcGlobalNmiEnable(); // Enable Global Interrupts intStat = CSL_intcGlobalEnable(&state); // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL); // Close handle CSL_IntcClose(hIntc20); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_intcOpen, ".text:csl_section:intc"); CSL_IntcHandle CSL_intcOpen ( CSL_IntcObj intcObj, CSL_IntcEventId eventId, CSL_IntcParam param, CSL_Status status ) { CSL_IntcHandle hIntc = (CSL_IntcHandle)CSL_INTC_BADHANDLE; CSL_Status openStatus; Uint32 evtId; Uint32 _yCo; Uint32 _xCo; evtId = (Uint32)(eventId); _yCo = evtId >> 5; /* _yCo co-ordinate / _xCo = 1 << (evtId & 0x1f); / _xCo co-ordinate / asm(" dint"); if (!(_CSL_intcAllocMask[_yCo] & _xCo)) { _CSL_intcAllocMask[_yCo] \|= _xCo; / set bit -> used / hIntc = intcObj; } asm(" rint"); if (hIntc != (CSL_IntcHandle)CSL_INTC_BADHANDLE) { intcObj->eventId = eventId; intcObj->vectId = ((CSL_IntcVectId)param); openStatus = CSL_SOK; / Do the Mapping for the Event -> CPU Interrupt / if (((CSL_IntcVectId)param) < ((Uint32)(CSL_INTC_VECTID_COMBINE))) { CSL_intcMapEventVector(eventId,param); if (eventId < 4) { switch (eventId) { case 0: CSL_intcHookIsr(((CSL_IntcVectId)param), \ _CSL_intcEvent0Dispatcher); break; case 1: CSL_intcHookIsr(((CSL_IntcVectId)param), \ _CSL_intcEvent1Dispatcher); break; case 2: CSL_intcHookIsr(((CSL_IntcVectId)param), \ _CSL_intcEvent2Dispatcher); break; case 3: CSL_intcHookIsr(((CSL_IntcVectId)param), \ _CSL_intcEvent3Dispatcher); break; } } } } else openStatus = CSL_ESYS_FAIL; if (status) { *status = openStatus; } return hIntc; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_mcbspAux.h	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / / ============================================================================ * @file csl_mcbspAux.h * * @path $(CSLPATH)\inc * * @desc Header file for functional layer of CSL_mcbspAux * / / ============================================================================ * Revision History * =============== * 15-Feb-2005 NSR File Created from CSL_mcbspHwControl.c * And CSL_mcbspGetHwStatus.c. * 17-May-2005 RMathew - Removed CSL_mcbspIdleControl() and added inlines * for Transmit and receive interrupt mode commands and * queries * 27-Oct-2005 ds - Removed CSL_mcbspGetPid () * * 01-Feb-2006 ds - Removed CSL_mcbspGetTxIntMode (), * CSL_mcbspGetRxIntMode (), CSL_mcbspTxIntMode () and * CSL_mcbspRxIntMode () APIs * ============================================================================ / #ifndef _CSL_MCBSPAUX_H_ #define _CSL_MCBSPAUX_H_ #include<csl_mcbsp.h> #ifdef __cplusplus extern "C" { #endif / * Status Query Functions of mcbsp. / / ============================================================================ * @n@b CSL_mcbspGetCurRxBlk * * @b Description * @n This function gets the current Receive Block. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n Mcbsp must be initialized and opened properly * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetCurRxBlk (hMcbsp, response); @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_mcbspGetCurRxBlk ( CSL_McbspHandle hMcbsp, void response ) { (CSL_McbspBlock )response = (CSL_McbspBlock) (CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_RCBLK)); } /* ============================================================================ * @n@b CSL_mcbspGetCurTxBlk * * @b Description * @n This function gets the current Transmit block. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n Mcbsp must be initialized and opened properly * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetCurTxBlk (hMcbsp, response); @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_mcbspGetCurTxBlk ( CSL_McbspHandle hMcbsp, void response ) { (CSL_McbspBlock )response = (CSL_McbspBlock)(CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_XCBLK)); } /* ============================================================================ * @n@b CSL_mcbspGetDevStatus * * @b Description * @n This function gets the transmit and receive status conditions. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n Mcbsp must be initialized and opened properly * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetDevStatus (hMcbsp, response); @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_mcbspGetDevStatus ( CSL_McbspHandle hMcbsp, void response ) { (CSL_BitMask16)response = (CSL_BitMask32) ((CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_RRDY)) \| (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_XRDY) << (1)) \| (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_RFULL) << (2)) \| (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_XEMPTY) << (3)) \| (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_RSYNCERR) << (4)) \| (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_XSYNCERR) << (5))); } /* ============================================================================ * @n@b CSL_mcbspGetTxRstStat * * @b Description * @n This function gets the transmit reset state. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n Mcbsp must be initialized and opened properly * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetTxRstStat (hMcbsp, response); @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_mcbspGetTxRstStat ( CSL_McbspHandle hMcbsp, void response ) { (CSL_McbspRstStat )response = (CSL_McbspRstStat)(CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_XRST)); } /* ============================================================================ * @n@b CSL_mcbspGetRxRstStat * * @b Description * @n This function gets the receive reset state. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * <b> Return Value </b> None * * <b> Pre Condition </b> * @n Mcbsp must be initialized and opened properly * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetRxRstStat (hMcbsp, response); @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_mcbspGetRxRstStat ( CSL_McbspHandle hMcbsp, void response ) { (CSL_McbspRstStat )response = (CSL_McbspRstStat) (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_RRST)); } #ifdef __cplusplus } #endif #endif /* CSL_MCBSPAUX_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/cache/src/Cache_example.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ============================================================================ / /* =========================================================================== * * @file Cache_example.c * * @path $(CSLPATH)\example\cache\src * * @desc Example of CACHE * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @n Usage of cache CSL API for the following operations * - Invalidate all L2 and L1D cache * - Write back invalidate all L2 and L1D cache * - Write back all L2 and L1D cache * - Invalidate the L2 and L1D cache * - Write back invalidate L2 and L1D cache * - Write back L2 and L1D cache * - L2 normal mode * - Freeze operation on L2 cache * * ============================================================================= * * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Cache_example.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================ * Revision History * =============== * 26-Jul-2005 ds File Created. * 08-Feb-2006 ds Changed during testing on EVM. Added EMIFB CE0 as a * device memory and supported DDR2 CSL to initialize and * setup EMIFB(DDR2) location. * * ============================================================================ / #include <stdio.h> #include <csl_cache.h> #include <_csl_cache.h> #include <csl_ddr2.h> #include <cslr_dev.h> / L1 and L2 Caching Memory area / #define CACHE_MEM (0xE0000000) / Globals variables used for storing the cache data / Uint32 temp; Uint32 Data_1; Uint32 Data_2; Uint32 Data_3; Uint32 Data_4; / Foraward declarations / void subExampleEndPrint(void); void exampleEndPrint (void); void init_ddr2 (void); void enableDdr2 (void); / * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= / void main(void) { Uint32 cacheExampleFail = 0; Uint16 loopCount; Uint16 count; CACHE_L2Size localSize[4]; / Initialize the DDR2 module / init_ddr2 (); / make sure L1P is turned off / CACHE_setL1pSize(CACHE_L1_0KCACHE); / make sure that L1D is turned off / CACHE_setL1dSize(CACHE_L1_0KCACHE); / make sure that L2 is turned off / CACHE_setL2Size(CACHE_0KCACHE); / Array used for setting L2 cache size / localSize[0] = CACHE_32KCACHE; localSize[1] = CACHE_64KCACHE; localSize[2] = CACHE_128KCACHE; localSize[3] = CACHE_256KCACHE; / This loop is used to display the L2 cache size while performing different * operations on different L2 cache sizes / for(loopCount = 0; loopCount <4; loopCount++) { switch(loopCount) { case 0: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 32K L2 cache.\n"); subExampleEndPrint(); break; case 1: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 64K L2 cache.\n"); subExampleEndPrint(); break; case 2: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 128K L2 cache.\n"); subExampleEndPrint(); break; case 3: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 256K L2 cache.\n"); subExampleEndPrint(); break; default: break; } for(count = 1; count <= 8; count++) { / set a memory location / (Uint32)CACHE_MEM = 0xABCDABCD; Data_2 = 0xa5a5a5a5; / set Mar bit for CACHE_MEM / CACHE_enableCaching(CACHE_EMIFB_CE00); / turn on the L2 cache. / CACHE_setL2Size( localSize[loopCount]); / read (allocate into cache) / Data_1 = (Uint32)CACHE_MEM; / write (dirty the cache line) / (Uint32)CACHE_MEM = Data_2; / Read the data back (make sure it matches Data_2 / Data_3 = (Uint32)CACHE_MEM; if(Data_2 != Data_3) printf("CACHE: Data read from cache is not same as \ data written.\n"); switch(count) { / Case #1 - invAllL2 / case 1: / Invalidate all the L2 cache / CACHE_invAllL2(CACHE_WAIT); for( temp =0 ; temp < 1000; temp++) {} / read, this data should match data_1 / Data_4 = (Uint32)CACHE_MEM; if(Data_1 != Data_4) { printf("CACHE: Invalidate the All L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Invalidate the All L2 cache Passed.\n"); } break; / Case #2 - wbInvAllL2 / case 2: / Writeback invalidate all the L2 cache / CACHE_wbInvAllL2(CACHE_WAIT); for( temp =0 ; temp < 1000; temp++) {} / read, this data should match data_2 / Data_4 = (Uint32)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back invalidate All"); printf("L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back invalidate All"); printf("L2 cache Passed.\n"); } break; / Case #3 wbAll / case 3: / Writeback all the L2 cache / CACHE_wbAllL2(CACHE_WAIT); for( temp =0 ; temp < 1000; temp++) {} / read, this data should match data_2 / Data_4 = (Uint32)CACHE_MEM; if(Data_2 != Data_4){ printf("CACHE: Write back All L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back All L2 cache Passed.\n"); } break; / Case #4 - invL2 / case 4: / Invalidate the L2 cache / CACHE_invL2((Uint32)CACHE_MEM, 4, CACHE_WAIT); /* read, this data should match data_1 / Data_4 = (Uint32)CACHE_MEM; if(Data_1 != Data_4) { printf("CACHE: Invalidate the L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Invalidate the L2 cache Passed.\n"); } break; / Case #5 - wbInv / case 5: / Writeback invalidate the L2 cache / CACHE_wbInvL2((Uint32)CACHE_MEM,1000, CACHE_WAIT); /* read, this data should match data_2 / Data_4 = (Uint32)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back invalidate"); printf(" L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back invalidate"); printf("L2 cache Passed.\n"); } break; / Case #6 wb / case 6: / Writeback L2 cache / CACHE_wbL2((Uint32)CACHE_MEM, 4, CACHE_WAIT); /* read, this data should match data_2 / Data_4 = (Uint32)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back L2 cache Passed.\n"); } break; / Case #6 wb / case 7: / Set L2 cache in normal mode / CACHE_setL2Mode(CACHE_L2_NORMAL); / read, this data should match data_3 / Data_4 = (Uint32)CACHE_MEM; if(Data_3 != Data_4) { printf("CACHE: L2 Normal Mode Failed.\n"); cacheExampleFail++; } else { printf("CACHE: L2 Normal Mode Passed.\n"); } break; case 8: / Writeback invalidate the cache / CACHE_wbInvAllL2(CACHE_WAIT); / freeze the cache / if(CACHE_setL2Mode(CACHE_L2_FREEZE) != CACHE_L2_NORMAL) {} / read, this would normally allocate space in the cache / temp = (Uint32)CACHE_MEM; (Uint32)CACHE_MEM = 0xABCDABCD; / write to external memory / (Uint32)CACHE_MEM =0xA5A5A5A5; if(CACHE_setL2Mode(CACHE_L2_NORMAL) != CACHE_L2_FREEZE) {} Data_4 = (Uint32)CACHE_MEM; / if the cache was frozen then the Data_4 should equal / if(Data_4 != 0xA5A5A5A5) { printf("CACHE: Freeze operation on Cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Freeze operation on Cache Passed.\n"); } break; default: break; } / L2 is turned off / CACHE_setL2Size(CACHE_0KCACHE); / disable caching for CE_00 / (Uint32) 0x01848380 = 0; } } subExampleEndPrint(); / Log the result./ if (cacheExampleFail > 0) { printf ("\nCACHE: Example on L2 cache FAILED. \ [Example Failed: %ld]\n", cacheExampleFail); } else { printf ("\nCACHE: Example on L2 cache PASSED\n"); } exampleEndPrint(); cacheExampleFail = 0; /========================================================================* * L1D * ========================================================================/ /* Array used for setting L1 cache size / localSize[0] = (CACHE_L2Size)CACHE_L1_4KCACHE; localSize[1] = (CACHE_L2Size)CACHE_L1_8KCACHE; localSize[2] = (CACHE_L2Size)CACHE_L1_16KCACHE; localSize[3] = (CACHE_L2Size)CACHE_L1_32KCACHE; / This loop is used to display the L1 cache size while performing different * operations on different L1 cache sizes / for(loopCount = 0; loopCount <4; loopCount++) { switch(loopCount) { case 0: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 4K L1 cache.\n"); subExampleEndPrint(); break; case 1: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 8K L1 cache.\n"); subExampleEndPrint(); break; case 2: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 16K L1 cache.\n"); subExampleEndPrint(); break; case 3: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 32K L1 cache.\n"); subExampleEndPrint(); break; default: break; } for(count = 1; count <= 6; count++) { / set a memory location / (Uint32)CACHE_MEM = 0xABCDABCD; Data_2 = 0xa5a5a5a5; / set Mar bit for CACHE_MEM / CACHE_enableCaching(CACHE_EMIFB_CE00); / turn on the L1D cache. / CACHE_setL1dSize( (CACHE_L1Size)localSize[loopCount]); / read (allocate into cache) / Data_1 = (Uint32)CACHE_MEM; / write (dirty the cache line) / (Uint32)CACHE_MEM = Data_2; / Read the data back (make sure it matches Data_2) / Data_3 = (Uint32)CACHE_MEM; if(Data_2 != Data_3) printf("CACHE: Data read from cache is not same as \ data written.\n"); switch(count) { / Case #1 - invAllL1D / case 1: / Invalidate all L1D cache / CACHE_invAllL1d(CACHE_WAIT); / read, this data should match data_1 / Data_4 = (Uint32)CACHE_MEM; if(Data_1 != Data_4) { printf("CACHE: Invalidate All L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Invalidate All L1D cache Passed.\n"); } break; / Case #2 - wbInvAllL1D / case 2: / Writeback invalidate all L1D cache / CACHE_wbInvAllL1d(CACHE_WAIT); / read, this data should match data_2 / Data_4 = (Uint32)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back invalidate All"); printf("L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back invalidate All"); printf(" L1D cache Passed.\n"); } break; / Case #3 wbAll / case 3: / Writeback all L1D cache / CACHE_wbAllL1d(CACHE_WAIT); / read, this data should match data_2 / Data_4 = (Uint32)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back All L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back All L1D cache Passed.\n"); } break; / Case #4 - invL1D / case 4: / Invalidate L1D cache / CACHE_invL1d((Uint32)CACHE_MEM,4, CACHE_WAIT); /* read, this data should match data_1 / Data_4 = (Uint32)CACHE_MEM; if(Data_1 != Data_4) { printf("CACHE: Invalidate L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Invalidate L1D cache Passed.\n"); } break; / Case #5 - wbInv / case 5: / Writeback invalidate L1D cache / CACHE_wbInvL1d((Uint32)CACHE_MEM,1000, CACHE_WAIT); /* read, this data should match data_2 / Data_4 = (Uint32)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back invalidate"); printf("L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back invalidate"); printf("L1D cache Passed\n"); } break; / Case #6 wb / case 6: / Writeback L1D cache / CACHE_wbL1d((Uint32)CACHE_MEM,1000, CACHE_WAIT); /* read, this data should match data_2 / Data_4 = (Uint32)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back L1D cache Passed.\n"); } break; default: break; } / L1D is turned off / CACHE_setL1dSize(CACHE_L1_0KCACHE); / disable caching for CE_00 / (Uint32) 0x01848380 = 0; } } subExampleEndPrint(); / Log the result./ if (cacheExampleFail > 0) { printf ("\nCACHE: Example on L1 cache FAILED. \ [Example Failed: %ld]\n", cacheExampleFail); } else { printf ("\nCACHE: Example on L1 cache PASSED\n"); } exampleEndPrint(); } / * ============================================================================ * @func init_ddr2 * * @desc * This function initialize and setup the DDR2 module * * @arg * None * * @return * None * ============================================================================ / void init_ddr2 (void) { CSL_Ddr2Handle hDdr2; CSL_Ddr2Obj ddr2Obj; CSL_Status status; CSL_Ddr2HwSetup hwSetup ; CSL_Ddr2Timing1 tim1 = {0x23, 0x4,0x4, 0x4, 0x0B, 0x0F, 0x2,0x2}; CSL_Ddr2Timing2 tim2 = {0x2, 0x25, 0xDC, 0x2, 0x04}; CSL_Ddr2Settings set = CSL_DDR2_SETTING_DEFAULTS; / setup the hardware parameters / hwSetup.refreshRate = 0x0000073B; hwSetup.timing1Param = &tim1; hwSetup.timing2Param = &tim2; hwSetup.setParam = &set; / Enable the DDR2 / enableDdr2 (); / Initialize DDR2 CSL module / status = CSL_ddr2Init(NULL); if (status != CSL_SOK) { printf("DDR2 EMIF: Initialization error.\n"); printf("\tReason: CSL_ddr2Init [status = 0x%x].\n", status); return; } / Opening the DDR2 instance / hDdr2 = CSL_ddr2Open(&ddr2Obj, CSL_DDR2, NULL, &status); if ((status != CSL_SOK) \|\| (hDdr2 == NULL)) { printf("DDR2 EMIF: Error opening the instance. [status = 0x%x, hDdr2 = \ 0x%x]\n", status, hDdr2); return; } / Setting up configuration parameter using HwSetup / status = CSL_ddr2HwSetup(hDdr2, &hwSetup); if (status != CSL_SOK) { printf("DDR2 EMIF: Error in HW Setup.\n"); printf("Read write operation fails\n"); return; } } / * ============================================================================ * @func enableDdr2 * * @desc * This function enables the powerSaver for DDR2 module * * @arg * None * * @return * None * ============================================================================ / void enableDdr2 (void) { / Unlock the PERCFG0 register / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the ddr2 / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERCFG1, DEV_PERCFG1_DDR2CTL, ENABLE); printf("Powersaver clock for DDR2 is enabled\n"); } void subExampleEndPrint (void) { printf ("*************************************************************\n"); } void exampleEndPrint (void) { printf ("=============================================================\n"); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/utopia2/csl_utopia2.c	<filename>DSP/TI-Header/csl_c6455_src/src/utopia2/csl_utopia2.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_utopia2.c * * @path $(CSLPATH)\src\utopia2 * * @desc This file contains the functions which are required to reset the * UTOPIA2. / #include "csl_utopia2.h" /****************************************************************************\ L O C A L S E C T I O N \*****************************************************************************/ / static macro declarations / / static typedef declarations / / static function declarations / / static variable definitions / / static function definitions / /****************************************************************************\ G L O B A L S E C T I O N \*****************************************************************************/ / global variable definitions / CSL_Utopia2Regs utopia2Regs = (CSL_Utopia2Regs ) CSL_UTOPIA2_0_REGS; / global function definitions / /* ============================================================================ * @n@b UTOPIA2_reset * * @b Description * @n This function resets UTOPIA2 Control Register and sets the Clock Detect * Register. * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n UTOPIA2 registers * * @b Example * @verbatim ... UTOPIA2_reset() ... @endverbatim * ============================================================================= / void UTOPIA2_reset ( void ) { Uint32 cs; cs = _disable_interrupts(); utopia2Regs->UCR = UTOPIA2_UCR_DEFAULT; utopia2Regs->CDR = UTOPIA2_CDR_DEFAULT; _restore_interrupts(cs); } / End of csl_utopia2.c */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_ddr2.h	<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_ddr2.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for DDR2 / #ifndef _CSLR_DDR2_H_ #define _CSLR_DDR2_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint32 MIDR; volatile Uint32 DMCSTAT; volatile Uint32 SDCFG; volatile Uint32 SDRFC; volatile Uint32 SDTIM1; volatile Uint32 SDTIM2; volatile Uint8 RSVD0[8]; volatile Uint32 BPRIO; volatile Uint8 RSVD1[192]; volatile Uint32 DMCCTL; } CSL_Ddr2Regs; /***********************************************************************\ Overlay structure typedef definition \*************************************************************************/ typedef volatile CSL_Ddr2Regs CSL_Ddr2RegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / MIDR / #define CSL_DDR2_MIDR_MOD_ID_MASK (0x3FFF0000u) #define CSL_DDR2_MIDR_MOD_ID_SHIFT (0x00000010u) #define CSL_DDR2_MIDR_MOD_ID_RESETVAL (0x00000031u) #define CSL_DDR2_MIDR_MJ_REV_MASK (0x0000FF00u) #define CSL_DDR2_MIDR_MJ_REV_SHIFT (0x00000008u) #define CSL_DDR2_MIDR_MJ_REV_RESETVAL (0x00000003u) #define CSL_DDR2_MIDR_MN_REV_MASK (0x000000FFu) #define CSL_DDR2_MIDR_MN_REV_SHIFT (0x00000000u) #define CSL_DDR2_MIDR_MN_REV_RESETVAL (0x0000000Fu) #define CSL_DDR2_MIDR_RESETVAL (0x0031030Fu) / DMCSTAT / #define CSL_DDR2_DMCSTAT_BE_MASK (0x80000000u) #define CSL_DDR2_DMCSTAT_BE_SHIFT (0x0000001Fu) #define CSL_DDR2_DMCSTAT_BE_RESETVAL (0x00000000u) /----BE Tokens----/ #define CSL_DDR2_DMCSTAT_BE_B_ENDIAN (0x00000001u) #define CSL_DDR2_DMCSTAT_BE_L_ENDIAN (0x00000000u) #define CSL_DDR2_DMCSTAT_IFRDY_MASK (0x00000004u) #define CSL_DDR2_DMCSTAT_IFRDY_SHIFT (0x00000002u) #define CSL_DDR2_DMCSTAT_IFRDY_RESETVAL (0x00000000u) /----IFRDY Tokens----/ #define CSL_DDR2_DMCSTAT_IFRDY_NOTREADY (0x00000000u) #define CSL_DDR2_DMCSTAT_IFRDY_READY (0x00000001u) #define CSL_DDR2_DMCSTAT_RESETVAL (0x40000000u) / SDCFG / #define CSL_DDR2_SDCFG_BOOT_UNLOCK_MASK (0x00800000u) #define CSL_DDR2_SDCFG_BOOT_UNLOCK_SHIFT (0x00000017u) #define CSL_DDR2_SDCFG_BOOT_UNLOCK_RESETVAL (0x00000000u) /----BOOT_UNLOCK Tokens----/ #define CSL_DDR2_SDCFG_BOOT_UNLOCK_LOCKED (0x00000000u) #define CSL_DDR2_SDCFG_BOOT_UNLOCK_UNLOCKED (0x00000001u) #define CSL_DDR2_SDCFG_DDR_DRIVE_MASK (0x00040000u) #define CSL_DDR2_SDCFG_DDR_DRIVE_SHIFT (0x00000012u) #define CSL_DDR2_SDCFG_DDR_DRIVE_RESETVAL (0x00000000u) /----DDR_DRIVE Tokens----/ #define CSL_DDR2_SDCFG_DDR_DRIVE_NORMAL (0x00000000u) #define CSL_DDR2_SDCFG_DDR_DRIVE_WEAK (0x00000001u) #define CSL_DDR2_SDCFG_TIMUNLOCK_MASK (0x00008000u) #define CSL_DDR2_SDCFG_TIMUNLOCK_SHIFT (0x0000000Fu) #define CSL_DDR2_SDCFG_TIMUNLOCK_RESETVAL (0x00000000u) /----TIMUNLOCK Tokens----/ #define CSL_DDR2_SDCFG_TIMUNLOCK_CLEAR (0x00000000u) #define CSL_DDR2_SDCFG_TIMUNLOCK_SET (0x00000001u) #define CSL_DDR2_SDCFG_NM_MASK (0x00004000u) #define CSL_DDR2_SDCFG_NM_SHIFT (0x0000000Eu) #define CSL_DDR2_SDCFG_NM_RESETVAL (0x00000000u) /----NM Tokens----/ #define CSL_DDR2_SDCFG_NM_32BIT (0x00000000u) #define CSL_DDR2_SDCFG_NM_16BIT (0x00000001u) #define CSL_DDR2_SDCFG_CL_MASK (0x00000E00u) #define CSL_DDR2_SDCFG_CL_SHIFT (0x00000009u) #define CSL_DDR2_SDCFG_CL_RESETVAL (0x00000005u) /----CL Tokens----/ #define CSL_DDR2_SDCFG_CL_TWO (0x00000002u) #define CSL_DDR2_SDCFG_CL_THREE (0x00000003u) #define CSL_DDR2_SDCFG_CL_FOUR (0x00000004u) #define CSL_DDR2_SDCFG_CL_FIVE (0x00000005u) #define CSL_DDR2_SDCFG_IBANK_MASK (0x00000070u) #define CSL_DDR2_SDCFG_IBANK_SHIFT (0x00000004u) #define CSL_DDR2_SDCFG_IBANK_RESETVAL (0x00000002u) /----IBANK Tokens----/ #define CSL_DDR2_SDCFG_IBANK_ONE (0x00000000u) #define CSL_DDR2_SDCFG_IBANK_TWO (0x00000001u) #define CSL_DDR2_SDCFG_IBANK_FOUR (0x00000002u) #define CSL_DDR2_SDCFG_IBANK_EIGHT (0x00000003u) #define CSL_DDR2_SDCFG_PAGESIZE_MASK (0x00000007u) #define CSL_DDR2_SDCFG_PAGESIZE_SHIFT (0x00000000u) #define CSL_DDR2_SDCFG_PAGESIZE_RESETVAL (0x00000000u) /----PAGESIZE Tokens----/ #define CSL_DDR2_SDCFG_PAGESIZE_256W_PAGE (0x00000000u) #define CSL_DDR2_SDCFG_PAGESIZE_512W_PAGE (0x00000001u) #define CSL_DDR2_SDCFG_PAGESIZE_1024W_PAGE (0x00000002u) #define CSL_DDR2_SDCFG_PAGESIZE_2048W_PAGE (0x00000003u) #define CSL_DDR2_SDCFG_RESETVAL (0x00530A20u) / SDRFC / #define CSL_DDR2_SDRFC_SR_MASK (0x80000000u) #define CSL_DDR2_SDRFC_SR_SHIFT (0x0000001Fu) #define CSL_DDR2_SDRFC_SR_RESETVAL (0x00000000u) /----SR Tokens----/ #define CSL_DDR2_SDRFC_SR_EXIT (0x00000000u) #define CSL_DDR2_SDRFC_SR_ENTER (0x00000001u) #define CSL_DDR2_SDRFC_REFRESH_RATE_MASK (0x0000FFFFu) #define CSL_DDR2_SDRFC_REFRESH_RATE_SHIFT (0x00000000u) #define CSL_DDR2_SDRFC_REFRESH_RATE_RESETVAL (0x00000753u) #define CSL_DDR2_SDRFC_RESETVAL (0x00000753u) / SDTIM1 / #define CSL_DDR2_SDTIM1_T_RFC_MASK (0xFE000000u) #define CSL_DDR2_SDTIM1_T_RFC_SHIFT (0x00000019u) #define CSL_DDR2_SDTIM1_T_RFC_RESETVAL (0x0000003Fu) #define CSL_DDR2_SDTIM1_T_RP_MASK (0x01C00000u) #define CSL_DDR2_SDTIM1_T_RP_SHIFT (0x00000016u) #define CSL_DDR2_SDTIM1_T_RP_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM1_T_RCD_MASK (0x00380000u) #define CSL_DDR2_SDTIM1_T_RCD_SHIFT (0x00000013u) #define CSL_DDR2_SDTIM1_T_RCD_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM1_T_WR_MASK (0x00070000u) #define CSL_DDR2_SDTIM1_T_WR_SHIFT (0x00000010u) #define CSL_DDR2_SDTIM1_T_WR_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM1_T_RAS_MASK (0x0000F800u) #define CSL_DDR2_SDTIM1_T_RAS_SHIFT (0x0000000Bu) #define CSL_DDR2_SDTIM1_T_RAS_RESETVAL (0x0000001Fu) #define CSL_DDR2_SDTIM1_T_RC_MASK (0x000007C0u) #define CSL_DDR2_SDTIM1_T_RC_SHIFT (0x00000006u) #define CSL_DDR2_SDTIM1_T_RC_RESETVAL (0x0000001Fu) #define CSL_DDR2_SDTIM1_T_RRD_MASK (0x00000038u) #define CSL_DDR2_SDTIM1_T_RRD_SHIFT (0x00000003u) #define CSL_DDR2_SDTIM1_T_RRD_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM1_T_WTR_MASK (0x00000003u) #define CSL_DDR2_SDTIM1_T_WTR_SHIFT (0x00000000u) #define CSL_DDR2_SDTIM1_T_WTR_RESETVAL (0x00000003u) #define CSL_DDR2_SDTIM1_RESETVAL (0x7FFFFFFBu) / SDTIM2 / #define CSL_DDR2_SDTIM2_T_ODT_MASK (0x01800000u) #define CSL_DDR2_SDTIM2_T_ODT_SHIFT (0x00000017u) #define CSL_DDR2_SDTIM2_T_ODT_RESETVAL (0x00000003u) #define CSL_DDR2_SDTIM2_T_SXNR_MASK (0x007F0000u) #define CSL_DDR2_SDTIM2_T_SXNR_SHIFT (0x00000010u) #define CSL_DDR2_SDTIM2_T_SXNR_RESETVAL (0x0000007Fu) #define CSL_DDR2_SDTIM2_T_SXRD_MASK (0x0000FF00u) #define CSL_DDR2_SDTIM2_T_SXRD_SHIFT (0x00000008u) #define CSL_DDR2_SDTIM2_T_SXRD_RESETVAL (0x000000FFu) #define CSL_DDR2_SDTIM2_T_RTP_MASK (0x000000E0u) #define CSL_DDR2_SDTIM2_T_RTP_SHIFT (0x00000005u) #define CSL_DDR2_SDTIM2_T_RTP_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM2_T_CKE_MASK (0x0000001Fu) #define CSL_DDR2_SDTIM2_T_CKE_SHIFT (0x00000000u) #define CSL_DDR2_SDTIM2_T_CKE_RESETVAL (0x0000001Fu) #define CSL_DDR2_SDTIM2_RESETVAL (0x01FFFFFFu) / BPRIO / #define CSL_DDR2_BPRIO_PRIO_RAISE_MASK (0x000000FFu) #define CSL_DDR2_BPRIO_PRIO_RAISE_SHIFT (0x00000000u) #define CSL_DDR2_BPRIO_PRIO_RAISE_RESETVAL (0x000000FFu) #define CSL_DDR2_BPRIO_RESETVAL (0x000000FFu) / DMCCTL / #define CSL_DDR2_DMCCTL_IFRESET_MASK (0x00000020u) #define CSL_DDR2_DMCCTL_IFRESET_SHIFT (0x00000005u) #define CSL_DDR2_DMCCTL_IFRESET_RESETVAL (0x00000001u) /----IFRESET Tokens----*/ #define CSL_DDR2_DMCCTL_IFRESET_RELEASE (0x00000000u) #define CSL_DDR2_DMCCTL_IFRESET_ASSERT (0x00000001u) #define CSL_DDR2_DMCCTL_RL_MASK (0x00000007u) #define CSL_DDR2_DMCCTL_RL_SHIFT (0x00000000u) #define CSL_DDR2_DMCCTL_RL_RESETVAL (0x00000007u) #define CSL_DDR2_DMCCTL_RESETVAL (0x50006427u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_tcp2Aux.h	<filename>DSP/TI-Header/csl_c6455_src/inc/csl_tcp2Aux.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_tcp2Aux.h * * @path $(CSLPATH)\tcp2\inc * * @desc Auxiliary API header file for TCP CSL * / / ============================================================================= * Revision History * =============== * 26-Mar-2005 sd File Created. * 21-Jul-2005 sd Updated for the requirement changes * 15-Sep-2005 sd Changed TCP to TCP2 in all the names * 30-Jan-2006 sd Updated the descriptions for TCP2_normalCeil and TCP2_ceil * and chnages for the bit field names TCPEND register * ============================================================================= / #ifndef _CSL_TCP2AUX_H_ #define _CSL_TCP2AUX_H_ #ifdef __cplusplus extern "C" { #endif #include <tistdtypes.h> #include <cslr_tcp2.h> #include <csl_tcp2.h> /* ============================================================================ * @n@b TCP2_normalCeil * * @b Description * @n Returns the value rounded to the nearest integer greater than or * equal to (val1/val2) * * @b Arguments @verbatim val1 Value to be augmented. val2 Value by which val1 must be divisible. @endverbatim * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 framelen = 51200; Uint32 numSubFrame; ... // to calculate the number of sub frames for SP mode numSubFrame = TCP2_normalCeil (framelen, TCP2_SUB_FRAME_SIZE_MAX); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_normalCeil ( Uint32 val1, Uint32 val2 ) { Uint32 x; / x = ceil(val1/val2) / / val1 is increased (if necessary) to be a multiple of val2 / x = (((val1) % (val2)) != 0) ? (((val1) / (val2)) + 1) : ((val1) / (val2)); return(x); } /* ============================================================================ * @n@b TCP2_ceil * * @b Description * @n Returns the value rounded to the nearest integer greater than or * equal to (val/(2^pwr2)). * * @b Arguments @verbatim val Value to be augmented. pwr2 The power of two by which val must be divisible. @endverbatim * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 val1 = 512; Uint32 val2 = 4; Uint32 val3; val3 = TCP2_ceil(val1, val2); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_ceil ( Uint32 val, Uint32 pwr2 ) { Uint32 x; / x = ceil(val/ (2^pwr2)) / / val is increased (if necessary) to be a multiple of 2^pwr2 / x = (((val) - (((val) >> (pwr2)) << (pwr2))) == 0) ? \ ((val) >> (pwr2)): (((val) >> (pwr2)) + 1); return(x); } /* ============================================================================ * @n@b TCP2_setExtScaling * * @b Description * @n This function formats individual bytes into a 32-bit word, which is * used to set the extrinsic configuration registers. * * @b Arguments @verbatim extrVal1 extrinsic scaling value 1 extrVal2 extrinsic scaling value 2 extrVal3 extrinsic scaling value 3 extrVal4 extrinsic scaling value 4 @endverbatim * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim TCP2_Params configParams; TCP2_IcConfig configIc configIc->ic12 = TCP2_setExtScaling (configParams->extrScaling [0], configParams->extrScaling [1], configParams->extrScaling [2], configParams->extrScaling [3]); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_setExtScaling ( Uint8 extrVal1, Uint8 extrVal2, Uint8 extrVal3, Uint8 extrVal4 ) { Uint32 icConfigVal; icConfigVal = (extrVal4 << 18) \| (extrVal3 << 12) \| (extrVal2 << 6) \| (extrVal1); return icConfigVal; } /* ============================================================================ * @n@b TCP2_makeTailArgs * * @b Description * @n This function formats individual bytes into a 32-bit word, which is * used to set the tail bits configuration registers. * * @b Arguments @verbatim byte17_12 Byte to be placed in bits 17-12 of the 32-bit value byte11_6 Byte to be placed in bits 11-6 of the 32-bit value byte5_0 Byte to be placed in bits 5-0 of the 32-bit value @endverbatim * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim TCP2_Params configParams; TCP2_IcConfig configIc configIc.ic6 = TCP2_makeTailArgs (xabData[10], xabData[8], xabData[6]); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_makeTailArgs ( Uint8 byte17_12, Uint8 byte11_6, Uint8 byte5_0 ) { Uint32 x = 0; x = (byte17_12 << 12) \| (byte11_6 << 6) \| byte5_0; return(x); } /* ============================================================================ * @n@b TCP2_getAccessErr * * @b Description * @n This function returns the ACC bit value of the TCPERR register * indicating whether an invalid access has been made to the TCP during * operation. * @n 0 - no error * @n 1 - TCP rams (syst, parities, hard decisions, extrinsics, aprioris) * access is not allowed in state 1. This causes an error interrupt * to occur * * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getAccessErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getAccessErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_ACC); } /* ============================================================================ * @n@b TCP2_getErr * * @b Description * @n This function returns the ERR bit value of the TCPERR register * indicating whether an error has occurred during TCP operation. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_ERR); } /* ============================================================================ * @n@b TCP2_getTcpErrors * * @b Description * @n This function returns the TCPERR register value. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getTcpErrors ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getTcpErrors ( void ) { return (tcp2Regs->TCPERR); } /* ============================================================================ * @n@b TCP2_getFrameLenErr * * @b Description * @n This function returns a boolean value indicating whether an invalid * frame length has been programmed in the TCP during operation. * @n 0 - no error. * @n 1 - (SA mode) frame length < 40 or frame length > 20730. * - (SP mode) frame length < 256 or frame length > 20480 and f%256!=0 * for the first or middle subframes. * - (SP mode) if f<128 or f>20480 for the last subframe. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getFrameLenErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getFrameLenErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_F); } /* ============================================================================ * @n@b TCP2_getProlLenErr * * @b Description * @n This function returns the P bit value indicating whether an invalid * prolog length has been programmed into the TCP. * 0 - no error * 1 - Prolog length < 4 or > 48 * * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getProlLenErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getProlLenErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_P); } /* ============================================================================ * @n@b TCP2_getSubFrameErr * * @b Description * @n This function returns a boolean value indicating whether the sub-frame * length programmed into the TCP is invalid. * 0 - no error * 1 - sub-frame length > 20480 (SP mode) * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getSubFrameErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getSubFrameErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_SF); } /* ============================================================================ * @n@b TCP2_getRelLenErr * * @b Description * @n This function returns the R bit value indicating whether an invalid * reliability length has been programmed into the TCP. The reliability * length must be 40 < RL < 128 for SA Mode, or * SW_R must = 128 during First/Middle subframes of SP mode, and * SW_R must be > 64 in the Last subframe. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getRelLenErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getRelLenErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_R); } /* ============================================================================ * @n@b TCP2_getSnrErr * * @b Description * @n This function returns the SNR bit value indicating whether the SNR * threshold exceeded 100 (1) or not (0). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getSnrErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getSnrErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_SNR); } /* ============================================================================ * @n@b TCP2_getInterleaveErr * * @b Description * @n This function returns the INTER value bit indicating whether the TCP * was incorrectly programmed to receive an interleaver table. An * interleaver table can only be sent when operating in standalone mode. * This bit(1) indicates if an interleaver table was sent when in shared * processing mode. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getInterleaveErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getInterleaveErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_INT); } /* ============================================================================ * @n@b TCP2_getOutParmErr * * @b Description * @n This function returns the OP bit value (1) indicating whether the TCP was * programmed to transfer output parameters in shared processing mode. * The output parameters are only valid when operating in standalone mode. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getOutParmErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getOutParmErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_OP); } /* ============================================================================ * @n@b TCP2_getMaxMinErr * * @b Description * @n This function returns the MAXMINITER bit value indicating whether the * TCP was programmed with the minimum iterations value greater than the * maximum iterations. * 0 = no error, 1 = min_iter > max_iter * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getMaxMinErr ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getMaxMinErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_MAXMINITER); } /* ============================================================================ * @n@b TCP2_getNumIt * * @b Description * @n This function returns the number of decoded iterations of the TCP in * standalone processing mode. This function reads the output parameters * register. Alternatively, the EDMA can be used to transfer the output * parameters following the hard decisions (recommended). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 numIter; numIter = TCP2_getNumIt (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getNumIt ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT0, TCP2_TCPOUT0_FINAL_ITER); } /* ============================================================================ * @n@b TCP2_getSnrM1 * * @b Description * @n This function returns the 1st moment of SNR calculation. This function * reads the output parameters register. Alternatively, the EDMA can be * used to transfer the output parameters following the hard decisions * (recommended). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 snrM1; snrM1 = TCP2_getSnrM1 (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getSnrM1 ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT0, TCP2_TCPOUT0_SNR_M1); } /* ============================================================================ * @n@b TCP2_getSnrM2 * * @b Description * @n This function returns the 2nd moment of SNR calculation. This function * reads the output parameters register. Alternatively, the EDMA can be * used to transfer the output parameters following the hard decisions * (recommended). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 snrM2; snrM2 = TCP2_getSnrM2 (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getSnrM2 ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT1, TCP2_TCPOUT1_SNR_M2); } /* ============================================================================ * @n@b TCP2_getMap * * @b Description * @n This function returns the active MAP of the TCP. * 0 - MAP 0 is active * 1 - MAP 1 is active * This function reads the output parameters register. Alternatively, * the EDMA can be used to transfer the output parameters following the * hard decisions (recommended). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 activeMap; activeMap = TCP2_getMap (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getMap ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT1, TCP2_TCPOUT1_ACTIVE_MAP); } /* ============================================================================ * @n@b TCP2_getMap0Err * * @b Description * @n This function returns the number of re-encode errors for MAP 0. * This function reads the output parameters register. Alternatively, * the EDMA can be used to transfer the output parameters following the * hard decisions (recommended). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 map0Err; map0Err = TCP2_getMap0Err (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getMap0Err ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT2, TCP2_TCPOUT2_CNT_RE_MAP0); } /* ============================================================================ * @n@b TCP2_getMap1Err * * @b Description * @n This function returns the number of re-encode errors for MAP 1. * This function reads the output parameters register. Alternatively, * the EDMA can be used to transfer the output parameters following the * hard decisions (recommended). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 map1Err; map1Err = TCP2_getMap1Err (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getMap1Err ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT2, TCP2_TCPOUT2_CNT_RE_MAP1); } /* ============================================================================ * @n@b TCP2_statRun * * @b Description * @n This function returns a boolean status indicating whether the TCP MAP * decoder is in state 0 or state 1-8 (running or not). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim while (!TCP2_statRun()); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statRun ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_DEC_BUSY); } /* ============================================================================ * @n@b TCP2_statError * * @b Description * @n This function returns the ERR bit value indicating whether any TCP * error has occurred. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statError ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statError ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ERR); } /* ============================================================================ * @n@b TCP2_statWaitIc * * @b Description * @n This function returns the WIC bit status indicating whether the TCP * is waiting to receive new IC values. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitIc ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statWaitIc ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_WIC); } /* ============================================================================ * @n@b TCP2_statWaitInter * * @b Description * @n This function returns the WINT status indicating whether the TCP is * waiting to receive interleaver table data. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitInter ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statWaitInter ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_WINT); } /* ============================================================================ * @n@b TCP2_statWaitSysPar * * @b Description * @n This function returns the WSP bit status indicating whether the TCP * is waiting to receive systematic and parity data. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitSysPar ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statWaitSysPar ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_WSP); } /* ============================================================================ * @n@b TCP2_statWaitApriori * * @b Description * @n This function returns the WAP bit status indicating whether the TCP is * waiting to receive apriori data. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitApriori ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statWaitApriori ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_WAP); } /* ============================================================================ * @n@b TCP2_statWaitExt * * @b Description * @n This function returns the REXT bit status indicating whether the TCP * is waiting for extrinsic data to be read. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitExt ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statWaitExt ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_REXT); } /* ============================================================================ * @n@b TCP2_statWaitHardDec * * @b Description * @n This function returns the RHD bit status indicating whether the TCP * is waiting for the hard decisions data to be read. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitHardDec ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statWaitHardDec ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_RHD); } /* ============================================================================ * @n@b TCP2_statWaitOutParm * * @b Description * @n This function returns the ROP bit status indicating whether the TCP * is waiting for the output parameters to be read. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitOutParm ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statWaitOutParm ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ROP); } /* ============================================================================ * @n@b TCP2_statEmuHalt * * @b Description * @n This function returns the emuhalt bit status indicating whether the * TCP is halted due to emulation. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statEmuHalt ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statEmuHalt ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_EMUHALT); } /* ============================================================================ * @n@b TCP2_statActMap * * @b Description * @n This function returns the active_map bit status indicating whether * the TCP MAP 0 is active (0) or the TCP MAP 1 is active (1). * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 activeMap; ..... activeMap = TCP2_statActMap (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statActMap ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ACTIVE_MAP); } /* ============================================================================ * @n@b TCP2_statActState * * @b Description * @n This function returns the active_state bit status indicating the * active TCP MAP decoder state. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 activeState; ..... activeState = TCP2_statActState (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statActState ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ACTIVE_STATE); } /* ============================================================================ * @n@b TCP2_statActIter * * @b Description * @n This function returns the active_iter bit status indicating the * active TCP iteration. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 activeIter; ..... activeIter = TCP2_statActIter (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statActIter ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ACTIVE_ITER); } /* ============================================================================ * @n@b TCP2_statSnr * * @b Description * @n This function returns the snr_exceed bits, indicating whether the * TCP MAP 0 or MAP 1 passed the SNR criteria in a particular iteration. * 0 - All fail * 1 - MAP 1 failed * 2 - MAP 0 failed * 3 - All passed * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 snrExceed; ..... snrExceed = TCP2_statSnr (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statSnr ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_SNR_EXCEED); } /* ============================================================================ * @n@b TCP2_statCrc * * @b Description * @n This function returns the crc_pass bit boolean status indicating whether * the TCP passed CRC check. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statCrc ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statCrc ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_CRC_PASS); } /* ============================================================================ * @n@b TCP2_statTcpState * * @b Description * @n This function returns the state of the TCP state machine for * the standalone mode or shared processing mode. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 tcpState; .... tcpState = TCP2_statTcpState (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_statTcpState ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_TCP_STATE); } /* ============================================================================ * @n@b TCP2_getExecStatus * * @b Description * @n This function returns the TCPSTAT register value. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 tcpStatus; tcpStatus = TCP2_getExecStatus (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getExecStatus ( void ) { return (tcp2Regs->TCPSTAT); } /* ============================================================================ * @n@b TCP2_getExtEndian * * @b Description * @n This function returns the value programmed into the TCP_END register * for the extrinsics data indicating whether the data is in its native * 8-bit format ('1') or consists of values packed in little endian format * into 32-bit words ('0'). This should always be '0' for little endian * operation. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getExtEndian ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getExtEndian ( void ) { return CSL_FEXT (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_EXTR); } /* ============================================================================ * @n@b TCP2_getInterEndian * * @b Description * @n Returns the value programmed into the TCP_END register for the * interleaver table data indicating whether the data is in its native * 8-bit format ('1') or consists of values packed in little endian format * into 32-bit words ('0'). This should always be '0' for little endian * operation. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getInterEndian ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getInterEndian ( void ) { return CSL_FEXT (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_INTR); } /* ============================================================================ * @n@b TCP2_getSlpzvss * * @b Description * @n This function gets the configuration of the internal control of * the slpzvss. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getSlpzvss ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getSlpzvss ( void ) { return CSL_FEXT (tcp2Regs->TCPEND, TCP2_TCPEND_SLPZVSS_EN); } /* ============================================================================ * @n@b TCP2_getSlpzvdd * * @b Description * @n This function gets the configuration of the internal control of * the slpzvdd. * * @b Arguments * @n None * * <b> Return Value </b> Uint32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getSlpzvdd ()){ ... } @endverbatim * ============================================================================= / CSL_IDEF_INLINE Uint32 TCP2_getSlpzvdd ( void ) { return CSL_FEXT (tcp2Regs->TCPEND, TCP2_TCPEND_SLPZVDD_EN); } /* ============================================================================ * @n@b TCP2_setExtEndian * * @b Description * @n This function programs TCP to view the format of the extrinsics data * as either native 8-bit format ('1') or values packed into 32-bit words * in little endian format ('0'). This should always be '0' for little * endian operation. * * @b Arguments @verbatim endianMode Endian setting for extrinsics data @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCPEND register bit for the extrinsics data is configured in the * mode passed. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setExtEndian (1); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_setExtEndian ( Uint32 endianMode ) { CSL_FINS (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_EXTR, endianMode); return; } /* ============================================================================ * @n@b TCP2_setInterEndian * * @b Description * @n This function programs TCP to view the format of the interleaver data * as either native 8-bit format ('1') or values packed into 32-bit words * in little endian format ('0'). This should always be '0' for little * endian operation. * * @b Arguments @verbatim endianMode Endian setting for interleaver data @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCPEND register bit for the interleaver data is configured in the * mode passed. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setInterEndian (1); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_setInterEndian ( Uint32 endianMode ) { CSL_FINS (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_INTR, endianMode); return; } /* ============================================================================ * @n@b TCP2_setNativeEndian * * @b Description * @n This function programs the TCP to view the format of all data as * native 8/16 bit format. This should only be used when running in * big endian mode. * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCPEND register configured to native mode for all data. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setNativeEndian (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_setNativeEndian ( void ) { CSL_FINST (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_INTR, NATIVE16); CSL_FINST (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_EXTR, NATIVE8); return; } /* ============================================================================ * @n@b TCP2_setPacked32Endian * * @b Description * @n This function programs the TCP to view the format of all data as * packed data in 32-bit words. This should always be used when running * in little endian mode and should be used in big endian mode only if * the CPU is formatting the data. * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCPEND register configured to packed 32 mode for all data. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setPacked32Endian (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_setPacked32Endian ( void ) { CSL_FINST (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_INTR, 32BITS); CSL_FINST (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_EXTR, 32BITS); return; } /* ============================================================================ * @n@b TCP2_start * * @b Description * @n This function starts the TCP by writing a 1 to the EXEINST field * of the TCPEXE register. See also TCP2_debug(), TCP2_debugStep() and * TCP2_debugComplete(). * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCP state machine starts executing. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_start (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_start ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, START); return; } /* ============================================================================ * @n@b TCP2_debug * * @b Description * @n This function puts the TCP into debug mode by writing '4h' to the * EXEINST field of the TCPEXE register. Normal initialization is * performed and TCP waits in MAP state 0 for Debug Step or Debug Complete * to be performed. See also TCP2_start(), TCP2_debugStep() and * TCP2_debugComplete() * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n EXEINST feild of the TCPEXE register is configured with the value passed. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_debug (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_debug ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, DEBUG0); return; } /* ============================================================================ * @n@b TCP2_debugStep * * @b Description * @n This function executes one MAP decode and waits in state 6 when the * TCP is in Debug mode, by writing '5h' to the EXEINST field of the * TCPEXE register. See also TCP2_start(), TCP2_debug() and * TCP2_debugComplete() * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n EXEINST feild of the TCPEXE register is configured with the value passed. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_debugStep (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_debugStep ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, DEBUG6); return; } /* ============================================================================ * @n@b TCP2_debugComplete * * @b Description * @n This function executes the remaing MAP decodes when the TCP is in * Debug mode, by writing '6h' to the EXEINST field of the TCPEXE register. * See also TCP2_start(), TCP2_debug() and TCP2_debugComplete() * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n EXEINST feild of the TCPEXE register is configured with the value passed. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_debugComplete (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_debugComplete ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, DEBUG); return; } /* ============================================================================ * @n@b TCP2_reset * * @b Description * @n This function performs a soft reset of all TCP registers except for * TCPEXE and TCPEND registers. * * @b Arguments * @n None * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n performs soft reset of TCP. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_reset (); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_reset ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, SOFTRESET); return; } /* ============================================================================ * @n@b TCP2_setSlpzvdd * * @b Description * @n This function enables/disables the internal control of the slpzvdd. * * @b Arguments @verbatim slpzvddCtrl enable/disable configuration of the slpzvdd @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCPEND register configured with the value passed. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setSlpzvdd (1); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_setSlpzvdd ( Uint32 slpzvddCtrl ) { CSL_FINS (tcp2Regs->TCPEND, TCP2_TCPEND_SLPZVDD_EN, slpzvddCtrl); return; } /* ============================================================================ * @n@b TCP2_setSlpzvss * * @b Description * @n This function enables/disables the internal control of the slpzvss. * * @b Arguments @verbatim slpzvssCtrl enable/disable configuration of the slpzvss @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCPEND register configured with the value passed. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setSlpzvss (1); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_setSlpzvss ( Uint32 slpzvssCtrl ) { CSL_FINS (tcp2Regs->TCPEND, TCP2_TCPEND_SLPZVSS_EN, slpzvssCtrl); return; } /* ============================================================================ * @n@b TCP2_getIcConfig * * @b Description * @n This function reads the input configuration values currently programmed * into the TCP. * * @b Arguments @verbatim config TCP configuration structure to hold the read values @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n config structure contains the TCP input configuration values. * * @b Modifies * @n None * * @b Example * @verbatim TCP2_getIcConfig (&config); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_getIcConfig ( TCP2_ConfigIc config ) { Uint32 gie; gie = _disable_interrupts (); config->ic0 = tcp2CfgRegs->TCPIC0; config->ic1 = tcp2CfgRegs->TCPIC1; config->ic2 = tcp2CfgRegs->TCPIC2; config->ic3 = tcp2CfgRegs->TCPIC3; config->ic4 = tcp2CfgRegs->TCPIC4; config->ic5 = tcp2CfgRegs->TCPIC5; config->ic6 = tcp2CfgRegs->TCPIC6; config->ic7 = tcp2CfgRegs->TCPIC7; config->ic8 = tcp2CfgRegs->TCPIC8; config->ic9 = tcp2CfgRegs->TCPIC9; config->ic10 = tcp2CfgRegs->TCPIC10; config->ic11 = tcp2CfgRegs->TCPIC11; config->ic12 = tcp2CfgRegs->TCPIC12; config->ic13 = tcp2CfgRegs->TCPIC13; config->ic14 = tcp2CfgRegs->TCPIC14; config->ic15 = tcp2CfgRegs->TCPIC15; _restore_interrupts (gie); } /** ============================================================================ * @n@b TCP2_icConfig * * @b Description * @n Programs the TCP with the input configuration values passed in the * TCP2_ConfigIc structure. This is not the recommended means by which to * program the TCP, as it is more efficient to transfer the IC values using * the EDMA. * * @b Arguments @verbatim config TCP configuration structure containing the values to be programmed @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCP input configuration registers are programmed with the values passed. * * @b Modifies * @n None * * @b Example * @verbatim TCP2_ConfigIc configIc; configIc.ic0 = 0x00283300; configIc.ic1 = 0x00270000; configIc.ic2 = 0x00080118; configIc.ic3 = 0x00000011; configIc.ic4 = 0x00000100; configIc.ic5 = 0x00000000; configIc.ic6 = 0x00032c2f; configIc.ic7 = 0x00027831; configIc.ic8 = 0x00000000; configIc.ic9 = 0x00018430; configIc.ic10 = 0x0003bfcd; configIc.ic11 = 0x00000000; configIc.ic12 = 0x00820820; configIc.ic13 = 0x00820820; configIc.ic14 = 0x00820820; configIc.ic15 = 0x00820820; TCP2_icConfig (&config); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_icConfig ( TCP2_ConfigIc config ) { Uint32 gie; gie = _disable_interrupts (); tcp2CfgRegs->TCPIC0 = config->ic0; tcp2CfgRegs->TCPIC1 = config->ic1; tcp2CfgRegs->TCPIC2 = config->ic2; tcp2CfgRegs->TCPIC3 = config->ic3; tcp2CfgRegs->TCPIC4 = config->ic4; tcp2CfgRegs->TCPIC5 = config->ic5; tcp2CfgRegs->TCPIC6 = config->ic6; tcp2CfgRegs->TCPIC7 = config->ic7; tcp2CfgRegs->TCPIC8 = config->ic8; tcp2CfgRegs->TCPIC9 = config->ic9; tcp2CfgRegs->TCPIC10 = config->ic10; tcp2CfgRegs->TCPIC11 = config->ic11; tcp2CfgRegs->TCPIC12 = config->ic12; tcp2CfgRegs->TCPIC13 = config->ic13; tcp2CfgRegs->TCPIC14 = config->ic14; tcp2CfgRegs->TCPIC15 = config->ic15; _restore_interrupts (gie); } /** ============================================================================ * @n@b TCP2_icConfigArgs * * @b Description * @n Programs the TCP with the input configuration values passed. This is * not the recommended means by which to program the TCP, as it is more * efficient to transfer the IC values using the EDMA. * * @b Arguments @verbatim ic0 TCP input configuration register 0 value ic1 TCP input configuration register 1 value ic2 TCP input configuration register 2 value ic3 TCP input configuration register 3 value ic4 TCP input configuration register 4 value ic5 TCP input configuration register 5 value ic6 TCP input configuration register 6 value ic7 TCP input configuration register 7 value ic8 TCP input configuration register 8 value ic9 TCP input configuration register 9 value ic10 TCP input configuration register 10 value ic11 TCP input configuration register 11 value ic12 TCP input configuration register 12 value ic13 TCP input configuration register 13 value ic14 TCP input configuration register 14 value ic15 TCP input configuration register 15 value @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n TCP input configuration registers are programmed with the values passed. * * @b Modifies * @n None * * @b Example * @verbatim Uint32 ic0, ic1, ic2, ic3, ic4, ic5, ic6, ic7, ic8, ic9 , ic10, ic11, ic12, ic13, ic14, ic15; ic0 = 0x00283300; ic1 = 0x00270000; ic2 = 0x00080118; ic3 = 0x00000011; ic4 = 0x00000100; ic5 = 0x00000000; ic6 = 0x00032c2f; ic7 = 0x00027831; ic8 = 0x00000000; ic9 = 0x00018430; ic10 = 0x0003bfcd; ic11 = 0x00000000; ic12 = 0x00820820; ic13 = 0x00820820; ic14 = 0x00820820; ic15 = 0x00820820; TCP2_icConfigArgs (ic0, ic1, ic2, ic3, ic4, ic5, ic6, ic7, ic8, ic9, ic10, ic11, ic12, ic13, ic14, ic15); @endverbatim * ============================================================================= / CSL_IDEF_INLINE void TCP2_icConfigArgs ( Uint32 ic0, Uint32 ic1, Uint32 ic2, Uint32 ic3, Uint32 ic4, Uint32 ic5, Uint32 ic6, Uint32 ic7, Uint32 ic8, Uint32 ic9, Uint32 ic10, Uint32 ic11, Uint32 ic12, Uint32 ic13, Uint32 ic14, Uint32 ic15 ) { Uint32 gie; gie = _disable_interrupts (); tcp2CfgRegs->TCPIC0 = ic0; tcp2CfgRegs->TCPIC1 = ic1; tcp2CfgRegs->TCPIC2 = ic2; tcp2CfgRegs->TCPIC3 = ic3; tcp2CfgRegs->TCPIC4 = ic4; tcp2CfgRegs->TCPIC5 = ic5; tcp2CfgRegs->TCPIC6 = ic6; tcp2CfgRegs->TCPIC7 = ic7; tcp2CfgRegs->TCPIC8 = ic8; tcp2CfgRegs->TCPIC9 = ic9; tcp2CfgRegs->TCPIC10 = ic10; tcp2CfgRegs->TCPIC11 = ic11; tcp2CfgRegs->TCPIC12 = ic12; tcp2CfgRegs->TCPIC13 = ic13; tcp2CfgRegs->TCPIC14 = ic14; tcp2CfgRegs->TCPIC15 = ic15; _restore_interrupts (gie); } #ifdef __cplusplus } #endif #endif / _CSL_TCP2AUX_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/cslr_memprot_L1D.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_memprot_L1D.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for MEMPROTL1D / #ifndef _CSLR_MEMPROT_L1D_H_ #define _CSLR_MEMPROT_L1D_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \*************************************************************************/ typedef struct { volatile Uint32 MPFAR; volatile Uint32 MPFSR; volatile Uint32 MPFCR; volatile Uint8 RSVD0[244]; volatile Uint32 MPLK0; volatile Uint32 MPLK1; volatile Uint32 MPLK2; volatile Uint32 MPLK3; volatile Uint32 MPLKCMD; volatile Uint32 MPLKSTAT; volatile Uint8 RSVD1[232]; volatile Uint32 MPPA[32]; } CSL_Memprotl1dRegs; typedef volatile CSL_Memprotl1dRegs CSL_Memprotl1dRegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / MPFAR / #define CSL_MEMPROTL1D_MPFAR_ADDR_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPFAR_ADDR_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPFAR_ADDR_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFAR_RESETVAL (0x00000000u) / MPFSR / #define CSL_MEMPROTL1D_MPFSR_FID_MASK (0x0000FE00u) #define CSL_MEMPROTL1D_MPFSR_FID_SHIFT (0x00000009u) #define CSL_MEMPROTL1D_MPFSR_FID_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_LOCAL_MASK (0x00000100u) #define CSL_MEMPROTL1D_MPFSR_LOCAL_SHIFT (0x00000008u) #define CSL_MEMPROTL1D_MPFSR_LOCAL_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_SR_MASK (0x00000020u) #define CSL_MEMPROTL1D_MPFSR_SR_SHIFT (0x00000005u) #define CSL_MEMPROTL1D_MPFSR_SR_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_SW_MASK (0x00000010u) #define CSL_MEMPROTL1D_MPFSR_SW_SHIFT (0x00000004u) #define CSL_MEMPROTL1D_MPFSR_SW_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_UR_MASK (0x00000004u) #define CSL_MEMPROTL1D_MPFSR_UR_SHIFT (0x00000002u) #define CSL_MEMPROTL1D_MPFSR_UR_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_UW_MASK (0x00000002u) #define CSL_MEMPROTL1D_MPFSR_UW_SHIFT (0x00000001u) #define CSL_MEMPROTL1D_MPFSR_UW_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_RESETVAL (0x00000000u) / MPFCR / #define CSL_MEMPROTL1D_MPFCR_MPFCLR_MASK (0x00000001u) #define CSL_MEMPROTL1D_MPFCR_MPFCLR_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPFCR_MPFCLR_RESETVAL (0x00000000u) /----MPFCLR Tokens----/ #define CSL_MEMPROTL1D_MPFCR_MPFCLR_CLEAR (0x00000001u) #define CSL_MEMPROTL1D_MPFCR_RESETVAL (0x00000000u) / MPLK0 / #define CSL_MEMPROTL1D_MPLK0_RESERVED_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPLK0_RESERVED_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLK0_RESERVED_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPLK0_RESETVAL (0x00000000u) / MPLK1 / #define CSL_MEMPROTL1D_MPLK1_RESERVED_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPLK1_RESERVED_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLK1_RESERVED_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPLK1_RESETVAL (0x00000000u) / MPLK2 / #define CSL_MEMPROTL1D_MPLK2_RESERVED_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPLK2_RESERVED_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLK2_RESERVED_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPLK2_RESETVAL (0x00000000u) / MPLK3 / #define CSL_MEMPROTL1D_MPLK3_RESERVED_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPLK3_RESERVED_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLK3_RESERVED_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPLK3_RESETVAL (0x00000000u) / MPLKCMD / #define CSL_MEMPROTL1D_MPLKCMD_KEYR_MASK (0x00000004u) #define CSL_MEMPROTL1D_MPLKCMD_KEYR_SHIFT (0x00000002u) #define CSL_MEMPROTL1D_MPLKCMD_KEYR_RESETVAL (0x00000000u) /----KEYR Tokens----/ #define CSL_MEMPROTL1D_MPLKCMD_KEYR_YES (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_KEYR_NO (0x00000000u) #define CSL_MEMPROTL1D_MPLKCMD_LOCK_MASK (0x00000002u) #define CSL_MEMPROTL1D_MPLKCMD_LOCK_SHIFT (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_LOCK_RESETVAL (0x00000000u) /----LOCK Tokens----/ #define CSL_MEMPROTL1D_MPLKCMD_LOCK_YES (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_LOCK_NO (0x00000000u) #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_MASK (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_RESETVAL (0x00000000u) /----UNLOCK Tokens----/ #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_YES (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_NO (0x00000000u) #define CSL_MEMPROTL1D_MPLKCMD_RESETVAL (0x00000000u) / MPLKSTAT / #define CSL_MEMPROTL1D_MPLKSTAT_LK_MASK (0x00000001u) #define CSL_MEMPROTL1D_MPLKSTAT_LK_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLKSTAT_LK_RESETVAL (0x00000000u) /----LK Tokens----/ #define CSL_MEMPROTL1D_MPLKSTAT_LK_YES (0x00000001u) #define CSL_MEMPROTL1D_MPLKSTAT_LK_NO (0x00000000u) #define CSL_MEMPROTL1D_MPLKSTAT_RESETVAL (0x00000000u) / MPPA / #define CSL_MEMPROTL1D_MPPA_AID5_MASK (0x00008000u) #define CSL_MEMPROTL1D_MPPA_AID5_SHIFT (0x0000000Fu) #define CSL_MEMPROTL1D_MPPA_AID5_RESETVAL (0x00000001u) /----AID5 Tokens----/ #define CSL_MEMPROTL1D_MPPA_AID5_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID5_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID4_MASK (0x00004000u) #define CSL_MEMPROTL1D_MPPA_AID4_SHIFT (0x0000000Eu) #define CSL_MEMPROTL1D_MPPA_AID4_RESETVAL (0x00000001u) /----AID4 Tokens----/ #define CSL_MEMPROTL1D_MPPA_AID4_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID4_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID3_MASK (0x00002000u) #define CSL_MEMPROTL1D_MPPA_AID3_SHIFT (0x0000000Du) #define CSL_MEMPROTL1D_MPPA_AID3_RESETVAL (0x00000001u) /----AID3 Tokens----/ #define CSL_MEMPROTL1D_MPPA_AID3_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID3_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID2_MASK (0x00001000u) #define CSL_MEMPROTL1D_MPPA_AID2_SHIFT (0x0000000Cu) #define CSL_MEMPROTL1D_MPPA_AID2_RESETVAL (0x00000001u) /----AID2 Tokens----/ #define CSL_MEMPROTL1D_MPPA_AID2_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID2_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID1_MASK (0x00000800u) #define CSL_MEMPROTL1D_MPPA_AID1_SHIFT (0x0000000Bu) #define CSL_MEMPROTL1D_MPPA_AID1_RESETVAL (0x00000001u) /----AID1 Tokens----/ #define CSL_MEMPROTL1D_MPPA_AID1_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID1_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID0_MASK (0x00000400u) #define CSL_MEMPROTL1D_MPPA_AID0_SHIFT (0x0000000Au) #define CSL_MEMPROTL1D_MPPA_AID0_RESETVAL (0x00000001u) /----AID0 Tokens----/ #define CSL_MEMPROTL1D_MPPA_AID0_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID0_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_ADX_MASK (0x00000200u) #define CSL_MEMPROTL1D_MPPA_ADX_SHIFT (0x00000009u) #define CSL_MEMPROTL1D_MPPA_ADX_RESETVAL (0x00000001u) /----ADX Tokens----/ #define CSL_MEMPROTL1D_MPPA_ADX_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_ADX_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_LOCAL_MASK (0x00000100u) #define CSL_MEMPROTL1D_MPPA_LOCAL_SHIFT (0x00000008u) #define CSL_MEMPROTL1D_MPPA_LOCAL_RESETVAL (0x00000001u) /----LOCAL Tokens----/ #define CSL_MEMPROTL1D_MPPA_LOCAL_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_LOCAL_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_SR_MASK (0x00000020u) #define CSL_MEMPROTL1D_MPPA_SR_SHIFT (0x00000005u) #define CSL_MEMPROTL1D_MPPA_SR_RESETVAL (0x00000001u) /----SR Tokens----/ #define CSL_MEMPROTL1D_MPPA_SR_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_SR_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_SW_MASK (0x00000010u) #define CSL_MEMPROTL1D_MPPA_SW_SHIFT (0x00000004u) #define CSL_MEMPROTL1D_MPPA_SW_RESETVAL (0x00000001u) /----SW Tokens----/ #define CSL_MEMPROTL1D_MPPA_SW_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_SW_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_UR_MASK (0x00000004u) #define CSL_MEMPROTL1D_MPPA_UR_SHIFT (0x00000002u) #define CSL_MEMPROTL1D_MPPA_UR_RESETVAL (0x00000001u) /----UR Tokens----/ #define CSL_MEMPROTL1D_MPPA_UR_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_UR_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_UW_MASK (0x00000002u) #define CSL_MEMPROTL1D_MPPA_UW_SHIFT (0x00000001u) #define CSL_MEMPROTL1D_MPPA_UW_RESETVAL (0x00000001u) /----UW Tokens----*/ #define CSL_MEMPROTL1D_MPPA_UW_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_UW_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_RESETVAL (0x0000FFF6u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_pllcAux.h	<filename>DSP/TI-Header/csl_c6455_src/inc/csl_pllcAux.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* @file csl_pllcAux.h * * @brief API Auxilary header file for PLLC CSL. * * Path: \(CSLPATH)\inc / / ============================================================================ * Revision History * =============== * 10-Feb-2004 kpn File Created. * 25-Aug-2005 Tej File Modified. * 27-oct-2005 sd changes for multiplier configuration * 18-Jan-2006 sd Changes according to spec changes * ============================================================================ / #ifndef _CSL_PPLCAUX_H_ #define _CSL_PLLCAUX_H_ #include <csl_pllc.h> #ifdef __cplusplus extern "C" { #endif / * Status command functions of the pllc / /* ============================================================================ * @n@b CSL_pllcGetStatus * * @b Description * @n Gets the Status of the pll controller. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance @endverbatim * * <b> Return Value </b> * @n CSL_BitMask32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 response; ... response = CSL_pllcGetStatus (hPllc); @endverbatim * ============================================================================ / CSL_IDEF_INLINE CSL_BitMask32 CSL_pllcGetStatus ( CSL_PllcHandle hPllc ) { CSL_BitMask32 response; response = (CSL_BitMask32) hPllc->regs->PLLSTAT; return response; } / * Status command functions of the pllc / /* ============================================================================ * @n@b CSL_pllcGetSysClkStatus * * @b Description * @n Gets the System Clock ON/OFF Status of the pllc. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance @endverbatim * * <b> Return Value </b> * @n CSL_BitMask32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 response; ... response = CSL_pllcGetSysClkStatus (hPllc); @endverbatim * ============================================================================ / CSL_IDEF_INLINE CSL_BitMask32 CSL_pllcGetSysClkStatus ( CSL_PllcHandle hPllc ) { CSL_BitMask32 response; response = (CSL_BitMask32) hPllc->regs->SYSTAT; return response; } / * Status command functions of the pllc / /* ============================================================================ * @n@b CSL_pllcGetResetStatus * * @b Description * @n Gets the Reset Type Status of the pllc. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance @endverbatim * * <b> Return Value </b> * @n CSL_BitMask32 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 response; ... response = CSL_pllcGetResetStatus (hPllc); @endverbatim * ============================================================================ / CSL_IDEF_INLINE CSL_BitMask32 CSL_pllcGetResetStatus ( CSL_PllcHandle hPllc ) { CSL_BitMask32 response; response = (Uint32) hPllc->regs->RSTYPE; return response; } / * Control command functions of the pllc / /* ============================================================================ * @n@b CSL_pllcCommandCtrl * * @b Description * Controls the pllc operation. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc PLLCMD register status Status variable @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc operation is controlled according to value set. * * @b Modifies * @n pllc PLLCMD register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 loadVal; CSL_Status status ... CSL_pllcCommandCtrl (hPllc, loadVal, &status); @endverbatim * ============================================================================ / CSL_IDEF_INLINE void CSL_pllcCommandCtrl ( CSL_PllcHandle hPllc, CSL_BitMask32 loadVal, CSL_Status status ) { if (hPllc->pllcNum == CSL_PLLC_1) { hPllc->regs->PLLCTL = (loadVal & 0xFFFF); loadVal = (loadVal & 0xFFFF0000)>>16; if (loadVal) hPllc->regs->PLLCMD = loadVal; } else if (hPllc->pllcNum == CSL_PLLC_2) { loadVal = (loadVal & 0xFFFF0000)>>16; if (loadVal) hPllc->regs->PLLCMD = loadVal; } else status = CSL_ESYS_INVPARAMS; } /* ============================================================================ * @n@b CSL_pllcMultiplierCtrl * * @b Description * Controls the pllc Multiplier. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc PLLM register status Status variable @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc multiplier is controlled accordingly. * * @b Modifies * @n pllc PLLM register. * * @b Example * @verbatim CSL_PllcHandle hPllc; Uint32 loadVal; CSL_Status status ... CSL_pllcMultiplierCtrl (hPllc, loadVal, &status); @endverbatim * ============================================================================ / CSL_IDEF_INLINE void CSL_pllcMultiplierCtrl ( CSL_PllcHandle hPllc, Uint32 loadVal, CSL_Status status ) { if (hPllc->pllcNum == CSL_PLLC_1) CSL_FINS (hPllc->regs->PLLM, PLLC_PLLM_PLLM, loadVal - 1); else status = CSL_ESYS_INVPARAMS; } /* ============================================================================ * @n@b CSL_pllcSetPLLDivRatio * * @b Description * Sets the pllc Dividers ratios. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc divider registers status Status variable @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc dividers ratios are set. * * @b Modifies * @n pllc divider registers. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcDivRatio loadVal; CSL_Status status; ... CSL_pllcSetPLLDivRatio (hPllc, loadVal, &status); @endverbatim * ============================================================================ / CSL_IDEF_INLINE void CSL_pllcSetPLLDivRatio ( CSL_PllcHandle hPllc, CSL_PllcDivRatio loadVal, CSL_Status status ) { switch (loadVal.divNum) { case CSL_PLLC_DIVSEL_PLLDIV1: if (hPllc->pllcNum == CSL_PLLC_2) { CSL_FINS (hPllc->regs->PLLDIV1, PLLC_PLLDIV1_RATIO, (Uint32)loadVal.divRatio - 1); } else status = CSL_ESYS_INVPARAMS; break; case CSL_PLLC_DIVSEL_PLLDIV4: if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLDIV4, PLLC_PLLDIV4_RATIO, (Uint32)loadVal.divRatio - 1); } else status = CSL_ESYS_INVPARAMS; break; case CSL_PLLC_DIVSEL_PLLDIV5: if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLDIV5, PLLC_PLLDIV5_RATIO, (Uint32)loadVal.divRatio - 1); } else status = CSL_ESYS_INVPARAMS; break; default: status = CSL_ESYS_INVPARAMS; break; } } /** ============================================================================ * @n@b CSL_pllcPLLDivCtrl * * @b Description * Controls the pllc dividers. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc dividers register. status Status variable @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc dividers are controlled. * * @b Modifies * @n pllc dividers register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcDivideControl loadVal; CSL_Status status; ... CSL_pllcPLLDivCtrl (hPllc, loadVal, &status); @endverbatim * ============================================================================ / CSL_IDEF_INLINE void CSL_pllcPLLDivCtrl ( CSL_PllcHandle hPllc, CSL_PllcDivideControl loadVal, CSL_Status status ) { switch (loadVal.divNum) { case CSL_PLLC_DIVSEL_PLLDIV1: if (hPllc->pllcNum == CSL_PLLC_2) { CSL_FINS (hPllc->regs->PLLDIV1, PLLC_PLLDIV1_D1EN, (CSL_PllcDivCtrl)loadVal.divCtrl); } else status = CSL_ESYS_INVPARAMS; break; case CSL_PLLC_DIVSEL_PLLDIV4: if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLDIV4, PLLC_PLLDIV4_D4EN, (CSL_PllcDivCtrl)loadVal.divCtrl); } else status = CSL_ESYS_INVPARAMS; break; case CSL_PLLC_DIVSEL_PLLDIV5: if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLDIV5, PLLC_PLLDIV5_D5EN, (CSL_PllcDivCtrl)loadVal.divCtrl); } else status = CSL_ESYS_INVPARAMS; break; default: status = CSL_ESYS_INVPARAMS; break; } } #ifdef __cplusplus } #endif #endif /* _CSL_PLLCAUX_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_edma3.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_edma3.h * * @path $(CSLPATH)\inc * * @desc Header file for functional layer CSL of EDMA * / /* @mainpage EDMA3 * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to detail the CSL APIs for the EDMA3 * Module. The CSL developer is expected to refer to this document * while designing APIs for the modules which use Edma module. Some of the * listed APIs may not be applicable to a given module. While other cases * this list of APIs may not be sufficient to cover all the features required * for a particular Module. The CSL developer should use his discretion * designing new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * -# EDMA: Enhanced Direct Memory Access * * @subsection References * -# CSL 3.x Technical Requirements Specifications Version 0.5, dated * May 14th, 2003 * -# EDMA Channel Controller Specification (Revision 3.0.2) * -# EDMA Transfer Controller Specification (Revision 3.0.1) * * @subsection Assumptions * The abbreviations EDMA, edma and Edma have been used throughout this * document to refer to Enhanced Direct Memory Access. / / ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= / #ifndef _CSL_EDMA3_H_ #define _CSL_EDMA3_H_ #ifdef __cplusplus extern "C" { #endif #include <csl.h> #include <soc.h> #include <cslr_edma3cc.h> / EDMA Symbols Defined / /* Link to a Null Param set / #define CSL_EDMA3_LINK_NULL 0xFFFF /* Link to a Null Param set / #define CSL_EDMA3_LINK_DEFAULT 0xFFFF /* A synchronized transfer / #define CSL_EDMA3_SYNC_A 0 /* AB synchronized transfer / #define CSL_EDMA3_SYNC_AB 1 /* Normal Completion / #define CSL_EDMA3_TCC_NORMAL 0 /* Early Completion / #define CSL_EDMA3_TCC_EARLY 1 /* Only for ease / #define CSL_EDMA3_FIFOWIDTH_NONE 0 /* 8 bit FIFO Width / #define CSL_EDMA3_FIFOWIDTH_8BIT 0 /* 16 bit FIFO Width / #define CSL_EDMA3_FIFOWIDTH_16BIT 1 /* 32 bit FIFO Width / #define CSL_EDMA3_FIFOWIDTH_32BIT 2 /* 64 bit FIFO Width / #define CSL_EDMA3_FIFOWIDTH_64BIT 3 /* 128 bit FIFO Width / #define CSL_EDMA3_FIFOWIDTH_128BIT 4 /* 256 bit FIFO Width / #define CSL_EDMA3_FIFOWIDTH_256BIT 5 /* Address Mode is incremental / #define CSL_EDMA3_ADDRMODE_INCR 0 /* Address Mode is such it wraps around after reaching FIFO width / #define CSL_EDMA3_ADDRMODE_CONST 1 / Bitwise OR of the below symbols are used for setting the Memory attributes These are defined only if the Memory Protection feature exists / #if CSL_EDMA3_MEMPROTECT /* User Execute permission / #define CSL_EDMA3_MEMACCESS_UX 0x0001 /* User Write permission / #define CSL_EDMA3_MEMACCESS_UW 0x0002 /* User Read permission / #define CSL_EDMA3_MEMACCESS_UR 0x0004 /* Supervisor Execute permission / #define CSL_EDMA3_MEMACCESS_SX 0x0008 /* Supervisor Write permission / #define CSL_EDMA3_MEMACCESS_SW 0x0010 /* Supervisor Read permission / #define CSL_EDMA3_MEMACCESS_SR 0x0020 /* External Allowed ID. Requests with PrivID >= '6' are permitted * if access type is allowed / #define CSL_EDMA3_MEMACCESS_EXT 0x0200 /* Allowed ID '0' / #define CSL_EDMA3_MEMACCESS_AID0 0x0400 /* Allowed ID '1' / #define CSL_EDMA3_MEMACCESS_AID1 0x0800 /* Allowed ID '2' / #define CSL_EDMA3_MEMACCESS_AID2 0x1000 /* Allowed ID '3' / #define CSL_EDMA3_MEMACCESS_AID3 0x2000 /* Allowed ID '4' / #define CSL_EDMA3_MEMACCESS_AID4 0x4000 /* Allowed ID '5' / #define CSL_EDMA3_MEMACCESS_AID5 0x8000 #endif /* Intermediate transfer completion interrupt enable / #define CSL_EDMA3_ITCINT_EN 1 /* Intermediate transfer completion interrupt disable / #define CSL_EDMA3_ITCINT_DIS 0 /* Intermediate transfer completion chaining enable / #define CSL_EDMA3_ITCCH_EN 1 /* Intermediate transfer completion chaining disable / #define CSL_EDMA3_ITCCH_DIS 0 /* Transfer completion interrupt enable / #define CSL_EDMA3_TCINT_EN 1 /* Transfer completion interrupt disable / #define CSL_EDMA3_TCINT_DIS 0 /* Transfer completion chaining enable / #define CSL_EDMA3_TCCH_EN 1 /* Transfer completion chaining disable / #define CSL_EDMA3_TCCH_DIS 0 /* Enable Static / #define CSL_EDMA3_STATIC_EN 1 /* Disable Static / #define CSL_EDMA3_STATIC_DIS 0 /* Last trigger word in a QDMA parameter set / #define CSL_EDMA3_TRIGWORD_DEFAULT 7 /* Trigger word option field / #define CSL_EDMA3_TRIGWORD_OPT 0 /* Trigger word source / #define CSL_EDMA3_TRIGWORD_SRC 1 /* Trigger word AB count / #define CSL_EDMA3_TRIGWORD_A_B_CNT 2 /* Trigger word destination / #define CSL_EDMA3_TRIGWORD_DST 3 /* Trigger word src and dst B index / #define CSL_EDMA3_TRIGWORD_SRC_DST_BIDX 4 /* Trigger word B count reload / #define CSL_EDMA3_TRIGWORD_LINK_BCNTRLD 5 /* Trigger word src and dst C index / #define CSL_EDMA3_TRIGWORD_SRC_DST_CIDX 6 /* Trigger word C count / #define CSL_EDMA3_TRIGWORD_CCNT 7 /* Used for creating the options entry in the parameter ram / #define CSL_EDMA3_OPT_MAKE(itcchEn, tcchEn, itcintEn, tcintEn, tcc, tccMode, \ fwid, stat, syncDim, dam, sam) \ (Uint32)(\ CSL_FMKR(23,23,itcchEn) \ \|CSL_FMKR(22,22,tcchEn) \ \|CSL_FMKR(21,21,itcintEn) \ \|CSL_FMKR(20,20,tcintEn) \ \|CSL_FMKR(17,12,tcc) \ \|CSL_FMKR(11,11,tccMode) \ \|CSL_FMKR(10,8,fwid) \ \|CSL_FMKR(3,3,stat) \ \|CSL_FMKR(2,2,syncDim) \ \|CSL_FMKR(1,1,dam) \ \|CSL_FMKR(0,0,sam)) /* Used for creating the A,B Count entry in the parameter ram / #define CSL_EDMA3_CNT_MAKE(aCnt,bCnt) \ (Uint32)(\ CSL_FMK(EDMA3CC_A_B_CNT_ACNT,aCnt) \ \|CSL_FMK(EDMA3CC_A_B_CNT_BCNT,bCnt)\ ) /* Used for creating the link and B count reload entry in the parameter ram / #define CSL_EDMA3_LINKBCNTRLD_MAKE(link,bCntRld) \ (Uint32)(\ CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK,(Uint32)link) \ \|CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD,bCntRld)\ ) /* Used for creating the B index entry in the parameter ram / #define CSL_EDMA3_BIDX_MAKE(src,dst) \ (Uint32)(\ CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX,(Uint32)dst) \ \|CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX,(Uint32)src)\ ) /* Used for creating the C index entry in the parameter ram / #define CSL_EDMA3_CIDX_MAKE(src,dst) \ (Uint32)(\ CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX,(Uint32)dst) \ \|CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX,(Uint32)src)\ ) /* DMA Channel Setup / #define CSL_EDMA3_DMACHANNELSETUP_DEFAULT { \ {CSL_EDMA3_QUE_0,0}, \ {CSL_EDMA3_QUE_0,1}, \ {CSL_EDMA3_QUE_0,2}, \ {CSL_EDMA3_QUE_0,3}, \ {CSL_EDMA3_QUE_0,4}, \ {CSL_EDMA3_QUE_0,5}, \ {CSL_EDMA3_QUE_0,6}, \ {CSL_EDMA3_QUE_0,7}, \ {CSL_EDMA3_QUE_0,8}, \ {CSL_EDMA3_QUE_0,9}, \ {CSL_EDMA3_QUE_0,10}, \ {CSL_EDMA3_QUE_0,11}, \ {CSL_EDMA3_QUE_0,12}, \ {CSL_EDMA3_QUE_0,13}, \ {CSL_EDMA3_QUE_0,14}, \ {CSL_EDMA3_QUE_0,15}, \ {CSL_EDMA3_QUE_0,16}, \ {CSL_EDMA3_QUE_0,17}, \ {CSL_EDMA3_QUE_0,18}, \ {CSL_EDMA3_QUE_0,19}, \ {CSL_EDMA3_QUE_0,20}, \ {CSL_EDMA3_QUE_0,21}, \ {CSL_EDMA3_QUE_0,22}, \ {CSL_EDMA3_QUE_0,23}, \ {CSL_EDMA3_QUE_0,24}, \ {CSL_EDMA3_QUE_0,25}, \ {CSL_EDMA3_QUE_0,26}, \ {CSL_EDMA3_QUE_0,27}, \ {CSL_EDMA3_QUE_0,28}, \ {CSL_EDMA3_QUE_0,29}, \ {CSL_EDMA3_QUE_0,30}, \ {CSL_EDMA3_QUE_0,31}, \ {CSL_EDMA3_QUE_0,32}, \ {CSL_EDMA3_QUE_0,33}, \ {CSL_EDMA3_QUE_0,34}, \ {CSL_EDMA3_QUE_0,35}, \ {CSL_EDMA3_QUE_0,36}, \ {CSL_EDMA3_QUE_0,37}, \ {CSL_EDMA3_QUE_0,38}, \ {CSL_EDMA3_QUE_0,39}, \ {CSL_EDMA3_QUE_0,40}, \ {CSL_EDMA3_QUE_0,41}, \ {CSL_EDMA3_QUE_0,42}, \ {CSL_EDMA3_QUE_0,43}, \ {CSL_EDMA3_QUE_0,44}, \ {CSL_EDMA3_QUE_0,45}, \ {CSL_EDMA3_QUE_0,46}, \ {CSL_EDMA3_QUE_0,47}, \ {CSL_EDMA3_QUE_0,48}, \ {CSL_EDMA3_QUE_0,49}, \ {CSL_EDMA3_QUE_0,50}, \ {CSL_EDMA3_QUE_0,51}, \ {CSL_EDMA3_QUE_0,52}, \ {CSL_EDMA3_QUE_0,53}, \ {CSL_EDMA3_QUE_0,54}, \ {CSL_EDMA3_QUE_0,55}, \ {CSL_EDMA3_QUE_0,56}, \ {CSL_EDMA3_QUE_0,57}, \ {CSL_EDMA3_QUE_0,58}, \ {CSL_EDMA3_QUE_0,59}, \ {CSL_EDMA3_QUE_0,60}, \ {CSL_EDMA3_QUE_0,61}, \ {CSL_EDMA3_QUE_0,62}, \ {CSL_EDMA3_QUE_0,63} \ } /* QDMA Channel Setup / #define CSL_EDMA3_QDMACHANNELSETUP_DEFAULT { \ {CSL_EDMA3_QUE_0,64,CSL_EDMA3_TRIGWORD_DEFAULT}, \ {CSL_EDMA3_QUE_0,65,CSL_EDMA3_TRIGWORD_DEFAULT}, \ {CSL_EDMA3_QUE_0,66,CSL_EDMA3_TRIGWORD_DEFAULT}, \ {CSL_EDMA3_QUE_0,67,CSL_EDMA3_TRIGWORD_DEFAULT} \ } /* @brief Enumeration for System priorities * * This is used for Setting up the Que Priority level / typedef enum { /* System priority level 0 / CSL_EDMA3_QUE_PRI_0 = 0, /* System priority level 1 / CSL_EDMA3_QUE_PRI_1 = 1, /* System priority level 2 / CSL_EDMA3_QUE_PRI_2 = 2, /* System priority level 3 / CSL_EDMA3_QUE_PRI_3 = 3, /* System priority level 4 / CSL_EDMA3_QUE_PRI_4 = 4, /* System priority level 5 / CSL_EDMA3_QUE_PRI_5 = 5, /* System priority level 6 / CSL_EDMA3_QUE_PRI_6 = 6, /* System priority level 7 / CSL_EDMA3_QUE_PRI_7 = 7 }CSL_Edma3QuePri; /* @brief Enumeration for EDMA Que Thresholds * * This is used for Setting up the Que thresholds / typedef enum { /* EDMA Que Threshold 0 / CSL_EDMA3_QUE_THR_0 = 0, /* EDMA Que Threshold 1 / CSL_EDMA3_QUE_THR_1 = 1, /* EDMA Que Threshold 2 / CSL_EDMA3_QUE_THR_2 = 2, /* EDMA Que Threshold 3 / CSL_EDMA3_QUE_THR_3 = 3, /* EDMA Que Threshold 4 / CSL_EDMA3_QUE_THR_4 = 4, /* EDMA Que Threshold 5 / CSL_EDMA3_QUE_THR_5 = 5, /* EDMA Que Threshold 6 / CSL_EDMA3_QUE_THR_6 = 6, /* EDMA Que Threshold 7 / CSL_EDMA3_QUE_THR_7 = 7, /* EDMA Que Threshold 8 / CSL_EDMA3_QUE_THR_8 = 8, /* EDMA Que Threshold 9 / CSL_EDMA3_QUE_THR_9 = 9, /* EDMA Que Threshold 10 / CSL_EDMA3_QUE_THR_10 = 10, /* EDMA Que Threshold 11 / CSL_EDMA3_QUE_THR_11 = 11, /* EDMA Que Threshold 12 / CSL_EDMA3_QUE_THR_12 = 12, /* EDMA Que Threshold 13 / CSL_EDMA3_QUE_THR_13 = 13, /* EDMA Que Threshold 14 / CSL_EDMA3_QUE_THR_14 = 14, /* EDMA Que Threshold 15 / CSL_EDMA3_QUE_THR_15 = 15, /* EDMA Que Threshold 16 / CSL_EDMA3_QUE_THR_16 = 16, / EDMA Que Threshold Disable Errors / CSL_EDMA3_QUE_THR_DISABLE = 17 }CSL_Edma3QueThr; /* MODULE Level Commands / typedef enum { #if CSL_EDMA3_MEMPROTECT /* * @brief Programmation of MPPAG,MPPA[0-7] attributes * * @param (CSL_Edma3CmdRegion ) / CSL_EDMA3_CMD_MEMPROTECT_SET, /** * @brief Clear Memory Fault * * @param (None) / CSL_EDMA3_CMD_MEMFAULT_CLEAR, #endif /* * @brief Enables bits as specified in the argument passed in * DRAE/DRAEH. Please note:If bits are already set in * DRAE/DRAEH this Control command will cause additional bits * (as specified by the bitmask) to be set and does * @param (CSL_Edma3CmdDrae ) / CSL_EDMA3_CMD_DMAREGION_ENABLE, /** * @brief Disables bits as specified in the argument passed in * DRAE/DRAEH * @param (CSL_Edma3CmdDrae ) / CSL_EDMA3_CMD_DMAREGION_DISABLE, /** * @brief Enables bits as specified in the argument * passed in QRAE.Pleasenote:If bits are already set in * QRAE/QRAEH this Control command will cause additional bits * (as specified by the bitmask) to be set and does * @param (CSL_Edma3CmdQrae ) / CSL_EDMA3_CMD_QDMAREGION_ENABLE, /** * @brief Disables bits as specified in the argument passed in QRAE * DRAE/DRAEH * @param (CSL_Edma3CmdQrae ) / CSL_EDMA3_CMD_QDMAREGION_DISABLE, /** * @brief Programmation of QUEPRI register with the specified priority * DRAE/DRAEH * @param (CSL_Edma3CmdQuePri ) / CSL_EDMA3_CMD_QUEPRIORITY_SET, /** * @brief Programmation of QUE Threshold levels * * @param (CSL_Edma3CmdQueThr ) / CSL_EDMA3_CMD_QUETHRESHOLD_SET, /** * @brief Sets the EVAL bit in the EEVAL register * * @param (None) / CSL_EDMA3_CMD_ERROR_EVAL, /* * @brief Clears specified (Bitmask)pending interrupt at Module/Region * Level * @param (CSL_Edma3CmdIntr ) / CSL_EDMA3_CMD_INTRPEND_CLEAR, /** * @brief Enables specified interrupts(BitMask) at Module/Region Level * * @param (CSL_Edma3CmdIntr ) / CSL_EDMA3_CMD_INTR_ENABLE, /** * @brief Disables specified interrupts(BitMask) at Module/Region * Level * @param (CSL_Edma3CmdIntr ) / CSL_EDMA3_CMD_INTR_DISABLE, /** * @brief Interrupt Evaluation asserted for the Module/Region * * @param (Int ) / CSL_EDMA3_CMD_INTR_EVAL, /** * @brief Clear the EDMA Controller Erorr * * @param (CSL_Edma3CtrlErrStat ) / CSL_EDMA3_CMD_CTRLERROR_CLEAR , /** * @brief Pointer to an array of 3 elements, where element0 refers to * the EMR register to be cleared, element1 refers to the EMRH * register to be cleared, element2 refers to the QEMR register * to be cleared. * @param (CSL_BitMask32 ) / CSL_EDMA3_CMD_EVENTMISSED_CLEAR } CSL_Edma3HwControlCmd; /** @brief MODULE Level Queries / typedef enum { #if CSL_EDMA3_MEMPROTECT /* * @brief Return the Memory fault details * * @param (CSL_Edma3MemFaultStat ) / CSL_EDMA3_QUERY_MEMFAULT, /** * @brief Return memory attribute of the specified region * * @param (CSL_Edma3CmdRegion ) / CSL_EDMA3_QUERY_MEMPROTECT, #endif /** * @brief Return Controller Error * * @param (CSL_Edma3CtrlErrStat ) / CSL_EDMA3_QUERY_CTRLERROR, /** * @brief Return pend status of specified interrupt * * @param (CSL_Edma3CmdIntr ) / CSL_EDMA3_QUERY_INTRPEND, /** * @brief Returns Miss Status of all Channels * Pointer to an array of 3 elements, where element0 refers to * the EMR registr, element1 refers to the EMRH register, * element2 refers to the QEMR register * @param (CSL_BitMask32 ) / CSL_EDMA3_QUERY_EVENTMISSED, /** * @brief Returns the Que status * * @param (CSL_Edma3QueStat ) / CSL_EDMA3_QUERY_QUESTATUS, /** * @brief Returns the Channel Controller Active Status * * @param (CSL_Edma3ActivityStat ) / CSL_EDMA3_QUERY_ACTIVITY, /** * @brief Returns the Channel Controller Information viz. * Configuration, Revision Id * @param (CSL_Edma3QueryInfo ) / CSL_EDMA3_QUERY_INFO } CSL_Edma3HwStatusQuery; /** @brief CHANNEL Commands / typedef enum { /* * @brief Enables specified Channel * * @param (None) / CSL_EDMA3_CMD_CHANNEL_ENABLE, /* * @brief Disables specified Channel * * @param (None) / CSL_EDMA3_CMD_CHANNEL_DISABLE, /* * @brief Manually sets the Channel Event,writes into ESR/ESRH * and not ER.NA for QDMA * @param (None) / CSL_EDMA3_CMD_CHANNEL_SET, /* * @brief Manually clears the Channel Event, does not write into * ESR/ESRH or ER/ERH but the ECR/ECRH. NA for QDMA * @param (None) / CSL_EDMA3_CMD_CHANNEL_CLEAR, /* * @brief In case of DMA channels clears SER/SERH(by writing into * SECR/SECRH if "secEvt" and "missed" are both TRUE) and * EMR/EMRH(by writing into EMCR/EMCRH if "missed" is TRUE). * In case of QDMA channels clears QSER(by writing into QSECR * if "ser" and "missed" are both TRUE) and QEMR(by writing * into QEMCR if "missed" is TRUE) * @param (CSL_Edma3ChannelErr ) / CSL_EDMA3_CMD_CHANNEL_CLEARERR } CSL_Edma3HwChannelControlCmd; /** @brief CHANNEL Queries / typedef enum { /* * @brief In case of DMA channels returns TRUE if ER/ERH is set, * In case of QDMA channels returns TRUE if QER is set * @param (Bool ) / CSL_EDMA3_QUERY_CHANNEL_STATUS, /** * @brief In case of DMA channels,'missed' is set * to TRUE if EMR/EMRH is set, 'secEvt' is set to TRUE if * SER/SERH is set.In case of QDMA channels,'missed' is set to * TRUE if QEMR is set, 'secEvt' is set to TRUE if QSER is set. * It should be noted that if secEvt ONLY is set to TRUE it * may not be a valid error condition * @param (CSL_Edma3ChannelErr ) / CSL_EDMA3_QUERY_CHANNEL_ERR } CSL_Edma3HwChannelStatusQuery; /** @brief Module specific context information. * This is a dummy handle. / typedef void CSL_Edma3Context; /** @brief Module Attributes specific information. * This is a dummy handle. / typedef void CSL_Edma3ModuleAttr; /** @brief This object contains the reference to the instance of Edma Module * opened using the @a CSL_edma3Open(). * * A pointer to this object is passed to all Edma Module level CSL APIs. / typedef struct CSL_Edma3Obj { /* This is a pointer to the Edma Channel Controller registers of the module * requested / CSL_Edma3ccRegsOvly regs; /* This is the instance of module number i.e CSL_EDMA3 / CSL_InstNum instNum; } CSL_Edma3Obj; /* @brief EDMA handle / typedef struct CSL_Edma3Obj CSL_Edma3Handle; /** CSL Parameter Set Handle / typedef volatile CSL_Edma3ccParamsetRegs CSL_Edma3ParamHandle; /** @brief Edma ParamSetup Structure * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3ParamSetup(). * This structure is used to program the Param Set for EDMA/QDMA. * The macros can be used to assign values to the fields of the structure. * The setup structure should be setup using the macros provided OR * as per the bit descriptions in the user guide.. * / typedef struct CSL_Edma3ParamSetup { /* Options / Uint32 option; /* Specifies the source address / Uint32 srcAddr; /* Lower 16 bits are A Count Upper 16 bits are B Count/ Uint32 aCntbCnt; /* Specifies the destination address / Uint32 dstAddr; /* Lower 16 bits are source b index Upper 16 bits are * destination b index / Uint32 srcDstBidx; /* Lower 16 bits are link of the next param entry Upper 16 bits are * b count reload / Uint32 linkBcntrld; /* Lower 16 bits are source c index Upper 16 bits are destination * c index / Uint32 srcDstCidx; /* C count / Uint32 cCnt; } CSL_Edma3ParamSetup; /* @brief Edma Object Structure * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3ChannelOpen() * The CSL_edma3ChannelOpen() updates all the members of the data structure * and returns the objects address as a @a #CSL_Edma3ChannelHandle. The * @a #CSL_Edma3ChannelHandle is used in all subsequent function calls. / typedef struct CSL_Edma3ChannelObj { /* Pointer to the Edma Channel Controller module register * Overlay structure / CSL_Edma3ccRegsOvly regs; /* Region number to which the channel belongs to / Int region; /* EDMA instance whose channel is being requested / Int edmaNum; /* Channel Number being requested / Int chaNum; } CSL_Edma3ChannelObj; /* CSL Channel Handle * All channel level API calls must be made with this handle. / typedef struct CSL_Edma3ChannelObj CSL_Edma3ChannelHandle; #if CSL_EDMA3_MEMPROTECT /** @brief Edma Memory Protection Fault Error Status * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetMemoryFaultError() * / CSL_edma3GetHwStatus() with the relevant command. This is relevant only is * MPEXIST is present for a given device. / typedef struct CSL_Edma3MemFaultStat { /* Memory Protection Fault Address / Uint32 addr; /* Bit Mask of the Errors / CSL_BitMask16 error; /* Faulted ID / Uint16 fid; } CSL_Edma3MemFaultStat; #endif /* @brief Edma Controller Error Status. * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetControllerError() * /CSL_edma3GetHwStatus(). / typedef struct CSL_Edma3CtrlErrStat { /* Bit Mask of the Que Threshold Errors / CSL_BitMask16 error; /* Whether number of permissible outstanding Tcc's is exceeded / Bool exceedTcc; } CSL_Edma3CtrlErrStat; /* @brief Edma Controller Information * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetInfo() * /CSL_edma3GetHwStatus(). / typedef struct CSL_Edma3QueryInfo{ /* Revision/Periperhal id of the EDMA3 Channel Controller / Uint32 revision; /* Channel Controller Configuration obtained from the CCCFG register / Uint32 config; } CSL_Edma3QueryInfo; /* @brief Edma Channel Controller Activity Status * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetActivityStatus() * /CSL_edma3GetHwStatus(). / typedef struct CSL_Edma3ActivityStat { /* Number of outstanding completion requests / Uint16 outstandingTcc; /* BitMask of the que active in the Channel Controller / CSL_BitMask16 queActive; /* Indicates if the Channel Controller is active at all / Bool active; /* Indicates whether any QDMA events are active / Bool qevtActive; /* Indicates whether any EDMA events are active / Bool evtActive; /* Indicates whether the TR processing/submission logic is active/ Bool trActive; } CSL_Edma3ActivityStat; /* @brief Edma Controller Que Status. * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetQueStatus() * /CSL_edma3GetHwStatus(). / typedef struct CSL_Edma3QueStat { /* Input field: Event Que. This needs to be specified by the user * before invocation of the above API / CSL_Edma3Que que; /* Output field: The number of valid entries in a queue has exceeded the * threshold specified in QWMTHRA has been exceeded / Bool exceed; /* Output field: The most entries that have been in Que since reset/last * time the watermark was cleared / Uint8 waterMark; /* Output field: Number of valid entries in Que N/ Uint8 numVal; /* Output field: Start pointer/Head of the queue / Uint8 startPtr; } CSL_Edma3QueStat; /* @brief Edma Control/Query Command Structure for querying region specific * attributes. * * An object of this type is allocated by the user and * its address is passed as a parameter to the * CSL_edma3GetHwStatus/CSL_edma3HwControl with the relevant command. / typedef struct CSL_Edma3CmdRegion { /* Input field:- this field needs to be initialized by the user before * issuing the query/command / Int region; /* Input/Output field:-this needs to be filled by the user in case * of issuing a COMMAND or it will be filled in by the CSL when * used with a QUERY / CSL_BitMask32 regionVal; } CSL_Edma3CmdRegion; /* @brief Edma Control/Query Command Structure for querying qdma region access * enable attributes. * * An object of this type is allocated by the user and * its address is passed as a parameter to the * CSL_edma3GetHwStatus/CSL_edma3HwControl with the relevant command. / typedef struct CSL_Edma3CmdQrae { /* this field needs to be initialized by the user before issuing * the query/command / Int region; /* this needs to be filled by the user in case of issuing a * COMMAND or it will be filled in by the CSL when used with a QUERY / CSL_BitMask32 qrae; } CSL_Edma3CmdQrae; /* @brief Edma Control/Query Control Command structure for issuing commands * for Interrupt related APIs * An object of this type is allocated by the user and * its address is passed to the Control API. / typedef struct CSL_Edma3CmdIntr{ /* Input field:- this field needs to be initialized by the user before * issuing the query/command / Int region; /* Input/Output field:- this needs to be filled by the user in case * of issuing a COMMAND or it will be filled in by the CSL when used with * a QUERY / CSL_BitMask32 intr; /* Input/Output:- this needs to be filled by the user in case of issuing a * COMMAND or it will be filled in by the CSL when used with a QUERY / CSL_BitMask32 intrh; } CSL_Edma3CmdIntr; /* @brief Edma Command Structure for setting region specific * attributes. * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetHwStatus * when / typedef struct CSL_Edma3CmdDrae { /* this field needs to be initialiazed by the user before issuing * the command specifying the region for which attributes need to be set / Int region; /* DRAE Setting for the region / CSL_BitMask32 drae; /* DRAEH Setting for the region / CSL_BitMask32 draeh; } CSL_Edma3CmdDrae; /* @brief Edma Command Structure used for setting Event Que priority level * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3HwControl API. / typedef struct CSL_Edma3CmdQuePri { /* Specifies the Que that needs a priority change / CSL_Edma3Que que; /* Que priority / CSL_Edma3QuePri pri; } CSL_Edma3CmdQuePri; /* @brief Edma Command Structure used for setting Event Que threshold level * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3HwControl API. / typedef struct CSL_Edma3CmdQueThr { /* Specifies the Que that needs a change in the threshold setting / CSL_Edma3Que que; /* Que threshold setting / CSL_Edma3QueThr threshold; } CSL_Edma3CmdQueThr; /* @brief This will have the base-address information for the module * instance / typedef struct { /* Base-address of the peripheral registers / CSL_Edma3ccRegsOvly regs; } CSL_Edma3ModuleBaseAddress; /* @brief Edma Channel parameter structure used for opening a channel / typedef struct { /* Region Number / Int regionNum; /* Channel number / Int chaNum; } CSL_Edma3ChannelAttr; /* @brief Edma Channel Error . * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetChannelError() * /CSL_edma3GetHwStatus()/ CSL_edma3ChannelErrorClear() * /CSL_edma3HwChannelControl(). / typedef struct CSL_Edma3ChannelErr { /* a TRUE indicates an event is missed on this channel. / Bool missed; /* a TRUE indicates an event that no events on this channel will be * prioritized till this is cleared. This being TRUE does NOT necessarily * mean it is an error. ONLY if both missed and ser are set, this kind of * error need to be cleared. / Bool secEvt; } CSL_Edma3ChannelErr; /* @brief QDMA Edma Channel Setup * * An array of such objects are allocated by the user and * address initialized in the CSL_Edma3HwSetup structure which is passed * CSL_edma3HwSetup() / typedef struct CSL_Edma3HwQdmaChannelSetup { /* Que number for the channel / CSL_Edma3Que que; /* Parameter set mapping for the channel. / Uint16 paramNum; /* Trigger word for the QDMA channels. / Uint8 triggerWord; } CSL_Edma3HwQdmaChannelSetup; /* @brief QDMA Edma Channel Setup * * An array of such objects are allocated by the user and * address initialized in the CSL_Edma3HwSetup structure which is passed * CSL_edma3HwSetup() / typedef struct CSL_Edma3HwDmaChannelSetup { /* Que number for the channel / CSL_Edma3Que que; #ifdef CSL_EDMA3_CHMAPEXIST /* Parameter set mapping for the channel. This may not be initialized * for Edma channels on devices that do not have CHMAPEXIST. / Uint16 paramNum; #endif } CSL_Edma3HwDmaChannelSetup; /* @brief Edma Hw Setup Structure / typedef struct { /* Edma Hw Channel setup / CSL_Edma3HwDmaChannelSetup dmaChaSetup; /** QEdma Hw Channel setup / CSL_Edma3HwQdmaChannelSetup qdmaChaSetup; } CSL_Edma3HwSetup; /*************************************************************************\ EDMA global function declarations \*************************************************************************/ / * ============================================================================= * @func CSL_edma3Init * * @desc * This is EDMA module's init function. This initializes the context Object * variables.Needs to be invoked before using EDMA module. * * @arg pContext * Context information for edma * * @ret CSL_Status * CSL_SOK - Always returns * * @eg * CSL_edma3Init (NULL); * ============================================================================= / extern CSL_Status CSL_edma3Init ( CSL_Edma3Context pContext ); /* ============================================================================ @func CSL_edma3Open * * @desc * Returns a handle to the EDMA Module. This handle is further used * for invoking all module level control APIs.This call enables * the relocatability of code since the handle can be subsequently used for * Module level control commands rather than the usage of of the register * layer base address directly. * * @arg edmaObj * Pointer to the object to which a handle is returned. * * @arg edmaNum * Instance Number of the EDMA * * @arg param * Pointer to module specific parameters * * @arg status * pointer for returning status of the function call * * @ret CSL_Edma3Handle * Valid edma handle will be returned if status value is equal to * CSL_SOK * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); * * =========================================================================== / extern CSL_Edma3Handle CSL_edma3Open ( CSL_Edma3Obj edmaObj, CSL_InstNum edmaNum, CSL_Edma3ModuleAttr attr, CSL_Status status ); /* ============================================================================ @func CSL_edma3Close * * @desc * The EDMA module handle is invalidated and in order to use the EDMA module * it needs to be opened again. * * @arg hEdma * Handle to the EDMA module * * @ret CSL_Status * CSL_SOK - Close successful * CSL_ESYS_BADHANDLE - Invalid handle * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Close Module CSL_edma3Close(hModule); * * =========================================================================== / extern CSL_Status CSL_edma3Close ( CSL_Edma3Handle hEdma ); / * ============================================================================= * @func CSL_edma3HwSetup * * @desc * Does a module level HW setup of EDMA. This programs the * Channel to Param mapping, Channel to Que map and the trigger * word (if applicable) of ALL channels (DMA, QDMA). * * @arg hMod * Edma Module Handle * * @arg setup * Pointer to hardware setup structure containing the setup parameters * of all DMA, QDMA channels. * * @ret CSL_Status * CSL_SOK - Hardware setup successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); ... * * =========================================================================== / extern CSL_Status CSL_edma3HwSetup ( CSL_Edma3Handle hMod, CSL_Edma3HwSetup setup ); /* * ============================================================================= * @func CSL_edma3GetHwSetup * * @desc * Obtains the module level HW setup of EDMA. This reads the * Channel to Param mapping.Channel to Que map and the trigger word * (if applicable) of ALL channels (DMA, QDMA) into the placeholder * provided by the user. * * @arg hMod * Edma Module Handle * * @arg setup * Pointer to the Module Setup structure * * @ret CSL_Status * CSL_SOK - Hardware setup successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup, gethwSetup; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Get Module Setup gethwSetup.dmaChaSetup = &getdmahwSetup[0]; gethwSetup.qdmaChaSetup = NULL; CSL_edma3GetHwSetup(hModule,&gethwSetup); ... * * =========================================================================== / extern CSL_Status CSL_edma3GetHwSetup ( CSL_Edma3Handle hMod, CSL_Edma3HwSetup setup ); /* * ============================================================================= * @func CSL_edma3HwControl * * @desc * Module level control commands are handled by this API. * * @arg hMod * Edma Module Handle * * @arg cmd * Module Command * * @arg cmdArg * Additional command arguments are passed to the API using this. * The CSL function type casts to the appropriate arguments type * depending on the cmd. * * @ret CSL_Status * CSL_SOK - Command execution successful. * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVCMD - Invalid command * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup, gethwSetup; CSL_Edma3CmdDrae regionAccess; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // DRAE Enable(Bits 0-15) for the Shadow Region 0. regionAccess.region = CSL_EDMA3_REGION_0 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); ... * * =========================================================================== / extern CSL_Status CSL_edma3HwControl ( CSL_Edma3Handle hMod, CSL_Edma3HwControlCmd cmd, void cmdArg ); /** ============================================================================ * @n@b CSL_edma3ccGetModuleBaseAddr * * @b Description * @n This function is used for getting the base-address of the peripheral * instance. This function will be called inside the @ CSL_edma3Open() * /CSL_edma3ChannelOpen() function call. * * Note: This function is open for re-implementing if the user wants to * modify the base address of the peripheral object to point to a different * location and there by allow CSL initiated write/reads into peripheral * MMR's go to an alternate location. * * @b Arguments * @verbatim edmaNum Specifies the instance of the edma to be opened. pAttr Module specific parameters. pBaseAddress Pointer to baseaddress structure containing base address details. @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Base Address structure is populated * * @b Modifies * @li The status variable * @li Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_Edma3ModuleBaseAddress baseAddress; ... status = CSL_edma3ccGetModuleBaseAddr(CSL_EDMA3, NULL, &baseAddress); @endverbatim * =========================================================================== / extern CSL_Status CSL_edma3ccGetModuleBaseAddr ( CSL_InstNum edmaNum, CSL_Edma3ModuleAttr pAttr, CSL_Edma3ModuleBaseAddress pBaseAddress ); / * ============================================================================= * @n@b CSL_edma3GetHwStatus * * @desc * Module level queries to the EDMA module are handled through this API * * @arg hMod * Edma Module Handle * * @arg myQuery * Query to be performed. * * @arg response * Pointer to buffer to return the data requested by the query passed * * @arg CSL_Status * CSL_SOK - Successful completion of the query * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVQUERY - Query command not supported * * @eg * CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3QueryInfo info; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3Context context; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; CSL_Status status; Uint32 i,passStatus = 1; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Query Module Info CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INFO,&info); ... * * =========================================================================== / extern CSL_Status CSL_edma3GetHwStatus ( CSL_Edma3Handle hMod, CSL_Edma3HwStatusQuery myQuery, void response ); /* ============================================================================ @func CSL_edma3ChannelOpen * * @desc * Opens an EDMA channel to get access to the resources for a * particular channel. * * @arg edmaObj * Pointer to the EDMA Handle Object - to be allocated by the user * * @arg edmaNum * Instance Number of the EDMA * * @arg param * Channel specific parameters * * @arg status * Pointer to CSL Status * * @ret CSL_Edma3ChannelHandle * Valid edma channel handle will be returned if status value is * equal to CSL_SOK * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3ChannelAttr chAttr; CSL_Edma3ChannelHandle hChannel; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); ... * * =========================================================================== / extern CSL_Edma3ChannelHandle CSL_edma3ChannelOpen ( CSL_Edma3ChannelObj edmaObj, CSL_InstNum edmaNum, CSL_Edma3ChannelAttr chAttr, CSL_Status status ); /* ============================================================================ @func CSL_edma3ChannelClose * * @desc * Closes (Invalidates) an EDMA channel (passed as handle) after it has * finished operating. The channel cannot be accessed any more. * * @arg hEdma * Channel Handle * * @ret CSL_Status * CSL_SOK - Close successful * CSL_ESYS_BADHANDLE - Invalid handle * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Close Module CSL_edma3Close(hModule); //Close channel CSL_edma3ChannelClose (hChannel); * * =========================================================================== / extern CSL_Status CSL_edma3ChannelClose ( CSL_Edma3ChannelHandle hEdma ); / * ============================================================================= * @func CSL_edma3ChannelSetupParam * * @desc * Does the Channel setup i.e the channel to param set mapping(if relevant) * * @arg hEdma * Channel Handle * * @arg paramNum * parameter set to be mapped to the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; Uint16 paramNum; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Set the parameter entry number to channel paramNum = 100; CSL_edma3HwChannelSetupParam(hChannel,paramNum); ... * * =========================================================================== / extern CSL_Status CSL_edma3HwChannelSetupParam ( CSL_Edma3ChannelHandle hEdma, Uint16 paramNum ); / * ============================================================================= * @func CSL_edma3ChannelSetupTriggerWord * * @desc * Sets up the channel trigger word.This is applicable only * for QDMA channels. * * @arg hEdma * Channel Handle * * @arg triggerWord * trigger word (0-7) for the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Sets up the QDMA Channel 0 trigger Word to the 3rd trigger word CSL_edma3HwChannelSetupTriggerWord(hChannel,3); ... * * =========================================================================== / extern CSL_Status CSL_edma3HwChannelSetupTriggerWord ( CSL_Edma3ChannelHandle hEdma, Uint8 triggerWord ); / * ============================================================================= * @func CSL_edma3ChannelSetupQue * * @desc * Does the Channel setup i.e the channel to que mapping * * @arg hEdma * Channel Handle * * @arg que * Queue to be mapped to the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3Que evtQue; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Set up the channel to que mapping CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_3); ... * * =========================================================================== / extern CSL_Status CSL_edma3HwChannelSetupQue ( CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que que ); / * ============================================================================= * @func CSL_edma3GetHwChannelSetupParam * * @desc * Obtains the current channel to parameter set mapping. * * @arg hEdma * Channel Handle * * @arg paramNum * parameter set currently mapped to the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; Uint16 paramNum; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the parameter entry number to which a channel is mapped to CSL_edma3GetHwChannelSetupParam(hChannel,&paramNum); ... * * =========================================================================== / extern CSL_Status CSL_edma3GetHwChannelSetupParam ( CSL_Edma3ChannelHandle hEdma, Uint16 paramNum ); /* * ============================================================================= * @func CSL_edma3GetHwChannelSetupTriggerWord * * @desc * Gets channel trigger word.This is applicable only for QDMA channels. * * @arg hEdma * Channel Handle * * @arg triggerWord * Trigger word setup in the (QDMA)channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3ChannelHandle hChannel; Uint8 triggerWord; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the trigger word programmed for a channel CSL_edma3GetHwChannelSetupTriggerWord(hChannel,&triggerWord); ... * * =========================================================================== / extern CSL_Status CSL_edma3GetHwChannelSetupTriggerWord ( CSL_Edma3ChannelHandle hEdma, Uint8 triggerWord ); /* * ============================================================================= * @func CSL_edma3GetHwChannelSetupQue * * @desc * Obtains the Channel setup i.e the channel to que mapping * * @arg hEdma * Channel Handle * * @arg que * Queue currently mapped to the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3Que evtQue; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the que to which a channel is mapped CSL_edma3GetHwChannelSetupQue(hChannel,&evtQue); ... * * =========================================================================== / extern CSL_Status CSL_edma3GetHwChannelSetupQue ( CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que que ); /* * ============================================================================= * @func CSL_edma3HwChannelControl * * @desc * Channel level control commands are handled by this API. * * @arg hCh * Channel Handle * * @arg cmd * Channel Command * * @arg cmdArg * Additional command arguments are passed to the API using this. * The CSL function type casts to the appropriate arguments type * depending on the cmd. * * @ret CSL_Status * CSL_SOK - Command execution successful. * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVCMD - Invalid command * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup; CSL_Edma3ChannelObj ChObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL); ... * * =========================================================================== / extern CSL_Status CSL_edma3HwChannelControl ( CSL_Edma3ChannelHandle hCh, CSL_Edma3HwChannelControlCmd cmd, void cmdArg ); /* * ============================================================================= * @n@b CSL_edma3GetHwChannelStatus * * @desc * Channel level queries to the EDMA module are handled through this API. * * @arg hCh * Channel Handle * * @arg myQuery * Channel query to be performed. * * @arg response * Pointer to buffer to return the data requested by the query passed * * @ret CSL_Status * CSL_SOK - Successful completion of the query * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVQUERY - Query command not supported * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup; CSL_Edma3ChannelObj ChObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; Bool errStat; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Obtain Channel Error Status CSL_edma3GetHwChannelStatus(hChannel,CSL_EDMA3_QUERY_CHANNEL_ERR, \ errStat); ... * * =========================================================================== / extern CSL_Status CSL_edma3GetHwChannelStatus ( CSL_Edma3ChannelHandle hCh, CSL_Edma3HwChannelStatusQuery myQuery, void response ); /* * ============================================================================= * @n@b CSL_edma3GetParamHandle * * @desc * Returns the handle to the requested parameter set. * * @arg hEdma * Channel Handle * * @arg paramNum * Param set number desired * * @arg status * Pointer to the placeholder for the status * * @ret CSL_Edma3ParamHandle * Valid param handle will be returned if status value * is equal to CSL_SOK. * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup; CSL_Edma3ChannelObj ChObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Obtain a handle to parameter entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL); ... * * =========================================================================== / extern CSL_Edma3ParamHandle CSL_edma3GetParamHandle ( CSL_Edma3ChannelHandle hEdma, Int16 paramNum, CSL_Status status ); /* * ============================================================================= * @n@b CSL_edma3ParamSetup * * @desc * Configures a EDMA Parameter Set. * * @arg hParam * Handle to the Parameter Set * * @arg pSetup * Pointer to the CSL_Edma3ParamSetup * * @ret CSL_Status * CSL_SOK - Command execution successful * CSL_ESYS_BADHANDLE - The handle passed is * invalid * CSL_ESYS_INVPARAMS - The parameter passed is invalid * * @eg * CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamPing; CSL_Edma3ChannelObj ChObj; CSL_Edma3QueryInfo info; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; CSL_Status status; Uint32 i, passStatus = 1; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // DRAE Enable(Bits 0-15) for the Shadow Region 0. regionAccess.region = CSL_EDMA3_REGION_0 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); // Interrupt Enable (Bits 0-11) for the Shadow Region 0. regionIntr.region = CSL_EDMA3_REGION_0 ; regionIntr.intr = 0x0FFF ; regionIntr.intrh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Obtain a handle to parameter entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL); // Setup the first param Entry (Ping buffer) myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCHEN_DIS, \ CSL_EDMA3_TCCHEN_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 0,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff1; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1); myParamSetup.dstAddr = (Uint32)dstBuff1; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup.cCnt = 1; CSL_edma3ParamSetup(hParamBasic,&myParamSetup); ... * * =========================================================================== / extern CSL_Status CSL_edma3ParamSetup ( CSL_Edma3ParamHandle hParam, CSL_Edma3ParamSetup pSetup ); /* * ============================================================================= * @n@b CSL_edma3ParamWriteWord * * @desc * Writes specified word at the specified parameter set offset. * * @arg hParam * Handle to the Parameter Set * * @arg wordOffset * Word Offset at which the specified word is to be written * * @arg word * Word itself that needs to be written * * @ret CSL_Status * CSL_SOK - Param Write Word successful * * @eg * CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamPing; CSL_Edma3ChannelObj ChObj; CSL_Edma3QueryInfo info; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdQrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmahwSetup[0];; CSL_edma3HwSetup(hModule,&hwSetup); // DRAE Enable(Bits 0-15) for the Shadow Region 0. regionAccess.region = CSL_EDMA3_REGION_0 ; regionAccess.qrae = 0x000F ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_QDMAREGION_ENABLE, \ &regionAccess); // Interrupt Enable (Bits 0-11) for the Shadow Region 0. regionIntr.region = CSL_EDMA3_REGION_0 ; regionIntr.intr = 0x0FFF ; regionIntr.intrh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE, &regionIntr); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Obtain a handle to parameter entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL); // Setup the first param Entry (Ping buffer) myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCHEN_DIS, \ CSL_EDMA3_TCCHEN_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 0,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_EN, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff1; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1); myParamSetup.dstAddr = (Uint32)dstBuff1; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup.cCnt = 1; CSL_edma3ParamSetup(hParamBasic,&myParamSetup); // Enable Channel CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL); // Write trigger word CSL_edma3ParamWriteWord(hParamBasic,7,myParamSetup.cCnt); ... * * =========================================================================== */ extern CSL_Status CSL_edma3ParamWriteWord ( CSL_Edma3ParamHandle hParamHndl, Uint16 wordOffset, Uint32 word ); #ifdef __cplusplus } #endif #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_error.h	/* ========================================================================== * Copyright (c) Texas Instruments Inc 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * provided * ========================================================================== / / ---- File: <csl_error.h> ---- / #ifndef _CSL_ERROR_H_ #define _CSL_ERROR_H_ / Below Error codes are Global across all CSL Modules. / #define CSL_SOK (1) / Success / #define CSL_ESYS_FAIL (-1) / Generic failure / #define CSL_ESYS_INUSE (-2) / Peripheral resource is already in use / #define CSL_ESYS_XIO (-3) / Encountered a shared I/O(XIO) pin conflict / #define CSL_ESYS_OVFL (-4) / Encoutered CSL system resource overflow / #define CSL_ESYS_BADHANDLE (-5) / Handle passed to CSL was invalid / #define CSL_ESYS_INVPARAMS (-6) / invalid parameters / #define CSL_ESYS_INVCMD (-7) / invalid command / #define CSL_ESYS_INVQUERY (-8) / invalid query / #define CSL_ESYS_NOTSUPPORTED (-9) / action not supported / / Peripheral IDs / #define CSL_MCBSP_ID (7) #define CSL_GPIO_ID (8) / Error codes individual to various modules. / / Error code for DMA, individual error would be assigned as * eg: #define CSL_E<Peripheral name>_<error code> CSL_EDMA_FIRST - 1 / #define CSL_EPWM_FIRST -( ((CSL_PWM_ID + 1) << 5 ) + 1 ) #define CSL_EPWM_LAST -( (CSL_PWM_ID + 1) << 6 ) #define CSL_EUART_FIRST -( ((CSL_UART_ID + 1) << 5 ) + 1 ) #define CSL_EUART_LAST -( (CSL_UART_ID + 1) << 6 ) #define CSL_ESPI_FIRST -( ((CSL_SPI_ID + 1) << 5 ) + 1 ) #define CSL_ESPI_LAST -( (CSL_SPI_ID + 1) << 6 ) #define CSL_EATA_FIRST -( ((CSL_ATA_ID + 1) << 5 ) + 1 ) #define CSL_EATA_LAST -( (CSL_ATA_ID + 1) << 6 ) #define CSL_EMMCSD_FIRST -( ((CSL_MMCSD_ID + 1) << 5 ) + 1 ) #define CSL_EMMCSD_LAST -( (CSL_MMCSD_ID + 1) << 6 ) #define CSL_EVLYNQ_FIRST -( ((CSL_VLYNQ_ID + 1) << 5 ) + 1 ) #define CSL_EVLYNQ_LAST -( (CSL_VLYNQ_ID + 1) << 6 ) #define CSL_EMCBSP_FIRST -( ((CSL_MCBSP_ID + 1) << 5 ) + 1 ) #define CSL_EMCBSP_LAST -( (CSL_MCBSP_ID + 1) << 6 ) #define CSL_EI2C_FIRST -( ((CSL_I2C_ID + 1) << 5 ) + 1 ) #define CSL_EI2C_LAST -( (CSL_I2C_ID + 1) << 6 ) #define CSL_EGPIO_FIRST -( ((CSL_GPIO_ID + 1) << 5 ) + 1 ) #define CSL_EGPIO_LAST -( (CSL_GPIO_ID + 1) << 6 ) #define CSL_EMS_FIRST -( ((CSL_MS_ID + 1) << 5 ) + 1 ) #define CSL_EMS_LAST -( (CSL_MS_ID + 1) << 6 ) #define CSL_EINTC_FIRST -( ((CSL_INTC_ID + 1) << 5 ) + 1 ) #define CSL_EINTC_LAST -( (CSL_INTC_ID + 1) << 6 ) #define CSL_EEMIF_FIRST -( ((CSL_EMIF_ID + 1) << 5 ) + 1 ) #define CSL_EEMIF_LAST -( (CSL_EMIF_ID + 1) << 6 ) #define CSL_EPLLC_FIRST -( ((CSL_PLLC_ID + 1) << 5 ) + 1 ) #define CSL_EPLLC_LAST -( (CSL_PLLC_ID + 1) << 6 ) #define CSL_EDDR_FIRST -( ((CSL_DDR_ID + 1) << 5 ) + 1 ) #define CSL_EDDR_LAST -( (CSL_DDR_ID + 1) << 6 ) #define CSL_EEDMA_FIRST -( ((CSL_EDMA_ID + 1) << 5 ) + 1 ) #define CSL_EEDMA_LAST -( (CSL_EDMA_ID + 1) << 6 ) #endif / _CSL_ERROR_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/FB_W2100_SCU_MEA256/Stimulation.c	<filename>DSP/FB_W2100_SCU_MEA256/Stimulation.c /* * Stimulation.c * * Created on: 14.05.2018 * Author: jesinger / #include "Device_lib.h" #include "Stimulation.h" #include <math.h> void UploadBiphaseRect(int channel, int segment, int amplitude, int duration, int repeats) { int vectors_used; vectors_used = 0; ClearChannel(channel, segment); vectors_used += AddDataPoint(channel, duration, 0x8000 + amplitude); vectors_used += AddDataPoint(channel, duration, 0x8000 - amplitude); AddLoop(channel, vectors_used, repeats); vectors_used = 0; ClearChannel(channel+1, segment); vectors_used += AddDataPoint(channel+1, duration, 0x0119); // bit 1,3,4 and 8 vectors_used += AddDataPoint(channel+1, duration, 0x0019); // bit 1,3,4 AddLoop(channel+1, vectors_used, repeats); } void UploadSine(int channel, int segment, int amplitude, int period, int repeats, int stepsize) { int yold = 0; int duration = 0; int datapoints = 0; volatile int i; int y; int vectors_used; vectors_used = 0; ClearChannel(channel, segment); for (i = 0; i < period; i++) { y = amplitude sin((((double)i)/period)23.1415); // y = -(Amplitude i)/Period; if (abs(y - yold) > stepsize) { vectors_used += AddDataPoint(channel, duration, yold+0x8000); datapoints++; yold = y; duration = 1; // 20 us } else { duration++; } } vectors_used += AddDataPoint(channel, duration, yold+0x8000); AddLoop(channel, vectors_used, repeats); // Create Sideband Information ClearChannel(channel+1, segment); vectors_used = 0; vectors_used += AddDataPoint(channel+1, period, 0x0019); AddLoop(channel+1, vectors_used, repeats); // AddDataPoint(Channel+1, 10, 0x0009); // keep Electrode connected to ground after stimulation } void AddLoop(int channel, int vectors, int repeats) { Uint32 ChannelReg = STG_DATA_MEMORY + channel REGISTER_OFFSET; Uint32 LoopVector; if (repeats > 1) { LoopVector = 0x10000000 \| (repeats << 16) \| vectors; WRITE_REGISTER(ChannelReg, LoopVector); } } void SetSegment(int channel, int segment) { Uint32 SegmentReg = STG_MEMPOINT_CC_BASE + (channel * MEMPOINT_OFFSET); WRITE_REGISTER(SegmentReg, segment); } void ClearChannel(int channel, int segment) { Uint32 ClearReg = STG_MEMPOINT_WP_BASE + (channel * MEMPOINT_OFFSET); // SetSegment(channel, segment); WRITE_REGISTER(ClearReg, 0); // Any write to this register clears the channeldata } int AddDataPoint(int channel, int duration, int value) { int vectors_used = 0; int Vector; Uint32 ChannelReg = STG_DATA_MEMORY + channel * REGISTER_OFFSET; if (duration > 1000) { Vector = 0x04000000 \| (((duration / 1000) - 1) << 16) \| (value & 0xffff); WRITE_REGISTER(ChannelReg, Vector); // Write Datapoint to STG Memory duration %= 1000; vectors_used++; } if (duration > 0) { Vector = ((duration - 1) << 16) \| (value & 0xffff); WRITE_REGISTER(ChannelReg, Vector); // Write Datapoint to STG Memory vectors_used++; } return vectors_used; } void SetupTrigger() { int i; WRITE_REGISTER(TRIGGER_CTRL_HS1, 0x1); // Enable Trigger Packets for (i = 0; i < TIGGER_PER_HS; i++) { WRITE_REGISTER(TRIGGER_ID_HS1+i, 0x0); // Setup Trigger WRITE_REGISTER(STG_TRIGGER_CONFIG+i, (4 << 1) \| 1); WRITE_REGISTER(STG_TRIGGER_REPEAT+i, 1); // Trigger Repeat: only once } // WRITE_REGISTER(0x9104, 0x00020100); // DAC1 to Trigger1, DAC2 to Trigger2, DAC3 to Trigger3 // WRITE_REGISTER(0x9108, 0x00020100); // SBS1 to Trigger1, SBS2 to Trigger2, SBS3 to Trigger3 }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cHwSetup.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_i2cHwSetup.c * * @brief File for functional layer of CSL API @a CSL_i2cHwSetup() * * @path $(CSLPATH)\i2c\src * * Description * - The @a CSL_i2cHwSetup() function definition & it's associated * functions * * Modification 1 * - Modified on: 28/5/2004 * - Reason: created the sources * * @date 28th May, 2004 * @author <NAME>. * ============================================================================ / #include <csl_i2c.h> /* ============================================================================ * @n@b CSL_i2cHwSetup * * @b Description * @n This function initializes the device registers with the appropriate * values provided through the HwSetup Data structure. This function needs * to be called only if the HwSetup Structure was not previously passed * through the Open call. After the Setup is completed, the device is ready * for operation.For information passed through the HwSetup Data structure * refer @a CSL_i2cHwSetup. * @b Arguments * @verbatim hI2c Handle to the I2C setup Pointer to setup structure which contains the information to program I2C to a useful state @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Hardware setup Successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * <b> Pre Condition </b> * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before this function can be called. The user has to * allocate space for & fill in the main setup structure appropriately * before calling this function. * * <b> Post Condition </b> * @n The registers of the specified I2C instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified I2C instance. * * @b Example * @verbatim CSL_i2cHandle hI2c; CSL_i2cHwSetup hwSetup = CSL_I2C_HWSETUP_DEFAULTS; ... CSL_i2cHwSetup(hI2c, &hwSetup); ... @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_i2cHwSetup, ".text:csl_section:i2c"); CSL_Status CSL_i2cHwSetup ( CSL_I2cHandle hI2c, CSL_I2cHwSetup setup ) { CSL_Status status = CSL_SOK; if (hI2c == NULL) { status = CSL_ESYS_BADHANDLE; } else if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Set the mode(Master/Slave), direction(Transmitter/Receiver), * addressing mode(7-bit or 10-bit, free run mode, free data * format and start byte mode. / hI2c->regs->ICMDR = ((hI2c->regs->ICMDR & 0x3807) \| (CSL_FMK(I2C_ICMDR_MST,setup->mode) \| CSL_FMK(I2C_ICMDR_NACKMOD, setup->ackMode) \| CSL_FMK(I2C_ICMDR_TRX, setup->dir) \| CSL_FMK(I2C_ICMDR_XA, setup->addrMode) \| CSL_FMK(I2C_ICMDR_FREE, setup->runMode) \| CSL_FMK(I2C_ICMDR_STB, setup->sttbyteen) \| CSL_FMK(I2C_ICMDR_FDF, setup->freeDataFormat) \| CSL_FMK(I2C_ICMDR_RM, setup->repeatMode) \| CSL_FMK(I2C_ICMDR_DLB, setup->loopBackMode) \| CSL_FMK(I2C_ICMDR_IRS, setup->resetMode))); / set Backward Compatibility Mode / hI2c->regs->ICEMDR = (hI2c->regs->ICEMDR & 0x1) \| (CSL_FMK(I2C_ICEMDR_BCM, setup->bcm)); / Set the own address of the given instance / CSL_FINS(hI2c->regs->ICOAR, I2C_ICOAR_OADDR, setup->ownaddr); / The interrupt status is set into the interrupt enable register / hI2c->regs->ICIMR = setup->inten ; / Set up the prescalar value / CSL_FINS(hI2c->regs->ICPSC, I2C_ICPSC_IPSC, setup->clksetup->prescalar); / Set the clock low value / CSL_FINS(hI2c->regs->ICCLKL, I2C_ICCLKL_ICCL, setup->clksetup->clklowdiv); / Set the clock high value */ CSL_FINS(hI2c->regs->ICCLKH, I2C_ICCLKH_ICCH, setup->clksetup->clkhighdiv); } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example1/src/Intc_example1.c	<filename>DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example1/src/Intc_example1.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file Intc_example.c * * @path $(CSLPATH)\example\c64xplus\intc\intc_example1\src * * @desc Example of INTC * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @n The example shows how to use INTC CSL with EDMA module. * This is an example of the CSL Interrupt Controller usage. * A event object is opened and is simply hooked up to a CPU vector. * An event hnadler is associaed with it. This example, * 1. Initalizes the intc CSL required with proper ISR * 2. Intializes and opens EDMA * 3. Associates EDMA event handler with the INTC routine * CSL_intcPlugEventHandler () * 4. Enables the edma interrupt * 5. Waits for edma interrupt generate. * 6. Compares the transferred data * 7. Displays the messages based on step 6 * ============================================================================= * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Intc_example1.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================= * Revision History * =============== * 30-Jun-2004 <NAME> File Created * 22-Jul-2005 ds changed to support edma3 csl * 16-Dec-2005 ds Updated documentation * 28-Mar-2006 ds Added code to clear all the evnts * ============================================================================= / #include <stdio.h> #include <csl_edma3.h> #include <csl_intc.h> #include <soc.h> / Pragma to edma tcc handler table / #pragma DATA_SECTION(TccHandlerTable,".testMem"); / Global variable to Edma Tcc handler table / typedef void ( EdmaTccHandler)(void); EdmaTccHandler TccHandlerTable[64]; /* Macro for tcc handler table / #define InvokeHandle(num) TccHandlerTable[num]() / Funtion forwards, for which registers individual event handlers in a table / void EdmaEventHook(Uint16 , EdmaTccHandler); void eventEdmaHandler(void ); /* Function forwards / void tcc1Fxn(); void intc_example (void); / Intc variable declarartion / CSL_IntcContext intcContext; CSL_IntcEventHandlerRecord EventHandler[30]; CSL_IntcObj intcObjEdma; CSL_IntcHandle hIntcEdma; CSL_IntcGlobalEnableState state; CSL_IntcEventHandlerRecord EventRecord; CSL_IntcParam vectId; / Global variable declarations / Uint8 srcBuff[512]; Uint8 dstBuff[512]; volatile Uint32 intFlag = 0; CSL_Edma3Handle hModule; / * ============================================================================= * @func main * * @desc * This is the main routine,which invokes the example * ============================================================================= / void main() { printf ("Running Interrupt Example\n"); intc_example (); return; } / * ============================================================================= * @func intc_example * * @arg None * * @desc * This is an example of the CSL Interrupt Controller usage. * A event object is opened and is simply hooked up to a CPU vector. * An event hnadler is associaed with it. * 1. Initalizes the intc CSL required with proper ISR * 2. Intializes and opens EDMA * 3. Associates EDMA event handler with the INTC routine * CSL_intcPlugEventHandler () * 4. Enables the edma interrupt * 5. Waits for edma interrupt generate. * 6. Compares the transferred data * 7. Closes the edma module and edma channel. * 8. Closes the Intc module * * @return * None * * @eg * intc_example (); * ============================================================================= / void intc_example (void) { CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ChannelObj chObj; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Status status; Uint32 loopIndex; Uint32 passStatus = 1; Uint32 evtClr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; / Initialize Data Buffers / for (loopIndex = 0; loopIndex < 512;loopIndex++) { srcBuff[loopIndex] = loopIndex; dstBuff[loopIndex] = 0; } / Edma CSL initialization / CSL_edma3Init(&context); / Intc module initialization / intcContext.eventhandlerRecord = EventHandler; intcContext.numEvtEntries = 10; status = CSL_intcInit(&intcContext); if (status != CSL_SOK) { printf("Intc initialization failed\n"); return; } / Enable NMIs / status = CSL_intcGlobalNmiEnable(); if (status != CSL_SOK) { printf("Intc global NMI enable failed\n"); return; } / Enable global interrupts / status = CSL_intcGlobalEnable(&state); if (status != CSL_SOK) { printf ("Intc global enable failed\n"); return; } / Opening intc module / vectId = CSL_INTC_VECTID_4; hIntcEdma = CSL_intcOpen (&intcObjEdma, CSL_INTC_EVENTID_EDMA3CC_INT1, \ &vectId , NULL); if (hIntcEdma == NULL) { printf("Intc open failed\n"); return; } / Opening a edma module / hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); / Edma module setup / hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); / Setup the DRAE Masks * DRAE Enable(Bits 0-15) for the Shadow Region 1. / regionAccess.region = CSL_EDMA3_REGION_1 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); / Edma channel open / chAttr.regionNum = CSL_EDMA3_REGION_1; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj,CSL_EDMA3,&chAttr,&status); / Parameter Set Setup / hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 1,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1); myParamSetup.dstAddr = (Uint32)dstBuff; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,1); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0); myParamSetup.cCnt = 1; CSL_edma3ParamSetup(hParamBasic,&myParamSetup); / Association of an EDMA event handler with the INTC routine / EventRecord.handler = &eventEdmaHandler; EventRecord.arg = (void)(hModule); status = CSL_intcPlugEventHandler(hIntcEdma,&EventRecord); if (status != CSL_SOK) { printf("Intc plug event handler failed\n"); return; } /* Enabling event edma / status = CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL); if (status != CSL_SOK) { printf("Intc CSL_INTC_CMD_EVTENABLE command failed\n"); return; } / Hook up the EDMA Event with an completion code function handler / EdmaEventHook(1, tcc1Fxn); / Enable Interrupts / regionIntr.region = CSL_EDMA3_REGION_1 ; regionIntr.intr = 0x2 ; regionIntr.intrh = 0x0 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr); / Enable Channel :- though not required for a manual trigger / status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \ NULL); / Manually trigger the channel / status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL); / Wait for generation of interrut / while (!intFlag); / Verify destination buffer to be equal to the source buffer / for (loopIndex = 0; loopIndex < 256; loopIndex++) if (srcBuff[loopIndex] != dstBuff[loopIndex]) passStatus = 0; if (passStatus != 0) { printf ("<<Example Passed>>: Interrupt example passed\n"); } else { printf ("<<Example Failed>>: Interrupt example failed\n"); return; } / Clear the all events / for (loopIndex = 0; loopIndex < 4; loopIndex++) { evtClr = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTFLAG[loopIndex]; ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[loopIndex] = evtClr; } / Close handles / CSL_edma3ChannelClose(hChannel); CSL_edma3Close(hModule); CSL_intcClose (hIntcEdma); return; } / * ============================================================================= * @func tcc1Fxn * @desc * This is the Interrupt service routine * * @arg None * * @eg * tcc1Fxn (); * * * ============================================================================= / void tcc1Fxn(void) { intFlag = 1; } / * ============================================================================= * @func EdmaEventHook * * @arg * tcc - Tcc number * fxn - Pointer to function which points to edma isr * * @desc * This is the interrupt handler routine for edma interrupt * * @return * NONE * * ============================================================================= / void EdmaEventHook ( Uint16 tcc, EdmaTccHandler fxn ) { TccHandlerTable[tcc] = (fxn); } / * ============================================================================= * @func eventEdmaHandler * * @desc * This is the event handler for edma * * @arg handle * Pointer to edma handle * * * @eg * eventEdmaHandler (); * ============================================================================= / void eventEdmaHandler ( void handle ) { CSL_BitMask32 mask; CSL_BitMask32 maskVal; CSL_Edma3CmdIntr regionIntr; Uint32 tcc; Uint32 intr; Uint32 intrh; Int region; CSL_Edma3Handle hModule = (CSL_Edma3Handle)handle; regionIntr.region = CSL_EDMA3_REGION_GLOBAL; CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr); intr = regionIntr.intr; intrh = regionIntr.intrh; mask = 1; tcc = 0; while (intr) { maskVal = mask << tcc; if (regionIntr.intr & maskVal) { InvokeHandle(tcc); intr &= ~maskVal; } tcc++; } mask = 1; tcc = 0; while (intrh) { maskVal = mask << tcc; if (intrh & maskVal) { InvokeHandle((tcc+32)); intrh &= ~maskVal; } tcc++; } CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&regionIntr); CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr); if ((regionIntr.intr !=0)\|\|(regionIntr.intrh !=0)) { region = CSL_EDMA3_REGION_GLOBAL; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_EVAL,&region); } }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcInit.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_intcInit.c * * @brief File for functional layer of CSL API CSL_intcInit() * * PATH $(CSLPATH)\src\intc / / ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= / #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /* ============================================================================ * @n@b CSL_intcInit * * @b Description * @n This is the initialization function for the INTC. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. * * @b Arguments * @verbatim pContext Pointer to module-context structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Always returns * * <b> Pre Condition </b> * @n This function should be called before using any of the CSL INTC APIs. * The context should be initialized such that numEvtEntries is equal to * the number of records capable of being held in the eventhandlerRecord * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; CSL_IntcEventHandlerRecord recordTable[10]; context.numEvtEntries = 10; context.eventhandlerRecord = &recordTable; // Init Module ... if (CSL_intcInit(&context) != CSL_SOK) { exit; } @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_intcInit, ".text:csl_section:intc"); CSL_Status CSL_intcInit ( CSL_IntcContext pContext ) { Uint16 i; asm(" dint"); if (pContext != NULL) { _CSL_intcEventOffsetMap = pContext->offsetResv; _CSL_intcAllocMask = pContext->eventAllocMask; _CSL_intcNumEvents = pContext->numEvtEntries; for (i = 0; i < ((CSL_INTC_EVENTID_CNT + 31) / 32); i++) _CSL_intcAllocMask[i] = 0; for (i = 0; i < CSL_INTC_EVENTID_CNT ; i++) _CSL_intcEventOffsetMap[i] = CSL_INTC_MAPPED_NONE; if (pContext->eventhandlerRecord != NULL) { _CSL_intcEventHandlerRecord = pContext->eventhandlerRecord; for (i = 0; i < _CSL_intcNumEvents; i++) _CSL_intcEventHandlerRecord[i].handler = CSL_INTC_EVTHANDLER_NONE; } } _CSL_intcIvpSet(); _CSL_intcCpuIntrTable.nmiIsr = _CSL_intcNmiDummy; _CSL_intcCpuIntrTable.isr4 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr5 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr6 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr7 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr8 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr9 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr10 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr11 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr12 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr13 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr14 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr15 = _CSL_intcDispatcher; asm(" rint"); return CSL_SOK; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspHwControl.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_mcbspHwControl.c * * @path $(CSLPATH)\src\mcbsp * * @desc File for functional layer of CSL API CSL_mcbspHwControl() * / / ============================================================================= * Revision History * ================ * June 29,2004 <NAME> - Created * * July 26, 2005 ds - Removed control cmd CSL_MCBSP_CMD_IO_MODE_CONTROL * * Feb 01, 2006 ds - Removed CSL_MCBSP_CMD_TX_INT_MODE and * CSL_MCBSP_CMD_RX_INT_MODE control commands * ============================================================================= / #include <csl_mcbsp.h> #include <_csl_mcbsp.h> #include <csl_mcbspAux.h> /* ============================================================================ * @n@b CSL_mcbspHwControl * * @b Description * @n This function takes an input control command with an optional argument * and accordingly controls the operation/configuration of MCBSP. * * @b Arguments * @verbatim hMcbsp MCBSP handle returned by successful 'open' cmd Control command arg Optional argument as per the control command @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Command successful * @li CSL_ESYS_INVCMD - The Command passed is invalid * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVPARAMS - The parameter is invalid * * <b> Pre Condition </b> * @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully * in that order before CSL_mcbspHwControl() can be called. * * <b> Post Condition </b> * @n Mcbsp registers are configured according to the command passed * * @b Modifies * @n MCBSP registers * * @b Example * @verbatim CSL_Status status; CSL_BitMask16 ctrlMask; CSL_McbspHandle hMcbsp; ... // MCBSP object defined and HwSetup structure defined and initialized ... // Init successfully done ... // Open successfully done ... // HwSetup sucessfully done ... // MCBSP SRG and Frame sync taken out of reset ... ctrlMask = CSL_MCBSP_CTRL_RX_ENABLE \| CSL_MCBSP_CTRL_TX_ENABLE; status = CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask); ... @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_mcbspHwControl, ".text:csl_section:mcbsp"); CSL_Status CSL_mcbspHwControl ( CSL_McbspHandle hMcbsp, CSL_McbspControlCmd cmd, void arg ) { CSL_Status status = CSL_SOK; CSL_McbspBlkAssign blkAsg; CSL_McbspChanControl ch; CSL_McbspChType chan; CSL_BitMask16 ctrl; if(hMcbsp == NULL) { status=CSL_ESYS_BADHANDLE; } else if(((cmd <= CSL_MCBSP_CMD_RESET_CONTROL) && \ (cmd != CSL_MCBSP_CMD_RESET))&& \ (arg == NULL)) { status=CSL_ESYS_INVPARAMS; } else { switch(cmd) { case CSL_MCBSP_CMD_ASSIGN_BLOCK: blkAsg = (CSL_McbspBlkAssign )arg; _CSL_mcbspBlockAssign(hMcbsp, blkAsg->partition, blkAsg->block); break; case CSL_MCBSP_CMD_CHANNEL_CONTROL: ch = (CSL_McbspChanControl )arg; _CSL_mcbspChannelControl(hMcbsp, (ch->channelNo & 0xf), \ (CSL_McbspBlock)(ch->channelNo >> 4),\ ch->operation); break; case CSL_MCBSP_CMD_CLEAR_FRAME_SYNC: chan = (CSL_McbspChType )arg; _CSL_mcbspClearFrmSyncErr(hMcbsp,chan); break; case CSL_MCBSP_CMD_RESET: _CSL_mcbspRegReset(hMcbsp); break; case CSL_MCBSP_CMD_RESET_CONTROL: ctrl = (CSL_BitMask16 )arg; _CSL_mcbspResetCtrl(hMcbsp, ctrl); break; default: status = CSL_ESYS_INVCMD; break; } } return (status); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455/example/edma/edma_interrupt/src/Edma_interrupt_example.c	<filename>DSP/TI-Header/csl_c6455/example/edma/edma_interrupt/src/Edma_interrupt_example.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * * @file Edma_interrupt_example.c * * @path $(CSLPATH)\example\edma\edma_interrupt\src * * @desc Example of EDMA * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n <b> Example Description </b> * @n This is an example of the CSL EDMA usage along with interrupts * in the context of a shadow region and illustrates a sample EDMA * interrupt handler implementation. This example, * 1. Initializes the CSL EDMA module * 2. Intializes and Sets up the Intc Module for EDMA module * 3. Opens and Sets up Edma module to default values * 4. Opens EDMA channel 0 in the region 1 * 5. Sets up the EDMA PARAM using CSL_edma3ParamSetup() API * 6. Enable the Edma interupt and Channel * 7. Manually triggers the channel 0 * 8. Waits for EDMA transfer to complete * 9. Does the data comparision to ensure the transffered data is proper * or not and * 10. Displays the messages based on step 9 * * ============================================================================= * * <b> Procedure to run the example </b> * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Edma_interrupt_example.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * / / ============================================================================= * Revision History * =============== * 08-Jul-2005 <NAME> File Created * 16-Dec-2005 ds Updated documentation * 28-Mar-2006 ds Added code to disable the region 1 access at * the end of example * ============================================================================ / #include <stdio.h> #include <csl_edma3.h> #include <csl_intc.h> #include <soc.h> #include <edmaCommon.h> / Intc declaration / CSL_IntcContext intcContext; CSL_IntcEventHandlerRecord EventHandler[30]; CSL_IntcObj intcObjEdma; CSL_IntcHandle hIntcEdma; CSL_IntcGlobalEnableState state; CSL_IntcEventHandlerRecord EventRecord; CSL_IntcParam vectId; / Globals / Uint8 srcBuff[512]; Uint8 dstBuff[512]; volatile Uint32 intFlag = 0; Uint32 passStatus = 1; / Edma handle / CSL_Edma3Handle hModule; / Forward declaration / void tcc1Fxn(void); void edma_interrupt_example (void); / * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= / void main(void) { / Invoking a example / edma_interrupt_example (); return; } / * ============================================================================= * @func edma_interrupt_example * * @arg * NONE * * @desc * This is the example routine which perform edma interrupt. * It implements following steps * 1. Intializes and Opens the Edma and Intc module. * 2. Sets up the interrupt for the edma Regoin1. * 3. Sets up the edma module using the API csl_edma3Hwsetup () * 4. Enables the edma region1 using CSL_EDMA3_CMD_DMAREGION_ENABLE. * 5. Opens the channel 0 and get the param handle. * 6. Sets up the edma param entry * 7. Enables the edma interrupt using CSL_EDMA3_CMD_INTR_ENABLE. * 8. Enables the channel using CSL_EDMA3_CMD_CHANNEL_ENABLE * 9. Manually trigger the channel using CSL_EDMA3_CMD_CHANNEL_SET. * 10. Waits for transfer to complete. * 11. Compares the data in the destination buffer is proper or not. * 12. Closes the edma module and channel. * * @return * NONE * * ============================================================================= / void edma_interrupt_example (void) { CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ChannelObj chObj; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Status status; CSL_Edma3HwDmaChannelSetup dmahwSetup; Uint32 loopIndex; / Initialize data buffers / for (loopIndex = 0; loopIndex < 512; loopIndex++) { srcBuff[loopIndex] = loopIndex; dstBuff[loopIndex] = 0; } / Module initialization / status = CSL_edma3Init(&context); if (status != CSL_SOK) { printf ("Edma module initialization failed\n"); return; } / Intc module initialization / intcContext.eventhandlerRecord = EventHandler; intcContext.numEvtEntries = 10; CSL_intcInit(&intcContext); / Enable NMIs / CSL_intcGlobalNmiEnable(); / Enable global interrupts / CSL_intcGlobalEnable(&state); / Opening a intc handle for edma event / vectId = CSL_INTC_VECTID_4; hIntcEdma = CSL_intcOpen (&intcObjEdma, CSL_INTC_EVENTID_EDMA3CC_INT1, \ &vectId , NULL); / Edma module open / hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); if ( (hModule == NULL) \|\| (status != CSL_SOK)) { printf ("Edma module open failed\n"); return; } / Edma module setup / dmahwSetup.paramNum = 0; dmahwSetup.que = CSL_EDMA3_QUE_0; hwSetup.dmaChaSetup = &dmahwSetup; hwSetup.qdmaChaSetup = NULL; status = CSL_edma3HwSetup(hModule,&hwSetup); if (status != CSL_SOK) { printf ("Hardware setup failed\n"); CSL_edma3Close (hModule); return; } / Setup the DRAE masks * DRAE enable(Bits 0-15) for the shadow region 1. / regionAccess.region = CSL_EDMA3_REGION_1 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); if (status != CSL_SOK) { printf("Edma region enable command failed\n"); return; } / Channel open / chAttr.regionNum = CSL_EDMA3_REGION_1; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); if ( (hChannel == NULL) \|\| (status != CSL_SOK)) { printf ("Edma channel open failed\n"); return; } / Get the parameter handle / hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); if (hParamBasic == NULL) { printf("Edma get param handle failed\n"); return; } / Edma parameter entry Setup / myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 1,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(512,1); myParamSetup.dstAddr = (Uint32)dstBuff; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (CSL_EDMA3_LINK_NULL, 1); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0); myParamSetup.cCnt = 1; status = CSL_edma3ParamSetup(hParamBasic,&myParamSetup); if (status != CSL_SOK) { printf ("Edma param setup failed\n"); return; } / Association of an EDMA event handler with the INTC routine / EventRecord.handler = &eventEdmaHandler; EventRecord.arg = (void)(hModule); CSL_intcPlugEventHandler(hIntcEdma,&EventRecord); /* Enabling event edma / CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL); / Hook up the EDMA event with an completion code function handler / EdmaEventHook(1, tcc1Fxn); / Enable interrupts / regionIntr.region = CSL_EDMA3_REGION_1 ; regionIntr.intr = 0x2 ; regionIntr.intrh = 0x0 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr); if (status != CSL_SOK) { printf ("Edma interrupt enable command failed\n"); return; } / Manually trigger the channel / status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL); if (status != CSL_SOK) { printf ("Edma channel set command failed\n"); return; } / Wait for completion / while (!intFlag); / Disable the region 1 access / regionAccess.region = CSL_EDMA3_REGION_1 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_DISABLE, \ &regionAccess); / Verify destination buffer to be equal to the source buffer / if(Verify_Transfer(512, 1, 1, 0, 0, 0, 0, srcBuff, dstBuff,TRUE) == FALSE) passStatus = 0; if (passStatus == 1) printf ("<<EXAMPLE PASSED>>: Edma Interrupt Example Passed\n"); printf ("=============================================================\n"); / Channel close / status = CSL_edma3ChannelClose(hChannel); if (status != CSL_SOK) { printf ("Edma channle close failed\n"); return; } / Edma module close / status = CSL_edma3Close(hModule); if (status != CSL_SOK) { printf ("Edma module close failed\n"); return; } return; } / * ============================================================================= * @func tcc1Fxn * * @arg * NONE * * @desc * This is the interrupt service routine for edma interrupt * * @return * NONE * * ============================================================================= */ void tcc1Fxn(void) { intFlag = 1; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/cfg/csl_cfgOpen.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_cfgOpen.c * * @path $(CSLPATH)\src\cfg * * @desc File for functional layer of CSL API CSL_cfgOpen() * / / ============================================================================= * Revision History * =============== * 11-Apr-2005 Brn Updated the file for doxygen compatibiliy * * 16-Nov-2005 ds Updated the documentation * * 31-Jan-2006 ds Supported to use the CSL_cfgGetBaseAddress() API * ============================================================================= / #include <csl_cfg.h> /* =========================================================================== * @n@b CSL_cfgOpen * * @b Description * @n This function populates the peripheral data object for the instance * and returns a handle to the instance. * The open call sets up the data structures for the particular instance * of CFG device. The device can be re-opened anytime after it has * been normally closed, if so required. The handle returned by this call * is input as an essential argument for rest of the APIs described for * this module. * * @b Arguments * @verbatim pCfgObj Pointer to the CFG instance object cfgNum Instance of the CFG to be opened. pCfgParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * <b> Return Value </b> CSL_CfgHandle * @n Valid CFG instance handle will be returned if status value is * equal to CSL_SOK. * * <b> Pre Condition </b> * @n CSL_cfgInit() has to be called before this function get called * * <b> Post Condition </b> * @n CSL_cfgInit has to be called before calling this function. * Post Condition * 1. The status is returned in the status variable. If status returned is * - CSL_SOK - Valid CFG handle is returned. * - CSL_ESYS_FAIL - The CFG instance is invalid. * - CSL_ESYS_INVPARAMS - The Obj structure passed is invalid * 2. CFG object structure is populated. * * * @b Modifies * @n 1. The status variable * 2. CFG object structure * * @b Example * @verbatim CSL_status status; CSL_CfgObj cfgObj; CSL_CfgHandle hCfg; ... hCfg = CSL_cfgOpen (&cfgObj, CSL_MEMPROT_CONFIG, NULL, &status); @endverbatim * =========================================================================== / #pragma CODE_SECTION (CSL_cfgOpen, ".text:csl_section:cfg"); CSL_CfgHandle CSL_cfgOpen ( CSL_CfgObj pCfgObj, CSL_InstNum cfgNum, CSL_CfgParam pCfgParam, CSL_Status pStatus ) { CSL_CfgHandle hCfg = (CSL_CfgHandle)NULL; CSL_CfgBaseAddress baseAddress; if (pStatus == NULL) { /* do nothing : already the module is initialized to NULL / } else if (pCfgObj == NULL) { pStatus = CSL_ESYS_INVPARAMS; } else { pStatus = CSL_cfgGetBaseAddress(cfgNum, pCfgParam, &baseAddress); if (pStatus == CSL_SOK) { pCfgObj->regs = baseAddress.regs; pCfgObj->cfgNum = (CSL_InstNum)cfgNum; hCfg = (CSL_CfgHandle)pCfgObj; } else { pCfgObj->regs = (CSL_CfgRegsOvly)NULL; pCfgObj->cfgNum = (CSL_InstNum)-1; } } return (hCfg); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiOpen.c	<filename>DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiOpen.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_hpiOpen.c * * @path $(CSLPATH)\src\hpi * * @brief File for functional layer of CSL API @a CSL_hpiOpen() * / #include <csl_hpi.h> /* ============================================================================ * @n@b CSL_hpiOpen * * @b Description * @n This function returns the handle to the HPI controller * instance. This handle is passed to all other CSL APIs. * * @b Arguments * @verbatim hpiObj Pointer to the object that holds reference to the instance of HPI requested after the call. hpiNum Instance of HPI to which a handle is requested. There is only one instance of the hpi available. So, the value for this parameter will be CSL_HPI always. pHpiParam Module specific parameters. status Status of the function call @endverbatim * * <b> Return Value </b> CSL_HpiHandle * @n Valid HPI handle will be returned if * status value is equal to CSL_SOK. * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n 1. The status is returned in the status variable. If status * returned is * @li CSL_SOK - Valid HPI handle is returned * @li CSL_ESYS_FAIL - The HPI instance is invalid * @li CSL_ESYS_INVPARAMS - Invalid parameter * * 2. HPI object structure is populated * * @b Modifies * @n 1. The status variable * * 2. HPI object structure * * @b Example * @verbatim CSL_status status; CSL_HpiObj hpiObj; CSL_HpiHandle hHpi; ... hHpi = CSL_hpiOpen(&hpiObj, CSL_HPI, NULL, &status); ... @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_hpiOpen, ".text:csl_section:hpi"); CSL_HpiHandle CSL_hpiOpen ( CSL_HpiObj pHpiObj, CSL_InstNum hpiNum, CSL_HpiParam pHpiParam, CSL_Status pStatus ) { CSL_HpiHandle hHpi = (CSL_HpiHandle)NULL; CSL_HpiBaseAddress baseAddress; if (pStatus == NULL) { /* do nothing : module handle is already initialized to NULL / } else if (pHpiObj == NULL) { pStatus = CSL_ESYS_INVPARAMS; } else { pStatus = CSL_hpiGetBaseAddress (hpiNum, pHpiParam, &baseAddress); if (pStatus == CSL_SOK) { pHpiObj->regs = baseAddress.regs; pHpiObj->hpiNum = (CSL_InstNum) hpiNum; hHpi = (CSL_HpiHandle) pHpiObj; } else { pHpiObj->regs = (CSL_HpiRegsOvly)NULL; pHpiObj->hpiNum = (CSL_InstNum)-1; } } return (hHpi); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcClose.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* * @file csl_intcClose.c * * @brief File for functional layer of CSL API CSL_intcClose() * * PATH $(CSLPATH)\src\intc / / ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= / #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /* ============================================================================ * @n@b CSL_intcClose * * @b Description * @n This intc Handle can no longer be used to access the event. The event is * de-allocated and further access to the event resources are possible only * after opening the event object again. * * @b Arguments * @verbatim hIntc Handle identifying the event @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Close successful * @li CSL_INTC_BADHANDLE - The handle passed is invalid * * <b> Pre Condition </b> * @n Functions CSL_intcInit() and CSL_intcOpen() have to be called in that * order successfully before calling this function. * * <b> Post Condition </b> * @n The intc CSL APIs can not be called until the intc CSL is reopened * again using CSL_intcOpen() * * @b Modifies * @n None * * @b Example * @verbatim CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; CSL_IntcObj intcObj20; CSL_IntcHandle hIntc20; CSL_IntcEventHandlerRecord recordTable[10]; context.numEvtEntries = 10; context.eventhandlerRecord = &recordTable; // Init Module ... if (CSL_intcInit(&context) != CSL_SOK) { exit; // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId, \ NULL); // Close handle CSL_IntcClose(hIntc20); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_intcClose, ".text:csl_section:intc"); CSL_Status CSL_intcClose ( CSL_IntcHandle hIntc ) { CSL_Status closeStatus = CSL_ESYS_BADHANDLE; Uint32 evt; Uint32 x; Uint32 y; if (hIntc != (CSL_IntcHandle) CSL_INTC_BADHANDLE) { evt = (Uint32)(hIntc->eventId); y = evt >> 5; x = 1 << (evt & 0x1f); asm(" dint"); _CSL_intcAllocMask[y] &= ~x; / clear bit -> unused */ if (_CSL_intcEventOffsetMap[hIntc->eventId] != CSL_INTC_MAPPED_NONE) { _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[hIntc->eventId]].handler = CSL_INTC_EVTHANDLER_NONE; _CSL_intcEventOffsetMap[hIntc->eventId] = CSL_INTC_MAPPED_NONE; } hIntc = (CSL_IntcHandle) CSL_INTC_BADHANDLE; asm(" rint"); closeStatus = CSL_SOK; } return closeStatus; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/inc/csl_ddr2Aux.h	<filename>DSP/TI-Header/csl_c6455_src/inc/csl_ddr2Aux.h<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ / /* ============================================================================ * @file csl_ddr2Aux.h * * @path $(CSLPATH)\inc * * @desc Header file for functional layer of CSL * - The defines inline function definitions * / / ============================================================================= * Revision History * =============== * 11-Apr-2005 RM File Created. * * 05-Oct-2005 NG Updation done according to new register layer * * ============================================================================= / #ifndef _CSL_DDR2AUX_H_ #define _CSL_DDR2AUX_H_ #include <csl_ddr2.h> #ifdef __cplusplus extern "C" { #endif /* * Status query functions of the DDR2 EMIF / /* ============================================================================ * @n@b CSL_ddr2GetRevId * * @b Description * @n Gets the the current value of Rev ID value of DDR2 external memory * interface * * @b Arguments * @verbatim hDdr2 Handle to the external memory interface instance status Revision status structure * @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n assigns the current value of the revision status of DDR2 external * @n memory interface to the rev status structure parameter passed as * parameter * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; CSL_Ddr2ModIdRev status; CSL_ddr2GetRevId(hDdr2, status); ... @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_ddr2GetRevId ( CSL_Ddr2Handle hDdr2, CSL_Ddr2ModIdRev status ) { status->modId = (Uint16)CSL_FEXT(hDdr2->regs->MIDR, DDR2_MIDR_MOD_ID); status->majRev = (Uint8)CSL_FEXT(hDdr2->regs->MIDR, DDR2_MIDR_MJ_REV); status->minRev = (Uint8)CSL_FEXT(hDdr2->regs->MIDR, DDR2_MIDR_MN_REV); } /** ============================================================================ * @n@b CSL_ddr2GetEndian * * @b Description * @n Gets the the current endian of DDR2 emif from the SDRAM Status register * * @b Arguments * @verbatim hDdr2 Handle to the external memory interface instance response holds the endian of DDR2 after function call * @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; Bool response; CSL_ddr2GetEndian(hDdr2, response); ... @endverbatim =========================================================================== / CSL_IDEF_INLINE void CSL_ddr2GetEndian ( CSL_Ddr2Handle hDdr2, Uint8 response ) { (response) = (Uint8)CSL_FEXT(hDdr2->regs->DMCSTAT, DDR2_DMCSTAT_BE); } /* ============================================================================ * @n@b CSL_ddr2GetIFRDY * * @b Description * @n Gets the the current IFRDY status of DDR2 emif from the SDRAM * Status register * * @b Arguments * @verbatim hDdr2 Handle to the external memory interface instance response holds IFRDY status after function call * @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; Bool response; CSL_ddr2GetIFRDY(hDdr2, response); ... @endverbatim ============================================================================ / CSL_IDEF_INLINE void CSL_ddr2GetIFRDY ( CSL_Ddr2Handle hDdr2, Uint8 response ) { (response) = (Uint8)CSL_FEXT(hDdr2->regs->DMCSTAT, DDR2_DMCSTAT_IFRDY); } /* ============================================================================ * @n@b CSL_ddr2GetRefreshRate * * @b Description * @n Gets the refresh rate information of the DDR2 external memory interface * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 external memory interface instance * @endverbatim * * <b> Return Value </b> Uint16 * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; Uint16 rate; rate = CSL_ddr2GetRefreshRate(hDdr2); ... @endverbatim * ============================================================================ / CSL_IDEF_INLINE Uint16 CSL_ddr2GetRefreshRate ( CSL_Ddr2Handle hDdr2 ) { Uint16 rate; rate = (Uint16) CSL_FEXT(hDdr2->regs->SDRFC, DDR2_SDRFC_REFRESH_RATE); return rate; } /* ============================================================================ * @n@b CSL_ddr2GetSlfRfrsh * * @b Description * @n Gets the DDR2 EMIF self refresh status * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 external memory interface instance * @endverbatim * * <b> Return Value </b> CSL_Ddr2SelfRefresh * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; CSL_Ddr2SelfRefresh ddrStatus; ddrStatus = CSL_ddr2GetSlfRfrsh(hDdr2); ... @endverbatim * =========================================================================== / CSL_IDEF_INLINE CSL_Ddr2SelfRefresh CSL_ddr2GetSlfRfrsh ( CSL_Ddr2Handle hDdr2 ) { CSL_Ddr2SelfRefresh status; status = (CSL_Ddr2SelfRefresh)CSL_FEXT(hDdr2->regs->SDRFC, DDR2_SDRFC_SR); return status; } /* * Control command functions external memory interface / /* ============================================================================ * @n@b CSL_ddr2Selfrefresh * * @b Description * This API sets or clears the sr bit in Refresh Control register according * to the arg passed * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 EMIF instance val Value to refresh @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n 1) CSL_ddr2Init () and CSL_ddr2Open should be successfully called. * * <b> Post Condition </b> * @n 1) Setting the bit places DDR2 EMIF into self refresh state * 2) Clearing the bit takes it out of self refresh state * * @b Modifies * @n sr bit in SDRAM Refresh Control register * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; void arg; (CSL_Ddr2SelfRefresh) arg = CSL_DDR2_SELF_REFRESH_ENABLE; ... CSL_ddr2Selfrefresh(hDdr2, arg); ... @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_ddr2Selfrefresh ( CSL_Ddr2Handle hDdr2, CSL_Ddr2SelfRefresh val ) { CSL_FINS(hDdr2->regs->SDRFC, DDR2_SDRFC_SR, val); } /* ============================================================================ * @n@b CSL_ddr2RefreshRate * * @b Description * This API sets the refresh rate value with the value of arg passed as * parameter * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 EMIF instance val refresh rate value @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n CSL_ddr2Init () and CSL_ddr2Open should be successfully called. * * <b> Post Condition </b> * @n DDR2 refresh rate will be set with the argument passed * * @b Modifies * @n SDRAM Refresh control register * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; void arg; (Uint16) arg = 0x00010; ... CSL_ddr2RefreshRate(hDdr2, arg); ... @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_ddr2RefreshRate ( CSL_Ddr2Handle hDdr2, Uint16 refRate ) { CSL_FINS(hDdr2->regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, refRate); } /* ============================================================================ * @n@b CSL_ddr2PrioRaise * * @b Description * This API writes the arg passed into the pr_old_count field of VBUSM * Burst Priority register. * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 EMIF val Value to raise priority value @endverbatim * * <b> Return Value </b> * None * * <b> Pre Condition </b> * @n CSL_ddr2Init () and CSL_ddr2Open should be successfully called. * * <b> Post Condition </b> * @n None * * @b Modifies * @n VBUSM Burst Priority register * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; void arg; (Uint8) arg = 0x00010; ... CSL_ddr2PrioRaise(hDdr2, arg); ... @endverbatim * =========================================================================== / CSL_IDEF_INLINE void CSL_ddr2PrioRaise ( CSL_Ddr2Handle hDdr2, Uint8 val ) { CSL_FINS(hDdr2->regs->BPRIO, DDR2_BPRIO_PRIO_RAISE, val); } #ifdef __cplusplus } #endif #endif / _CSL_DDR2AUX_H_ */
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcHwSetupRaw.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ / /* @file csl_pllcHwSetupRaw.c * * @brief File for functional layer of CSL API @a CSL_pllcHwSetupRaw() * * Path: \(CSLPATH)\src\pllc * / / ============================================================================ * Revision History * =============== * 10-Feb-2004 kpn File Created. * 25-Aug-2005 Tej File Modified. * 17-Jan-2006 sd Changes according to spec changes * ============================================================================ / #include <csl_pllc.h> /* ============================================================================ * @n@b CSL_pllcHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hpllc Handle to the PLLC instance config Pointer to config structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not properly initialized * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The registers of the specified PLLC instance will be setup * according to input configuration structure values. * * @b Modifies * @n Hardware registers of the specified PLLC instance. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcConfig config = CSL_PLLC_CONFIG_DEFAULTS; CSL_Status status; ... status = CSL_pllcHwSetupRaw (hPllc, &config); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_pllcHwSetupRaw, ".text:csl_section:pllc"); CSL_Status CSL_pllcHwSetupRaw ( CSL_PllcHandle hPllc, CSL_PllcConfig config ) { CSL_Status status = CSL_SOK; volatile Uint32 loopCount; if (hPllc == NULL) { status = CSL_ESYS_BADHANDLE; } else if (config == NULL) { status = CSL_ESYS_INVPARAMS; } else { loopCount = 65000; /* Set PLLCTL, PLLENSRC bit to 0 first to modify PLLEN bit / if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLENSRC, CSL_PLLC_PLLCTL_PLLENSRC_REGBIT); / Ensure that PLLCTL is not in the PLL Mode / CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLEN, CSL_PLLC_PLLCTL_PLLEN_BYPASS); CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLRST, CSL_PLLC_PLLCTL_PLLRST_YES); / Ensure that PLLCTL is not in the Power-Down state / CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLPWRDN, CSL_PLLC_PLLCTL_PLLPWRDN_NO); / PLL Multiplier Control register / hPllc->regs->PLLM = config->PLLM; / PLL Pre-Divider Control register / hPllc->regs->PREDIV = config->PREDIV; / PLL Controller Divider 4 register / hPllc->regs->PLLDIV4 = config->PLLDIV4; / PLL Controller Divider 5 register / hPllc->regs->PLLDIV5 = config->PLLDIV5; } / PLL Controller Divider 1 register if instance is 2 / if (hPllc->pllcNum == CSL_PLLC_2) { hPllc->regs->PLLDIV1 = config->PLLDIV1; } / Set GOSET bit to change/set the dividers / CSL_FINS (hPllc->regs->PLLCMD, PLLC_PLLCMD_GOSET, CSL_PLLC_PLLCMD_GOSET_SET); while (CSL_FEXT (hPllc->regs->PLLSTAT, PLLC_PLLSTAT_GOSTAT)) { / Poll for divide-ratio change and clock alignment to complete / } if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLRST, CSL_PLLC_PLLCTL_PLLRST_NO); / Wait for 4 cycles of the slowest of the CLKIN/OSCIN * Introducing some arbitrary delay. / loopCount = 65000; while (loopCount--) { asm(" NOP"); } / PLL Control register */ hPllc->regs->PLLCTL = config->PLLCTL; } } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/FB_Example/main.c	#include <stdio.h> #include <string.h> #include <cslr_pllc.h> #include <cslr_gpio.h> #include <cslr_emifa.h> #include <cslr_ddr2.h> #include <cslr_dev.h> #include <cslr_intc.h> #include <cslr_chip.h> #include <cslr_edma3cc.h> #include <cslr_tmr.h> #include <soc.h> #include <math.h> #include <c6x.h> extern void intcVectorTable(void); #include "main.h" #include "version.h" #include "MEA21_lib.h" char dsp_version[] = "(>)"SW_STRING"(<)"; CSL_GpioRegsOvly gpioRegs = (CSL_GpioRegsOvly)CSL_GPIO_0_REGS; void timer_setup() { CSL_TmrRegsOvly tmr1Regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; // clear TIM12 register CSL_FINST(tmr1Regs->TIMLO,TMR_TIMLO_TIMLO,RESETVAL); CSL_FINS(tmr1Regs->TCR, TMR_TCR_CLKSRC_LO, 0); // select 32 bit unchained mode and take the timer out of reset CSL_FINS(tmr1Regs->TGCR, TMR_TGCR_TIMMODE, 1); // 32bit unchained CSL_FINST(tmr1Regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); } void timer_setperiod(int period) { CSL_TmrRegsOvly tmr1Regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; CSL_FINST(tmr1Regs->TCR, TMR_TCR_ENAMODE_LO, DISABLE); CSL_FINS(tmr1Regs->PRDLO,TMR_PRDLO_PRDLO, period); CSL_FINST(tmr1Regs->TIMLO,TMR_TIMLO_TIMLO,RESETVAL); CSL_FINS(tmr1Regs->TCR, TMR_TCR_ENAMODE_LO, 2); // continous mode } void main() { static int count = 0; int count_test1; int count_test2; static int value = 0; volatile int i; int StimAmplitude; int StimPeriod; int StimRepeats; int StimStepsize; MEA21_init(); // Communication betwen USB and DSP via i2c //init_i2c(); //IER \|= 0x20; // enable CPUINT5 (i2c) WRITE_REGISTER(DSP_INDATA_CTRL, DSPINDATACTRL_VALUE); // Enable Irq and HS1 Data #ifdef USE_SIMULATOR timer_setup(); timer_setperiod(1000); IER \|= 0x80; // enable CPUINT7 (timer) #else timer_setup(); timer_setperiod(13653332); // 10 Hz timer frequency, blink LED with 5 Hz IER \|= 0x80; // enable CPUINT7 (timer) #endif WRITE_REGISTER(0x318, 0x1); // set AUX 1 as output threshold = READ_REGISTER(0x1000); deadtime = READ_REGISTER(0x1004); StimAmplitude = READ_REGISTER(0x1008); StimPeriod = READ_REGISTER(0x100c); StimRepeats = READ_REGISTER(0x1010); StimStepsize = READ_REGISTER(0x1014); // WRITE_REGISTER(0x9200, 0x10000000; // Inititialze STG Memory, use only one segment WRITE_REGISTER(0x9200, 0x20000000); // Inititialze STG Memory, use 256 segments #ifndef USE_SIMULATOR while (READ_REGISTER(0x9200) & 0x30000000); // wait for segment initialization to finish #endif WRITE_REGISTER(0x0310, 0x0); // set AUX 1 to value 0 WRITE_REGISTER(0x0310, 0x1); // set AUX 1 to value one SetSegment(0, 0); // select Segment 0 for DAC 1 SetSegment(1, 0); // select Segment 0 for Sideband 1 UploadSine(0, StimAmplitude, StimPeriod, StimRepeats, StimStepsize); SetSegment(0, 1); // select Segment 1 for DAC 1 SetSegment(1, 1); // select Segment 0 for Sideband 1 UploadSine(0, StimAmplitude/2, StimPeriod, StimRepeats, StimStepsize); WRITE_REGISTER(0x0310, 0x0); // set AUX 1 to value 0 SetupTrigger(); while(1) { WRITE_REGISTER(0x002C, 0x700 + 1value); for (i = 0; i < 100000; i++); value = 1 - value; // switch on/off } } void UploadSine(int Channel, int Amplitude, int Period, int Repeats, int Stepsize) { int yold = 0; int duration = 0; int datapoints = 0; volatile int i; int y; int vectors_used; vectors_used = 0; ClearChannel(Channel); for (i = 0; i < Period; i++) { y = Amplitude sin((((double)i)/Period)23.1415); // y = -(Amplitude i)/Period; if (abs(y - yold) > Stepsize) { vectors_used += AddDataPoint(Channel, duration, yold+0x8000); datapoints++; yold = y; duration = 1; // 20 us } else { duration++; } } vectors_used += AddDataPoint(Channel, duration, yold+0x8000); AddLoop(Channel, vectors_used, Repeats); // Create Sideband Information ClearChannel(Channel+1); vectors_used = 0; vectors_used += AddDataPoint(Channel+1, Period, 0x0019); AddLoop(Channel+1, vectors_used, Repeats); // AddDataPoint(Channel+1, 10, 0x0009); // keep Electrode connected to ground after stimulation } void AddLoop(int Channel, int Vectors, int Repeats) { Uint32 ChannelReg; Uint32 LoopVector; ChannelReg = 0x9f20 + Channel4; if (Repeats > 1) { LoopVector = 0x10000000 \| (Repeats << 16) \| Vectors; WRITE_REGISTER(ChannelReg, LoopVector); } } void SetSegment(int Channel, int Segment) { Uint32 SegmentReg = 0x9200 + Channel0x20; WRITE_REGISTER(SegmentReg, Segment); // Any write to this register clears the Channeldata } void ClearChannel(int Channel) { Uint32 ClearReg = 0x920c + Channel0x20; WRITE_REGISTER(ClearReg, 0); // Any write to this register clears the Channeldata } int AddDataPoint(int Channel, int duration, int value) { int vectors_used = 0; int Vector; Uint32 ChannelReg = 0x9f20 + Channel*4; if (duration > 1000) { Vector = 0x04000000 \| (((duration / 1000) - 1) << 16) \| (value & 0xffff); WRITE_REGISTER(ChannelReg, Vector); // Write Datapoint to STG Memory duration %= 1000; vectors_used++; } if (duration > 0) { Vector = ((duration - 1) << 16) \| (value & 0xffff); WRITE_REGISTER(ChannelReg, Vector); // Write Datapoint to STG Memory vectors_used++; } return vectors_used; } void SetupTrigger() { WRITE_REGISTER(0x0200, 0x1); // Enable Trigger Packets WRITE_REGISTER(0x0204, 0x0); // Setup Trigger WRITE_REGISTER(0x0208, 0x0); // Setup Trigger WRITE_REGISTER(0x020c, 0x0); // Setup Trigger WRITE_REGISTER(0x0210, 0x0); // Setup Trigger WRITE_REGISTER(0x0218, 0x0); // Setup Trigger WRITE_REGISTER(0x021c, 0x0); // Setup Trigger WRITE_REGISTER(0x0220, 0x0); // Setup Trigger WRITE_REGISTER(0x0224, 0x0); // Setup Trigger WRITE_REGISTER(0x0228, 0x0); // Setup Trigger WRITE_REGISTER(0x022c, 0x0); // Setup Trigger WRITE_REGISTER(0x9190, 1); // Trigger 1 Repeat WRITE_REGISTER(0x9194, 1); // Trigger 2 Repeat WRITE_REGISTER(0x9198, 1); // Trigger 3 Repeat WRITE_REGISTER(0x9104, 0x00020100); // DAC1 to Trigger1, DAC2 to Trigger2, DAC3 to Trigger3 WRITE_REGISTER(0x9108, 0x00020100); // SBS1 to Trigger1, SBS2 to Trigger2, SBS3 to Trigger3 } // Mask: Set to 1 for each bit which is to be modified // Value: New Value for modified bits void ModifyRegister(Uint32 reg, Uint32 Mask, Uint32 Value) { Uint32 Temp; Temp = READ_REGISTER(reg); Temp &= ~Mask; Temp \|= (Value & Mask); WRITE_REGISTER(reg, Temp); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspHwSetupRaw.c	<filename>DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspHwSetupRaw.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file csl_mcbspHwSetupRaw.c * * @path $(CSLPATH)\src\mcbsp * * @desc File for functional layer of CSL API CSL_mcbspHwSetupRaw() * / / ============================================================================= * Revision History * =============== * 15-Feb-2005 NSR File Created. * * 04-Jul-2005 ds - Register naming convention used for * multichannel registers are changed according * the changes in cslr_mcbsp.h * 21-Sep-2005 ds - Removed the DXR and DRR register from config * data structure * ============================================================================= / #include <csl_mcbsp.h> /* ============================================================================ * @n@b CSL_mcbspHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hMcbsp Handle to the Mcbsp instance config Pointer to config structure @endverbatim * * <b> Return Value </b> CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not * properly initialized * * <b> Pre Condition </b> * @n Both CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully * in that order before this function can be called. * * <b> Post Condition </b> * @n The registers of the specified MCBSP instance will be configured * according to value passed. * * @b Modifies * @n Hardware registers of the specified MCBSP instance. * * @b Example * @verbatim CSL_McbspHandle hMcbsp; CSL_McbspConfig config; CSL_Status status; config.SPCR = 0x02008000; config.RCR = 0x010001A0; config.XCR = 0x010001A0; config.SRGR = 0x200F010F; config.PCR = 0x00000A00; // Init Successfully done CSL_mcbspInit (NULL); // Open Successfully done hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL, &status); status = CSL_mcbspHwSetupRaw (hMcbsp, &config); @endverbatim * ============================================================================= / #pragma CODE_SECTION (CSL_mcbspHwSetupRaw, ".text:csl_section:mcbsp"); CSL_Status CSL_mcbspHwSetupRaw ( CSL_McbspHandle hMcbsp, CSL_McbspConfig config ) { CSL_Status status = CSL_SOK; if (hMcbsp == NULL) { status = CSL_ESYS_BADHANDLE; } else if (config == NULL ) { status = CSL_ESYS_INVPARAMS; } else{ hMcbsp->regs->SPCR = config->SPCR; hMcbsp->regs->RCR = config->RCR ; hMcbsp->regs->XCR = config->XCR ; hMcbsp->regs->SRGR = config->SRGR; hMcbsp->regs->MCR = config->MCR ; hMcbsp->regs->RCERE0 = config->RCERE0; hMcbsp->regs->XCERE0 = config->XCERE0; hMcbsp->regs->PCR = config->PCR ; hMcbsp->regs->RCERE1 = config->RCERE1; hMcbsp->regs->XCERE1 = config->XCERE1; hMcbsp->regs->RCERE2 = config->RCERE2; hMcbsp->regs->XCERE2 = config->XCERE2; hMcbsp->regs->RCERE3 = config->RCERE3; hMcbsp->regs->XCERE3 = config->XCERE3; } return status; }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c64xplus_intc_src/inc/cslr_intc.h	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / /* ============================================================================ * @file cslr_intc.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for INTC / #ifndef _CSLR_INTC_H_ #define _CSLR_INTC_H_ #include <cslr.h> #include <tistdtypes.h> /************************************************************************\ Register Overlay Structure \************************************************************************/ typedef struct { volatile Uint32 EVTFLAG[4]; volatile Uint8 RSVD0[16]; volatile Uint32 EVTSET[4]; volatile Uint8 RSVD1[16]; volatile Uint32 EVTCLR[4]; volatile Uint8 RSVD2[48]; volatile Uint32 EVTMASK[4]; volatile Uint8 RSVD3[16]; volatile Uint32 MEVTFLAG[4]; volatile Uint8 RSVD4[16]; volatile Uint32 EXPMASK[4]; volatile Uint8 RSVD5[16]; volatile Uint32 MEXPFLAG[4]; volatile Uint8 RSVD6[20]; volatile Uint32 INTMUX1; volatile Uint32 INTMUX2; volatile Uint32 INTMUX3; volatile Uint8 RSVD7[112]; volatile Uint32 INTXSTAT; volatile Uint32 INTXCLR; volatile Uint32 INTDMASK; } CSL_IntcRegs; /***********************************************************************\ Overlay structure typedef definition \*************************************************************************/ typedef volatile CSL_IntcRegs CSL_IntcRegsOvly; /*************************************************************************\ Field Definition Macros \*************************************************************************/ / EVTFLAG / #define CSL_INTC_EVTFLAG_EF31_MASK (0x80000000u) #define CSL_INTC_EVTFLAG_EF31_SHIFT (0x0000001Fu) #define CSL_INTC_EVTFLAG_EF31_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF30_MASK (0x40000000u) #define CSL_INTC_EVTFLAG_EF30_SHIFT (0x0000001Eu) #define CSL_INTC_EVTFLAG_EF30_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF29_MASK (0x20000000u) #define CSL_INTC_EVTFLAG_EF29_SHIFT (0x0000001Du) #define CSL_INTC_EVTFLAG_EF29_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF28_MASK (0x10000000u) #define CSL_INTC_EVTFLAG_EF28_SHIFT (0x0000001Cu) #define CSL_INTC_EVTFLAG_EF28_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF27_MASK (0x08000000u) #define CSL_INTC_EVTFLAG_EF27_SHIFT (0x0000001Bu) #define CSL_INTC_EVTFLAG_EF27_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF26_MASK (0x04000000u) #define CSL_INTC_EVTFLAG_EF26_SHIFT (0x0000001Au) #define CSL_INTC_EVTFLAG_EF26_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF25_MASK (0x02000000u) #define CSL_INTC_EVTFLAG_EF25_SHIFT (0x00000019u) #define CSL_INTC_EVTFLAG_EF25_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF24_MASK (0x01000000u) #define CSL_INTC_EVTFLAG_EF24_SHIFT (0x00000018u) #define CSL_INTC_EVTFLAG_EF24_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF23_MASK (0x00800000u) #define CSL_INTC_EVTFLAG_EF23_SHIFT (0x00000017u) #define CSL_INTC_EVTFLAG_EF23_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF22_MASK (0x00400000u) #define CSL_INTC_EVTFLAG_EF22_SHIFT (0x00000016u) #define CSL_INTC_EVTFLAG_EF22_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF21_MASK (0x00200000u) #define CSL_INTC_EVTFLAG_EF21_SHIFT (0x00000015u) #define CSL_INTC_EVTFLAG_EF21_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF20_MASK (0x00100000u) #define CSL_INTC_EVTFLAG_EF20_SHIFT (0x00000014u) #define CSL_INTC_EVTFLAG_EF20_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF19_MASK (0x00080000u) #define CSL_INTC_EVTFLAG_EF19_SHIFT (0x00000013u) #define CSL_INTC_EVTFLAG_EF19_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF18_MASK (0x00040000u) #define CSL_INTC_EVTFLAG_EF18_SHIFT (0x00000012u) #define CSL_INTC_EVTFLAG_EF18_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF17_MASK (0x00020000u) #define CSL_INTC_EVTFLAG_EF17_SHIFT (0x00000011u) #define CSL_INTC_EVTFLAG_EF17_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF16_MASK (0x00010000u) #define CSL_INTC_EVTFLAG_EF16_SHIFT (0x00000010u) #define CSL_INTC_EVTFLAG_EF16_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF15_MASK (0x00008000u) #define CSL_INTC_EVTFLAG_EF15_SHIFT (0x0000000Fu) #define CSL_INTC_EVTFLAG_EF15_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF14_MASK (0x00004000u) #define CSL_INTC_EVTFLAG_EF14_SHIFT (0x0000000Eu) #define CSL_INTC_EVTFLAG_EF14_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF13_MASK (0x00002000u) #define CSL_INTC_EVTFLAG_EF13_SHIFT (0x0000000Du) #define CSL_INTC_EVTFLAG_EF13_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF12_MASK (0x00001000u) #define CSL_INTC_EVTFLAG_EF12_SHIFT (0x0000000Cu) #define CSL_INTC_EVTFLAG_EF12_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF11_MASK (0x00000800u) #define CSL_INTC_EVTFLAG_EF11_SHIFT (0x0000000Bu) #define CSL_INTC_EVTFLAG_EF11_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF10_MASK (0x00000400u) #define CSL_INTC_EVTFLAG_EF10_SHIFT (0x0000000Au) #define CSL_INTC_EVTFLAG_EF10_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF9_MASK (0x00000200u) #define CSL_INTC_EVTFLAG_EF9_SHIFT (0x00000009u) #define CSL_INTC_EVTFLAG_EF9_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF8_MASK (0x00000100u) #define CSL_INTC_EVTFLAG_EF8_SHIFT (0x00000008u) #define CSL_INTC_EVTFLAG_EF8_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF7_MASK (0x00000080u) #define CSL_INTC_EVTFLAG_EF7_SHIFT (0x00000007u) #define CSL_INTC_EVTFLAG_EF7_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF6_MASK (0x00000040u) #define CSL_INTC_EVTFLAG_EF6_SHIFT (0x00000006u) #define CSL_INTC_EVTFLAG_EF6_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF5_MASK (0x00000020u) #define CSL_INTC_EVTFLAG_EF5_SHIFT (0x00000005u) #define CSL_INTC_EVTFLAG_EF5_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF4_MASK (0x00000010u) #define CSL_INTC_EVTFLAG_EF4_SHIFT (0x00000004u) #define CSL_INTC_EVTFLAG_EF4_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF3_MASK (0x00000008u) #define CSL_INTC_EVTFLAG_EF3_SHIFT (0x00000003u) #define CSL_INTC_EVTFLAG_EF3_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF2_MASK (0x00000004u) #define CSL_INTC_EVTFLAG_EF2_SHIFT (0x00000002u) #define CSL_INTC_EVTFLAG_EF2_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF1_MASK (0x00000002u) #define CSL_INTC_EVTFLAG_EF1_SHIFT (0x00000001u) #define CSL_INTC_EVTFLAG_EF1_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF0_MASK (0x00000001u) #define CSL_INTC_EVTFLAG_EF0_SHIFT (0x00000000u) #define CSL_INTC_EVTFLAG_EF0_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_RESETVAL (0x00000000u) / EVTSET / #define CSL_INTC_EVTSET_ES31_MASK (0x80000000u) #define CSL_INTC_EVTSET_ES31_SHIFT (0x0000001Fu) #define CSL_INTC_EVTSET_ES31_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES30_MASK (0x40000000u) #define CSL_INTC_EVTSET_ES30_SHIFT (0x0000001Eu) #define CSL_INTC_EVTSET_ES30_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES29_MASK (0x20000000u) #define CSL_INTC_EVTSET_ES29_SHIFT (0x0000001Du) #define CSL_INTC_EVTSET_ES29_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES28_MASK (0x10000000u) #define CSL_INTC_EVTSET_ES28_SHIFT (0x0000001Cu) #define CSL_INTC_EVTSET_ES28_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES27_MASK (0x08000000u) #define CSL_INTC_EVTSET_ES27_SHIFT (0x0000001Bu) #define CSL_INTC_EVTSET_ES27_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES26_MASK (0x04000000u) #define CSL_INTC_EVTSET_ES26_SHIFT (0x0000001Au) #define CSL_INTC_EVTSET_ES26_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES25_MASK (0x02000000u) #define CSL_INTC_EVTSET_ES25_SHIFT (0x00000019u) #define CSL_INTC_EVTSET_ES25_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES24_MASK (0x01000000u) #define CSL_INTC_EVTSET_ES24_SHIFT (0x00000018u) #define CSL_INTC_EVTSET_ES24_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES23_MASK (0x00800000u) #define CSL_INTC_EVTSET_ES23_SHIFT (0x00000017u) #define CSL_INTC_EVTSET_ES23_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES22_MASK (0x00400000u) #define CSL_INTC_EVTSET_ES22_SHIFT (0x00000016u) #define CSL_INTC_EVTSET_ES22_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES21_MASK (0x00200000u) #define CSL_INTC_EVTSET_ES21_SHIFT (0x00000015u) #define CSL_INTC_EVTSET_ES21_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES20_MASK (0x00100000u) #define CSL_INTC_EVTSET_ES20_SHIFT (0x00000014u) #define CSL_INTC_EVTSET_ES20_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES19_MASK (0x00080000u) #define CSL_INTC_EVTSET_ES19_SHIFT (0x00000013u) #define CSL_INTC_EVTSET_ES19_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES18_MASK (0x00040000u) #define CSL_INTC_EVTSET_ES18_SHIFT (0x00000012u) #define CSL_INTC_EVTSET_ES18_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES17_MASK (0x00020000u) #define CSL_INTC_EVTSET_ES17_SHIFT (0x00000011u) #define CSL_INTC_EVTSET_ES17_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES16_MASK (0x00010000u) #define CSL_INTC_EVTSET_ES16_SHIFT (0x00000010u) #define CSL_INTC_EVTSET_ES16_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES15_MASK (0x00008000u) #define CSL_INTC_EVTSET_ES15_SHIFT (0x0000000Fu) #define CSL_INTC_EVTSET_ES15_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES14_MASK (0x00004000u) #define CSL_INTC_EVTSET_ES14_SHIFT (0x0000000Eu) #define CSL_INTC_EVTSET_ES14_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES13_MASK (0x00002000u) #define CSL_INTC_EVTSET_ES13_SHIFT (0x0000000Du) #define CSL_INTC_EVTSET_ES13_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES12_MASK (0x00001000u) #define CSL_INTC_EVTSET_ES12_SHIFT (0x0000000Cu) #define CSL_INTC_EVTSET_ES12_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES11_MASK (0x00000800u) #define CSL_INTC_EVTSET_ES11_SHIFT (0x0000000Bu) #define CSL_INTC_EVTSET_ES11_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES10_MASK (0x00000400u) #define CSL_INTC_EVTSET_ES10_SHIFT (0x0000000Au) #define CSL_INTC_EVTSET_ES10_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES9_MASK (0x00000200u) #define CSL_INTC_EVTSET_ES9_SHIFT (0x00000009u) #define CSL_INTC_EVTSET_ES9_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES8_MASK (0x00000100u) #define CSL_INTC_EVTSET_ES8_SHIFT (0x00000008u) #define CSL_INTC_EVTSET_ES8_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES7_MASK (0x00000080u) #define CSL_INTC_EVTSET_ES7_SHIFT (0x00000007u) #define CSL_INTC_EVTSET_ES7_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES6_MASK (0x00000040u) #define CSL_INTC_EVTSET_ES6_SHIFT (0x00000006u) #define CSL_INTC_EVTSET_ES6_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES5_MASK (0x00000020u) #define CSL_INTC_EVTSET_ES5_SHIFT (0x00000005u) #define CSL_INTC_EVTSET_ES5_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES4_MASK (0x00000010u) #define CSL_INTC_EVTSET_ES4_SHIFT (0x00000004u) #define CSL_INTC_EVTSET_ES4_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES3_MASK (0x00000008u) #define CSL_INTC_EVTSET_ES3_SHIFT (0x00000003u) #define CSL_INTC_EVTSET_ES3_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES2_MASK (0x00000004u) #define CSL_INTC_EVTSET_ES2_SHIFT (0x00000002u) #define CSL_INTC_EVTSET_ES2_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES1_MASK (0x00000002u) #define CSL_INTC_EVTSET_ES1_SHIFT (0x00000001u) #define CSL_INTC_EVTSET_ES1_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES0_MASK (0x00000001u) #define CSL_INTC_EVTSET_ES0_SHIFT (0x00000000u) #define CSL_INTC_EVTSET_ES0_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_RESETVAL (0x00000000u) / EVTCLR / #define CSL_INTC_EVTCLR_EC31_MASK (0x80000000u) #define CSL_INTC_EVTCLR_EC31_SHIFT (0x0000001Fu) #define CSL_INTC_EVTCLR_EC31_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC30_MASK (0x40000000u) #define CSL_INTC_EVTCLR_EC30_SHIFT (0x0000001Eu) #define CSL_INTC_EVTCLR_EC30_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC29_MASK (0x20000000u) #define CSL_INTC_EVTCLR_EC29_SHIFT (0x0000001Du) #define CSL_INTC_EVTCLR_EC29_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC28_MASK (0x10000000u) #define CSL_INTC_EVTCLR_EC28_SHIFT (0x0000001Cu) #define CSL_INTC_EVTCLR_EC28_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC27_MASK (0x08000000u) #define CSL_INTC_EVTCLR_EC27_SHIFT (0x0000001Bu) #define CSL_INTC_EVTCLR_EC27_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC26_MASK (0x04000000u) #define CSL_INTC_EVTCLR_EC26_SHIFT (0x0000001Au) #define CSL_INTC_EVTCLR_EC26_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC25_MASK (0x02000000u) #define CSL_INTC_EVTCLR_EC25_SHIFT (0x00000019u) #define CSL_INTC_EVTCLR_EC25_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC24_MASK (0x01000000u) #define CSL_INTC_EVTCLR_EC24_SHIFT (0x00000018u) #define CSL_INTC_EVTCLR_EC24_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC23_MASK (0x00800000u) #define CSL_INTC_EVTCLR_EC23_SHIFT (0x00000017u) #define CSL_INTC_EVTCLR_EC23_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC22_MASK (0x00400000u) #define CSL_INTC_EVTCLR_EC22_SHIFT (0x00000016u) #define CSL_INTC_EVTCLR_EC22_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC21_MASK (0x00200000u) #define CSL_INTC_EVTCLR_EC21_SHIFT (0x00000015u) #define CSL_INTC_EVTCLR_EC21_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC20_MASK (0x00100000u) #define CSL_INTC_EVTCLR_EC20_SHIFT (0x00000014u) #define CSL_INTC_EVTCLR_EC20_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC19_MASK (0x00080000u) #define CSL_INTC_EVTCLR_EC19_SHIFT (0x00000013u) #define CSL_INTC_EVTCLR_EC19_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC18_MASK (0x00040000u) #define CSL_INTC_EVTCLR_EC18_SHIFT (0x00000012u) #define CSL_INTC_EVTCLR_EC18_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC17_MASK (0x00020000u) #define CSL_INTC_EVTCLR_EC17_SHIFT (0x00000011u) #define CSL_INTC_EVTCLR_EC17_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC16_MASK (0x00010000u) #define CSL_INTC_EVTCLR_EC16_SHIFT (0x00000010u) #define CSL_INTC_EVTCLR_EC16_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC15_MASK (0x00008000u) #define CSL_INTC_EVTCLR_EC15_SHIFT (0x0000000Fu) #define CSL_INTC_EVTCLR_EC15_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC14_MASK (0x00004000u) #define CSL_INTC_EVTCLR_EC14_SHIFT (0x0000000Eu) #define CSL_INTC_EVTCLR_EC14_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC13_MASK (0x00002000u) #define CSL_INTC_EVTCLR_EC13_SHIFT (0x0000000Du) #define CSL_INTC_EVTCLR_EC13_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC12_MASK (0x00001000u) #define CSL_INTC_EVTCLR_EC12_SHIFT (0x0000000Cu) #define CSL_INTC_EVTCLR_EC12_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC11_MASK (0x00000800u) #define CSL_INTC_EVTCLR_EC11_SHIFT (0x0000000Bu) #define CSL_INTC_EVTCLR_EC11_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC10_MASK (0x00000400u) #define CSL_INTC_EVTCLR_EC10_SHIFT (0x0000000Au) #define CSL_INTC_EVTCLR_EC10_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC9_MASK (0x00000200u) #define CSL_INTC_EVTCLR_EC9_SHIFT (0x00000009u) #define CSL_INTC_EVTCLR_EC9_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC8_MASK (0x00000100u) #define CSL_INTC_EVTCLR_EC8_SHIFT (0x00000008u) #define CSL_INTC_EVTCLR_EC8_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC7_MASK (0x00000080u) #define CSL_INTC_EVTCLR_EC7_SHIFT (0x00000007u) #define CSL_INTC_EVTCLR_EC7_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC6_MASK (0x00000040u) #define CSL_INTC_EVTCLR_EC6_SHIFT (0x00000006u) #define CSL_INTC_EVTCLR_EC6_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC5_MASK (0x00000020u) #define CSL_INTC_EVTCLR_EC5_SHIFT (0x00000005u) #define CSL_INTC_EVTCLR_EC5_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC4_MASK (0x00000010u) #define CSL_INTC_EVTCLR_EC4_SHIFT (0x00000004u) #define CSL_INTC_EVTCLR_EC4_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC3_MASK (0x00000008u) #define CSL_INTC_EVTCLR_EC3_SHIFT (0x00000003u) #define CSL_INTC_EVTCLR_EC3_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC2_MASK (0x00000004u) #define CSL_INTC_EVTCLR_EC2_SHIFT (0x00000002u) #define CSL_INTC_EVTCLR_EC2_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC1_MASK (0x00000002u) #define CSL_INTC_EVTCLR_EC1_SHIFT (0x00000001u) #define CSL_INTC_EVTCLR_EC1_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC0_MASK (0x00000001u) #define CSL_INTC_EVTCLR_EC0_SHIFT (0x00000000u) #define CSL_INTC_EVTCLR_EC0_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_RESETVAL (0x00000000u) / EVTMASK / #define CSL_INTC_EVTMASK_EM31_MASK (0x80000000u) #define CSL_INTC_EVTMASK_EM31_SHIFT (0x0000001Fu) #define CSL_INTC_EVTMASK_EM31_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM30_MASK (0x40000000u) #define CSL_INTC_EVTMASK_EM30_SHIFT (0x0000001Eu) #define CSL_INTC_EVTMASK_EM30_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM29_MASK (0x20000000u) #define CSL_INTC_EVTMASK_EM29_SHIFT (0x0000001Du) #define CSL_INTC_EVTMASK_EM29_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM28_MASK (0x10000000u) #define CSL_INTC_EVTMASK_EM28_SHIFT (0x0000001Cu) #define CSL_INTC_EVTMASK_EM28_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM27_MASK (0x08000000u) #define CSL_INTC_EVTMASK_EM27_SHIFT (0x0000001Bu) #define CSL_INTC_EVTMASK_EM27_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM26_MASK (0x04000000u) #define CSL_INTC_EVTMASK_EM26_SHIFT (0x0000001Au) #define CSL_INTC_EVTMASK_EM26_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM25_MASK (0x02000000u) #define CSL_INTC_EVTMASK_EM25_SHIFT (0x00000019u) #define CSL_INTC_EVTMASK_EM25_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM24_MASK (0x01000000u) #define CSL_INTC_EVTMASK_EM24_SHIFT (0x00000018u) #define CSL_INTC_EVTMASK_EM24_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM23_MASK (0x00800000u) #define CSL_INTC_EVTMASK_EM23_SHIFT (0x00000017u) #define CSL_INTC_EVTMASK_EM23_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM22_MASK (0x00400000u) #define CSL_INTC_EVTMASK_EM22_SHIFT (0x00000016u) #define CSL_INTC_EVTMASK_EM22_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM21_MASK (0x00200000u) #define CSL_INTC_EVTMASK_EM21_SHIFT (0x00000015u) #define CSL_INTC_EVTMASK_EM21_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM20_MASK (0x00100000u) #define CSL_INTC_EVTMASK_EM20_SHIFT (0x00000014u) #define CSL_INTC_EVTMASK_EM20_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM19_MASK (0x00080000u) #define CSL_INTC_EVTMASK_EM19_SHIFT (0x00000013u) #define CSL_INTC_EVTMASK_EM19_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM18_MASK (0x00040000u) #define CSL_INTC_EVTMASK_EM18_SHIFT (0x00000012u) #define CSL_INTC_EVTMASK_EM18_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM17_MASK (0x00020000u) #define CSL_INTC_EVTMASK_EM17_SHIFT (0x00000011u) #define CSL_INTC_EVTMASK_EM17_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM16_MASK (0x00010000u) #define CSL_INTC_EVTMASK_EM16_SHIFT (0x00000010u) #define CSL_INTC_EVTMASK_EM16_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM15_MASK (0x00008000u) #define CSL_INTC_EVTMASK_EM15_SHIFT (0x0000000Fu) #define CSL_INTC_EVTMASK_EM15_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM14_MASK (0x00004000u) #define CSL_INTC_EVTMASK_EM14_SHIFT (0x0000000Eu) #define CSL_INTC_EVTMASK_EM14_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM13_MASK (0x00002000u) #define CSL_INTC_EVTMASK_EM13_SHIFT (0x0000000Du) #define CSL_INTC_EVTMASK_EM13_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM12_MASK (0x00001000u) #define CSL_INTC_EVTMASK_EM12_SHIFT (0x0000000Cu) #define CSL_INTC_EVTMASK_EM12_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM11_MASK (0x00000800u) #define CSL_INTC_EVTMASK_EM11_SHIFT (0x0000000Bu) #define CSL_INTC_EVTMASK_EM11_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM10_MASK (0x00000400u) #define CSL_INTC_EVTMASK_EM10_SHIFT (0x0000000Au) #define CSL_INTC_EVTMASK_EM10_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM9_MASK (0x00000200u) #define CSL_INTC_EVTMASK_EM9_SHIFT (0x00000009u) #define CSL_INTC_EVTMASK_EM9_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM8_MASK (0x00000100u) #define CSL_INTC_EVTMASK_EM8_SHIFT (0x00000008u) #define CSL_INTC_EVTMASK_EM8_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM7_MASK (0x00000080u) #define CSL_INTC_EVTMASK_EM7_SHIFT (0x00000007u) #define CSL_INTC_EVTMASK_EM7_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM6_MASK (0x00000040u) #define CSL_INTC_EVTMASK_EM6_SHIFT (0x00000006u) #define CSL_INTC_EVTMASK_EM6_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM5_MASK (0x00000020u) #define CSL_INTC_EVTMASK_EM5_SHIFT (0x00000005u) #define CSL_INTC_EVTMASK_EM5_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM4_MASK (0x00000010u) #define CSL_INTC_EVTMASK_EM4_SHIFT (0x00000004u) #define CSL_INTC_EVTMASK_EM4_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM3_MASK (0x00000008u) #define CSL_INTC_EVTMASK_EM3_SHIFT (0x00000003u) #define CSL_INTC_EVTMASK_EM3_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM2_MASK (0x00000004u) #define CSL_INTC_EVTMASK_EM2_SHIFT (0x00000002u) #define CSL_INTC_EVTMASK_EM2_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM1_MASK (0x00000002u) #define CSL_INTC_EVTMASK_EM1_SHIFT (0x00000001u) #define CSL_INTC_EVTMASK_EM1_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM0_MASK (0x00000001u) #define CSL_INTC_EVTMASK_EM0_SHIFT (0x00000000u) #define CSL_INTC_EVTMASK_EM0_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_RESETVAL (0x00000000u) / MEVTFLAG / #define CSL_INTC_MEVTFLAG_MEVT31_MASK (0x80000000u) #define CSL_INTC_MEVTFLAG_MEVT31_SHIFT (0x0000001Fu) #define CSL_INTC_MEVTFLAG_MEVT31_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT30_MASK (0x40000000u) #define CSL_INTC_MEVTFLAG_MEVT30_SHIFT (0x0000001Eu) #define CSL_INTC_MEVTFLAG_MEVT30_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT29_MASK (0x20000000u) #define CSL_INTC_MEVTFLAG_MEVT29_SHIFT (0x0000001Du) #define CSL_INTC_MEVTFLAG_MEVT29_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT28_MASK (0x10000000u) #define CSL_INTC_MEVTFLAG_MEVT28_SHIFT (0x0000001Cu) #define CSL_INTC_MEVTFLAG_MEVT28_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT27_MASK (0x08000000u) #define CSL_INTC_MEVTFLAG_MEVT27_SHIFT (0x0000001Bu) #define CSL_INTC_MEVTFLAG_MEVT27_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT26_MASK (0x04000000u) #define CSL_INTC_MEVTFLAG_MEVT26_SHIFT (0x0000001Au) #define CSL_INTC_MEVTFLAG_MEVT26_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT25_MASK (0x02000000u) #define CSL_INTC_MEVTFLAG_MEVT25_SHIFT (0x00000019u) #define CSL_INTC_MEVTFLAG_MEVT25_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT24_MASK (0x01000000u) #define CSL_INTC_MEVTFLAG_MEVT24_SHIFT (0x00000018u) #define CSL_INTC_MEVTFLAG_MEVT24_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT23_MASK (0x00800000u) #define CSL_INTC_MEVTFLAG_MEVT23_SHIFT (0x00000017u) #define CSL_INTC_MEVTFLAG_MEVT23_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT22_MASK (0x00400000u) #define CSL_INTC_MEVTFLAG_MEVT22_SHIFT (0x00000016u) #define CSL_INTC_MEVTFLAG_MEVT22_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT21_MASK (0x00200000u) #define CSL_INTC_MEVTFLAG_MEVT21_SHIFT (0x00000015u) #define CSL_INTC_MEVTFLAG_MEVT21_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT20_MASK (0x00100000u) #define CSL_INTC_MEVTFLAG_MEVT20_SHIFT (0x00000014u) #define CSL_INTC_MEVTFLAG_MEVT20_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT19_MASK (0x00080000u) #define CSL_INTC_MEVTFLAG_MEVT19_SHIFT (0x00000013u) #define CSL_INTC_MEVTFLAG_MEVT19_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT18_MASK (0x00040000u) #define CSL_INTC_MEVTFLAG_MEVT18_SHIFT (0x00000012u) #define CSL_INTC_MEVTFLAG_MEVT18_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT17_MASK (0x00020000u) #define CSL_INTC_MEVTFLAG_MEVT17_SHIFT (0x00000011u) #define CSL_INTC_MEVTFLAG_MEVT17_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT16_MASK (0x00010000u) #define CSL_INTC_MEVTFLAG_MEVT16_SHIFT (0x00000010u) #define CSL_INTC_MEVTFLAG_MEVT16_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT15_MASK (0x00008000u) #define CSL_INTC_MEVTFLAG_MEVT15_SHIFT (0x0000000Fu) #define CSL_INTC_MEVTFLAG_MEVT15_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT14_MASK (0x00004000u) #define CSL_INTC_MEVTFLAG_MEVT14_SHIFT (0x0000000Eu) #define CSL_INTC_MEVTFLAG_MEVT14_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT13_MASK (0x00002000u) #define CSL_INTC_MEVTFLAG_MEVT13_SHIFT (0x0000000Du) #define CSL_INTC_MEVTFLAG_MEVT13_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT12_MASK (0x00001000u) #define CSL_INTC_MEVTFLAG_MEVT12_SHIFT (0x0000000Cu) #define CSL_INTC_MEVTFLAG_MEVT12_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT11_MASK (0x00000800u) #define CSL_INTC_MEVTFLAG_MEVT11_SHIFT (0x0000000Bu) #define CSL_INTC_MEVTFLAG_MEVT11_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT10_MASK (0x00000400u) #define CSL_INTC_MEVTFLAG_MEVT10_SHIFT (0x0000000Au) #define CSL_INTC_MEVTFLAG_MEVT10_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT9_MASK (0x00000200u) #define CSL_INTC_MEVTFLAG_MEVT9_SHIFT (0x00000009u) #define CSL_INTC_MEVTFLAG_MEVT9_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT8_MASK (0x00000100u) #define CSL_INTC_MEVTFLAG_MEVT8_SHIFT (0x00000008u) #define CSL_INTC_MEVTFLAG_MEVT8_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT7_MASK (0x00000080u) #define CSL_INTC_MEVTFLAG_MEVT7_SHIFT (0x00000007u) #define CSL_INTC_MEVTFLAG_MEVT7_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT6_MASK (0x00000040u) #define CSL_INTC_MEVTFLAG_MEVT6_SHIFT (0x00000006u) #define CSL_INTC_MEVTFLAG_MEVT6_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT5_MASK (0x00000020u) #define CSL_INTC_MEVTFLAG_MEVT5_SHIFT (0x00000005u) #define CSL_INTC_MEVTFLAG_MEVT5_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT4_MASK (0x00000010u) #define CSL_INTC_MEVTFLAG_MEVT4_SHIFT (0x00000004u) #define CSL_INTC_MEVTFLAG_MEVT4_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT3_MASK (0x00000008u) #define CSL_INTC_MEVTFLAG_MEVT3_SHIFT (0x00000003u) #define CSL_INTC_MEVTFLAG_MEVT3_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT2_MASK (0x00000004u) #define CSL_INTC_MEVTFLAG_MEVT2_SHIFT (0x00000002u) #define CSL_INTC_MEVTFLAG_MEVT2_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT1_MASK (0x00000002u) #define CSL_INTC_MEVTFLAG_MEVT1_SHIFT (0x00000001u) #define CSL_INTC_MEVTFLAG_MEVT1_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT0_MASK (0x00000001u) #define CSL_INTC_MEVTFLAG_MEVT0_SHIFT (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT0_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_RESETVAL (0x00000000u) / EXPMASK / #define CSL_INTC_EXPMASK_XM31_MASK (0x80000000u) #define CSL_INTC_EXPMASK_XM31_SHIFT (0x0000001Fu) #define CSL_INTC_EXPMASK_XM31_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM30_MASK (0x40000000u) #define CSL_INTC_EXPMASK_XM30_SHIFT (0x0000001Eu) #define CSL_INTC_EXPMASK_XM30_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM29_MASK (0x20000000u) #define CSL_INTC_EXPMASK_XM29_SHIFT (0x0000001Du) #define CSL_INTC_EXPMASK_XM29_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM28_MASK (0x10000000u) #define CSL_INTC_EXPMASK_XM28_SHIFT (0x0000001Cu) #define CSL_INTC_EXPMASK_XM28_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM27_MASK (0x08000000u) #define CSL_INTC_EXPMASK_XM27_SHIFT (0x0000001Bu) #define CSL_INTC_EXPMASK_XM27_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM26_MASK (0x04000000u) #define CSL_INTC_EXPMASK_XM26_SHIFT (0x0000001Au) #define CSL_INTC_EXPMASK_XM26_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM25_MASK (0x02000000u) #define CSL_INTC_EXPMASK_XM25_SHIFT (0x00000019u) #define CSL_INTC_EXPMASK_XM25_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM24_MASK (0x01000000u) #define CSL_INTC_EXPMASK_XM24_SHIFT (0x00000018u) #define CSL_INTC_EXPMASK_XM24_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM23_MASK (0x00800000u) #define CSL_INTC_EXPMASK_XM23_SHIFT (0x00000017u) #define CSL_INTC_EXPMASK_XM23_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM22_MASK (0x00400000u) #define CSL_INTC_EXPMASK_XM22_SHIFT (0x00000016u) #define CSL_INTC_EXPMASK_XM22_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM21_MASK (0x00200000u) #define CSL_INTC_EXPMASK_XM21_SHIFT (0x00000015u) #define CSL_INTC_EXPMASK_XM21_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM20_MASK (0x00100000u) #define CSL_INTC_EXPMASK_XM20_SHIFT (0x00000014u) #define CSL_INTC_EXPMASK_XM20_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM19_MASK (0x00080000u) #define CSL_INTC_EXPMASK_XM19_SHIFT (0x00000013u) #define CSL_INTC_EXPMASK_XM19_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM18_MASK (0x00040000u) #define CSL_INTC_EXPMASK_XM18_SHIFT (0x00000012u) #define CSL_INTC_EXPMASK_XM18_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM17_MASK (0x00020000u) #define CSL_INTC_EXPMASK_XM17_SHIFT (0x00000011u) #define CSL_INTC_EXPMASK_XM17_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM16_MASK (0x00010000u) #define CSL_INTC_EXPMASK_XM16_SHIFT (0x00000010u) #define CSL_INTC_EXPMASK_XM16_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM15_MASK (0x00008000u) #define CSL_INTC_EXPMASK_XM15_SHIFT (0x0000000Fu) #define CSL_INTC_EXPMASK_XM15_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM14_MASK (0x00004000u) #define CSL_INTC_EXPMASK_XM14_SHIFT (0x0000000Eu) #define CSL_INTC_EXPMASK_XM14_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM13_MASK (0x00002000u) #define CSL_INTC_EXPMASK_XM13_SHIFT (0x0000000Du) #define CSL_INTC_EXPMASK_XM13_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM12_MASK (0x00001000u) #define CSL_INTC_EXPMASK_XM12_SHIFT (0x0000000Cu) #define CSL_INTC_EXPMASK_XM12_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM11_MASK (0x00000800u) #define CSL_INTC_EXPMASK_XM11_SHIFT (0x0000000Bu) #define CSL_INTC_EXPMASK_XM11_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM10_MASK (0x00000400u) #define CSL_INTC_EXPMASK_XM10_SHIFT (0x0000000Au) #define CSL_INTC_EXPMASK_XM10_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM9_MASK (0x00000200u) #define CSL_INTC_EXPMASK_XM9_SHIFT (0x00000009u) #define CSL_INTC_EXPMASK_XM9_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM8_MASK (0x00000100u) #define CSL_INTC_EXPMASK_XM8_SHIFT (0x00000008u) #define CSL_INTC_EXPMASK_XM8_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM7_MASK (0x00000080u) #define CSL_INTC_EXPMASK_XM7_SHIFT (0x00000007u) #define CSL_INTC_EXPMASK_XM7_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM6_MASK (0x00000040u) #define CSL_INTC_EXPMASK_XM6_SHIFT (0x00000006u) #define CSL_INTC_EXPMASK_XM6_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM5_MASK (0x00000020u) #define CSL_INTC_EXPMASK_XM5_SHIFT (0x00000005u) #define CSL_INTC_EXPMASK_XM5_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM4_MASK (0x00000010u) #define CSL_INTC_EXPMASK_XM4_SHIFT (0x00000004u) #define CSL_INTC_EXPMASK_XM4_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM3_MASK (0x00000008u) #define CSL_INTC_EXPMASK_XM3_SHIFT (0x00000003u) #define CSL_INTC_EXPMASK_XM3_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM2_MASK (0x00000004u) #define CSL_INTC_EXPMASK_XM2_SHIFT (0x00000002u) #define CSL_INTC_EXPMASK_XM2_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM1_MASK (0x00000002u) #define CSL_INTC_EXPMASK_XM1_SHIFT (0x00000001u) #define CSL_INTC_EXPMASK_XM1_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM0_MASK (0x00000001u) #define CSL_INTC_EXPMASK_XM0_SHIFT (0x00000000u) #define CSL_INTC_EXPMASK_XM0_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_RESETVAL (0xFFFFFFFFu) / MEXPFLAG / #define CSL_INTC_MEXPFLAG_MEXP31_MASK (0x80000000u) #define CSL_INTC_MEXPFLAG_MEXP31_SHIFT (0x0000001Fu) #define CSL_INTC_MEXPFLAG_MEXP31_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP30_MASK (0x40000000u) #define CSL_INTC_MEXPFLAG_MEXP30_SHIFT (0x0000001Eu) #define CSL_INTC_MEXPFLAG_MEXP30_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP29_MASK (0x20000000u) #define CSL_INTC_MEXPFLAG_MEXP29_SHIFT (0x0000001Du) #define CSL_INTC_MEXPFLAG_MEXP29_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP28_MASK (0x10000000u) #define CSL_INTC_MEXPFLAG_MEXP28_SHIFT (0x0000001Cu) #define CSL_INTC_MEXPFLAG_MEXP28_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP27_MASK (0x08000000u) #define CSL_INTC_MEXPFLAG_MEXP27_SHIFT (0x0000001Bu) #define CSL_INTC_MEXPFLAG_MEXP27_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP26_MASK (0x04000000u) #define CSL_INTC_MEXPFLAG_MEXP26_SHIFT (0x0000001Au) #define CSL_INTC_MEXPFLAG_MEXP26_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP25_MASK (0x02000000u) #define CSL_INTC_MEXPFLAG_MEXP25_SHIFT (0x00000019u) #define CSL_INTC_MEXPFLAG_MEXP25_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP24_MASK (0x01000000u) #define CSL_INTC_MEXPFLAG_MEXP24_SHIFT (0x00000018u) #define CSL_INTC_MEXPFLAG_MEXP24_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP23_MASK (0x00800000u) #define CSL_INTC_MEXPFLAG_MEXP23_SHIFT (0x00000017u) #define CSL_INTC_MEXPFLAG_MEXP23_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP22_MASK (0x00400000u) #define CSL_INTC_MEXPFLAG_MEXP22_SHIFT (0x00000016u) #define CSL_INTC_MEXPFLAG_MEXP22_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP21_MASK (0x00200000u) #define CSL_INTC_MEXPFLAG_MEXP21_SHIFT (0x00000015u) #define CSL_INTC_MEXPFLAG_MEXP21_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP20_MASK (0x00100000u) #define CSL_INTC_MEXPFLAG_MEXP20_SHIFT (0x00000014u) #define CSL_INTC_MEXPFLAG_MEXP20_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP19_MASK (0x00080000u) #define CSL_INTC_MEXPFLAG_MEXP19_SHIFT (0x00000013u) #define CSL_INTC_MEXPFLAG_MEXP19_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP18_MASK (0x00040000u) #define CSL_INTC_MEXPFLAG_MEXP18_SHIFT (0x00000012u) #define CSL_INTC_MEXPFLAG_MEXP18_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP17_MASK (0x00020000u) #define CSL_INTC_MEXPFLAG_MEXP17_SHIFT (0x00000011u) #define CSL_INTC_MEXPFLAG_MEXP17_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP16_MASK (0x00010000u) #define CSL_INTC_MEXPFLAG_MEXP16_SHIFT (0x00000010u) #define CSL_INTC_MEXPFLAG_MEXP16_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP15_MASK (0x00008000u) #define CSL_INTC_MEXPFLAG_MEXP15_SHIFT (0x0000000Fu) #define CSL_INTC_MEXPFLAG_MEXP15_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP14_MASK (0x00004000u) #define CSL_INTC_MEXPFLAG_MEXP14_SHIFT (0x0000000Eu) #define CSL_INTC_MEXPFLAG_MEXP14_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP13_MASK (0x00002000u) #define CSL_INTC_MEXPFLAG_MEXP13_SHIFT (0x0000000Du) #define CSL_INTC_MEXPFLAG_MEXP13_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP12_MASK (0x00001000u) #define CSL_INTC_MEXPFLAG_MEXP12_SHIFT (0x0000000Cu) #define CSL_INTC_MEXPFLAG_MEXP12_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP11_MASK (0x00000800u) #define CSL_INTC_MEXPFLAG_MEXP11_SHIFT (0x0000000Bu) #define CSL_INTC_MEXPFLAG_MEXP11_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP10_MASK (0x00000400u) #define CSL_INTC_MEXPFLAG_MEXP10_SHIFT (0x0000000Au) #define CSL_INTC_MEXPFLAG_MEXP10_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP9_MASK (0x00000200u) #define CSL_INTC_MEXPFLAG_MEXP9_SHIFT (0x00000009u) #define CSL_INTC_MEXPFLAG_MEXP9_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP8_MASK (0x00000100u) #define CSL_INTC_MEXPFLAG_MEXP8_SHIFT (0x00000008u) #define CSL_INTC_MEXPFLAG_MEXP8_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP7_MASK (0x00000080u) #define CSL_INTC_MEXPFLAG_MEXP7_SHIFT (0x00000007u) #define CSL_INTC_MEXPFLAG_MEXP7_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP6_MASK (0x00000040u) #define CSL_INTC_MEXPFLAG_MEXP6_SHIFT (0x00000006u) #define CSL_INTC_MEXPFLAG_MEXP6_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP5_MASK (0x00000020u) #define CSL_INTC_MEXPFLAG_MEXP5_SHIFT (0x00000005u) #define CSL_INTC_MEXPFLAG_MEXP5_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP4_MASK (0x00000010u) #define CSL_INTC_MEXPFLAG_MEXP4_SHIFT (0x00000004u) #define CSL_INTC_MEXPFLAG_MEXP4_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP3_MASK (0x00000008u) #define CSL_INTC_MEXPFLAG_MEXP3_SHIFT (0x00000003u) #define CSL_INTC_MEXPFLAG_MEXP3_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP2_MASK (0x00000004u) #define CSL_INTC_MEXPFLAG_MEXP2_SHIFT (0x00000002u) #define CSL_INTC_MEXPFLAG_MEXP2_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP1_MASK (0x00000002u) #define CSL_INTC_MEXPFLAG_MEXP1_SHIFT (0x00000001u) #define CSL_INTC_MEXPFLAG_MEXP1_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP0_MASK (0x00000001u) #define CSL_INTC_MEXPFLAG_MEXP0_SHIFT (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP0_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_RESETVAL (0x00000000u) / INTMUX1 / #define CSL_INTC_INTMUX1_INTSEL7_MASK (0x7F000000u) #define CSL_INTC_INTMUX1_INTSEL7_SHIFT (0x00000018u) #define CSL_INTC_INTMUX1_INTSEL7_RESETVAL (0x00000007u) #define CSL_INTC_INTMUX1_INTSEL6_MASK (0x007F0000u) #define CSL_INTC_INTMUX1_INTSEL6_SHIFT (0x00000010u) #define CSL_INTC_INTMUX1_INTSEL6_RESETVAL (0x00000006u) #define CSL_INTC_INTMUX1_INTSEL5_MASK (0x00007F00u) #define CSL_INTC_INTMUX1_INTSEL5_SHIFT (0x00000008u) #define CSL_INTC_INTMUX1_INTSEL5_RESETVAL (0x00000005u) #define CSL_INTC_INTMUX1_INTSEL4_MASK (0x0000007Fu) #define CSL_INTC_INTMUX1_INTSEL4_SHIFT (0x00000000u) #define CSL_INTC_INTMUX1_INTSEL4_RESETVAL (0x00000004u) #define CSL_INTC_INTMUX1_RESETVAL (0x07060504u) / INTMUX2 / #define CSL_INTC_INTMUX2_INTSEL11_MASK (0x7F000000u) #define CSL_INTC_INTMUX2_INTSEL11_SHIFT (0x00000018u) #define CSL_INTC_INTMUX2_INTSEL11_RESETVAL (0x0000000Bu) #define CSL_INTC_INTMUX2_INTSEL10_MASK (0x007F0000u) #define CSL_INTC_INTMUX2_INTSEL10_SHIFT (0x00000010u) #define CSL_INTC_INTMUX2_INTSEL10_RESETVAL (0x0000000Au) #define CSL_INTC_INTMUX2_INTSEL9_MASK (0x00007F00u) #define CSL_INTC_INTMUX2_INTSEL9_SHIFT (0x00000008u) #define CSL_INTC_INTMUX2_INTSEL9_RESETVAL (0x00000009u) #define CSL_INTC_INTMUX2_INTSEL8_MASK (0x0000007Fu) #define CSL_INTC_INTMUX2_INTSEL8_SHIFT (0x00000000u) #define CSL_INTC_INTMUX2_INTSEL8_RESETVAL (0x00000008u) #define CSL_INTC_INTMUX2_RESETVAL (0x0B0A0908u) / INTMUX3 / #define CSL_INTC_INTMUX3_INTSEL15_MASK (0x7F000000u) #define CSL_INTC_INTMUX3_INTSEL15_SHIFT (0x00000018u) #define CSL_INTC_INTMUX3_INTSEL15_RESETVAL (0x0000000Fu) #define CSL_INTC_INTMUX3_INTSEL14_MASK (0x007F0000u) #define CSL_INTC_INTMUX3_INTSEL14_SHIFT (0x00000010u) #define CSL_INTC_INTMUX3_INTSEL14_RESETVAL (0x0000000Eu) #define CSL_INTC_INTMUX3_INTSEL13_MASK (0x00007F00u) #define CSL_INTC_INTMUX3_INTSEL13_SHIFT (0x00000008u) #define CSL_INTC_INTMUX3_INTSEL13_RESETVAL (0x0000000Du) #define CSL_INTC_INTMUX3_INTSEL12_MASK (0x0000007Fu) #define CSL_INTC_INTMUX3_INTSEL12_SHIFT (0x00000000u) #define CSL_INTC_INTMUX3_INTSEL12_RESETVAL (0x0000000Cu) #define CSL_INTC_INTMUX3_RESETVAL (0x0F0E0D0Cu) / INTXSTAT / #define CSL_INTC_INTXSTAT_SYSINT_MASK (0xFF000000u) #define CSL_INTC_INTXSTAT_SYSINT_SHIFT (0x00000018u) #define CSL_INTC_INTXSTAT_SYSINT_RESETVAL (0x00000000u) /----SYSINT Tokens----/ #define CSL_INTC_INTXSTAT_SYSINT_NUM0 (0x00000000u) #define CSL_INTC_INTXSTAT_SYSINT_NUM1 (0x00000001u) #define CSL_INTC_INTXSTAT_SYSINT_NUM2 (0x00000002u) #define CSL_INTC_INTXSTAT_SYSINT_NUM3 (0x00000003u) #define CSL_INTC_INTXSTAT_SYSINT_NUM4 (0x00000004u) #define CSL_INTC_INTXSTAT_SYSINT_NUM5 (0x00000005u) #define CSL_INTC_INTXSTAT_SYSINT_NUM6 (0x00000006u) #define CSL_INTC_INTXSTAT_SYSINT_NUM7 (0x00000007u) #define CSL_INTC_INTXSTAT_SYSINT_NUM8 (0x00000008u) #define CSL_INTC_INTXSTAT_SYSINT_NUM9 (0x00000009u) #define CSL_INTC_INTXSTAT_SYSINT_NUM10 (0x0000000Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM11 (0x0000000Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM12 (0x0000000Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM13 (0x0000000Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM14 (0x0000000Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM15 (0x0000000Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM16 (0x00000010u) #define CSL_INTC_INTXSTAT_SYSINT_NUM17 (0x00000011u) #define CSL_INTC_INTXSTAT_SYSINT_NUM18 (0x00000012u) #define CSL_INTC_INTXSTAT_SYSINT_NUM19 (0x00000013u) #define CSL_INTC_INTXSTAT_SYSINT_NUM20 (0x00000014u) #define CSL_INTC_INTXSTAT_SYSINT_NUM21 (0x00000015u) #define CSL_INTC_INTXSTAT_SYSINT_NUM22 (0x00000016u) #define CSL_INTC_INTXSTAT_SYSINT_NUM23 (0x00000017u) #define CSL_INTC_INTXSTAT_SYSINT_NUM24 (0x00000018u) #define CSL_INTC_INTXSTAT_SYSINT_NUM25 (0x00000019u) #define CSL_INTC_INTXSTAT_SYSINT_NUM26 (0x0000001Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM27 (0x0000001Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM28 (0x0000001Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM29 (0x0000001Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM30 (0x0000001Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM31 (0x0000001Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM32 (0x00000020u) #define CSL_INTC_INTXSTAT_SYSINT_NUM33 (0x00000021u) #define CSL_INTC_INTXSTAT_SYSINT_NUM34 (0x00000022u) #define CSL_INTC_INTXSTAT_SYSINT_NUM35 (0x00000023u) #define CSL_INTC_INTXSTAT_SYSINT_NUM36 (0x00000024u) #define CSL_INTC_INTXSTAT_SYSINT_NUM37 (0x00000025u) #define CSL_INTC_INTXSTAT_SYSINT_NUM38 (0x00000026u) #define CSL_INTC_INTXSTAT_SYSINT_NUM39 (0x00000027u) #define CSL_INTC_INTXSTAT_SYSINT_NUM40 (0x00000028u) #define CSL_INTC_INTXSTAT_SYSINT_NUM41 (0x00000029u) #define CSL_INTC_INTXSTAT_SYSINT_NUM42 (0x0000002Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM43 (0x0000002Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM44 (0x0000002Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM45 (0x0000002Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM46 (0x0000002Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM47 (0x0000002Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM48 (0x00000030u) #define CSL_INTC_INTXSTAT_SYSINT_NUM49 (0x00000031u) #define CSL_INTC_INTXSTAT_SYSINT_NUM50 (0x00000032u) #define CSL_INTC_INTXSTAT_SYSINT_NUM51 (0x00000033u) #define CSL_INTC_INTXSTAT_SYSINT_NUM52 (0x00000034u) #define CSL_INTC_INTXSTAT_SYSINT_NUM53 (0x00000035u) #define CSL_INTC_INTXSTAT_SYSINT_NUM54 (0x00000036u) #define CSL_INTC_INTXSTAT_SYSINT_NUM55 (0x00000037u) #define CSL_INTC_INTXSTAT_SYSINT_NUM56 (0x00000038u) #define CSL_INTC_INTXSTAT_SYSINT_NUM57 (0x00000039u) #define CSL_INTC_INTXSTAT_SYSINT_NUM58 (0x0000003Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM59 (0x0000003Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM60 (0x0000003Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM61 (0x0000003Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM62 (0x0000003Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM63 (0x0000003Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM64 (0x00000040u) #define CSL_INTC_INTXSTAT_SYSINT_NUM65 (0x00000041u) #define CSL_INTC_INTXSTAT_SYSINT_NUM66 (0x00000042u) #define CSL_INTC_INTXSTAT_SYSINT_NUM67 (0x00000043u) #define CSL_INTC_INTXSTAT_SYSINT_NUM68 (0x00000044u) #define CSL_INTC_INTXSTAT_SYSINT_NUM69 (0x00000045u) #define CSL_INTC_INTXSTAT_SYSINT_NUM70 (0x00000046u) #define CSL_INTC_INTXSTAT_SYSINT_NUM71 (0x00000047u) #define CSL_INTC_INTXSTAT_SYSINT_NUM72 (0x00000048u) #define CSL_INTC_INTXSTAT_SYSINT_NUM73 (0x00000049u) #define CSL_INTC_INTXSTAT_SYSINT_NUM74 (0x0000004Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM75 (0x0000004Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM76 (0x0000004Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM77 (0x0000004Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM78 (0x0000004Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM79 (0x0000004Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM80 (0x00000050u) #define CSL_INTC_INTXSTAT_SYSINT_NUM81 (0x00000051u) #define CSL_INTC_INTXSTAT_SYSINT_NUM82 (0x00000052u) #define CSL_INTC_INTXSTAT_SYSINT_NUM83 (0x00000053u) #define CSL_INTC_INTXSTAT_SYSINT_NUM84 (0x00000054u) #define CSL_INTC_INTXSTAT_SYSINT_NUM85 (0x00000055u) #define CSL_INTC_INTXSTAT_SYSINT_NUM86 (0x00000056u) #define CSL_INTC_INTXSTAT_SYSINT_NUM87 (0x00000057u) #define CSL_INTC_INTXSTAT_SYSINT_NUM88 (0x00000058u) #define CSL_INTC_INTXSTAT_SYSINT_NUM89 (0x00000059u) #define CSL_INTC_INTXSTAT_SYSINT_NUM90 (0x0000005Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM91 (0x0000005Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM92 (0x0000005Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM93 (0x0000005Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM94 (0x0000005Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM95 (0x0000005Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM96 (0x00000060u) #define CSL_INTC_INTXSTAT_SYSINT_NUM97 (0x00000061u) #define CSL_INTC_INTXSTAT_SYSINT_NUM98 (0x00000062u) #define CSL_INTC_INTXSTAT_SYSINT_NUM99 (0x00000063u) #define CSL_INTC_INTXSTAT_SYSINT_NUM100 (0x00000064u) #define CSL_INTC_INTXSTAT_SYSINT_NUM101 (0x00000065u) #define CSL_INTC_INTXSTAT_SYSINT_NUM102 (0x00000066u) #define CSL_INTC_INTXSTAT_SYSINT_NUM103 (0x00000067u) #define CSL_INTC_INTXSTAT_SYSINT_NUM104 (0x00000068u) #define CSL_INTC_INTXSTAT_SYSINT_NUM105 (0x00000069u) #define CSL_INTC_INTXSTAT_SYSINT_NUM106 (0x0000006Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM107 (0x0000006Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM108 (0x0000006Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM109 (0x0000006Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM110 (0x0000006Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM111 (0x0000006Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM112 (0x00000070u) #define CSL_INTC_INTXSTAT_SYSINT_NUM113 (0x00000071u) #define CSL_INTC_INTXSTAT_SYSINT_NUM114 (0x00000072u) #define CSL_INTC_INTXSTAT_SYSINT_NUM115 (0x00000073u) #define CSL_INTC_INTXSTAT_SYSINT_NUM116 (0x00000074u) #define CSL_INTC_INTXSTAT_SYSINT_NUM117 (0x00000075u) #define CSL_INTC_INTXSTAT_SYSINT_NUM118 (0x00000076u) #define CSL_INTC_INTXSTAT_SYSINT_NUM119 (0x00000077u) #define CSL_INTC_INTXSTAT_SYSINT_NUM120 (0x00000078u) #define CSL_INTC_INTXSTAT_SYSINT_NUM121 (0x00000079u) #define CSL_INTC_INTXSTAT_SYSINT_NUM122 (0x0000007Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM123 (0x0000007Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM124 (0x0000007Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM125 (0x0000007Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM126 (0x0000007Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM127 (0x0000007Fu) #define CSL_INTC_INTXSTAT_CPUINT_MASK (0x00FF0000u) #define CSL_INTC_INTXSTAT_CPUINT_SHIFT (0x00000010u) #define CSL_INTC_INTXSTAT_CPUINT_RESETVAL (0x00000000u) /----CPUINT Tokens----/ #define CSL_INTC_INTXSTAT_CPUINT_NUM0 (0x00000000u) #define CSL_INTC_INTXSTAT_CPUINT_NUM1 (0x00000001u) #define CSL_INTC_INTXSTAT_CPUINT_NUM2 (0x00000002u) #define CSL_INTC_INTXSTAT_CPUINT_NUM3 (0x00000003u) #define CSL_INTC_INTXSTAT_CPUINT_NUM4 (0x00000004u) #define CSL_INTC_INTXSTAT_CPUINT_NUM5 (0x00000005u) #define CSL_INTC_INTXSTAT_CPUINT_NUM6 (0x00000006u) #define CSL_INTC_INTXSTAT_CPUINT_NUM7 (0x00000007u) #define CSL_INTC_INTXSTAT_CPUINT_NUM8 (0x00000008u) #define CSL_INTC_INTXSTAT_CPUINT_NUM9 (0x00000009u) #define CSL_INTC_INTXSTAT_CPUINT_NUM10 (0x0000000Au) #define CSL_INTC_INTXSTAT_CPUINT_NUM11 (0x0000000Bu) #define CSL_INTC_INTXSTAT_CPUINT_NUM12 (0x0000000Cu) #define CSL_INTC_INTXSTAT_CPUINT_NUM13 (0x0000000Du) #define CSL_INTC_INTXSTAT_CPUINT_NUM14 (0x0000000Eu) #define CSL_INTC_INTXSTAT_CPUINT_NUM15 (0x0000000Fu) #define CSL_INTC_INTXSTAT_RESERVED_MASK (0x0000FFFEu) #define CSL_INTC_INTXSTAT_RESERVED_SHIFT (0x00000001u) #define CSL_INTC_INTXSTAT_RESERVED_RESETVAL (0x00000000u) #define CSL_INTC_INTXSTAT_DROP_MASK (0x00000001u) #define CSL_INTC_INTXSTAT_DROP_SHIFT (0x00000000u) #define CSL_INTC_INTXSTAT_DROP_RESETVAL (0x00000000u) /----DROP Tokens----/ #define CSL_INTC_INTXSTAT_DROP_NO (0x00000000u) #define CSL_INTC_INTXSTAT_DROP_YES (0x00000001u) #define CSL_INTC_INTXSTAT_RESETVAL (0x00000000u) / INTXCLR / #define CSL_INTC_INTXCLR_RESERVED_MASK (0xFFFFFFFEu) #define CSL_INTC_INTXCLR_RESERVED_SHIFT (0x00000001u) #define CSL_INTC_INTXCLR_RESERVED_RESETVAL (0x00000000u) #define CSL_INTC_INTXCLR_CLR_MASK (0x00000001u) #define CSL_INTC_INTXCLR_CLR_SHIFT (0x00000000u) #define CSL_INTC_INTXCLR_CLR_RESETVAL (0x00000000u) #define CSL_INTC_INTXCLR_RESETVAL (0x00000000u) / INTDMASK */ #define CSL_INTC_INTDMASK_IDM15_MASK (0x00008000u) #define CSL_INTC_INTDMASK_IDM15_SHIFT (0x0000000Fu) #define CSL_INTC_INTDMASK_IDM15_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM14_MASK (0x00004000u) #define CSL_INTC_INTDMASK_IDM14_SHIFT (0x0000000Eu) #define CSL_INTC_INTDMASK_IDM14_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM13_MASK (0x00002000u) #define CSL_INTC_INTDMASK_IDM13_SHIFT (0x0000000Du) #define CSL_INTC_INTDMASK_IDM13_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM12_MASK (0x00001000u) #define CSL_INTC_INTDMASK_IDM12_SHIFT (0x0000000Cu) #define CSL_INTC_INTDMASK_IDM12_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM11_MASK (0x00000800u) #define CSL_INTC_INTDMASK_IDM11_SHIFT (0x0000000Bu) #define CSL_INTC_INTDMASK_IDM11_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM10_MASK (0x00000400u) #define CSL_INTC_INTDMASK_IDM10_SHIFT (0x0000000Au) #define CSL_INTC_INTDMASK_IDM10_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM9_MASK (0x00000200u) #define CSL_INTC_INTDMASK_IDM9_SHIFT (0x00000009u) #define CSL_INTC_INTDMASK_IDM9_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM8_MASK (0x00000100u) #define CSL_INTC_INTDMASK_IDM8_SHIFT (0x00000008u) #define CSL_INTC_INTDMASK_IDM8_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM7_MASK (0x00000080u) #define CSL_INTC_INTDMASK_IDM7_SHIFT (0x00000007u) #define CSL_INTC_INTDMASK_IDM7_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM6_MASK (0x00000040u) #define CSL_INTC_INTDMASK_IDM6_SHIFT (0x00000006u) #define CSL_INTC_INTDMASK_IDM6_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM5_MASK (0x00000020u) #define CSL_INTC_INTDMASK_IDM5_SHIFT (0x00000005u) #define CSL_INTC_INTDMASK_IDM5_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM4_MASK (0x00000010u) #define CSL_INTC_INTDMASK_IDM4_SHIFT (0x00000004u) #define CSL_INTC_INTDMASK_IDM4_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_RESETVAL (0x00000000u) #endif
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/FB_W2100_SCU_MEA256/Device_lib.c	// use sprc234 (Version: 03.00.10.02) for the CSL include files #include <stdio.h> #include <string.h> #include <cslr_pllc.h> #include <cslr_gpio.h> #include <cslr_emifa.h> #include <cslr_ddr2.h> #include <cslr_dev.h> #include <cslr_intc.h> #include <cslr_chip.h> #include <cslr_edma3cc.h> #include <cslr_cache.h> #include <cslr_tmr.h> #include <soc.h> #include <c6x.h> #include "Device_config.h" #include "Device_lib.h" typedef volatile CSL_DevRegs CSL_DevRegsOvly; extern void intcVectorTable(void); void init_cache(); void init_gpio(); void init_pll1(); void init_pll2(); void init_emifa(); void init_ddr2(); void init_irq(); void init_timer(); void init_dma(int indata_channels); void init_qdma(int indata_channels); Uint32 MeaData[MAX_DATAPOINTS_PER_FRAME]; #pragma DATA_ALIGN(MeaData, 8); Uint32 MonitorData[MONITOR_ARRAY]; Uint32 ChannelsPerSweepConfigured; / Globals / CSL_DevRegsOvly devRegs = (CSL_DevRegsOvly)CSL_DEV_REGS; void MEA21_init() { init_gpio(); init_pll1(); init_ddr2(); init_emifa(); init_cache(); WRITE_REGISTER(DSP_INDATA_CTRL0, DSPINDATACTRL0_CLEAR_FIFO \| DSPINDATACTRL0_RESET_FIFO); // Disable all Data Channels and Clear Fifo WRITE_REGISTER(MAILBOX_CTRL, 0x100); // enable DSP Mailbox interrupts init_irq(); } void MEA21_enableData() { int i; WRITE_REGISTER(DSP_INDATA_CONFIG0, INDATA_CONFIG0_VALUE); // Enable Data Sources WRITE_REGISTER(DSP_INDATA_CONFIG1, INDATA_CONFIG1_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG2, INDATA_CONFIG2_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG3, INDATA_CONFIG3_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG4, INDATA_CONFIG4_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG5, INDATA_CONFIG5_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG6, INDATA_CONFIG6_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG7, INDATA_CONFIG7_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG8, INDATA_CONFIG8_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG9, INDATA_CONFIG9_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGa, INDATA_CONFIGa_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGb, INDATA_CONFIGb_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGc, INDATA_CONFIGc_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGd, INDATA_CONFIGd_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGe, INDATA_CONFIGe_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGf, INDATA_CONFIGf_VALUE); for (i = 0; i < 5000; i++) { ChannelsPerSweepConfigured = READ_REGISTER(DSP_INDATA_CHANNELS); // should be the same number as CHANNELS_PER_FRAME if (ChannelsPerSweepConfigured) break; // a non-zero value indicated the FPGA has finished configuration } if (ChannelsPerSweepConfigured > MAX_DATAPOINTS_PER_FRAME) { // You should increase MAX_DATAPOINTS_PER_FRAME if this condition is true ChannelsPerSweepConfigured = MAX_DATAPOINTS_PER_FRAME; } init_timer(); init_dma(ChannelsPerSweepConfigured); init_qdma(ChannelsPerSweepConfigured); WRITE_REGISTER(DSP_INDATA_CTRL0, DSPINDATACTRL0_INT_ENABLE \| DSPINDATACTRL0_CLEAR_FIFO \| DSPINDATACTRL0_RESET_FIFO); // Enable Irq SetMonitorSize(MONITOR_ARRAY); } void init_timer() { Bool timerRdy; // enable timer 0 // Unlock the control register CSL_FINST(((CSL_DevRegs )CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); CSL_FINST(((CSL_DevRegs )CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER0CTL, ENABLE); do { timerRdy = (Bool) CSL_FEXT(((CSL_DevRegs )CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TIMER0STAT); } while (!timerRdy); // enable timer 1 // Unlock the control register CSL_FINST(((CSL_DevRegs )CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); CSL_FINST(((CSL_DevRegs )CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER1CTL, ENABLE); do { timerRdy = (Bool) CSL_FEXT(((CSL_DevRegs )CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TIMER1STAT); } while (!timerRdy); CSL_TmrRegsOvly tmr1Regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; // clear TIM12 register CSL_FINST(tmr1Regs->TIMLO,TMR_TIMLO_TIMLO,RESETVAL); CSL_FINS(tmr1Regs->TCR, TMR_TCR_CLKSRC_LO, 0); // select 32 bit unchained mode and take the timer out of reset CSL_FINS(tmr1Regs->TGCR, TMR_TGCR_TIMMODE, 1); // 32bit unchained CSL_FINST(tmr1Regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); } void init_gpio() { CSL_GpioRegsOvly gpioRegs = (CSL_GpioRegsOvly)CSL_GPIO_0_REGS; Bool gpioEn; / Unlock the control register / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the GPIO / CSL_FINST(((CSL_DevRegs)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_GPIOCTL, ENABLE); do { gpioEn = (Bool) CSL_FEXT(((CSL_DevRegs)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_GPIOSTAT); } while (gpioEn != CSL_DEV_PERSTAT0_GPIOSTAT_ENABLE); CSL_FINS(gpioRegs->DIR, GPIO_DIR_DIR2 , CSL_GPIO_DIR_DIR_OUT); // LED CSL_FINS(gpioRegs->DIR, GPIO_DIR_DIR15, CSL_GPIO_DIR_DIR_OUT); // LED CSL_FINS(gpioRegs->OUT_DATA, GPIO_OUT_DATA_OUT2, 1); // LED CSL_FINS(gpioRegs->OUT_DATA, GPIO_OUT_DATA_OUT15, 0); // LED CSL_FINS(gpioRegs->DIR, GPIO_DIR_DIR4 , CSL_GPIO_DIR_DIR_IN); // FPGA Data available CSL_FINS(gpioRegs->DIR, GPIO_DIR_DIR6 , CSL_GPIO_DIR_DIR_IN); // Mailbox IRQ / Enable Interrupts for GP[4] / CSL_FINS(gpioRegs->SET_RIS_TRIG, GPIO_SET_RIS_TRIG_SETRIS4, CSL_GPIO_SET_RIS_TRIG_SETRIS_ENABLE); / Enable Interrupts for GP[6] / CSL_FINS(gpioRegs->SET_RIS_TRIG, GPIO_SET_RIS_TRIG_SETRIS6, CSL_GPIO_SET_RIS_TRIG_SETRIS_ENABLE); CSL_FINST(gpioRegs->BINTEN, GPIO_BINTEN_EN, ENABLE); } void init_cache() { ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCFG = CSL_CACHE_L1PCFG_MODE_32K; ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCFG = CSL_CACHE_L1DCFG_MODE_32K; } void init_pll1() { // input Clock is 51.2 MHz // max device clock is 850 MHz volatile int i; CSL_PllcRegsOvly pllRegs = (CSL_PllcRegsOvly)CSL_PLLC_1_REGS; CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLENSRC, REGBIT); CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLEN, BYPASS); // wait 4 cycles for (i = 0; i < 4; i++); CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLRST, YES); CSL_FINS(pllRegs->PREDIV, PLLC_PREDIV_RATIO, 0); // Prediv by 1 CSL_FINS(pllRegs->PLLM, PLLC_PLLM_PLLM, 15); // Multiply by 16 -> 51.2 16 = 819.2 MHz CSL_FINS(pllRegs->PLLDIV4, PLLC_PLLDIV4_RATIO, 7); // 7: divide by 16 -> 51.2 MHz (Max: 166 MHz) CSL_FINS(pllRegs->PLLDIV5, PLLC_PLLDIV5_RATIO, 2); // 2: divide by 3 -> 273.06 MHz (Max: 333 MHz) // CSL_FINST(pllRegs->ALNCTL, PLLC_ALNCTL_ALN4, YES); // Align SYSCLK4, default, do not change // CSL_FINST(pllRegs->ALNCTL, PLLC_ALNCTL_ALN5, YES); // Align SYSCLK5, default, do not change CSL_FINST(pllRegs->PLLCMD, PLLC_PLLCMD_GOSET, SET); // while (CSL_FEXT(pllRegs->PLLSTAT, PLLC_PLLSTAT_GOSTAT) == CSL_PLLC_PLLSTAT_GOSTAT_INPROG); // wait for PLL reset (128 * CLKIN1 cycle time) -> 2.5 us for (i = 0; i < 2000; i++); CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLRST, NO); // wait for PLL lock time (2000 * CLKIN1 cycle time) -> 96.9 us for (i = 0; i < 20000; i++); CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLEN, PLL); } void init_pll2() { // input Clock is 25.6 MHz // PLLOUT is 250 .. 533 MHz // DDR2 clock is fixed to PLLOUT/2 // PLLM is fixed to x20 -> 25.6 MHz -> 512 MHz PLLOUT -> 256 MHz DDR2 Clock // SYSLK1 is 50 or 125 MHz when EMAC is used } // we want ARDY pin is active-low (strobe period extended when ARDY is low) // Requirement for the Xilinx async Interface: // T_SETUP: >= 3x 38.4 MHz cycles (> 78.125 ns) (2 cycles should be ok?) // T_STROBE: > 2x 38.4 MHz cycles (> 52.083 ns) (+ ARDY; ARDY must be asserted and deasserted for 2 cycles) // T_HOLD: >= 1x 38.4 MHz cycle (> 26.042 ns) // Clock for EMIFA is AECLKIN, which is 38.4 MHz void init_emifa() { CSL_EmifaRegsOvly emifaRegs = (CSL_EmifaRegsOvly)CSL_EMIFA_0_REGS; CSL_FINST(devRegs->PERCFG1, DEV_PERCFG1_EMIFACTL, ENABLE); CSL_FINS(emifaRegs->BPRIO, EMIFA_BPRIO_PRIO_RAISE, 0xfe); // see SPRZ234N Silicon Errata CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_SSEL, ASYNCMEM); // CE2 (0xa0000000) uses ASYNC interface CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_SS, SSMDIS); // Disable Select Strobe Mode CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_BWEM, WESDIS); // Disable WE Strobe Mode CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_AE, ARDYEN); // enable ARDY Pin CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_SETUP, 2); // 3 cycles @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_STROBE, 1); // 2 cycles @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_HOLD, 0); // 1 cycle @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_SETUP, 2); // 3 cycles @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_STROBE, 1); // 2 cycles @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_HOLD, 0); // 1 cycle @38.4 MHz CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_ASIZE, 32BIT); // enable ARDY Pin CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_SSEL, SYNCMEM); // CE3 (0xb0000000) uses SYNC interface CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_RD_BE_EN, SET); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_CE_EXT, CLR); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_R_ENABLE, SET); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_W_LTNCY, ONECYCLE); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_R_LTNCY, THREECYCLE); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_SBSIZE, 32BIT); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_SSEL, SYNCMEM); // CE4 (0xc0000000) uses SYNC interface to stream Stimulus data CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_RD_BE_EN, SET); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_CE_EXT, CLR); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_R_ENABLE, SET); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_W_LTNCY, ONECYCLE); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_R_LTNCY, THREECYCLE); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_SBSIZE, 32BIT); CSL_FINS(emifaRegs->AWCC, EMIFA_AWCC_AP, 0); // define polarity of ARDY pin: active low CSL_FINS(emifaRegs->AWCC, EMIFA_AWCC_TA, 7); // Turn Around cycles CSL_FINS(emifaRegs->AWCC, EMIFA_AWCC_MAX_EXT_WAIT, 0xff); // Maximum Extended Wait cycles; 106.25 us @ AECLK of 38.4 MHz } void init_ddr2() { CSL_Ddr2RegsOvly ddr2Regs = (CSL_Ddr2RegsOvly)CSL_DDR2_0_REGS; CSL_FINST(devRegs->PERCFG1, DEV_PERCFG1_DDR2CTL, ENABLE); CSL_FINS(ddr2Regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, 3200); // 256 MHz * 200 us / 16 = 3200 CSL_FINST(ddr2Regs->DMCCTL, DDR2_DMCCTL_IFRESET, RELEASE); CSL_FINS(ddr2Regs->BPRIO, DDR2_BPRIO_PRIO_RAISE, 0xfe); // see SPRZ234N Silicon Errata CSL_FINS(ddr2Regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, 3200); // 256 MHz * 200 us / 16 = 3200 CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_BOOT_UNLOCK, UNLOCKED); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_DDR_DRIVE, NORMAL); // default is NORMAL CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_BOOT_UNLOCK, LOCKED); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_TIMUNLOCK, SET); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_NM, 16BIT); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_CL, FIVE); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_IBANK, EIGHT); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_PAGESIZE, 1024W_PAGE); CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RFC, 49); // 195 ns * 256 MHz = 49.92 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RP, 3); // 12.5 ns * 256 MHz = 3.2 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RCD, 3); // 12.5 ns * 256 MHz = 3.2 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_WR, 3); // 15.0 ns * 256 MHz = 3.84 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RAS, 11); // 45.0 ns * 256 MHz = 11.52 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RC, 14); // 57.5 ns * 256 MHz = 14.72 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RRD, 3); // 11.5 ns * 256 MHz = 3.06 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_WTR, 3); // 7.5 ns * 256 MHz = 1.92 CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_ODT, 2); // 2 cycles CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_SXNR, 52); // 205 ns * 256 MHz = 52.48 CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_SXRD,199); // 200 cycles CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_RTP, 1); // 7.5 ns * 256 MHz = 1.92 CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_CKE, 2); // 3 cycles CSL_FINS(ddr2Regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, 1997); // 256 MHz * 7.8 us = 1996.8 CSL_FINS(ddr2Regs->DMCCTL, DDR2_DMCCTL_RL, 6); // CAS Latency + 1 CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_TIMUNLOCK, CLEAR); } void init_irq() { CSL_IntcRegsOvly intcRegs = (CSL_IntcRegsOvly)CSL_INTC_0_REGS; // map GP[6] event (Mailbox write) to cpu int 8 CSL_FINS(intcRegs->INTMUX2, INTC_INTMUX2_INTSEL8, CSL_INTC_EVENTID_GPINT6); // set ISTP to point to the vector table address ISTP = (unsigned int)intcVectorTable; // clear all interrupts, bits 4 thru 15 ICR = 0xFFF0; // enable the bits for non maskable interrupt and CPUINT6 and CPUINT8 / IER \|= 0x02; IER \|= 0x40; // enable CPUINT6 (DMA completion) IER \|= 0x100; // enable CPUINT8 (Mailbox write) // enable interrupts, set GIE bit _enable_interrupts(); } void init_dma(int indata_channels) { CSL_IntcRegsOvly intcRegs = (CSL_IntcRegsOvly)CSL_INTC_0_REGS; CSL_Edma3ccRegsOvly edma3ccRegs = (CSL_Edma3ccRegsOvly)CSL_EDMA3CC_0_REGS; volatile CSL_Edma3ccParamsetRegs ParmsetGPINT4RLD = &edma3ccRegs->PARAMSET[CSL_EDMA3_CHA_GPINT3]; // inbound data reload set volatile CSL_Edma3ccParamsetRegs ParmsetGPINT4 = &edma3ccRegs->PARAMSET[CSL_EDMA3_CHA_GPINT4]; // inbound data volatile CSL_Edma3ccParamsetRegs ParmsetGPINT5 = &edma3ccRegs->PARAMSET[CSL_EDMA3_CHA_GPINT5]; // outbound data CSL_FINS(edma3ccRegs->DCHMAP[52], EDMA3CC_DCHMAP_PAENTRY, 52); // Map event 52 to parameter set 52 CSL_FINS(edma3ccRegs->DMAQNUM[6], EDMA3CC_DMAQNUM_E4, 0); // Use Q0 for event 52 CSL_FINS(edma3ccRegs->DCHMAP[53], EDMA3CC_DCHMAP_PAENTRY, 53); // Map event 53 to parameter set 53 CSL_FINS(edma3ccRegs->DMAQNUM[6], EDMA3CC_DMAQNUM_E5, 0); // Use Q0 for event 53 memset((void )ParmsetGPINT4RLD, 0, sizeof(CSL_Edma3ccParamsetRegs)); memset((void )ParmsetGPINT5, 0, sizeof(CSL_Edma3ccParamsetRegs)); CSL_FINST(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_TCINTEN, ENABLE); CSL_FINST(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_STATIC, NORMAL); CSL_FINS(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_TCC, 52); // Use a TCC of 52 for event 52 CSL_FINS(ParmsetGPINT4RLD->SRC, EDMA3CC_SRC_SRC, 0xb0000000); CSL_FINS(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_FWID, 2); CSL_FINST(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_SAM, CONST); CSL_FINS(ParmsetGPINT4RLD->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 4indata_channels); CSL_FINS(ParmsetGPINT4RLD->A_B_CNT, EDMA3CC_A_B_CNT_BCNT, FRAMES_PER_LOOP); CSL_FINS(ParmsetGPINT4RLD->SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 4indata_channels); CSL_FINS(ParmsetGPINT4RLD->DST, EDMA3CC_DST_DST, (Uint32)&MeaData); CSL_FINS(ParmsetGPINT4RLD->LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_LINK, CSL_EDMA3_CHA_GPINT3 << 5); // CSL_FINS(ParmsetGPINT4RLD->LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_BCNTRLD, FRAMES_PER_LOOP); CSL_FINS(ParmsetGPINT4RLD->CCNT, EDMA3CC_CCNT_CCNT, 1); memcpy((void )ParmsetGPINT4, (void )ParmsetGPINT4RLD, sizeof(CSL_Edma3ccParamsetRegs)); CSL_FINST(ParmsetGPINT5->OPT, EDMA3CC_OPT_TCINTEN, ENABLE); CSL_FINST(ParmsetGPINT5->OPT, EDMA3CC_OPT_STATIC, STATIC); CSL_FINS(ParmsetGPINT5->OPT, EDMA3CC_OPT_TCC, 53); // Use a TCC of 53 for event 53 CSL_FINS(ParmsetGPINT5->SRC, EDMA3CC_SRC_SRC, (Uint32)&MonitorData); CSL_FINS(ParmsetGPINT5->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 0); CSL_FINS(ParmsetGPINT5->A_B_CNT, EDMA3CC_A_B_CNT_BCNT, 1); CSL_FINS(ParmsetGPINT5->DST, EDMA3CC_DST_DST, 0xb0000000); CSL_FINS(ParmsetGPINT5->LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_LINK, 0xffff); CSL_FINS(ParmsetGPINT5->CCNT, EDMA3CC_CCNT_CCNT, 1); CSL_FINST(edma3ccRegs->EMCRH, EDMA3CC_EMCRH_E52, CLEAR); // clear missed events) CSL_FINST(edma3ccRegs->EMCRH, EDMA3CC_EMCRH_E53, CLEAR); // clear missed events) CSL_FINST(edma3ccRegs->SECRH, EDMA3CC_SECRH_E52, CLEAR); // clear secondary events) CSL_FINST(edma3ccRegs->SECRH, EDMA3CC_SECRH_E53, CLEAR); // clear secondary events) // CSL_FINST(edma3ccRegs->ESRH, EDMA3CC_ESRH_E52, SET); // Manual Trigger CSL_FINST(edma3ccRegs->EESRH, EDMA3CC_EESRH_E52, SET); // enable event CSL_FINST(edma3ccRegs->ICRH, EDMA3CC_ICRH_I52, CLEAR); // clear pending interrupts CSL_FINST(edma3ccRegs->IESRH, EDMA3CC_IESRH_I52, SET); // Enable interrupt for event 52 // map DMA global completion interrupt to cpu int6 CSL_FINS(intcRegs->INTMUX1, INTC_INTMUX1_INTSEL6, CSL_INTC_EVENTID_EDMA3CC_GINT); } void init_qdma(int indata_channels) { CSL_Edma3ccRegsOvly edma3ccRegs = (CSL_Edma3ccRegsOvly)CSL_EDMA3CC_0_REGS; volatile CSL_Edma3ccParamsetRegs ParmsetQDMA = &edma3ccRegs->PARAMSET[10]; // QDMA CSL_FINS(edma3ccRegs->QCHMAP[0], EDMA3CC_QCHMAP_PAENTRY, 10); // Map QDMA 0 to parameter set 10 CSL_FINS(edma3ccRegs->QCHMAP[0], EDMA3CC_QCHMAP_TRWORD, 3); // Define Trigger Word for QDMA 10, 3: DST CSL_FINS(edma3ccRegs->QDMAQNUM, EDMA3CC_QDMAQNUM_E0, 0); // Use Q0 for QDMA 0 CSL_FINST(edma3ccRegs->QEECR, EDMA3CC_QEECR_E0, CLEAR); // disable QDMA 0 event memset((void )ParmsetQDMA, 0, sizeof(CSL_Edma3ccParamsetRegs)); CSL_FINST(ParmsetQDMA->OPT, EDMA3CC_OPT_TCINTEN, ENABLE); CSL_FINST(ParmsetQDMA->OPT, EDMA3CC_OPT_STATIC, STATIC); CSL_FINST(ParmsetQDMA->OPT, EDMA3CC_OPT_SYNCDIM, ABSYNC); CSL_FINS(ParmsetQDMA->OPT, EDMA3CC_OPT_TCC, 10); // Use a TCC of 10 for QDMA 10 CSL_FINS(ParmsetQDMA->SRC, EDMA3CC_SRC_SRC, (Uint32)&MeaData); CSL_FINS(ParmsetQDMA->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 4indata_channels); CSL_FINS(ParmsetQDMA->A_B_CNT, EDMA3CC_A_B_CNT_BCNT, FRAMES_PER_LOOP/DOWNSAMPLE); CSL_FINS(ParmsetQDMA->SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 4indata_channelsDOWNSAMPLE); // use only every DOWNSAMPLE. Frame from Source CSL_FINS(ParmsetQDMA->SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 4indata_channels); // Destination is continous CSL_FINS(ParmsetQDMA->LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_LINK, 0xffff); CSL_FINS(ParmsetQDMA->CCNT, EDMA3CC_CCNT_CCNT, 1); CSL_FINST(edma3ccRegs->QEMCR, EDMA3CC_QEMCR_E0, CLEAR); // clear missed events CSL_FINST(edma3ccRegs->QSECR, EDMA3CC_QSECR_E0, CLEAR); // clear secondary events CSL_FINST(edma3ccRegs->ICR, EDMA3CC_ICR_I10, CLEAR); // clear pending interrupts CSL_FINST(edma3ccRegs->QEESR, EDMA3CC_QEESR_E0, SET); // enable QDMA event // CSL_FINS(ParmsetQDMA->DST, EDMA3CC_DST_DST, (Uint32)MatlabPointer); // write trigger word, start transfer // while (CSL_FEXT(edma3ccRegs->IPR, EDMA3CC_IPR_I10) == 0); // wait for completion // CSL_FINST(edma3ccRegs->ICR, EDMA3CC_ICR_I10, CLEAR); // clear pending interrupts } void timer_setperiod(int period) { CSL_TmrRegsOvly tmr1Regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; CSL_FINST(tmr1Regs->TCR, TMR_TCR_ENAMODE_LO, DISABLE); CSL_FINS(tmr1Regs->PRDLO,TMR_PRDLO_PRDLO, period); CSL_FINST(tmr1Regs->TIMLO,TMR_TIMLO_TIMLO,RESETVAL); CSL_FINS(tmr1Regs->TCR, TMR_TCR_ENAMODE_LO, 2); // continous mode } void SetMonitorSize(int datapoints) { CSL_Edma3ccRegsOvly edma3ccRegs = (CSL_Edma3ccRegsOvly)CSL_EDMA3CC_0_REGS; volatile CSL_Edma3ccParamsetRegs ParmsetGPINT5 = &edma3ccRegs->PARAMSET[CSL_EDMA3_CHA_GPINT5]; // outbound data CSL_FINS(ParmsetGPINT5->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 0); WRITE_REGISTER(DSP_OUTDATA_THR, datapoints); WRITE_REGISTER(DSP_OUTDATA_CTRL, 3); // Disable all Data Channels and Clear Fifo CSL_FINS(ParmsetGPINT5->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 4datapoints); }
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/dat/_csl_dat.c	/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== / / ============================================================================ * @file _csl_dat.c * * @path $(CSLPATH)\src\dst * * @desc This file defines section information * / / ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created. * * ============================================================================= */ #include <csl_dat.h> #include <_csl_dat.h> #pragma DATA_SECTION (_CSL_datStateStruct, ".bss:csl_section:dat"); CSL_DatStateStruct _CSL_datStateStruct;
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback	DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtGetHwStatus.c	<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtGetHwStatus.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * priovided * ============================================================================ / /* =========================================================================== * @file csl_bwmngmtGetHwStatus.c * * @brief File for functional layer of CSL API @a CSL_bwmngmtGetHwStatus() * * @path $(CSLPATH)\bwmngmt\src * * Description * - The @a CSL_bwmngmtGetHwStatus() function definition & it's associated * functions * * @date 17 Mar, 2006 * @author PSK * ============================================================================= / / ============================================================================= * Revision History * =============== * 17-Mar-2006 PSK file created * ============================================================================= / #include <csl_bwmngmt.h> /* ============================================================================ * @n@b CSL_bwmngmtGetHwStatus * * @b Description * @n Gets the status of the different operations of BWMNGMT. Not Implemented. * For future use. * @b Arguments * @verbatim hBwmngmt Handle to the BWMNGMT instance myQuery The query to this API of BWMNGMT which indicates the status to be returned response Placeholder to return the status @endverbatim * * <b> Return Value </b> CSL_Status * CSL_SOK - Always returns * * * <b> Pre Condition </b> * Both CSL_bwmngmtInit() and CSL_bwmngmtOpen() must * be called successfully in that order before this function can be called * * <b> Post Condition </b> * None * @b Modifies * None * @b Examples: * @verbatim CSL_BwmngmtHandle hBwmngmt; CSL_BwmngmtHwStatusQuery query; void response; // Init Successfully done ... // Open Successfully done ... ... status = CSL_bwmngmtGetHwStatus(hBwmngmt, query, &response); ... @endverbatim * * =========================================================================== / #pragma CODE_SECTION (CSL_bwmngmtGetHwStatus, ".text:csl_section:bwmngmt"); CSL_Status CSL_bwmngmtGetHwStatus ( / pointer to the object that holds reference to the * instance of BWMNGMT requested after the call / CSL_BwmngmtHandle hBwmngmt, / pointer to setup structure which contains the * information to program BWMNGMT to a useful state / CSL_BwmngmtHwStatusQuery myQuery, void response ) { return CSL_SOK; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/tcp2/tcp2_shared_mode/src/tcp2_syst_parities.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004 , 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file tcp2_syst_parities.c * * @path $(CSLPATH)\example\c6455\tcp2\tcp2_shared_mode\src * * @desc Systematics and parity data for the TCP2 shared mode * */ #include <tistdtypes.h> Uint32 sysParData [] = { 0x00000d7f,0x0000058b, 0x00000ff6,0x000000cd, 0x00000241,0x00000285, 0x00000336,0x000005c6, 0x00000d91,0x00000d87, 0x00000136,0x00000f01, 0x000004d4,0x00000c8a, 0x0000030f,0x0000017d, 0x00000ed1,0x000003cb, 0x00000f3f,0x00000133, 0x000001f6,0x00000586, 0x00000001,0x00000278, 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adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/srio/csl_srioHwSetup.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** =========================================================================== * @file csl_srioHwSetup.c * * @brief File for functional layer of CSL API CSL_srioHwSetup() * * @path $(CSLPATH)\src\srio * * @desc The CSL_srioHwSetup() function definition and it's associated * functions * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 25-Aug-2005 PSK File Created. * 15-Dec-2005 SD Updated the SERDES configuration. * 09-Aug-2006 NG Moved the GBL_EN & BLK_ENABLE before setting PER_SET_CNTL. * ============================================================================ */ #include <csl_srio.h> #include <csl_srioAux.h> /** ============================================================================ * @n@b CSL_srioHwSetup * * @b Description * @n It configures the SRIO instance registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim hSrio Handle to the SRIO instance setup Pointer to hardware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * Pre Condition * @n None * * Post Condition * @n The specified instance will be setup according to value passed * * @b Modifies * @n Hardware registers for the specified instance * * @b Example * @verbatim CSL_SrioHandle hSrio; CSL_SrioObj srioObj; CSL_SrioHwSetup hwSetup; CSL_Status status; CSL_SrioControlSetup periSetup; CSL_SrioBlkEn blockSetup; CSL_SrioPktFwdCntl pktFwdSetup; hwSetup.perEn = TRUE; periSetup.swMemSleepOverride = FALSE; periSetup.loopback = FALSE; . . . periSetup.prescalar = CSL_SRIO_CLK_PRESCALE_0; hwSetup.periCntlSetup = &periSetup; hwSetup.blkEn = &blockSetup; hwSetup.pktFwdCntl = &pktfwdSetup; ... hSrio = CSL_srioOpen (&srioObj, CSL_SRIO, NULL, &status); ... status = CSL_srioHwSetup(hSrio, &hwSetup); ... @endverbatim * =========================================================================== */ #pragma CODE_SECTION(CSL_srioHwSetup, ".text:csl_section:srio"); CSL_Status CSL_srioHwSetup ( CSL_SrioHandle hSrio, CSL_SrioHwSetup *hwSetup ) { Uint32 i; CSL_Status status = CSL_SOK; if (hSrio == NULL) { status = CSL_ESYS_BADHANDLE; } else if (hwSetup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* global enable setup */ CSL_FINS(hSrio->regs->GBL_EN, SRIO_GBL_EN_EN, hwSetup->gblEn); /* block enable setup */ for (i = 0; i < CSL_SRIO_BLOCKS_MAX; i++) { CSL_FINS(hSrio->regs->BLK_ENABLE[i].BLK_EN, SRIO_BLK_EN_EN, hwSetup->blkEn[i]); } /* sets up the PER_SET_CNTL register */ hSrio->regs->PER_SET_CNTL = CSL_FMK(SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE, \ hwSetup->periCntlSetup.swMemSleepOverride) | CSL_FMK( SRIO_PER_SET_CNTL_LOOPBACK, \ hwSetup->periCntlSetup.loopback) | CSL_FMK(SRIO_PER_SET_CNTL_BOOT_COMPLETE, \ hwSetup->periCntlSetup.bootComplete) | CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI2_WM, \ hwSetup->periCntlSetup.txPriority2Wm) | CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI1_WM, \ hwSetup->periCntlSetup.txPriority1Wm) | CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI0_WM, \ hwSetup->periCntlSetup.txPriority0Wm) | CSL_FMK(SRIO_PER_SET_CNTL_CBA_TRANS_PRI, \ hwSetup->periCntlSetup.busTransPriority) | CSL_FMK(SRIO_PER_SET_CNTL_1X_MODE, \ hwSetup->periCntlSetup.bufferMode) | CSL_FMK(SRIO_PER_SET_CNTL_PRESCALER_SELECT, \ hwSetup->periCntlSetup.prescalar) | CSL_FMKR(3, 0, hwSetup->periCntlSetup.pllEn); /* the device ids setup */ hSrio->regs->DEVICEID_REG1 = hwSetup->deviceId1; hSrio->regs->DEVICEID_REG2 = hwSetup->deviceId2; /* hardware packet forwading registers setup */ for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL, SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND, hwSetup->pktFwdCntl[i].largeUpBoundDevId); CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL, SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND, hwSetup->pktFwdCntl[i].largeLowBoundDevId); CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT, hwSetup->pktFwdCntl[i].outBoundPort); CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND, hwSetup->pktFwdCntl[i].smallUpBoundDevId); CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND, hwSetup->pktFwdCntl[i].smallLowBoundDevId); } /* SERDES PLL configuration setup */ for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { if (hwSetup->serDesPllCfg[i].pllEnable) { /* Configure the loop bandwidth */ CSL_FINS (hSrio->regs->SERDES_CFG_CNTL[i], SRIO_SERDES_CFG_CNTL_LB, hwSetup->serDesPllCfg[i].loopBandwidth); /* Configure the multiplication factor */ CSL_FINS (hSrio->regs->SERDES_CFG_CNTL[i], SRIO_SERDES_CFG_CNTL_MPY, hwSetup->serDesPllCfg[i].pllMplyFactor); /* Enable the internal PLL*/ CSL_FINST (hSrio->regs->SERDES_CFG_CNTL[i], SRIO_SERDES_CFG_CNTL_ENPLL, ENABLE); } } /* SERDES RX channel enable setup */ for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { if (hwSetup->serDesRxChannelCfg [i].enRx) { /* Configure the bus width */ CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_BUSWIDTH, hwSetup->serDesRxChannelCfg [i].busWidth); /* Configure the operating rate */ CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_RATE, hwSetup->serDesRxChannelCfg [i].rate); /* Configure the polarity */ CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_INVPAIR, hwSetup->serDesRxChannelCfg [i].invertedPolarity); /* Configure the termination */ CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_TERM, hwSetup->serDesRxChannelCfg [i].termination); /* Configure the symbol alignment */ CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_ALIGN, hwSetup->serDesRxChannelCfg [i].symAlign); /* Configure the loss of signal detection */ CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_LOS, hwSetup->serDesRxChannelCfg [i].los); /* Configure the clock and data recovery algorithm */ CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_CDR, hwSetup->serDesRxChannelCfg [i].clockDataRecovery); /* Configure the adaptive equalizer */ CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_EQ, hwSetup->serDesRxChannelCfg [i].equalizer); /* Enable the receiver */ CSL_FINST(hSrio->regs->SERDES_CFGRX_CNTL[i], SRIO_SERDES_CFGRX_CNTL_ENRX, ENABLE); } } /* SERDES TX channel enable setup */ for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { if (hwSetup->serDesTxChannelCfg [i].enTx) { /* Configure the bus width */ CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_BUSWIDTH, hwSetup->serDesTxChannelCfg [i].busWidth); /* Configure the operating rate */ CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_RATE, hwSetup->serDesTxChannelCfg [i].rate); /* Configure the polarity */ CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_INVPAIR, hwSetup->serDesTxChannelCfg [i].invertedPolarity); /* Configure the common mode */ CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_CM, hwSetup->serDesTxChannelCfg [i].commonMode); /* Configure the output swing */ CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_SWING, hwSetup->serDesTxChannelCfg [i].outputSwing); /* Configure the output de-emphasis */ CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_DE, hwSetup->serDesTxChannelCfg [i].outputDeEmphasis); /* Enable/disable the fixed phase */ CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_ENFTP, hwSetup->serDesTxChannelCfg [i].enableFixedPhase); /* Enable the transmitter */ CSL_FINST (hSrio->regs->SERDES_CFGTX_CNTL[i], SRIO_SERDES_CFGTX_CNTL_ENTX, ENABLE); } } /* flow control setup */ for (i = 0; i < CSL_SRIO_FLOW_CONTROL_REG_MAX; i++) { CSL_FINS(hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_TT, hwSetup->flowCntlIdLen[i]); CSL_FINS(hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_FLOW_CNTL_ID, hwSetup->flowCntlId[i]); } /* the processing element address bits setup */ hSrio->regs->PE_LL_CTL = hwSetup->peLlAddrCtrl; /* Base device configuration */ CSL_FINS(hSrio->regs->BASE_ID, SRIO_BASE_ID_BASE_DEVICEID, hwSetup->devIdSetup.smallTrBaseDevId); CSL_FINS(hSrio->regs->BASE_ID, SRIO_BASE_ID_LARGE_BASE_DEVICEID, hwSetup->devIdSetup.largeTrBaseDevId); CSL_FINS(hSrio->regs->HOST_BASE_ID_LOCK, SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID, hwSetup->devIdSetup.hostBaseDevId); /* Software defined component Tag for PE (processing element) setup */ hSrio->regs->COMP_TAG = hwSetup->componentTag; /* Port General configuration */ CSL_FINS(hSrio->regs->SP_LT_CTL, SRIO_SP_LT_CTL_TIMEOUT_VALUE, hwSetup->portGenSetup.portLinkTimeout); CSL_FINS(hSrio->regs->SP_RT_CTL, SRIO_SP_RT_CTL_TIMEOUT_VALUE, hwSetup->portGenSetup.portRespTimeout); CSL_FINS(hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_HOST, hwSetup->portGenSetup.hostEn); CSL_FINS(hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_MASTER_ENABLE, hwSetup->portGenSetup.masterEn); /* port control configuration */ for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_DISABLE, hwSetup->portCntlSetup[i].portDis); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_OUTPUT_PORT_ENABLE, hwSetup->portCntlSetup[i].outPortEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_INPUT_PORT_ENABLE, hwSetup->portCntlSetup[i].inPortEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_WIDTH_OVERRIDE, hwSetup->portCntlSetup[i].portWidthOverride); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_ERROR_CHECK_DISABLE, hwSetup->portCntlSetup[i].errCheckDis); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_MULTICAST_PARTICIPANT, hwSetup->portCntlSetup[i].multicastRcvEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE, hwSetup->portCntlSetup[i].stopOnPortFailEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_DROP_PACKET_ENABLE, hwSetup->portCntlSetup[i].dropPktEn); CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_LOCKOUT, hwSetup->portCntlSetup[i].portLockoutEn); } /* logical/transport layer errors setup */ hSrio->regs->ERR_EN = hwSetup->lgclTransErrEn; /* port error configuration */ for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { hSrio->regs->PORT_ERROR[i].SP_RATE_EN = hwSetup->portErrSetup[i].portErrRateEn; CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_RATE, SRIO_SP_ERR_RATE_ERROR_RATE_BIAS, hwSetup->portErrSetup[i].prtErrRtBias); CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_RATE, SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY, hwSetup->portErrSetup[i].portErrRtRec); CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH, SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD, hwSetup->portErrSetup[i].portErrRtFldThresh); CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH, SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES, hwSetup->portErrSetup[i].portErrRtDegrdThresh); } /* the discovery timer value setup */ CSL_FINS(hSrio->regs->SP_IP_DISCOVERY_TIMER, SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER, hwSetup->discoveryTimer); /* port write timer value setup */ CSL_FINS(hSrio->regs->SP_IP_DISCOVERY_TIMER, SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER, hwSetup->pwTimer); /* configuration of SP_IP_MODE register */ hSrio->regs->SP_IP_MODE = hwSetup->portIpModeSet; /* configuration of SP_IP_PRESCALE register */ CSL_FINS(hSrio->regs->IP_PRESCAL, SRIO_IP_PRESCAL_PRESCALE, hwSetup->portIpPrescalar); /* setups for silence timer and Port control independent error * register */ for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) { CSL_FINS(hSrio->regs->PORT_OPTION[i].SP_SILENCE_TIMER, SRIO_SP_SILENCE_TIMER_SILENCE_TIMER, hwSetup->silenceTimer[i]); hSrio->regs->PORT_OPTION[i].SP_CTL_INDEP = hwSetup->portCntlIndpEn[i]; } /* Enable the peripheral */ CSL_FINS(hSrio->regs->PCR, SRIO_PCR_PEREN, hwSetup->perEn); } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_cfgAux.h

<filename>DSP/TI-Header/csl_c6455_src/inc/csl_cfgAux.h<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** =========================================================================== * @file csl_cfgAux.h * * @brief Header file for functional layer of CSL * * @path $(CSLPATH)\inc * * Description * - The defines inline function definitions * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 14-Apr-2005 Brn File Created * ============================================================================ */ #ifndef _CSL_CFGAUX_H_ #define _CSL_CFGAUX_H_ #include <csl_cfg.h> #ifdef __cplusplus extern "C" { #endif /** * Control Functions of cfg. */ /** ============================================================================ * @n@b CSL_cfgClear * * @b Description * @n This function clears the CFG module. * * @b Arguments * @verbatim hCfg Handle to CFG instance @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n Clears the status and flag values * * @b Example * @verbatim CSL_cfgEnable(hCfg); @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_cfgCmdClear ( /* Handle to CFG instance */ CSL_CfgHandle hCfg ) { CSL_FINS(((CSL_CfgRegs *)CSL_MEMPROT_CONFIG_REGS)-> MPFCR, CFG_MPFCR_MPFCLR, 1); } /** Status query functions */ /** ============================================================================ * @n@b CSL_cfgGetFaultAddr * * @b Description * @n This function returns the Fault Adrress. * * @b Arguments * @verbatim hCfg Handle to CFG instance faultAddr Place holder to get the Fault Address @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_cfgGetFaultAddr(hCfg); @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_cfgGetFaultAddr ( /* Handle to CFG instance */ CSL_CfgHandle hCfg, /* Pointer which holds the fault address */ Uint32 *faultAddr ) { *faultAddr = ((CSL_CfgRegs*)CSL_MEMPROT_CONFIG_REGS)->MPFAR; } /** ============================================================================ * @n@b CSL_cfgGetCfgStat * * @b Description * @n This function gets the CFG status information. * * @b Arguments * @verbatim hCfg Handle to CFG instance cfgStatus Placeholder to return status. @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_cfgGetCfgStat(hCfg, &cfgStatus); @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_cfgGetFaultStat ( /* Handle to CFG instance */ CSL_CfgHandle hCfg, /* Placeholder to return the status. @a void* casted */ CSL_CfgFaultStatus *faultStatus ) { faultStatus->errorMask = CSL_FEXTR(((CSL_CfgRegs*)CSL_MEMPROT_CONFIG_REGS)->MPFSR, 8, 0); faultStatus->faultId = CSL_FEXTR(((CSL_CfgRegs*)CSL_MEMPROT_CONFIG_REGS)->MPFSR, 15, 9); } #ifdef __cplusplus } #endif #endif /* CSL_CFGAUX_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_srio.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_srio.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for SRIO */ #ifndef _CSLR_SRIO_H_ #define _CSLR_SRIO_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure for the Buffer Descriptors \**************************************************************************/ typedef struct buffDesc { Uint32 nextDescPtr; Uint32 buffPtr; Uint32 opt1; Uint32 opt2; } CSL_SrioBuffDesc; /**************************************************************************\ * Register Overlay Structure for BLK_ENABLE \**************************************************************************/ typedef struct { volatile Uint32 BLK_EN; volatile Uint32 BLK_EN_STAT; } CSL_SrioBlk_enableRegs; /**************************************************************************\ * Register Overlay Structure for HW_PKT_FWD \**************************************************************************/ typedef struct { volatile Uint32 PF_16BIT_CNTL; volatile Uint32 PF_8BIT_CNTL; } CSL_SrioHw_pkt_fwdRegs; /**************************************************************************\ * Register Overlay Structure for DOORBELL_INTR \**************************************************************************/ typedef struct { volatile Uint32 DOORBELL_ICSR; volatile Uint8 RSVD0[4]; volatile Uint32 DOORBELL_ICCR; volatile Uint8 RSVD1[4]; } CSL_SrioDoorbell_intrRegs; /**************************************************************************\ * Register Overlay Structure for DOORBELL_INTR_ROUTE \**************************************************************************/ typedef struct { volatile Uint32 DOORBELL_ICRR; volatile Uint32 DOORBELL_ICRR2; volatile Uint8 RSVD0[8]; } CSL_SrioDoorbell_intr_routeRegs; /**************************************************************************\ * Register Overlay Structure for LSU \**************************************************************************/ typedef struct { volatile Uint32 LSU_REG0; volatile Uint32 LSU_REG1; volatile Uint32 LSU_REG2; volatile Uint32 LSU_REG3; volatile Uint32 LSU_REG4; volatile Uint32 LSU_REG5; volatile Uint32 LSU_REG6; volatile Uint32 LSU_FLOW_MASKS; } CSL_SrioLsuRegs; /**************************************************************************\ * Register Overlay Structure for MAP \**************************************************************************/ typedef struct { volatile Uint32 RXU_MAP_L; volatile Uint32 RXU_MAP_H; } CSL_SrioMapRegs; /**************************************************************************\ * Register Overlay Structure for PORT \**************************************************************************/ typedef struct { volatile Uint32 SP_LM_REQ; volatile Uint32 SP_LM_RESP; volatile Uint32 SP_ACKID_STAT; volatile Uint8 RSVD0[12]; volatile Uint32 SP_ERR_STAT; volatile Uint32 SP_CTL; } CSL_SrioPortRegs; /**************************************************************************\ * Register Overlay Structure for PORT_ERROR \**************************************************************************/ typedef struct { volatile Uint32 SP_ERR_DET; volatile Uint32 SP_RATE_EN; volatile Uint32 SP_ERR_ATTR_CAPT_DBG0; volatile Uint32 SP_ERR_CAPT_DBG[4]; volatile Uint8 RSVD0[12]; volatile Uint32 SP_ERR_RATE; volatile Uint32 SP_ERR_THRESH; volatile Uint8 RSVD1[16]; } CSL_SrioPort_errorRegs; /**************************************************************************\ * Register Overlay Structure for PORT_OPTION \**************************************************************************/ typedef struct { volatile Uint32 SP_RST_OPT; volatile Uint32 SP_CTL_INDEP; volatile Uint32 SP_SILENCE_TIMER; volatile Uint32 SP_MULT_EVNT_CS; volatile Uint8 RSVD0[4]; volatile Uint32 SP_CS_TX; volatile Uint8 RSVD1[232]; } CSL_SrioPort_optionRegs; /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint32 PID; volatile Uint32 PCR; volatile Uint8 RSVD0[24]; volatile Uint32 PER_SET_CNTL; volatile Uint8 RSVD1[12]; volatile Uint32 GBL_EN; volatile Uint32 GBL_EN_STAT; CSL_SrioBlk_enableRegs BLK_ENABLE[9]; volatile Uint32 DEVICEID_REG1; volatile Uint32 DEVICEID_REG2; volatile Uint8 RSVD3[8]; CSL_SrioHw_pkt_fwdRegs HW_PKT_FWD[4]; volatile Uint8 RSVD4[80]; volatile Uint32 SERDES_CFGRX_CNTL[4]; volatile Uint32 SERDES_CFGTX_CNTL[4]; volatile Uint32 SERDES_CFG_CNTL[4]; volatile Uint8 RSVD5[208]; CSL_SrioDoorbell_intrRegs DOORBELL_INTR[4]; volatile Uint32 RX_CPPI_ICSR; volatile Uint8 RSVD6[4]; volatile Uint32 RX_CPPI_ICCR; volatile Uint8 RSVD7[4]; volatile Uint32 TX_CPPI_ICSR; volatile Uint8 RSVD8[4]; volatile Uint32 TX_CPPI_ICCR; volatile Uint8 RSVD9[4]; volatile Uint32 LSU_ICSR; volatile Uint8 RSVD10[4]; volatile Uint32 LSU_ICCR; volatile Uint8 RSVD11[4]; volatile Uint32 ERR_RST_EVNT_ICSR; volatile Uint8 RSVD12[4]; volatile Uint32 ERR_RST_EVNT_ICCR; volatile Uint8 RSVD13[4]; CSL_SrioDoorbell_intr_routeRegs DOORBELL_INTR_ROUTE[4]; volatile Uint32 RX_CPPI_ICRR; volatile Uint32 RX_CPPI_ICRR2; volatile Uint8 RSVD14[8]; volatile Uint32 TX_CPPI_ICRR; volatile Uint32 TX_CPPI_ICRR2; volatile Uint8 RSVD15[8]; volatile Uint32 LSU_ICRR[4]; volatile Uint32 ERR_RST_EVNT_ICRR; volatile Uint32 ERR_RST_EVNT_ICRR2; volatile Uint32 ERR_RST_EVNT_ICRR3; volatile Uint8 RSVD16[4]; volatile Uint32 INTDST_DECODE[8]; volatile Uint32 INTDST_RATE_CNTL[8]; volatile Uint8 RSVD17[192]; CSL_SrioLsuRegs LSU[4]; volatile Uint8 RSVD18[128]; volatile Uint32 QUEUE_TXDMA_HDP[16]; volatile Uint8 RSVD19[64]; volatile Uint32 QUEUE_TXDMA_CP[16]; volatile Uint8 RSVD20[64]; volatile Uint32 QUEUE_RXDMA_HDP[16]; volatile Uint8 RSVD21[64]; volatile Uint32 QUEUE_RXDMA_CP[16]; volatile Uint8 RSVD22[64]; volatile Uint32 TX_QUEUE_TEAR_DOWN; volatile Uint32 TX_CPPI_FLOW_MASKS[8]; volatile Uint8 RSVD23[28]; volatile Uint32 RX_QUEUE_TEAR_DOWN; volatile Uint32 RX_CPPI_CNTL; volatile Uint8 RSVD24[152]; volatile Uint32 TX_QUEUE_CNTL0; volatile Uint32 TX_QUEUE_CNTL1; volatile Uint32 TX_QUEUE_CNTL2; volatile Uint32 TX_QUEUE_CNTL3; volatile Uint8 RSVD25[16]; CSL_SrioMapRegs MAP[32]; volatile Uint32 FLOW_CNTL[16]; volatile Uint8 RSVD27[1728]; volatile Uint32 DEV_ID; volatile Uint32 DEV_INFO; volatile Uint32 ASBLY_ID; volatile Uint32 ASBLY_INFO; volatile Uint32 PE_FEAT; volatile Uint8 RSVD28[4]; volatile Uint32 SRC_OP; volatile Uint32 DEST_OP; volatile Uint8 RSVD29[44]; volatile Uint32 PE_LL_CTL; volatile Uint8 RSVD30[8]; volatile Uint32 LCL_CFG_HBAR; volatile Uint32 LCL_CFG_BAR; volatile Uint32 BASE_ID; volatile Uint8 RSVD31[4]; volatile Uint32 HOST_BASE_ID_LOCK; volatile Uint32 COMP_TAG; volatile Uint8 RSVD32[144]; volatile Uint32 SP_MB_HEAD; volatile Uint8 RSVD33[28]; volatile Uint32 SP_LT_CTL; volatile Uint32 SP_RT_CTL; volatile Uint8 RSVD34[20]; volatile Uint32 SP_GEN_CTL; CSL_SrioPortRegs PORT[4]; volatile Uint8 RSVD35[3648]; volatile Uint32 ERR_RPT_BH; volatile Uint8 RSVD36[4]; volatile Uint32 ERR_DET; volatile Uint32 ERR_EN; volatile Uint32 H_ADDR_CAPT; volatile Uint32 ADDR_CAPT; volatile Uint32 ID_CAPT; volatile Uint32 CTRL_CAPT; volatile Uint8 RSVD37[8]; volatile Uint32 PW_TGT_ID; volatile Uint8 RSVD38[20]; CSL_SrioPort_errorRegs PORT_ERROR[4]; volatile Uint8 RSVD39[65216]; volatile Uint32 SP_IP_DISCOVERY_TIMER; volatile Uint32 SP_IP_MODE; volatile Uint32 IP_PRESCAL; volatile Uint8 RSVD40[4]; volatile Uint32 SP_IP_PW_IN_CAPT[4]; volatile Uint8 RSVD41[8160]; CSL_SrioPort_optionRegs PORT_OPTION[4]; volatile Uint8 RSVD42[965864]; CSL_SrioBuffDesc txBuffDesc[32]; CSL_SrioBuffDesc rxBuffDesc[32]; } CSL_SrioRegs; /**************************************************************************\ * Overlay structure typedef definition \**************************************************************************/ typedef volatile CSL_SrioRegs *CSL_SrioRegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* PID */ #define CSL_SRIO_PID_TYPE_MASK (0x00FF0000u) #define CSL_SRIO_PID_TYPE_SHIFT (0x00000010u) #define CSL_SRIO_PID_TYPE_RESETVAL (0x00000001u) #define CSL_SRIO_PID_CLASS_MASK (0x0000FF00u) #define CSL_SRIO_PID_CLASS_SHIFT (0x00000008u) #define CSL_SRIO_PID_CLASS_RESETVAL (0x0000000Au) #define CSL_SRIO_PID_REV_MASK (0x000000FFu) #define CSL_SRIO_PID_REV_SHIFT (0x00000000u) #define CSL_SRIO_PID_REV_RESETVAL (0x00000001u) #define CSL_SRIO_PID_RESETVAL (0x00010A01u) /* PCR */ #define CSL_SRIO_PCR_PEREN_MASK (0x00000004u) #define CSL_SRIO_PCR_PEREN_SHIFT (0x00000002u) #define CSL_SRIO_PCR_PEREN_RESETVAL (0x00000000u) /*----PEREN Tokens----*/ #define CSL_SRIO_PCR_PEREN_DISABLE (0x00000000u) #define CSL_SRIO_PCR_PEREN_ENABLE (0x00000001u) #define CSL_SRIO_PCR_SOFT_MASK (0x00000002u) #define CSL_SRIO_PCR_SOFT_SHIFT (0x00000001u) #define CSL_SRIO_PCR_SOFT_RESETVAL (0x00000000u) #define CSL_SRIO_PCR_FREE_MASK (0x00000001u) #define CSL_SRIO_PCR_FREE_SHIFT (0x00000000u) #define CSL_SRIO_PCR_FREE_RESETVAL (0x00000001u) #define CSL_SRIO_PCR_RESETVAL (0x00000001u) /* PER_SET_CNTL */ #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_MASK (0x04000000u) #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_SHIFT (0x0000001Au) #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_RESETVAL (0x00000001u) /*----SW_MEM_SLEEP_OVERRIDE Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_MASK (0x02000000u) #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_SHIFT (0x00000019u) #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_RESETVAL (0x00000000u) /*----LOOPBACK Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_NORMAL (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_LOOPBACK_LOOPBACK (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_MASK (0x01000000u) #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_SHIFT (0x00000018u) #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_RESETVAL (0x00000000u) /*----BOOT_COMPLETE Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_WRITE_ENABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_WRITE_DISABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI2_WM_MASK (0x001C0000u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI2_WM_SHIFT (0x00000012u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI2_WM_RESETVAL (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI1_WM_MASK (0x00038000u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI1_WM_SHIFT (0x0000000Fu) #define CSL_SRIO_PER_SET_CNTL_TX_PRI1_WM_RESETVAL (0x00000002u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI0_WM_MASK (0x00007000u) #define CSL_SRIO_PER_SET_CNTL_TX_PRI0_WM_SHIFT (0x0000000Cu) #define CSL_SRIO_PER_SET_CNTL_TX_PRI0_WM_RESETVAL (0x00000003u) #define CSL_SRIO_PER_SET_CNTL_CBA_TRANS_PRI_MASK (0x00000E00u) #define CSL_SRIO_PER_SET_CNTL_CBA_TRANS_PRI_SHIFT (0x00000009u) #define CSL_SRIO_PER_SET_CNTL_CBA_TRANS_PRI_RESETVAL (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_1X_MODE_MASK (0x00000100u) #define CSL_SRIO_PER_SET_CNTL_1X_MODE_SHIFT (0x00000008u) #define CSL_SRIO_PER_SET_CNTL_1X_MODE_RESETVAL (0x00000000u) /*----1X_MODE Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_1X_MODE_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_1X_MODE_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_MASK (0x000000F0u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_SHIFT (0x00000004u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_RESETVAL (0x00000000u) /*----PRESCALER_SELECT Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_1 (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_2 (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_3 (0x00000002u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_4 (0x00000003u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_5 (0x00000004u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_6 (0x00000005u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_7 (0x00000006u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_8 (0x00000007u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_9 (0x00000008u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_10 (0x00000009u) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_11 (0x0000000Au) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_12 (0x0000000Bu) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_13 (0x0000000Cu) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_14 (0x0000000Du) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_15 (0x0000000Eu) #define CSL_SRIO_PER_SET_CNTL_PRESCALER_SELECT_16 (0x0000000Fu) #define CSL_SRIO_PER_SET_CNTL_ENPLL4_MASK (0x00000008u) #define CSL_SRIO_PER_SET_CNTL_ENPLL4_SHIFT (0x00000003u) #define CSL_SRIO_PER_SET_CNTL_ENPLL4_RESETVAL (0x00000000u) /*----ENPLL4 Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_ENPLL4_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL4_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL3_MASK (0x00000004u) #define CSL_SRIO_PER_SET_CNTL_ENPLL3_SHIFT (0x00000002u) #define CSL_SRIO_PER_SET_CNTL_ENPLL3_RESETVAL (0x00000000u) /*----ENPLL3 Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_ENPLL3_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL3_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL2_MASK (0x00000002u) #define CSL_SRIO_PER_SET_CNTL_ENPLL2_SHIFT (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL2_RESETVAL (0x00000000u) /*----ENPLL2 Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_ENPLL2_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL2_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL1_MASK (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_ENPLL1_SHIFT (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL1_RESETVAL (0x00000000u) /*----ENPLL1 Tokens----*/ #define CSL_SRIO_PER_SET_CNTL_ENPLL1_DISABLE (0x00000000u) #define CSL_SRIO_PER_SET_CNTL_ENPLL1_ENABLE (0x00000001u) #define CSL_SRIO_PER_SET_CNTL_RESETVAL (0x04053000u) /* GBL_EN */ #define CSL_SRIO_GBL_EN_EN_MASK (0x00000001u) #define CSL_SRIO_GBL_EN_EN_SHIFT (0x00000000u) #define CSL_SRIO_GBL_EN_EN_RESETVAL (0x00000000u) /*----EN Tokens----*/ #define CSL_SRIO_GBL_EN_EN_DISABLE (0x00000000u) #define CSL_SRIO_GBL_EN_EN_ENABLE (0x00000001u) #define CSL_SRIO_GBL_EN_RESETVAL (0x00000000u) /* GBL_EN_STAT */ #define CSL_SRIO_GBL_EN_STAT_GBL_EN_STAT_MASK (0x00000001u) #define CSL_SRIO_GBL_EN_STAT_GBL_EN_STAT_SHIFT (0x00000000u) #define CSL_SRIO_GBL_EN_STAT_GBL_EN_STAT_RESETVAL (0x00000000u) #define CSL_SRIO_GBL_EN_STAT_RESETVAL (0x00000000u) /* BLK_EN */ #define CSL_SRIO_BLK_EN_EN_MASK (0x00000001u) #define CSL_SRIO_BLK_EN_EN_SHIFT (0x00000000u) #define CSL_SRIO_BLK_EN_EN_RESETVAL (0x00000000u) /*----EN Tokens----*/ #define CSL_SRIO_BLK_EN_EN_DISABLE (0x00000000u) #define CSL_SRIO_BLK_EN_EN_ENABLE (0x00000001u) #define CSL_SRIO_BLK_EN_RESETVAL (0x00000000u) /* BLK_EN_STAT */ #define CSL_SRIO_BLK_EN_STAT_EN_STAT_MASK (0x00000001u) #define CSL_SRIO_BLK_EN_STAT_EN_STAT_SHIFT (0x00000000u) #define CSL_SRIO_BLK_EN_STAT_EN_STAT_RESETVAL (0x00000000u) #define CSL_SRIO_BLK_EN_STAT_RESETVAL (0x00000000u) /* DEVICEID_REG1 */ #define CSL_SRIO_DEVICEID_REG1_8BNODEID_MASK (0x00FF0000u) #define CSL_SRIO_DEVICEID_REG1_8BNODEID_SHIFT (0x00000010u) #define CSL_SRIO_DEVICEID_REG1_8BNODEID_RESETVAL (0x000000FFu) #define CSL_SRIO_DEVICEID_REG1_16BNODEID_MASK (0x0000FFFFu) #define CSL_SRIO_DEVICEID_REG1_16BNODEID_SHIFT (0x00000000u) #define CSL_SRIO_DEVICEID_REG1_16BNODEID_RESETVAL (0x0000FFFFu) #define CSL_SRIO_DEVICEID_REG1_RESETVAL (0x00FFFFFFu) /* DEVICEID_REG2 */ #define CSL_SRIO_DEVICEID_REG2_8BNODEID_MASK (0x00FF0000u) #define CSL_SRIO_DEVICEID_REG2_8BNODEID_SHIFT (0x00000010u) #define CSL_SRIO_DEVICEID_REG2_8BNODEID_RESETVAL (0x000000FFu) #define CSL_SRIO_DEVICEID_REG2_16BNODEID_MASK (0x0000FFFFu) #define CSL_SRIO_DEVICEID_REG2_16BNODEID_SHIFT (0x00000000u) #define CSL_SRIO_DEVICEID_REG2_16BNODEID_RESETVAL (0x0000FFFFu) #define CSL_SRIO_DEVICEID_REG2_RESETVAL (0x00FFFFFFu) /* PF_16BIT_CNTL */ #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND_MASK (0xFFFF0000u) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND_SHIFT (0x00000010u) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND_RESETVAL (0x0000FFFFu) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND_MASK (0x0000FFFFu) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND_SHIFT (0x00000000u) #define CSL_SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND_RESETVAL (0x0000FFFFu) #define CSL_SRIO_PF_16BIT_CNTL_RESETVAL (0xFFFFFFFFu) /* PF_8BIT_CNTL */ #define CSL_SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT_MASK (0x00030000u) #define CSL_SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT_SHIFT (0x00000010u) #define CSL_SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT_RESETVAL (0x00000003u) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND_MASK (0x0000FF00u) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND_SHIFT (0x00000008u) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND_RESETVAL (0x000000FFu) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND_MASK (0x000000FFu) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND_SHIFT (0x00000000u) #define CSL_SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND_RESETVAL (0x000000FFu) #define CSL_SRIO_PF_8BIT_CNTL_RESETVAL (0x0003FFFFu) /* SERDES_CFGRX_CNTL */ #define CSL_SRIO_SERDES_CFGRX_CNTL_EQ_MASK (0x00780000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_EQ_SHIFT (0x00000013u) #define CSL_SRIO_SERDES_CFGRX_CNTL_EQ_RESETVAL (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_CDR_MASK (0x00070000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_CDR_SHIFT (0x00000010u) #define CSL_SRIO_SERDES_CFGRX_CNTL_CDR_RESETVAL (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_MASK (0x0000C000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_SHIFT (0x0000000Eu) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_RESETVAL (0x00000000u) /*----LOS Tokens----*/ #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_DISABLED (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_HIGH_THRESHOLD (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_LOS_LOW_THRESHOLD (0x00000002u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_MASK (0x00003000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_SHIFT (0x0000000Cu) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_RESETVAL (0x00000000u) /*----ALIGN Tokens----*/ #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_DISABLE (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_COMMA (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ALIGN_JOG (0x00000002u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_MASK (0x00000700u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_SHIFT (0x00000008u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_RESETVAL (0x00000000u) /*----TERM Tokens----*/ #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_VDDT (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_0_8_VDDT (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_TERM_FLOATING (0x00000003u) #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_MASK (0x00000080u) #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_SHIFT (0x00000007u) #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_RESETVAL (0x00000000u) /*----INVPAIR Tokens----*/ #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_NORMAL (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_INVPAIR_INVERTED (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_MASK (0x00000060u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_SHIFT (0x00000005u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_RESETVAL (0x00000000u) /*----RATE Tokens----*/ #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_FULL (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_HALF (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RATE_QUARTER (0x00000002u) #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_MASK (0x0000001Cu) #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_SHIFT (0x00000002u) #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_RESETVAL (0x00000000u) /*----BUSWIDTH Tokens----*/ #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_10BIT (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_BUSWIDTH_8BIT (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_MASK (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_SHIFT (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_RESETVAL (0x00000000u) /*----ENRX Tokens----*/ #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_DISABLE (0x00000000u) #define CSL_SRIO_SERDES_CFGRX_CNTL_ENRX_ENABLE (0x00000001u) #define CSL_SRIO_SERDES_CFGRX_CNTL_RESETVAL (0x00000000u) /* SERDES_CFGTX_CNTL */ #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_MASK (0x00010000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_SHIFT (0x00000010u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_RESETVAL (0x00000000u) /*----ENFTP Tokens----*/ #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_ARBITRARY (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENFTP_FIXED (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_MASK (0x0000F000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_SHIFT (0x0000000Cu) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_RESETVAL (0x00000000u) /*----DE Tokens----*/ #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_4_76 (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_9_52 (0x00000002u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_14_28 (0x00000003u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_19_04 (0x00000004u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_23_80 (0x00000005u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_28_56 (0x00000006u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_33_32 (0x00000007u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_38_08 (0x00000008u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_42_85 (0x00000009u) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_47_61 (0x0000000Au) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_52_38 (0x0000000Bu) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_57_14 (0x0000000Cu) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_61_90 (0x0000000Du) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_66_66 (0x0000000Eu) #define CSL_SRIO_SERDES_CFGTX_CNTL_DE_71_42 (0x0000000Fu) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_MASK (0x00000E00u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_SHIFT (0x00000009u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_RESETVAL (0x00000000u) /*----SWING Tokens----*/ #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_125 (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_250 (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_500 (0x00000002u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_625 (0x00000003u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_750 (0x00000004u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_1000 (0x00000005u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_1125 (0x00000006u) #define CSL_SRIO_SERDES_CFGTX_CNTL_SWING_1250 (0x00000007u) #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_MASK (0x00000100u) #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_SHIFT (0x00000008u) #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_RESETVAL (0x00000000u) /*----CM Tokens----*/ #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_NORMAL (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_CM_RAISED (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_MASK (0x00000080u) #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_SHIFT (0x00000007u) #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_RESETVAL (0x00000000u) /*----INVPAIR Tokens----*/ #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_NORMAL (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_INVPAIR_INVERTED (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_MASK (0x00000060u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_SHIFT (0x00000005u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_RESETVAL (0x00000000u) /*----RATE Tokens----*/ #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_FULL (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_HALF (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RATE_QUARTER (0x00000002u) #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_MASK (0x0000001Cu) #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_SHIFT (0x00000002u) #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_RESETVAL (0x00000000u) /*----BUSWIDTH Tokens----*/ #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_10BIT (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_BUSWIDTH_8BIT (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_MASK (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_SHIFT (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_RESETVAL (0x00000000u) /*----ENTX Tokens----*/ #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_DISABLE (0x00000000u) #define CSL_SRIO_SERDES_CFGTX_CNTL_ENTX_ENABLE (0x00000001u) #define CSL_SRIO_SERDES_CFGTX_CNTL_RESETVAL (0x00000000u) /* SERDES_CFG_CNTL */ #define CSL_SRIO_SERDES_CFG_CNTL_LB_MASK (0x00000300u) #define CSL_SRIO_SERDES_CFG_CNTL_LB_SHIFT (0x00000008u) #define CSL_SRIO_SERDES_CFG_CNTL_LB_RESETVAL (0x00000000u) /*----LB Tokens----*/ #define CSL_SRIO_SERDES_CFG_CNTL_LB_FREQ_DEP (0x00000000u) #define CSL_SRIO_SERDES_CFG_CNTL_LB_LOW (0x00000002u) #define CSL_SRIO_SERDES_CFG_CNTL_LB_HIGH (0x00000003u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_MASK (0x0000003Eu) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_SHIFT (0x00000001u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_RESETVAL (0x00000000u) /*----MPY Tokens----*/ #define CSL_SRIO_SERDES_CFG_CNTL_MPY_4 (0x00000000u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_5 (0x00000001u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_6 (0x00000002u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_8 (0x00000004u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_10 (0x00000005u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_12 (0x00000006u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_12_5 (0x00000007u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_15 (0x00000008u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_20 (0x00000009u) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_25 (0x0000000Au) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_50 (0x0000000Du) #define CSL_SRIO_SERDES_CFG_CNTL_MPY_60 (0x0000000Eu) #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_MASK (0x00000001u) #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_SHIFT (0x00000000u) #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_RESETVAL (0x00000000u) /*----ENPLL Tokens----*/ #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_DISABLE (0x00000000u) #define CSL_SRIO_SERDES_CFG_CNTL_ENPLL_ENABLE (0x00000001u) #define CSL_SRIO_SERDES_CFG_CNTL_RESETVAL (0x00000000u) /* DOORBELL_ICSR */ #define CSL_SRIO_DOORBELL_ICSR_ICS15_MASK (0x00008000u) #define CSL_SRIO_DOORBELL_ICSR_ICS15_SHIFT (0x0000000Fu) #define CSL_SRIO_DOORBELL_ICSR_ICS15_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS14_MASK (0x00004000u) #define CSL_SRIO_DOORBELL_ICSR_ICS14_SHIFT (0x0000000Eu) #define CSL_SRIO_DOORBELL_ICSR_ICS14_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS13_MASK (0x00002000u) #define CSL_SRIO_DOORBELL_ICSR_ICS13_SHIFT (0x0000000Du) #define CSL_SRIO_DOORBELL_ICSR_ICS13_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS12_MASK (0x00001000u) #define CSL_SRIO_DOORBELL_ICSR_ICS12_SHIFT (0x0000000Cu) #define CSL_SRIO_DOORBELL_ICSR_ICS12_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_DOORBELL_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_DOORBELL_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_DOORBELL_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_DOORBELL_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_DOORBELL_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_DOORBELL_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_DOORBELL_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_DOORBELL_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS7_MASK (0x00000080u) #define CSL_SRIO_DOORBELL_ICSR_ICS7_SHIFT (0x00000007u) #define CSL_SRIO_DOORBELL_ICSR_ICS7_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS6_MASK (0x00000040u) #define CSL_SRIO_DOORBELL_ICSR_ICS6_SHIFT (0x00000006u) #define CSL_SRIO_DOORBELL_ICSR_ICS6_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS5_MASK (0x00000020u) #define CSL_SRIO_DOORBELL_ICSR_ICS5_SHIFT (0x00000005u) #define CSL_SRIO_DOORBELL_ICSR_ICS5_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS4_MASK (0x00000010u) #define CSL_SRIO_DOORBELL_ICSR_ICS4_SHIFT (0x00000004u) #define CSL_SRIO_DOORBELL_ICSR_ICS4_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS3_MASK (0x00000008u) #define CSL_SRIO_DOORBELL_ICSR_ICS3_SHIFT (0x00000003u) #define CSL_SRIO_DOORBELL_ICSR_ICS3_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_DOORBELL_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_DOORBELL_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_DOORBELL_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_DOORBELL_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_DOORBELL_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICSR_RESETVAL (0x00000000u) /* DOORBELL_ICCR */ #define CSL_SRIO_DOORBELL_ICCR_ICC15_MASK (0x00008000u) #define CSL_SRIO_DOORBELL_ICCR_ICC15_SHIFT (0x0000000Fu) #define CSL_SRIO_DOORBELL_ICCR_ICC15_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC14_MASK (0x00004000u) #define CSL_SRIO_DOORBELL_ICCR_ICC14_SHIFT (0x0000000Eu) #define CSL_SRIO_DOORBELL_ICCR_ICC14_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC13_MASK (0x00002000u) #define CSL_SRIO_DOORBELL_ICCR_ICC13_SHIFT (0x0000000Du) #define CSL_SRIO_DOORBELL_ICCR_ICC13_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC12_MASK (0x00001000u) #define CSL_SRIO_DOORBELL_ICCR_ICC12_SHIFT (0x0000000Cu) #define CSL_SRIO_DOORBELL_ICCR_ICC12_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_DOORBELL_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_DOORBELL_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_DOORBELL_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_DOORBELL_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_DOORBELL_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_DOORBELL_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_DOORBELL_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_DOORBELL_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC7_MASK (0x00000080u) #define CSL_SRIO_DOORBELL_ICCR_ICC7_SHIFT (0x00000007u) #define CSL_SRIO_DOORBELL_ICCR_ICC7_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC6_MASK (0x00000040u) #define CSL_SRIO_DOORBELL_ICCR_ICC6_SHIFT (0x00000006u) #define CSL_SRIO_DOORBELL_ICCR_ICC6_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC5_MASK (0x00000020u) #define CSL_SRIO_DOORBELL_ICCR_ICC5_SHIFT (0x00000005u) #define CSL_SRIO_DOORBELL_ICCR_ICC5_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC4_MASK (0x00000010u) #define CSL_SRIO_DOORBELL_ICCR_ICC4_SHIFT (0x00000004u) #define CSL_SRIO_DOORBELL_ICCR_ICC4_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC3_MASK (0x00000008u) #define CSL_SRIO_DOORBELL_ICCR_ICC3_SHIFT (0x00000003u) #define CSL_SRIO_DOORBELL_ICCR_ICC3_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_DOORBELL_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_DOORBELL_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_DOORBELL_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_DOORBELL_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_DOORBELL_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICCR_RESETVAL (0x00000000u) /* RX_CPPI_ICSR */ #define CSL_SRIO_RX_CPPI_ICSR_ICS15_MASK (0x00008000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS15_SHIFT (0x0000000Fu) #define CSL_SRIO_RX_CPPI_ICSR_ICS15_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS14_MASK (0x00004000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS14_SHIFT (0x0000000Eu) #define CSL_SRIO_RX_CPPI_ICSR_ICS14_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS13_MASK (0x00002000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS13_SHIFT (0x0000000Du) #define CSL_SRIO_RX_CPPI_ICSR_ICS13_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS12_MASK (0x00001000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS12_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_ICSR_ICS12_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_RX_CPPI_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_RX_CPPI_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_RX_CPPI_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_RX_CPPI_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_RX_CPPI_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_RX_CPPI_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_RX_CPPI_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS7_MASK (0x00000080u) #define CSL_SRIO_RX_CPPI_ICSR_ICS7_SHIFT (0x00000007u) #define CSL_SRIO_RX_CPPI_ICSR_ICS7_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS6_MASK (0x00000040u) #define CSL_SRIO_RX_CPPI_ICSR_ICS6_SHIFT (0x00000006u) #define CSL_SRIO_RX_CPPI_ICSR_ICS6_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS5_MASK (0x00000020u) #define CSL_SRIO_RX_CPPI_ICSR_ICS5_SHIFT (0x00000005u) #define CSL_SRIO_RX_CPPI_ICSR_ICS5_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS4_MASK (0x00000010u) #define CSL_SRIO_RX_CPPI_ICSR_ICS4_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_ICSR_ICS4_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS3_MASK (0x00000008u) #define CSL_SRIO_RX_CPPI_ICSR_ICS3_SHIFT (0x00000003u) #define CSL_SRIO_RX_CPPI_ICSR_ICS3_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_RX_CPPI_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_RX_CPPI_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_RX_CPPI_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_RX_CPPI_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_RX_CPPI_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICSR_RESETVAL (0x00000000u) /* RX_CPPI_ICCR */ #define CSL_SRIO_RX_CPPI_ICCR_ICC15_MASK (0x00008000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC15_SHIFT (0x0000000Fu) #define CSL_SRIO_RX_CPPI_ICCR_ICC15_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC14_MASK (0x00004000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC14_SHIFT (0x0000000Eu) #define CSL_SRIO_RX_CPPI_ICCR_ICC14_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC13_MASK (0x00002000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC13_SHIFT (0x0000000Du) #define CSL_SRIO_RX_CPPI_ICCR_ICC13_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC12_MASK (0x00001000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC12_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_ICCR_ICC12_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_RX_CPPI_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_RX_CPPI_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_RX_CPPI_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_RX_CPPI_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_RX_CPPI_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_RX_CPPI_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_RX_CPPI_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC7_MASK (0x00000080u) #define CSL_SRIO_RX_CPPI_ICCR_ICC7_SHIFT (0x00000007u) #define CSL_SRIO_RX_CPPI_ICCR_ICC7_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC6_MASK (0x00000040u) #define CSL_SRIO_RX_CPPI_ICCR_ICC6_SHIFT (0x00000006u) #define CSL_SRIO_RX_CPPI_ICCR_ICC6_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC5_MASK (0x00000020u) #define CSL_SRIO_RX_CPPI_ICCR_ICC5_SHIFT (0x00000005u) #define CSL_SRIO_RX_CPPI_ICCR_ICC5_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC4_MASK (0x00000010u) #define CSL_SRIO_RX_CPPI_ICCR_ICC4_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_ICCR_ICC4_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC3_MASK (0x00000008u) #define CSL_SRIO_RX_CPPI_ICCR_ICC3_SHIFT (0x00000003u) #define CSL_SRIO_RX_CPPI_ICCR_ICC3_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_RX_CPPI_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_RX_CPPI_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_RX_CPPI_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_RX_CPPI_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_RX_CPPI_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICCR_RESETVAL (0x00000000u) /* TX_CPPI_ICSR */ #define CSL_SRIO_TX_CPPI_ICSR_ICS15_MASK (0x00008000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS15_SHIFT (0x0000000Fu) #define CSL_SRIO_TX_CPPI_ICSR_ICS15_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS14_MASK (0x00004000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS14_SHIFT (0x0000000Eu) #define CSL_SRIO_TX_CPPI_ICSR_ICS14_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS13_MASK (0x00002000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS13_SHIFT (0x0000000Du) #define CSL_SRIO_TX_CPPI_ICSR_ICS13_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS12_MASK (0x00001000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS12_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_ICSR_ICS12_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_TX_CPPI_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_TX_CPPI_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_TX_CPPI_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_TX_CPPI_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_TX_CPPI_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_TX_CPPI_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_TX_CPPI_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS7_MASK (0x00000080u) #define CSL_SRIO_TX_CPPI_ICSR_ICS7_SHIFT (0x00000007u) #define CSL_SRIO_TX_CPPI_ICSR_ICS7_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS6_MASK (0x00000040u) #define CSL_SRIO_TX_CPPI_ICSR_ICS6_SHIFT (0x00000006u) #define CSL_SRIO_TX_CPPI_ICSR_ICS6_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS5_MASK (0x00000020u) #define CSL_SRIO_TX_CPPI_ICSR_ICS5_SHIFT (0x00000005u) #define CSL_SRIO_TX_CPPI_ICSR_ICS5_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS4_MASK (0x00000010u) #define CSL_SRIO_TX_CPPI_ICSR_ICS4_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_ICSR_ICS4_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS3_MASK (0x00000008u) #define CSL_SRIO_TX_CPPI_ICSR_ICS3_SHIFT (0x00000003u) #define CSL_SRIO_TX_CPPI_ICSR_ICS3_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_TX_CPPI_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_TX_CPPI_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_TX_CPPI_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_TX_CPPI_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_TX_CPPI_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICSR_RESETVAL (0x00000000u) /* TX_CPPI_ICCR */ #define CSL_SRIO_TX_CPPI_ICCR_ICC15_MASK (0x00008000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC15_SHIFT (0x0000000Fu) #define CSL_SRIO_TX_CPPI_ICCR_ICC15_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC14_MASK (0x00004000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC14_SHIFT (0x0000000Eu) #define CSL_SRIO_TX_CPPI_ICCR_ICC14_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC13_MASK (0x00002000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC13_SHIFT (0x0000000Du) #define CSL_SRIO_TX_CPPI_ICCR_ICC13_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC12_MASK (0x00001000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC12_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_ICCR_ICC12_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_TX_CPPI_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_TX_CPPI_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_TX_CPPI_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_TX_CPPI_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_TX_CPPI_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_TX_CPPI_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_TX_CPPI_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC7_MASK (0x00000080u) #define CSL_SRIO_TX_CPPI_ICCR_ICC7_SHIFT (0x00000007u) #define CSL_SRIO_TX_CPPI_ICCR_ICC7_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC6_MASK (0x00000040u) #define CSL_SRIO_TX_CPPI_ICCR_ICC6_SHIFT (0x00000006u) #define CSL_SRIO_TX_CPPI_ICCR_ICC6_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC5_MASK (0x00000020u) #define CSL_SRIO_TX_CPPI_ICCR_ICC5_SHIFT (0x00000005u) #define CSL_SRIO_TX_CPPI_ICCR_ICC5_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC4_MASK (0x00000010u) #define CSL_SRIO_TX_CPPI_ICCR_ICC4_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_ICCR_ICC4_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC3_MASK (0x00000008u) #define CSL_SRIO_TX_CPPI_ICCR_ICC3_SHIFT (0x00000003u) #define CSL_SRIO_TX_CPPI_ICCR_ICC3_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_TX_CPPI_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_TX_CPPI_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_TX_CPPI_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_TX_CPPI_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_TX_CPPI_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICCR_RESETVAL (0x00000000u) /* LSU_ICSR */ #define CSL_SRIO_LSU_ICSR_ICS31_MASK (0x80000000u) #define CSL_SRIO_LSU_ICSR_ICS31_SHIFT (0x0000001Fu) #define CSL_SRIO_LSU_ICSR_ICS31_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS30_MASK (0x40000000u) #define CSL_SRIO_LSU_ICSR_ICS30_SHIFT (0x0000001Eu) #define CSL_SRIO_LSU_ICSR_ICS30_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS29_MASK (0x20000000u) #define CSL_SRIO_LSU_ICSR_ICS29_SHIFT (0x0000001Du) #define CSL_SRIO_LSU_ICSR_ICS29_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS28_MASK (0x10000000u) #define CSL_SRIO_LSU_ICSR_ICS28_SHIFT (0x0000001Cu) #define CSL_SRIO_LSU_ICSR_ICS28_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS27_MASK (0x08000000u) #define CSL_SRIO_LSU_ICSR_ICS27_SHIFT (0x0000001Bu) #define CSL_SRIO_LSU_ICSR_ICS27_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS26_MASK (0x04000000u) #define CSL_SRIO_LSU_ICSR_ICS26_SHIFT (0x0000001Au) #define CSL_SRIO_LSU_ICSR_ICS26_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS25_MASK (0x02000000u) #define CSL_SRIO_LSU_ICSR_ICS25_SHIFT (0x00000019u) #define CSL_SRIO_LSU_ICSR_ICS25_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS24_MASK (0x01000000u) #define CSL_SRIO_LSU_ICSR_ICS24_SHIFT (0x00000018u) #define CSL_SRIO_LSU_ICSR_ICS24_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS23_MASK (0x00800000u) #define CSL_SRIO_LSU_ICSR_ICS23_SHIFT (0x00000017u) #define CSL_SRIO_LSU_ICSR_ICS23_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS22_MASK (0x00400000u) #define CSL_SRIO_LSU_ICSR_ICS22_SHIFT (0x00000016u) #define CSL_SRIO_LSU_ICSR_ICS22_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS21_MASK (0x00200000u) #define CSL_SRIO_LSU_ICSR_ICS21_SHIFT (0x00000015u) #define CSL_SRIO_LSU_ICSR_ICS21_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS20_MASK (0x00100000u) #define CSL_SRIO_LSU_ICSR_ICS20_SHIFT (0x00000014u) #define CSL_SRIO_LSU_ICSR_ICS20_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS19_MASK (0x00080000u) #define CSL_SRIO_LSU_ICSR_ICS19_SHIFT (0x00000013u) #define CSL_SRIO_LSU_ICSR_ICS19_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS18_MASK (0x00040000u) #define CSL_SRIO_LSU_ICSR_ICS18_SHIFT (0x00000012u) #define CSL_SRIO_LSU_ICSR_ICS18_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS17_MASK (0x00020000u) #define CSL_SRIO_LSU_ICSR_ICS17_SHIFT (0x00000011u) #define CSL_SRIO_LSU_ICSR_ICS17_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS16_MASK (0x00010000u) #define CSL_SRIO_LSU_ICSR_ICS16_SHIFT (0x00000010u) #define CSL_SRIO_LSU_ICSR_ICS16_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS15_MASK (0x00008000u) #define CSL_SRIO_LSU_ICSR_ICS15_SHIFT (0x0000000Fu) #define CSL_SRIO_LSU_ICSR_ICS15_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS14_MASK (0x00004000u) #define CSL_SRIO_LSU_ICSR_ICS14_SHIFT (0x0000000Eu) #define CSL_SRIO_LSU_ICSR_ICS14_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS13_MASK (0x00002000u) #define CSL_SRIO_LSU_ICSR_ICS13_SHIFT (0x0000000Du) #define CSL_SRIO_LSU_ICSR_ICS13_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS12_MASK (0x00001000u) #define CSL_SRIO_LSU_ICSR_ICS12_SHIFT (0x0000000Cu) #define CSL_SRIO_LSU_ICSR_ICS12_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_LSU_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_LSU_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_LSU_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_LSU_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_LSU_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_LSU_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_LSU_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_LSU_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS7_MASK (0x00000080u) #define CSL_SRIO_LSU_ICSR_ICS7_SHIFT (0x00000007u) #define CSL_SRIO_LSU_ICSR_ICS7_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS6_MASK (0x00000040u) #define CSL_SRIO_LSU_ICSR_ICS6_SHIFT (0x00000006u) #define CSL_SRIO_LSU_ICSR_ICS6_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS5_MASK (0x00000020u) #define CSL_SRIO_LSU_ICSR_ICS5_SHIFT (0x00000005u) #define CSL_SRIO_LSU_ICSR_ICS5_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS4_MASK (0x00000010u) #define CSL_SRIO_LSU_ICSR_ICS4_SHIFT (0x00000004u) #define CSL_SRIO_LSU_ICSR_ICS4_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS3_MASK (0x00000008u) #define CSL_SRIO_LSU_ICSR_ICS3_SHIFT (0x00000003u) #define CSL_SRIO_LSU_ICSR_ICS3_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_LSU_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_LSU_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_LSU_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_LSU_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_LSU_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_LSU_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICSR_RESETVAL (0x00000000u) /* LSU_ICCR */ #define CSL_SRIO_LSU_ICCR_ICC31_MASK (0x80000000u) #define CSL_SRIO_LSU_ICCR_ICC31_SHIFT (0x0000001Fu) #define CSL_SRIO_LSU_ICCR_ICC31_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC30_MASK (0x40000000u) #define CSL_SRIO_LSU_ICCR_ICC30_SHIFT (0x0000001Eu) #define CSL_SRIO_LSU_ICCR_ICC30_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC29_MASK (0x20000000u) #define CSL_SRIO_LSU_ICCR_ICC29_SHIFT (0x0000001Du) #define CSL_SRIO_LSU_ICCR_ICC29_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC28_MASK (0x10000000u) #define CSL_SRIO_LSU_ICCR_ICC28_SHIFT (0x0000001Cu) #define CSL_SRIO_LSU_ICCR_ICC28_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC27_MASK (0x08000000u) #define CSL_SRIO_LSU_ICCR_ICC27_SHIFT (0x0000001Bu) #define CSL_SRIO_LSU_ICCR_ICC27_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC26_MASK (0x04000000u) #define CSL_SRIO_LSU_ICCR_ICC26_SHIFT (0x0000001Au) #define CSL_SRIO_LSU_ICCR_ICC26_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC25_MASK (0x02000000u) #define CSL_SRIO_LSU_ICCR_ICC25_SHIFT (0x00000019u) #define CSL_SRIO_LSU_ICCR_ICC25_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC24_MASK (0x01000000u) #define CSL_SRIO_LSU_ICCR_ICC24_SHIFT (0x00000018u) #define CSL_SRIO_LSU_ICCR_ICC24_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC23_MASK (0x00800000u) #define CSL_SRIO_LSU_ICCR_ICC23_SHIFT (0x00000017u) #define CSL_SRIO_LSU_ICCR_ICC23_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC22_MASK (0x00400000u) #define CSL_SRIO_LSU_ICCR_ICC22_SHIFT (0x00000016u) #define CSL_SRIO_LSU_ICCR_ICC22_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC21_MASK (0x00200000u) #define CSL_SRIO_LSU_ICCR_ICC21_SHIFT (0x00000015u) #define CSL_SRIO_LSU_ICCR_ICC21_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC20_MASK (0x00100000u) #define CSL_SRIO_LSU_ICCR_ICC20_SHIFT (0x00000014u) #define CSL_SRIO_LSU_ICCR_ICC20_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC19_MASK (0x00080000u) #define CSL_SRIO_LSU_ICCR_ICC19_SHIFT (0x00000013u) #define CSL_SRIO_LSU_ICCR_ICC19_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC18_MASK (0x00040000u) #define CSL_SRIO_LSU_ICCR_ICC18_SHIFT (0x00000012u) #define CSL_SRIO_LSU_ICCR_ICC18_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC17_MASK (0x00020000u) #define CSL_SRIO_LSU_ICCR_ICC17_SHIFT (0x00000011u) #define CSL_SRIO_LSU_ICCR_ICC17_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC16_MASK (0x00010000u) #define CSL_SRIO_LSU_ICCR_ICC16_SHIFT (0x00000010u) #define CSL_SRIO_LSU_ICCR_ICC16_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC15_MASK (0x00008000u) #define CSL_SRIO_LSU_ICCR_ICC15_SHIFT (0x0000000Fu) #define CSL_SRIO_LSU_ICCR_ICC15_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC14_MASK (0x00004000u) #define CSL_SRIO_LSU_ICCR_ICC14_SHIFT (0x0000000Eu) #define CSL_SRIO_LSU_ICCR_ICC14_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC13_MASK (0x00002000u) #define CSL_SRIO_LSU_ICCR_ICC13_SHIFT (0x0000000Du) #define CSL_SRIO_LSU_ICCR_ICC13_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC12_MASK (0x00001000u) #define CSL_SRIO_LSU_ICCR_ICC12_SHIFT (0x0000000Cu) #define CSL_SRIO_LSU_ICCR_ICC12_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_LSU_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_LSU_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_LSU_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_LSU_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_LSU_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_LSU_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_LSU_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_LSU_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC7_MASK (0x00000080u) #define CSL_SRIO_LSU_ICCR_ICC7_SHIFT (0x00000007u) #define CSL_SRIO_LSU_ICCR_ICC7_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC6_MASK (0x00000040u) #define CSL_SRIO_LSU_ICCR_ICC6_SHIFT (0x00000006u) #define CSL_SRIO_LSU_ICCR_ICC6_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC5_MASK (0x00000020u) #define CSL_SRIO_LSU_ICCR_ICC5_SHIFT (0x00000005u) #define CSL_SRIO_LSU_ICCR_ICC5_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC4_MASK (0x00000010u) #define CSL_SRIO_LSU_ICCR_ICC4_SHIFT (0x00000004u) #define CSL_SRIO_LSU_ICCR_ICC4_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC3_MASK (0x00000008u) #define CSL_SRIO_LSU_ICCR_ICC3_SHIFT (0x00000003u) #define CSL_SRIO_LSU_ICCR_ICC3_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_LSU_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_LSU_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_LSU_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_LSU_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_LSU_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_LSU_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICCR_RESETVAL (0x00000000u) /* ERR_RST_EVNT_ICSR */ #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS16_MASK (0x00010000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS16_SHIFT (0x00000010u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS16_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS11_MASK (0x00000800u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS11_SHIFT (0x0000000Bu) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS11_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS10_MASK (0x00000400u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS10_SHIFT (0x0000000Au) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS10_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS9_MASK (0x00000200u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS9_SHIFT (0x00000009u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS9_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS8_MASK (0x00000100u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS8_SHIFT (0x00000008u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS8_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS2_MASK (0x00000004u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS2_SHIFT (0x00000002u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS2_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS1_MASK (0x00000002u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS1_SHIFT (0x00000001u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS1_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS0_MASK (0x00000001u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS0_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_ICS0_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICSR_RESETVAL (0x00000000u) /* ERR_RST_EVNT_ICCR */ #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC16_MASK (0x00010000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC16_SHIFT (0x00000010u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC16_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC11_MASK (0x00000800u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC11_SHIFT (0x0000000Bu) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC11_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC10_MASK (0x00000400u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC10_SHIFT (0x0000000Au) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC10_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC9_MASK (0x00000200u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC9_SHIFT (0x00000009u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC9_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC8_MASK (0x00000100u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC8_SHIFT (0x00000008u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC8_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC2_MASK (0x00000004u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC2_SHIFT (0x00000002u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC2_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC1_MASK (0x00000002u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC1_SHIFT (0x00000001u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC1_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC0_MASK (0x00000001u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC0_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_ICC0_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICCR_RESETVAL (0x00000000u) /* DOORBELL_ICRR */ #define CSL_SRIO_DOORBELL_ICRR_ICR7_MASK (0xF0000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_DOORBELL_ICRR_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR6_MASK (0x0F000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_DOORBELL_ICRR_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR5_MASK (0x00F00000u) #define CSL_SRIO_DOORBELL_ICRR_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_DOORBELL_ICRR_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR4_MASK (0x000F0000u) #define CSL_SRIO_DOORBELL_ICRR_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_DOORBELL_ICRR_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR3_MASK (0x0000F000u) #define CSL_SRIO_DOORBELL_ICRR_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_DOORBELL_ICRR_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_DOORBELL_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_DOORBELL_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_DOORBELL_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_DOORBELL_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_DOORBELL_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR_RESETVAL (0x00000000u) /* DOORBELL_ICRR2 */ #define CSL_SRIO_DOORBELL_ICRR2_ICR7_MASK (0xF0000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_DOORBELL_ICRR2_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR6_MASK (0x0F000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_DOORBELL_ICRR2_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR5_MASK (0x00F00000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_DOORBELL_ICRR2_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR4_MASK (0x000F0000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_DOORBELL_ICRR2_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR3_MASK (0x0000F000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_DOORBELL_ICRR2_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR2_MASK (0x00000F00u) #define CSL_SRIO_DOORBELL_ICRR2_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_DOORBELL_ICRR2_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR1_MASK (0x000000F0u) #define CSL_SRIO_DOORBELL_ICRR2_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_DOORBELL_ICRR2_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_DOORBELL_ICRR2_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_DOORBELL_ICRR2_RESETVAL (0x00000000u) /* RX_CPPI_ICRR */ #define CSL_SRIO_RX_CPPI_ICRR_ICR7_MASK (0xF0000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_RX_CPPI_ICRR_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR6_MASK (0x0F000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_RX_CPPI_ICRR_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR5_MASK (0x00F00000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_RX_CPPI_ICRR_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR4_MASK (0x000F0000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_RX_CPPI_ICRR_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR3_MASK (0x0000F000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_ICRR_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_RX_CPPI_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_RX_CPPI_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_RX_CPPI_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR_RESETVAL (0x00000000u) /* RX_CPPI_ICRR2 */ #define CSL_SRIO_RX_CPPI_ICRR2_ICR7_MASK (0xF0000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_RX_CPPI_ICRR2_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR6_MASK (0x0F000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR5_MASK (0x00F00000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR4_MASK (0x000F0000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR3_MASK (0x0000F000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_ICRR2_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR2_MASK (0x00000F00u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR1_MASK (0x000000F0u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_RX_CPPI_ICRR2_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_ICRR2_RESETVAL (0x00000000u) /* TX_CPPI_ICRR */ #define CSL_SRIO_TX_CPPI_ICRR_ICR7_MASK (0xF0000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_CPPI_ICRR_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR6_MASK (0x0F000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_TX_CPPI_ICRR_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR5_MASK (0x00F00000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_TX_CPPI_ICRR_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR4_MASK (0x000F0000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_TX_CPPI_ICRR_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR3_MASK (0x0000F000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_ICRR_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_TX_CPPI_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_TX_CPPI_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_TX_CPPI_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR_RESETVAL (0x00000000u) /* TX_CPPI_ICRR2 */ #define CSL_SRIO_TX_CPPI_ICRR2_ICR7_MASK (0xF0000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_CPPI_ICRR2_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR6_MASK (0x0F000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR5_MASK (0x00F00000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR4_MASK (0x000F0000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR3_MASK (0x0000F000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_ICRR2_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR2_MASK (0x00000F00u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR1_MASK (0x000000F0u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_TX_CPPI_ICRR2_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_TX_CPPI_ICRR2_RESETVAL (0x00000000u) /* LSU_ICRR */ #define CSL_SRIO_LSU_ICRR_ICR7_MASK (0xF0000000u) #define CSL_SRIO_LSU_ICRR_ICR7_SHIFT (0x0000001Cu) #define CSL_SRIO_LSU_ICRR_ICR7_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR6_MASK (0x0F000000u) #define CSL_SRIO_LSU_ICRR_ICR6_SHIFT (0x00000018u) #define CSL_SRIO_LSU_ICRR_ICR6_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR5_MASK (0x00F00000u) #define CSL_SRIO_LSU_ICRR_ICR5_SHIFT (0x00000014u) #define CSL_SRIO_LSU_ICRR_ICR5_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR4_MASK (0x000F0000u) #define CSL_SRIO_LSU_ICRR_ICR4_SHIFT (0x00000010u) #define CSL_SRIO_LSU_ICRR_ICR4_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR3_MASK (0x0000F000u) #define CSL_SRIO_LSU_ICRR_ICR3_SHIFT (0x0000000Cu) #define CSL_SRIO_LSU_ICRR_ICR3_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_LSU_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_LSU_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_LSU_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_LSU_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_LSU_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_LSU_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_ICRR_RESETVAL (0x00000000u) /* ERR_RST_EVNT_ICRR */ #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR2_MASK (0x00000F00u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR2_SHIFT (0x00000008u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR2_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR1_MASK (0x000000F0u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR1_SHIFT (0x00000004u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR1_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR0_MASK (0x0000000Fu) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR0_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_ICR0_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR_RESETVAL (0x00000000u) /* ERR_RST_EVNT_ICRR2 */ #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR11_MASK (0x0000F000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR11_SHIFT (0x0000000Cu) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR11_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR10_MASK (0x00000F00u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR10_SHIFT (0x00000008u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR10_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR9_MASK (0x000000F0u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR9_SHIFT (0x00000004u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR9_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR8_MASK (0x0000000Fu) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR8_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_ICR8_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR2_RESETVAL (0x00000000u) /* ERR_RST_EVNT_ICRR3 */ #define CSL_SRIO_ERR_RST_EVNT_ICRR3_ICR16_MASK (0x0000000Fu) #define CSL_SRIO_ERR_RST_EVNT_ICRR3_ICR16_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR3_ICR16_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RST_EVNT_ICRR3_RESETVAL (0x00000000u) /* INTDST_DECODE */ #define CSL_SRIO_INTDST_DECODE_ISDR31_MASK (0x80000000u) #define CSL_SRIO_INTDST_DECODE_ISDR31_SHIFT (0x0000001Fu) #define CSL_SRIO_INTDST_DECODE_ISDR31_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR30_MASK (0x40000000u) #define CSL_SRIO_INTDST_DECODE_ISDR30_SHIFT (0x0000001Eu) #define CSL_SRIO_INTDST_DECODE_ISDR30_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR29_MASK (0x20000000u) #define CSL_SRIO_INTDST_DECODE_ISDR29_SHIFT (0x0000001Du) #define CSL_SRIO_INTDST_DECODE_ISDR29_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR28_MASK (0x10000000u) #define CSL_SRIO_INTDST_DECODE_ISDR28_SHIFT (0x0000001Cu) #define CSL_SRIO_INTDST_DECODE_ISDR28_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR27_MASK (0x08000000u) #define CSL_SRIO_INTDST_DECODE_ISDR27_SHIFT (0x0000001Bu) #define CSL_SRIO_INTDST_DECODE_ISDR27_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR26_MASK (0x04000000u) #define CSL_SRIO_INTDST_DECODE_ISDR26_SHIFT (0x0000001Au) #define CSL_SRIO_INTDST_DECODE_ISDR26_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR25_MASK (0x02000000u) #define CSL_SRIO_INTDST_DECODE_ISDR25_SHIFT (0x00000019u) #define CSL_SRIO_INTDST_DECODE_ISDR25_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR24_MASK (0x01000000u) #define CSL_SRIO_INTDST_DECODE_ISDR24_SHIFT (0x00000018u) #define CSL_SRIO_INTDST_DECODE_ISDR24_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR23_MASK (0x00800000u) #define CSL_SRIO_INTDST_DECODE_ISDR23_SHIFT (0x00000017u) #define CSL_SRIO_INTDST_DECODE_ISDR23_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR22_MASK (0x00400000u) #define CSL_SRIO_INTDST_DECODE_ISDR22_SHIFT (0x00000016u) #define CSL_SRIO_INTDST_DECODE_ISDR22_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR21_MASK (0x00200000u) #define CSL_SRIO_INTDST_DECODE_ISDR21_SHIFT (0x00000015u) #define CSL_SRIO_INTDST_DECODE_ISDR21_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR20_MASK (0x00100000u) #define CSL_SRIO_INTDST_DECODE_ISDR20_SHIFT (0x00000014u) #define CSL_SRIO_INTDST_DECODE_ISDR20_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR19_MASK (0x00080000u) #define CSL_SRIO_INTDST_DECODE_ISDR19_SHIFT (0x00000013u) #define CSL_SRIO_INTDST_DECODE_ISDR19_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR18_MASK (0x00040000u) #define CSL_SRIO_INTDST_DECODE_ISDR18_SHIFT (0x00000012u) #define CSL_SRIO_INTDST_DECODE_ISDR18_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR17_MASK (0x00020000u) #define CSL_SRIO_INTDST_DECODE_ISDR17_SHIFT (0x00000011u) #define CSL_SRIO_INTDST_DECODE_ISDR17_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR16_MASK (0x00010000u) #define CSL_SRIO_INTDST_DECODE_ISDR16_SHIFT (0x00000010u) #define CSL_SRIO_INTDST_DECODE_ISDR16_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR15_MASK (0x00008000u) #define CSL_SRIO_INTDST_DECODE_ISDR15_SHIFT (0x0000000Fu) #define CSL_SRIO_INTDST_DECODE_ISDR15_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR14_MASK (0x00004000u) #define CSL_SRIO_INTDST_DECODE_ISDR14_SHIFT (0x0000000Eu) #define CSL_SRIO_INTDST_DECODE_ISDR14_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR13_MASK (0x00002000u) #define CSL_SRIO_INTDST_DECODE_ISDR13_SHIFT (0x0000000Du) #define CSL_SRIO_INTDST_DECODE_ISDR13_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR12_MASK (0x00001000u) #define CSL_SRIO_INTDST_DECODE_ISDR12_SHIFT (0x0000000Cu) #define CSL_SRIO_INTDST_DECODE_ISDR12_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR11_MASK (0x00000800u) #define CSL_SRIO_INTDST_DECODE_ISDR11_SHIFT (0x0000000Bu) #define CSL_SRIO_INTDST_DECODE_ISDR11_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR10_MASK (0x00000400u) #define CSL_SRIO_INTDST_DECODE_ISDR10_SHIFT (0x0000000Au) #define CSL_SRIO_INTDST_DECODE_ISDR10_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR9_MASK (0x00000200u) #define CSL_SRIO_INTDST_DECODE_ISDR9_SHIFT (0x00000009u) #define CSL_SRIO_INTDST_DECODE_ISDR9_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR8_MASK (0x00000100u) #define CSL_SRIO_INTDST_DECODE_ISDR8_SHIFT (0x00000008u) #define CSL_SRIO_INTDST_DECODE_ISDR8_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR7_MASK (0x00000080u) #define CSL_SRIO_INTDST_DECODE_ISDR7_SHIFT (0x00000007u) #define CSL_SRIO_INTDST_DECODE_ISDR7_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR6_MASK (0x00000040u) #define CSL_SRIO_INTDST_DECODE_ISDR6_SHIFT (0x00000006u) #define CSL_SRIO_INTDST_DECODE_ISDR6_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR5_MASK (0x00000020u) #define CSL_SRIO_INTDST_DECODE_ISDR5_SHIFT (0x00000005u) #define CSL_SRIO_INTDST_DECODE_ISDR5_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR4_MASK (0x00000010u) #define CSL_SRIO_INTDST_DECODE_ISDR4_SHIFT (0x00000004u) #define CSL_SRIO_INTDST_DECODE_ISDR4_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR3_MASK (0x00000008u) #define CSL_SRIO_INTDST_DECODE_ISDR3_SHIFT (0x00000003u) #define CSL_SRIO_INTDST_DECODE_ISDR3_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR2_MASK (0x00000004u) #define CSL_SRIO_INTDST_DECODE_ISDR2_SHIFT (0x00000002u) #define CSL_SRIO_INTDST_DECODE_ISDR2_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR1_MASK (0x00000002u) #define CSL_SRIO_INTDST_DECODE_ISDR1_SHIFT (0x00000001u) #define CSL_SRIO_INTDST_DECODE_ISDR1_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR0_MASK (0x00000001u) #define CSL_SRIO_INTDST_DECODE_ISDR0_SHIFT (0x00000000u) #define CSL_SRIO_INTDST_DECODE_ISDR0_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_DECODE_RESETVAL (0x00000000u) /* INTDST_RATE_CNTL */ #define CSL_SRIO_INTDST_RATE_CNTL_COUNT_DOWN_VALUE_MASK (0xFFFFFFFFu) #define CSL_SRIO_INTDST_RATE_CNTL_COUNT_DOWN_VALUE_SHIFT (0x00000000u) #define CSL_SRIO_INTDST_RATE_CNTL_COUNT_DOWN_VALUE_RESETVAL (0x00000000u) #define CSL_SRIO_INTDST_RATE_CNTL_RESETVAL (0x00000000u) /* LSU_REG0 */ #define CSL_SRIO_LSU_REG0_ADDRESS_MSB_MASK (0xFFFFFFFFu) #define CSL_SRIO_LSU_REG0_ADDRESS_MSB_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG0_ADDRESS_MSB_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG0_RESETVAL (0x00000000u) /* LSU_REG1 */ #define CSL_SRIO_LSU_REG1_ADDRESS_LSB_CONFIG_OFFSET_MASK (0xFFFFFFFFu) #define CSL_SRIO_LSU_REG1_ADDRESS_LSB_CONFIG_OFFSET_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG1_ADDRESS_LSB_CONFIG_OFFSET_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG1_RESETVAL (0x00000000u) /* LSU_REG2 */ #define CSL_SRIO_LSU_REG2_DSP_ADDRESS_MASK (0xFFFFFFFFu) #define CSL_SRIO_LSU_REG2_DSP_ADDRESS_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG2_DSP_ADDRESS_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG2_RESETVAL (0x00000000u) /* LSU_REG3 */ #define CSL_SRIO_LSU_REG3_BYTE_COUNT_MASK (0x00000FFFu) #define CSL_SRIO_LSU_REG3_BYTE_COUNT_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG3_BYTE_COUNT_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG3_RESETVAL (0x00000000u) /* LSU_REG4 */ #define CSL_SRIO_LSU_REG4_OUTPORTID_MASK (0xC0000000u) #define CSL_SRIO_LSU_REG4_OUTPORTID_SHIFT (0x0000001Eu) #define CSL_SRIO_LSU_REG4_OUTPORTID_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG4_PRIORITY_MASK (0x30000000u) #define CSL_SRIO_LSU_REG4_PRIORITY_SHIFT (0x0000001Cu) #define CSL_SRIO_LSU_REG4_PRIORITY_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG4_XAMBS_MASK (0x0C000000u) #define CSL_SRIO_LSU_REG4_XAMBS_SHIFT (0x0000001Au) #define CSL_SRIO_LSU_REG4_XAMBS_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG4_ID_SIZE_MASK (0x03000000u) #define CSL_SRIO_LSU_REG4_ID_SIZE_SHIFT (0x00000018u) #define CSL_SRIO_LSU_REG4_ID_SIZE_RESETVAL (0x00000000u) /*----ID_SIZE Tokens----*/ #define CSL_SRIO_LSU_REG4_ID_SIZE_8BIT (0x00000000u) #define CSL_SRIO_LSU_REG4_ID_SIZE_16BIT (0x00000001u) #define CSL_SRIO_LSU_REG4_DESTID_MASK (0x00FFFF00u) #define CSL_SRIO_LSU_REG4_DESTID_SHIFT (0x00000008u) #define CSL_SRIO_LSU_REG4_DESTID_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_MASK (0x00000001u) #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_RESETVAL (0x00000000u) /*----INTERRUPT_REQ Tokens----*/ #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_DISABLE (0x00000000u) #define CSL_SRIO_LSU_REG4_INTERRUPT_REQ_ENABLE (0x00000001u) #define CSL_SRIO_LSU_REG4_RESETVAL (0x00000000u) /* LSU_REG5 */ #define CSL_SRIO_LSU_REG5_DRBLL_INFO_MASK (0xFFFF0000u) #define CSL_SRIO_LSU_REG5_DRBLL_INFO_SHIFT (0x00000010u) #define CSL_SRIO_LSU_REG5_DRBLL_INFO_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG5_HOP_COUNT_MASK (0x0000FF00u) #define CSL_SRIO_LSU_REG5_HOP_COUNT_SHIFT (0x00000008u) #define CSL_SRIO_LSU_REG5_HOP_COUNT_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG5_PACKET_TYPE_MASK (0x000000FFu) #define CSL_SRIO_LSU_REG5_PACKET_TYPE_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG5_PACKET_TYPE_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG5_RESETVAL (0x00000000u) /* LSU_REG6 */ #define CSL_SRIO_LSU_REG6_COMPLETION_CODE_MASK (0x0000001Eu) #define CSL_SRIO_LSU_REG6_COMPLETION_CODE_SHIFT (0x00000001u) #define CSL_SRIO_LSU_REG6_COMPLETION_CODE_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG6_BSY_MASK (0x00000001u) #define CSL_SRIO_LSU_REG6_BSY_SHIFT (0x00000000u) #define CSL_SRIO_LSU_REG6_BSY_RESETVAL (0x00000000u) #define CSL_SRIO_LSU_REG6_RESETVAL (0x00000000u) /* LSU_FLOW_MASKS */ #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK15_MASK (0x00008000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK15_SHIFT (0x0000000Fu) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK15_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK14_MASK (0x00004000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK14_SHIFT (0x0000000Eu) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK14_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK13_MASK (0x00002000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK13_SHIFT (0x0000000Du) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK13_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK12_MASK (0x00001000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK12_SHIFT (0x0000000Cu) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK12_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK11_MASK (0x00000800u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK11_SHIFT (0x0000000Bu) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK11_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK10_MASK (0x00000400u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK10_SHIFT (0x0000000Au) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK10_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK9_MASK (0x00000200u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK9_SHIFT (0x00000009u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK9_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK8_MASK (0x00000100u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK8_SHIFT (0x00000008u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK8_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK7_MASK (0x00000080u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK7_SHIFT (0x00000007u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK7_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK6_MASK (0x00000040u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK6_SHIFT (0x00000006u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK6_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK5_MASK (0x00000020u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK5_SHIFT (0x00000005u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK5_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK4_MASK (0x00000010u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK4_SHIFT (0x00000004u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK4_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK3_MASK (0x00000008u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK3_SHIFT (0x00000003u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK3_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK2_MASK (0x00000004u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK2_SHIFT (0x00000002u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK2_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK1_MASK (0x00000002u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK1_SHIFT (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK1_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK0_MASK (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK0_SHIFT (0x00000000u) #define CSL_SRIO_LSU_FLOW_MASKS_FLOW_MASK0_RESETVAL (0x00000001u) #define CSL_SRIO_LSU_FLOW_MASKS_RESETVAL (0x0000FFFFu) /* QUEUE_TXDMA_HDP */ #define CSL_SRIO_QUEUE_TXDMA_HDP_TX_HDP_MASK (0xFFFFFFFFu) #define CSL_SRIO_QUEUE_TXDMA_HDP_TX_HDP_SHIFT (0x00000000u) #define CSL_SRIO_QUEUE_TXDMA_HDP_TX_HDP_RESETVAL (0x00000000u) #define CSL_SRIO_QUEUE_TXDMA_HDP_RESETVAL (0x00000000u) /* QUEUE_TXDMA_CP */ #define CSL_SRIO_QUEUE_TXDMA_CP_TX_CP_MASK (0xFFFFFFFFu) #define CSL_SRIO_QUEUE_TXDMA_CP_TX_CP_SHIFT (0x00000000u) #define CSL_SRIO_QUEUE_TXDMA_CP_TX_CP_RESETVAL (0x00000000u) #define CSL_SRIO_QUEUE_TXDMA_CP_RESETVAL (0x00000000u) /* QUEUE_RXDMA_HDP */ #define CSL_SRIO_QUEUE_RXDMA_HDP_RX_HDP_MASK (0xFFFFFFFFu) #define CSL_SRIO_QUEUE_RXDMA_HDP_RX_HDP_SHIFT (0x00000000u) #define CSL_SRIO_QUEUE_RXDMA_HDP_RX_HDP_RESETVAL (0x00000000u) #define CSL_SRIO_QUEUE_RXDMA_HDP_RESETVAL (0x00000000u) /* QUEUE_RXDMA_CP */ #define CSL_SRIO_QUEUE_RXDMA_CP_RX_CP_MASK (0xFFFFFFFFu) #define CSL_SRIO_QUEUE_RXDMA_CP_RX_CP_SHIFT (0x00000000u) #define CSL_SRIO_QUEUE_RXDMA_CP_RX_CP_RESETVAL (0x00000000u) #define CSL_SRIO_QUEUE_RXDMA_CP_RESETVAL (0x00000000u) /* TX_QUEUE_TEAR_DOWN */ #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_MASK (0x00008000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_SHIFT (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_MASK (0x00004000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_SHIFT (0x0000000Eu) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_MASK (0x00002000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_SHIFT (0x0000000Du) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_MASK (0x00001000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_MASK (0x00000800u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_SHIFT (0x0000000Bu) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_MASK (0x00000400u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_SHIFT (0x0000000Au) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_MASK (0x00000200u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_SHIFT (0x00000009u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_MASK (0x00000100u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_MASK (0x00000080u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_SHIFT (0x00000007u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_MASK (0x00000040u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_SHIFT (0x00000006u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_MASK (0x00000020u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_SHIFT (0x00000005u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_MASK (0x00000010u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_MASK (0x00000008u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_SHIFT (0x00000003u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_MASK (0x00000004u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_SHIFT (0x00000002u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_MASK (0x00000002u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_SHIFT (0x00000001u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_MASK (0x00000001u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_RESETVAL (0x00000000u) /*----QUEUE Tokens----*/ #define CSL_SRIO_QUEUE_TEAR_DOWN (0x00000001u) #define CSL_SRIO_TX_QUEUE_TEAR_DOWN_RESETVAL (0x00000000u) /* TX_CPPI_FLOW_MASKS */ #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK15_MASK (0x80000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK15_SHIFT (0x0000001Fu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK15_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK14_MASK (0x40000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK14_SHIFT (0x0000001Eu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK14_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK13_MASK (0x20000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK13_SHIFT (0x0000001Du) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK13_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK12_MASK (0x10000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK12_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK12_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK11_MASK (0x08000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK11_SHIFT (0x0000001Bu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK11_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK10_MASK (0x04000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK10_SHIFT (0x0000001Au) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK10_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK9_MASK (0x02000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK9_SHIFT (0x00000019u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK9_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK8_MASK (0x01000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK8_SHIFT (0x00000018u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK8_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK7_MASK (0x00800000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK7_SHIFT (0x00000017u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK7_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK6_MASK (0x00400000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK6_SHIFT (0x00000016u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK6_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK5_MASK (0x00200000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK5_SHIFT (0x00000015u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK5_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK4_MASK (0x00100000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK4_SHIFT (0x00000014u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK4_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK3_MASK (0x00080000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK3_SHIFT (0x00000013u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK3_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK2_MASK (0x00040000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK2_SHIFT (0x00000012u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK2_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK1_MASK (0x00020000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK1_SHIFT (0x00000011u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK1_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK0_MASK (0x00010000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK0_SHIFT (0x000000010u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK0_RESETVAL (0x00000001u) /*----QUEUE1_FLOW_MASK Tokens----*/ #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK_DISABLE (0x00000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE1_FLOW_MASK_ENABLE (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK15_MASK (0x00008000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK15_SHIFT (0x0000000Fu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK15_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK14_MASK (0x00004000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK14_SHIFT (0x0000000Eu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK14_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK13_MASK (0x00002000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK13_SHIFT (0x0000000Du) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK13_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK12_MASK (0x00001000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK12_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK12_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK11_MASK (0x00000800u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK11_SHIFT (0x0000000Bu) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK11_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK10_MASK (0x00000400u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK10_SHIFT (0x0000000Au) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK10_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK9_MASK (0x00000200u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK9_SHIFT (0x00000009u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK9_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK8_MASK (0x00000100u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK8_SHIFT (0x00000008u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK8_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK7_MASK (0x00000080u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK7_SHIFT (0x00000007u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK7_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK6_MASK (0x00000040u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK6_SHIFT (0x00000006u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK6_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK5_MASK (0x00000020u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK5_SHIFT (0x00000005u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK5_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK4_MASK (0x00000010u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK4_SHIFT (0x00000004u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK4_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK3_MASK (0x00000008u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK3_SHIFT (0x00000003u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK3_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK2_MASK (0x00000004u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK2_SHIFT (0x00000002u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK2_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK1_MASK (0x00000002u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK1_SHIFT (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK1_RESETVAL (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK0_MASK (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK0_SHIFT (0x00000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK0_RESETVAL (0x00000001u) /*----QUEUE0_FLOW_MASK Tokens----*/ #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK_DISABLE (0x00000000u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_QUEUE0_FLOW_MASK_ENABLE (0x00000001u) #define CSL_SRIO_TX_CPPI_FLOW_MASKS_RESETVAL (0xFFFFFFFFu) /* RX_QUEUE_TEAR_DOWN */ #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_MASK (0x00008000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_SHIFT (0x0000000Fu) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE15_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_MASK (0x00004000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_SHIFT (0x0000000Eu) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE14_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_MASK (0x00002000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_SHIFT (0x0000000Du) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE13_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_MASK (0x00001000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE12_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_MASK (0x00000800u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_SHIFT (0x0000000Bu) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE11_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_MASK (0x00000400u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_SHIFT (0x0000000Au) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE10_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_MASK (0x00000200u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_SHIFT (0x00000009u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE9_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_MASK (0x00000100u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_SHIFT (0x00000008u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE8_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_MASK (0x00000080u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_SHIFT (0x00000007u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE7_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_MASK (0x00000040u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_SHIFT (0x00000006u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE6_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_MASK (0x00000020u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_SHIFT (0x00000005u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE5_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_MASK (0x00000010u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_SHIFT (0x00000004u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE4_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_MASK (0x00000008u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_SHIFT (0x00000003u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE3_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_MASK (0x00000004u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_SHIFT (0x00000002u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE2_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_MASK (0x00000002u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_SHIFT (0x00000001u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE1_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_MASK (0x00000001u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_SHIFT (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_QUEUE0_TEAR_DWN_RESETVAL (0x00000000u) #define CSL_SRIO_RX_QUEUE_TEAR_DOWN_RESETVAL (0x00000000u) /* RX_CPPI_CNTL */ #define CSL_SRIO_RX_CPPI_CNTL_QUEUE15_IN_ORDER_MASK (0x00008000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE15_IN_ORDER_SHIFT (0x0000000Fu) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE15_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE14_IN_ORDER_MASK (0x00004000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE14_IN_ORDER_SHIFT (0x0000000Eu) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE14_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE13_IN_ORDER_MASK (0x00002000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE13_IN_ORDER_SHIFT (0x0000000Du) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE13_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE12_IN_ORDER_MASK (0x00001000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE12_IN_ORDER_SHIFT (0x0000000Cu) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE12_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE11_IN_ORDER_MASK (0x00000800u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE11_IN_ORDER_SHIFT (0x0000000Bu) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE11_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE10_IN_ORDER_MASK (0x00000400u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE10_IN_ORDER_SHIFT (0x0000000Au) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE10_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE9_IN_ORDER_MASK (0x00000200u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE9_IN_ORDER_SHIFT (0x00000009u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE9_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE8_IN_ORDER_MASK (0x00000100u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE8_IN_ORDER_SHIFT (0x00000008u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE8_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE7_IN_ORDER_MASK (0x00000080u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE7_IN_ORDER_SHIFT (0x00000007u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE7_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE6_IN_ORDER_MASK (0x00000040u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE6_IN_ORDER_SHIFT (0x00000006u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE6_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE5_IN_ORDER_MASK (0x00000020u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE5_IN_ORDER_SHIFT (0x00000005u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE5_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE4_IN_ORDER_MASK (0x00000010u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE4_IN_ORDER_SHIFT (0x00000004u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE4_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE3_IN_ORDER_MASK (0x00000008u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE3_IN_ORDER_SHIFT (0x00000003u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE3_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE2_IN_ORDER_MASK (0x00000004u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE2_IN_ORDER_SHIFT (0x00000002u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE2_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE1_IN_ORDER_MASK (0x00000002u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE1_IN_ORDER_SHIFT (0x00000001u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE1_IN_ORDER_RESETVAL (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE0_IN_ORDER_MASK (0x00000001u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE0_IN_ORDER_SHIFT (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE0_IN_ORDER_RESETVAL (0x00000000u) /*----QUEUE Tokens----*/ #define CSL_SRIO_RX_CPPI_CNTL_QUEUE_IN_ORDER_DISABLE (0x00000000u) #define CSL_SRIO_RX_CPPI_CNTL_QUEUE_IN_ORDER_ENABLE (0x00000001u) #define CSL_SRIO_RX_CPPI_CNTL_RESETVAL (0x00000000u) /* TX_QUEUE_CNTL0 */ #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_NUM_MSGS_MASK (0xF0000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_NUM_MSGS_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_QUEUE_PTR_MASK (0x0F000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_QUEUE_PTR_SHIFT (0x00000018u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP3_QUEUE_PTR_RESETVAL (0x00000003u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_NUM_MSGS_MASK (0x00F00000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_NUM_MSGS_SHIFT (0x00000014u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_QUEUE_PTR_MASK (0x000F0000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_QUEUE_PTR_SHIFT (0x00000010u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP2_QUEUE_PTR_RESETVAL (0x00000002u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_NUM_MSGS_MASK (0x0000F000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_NUM_MSGS_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_QUEUE_PTR_MASK (0x00000F00u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_QUEUE_PTR_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP1_QUEUE_PTR_RESETVAL (0x00000001u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_NUM_MSGS_MASK (0x000000F0u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_NUM_MSGS_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_QUEUE_PTR_MASK (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_QUEUE_PTR_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_TX_QUEUE_MAP0_QUEUE_PTR_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL0_RESETVAL (0x03020100u) /* TX_QUEUE_CNTL1 */ #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_NUM_MSGS_MASK (0xF0000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_NUM_MSGS_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_QUEUE_PTR_MASK (0x0F000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_QUEUE_PTR_SHIFT (0x00000018u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP7_QUEUE_PTR_RESETVAL (0x00000007u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_NUM_MSGS_MASK (0x00F00000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_NUM_MSGS_SHIFT (0x00000014u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_QUEUE_PTR_MASK (0x000F0000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_QUEUE_PTR_SHIFT (0x00000010u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP6_QUEUE_PTR_RESETVAL (0x00000006u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_NUM_MSGS_MASK (0x0000F000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_NUM_MSGS_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_QUEUE_PTR_MASK (0x00000F00u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_QUEUE_PTR_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP5_QUEUE_PTR_RESETVAL (0x00000005u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_NUM_MSGS_MASK (0x000000F0u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_NUM_MSGS_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_QUEUE_PTR_MASK (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_QUEUE_PTR_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL1_TX_QUEUE_MAP4_QUEUE_PTR_RESETVAL (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL1_RESETVAL (0x07060504u) /* TX_QUEUE_CNTL2 */ #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_NUM_MSGS_MASK (0xF0000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_NUM_MSGS_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_QUEUE_PTR_MASK (0x0F000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_QUEUE_PTR_SHIFT (0x00000018u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP11_QUEUE_PTR_RESETVAL (0x0000000Bu) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_NUM_MSGS_MASK (0x00F00000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_NUM_MSGS_SHIFT (0x00000014u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_QUEUE_PTR_MASK (0x000F0000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_QUEUE_PTR_SHIFT (0x00000010u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP10_QUEUE_PTR_RESETVAL (0x0000000Au) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_NUM_MSGS_MASK (0x0000F000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_NUM_MSGS_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_QUEUE_PTR_MASK (0x00000F00u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_QUEUE_PTR_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP9_QUEUE_PTR_RESETVAL (0x00000009u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_NUM_MSGS_MASK (0x000000F0u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_NUM_MSGS_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_QUEUE_PTR_MASK (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_QUEUE_PTR_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL2_TX_QUEUE_MAP8_QUEUE_PTR_RESETVAL (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL2_RESETVAL (0x0B0A0908u) /* TX_QUEUE_CNTL3 */ #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_NUM_MSGS_MASK (0xF0000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_NUM_MSGS_SHIFT (0x0000001Cu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_QUEUE_PTR_MASK (0x0F000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_QUEUE_PTR_SHIFT (0x00000018u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP15_QUEUE_PTR_RESETVAL (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_NUM_MSGS_MASK (0x00F00000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_NUM_MSGS_SHIFT (0x00000014u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_QUEUE_PTR_MASK (0x000F0000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_QUEUE_PTR_SHIFT (0x00000010u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP14_QUEUE_PTR_RESETVAL (0x0000000Eu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_NUM_MSGS_MASK (0x0000F000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_NUM_MSGS_SHIFT (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_QUEUE_PTR_MASK (0x00000F00u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_QUEUE_PTR_SHIFT (0x00000008u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP13_QUEUE_PTR_RESETVAL (0x0000000Du) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_NUM_MSGS_MASK (0x000000F0u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_NUM_MSGS_SHIFT (0x00000004u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_NUM_MSGS_RESETVAL (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_QUEUE_PTR_MASK (0x0000000Fu) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_QUEUE_PTR_SHIFT (0x00000000u) #define CSL_SRIO_TX_QUEUE_CNTL3_TX_QUEUE_MAP12_QUEUE_PTR_RESETVAL (0x0000000Cu) #define CSL_SRIO_TX_QUEUE_CNTL3_RESETVAL (0x0F0E0D0Cu) /* RXU_MAP_L */ #define CSL_SRIO_RXU_MAP_L_LETTER_MASK_MASK (0xC0000000u) #define CSL_SRIO_RXU_MAP_L_LETTER_MASK_SHIFT (0x0000001Eu) #define CSL_SRIO_RXU_MAP_L_LETTER_MASK_RESETVAL (0x00000003u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_MASK_MASK (0x3F000000u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_MASK_SHIFT (0x00000018u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_MASK_RESETVAL (0x0000003Fu) #define CSL_SRIO_RXU_MAP_L_LETTER_MASK (0x00C00000u) #define CSL_SRIO_RXU_MAP_L_LETTER_SHIFT (0x00000016u) #define CSL_SRIO_RXU_MAP_L_LETTER_RESETVAL (0x00000000u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_MASK (0x003F0000u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_SHIFT (0x00000010u) #define CSL_SRIO_RXU_MAP_L_MAILBOX_RESETVAL (0x00000000u) #define CSL_SRIO_RXU_MAP_L_SOURCEID_MASK (0x0000FFFFu) #define CSL_SRIO_RXU_MAP_L_SOURCEID_SHIFT (0x00000000u) #define CSL_SRIO_RXU_MAP_L_SOURCEID_RESETVAL (0x00000000u) #define CSL_SRIO_RXU_MAP_L_RESETVAL (0xFF000000u) /* RXU_MAP_H */ #define CSL_SRIO_RXU_MAP_H_TT_MASK (0x00000300u) #define CSL_SRIO_RXU_MAP_H_TT_SHIFT (0x00000008u) #define CSL_SRIO_RXU_MAP_H_TT_RESETVAL (0x00000001u) /*----TT Tokens----*/ #define CSL_SRIO_RXU_MAP_H_TT_MATCH_8BIT_SRCID (0x00000000u) #define CSL_SRIO_RXU_MAP_H_TT_MATCH_16BIT_SRCID (0x00000001u) #define CSL_SRIO_RXU_MAP_H_QUEUE_ID_MASK (0x0000003Cu) #define CSL_SRIO_RXU_MAP_H_QUEUE_ID_SHIFT (0x00000002u) #define CSL_SRIO_RXU_MAP_H_QUEUE_ID_RESETVAL (0x00000000u) #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_MASK (0x00000002u) #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_SHIFT (0x00000001u) #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_RESETVAL (0x00000000u) /*----PROMISCUOUS Tokens----*/ #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_DISABLE (0x00000000u) #define CSL_SRIO_RXU_MAP_H_PROMISCUOUS_ENABLE (0x00000001u) #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_MASK (0x00000001u) #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_SHIFT (0x00000000u) #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_RESETVAL (0x00000000u) /*----SEGMENT_MAPPING Tokens----*/ #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_SINGLE_SEGMENT (0x00000000u) #define CSL_SRIO_RXU_MAP_H_SEGMENT_MAPPING_MULTI_SEGMENT (0x00000001u) #define CSL_SRIO_RXU_MAP_H_RESETVAL (0x00000100u) /* FLOW_CNTL */ #define CSL_SRIO_FLOW_CNTL_TT_MASK (0x00030000u) #define CSL_SRIO_FLOW_CNTL_TT_SHIFT (0x00000010u) #define CSL_SRIO_FLOW_CNTL_TT_RESETVAL (0x00000001u) /*----TT Tokens----*/ #define CSL_SRIO_FLOW_CNTL_TT_8BIT_ID (0x00000000u) #define CSL_SRIO_FLOW_CNTL_TT_16BIT_ID (0x00000001u) #define CSL_SRIO_FLOW_CNTL_FLOW_CNTL_ID_MASK (0x0000FFFFu) #define CSL_SRIO_FLOW_CNTL_FLOW_CNTL_ID_SHIFT (0x00000000u) #define CSL_SRIO_FLOW_CNTL_FLOW_CNTL_ID_RESETVAL (0x00000000u) #define CSL_SRIO_FLOW_CNTL_RESETVAL (0x00010000u) /* DEV_ID */ #define CSL_SRIO_DEV_ID_DEVICEIDENTITY_MASK (0xFFFF0000u) #define CSL_SRIO_DEV_ID_DEVICEIDENTITY_SHIFT (0x00000010u) #define CSL_SRIO_DEV_ID_DEVICEIDENTITY_RESETVAL (0x00000000u) #define CSL_SRIO_DEV_ID_DEVICE_VENDORIDENTITY_MASK (0x0000FFFFu) #define CSL_SRIO_DEV_ID_DEVICE_VENDORIDENTITY_SHIFT (0x00000000u) #define CSL_SRIO_DEV_ID_DEVICE_VENDORIDENTITY_RESETVAL (0x00000030u) #define CSL_SRIO_DEV_ID_RESETVAL (0x00000030u) /* DEV_INFO */ #define CSL_SRIO_DEV_INFO_DEVICEREV_MASK (0xFFFFFFFFu) #define CSL_SRIO_DEV_INFO_DEVICEREV_SHIFT (0x00000000u) #define CSL_SRIO_DEV_INFO_DEVICEREV_RESETVAL (0x00000000u) #define CSL_SRIO_DEV_INFO_RESETVAL (0x00000000u) /* ASBLY_ID */ #define CSL_SRIO_ASBLY_ID_ASSY_IDENTITY_MASK (0xFFFF0000u) #define CSL_SRIO_ASBLY_ID_ASSY_IDENTITY_SHIFT (0x00000010u) #define CSL_SRIO_ASBLY_ID_ASSY_IDENTITY_RESETVAL (0x00000000u) #define CSL_SRIO_ASBLY_ID_ASSY_VENDORIDENTITY_MASK (0x0000FFFFu) #define CSL_SRIO_ASBLY_ID_ASSY_VENDORIDENTITY_SHIFT (0x00000000u) #define CSL_SRIO_ASBLY_ID_ASSY_VENDORIDENTITY_RESETVAL (0x00000030u) #define CSL_SRIO_ASBLY_ID_RESETVAL (0x00000030u) /* ASBLY_INFO */ #define CSL_SRIO_ASBLY_INFO_ASSYREV_MASK (0xFFFF0000u) #define CSL_SRIO_ASBLY_INFO_ASSYREV_SHIFT (0x00000010u) #define CSL_SRIO_ASBLY_INFO_ASSYREV_RESETVAL (0x00000000u) #define CSL_SRIO_ASBLY_INFO_EXTENDEDFEATURESPTR_MASK (0x0000FFFFu) #define CSL_SRIO_ASBLY_INFO_EXTENDEDFEATURESPTR_SHIFT (0x00000000u) #define CSL_SRIO_ASBLY_INFO_EXTENDEDFEATURESPTR_RESETVAL (0x00000100u) #define CSL_SRIO_ASBLY_INFO_RESETVAL (0x00000100u) /* PE_FEAT */ #define CSL_SRIO_PE_FEAT_BRIDGE_MASK (0x80000000u) #define CSL_SRIO_PE_FEAT_BRIDGE_SHIFT (0x0000001Fu) #define CSL_SRIO_PE_FEAT_BRIDGE_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_MEMORY_MASK (0x40000000u) #define CSL_SRIO_PE_FEAT_MEMORY_SHIFT (0x0000001Eu) #define CSL_SRIO_PE_FEAT_MEMORY_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_PROCESSOR_MASK (0x20000000u) #define CSL_SRIO_PE_FEAT_PROCESSOR_SHIFT (0x0000001Du) #define CSL_SRIO_PE_FEAT_PROCESSOR_RESETVAL (0x00000001u) #define CSL_SRIO_PE_FEAT_SWITCH_MASK (0x10000000u) #define CSL_SRIO_PE_FEAT_SWITCH_SHIFT (0x0000001Cu) #define CSL_SRIO_PE_FEAT_SWITCH_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_FLOW_CONTROL_SUPPORT_MASK (0x00000080u) #define CSL_SRIO_PE_FEAT_FLOW_CONTROL_SUPPORT_SHIFT (0x00000007u) #define CSL_SRIO_PE_FEAT_FLOW_CONTROL_SUPPORT_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_RETRANSMIT_SUPPRESS_MASK (0x00000040u) #define CSL_SRIO_PE_FEAT_RETRANSMIT_SUPPRESS_SHIFT (0x00000006u) #define CSL_SRIO_PE_FEAT_RETRANSMIT_SUPPRESS_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_CRF_SUPPORT_MASK (0x00000020u) #define CSL_SRIO_PE_FEAT_CRF_SUPPORT_SHIFT (0x00000005u) #define CSL_SRIO_PE_FEAT_CRF_SUPPORT_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_LARGE_SUPPORT_MASK (0x00000010u) #define CSL_SRIO_PE_FEAT_LARGE_SUPPORT_SHIFT (0x00000004u) #define CSL_SRIO_PE_FEAT_LARGE_SUPPORT_RESETVAL (0x00000000u) #define CSL_SRIO_PE_FEAT_EXTENDED_FEATURES_MASK (0x00000008u) #define CSL_SRIO_PE_FEAT_EXTENDED_FEATURES_SHIFT (0x00000003u) #define CSL_SRIO_PE_FEAT_EXTENDED_FEATURES_RESETVAL (0x00000001u) #define CSL_SRIO_PE_FEAT_EXTENDED_ADDRESSING_SUPPORT_MASK (0x00000007u) #define CSL_SRIO_PE_FEAT_EXTENDED_ADDRESSING_SUPPORT_SHIFT (0x00000000u) #define CSL_SRIO_PE_FEAT_EXTENDED_ADDRESSING_SUPPORT_RESETVAL (0x00000001u) #define CSL_SRIO_PE_FEAT_RESETVAL (0x20000009u) /* SRC_OP */ #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_2_MASK (0x00030000u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_2_SHIFT (0x00000010u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_2_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_READ_MASK (0x00008000u) #define CSL_SRIO_SRC_OP_READ_SHIFT (0x0000000Fu) #define CSL_SRIO_SRC_OP_READ_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_WRITE_MASK (0x00004000u) #define CSL_SRIO_SRC_OP_WRITE_SHIFT (0x0000000Eu) #define CSL_SRIO_SRC_OP_WRITE_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_STREAM_WRITE_MASK (0x00002000u) #define CSL_SRIO_SRC_OP_STREAM_WRITE_SHIFT (0x0000000Du) #define CSL_SRIO_SRC_OP_STREAM_WRITE_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_WRITE_WITH_RESP_MASK (0x00001000u) #define CSL_SRIO_SRC_OP_WRITE_WITH_RESP_SHIFT (0x0000000Cu) #define CSL_SRIO_SRC_OP_WRITE_WITH_RESP_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_DATA_MESS_MASK (0x00000800u) #define CSL_SRIO_SRC_OP_DATA_MESS_SHIFT (0x0000000Bu) #define CSL_SRIO_SRC_OP_DATA_MESS_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_DOORBELL_MASK (0x00000400u) #define CSL_SRIO_SRC_OP_DOORBELL_SHIFT (0x0000000Au) #define CSL_SRIO_SRC_OP_DOORBELL_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_TEST_AND_SWAP_MASK (0x00000100u) #define CSL_SRIO_SRC_OP_ATOMIC_TEST_AND_SWAP_SHIFT (0x00000008u) #define CSL_SRIO_SRC_OP_ATOMIC_TEST_AND_SWAP_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_INCRMNT_MASK (0x00000080u) #define CSL_SRIO_SRC_OP_ATOMIC_INCRMNT_SHIFT (0x00000007u) #define CSL_SRIO_SRC_OP_ATOMIC_INCRMNT_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_DCRMNT_MASK (0x00000040u) #define CSL_SRIO_SRC_OP_ATOMIC_DCRMNT_SHIFT (0x00000006u) #define CSL_SRIO_SRC_OP_ATOMIC_DCRMNT_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_SET_MASK (0x00000020u) #define CSL_SRIO_SRC_OP_ATOMIC_SET_SHIFT (0x00000005u) #define CSL_SRIO_SRC_OP_ATOMIC_SET_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_ATOMIC_CLEAR_MASK (0x00000010u) #define CSL_SRIO_SRC_OP_ATOMIC_CLEAR_SHIFT (0x00000004u) #define CSL_SRIO_SRC_OP_ATOMIC_CLEAR_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_PORT_WRITE_MASK (0x00000004u) #define CSL_SRIO_SRC_OP_PORT_WRITE_SHIFT (0x00000002u) #define CSL_SRIO_SRC_OP_PORT_WRITE_RESETVAL (0x00000001u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_1_MASK (0x00000003u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_1_SHIFT (0x00000000u) #define CSL_SRIO_SRC_OP_IMPLMNT_DEFINED_1_RESETVAL (0x00000000u) #define CSL_SRIO_SRC_OP_RESETVAL (0x00000004u) /* DEST_OP */ #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_2_MASK (0x00030000u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_2_SHIFT (0x00000010u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_2_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_READ_MASK (0x00008000u) #define CSL_SRIO_DEST_OP_READ_SHIFT (0x0000000Fu) #define CSL_SRIO_DEST_OP_READ_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_WRITE_MASK (0x00004000u) #define CSL_SRIO_DEST_OP_WRITE_SHIFT (0x0000000Eu) #define CSL_SRIO_DEST_OP_WRITE_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_STREAM_WRITE_MASK (0x00002000u) #define CSL_SRIO_DEST_OP_STREAM_WRITE_SHIFT (0x0000000Du) #define CSL_SRIO_DEST_OP_STREAM_WRITE_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_WRITE_WITH_RESP_MASK (0x00001000u) #define CSL_SRIO_DEST_OP_WRITE_WITH_RESP_SHIFT (0x0000000Cu) #define CSL_SRIO_DEST_OP_WRITE_WITH_RESP_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_DATA_MESS_MASK (0x00000800u) #define CSL_SRIO_DEST_OP_DATA_MESS_SHIFT (0x0000000Bu) #define CSL_SRIO_DEST_OP_DATA_MESS_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_DOORBELL_MASK (0x00000400u) #define CSL_SRIO_DEST_OP_DOORBELL_SHIFT (0x0000000Au) #define CSL_SRIO_DEST_OP_DOORBELL_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_TEST_AND_SWAP_MASK (0x00000100u) #define CSL_SRIO_DEST_OP_ATOMIC_TEST_AND_SWAP_SHIFT (0x00000008u) #define CSL_SRIO_DEST_OP_ATOMIC_TEST_AND_SWAP_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_INCRMNT_MASK (0x00000080u) #define CSL_SRIO_DEST_OP_ATOMIC_INCRMNT_SHIFT (0x00000007u) #define CSL_SRIO_DEST_OP_ATOMIC_INCRMNT_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_DCRMNT_MASK (0x00000040u) #define CSL_SRIO_DEST_OP_ATOMIC_DCRMNT_SHIFT (0x00000006u) #define CSL_SRIO_DEST_OP_ATOMIC_DCRMNT_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_SET_MASK (0x00000020u) #define CSL_SRIO_DEST_OP_ATOMIC_SET_SHIFT (0x00000005u) #define CSL_SRIO_DEST_OP_ATOMIC_SET_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_ATOMIC_CLEAR_MASK (0x00000010u) #define CSL_SRIO_DEST_OP_ATOMIC_CLEAR_SHIFT (0x00000004u) #define CSL_SRIO_DEST_OP_ATOMIC_CLEAR_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_PORT_WRITE_MASK (0x00000004u) #define CSL_SRIO_DEST_OP_PORT_WRITE_SHIFT (0x00000002u) #define CSL_SRIO_DEST_OP_PORT_WRITE_RESETVAL (0x00000001u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_1_MASK (0x00000003u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_1_SHIFT (0x00000000u) #define CSL_SRIO_DEST_OP_IMPLMNT_DEFINED_1_RESETVAL (0x00000000u) #define CSL_SRIO_DEST_OP_RESETVAL (0x00000004u) /* PE_LL_CTL */ #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_MASK (0x00000007u) #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_SHIFT (0x00000000u) #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_RESETVAL (0x00000001u) /*----EXTENDED_ADDRESSING_CONTROL Tokens----*/ #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_66BIT (0x00000004u) #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_50BIT (0x00000002u) #define CSL_SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL_34BIT (0x00000001u) #define CSL_SRIO_PE_LL_CTL_RESETVAL (0x00000001u) /* LCL_CFG_HBAR */ #define CSL_SRIO_LCL_CFG_HBAR_LCSBA_MASK (0x7FFFFFFFu) #define CSL_SRIO_LCL_CFG_HBAR_LCSBA_SHIFT (0x00000000u) #define CSL_SRIO_LCL_CFG_HBAR_LCSBA_RESETVAL (0x00000000u) #define CSL_SRIO_LCL_CFG_HBAR_RESETVAL (0x00000000u) /* LCL_CFG_BAR */ #define CSL_SRIO_LCL_CFG_BAR_LCSBA_MASK (0xFFFFFFFFu) #define CSL_SRIO_LCL_CFG_BAR_LCSBA_SHIFT (0x00000000u) #define CSL_SRIO_LCL_CFG_BAR_LCSBA_RESETVAL (0x00000000u) #define CSL_SRIO_LCL_CFG_BAR_RESETVAL (0x00000000u) /* BASE_ID */ #define CSL_SRIO_BASE_ID_BASE_DEVICEID_MASK (0x00FF0000u) #define CSL_SRIO_BASE_ID_BASE_DEVICEID_SHIFT (0x00000010u) #define CSL_SRIO_BASE_ID_BASE_DEVICEID_RESETVAL (0x000000FFu) #define CSL_SRIO_BASE_ID_LARGE_BASE_DEVICEID_MASK (0x0000FFFFu) #define CSL_SRIO_BASE_ID_LARGE_BASE_DEVICEID_SHIFT (0x00000000u) #define CSL_SRIO_BASE_ID_LARGE_BASE_DEVICEID_RESETVAL (0x0000FFFFu) #define CSL_SRIO_BASE_ID_RESETVAL (0x00FFFFFFu) /* HOST_BASE_ID_LOCK */ #define CSL_SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID_MASK (0x0000FFFFu) #define CSL_SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID_SHIFT (0x00000000u) #define CSL_SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID_RESETVAL (0x0000FFFFu) #define CSL_SRIO_HOST_BASE_ID_LOCK_RESETVAL (0x0000FFFFu) /* COMP_TAG */ #define CSL_SRIO_COMP_TAG_COMPONENT_TAG_MASK (0xFFFFFFFFu) #define CSL_SRIO_COMP_TAG_COMPONENT_TAG_SHIFT (0x00000000u) #define CSL_SRIO_COMP_TAG_COMPONENT_TAG_RESETVAL (0x00000000u) #define CSL_SRIO_COMP_TAG_RESETVAL (0x00000000u) /* SP_MB_HEAD */ #define CSL_SRIO_SP_MB_HEAD_EF_PTR_MASK (0xFFFF0000u) #define CSL_SRIO_SP_MB_HEAD_EF_PTR_SHIFT (0x00000010u) #define CSL_SRIO_SP_MB_HEAD_EF_PTR_RESETVAL (0x00001000u) #define CSL_SRIO_SP_MB_HEAD_EF_ID_MASK (0x0000FFFFu) #define CSL_SRIO_SP_MB_HEAD_EF_ID_SHIFT (0x00000000u) #define CSL_SRIO_SP_MB_HEAD_EF_ID_RESETVAL (0x00000001u) #define CSL_SRIO_SP_MB_HEAD_RESETVAL (0x10000001u) /* SP_LT_CTL */ #define CSL_SRIO_SP_LT_CTL_TIMEOUT_VALUE_MASK (0xFFFFFF00u) #define CSL_SRIO_SP_LT_CTL_TIMEOUT_VALUE_SHIFT (0x00000008u) #define CSL_SRIO_SP_LT_CTL_TIMEOUT_VALUE_RESETVAL (0x00FFFFFFu) #define CSL_SRIO_SP_LT_CTL_RESETVAL (0xFFFFFF00u) /* SP_RT_CTL */ #define CSL_SRIO_SP_RT_CTL_TIMEOUT_VALUE_MASK (0xFFFFFF00u) #define CSL_SRIO_SP_RT_CTL_TIMEOUT_VALUE_SHIFT (0x00000008u) #define CSL_SRIO_SP_RT_CTL_TIMEOUT_VALUE_RESETVAL (0x00FFFFFFu) #define CSL_SRIO_SP_RT_CTL_RESETVAL (0xFFFFFF00u) /* SP_GEN_CTL */ #define CSL_SRIO_SP_GEN_CTL_HOST_MASK (0x80000000u) #define CSL_SRIO_SP_GEN_CTL_HOST_SHIFT (0x0000001Fu) #define CSL_SRIO_SP_GEN_CTL_HOST_RESETVAL (0x00000000u) /*----HOST Tokens----*/ #define CSL_SRIO_SP_GEN_CTL_HOST_DISABLE (0x00000000u) #define CSL_SRIO_SP_GEN_CTL_HOST_ENABLE (0x00000001u) #define CSL_SRIO_SP_GEN_CTL_MASTER_ENABLE_MASK (0x40000000u) #define CSL_SRIO_SP_GEN_CTL_MASTER_ENABLE_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_GEN_CTL_MASTER_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_GEN_CTL_DISCOVERED_MASK (0x20000000u) #define CSL_SRIO_SP_GEN_CTL_DISCOVERED_SHIFT (0x0000001Du) #define CSL_SRIO_SP_GEN_CTL_DISCOVERED_RESETVAL (0x00000000u) #define CSL_SRIO_SP_GEN_CTL_RESETVAL (0x00000000u) /* SP_LM_REQ */ #define CSL_SRIO_SP_LM_REQ_COMMAND_MASK (0x00000007u) #define CSL_SRIO_SP_LM_REQ_COMMAND_SHIFT (0x00000000u) #define CSL_SRIO_SP_LM_REQ_COMMAND_RESETVAL (0x00000000u) #define CSL_SRIO_SP_LM_REQ_RESETVAL (0x00000000u) /* SP_LM_RESP */ #define CSL_SRIO_SP_LM_RESP_RESPONSE_VALID_MASK (0x80000000u) #define CSL_SRIO_SP_LM_RESP_RESPONSE_VALID_SHIFT (0x0000001Fu) #define CSL_SRIO_SP_LM_RESP_RESPONSE_VALID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_LM_RESP_ACKID_STATUS_MASK (0x000003E0u) #define CSL_SRIO_SP_LM_RESP_ACKID_STATUS_SHIFT (0x00000005u) #define CSL_SRIO_SP_LM_RESP_ACKID_STATUS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_LM_RESP_LINK_STATUS_MASK (0x0000001Fu) #define CSL_SRIO_SP_LM_RESP_LINK_STATUS_SHIFT (0x00000000u) #define CSL_SRIO_SP_LM_RESP_LINK_STATUS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_LM_RESP_RESETVAL (0x00000000u) /* SP_ACKID_STAT */ #define CSL_SRIO_SP_ACKID_STAT_INBOUND_ACKID_MASK (0x1F000000u) #define CSL_SRIO_SP_ACKID_STAT_INBOUND_ACKID_SHIFT (0x00000018u) #define CSL_SRIO_SP_ACKID_STAT_INBOUND_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ACKID_STAT_OUTSTANDING_ACKID_MASK (0x00001F00u) #define CSL_SRIO_SP_ACKID_STAT_OUTSTANDING_ACKID_SHIFT (0x00000008u) #define CSL_SRIO_SP_ACKID_STAT_OUTSTANDING_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ACKID_STAT_OUTBOUND_ACKID_MASK (0x0000001Fu) #define CSL_SRIO_SP_ACKID_STAT_OUTBOUND_ACKID_SHIFT (0x00000000u) #define CSL_SRIO_SP_ACKID_STAT_OUTBOUND_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ACKID_STAT_RESETVAL (0x00000000u) /* SP_ERR_STAT */ #define CSL_SRIO_SP_ERR_STAT_OUTPUT_PKT_DROP_MASK (0x04000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_PKT_DROP_SHIFT (0x0000001Au) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_PKT_DROP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_FLD_ENC_MASK (0x02000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_FLD_ENC_SHIFT (0x00000019u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_FLD_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_DEGRD_ENC_MASK (0x01000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_DEGRD_ENC_SHIFT (0x00000018u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_DEGRD_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_ENC_MASK (0x00100000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_ENC_SHIFT (0x00000014u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRIED_MASK (0x00080000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRIED_SHIFT (0x00000013u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRIED_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_STP_MASK (0x00040000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_STP_SHIFT (0x00000012u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_RETRY_STP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_ENC_MASK (0x00020000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_ENC_SHIFT (0x00000011u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_STP_MASK (0x00010000u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_STP_SHIFT (0x00000010u) #define CSL_SRIO_SP_ERR_STAT_OUTPUT_ERROR_STP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_INPUT_RETRY_STP_MASK (0x00000400u) #define CSL_SRIO_SP_ERR_STAT_INPUT_RETRY_STP_SHIFT (0x0000000Au) #define CSL_SRIO_SP_ERR_STAT_INPUT_RETRY_STP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_ENC_MASK (0x00000200u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_ENC_SHIFT (0x00000009u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_ENC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_STP_MASK (0x00000100u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_STP_SHIFT (0x00000008u) #define CSL_SRIO_SP_ERR_STAT_INPUT_ERROR_STP_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_WRITE_PND_MASK (0x00000010u) #define CSL_SRIO_SP_ERR_STAT_PORT_WRITE_PND_SHIFT (0x00000004u) #define CSL_SRIO_SP_ERR_STAT_PORT_WRITE_PND_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_ERROR_MASK (0x00000004u) #define CSL_SRIO_SP_ERR_STAT_PORT_ERROR_SHIFT (0x00000002u) #define CSL_SRIO_SP_ERR_STAT_PORT_ERROR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_OK_MASK (0x00000002u) #define CSL_SRIO_SP_ERR_STAT_PORT_OK_SHIFT (0x00000001u) #define CSL_SRIO_SP_ERR_STAT_PORT_OK_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_UNINITIALIZED_MASK (0x00000001u) #define CSL_SRIO_SP_ERR_STAT_PORT_UNINITIALIZED_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_STAT_PORT_UNINITIALIZED_RESETVAL (0x00000001u) #define CSL_SRIO_SP_ERR_STAT_RESETVAL (0x00000001u) /* SP_CTL */ #define CSL_SRIO_SP_CTL_PORT_WIDTH_MASK (0xC0000000u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_CTL_PORT_WIDTH_RESETVAL (0x00000001u) #define CSL_SRIO_SP_CTL_INITIALIZED_PORT_WIDTH_MASK (0x38000000u) #define CSL_SRIO_SP_CTL_INITIALIZED_PORT_WIDTH_SHIFT (0x0000001Bu) #define CSL_SRIO_SP_CTL_INITIALIZED_PORT_WIDTH_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_MASK (0x07000000u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_SHIFT (0x00000018u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_RESETVAL (0x00000000u) /*----PORT_WIDTH_OVERRIDE Tokens----*/ #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_NO_OVERRIDE (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_SINGLE_LANE_0 (0x00000002u) #define CSL_SRIO_SP_CTL_PORT_WIDTH_OVERRIDE_SINGLE_LANE_2 (0x00000003u) #define CSL_SRIO_SP_CTL_PORT_DISABLE_MASK (0x00800000u) #define CSL_SRIO_SP_CTL_PORT_DISABLE_SHIFT (0x00000017u) #define CSL_SRIO_SP_CTL_PORT_DISABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_OUTPUT_PORT_ENABLE_MASK (0x00400000u) #define CSL_SRIO_SP_CTL_OUTPUT_PORT_ENABLE_SHIFT (0x00000016u) #define CSL_SRIO_SP_CTL_OUTPUT_PORT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INPUT_PORT_ENABLE_MASK (0x00200000u) #define CSL_SRIO_SP_CTL_INPUT_PORT_ENABLE_SHIFT (0x00000015u) #define CSL_SRIO_SP_CTL_INPUT_PORT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_ERROR_CHECK_DISABLE_MASK (0x00100000u) #define CSL_SRIO_SP_CTL_ERROR_CHECK_DISABLE_SHIFT (0x00000014u) #define CSL_SRIO_SP_CTL_ERROR_CHECK_DISABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_MULTICAST_PARTICIPANT_MASK (0x00080000u) #define CSL_SRIO_SP_CTL_MULTICAST_PARTICIPANT_SHIFT (0x00000013u) #define CSL_SRIO_SP_CTL_MULTICAST_PARTICIPANT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE_MASK (0x00000008u) #define CSL_SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE_SHIFT (0x00000003u) #define CSL_SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_DROP_PACKET_ENABLE_MASK (0x00000004u) #define CSL_SRIO_SP_CTL_DROP_PACKET_ENABLE_SHIFT (0x00000002u) #define CSL_SRIO_SP_CTL_DROP_PACKET_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_LOCKOUT_MASK (0x00000002u) #define CSL_SRIO_SP_CTL_PORT_LOCKOUT_SHIFT (0x00000001u) #define CSL_SRIO_SP_CTL_PORT_LOCKOUT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_TYPE_MASK (0x00000001u) #define CSL_SRIO_SP_CTL_PORT_TYPE_SHIFT (0x00000000u) #define CSL_SRIO_SP_CTL_PORT_TYPE_RESETVAL (0x00000001u) #define CSL_SRIO_SP_CTL_RESETVAL (0x40000001u) /* ERR_RPT_BH */ #define CSL_SRIO_ERR_RPT_BH_EF_PTR_MASK (0xFFFF0000u) #define CSL_SRIO_ERR_RPT_BH_EF_PTR_SHIFT (0x00000010u) #define CSL_SRIO_ERR_RPT_BH_EF_PTR_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_RPT_BH_EF_ID_MASK (0x0000FFFFu) #define CSL_SRIO_ERR_RPT_BH_EF_ID_SHIFT (0x00000000u) #define CSL_SRIO_ERR_RPT_BH_EF_ID_RESETVAL (0x00000007u) #define CSL_SRIO_ERR_RPT_BH_RESETVAL (0x00000007u) /* ERR_DET */ #define CSL_SRIO_ERR_DET_IO_ERR_RSPNS_MASK (0x80000000u) #define CSL_SRIO_ERR_DET_IO_ERR_RSPNS_SHIFT (0x0000001Fu) #define CSL_SRIO_ERR_DET_IO_ERR_RSPNS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_MSG_ERR_RSPNS_MASK (0x40000000u) #define CSL_SRIO_ERR_DET_MSG_ERR_RSPNS_SHIFT (0x0000001Eu) #define CSL_SRIO_ERR_DET_MSG_ERR_RSPNS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_GSM_ERR_RSPNS_MASK (0x20000000u) #define CSL_SRIO_ERR_DET_GSM_ERR_RSPNS_SHIFT (0x0000001Du) #define CSL_SRIO_ERR_DET_GSM_ERR_RSPNS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_ERR_MSG_FORMAT_MASK (0x10000000u) #define CSL_SRIO_ERR_DET_ERR_MSG_FORMAT_SHIFT (0x0000001Cu) #define CSL_SRIO_ERR_DET_ERR_MSG_FORMAT_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_ILL_TRANS_DECODE_MASK (0x08000000u) #define CSL_SRIO_ERR_DET_ILL_TRANS_DECODE_SHIFT (0x0000001Bu) #define CSL_SRIO_ERR_DET_ILL_TRANS_DECODE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_ILL_TRANS_TRGT_ERR_MASK (0x04000000u) #define CSL_SRIO_ERR_DET_ILL_TRANS_TRGT_ERR_SHIFT (0x0000001Au) #define CSL_SRIO_ERR_DET_ILL_TRANS_TRGT_ERR_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_MSG_REQ_TIMEOUT_MASK (0x02000000u) #define CSL_SRIO_ERR_DET_MSG_REQ_TIMEOUT_SHIFT (0x00000019u) #define CSL_SRIO_ERR_DET_MSG_REQ_TIMEOUT_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_PKT_RSPNS_TIMEOUT_MASK (0x01000000u) #define CSL_SRIO_ERR_DET_PKT_RSPNS_TIMEOUT_SHIFT (0x00000018u) #define CSL_SRIO_ERR_DET_PKT_RSPNS_TIMEOUT_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_UNSOLICITED_RSPNS_MASK (0x00800000u) #define CSL_SRIO_ERR_DET_UNSOLICITED_RSPNS_SHIFT (0x00000017u) #define CSL_SRIO_ERR_DET_UNSOLICITED_RSPNS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_UNSUPPORTED_TRANS_MASK (0x00400000u) #define CSL_SRIO_ERR_DET_UNSUPPORTED_TRANS_SHIFT (0x00000016u) #define CSL_SRIO_ERR_DET_UNSUPPORTED_TRANS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_RX_CPPI_SECURITY_MASK (0x00000080u) #define CSL_SRIO_ERR_DET_RX_CPPI_SECURITY_SHIFT (0x00000007u) #define CSL_SRIO_ERR_DET_RX_CPPI_SECURITY_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_RX_IO_DMA_ACCESS_MASK (0x00000040u) #define CSL_SRIO_ERR_DET_RX_IO_DMA_ACCESS_SHIFT (0x00000006u) #define CSL_SRIO_ERR_DET_RX_IO_DMA_ACCESS_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_DET_RESETVAL (0x00000000u) /* ERR_EN */ #define CSL_SRIO_ERR_EN_IO_ERR_RESP_ENABLE_MASK (0x80000000u) #define CSL_SRIO_ERR_EN_IO_ERR_RESP_ENABLE_SHIFT (0x0000001Fu) #define CSL_SRIO_ERR_EN_IO_ERR_RESP_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_MSG_ERR_RESP_ENABLE_MASK (0x40000000u) #define CSL_SRIO_ERR_EN_MSG_ERR_RESP_ENABLE_SHIFT (0x0000001Eu) #define CSL_SRIO_ERR_EN_MSG_ERR_RESP_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_GSM_ERR_RESP_ENABLE_MASK (0x20000000u) #define CSL_SRIO_ERR_EN_GSM_ERR_RESP_ENABLE_SHIFT (0x0000001Du) #define CSL_SRIO_ERR_EN_GSM_ERR_RESP_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_ERR_MSG_FORMAT_ENABLE_MASK (0x10000000u) #define CSL_SRIO_ERR_EN_ERR_MSG_FORMAT_ENABLE_SHIFT (0x0000001Cu) #define CSL_SRIO_ERR_EN_ERR_MSG_FORMAT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_ILL_TRANS_DECODE_ENABLE_MASK (0x08000000u) #define CSL_SRIO_ERR_EN_ILL_TRANS_DECODE_ENABLE_SHIFT (0x0000001Bu) #define CSL_SRIO_ERR_EN_ILL_TRANS_DECODE_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_ILL_TRANS_TARGET_ERR_ENABLE_MASK (0x04000000u) #define CSL_SRIO_ERR_EN_ILL_TRANS_TARGET_ERR_ENABLE_SHIFT (0x0000001Au) #define CSL_SRIO_ERR_EN_ILL_TRANS_TARGET_ERR_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_MSG_REQ_TIMEOUT_ENABLE_MASK (0x02000000u) #define CSL_SRIO_ERR_EN_MSG_REQ_TIMEOUT_ENABLE_SHIFT (0x00000019u) #define CSL_SRIO_ERR_EN_MSG_REQ_TIMEOUT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_PKT_RESP_TIMEOUT_ENABLE_MASK (0x01000000u) #define CSL_SRIO_ERR_EN_PKT_RESP_TIMEOUT_ENABLE_SHIFT (0x00000018u) #define CSL_SRIO_ERR_EN_PKT_RESP_TIMEOUT_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_UNSOLICITED_RESP_ENABLE_MASK (0x00800000u) #define CSL_SRIO_ERR_EN_UNSOLICITED_RESP_ENABLE_SHIFT (0x00000017u) #define CSL_SRIO_ERR_EN_UNSOLICITED_RESP_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_UNSUPPORTED_TRANS_ENABLE_MASK (0x00400000u) #define CSL_SRIO_ERR_EN_UNSUPPORTED_TRANS_ENABLE_SHIFT (0x00000016u) #define CSL_SRIO_ERR_EN_UNSUPPORTED_TRANS_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_RX_CPPI_SECURITY_MASK (0x00000080u) #define CSL_SRIO_ERR_EN_RX_CPPI_SECURITY_SHIFT (0x00000007u) #define CSL_SRIO_ERR_EN_RX_CPPI_SECURITY_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_RX_IO_SECURITY_MASK (0x00000040u) #define CSL_SRIO_ERR_EN_RX_IO_SECURITY_SHIFT (0x00000006u) #define CSL_SRIO_ERR_EN_RX_IO_SECURITY_RESETVAL (0x00000000u) #define CSL_SRIO_ERR_EN_RESETVAL (0x00000000u) /* H_ADDR_CAPT */ #define CSL_SRIO_H_ADDR_CAPT_ADDRESS_63_32_MASK (0xFFFFFFFFu) #define CSL_SRIO_H_ADDR_CAPT_ADDRESS_63_32_SHIFT (0x00000000u) #define CSL_SRIO_H_ADDR_CAPT_ADDRESS_63_32_RESETVAL (0x00000000u) #define CSL_SRIO_H_ADDR_CAPT_RESETVAL (0x00000000u) /* ADDR_CAPT */ #define CSL_SRIO_ADDR_CAPT_ADDRESS_31_3_MASK (0xFFFFFFF8u) #define CSL_SRIO_ADDR_CAPT_ADDRESS_31_3_SHIFT (0x00000003u) #define CSL_SRIO_ADDR_CAPT_ADDRESS_31_3_RESETVAL (0x00000000u) #define CSL_SRIO_ADDR_CAPT_XAMSBS_MASK (0x00000003u) #define CSL_SRIO_ADDR_CAPT_XAMSBS_SHIFT (0x00000000u) #define CSL_SRIO_ADDR_CAPT_XAMSBS_RESETVAL (0x00000000u) #define CSL_SRIO_ADDR_CAPT_RESETVAL (0x00000000u) /* ID_CAPT */ #define CSL_SRIO_ID_CAPT_MSB_DESTID_MASK (0xFF000000u) #define CSL_SRIO_ID_CAPT_MSB_DESTID_SHIFT (0x00000018u) #define CSL_SRIO_ID_CAPT_MSB_DESTID_RESETVAL (0x00000000u) #define CSL_SRIO_ID_CAPT_DESTID_MASK (0x00FF0000u) #define CSL_SRIO_ID_CAPT_DESTID_SHIFT (0x00000010u) #define CSL_SRIO_ID_CAPT_DESTID_RESETVAL (0x00000000u) #define CSL_SRIO_ID_CAPT_MSB_SOURCEID_MASK (0x0000FF00u) #define CSL_SRIO_ID_CAPT_MSB_SOURCEID_SHIFT (0x00000008u) #define CSL_SRIO_ID_CAPT_MSB_SOURCEID_RESETVAL (0x00000000u) #define CSL_SRIO_ID_CAPT_SOURCEID_MASK (0x000000FFu) #define CSL_SRIO_ID_CAPT_SOURCEID_SHIFT (0x00000000u) #define CSL_SRIO_ID_CAPT_SOURCEID_RESETVAL (0x00000000u) #define CSL_SRIO_ID_CAPT_RESETVAL (0x00000000u) /* CTRL_CAPT */ #define CSL_SRIO_CTRL_CAPT_FTYPE_MASK (0xF0000000u) #define CSL_SRIO_CTRL_CAPT_FTYPE_SHIFT (0x0000001Cu) #define CSL_SRIO_CTRL_CAPT_FTYPE_RESETVAL (0x00000000u) #define CSL_SRIO_CTRL_CAPT_TTYPE_MASK (0x0F000000u) #define CSL_SRIO_CTRL_CAPT_TTYPE_SHIFT (0x00000018u) #define CSL_SRIO_CTRL_CAPT_TTYPE_RESETVAL (0x00000000u) #define CSL_SRIO_CTRL_CAPT_MSGINFO_MASK (0x00FF0000u) #define CSL_SRIO_CTRL_CAPT_MSGINFO_SHIFT (0x00000010u) #define CSL_SRIO_CTRL_CAPT_MSGINFO_RESETVAL (0x00000000u) #define CSL_SRIO_CTRL_CAPT_IMP_SPECIFIC_MASK (0x0000FFFFu) #define CSL_SRIO_CTRL_CAPT_IMP_SPECIFIC_SHIFT (0x00000000u) #define CSL_SRIO_CTRL_CAPT_IMP_SPECIFIC_RESETVAL (0x00000000u) #define CSL_SRIO_CTRL_CAPT_RESETVAL (0x00000000u) /* PW_TGT_ID */ #define CSL_SRIO_PW_TGT_ID_DEVICEID_MSB_MASK (0xFF000000u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_MSB_SHIFT (0x00000018u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_MSB_RESETVAL (0x00000000u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_MASK (0x00FF0000u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_SHIFT (0x00000010u) #define CSL_SRIO_PW_TGT_ID_DEVICEID_RESETVAL (0x00000000u) #define CSL_SRIO_PW_TGT_ID_RESETVAL (0x00000000u) /* SP_ERR_DET */ #define CSL_SRIO_SP_ERR_DET_ERR_IMP_SPECIFIC_MASK (0x80000000u) #define CSL_SRIO_SP_ERR_DET_ERR_IMP_SPECIFIC_SHIFT (0x0000001Fu) #define CSL_SRIO_SP_ERR_DET_ERR_IMP_SPECIFIC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_CORRUPT_CNTL_SYM_MASK (0x00400000u) #define CSL_SRIO_SP_ERR_DET_CORRUPT_CNTL_SYM_SHIFT (0x00000016u) #define CSL_SRIO_SP_ERR_DET_CORRUPT_CNTL_SYM_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_CNTL_SYM_UNEXPECTED_ACKID_MASK (0x00200000u) #define CSL_SRIO_SP_ERR_DET_CNTL_SYM_UNEXPECTED_ACKID_SHIFT (0x00000015u) #define CSL_SRIO_SP_ERR_DET_CNTL_SYM_UNEXPECTED_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_NOT_ACCPT_MASK (0x00100000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_NOT_ACCPT_SHIFT (0x00000014u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_NOT_ACCPT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_PKT_UNEXPECTED_ACKID_MASK (0x00080000u) #define CSL_SRIO_SP_ERR_DET_PKT_UNEXPECTED_ACKID_SHIFT (0x00000013u) #define CSL_SRIO_SP_ERR_DET_PKT_UNEXPECTED_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_WITH_BAD_CRC_MASK (0x00040000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_WITH_BAD_CRC_SHIFT (0x00000012u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_WITH_BAD_CRC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_OVER_276B_MASK (0x00020000u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_OVER_276B_SHIFT (0x00000011u) #define CSL_SRIO_SP_ERR_DET_RCVD_PKT_OVER_276B_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_NON_OUTSTANDING_ACKID_MASK (0x00000020u) #define CSL_SRIO_SP_ERR_DET_NON_OUTSTANDING_ACKID_SHIFT (0x00000005u) #define CSL_SRIO_SP_ERR_DET_NON_OUTSTANDING_ACKID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_PROTOCOL_ERROR_MASK (0x00000010u) #define CSL_SRIO_SP_ERR_DET_PROTOCOL_ERROR_SHIFT (0x00000004u) #define CSL_SRIO_SP_ERR_DET_PROTOCOL_ERROR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_DELINEATION_ERROR_MASK (0x00000004u) #define CSL_SRIO_SP_ERR_DET_DELINEATION_ERROR_SHIFT (0x00000002u) #define CSL_SRIO_SP_ERR_DET_DELINEATION_ERROR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_UNSOLICITED_ACK_CNTL_SYM_MASK (0x00000002u) #define CSL_SRIO_SP_ERR_DET_UNSOLICITED_ACK_CNTL_SYM_SHIFT (0x00000001u) #define CSL_SRIO_SP_ERR_DET_UNSOLICITED_ACK_CNTL_SYM_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_LINK_TIMEOUT_MASK (0x00000001u) #define CSL_SRIO_SP_ERR_DET_LINK_TIMEOUT_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_DET_LINK_TIMEOUT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_DET_RESETVAL (0x00000000u) /* SP_RATE_EN */ #define CSL_SRIO_SP_RATE_EN_EN_IMP_SPECIFIC_MASK (0x80000000u) #define CSL_SRIO_SP_RATE_EN_EN_IMP_SPECIFIC_SHIFT (0x0000001Fu) #define CSL_SRIO_SP_RATE_EN_EN_IMP_SPECIFIC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_CORRUPT_CNTL_SYM_ENABLE_MASK (0x00400000u) #define CSL_SRIO_SP_RATE_EN_CORRUPT_CNTL_SYM_ENABLE_SHIFT (0x00000016u) #define CSL_SRIO_SP_RATE_EN_CORRUPT_CNTL_SYM_ENABLE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_CNTL_SYM_UNEXPECTED_ACKID_EN_MASK (0x00200000u) #define CSL_SRIO_SP_RATE_EN_CNTL_SYM_UNEXPECTED_ACKID_EN_SHIFT (0x00000015u) #define CSL_SRIO_SP_RATE_EN_CNTL_SYM_UNEXPECTED_ACKID_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_NOT_ACCPT_EN_MASK (0x00100000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_NOT_ACCPT_EN_SHIFT (0x00000014u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_NOT_ACCPT_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_PKT_UNEXPECTED_ACKID_EN_MASK (0x00080000u) #define CSL_SRIO_SP_RATE_EN_PKT_UNEXPECTED_ACKID_EN_SHIFT (0x00000013u) #define CSL_SRIO_SP_RATE_EN_PKT_UNEXPECTED_ACKID_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_WITH_BAD_CRC_EN_MASK (0x00040000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_WITH_BAD_CRC_EN_SHIFT (0x00000012u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_WITH_BAD_CRC_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_OVER_276B_EN_MASK (0x00020000u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_OVER_276B_EN_SHIFT (0x00000011u) #define CSL_SRIO_SP_RATE_EN_RCVED_PKT_OVER_276B_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_NON_OUTSTANDING_ACKID_EN_MASK (0x00000020u) #define CSL_SRIO_SP_RATE_EN_NON_OUTSTANDING_ACKID_EN_SHIFT (0x00000005u) #define CSL_SRIO_SP_RATE_EN_NON_OUTSTANDING_ACKID_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_PROTOCOL_ERROR_EN_MASK (0x00000010u) #define CSL_SRIO_SP_RATE_EN_PROTOCOL_ERROR_EN_SHIFT (0x00000004u) #define CSL_SRIO_SP_RATE_EN_PROTOCOL_ERROR_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_DELINEATION_ERROR_EN_MASK (0x00000004u) #define CSL_SRIO_SP_RATE_EN_DELINEATION_ERROR_EN_SHIFT (0x00000002u) #define CSL_SRIO_SP_RATE_EN_DELINEATION_ERROR_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_UNSOLICITED_ACK_CNTL_SYM_EN_MASK (0x00000002u) #define CSL_SRIO_SP_RATE_EN_UNSOLICITED_ACK_CNTL_SYM_EN_SHIFT (0x00000001u) #define CSL_SRIO_SP_RATE_EN_UNSOLICITED_ACK_CNTL_SYM_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_LINK_TIMEOUT_EN_MASK (0x00000001u) #define CSL_SRIO_SP_RATE_EN_LINK_TIMEOUT_EN_SHIFT (0x00000000u) #define CSL_SRIO_SP_RATE_EN_LINK_TIMEOUT_EN_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RATE_EN_RESETVAL (0x00000000u) /* SP_ERR_ATTR_CAPT_DBG0 */ #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_INFO_TYPE_MASK (0xC0000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_INFO_TYPE_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_INFO_TYPE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_ERROR_TYPE_MASK (0x1F000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_ERROR_TYPE_SHIFT (0x00000018u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_ERROR_TYPE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_IMP_SPECIFIC_MASK (0x00FFFFF0u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_IMP_SPECIFIC_SHIFT (0x00000004u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_IMP_SPECIFIC_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_CAPTURE_VALID_INFO_MASK (0x00000001u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_CAPTURE_VALID_INFO_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_CAPTURE_VALID_INFO_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_ATTR_CAPT_DBG0_RESETVAL (0x00000000u) /* SP_ERR_CAPT_DBG */ #define CSL_SRIO_SP_ERR_CAPT_DBG_CAPTURE_MASK (0xFFFFFFFFu) #define CSL_SRIO_SP_ERR_CAPT_DBG_CAPTURE_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_CAPT_DBG_CAPTURE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_CAPT_DBG_RESETVAL (0x00000000u) /* SP_ERR_RATE */ #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_BIAS_MASK (0xFF000000u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_BIAS_SHIFT (0x00000018u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_BIAS_RESETVAL (0x000000FFu) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY_MASK (0x00030000u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY_SHIFT (0x00000010u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_RATE_PEAK_ERROR_RATE_MASK (0x0000FF00u) #define CSL_SRIO_SP_ERR_RATE_PEAK_ERROR_RATE_SHIFT (0x00000008u) #define CSL_SRIO_SP_ERR_RATE_PEAK_ERROR_RATE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_COUNTER_MASK (0x000000FFu) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_COUNTER_SHIFT (0x00000000u) #define CSL_SRIO_SP_ERR_RATE_ERROR_RATE_COUNTER_RESETVAL (0x00000000u) #define CSL_SRIO_SP_ERR_RATE_RESETVAL (0xFF000000u) /* SP_ERR_THRESH */ #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD_MASK (0xFF000000u) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD_SHIFT (0x00000018u) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD_RESETVAL (0x000000FFu) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES_MASK (0x00FF0000u) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES_SHIFT (0x00000010u) #define CSL_SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES_RESETVAL (0x000000FFu) #define CSL_SRIO_SP_ERR_THRESH_RESETVAL (0xFFFF0000u) /* SP_IP_DISCOVERY_TIMER */ #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER_MASK (0xF0000000u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER_SHIFT (0x0000001Cu) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER_RESETVAL (0x00000009u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER_MASK (0x00F00000u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER_SHIFT (0x00000014u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER_RESETVAL (0x00000008u) #define CSL_SRIO_SP_IP_DISCOVERY_TIMER_RESETVAL (0x90800000u) /* SP_IP_MODE */ #define CSL_SRIO_SP_IP_MODE_SP_MODE_MASK (0xC0000000u) #define CSL_SRIO_SP_IP_MODE_SP_MODE_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_IP_MODE_SP_MODE_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_MASK (0x20000000u) #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_SHIFT (0x0000001Du) #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_RESETVAL (0x00000000u) /*----IDLE_ERR_DIS Tokens----*/ #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_DISABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_IDLE_ERR_DIS_ENABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_MASK (0x10000000u) #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_SHIFT (0x0000001Cu) #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_RESETVAL (0x00000000u) /*----TX_FIFO_BYPASS Tokens----*/ #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_TX_FIFO_BYPASS_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_DIS_MASK (0x08000000u) #define CSL_SRIO_SP_IP_MODE_PW_DIS_SHIFT (0x0000001Bu) #define CSL_SRIO_SP_IP_MODE_PW_DIS_RESETVAL (0x00000000u) /*----PW_DIS Tokens----*/ #define CSL_SRIO_SP_IP_MODE_PW_DIS_DISABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_DIS_ENABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_TGT_ID_DIS_MASK (0x04000000u) #define CSL_SRIO_SP_IP_MODE_TGT_ID_DIS_SHIFT (0x0000001Au) #define CSL_SRIO_SP_IP_MODE_TGT_ID_DIS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_SELF_RST_MASK (0x02000000u) #define CSL_SRIO_SP_IP_MODE_SELF_RST_SHIFT (0x00000019u) #define CSL_SRIO_SP_IP_MODE_SELF_RST_RESETVAL (0x00000000u) /*----SELF_RST Tokens----*/ #define CSL_SRIO_SP_IP_MODE_SELF_RST_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_SELF_RST_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_MLTC_EN_MASK (0x00000020u) #define CSL_SRIO_SP_IP_MODE_MLTC_EN_SHIFT (0x00000005u) #define CSL_SRIO_SP_IP_MODE_MLTC_EN_RESETVAL (0x00000000u) /*----MLTC_EN Tokens----*/ #define CSL_SRIO_SP_IP_MODE_MLTC_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_MLTC_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_MLTC_IRQ_MASK (0x00000010u) #define CSL_SRIO_SP_IP_MODE_MLTC_IRQ_SHIFT (0x00000004u) #define CSL_SRIO_SP_IP_MODE_MLTC_IRQ_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_RST_EN_MASK (0x00000008u) #define CSL_SRIO_SP_IP_MODE_RST_EN_SHIFT (0x00000003u) #define CSL_SRIO_SP_IP_MODE_RST_EN_RESETVAL (0x00000000u) /*----RST_EN Tokens----*/ #define CSL_SRIO_SP_IP_MODE_RST_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_RST_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_RST_CS_MASK (0x00000004u) #define CSL_SRIO_SP_IP_MODE_RST_CS_SHIFT (0x00000002u) #define CSL_SRIO_SP_IP_MODE_RST_CS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_PW_EN_MASK (0x00000002u) #define CSL_SRIO_SP_IP_MODE_PW_EN_SHIFT (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_EN_RESETVAL (0x00000000u) /*----PW_EN Tokens----*/ #define CSL_SRIO_SP_IP_MODE_PW_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_IP_MODE_PW_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_IRQ_MASK (0x00000001u) #define CSL_SRIO_SP_IP_MODE_PW_IRQ_SHIFT (0x00000000u) #define CSL_SRIO_SP_IP_MODE_PW_IRQ_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_MODE_RESETVAL (0x00000000u) /* IP_PRESCAL */ #define CSL_SRIO_IP_PRESCAL_PRESCALE_MASK (0x000000FFu) #define CSL_SRIO_IP_PRESCAL_PRESCALE_SHIFT (0x00000000u) #define CSL_SRIO_IP_PRESCAL_PRESCALE_RESETVAL (0x0000000Fu) #define CSL_SRIO_IP_PRESCAL_RESETVAL (0x0000000Fu) /* SP_IP_PW_IN_CAPT */ #define CSL_SRIO_SP_IP_PW_IN_CAPT_PW_CAPT_MASK (0xFFFFFFFFu) #define CSL_SRIO_SP_IP_PW_IN_CAPT_PW_CAPT_SHIFT (0x00000000u) #define CSL_SRIO_SP_IP_PW_IN_CAPT_PW_CAPT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_IP_PW_IN_CAPT_RESETVAL (0x00000000u) /* SP_RST_OPT */ #define CSL_SRIO_SP_RST_OPT_PORT_ID_MASK (0x000000FFu) #define CSL_SRIO_SP_RST_OPT_PORT_ID_SHIFT (0x00000000u) #define CSL_SRIO_SP_RST_OPT_PORT_ID_RESETVAL (0x00000000u) #define CSL_SRIO_SP_RST_OPT_RESETVAL (0x00000000u) /* SP_CTL_INDEP */ #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_MASK (0x40000000u) #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_SHIFT (0x0000001Eu) #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_RESETVAL (0x00000000u) /*----TX_FLW Tokens----*/ #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_TX_FLW_ENABLE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_MASK (0x20000000u) #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_SHIFT (0x0000001Du) #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_RESETVAL (0x00000000u) /*----SOFT_REC Tokens----*/ #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_BYHARDWARE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_SOFT_REC_BYSOFTWARE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_FORCE_REINIT_MASK (0x04000000u) #define CSL_SRIO_SP_CTL_INDEP_FORCE_REINIT_SHIFT (0x0000001Au) #define CSL_SRIO_SP_CTL_INDEP_FORCE_REINIT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_TRANS_MODE_MASK (0x03000000u) #define CSL_SRIO_SP_CTL_INDEP_TRANS_MODE_SHIFT (0x00000018u) #define CSL_SRIO_SP_CTL_INDEP_TRANS_MODE_RESETVAL (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_DEBUG_MASK (0x00800000u) #define CSL_SRIO_SP_CTL_INDEP_DEBUG_SHIFT (0x00000017u) #define CSL_SRIO_SP_CTL_INDEP_DEBUG_RESETVAL (0x00000000u) /*----DEBUG Tokens----*/ #define CSL_SRIO_SP_CTL_INDEP_DEBUG_NORMAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_DEBUG_DEBUG (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_SEND_DBG_PKT_MASK (0x00400000u) #define CSL_SRIO_SP_CTL_INDEP_SEND_DBG_PKT_SHIFT (0x00000016u) #define CSL_SRIO_SP_CTL_INDEP_SEND_DBG_PKT_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_MASK (0x00200000u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_SHIFT (0x00000015u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_RESETVAL (0x00000000u) /*----ILL_TRANS_EN Tokens----*/ #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_ERR_MASK (0x00100000u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_ERR_SHIFT (0x00000014u) #define CSL_SRIO_SP_CTL_INDEP_ILL_TRANS_ERR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_MASK (0x00020000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_SHIFT (0x00000011u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_RESETVAL (0x00000000u) /*----MAX_RETRY_EN Tokens----*/ #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_ERR_MASK (0x00010000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_ERR_SHIFT (0x00000010u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_ERR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_THR_MASK (0x0000FF00u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_THR_SHIFT (0x00000008u) #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_THR_RESETVAL (0x00000000u) /*----MAX_RETRY_THR Tokens----*/ #define CSL_SRIO_SP_CTL_INDEP_MAX_RETRY_THR_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_MASK (0x00000080u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_SHIFT (0x00000007u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_RESETVAL (0x00000000u) /*----IRQ_EN Tokens----*/ #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_ENABLE (0x00000001u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_EN_DISABLE (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_ERR_MASK (0x00000040u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_ERR_SHIFT (0x00000006u) #define CSL_SRIO_SP_CTL_INDEP_IRQ_ERR_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CTL_INDEP_RESETVAL (0x01000000u) /* SP_SILENCE_TIMER */ #define CSL_SRIO_SP_SILENCE_TIMER_SILENCE_TIMER_MASK (0xF0000000u) #define CSL_SRIO_SP_SILENCE_TIMER_SILENCE_TIMER_SHIFT (0x0000001Cu) #define CSL_SRIO_SP_SILENCE_TIMER_SILENCE_TIMER_RESETVAL (0x0000000Bu) #define CSL_SRIO_SP_SILENCE_TIMER_RESETVAL (0xB0000000u) /* SP_MULT_EVNT_CS */ #define CSL_SRIO_SP_MULT_EVNT_CS_MULT_EVNT_CS_MASK (0xFFFFFFFFu) #define CSL_SRIO_SP_MULT_EVNT_CS_MULT_EVNT_CS_SHIFT (0x00000000u) #define CSL_SRIO_SP_MULT_EVNT_CS_MULT_EVNT_CS_RESETVAL (0x00000000u) #define CSL_SRIO_SP_MULT_EVNT_CS_RESETVAL (0x00000000u) /* SP_CS_TX */ #define CSL_SRIO_SP_CS_TX_STYPE_0_MASK (0xE0000000u) #define CSL_SRIO_SP_CS_TX_STYPE_0_SHIFT (0x0000001Du) #define CSL_SRIO_SP_CS_TX_STYPE_0_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_PAR_0_MASK (0x1F000000u) #define CSL_SRIO_SP_CS_TX_PAR_0_SHIFT (0x00000018u) #define CSL_SRIO_SP_CS_TX_PAR_0_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_PAR_1_MASK (0x00F80000u) #define CSL_SRIO_SP_CS_TX_PAR_1_SHIFT (0x00000013u) #define CSL_SRIO_SP_CS_TX_PAR_1_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_STYPE_1_MASK (0x00070000u) #define CSL_SRIO_SP_CS_TX_STYPE_1_SHIFT (0x00000010u) #define CSL_SRIO_SP_CS_TX_STYPE_1_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_CMD_MASK (0x0000E000u) #define CSL_SRIO_SP_CS_TX_CMD_SHIFT (0x0000000Du) #define CSL_SRIO_SP_CS_TX_CMD_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_CS_EMB_MASK (0x00001000u) #define CSL_SRIO_SP_CS_TX_CS_EMB_SHIFT (0x0000000Cu) #define CSL_SRIO_SP_CS_TX_CS_EMB_RESETVAL (0x00000000u) #define CSL_SRIO_SP_CS_TX_RESETVAL (0x00000000u) /**************************************************************************\ * Field Definition Macros for Tx Buffer Descriptor \**************************************************************************/ /* TXBUFFDESC (for opt1) */ #define CSL_SRIO_TXBUFFDESC_DEST_ID_MASK (0xFFFF0000u) #define CSL_SRIO_TXBUFFDESC_DEST_ID_SHIFT (0x00000010u) #define CSL_SRIO_TXBUFFDESC_DEST_ID_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_PRI_MASK (0x0000C000u) #define CSL_SRIO_TXBUFFDESC_PRI_SHIFT (0x0000000Eu) #define CSL_SRIO_TXBUFFDESC_PRI_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_TT_MASK (0x00003000u) #define CSL_SRIO_TXBUFFDESC_TT_SHIFT (0x0000000Cu) #define CSL_SRIO_TXBUFFDESC_TT_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_PORT_ID_MASK (0x00000C00u) #define CSL_SRIO_TXBUFFDESC_PORT_ID_SHIFT (0x0000000Au) #define CSL_SRIO_TXBUFFDESC_PORT_ID_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_SSIZE_MASK (0x000003C0u) #define CSL_SRIO_TXBUFFDESC_SSIZE_SHIFT (0x00000006u) #define CSL_SRIO_TXBUFFDESC_SSIZE_RESETVAL (0x00000000u) /*----SSIZE Tokens----*/ #define CSL_SRIO_TXBUFFDESC_SSIZE_128B (0x00000009u) #define CSL_SRIO_TXBUFFDESC_SSIZE_256B (0x0000000Au) #define CSL_SRIO_TXBUFFDESC_SSIZE_512B (0x0000000Bu) #define CSL_SRIO_TXBUFFDESC_SSIZE_1024B (0x0000000Cu) #define CSL_SRIO_TXBUFFDESC_SSIZE_2048B (0x0000000Du) #define CSL_SRIO_TXBUFFDESC_SSIZE_4096B (0x0000000Eu) #define CSL_SRIO_TXBUFFDESC_MAILBOX_MASK (0x0000003Fu) #define CSL_SRIO_TXBUFFDESC_MAILBOX_SHIFT (0x00000000u) #define CSL_SRIO_TXBUFFDESC_MAILBOX_RESETVAL (0x00000000u) /* TXBUFFDESC (for opt2) */ #define CSL_SRIO_TXBUFFDESC_SOP_MASK (0x80000000u) #define CSL_SRIO_TXBUFFDESC_SOP_SHIFT (0x0000001Fu) #define CSL_SRIO_TXBUFFDESC_SOP_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_EOP_MASK (0x40000000u) #define CSL_SRIO_TXBUFFDESC_EOP_SHIFT (0x0000001Eu) #define CSL_SRIO_TXBUFFDESC_EOP_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_MASK (0x20000000u) #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_SHIFT (0x0000001Du) #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_RESETVAL (0x00000000u) /*----OWNERSHIP Tokens----*/ #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_HOST (0x00000000u) #define CSL_SRIO_TXBUFFDESC_OWNERSHIP_PORT (0x00000001u) #define CSL_SRIO_TXBUFFDESC_EOQ_MASK (0x10000000u) #define CSL_SRIO_TXBUFFDESC_EOQ_SHIFT (0x0000001Cu) #define CSL_SRIO_TXBUFFDESC_EOQ_RESETVAL (0x00000000u) /*----EOQ Tokens----*/ #define CSL_SRIO_TXBUFFDESC_EOQ_TRUE (0x00000001u) #define CSL_SRIO_TXBUFFDESC_EOQ_FALSE (0x00000000u) #define CSL_SRIO_TXBUFFDESC_TEARDOWN_MASK (0x08000000u) #define CSL_SRIO_TXBUFFDESC_TEARDOWN_SHIFT (0x0000001Bu) #define CSL_SRIO_TXBUFFDESC_TEARDOWN_RESETVAL (0x00000000u) /*----TEARDOWN Tokens----*/ #define CSL_SRIO_TXBUFFDESC_TEARDOWN_NOT_COMPLETE (0x00000000u) #define CSL_SRIO_TXBUFFDESC_TEARDOWN_COMPLETE (0x00000001u) #define CSL_SRIO_TXBUFFDESC_RESERVED_MASK (0x07FC0000u) #define CSL_SRIO_TXBUFFDESC_RESERVED_SHIFT (0x00000012u) #define CSL_SRIO_TXBUFFDESC_RESERVED_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_RETRY_COUNT_MASK (0x0003F000u) #define CSL_SRIO_TXBUFFDESC_RETRY_COUNT_SHIFT (0x0000000Cu) #define CSL_SRIO_TXBUFFDESC_RETRY_COUNT_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_CC_MASK (0x00000E00u) #define CSL_SRIO_TXBUFFDESC_CC_SHIFT (0x00000009u) #define CSL_SRIO_TXBUFFDESC_CC_RESETVAL (0x00000000u) #define CSL_SRIO_TXBUFFDESC_MESSAGE_LENGTH_MASK (0x000001FFu) #define CSL_SRIO_TXBUFFDESC_MESSAGE_LENGTH_SHIFT (0x00000000u) #define CSL_SRIO_TXBUFFDESC_MESSAGE_LENGTH_RESETVAL (0x00000000u) /**************************************************************************\ * Field Definition Macros for Rx Buffer Descriptor \**************************************************************************/ /* RXBUFFDESC (for opt1) */ #define CSL_SRIO_RXBUFFDESC_SRC_ID_MASK (0xFFFF0000u) #define CSL_SRIO_RXBUFFDESC_SRC_ID_SHIFT (0x00000010u) #define CSL_SRIO_RXBUFFDESC_SRC_ID_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_PRI_MASK (0x0000C000u) #define CSL_SRIO_RXBUFFDESC_PRI_SHIFT (0x0000000Eu) #define CSL_SRIO_RXBUFFDESC_PRI_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_TT_MASK (0x00003000u) #define CSL_SRIO_RXBUFFDESC_TT_SHIFT (0x0000000Cu) #define CSL_SRIO_RXBUFFDESC_TT_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_MAILBOX_MASK (0x0000003Fu) #define CSL_SRIO_RXBUFFDESC_MAILBOX_SHIFT (0x00000000u) #define CSL_SRIO_RXBUFFDESC_MAILBOX_RESETVAL (0x00000000u) /* RXBUFFDESC (option 2) */ #define CSL_SRIO_RXBUFFDESC_SOP_MASK (0x80000000u) #define CSL_SRIO_RXBUFFDESC_SOP_SHIFT (0x0000001Fu) #define CSL_SRIO_RXBUFFDESC_SOP_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_EOP_MASK (0x40000000u) #define CSL_SRIO_RXBUFFDESC_EOP_SHIFT (0x0000001Eu) #define CSL_SRIO_RXBUFFDESC_EOP_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_MASK (0x20000000u) #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_SHIFT (0x0000001Du) #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_RESETVAL (0x00000000u) /*----OWNERSHIP Tokens----*/ #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_HOST (0x00000000u) #define CSL_SRIO_RXBUFFDESC_OWNERSHIP_PORT (0x00000001u) #define CSL_SRIO_RXBUFFDESC_EOQ_MASK (0x10000000u) #define CSL_SRIO_RXBUFFDESC_EOQ_SHIFT (0x0000001Cu) #define CSL_SRIO_RXBUFFDESC_EOQ_RESETVAL (0x00000000u) /*----EOQ Tokens----*/ #define CSL_SRIO_RXBUFFDESC_EOQ_TRUE (0x00000001u) #define CSL_SRIO_RXBUFFDESC_EOQ_FALSE (0x00000000u) #define CSL_SRIO_RXBUFFDESC_TEARDOWN_MASK (0x08000000u) #define CSL_SRIO_RXBUFFDESC_TEARDOWN_SHIFT (0x0000001Bu) #define CSL_SRIO_RXBUFFDESC_TEARDOWN_RESETVAL (0x00000000u) /*----TEARDOWN Tokens----*/ #define CSL_SRIO_RXBUFFDESC_TEARDOWN_NOT_COMPLETE (0x00000000u) #define CSL_SRIO_RXBUFFDESC_TEARDOWN_COMPLETE (0x00000001u) #define CSL_SRIO_RXBUFFDESC_CC_MASK (0x00000E00u) #define CSL_SRIO_RXBUFFDESC_CC_SHIFT (0x00000009u) #define CSL_SRIO_RXBUFFDESC_CC_RESETVAL (0x00000000u) #define CSL_SRIO_RXBUFFDESC_MESSAGE_LENGTH_MASK (0x000001FFu) #define CSL_SRIO_RXBUFFDESC_MESSAGE_LENGTH_SHIFT (0x00000000u) #define CSL_SRIO_RXBUFFDESC_MESSAGE_LENGTH_RESETVAL (0x00000000u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/src/intc/_csl_intcCombEventDispatcher.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /* * @file _csl_intcCombEventDispatcher.c * * @brief File for functional layer of CSL API _CSL_intcEvent0Dispatcher() * * PATH $(CSLPATH)\src\intc */ /* ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * ============================================================================= */ #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /* ============================================================================ * @n@b _CSL_intcEvent0Dispatcher * * @b Description * @n Get the event source of the combiner interrupt0 * * @b Arguments * @n None * * Return Value * @li None * * * @b Example: * @verbatim CSL_IntcParam *param; ... CSL_intcHookIsr(*((CSL_IntcVectId*)param),_CSL_intcEvent0Dispatcher); ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (_CSL_intcEvent0Dispatcher, ".text:csl_section:intc"); interrupt void _CSL_intcEvent0Dispatcher (void) { volatile CSL_BitMask32 evtRcv; Uint32 evtId; Uint32 evtMask ; evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[0]; while (evtRcv) { /* Clear the events */ ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[0] = evtRcv ; evtMask = 1 << 4; evtId = 4; evtRcv &= ~(0xF); do { if (evtRcv & evtMask) { if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE) _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].handler ( _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].arg ); evtRcv &= ~evtMask; } evtMask = evtMask << 1; evtId++; } while (evtRcv); /* Read the MEVTFLAG[0] register */ evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[0]; } } /* ============================================================================ * @n@b _CSL_intcEvent1Dispatcher * * @b Description * @n Get the event source of the combiner interrupt1 * * @b Arguments * @n None * * Return Value * @li None * * * @b Example: * @verbatim CSL_IntcParam *param; ... CSL_intcHookIsr(*((CSL_IntcVectId*)param),_CSL_intcEvent1Dispatcher); ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (_CSL_intcEvent1Dispatcher, ".text:csl_section:intc"); interrupt void _CSL_intcEvent1Dispatcher (void) { volatile CSL_BitMask32 evtRcv; Uint32 evtId; Uint32 evtMask ; /* Read the MEVTFLAG[1] register */ evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[1]; while (evtRcv) { /* Clear the events */ ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[1] = evtRcv ; evtId = 32; evtMask = 1; do { if (evtRcv & evtMask) { if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE) _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].handler ( _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].arg ); evtRcv &= ~evtMask; } evtMask = evtMask << 1; evtId++; } while (evtRcv); /* Read the MEVTFLAG[1] register */ evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[1]; } } /* ============================================================================ * @n@b _CSL_intcEvent2Dispatcher * * @b Description * @n Get the event source of the combiner interrupt2 * * @b Arguments * @n None * * Return Value * @li None * * * @b Example: * @verbatim CSL_IntcParam *param; ... CSL_intcHookIsr(*((CSL_IntcVectId*)param),_CSL_intcEvent2Dispatcher); ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (_CSL_intcEvent2Dispatcher, ".text:csl_section:intc"); interrupt void _CSL_intcEvent2Dispatcher (void) { volatile CSL_BitMask32 evtRcv; Uint32 evtId; Uint32 evtMask ; /* Read the MEVTFLAG[2] register */ evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[2]; while (evtRcv) { /* Clear the events */ ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[2] = evtRcv ; evtId = 64; evtMask = 1; do { if (evtRcv & evtMask) { if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE) _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].handler ( _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].arg ); evtRcv &= ~evtMask; } evtMask = evtMask << 1; evtId++; } while (evtRcv); /* Read the MEVTFLAG[2] register */ evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[2]; } } /* ============================================================================ * @n@b _CSL_intcEvent3Dispatcher * * @b Description * @n Get the event source of the combiner interrupt3 * * @b Arguments * @n None * * Return Value * @li None * * * @b Example: * @verbatim CSL_IntcParam *param; ... CSL_intcHookIsr(*((CSL_IntcVectId*)param),_CSL_intcEvent3Dispatcher); ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (_CSL_intcEvent3Dispatcher, ".text:csl_section:intc"); interrupt void _CSL_intcEvent3Dispatcher (void) { volatile CSL_BitMask32 evtRcv; Uint32 evtId; Uint32 evtMask ; /* Read the MEVTFLAG[3] register */ evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[3]; while (evtRcv) { /* Clear the events */ ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[3] = evtRcv ; evtId = 96; evtMask = 1; do { if (evtRcv & evtMask) { if (_CSL_intcEventOffsetMap[evtId] != CSL_INTC_MAPPED_NONE) _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].handler ( _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[evtId]].arg ); evtRcv &= ~evtMask; } evtMask = evtMask << 1; evtId++; } while (evtRcv); /* Read the MEVTFLAG[3] register */ evtRcv = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEVTFLAG[3]; } }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_vcp2.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_vcp2.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for VCP2 */ /* ============================================================================= * Revision History * ================ * 23-March-2005 SPrasad File created. * * ============================================================================= */ #ifndef _CSLR_VCP2_H_ #define _CSLR_VCP2_H_ #include <cslr.h> #include <tistdtypes.h> /** * Register Overlay Structure for registers accessible through Config bus */ typedef struct { volatile Uint8 RSVD0[24]; volatile Uint32 VCPEXE; volatile Uint8 RSVD1[4]; volatile Uint32 VCPEND; volatile Uint8 RSVD2[28]; volatile Uint32 VCPSTAT0; volatile Uint32 VCPSTAT1; volatile Uint8 RSVD3[8]; volatile Uint32 VCPERR; volatile Uint8 RSVD4[12]; volatile Uint32 VCPEMU; } CSL_Vcp2ConfigRegs; /** * Register Overlay Structure for registers accessible through EDMA bus */ typedef struct { volatile Uint32 VCPIC0; volatile Uint32 VCPIC1; volatile Uint32 VCPIC2; volatile Uint32 VCPIC3; volatile Uint32 VCPIC4; volatile Uint32 VCPIC5; volatile Uint8 RSVD0[48]; volatile Uint32 VCPOUT0; volatile Uint32 VCPOUT1; volatile Uint8 RSVD1[48]; volatile Uint32 VCPWBM; volatile Uint8 RSVD2[60]; volatile Uint32 VCPRDECS; } CSL_Vcp2EdmaRegs; /**************************************************************************\ * Field Definition Macros for registers accessible through config bus \**************************************************************************/ /* VCPEXE */ #define CSL_VCP2_VCPEXE_COMMAND_MASK (0x0000000Fu) #define CSL_VCP2_VCPEXE_COMMAND_SHIFT (0x00000000u) #define CSL_VCP2_VCPEXE_COMMAND_RESETVAL (0x00000000u) /*----COMMAND Tokens----*/ #define CSL_VCP2_VCPEXE_COMMAND_NOCMD (0x00000000u) #define CSL_VCP2_VCPEXE_COMMAND_START (0x00000001u) #define CSL_VCP2_VCPEXE_COMMAND_PAUSE (0x00000002u) #define CSL_VCP2_VCPEXE_COMMAND_RESTART_PAUSE (0x00000003u) #define CSL_VCP2_VCPEXE_COMMAND_RESTART (0x00000004u) #define CSL_VCP2_VCPEXE_COMMAND_STOP (0x00000005u) #define CSL_VCP2_VCPEXE_RESETVAL (0x00000000u) /* VCPEND */ #define CSL_VCP2_VCPEND_SLPZVSS_EN_MASK (0x00000200u) #define CSL_VCP2_VCPEND_SLPZVSS_EN_SHIFT (0x00000009u) #define CSL_VCP2_VCPEND_SLPZVSS_EN_RESETVAL (0x00000001u) /*----SLPZVSS_EN Tokens----*/ #define CSL_VCP2_VCPEND_SLPZVSS_EN_SLEEP_DIS (0x00000000u) #define CSL_VCP2_VCPEND_SLPZVSS_EN_SLPVSS_EN (0x00000001u) #define CSL_VCP2_VCPEND_SLPZVDD_EN_MASK (0x00000100u) #define CSL_VCP2_VCPEND_SLPZVDD_EN_SHIFT (0x00000008u) #define CSL_VCP2_VCPEND_SLPZVDD_EN_RESETVAL (0x00000001u) /*----SLPZVDD_EN Tokens----*/ #define CSL_VCP2_VCPEND_SLPZVDD_EN_SLEEP_DIS (0x00000000u) #define CSL_VCP2_VCPEND_SLPZVDD_EN_SLPVDD_EN (0x00000001u) #define CSL_VCP2_VCPEND_SD_MASK (0x00000002u) #define CSL_VCP2_VCPEND_SD_SHIFT (0x00000001u) #define CSL_VCP2_VCPEND_SD_RESETVAL (0x00000000u) /*----SD Tokens----*/ #define CSL_VCP2_VCPEND_SD_32BIT (0x00000000u) #define CSL_VCP2_VCPEND_SD_NATIVE (0x00000001u) #define CSL_VCP2_VCPEND_BM_MASK (0x00000001u) #define CSL_VCP2_VCPEND_BM_SHIFT (0x00000000u) #define CSL_VCP2_VCPEND_BM_RESETVAL (0x00000000u) /*----BM Tokens----*/ #define CSL_VCP2_VCPEND_BM_32BIT (0x00000000u) #define CSL_VCP2_VCPEND_BM_NATIVE (0x00000001u) #define CSL_VCP2_VCPEND_RESETVAL (0x00000300u) /* VCPSTAT0 */ #define CSL_VCP2_VCPSTAT0_NSYMPROC_MASK (0x1FFFF000u) #define CSL_VCP2_VCPSTAT0_NSYMPROC_SHIFT (0x0000000Cu) #define CSL_VCP2_VCPSTAT0_NSYMPROC_RESETVAL (0x00000000u) #define CSL_VCP2_VCPSTAT0_EMUHALT_MASK (0x00000040u) #define CSL_VCP2_VCPSTAT0_EMUHALT_SHIFT (0x00000006u) #define CSL_VCP2_VCPSTAT0_EMUHALT_RESETVAL (0x00000000u) /*----EMUHALT Tokens----*/ #define CSL_VCP2_VCPSTAT0_EMUHALT_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_EMUHALT_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_OFFUL_MASK (0x00000020u) #define CSL_VCP2_VCPSTAT0_OFFUL_SHIFT (0x00000005u) #define CSL_VCP2_VCPSTAT0_OFFUL_RESETVAL (0x00000000u) /*----OFFUL Tokens----*/ #define CSL_VCP2_VCPSTAT0_OFFUL_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_OFFUL_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_IFEMP_MASK (0x00000010u) #define CSL_VCP2_VCPSTAT0_IFEMP_SHIFT (0x00000004u) #define CSL_VCP2_VCPSTAT0_IFEMP_RESETVAL (0x00000000u) /*----IFEMP Tokens----*/ #define CSL_VCP2_VCPSTAT0_IFEMP_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_IFEMP_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_WIC_MASK (0x00000008u) #define CSL_VCP2_VCPSTAT0_WIC_SHIFT (0x00000003u) #define CSL_VCP2_VCPSTAT0_WIC_RESETVAL (0x00000000u) /*----WIC Tokens----*/ #define CSL_VCP2_VCPSTAT0_WIC_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_WIC_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_ERR_MASK (0x00000004u) #define CSL_VCP2_VCPSTAT0_ERR_SHIFT (0x00000002u) #define CSL_VCP2_VCPSTAT0_ERR_RESETVAL (0x00000000u) /*----ERR Tokens----*/ #define CSL_VCP2_VCPSTAT0_ERR_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_ERR_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_RUN_MASK (0x00000002u) #define CSL_VCP2_VCPSTAT0_RUN_SHIFT (0x00000001u) #define CSL_VCP2_VCPSTAT0_RUN_RESETVAL (0x00000000u) /*----RUN Tokens----*/ #define CSL_VCP2_VCPSTAT0_RUN_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_RUN_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_PAUSE_MASK (0x00000001u) #define CSL_VCP2_VCPSTAT0_PAUSE_SHIFT (0x00000000u) #define CSL_VCP2_VCPSTAT0_PAUSE_RESETVAL (0x00000000u) /*----PAUSE Tokens----*/ #define CSL_VCP2_VCPSTAT0_PAUSE_NO (0x00000000u) #define CSL_VCP2_VCPSTAT0_PAUSE_YES (0x00000001u) #define CSL_VCP2_VCPSTAT0_RESETVAL (0x00000000u) /* VCPSTAT1 */ #define CSL_VCP2_VCPSTAT1_NSYMOF_MASK (0xFFFF0000u) #define CSL_VCP2_VCPSTAT1_NSYMOF_SHIFT (0x00000010u) #define CSL_VCP2_VCPSTAT1_NSYMOF_RESETVAL (0x00000000u) #define CSL_VCP2_VCPSTAT1_NSYMIF_MASK (0x0000FFFFu) #define CSL_VCP2_VCPSTAT1_NSYMIF_SHIFT (0x00000000u) #define CSL_VCP2_VCPSTAT1_NSYMIF_RESETVAL (0x00000000u) #define CSL_VCP2_VCPSTAT1_RESETVAL (0x00000000u) /* VCPERR */ #define CSL_VCP2_VCPERR_E_SYMR_MASK (0x00000040u) #define CSL_VCP2_VCPERR_E_SYMR_SHIFT (0x00000006u) #define CSL_VCP2_VCPERR_E_SYMR_RESETVAL (0x00000000u) /*----E_SYMR Tokens----*/ #define CSL_VCP2_VCPERR_E_SYMR_NO (0x00000000u) #define CSL_VCP2_VCPERR_E_SYMR_YES (0x00000001u) #define CSL_VCP2_VCPERR_E_SYMX_MASK (0x00000020u) #define CSL_VCP2_VCPERR_E_SYMX_SHIFT (0x00000005u) #define CSL_VCP2_VCPERR_E_SYMX_RESETVAL (0x00000000u) /*----E_SYMX Tokens----*/ #define CSL_VCP2_VCPERR_E_SYMX_NO (0x00000000u) #define CSL_VCP2_VCPERR_E_SYMX_YES (0x00000001u) #define CSL_VCP2_VCPERR_MAXMINERR_MASK (0x00000010u) #define CSL_VCP2_VCPERR_MAXMINERR_SHIFT (0x00000004u) #define CSL_VCP2_VCPERR_MAXMINERR_RESETVAL (0x00000000u) /*----MAXMINERR Tokens----*/ #define CSL_VCP2_VCPERR_MAXMINERR_NO (0x00000000u) #define CSL_VCP2_VCPERR_MAXMINERR_YES (0x00000001u) #define CSL_VCP2_VCPERR_FCTLERR_MASK (0x00000008u) #define CSL_VCP2_VCPERR_FCTLERR_SHIFT (0x00000003u) #define CSL_VCP2_VCPERR_FCTLERR_RESETVAL (0x00000000u) /*----FCTLERR Tokens----*/ #define CSL_VCP2_VCPERR_FCTLERR_NO (0x00000000u) #define CSL_VCP2_VCPERR_FCTLERR_YES (0x00000001u) #define CSL_VCP2_VCPERR_FTLERR_MASK (0x00000004u) #define CSL_VCP2_VCPERR_FTLERR_SHIFT (0x00000002u) #define CSL_VCP2_VCPERR_FTLERR_RESETVAL (0x00000000u) /*----FTLERR Tokens----*/ #define CSL_VCP2_VCPERR_FTLERR_NO (0x00000000u) #define CSL_VCP2_VCPERR_FTLERR_YES (0x00000001u) #define CSL_VCP2_VCPERR_TBNAERR_MASK (0x00000002u) #define CSL_VCP2_VCPERR_TBNAERR_SHIFT (0x00000001u) #define CSL_VCP2_VCPERR_TBNAERR_RESETVAL (0x00000000u) /*----TBNAERR Tokens----*/ #define CSL_VCP2_VCPERR_TBNAERR_NO (0x00000000u) #define CSL_VCP2_VCPERR_TBNAERR_YES (0x00000001u) #define CSL_VCP2_VCPERR_ERROR_MASK (0x00000001u) #define CSL_VCP2_VCPERR_ERROR_SHIFT (0x00000000u) #define CSL_VCP2_VCPERR_ERROR_RESETVAL (0x00000000u) /*----ERROR Tokens----*/ #define CSL_VCP2_VCPERR_ERROR_NO (0x00000000u) #define CSL_VCP2_VCPERR_ERROR_YES (0x00000001u) #define CSL_VCP2_VCPERR_RESETVAL (0x00000000u) /* VCPEMU */ #define CSL_VCP2_VCPEMU_SOFT_MASK (0x00000002u) #define CSL_VCP2_VCPEMU_SOFT_SHIFT (0x00000001u) #define CSL_VCP2_VCPEMU_SOFT_RESETVAL (0x00000000u) /*----SOFT Tokens----*/ #define CSL_VCP2_VCPEMU_SOFT_HALT_DEFAULT (0x00000000u) #define CSL_VCP2_VCPEMU_SOFT_HALT_FRAMEEND (0x00000001u) #define CSL_VCP2_VCPEMU_FREE_MASK (0x00000001u) #define CSL_VCP2_VCPEMU_FREE_SHIFT (0x00000000u) #define CSL_VCP2_VCPEMU_FREE_RESETVAL (0x00000000u) /*----FREE Tokens----*/ #define CSL_VCP2_VCPEMU_FREE_SOFT_EN (0x00000000u) #define CSL_VCP2_VCPEMU_FREE_FREE (0x00000001u) #define CSL_VCP2_VCPEMU_RESETVAL (0x00000000u) /**************************************************************************\ * Field Definition Macros for registers accessible through EDMA bus \**************************************************************************/ /* VCPIC0 */ #define CSL_VCP2_VCPIC0_POLY3_MASK (0xFF000000u) #define CSL_VCP2_VCPIC0_POLY3_SHIFT (0x00000018u) #define CSL_VCP2_VCPIC0_POLY3_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC0_POLY2_MASK (0x00FF0000u) #define CSL_VCP2_VCPIC0_POLY2_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC0_POLY2_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC0_POLY1_MASK (0x0000FF00u) #define CSL_VCP2_VCPIC0_POLY1_SHIFT (0x00000008u) #define CSL_VCP2_VCPIC0_POLY1_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC0_POLY0_MASK (0x000000FFu) #define CSL_VCP2_VCPIC0_POLY0_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC0_POLY0_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC0_RESETVAL (0x00000000u) /* VCPIC1 */ #define CSL_VCP2_VCPIC1_YAMEN_MASK (0x10000000u) #define CSL_VCP2_VCPIC1_YAMEN_SHIFT (0x0000001Cu) #define CSL_VCP2_VCPIC1_YAMEN_RESETVAL (0x00000000u) /*----YAMEN Tokens----*/ #define CSL_VCP2_VCPIC1_YAMEN_DISABLE (0x00000000u) #define CSL_VCP2_VCPIC1_YAMEN_ENABLE (0x00000001u) #define CSL_VCP2_VCPIC1_YAMT_MASK (0x0FFF0000u) #define CSL_VCP2_VCPIC1_YAMT_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC1_YAMT_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC1_RESETVAL (0x00000000u) /* VCPIC2 */ #define CSL_VCP2_VCPIC2_R_MASK (0xFFFF0000u) #define CSL_VCP2_VCPIC2_R_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC2_R_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC2_FL_MASK (0x0000FFFFu) #define CSL_VCP2_VCPIC2_FL_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC2_FL_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC2_RESETVAL (0x00000000u) /* VCPIC3 */ #define CSL_VCP2_VCPIC3_OUT_ORDER_MASK (0x10000000u) #define CSL_VCP2_VCPIC3_OUT_ORDER_SHIFT (0x0000001Cu) #define CSL_VCP2_VCPIC3_OUT_ORDER_RESETVAL (0x00000000u) /*----OUT_ORDER Tokens----*/ #define CSL_VCP2_VCPIC3_OUT_ORDER_LSB (0x00000000u) #define CSL_VCP2_VCPIC3_OUT_ORDER_MSB (0x00000001u) #define CSL_VCP2_VCPIC3_ITBEN_MASK (0x01000000u) #define CSL_VCP2_VCPIC3_ITBEN_SHIFT (0x00000018u) #define CSL_VCP2_VCPIC3_ITBEN_RESETVAL (0x00000000u) /*----ITBEN Tokens----*/ #define CSL_VCP2_VCPIC3_ITBEN_DISABLE (0x00000000u) #define CSL_VCP2_VCPIC3_ITBEN_ENABLE (0x00000001u) #define CSL_VCP2_VCPIC3_ITBI_MASK (0x00FF0000u) #define CSL_VCP2_VCPIC3_ITBI_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC3_ITBI_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC3_C_MASK (0x0000FFFFu) #define CSL_VCP2_VCPIC3_C_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC3_C_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC3_RESETVAL (0x00000000u) /* VCPIC4 */ #define CSL_VCP2_VCPIC4_IMINS_MASK (0x1FFF0000u) #define CSL_VCP2_VCPIC4_IMINS_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC4_IMINS_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC4_IMAXS_MASK (0x00001FFFu) #define CSL_VCP2_VCPIC4_IMAXS_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC4_IMAXS_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC4_RESETVAL (0x00000000u) /* VCPIC5 */ #define CSL_VCP2_VCPIC5_SDHD_MASK (0x80000000u) #define CSL_VCP2_VCPIC5_SDHD_SHIFT (0x0000001Fu) #define CSL_VCP2_VCPIC5_SDHD_RESETVAL (0x00000000u) /*----SDHD Tokens----*/ #define CSL_VCP2_VCPIC5_SDHD_HARD (0x00000000u) #define CSL_VCP2_VCPIC5_SDHD_SOFT (0x00000001u) #define CSL_VCP2_VCPIC5_OUTF_MASK (0x40000000u) #define CSL_VCP2_VCPIC5_OUTF_SHIFT (0x0000001Eu) #define CSL_VCP2_VCPIC5_OUTF_RESETVAL (0x00000000u) /*----OUTF Tokens----*/ #define CSL_VCP2_VCPIC5_OUTF_NO (0x00000000u) #define CSL_VCP2_VCPIC5_OUTF_YES (0x00000001u) #define CSL_VCP2_VCPIC5_TB_MASK (0x30000000u) #define CSL_VCP2_VCPIC5_TB_SHIFT (0x0000001Cu) #define CSL_VCP2_VCPIC5_TB_RESETVAL (0x00000000u) /*----TB Tokens----*/ #define CSL_VCP2_VCPIC5_TB_NO (0x00000000u) #define CSL_VCP2_VCPIC5_TB_TAIL (0x00000001u) #define CSL_VCP2_VCPIC5_TB_CONV (0x00000002u) #define CSL_VCP2_VCPIC5_TB_MIX (0x00000003u) #define CSL_VCP2_VCPIC5_SYMR_MASK (0x01F00000u) #define CSL_VCP2_VCPIC5_SYMR_SHIFT (0x00000014u) #define CSL_VCP2_VCPIC5_SYMR_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC5_SYMX_MASK (0x000F0000u) #define CSL_VCP2_VCPIC5_SYMX_SHIFT (0x00000010u) #define CSL_VCP2_VCPIC5_SYMX_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC5_IMAXI_MASK (0x000000FFu) #define CSL_VCP2_VCPIC5_IMAXI_SHIFT (0x00000000u) #define CSL_VCP2_VCPIC5_IMAXI_RESETVAL (0x00000000u) #define CSL_VCP2_VCPIC5_RESETVAL (0x00000000u) /* VCPOUT0 */ #define CSL_VCP2_VCPOUT0_FMINS_MASK (0x1FFF0000u) #define CSL_VCP2_VCPOUT0_FMINS_SHIFT (0x00000010u) #define CSL_VCP2_VCPOUT0_FMINS_RESETVAL (0x00000000u) #define CSL_VCP2_VCPOUT0_FMAXS_MASK (0x00001FFFu) #define CSL_VCP2_VCPOUT0_FMAXS_SHIFT (0x00000000u) #define CSL_VCP2_VCPOUT0_FMAXS_RESETVAL (0x00000000u) #define CSL_VCP2_VCPOUT0_RESETVAL (0x00000000u) /* VCPOUT1 */ #define CSL_VCP2_VCPOUT1_YAM_MASK (0x00010000u) #define CSL_VCP2_VCPOUT1_YAM_SHIFT (0x00000010u) #define CSL_VCP2_VCPOUT1_YAM_RESETVAL (0x00000000u) /*----YAM Tokens----*/ #define CSL_VCP2_VCPOUT1_YAM_NO (0x00000000u) #define CSL_VCP2_VCPOUT1_YAM_YES (0x00000001u) #define CSL_VCP2_VCPOUT1_FMAXI_MASK (0x000000FFu) #define CSL_VCP2_VCPOUT1_FMAXI_SHIFT (0x00000000u) #define CSL_VCP2_VCPOUT1_FMAXI_RESETVAL (0x00000000u) #define CSL_VCP2_VCPOUT1_RESETVAL (0x00000000u) /* VCPWBM */ #define CSL_VCP2_VCPWBM_WRITE_MASK (0xFFFFFFFFu) #define CSL_VCP2_VCPWBM_WRITE_SHIFT (0x00000000u) #define CSL_VCP2_VCPWBM_WRITE_RESETVAL (0x00000000u) #define CSL_VCP2_VCPWBM_RESETVAL (0x00000000u) /* VCPRDECS */ #define CSL_VCP2_VCPRDECS_READ_MASK (0xFFFFFFFFu) #define CSL_VCP2_VCPRDECS_READ_SHIFT (0x00000000u) #define CSL_VCP2_VCPRDECS_READ_RESETVAL (0x00000000u) #define CSL_VCP2_VCPRDECS_RESETVAL (0x00000000u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcGetHwStatus.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** @file csl_pllcGetHwStatus.c * * @brief File for functional layer of CSL API @a CSL_pllcGetHwStatus() * * Path: \(CSLPATH)\src\pllc */ /* ============================================================================ * Revision History * =============== * 25-Aug-2005 Tej File Created. * 27-oct-2005 sd changes for multiplier configuration * 18-Jan-2006 sd Changes according to spec changes * ============================================================================ */ #include <csl_pllc.h> #include <csl_pllcAux.h> /** ============================================================================ * @n@b CSL_pllcGetHwStatus * * @b Description * @n Gets the status of the different operations of PLLC. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance query The query to this API of PLLC which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVQUERY - Invalid query command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcHwStatusQuery query = CSL_PLLC_QUERY_STATUS; CSL_BitMask32 reponse; ... status = CSL_pllcGetHwStatus (hPllc, query, &response); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_pllcGetHwStatus, ".text:csl_section:pllc"); CSL_Status CSL_pllcGetHwStatus ( CSL_PllcHandle hPllc, CSL_PllcHwStatusQuery query, void *response ) { CSL_Status status = CSL_SOK; if (hPllc == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (query) { /* Query for GOSTAT bit in PLLSTAT register*/ case CSL_PLLC_QUERY_STATUS: *(CSL_BitMask32*) response = CSL_pllcGetStatus (hPllc); break; /* Query for SYSnOn bits SYSSTAT register*/ case CSL_PLLC_QUERY_SYSCLKSTAT: *(CSL_BitMask32*) response = CSL_pllcGetSysClkStatus (hPllc); break; /* Query for status of RSTYPE register*/ case CSL_PLLC_QUERY_RESETSTAT: if (hPllc->pllcNum == CSL_PLLC_1) *(CSL_BitMask32*) response = CSL_pllcGetResetStatus (hPllc); else status = CSL_ESYS_INVPARAMS; break; default: status = CSL_ESYS_INVQUERY; break; } } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrGetHwStatus.c

<filename>DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrGetHwStatus.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** =========================================================================== * @file csl_tmrGetHwStatus.c * * @brief File for functional layer of CSL API CSL_tmrGetHwStatus() * * @path $(CSLPATH)\src\timer * * @desc The CSL_tmrGetHwStatus() function definition & it's associated * functions * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 1-Sept-2004 HMM File Created. * 29-Jul-2005 PSK updted changes acooriding to revised timer spec. the number * convention TIM12, TIM34 are changed to TIMLO and TIMHI. * ============================================================================ */ #include <csl_tmr.h> #include <csl_tmrAux.h> /** =========================================================================== * @n@b CSL_tmrGetHwStatus * * @b Description * @n This function is used to get the value of various parameters of the * timer instance. The value returned depends on the query passed. * * @b Arguments * @verbatim hTmr Handle to the timer instance query Query to be performed response Pointer to buffer to return the data requested by the query passed @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Successful completion of the * query * * @li CSL_ESYS_BADHANDLE - Invalid handle * * @li CSL_ESYS_INVQUERY - Query command not supported * * @li CSL_ESYS_INVPARAMS - Invalid Parameter * * Pre Condition * @n None * * Post Condition * Data requested by the query is returned through the variable "response" * * @b Modifies * @n The input arguement "response" is modified * * @b Example * @verbatim CSL_status status; Uint8 hwRevId; ... status = CSL_tmrGetHwStatus(hGptimer, CSL_TMR_QUERY_COUNT_LO, &hwRevId); ... @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_tmrGetHwStatus, ".text:csl_section:tmr"); CSL_Status CSL_tmrGetHwStatus ( CSL_TmrHandle hTmr, CSL_TmrHwStatusQuery query, void *response ) { CSL_Status status = CSL_SOK; if (hTmr == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (query) { case CSL_TMR_QUERY_COUNT_LO: CSL_tmrGetTimLoCount(hTmr, (Uint32 *)response); break; case CSL_TMR_QUERY_COUNT_HI: CSL_tmrGetTimHiCount(hTmr, (Uint32 *)response); break; case CSL_TMR_QUERY_TSTAT_LO: *((CSL_TmrTstat *)response) = CSL_tmrGetTstatLoStatus(hTmr); break; case CSL_TMR_QUERY_TSTAT_HI: *((CSL_TmrTstat *)response) = CSL_tmrGetTstatHiStatus(hTmr); break; case CSL_TMR_QUERY_WDFLAG_STATUS: *((CSL_TmrWdflagBitStatus*)response) = CSL_tmrGetWdflagStatus(hTmr); break; default: status = CSL_ESYS_INVQUERY; break; } } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/srio/csl_srioInit.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ========================================================================== */ /** =========================================================================== * @file csl_srioInit.c * * @brief File for functional layer of CSL API CSL_srioInit() * * @path $(CSLPATH)\srio\src * * @desc The CSL_srioInit() function definition and it's associated * functions * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 20-Aug-2005 PSK File Created. * ============================================================================ */ #include <csl_srio.h> /** ============================================================================ * @n@b CSL_srioInit * * @b Description * @n This is the initialization function for the SRIO CSL. * The function must be called before calling any other API from this CSL. * This function is idem-potent. Currently, the function just return * status CSL_SOK, without doing anything. * * @b Arguments * @verbatim pContext Pointer to module-context. As SRIO doesn't have any context based information user is expected to pass NULL. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n None * * Post Condition * @n The CSL for SRIO is initialized * * @b Modifies * @n None * * @b Example * @verbatim CSL_Status status; ... status = CSL_srioInit(NULL); ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_srioInit, ".text:csl_section:srio"); CSL_Status CSL_srioInit ( CSL_SrioContext *pContext ) { return (CSL_SOK); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3Init.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_edma3Init.c * * @path $(CSLPATH)\src\edma * * @desc File for functional layer of CSL API CSL_edma3Init () * */ /* ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= */ #include <csl_edma3.h> /** ============================================================================ * @n@b CSL_edma3Init * * @b Description * @n This is the initialization function for the edma CSL. The function must * be called before calling any other API from this CSL.This function is * idem-potent. Currently, the function just return status CSL_SOK, * without doing anything. * * @b Arguments @verbatim pContext Pointer to module-context. As edma doesn't have any context based information user is expected to pass NULL. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n None * * Post Condition * @n The CSL for EDMA is initialized * * @b Modifies * @n None * * @b Example * @verbatim ... if (CSL_edma3Init(NULL) != CSL_SOK) { exit; } @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3Init, ".text:csl_section:edma3"); CSL_Status CSL_edma3Init ( CSL_Edma3Context *pContext ) { return CSL_SOK; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcPlugEventHandler.c

<filename>DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcPlugEventHandler.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_intcPlugEventHandler.c * * @brief File for functional layer of CSL API @a CSL_intcPlugEventHandler() * * PATH $(CSLPATH)\src\intc * */ /* ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= */ #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /** ============================================================================ * @n@b CSL_intcPlugEventHandler * * @b Description * @n Associate an event-handler with an event * CSL_intcPlugEventHandler(..) ties an event-handler to an event; so * that the occurence of the event, would result in the event-handler * being invoked. * * @b Arguments * @verbatim hIntc Intc handle identifies the interrupt-event eventHandlerRecord Provides the details of the event-handler @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Succussful completion of PlugEventHandler * @li CSL_ESYS_FAIL - Non completion of PlugEventHandler * * @b Example: * @verbatim CSL_IntcObj intcObj20; CSL_IntcGlobalEnableState state; CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; context.numEvtEntries = 0; context.eventhandlerRecord = NULL; // Init Module CSL_intcInit(&context); // NMI Enable CSL_intcGlobalNmiEnable(); // Enable Global Interrupts intStat = CSL_intcGlobalEnable(&state); // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL); EventRecord.handler = &event20Handler; EventRecord.arg = hIntc20; CSL_intcPlugEventHandler(hIntc20,&EventRecord); // Close handle CSL_IntcClose(hIntc20); } void event20Handler( CSL_IntcHandle hIntc) { } @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_intcPlugEventHandler, ".text:csl_section:intc"); CSL_Status CSL_intcPlugEventHandler ( CSL_IntcHandle hIntc, CSL_IntcEventHandlerRecord *eventHandlerRecord ) { volatile Uint16 i; CSL_Status status = CSL_ESYS_FAIL; asm(" dint"); /* Search for free entry and plug in handler */ for (i = 0; i < _CSL_intcNumEvents; i++) { if (_CSL_intcEventHandlerRecord[i].handler == CSL_INTC_EVTHANDLER_NONE){ /* Plug in Handler */ _CSL_intcEventHandlerRecord[i].handler = eventHandlerRecord->handler; _CSL_intcEventHandlerRecord[i].arg = eventHandlerRecord->arg; /* Establish mapping */ _CSL_intcEventOffsetMap[hIntc->eventId] = i; status = CSL_SOK; break; } } asm(" rint"); return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcHwControl.c

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** @file csl_pllcHwControl.c * * @brief File for functional layer of CSL API @a CSL_pllcHwControl() * * Path: \(CSLPATH)\src\pllc */ /* ============================================================================ * Revision History * =============== * 25-Aug-2005 Tej File Created. * 18-Jan-2006 sd Changes according to spec changes * ============================================================================ */ #include <csl_pllc.h> #include <csl_pllcAux.h> /** ============================================================================ * @n@b CSL_pllcHwControl * * @b Description * @n Takes a command of PLLC with an optional argument & implements it. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance cmd The command to this API indicates the action to be taken on PLLC. arg An optional argument. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n To change PLLM, PREDIV & PLLDIVn, PLLCTL_PLLEN bit must be in BYPASS * * Post Condition * @n None * * @b Modifies * @n The hardware registers of PLLC. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcHwControlCmd cmd = CSL_PLLC_CMD_SET_PLLM; void arg = 0x7; ... status = CSL_pllcHwControl (hPllc, cmd, &arg); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_pllcHwControl, ".text:csl_section:pllc"); CSL_Status CSL_pllcHwControl ( CSL_PllcHandle hPllc, CSL_PllcHwControlCmd cmd, void *arg ) { CSL_Status status = CSL_SOK; if (hPllc == NULL) { status = CSL_ESYS_BADHANDLE; } else if (arg == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (cmd) { /* cmd to change PLLCTL and PLLCMD register of PLL controller */ case CSL_PLLC_CMD_PLLCONTROL: CSL_pllcCommandCtrl (hPllc, *(CSL_BitMask32*)arg, &status); break; /* cmd to change PLLM register of PLL controller */ case CSL_PLLC_CMD_SET_PLLM: CSL_pllcMultiplierCtrl (hPllc, *(Uint32*)arg, &status); break; /* cmd to change PLLDIVn_RATIO of PLLDIVn register */ case CSL_PLLC_CMD_SET_PLLRATIO: CSL_pllcSetPLLDivRatio (hPllc, *(CSL_PllcDivRatio*) arg, &status); break; /* cmd to change PLLDIVn_DnEN of PLLDIVn register */ case CSL_PLLC_CMD_PLLDIV_CONTROL: CSL_pllcPLLDivCtrl (hPllc, *(CSL_PllcDivideControl*) arg, &status); break; default: status = CSL_ESYS_INVCMD; break; } } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_gpio.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * provided * ============================================================================ */ /** =========================================================================== * @file csl_gpio.h * * @path $(CSLPATH)\inc * * @desc GPIO functional layer APIs header file. The different enumerations, * structure definitions and function declarations * ============================================================================ * @mainpage GPIO CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the GPIO module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given GPIO module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular GPIO Module.The CSL developer should use his discretion designing * new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 *============================================================================= */ /* ============================================================================ * Revision History * =============== * 11-Jun-2004 PGR file created * 04-sep-2004 Nsr - Updated CSL_GpioObj and added CSL_GpioBaseAddress, * CSL_GpioParam, SL_GpioContext, CSL_GpioConfig structures. * - Updated comments for H/W control cmd and status query * enums. * - Added prototypes for CSL_gpioGetBaseAdddress and * CSL_gpioHwSetupRaw. * - Changed prototypes of CSL_gpioInit, CSL_gpioOpen. * - Updated respective comments along with that of * CSL_gpioClose. * 11-Oct-2004 Nsr - Removed the extern keyword before function declaration and * - Changed this file according to review. * 22-Feb-2005 Nsr - Added control command CSL_GPIO_CMD_GET_BIT according to * TI issue PSG00000310. * 28-Jul-2005 PSK - Updated the CSL source to support only one BANK * * 11-Jan-2006 NG - Added CSL_GPIO_CMD_SET_OUT_BIT Control Command * 06-Mar-2006 ds - Rename CSL_GPIO_CMD_SET_OUT_BIT to * CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT * - Moved CSL_GpioPinNum Enumeration from the cslr_gpio.h * ============================================================================ */ #ifndef _CSL_GPIO_H_ #define _CSL_GPIO_H_ #ifdef __cplusplus extern "C" { #endif #include <soc.h> #include <csl.h> #include <cslr_gpio.h> /**< Invalid argument */ #define CSL_EGPIO_INVPARAM CSL_EGPIO_FIRST /*****************************************************************************\ GPIO global typedef declarations \*****************************************************************************/ /** * \brief Base-address of the Configuration registers of GPIO. */ typedef struct { /** Base-address of the configuration registers of the peripheral */ CSL_GpioRegsOvly regs; } CSL_GpioBaseAddress; /** * \brief GPIO specific parameters. Present implementation doesn't have * any specific parameters. */ typedef struct { /** Bit mask to be used for module specific parameters. * The below declaration is just a place-holder for future * implementation. */ CSL_BitMask16 flags; } CSL_GpioParam; /** \brief GPIO specific context information. Present implementation doesn't * have any Context information. */ typedef struct { /** Context information of GPIO. * The below declaration is just a place-holder for future * implementation. */ Uint16 contextInfo; } CSL_GpioContext; /** * @brief Config structure of GPIO. This is used to configure GPIO * using CSL_HwSetupRaw function */ typedef struct { /** GPIO Interrupt Per-Bank Enable Register */ volatile Uint32 BINTEN; /** GPIO Direction Register */ volatile Uint32 DIR; /** GPIO Output Data Register */ volatile Uint32 OUT_DATA; /** GPIO Set Data Register */ volatile Uint32 SET_DATA; /** GPIO Clear Data Register */ volatile Uint32 CLR_DATA; /** GPIO Set Rising Edge Interrupt Register */ volatile Uint32 SET_RIS_TRIG; /** GPIO Clear Rising Edge Interrupt Register */ volatile Uint32 CLR_RIS_TRIG; /** GPIO Set Falling Edge Interrupt Register */ volatile Uint32 SET_FAL_TRIG; /** GPIO Clear Falling Edge Interrupt Register */ volatile Uint32 CLR_FAL_TRIG; } CSL_GpioConfig; /** @brief Default Values for GPIO Config structure */ #define CSL_GPIO_CONFIG_DEFAULTS { \ CSL_GPIO_BINTEN_RESETVAL , \ CSL_GPIO_DIR_RESETVAL, \ CSL_GPIO_OUT_DATA_RESETVAL, \ CSL_GPIO_SET_DATA_RESETVAL, \ CSL_GPIO_CLR_DATA_RESETVAL, \ CSL_GPIO_SET_RIS_TRIG_RESETVAL, \ CSL_GPIO_CLR_RIS_TRIG_RESETVAL, \ CSL_GPIO_SET_FAL_TRIG_RESETVAL, \ CSL_GPIO_CLR_FAL_TRIG_RESETVAL, \ } /** Enumeration used for specifying the GPIO pin numbers */ typedef enum { /** Gpio pin 0 */ CSL_GPIO_PIN0, /** Gpio pin 1 */ CSL_GPIO_PIN1, /** Gpio pin 2 */ CSL_GPIO_PIN2, /** Gpio pin 3 */ CSL_GPIO_PIN3, /** Gpio pin 4 */ CSL_GPIO_PIN4, /** Gpio pin 5 */ CSL_GPIO_PIN5, /** Gpio pin 6 */ CSL_GPIO_PIN6, /** Gpio pin 7 */ CSL_GPIO_PIN7, /** Gpio pin 8 */ CSL_GPIO_PIN8, /** Gpio pin 0 */ CSL_GPIO_PIN9, /** Gpio pin 10 */ CSL_GPIO_PIN10, /** Gpio pin 11 */ CSL_GPIO_PIN11, /** Gpio pin 12 */ CSL_GPIO_PIN12, /** Gpio pin 13 */ CSL_GPIO_PIN13, /** Gpio pin 14 */ CSL_GPIO_PIN14, /** Gpio pin 15 */ CSL_GPIO_PIN15 } CSL_GpioPinNum; /**\brief Enums for configuring GPIO pin direction * */ typedef enum { CSL_GPIO_DIR_OUTPUT,/**<: Output pin*/ CSL_GPIO_DIR_INPUT /**<: Input pin*/ } CSL_GpioDirection; /** \brief Enums for configuring GPIO pin edge detection * */ typedef enum { /**<: No edge detection */ CSL_GPIO_TRIG_CLEAR_EDGE, /**<: Rising edge detection */ CSL_GPIO_TRIG_RISING_EDGE, /**<: Falling edge detection */ CSL_GPIO_TRIG_FALLING_EDGE, /**<: Dual edge detection */ CSL_GPIO_TRIG_DUAL_EDGE } CSL_GpioTriggerType; /** \brief Enumeration for control commands passed to \a CSL_gpioHwControl() * * This is the set of commands that are passed to the \a CSL_gpioHwControl() * with an optional argument type-casted to \a void* . * The arguments to be passed with each enumeration (if any) are specified * next to the enumeration */ typedef enum { /** * @brief Enables interrupt on bank * @param ( None ) */ CSL_GPIO_CMD_BANK_INT_ENABLE = 0, /** * @brief Disables interrupt on bank * @param ( None ) */ CSL_GPIO_CMD_BANK_INT_DISABLE = 1, /** * @brief Configures GPIO pin direction and edge detection properties * @param ( CSL_GpioPinConfig ) */ CSL_GPIO_CMD_CONFIG_BIT = 2, /** * @brief Changes output state of GPIO pin to logic-1 * @param ( CSL_GpioPinNum ) */ CSL_GPIO_CMD_SET_BIT = 3, /** * @brief Changes output state of GPIO pin to logic-0 * @param ( CSL_GpioPinNum ) */ CSL_GPIO_CMD_CLEAR_BIT = 4, /** * @brief Gets the state of input pins on bank * The "data" field act as output parameter reporting * the input state of the GPIO pins on the bank. * @param ( CSL_BitMask16*) */ CSL_GPIO_CMD_GET_INPUTBIT = 5, /** * @brief Gets the state of output pins on bank. * The "data" field act as output parameter reporting the * output drive state of the GPIO pins on the bank * @param ( CSL_BitMask16* ) */ CSL_GPIO_CMD_GET_OUTDRVSTATE = 6, /** * @brief Gets the state of input pin on bank. * @param ( CSL_GpioPinData * ) */ CSL_GPIO_CMD_GET_BIT = 7, /** * @brief Changes output state of GPIO pin to logic-1 * @param ( CSL_GpioPinData *) */ CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT = 8 } CSL_GpioHwControlCmd; /** \brief Enumeration for queries passed to \a CSL_GpioGetHwStatus() * * This is used to get the status of different operations.The arguments * to be passed with each enumeration if any are specified next to * the enumeration */ typedef enum { /** * @brief Queries GPIO bank interrupt enable status * @param ( CSL_BitMask16* ) */ CSL_GPIO_QUERY_BINTEN_STAT = 2 } CSL_GpioHwStatusQuery; /** \brief Input parameters for configuring a GPIO pin * This is used to configure the direction and edge detection */ typedef struct { /**< Pin number for GPIO bank */ CSL_GpioPinNum pinNum; /**< Direction for GPIO Pin */ CSL_GpioDirection direction; /**< GPIO pin edge detection */ CSL_GpioTriggerType trigger; } CSL_GpioPinConfig; /**\brief this is used for getting a specific pin staus */ typedef struct { /**< Pin number for GPIO bank */ CSL_GpioPinNum pinNum; /** pin value */ Int16 pinVal; } CSL_GpioPinData; /** \brief Input parameters for setting up GPIO during startup * * This is just a placeholder as GPIO is a simple module, which doesn't * require any setup */ typedef struct { /** The extendSetup is just a place-holder for future * implementation. */ void *extendSetup; } CSL_GpioHwSetup; /** \brief This object contains the reference to the instance of GPIO * opened using the @a CSL_gpioOpen() * * The pointer to this is passed to all GPIO CSL APIs * This structure has the fields required to configure GPIO for any test * case/application. It should be initialized as per requirements of a * test case/application and passed on to the setup function */ typedef struct CSL_GpioObj { /**< This is a pointer to the registers of the * instance of GPIO referred to by this object */ CSL_GpioRegsOvly regs; /**< This is the instance of GPIO being referred to * by this object */ CSL_InstNum gpioNum; /**< This is the maximum number of pins supported by this * instance of GPIO */ Uint8 numPins; } CSL_GpioObj; /** \brief this is a pointer to @a CSL_GpioObj and is passed as the first * parameter to all GPIO CSL APIs */ typedef CSL_GpioObj *CSL_GpioHandle; /*****************************************************************************\ CSL3.x mandatory function prototype definitions \*****************************************************************************/ /** =========================================================================== * @n@b CSL_gpioInit * * @b Description * @n This is the initialization function for the GPIO. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. * * @b Arguments * @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... CSL_gpioInit(); @endverbatim * =========================================================================== */ CSL_Status CSL_gpioInit( CSL_GpioContext *pContext ); /** ============================================================================ * @n@b CSL_gpioOpen * * @b Description * @n This function populates the peripheral dgpio object for the GPIO instance * and returns a handle to the instance. * The open call sets up the dgpio structures for the particular instance * of GPIO device. The device can be re-opened anytime after it has been * normally closed if so required. The handle returned by this call is * input as an essential argument for rest of the APIs described * for this module. * * @b Arguments * @verbatim pGpioObj Pointer to the GPIO instance object gpioNum Instance of the GPIO to be opened pGpioParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * Return Value CSL_GpioHandle * @n Valid GPIO instance handle will be returned if status value is equal to CSL_SOK. * * Pre Condition * @n None * * Post Condition * @n 1. GPIO object structure is populated * @n 2. The status is returned in the status variable. If status * returned is * @li CSL_SOK Valid gpio handle is returned * @li CSL_ESYS_FAIL The gpio instance is invalid * @li CSL_ESYS_INVPARAMS Invalid parameter * * @b Modifies * @n 1. The status variable * @n 2. GPIO object structure * * @b Example * @verbatim CSL_status status; CSL_GpioObj gpioObj; CSL_GpioHandle hGpio; ... hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO_PER_CNT, NULL, &status); ... @endverbatim * ============================================================================= */ CSL_GpioHandle CSL_gpioOpen ( CSL_GpioObj *hGpioObj, CSL_InstNum gpioNum, CSL_GpioParam *pGpioParam, CSL_Status *status ); /** ============================================================================ * @n@b CSL_gpioClose * * @b Description * @n This function closes the specified instance of GPIO. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Close successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_status status; ... status = CSL_gpioClose(hGpio); @endverbatim * ============================================================================= */ CSL_Status CSL_gpioClose ( CSL_GpioHandle hGpio ); /** ============================================================================ * @n@b CSL_gpioHwSetup * * @b Description * @n It configures the gpio registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance hwSetup Pointer to harware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @b Modifies * @n The hardware registers of GPIO. * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioObj gpioObj; CSL_GpioHwSetup hwSetup; CSL_status status; ... hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO_PRIMARY, NULL, &status); status = CSL_gpioHwSetup(hGpio, &hwSetup); @endverbatim * ============================================================================= */ CSL_Status CSL_gpioHwSetup ( CSL_GpioHandle hGpio, CSL_GpioHwSetup *setup ); /** =========================================================================== * @n@b CSL_gpioHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hGpio Handle to the Gpio instance config Pointer to config structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not * properly initialized * * Pre Condition * @n None * * Post Condition * @n The registers of the specified GPIO instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified GPIO instance. * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioConfig config = CSL_GPIO_CONFIG_DEFAULTS; CSL_Status status; status = CSL_gpioHwSetupRaw(hGpio, &config); @endverbatim * =========================================================================== */ CSL_Status CSL_gpioHwSetupRaw ( CSL_GpioHandle hGpio, CSL_GpioConfig *config ); /** ============================================================================ * @n@b CSL_gpioGetHwSetup * * @b Description * @n Gets the current setup of GPIO. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance setup Pointer to setup structure which contains the setup information of GPIO. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Setup info load successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n None * * Post Condition * @n The registers of the specified GPIO instance will be setup. * * @b Modifies * @n Hardware registers of the specified GPIO instance. * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioHwSetup setup; CSL_Status status; status = CSL_gpioGetHwSetup(hGpio, &setup); @endverbatim * ============================================================================= */ CSL_Status CSL_gpioGetHwSetup ( CSL_GpioHandle hGpio, CSL_GpioHwSetup *setup ); /** ============================================================================ * @n@b CSL_gpioHwControl * * @b Description * @n Takes a command of GPIO with an optional argument & implements it. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance cmd The command to this API indicates the action to be taken on GPIO. arg An optional argument. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_FAIL - Invalid instance number * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n The hardware registers of GPIO. * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioHwControlCmd cmd; void arg; status = CSL_gpioHwControl(hGpio, cmd, &arg); @endverbatim * ============================================================================= */ CSL_Status CSL_gpioHwControl ( CSL_GpioHandle hGpio, CSL_GpioHwControlCmd cmd, void *arg ); /** ============================================================================ * @n@b CSL_gpioGetHwStatus * * @b Description * @n Gets the status of the different operations of GPIO. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance query The query to this API of GPIO which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_GpioHwStatusQuery query; void reponse; status = CSL_gpioGetHwStatus(hGpio, query, &response); @endverbatim * ============================================================================= */ CSL_Status CSL_gpioGetHwStatus( CSL_GpioHandle hGpio, CSL_GpioHwStatusQuery query, void *response ); /** =========================================================================== * @n@b CSL_gpioGetBaseAddress * * @b Description * @n Function to get the base address of the peripheral instance. * This function is used for getting the base address of the peripheral * instance. This function will be called inside the CSL_gpioOpen() * function call. This function is open for re-implementing if the user * wants to modify the base address of the peripheral object to point to * a different location and there by allow CSL initiated write/reads into * peripheral MMR's go to an alternate location. * * @b Arguments * @verbatim gpioNum Specifies the instance of GPIO to be opened. pGpioParam Module specific parameters. pBaseAddress Pointer to baseaddress structure containing base address details. @endverbatim * * Return Value CSL_Status * @li CSL_OK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * * Pre Condition * @n None * * Post Condition * @n Base Address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_GpioBaseAddress baseAddress; ... status = CSL_gpioGetBaseAddress(CSL_GPIO_PER_CNT, NULL, &baseAddress); @endverbatim * =========================================================================== */ CSL_Status CSL_gpioGetBaseAddress ( CSL_InstNum gpioNum, CSL_GpioParam *pGpioParam, CSL_GpioBaseAddress *pBaseAddress ); #ifdef __cplusplus } #endif #endif /*_CSL_GPIO_H_*/

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtOpen.c

<filename>DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtOpen.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * priovided * ============================================================================ */ /** ============================================================================ * @file csl_bwmngmtOpen.c * * @path $(CSLPATH)\src\bwmngmt * * @desc File for functional layer of CSL API CSL_bwmngmtOpen() * */ /* ============================================================================= * Revision History * =============== * 03-Jun-2004 <NAME> File Created * 11-Apr-2005 Brn Updated the file for doxygen compatibiliy * 16-Nov-2005 ds Updated the documentation * 31-Jan-2006 ds Supported to use the CSL_bwmngmtGetBaseAddress() API * ============================================================================= */ #include <csl_bwmngmt.h> /** =========================================================================== * @n@b CSL_bwmngmtOpen * * @b Description * This function populates the peripheral data object for the instance * and returns a handle to the BWMNGMT instance. * The open call sets up the data structures for the particular instance * of BWMNGMT device. The device can be re-opened anytime after it has * been normally closed, if so required.The handle returned by this call * is input as an essential argument for rest of the APIs described for * this module. * * @b Arguments * @verbatim pBwmngmtObj Pointer to the BWMNGMT instance object bwmngmtNum Instance of the BWMNGMT to be opened. pBwmngmtParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * Return Value CSL_BwmngmtHandle * Valid BWMNGMT instance handle will be returned if status value is * equal to CSL_SOK. * * Pre Condition * @n The BWMNGMT module must be successfully initialized via * CSL_bwmngmtInit() before calling this function. * * Post Condition * @n 1. The status is returned in the status variable. If status returned is * CSL_SOK - Valid BWMNGMT handle is returned. * CSL_ESYS_FAIL - The BWMNGMT instance is invalid. CSL_ESYS_INVPARAMS - The Obj structure passed is invalid * 2. BWMNGMT object structure is populated. * * * @b Modifies * @n 1. The status variable * 2. BWMNGMT object structure * * @b Example * @verbatim CSL_status status; CSL_BwmngmtObj bwmngmtObj; CSL_BwmngmtHandle hBwmngmt; hBwmngmt = CSL_bwmngmtOpen (&bwmngmtObj, CSL_BWMNGMT, NULL, &status ); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_bwmngmtOpen, ".text:csl_section:bwmngmt"); CSL_BwmngmtHandle CSL_bwmngmtOpen ( CSL_BwmngmtObj *pBwmngmtObj, CSL_InstNum bwmngmtNum, CSL_BwmngmtParam *pBwmmngmtParam, CSL_Status *pStatus ) { CSL_BwmngmtHandle hBwmngmt = (CSL_BwmngmtHandle)NULL; CSL_BwmngmtBaseAddress baseAddress; if (pStatus == NULL) { /* do nothing : already the module is initialized to NULL */ } else if (pBwmngmtObj == NULL) { *pStatus = CSL_ESYS_INVPARAMS; } else { *pStatus = CSL_bwmngmtGetBaseAddress(bwmngmtNum, pBwmmngmtParam, &baseAddress); if (*pStatus == CSL_SOK) { pBwmngmtObj->regs = baseAddress.regs; pBwmngmtObj->bwmngmtNum = (CSL_InstNum)bwmngmtNum; hBwmngmt = (CSL_BwmngmtHandle)pBwmngmtObj; } else { pBwmngmtObj->regs = (CSL_BwmngmtRegsOvly)NULL; pBwmngmtObj->bwmngmtNum = (CSL_InstNum)-1; } } return (hBwmngmt); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiHwSetup.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_hpiHwSetup.c * * @path $(CSLPATH)\src\hpi * * @brief File for functional layer of CSL API @a CSL_hpiHwSetup() * */ #include <csl_hpi.h> /** ============================================================================ * @n@b CSL_hpiHwSetup * * @b Description * @n It configures the hpi registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim hHpi Handle to the hpi hwSetup Pointer to harware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup successful * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVPARAMS - The parameter passed is * invalid * * Pre Condition * @n None * * Post Condition * @n HPI registers are configured according to the hardware setup * parameters. * * @b Modifies * @n HPI registers * * @b Example * @verbatim CSL_status status; CSL_HpiHwSetup myHwSetup; CSL_HpiHandle hHpi; myHwSetup.HPIC = hwSetup->hpiCtrl; ..... status = CSL_hpiHwSetup(hHpi, &hwSetup); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_hpiHwSetup, ".text:csl_section:hpi"); CSL_Status CSL_hpiHwSetup ( CSL_HpiHandle hHpi, CSL_HpiHwSetup *hwSetup ) { CSL_Status status = CSL_SOK; CSL_HpiRegsOvly hpiRegs = hHpi->regs; if (hHpi == NULL) { status = CSL_ESYS_BADHANDLE; } else if (hwSetup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Configure the Control Register */ hpiRegs->HPIC = hwSetup->hpiCtrl; } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_gpioAux.h

<filename>DSP/TI-Header/csl_c6455_src/inc/csl_gpioAux.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ============================================================================ */ /** =========================================================================== * @file csl_gpioAux.h * * @brief APIs Auxilary header file for GPIO CSL * * @Path $(CSLPATH)\inc * * @desc Control command and status query Functions of gpio * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 04-Sep-2004 Nsr File Created from CSL_gpioHwControl.c And * CSL_gpioGetHwStatus.c. * 04-Sep-2004 Nsr Added inline functions for query commands also. * 11-Oct-2004 Nsr Changed this file according to review commnets. * 22-Feb-2005 Nsr Added CSL_gpioGetBit API according to TI Issue PSG00000310. * 03-Mar-2005 Nsr Updated changes (PSG00000289) in CSL_gpioSetBit and * CSL_gpioClearBit. * 28-Jul-2005 PSK updated CSL source to support only ONE BANK. * bank "index" is removed. * 11-Jan-2006 NG Added CSL_GPIO_CMD_SET_OUT_BIT Control Command * 06-Mar-2006 ds Changed CSL_GPIO_CMD_SET_OUT_BIT cmd to clear and set the * outbit and Renamed CSL_GPIO_CMD_SET_OUT_BIT to * CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT * ============================================================================ */ #ifndef _CSL_GPIOAUX_H_ #define _CSL_GPIOAUX_H_ #include <csl_gpio.h> #ifdef __cplusplus extern "C" { #endif /* Control command and status query Functions of gpio. */ /** =========================================================================== * @n@b CSL_gpioBankIntEnable * * @b Description * @n This function enables the GPIO bank interrupt . * * @b Arguments * @verbatim hGpio Handle to GPIO instance. @endverbatim * * Return Value * @n CSL_SOK * * Pre Condition * @n None * * Post Condition * @n Bank interrupt will be enabled * * @b Modifies * @n BINTEN register * * @b Example * @verbatim CSL_gpioBankIntEnable(hGpio); @endverbatim * ============================================================================ */ static inline CSL_Status CSL_gpioBankIntEnable ( CSL_GpioHandle hGpio ) { CSL_FINSR(hGpio->regs->BINTEN, 0, 0, TRUE); return CSL_SOK; } /** =========================================================================== * @n@b CSL_gpioBankIntDisable * * @b Description * @n This function disables the GPIO bank interrupt . * * @b Arguments * @verbatim hGpio Handle to GPIO instance. @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n Bank interrupt will be disabled * * @b Modifies * @n BINTEN register * * @b Example * @verbatim CSL_gpioBankIntDisable(hGpio); @endverbatim * ============================================================================ */ static inline CSL_Status CSL_gpioBankIntDisable ( CSL_GpioHandle hGpio ) { CSL_FINSR(hGpio->regs->BINTEN, 0, 0, FALSE); return CSL_SOK; } /** =========================================================================== * @n@b CSL_gpioConfigBit * * @b Description * @n This function used to configure the direction and rising and falling edge trigger registers. * * @b Arguments * @verbatim hGpio Handle to GPIO instance config Pointer to the CSL_GpioPinConfig structure. @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n Configures any of the 16 GPIO signals * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioConfigBit (hGpio, &config); @endverbatim * ============================================================================ */ static inline CSL_Status CSL_gpioConfigBit ( CSL_GpioHandle hGpio, CSL_GpioPinConfig *config ) { CSL_Status status = CSL_SOK; CSL_GpioPinNum pinNum; CSL_GpioTriggerType trigger; CSL_GpioRegsOvly gpioRegs = hGpio->regs; pinNum = config->pinNum; if (pinNum < hGpio->numPins) { pinNum = (CSL_GpioPinNum)(pinNum & 0x1f); trigger = config->trigger; CSL_FINSR(gpioRegs->DIR, pinNum, pinNum, config->direction); if (trigger & CSL_GPIO_TRIG_RISING_EDGE) { CSL_FINSR(gpioRegs->SET_RIS_TRIG, pinNum, pinNum, TRUE); } else { CSL_FINSR(gpioRegs->CLR_RIS_TRIG, pinNum, pinNum, TRUE); } if (trigger & CSL_GPIO_TRIG_FALLING_EDGE) { CSL_FINSR(gpioRegs->SET_FAL_TRIG, pinNum, pinNum, TRUE); } else { CSL_FINSR (gpioRegs->CLR_FAL_TRIG, pinNum, pinNum, TRUE); } } else { status = CSL_EGPIO_INVPARAM; } return status; } /** =========================================================================== * @n@b CSL_gpioSetBit * * @b Description * @n This function sets the bit value of SET_DATA register in the GPIO * module. * * @b Arguments * @verbatim hGpio Handle to GPIO instance pinNum This variable holds the GPIO pin number. @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioSetBit(hGpio,pinNum); @endverbatim * ============================================================================ */ static inline CSL_Status CSL_gpioSetBit ( CSL_GpioHandle hGpio, CSL_GpioPinNum pinNum ) { CSL_Status status = CSL_SOK; CSL_GpioRegsOvly gpioRegs = hGpio->regs; if (pinNum < hGpio->numPins) { pinNum = (CSL_GpioPinNum)(pinNum & 0x1f); gpioRegs->SET_DATA = (1<<pinNum); } else { status = CSL_EGPIO_INVPARAM; } return status; } /** =========================================================================== * @n@b CSL_gpioEnDisOutBit * * @b Description * @n This function sets and clear the bit value of OUT_DATA register in the * GPIO * module. * * @b Arguments * @verbatim hGpio Handle to GPIO instance pinData Pointer to Gpio PinData structure @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioSetOutBit(hGpio,pinNum); @endverbatim * ============================================================================ */ static inline CSL_Status CSL_gpioEnDisOutBit ( CSL_GpioHandle hGpio, CSL_GpioPinData *pinData ) { CSL_Status status = CSL_SOK; CSL_GpioRegsOvly gpioRegs = hGpio->regs; if (pinData->pinNum < hGpio->numPins) { pinData->pinNum = (CSL_GpioPinNum)(pinData->pinNum & 0x1f); CSL_FINSR(gpioRegs->OUT_DATA, pinData->pinNum, pinData->pinNum, \ pinData->pinVal); } else { status = CSL_EGPIO_INVPARAM; } return status; } /** =========================================================================== * @n@b CSL_gpioClearBit * * @b Description * @n This function sets the bit value of CLR_DATA register. * * @b Arguments * @verbatim hGpio Handle to GPIO instance pinNum This variable holds the GPIO pin number. @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioClearBit(hGpio,pinNum); @endverbatim * ============================================================================ */ static inline CSL_Status CSL_gpioClearBit ( CSL_GpioHandle hGpio, CSL_GpioPinNum pinNum ) { CSL_Status status = CSL_SOK; CSL_GpioRegsOvly gpioRegs = hGpio->regs; if (pinNum < hGpio->numPins) { pinNum = (CSL_GpioPinNum)(pinNum & 0x1f); gpioRegs->CLR_DATA = (1<<pinNum); } else { status = CSL_EGPIO_INVPARAM; } return status; } /** =========================================================================== * @n@b CSL_gpioGetInputBit * * @b Description * @n This function gets the IN_DATA register value of the GPIO bank. * * @b Arguments * @verbatim hGpio Handle to GPIO instance value Read IN_DATA register value. @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioGetInputBit(hGpio,&value); @endverbatim * ============================================================================ */ static inline CSL_Status CSL_gpioGetInputBit ( CSL_GpioHandle hGpio, CSL_BitMask16 *value ) { *(CSL_BitMask16 *)value = hGpio->regs->IN_DATA; return CSL_SOK; } /** =========================================================================== * @n@b CSL_gpioGetBit * * @b Description * @n This function gets the Pin number status of GPIO module. * @b Arguments * @verbatim hGpio Handle to GPIO instance pinNum pin number to get the status. @endverbatim * * Return Value * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioGetBit(hGpio,pinNum); @endverbatim * =========================================================================== */ static inline CSL_Status CSL_gpioGetBit ( CSL_GpioHandle hGpio, CSL_GpioPinData *pinData ) { CSL_Status status = CSL_SOK; CSL_GpioRegsOvly gpioRegs = hGpio->regs; if (pinData->pinNum < hGpio->numPins) { pinData->pinNum = (CSL_GpioPinNum)(pinData->pinNum & 0x1f); pinData->pinVal = CSL_FEXTR(gpioRegs->IN_DATA, pinData->pinNum, pinData->pinNum); } else { pinData->pinVal = CSL_ESYS_FAIL; status = CSL_EGPIO_INVPARAM; } return status; } /** =========================================================================== * @n@b CSL_gpioGetOutDrvState * * @b Description * @n This function gets the OUT_DATA value of the GPIO bank. * * @b Arguments * @verbatim hGpio Handle to GPIO instance value Read OUT_DATA register value. @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioGetOutDrvState(hGpio,&value); @endverbatim * =========================================================================== */ static inline CSL_Status CSL_gpioGetOutDrvState ( CSL_GpioHandle hGpio, void *value ) { *(CSL_BitMask16 *)value = hGpio->regs->OUT_DATA; return CSL_SOK; } /** =========================================================================== * @n@b CSL_gpioGetBintenStat * * @b Description * @n This function gets the interrupt capabilities of all banks in GPIO. * * @b Arguments * @verbatim hGpio Handle to GPIO instance response Placeholder to return status. @endverbatim * * Return Value None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_gpioGetBintenStat(hGpio, &response); @endverbatim * =========================================================================== */ static inline void CSL_gpioGetBintenStat ( CSL_GpioHandle hGpio, void *response ) { *(CSL_BitMask16 *)response = hGpio->regs->BINTEN; } #ifdef __cplusplus extern "C" { #endif #endif /* CSL_GPIOAUX_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtInit.c

<filename>DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtInit.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * priovided * ============================================================================ */ /** ============================================================================ * @file csl_bwmngmtInit.c * * @path $(CSLPATH)\src\bwmngmt * * @desc File for functional layer of CSL API CSL_bwmngmtInit() * */ /* ============================================================================= * Revision History * =============== * 03-Jun-2004 <NAME> File Created * * 11-Apr-2005 Brn updated the file for doxygen compatibiliy * * 16-Nov-2005 ds updated the documentation * ============================================================================= */ #include <csl_bwmngmt.h> /** ============================================================================ * @n@b CSL_bwmngmtInit * * @b Description * @n This is the initialization function for the BWMNGMT. This function must * be called before calling any other API from this CSL.This function is * idem-potent. Currently, the function just returns status CSL_SOK, * without doing anything. * * @b Arguments @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... CSL_bwmngmtInit(); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_bwmngmtInit, ".text:csl_section:bwmngmt"); CSL_Status CSL_bwmngmtInit ( CSL_BwmngmtContext *pContext ) { return CSL_SOK; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspIoRead.c

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_mcbspIoRead.c * * @path $(CSLPATH)\src\mcbsp * * @desc File for functional layer of CSL API CSL_mcbspIoRead() * */ /* ============================================================================= * Revision History * ================ * June 29,2004 <NAME> - Created * * ============================================================================= */ #include <csl_mcbsp.h> /** ============================================================================ * @n@b CSL_mcbspIoRead * * @b Description * @n Reads the data from MCBSP pin which is configured as general purpose * input.The 16-bit data read from this pin is returned by this API. MCBSP * pin to use in this read operation is identified by the second argument. * * @b Arguments * @verbatim hMcbsp MCBSP handle returned by successful 'open' inputSel MCBSP pin to be used as general purpose input @endverbatim * * Return Value Uint16 * @li Data read from the pin * * Pre Condition * @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully * in that order before CSL_mcbspIoRead() can be called. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint16 inData; Uint16 clkx_data; Uint16 clkr_data; CSL_Status status; CSL_BitMask16 inMask; CSL_McbspHandle hMcbsp; ... // MCBSP object defined and HwSetup structure defined and initialized ... // Init, Open, HwSetup successfully done in that order ... inMask = CSL_MCBSP_IO_CLKX | CSL_MCBSP_IO_CLKR; inData = CSL_mcbspIoRead(hMcbsp, inMask); if ((inData & CSL_MCBSP_IO_CLKX) != 0) clkx_data = 1; else clkx_data = 0; if ((inData & CSL_MCBSP_IO_CLKR) != 0) clkr_data = 1; else clkr_data = 0; ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_mcbspIoRead, ".text:csl_section:mcbsp"); Uint16 CSL_mcbspIoRead ( CSL_McbspHandle hMcbsp, CSL_BitMask16 inputSel ) { Uint16 ret_value = 0; if(inputSel & CSL_MCBSP_IO_CLKX) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_CLKXP)) ret_value |= CSL_MCBSP_IO_CLKX; } if(inputSel & CSL_MCBSP_IO_FSX) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_FSXP)) ret_value |= CSL_MCBSP_IO_FSX; } if(inputSel & CSL_MCBSP_IO_CLKR) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_CLKRP)) ret_value |= CSL_MCBSP_IO_CLKR; } if(inputSel & CSL_MCBSP_IO_FSR) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_FSRP)) ret_value |= CSL_MCBSP_IO_FSR; } if(inputSel & CSL_MCBSP_IO_DR) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_DRSTAT)) ret_value |= CSL_MCBSP_IO_DR; } if(inputSel & CSL_MCBSP_IO_CLKS) { if( CSL_FEXT( hMcbsp->regs->PCR, MCBSP_PCR_CLKSSTAT)) ret_value |= CSL_MCBSP_IO_CLKS; } return( ret_value ); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiHwControl.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_hpiHwControl.c * * @path $(CSLPATH)\src\hpi * * @brief File for functional layer of CSL API @a CSL_hpiHwControl() * */ /* ============================================================================ * Revision History * =============== * 06-Mar-2006 sd Removed the invalid parameter check * ============================================================================ */ #include <csl_hpi.h> #include <csl_hpiAux.h> /** ============================================================================ * @n@b CSL_hpiHwControl * * @b Description * @n This function takes an input control command with an optional argument * and accordingly controls the operation/configuration of HPI. * * @b Arguments * @verbatim hHpi Handle to the HPI instance cmd The command to this API indicates the action to be taken on HPI. arg An optional argument. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Command successful. * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order * before calling CSL_hpiHwControl(). * * Post Condition * @n HPI registers are configured according to the command passed. * * @b Modifies * @n The hardware registers of HPI. * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_Status status; CSL_HpiHwControlCmd cmd = CSL_HPI_CMD_SET_DSP_INT; status = CSL_hpiHwControl(hHpi, cmd, NULL); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_hpiHwControl, ".text:csl_section:hpi"); CSL_Status CSL_hpiHwControl ( CSL_HpiHandle hHpi, CSL_HpiHwControlCmd cmd, void *arg ) { CSL_Status status = CSL_SOK; if (hHpi == NULL) { status = CSL_ESYS_BADHANDLE; } else { switch (cmd) { /* Set the Host-to-DSP Interrupt */ case CSL_HPI_CMD_SET_DSP_INT: CSL_hpiSetDspInt(hHpi); break; /* Reset the Host-to-DSP Interrupt */ case CSL_HPI_CMD_RESET_DSP_INT: CSL_hpiResetDspInt(hHpi); break; /* Set the HPIC Host Interrupt */ case CSL_HPI_CMD_SET_HINT: CSL_hpiSetHint(hHpi); break; /* Rest the HPIC Host Interrupt */ case CSL_HPI_CMD_RESET_HINT: CSL_hpiResetHint(hHpi); break; default: status = CSL_ESYS_INVCMD; } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotHwSetupRaw.c

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_memprotHwSetupRaw.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotHwSetupRaw () * */ /* ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * * ============================================================================= */ #include <csl_memprot.h> /** @brief Configures the Memory protection using the register-values passed in * through the config structure. For this module this API is a dummy. */ #pragma CODE_SECTION (CSL_memprotHwSetupRaw, ".text:csl_section:memprot"); CSL_Status CSL_memprotHwSetupRaw ( /* Pointer to the object that holds reference to the * instance of memory protection unit. */ CSL_MemprotHandle hMemprot, /* Pointer to setup structure which contains the * information to program the memory protection unit to a useful state */ CSL_MemprotConfig *config ) { return CSL_SOK; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3GetHwStatus.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_edma3GetHwStatus.c * * @path $(CSLPATH)\src\edma * * @desc File for functional layer of CSL API @a CSL_edma3GetHwStatus() * */ /* ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= */ #include <csl_edma3.h> #include <csl_edma3Aux.h> /** ============================================================================ * @n@b CSL_edma3GetHwStatus * * @b Description * @n Gets the status of the different operations or the current setup of EDMA * module. * * @b Arguments * @verbatim hMod Edma module handle myQuery Query to be performed response Pointer to buffer to return the data requested by the query passed @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Get the status of edma * @li CSL_ESYS_BADHANDLE - The handle passed is * invalid * @li CSL_ESYS_INVQUERY - The query passed is invalid * @li CSL_ESYS_INVPARAMS - The parameter passed is * invalid * * Pre Condition * @n Functions CSL_edma3Init(), CSL_edma3Open() must be called successfully * in that order before this API can be invoked.argument type that can be * void* casted & passed with a particular command refer to * CSL_Edma3HwStatusQuery * * Post Condition * @n None * * @b Modifies * @n The input arguement "response" is modified * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3QueryInfo info; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Query Module Info CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INFO,&info); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3GetHwStatus, ".text:csl_section:edma3"); CSL_Status CSL_edma3GetHwStatus ( CSL_Edma3Handle hMod, CSL_Edma3HwStatusQuery myQuery, void *response ) { CSL_Status status = CSL_SOK; if (hMod == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch(myQuery) { #if CSL_EDMA3_MEMPROTECT case CSL_EDMA3_QUERY_MEMFAULT: status = CSL_edma3GetMemoryFaultError(hMod, \ (CSL_Edma3MemFaultStat*)response); break; case CSL_EDMA3_QUERY_MEMPROTECT: ((CSL_Edma3CmdRegion*)response)->regionVal = \ CSL_edma3GetMemoryProtectionAttrib(hMod, \ ((CSL_Edma3CmdRegion*)response)->region); break; #endif case CSL_EDMA3_QUERY_CTRLERROR: status = CSL_edma3GetControllerError(hMod, \ (CSL_Edma3CtrlErrStat*)response); break; case CSL_EDMA3_QUERY_INTRPEND: status = CSL_edma3GetIntrPendStatus(hMod, \ ((CSL_Edma3CmdIntr*)response)->region, \ &((CSL_Edma3CmdIntr*)response)->intr, \ &((CSL_Edma3CmdIntr*)response)->intrh ); break; case CSL_EDMA3_QUERY_EVENTMISSED: status = \ CSL_edma3GetEventMissed(hMod,&((CSL_BitMask32*)response)[0],\ &((CSL_BitMask32*)response)[1], \ &((CSL_BitMask32*)response)[2]); break; case CSL_EDMA3_QUERY_QUESTATUS: status = \ CSL_edma3GetQueStatus(hMod,((CSL_Edma3QueStat*)response)->que,\ ((CSL_Edma3QueStat*)response)); break; case CSL_EDMA3_QUERY_ACTIVITY: status = \ CSL_edma3GetActivityStatus(hMod,\ ((CSL_Edma3ActivityStat*)response)); break; case CSL_EDMA3_QUERY_INFO: status = CSL_edma3GetInfo(hMod,((CSL_Edma3QueryInfo*)response)); break; default: status = CSL_ESYS_INVQUERY; break; } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/FB_Example/global.h

#ifndef GLOBAL_H_ #define GLOBAL_H_ // #define USE_SIMULATOR #define INIT_IRQ #define USE_MAILBOX_IRQ #include <csl.h> #define I2C_BUFFER_SIZE 512 #define MONITOR_ARRAY 256 #define STIMULUS_VECTOR_SIZE 10 #define SENDDATA_PER_FRAME 64 #define DOWNSAMPLE 1 #define FRAMES_PER_LOOP 1 #define INCLUDE_HS1_DATA //#define INCLUDE_HS2_DATA #define INCLUDE_IF_DATA #define INCLUDE_HS1_FILTER_DATA //#define INCLUDE_HS2_FILTER_DATA //#define INCLUDE_DIGIO_DATA //#define INCLUDE_STATUS_DATA #define TOTAL_ANALOG_CHANNELS 256 extern Int32 adc_intern[TOTAL_ANALOG_CHANNELS]; extern unsigned int ddr_data[1000000]; // this makes the variable visible to all .c files that include global.h extern int threshold; extern int deadtime; extern Uint32 StimulusEnable[2]; extern Uint32 DAC_select[4]; extern Uint32 elec_config[4]; #endif /*GLOBAL_H_*/

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/bwmngmt/src/Bwmngmt_example.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /* ============================================================================ * @file Bwmngmt_example.c * * @path $(CSLPATH)\example\bwmngmt\src * * @desc Example for BWMNGMT CSL * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @n This example, * 1. Initializes and opens the CSL BWMNGMT module instance. * 2. Sets up the hardware to default values and mapPriority, * ControlBlocks i.e., CSL_bwmngmtHwSetup() is called for * module configuration. * 3. Read back the hardware setup parameters * 4. Does the comparision of configured setup parameters and red * hardware setup parameters * 5. Displays the messages based on step 4 * * ============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Bwmngmt_example.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================= * Revision History * =============== * 23-sept-2005 PSK File Created * * 16-Dec-2005 ds Updated documentation * ============================================================================= */ #include <csl_bwmngmt.h> #include <soc.h> #include <stdio.h> /* Forward declarations */ void bwmngmt_example (void); CSL_Status bwmngmtHwSetupVerify(CSL_BwmngmtHwSetup*, CSL_BwmngmtHwSetup*); /* Handle for the BWMNGMT instance */ CSL_BwmngmtHandle hBwmngmt; /* Global variable used to log the error */ Uint32 bwmngmtExampleFailed = 0; /* * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= */ void main (void) { bwmngmt_example(); return; } /* * ============================================================================= * @func bwmngmt_example * * @desc * This function invokes example that prove functionalites of hardware * setup function with different value for the setup parameters. * The CSL API to retrive hardware setup parameters is also verified * * @arg * None * * @expected result * If the example passes, it displays the message "PASSED" * If the example fails, it displays the messae "FAILED" * * @eg * bwmngmt_example(); * ============================================================================= */ void bwmngmt_example ( void ) { CSL_BwmngmtObj bwmngmtObj; CSL_Status status; CSL_BwmngmtHwSetup hwSetupRead; CSL_BwmngmtHwSetup hwSetup = CSL_BWMNGMT_HWSETUP_DEFAULTS; /* Clear local data structures */ memset(&bwmngmtObj, 0, sizeof(CSL_BwmngmtObj)); memset(&hwSetupRead, 0, sizeof(CSL_BwmngmtHwSetup)); /* Setup parameters for Bwmngmt */ hwSetupRead.control = (CSL_BwmngmtControlBlocks)2; hwSetup.mapPriority = (CSL_BwmngmtPriority)0x0; /* Initialize BWMNGMT module */ status = CSL_bwmngmtInit(NULL); if (status != CSL_SOK) { printf("BWMNGMT: Initialization... Failed.\n"); bwmngmtExampleFailed++; return; } /* open the module */ hBwmngmt = CSL_bwmngmtOpen(&bwmngmtObj, CSL_BWMNGMT, NULL, &status); if (status != CSL_SOK || hBwmngmt == NULL) { printf ("BWMNGMT: Opening instance... Failed.\n"); bwmngmtExampleFailed++; return; } /* hardware setup */ status = CSL_bwmngmtHwSetup(hBwmngmt, &hwSetup); if (status != CSL_SOK) { printf ("BWMNGMT: HW Setup... Failed.\n"); bwmngmtExampleFailed++; return; } /* Read back and verify setup */ status = CSL_bwmngmtGetHwSetup(hBwmngmt, &hwSetupRead); if (status != CSL_SOK) { printf ("BWMNGMT: Get HW Setup... Failed.\n"); bwmngmtExampleFailed++; return; } /* Verify the setup parameter with red parameters */ status = bwmngmtHwSetupVerify(&hwSetup, &hwSetupRead); if (status != CSL_SOK) { printf ("BWMNGMT: Example FAILED.\n"); return; } else { printf ("BWMNGMT: Example PASSED.\n"); } return; } /* * ============================================================================= * @func bwmngmtHwSetupVerify * * @desc * This function compares the hw setup that was configured and that was * returned by CSL_bwmngmtGetHwSetup() of BWMNGMT. * * @arg Pointer to the original configuration * Pointer to the configuration that was returned by * bwmngmtGetHwSetup() * * @eg * CSL_BwmngmtHwSetup hwSetup; * CSL_BwmngmtHwSetup hwSetupRead; * * ...... ; * * bwmngmtHwSetupVerify (hwSetup, hwSetupRead); * ============================================================================= */ CSL_Status bwmngmtHwSetupVerify ( CSL_BwmngmtHwSetup *hwSetup, CSL_BwmngmtHwSetup *hwSetupRead ) { CSL_Status status = CSL_SOK; /* Compare each and every filed of hw setup structure and * print the read values. */ /* Cpu Priority value */ if (hwSetup->cpuPriority != hwSetupRead->cpuPriority) { bwmngmtExampleFailed++; } /* Cpu Maxwait value */ if (hwSetup->cpuMaxwait != hwSetupRead->cpuMaxwait) { bwmngmtExampleFailed++; } /* Internal DMA max wait value */ if (hwSetup->idmaMaxwait != hwSetupRead->idmaMaxwait) { bwmngmtExampleFailed++; } /* Slave Port Max Wait value */ if (hwSetup->slapMaxwait != hwSetupRead->slapMaxwait) { bwmngmtExampleFailed++; } /* Master Port Priority value */ if (hwSetup->mapPriority != hwSetupRead->mapPriority) { bwmngmtExampleFailed++; } /* User Coherance Max Wait value */ if (hwSetup->ucMaxwait != hwSetupRead->ucMaxwait) { bwmngmtExampleFailed++; } if (bwmngmtExampleFailed > 0) { status = CSL_ESYS_FAIL; } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/FB_W2100_SCU_MEA256/global.c

#include "global.h" int threshold; int deadtime; int StimAmplitude; int StimDuration; int StimRepeats; int StimStepsize; Uint32 StimulusEnable[HS1_CHANNELS / ELECTRODES_PER_REGISTER]; Uint32 elec_config[HS1_CHANNELS / ELECTRODES_PER_REGISTER]; Uint32 DAC_select[HS1_CHANNELS / (ELECTRODES_PER_REGISTER/2)];

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/common/csl_timerGetBaseAddress.c

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_tmrGetBaseAddress.c * * @path $(CSLPATH)\src\common * * @desc CSL Implementation of CSL_tmrGetBaseAddress * */ /* ============================================================================= * Revision History * =============== * 1-Sept-2004 HMM File Created. * ============================================================================= */ #include <soc.h> #include <csl_tmr.h> /** ============================================================================ * @n@b CSL_tmrGetBaseAddress * * @b Description * @n This function gets the base address of the given gptimer * instance. * * @b Arguments * @verbatim tmrNum Specifies the instance of the gptimer to be opened pTmrParam Gptimer module specific parameters pBaseAddress Pointer to base address structure containing base address details @endverbatim * * Return Value CSL_Status * @li CSL_OK Successful on getting the base * address of timer * @li CSL_ESYS_FAIL gptimer instance is not * available. * @li CSL_ESYS_INVPARAMS Invalid Parameters * * Pre Condition * @n None * * Post Condition * @n Base address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_TmrBaseAddress baseAddress; ... status = CSL_tmrGetBaseAddress(CSL_TMR_1, NULL, &baseAddress); ... @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_tmrGetBaseAddress, ".text:csl_section:tmr"); CSL_Status CSL_tmrGetBaseAddress ( CSL_InstNum tmrNum, CSL_TmrParam *pTmrParam, CSL_TmrBaseAddress *pBaseAddress ) { CSL_Status status = CSL_SOK; if (pBaseAddress == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (tmrNum) { case CSL_TMR_0: pBaseAddress->regs = (CSL_TmrRegsOvly)CSL_TMR_0_REGS; break; case CSL_TMR_1: pBaseAddress->regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; break; default: pBaseAddress->regs = (CSL_TmrRegsOvly)NULL; status = CSL_ESYS_FAIL; break; } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/vcp2/vcp2_soft_decisions/src/vcp2_data.c

/* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ========================================================================== */ /** =========================================================================== * @file vcp2_data.c * * @path $(CSLPATH)\example\c6455\vcp2\vcp2_soft_decisions\src * * @desc reference VCP2 soft decisions data * * ============================================================================ */ #include <csl_vcp2.h> #pragma DATA_SECTION(branch_metric, ".channelBmData") Uint32 branch_metric[] = { 0xfdf92507, 0xf224dd0f, 0x1612ddcb, 0xf22c0816, 0xf8163301, 0xe1efe3f5, 0x2a0005fd, 0xebeb07df, 0xefe701e3, 0x14c8de10, 0xf2eaf927, 0xd3fdee3a, 0xf341e307, 0x0606f2da, 0x1ad20f27, 0x48cce014, 0xf40e061c, 0xe5f1f83c, 0x1b1118ec, 0x1ff30a3e, 0xf23605d9, 0xbc20f6e4, 0xfd23fc12, 0x08eaf539, 0xf0e2d8dc, 0xf9ed01e9, 0xd7f5d7cd, 0x0de11ded, 0xf838d4da, 0x1428eed0, 0xe8ea1002, 0xe5050cdc, 0xfd0d13d5, 0x1cea2917, 0xedbb4509, 0x57053519, 0xea36dffd, 0x2c248100, 0x261cf416, 0xdc2cf808, 0x22ec01eb, 0xf2262202, 0x101406fe, 0xf7fd0d07, 0x0d091517, 0xf4dcdbe1, 0x08f216f0, 0x13fb1f33, 0x02b8f60a, 0xf31fca08, 0x200cd5fd, 0xfbc7dcd8, 0xf2063218, 0xcbfbe129, 0x13fd041c, 0x0fe1e8f8, 0x30ee04f6, 0xd7e918be, 0x18f81d0b, 0xf9130def, 0x06061e2c, 0xefdd04ee, 0xeeeeeae4, 0xd919ffd9, 0xf21a091d, 0xf20229c9, 0xe3f5102c, 0xeded01dd, 0x17f1e804, 0x10f612e0, 0xeb412a08, 0xfe0a0be9, 0x0802edc9, 0x1ed6f21c, 0xe537f10d, 0xeaf21ad4, 0xf9350131, 0x330f1509, 0xdc18eeb6, 0xf8f2f331, 0xdb0b0ce4, 0x02debc30, 0x0cdee6fc, 0x19c926da, 0x4a22210b, 0x1d271412, 0xfae6fdff, 0xfde73218, 0x15c9070b, 0x2905270f, 0x32fac408, 0xdbd71b03, 0x3cf00a04, 0x00f81fe7, 0xf9cde30b, 0x27e902fe, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; /* End of branch metrics */ Uint32 soft_decisionRef[] = { 0x8080807f, 0x7fc68086, 0x80807e7f, 0x94807f80, 0x8080807f, 0x7f7f807f, 0x7f7f807f, 0x7f807f80, 0x807f7f80, 0x80807f80, 0x807f7f80, 0x807f7f7f, 0x7f7f807f, 0x807f7f80, 0x967f7f80, 0x807f64e4, 0x7f807f7f, 0x7f7f807f, 0x803f7f4c, 0xb8c28080, 0x51975c4a, 0x224e6e6c, 0x7f305480, 0x807f6e80, 0x7f7f8080, 0x807f7f80, 0x7f92907f, 0x7f807f80, 0x327f787f, 0xee3e4ce7, 0x7fc48056, 0x7c7fb87f, 0x7f80607f, 0x807f5480, 0x6a80547f, 0x80ce7678, 0x7f7f7080, 0x7f807f80, 0x7f7a7f80, 0x80807f7f, 0x7f808080, 0x7f807880, 0x80807f7f, 0x8080807f, 0x7f7f7f7f, 0x80808080, 0x0000807f, 0x00000000 }; /* End of soft decision reference data */ Uint32 soft_decision[] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; /* End of soft decisions area */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotGetHwStatus.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_memprotGetHwStatus.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotGetHwStatus () * */ /* ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * * 16-Nov-2005 ds Updated the documentation * ============================================================================= */ #include <csl_memprot.h> #include <csl_memprotAux.h> /** =========================================================================== * @n@b CSL_memprotGetHwStatus * * @b Description * @n This function is used to read the current module configuration, status * flags and the value present associated registers. User should allocate * memory for the said data type and pass its pointer as an unadorned * void* argument to the status query call. For details about the various * status queries supported and the associated data structure to record * the response refer to @a CSL_MemprotHwStatusQuery * * @b Arguments * @verbatim hMemprot Handle to the MEMPROT instance query The query to this API of MEMPROT which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * @li CSL_ESYS_INVQUERY - Invalid Query * * Pre Condition * Both @a CSL_memprotInit() and @a CSL_memprotOpen() must be called * successfully in that order before @a CSL_memprotGetHwStatus() can be * called. For the argument type that can be @a void* casted & passed * with a particular command refer to @a CSL_MemprotHwStatusQuery * * Post Condition * @n None * * @b Modifies * @n Third parameter "response" value * * @b Example * @verbatim #define PAGE_ATTR 0xFFF0 Uint16 pageAttrTable[10] = {PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR, PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR}; Uint32 key[2] = {<KEY>}; CSL_MemprotObj mpL2Obj; CSL_MemprotHandle hmpL2; CSL_Status status; CSL_MemprotHwSetup L2MpSetup,L2MpGetSetup; CSL_MemprotLockStatus lockStat; CSL_MemprotPageAttr pageAttr; CSL_MemprotFaultStatus queryFaultStatus; // Initializing the module CSL_memprotInit(NULL); // Opening the Handle for the L2 hmpL2 = CSL_memprotOpen(&mpL2Obj,CSL_MEMPROT_L2,NULL,&status); L2MpSetup. memPageAttr = pageAttrTable; L2MpSetup.numPages = 10; L2MpSetup.key = key; // Do Setup for the L2 Memory protection/ CSL_memprotHwSetup (hmpL2,&L2MpSetup); // Query Lock Status CSL_memprotGetHwStatus(hmpL2,CSL_MEMPROT_QUERY_LOCKSTAT,&lockStat); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_memprotGetHwStatus, ".text:csl_section:memprot") CSL_Status CSL_memprotGetHwStatus ( CSL_MemprotHandle hMemprot, CSL_MemprotHwStatusQuery query, void *response ) { CSL_Status status = CSL_SOK; if (hMemprot == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (query) { case CSL_MEMPROT_QUERY_FAULT: CSL_memprotGetFaultStatus(hMemprot, (CSL_MemprotFaultStatus *)response); break; case CSL_MEMPROT_QUERY_PAGEATTR: ((CSL_MemprotPageAttr *)response)->attr = CSL_memprotGetPageAttr(hMemprot, ((CSL_MemprotPageAttr*)response)->page); break; case CSL_MEMPROT_QUERY_LOCKSTAT: *((CSL_MemprotLockStatus *)response) = CSL_memprotGetLockStat(hMemprot); break; default: status = CSL_ESYS_INVQUERY ; } } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcGetHwStatus.c

<filename>DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcGetHwStatus.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_intcGetHwStatus.c * * @brief File for functional layer of CSL API @a CSL_intcGetHwStatus() * * PATH $(CSLPATH)\src\intc */ /* ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= */ #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /** ============================================================================ * @n@b CSL_intcGetHwStatus * * @b Description * @n Queries the peripheral for status. The CSL_intcGetHwStatus(..) API * could be used to retrieve status or configuration information from * the peripheral. The user must allocate an object that would hold * the retrieved information and pass a pointer to it to the function. * The type of the object is specific to the query-command. * * @b Arguments * @verbatim hIntc Handle identifying the event query The query to this API of INTC which indicates the status to be returned. answer Placeholder to return the status. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful * @li CSL_ESYS_INVQUERY - Invalid query * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example: * @verbatim CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; CSL_IntcObj intcObj20; CSL_IntcHandle hIntc20; CSL_IntcEventHandlerRecord recordTable[10]; CSL_IntcGlobalEnableState state; Uint32 intrStat; context.numEvtEntries = 10; context.eventhandlerRecord = &recordTable; // Init Module ... if (CSL_intcInit(&context) != CSL_SOK) exit; // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL); // NMI Enable CSL_intcGlobalNmiEnable(); // Enable Global Interrupts intStat = CSL_intcGlobalEnable(&state); do { CSL_intcGetHwStatus(hIntc20,CSL_INTC_QUERY_PENDSTATUS, \ (void*)&intrStat); } while (!stat); // Close handle CSL_IntcClose(hIntc20); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_intcGetHwStatus, ".text:csl_section:intc"); CSL_Status CSL_intcGetHwStatus ( CSL_IntcHandle hIntc, CSL_IntcHwStatusQuery myQuery, void *answer ) { CSL_Status status = CSL_SOK; if (hIntc && answer) { switch (myQuery) { case CSL_INTC_QUERY_PENDSTATUS: if (hIntc->vectId < CSL_INTC_VECTID_EXCEP) { if (hIntc->eventId < 4) *((Uint32*)answer) = \ (Uint32)(CSL_intcCombinedEventGet(hIntc->eventId)); else *((Bool*)answer) = \ (Bool)(CSL_intcQueryEventStatus(hIntc->eventId)); } break; default: status = CSL_ESYS_INVQUERY; break; } } else status = CSL_ESYS_INVPARAMS; return status; } /** ============================================================================ * @n@b CSL_intcQueryDropStatus * * @b Description * @n Queries the peripheral for Drop status. The CSL_intcQueryDropStatus(..) * API could be used to retrieve drop status * * @b Arguments * @verbatim drop Pointer to drop status structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful * @li CSL_ESYS_INVPARAMS - Invalid handle * * Pre Condition * @n CSL_intcInit(), CSL_intcOpen() must be invoked before this call * * Post Condition * @n None * * @b Modifies * @n None * * @b Example: * @verbatim CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; CSL_IntcObj intcObj20; CSL_IntcHandle hIntc20; CSL_IntcDropStatus drop; CSL_IntcEventHandlerRecord recordTable[10]; CSL_IntcGlobalEnableState state; Uint32 intrStat; context.numEvtEntries = 10; context.eventhandlerRecord = &recordTable; // Init Module ... if (CSL_intcInit(&context) != CSL_SOK) exit; // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL); // Drop Enable CSL_intHwControl(hIntc20,CSL_INTC_CMD_EVTDROPENABLE,NULL); // Query Drop status CSL_intcQueryDropStatus(&drop); // Close handle CSL_IntcClose(hIntc20); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_intcQueryDropStatus, ".text:csl_section:intc"); CSL_Status CSL_intcQueryDropStatus ( CSL_IntcDropStatus *drop ) { Uint32 dropVal; CSL_Status status = CSL_ESYS_INVPARAMS ; if (drop) { dropVal = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTXSTAT; drop->drop = (Bool)(CSL_FEXT(dropVal,INTC_INTXSTAT_DROP)); drop->eventId = (CSL_IntcEventId)(CSL_FEXT(dropVal,INTC_INTXSTAT_SYSINT)); drop->vectId = (CSL_IntcVectId)(CSL_FEXT(dropVal,INTC_INTXSTAT_CPUINT)); /* Clear the drop condition */ ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTXCLR = 1; status = CSL_SOK; } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotInit.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_memprotInit.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotInit () * */ /* ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * * 16-Nov-2005 ds Updated the documentation * ============================================================================= */ #include <csl_memprot.h> /** =========================================================================== * @n@b CSL_memprotInit * * @b Description * @n This is the initialization function for the MEMPROT. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. The function must be called before calling any other API from * this CSL. * * @b Arguments @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * This function should be called before using any of the CSL APIs * in the Memory Protection module. * * Note: As Memory Protection doesn't have any context based information, * the function just returns CSL_SOK. User is expected to pass NULL. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... CSL_memprotInit(); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_memprotInit, ".text:csl_section:memprot"); CSL_Status CSL_memprotInit ( CSL_MemprotContext *pContext ) { /* If the module is already initialized, then error is * returned as init done(CSL_EINITDONE). If the user * needs to force init more than once, then set the * global Context pointer to NULL and invoke CSL_memprotInit() */ return CSL_SOK; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_pwrdwnL2.h

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_pwrdwnL2.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for L2PWRDWN */ #ifndef _CSLR_PWRDWNL2_H_ #define _CSLR_PWRDWNL2_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint8 RSVD0[64]; volatile Uint32 L2PDWAKE[2]; volatile Uint8 RSVD1[8]; volatile Uint32 L2PDSLEEP[2]; volatile Uint8 RSVD2[8]; volatile Uint32 L2PDSTAT[2]; } CSL_L2pwrdwnRegs; /**************************************************************************\ * Overlay structure typedef definition \**************************************************************************/ typedef volatile CSL_L2pwrdwnRegs *CSL_L2pwrdwnRegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* L2PDWAKE */ #define CSL_L2PWRDWN_L2PDWAKE_P1_MASK (0x00000002u) #define CSL_L2PWRDWN_L2PDWAKE_P1_SHIFT (0x00000001u) #define CSL_L2PWRDWN_L2PDWAKE_P1_RESETVAL (0x00000000u) /*----P1 Tokens----*/ #define CSL_L2PWRDWN_L2PDWAKE_P1_DISABLE (0x00000000u) #define CSL_L2PWRDWN_L2PDWAKE_P1_ENABLE (0x00000001u) #define CSL_L2PWRDWN_L2PDWAKE_P0_MASK (0x00000001u) #define CSL_L2PWRDWN_L2PDWAKE_P0_SHIFT (0x00000000u) #define CSL_L2PWRDWN_L2PDWAKE_P0_RESETVAL (0x00000000u) /*----P0 Tokens----*/ #define CSL_L2PWRDWN_L2PDWAKE_P0_DISABLE (0x00000000u) #define CSL_L2PWRDWN_L2PDWAKE_P0_ENABLE (0x00000001u) #define CSL_L2PWRDWN_L2PDWAKE_RESETVAL (0x00000000u) /* L2PDSLEEP */ #define CSL_L2PWRDWN_L2PDSLEEP_P1_MASK (0x00000002u) #define CSL_L2PWRDWN_L2PDSLEEP_P1_SHIFT (0x00000001u) #define CSL_L2PWRDWN_L2PDSLEEP_P1_RESETVAL (0x00000000u) /*----P1 Tokens----*/ #define CSL_L2PWRDWN_L2PDSLEEP_P1_DISABLE (0x00000000u) #define CSL_L2PWRDWN_L2PDSLEEP_P1_ENABLE (0x00000001u) #define CSL_L2PWRDWN_L2PDSLEEP_P0_MASK (0x00000001u) #define CSL_L2PWRDWN_L2PDSLEEP_P0_SHIFT (0x00000000u) #define CSL_L2PWRDWN_L2PDSLEEP_P0_RESETVAL (0x00000000u) /*----P0 Tokens----*/ #define CSL_L2PWRDWN_L2PDSLEEP_P0_DISABLE (0x00000000u) #define CSL_L2PWRDWN_L2PDSLEEP_P0_ENABLE (0x00000001u) #define CSL_L2PWRDWN_L2PDSLEEP_RESETVAL (0x00000000u) /* L2PDSTAT */ #define CSL_L2PWRDWN_L2PDSTAT_P1_MASK (0x00000002u) #define CSL_L2PWRDWN_L2PDSTAT_P1_SHIFT (0x00000001u) #define CSL_L2PWRDWN_L2PDSTAT_P1_RESETVAL (0x00000000u) #define CSL_L2PWRDWN_L2PDSTAT_P0_MASK (0x00000001u) #define CSL_L2PWRDWN_L2PDSTAT_P0_SHIFT (0x00000000u) #define CSL_L2PWRDWN_L2PDSTAT_P0_RESETVAL (0x00000000u) #define CSL_L2PWRDWN_L2PDSTAT_RESETVAL (0x00000000u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/dat/csl_dat.c

<filename>DSP/TI-Header/csl_c6455_src/src/dat/csl_dat.c /** =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_dat.c * * @desc This file defines the functions in the DAT module. * * @path $(CSLPATH)\src\dat */ /* ============================================================================= * Revision History * =============== * 14-Nov-2005 ds File modified - In the APIs DAT_copy(), DAT_copy2d(), * DAT_fill() added macro to set the STATIC when * OPT is programmed. * ============================================================================= */ #include <csl_dat.h> #include <_csl_dat.h> /** ============================================================================ * @n@b DAT_open * * @b Description * @n This API * a. Sets up the channel to Parameter set mapping \n * b. Sets up the priority. This is essentially done by specifying the * queue to which the channel is submitted to viz Queue0- Queue7. * Queue 0 being the highest priority. \n * c. Enables the region access bit for the channel if a region is * specified. * * @b Arguments @verbatim setup Pointer to the DAT setup structure @endverbatim * * Return Value CSL_SOK * * Pre Condition * @n None * * Post Condition * @n The EDMA registers are configured with the setup values passed. * * @b Modifies * @n None * * @b Example * @verbatim DAT_Setup datSetup; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (DAT_open, ".text:csl_section:dat"); Int16 DAT_open ( DAT_Setup *setup ) { Uint32 cs; /* Enter critical section */ cs = _disable_interrupts (); _CSL_datStateStruct.qchNum = setup->qchNum; _CSL_datStateStruct.regionNum = setup->regionNum; _CSL_datStateStruct.tccNum = setup->tccNum; _CSL_datStateStruct.priority = setup->priority; _CSL_datStateStruct.paramNum = setup->paramNum; _CSL_datStateStruct.pending = FALSE; /* the que entry number mapping */ CSL_FINSR (((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QDMAQNUM, setup->qchNum * 4 + 2, setup->qchNum * 4, setup->priority); /* The parameter set mapping */ ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QCHMAP[setup->qchNum] = CSL_FMK (EDMA3CC_QCHMAP_PAENTRY, setup->paramNum) | CSL_FMK (EDMA3CC_QCHMAP_TRWORD, 7); /* Enable the DRAE Bit */ if (setup->regionNum != CSL_DAT_REGION_GLOBAL) { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QRAE[setup->regionNum] |= (1 << setup->qchNum); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[setup->regionNum].QEESR = (1 << setup->qchNum); } else { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QEESR = (1 << setup->qchNum); } /* Leave critical section */ _restore_interrupts (cs); return CSL_SOK; } /** ============================================================================ * @n@b DAT_close * * @b Description * @n This API * a. Disables the region access bit if specified. * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n DAT_open() must be successfully invoked prior to this call. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim DAT_Setup datSetup; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... DAT_close(); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (DAT_close, ".text:csl_section:dat"); void DAT_close (void) { Uint32 cs; if (_CSL_datStateStruct.regionNum != CSL_DAT_REGION_GLOBAL) { cs = _disable_interrupts (); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QRAE[_CSL_datStateStruct.regionNum] &= ~(1 << _CSL_datStateStruct.qchNum); _restore_interrupts (cs); } } /** ============================================================================ * @n@b DAT_copy * * @b Description * @n This API copies data from source to destination for one dimension * transfer. * * @b Arguments @verbatim src Source memory address for the data transfer dst Destination memory address of the data transfer byteCnt Number of bytes to be transferred @endverbatim * * Return Value tccNum * * Pre Condition * @n DAT_open() must be successfully invoked prior to this call. * * Post Condition * @n The EDMA registers are configured to transfer byteCnt bytes from the * source memory address to the destination memory address * * @b Modifies * @n EDMA registers * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst1d[8*16]; Uint8 src1d[8*16]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... DAT_copy(&src1d,&dst1d,256); ... DAT_close(); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (DAT_copy, ".text:csl_section:dat"); Uint32 DAT_copy ( void *src, void *dst, Uint16 byteCnt ) { volatile CSL_Edma3ccParamsetRegs *param; Uint32 cs; cs = _disable_interrupts (); param = &((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->PARAMSET[_CSL_datStateStruct.paramNum]; if (_CSL_datStateStruct.pending) DAT_wait (_CSL_datStateStruct.tccNum); /* The options in the param set programmed need to have STATIC = 1. * If STATIC != 1 then when QDMA links to NULL SER will get set causing * further issue of Transfer requests */ param->OPT = CSL_FMKT (EDMA3CC_OPT_TCINTEN, ENABLE) | CSL_FMK (EDMA3CC_OPT_TCC, _CSL_datStateStruct.tccNum) | CSL_FMKT (EDMA3CC_OPT_STATIC, STATIC); param->SRC = (Uint32) (src); param->A_B_CNT = CSL_FMK (EDMA3CC_A_B_CNT_ACNT, byteCnt) | CSL_FMK (EDMA3CC_A_B_CNT_BCNT, 1); param->DST = (Uint32) (dst); param->LINK_BCNTRLD = CSL_FMK (EDMA3CC_LINK_BCNTRLD_LINK, 0xFFFF); param->CCNT = 0x00000001; _CSL_datStateStruct.pending = TRUE; _restore_interrupts (cs); return _CSL_datStateStruct.tccNum; } /** ============================================================================ * @n@b DAT_fill * * @b Description * @n This API fill destination by given fill value. * * @b Arguments @verbatim dst Destination memory address to be filled byteCnt Number of bytes to be filled value Value to be filled @endverbatim * * Return Value tccNum * * Pre Condition * @n DAT_open() must be successfully invoked prior to this call. * * Post Condition * @n The EDMA registers are configured to transfer a value to byteCnt bytes * of the destination memory address * * @b Modifies * @n EDMA registers * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst[8*16]; Uint8 fillVal; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... fillVal = 0x5a; DAT_fill(&dst,256,&fillval); ... DAT_close(); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (DAT_fill, ".text:csl_section:dat"); Uint32 DAT_fill ( void *dst, Uint16 byteCnt, Uint32 *value ) { volatile CSL_Edma3ccParamsetRegs *param; Uint32 cs; cs = _disable_interrupts (); param = &((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->PARAMSET[_CSL_datStateStruct.paramNum]; if (_CSL_datStateStruct.pending) DAT_wait (_CSL_datStateStruct.tccNum); /* The options in the param set programmed need to have STATIC = 1. * If STATIC != 1 then when QDMA links to NULL SER will get set causing * further issue of Transfer requests */ param->OPT = CSL_FMKT (EDMA3CC_OPT_TCINTEN, ENABLE) | CSL_FMK (EDMA3CC_OPT_TCC, _CSL_datStateStruct.tccNum) | CSL_FMKT (EDMA3CC_OPT_SYNCDIM, ABSYNC) | CSL_FMKT (EDMA3CC_OPT_STATIC, STATIC); param->SRC = (Uint32) (value); param->A_B_CNT = CSL_FMK (EDMA3CC_A_B_CNT_ACNT, 1) | CSL_FMK (EDMA3CC_A_B_CNT_BCNT, byteCnt); param->DST = (Uint32) (dst); param->SRC_DST_BIDX = CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, 1) | CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0); param->LINK_BCNTRLD = CSL_FMK (EDMA3CC_LINK_BCNTRLD_LINK, 0xFFFF); param->CCNT = 0x00000001; _CSL_datStateStruct.pending = TRUE; _restore_interrupts (cs); return _CSL_datStateStruct.tccNum; } /** ============================================================================ * @n@b DAT_wait * * @b Description * @n This API Waits for completion of the ongoing transfer. * * @b Arguments @verbatim id Channel number of the previous transfer @endverbatim * * Return Value * @n None * * Pre Condition * @n DAT_copy()/DAT_fill must be successfully invoked prior to this call. * * Post Condition * @n Indicates that the transfer ongoing is complete * * @b Modifies * @n None * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst1d[8*16]; Uint8 src1d[8*16]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... id = DAT_copy(&src1d,&dst1d,256); DAT_wait(id); ... DAT_close(); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (DAT_wait, ".text:csl_section:dat"); void DAT_wait ( Uint32 id ) { Uint32 cs; cs = _disable_interrupts (); if (_CSL_datStateStruct.regionNum != CSL_DAT_REGION_GLOBAL) { if (_CSL_datStateStruct.tccNum < 32) { while (!(((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct. regionNum].IPR & (1 << _CSL_datStateStruct.tccNum))); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum].ICR = (1 << _CSL_datStateStruct.tccNum); } else { while (!(((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct. regionNum].IPRH & (1 << (_CSL_datStateStruct.tccNum - 32)))); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum]. ICRH = (1 << _CSL_datStateStruct.tccNum - 32); } } else { if (_CSL_datStateStruct.tccNum < 32) { while (!(((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->IPR & (1 << _CSL_datStateStruct.tccNum))); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ICR = (1 << _CSL_datStateStruct.tccNum); } else { while (!(((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->IPRH & (1 << (_CSL_datStateStruct.tccNum - 32)))); ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ICRH = (1 << _CSL_datStateStruct.tccNum - 32); } } _CSL_datStateStruct.pending = FALSE; _restore_interrupts (cs); } /** ============================================================================ * @n@b DAT_busy * * @b Description * @n This API polls for transfer completion. * * @b Arguments @verbatim id Channel number of the previous transfer @endverbatim * * Return Value Int16 * TRUE/FALSE * * Pre Condition * @n DAT_copy()/DAT_fill must be successfully invoked prior to this call. * * Post Condition * @n Indicates that the transfer ongoing is complete * * @b Modifies * @n None * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst1d[8*16]; Uint8 src1d[8*16]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... id = DAT_copy(&src1d,&dst1d,256); do { ... }while (DAT_busy(id)); ... DAT_close(); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (DAT_busy, ".text:csl_section:dat"); Int16 DAT_busy ( Uint32 id ) { Bool status = TRUE; Uint32 temp; Uint32 cs; cs = _disable_interrupts (); /* The number 32 signifies lower 32 channels */ if (_CSL_datStateStruct.regionNum != CSL_DAT_REGION_GLOBAL) { if (_CSL_datStateStruct.tccNum < 32) { temp = ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum].IPR & (1 << _CSL_datStateStruct.tccNum); } else { temp = ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum]. IPRH & (1 << (_CSL_datStateStruct.tccNum - 32)); } } else { if (_CSL_datStateStruct.tccNum < 32) { temp = ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->IPR & (1 << _CSL_datStateStruct.tccNum); } else { temp = ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->IPRH & (1 << (_CSL_datStateStruct.tccNum - 32)); } } if (temp) { if (_CSL_datStateStruct.regionNum != CSL_DAT_REGION_GLOBAL) { if (_CSL_datStateStruct.tccNum < 32) { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum]. ICR = (1 << _CSL_datStateStruct.tccNum); } else { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->SHADOW[_CSL_datStateStruct.regionNum]. ICRH = (1 << (_CSL_datStateStruct.tccNum - 32)); } } else { if (_CSL_datStateStruct.tccNum < 32) { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ICR = (1 << _CSL_datStateStruct.tccNum); } else { ((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ICRH = (1 << (_CSL_datStateStruct.tccNum - 32)); } } _CSL_datStateStruct.pending = FALSE; status = FALSE; } _restore_interrupts (cs); return status; } /** ============================================================================ * @n@b DAT_copy2d * * @b Description * @n This API copies data from source to destination for two dimension * transfer. * * @b Arguments @verbatim type Indicates the type of the transfer DAT_1D2D - 1 dimension to 2 dimension DAT_2D1D - 2 dimension to 1 dimension DAT_2D2D - 2 dimension to 2 dimension src Source memory address for the data transfer dst Destination memory address of the data transfer lineLen Number of bytes per line lineCnt Number of lines linePitch Number of bytes between start of one line to start of next line @endverbatim * * Return Value tccNum * * Pre Condition * @n DAT_open() must be successfully invoked prior to this call. * * Post Condition * @n The EDMA registers are configured for the transfer * * @b Modifies * @n EDMA registers * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst2d[8][20]; Uint8 src1d[8*16]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... id = DAT_copy2d(DAT_1D2D,src1d,dst2d,16,8,20); do { ... }while (DAT_busy(id)); ... DAT_close(); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (DAT_copy2d, ".text:csl_section:dat"); Uint32 DAT_copy2d ( Uint32 type, void *src, void *dst, Uint16 lineLen, Uint16 lineCnt, Uint16 linePitch ) { volatile CSL_Edma3ccParamsetRegs *param; Uint32 cs; cs = _disable_interrupts (); param = &((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->PARAMSET[_CSL_datStateStruct.paramNum]; if (_CSL_datStateStruct.pending) DAT_wait (_CSL_datStateStruct.tccNum); /* The options in the param set programmed need to have STATIC = 1. * If STATIC != 1 then when QDMA links to NULL SER will get set causing * further issue of Transfer requests */ param->OPT = CSL_FMKT (EDMA3CC_OPT_TCINTEN, ENABLE) | CSL_FMK (EDMA3CC_OPT_TCC, _CSL_datStateStruct.tccNum) | CSL_FMKT (EDMA3CC_OPT_SYNCDIM, ABSYNC) | CSL_FMKT (EDMA3CC_OPT_STATIC, STATIC); param->SRC = (Uint32) (src); param->A_B_CNT = CSL_FMK (EDMA3CC_A_B_CNT_ACNT, lineLen) | CSL_FMK (EDMA3CC_A_B_CNT_BCNT, lineCnt); param->DST = (Uint32) (dst); if (type == DAT_2D2D) { param->SRC_DST_BIDX = CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, linePitch) | CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, linePitch); } else { if (type == DAT_1D2D) { param->SRC_DST_BIDX = CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, linePitch) | CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, lineLen); } else { if (type == DAT_2D1D) { param->SRC_DST_BIDX = CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, lineLen) | CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, linePitch); } } } param->LINK_BCNTRLD = CSL_FMK (EDMA3CC_LINK_BCNTRLD_LINK, 0xFFFF); param->CCNT = 0x00000001; _CSL_datStateStruct.pending = TRUE; _restore_interrupts (cs); return _CSL_datStateStruct.tccNum; } /** ============================================================================ * @n@b DAT_setPriority * * @b Description * @n Sets the priority bit value PRI of OPT register. The priority value * can be set by using the type CSL_DatPriority. * * @b Arguments @verbatim priority priority value @endverbatim * * Return Value * @n None * * Pre Condition * @n DAT_open must be successfully invoked prior to this call. * * Post Condition * @n OPT register is set for the priority value * * @b Modifies * @n OPT register * * @b Example * @verbatim DAT_Setup datSetup; Uint8 dst2d[8][20]; Uint8 src1d[8*16]; datSetup.qchNum = CSL_DAT_QCHA0; datSetup.regionNum = CSL_DAT_REGION_GLOBAL ; datSetup.tccNum = 1; datSetup.paramNum = 0 ; datSetup.priority = CSL_DAT_PRI_0; DAT_open(&datSetup); ... DAT_setPriority(CSL_DAT_PRI_3); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (DAT_setPriority, ".text:csl_section:dat"); void DAT_setPriority ( Int priority ) { Uint32 cs; if (_CSL_datStateStruct.pending) DAT_wait (_CSL_datStateStruct.tccNum); cs = _disable_interrupts (); /* The que entry number mapping */ /* The numbers 4 and 2 used to calculate the MSB and LSB of qdma Qnumber */ CSL_FINSR (((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->QDMAQNUM, _CSL_datStateStruct.qchNum * 4 + 2, _CSL_datStateStruct.qchNum * 4, priority); _CSL_datStateStruct.priority = priority; _restore_interrupts (cs); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnGetHwSetup.c

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_pwrdwnGetHwSetup.c * * @path $(CSLPATH)\src\pwrdwn * * @desc File for functional layer of CSL API CSL_pwrdwnGetHwSetup () * */ /* ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * ============================================================================= */ #include <csl_pwrdwn.h> /** =========================================================================== * @n@b CSL_pwrdwnGetHwSetup * * @b Description * @n It retrives the hardware setup parameters * * @b Arguments * @verbatim hPwr Handle to the PWRDWN instance hwSetup Pointer to hardware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup retrived * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @b CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call. * * Post Condition * @n The hardware set up structure will be populated with values from * the registers * * @b Modifies * @n None * * @b Example @verbatim CSL_PwrdwnObj pwrObj; CSL_PwrdwnHwSetup pwrSetup, querySetup; CSL_PwrdwnHandle hPwr; // Init Module ... if (CSL_pwrdwnInit(NULL) != CSL_SOK) exit; // Opening a handle for the Module hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL); // Setup the arguments for the Setup structure ... // Setup CSL_pwrdwnHwSetup(hPwr,&pwrSetup); // Query Setup CSL_pwrdwnGetHwSetup(hPwr,&querySetup); // Close handle CSL_pwrdwnClose(hPwr); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_pwrdwnGetHwSetup, ".text:csl_section:pwrdwn"); CSL_Status CSL_pwrdwnGetHwSetup ( CSL_PwrdwnHandle hPwrdwn, CSL_PwrdwnHwSetup *setup ) { CSL_Status status = CSL_SOK; /* This is a pointer to the registers of the instance of L2 PWRDWN * referred to by this object */ if (hPwrdwn == NULL) { status = CSL_ESYS_BADHANDLE; } else if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else { setup->idlePwrdwn = (Bool)CSL_FEXT(hPwrdwn->pdcRegs->PDCCMD, \ PDC_PDCCMD_MEGPD); if (setup->manualPwrdwn) { setup->manualPwrdwn->port0PageWake = CSL_FEXTR(hPwrdwn->l2pwrdwnRegs->L2PDWAKE[0], 2, 0); setup->manualPwrdwn->port1PageWake = CSL_FEXTR(hPwrdwn->l2pwrdwnRegs->L2PDWAKE[1], 2, 0); setup->manualPwrdwn->port0PageSleep = CSL_FEXTR(hPwrdwn->l2pwrdwnRegs->L2PDSLEEP[0], 2, 0); setup->manualPwrdwn->port1PageSleep = CSL_FEXTR(hPwrdwn->l2pwrdwnRegs->L2PDSLEEP[1], 2, 0); } } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_pllc.h

<filename>DSP/TI-Header/csl_c6455_src/inc/cslr_pllc.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_pllc.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for PLLC */ #ifndef _CSLR_PLLC_H_ #define _CSLR_PLLC_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint8 RSVD0[228]; volatile Uint32 RSTYPE; volatile Uint8 RSVD1[24]; volatile Uint32 PLLCTL; volatile Uint8 RSVD2[12]; volatile Uint32 PLLM; volatile Uint32 PREDIV; volatile Uint32 PLLDIV1; volatile Uint8 RSVD3[28]; volatile Uint32 PLLCMD; volatile Uint32 PLLSTAT; volatile Uint32 ALNCTL; volatile Uint32 DCHANGE; volatile Uint8 RSVD4[8]; volatile Uint32 SYSTAT; volatile Uint8 RSVD5[12]; volatile Uint32 PLLDIV4; volatile Uint32 PLLDIV5; } CSL_PllcRegs; /**************************************************************************\ * Overlay structure typedef definition \**************************************************************************/ typedef volatile CSL_PllcRegs *CSL_PllcRegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* RSTYPE */ #define CSL_PLLC_RSTYPE_SRST_MASK (0x00000008u) #define CSL_PLLC_RSTYPE_SRST_SHIFT (0x00000003u) #define CSL_PLLC_RSTYPE_SRST_RESETVAL (0x00000000u) /*----SRST Tokens----*/ #define CSL_PLLC_RSTYPE_SRST_NO (0x00000000u) #define CSL_PLLC_RSTYPE_SRST_YES (0x00000001u) #define CSL_PLLC_RSTYPE_MRST_MASK (0x00000004u) #define CSL_PLLC_RSTYPE_MRST_SHIFT (0x00000002u) #define CSL_PLLC_RSTYPE_MRST_RESETVAL (0x00000000u) /*----MRST Tokens----*/ #define CSL_PLLC_RSTYPE_MRST_NO (0x00000000u) #define CSL_PLLC_RSTYPE_MRST_YES (0x00000001u) #define CSL_PLLC_RSTYPE_WRST_MASK (0x00000002u) #define CSL_PLLC_RSTYPE_WRST_SHIFT (0x00000001u) #define CSL_PLLC_RSTYPE_WRST_RESETVAL (0x00000000u) /*----WRST Tokens----*/ #define CSL_PLLC_RSTYPE_WRST_NO (0x00000000u) #define CSL_PLLC_RSTYPE_WRST_YES (0x00000001u) #define CSL_PLLC_RSTYPE_POR_MASK (0x00000001u) #define CSL_PLLC_RSTYPE_POR_SHIFT (0x00000000u) #define CSL_PLLC_RSTYPE_POR_RESETVAL (0x00000000u) /*----POR Tokens----*/ #define CSL_PLLC_RSTYPE_POR_NO (0x00000000u) #define CSL_PLLC_RSTYPE_POR_YES (0x00000001u) #define CSL_PLLC_RSTYPE_RESETVAL (0x00000000u) /* PLLCTL */ #define CSL_PLLC_PLLCTL_PLLENSRC_MASK (0x00000020u) #define CSL_PLLC_PLLCTL_PLLENSRC_SHIFT (0x00000005u) #define CSL_PLLC_PLLCTL_PLLENSRC_RESETVAL (0x00000000u) /*----PLLENSRC Tokens----*/ #define CSL_PLLC_PLLCTL_PLLENSRC_REGBIT (0x00000000u) #define CSL_PLLC_PLLCTL_PLLENSRC_NONREGBIT (0x00000001u) #define CSL_PLLC_PLLCTL_PLLRST_MASK (0x00000008u) #define CSL_PLLC_PLLCTL_PLLRST_SHIFT (0x00000003u) #define CSL_PLLC_PLLCTL_PLLRST_RESETVAL (0x00000001u) /*----PLLRST Tokens----*/ #define CSL_PLLC_PLLCTL_PLLRST_NO (0x00000000u) #define CSL_PLLC_PLLCTL_PLLRST_YES (0x00000001u) #define CSL_PLLC_PLLCTL_PLLPWRDN_MASK (0x00000002u) #define CSL_PLLC_PLLCTL_PLLPWRDN_SHIFT (0x00000001u) #define CSL_PLLC_PLLCTL_PLLPWRDN_RESETVAL (0x00000000u) /*----PLLPWRDN Tokens----*/ #define CSL_PLLC_PLLCTL_PLLPWRDN_NO (0x00000000u) #define CSL_PLLC_PLLCTL_PLLPWRDN_YES (0x00000001u) #define CSL_PLLC_PLLCTL_PLLEN_MASK (0x00000001u) #define CSL_PLLC_PLLCTL_PLLEN_SHIFT (0x00000000u) #define CSL_PLLC_PLLCTL_PLLEN_RESETVAL (0x00000000u) /*----PLLEN Tokens----*/ #define CSL_PLLC_PLLCTL_PLLEN_BYPASS (0x00000000u) #define CSL_PLLC_PLLCTL_PLLEN_PLL (0x00000001u) #define CSL_PLLC_PLLCTL_RESETVAL (0x00000048u) /* PLLM */ #define CSL_PLLC_PLLM_PLLM_MASK (0x0000003Fu) #define CSL_PLLC_PLLM_PLLM_SHIFT (0x00000000u) #define CSL_PLLC_PLLM_PLLM_RESETVAL (0x00000000u) #define CSL_PLLC_PLLM_RESETVAL (0x00000000u) /* PREDIV */ #define CSL_PLLC_PREDIV_PREDEN_MASK (0x00008000u) #define CSL_PLLC_PREDIV_PREDEN_SHIFT (0x0000000Fu) #define CSL_PLLC_PREDIV_PREDEN_RESETVAL (0x00000001u) /*----PREDEN Tokens----*/ #define CSL_PLLC_PREDIV_PREDEN_DISABLE (0x00000000u) #define CSL_PLLC_PREDIV_PREDEN_ENABLE (0x00000001u) #define CSL_PLLC_PREDIV_RATIO_MASK (0x0000001Fu) #define CSL_PLLC_PREDIV_RATIO_SHIFT (0x00000000u) #define CSL_PLLC_PREDIV_RATIO_RESETVAL (0x00000002u) #define CSL_PLLC_PREDIV_RESETVAL (0x00008002u) /* PLLDIV1 */ #define CSL_PLLC_PLLDIV1_D1EN_MASK (0x00008000u) #define CSL_PLLC_PLLDIV1_D1EN_SHIFT (0x0000000Fu) #define CSL_PLLC_PLLDIV1_D1EN_RESETVAL (0x00000001u) /*----D1EN Tokens----*/ #define CSL_PLLC_PLLDIV1_D1EN_DISABLE (0x00000000u) #define CSL_PLLC_PLLDIV1_D1EN_ENABLE (0x00000001u) #define CSL_PLLC_PLLDIV1_RATIO_MASK (0x0000001Fu) #define CSL_PLLC_PLLDIV1_RATIO_SHIFT (0x00000000u) #define CSL_PLLC_PLLDIV1_RATIO_RESETVAL (0x00000001u) /*----RATIO Tokens----*/ #define CSL_PLLC_PLLDIV1_RATIO_DIV2 (0x00000001u) #define CSL_PLLC_PLLDIV1_RATIO_DIV5 (0x00000004u) #define CSL_PLLC_PLLDIV1_RESETVAL (0x00008001u) /* PLLCMD */ #define CSL_PLLC_PLLCMD_GOSET_MASK (0x00000001u) #define CSL_PLLC_PLLCMD_GOSET_SHIFT (0x00000000u) #define CSL_PLLC_PLLCMD_GOSET_RESETVAL (0x00000000u) /*----GOSET Tokens----*/ #define CSL_PLLC_PLLCMD_GOSET_CLRBIT (0x00000000u) #define CSL_PLLC_PLLCMD_GOSET_SET (0x00000001u) #define CSL_PLLC_PLLCMD_RESETVAL (0x00000000u) /* PLLSTAT */ #define CSL_PLLC_PLLSTAT_GOSTAT_MASK (0x00000001u) #define CSL_PLLC_PLLSTAT_GOSTAT_SHIFT (0x00000000u) #define CSL_PLLC_PLLSTAT_GOSTAT_RESETVAL (0x00000000u) /*----GOSTAT Tokens----*/ #define CSL_PLLC_PLLSTAT_GOSTAT_NONE (0x00000000u) #define CSL_PLLC_PLLSTAT_GOSTAT_INPROG (0x00000001u) #define CSL_PLLC_PLLSTAT_RESETVAL (0x00000000u) /* ALNCTL */ #define CSL_PLLC_ALNCTL_ALN5_MASK (0x00000010u) #define CSL_PLLC_ALNCTL_ALN5_SHIFT (0x00000004u) #define CSL_PLLC_ALNCTL_ALN5_RESETVAL (0x00000001u) /*----ALN5 Tokens----*/ #define CSL_PLLC_ALNCTL_ALN5_NO (0x00000000u) #define CSL_PLLC_ALNCTL_ALN5_YES (0x00000001u) #define CSL_PLLC_ALNCTL_ALN4_MASK (0x00000008u) #define CSL_PLLC_ALNCTL_ALN4_SHIFT (0x00000003u) #define CSL_PLLC_ALNCTL_ALN4_RESETVAL (0x00000001u) /*----ALN4 Tokens----*/ #define CSL_PLLC_ALNCTL_ALN4_NO (0x00000000u) #define CSL_PLLC_ALNCTL_ALN4_YES (0x00000001u) #define CSL_PLLC_ALNCTL_ALN1_MASK (0x00000001u) #define CSL_PLLC_ALNCTL_ALN1_SHIFT (0x00000000u) #define CSL_PLLC_ALNCTL_ALN1_RESETVAL (0x00000001u) /*----ALN1 Tokens----*/ #define CSL_PLLC_ALNCTL_ALN1_NO (0x00000000u) #define CSL_PLLC_ALNCTL_ALN1_YES (0x00000001u) #define CSL_PLLC_ALNCTL_RESETVAL (0x00000019u) /* DCHANGE */ #define CSL_PLLC_DCHANGE_SYS5_MASK (0x00000010u) #define CSL_PLLC_DCHANGE_SYS5_SHIFT (0x00000004u) #define CSL_PLLC_DCHANGE_SYS5_RESETVAL (0x00000000u) /*----SYS5 Tokens----*/ #define CSL_PLLC_DCHANGE_SYS5_NO (0x00000000u) #define CSL_PLLC_DCHANGE_SYS5_YES (0x00000001u) #define CSL_PLLC_DCHANGE_SYS4_MASK (0x00000008u) #define CSL_PLLC_DCHANGE_SYS4_SHIFT (0x00000003u) #define CSL_PLLC_DCHANGE_SYS4_RESETVAL (0x00000000u) /*----SYS4 Tokens----*/ #define CSL_PLLC_DCHANGE_SYS4_NO (0x00000000u) #define CSL_PLLC_DCHANGE_SYS4_YES (0x00000001u) #define CSL_PLLC_DCHANGE_SYS1_MASK (0x00000001u) #define CSL_PLLC_DCHANGE_SYS1_SHIFT (0x00000000u) #define CSL_PLLC_DCHANGE_SYS1_RESETVAL (0x00000000u) /*----SYS1 Tokens----*/ #define CSL_PLLC_DCHANGE_SYS1_NO (0x00000000u) #define CSL_PLLC_DCHANGE_SYS1_YES (0x00000001u) #define CSL_PLLC_DCHANGE_RESETVAL (0x00000000u) /* SYSTAT */ #define CSL_PLLC_SYSTAT_SYS5ON_MASK (0x00000010u) #define CSL_PLLC_SYSTAT_SYS5ON_SHIFT (0x00000004u) #define CSL_PLLC_SYSTAT_SYS5ON_RESETVAL (0x00000001u) /*----SYS5ON Tokens----*/ #define CSL_PLLC_SYSTAT_SYS5ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS5ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_SYS4ON_MASK (0x00000008u) #define CSL_PLLC_SYSTAT_SYS4ON_SHIFT (0x00000003u) #define CSL_PLLC_SYSTAT_SYS4ON_RESETVAL (0x00000001u) /*----SYS4ON Tokens----*/ #define CSL_PLLC_SYSTAT_SYS4ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS4ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_SYS3ON_MASK (0x00000004u) #define CSL_PLLC_SYSTAT_SYS3ON_SHIFT (0x00000002u) #define CSL_PLLC_SYSTAT_SYS3ON_RESETVAL (0x00000001u) /*----SYS3ON Tokens----*/ #define CSL_PLLC_SYSTAT_SYS3ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS3ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_SYS2ON_MASK (0x00000002u) #define CSL_PLLC_SYSTAT_SYS2ON_SHIFT (0x00000001u) #define CSL_PLLC_SYSTAT_SYS2ON_RESETVAL (0x00000001u) /*----SYS2ON Tokens----*/ #define CSL_PLLC_SYSTAT_SYS2ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS2ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_SYS1ON_MASK (0x00000001u) #define CSL_PLLC_SYSTAT_SYS1ON_SHIFT (0x00000000u) #define CSL_PLLC_SYSTAT_SYS1ON_RESETVAL (0x00000001u) /*----SYS1ON Tokens----*/ #define CSL_PLLC_SYSTAT_SYS1ON_OFF (0x00000000u) #define CSL_PLLC_SYSTAT_SYS1ON_ON (0x00000001u) #define CSL_PLLC_SYSTAT_RESETVAL (0x0000001Fu) /* PLLDIV4 */ #define CSL_PLLC_PLLDIV4_D4EN_MASK (0x00008000u) #define CSL_PLLC_PLLDIV4_D4EN_SHIFT (0x0000000Fu) #define CSL_PLLC_PLLDIV4_D4EN_RESETVAL (0x00000001u) /*----D4EN Tokens----*/ #define CSL_PLLC_PLLDIV4_D4EN_DISABLE (0x00000000u) #define CSL_PLLC_PLLDIV4_D4EN_ENABLE (0x00000001u) #define CSL_PLLC_PLLDIV4_RATIO_MASK (0x0000001Fu) #define CSL_PLLC_PLLDIV4_RATIO_SHIFT (0x00000000u) #define CSL_PLLC_PLLDIV4_RATIO_RESETVAL (0x00000007u) #define CSL_PLLC_PLLDIV4_RESETVAL (0x00008007u) /* PLLDIV5 */ #define CSL_PLLC_PLLDIV5_D5EN_MASK (0x00008000u) #define CSL_PLLC_PLLDIV5_D5EN_SHIFT (0x0000000Fu) #define CSL_PLLC_PLLDIV5_D5EN_RESETVAL (0x00000001u) /*----D5EN Tokens----*/ #define CSL_PLLC_PLLDIV5_D5EN_DISABLE (0x00000000u) #define CSL_PLLC_PLLDIV5_D5EN_ENABLE (0x00000001u) #define CSL_PLLC_PLLDIV5_RATIO_MASK (0x0000001Fu) #define CSL_PLLC_PLLDIV5_RATIO_SHIFT (0x00000000u) #define CSL_PLLC_PLLDIV5_RATIO_RESETVAL (0x00000002u) #define CSL_PLLC_PLLDIV5_RESETVAL (0x00008002u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/vcp2/vcp2_hard_decisions/inc/Vcp2_example.h

<gh_stars>0 /* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ========================================================================== */ /** =========================================================================== * @file Vcp2_example.h * * @path $(CSLPATH)\example\c6455\vcp2\vcp2_hard_decisions\inc * * @desc Example header file for VCP. * * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 20-May-2005 SPrasad File Created. * 01-Aug-2005 Chandra Beautified * 11-Aug-2005 Chandra Minor format chagnes. * ============================================================================ */ #ifndef _VCP2_EXAMPLE_H_ #define _VCP2_EXAMPLE_H_ #ifdef __cplusplus extern "C" { #endif /* Space for the banch metrics */ extern Uint32 branch_metric[]; /* Space for the hard decisions */ extern Uint32 hard_decision[]; /* Space for the pre-computed hard decisions */ extern Uint32 hard_decisionRef[]; #ifdef __cplusplus } #endif #endif /*_VCP2_EXAMPLE_H_*/

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3GetHwChannelSetup.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_edma3GetHwChannelSetup.c * * @path $(CSLPATH)\src\edma * * @desc EDMA3 CSL Implementation on DSP side * */ /* ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= */ #include <csl_edma3.h> #include <csl_edma3Aux.h> /** ============================================================================ * @n@b CSL_edma3GetHwChannelSetupParam * * @b Description * @n Obtains the Channel to Parameter Set mapping.This reads the * DCHMAP/QCHMAP appropriately. * * @b Arguments * @verbatim hEdma Channel Handle paramNum Pointer to parameter entry @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Retrieving the parameter entry * number to which a channel is * mapped * @li CSL_ESYS_BADHANDLE - The handle is passed is * invalid * @li CSL_ESYS_INVPARAMS - Invalid Parameter entry * * * Pre Condition * @n Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() * must be called successfully in that order before * CSL_edma3GetHwChannelSetupParam() can be invoked. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; Uint16 paramNum; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the parameter entry number to which a channel is mapped to CSL_edma3GetHwChannelSetupParam(hChannel,&paramNum); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3GetHwChannelSetupParam, ".text:csl_section:edma3"); CSL_Status CSL_edma3GetHwChannelSetupParam ( CSL_Edma3ChannelHandle hEdma, Uint16 *paramNum ) { CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else if (paramNum == NULL) { status = CSL_ESYS_INVPARAMS; } else { if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH) { #if CSL_EDMA3_CHMAPEXIST *paramNum = CSL_FEXT(hEdma->regs->DCHMAP[hEdma->chaNum], \ EDMA3CC_DCHMAP_PAENTRY); #endif } else *paramNum = CSL_FEXT(hEdma->regs->QCHMAP[hEdma->chaNum-CSL_EDMA3_NUM_DMACH],\ EDMA3CC_QCHMAP_PAENTRY); } return (status); } /** ============================================================================ * @n@b CSL_edma3GetHwChannelSetupTriggerWord * * @b Description * @n Reads the QDMA channel triggerword.This reads the QCHMAP to obtain the * trigger word appropriately. * * @b Arguments * @verbatim hEdma Channel Handle triggerWord Pointer to Trigger word @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Retrieving the parameter entry * number to which a channel is * mapped * @li CSL_ESYS_BADHANDLE - The handle is passed is * invalid * @li CSL_ESYS_INVPARAMS - Invalid Parameter entry * * * Pre Condition * @n Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() * must be called successfully in that order before * CSL_edma3GetHwChannelSetupTriggerWord() can be called. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; Uint8 triggerWord; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the trigger word programmed for a channel CSL_edma3GetHwChannelSetupTriggerWord(hChannel,&triggerWord); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3GetHwChannelSetupTriggerWord, ".text:csl_section:edma3"); CSL_Status CSL_edma3GetHwChannelSetupTriggerWord ( CSL_Edma3ChannelHandle hEdma, Uint8 *triggerWord ) { CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else { if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH) { status = CSL_ESYS_INVPARAMS; } else *triggerWord = \ CSL_FEXT(hEdma->regs->QCHMAP[hEdma->chaNum-CSL_EDMA3_NUM_DMACH], \ EDMA3CC_QCHMAP_TRWORD); } return (status); } /** ============================================================================ * @n@b CSL_edma3GetHwChannelSetupQue * * @b Description * @n Obtains the Channel to Queue map for the channel.This reads the * DMAQNUM/QDAMQNUM appropriately. * * @b Arguments * @verbatim hEdma Channel Handle evtQue Pointer to Queue setup @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Retrieving the que to which a * channel is mapped * @li CSL_ESYS_BADHANDLE - The handle is passed is * invalid * @li CSL_ESYS_INVPARAMS - Invalid Parameter entry * * * Pre Condition * @n Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() * must be called successfully in that order before * CSL_edma3GetHwChannelSetupQue() can be called. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3Que evtQue; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); // Get the que to which a channel is mapped CSL_edma3GetHwChannelSetupQue(hChannel,&evtQue); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3GetHwChannelSetupQue, ".text:csl_section:edma3"); CSL_Status CSL_edma3GetHwChannelSetupQue ( CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que *evtQue ) { Uint32 _cha; Uint32 _qNumIndex; Uint32 _qchMap; CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else if (evtQue == NULL) { status = CSL_ESYS_INVPARAMS; } else { if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH) { /* Extracting the Channel Number in case of QDMA */ _cha = hEdma->chaNum - CSL_EDMA3_NUM_DMACH; /* Channel to Event Queue mapping */ *evtQue = (CSL_Edma3Que)CSL_FEXTR(hEdma->regs->QDMAQNUM, _cha * 4 + 2, \ _cha * 4); } else { /* Finding out the relevant DMAQNUM register and the correct bit * positions to write into */ _qNumIndex = hEdma->chaNum >> 3; _qchMap = hEdma->chaNum - (_qNumIndex * 8); *evtQue = (CSL_Edma3Que)CSL_FEXTR(hEdma->regs->DMAQNUM[_qNumIndex], \ _qchMap * 4 + 2, _qchMap * 4); } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_i2c.h

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @mainpage I2C CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the I2C module across various devices. The CSL developer is expected to * refer to this document while designing APIs for this module. Some of the * listed APIs may not be applicable to a given I2C module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular I2C Module. The CSL developer should use his discretion designing * new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 * -# i2c_fs_25.pdf, I2C Peripheral Module * Design Requirement/Specification V2.5 */ /** ============================================================================ * @file csl_i2c.h * * @brief Header file for functional layer of CSL * * @path $(CSLPATH)\inc * * Description * - The different enumerations, structure definitions * and function declarations * * * Modification 1 * - modified on: 28/5/2004 * - reason: Created the sources * * @date 28th May, 2004 * @author <NAME>. * =========================================================================== */ /* ============================================================================= * Revision History * =============== * 30-aug-2004 Hs updated CSL_I2cObj and added CSL_I2cBaseAddress, CSL_i2cParam, * CSL_i2cContext, CSL_i2cConfig structures. * - Updated comments for H/W control cmd and status query enums. * - Added prototypes for CSL_i2cGetBaseAdddress and * CSL_I2cHwSetupRaw. * - Changed prototypes of CSL_i2cInit, CSL_i2cOpen. * - Updated respective comments along with that of * CSL_i2cClose. * 11-oct-2004 Hs updated according to code review comments. * 28-jul-2005 sv removed gpio support * 06-Feb-2006 ds removed CSL_I2C_QUERY_REV, CSL_I2C_QUERY_CLASS and * CSL_I2C_QUERY_TYPE queries from the CSL_I2cHwStatusQuery * =========================================================================== */ #ifndef _CSL_I2C_H_ #define _CSL_I2C_H_ #ifdef __cplusplus extern "C" { #endif #include <csl.h> #include <soc.h> #include <cslr_i2c.h> /**************************************************************************\ * I2C global macro declarations \**************************************************************************/ /** Constants for passing parameters to the I2C Hardware Setup function */ /** For setting the SLAVE Mode for I2C */ #define CSL_I2C_MODE_SLAVE (0) /** For setting the MASTER Mode for I2C */ #define CSL_I2C_MODE_MASTER (1) /** For setting the RECEIVER Mode for I2C */ #define CSL_I2C_DIR_RECEIVE (0) /** For setting the TRANSMITTER Mode for I2C */ #define CSL_I2C_DIR_TRANSMIT (1) /** For setting the 7-bit Addressing Mode for I2C */ #define CSL_I2C_ADDRSZ_SEVEN (0) /** For setting the 10-bit Addressing Mode */ #define CSL_I2C_ADDRSZ_TEN (1) /** For Disabling the Start Byte Mode for I2C(Normal Mode) */ #define CSL_I2C_STB_DISABLE (0) /** For Enabling the Start Byte Mode for I2C */ #define CSL_I2C_STB_ENABLE (1) /** For enabling the tx of a ACK to the TX-ER, while in the RECEIVER mode */ #define CSL_I2C_ACK_ENABLE (0) /** For enabling the tx of a NACK to the TX-ER, while in the RECEIVER mode */ #define CSL_I2C_ACK_DISABLE (1) /** For enabling the free run mode of the I2C */ #define CSL_I2C_FREE_MODE_ENABLE (1) /** For disabling the free run mode of the I2C */ #define CSL_I2C_FREE_MODE_DISABLE (0) /** For enabling the Repeat Mode of the I2C */ #define CSL_I2C_REPEAT_MODE_ENABLE (1) /** For disabling the Repeat Mode of the I2C */ #define CSL_I2C_REPEAT_MODE_DISABLE (0) /** For enabling DLB mode of I2C (applicable only in case of MASTER TX-ER) */ #define CSL_I2C_DLB_ENABLE (1) /** For disabling DLB mode of I2C (applicable only in case of MASTER TX-ER) */ #define CSL_I2C_DLB_DISABLE (0) /** For putting the I2C in Reset */ #define CSL_I2C_IRS_ENABLE (0) /** For taking the I2C out of Reset */ #define CSL_I2C_IRS_DISABLE (1) /** For enabling the Free Data Format of I2C */ #define CSL_I2C_FDF_ENABLE (1) /** For disabling the Free Data Format of I2C */ #define CSL_I2C_FDF_DISABLE (0) /** For enabling the Backward Compatibility mode of I2C */ #define CSL_I2C_BCM_ENABLE (1) /** For disabling the Backward Compatibility mode of I2C */ #define CSL_I2C_BCM_DISABLE (0) /** Constants for passing parameters to the I2C Status Query function */ /** For indicating the non-completion of Reset */ #define CSL_I2C_RESET_NOT_DONE (0) /** For indicating the completion of Reset */ #define CSL_I2C_RESET_DONE (1) /** For indicating that the bus is not busy */ #define CSL_I2C_BUS_NOT_BUSY (0) /** For indicating that the bus is busy */ #define CSL_I2C_BUS_BUSY (1) /** For indicating that the Receive ready signal is low */ #define CSL_I2C_RX_NOT_READY (0) /** For indicating that the Receive ready signal is high */ #define CSL_I2C_RX_READY (1) /** For indicating that the Transmit ready signal is low */ #define CSL_I2C_TX_NOT_READY (0) /** For indicating that the Transmit ready signal is high */ #define CSL_I2C_TX_READY (1) /** For indicating that the Access ready signal is low */ #define CSL_I2C_ACS_NOT_READY (0) /** For indicating that the Access ready signal is high */ #define CSL_I2C_ACS_READY (1) /** For indicating Single Byte Data signal is set */ #define CSL_I2C_SINGLE_BYTE_DATA (1) /** For indicating Receive overflow signal is set */ #define CSL_I2C_RECEIVE_OVERFLOW (1) /** For indicating Transmit underflow signal is set */ #define CSL_I2C_TRANSMIT_UNDERFLOW (1) /** For indicating Arbitration Lost signal is set */ #define CSL_I2C_ARBITRATION_LOST (1) /** Constants for status bit clear */ /** Clear the Arbitration Lost status bit */ #define CSL_I2C_CLEAR_AL 0x1 /** Clear the No acknowledge status bit */ #define CSL_I2C_CLEAR_NACK 0x2 /** Clear the Register access ready status bit */ #define CSL_I2C_CLEAR_ARDY 0x4 /** Clear the Receive ready status bit */ #define CSL_I2C_CLEAR_RRDY 0x8 /** Clear the Transmit ready status bit */ #define CSL_I2C_CLEAR_XRDY 0x10 /** Clear the Stop Condition Detect status bit */ #define CSL_I2C_CLEAR_SCD 0x20 /**************************************************************************\ * I2C global typedef declarations \**************************************************************************/ /** @brief This object contains the reference to the instance of I2C opened * using the @a CSL_i2cOpen(). * * The pointer to this, is passed to all I2C CSL APIs. */ typedef struct CSL_I2cObj { /** The register overlay structure of I2C. */ CSL_I2cRegsOvly regs; /** This is the instance of I2C being referred to by this object */ CSL_InstNum perNum; } CSL_I2cObj; /** @brief Holds the base-address information for I2C peripheral * instance */ typedef struct { /** Base-address of the Configuration registers of I2C. */ CSL_I2cRegsOvly regs; } CSL_I2cBaseAddress; /** @brief I2C specific parameters. Present implementation doesn't have * any specific parameters. */ typedef struct { /** Bit mask to be used for module specific parameters. * The below declaration is just a place-holder for future * implementation. */ CSL_BitMask16 flags; } CSL_I2cParam; /** @brief I2C specific context information. Present implementation doesn't * have any Context information. */ typedef struct { /** Context information of I2C. * The below declaration is just a place-holder for future * implementation. */ Uint16 contextInfo; } CSL_I2cContext; /** @brief I2C Configuration Structure, is used to configure I2C * using CSL_HwSetupRaw function. */ typedef struct { volatile Uint32 ICOAR; /**< I2C Own address register */ volatile Uint32 ICIMR; /**< I2C Interrupt Mask register */ volatile Uint32 ICSTR; /**< I2C Status register */ volatile Uint32 ICCLKL; /**< I2C Clock low register */ volatile Uint32 ICCLKH; /**< I2C clock high register */ volatile Uint32 ICCNT; /**< I2C Data Count register */ volatile Uint32 ICSAR; /**< I2C Slave address register */ volatile Uint32 ICDXR; /**< I2C Data Transmit register */ volatile Uint32 ICMDR; /**< I2C Mode register */ volatile Uint32 ICIVR; /**< I2C Interrupt vector register */ volatile Uint32 ICEMDR; /**< I2C Extended mode register */ volatile Uint32 ICPSC; /**< I2C Prescalar register */ } CSL_I2cConfig; /** Default Values for Config structure */ #define CSL_I2C_CONFIG_DEFAULTS { \ CSL_I2C_ICOAR_RESETVAL, \ CSL_I2C_ICIMR_RESETVAL, \ CSL_I2C_ICSTR_RESETVAL, \ CSL_I2C_ICCLKL_RESETVAL, \ CSL_I2C_ICCLKH_RESETVAL, \ CSL_I2C_ICCNT_RESETVAL, \ CSL_I2C_ICSAR_RESETVAL, \ CSL_I2C_ICDXR_RESETVAL, \ CSL_I2C_ICMDR_RESETVAL, \ CSL_I2C_ICIVR_RESETVAL, \ CSL_I2C_ICEMDR_RESETVAL, \ CSL_I2C_ICPSC_RESETVAL, \ } /** @brief Handle to the I2C object * Handle is used in all accesses to the device parameters. */ typedef struct CSL_I2cObj *CSL_I2cHandle; /** @brief The clock setup structure has all the fields required to configure * the I2C clock. */ typedef struct { /** Prescalar to the input clock */ Uint32 prescalar; /** Low time period of the clock */ Uint32 clklowdiv; /** High time period of the clock */ Uint32 clkhighdiv; } CSL_I2cClkSetup; /** @brief This has all the fields required to configure I2C at Power Up * (After a Hardware Reset) or a Soft Reset * * This structure is used to setup or obtain existing setup of * I2C using @a CSL_i2cHwSetup() & @a CSL_i2cGetHwSetup() functions * respectively. */ typedef struct { /** Master or Slave Mode : 1==> Master Mode, 0==> Slave Mode */ Uint32 mode; /** Transmitter Mode or Receiver Mode: 1==> Transmitter Mode, * 0 ==> Receiver Mode */ Uint32 dir; /** Addressing Mode :0==> 7-bit Mode, 1==> 10-bit Mode */ Uint32 addrMode; /** Start Byte Mode : 1 ==> Start Byte Mode, 0 ==> Normal Mode */ Uint32 sttbyteen; /** Address of the own device */ Uint32 ownaddr; /** ACK mode while receiver: 0==> ACK Mode, 1==> NACK Mode */ Uint32 ackMode; /** Run mode of I2C: 0==> No Free Run, 1==> Free Run mode */ Uint32 runMode; /** Repeat Mode of I2C: 0==> No repeat mode 1==> Repeat mode */ Uint32 repeatMode; /** DLBack mode of I2C (master tx-er only): * 0 ==> No loopback, * 1 ==> Loopback Mode */ Uint32 loopBackMode; /** Free Data Format of I2C: * 0 ==>Free data format disable, * 1 ==> Free data format enable */ Uint32 freeDataFormat; /** I2C Reset Mode: 0==> Reset, 1==> Out of reset */ Uint32 resetMode; /** I2C Backward Compatibility Mode : * 0 ==> Not compatible, * 1 ==> Compatible */ Uint32 bcm; /** Interrupt Enable mask The mask can be for one interrupt or * OR of multiple interrupts. */ Uint32 inten; /** Prescalar, Clock Low and Clock High for Clock Setup */ CSL_I2cClkSetup *clksetup; } CSL_I2cHwSetup; /** @brief Enumeration for queries passed to @a CSL_i2cGetHwStatus() * * This is used to get the status of different operations or to get the * existing setup of I2C. */ typedef enum { /** * @brief Get current clock setup parameters * @param (CSL_I2cClkSetup *) */ CSL_I2C_QUERY_CLOCK_SETUP = 1, /** * @brief Get the Bus Busy status information * @param (Uint16*) */ CSL_I2C_QUERY_BUS_BUSY = 2, /** * @brief Get the Receive Ready status information * @param (Uint16*) */ CSL_I2C_QUERY_RX_RDY = 3, /** * @brief Get the Transmit Ready status information * @param (Uint16*) */ CSL_I2C_QUERY_TX_RDY = 4, /** * @brief Get the Register Ready status information * @param (Uint16*) */ CSL_I2C_QUERY_ACS_RDY = 5, /** * @brief Get the Stop Condition Data bit information * @param (Uint16*) */ CSL_I2C_QUERY_SCD = 6, /** * @brief Get the Address Zero (General Call) detection status * @param (Uint16*) */ CSL_I2C_QUERY_AD0 = 7, /** * @brief Get the Receive overflow status information * @param (Uint16*) */ CSL_I2C_QUERY_RSFULL = 8, /** * @brief Get the Transmit underflow status information * @param (Uint16*) */ CSL_I2C_QUERY_XSMT = 9, /** * @brief Get the Address as Slave bit information * @param (Uint16*) */ CSL_I2C_QUERY_AAS = 10, /** * @brief Get the Arbitration Lost status information * @param (Uint16*) */ CSL_I2C_QUERY_AL = 11, /** * @brief Get the Reset Done status bit information * @param (Uint16*) */ CSL_I2C_QUERY_RDONE = 12, /** * @brief Get no of bits of next byte to be received or transmitted * @param (Uint16*) */ CSL_I2C_QUERY_BITCOUNT = 13, /** * @brief Get the interrupt code for the interrupt that occured * @param (Uint16*) */ CSL_I2C_QUERY_INTCODE = 14, /** * @brief Get the slave direction * @param (Uint16*) */ CSL_I2C_QUERY_SDIR = 15, /** * @brief Get the acknowledgement status * @param (Uint16*) */ CSL_I2C_QUERY_NACKSNT = 16 } CSL_I2cHwStatusQuery; /** @brief Enumeration for queries passed to @a CSL_i2cHwControl() * * This is used to select the commands to control the operations * existing setup of I2C. The arguments to be passed with each * enumeration if any are specified next to the enumeration. */ typedef enum { /** * @brief Enable the I2C * @param (None) */ CSL_I2C_CMD_ENABLE = 1, /** * @brief Reset command to the I2C * @param (None) */ CSL_I2C_CMD_RESET = 2, /** * @brief Bring the I2C out of reset * @param (None) */ CSL_I2C_CMD_OUTOFRESET = 3, /** * @brief Clear the status bits. The argument next to the command * specifies the status bit to be cleared. The status bit * can be : * CSL_I2C_CLEAR_AL, * CSL_I2C_CLEAR_NACK, * CSL_I2C_CLEAR_ARDY, * CSL_I2C_CLEAR_RRDY, * CSL_I2C_CLEAR_XRDY, * CSL_I2C_CLEAR_GC * @param (None) */ CSL_I2C_CMD_CLEAR_STATUS = 4, /** * @brief Set the address of the Slave device * @param (Uint16 *) */ CSL_I2C_CMD_SET_SLAVE_ADDR = 5, /** * @brief Set the Data Count * @param (Uint16 *) */ CSL_I2C_CMD_SET_DATA_COUNT = 6, /** * @brief Set the start condition * @param (None) */ CSL_I2C_CMD_START = 7, /** * @brief Set the stop condition * @param (None) */ CSL_I2C_CMD_STOP = 8, /** * @brief Set the transmission mode * @param (None) */ CSL_I2C_CMD_DIR_TRANSMIT = 9, /** * @brief Set the receiver mode * @param (None) */ CSL_I2C_CMD_DIR_RECEIVE = 10, /** * @brief Set the Repeat Mode * @param (None) */ CSL_I2C_CMD_RM_ENABLE = 11, /** * @brief Disable the Repeat Mode * @param (None) */ CSL_I2C_CMD_RM_DISABLE = 12, /** * @brief Set the loop back mode * @param (None) */ CSL_I2C_CMD_DLB_ENABLE = 13, /** * @brief Disable the loop back mode * @param (None) */ CSL_I2C_CMD_DLB_DISABLE = 14 } CSL_I2cHwControlCmd; /**************************************************************************\ * I2C global function declarations \**************************************************************************/ /** ============================================================================ * @n@b CSL_i2cInit * * @b Description * @n This is the initialization function for the I2C. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. * * @b Arguments @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Status status; ... status = CSL_i2cInit(); ... @endverbatim * =========================================================================== */ CSL_Status CSL_i2cInit ( CSL_I2cContext *pContext ); /** ============================================================================ * @n@b CSL_i2cOpen * * @b Description * @n This function populates the peripheral data object for the instance * and returns a handle to the instance. * The open call sets up the data structures for the particular instance * of I2C device. The device can be re-opened anytime after it has been * normally closed if so required. The handle returned by this call is * input as an essential argument for rest of the APIs described for * this module. * * @b Arguments * @verbatim pI2cObj Pointer to the I2C instance object i2cNum Instance of the I2C to be opened. pI2cParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * Return Value * CSL_I2cHandle * Valid I2C instance handle will be returned if status value is * equal to CSL_SOK. * * Pre Condition * @n @a CSL_i2cInit() must be called successfully. * * Post Condition * @n i2c instance will be opened * * @b Modifies * @n None * * @b Example: * @verbatim CSL_status status; CSL_I2cObj i2cObj; CSL_I2cHandle hI2c; ... hI2c = CSL_I2cOpen (&i2cObj, CSL_I2C, NULL, &status ); ... @endverbatim * * =========================================================================== */ CSL_I2cHandle CSL_i2cOpen ( CSL_I2cObj *hI2cObj, CSL_InstNum i2cNum, CSL_I2cParam *pI2cParam, CSL_Status *status ); /** ============================================================================ * @n@b CSL_i2cClose * * @b Description * @n This function closes the specified instance of I2C. * * @b Arguments * @verbatim hI2c Handle to the I2C @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Close Successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * Pre Condition * @n The device should be successfully opened. * * Post Condition * @n None * * @b Modifies * @n I2C Handle * * @b Example * @verbatim CSL_I2cHandle hI2c; ... status = CSL_i2cClose(hI2c); ... @endverbatim * ============================================================================ */ CSL_Status CSL_i2cClose ( CSL_I2cHandle hI2c ); /** ============================================================================ * @n@b CSL_i2cHwSetup * * @b Description * @n This function initializes the device registers with the appropriate * values provided through the HwSetup Data structure. This function needs * to be called only if the HwSetup Structure was not previously passed * through the Open call. After the Setup is completed, the device is ready * for operation.For information passed through the HwSetup Data structure * refer @a CSL_i2cHwSetup. * @b Arguments * @verbatim hI2c Handle to the I2C setup Pointer to setup structure which contains the information to program I2C to a useful state @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup Successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before this function can be called. The user has to * allocate space for & fill in the main setup structure appropriately * before calling this function. * * Post Condition * @n The registers of the specified I2C instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified I2C instance. * * @b Example * @verbatim CSL_i2cHandle hI2c; CSL_i2cHwSetup hwSetup = CSL_I2C_HWSETUP_DEFAULTS; ... CSL_i2cHwSetup(hI2c, &hwSetup); ... @endverbatim * =========================================================================== */ CSL_Status CSL_i2cHwSetup ( CSL_I2cHandle hI2c, CSL_I2cHwSetup *setup ); /** ============================================================================ * @n@b CSL_i2cGetHwSetup * * @b Description * @n This function gets the current setup of the I2C. The status is * returned through @a CSL_I2cHwSetup. The obtaining of status * is the reverse operation of @a CSL_i2cHwSetup() function. * * @b Arguments * @verbatim hI2c Handle to the I2C hwSetup Pointer to the hardware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Retrieving the hardware setup * parameters is successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cGetHwSetup() can be called. * * Post Condition * @n The hardware setup structure is populated with the hardware setup * parameters * * @b Modifies * @n hwSetup variable * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cHwSetup hwSetup; ... status = CSL_i2cGetHwSetup(hI2c, &hwSetup); ... @endverbatim * =========================================================================== */ CSL_Status CSL_i2cGetHwSetup ( CSL_I2cHandle hI2c, CSL_I2cHwSetup *setup ); /** ============================================================================ * @n@b CSL_i2cHwControl * * @b Description * @n Control operations for the I2C. For a particular control operation, * the pointer to the corresponding data type need to be passed as argument * to HwControl function Call.All the arguments(Structure element included) * passed to the HwControl function are inputs. For the list of commands * supported and argument type that can be @a void* casted & passed with a * particular command refer to @a CSL_I2cHwControlCmd. * @b Arguments * @verbatim hI2c Handle to the I2C instance cmd The command to this API indicates the action to be taken on I2C. arg An optional argument. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cHwControl() can be called. * * Post Condition * @n None * * @b Modifies * @n The hardware registers of I2C. * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cHwControlCmd cmd = CSL_I2C_CMD_RESET; void arg; CSL_Status status; ... status = CSL_i2cHwControl (hI2c, cmd, &arg); ... @endverbatim * ============================================================================= */ CSL_Status CSL_i2cHwControl ( CSL_I2cHandle hI2c, CSL_I2cHwControlCmd cmd, void *arg ); /** ============================================================================ * @n@b CSL_i2cRead * * @b Description * @n This function reads I2C data. * * @b Arguments * @verbatim hI2c Handle to I2C instance buf Buffer to store the data read @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Operation Successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cRead() can be called. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example: * @verbatim Uint16 outData; CSL_Status status; CSL_I2cHandle hI2c; ... // I2C object defined and HwSetup structure defined and initialized ... // Init, Open, HwSetup successfully done in that order ... status = CSL_i2cRead(hI2c, &outData); @endverbatim * =========================================================================== */ CSL_Status CSL_i2cRead ( CSL_I2cHandle hI2c, void *buf ); /** ============================================================================ * @n@b CSL_i2cWrite * * @b Description * @n This function writes the specified data into I2C data register. * * @b Arguments * @verbatim hI2c Handle to I2C instance buf data to be written @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Success (doesnot verify written data) * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cWrite() can be called. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example: * @verbatim Uint16 inData; CSL_Status status; CSL_I2cHandle hI2c; ... // I2C object defined and HwSetup structure defined and initialized ... // Init, Open, HwSetup successfully done in that order ... status = CSL_i2cWrite(hi2c, &inData); @endverbatim * =========================================================================== */ CSL_Status CSL_i2cWrite ( CSL_I2cHandle hI2c, void *buf ); /** ============================================================================ * @n@b CSL_i2cHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hI2c Handle to the I2C config Pointer to config structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not * properly initialized * * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cHwSetupRaw() can be called. * * Post Condition * @n The registers of the specified I2C instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified I2C instance. * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cConfig config = CSL_I2C_CONFIG_DEFAULTS; CSL_Status status; ... status = CSL_i2cHwSetupRaw(hI2c, &config); ... @endverbatim * =========================================================================== */ CSL_Status CSL_i2cHwSetupRaw ( CSL_I2cHandle hI2c, CSL_I2cConfig *config ); /** ============================================================================ * @n@b CSL_i2cGetHwStatus * * @b Description * @n This function is used to read the current device configuration, status * flags and the value present associated registers.Following table details * the various status queries supported and the associated data structureto * record the response. User should allocate memory for the said data type * and pass its pointer as an unadorned void* argument to the status query * call.For details about the various status queries supported and the * associated data structure to record the response, * refer to @a CSL_I2cHwStatusQuery * * @b Arguments * @verbatim hI2c Handle to the I2C instance query The query to this API of I2C which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Status info return successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVQUERY - Invalid query command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cGetHwStatus() can be called. * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cHwStatusQuery query; void reponse; status = CSL_i2cGetHwStatus(hI2c, query, &response); @endverbatim * ============================================================================= */ CSL_Status CSL_i2cGetHwStatus ( CSL_I2cHandle hI2c, CSL_I2cHwStatusQuery query, void *response ); /** ============================================================================ * @n@b CSL_i2cGetBaseAddress * * @b Description * @n Function to get the base address of the peripheral instance. * This function is used for getting the base address of the peripheral * instance. This function will be called inside the CSL_i2cOpen() * function call. This function is open for re-implementing if the user * wants to modify the base address of the peripheral object to point to * a different location and there by allow CSL initiated write/reads into * peripheral MMR's go to an alternate location. * * @b Arguments * @verbatim i2cNum Specifies the instance of I2C to be opened. pI2cParam Module specific parameters. pBaseAddress Pointer to baseaddress structure containing base address details. @endverbatim * * Return Value CSL_Status * @li CSL_OK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * * Pre Condition * @n None * * Post Condition * @n Base Address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_I2cBaseAddress baseAddress; ... status = CSL_i2cGetBaseAddress(CSL_I2C, NULL, &baseAddress); @endverbatim * =========================================================================== */ CSL_Status CSL_i2cGetBaseAddress ( CSL_InstNum i2cNum, CSL_I2cParam *pI2cParam, CSL_I2cBaseAddress *pBaseAddress ); #ifdef __cplusplus } #endif #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/cache/_csl_cache.c

<filename>DSP/TI-Header/csl_c6455_src/src/cache/_csl_cache.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /* ============================================================================ * @file _csl_cache.c * * @path $(CSLPATH)\src\cache * * @desc File for functional layer of CSL API _CSL_cacheApplyPatch() and * _CACHE_wait () * */ /* ============================================================================= * Revision History * =============== * 23-Mar-2004 <NAME> File Created * * 21-Jun-2004 <NAME> modified. * * ============================================================================= */ #include <csl_cache.h> #include <_csl_cache.h> #pragma DATA_SECTION (_CSL_cachebusyState, ".bss:csl_section:cache"); volatile CACHE_waitState _CSL_cachebusyState = CACHE_WAIT_NONE; #pragma DATA_SECTION (_CSL_cacheEmifState, ".bss:csl_section:cache"); volatile CACHE_emifState _CSL_cacheEmifState = CACHE_EMIF_NONE; /* ============================================================================ * @n@b _CSL_cacheApplyPatch * * @b Description * @n This API used to set the cacheability of the specified EMIF range. * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... _CSL_cacheApplyPatch (); ... @endverbatim * ============================================================================ */ #pragma CODE_SECTION (_CSL_cacheApplyPatch, ".text:csl_section:cache"); void _CSL_cacheApplyPatch(void) { switch (_CSL_cacheEmifState) { case CACHE_EMIF_NONE: break; case CACHE_EMIF_A: CSL_CACHE_EMIFA_PATCH(); break; case CACHE_EMIF_B: CSL_CACHE_EMIFB_PATCH(); break; case CACHE_EMIF_AB: CSL_CACHE_EMIFA_PATCH(); CSL_CACHE_EMIFB_PATCH(); break; } _CSL_cacheEmifState = CACHE_EMIF_NONE; } /* ============================================================================ * @n@b _CACHE_wait * * @b Description * @n This API call the CACHE_waitInternal() and CACHE_wait() APIs. * * @b Arguments * @n wait - Specifies whether the cache operations should block * till the desired operation is complete * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim ... _CACHE_wait(CACHE_NOWAIT); ... @endverbatim * ============================================================================ */ #pragma CODE_SECTION (_CACHE_wait, ".text:csl_section:cache"); void _CACHE_wait ( CACHE_Wait wait ) { if (wait == CACHE_WAITINTERNAL) CACHE_waitInternal(); else CACHE_wait(); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/gpio/src/Gpio_example.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * * @file gpioExample.c * * @path $(CSLPATH)\example\gpio\src * * @desc example for GPIO. * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @verbatim This Example, 1. Initializes INTC, enables NMIs, enables event 2. Initializes and opens GPIO CSL module 3. Configures pin 5 to generate an interrupt on rising edge and configures the pin as an output. 4. Enables the bank interrupt. 5. Sets data high. 6. Waits for interrupt to be generated 7. Sets the data low and closes the GPIO instance. * * ============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project gpioExample.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================= * Revision History * =============== * 23-Sep-2005 PSK File Created * * 07-Nov-2005 NG Updated documentation * * ============================================================================= */ #include <csl_gpio.h> #include <csl_intc.h> #include <stdio.h> #include <string.h> #include <csl_intcAux.h> #include <cslr_dev.h> /* Locals & Forwards */ void gpioInternalLoopbackDemo(void); /* Globals */ CSL_GpioHandle hGpio; volatile Uint8 intrCnt; int demoFail = 0; /* Interrupt module Declarations */ CSL_IntcObj gpioIntcObj; CSL_IntcHandle gpioIntcHandle; CSL_IntcContext context; CSL_IntcEventHandlerRecord isr_gpio; CSL_IntcEventHandlerRecord record[1]; /* * ============================================================================= * @func HandleGPIO_INT * * @arg * NONE * * @desc * This function is Handler for Interrupt. * * @return * NONE * * ============================================================================= */ void HandleGPIO_INT ( void *arg ) { intrCnt++; return; } /* * ============================================================================= * @func main * * @desc * This is the main routine, which invokes the example script. * * ============================================================================= */ void main ( void ) { Bool gpioEn; /* Unlock the control register */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the GPIO */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_GPIOCTL, ENABLE); do { gpioEn = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_GPIOSTAT); } while (gpioEn != TRUE); printf("Powersaver clock for GPIO is enabled\n"); /* Invoking example script */ gpioInternalLoopbackDemo(); if (demoFail) { printf("\nGPIO: EXAMPLE fails. \n"); } else { printf("\nGPIO: EXAMPLE completed\n"); } return; } /* * ============================================================================= * @func gpioInternalLoopbackDemo * * @arg * NONE * * @desc * Gives demo for the internal loopback mechanism for the interrupt path; * the value sent on a output pin can trigger a Rising or Falling edge * interrupt. * * @return * NONE * * ============================================================================= */ void gpioInternalLoopbackDemo ( void ) { CSL_Status intStat; CSL_GpioPinConfig config; CSL_GpioPinNum pinNum; CSL_Status status; CSL_GpioContext pContext; CSL_GpioObj gpioObj; CSL_GpioHwSetup hwSetup; CSL_IntcGlobalEnableState state; CSL_IntcParam vectId; /* Initialize INTC */ context.numEvtEntries = 1; context.eventhandlerRecord = record; intStat = CSL_intcInit(&context); if (intStat != CSL_SOK) { printf("INTR: Initialization error.\n"); demoFail++; return; } /* Enable NMIs */ intStat = CSL_intcGlobalNmiEnable(); if (intStat != CSL_SOK) { printf("INTR: Error while enabling NMI.\n"); demoFail++; return; } /* Enable all interrupts */ intStat = CSL_intcGlobalEnable(&state); if (intStat != CSL_SOK) { printf("INTR: Error while enabling interrupt.\n"); demoFail++; return; } /* Open interrupt module */ vectId = CSL_INTC_VECTID_12; gpioIntcHandle = CSL_intcOpen(&gpioIntcObj, CSL_INTC_EVENTID_GPINT5, &vectId, &intStat); if ((gpioIntcHandle == NULL) || (intStat != CSL_SOK)) { printf("INTR: Error opening the instance.\n"); demoFail++; return; } /* Bind ISR to Interrupt */ isr_gpio.handler = (CSL_IntcEventHandler)&HandleGPIO_INT; isr_gpio.arg = gpioIntcHandle; CSL_intcPlugEventHandler(gpioIntcHandle, &isr_gpio); /* Event Enable */ CSL_intcHwControl(gpioIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL); if (intStat != CSL_SOK) { printf("INTR: Error in enabling event.\n"); demoFail++; return; } /* Initialize the GPIO CSL module */ status = CSL_gpioInit(&pContext); if (status != CSL_SOK) { printf("GPIO: Initialization error.\n"); demoFail++; return; } /* Open the CSL module */ hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO, NULL, &status); if ((hGpio == NULL) || (status != CSL_SOK)) { printf("GPIO: Error opening the instance.\n"); demoFail++; return; } intrCnt = 0; /* Setup hardware parameters */ hwSetup.extendSetup = NULL; /* Setup the General Purpose IO */ status = CSL_gpioHwSetup(hGpio, &hwSetup); /* Configure pin 5 to generate an interrupt on Rising Edge, and * configure it as an output, then set the data High (Low->High). * Set Trigger: */ config.pinNum = CSL_GPIO_PIN5; config.trigger = CSL_GPIO_TRIG_RISING_EDGE; config.direction = CSL_GPIO_DIR_OUTPUT; /* Enable the bank interrupt */ status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_BANK_INT_ENABLE, NULL); if (status != CSL_SOK) { printf("GPIO: Command to enable bank interrupt... Failed.\n"); demoFail++; } /* configure the gpio pin 5 */ status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_CONFIG_BIT, &config); if (status != CSL_SOK) { printf("GPIO: GPIO pin configuration error.\n"); demoFail++; return; } /* Set Data High: */ pinNum = CSL_GPIO_PIN5; status = CSL_gpioHwControl (hGpio, CSL_GPIO_CMD_SET_BIT, &pinNum); if (status != CSL_SOK) { printf("GPIO: Command to set bit... Failed.\n"); demoFail++; return; } /* Wait for interrupt to be generated. */ while (1) { if (intrCnt == 1) break; } printf("\n GPIO: Interrupt Occurred.\n"); /* Set Data Low again: */ pinNum = CSL_GPIO_PIN5; status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_CLEAR_BIT, &pinNum); if (status != CSL_SOK) { printf("GPIO: Command to clear bit... Failed.\n"); demoFail++; return; } status = CSL_gpioClose(hGpio); if (status != CSL_SOK) { printf("GPIO: Unable to Close the instance.[status = 0x%x].\n", status); demoFail++; return; } }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/mcbsp/_csl_mcbspBlockAssign.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /* ============================================================================ * @file _csl_mcbspBlockAssign.c * * @path $(CSLPATH)\src\mcbsp * * @desc File for functional layer of CSL API _CSL_mcbspBlockAssign() * */ /* ============================================================================= * Revision History * ================ * June 29,2004 <NAME> - Created * * ============================================================================= */ #include <csl_mcbsp.h> #include <_csl_mcbsp.h> /* ============================================================================ * @n@b _CSL_mcbspBlockAssign * * @b Description * @n The funtion is used to assign block to a particular partition * This is an Internal function and is used by the CSL_mcbspHwControl * function * * @b Arguments * @verbatim hMcbsp Handle to MCBSP Obj used partition Partition to which the block is to be assigned block Identifies the block @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Successful completion * @li CSL_ESYS_FAIL - Operation could not the done * @li CSL_ESYS_BADHANDLE - Invalid Handle * * Pre Condition * @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully * in that order before _CSL_mcbspBlockAssign() can be called. * * Post Condition * @n Assign block to a specified partition * * @b Modifies * @n None * * @b Example * @verbatim CSL_McbspHandle hMcbsp; ... CSL_mcbspBlockAssign(hMcbsp, CSL_MCBSP_PARTITION_ATX, \ CSL_MCBSP_BLOCK0); ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (_CSL_mcbspBlockAssign, ".text:csl_section:mcbsp"); CSL_Status _CSL_mcbspBlockAssign ( CSL_McbspHandle hMcbsp, CSL_McbspPartition partition, CSL_McbspBlock block ) { CSL_Status status = CSL_SOK; if (partition & 0x01) { if ((CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_RMCME) == 0) && (CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_RMCM) == 1)) { if ((block & 0x01) && partition == 3) { /* Odd blocks can be assinged to only partition B */ CSL_FINS( hMcbsp->regs->MCR, MCBSP_MCR_RPBBLK, block ); } else { if ((!(block & 0x01)) && partition == 1) { /* Even blocks can be assinged to only partition A */ CSL_FINS( hMcbsp->regs->MCR, MCBSP_MCR_RPABLK, block ); } else status = CSL_EMCBSP_INVPARAMS; } } else status = CSL_EMCBSP_INVMODE; } else { if ((CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_XMCME) == 0) && (CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_XMCM) != 0)) { if ((block & 0x01) && partition == 2) { /* Odd blocks can be assinged to only partition B */ CSL_FINS( hMcbsp->regs->MCR, MCBSP_MCR_XPBBLK, block ); } else { if ((!(block & 0x01)) && partition == 0) { /* Even blocks can be assinged to only partition A */ CSL_FINS( hMcbsp->regs->MCR, MCBSP_MCR_XPABLK, block ); } else status = CSL_EMCBSP_INVPARAMS; } } else status = CSL_EMCBSP_INVMODE; } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_vcp2.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * =========================================================================== */ /** =========================================================================== * @file csl_vcp2.h * * @path $(CSLPATH)\inc * * @desc API header for VCP2 * */ /** @mainpage VCP2 CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the VCP2 module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given VCP2 module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular VCP2 Module. The CSL developer should use his discretion * designing new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# VCP2 FUNCTIONAL SPEC 2.00.W.12 * */ /* ============================================================================ * Revision History * ================ * 24-March-2005 SPrasad File Created. * 27-May-2005 SPrasad Updated with new requirements' specification. * 03-Aug-2005 Chandra Minor changes to beautify the file. * 08-dec-2005 sd changed the maxSm and minSm to be signed * integers * 07-mar-2006 ds Rename of Out order tokens according to register * header file. * - CSL_VCP2_VCPIC3_OUT_ORDER_0_31 to * CSL_VCP2_VCPIC3_OUT_ORDER_LSB and * - CSL_VCP2_VCPIC3_OUT_ORDER_31_0 to * CSL_VCP2_VCPIC3_OUT_ORDER_MSB * * ============================================================================ */ #ifndef _CSL_VCP2_H_ #define _CSL_VCP2_H_ #include <csl.h> #include <cslr_vcp2.h> #include <soc.h> #ifdef __cplusplus extern "C" { #endif /****************************************************************************** * VCP Macros *****************************************************************************/ /** Code rate = 2 */ #define VCP2_RATE_1_2 2 /** Code rate = 3 */ #define VCP2_RATE_1_3 3 /** Code rate = 4 */ #define VCP2_RATE_1_4 4 /** Speed critical */ #define VCP2_SPEED_CRITICAL 0 /** Speed most critical */ #define VCP2_SPEED_MOST_CRITICAL 1 /** Performance critical */ #define VCP2_PERF_CRITICAL 2 /** Performance most critical */ #define VCP2_PERF_MOST_CRITICAL 3 /** Default value */ #define VCP2_PERF_DEFAULT VCP2_SPEED_CRITICAL /** Out order of VCP output for decoded data : 0 to 31 */ #define VCP2_OUTORDER_0_31 CSL_VCP2_VCPIC3_OUT_ORDER_LSB /** Out order of VCP output for decoded data : 31 to 0 */ #define VCP2_OUTORDER_31_0 CSL_VCP2_VCPIC3_OUT_ORDER_MSB /** Output decision type : Hard decisions */ #define VCP2_DECISION_HARD CSL_VCP2_VCPIC5_SDHD_HARD /** Output decision type : Soft decisions */ #define VCP2_DECISION_SOFT CSL_VCP2_VCPIC5_SDHD_SOFT /** Output parameters read flag : VCP read event is not generated */ #define VCP2_OUTF_NO CSL_VCP2_VCPIC5_OUTF_NO /** Output parameters read flag : VCP read event is generated */ #define VCP2_OUTF_YES CSL_VCP2_VCPIC5_OUTF_YES /** No trace back allowed */ #define VCP2_TRACEBACK_NONE CSL_VCP2_VCPIC5_TB_NO /** Traceback mode : Tailed */ #define VCP2_TRACEBACK_TAILED CSL_VCP2_VCPIC5_TB_TAIL /** Traceback mode : Convergent */ #define VCP2_TRACEBACK_CONVERGENT CSL_VCP2_VCPIC5_TB_CONV /** Traceback mode : Mixed */ #define VCP2_TRACEBACK_MIXED CSL_VCP2_VCPIC5_TB_MIX /** * VCP unpause type : VCP restarts and processes one sliding window before * pausing again */ #define VCP2_UNPAUSE_ONESW CSL_VCP2_VCPEXE_COMMAND_RESTART_PAUSE /** VCP unpause type : VCP restarts */ #define VCP2_UNPAUSE_NORMAL CSL_VCP2_VCPEXE_COMMAND_RESTART /** Soft decisions memory format : 32-bit word packed */ #define VCP2_END_PACKED32 CSL_VCP2_VCPEND_SD_32BIT /** Soft decisions memory format : Native (8 bits) */ #define VCP2_END_NATIVE CSL_VCP2_VCPEND_SD_NATIVE /** EMU mode : VCP halts at the end of completion of the current window of * state metric processing or at the end of a frame */ #define VCP2_EMUHALT_DEFAULT CSL_VCP2_VCPEMU_SOFT_HALT_DEFAULT /** * EMU mode : VCP halts at the end of completion of the processing of the * frame */ #define VCP2_EMUHALT_FRAMEEND CSL_VCP2_VCPEMU_SOFT_HALT_FRAMEEND /*************************************************************************** * Following are Polynomials used in GSM/Edge/GPRS **************************************************************************/ /** * GSM/Edge/GPRS generator polynomial 0 */ #define VCP2_GEN_POLY_0 0x30 /** * GSM/Edge/GPRS generator polynomial 1 */ #define VCP2_GEN_POLY_1 0xB0 /** * GSM/Edge/GPRS generator polynomial 2 */ #define VCP2_GEN_POLY_2 0x50 /** * GSM/Edge/GPRS generator polynomial 3 */ #define VCP2_GEN_POLY_3 0xF0 /** * GSM/Edge/GPRS generator polynomial 4 */ #define VCP2_GEN_POLY_4 0x6C /** * GSM/Edge/GPRS generator polynomial 5 */ #define VCP2_GEN_POLY_5 0x94 /** * GSM/Edge/GPRS generator polynomial 6 */ #define VCP2_GEN_POLY_6 0xF4 /** * GSM/Edge/GPRS generator polynomial 7 */ #define VCP2_GEN_POLY_7 0xE4 /** * NULL generator polynomial for GSM/Edge/GPRS */ #define VCP2_GEN_POLY_GNULL 0x00 /****************************************************************************** * VCP global typedef declarations *****************************************************************************/ /** * Handle to access VCP2 registers accessible through config bus. */ #define hVcp2 ((CSL_Vcp2ConfigRegs*)CSL_VCP2_0_REGS) /** * Handle to access VCP2 registers accessible through EDMA bus. */ #define hVcp2Vbus ((CSL_Vcp2EdmaRegs *)CSL_VCP2_EDMA_REGS) /** * VCP code rate type */ typedef Uint32 VCP2_Rate; /** * VCP input configuration structure that holds all of the configuration * values that are to be transferred to the VCP via the EDMA. */ typedef struct { /** Value of VCP input configuration register 0 */ Uint32 ic0; /** Value of VCP input configuration register 1 */ Uint32 ic1; /** Value of VCP input configuration register 2 */ Uint32 ic2; /** Value of VCP input configuration register 3 */ Uint32 ic3; /** Value of VCP input configuration register 4 */ Uint32 ic4; /** Value of VCP input configuration register 5 */ Uint32 ic5; } VCP2_ConfigIc; /** * VCP channel parameters structure that holds all of the information * concerning the user channel. These values are used to generate the * appropriate input configuration values for the VCP and to program * the EDMA. */ typedef struct { /** Code rate */ VCP2_Rate rate; /** Constraint length */ Uint8 constLen; /** Polynomial 0 */ Uint8 poly0; /** Polynomial 1 */ Uint8 poly1; /** Polynomial 2 */ Uint8 poly2; /** Polynomial 3 */ Uint8 poly3; /** Yamamoto threshold value*/ Uint16 yamTh; /** Frame length i.e. number of symbols in a frame*/ Uint16 frameLen; /** Reliability length */ Uint16 relLen; /** Convergence distance */ Uint16 convDist; /** Traceback state index */ Uint16 traceBackIndex; /** Traceback state index enable/disable */ Bool traceBackEn; /** Hard decision output ordering */ Uint16 outOrder; /** Maximum initial state metric */ Int16 maxSm; /** Minimum initial state metric */ Int16 minSm; /** State index set to the maximum initial state metric*/ Uint8 stateNum; /** Branch metrics buffer length in input FIFO */ Uint8 bmBuffLen; /** Decisions buffer length in output FIFO */ Uint8 decBuffLen; /** Traceback mode */ Uint8 traceBack; /** Output parameters read flag */ Uint8 readFlag; /** Decision selection: hard or soft */ Uint8 decision; /** Number of branch metric frames*/ Uint16 numBmFrames; /** Number of decision frames */ Uint16 numDecFrames; } VCP2_Params; /** * VCP base parameter structure that is used to configure the VCP parameters * structure with the given values using VCP2_genParams() function. */ typedef struct { /** Code rate */ VCP2_Rate rate; /** Constraint length */ Uint8 constLen; /** Frame length */ Uint16 frameLen; /** Yamamoto threshold value */ Uint16 yamTh; /** Maximum initial state metric value */ Uint8 stateNum; /** Traceback convergement mode */ Bool tbConvrgMode; /** Output decision type */ Uint8 decision; /** Output parameters read flag */ Uint8 readFlag; /** Enable/Disable tail biting */ Bool tailBitEnable; /** Tailbiting traceback index mode */ Uint16 traceBackIndex; /** Hard decision output ordering */ Uint8 outOrder; /** Performance and speed */ Uint8 perf; } VCP2_BaseParams; /** VCP Error structure */ typedef struct { /** Traceback mode error */ Bool tbnaErr; /** Frame length error */ Bool ftlErr; /** Reliability + convergence distance error */ Bool fctlErr; /** Max-Min error */ Bool maxminErr; /** SYMX error */ Bool symxErr; /** SYMR error */ Bool symrErr; } VCP2_Errors; /** VCP generator polynomials structure */ typedef struct { /** Generator polynomial 0 */ Uint8 poly0; /** Generator polynomial 1 */ Uint8 poly1; /** Generator polynomial 2 */ Uint8 poly2; /** Generator polynomial 3 */ Uint8 poly3; } VCP2_Poly; /****************************************************************************** * VCP2 global function declarations *****************************************************************************/ /* * ============================================================================ * @func VCP2_genParams * * @desc * This function calculates the VCP parameters based on the input * VCP2_BaseParams object values and set the values to the output * VCP2_Params parameters structure. * * @arg pConfigBase * Pointer to VCP base parameters structure. * * @arg pConfigParams * Pointer to output VCP channel parameters structure. * * @ret None * * @eg * VCP2_Params vcpParam; * VCP2_BaseParams vcpBaseParam; * ... * vcpBaseParam.rate = VCP2_RATE_1_4; * vcpBaseParam.constLen = 5; * vcpBaseParam.frameLen = 2042; * vcpBaseParam.yamTh = 50; * vcpBaseParam.stateNum = 2048; * vcpBaseParam.tbConvrgMode = FALSE; * vcpBaseParam.decision = VCP2_DECISION_HARD; * vcpBaseParam.readFlag = VCP2_OUTF_YES; * vcpBaseParam.tailBitEnable = FALSE; * vcpBaseParam.traceBackIndex = 0x0; * vcpBaseParam.outOrder = VCP2_OUTORDER_0_31; * vcpBaseParam.perf = VCP2_SPEED_CRITICAL; * ... * VCP2_genParams (&vcpBaseParam, &vcpParam); * * ============================================================================ */ extern void VCP2_genParams ( VCP2_BaseParams * pConfigBase, VCP2_Params * pConfigParams ); /* * ============================================================================ * @func VCP2_genIc * * @desc * This function generates the required input configuration registers' * values needed to program the VCP based on the parameters provided by * VCP2_Params object values. * * @arg pConfigParams * Pointer to channel parameters structure. * * @arg pConfigIc * Pointer to input configuration structure. * * @ret None * * @eg * VCP2_Params vcpParam; * VCP2_ConfigIc vcpConfig; * VCP2_BaseParams vcpBaseParam; * ... * vcpBaseParam.rate = VCP2_RATE_1_4; * vcpBaseParam.constLen = 5; * vcpBaseParam.frameLen = 2042; * vcpBaseParam.yamTh = 50; * vcpBaseParam.stateNum = 2048; * vcpBaseParam.tbConvrgMode = FALSE; * vcpBaseParam.decision = VCP2_DECISION_HARD; * vcpBaseParam.readFlag = VCP2_OUTF_YES; * vcpBaseParam.tailBitEnable = FALSE; * vcpBaseParam.traceBackIndex = 0x0; * vcpBaseParam.outOrder = VCP2_OUTORDER_0_31; * vcpBaseParam.perf = VCP2_SPEED_CRITICAL; * ... * VCP2_genParams (&vcpBaseParam, &vcpParam); * * VCP2_genIc (&vcpParam, &vcpConfig); * * ============================================================================ */ extern void VCP2_genIc ( VCP2_Params * pConfigParams, VCP2_ConfigIc * pConfigIc ); #ifdef __cplusplus } #endif #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_ectl.h

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_ectl.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for ECTL */ #ifndef _CSLR_ECTL_H_ #define _CSLR_ECTL_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint8 RSVD0[4]; volatile Uint32 EWCTL; volatile Uint32 EWINTTCNT; } CSL_EctlRegs; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* EWCTL */ #define CSL_ECTL_EWCTL_INTEN_MASK (0x00000001u) #define CSL_ECTL_EWCTL_INTEN_SHIFT (0x00000000u) #define CSL_ECTL_EWCTL_INTEN_RESETVAL (0x00000000u) /*----INTEN Tokens----*/ #define CSL_ECTL_EWCTL_INTEN_DISABLE (0x00000000u) #define CSL_ECTL_EWCTL_INTEN_ENABLE (0x00000001u) #define CSL_ECTL_EWCTL_RESETVAL (0x00000000u) /* EWINTTCNT */ #define CSL_ECTL_EWINTTCNT_EWINTTCNT_MASK (0x0001FFFFu) #define CSL_ECTL_EWINTTCNT_EWINTTCNT_SHIFT (0x00000000u) #define CSL_ECTL_EWINTTCNT_EWINTTCNT_RESETVAL (0x00000000u) #define CSL_ECTL_EWINTTCNT_RESETVAL (0x00000000u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/FB_Example/MEA21_lib.h

#include <csl_types.h> #include "global.h" #define MEA21_REGISTER(reg) (*(volatile Uint32 *)(0xa0000000+reg)) #define READ_REGISTER(reg) MEA21_REGISTER(reg) #define WRITE_REGISTER(reg, value) {MEA21_REGISTER(reg) = value; (*(volatile Uint32 *)(0x70000000)) = 0; (*(volatile Uint32 *)(0x70000000));} #ifdef INCLUDE_HS1_DATA #define HS1_CHANNELS 120 #define HS1_DATA_WORDS (HS1_CHANNELS+2) #define HS1_DATA_ENABLE 0x0200 #else #define HS1_CHANNELS 0 #define HS1_DATA_WORDS 0 #define HS1_DATA_ENABLE 0 #endif #ifdef INCLUDE_HS2_DATA #define HS2_CHANNELS 120 #define HS2_DATA_WORDS (HS2_CHANNELS+2) #define HS2_DATA_ENABLE 0x0400 #else #define HS2_CHANNELS 0 #define HS2_DATA_WORDS 0 #define HS2_DATA_ENABLE 0 #endif #ifdef INCLUDE_IF_DATA #define IF_CHANNELS 8 #define IF_DATA_WORDS (IF_CHANNELS+1) #define IF_DATA_ENABLE 0x0800 #else #define IF_CHANNELS 0 #define IF_DATA_WORDS 0 #define IF_DATA_ENABLE 0 #endif #ifdef INCLUDE_HS1_FILTER_DATA #define HF1_CHANNELS 120 #define HF1_DATA_WORDS (HF1_CHANNELS+2) #define HF1_DATA_ENABLE 0x4000 #else #define HF1_CHANNELS 0 #define HF1_DATA_WORDS 0 #define HF1_DATA_ENABLE 0 #endif #ifdef INCLUDE_HS2_FILTER_DATA #define HF2_CHANNELS 120 #define HF2_DATA_WORDS (HF2_CHANNELS+2) #define HF2_DATA_ENABLE 0x8000 #else #define HF2_CHANNELS 0 #define HF2_DATA_WORDS 0 #define HF2_DATA_ENABLE 0 #endif #ifdef INCLUDE_DIGITAL_DATA #define DIGITAL_CHANNELS 31 #define DIGITAL_DATA_WORDS (DIGITAL_CHANNELS+1) #define DIGITAL_DATA_ENABLE 0x1000 #else #define DIGITAL_CHANNELS 0 #define DIGITAL_DATA_WORDS 0 #define DIGITAL_DATA_ENABLE 0 #endif #ifdef INCLUDE_TIMESTAMP_DATA #define TIMESTAMP_CHANNELS 2 #define TIMESTAMP_DATA_WORDS (TIMESTAMP_CHANNELS+1) #define TIMESTAMP_DATA_ENABLE 0x2000 #else #define TIMESTAMP_CHANNELS 0 #define TIMESTAMP_DATA_WORDS 0 #define TIMESTAMP_DATA_ENABLE 0 #endif #define HS1_DATA_OFFSET (1) #define HS2_DATA_OFFSET (HS1_DATA_OFFSET + HS1_DATA_WORDS) #define IF_DATA_OFFSET (HS2_DATA_OFFSET + HS2_DATA_WORDS) #define HF1_DATA_OFFSET (IF_DATA_OFFSET + IF_DATA_WORDS) #define HF2_DATA_OFFSET (HF1_DATA_OFFSET + HF1_DATA_WORDS) #define DIGITAL_DATA_OFFSET (HF2_DATA_OFFSET + HF2_DATA_WORDS) #define TIMESTAMP_DATA_OFFSET (DIGITAL_DATA_OFFSET + DIGITAL_DATA_WORDS) #define CHANNELS_PER_FRAME (HS1_DATA_WORDS+HS2_DATA_WORDS+IF_DATA_WORDS+HF1_DATA_WORDS+HF2_DATA_WORDS+DIGITAL_DATA_WORDS+TIMESTAMP_DATA_WORDS) #define DSPINDATACTRL_VALUE (0x0100| HS1_DATA_ENABLE | HS2_DATA_ENABLE | IF_DATA_ENABLE | DIGITAL_DATA_ENABLE | TIMESTAMP_DATA_ENABLE | HF1_DATA_ENABLE | HF2_DATA_ENABLE ) // Enable IRQ and selected data streams extern Uint32 MeaData[CHANNELS_PER_FRAME*FRAMES_PER_LOOP]; extern Uint32 MonitorData[MONITOR_ARRAY]; #define DSP_INDATA_CTRL 0x0400 #define DSP_OUTDATA_CTRL 0x0404 #define DSP_OUTDATA_THR 0x0414 #define FEEDBACK_REGISTER 0x0780 #define MAILBOX_CTRL 0x0424 void MEA21_init(); void SetMonitorSize(int datapoints);

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_mcbsp.h

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_mcbsp.h * * @path $(CSLPATH)\inc * * @desc Header file for functional layer of McBSP CSL * */ /** @mainpage MCBSP CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the MCBSP module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given MCBSP module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular MCBSP Module. The CSL developer should use his discretion * designing new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 * */ /* ============================================================================= * Revision History * ================ * June 29,2004 <NAME> - Created * * May 17,2005 <NAME> - Removed support for 512 channel mode * - Removed support for Super synchronization * - IntEvent removed from CSL_McbspHwSetup and * added commands and queries for interrupt mode * - CSL_MCBSP_CMD_REG_RESET changed to * CSL_MCBSP_CMD_RESET * * July 04, 2005 ds - Removed support for DX Mode.Hence removed * dxState from CSL_McbspHwSetup * - Removed support for enhanced sample clock * mode. * - Register Naming convention used for * Multichannel registers are changed according * the changes in cslr_mcbsp.h * * July 26, 2005 ds - Removed control cmd * CSL_MCBSP_CMD_IO_MODE_CONTROL. * * Sept 21, 2005 ds - Removed the DXR and DRR register from the * config data structure * * Oct 27, 2005 ds - Removed CSL_MCBSP_QUERY_PID query from * CSL_McbspHwStatusQuery * * Feb 02 , 2006 ds - IntEvent added to CSL_McbspHwSetup and * removed interrupt mode commands and queries * ============================================================================= */ #ifndef _CSL_MCBSP_H_ #define _CSL_MCBSP_H_ #ifdef __cplusplus extern "C" { #endif #include <soc.h> #include <csl.h> #include <cslr_mcbsp.h> /**************************************************************************\ * MCBSP global macro declarations \**************************************************************************/ /** * Use this symbol as pin mask for @a CSL_mcbspIoRead() and * CSL_mcbspIoWrite() functions */ /** I/O Pin Input/Output configuration for CLKX Pin */ #define CSL_MCBSP_IO_CLKX (1) /** I/O Pin Input/Output configuration for FSX Pin */ #define CSL_MCBSP_IO_FSX (2) /** Not Configurable. Always Output. */ #define CSL_MCBSP_IO_DX (4) /** I/O Pin Input/Output configuration for CLKR Pin */ #define CSL_MCBSP_IO_CLKR (8) /** I/O Pin Input/Output configuration for FSR Pin */ #define CSL_MCBSP_IO_FSR (16) /** Not Configurable. Always Input. */ #define CSL_MCBSP_IO_DR (32) /** Not Configurable. Always Input. */ #define CSL_MCBSP_IO_CLKS (64) /** * Use this symbol as enable/disable control bitmask for * CSL_mcbspHwControl() function */ /** To enable Receiver in resetControl Function */ #define CSL_MCBSP_CTRL_RX_ENABLE (1) /** To enable Transmitter in resetControl Function */ #define CSL_MCBSP_CTRL_TX_ENABLE (2) /** To disable Receiver in resetControl Function */ #define CSL_MCBSP_CTRL_RX_DISABLE (4) /** To disable Transmitter in resetControl Function */ #define CSL_MCBSP_CTRL_TX_DISABLE (8) /** To enable Frame Sync Generation in resetControl Function */ #define CSL_MCBSP_CTRL_FSYNC_ENABLE (16) /** To enable Sample Rate Generator in resetControl Function */ #define CSL_MCBSP_CTRL_SRG_ENABLE (32) /** To disable Frame Sync Generation in resetControl Function */ #define CSL_MCBSP_CTRL_FSYNC_DISABLE (64) /** To disable Sample Rate Generator in resetControl Function */ #define CSL_MCBSP_CTRL_SRG_DISABLE (128) /** * Use this symbol to compare the return value of @a CSL_mcbspGetHwStatus() * function for @a CSL_MCBSP_QUERY_DEV_STATUS query * \n For eg:- On RFULL event, (response & CSL_MCBSP_RFULL) == 0x0004 */ /** RCV ready status */ #define CSL_MCBSP_RRDY 0x0001 /** XMT ready status */ #define CSL_MCBSP_XRDY 0x0002 /** RCV full status */ #define CSL_MCBSP_RFULL 0x0004 /** XMT empty status */ #define CSL_MCBSP_XEMPTY 0x0008 /** RCV frame sync error status */ #define CSL_MCBSP_RSYNCERR 0x0010 /** XMT frame sync error status */ #define CSL_MCBSP_XSYNCERR 0x0020 /** CSL_EMCBSP_SYMBOL Error codes */ /** Invalid Control Command */ #define CSL_EMCBSP_INVCNTLCMD (CSL_EMCBSP_FIRST - 0) /** Invalid Query */ #define CSL_EMCBSP_INVQUERY (CSL_EMCBSP_FIRST - 1) /** Invalid Parameter */ #define CSL_EMCBSP_INVPARAMS (CSL_EMCBSP_FIRST - 2) /** Invalid Size */ #define CSL_EMCBSP_INVSIZE (CSL_EMCBSP_FIRST - 3) /** 'Does not exist' */ #define CSL_EMCBSP_NOTEXIST (CSL_EMCBSP_FIRST - 4) /** Invalid mode to conduct operation */ #define CSL_EMCBSP_INVMODE (CSL_EMCBSP_FIRST - 5) /** CSL_MCBSP_DEFAULT_SYMBOL MCBSP CSL Defaults */ /** Data Setup defaults */ #define CSL_MCBSP_DATASETUP_DEFAULTS { \ (CSL_McbspPhase)CSL_MCBSP_PHASE_SINGLE, \ (CSL_McbspWordLen)CSL_MCBSP_WORDLEN_16, \ 1, \ (CSL_McbspWordLen)0, \ 0, \ (CSL_McbspFrmSync)CSL_MCBSP_FRMSYNC_DETECT, \ (CSL_McbspCompand)CSL_MCBSP_COMPAND_OFF_MSB_FIRST, \ (CSL_McbspDataDelay)CSL_MCBSP_DATADELAY_0_BIT, \ (CSL_McbspRjustDxena)0, \ (CSL_McbspIntMode)CSL_MCBSP_INTMODE_ON_READY, \ (CSL_McbspBitReversal)CSL_MCBSP_32BIT_REVERS_DISABLE }\ /** Clock Setup defaults */ #define CSL_MCBSP_CLOCKSETUP_DEFAULTS { \ (CSL_McbspFsClkMode)CSL_MCBSP_FSCLKMODE_EXTERNAL, \ (CSL_McbspFsClkMode)CSL_MCBSP_FSCLKMODE_EXTERNAL, \ (CSL_McbspTxRxClkMode)CSL_MCBSP_TXRXCLKMODE_INTERNAL, \ (CSL_McbspTxRxClkMode)CSL_MCBSP_TXRXCLKMODE_EXTERNAL, \ (CSL_McbspFsPol)0, \ (CSL_McbspFsPol)0, \ (CSL_McbspClkPol)0, \ (CSL_McbspClkPol)0, \ 1, \ 0x40, \ 0xFF, \ (CSL_McbspSrgClk)0, \ (CSL_McbspClkPol)0, \ (CSL_McbspTxFsMode)CSL_MCBSP_TXFSMODE_SRG, \ (CSL_McbspClkgSyncMode)CSL_MCBSP_CLKGSYNCMODE_OFF }\ /** Multichannel Setup defaults */ #define CSL_MCBSP_MULTICHAN_DEFAULTS { \ (CSL_McbspPartMode)CSL_MCBSP_PARTMODE_2PARTITION, \ (CSL_McbspPartMode)CSL_MCBSP_PARTMODE_2PARTITION, \ (Uint16)0, \ (Uint16)0, \ (CSL_McbspPABlk)CSL_MCBSP_PABLK_0, \ (CSL_McbspPBBlk)CSL_MCBSP_PBBLK_1, \ (CSL_McbspPABlk)CSL_MCBSP_PABLK_0, \ (CSL_McbspPBBlk)CSL_MCBSP_PBBLK_1, \ }\ /** Global parameters Setup defaults */ #define CSL_MCBSP_GLOBALSETUP_DEFAULTS { \ (CSL_McbspIOMode)CSL_MCBSP_IOMODE_TXDIS_RXDIS, \ (CSL_McbspDlbMode)CSL_MCBSP_DLBMODE_OFF, \ (CSL_McbspClkStp)CSL_MCBSP_CLKSTP_DISABLE } \ /** Default Emulation mode - Stop */ #define CSL_MCBSP_EMUMODE_DEFAULT CSL_MCBSP_EMU_STOP /** Extend Setup default - NULL */ #define CSL_MCBSP_EXTENDSETUP_DEFAULT NULL /**************************************************************************\ * MCBSP global typedef declarations \**************************************************************************/ /** * Word lengths supported on MCBSP.Use this symbol for setting Word * Length in each Phase for every Frame */ typedef enum { /** Word Length for Frame is 8 */ CSL_MCBSP_WORDLEN_8 = 0, /** Word Length for Frame is 12 */ CSL_MCBSP_WORDLEN_12 = 1, /** Word Length for Frame is 16 */ CSL_MCBSP_WORDLEN_16 = 2, /** Word Length for Frame is 20 */ CSL_MCBSP_WORDLEN_20 = 3, /** Word Length for Frame is 24 */ CSL_MCBSP_WORDLEN_24 = 4, /** Word Length for Frame is 32 */ CSL_MCBSP_WORDLEN_32 = 5 } CSL_McbspWordLen; /** * MCBSP companding options - Use this symbol to set Companding related options */ typedef enum { /** no companding for msb */ CSL_MCBSP_COMPAND_OFF_MSB_FIRST = 0, /** no companding for lsb */ CSL_MCBSP_COMPAND_OFF_LSB_FIRST = 1, /** mu-law comapanding enable for channel */ CSL_MCBSP_COMPAND_MULAW = 2, /** A-law comapanding enable for channel */ CSL_MCBSP_COMPAND_ALAW = 3 } CSL_McbspCompand; /** * Data delay in bits - Use this symbol to set XMT/RCV Data Delay (in bits) */ typedef enum { /** sets XMT/RCV Data Delay is 0 */ CSL_MCBSP_DATADELAY_0_BIT = 0, /** sets XMT/RCV Data Delay is 1 */ CSL_MCBSP_DATADELAY_1_BIT = 1, /** sets XMT/RCV Data Delay is 2 */ CSL_MCBSP_DATADELAY_2_BITS = 2 } CSL_McbspDataDelay; /** * MCBSP Interrupt mode - * Use this symbol to set Interrupt mode (i.e. source of interrupt generation). * This symbol is used on both RCV and XMT for RINT and XINT generation mode. */ typedef enum { /** Interrupt generated on RRDY of RCV or XRDY of XMT */ CSL_MCBSP_INTMODE_ON_READY = 0, /** Interrupt generated on end of 16-channel block transfer * in multichannel mode */ CSL_MCBSP_INTMODE_ON_EOB = 1, /** Interrupt generated on frame sync */ CSL_MCBSP_INTMODE_ON_FSYNC = 2, /** Interrupt generated on synchronisation error */ CSL_MCBSP_INTMODE_ON_SYNCERR = 3 } CSL_McbspIntMode; /** * Frame sync clock source - Use this symbol to set the frame sync clock * source as internal or external */ typedef enum { /** frame sync clock source as external */ CSL_MCBSP_FSCLKMODE_EXTERNAL = 0, /** frame sync clock source as internal */ CSL_MCBSP_FSCLKMODE_INTERNAL = 1 } CSL_McbspFsClkMode; /** * Clock source - Use this symbol to set the clock source as * internal or external */ typedef enum { /** clock source as external */ CSL_MCBSP_TXRXCLKMODE_EXTERNAL = 0, /** clock source as internal */ CSL_MCBSP_TXRXCLKMODE_INTERNAL = 1 } CSL_McbspTxRxClkMode; /** * Frame sync polarity - Use this symbol to set frame sync polarity as * active-high or active-low */ typedef enum { /** frame sync polarity is active-high */ CSL_MCBSP_FSPOL_ACTIVE_HIGH = 0, /** frame sync polarity is active-low */ CSL_MCBSP_FSPOL_ACTIVE_LOW = 1 } CSL_McbspFsPol; /** * Clock polarity - Use this symbol to set XMT or RCV clock polarity as * rising or falling edge */ typedef enum { /** XMT clock polarity is rising edge */ CSL_MCBSP_CLKPOL_TX_RISING_EDGE = 0, /** RCV clock polarity is falling edge */ CSL_MCBSP_CLKPOL_RX_FALLING_EDGE = 0, /** SRG clock polarity is rising edge */ CSL_MCBSP_CLKPOL_SRG_RISING_EDGE = 0, /** XMT clock polarity is falling edge */ CSL_MCBSP_CLKPOL_TX_FALLING_EDGE = 1, /** RCV clock polarity is rising edge */ CSL_MCBSP_CLKPOL_RX_RISING_EDGE = 1, /** SRG clock polarity Is falling edge */ CSL_MCBSP_CLKPOL_SRG_FALLING_EDGE = 1 } CSL_McbspClkPol; /** * SRG clock source - Use this symbol to select input clock source * for Sample Rate Generator */ typedef enum { /** input clock source for Sample Rate Generator is CLKS pin */ CSL_MCBSP_SRGCLK_CLKS = 0, /** input clock source for Sample Rate Generator is CPU */ CSL_MCBSP_SRGCLK_CLKCPU = 1 } CSL_McbspSrgClk; /** * XMT Frame Sync generation mode - Use this symbol to set XMT Frame Sync * generation mode */ typedef enum { /** Disables the frame sync generation mode */ CSL_MCBSP_TXFSMODE_DXRCOPY = 0, /** Enables the frame sync generation mode */ CSL_MCBSP_TXFSMODE_SRG = 1 } CSL_McbspTxFsMode; /** * XMT and RCV IO Mode - Use this symbol to Enable/Disable IO Mode * for XMT and RCV */ typedef enum { /** Disable the both XMT and RCV IO mode */ CSL_MCBSP_IOMODE_TXDIS_RXDIS = 0, /** Disable XMT and enable RCV IO mode */ CSL_MCBSP_IOMODE_TXDIS_RXEN = 1, /** Enable XMT and Disble RCV IO mode */ CSL_MCBSP_IOMODE_TXEN_RXDIS = 2, /** Enable XMT and enable RCV IO mode */ CSL_MCBSP_IOMODE_TXEN_RXEN = 3 } CSL_McbspIOMode; /** * Clock Stop Mode - Use this symbol to Enable/Disable Clock Stop Mode */ typedef enum { /** Disable the clock stop mode */ CSL_MCBSP_CLKSTP_DISABLE = 0, /** Emable the clock stop mode with out delay */ CSL_MCBSP_CLKSTP_WITHOUT_DELAY = 2, /** Emable the clock stop mode with delay */ CSL_MCBSP_CLKSTP_WITH_DELAY = 3 } CSL_McbspClkStp; /** * Multichannel mode Partition type - Use this symbol to select the partition * type in multichannel mode */ typedef enum { /** two partition mode */ CSL_MCBSP_PARTMODE_2PARTITION = 0, /** Eight partition multichannel mode */ CSL_MCBSP_PARTMODE_8PARTITION = 1 } CSL_McbspPartMode; /** * Multichannel mode PartitionA block - Use this symbol to assign Blocks to * Partition-A in multichannel mode */ typedef enum { /** Block 0 for partition A */ CSL_MCBSP_PABLK_0 = 0, /** Block 2 for partition A */ CSL_MCBSP_PABLK_2 = 1, /** Block 4 for partition A */ CSL_MCBSP_PABLK_4 = 2, /** Block 6 for partition A */ CSL_MCBSP_PABLK_6 = 3 } CSL_McbspPABlk; /** * Multichannel mode PartitionB block - Use this symbol to assign Blocks to * Partition-B in multichannel mode */ typedef enum { /** Block 1 for partition B */ CSL_MCBSP_PBBLK_1 = 0, /** Block 3 for partition B */ CSL_MCBSP_PBBLK_3 = 1, /** Block 5 for partition B */ CSL_MCBSP_PBBLK_5 = 2, /** Block 7 for partition B */ CSL_MCBSP_PBBLK_7 = 3 } CSL_McbspPBBlk; /** * Emulation mode setting - Use this symbol to set the Emulation Mode */ typedef enum { /** Emulation mode stop */ CSL_MCBSP_EMU_STOP = 0, /** Emulation mode TX stop */ CSL_MCBSP_EMU_TX_STOP = 1, /** Emulation free run mode */ CSL_MCBSP_EMU_FREERUN = 2 } CSL_McbspEmu; /** * Multichannel mode Partition select - Use this symbol in multichannel mode to * select the Partition for assigning a block to */ typedef enum { /** TX partition for A */ CSL_MCBSP_PARTITION_ATX = 0, /** RX partition for A */ CSL_MCBSP_PARTITION_ARX = 1, /** TX partition for B */ CSL_MCBSP_PARTITION_BTX = 2, /** RX partition for B */ CSL_MCBSP_PARTITION_BRX = 3 } CSL_McbspPartition; /** * Multichannel mode Block select - Use this symbol in multichannel mode to * select block on which the operation is to be performed */ typedef enum { /** Block 0 for multichannel mode */ CSL_MCBSP_BLOCK_0 = 0, /** Block 1 for multichannel mode */ CSL_MCBSP_BLOCK_1 = 1, /** Block 2 for multichannel mode */ CSL_MCBSP_BLOCK_2 = 2, /** Block 3 for multichannel mode */ CSL_MCBSP_BLOCK_3 = 3, /** Block 4 for multichannel mode */ CSL_MCBSP_BLOCK_4 = 4, /** Block 5 for multichannel mode */ CSL_MCBSP_BLOCK_5 = 5, /** Block 6 for multichannel mode */ CSL_MCBSP_BLOCK_6 = 6, /** Block 7 for multichannel mode */ CSL_MCBSP_BLOCK_7 = 7 } CSL_McbspBlock; /** * Channel control in multichannel mode * Use this symbol to enable/disable a channel in multichannel mode. * This is a member of CSL_McbspChanControl structure, which is input to * CSL_mcbspHwControl() function for CSL_MCBSP_CMD_CHANNEL_CONTROL command */ typedef enum { /** TX enable for multichannel mode */ CSL_MCBSP_CHCTRL_TX_ENABLE = 0, /** TX disable for multichannel mode */ CSL_MCBSP_CHCTRL_TX_DISABLE = 1, /** RX enable for multichannel mode */ CSL_MCBSP_CHCTRL_RX_ENABLE = 2, /** RX disable for multichannel mode */ CSL_MCBSP_CHCTRL_RX_DISABLE = 3 } CSL_McbspChCtrl; /** * Channel type: TX, RX or both - Use this symbol to select the channel type for * CSL_mcbspHwControl() */ typedef enum { /** Channel type is RX */ CSL_MCBSP_CHTYPE_RX = 1, /** Channel type is TX */ CSL_MCBSP_CHTYPE_TX = 2, /** Channel type is TXRX */ CSL_MCBSP_CHTYPE_TXRX = 4 } CSL_McbspChType; /** * Digital Loopback mode selection - Use this symbol to enable/disable digital * loopback mode */ typedef enum { /** disable digital loopback mode */ CSL_MCBSP_DLBMODE_OFF = 0, /** enable digital loopback mode */ CSL_MCBSP_DLBMODE_ON = 1 } CSL_McbspDlbMode; /** * Phase count selection - Use this symbol to select number of phases per frame */ typedef enum { /** Single phase for frame */ CSL_MCBSP_PHASE_SINGLE = 0, /** Dual phase for frame */ CSL_MCBSP_PHASE_DUAL = 1 } CSL_McbspPhase; /** * Frame sync ignore status - Use this symbol to detect or ignore * frame synchronisation */ typedef enum { /** detect frame synchronisation */ CSL_MCBSP_FRMSYNC_DETECT = 0, /** ignore frame synchronisation */ CSL_MCBSP_FRMSYNC_IGNORE = 1 } CSL_McbspFrmSync; /** * RJUST or DXENA settings - Use this symbol for setting up RCV sign-extension * and justification mode or enabling/disabling XMT DX pin delay */ typedef enum { /** RCV setting - right justify, fill MSBs with zeros */ CSL_MCBSP_RJUSTDXENA_RJUST_RZF = 0, /** XMT setting - Delay at DX pin disabled */ CSL_MCBSP_RJUSTDXENA_DXENA_OFF = 0, /** RCV setting - right justify, sign-extend the data into MSBs */ CSL_MCBSP_RJUSTDXENA_RJUST_RSE = 1, /** XMT setting - Delay at DX pin enabled */ CSL_MCBSP_RJUSTDXENA_DXENA_ON = 1, /** RCV setting - left justify, fill LSBs with zeros */ CSL_MCBSP_RJUSTDXENA_RJUST_LZF = 2 } CSL_McbspRjustDxena; /** * CLKG sync mode selection - Use this symbol to enable/disable CLKG * synchronisation when input CLK source for SRGR is external */ typedef enum { /** disable CLKG synchronisation */ CSL_MCBSP_CLKGSYNCMODE_OFF = 0, /** enable CLKG synchronisation */ CSL_MCBSP_CLKGSYNCMODE_ON = 1 } CSL_McbspClkgSyncMode; /** * Tx/Rx reset status - Use this symbol to compare the output of * CSL_mcbspGetHwStatus() for CSL_MCBSP_QUERY_TX_RST_STAT and * CSL_MCBSP_QUERY_RX_RST_STAT queries */ typedef enum { /** disable the XRST bit */ CSL_MCBSP_RSTSTAT_TX_IN_RESET = 0, /** disable the RRST bit */ CSL_MCBSP_RSTSTAT_RX_IN_RESET = 0, /** enable the XRST bit */ CSL_MCBSP_RSTSTAT_TX_OUTOF_RESET = 1, /** enable the RRST bit */ CSL_MCBSP_RSTSTAT_RX_OUTOF_RESET = 1 } CSL_McbspRstStat; /** McBSP 32-bit reversal feature */ typedef enum { /** 32-bit reversal disabled */ CSL_MCBSP_32BIT_REVERS_DISABLE = 0, /** 32-bit reversal enabled. 32-bit data is received LSB first. Word length * should be set for 32-bit operation; else operation undefined */ CSL_MCBSP_32BIT_REVERS_ENABLE = 1 } CSL_McbspBitReversal; /** * This is the set of control commands that are passed to * CSL_mcbspHwControl(), with an optional argument type-casted to void* * The arguments, if any, to be passed with each command are specified * next to that command. */ typedef enum { /** * @brief Assigns a block to a particular partition in multichannel * mode * @param (CSL_McbspBlkAssign *) */ CSL_MCBSP_CMD_ASSIGN_BLOCK = 0, /** * @brief Enables or disables a channel in multichannel mode * @param (CSL_McbspChanControl *) */ CSL_MCBSP_CMD_CHANNEL_CONTROL = 1, /** * @brief Clears frame sync error for XMT or RCV * @param (CSL_McbspChType *) */ CSL_MCBSP_CMD_CLEAR_FRAME_SYNC = 2, /** * @brief Resets all the registers to their power-on default values * @param None */ CSL_MCBSP_CMD_RESET = 3, /** * @brief Enable/Disable - Frame Sync, Sample Rate Generator and * XMT/RCV Operation * @param (CSL_BitMask16 *) */ CSL_MCBSP_CMD_RESET_CONTROL = 4 } CSL_McbspControlCmd; /** * This is the set of query commands to get the status of various * operations in MCBSP * The arguments, if any, to be passed with each command are specified * next to that command */ typedef enum { /** * @brief Queries the current XMT block * @param (CSL_McbspBlock *) */ CSL_MCBSP_QUERY_CUR_TX_BLK = 1, /** * @brief Queries the current RCV block * @param (CSL_McbspBlock *) */ CSL_MCBSP_QUERY_CUR_RX_BLK = 2, /** * @brief Queries the status of RRDY, XRDY, RFULL, XEMPTY, RSYNCERR * and XSYNCERR events and returns them in supplied * CSL_BitMask16 argument * @param (CSL_BitMask16 *) */ CSL_MCBSP_QUERY_DEV_STATUS = 3, /** * @brief Queries XMT reset status * @param (CSL_McbspRstStat *) * @return CSL_SOK */ CSL_MCBSP_QUERY_TX_RST_STAT = 4, /** * @brief Queries RCV reset status * @param (CSL_McbspRstStat *) */ CSL_MCBSP_QUERY_RX_RST_STAT = 5 } CSL_McbspHwStatusQuery; /** * This will have the base-address information for the peripheral instance */ typedef struct { /** Base-address of the Configuration registers of MCBSP */ CSL_McbspRegsOvly regs; } CSL_McbspBaseAddress; /** * MCBSP specific parameters. Present implementation doesn't have * any specific parameters. */ typedef struct { /** Bit mask to be used for module specific parameters. * The below declaration is just a place-holder for future * implementation. */ CSL_BitMask16 flags; } CSL_McbspParam; /** * MCBSP specific context information. Present implementation doesn't * have any Context information. */ typedef struct { /** Context information of MCBSP. * The below declaration is just a place-holder for future * implementation. */ Uint16 contextInfo; } CSL_McbspContext; /** * Pointer to this structure is used as the third argument in * CSL_mcbspHwControl() for block assignment in multichannel mode */ typedef struct CSL_McbspBlkAssign { /** Partition to choose */ CSL_McbspPartition partition; /** Block to choose */ CSL_McbspBlock block; } CSL_McbspBlkAssign; /** * Pointer to this structure is used as the third argument in * CSL_mcbspHwControl() for channel control operations (Enable/Disable TX/RX) * in multichannel mode. */ typedef struct CSL_McbspChanControl { /** Channel number to control */ Uint16 channelNo; /** Control operation */ CSL_McbspChCtrl operation; } CSL_McbspChanControl; /** * This is a sub-structure in @ CSL_McbspHwSetup. This structure is used for * configuring input/output data related parameters. */ typedef struct CSL_McbspDataSetup { /** Number of phases in a frame */ CSL_McbspPhase numPhases; /** Number of bits per word in phase 1 */ CSL_McbspWordLen wordLength1; /** Number of words per frame in phase 1 */ Uint16 frmLength1; /** Number of bits per word in phase 2 */ CSL_McbspWordLen wordLength2; /** Number of words per frame in phase 2 */ Uint16 frmLength2; /** Frame Sync ignore */ CSL_McbspFrmSync frmSyncIgn; /** Companding options */ CSL_McbspCompand compand; /** Data delay in number of bits */ CSL_McbspDataDelay dataDelay; /** Controls DX delay for XMT or sign-extension and justification for RCV */ CSL_McbspRjustDxena rjust_dxenable; /** Interrupt event mask */ CSL_McbspIntMode intEvent; /** 32-bit reversal feature */ CSL_McbspBitReversal wordReverse; } CSL_McbspDataSetup; /** * This is a sub-structure in @a CSL_McbspHwSetup. This structure is used for * configuring Clock and Frame Sync generation parameters. */ typedef struct CSL_McbspClkSetup { /** XMT frame sync mode */ CSL_McbspFsClkMode frmSyncTxMode; /** RCV frame sync mode */ CSL_McbspFsClkMode frmSyncRxMode; /** XMT clock mode */ CSL_McbspTxRxClkMode clkTxMode; /** RCV clock mode */ CSL_McbspTxRxClkMode clkRxMode; /** XMT frame sync polarity */ CSL_McbspFsPol frmSyncTxPolarity; /** RCV frame sync polarty */ CSL_McbspFsPol frmSyncRxPolarity; /** XMT clock polarity */ CSL_McbspClkPol clkTxPolarity; /** RCV clock polarity */ CSL_McbspClkPol clkRxPolarity; /** SRG frame sync pulse width */ Uint16 srgFrmPulseWidth; /** SRG frame sync period */ Uint16 srgFrmPeriod; /** SRG divide-down ratio */ Uint16 srgClkDivide; /** SRG input clock mode */ CSL_McbspSrgClk srgInputClkMode; /** SRG clock polarity */ CSL_McbspClkPol srgClkPolarity; /** SRG XMT frame-synchronisatoin mode */ CSL_McbspTxFsMode srgTxFrmSyncMode; /** SRG clock synchronisation mode */ CSL_McbspClkgSyncMode srgClkSync; } CSL_McbspClkSetup; /** * This is a sub-structure in @a CSL_McbspHwSetup. This structure is used * for configuring the parameters global to MCBSP */ typedef struct CSL_McbspGlobalSetup { /** XMT and RCV IO enable bit */ CSL_McbspIOMode ioEnableMode; /** Digital Loopback mode */ CSL_McbspDlbMode dlbMode; /** Clock stop mode */ CSL_McbspClkStp clkStopMode; } CSL_McbspGlobalSetup; /** * This is a sub-structure in @a CSL_McbspHwSetup. This structure is used * for configuring Multichannel mode parameters */ typedef struct CSL_McbspMulChSetup { /** RCV partition */ CSL_McbspPartMode rxPartition; /** XMT partition */ CSL_McbspPartMode txPartition; /** RCV multichannel selection mode */ Uint16 rxMulChSel; /** XMT multichannel selection mode */ Uint16 txMulChSel; /** RCV partition A block */ CSL_McbspPABlk rxPartABlk; /** RCV partition B block */ CSL_McbspPBBlk rxPartBBlk; /** XMT partition A block */ CSL_McbspPABlk txPartABlk; /** XMT partition B block */ CSL_McbspPBBlk txPartBBlk; } CSL_McbspMulChSetup; /** * This is the Setup structure for configuring MCBSP using CSL_mcbspHwSetup() * function. */ typedef struct CSL_McbspHwSetup { /** Global configuration parameters */ CSL_McbspGlobalSetup *global; /** RCV data setup related parameters */ CSL_McbspDataSetup *rxdataset; /** XMT data setup related parameters */ CSL_McbspDataSetup *txdataset; /** Clock configuration parameters */ CSL_McbspClkSetup *clkset; /** Multichannel mode configuration parameters */ CSL_McbspMulChSetup *mulCh; /** Emulation mode parameters */ CSL_McbspEmu emumode ; /** Any extra parameters, for future use */ void *extendSetup; } CSL_McbspHwSetup; /** * This structure/object holds the context of the instance of MCBSP * opened using CSL_mcbspOpen() function. * * Pointer to this object is passed as MCBSP Handle to all MCBSP CSL APIs. * CSL_mcbspOpen() function intializes this structure based on the parameters * passed */ typedef struct CSL_McbspObj { /** Pointer to the register overlay structure of the MCBSP */ CSL_McbspRegsOvly regs; /** Instance of MCBSP being referred by this object */ CSL_InstNum perNum; } CSL_McbspObj; /** This is a pointer to @a CSL_McbspObj and is passed as the first * parameter to all MCBSP CSL APIs */ typedef struct CSL_McbspObj *CSL_McbspHandle; /**************************************************************************\ * Register Configuration Structure of MCBSP \**************************************************************************/ /** @brief Config structure of MCBSP. * * This is used to configure MCBSP using CSL_HwSetupRaw function */ typedef struct { /** Config structure of MCBSP. This is used to configure MCBSP * using CSL_HwSetupRaw function */ /** Serial Port Control Register */ volatile Uint32 SPCR; /** Receive Control Register */ volatile Uint32 RCR; /** Transmit Control Register */ volatile Uint32 XCR; /** Sample Rate Generator Register */ volatile Uint32 SRGR; /** Multichannel Control Register */ volatile Uint32 MCR; /** Receive Channel Enable Register for Partition A and B */ volatile Uint32 RCERE0; /** Transmit Channel Enable Register for Partition A and B */ volatile Uint32 XCERE0; /** Pin Control Register */ volatile Uint32 PCR; /** Receive Channel Enable Register for Partition C and D */ volatile Uint32 RCERE1; /** Transmit Channel Enable Register for Partition C and D */ volatile Uint32 XCERE1; /** Receive Channel Enable Register for Partition E and F */ volatile Uint32 RCERE2; /** Transmit Channel Enable Register for Partition E and F */ volatile Uint32 XCERE2; /** Receive Channel Enable Register for Partition G and H */ volatile Uint32 RCERE3; /** Transmit Channel Enable Register for Partition G and H */ volatile Uint32 XCERE3; } CSL_McbspConfig; /** Default Values for Config structure */ #define CSL_MCBSP_CONFIG_DEFAULTS { \ CSL_MCBSP_SPCR_RESETVAL, \ CSL_MCBSP_RCR_RESETVAL, \ CSL_MCBSP_XCR_RESETVAL, \ CSL_MCBSP_SRGR_RESETVAL, \ CSL_MCBSP_MCR_RESETVAL, \ CSL_MCBSP_RCERE0_RESETVAL, \ CSL_MCBSP_XCERE0_RESETVAL, \ CSL_MCBSP_PCR_RESETVAL, \ CSL_MCBSP_RCERE1_RESETVAL, \ CSL_MCBSP_XCERE1_RESETVAL, \ CSL_MCBSP_RCERE2_RESETVAL, \ CSL_MCBSP_XCERE2_RESETVAL, \ CSL_MCBSP_RCERE3_RESETVAL, \ CSL_MCBSP_XCERE3_RESETVAL \ } /* ************************************************************************\ * MCBSP global function declarations \* ************************************************************************/ /* * ============================================================================= * @func CSL_mcbspInit * * @desc * This function is idempotent i.e. calling it many times is same as * calling it once. This function is only for book-keeping purpose * and it doesn't touch the hardware (read/write registers) in any manner. * * @arg pContext * Context information for mcbsp * * @ret CSL_Status * CSL_SOK - Always returns * * @eg * CSL_mcbspInit (NULL); * ============================================================================= */ extern CSL_Status CSL_mcbspInit ( CSL_McbspContext *pContext ); /* *============================================================================ * @func CSL_mcbspOpen * * @desc * Reserves the specified MCBSP for use. The device can be re-opened * anytime after it has been normally closed, if so required. The MCBSP * handle returned by this call is input as an essential argument for * the rest of the APIs in MCBSP module. * * @arg pMcbspObj * Pointer to the object that holds reference to the instance of MCBSP * requested after the call * * @arg mcbspNum * Instance of mcbsp CSL to be opened. * * @arg pMcbspParam * Pointer to module specific parameters * * @arg pStatus * pointer for returning status of the function call * * @ret CSL_McbspHandle * Valid mcbsp instance handle will be returned * if status value is equal to CSL_SOK. * * @eg * CSL_McbspHandle hMcbsp; * CSL_McbspObj mcbspObj; * CSL_McbspHwSetup mcbspSetup; * CSL_Status status; * ... * hMcbsp = CSL_mcbspOpen(&mcbspObj, CSL_MCBSP_0, NULL, &status); * ... * =========================================================================== */ extern CSL_McbspHandle CSL_mcbspOpen ( CSL_McbspObj *pMcbspObj, CSL_InstNum mcbspNum, CSL_McbspParam *pMcbspParam, CSL_Status *pStatus ); /* *============================================================================ * @func CSL_mcbspClose * * @desc * Unreserves the MCBSP identified by the handle passed. * * @arg hMcbsp * Mcbsp handle * * @ret CSL_Status * CSL_SOK - Close successful * CSL_ESYS_BADHANDLE - Invalid handle * * @eg * CSL_McbspHandle hMcbsp; * CSL_McbspObj mcbspObj; * CSL_McbspHwSetup mcbspSetup; * CSL_Status status; * ... * hMcbsp = CSL_mcbspOpen(&mcbspObj, CSL_MCBSP_0, NULL, &status); * ... * CSL_mcbspClose(hMcbsp); * =========================================================================== */ extern CSL_Status CSL_mcbspClose ( CSL_McbspHandle hMcbsp ); /* * ============================================================================= * @func CSL_mcbspHwSetup * * @desc * Configures the MCBSP using the values passed in the setup structure. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg hwSetup * Pointer to hardware setup structure * * @ret CSL_Status * CSL_SOK - Hardware setup successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @eg * CSL_mcbspHandle hMcbsp; * CSL_McbspHwSetup hwSetup = CSL_MCBSP_HWSETUP_DEFAULTS; * ... * * // Init Successfully done * ... * // Open Successfully done * ... * CSL_mcbspHwSetup(hMcbsp, &hwSetup); * ... * =========================================================================== */ extern CSL_Status CSL_mcbspHwSetup ( CSL_McbspHandle hMcbsp, CSL_McbspHwSetup *setup ); /* * ============================================================================= * @func CSL_mcbspHwSetupRaw * * @desc * This function initializes the device registers with the register-values * provided through the Config Data structure. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg config * Pointer to config structure * * @ret CSL_Status * CSL_SOK - Configuration successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Config structure is not * properly initialized * * @eg * CSL_mcbspHandle hMcbsp; * CSL_McbspConfig config = CSL_MCBSP_CONFIG_DEFAULTS; * CSL_Status status; * ... * status = CSL_mcbspHwSetupRaw (hMcbsp, &config); * ... * =========================================================================== */ extern CSL_Status CSL_mcbspHwSetupRaw ( CSL_McbspHandle hMcbsp, CSL_McbspConfig *config ); /* * ============================================================================= * @func CSL_mcbspRead * * @desc * Reads the data from MCBSP. The word length for the read operation is * specefied using wordLen argument. According to this word length, * appropriate amount of data will read in the data object (variable); * the pointer to which is passed as the third argument. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg wordLen * Word length of data to be read in * * @arg data * Pointer to data object (variable) that will hold the input data * * @ret CSL_Status * CSL_SOK - Read successful * CSL_EMCBSP_INVSIZE - Invalid word length * CSL_ESYS_INVPARAMS - Invalid data pointer * * @eg * CSL_mcbspHandle hMcbsp; * Uint16 inData; * CSL_Status status; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init, Open, HwSetup successfully done in that order * ... * // MCBSP SRG, Frame sync, RCV taken out of reset in that order * ... * status = CSL_mcbspRead(hMcbsp, CSL_MCBSP_WORDLEN_16, &inData); * ... * =========================================================================== */ extern CSL_Status CSL_mcbspRead ( CSL_McbspHandle hMcbsp, CSL_McbspWordLen wordLen, void *data ); /* * ============================================================================= * @func CSL_mcbspWrite * * @desc * Transmits the data from MCBSP. The word length for the write operation is * specefied using wordLen argument. According to this word length, the * appropriate amount of data will transmitted from the data object (variable); * the pointer to which is passed as the third argument. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg wordLen * Word length of data to be write * * @arg data * Pointer to data object (variable) that holds the data to be sent out * * @ret CSL_Status * CSL_SOK - Read successful * CSL_EMCBSP_INVSIZE - Invalid word length * CSL_ESYS_INVPARAMS - Invalid data pointer * * @eg * CSL_mcbspHandle hMcbsp; * Uint16 outData; * CSL_Status status; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init, Open, HwSetup successfully done in that order * ... * // MCBSP SRG, Frame sync, RCV taken out of reset in that order * ... * outData = 0x1234; * status = CSL_mcbspWrite(hMcbsp,CSL_MCBSP_WORDLEN_16,&outData); * ... * =========================================================================== */ extern CSL_Status CSL_mcbspWrite ( CSL_McbspHandle hMcbsp, CSL_McbspWordLen wordLen, void *data ); /* * ============================================================================= * @func CSL_mcbspIoWrite * * @desc * Sends the data using MCBSP pin which is configured as general purpose * output.The 16-bit data trasnmitted is specified by 'outputData' argument. * MCBSP pin to use in this write operation is identified by the second * argument. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg outputSel * MCBSP pin to be used as general purpose output * * @arg outputData * 1 bit output data to be transmitted * * @ret * None * * @eg * Uint16 outData; * CSL_Status status; * CSL_McbspHandle hMcbsp; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init, Open, HwSetup successfully done in that order * ... * outData = 1; * inData = CSL_mcbspIoWrite(hMcbsp, CSL_MCBSP_IO_CLKX, outData); * ... * =========================================================================== */ extern void CSL_mcbspIoWrite ( CSL_McbspHandle hMcbsp, CSL_BitMask16 outputSel, Uint16 outputData ); /* * ============================================================================= * @func CSL_mcbspIoWrite * * @desc * Reads the data from MCBSP pin which is configured as general purpose * input.The 16-bit data read from this pin is returned by this API. MCBSP * pin to use in this read operation is identified by the second argument. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg inputSel * MCBSP pin to be used as general purpose input * * @ret Uint16 * data read from the pin(s) * * @eg * Uint16 inData, clkx_data, clkr_data; * CSL_Status status; * CSL_BitMask16 inMask; * CSL_McbspHandle hMcbsp; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init, Open, HwSetup successfully done in that order * ... * inMask = CSL_MCBSP_IO_CLKX | CSL_MCBSP_IO_CLKR; * inData = CSL_mcbspIoRead(hMcbsp, inMask); * * if ((inData & CSL_MCBSP_IO_CLKX) != 0) * clkx_data = 1; * else * clkx_data = 0; * if ((inData & CSL_MCBSP_IO_CLKR) != 0) * clkr_data = 1; * else * clkr_data = 0; * ... * =========================================================================== */ extern Uint16 CSL_mcbspIoRead ( CSL_McbspHandle hMcbsp, CSL_BitMask16 inputSel ); /** ============================================================================ * @func CSL_mcbspHwControl * * @desc * This function takes an input control command with an optional argument * and accordingly controls the operation/configuration of MCBSP. * * @arg hMcbsp * Handle to the Mcbsp instance * * @arg cmd * Operation to be performed on the mcbsp instance * * @arg cmdArg * Arguement specific to the command * * @ret CSL_Status * CSL_SOK - Command execution successful. * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVCMD - Invalid command * CSL_ESYS_INVPARAMS - The parameter is invalid * * @eg * CSL_Status status; * CSL_BitMask16 ctrlMask; * CSL_McbspHandle hMcbsp; * ... * // MCBSP object defined and HwSetup structure defined and initialized * ... * * // Init successfully done * ... * // Open successfully done * ... * // HwSetup sucessfully done * ... * // MCBSP SRG and Frame sync taken out of reset * ... * * ctrlMask = CSL_MCBSP_CTRL_RX_ENABLE | CSL_MCBSP_CTRL_TX_ENABLE; * status = CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, * &ctrlMask); * ... * =========================================================================== */ extern CSL_Status CSL_mcbspHwControl ( CSL_McbspHandle hMcbsp, CSL_McbspControlCmd cmd, void *arg ); /** ============================================================================ * @func CSL_mcbspGetHwStatus * * @desc * Gets the status of different operations or some setup-parameters of MCBSP. * The status is returned through the third parameter. * * @arg hMcbsp * Handle to the Mcbsp instance * * @arg myQuery * Query to be performed * * @arg response * Pointer to buffer to return the data requested by the query passed * * @ret CSL_Status * CSL_SOK - Query execution successful. * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVQUERY - Invalid Query * CSL_ESYS_INVPARAMS - The parameter is invalid * * @eg * CSL_Status status; * CSL_BitMask16 ctrlMask; * CSL_McbspHandle hMcbsp; * Uint16 response; * ... * status = CSL_mcbspGetHwStatus(hMcbsp,CSL_MCBSP_QUERY_DEV_STATUS, * &response); * * if (response & CSL_MCBSP_RRDY) { * // Receiver is ready to with new data * ... * } * ... * =========================================================================== */ extern CSL_Status CSL_mcbspGetHwStatus ( CSL_McbspHandle hMcbsp, CSL_McbspHwStatusQuery myQuery, void *response ); /* * ============================================================================ * @func CSL_mcbspGetHwSetup * * @desc * Gets the status of some or all of the setup-parameters of MCBSP. * To get the status of complete MCBSP h/w setup, all the sub-structure * pointers inside the main HwSetup structure, should be non-NULL. * * @arg hMcbsp * Handle to the mcbsp instance * * @arg hwSetup * Pointer to hardware setup structure * * @ret CSL_Status * CSL_SOK - Hardware setup successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @eg * CSL_status status; * CSL_McbspGlobalSetup gblSetup; * CSL_McbspClkSetup clkSetup; * CSL_McbspEmu emuMode; * * CSL_McbspHwSetup readSetup = { &gblSetup, NULL, // RX Data-setup structure if not required NULL, // TX Data-setup structure if not required &clkSetup, NULL, // Multichannel-setup structure if not required emuMode }; * * status = CSL_mcbspGetHwSetup (hMcbs, &hwSetup); * * =========================================================================== */ extern CSL_Status CSL_mcbspGetHwSetup ( CSL_McbspHandle hMcbsp, CSL_McbspHwSetup *myHwSetup ); /** ============================================================================ * @n@b CSL_mcbspGetBaseAddress * * @b Description * @n Function to get the base address of the peripheral instance. * This function is used for getting the base address of the peripheral * instance. This function will be called inside the CSL_mcbspOpen() * function call. This function is open for re-implementing if the user * wants to modify the base address of the peripheral object to point to * a different location and there by allow CSL initiated write/reads into * peripheral. MMR's go to an alternate location. * * @b Arguments * @verbatim mcbspNum Specifies the instance of the MCBSP to be opened. pMcbspParam Module specific parameters. pBaseAddress Pointer to baseaddress structure. @endverbatim * * Return Value CSL_Status * @li CSL_OK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * * Pre Condition * @n None * * Post Condition * @n Base Address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_McbspBaseAddress baseAddress; ... status = CSL_mcbspGetBaseAddress(CSL_MCBSP_PER_CNT, NULL, &baseAddress); @endverbatim * =========================================================================== */ CSL_Status CSL_mcbspGetBaseAddress ( CSL_InstNum mcbspNum, CSL_McbspParam *pMcbspParam, CSL_McbspBaseAddress *pBaseAddress ); #ifdef __cplusplus } #endif #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cHwSetupRaw.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_i2cHwSetupRaw.c * * @brief File for functional layer of CSL API @a CSL_i2cHwSetupRaw() * * @path $(CSLPATH)\i2c\src * * Description * - The @a CSL_i2cHwSetupRaw() function definition & it's associated * functions * * Modification 1 * - Modified on: 28/5/2004 * - Reason: created the sources * * @date 28th May, 2004 * @author <NAME>. */ /* ============================================================================= * Revision History * =============== * 01-Sep-2004 Hs File Created. * 11-oct-2004 Hs updated code according to code review comments. * ============================================================================= */ #include <csl_i2c.h> /** ============================================================================ * @n@b CSL_i2cHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hI2c Handle to the I2C config Pointer to config structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not * properly initialized * * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cHwSetupRaw() can be called. * * Post Condition * @n The registers of the specified I2C instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified I2C instance. * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cConfig config = CSL_I2C_CONFIG_DEFAULTS; CSL_Status status; ... status = CSL_i2cHwSetupRaw(hI2c, &config); ... @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_i2cHwSetupRaw, ".text:csl_section:i2c"); CSL_Status CSL_i2cHwSetupRaw ( CSL_I2cHandle hI2c, CSL_I2cConfig *config ) { CSL_Status status = CSL_SOK; if (hI2c == NULL) { status = CSL_ESYS_BADHANDLE; } else if (config == NULL ) { status = CSL_ESYS_INVPARAMS; } else { hI2c->regs->ICOAR = config->ICOAR; hI2c->regs->ICIMR = config->ICIMR; hI2c->regs->ICSTR = config->ICSTR; hI2c->regs->ICCLKL = config->ICCLKL; hI2c->regs->ICCLKH = config->ICCLKH; hI2c->regs->ICCNT = config->ICCNT; hI2c->regs->ICSAR = config->ICSAR; hI2c->regs->ICDXR = config->ICDXR; hI2c->regs->ICMDR = config->ICMDR; hI2c->regs->ICIVR = config->ICIVR; hI2c->regs->ICEMDR = config->ICEMDR; hI2c->regs->ICPSC = config->ICPSC; } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_types.h

<filename>DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_types.h<gh_stars>0 /*****************************************************\ * Copyright 2003, 2005 Texas Instruments Incorporated. * * All rights reserved. * * Restricted rights to use, duplicate or disclose * * this code are granted through contract. * * * * "@(#) PSP/CSL 3.0.0.0 (2003-09-30) * \*****************************************************/ #ifndef _CSL_TYPES_H_ #define _CSL_TYPES_H_ #include <tistdtypes.h> #ifndef TRUE #define TRUE ((Bool) 1) #define FALSE ((Bool) 0) #endif typedef Int16 CSL_Uid; typedef Int16 CSL_ModuleId; typedef Uint32 CSL_Xio; typedef Uint8 CSL_BitMask8; typedef Uint16 CSL_BitMask16; typedef Uint32 CSL_BitMask32; typedef volatile Uint8 CSL_Reg8; typedef volatile Uint16 CSL_Reg16; typedef volatile Uint32 CSL_Reg32; typedef Int16 CSL_Status; typedef Int16 CSL_InstNum; typedef Int16 CSL_ChaNum; typedef unsigned long long int CSL_Uint64; typedef enum { CSL_EXCLUSIVE = 0, CSL_SHARED = 1 } CSL_OpenMode; typedef enum { CSL_FAIL = 0, CSL_PASS = 1 } CSL_Test; #ifndef NULL #define NULL ((void*)0) #endif #endif /* _CSL_TYPES_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cOpen.c

<filename>DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cOpen.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_i2cOpen.c * * @brief File for functional layer of CSL API @a CSL_i2cOpen() * * @path $(CSLPATH)\i2c\src * * Description * - The @a CSL_i2cOpen() function definition & it's associated functions * Modification 1 * - Created on: 28/05/2004 * * @date 28th May, 2004 * @author <NAME>. */ /* ============================================================================= * Revision History * =============== * 31-aug-2004 Hs Updated function and documentation for CSL_i2cOpen. * - Removed the include file, csl_resource.h. * 11-oct-2004 Hs updated code according to code review comments. * 15-nov-2005 Hs Removed the assignment of pI2cParam and redundant pStatus check * * ============================================================================= */ #include <csl_i2c.h> /** ============================================================================ * @n@b CSL_i2cOpen * * @b Description * @n This function populates the peripheral data object for the instance * and returns a handle to the instance. * The open call sets up the data structures for the particular instance * of I2C device. The device can be re-opened anytime after it has been * normally closed if so required. The handle returned by this call is * input as an essential argument for rest of the APIs described for * this module. * * @b Arguments * @verbatim pI2cObj Pointer to the I2C instance object i2cNum Instance of the I2C to be opened. pI2cParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * Return Value * CSL_I2cHandle * Valid I2C instance handle will be returned if status value is * equal to CSL_SOK. * * Pre Condition * @n @a CSL_i2cInit() must be called successfully. * * Post Condition * @n i2c instance will be opened * * @b Modifies * @n None * * @b Example: * @verbatim CSL_status status; CSL_I2cObj i2cObj; CSL_I2cHandle hI2c; ... hI2c = CSL_I2cOpen (&i2cObj, CSL_I2C, NULL, &status ); ... @endverbatim * * =========================================================================== */ #pragma CODE_SECTION (CSL_i2cOpen, ".text:csl_section:i2c"); CSL_I2cHandle CSL_i2cOpen ( CSL_I2cObj *pI2cObj, CSL_InstNum i2cNum, CSL_I2cParam *pI2cParam, CSL_Status *pStatus ) { CSL_I2cHandle hI2c = (CSL_I2cHandle)NULL; CSL_I2cBaseAddress baseAddress; /* Added according to review comment 1. */ if (pStatus == NULL) { /* do nothing : module handle is already initialized to NULL */ } else if (pI2cObj == NULL) { *pStatus = CSL_ESYS_INVPARAMS; } else { *pStatus = CSL_i2cGetBaseAddress(i2cNum, pI2cParam, &baseAddress); if (*pStatus == CSL_SOK) { pI2cObj->regs = baseAddress.regs; pI2cObj->perNum = (CSL_InstNum)i2cNum; hI2c = (CSL_I2cHandle)pI2cObj; } else { pI2cObj->regs = (CSL_I2cRegsOvly)NULL; pI2cObj->perNum = (CSL_InstNum)-1; } } return (hI2c); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2HwSetupRaw.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_ddr2HwSetupRaw.c * * @path: $(CSLPATH)\src\ddr2 * * @desc File for functional layer of CSL API @a CSL_ddr2HwSetupRaw() * - The @a CSL_ddr2HwSetupRaw() function definition & it's associated * functions * */ /* ============================================================================= * Revision History * =============== * 12-Apr-2005 RM File Created. * * 05-Oct-2005 NG Updation done according to new register layer * * 03-Feb-2006 ds Updated configuration of SDCFG register * ============================================================================= */ #include <csl_ddr2.h> /** ============================================================================ * @n@b CSL_ddr2HwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the config data structure. * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 external memory interface instance config Pointer to the config structure containing the device register values @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration structure * pointer is not properly * initialized * * Pre Condition * @n @a CSL_ddr2Init() and @a CSL_ddr2Open () must be called successfully. * before calling this function. * * Post Condition * @n The registers of the specified DDR2 EMIF instance will be * setup according to the values passed through the config structure * * @b Modifies * @n Hardware registers of the DDR2 EMIF * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; CSL_Ddr2Config config = CSL_DDR2_CONFIG_DEFAULTS; CSL_Status status; ... status = CSL_ddr2HwSetupRaw (hDdr2, &config); .. @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_ddr2HwSetupRaw, ".text:csl_section:ddr2"); CSL_Status CSL_ddr2HwSetupRaw ( CSL_Ddr2Handle hDdr2, CSL_Ddr2Config *config ) { CSL_Status status = CSL_SOK; Uint32 mask = 0; if(hDdr2 == NULL) { status = CSL_ESYS_BADHANDLE; } else if(config == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Disabling the Initialization sequence. */ /* setting the SDRAM Config Register */ /* The mask is used to leave the reserved fields at their default * values */ mask = CSL_DDR2_SDCFG_BOOT_UNLOCK_MASK | CSL_DDR2_SDCFG_DDR_DRIVE_MASK | CSL_DDR2_SDCFG_TIMUNLOCK_MASK | CSL_DDR2_SDCFG_NM_MASK | CSL_DDR2_SDCFG_CL_MASK | CSL_DDR2_SDCFG_IBANK_MASK | CSL_DDR2_SDCFG_PAGESIZE_MASK; hDdr2->regs->SDCFG = (hDdr2->regs->SDCFG & ~mask) | (config->SDCFG & mask); /* setting SDRAM Timing1 Register */ hDdr2->regs->SDTIM1 = config->SDTIM1; /* setting the SDRAM Timing2 Register */ hDdr2->regs->SDTIM2 = config->SDTIM2; /* Clearing the timing unlock bit to prevent further changes*/ CSL_FINS(hDdr2->regs->SDCFG,DDR2_SDCFG_TIMUNLOCK, CSL_DDR2_SDCFG_TIMUNLOCK_CLEAR ); /* setting the SDRAM Refresh Control Register */ /* The mask is used to leave the reserved fields at their default * values */ mask = CSL_DDR2_SDRFC_SR_MASK | CSL_DDR2_SDRFC_REFRESH_RATE_MASK; hDdr2->regs->SDRFC = (hDdr2->regs->SDRFC & ~mask) | (config->SDRFC & mask); /* setting the VBUSM Burst Priority Register */ hDdr2->regs->BPRIO = config->BPRIO; } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_tmrAux.h

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ========================================================================= */ /** =========================================================================== * @file csl_tmrAux.h * * @brief API Auxilary header file for TIMER CSL * * @Path $(CSLPATH)\inc * * @desc It gives the definitions of the status query & control functions. * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 1-Sept-2004 HMM File Created. * 29-Jul-2005 PSK updted changes acooriding to revised timer spec. the number * convention TIM12, TIM34 are changed to TIMLO and TIMHI. * ============================================================================ */ #ifndef _CSL_TMRAUX_H_ #define _CSL_TMRAUX_H_ #include <csl_tmr.h> #ifdef __cplusplus extern "C" { #endif /* Status Query Functions of General purpose timer */ /** ============================================================================ * @n@b CSL_tmrGetTimHiCount * * @b Description * @n This function gets the value of the TIMHI counter * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call countHi output parameter to get the TIMHI value @endverbatim * * Return Value None * * Pre Condition * @n Timer should be set to GPTimer OR Unchained mode OR Chained mode * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; Unit32 *countHi; ... CSL_tmrGetTimHiCount(hTmr, &countHi); ... @endverbatim * ============================================================================ */ static inline void CSL_tmrGetTimHiCount ( CSL_TmrHandle hTmr, Uint32 *countHi ) { *countHi = hTmr->regs->TIMHI; } /** =========================================================================== * @n@b CSL_tmrGetTimLoCount * * @b Description * @n This function gets the value of the TIMLO counter * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call countLo output parameter to get the TIMHI value @endverbatim * * Return Value None * * Pre Condition * @n Timer should be set to GPTimer OR Unchained mode OR Chained mode * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; Unit32 *countLo; ... CSL_tmrGetTimLoCount(hTmr, &countLo); ... @endverbatim * ============================================================================ */ static inline void CSL_tmrGetTimLoCount ( CSL_TmrHandle hTmr, Uint32 *countLo ) { *countLo = hTmr->regs->TIMLO; } /** =========================================================================== * @n@b CSL_tmrGetTstatLoStatus * * @b Description * @n This function gets the status of the TINTLO * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call @endverbatim * * Return Value CSL_TmrTstatLo - TINTLO status value * * @li CSL_TMR_TSTAT_LO_LOW - Data low * @li CSL_TMR_TSTAT_LO_HIGH - Data High * * Pre Condition * @n Timer should be set to GPTimer OR Unchained mode OR Chained mode * * Post Condition * @n TINTLO status value * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrTstatLo statusLo; ... statusLo = CSL_tmrGetTstatLoStatus(hTmr); ... @endverbatim * =========================================================================== */ static inline CSL_TmrTstat CSL_tmrGetTstatLoStatus ( CSL_TmrHandle hTmr ) { return (CSL_TmrTstat)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_TSTAT_LO); } /** =========================================================================== * @n@b CSL_tmrGetTstatHiStatus * * @b Description * @n This function gets the status of the TINTHI * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call @endverbatim * * Return Value CSL_TmrTstatHi - TINTHI status value * * @li CSL_TMR_TSTATHI_LOW - Data low * @li CSL_TMR_TSTATHI_HIGH - Data High * * Pre Condition * @n Timer should be set to GPTimer OR Unchained mode OR Chained mode * * Post Condition * @n TINTHI status value * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrTstatHi statusHi; ... statusHi = CSL_tmrGetTstatHiStatus(hTmr); ... @endverbatim * ============================================================================ */ static inline CSL_TmrTstat CSL_tmrGetTstatHiStatus ( CSL_TmrHandle hTmr ) { return (CSL_TmrTstat)CSL_FEXT(hTmr->regs->TCR, TMR_TCR_TSTAT_HI); } /** =========================================================================== * @n@b CSL_tmrGetWdflagStatus * * @b Description * @n This function gets the status of the WDFLAG * * @b Arguments * @verbatim hTmr Pointer to the object that holds reference to the instance of TIMER requested after the call @endverbatim * * Return Value CSL_TmrFlagBitStatus - WDFLAG status value * * @li CSL_TMR_WDFLAG_NOTIMEOUT - no watchdog timeout occured * @li CSL_TMR_WDFLAG_TIMEOUT - watchdog timeout occured * * Pre Condition * @n Timer should be set to WATCHDOG mode * * Post Condition * @n WDFLAG status value * * @b Modifies * @n None * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrWdflagBitStatus status; ... status = CSL_tmrGetWdflagStatus(hTmr); ... @endverbatim * =========================================================================== */ static inline CSL_TmrWdflagBitStatus CSL_tmrGetWdflagStatus ( CSL_TmrHandle hTmr ) { return (CSL_TmrWdflagBitStatus)CSL_FEXT(hTmr->regs->WDTCR, TMR_WDTCR_WDFLAG); } /** ============================================================================ * @n@b CSL_TmrLoadPrdLo * * @b Description * Loads the General purpose timer period register Low * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance loadVal Value to be loaded to the Gptimer period register Low @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to timer mode * * Post Condition * @n Gptimer period register is loaded with the given value. * * * @b Modifies * @n Gptimer period register Low * * @b Example * @verbatim CSL_TmrHandle hTmr; Uint32 *loadVal; ... CSL_TmrLoadPrdLo(hWdt, &loadVal); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrLoadPrdLo ( CSL_TmrHandle hTmr, Uint32 *loadVal ) { hTmr->regs->PRDLO = *(loadVal); } /** ============================================================================ * @n@b CSL_TmrLoadPrdHi * * @b Description * Loads the General purpose timer period register High * * @b Arguments * @verbatim hTmr Handle to the GPtimer instance loadVal Value to be loaded to the Gptimer period register High @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to timer mode * * Post Condition * @n Gptimer period register is loaded with the given value. * * * @b Modifies * @n Gptimer period register High * * @b Example * @verbatim CSL_TmrHandle hTmr; Uint32 *loadVal; ... CSL_TmrLoadPrdHi(hWdt, &loadVal); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrLoadPrdHi ( CSL_TmrHandle hTmr, Uint32 *loadVal ) { hTmr->regs->PRDHI = *(loadVal); } /** ============================================================================ * @n@b CSL_TmrLoadPrescalarHi * * @b Description * Loads the General purpose timer prescalr register High * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance loadVal Value to be loaded to the Gptimer prescalar register High @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to unchained mode * * Post Condition * @n Gptimer prescalar register is loaded with the given value. * * * @b Modifies * @n Gptimer prescalar register High * * @b Example * @verbatim CSL_TmrHandle hTmr; Uint8 *loadVal; ... CSL_TmrLoadPrescalarHi(hWdt, &loadVal); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrLoadPrescalarHi ( CSL_TmrHandle hTmr, Uint8 *loadVal ) { CSL_FINS(hTmr->regs->TGCR, TMR_TGCR_PSCHI, *((Uint8 *)loadVal)); } /** ============================================================================ * @n@b CSL_TmrStartHi * * @b Description * sets the timer counting mode and timer reset * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance countMode specifies the timer counting mode @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any GPtimer mode * * Post Condition * @n Set the GP Timer counting mode and timer High reset. * * @b Modifies * @n Gptimer TCR and TGCR register of timer High * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrEnamode countMode; ... CSL_TmrStartHi(hWdt, countMode); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrStartHi ( CSL_TmrHandle hTmr, CSL_TmrEnamode countMode ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_OFF); CSL_FINS(hTmr->regs->TCR, TMR_TCR_ENAMODE_HI, countMode); } /** ============================================================================ * @n@b CSL_TmrStartLo * * @b Description * sets the timer counting mode and timer reset * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance countMode specifies the timer counting mode @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any GPtimer mode * * Post Condition * @n Set the GP Timer counting mode and timer Low reset. * * * @b Modifies * @n Gptimer TCR and TGCR register of timer Low * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrEnamode countMode; ... CSL_TmrStartLo(hWdt, countMode); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrStartLo ( CSL_TmrHandle hTmr, CSL_TmrEnamode countMode ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); CSL_FINS(hTmr->regs->TCR, TMR_TCR_ENAMODE_LO, countMode); } /** =========================================================================== * @n@b CSL_TmrStart64 * * @b Description * sets the timer counting mode and timer reset of GP OR chained timer * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance countMode specifies the timer counting mode @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any GPtimer mode * * Post Condition * @n Set the GP OR chained timer counting mode and timer Low and High reset register. * * * @b Modifies * @n Gptimer TCR and TGCR register of timer Low AND High * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrEnamode countMode; ... CSL_TmrStart64(hWdt, countMode); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrStart64 ( CSL_TmrHandle hTmr, CSL_TmrEnamode countMode ) { Uint32 temp; CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_OFF); /* enable TIML0 and TIMHI simultaneously by making 32 bit write to TGCR */ temp = CSL_FMK(TMR_TCR_ENAMODE_LO, countMode) | CSL_FMK(TMR_TCR_ENAMODE_HI, countMode); /* do read, modify write operation for mode bits for TIMLO, TIMHI */ hTmr->regs->TCR = (hTmr->regs->TCR & ~temp) | temp; } /** =========================================================================== * @n@b CSL_TmrStopLo * * @b Description * sets the timer counting mode to stop the timer. * The timer maintains the current value * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any GPtimer mode * * Post Condition * @n Set the GP Timer counting mode to stop the counting. * * * @b Modifies * @n Gptimer TCR of timer Low * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrStopLo(hWdt); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrStopLo ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TCR, TMR_TCR_ENAMODE_LO, DISABLE); } /** =========================================================================== * @n@b CSL_TmrStopHi * * @b Description * sets the timer counting mode to stop the timer. * The timer maintains the current value * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any GPtimer mode * * Post Condition * @n Set the GP Timer counting mode to stop the counting. * * * @b Modifies * @n Gptimer TCR of timer High * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrStopHi(hWdt); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrStopHi ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TCR, TMR_TCR_ENAMODE_HI, DISABLE); } /** =========================================================================== * @n@b CSL_TmrStop64 * * @b Description * sets the timer counting mode to stop the timer. * The timer maintains the current value * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to GPtimer or Chained mode * * Post Condition * @n Set the GP Timer counting mode to stop the counting. * * * @b Modifies * @n Gptimer TCR of timer Low and High * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrStop64(hWdt); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrStop64 ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TCR, TMR_TCR_ENAMODE_LO, DISABLE); CSL_FINST(hTmr->regs->TCR, TMR_TCR_ENAMODE_HI, DISABLE); } /** =========================================================================== * @n@b CSL_TmrResetHi * * @b Description * TSTAT_HI is set to reset state * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any unchained mode * * Post Condition * @n TTSTAT_HI is set to reset state * * * @b Modifies * @n Gptimer TCR of timer High * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrResetHi(hWdt); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrResetHi ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_ON); } /** =========================================================================== * @n@b CSL_TmrResetLo * * @b Description * TSTAT_LO is set to reset state * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any unchained mode * * Post Condition * @n TSTAT_LO is set to reset state * * * @b Modifies * @n Gptimer TCR of timer Low * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrResetLo(hWdt); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrResetLo ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_ON); } /** =========================================================================== * @n@b CSL_TmrReset64 * * @b Description * TSTAT_LO and TSTAT_HI is set to reset state. * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to GPtimer or chained mode * * Post Condition * @n TSTAT_LO and TSTAT_HI is set to reset state * * * @b Modifies * @n Gptimer TCR of timer Low and High * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrReset64(hWdt); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrReset64 ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_ON); CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_ON); } /** =========================================================================== * @n@b CSL_TmrStartWdt * * @b Description * sets the timer in watchdog mode and counting mode for it * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance countMode specifies the timer counting mode @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any GPtimer mode * * Post Condition * @n Set the watchdog timer counting mode and timer Low and High reset register and WDEN bit and WDKEY. * * * @b Modifies * @n Gptimer TCR and TGCR register of timer Low AND High and WDTCR rgister * * @b Example * @verbatim CSL_TmrHandle hTmr; CSL_TmrEnamode countMode; ... CSL_TmrStartWdt(hWdt, countMode); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrStartWdt ( CSL_TmrHandle hTmr, CSL_TmrEnamode countMode ) { CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); CSL_FINST(hTmr->regs->TGCR, TMR_TGCR_TIMHIRS, RESET_OFF); CSL_FINST(hTmr->regs->WDTCR, TMR_WDTCR_WDEN, ENABLE); CSL_FINS(hTmr->regs->TCR, TMR_TCR_ENAMODE_LO, countMode); CSL_FINS(hTmr->regs->TCR, TMR_TCR_ENAMODE_HI, countMode); } /** =========================================================================== * @n@b CSL_TmrLoadtWdkey * * @b Description * sets the watchdog key * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance cmd specifies the key @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any GPtimer mode * * Post Condition * @n Loads the WDKEY in WDTCR register. * * * @b Modifies * @n WDTCR rgister * * @b Example * @verbatim CSL_TmrHandle hTmr; Uint16 cmd; ... CSL_TmrStartWdt(hTmr, cmd); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrLoadWdkey ( CSL_TmrHandle hTmr, Uint16 cmd ) { CSL_FINS(hTmr->regs->WDTCR, TMR_WDTCR_WDKEY, cmd); } /** =========================================================================== * @n@b CSL_TmrDisableWdt * * @b Description * disables the timer in watchdog mode and counting mode for it * * @b Arguments * @verbatim hTmr Handle to the Gptimer instance @endverbatim * * Return Value * None * * Pre Condition * @n Timer should be set it to any GPtimer mode * * Post Condition * @n Set the watchdog timer counting mode and timer Low and High reset register and WDEN bit and WDKEY. * * * @b Modifies * @n Gptimer TCR and TGCR register of timer Low AND High and WDTCR rgister * * @b Example * @verbatim CSL_TmrHandle hTmr; ... CSL_TmrStartWdt(hTmr); ... @endverbatim * =========================================================================== */ static inline void CSL_TmrDisableWdt ( CSL_TmrHandle hTmr ) { CSL_FINST(hTmr->regs->WDTCR, TMR_WDTCR_WDEN, DISABLE); } #ifdef __cplusplus extern "C" { #endif #endif /* CSL_TMRAUX_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cInit.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_i2cInit.c * * @brief File for functional layer of CSL API @a CSL_i2cInit() * * @path $(CSLPATH)\i2c\src * * Description * - The @a CSL_i2cInit() function definition & it's associated functions * * Modification 1 * - Modified on: 28/5/2004 * - Reason: created the sources * * @date 28th May, 2004 * @author <NAME>. */ /* ============================================================================= * Revision History * =============== * 31-aug-2004 Hs Updated the function and documentation for CSL_i2cInit. * 11-oct-2004 Hs updated code according to code review comments. * ============================================================================= */ #include <csl_i2c.h> /** ============================================================================ * @n@b CSL_i2cInit * * @b Description * @n This is the initialization function for the I2C. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. * * @b Arguments @verbatim pContext Context information for the instance. Should be NULL @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Status status; ... status = CSL_i2cInit(); ... @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_i2cInit, ".text:csl_section:i2c"); CSL_Status CSL_i2cInit ( CSL_I2cContext *pContext ) { /* Added according to review comment 1. */ pContext = pContext; /* To remove compiler warning/remarks */ return CSL_SOK; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/tcp2/tcp2_standalone_mode/src/Tcp2_standalone_mode_example.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file Tcp2_standalone_mode_example.c * * @path $(CSLPATH)\example\tcp2\tcp2_standalone_mode\src * * @desc Example file for the TCP2 CSL * ============================================================================ * @n Target Platform: EVM * ============================================================================ * The example demonstrates the usage of the TCP2 CSL API for decoding the * input data in stand alone mode. * * ============================================================================ * @n Description * This is an example for the usage of the TCP2 CSL API in the standalone * mode. * * @b Procedure * 1 - Sets up the TCP2 input configuration parameters * 2 - Configures the EDMA to transfer the input paramters, * systematics and parity data, interleaver data on successful TCPXEVT * 3 - Configures the EDMA for the hard decisions transfer on TCPREVT. * 4 - Starts the turbo coprocessor and waits for the completion of the * processing * 5 - After the state indicates the hard decisions are read, they are * displayed. *============================================================================= * * The steps to run this example are as follows: * 1 - Open the Tcp2_standalone_mode_example.pjt in the CCS studio * 2 - Build the example * 3 - Execute the .out file * */ /* ============================================================================= * Revision History * =============== * 23-May-2005 sd File Created. * 05-Aug-2005 sd Changes for EDMA CSL * 17-Dec-2005 sd Adding EDMA error registers clearing before enabling * the channel * 05-Feb-2006 sd Changes according to the spec changes * 21-Feb-2006 ds Added clearing the EDMA error registers at end of the * example * 22-Mar-2006 ds Removed "mode" bit from TCP2_BaseParams structure * ============================================================================= */ #include <csl_tcp2.h> #include <csl_tcp2Aux.h> #include <csl_edma3.h> #include <stdio.h> #include <cslr_dev.h> /* defines */ /* To load the interleaver RAM*/ #define INTERLEAVER_LOAD_FLAG TRUE /* Maximum iterations of the TCP */ #define MAX_TCP_ITERATIONS 8 /* Maximum iterations of the TCP */ #define MIN_TCP_ITERATIONS 1 /* Output paramters read flag */ #define OUT_PARAM_READ_FLAG TRUE /* prolog size */ #define PROLOG_SIZE 24 /* externs */ /* systematic and parity data to be input to TCP */ extern Uint32 sysParData []; /* Interleaver table to be input to TCP */ extern Uint32 interleaverTbl []; /* tail data for TCP configuration */ extern Int8 tailData []; /* Hard decisions expected */ extern Uint32 hdRefBuff []; /* Frame length of the TCP input data */ extern Uint32 frameLength; /* globals */ /* TCP input configuration structure */ TCP2_ConfigIc configIc; /* EDMA CSL configuration structures */ CSL_Edma3Context context; CSL_Edma3ChannelObj ChObj, ChObj1; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelHandle hChannel, hChannel1; CSL_Edma3ParamHandle hParam[4]; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3ChannelAttr chParam, chParam1; CSL_Edma3ChannelErr chErrClear; /* forward declarations */ Uint16 tcp2_configEdma ( Uint32 *hdDecisionBuffer ); /* * ============================================================================ * @func main () * * @desc * Example to show the usage of the TCP2 CSL API for standalone mode * processing * * @b Arguments * @verbatim None @endverbatim * * Return Value None * * @b Procedure * 1 - Sets up the TCP2 input configuration parameters * 2 - Configures the EDMA to transfer the input paramters, * systematics and parity data, interleaver data on successful TCPXEVT * 3 - Configures the EDMA for the hard decision transfer on TCPREVT. * 4 - Starts the turbo coprocessor and waits for the completion of the * processing * 5 - After the state indicates the hard decisions are read, they are * displayed. * * * ============================================================================ */ void main ( void ) { TCP2_BaseParams configBase; /* base params to configure TCP2 */ TCP2_Params configParams; /* holds all the input configuration parameters for TCP*/ Uint32 frameLen = frameLength; Uint32 cnt; Uint32 numHd; /* number of hard decisions */ Uint32 *hdDecisionBuffer; /* to hold the hard decisions */ /* Enable the TCP2 in power saver */ CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TCPCTL, ENABLE); while (CSL_DEV_PERSTAT0_TCPSTAT_ENABLE != CSL_FEXT (((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TCPSTAT)); /* calculate the number of hard decision 32 bit words expected */ numHd = frameLen / 32; /* for 32 bits */ /** account for the hard decision data if the frame len is not * 32 bit aligned */ if (0 != (frameLen % 32)) numHd++; /* Allocate memory for the hard decisions */ hdDecisionBuffer = (Uint32*) malloc ( sizeof (Uint32) * numHd); /* setup the base params */ configBase.frameLen = frameLen; configBase.inputSign = TCP2_INPUT_SIGN_POSITIVE; configBase.intFlag = INTERLEAVER_LOAD_FLAG; configBase.maxIter = MAX_TCP_ITERATIONS; configBase.maxStarEn = TRUE; configBase.standard = TCP2_STANDARD_3GPP; configBase.crcLen = 0; /* Disable CRC */ configBase.crcPoly = 0; /* not used */ configBase.minIter = MIN_TCP_ITERATIONS; configBase.numCrcPass = 0; /* default value */ configBase.outParmFlag = OUT_PARAM_READ_FLAG; configBase.outputOrder = TCP2_OUT_ORDER_0_31; configBase.prologRedEn = FALSE; configBase.prologSize = PROLOG_SIZE; configBase.rate = TCP2_RATE_1_3; configBase.snr = 0; /* disable SNR threshold checking */ /* assign the extrinsic scaling factors */ for (cnt = 0; cnt < 16; cnt++) configBase.extrScaling [cnt] = 32; /* setup the TCP configuration registers parmeters */ TCP2_genParams (&configBase, &configParams); /* generate the configuration register values */ TCP2_genIc (&configParams, tailData, &configIc); /* configure the Endian register */ TCP2_setInterEndian (CSL_TCP2_TCPEND_ENDIAN_INTR_32BITS); TCP2_setExtEndian (CSL_TCP2_TCPEND_ENDIAN_EXTR_32BITS); /* configure the sleep modes */ TCP2_setSlpzvdd (CSL_TCP2_TCPEND_SLPZVDD_EN_ENABLE); TCP2_setSlpzvss (CSL_TCP2_TCPEND_SLPZVSS_EN_ENABLE); /* Configure EDMA to write/read TCP data on app. events */ tcp2_configEdma (hdDecisionBuffer); /* Disable cahnnels and clear the EDMA event registers */ CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); /* Enable Channel */ CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL); /* reset and start the TCP */ TCP2_reset (); TCP2_start (); /* wait for the status to indicate hard decisions are read */ while (0xA != TCP2_statTcpState ()); /* compare the hard decisions and check if they are as expected */ for (cnt = 0; cnt < numHd; cnt++) { printf ("Hard decisions : 0x%x \n", hdDecisionBuffer [cnt]); } /* end of for */ /* free the allocated memory */ free (hdDecisionBuffer); /* Disable cahnnels and clear the EDMA event registers */ CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); /* clear the EDMA error registers */ chErrClear.missed = TRUE; chErrClear.secEvt = TRUE; CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear); printf ("Example complete \n"); } /* * ============================================================================= * @func tcp2_configEdma * @desc * Configures EDMA channels 30 and 31. * For channel 31 there are 3 param entries(0, 1 and 2) which are linked. * Link 0 transfers the TCP2 input configuration register values. * Link 1 transfer the systematics and parity data. * Link 2 transfers the interleaver data * For channel 30 there is 1 param entry (3). * Link 3 transfers the Hard decisions. * * * @eg * tcp2_configEdma(); * ============================================================================= */ Uint16 tcp2_configEdma ( Uint32 *hdDecisionBuffer ) { volatile Uint16 count; CSL_Status chStatus, chStatus1; CSL_edma3Init(&context); CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&chStatus); /* Channel Configuration for TCPXEVT event */ /* Channel Open */ chParam.regionNum = CSL_EDMA3_REGION_GLOBAL; chParam.chaNum = CSL_EDMA3_CHA_TCP2XEVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chParam, &chStatus); if ((chStatus != CSL_SOK) || (hChannel == NULL)) { printf("Error in EDMA channel open function\n"); return 0; } /* Channel Setup for PARAM entry 0 */ if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel, 0 )){ printf("Error is EDMA channel setup for channel #31\n"); return 0; } if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel, CSL_EDMA3_QUE_0)) { printf("Error is EDMA channel setup for channel #31\n"); return 0; } /* Setup EDMA to transmit the input configuration parameters */ hParam[0] = CSL_edma3GetParamHandle (hChannel, 0, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)&configIc; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1, 1); myParamSetup.dstAddr = (Uint32)CSL_TCP2_CFG_REGS; myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(0x20, 0); /* offset to the next PARAM entry */ myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(sizeof (configIc), 1); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[0], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #0\n"); return 0; } /* Setup link to transmit systematics and parity data using param 1*/ hParam[1] = CSL_edma3GetParamHandle (hChannel, 1, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)sysParData; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1, 1); myParamSetup.dstAddr = (Uint32)CSL_TCP2_X0_MEM; /* linking to the offset to the next PARAM entry */ myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(0x40, 0); /* length of the systematic and parity data to be transferred */ myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(frameLength * 4, 1); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[1], &myParamSetup)) { printf("Error in EDMA paRam setup for entry #1\n"); return 0; } /* Setup link to transmit interleaver data */ hParam[2] = CSL_edma3GetParamHandle (hChannel, 2, &chStatus); /* param entry 2 */ myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)interleaverTbl; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1, 1); myParamSetup.dstAddr = (Uint32)CSL_TCP2_I0_MEM; myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( CSL_EDMA3_LINK_NULL, 0); myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(88, 1); /* number of bytes of interleaver data */ myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[2], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #2\n"); return 0; } /* Receive Channel Open */ chParam1.regionNum = CSL_EDMA3_REGION_GLOBAL; chParam1.chaNum = CSL_EDMA3_CHA_TCP2REVT; hChannel1 = CSL_edma3ChannelOpen (&ChObj1, CSL_EDMA3, &chParam1, &chStatus1); if ((chStatus1 != CSL_SOK) | (hChannel1 == NULL)) { printf("Error in EDMA channel open function\n"); return 0; } /* Channel Setup */ if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel1, 3 /* PaRAM entry 3*/)) { printf("Error is EDMA channel setup for channel #30\n"); return 0; } if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel1, CSL_EDMA3_QUE_0)) { printf("Error is EDMA channel setup for channel #30\n"); return 0; } /* Channel Setup */ /* configure param entry 3 to read the hard decisions */ hParam[3] = CSL_edma3GetParamHandle (hChannel1, 3, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)CSL_TCP2_O0_MEM; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (8, 1); /* number of bytes of hard decision data to be read */ myParamSetup.dstAddr = (Uint32)hdDecisionBuffer; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE (1, 1); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( CSL_EDMA3_LINK_NULL, 0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE (1, 1); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[3], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #3\n"); return 0; } return 1; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example4/src/Intc_example4.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ========================================================================== */ /** =========================================================================== * @file Intc_example4.c * * @path $(CSLPATH)\example\c64xplus\intc\intc_example4\src * * @desc Example of INTC * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @n Demonstraing the usage and occurence of the dropped event. * 1. Initalizes the intc CSL required with proper ISR * 2. Opens the INTERR/DROP and timer events * 3. Enables the timer event drop * 4. Intializes and setup timer module * 5. Poll for the event to be set * 6. Closes the Intc module * * ============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Intc_example4.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================ * Revision History * =============== * 29-Jun-2004 <NAME> File Created. * * 04-Aug-2005 ds Changed to support timer CSL * 11-Nov-2005 ds Changed to add powersaver for timer * 16-Dec-2005 ds Updated documentation * ============================================================================ */ #include <stdio.h> #include <csl_intc.h> #include <csl_intcAux.h> #include <csl_tmr.h> #include <cslr_dev.h> /* Intc variables declarations */ CSL_IntcEventHandlerRecord EventHandler[30]; CSL_IntcGlobalEnableState state; CSL_IntcEventHandlerRecord EventRecord; CSL_IntcEventHandlerRecord Record[2]; /* Suficient Entries */ CSL_IntcDropStatus drop; CSL_IntcContext context; CSL_IntcHandle hIntcTimer; CSL_IntcHandle hDrop; /* Function forwards */ interrupt void eventTimerHandler(); void eventDropHandler(void *handle); void intc_example (void); /* Global variables declarations */ volatile Uint32 intrCnt = 0; volatile Uint32 passed = 0; volatile Uint32 intrDrop = 0; /* ============================================================================ * * @func main * * @desc * This is the main routine,which invokes the example * ============================================================================ */ void main(void) { Bool timer0En; printf ("Running Interrupt Example\n"); /* Unlock the control register */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the Powersaver clock for TIMER 0 */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER0CTL, ENABLE); do { timer0En = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TIMER0STAT); } while (timer0En != TRUE); printf("Powersaver clock for TIMER 0 is enabled\n"); intc_example (); return; } /* * ============================================================================= * @func intc_example * * @arg None * * @desc * This is the usage and occurence of the dropped event. * It implements following steps * 1. Initalizes the intc CSL required with proper ISR * 2. Opens the INTERR/DROP and timer events * 3. Enables the timer event drop * 4. Intializes and setup timer module * 5. Poll for the event to be set * 6. Closes the Intc module * * @return * None * * @eg * intc_example (); * ============================================================================= */ void intc_example (void) { CSL_IntcObj intcTimerObj; CSL_IntcObj intcDropObj; CSL_IntcParam vectId; volatile Uint32 dropStat; volatile Uint32 timerStat; CSL_TmrHandle hTmr; CSL_TmrObj TmrObj; CSL_Status status; CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS; CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_CONT; Uint32 LoadValue = 100; printf ("Demonstraing the usage and occurence of the dropped event\n"); /* Initialize Intc */ context.numEvtEntries = 2; context.eventhandlerRecord = Record; CSL_intcInit(&context); /* Enable NMIs */ CSL_intcGlobalNmiEnable(); /* Enable Global Interrupts */ CSL_intcGlobalEnable(&state); /* Open the INTERR/DROP EVENT Object */ vectId = CSL_INTC_VECTID_4; hDrop = CSL_intcOpen (&intcDropObj, CSL_INTC_EVENTID_INTERR, &vectId , NULL); EventRecord.handler = &eventDropHandler; EventRecord.arg = hDrop; CSL_intcPlugEventHandler(hDrop,&EventRecord); CSL_intcQueryDropStatus(&drop); /* Opening a handle for the Timer 0 Event onto CPU vector 13 */ vectId = CSL_INTC_VECTID_13; hIntcTimer = CSL_intcOpen (&intcTimerObj, CSL_INTC_EVENTID_TINTLO0, &vectId, NULL); /* Enabling timer event */ CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDROPENABLE,NULL); CSL_intcHwControl(hDrop,CSL_INTC_CMD_EVTENABLE,NULL); /* Initialize timer CSL module */ CSL_tmrInit(NULL); hTmr = CSL_tmrOpen(&TmrObj, CSL_TMR_0, NULL, &status); CSL_tmrHwSetup(hTmr, &hwSetup); /* Stop the Timer */ status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL); /* set the timer mode to unchained dual mode */ hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED; CSL_tmrHwSetup(hTmr, &hwSetup); /* Load the period register */ CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void *)&LoadValue); /* Start the timer with one shot*/ CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, (void *)&TimeCountMode); /* Poll mode, query for the event to be set */ do { CSL_intcGetHwStatus(hIntcTimer,CSL_INTC_QUERY_PENDSTATUS, \ (void*)&timerStat); if (timerStat) intrCnt++; if (intrDrop) break; } while (1); printf ("Example Passed for usage and occurence of the dropped event\n"); } /* * ============================================================================= * @func eventDropHandler * * @desc * This is the interrupt event drop handler * * @arg handle * Pointer to timer handle * * * @eg * eventDropHandler (); * ============================================================================= */ void eventDropHandler(void *handle) { intrDrop++; CSL_intcQueryDropStatus(&drop); /* Want only one drop */ CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDROPDISABLE,NULL); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cGetHwSetup.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_i2cGetHwSetup.c * * @brief File for functional layer of CSL API CSL_i2cGetHwSetup() * * @path $(CSLPATH)\i2c\src * * Description * - The CSL_i2cGetHwSetup() function definition & it's associated * functions * * Modification 1 * - Modified on: 28/5/2004 * - Reason: created the sources * * @date 28th May, 2004 * @author <NAME>. */ #include <csl_i2c.h> /** ============================================================================ * @n@b CSL_i2cGetHwSetup * * @b Description * @n This function gets the current setup of the I2C. The status is * returned through @a CSL_I2cHwSetup. The obtaining of status * is the reverse operation of @a CSL_i2cHwSetup() function. * * @b Arguments * @verbatim hI2c Handle to the I2C hwSetup Pointer to the hardware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Retrieving the hardware setup * parameters is successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before @a CSL_i2cGetHwSetup() can be called. * * Post Condition * @n The hardware setup structure is populated with the hardware setup * parameters * * @b Modifies * @n hwSetup variable * * @b Example * @verbatim CSL_I2cHandle hI2c; CSL_I2cHwSetup hwSetup; ... status = CSL_i2cGetHwSetup(hI2c, &hwSetup); ... @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_i2cGetHwSetup, ".text:csl_section:i2c") CSL_Status CSL_i2cGetHwSetup ( CSL_I2cHandle hI2c, CSL_I2cHwSetup *setup ) { CSL_Status status = CSL_SOK; CSL_I2cClkSetup clkSetup; if (hI2c == NULL) { status = CSL_ESYS_BADHANDLE; } else if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else { setup->mode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_MST); setup->dir = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_TRX); setup->addrMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_XA); setup->ownaddr = CSL_FEXT(hI2c->regs->ICOAR, I2C_ICOAR_OADDR); setup->sttbyteen = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_STB); setup->ackMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_NACKMOD); setup ->runMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_FREE); setup ->repeatMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_RM); setup->loopBackMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_DLB); setup->freeDataFormat = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_FDF); setup->resetMode = CSL_FEXT(hI2c->regs->ICMDR, I2C_ICMDR_IRS); setup->bcm = CSL_FEXT(hI2c->regs->ICEMDR, I2C_ICEMDR_BCM); setup->inten = hI2c->regs->ICIMR ; clkSetup.prescalar = CSL_FEXT(hI2c->regs->ICPSC, I2C_ICPSC_IPSC); clkSetup.clklowdiv = CSL_FEXT(hI2c->regs->ICCLKL, I2C_ICCLKL_ICCL); clkSetup.clkhighdiv= CSL_FEXT(hI2c->regs->ICCLKH, I2C_ICCLKH_ICCH); setup->clksetup->prescalar = clkSetup.prescalar; setup->clksetup->clklowdiv = clkSetup.clklowdiv; setup->clksetup->clkhighdiv = clkSetup.clkhighdiv; } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_cfg.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_cfg.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for CFG */ #ifndef _CSLR_CFG_H_ #define _CSLR_CFG_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint32 MPFAR; volatile Uint32 MPFSR; volatile Uint32 MPFCR; } CSL_CfgRegs; /**************************************************************************\ * Overlay structure typedef definition \**************************************************************************/ typedef volatile CSL_CfgRegs *CSL_CfgRegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* MPFAR */ #define CSL_CFG_MPFAR_ADDR_MASK (0xFFFFFFFFu) #define CSL_CFG_MPFAR_ADDR_SHIFT (0x00000000u) #define CSL_CFG_MPFAR_ADDR_RESETVAL (0x00000000u) #define CSL_CFG_MPFAR_RESETVAL (0x00000000u) /* MPFSR */ #define CSL_CFG_MPFSR_FID_MASK (0x0000FE00u) #define CSL_CFG_MPFSR_FID_SHIFT (0x00000009u) #define CSL_CFG_MPFSR_FID_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_LOCAL_MASK (0x00000100u) #define CSL_CFG_MPFSR_LOCAL_SHIFT (0x00000008u) #define CSL_CFG_MPFSR_LOCAL_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_SR_MASK (0x00000020u) #define CSL_CFG_MPFSR_SR_SHIFT (0x00000005u) #define CSL_CFG_MPFSR_SR_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_SW_MASK (0x00000010u) #define CSL_CFG_MPFSR_SW_SHIFT (0x00000004u) #define CSL_CFG_MPFSR_SW_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_SX_MASK (0x00000008u) #define CSL_CFG_MPFSR_SX_SHIFT (0x00000003u) #define CSL_CFG_MPFSR_SX_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_UR_MASK (0x00000004u) #define CSL_CFG_MPFSR_UR_SHIFT (0x00000002u) #define CSL_CFG_MPFSR_UR_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_UW_MASK (0x00000002u) #define CSL_CFG_MPFSR_UW_SHIFT (0x00000001u) #define CSL_CFG_MPFSR_UW_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_UX_MASK (0x00000001u) #define CSL_CFG_MPFSR_UX_SHIFT (0x00000000u) #define CSL_CFG_MPFSR_UX_RESETVAL (0x00000000u) #define CSL_CFG_MPFSR_RESETVAL (0x00000000u) /* MPFCR */ #define CSL_CFG_MPFCR_MPFCLR_MASK (0x00000001u) #define CSL_CFG_MPFCR_MPFCLR_SHIFT (0x00000000u) #define CSL_CFG_MPFCR_MPFCLR_RESETVAL (0x00000000u) /*----MPFCLR Tokens----*/ #define CSL_CFG_MPFCR_MPFCLR_CLEAR (0x00000001u) #define CSL_CFG_MPFCR_RESETVAL (0x00000000u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3Close.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_edma3Close.c * * @path $(CSLPATH)\src\edma * * @desc EDMA3 CSL Implementation on DSP side * */ /* ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= */ #include <csl_edma3.h> /** ============================================================================ * @n@b CSL_edma3Close.c * * @b Description * @n This is a module level close require to invalidate the module handle. * The module handle must not be used after this API call. * * @b Arguments * @verbatim hEdma Handle to the Edma Instance @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Edma is closed successfully. * * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * * Pre Condition * @n Functions CSL_edma3Init() and CSL_edma3Open() have to be called in that * order successfully before calling this function. * * Post Condition * @n The edma CSL APIs can not be called until the edma CSL is reopened * again using CSL_edma3Open() * * @b Modifies * @n CSL_edma3Obj structure values * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule, &hwSetup); // Open Channels, setup transfers etc // Close Module CSL_edma3Close(hModule); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3Close, ".text:csl_section:edma3"); CSL_Status CSL_edma3Close ( CSL_Edma3Handle hEdma ) { CSL_Status status = CSL_SOK; if (hEdma != NULL) { hEdma->regs = (CSL_Edma3ccRegsOvly) NULL; hEdma->instNum = (CSL_InstNum)-1; } else { status = CSL_ESYS_BADHANDLE; } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_mcbsp.h

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/inc/cslr_mcbsp.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_mcbsp.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for MCBSP * */ #ifndef _CSLR_MCBSP_H_ #define _CSLR_MCBSP_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint32 DRR; volatile Uint32 DXR; volatile Uint32 SPCR; volatile Uint32 RCR; volatile Uint32 XCR; volatile Uint32 SRGR; volatile Uint32 MCR; volatile Uint32 RCERE0; volatile Uint32 XCERE0; volatile Uint32 PCR; volatile Uint32 RCERE1; volatile Uint32 XCERE1; volatile Uint32 RCERE2; volatile Uint32 XCERE2; volatile Uint32 RCERE3; volatile Uint32 XCERE3; } CSL_McbspRegs; /**************************************************************************\ * Overlay structure typedef definition \**************************************************************************/ typedef volatile CSL_McbspRegs *CSL_McbspRegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* DRR */ #define CSL_MCBSP_DRR_DRR_MASK (0xFFFFFFFFu) #define CSL_MCBSP_DRR_DRR_SHIFT (0x00000000u) #define CSL_MCBSP_DRR_DRR_RESETVAL (0x00000000u) #define CSL_MCBSP_DRR_RESETVAL (0x00000000u) /* DXR */ #define CSL_MCBSP_DXR_DXR_MASK (0xFFFFFFFFu) #define CSL_MCBSP_DXR_DXR_SHIFT (0x00000000u) #define CSL_MCBSP_DXR_DXR_RESETVAL (0x00000000u) #define CSL_MCBSP_DXR_RESETVAL (0x00000000u) /* SPCR */ #define CSL_MCBSP_SPCR_FREE_MASK (0x02000000u) #define CSL_MCBSP_SPCR_FREE_SHIFT (0x00000019u) #define CSL_MCBSP_SPCR_FREE_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_SOFT_MASK (0x01000000u) #define CSL_MCBSP_SPCR_SOFT_SHIFT (0x00000018u) #define CSL_MCBSP_SPCR_SOFT_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_FRST_MASK (0x00800000u) #define CSL_MCBSP_SPCR_FRST_SHIFT (0x00000017u) #define CSL_MCBSP_SPCR_FRST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_GRST_MASK (0x00400000u) #define CSL_MCBSP_SPCR_GRST_SHIFT (0x00000016u) #define CSL_MCBSP_SPCR_GRST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_XINTM_MASK (0x00300000u) #define CSL_MCBSP_SPCR_XINTM_SHIFT (0x00000014u) #define CSL_MCBSP_SPCR_XINTM_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_XSYNCERR_MASK (0x00080000u) #define CSL_MCBSP_SPCR_XSYNCERR_SHIFT (0x00000013u) #define CSL_MCBSP_SPCR_XSYNCERR_RESETVAL (0x00000000u) /*----XSYNCERR Tokens----*/ #define CSL_MCBSP_SPCR_XSYNCERR_CLEAR (0x00000000u) #define CSL_MCBSP_SPCR_XEMPTY_MASK (0x00040000u) #define CSL_MCBSP_SPCR_XEMPTY_SHIFT (0x00000012u) #define CSL_MCBSP_SPCR_XEMPTY_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_XRDY_MASK (0x00020000u) #define CSL_MCBSP_SPCR_XRDY_SHIFT (0x00000011u) #define CSL_MCBSP_SPCR_XRDY_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_XRST_MASK (0x00010000u) #define CSL_MCBSP_SPCR_XRST_SHIFT (0x00000010u) #define CSL_MCBSP_SPCR_XRST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_DLB_MASK (0x00008000u) #define CSL_MCBSP_SPCR_DLB_SHIFT (0x0000000Fu) #define CSL_MCBSP_SPCR_DLB_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RJUST_MASK (0x00006000u) #define CSL_MCBSP_SPCR_RJUST_SHIFT (0x0000000Du) #define CSL_MCBSP_SPCR_RJUST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_CLKSTP_MASK (0x00001800u) #define CSL_MCBSP_SPCR_CLKSTP_SHIFT (0x0000000Bu) #define CSL_MCBSP_SPCR_CLKSTP_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_DXENA_MASK (0x00000080u) #define CSL_MCBSP_SPCR_DXENA_SHIFT (0x00000007u) #define CSL_MCBSP_SPCR_DXENA_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RINTM_MASK (0x00000030u) #define CSL_MCBSP_SPCR_RINTM_SHIFT (0x00000004u) #define CSL_MCBSP_SPCR_RINTM_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RSYNCERR_MASK (0x00000008u) #define CSL_MCBSP_SPCR_RSYNCERR_SHIFT (0x00000003u) #define CSL_MCBSP_SPCR_RSYNCERR_RESETVAL (0x00000000u) /*----RSYNCERR Tokens----*/ #define CSL_MCBSP_SPCR_RSYNCERR_CLEAR (0x00000000u) #define CSL_MCBSP_SPCR_RFULL_MASK (0x00000004u) #define CSL_MCBSP_SPCR_RFULL_SHIFT (0x00000002u) #define CSL_MCBSP_SPCR_RFULL_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RRDY_MASK (0x00000002u) #define CSL_MCBSP_SPCR_RRDY_SHIFT (0x00000001u) #define CSL_MCBSP_SPCR_RRDY_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RRST_MASK (0x00000001u) #define CSL_MCBSP_SPCR_RRST_SHIFT (0x00000000u) #define CSL_MCBSP_SPCR_RRST_RESETVAL (0x00000000u) #define CSL_MCBSP_SPCR_RESETVAL (0x00000000u) /* RCR */ #define CSL_MCBSP_RCR_RPHASE_MASK (0x80000000u) #define CSL_MCBSP_RCR_RPHASE_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCR_RPHASE_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RFRLEN2_MASK (0x7F000000u) #define CSL_MCBSP_RCR_RFRLEN2_SHIFT (0x00000018u) #define CSL_MCBSP_RCR_RFRLEN2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RWDLEN2_MASK (0x00E00000u) #define CSL_MCBSP_RCR_RWDLEN2_SHIFT (0x00000015u) #define CSL_MCBSP_RCR_RWDLEN2_RESETVAL (0x00000000u) /*----RWDLEN2 Tokens----*/ #define CSL_MCBSP_RCR_RWDLEN2_8BITS (0x00000000u) #define CSL_MCBSP_RCR_RWDLEN2_12BITS (0x00000001u) #define CSL_MCBSP_RCR_RWDLEN2_16BITS (0x00000002u) #define CSL_MCBSP_RCR_RWDLEN2_20BITS (0x00000003u) #define CSL_MCBSP_RCR_RWDLEN2_24BITS (0x00000004u) #define CSL_MCBSP_RCR_RWDLEN2_32BITS (0x00000005u) #define CSL_MCBSP_RCR_RCOMPAND_MASK (0x00180000u) #define CSL_MCBSP_RCR_RCOMPAND_SHIFT (0x00000013u) #define CSL_MCBSP_RCR_RCOMPAND_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RFIG_MASK (0x00040000u) #define CSL_MCBSP_RCR_RFIG_SHIFT (0x00000012u) #define CSL_MCBSP_RCR_RFIG_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RDATDLY_MASK (0x00030000u) #define CSL_MCBSP_RCR_RDATDLY_SHIFT (0x00000010u) #define CSL_MCBSP_RCR_RDATDLY_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RFRLEN1_MASK (0x00007F00u) #define CSL_MCBSP_RCR_RFRLEN1_SHIFT (0x00000008u) #define CSL_MCBSP_RCR_RFRLEN1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RWDLEN1_MASK (0x000000E0u) #define CSL_MCBSP_RCR_RWDLEN1_SHIFT (0x00000005u) #define CSL_MCBSP_RCR_RWDLEN1_RESETVAL (0x00000000u) /*----RWDLEN1 Tokens----*/ #define CSL_MCBSP_RCR_RWDLEN1_8BITS (0x00000000u) #define CSL_MCBSP_RCR_RWDLEN1_12BITS (0x00000001u) #define CSL_MCBSP_RCR_RWDLEN1_16BITS (0x00000002u) #define CSL_MCBSP_RCR_RWDLEN1_20BITS (0x00000003u) #define CSL_MCBSP_RCR_RWDLEN1_24BITS (0x00000004u) #define CSL_MCBSP_RCR_RWDLEN1_32BITS (0x00000005u) #define CSL_MCBSP_RCR_RWDREVRS_MASK (0x00000010u) #define CSL_MCBSP_RCR_RWDREVRS_SHIFT (0x00000004u) #define CSL_MCBSP_RCR_RWDREVRS_RESETVAL (0x00000000u) #define CSL_MCBSP_RCR_RESETVAL (0x00000000u) /* XCR */ #define CSL_MCBSP_XCR_XPHASE_MASK (0x80000000u) #define CSL_MCBSP_XCR_XPHASE_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCR_XPHASE_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XFRLEN2_MASK (0x7F000000u) #define CSL_MCBSP_XCR_XFRLEN2_SHIFT (0x00000018u) #define CSL_MCBSP_XCR_XFRLEN2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XWDLEN2_MASK (0x00E00000u) #define CSL_MCBSP_XCR_XWDLEN2_SHIFT (0x00000015u) #define CSL_MCBSP_XCR_XWDLEN2_RESETVAL (0x00000000u) /*----XWDLEN2 Tokens----*/ #define CSL_MCBSP_XCR_XWDLEN2_8BITS (0x00000000u) #define CSL_MCBSP_XCR_XWDLEN2_12BITS (0x00000001u) #define CSL_MCBSP_XCR_XWDLEN2_16BITS (0x00000002u) #define CSL_MCBSP_XCR_XWDLEN2_20BITS (0x00000003u) #define CSL_MCBSP_XCR_XWDLEN2_24BITS (0x00000004u) #define CSL_MCBSP_XCR_XWDLEN2_32BITS (0x00000005u) #define CSL_MCBSP_XCR_XCOMPAND_MASK (0x00180000u) #define CSL_MCBSP_XCR_XCOMPAND_SHIFT (0x00000013u) #define CSL_MCBSP_XCR_XCOMPAND_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XFIG_MASK (0x00040000u) #define CSL_MCBSP_XCR_XFIG_SHIFT (0x00000012u) #define CSL_MCBSP_XCR_XFIG_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XDATDLY_MASK (0x00030000u) #define CSL_MCBSP_XCR_XDATDLY_SHIFT (0x00000010u) #define CSL_MCBSP_XCR_XDATDLY_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XFRLEN1_MASK (0x00007F00u) #define CSL_MCBSP_XCR_XFRLEN1_SHIFT (0x00000008u) #define CSL_MCBSP_XCR_XFRLEN1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_XWDLEN1_MASK (0x000000E0u) #define CSL_MCBSP_XCR_XWDLEN1_SHIFT (0x00000005u) #define CSL_MCBSP_XCR_XWDLEN1_RESETVAL (0x00000000u) /*----XWDLEN1 Tokens----*/ #define CSL_MCBSP_XCR_XWDLEN1_8BITS (0x00000000u) #define CSL_MCBSP_XCR_XWDLEN1_12BITS (0x00000001u) #define CSL_MCBSP_XCR_XWDLEN1_16BITS (0x00000002u) #define CSL_MCBSP_XCR_XWDLEN1_20BITS (0x00000003u) #define CSL_MCBSP_XCR_XWDLEN1_24BITS (0x00000004u) #define CSL_MCBSP_XCR_XWDLEN1_32BITS (0x00000005u) #define CSL_MCBSP_XCR_XWDREVRS_MASK (0x00000010u) #define CSL_MCBSP_XCR_XWDREVRS_SHIFT (0x00000004u) #define CSL_MCBSP_XCR_XWDREVRS_RESETVAL (0x00000000u) #define CSL_MCBSP_XCR_RESETVAL (0x00000000u) /* SRGR */ #define CSL_MCBSP_SRGR_GSYNC_MASK (0x80000000u) #define CSL_MCBSP_SRGR_GSYNC_SHIFT (0x0000001Fu) #define CSL_MCBSP_SRGR_GSYNC_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_CLKSP_MASK (0x40000000u) #define CSL_MCBSP_SRGR_CLKSP_SHIFT (0x0000001Eu) #define CSL_MCBSP_SRGR_CLKSP_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_CLKSM_MASK (0x20000000u) #define CSL_MCBSP_SRGR_CLKSM_SHIFT (0x0000001Du) #define CSL_MCBSP_SRGR_CLKSM_RESETVAL (0x00000001u) #define CSL_MCBSP_SRGR_FSGM_MASK (0x10000000u) #define CSL_MCBSP_SRGR_FSGM_SHIFT (0x0000001Cu) #define CSL_MCBSP_SRGR_FSGM_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_FPER_MASK (0x0FFF0000u) #define CSL_MCBSP_SRGR_FPER_SHIFT (0x00000010u) #define CSL_MCBSP_SRGR_FPER_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_FWID_MASK (0x0000FF00u) #define CSL_MCBSP_SRGR_FWID_SHIFT (0x00000008u) #define CSL_MCBSP_SRGR_FWID_RESETVAL (0x00000000u) #define CSL_MCBSP_SRGR_CLKGDV_MASK (0x000000FFu) #define CSL_MCBSP_SRGR_CLKGDV_SHIFT (0x00000000u) #define CSL_MCBSP_SRGR_CLKGDV_RESETVAL (0x00000001u) #define CSL_MCBSP_SRGR_RESETVAL (0x20000001u) /* MCR */ #define CSL_MCBSP_MCR_XMCME_MASK (0x02000000u) #define CSL_MCBSP_MCR_XMCME_SHIFT (0x00000019u) #define CSL_MCBSP_MCR_XMCME_RESETVAL (0x00000000u) /*----XMCME Tokens----*/ #define CSL_MCBSP_MCR_XMCME_PARTITIONS2 (0x00000000u) #define CSL_MCBSP_MCR_XPBBLK_MASK (0x01800000u) #define CSL_MCBSP_MCR_XPBBLK_SHIFT (0x00000017u) #define CSL_MCBSP_MCR_XPBBLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_XPABLK_MASK (0x00600000u) #define CSL_MCBSP_MCR_XPABLK_SHIFT (0x00000015u) #define CSL_MCBSP_MCR_XPABLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_XCBLK_MASK (0x001C0000u) #define CSL_MCBSP_MCR_XCBLK_SHIFT (0x00000012u) #define CSL_MCBSP_MCR_XCBLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_XMCM_MASK (0x00030000u) #define CSL_MCBSP_MCR_XMCM_SHIFT (0x00000010u) #define CSL_MCBSP_MCR_XMCM_RESETVAL (0x00000000u) /*----XMCM Tokens----*/ #define CSL_MCBSP_MCR_XMCM_ENABLE (0x00000000u) #define CSL_MCBSP_MCR_XMCM_DISABLE (0x00000001u) #define CSL_MCBSP_MCR_XMCM_ENABLE_MASK (0x00000002u) #define CSL_MCBSP_MCR_XMCM_SYMMETRIC (0x00000003u) #define CSL_MCBSP_MCR_RMCME_MASK (0x00000200u) #define CSL_MCBSP_MCR_RMCME_SHIFT (0x00000009u) #define CSL_MCBSP_MCR_RMCME_RESETVAL (0x00000000u) /*----RMCME Tokens----*/ #define CSL_MCBSP_MCR_RMCME_PARTITIONS2 (0x00000000u) #define CSL_MCBSP_MCR_RMCME_PARTITIONS8 (0x00000001u) #define CSL_MCBSP_MCR_RPBBLK_MASK (0x00000180u) #define CSL_MCBSP_MCR_RPBBLK_SHIFT (0x00000007u) #define CSL_MCBSP_MCR_RPBBLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_RPABLK_MASK (0x00000060u) #define CSL_MCBSP_MCR_RPABLK_SHIFT (0x00000005u) #define CSL_MCBSP_MCR_RPABLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_RCBLK_MASK (0x0000001Cu) #define CSL_MCBSP_MCR_RCBLK_SHIFT (0x00000002u) #define CSL_MCBSP_MCR_RCBLK_RESETVAL (0x00000000u) #define CSL_MCBSP_MCR_RMCM_MASK (0x00000001u) #define CSL_MCBSP_MCR_RMCM_SHIFT (0x00000000u) #define CSL_MCBSP_MCR_RMCM_RESETVAL (0x00000000u) /*----RMCM Tokens----*/ #define CSL_MCBSP_MCR_RMCM_ENABLE (0x00000000u) #define CSL_MCBSP_MCR_RMCM_DISABLE (0x00000001u) #define CSL_MCBSP_MCR_RESETVAL (0x00000000u) /* RCERE0 */ #define CSL_MCBSP_RCERE0_RCE31_MASK (0x80000000u) #define CSL_MCBSP_RCERE0_RCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCERE0_RCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE30_MASK (0x40000000u) #define CSL_MCBSP_RCERE0_RCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_RCERE0_RCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE29_MASK (0x20000000u) #define CSL_MCBSP_RCERE0_RCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_RCERE0_RCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE28_MASK (0x10000000u) #define CSL_MCBSP_RCERE0_RCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_RCERE0_RCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE27_MASK (0x08000000u) #define CSL_MCBSP_RCERE0_RCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_RCERE0_RCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE26_MASK (0x04000000u) #define CSL_MCBSP_RCERE0_RCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_RCERE0_RCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE25_MASK (0x02000000u) #define CSL_MCBSP_RCERE0_RCE25_SHIFT (0x00000019u) #define CSL_MCBSP_RCERE0_RCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE24_MASK (0x01000000u) #define CSL_MCBSP_RCERE0_RCE24_SHIFT (0x00000018u) #define CSL_MCBSP_RCERE0_RCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE23_MASK (0x00800000u) #define CSL_MCBSP_RCERE0_RCE23_SHIFT (0x00000017u) #define CSL_MCBSP_RCERE0_RCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE22_MASK (0x00400000u) #define CSL_MCBSP_RCERE0_RCE22_SHIFT (0x00000016u) #define CSL_MCBSP_RCERE0_RCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE21_MASK (0x00200000u) #define CSL_MCBSP_RCERE0_RCE21_SHIFT (0x00000015u) #define CSL_MCBSP_RCERE0_RCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE20_MASK (0x00100000u) #define CSL_MCBSP_RCERE0_RCE20_SHIFT (0x00000014u) #define CSL_MCBSP_RCERE0_RCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE19_MASK (0x00080000u) #define CSL_MCBSP_RCERE0_RCE19_SHIFT (0x00000013u) #define CSL_MCBSP_RCERE0_RCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE18_MASK (0x00040000u) #define CSL_MCBSP_RCERE0_RCE18_SHIFT (0x00000012u) #define CSL_MCBSP_RCERE0_RCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE17_MASK (0x00020000u) #define CSL_MCBSP_RCERE0_RCE17_SHIFT (0x00000011u) #define CSL_MCBSP_RCERE0_RCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE16_MASK (0x00010000u) #define CSL_MCBSP_RCERE0_RCE16_SHIFT (0x00000010u) #define CSL_MCBSP_RCERE0_RCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE15_MASK (0x00008000u) #define CSL_MCBSP_RCERE0_RCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_RCERE0_RCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE14_MASK (0x00004000u) #define CSL_MCBSP_RCERE0_RCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_RCERE0_RCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE13_MASK (0x00002000u) #define CSL_MCBSP_RCERE0_RCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_RCERE0_RCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE12_MASK (0x00001000u) #define CSL_MCBSP_RCERE0_RCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_RCERE0_RCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE11_MASK (0x00000800u) #define CSL_MCBSP_RCERE0_RCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_RCERE0_RCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE10_MASK (0x00000400u) #define CSL_MCBSP_RCERE0_RCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_RCERE0_RCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE9_MASK (0x00000200u) #define CSL_MCBSP_RCERE0_RCE9_SHIFT (0x00000009u) #define CSL_MCBSP_RCERE0_RCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE8_MASK (0x00000100u) #define CSL_MCBSP_RCERE0_RCE8_SHIFT (0x00000008u) #define CSL_MCBSP_RCERE0_RCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE7_MASK (0x00000080u) #define CSL_MCBSP_RCERE0_RCE7_SHIFT (0x00000007u) #define CSL_MCBSP_RCERE0_RCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE6_MASK (0x00000040u) #define CSL_MCBSP_RCERE0_RCE6_SHIFT (0x00000006u) #define CSL_MCBSP_RCERE0_RCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE5_MASK (0x00000020u) #define CSL_MCBSP_RCERE0_RCE5_SHIFT (0x00000005u) #define CSL_MCBSP_RCERE0_RCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE4_MASK (0x00000010u) #define CSL_MCBSP_RCERE0_RCE4_SHIFT (0x00000004u) #define CSL_MCBSP_RCERE0_RCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE3_MASK (0x00000008u) #define CSL_MCBSP_RCERE0_RCE3_SHIFT (0x00000003u) #define CSL_MCBSP_RCERE0_RCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE2_MASK (0x00000004u) #define CSL_MCBSP_RCERE0_RCE2_SHIFT (0x00000002u) #define CSL_MCBSP_RCERE0_RCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE1_MASK (0x00000002u) #define CSL_MCBSP_RCERE0_RCE1_SHIFT (0x00000001u) #define CSL_MCBSP_RCERE0_RCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RCE0_MASK (0x00000001u) #define CSL_MCBSP_RCERE0_RCE0_SHIFT (0x00000000u) #define CSL_MCBSP_RCERE0_RCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE0_RESETVAL (0x00000000u) /* XCERE0 */ #define CSL_MCBSP_XCERE0_XCE31_MASK (0x80000000u) #define CSL_MCBSP_XCERE0_XCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCERE0_XCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE30_MASK (0x40000000u) #define CSL_MCBSP_XCERE0_XCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_XCERE0_XCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE29_MASK (0x20000000u) #define CSL_MCBSP_XCERE0_XCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_XCERE0_XCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE28_MASK (0x10000000u) #define CSL_MCBSP_XCERE0_XCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_XCERE0_XCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE27_MASK (0x08000000u) #define CSL_MCBSP_XCERE0_XCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_XCERE0_XCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE26_MASK (0x04000000u) #define CSL_MCBSP_XCERE0_XCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_XCERE0_XCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE25_MASK (0x02000000u) #define CSL_MCBSP_XCERE0_XCE25_SHIFT (0x00000019u) #define CSL_MCBSP_XCERE0_XCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE24_MASK (0x01000000u) #define CSL_MCBSP_XCERE0_XCE24_SHIFT (0x00000018u) #define CSL_MCBSP_XCERE0_XCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE23_MASK (0x00800000u) #define CSL_MCBSP_XCERE0_XCE23_SHIFT (0x00000017u) #define CSL_MCBSP_XCERE0_XCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE22_MASK (0x00400000u) #define CSL_MCBSP_XCERE0_XCE22_SHIFT (0x00000016u) #define CSL_MCBSP_XCERE0_XCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE21_MASK (0x00200000u) #define CSL_MCBSP_XCERE0_XCE21_SHIFT (0x00000015u) #define CSL_MCBSP_XCERE0_XCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE20_MASK (0x00100000u) #define CSL_MCBSP_XCERE0_XCE20_SHIFT (0x00000014u) #define CSL_MCBSP_XCERE0_XCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE19_MASK (0x00080000u) #define CSL_MCBSP_XCERE0_XCE19_SHIFT (0x00000013u) #define CSL_MCBSP_XCERE0_XCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE18_MASK (0x00040000u) #define CSL_MCBSP_XCERE0_XCE18_SHIFT (0x00000012u) #define CSL_MCBSP_XCERE0_XCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE17_MASK (0x00020000u) #define CSL_MCBSP_XCERE0_XCE17_SHIFT (0x00000011u) #define CSL_MCBSP_XCERE0_XCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE16_MASK (0x00010000u) #define CSL_MCBSP_XCERE0_XCE16_SHIFT (0x00000010u) #define CSL_MCBSP_XCERE0_XCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE15_MASK (0x00008000u) #define CSL_MCBSP_XCERE0_XCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_XCERE0_XCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE14_MASK (0x00004000u) #define CSL_MCBSP_XCERE0_XCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_XCERE0_XCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE13_MASK (0x00002000u) #define CSL_MCBSP_XCERE0_XCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_XCERE0_XCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE12_MASK (0x00001000u) #define CSL_MCBSP_XCERE0_XCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_XCERE0_XCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE11_MASK (0x00000800u) #define CSL_MCBSP_XCERE0_XCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_XCERE0_XCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE10_MASK (0x00000400u) #define CSL_MCBSP_XCERE0_XCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_XCERE0_XCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE9_MASK (0x00000200u) #define CSL_MCBSP_XCERE0_XCE9_SHIFT (0x00000009u) #define CSL_MCBSP_XCERE0_XCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE8_MASK (0x00000100u) #define CSL_MCBSP_XCERE0_XCE8_SHIFT (0x00000008u) #define CSL_MCBSP_XCERE0_XCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE7_MASK (0x00000080u) #define CSL_MCBSP_XCERE0_XCE7_SHIFT (0x00000007u) #define CSL_MCBSP_XCERE0_XCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE6_MASK (0x00000040u) #define CSL_MCBSP_XCERE0_XCE6_SHIFT (0x00000006u) #define CSL_MCBSP_XCERE0_XCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE5_MASK (0x00000020u) #define CSL_MCBSP_XCERE0_XCE5_SHIFT (0x00000005u) #define CSL_MCBSP_XCERE0_XCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE4_MASK (0x00000010u) #define CSL_MCBSP_XCERE0_XCE4_SHIFT (0x00000004u) #define CSL_MCBSP_XCERE0_XCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE3_MASK (0x00000008u) #define CSL_MCBSP_XCERE0_XCE3_SHIFT (0x00000003u) #define CSL_MCBSP_XCERE0_XCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE2_MASK (0x00000004u) #define CSL_MCBSP_XCERE0_XCE2_SHIFT (0x00000002u) #define CSL_MCBSP_XCERE0_XCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE1_MASK (0x00000002u) #define CSL_MCBSP_XCERE0_XCE1_SHIFT (0x00000001u) #define CSL_MCBSP_XCERE0_XCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_XCE0_MASK (0x00000001u) #define CSL_MCBSP_XCERE0_XCE0_SHIFT (0x00000000u) #define CSL_MCBSP_XCERE0_XCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE0_RESETVAL (0x00000000u) /* PCR */ #define CSL_MCBSP_PCR_XIOEN_MASK (0x00002000u) #define CSL_MCBSP_PCR_XIOEN_SHIFT (0x0000000Du) #define CSL_MCBSP_PCR_XIOEN_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_RIOEN_MASK (0x00001000u) #define CSL_MCBSP_PCR_RIOEN_SHIFT (0x0000000Cu) #define CSL_MCBSP_PCR_RIOEN_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_FSXM_MASK (0x00000800u) #define CSL_MCBSP_PCR_FSXM_SHIFT (0x0000000Bu) #define CSL_MCBSP_PCR_FSXM_RESETVAL (0x00000000u) /*----FSXM Tokens----*/ #define CSL_MCBSP_PCR_FSXM_INPUT (0x00000000u) #define CSL_MCBSP_PCR_FSXM_OUTPUT (0x00000001u) #define CSL_MCBSP_PCR_FSRM_MASK (0x00000400u) #define CSL_MCBSP_PCR_FSRM_SHIFT (0x0000000Au) #define CSL_MCBSP_PCR_FSRM_RESETVAL (0x00000000u) /*----FSRM Tokens----*/ #define CSL_MCBSP_PCR_FSRM_INPUT (0x00000000u) #define CSL_MCBSP_PCR_FSRM_OUTPUT (0x00000001u) #define CSL_MCBSP_PCR_CLKXM_MASK (0x00000200u) #define CSL_MCBSP_PCR_CLKXM_SHIFT (0x00000009u) #define CSL_MCBSP_PCR_CLKXM_RESETVAL (0x00000000u) /*----CLKXM Tokens----*/ #define CSL_MCBSP_PCR_CLKXM_INPUT (0x00000000u) #define CSL_MCBSP_PCR_CLKXM_OUTPUT (0x00000001u) #define CSL_MCBSP_PCR_CLKRM_MASK (0x00000100u) #define CSL_MCBSP_PCR_CLKRM_SHIFT (0x00000008u) #define CSL_MCBSP_PCR_CLKRM_RESETVAL (0x00000000u) /*----CLKRM Tokens----*/ #define CSL_MCBSP_PCR_CLKRM_INPUT (0x00000000u) #define CSL_MCBSP_PCR_CLKRM_OUTPUT (0x00000001u) #define CSL_MCBSP_PCR_CLKSSTAT_MASK (0x00000040u) #define CSL_MCBSP_PCR_CLKSSTAT_SHIFT (0x00000006u) #define CSL_MCBSP_PCR_CLKSSTAT_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_DXSTAT_MASK (0x00000020u) #define CSL_MCBSP_PCR_DXSTAT_SHIFT (0x00000005u) #define CSL_MCBSP_PCR_DXSTAT_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_DRSTAT_MASK (0x00000010u) #define CSL_MCBSP_PCR_DRSTAT_SHIFT (0x00000004u) #define CSL_MCBSP_PCR_DRSTAT_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_FSXP_MASK (0x00000008u) #define CSL_MCBSP_PCR_FSXP_SHIFT (0x00000003u) #define CSL_MCBSP_PCR_FSXP_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_FSRP_MASK (0x00000004u) #define CSL_MCBSP_PCR_FSRP_SHIFT (0x00000002u) #define CSL_MCBSP_PCR_FSRP_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_CLKXP_MASK (0x00000002u) #define CSL_MCBSP_PCR_CLKXP_SHIFT (0x00000001u) #define CSL_MCBSP_PCR_CLKXP_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_CLKRP_MASK (0x00000001u) #define CSL_MCBSP_PCR_CLKRP_SHIFT (0x00000000u) #define CSL_MCBSP_PCR_CLKRP_RESETVAL (0x00000000u) #define CSL_MCBSP_PCR_RESETVAL (0x00000000u) /* RCERE1 */ #define CSL_MCBSP_RCERE1_RCE31_MASK (0x80000000u) #define CSL_MCBSP_RCERE1_RCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCERE1_RCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE30_MASK (0x40000000u) #define CSL_MCBSP_RCERE1_RCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_RCERE1_RCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE29_MASK (0x20000000u) #define CSL_MCBSP_RCERE1_RCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_RCERE1_RCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE28_MASK (0x10000000u) #define CSL_MCBSP_RCERE1_RCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_RCERE1_RCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE27_MASK (0x08000000u) #define CSL_MCBSP_RCERE1_RCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_RCERE1_RCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE26_MASK (0x04000000u) #define CSL_MCBSP_RCERE1_RCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_RCERE1_RCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE25_MASK (0x02000000u) #define CSL_MCBSP_RCERE1_RCE25_SHIFT (0x00000019u) #define CSL_MCBSP_RCERE1_RCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE24_MASK (0x01000000u) #define CSL_MCBSP_RCERE1_RCE24_SHIFT (0x00000018u) #define CSL_MCBSP_RCERE1_RCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE23_MASK (0x00800000u) #define CSL_MCBSP_RCERE1_RCE23_SHIFT (0x00000017u) #define CSL_MCBSP_RCERE1_RCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE22_MASK (0x00400000u) #define CSL_MCBSP_RCERE1_RCE22_SHIFT (0x00000016u) #define CSL_MCBSP_RCERE1_RCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE21_MASK (0x00200000u) #define CSL_MCBSP_RCERE1_RCE21_SHIFT (0x00000015u) #define CSL_MCBSP_RCERE1_RCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE20_MASK (0x00100000u) #define CSL_MCBSP_RCERE1_RCE20_SHIFT (0x00000014u) #define CSL_MCBSP_RCERE1_RCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE19_MASK (0x00080000u) #define CSL_MCBSP_RCERE1_RCE19_SHIFT (0x00000013u) #define CSL_MCBSP_RCERE1_RCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE18_MASK (0x00040000u) #define CSL_MCBSP_RCERE1_RCE18_SHIFT (0x00000012u) #define CSL_MCBSP_RCERE1_RCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE17_MASK (0x00020000u) #define CSL_MCBSP_RCERE1_RCE17_SHIFT (0x00000011u) #define CSL_MCBSP_RCERE1_RCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE16_MASK (0x00010000u) #define CSL_MCBSP_RCERE1_RCE16_SHIFT (0x00000010u) #define CSL_MCBSP_RCERE1_RCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE15_MASK (0x00008000u) #define CSL_MCBSP_RCERE1_RCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_RCERE1_RCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE14_MASK (0x00004000u) #define CSL_MCBSP_RCERE1_RCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_RCERE1_RCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE13_MASK (0x00002000u) #define CSL_MCBSP_RCERE1_RCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_RCERE1_RCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE12_MASK (0x00001000u) #define CSL_MCBSP_RCERE1_RCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_RCERE1_RCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE11_MASK (0x00000800u) #define CSL_MCBSP_RCERE1_RCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_RCERE1_RCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE10_MASK (0x00000400u) #define CSL_MCBSP_RCERE1_RCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_RCERE1_RCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE9_MASK (0x00000200u) #define CSL_MCBSP_RCERE1_RCE9_SHIFT (0x00000009u) #define CSL_MCBSP_RCERE1_RCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE8_MASK (0x00000100u) #define CSL_MCBSP_RCERE1_RCE8_SHIFT (0x00000008u) #define CSL_MCBSP_RCERE1_RCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE7_MASK (0x00000080u) #define CSL_MCBSP_RCERE1_RCE7_SHIFT (0x00000007u) #define CSL_MCBSP_RCERE1_RCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE6_MASK (0x00000040u) #define CSL_MCBSP_RCERE1_RCE6_SHIFT (0x00000006u) #define CSL_MCBSP_RCERE1_RCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE5_MASK (0x00000020u) #define CSL_MCBSP_RCERE1_RCE5_SHIFT (0x00000005u) #define CSL_MCBSP_RCERE1_RCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE4_MASK (0x00000010u) #define CSL_MCBSP_RCERE1_RCE4_SHIFT (0x00000004u) #define CSL_MCBSP_RCERE1_RCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE3_MASK (0x00000008u) #define CSL_MCBSP_RCERE1_RCE3_SHIFT (0x00000003u) #define CSL_MCBSP_RCERE1_RCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE2_MASK (0x00000004u) #define CSL_MCBSP_RCERE1_RCE2_SHIFT (0x00000002u) #define CSL_MCBSP_RCERE1_RCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE1_MASK (0x00000002u) #define CSL_MCBSP_RCERE1_RCE1_SHIFT (0x00000001u) #define CSL_MCBSP_RCERE1_RCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RCE0_MASK (0x00000001u) #define CSL_MCBSP_RCERE1_RCE0_SHIFT (0x00000000u) #define CSL_MCBSP_RCERE1_RCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE1_RESETVAL (0x00000000u) /* XCERE1 */ #define CSL_MCBSP_XCERE1_XCE31_MASK (0x80000000u) #define CSL_MCBSP_XCERE1_XCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCERE1_XCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE30_MASK (0x40000000u) #define CSL_MCBSP_XCERE1_XCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_XCERE1_XCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE29_MASK (0x20000000u) #define CSL_MCBSP_XCERE1_XCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_XCERE1_XCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE28_MASK (0x10000000u) #define CSL_MCBSP_XCERE1_XCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_XCERE1_XCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE27_MASK (0x08000000u) #define CSL_MCBSP_XCERE1_XCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_XCERE1_XCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE26_MASK (0x04000000u) #define CSL_MCBSP_XCERE1_XCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_XCERE1_XCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE25_MASK (0x02000000u) #define CSL_MCBSP_XCERE1_XCE25_SHIFT (0x00000019u) #define CSL_MCBSP_XCERE1_XCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE24_MASK (0x01000000u) #define CSL_MCBSP_XCERE1_XCE24_SHIFT (0x00000018u) #define CSL_MCBSP_XCERE1_XCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE23_MASK (0x00800000u) #define CSL_MCBSP_XCERE1_XCE23_SHIFT (0x00000017u) #define CSL_MCBSP_XCERE1_XCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE22_MASK (0x00400000u) #define CSL_MCBSP_XCERE1_XCE22_SHIFT (0x00000016u) #define CSL_MCBSP_XCERE1_XCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE21_MASK (0x00200000u) #define CSL_MCBSP_XCERE1_XCE21_SHIFT (0x00000015u) #define CSL_MCBSP_XCERE1_XCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE20_MASK (0x00100000u) #define CSL_MCBSP_XCERE1_XCE20_SHIFT (0x00000014u) #define CSL_MCBSP_XCERE1_XCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE19_MASK (0x00080000u) #define CSL_MCBSP_XCERE1_XCE19_SHIFT (0x00000013u) #define CSL_MCBSP_XCERE1_XCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE18_MASK (0x00040000u) #define CSL_MCBSP_XCERE1_XCE18_SHIFT (0x00000012u) #define CSL_MCBSP_XCERE1_XCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE17_MASK (0x00020000u) #define CSL_MCBSP_XCERE1_XCE17_SHIFT (0x00000011u) #define CSL_MCBSP_XCERE1_XCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE16_MASK (0x00010000u) #define CSL_MCBSP_XCERE1_XCE16_SHIFT (0x00000010u) #define CSL_MCBSP_XCERE1_XCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE15_MASK (0x00008000u) #define CSL_MCBSP_XCERE1_XCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_XCERE1_XCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE14_MASK (0x00004000u) #define CSL_MCBSP_XCERE1_XCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_XCERE1_XCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE13_MASK (0x00002000u) #define CSL_MCBSP_XCERE1_XCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_XCERE1_XCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE12_MASK (0x00001000u) #define CSL_MCBSP_XCERE1_XCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_XCERE1_XCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE11_MASK (0x00000800u) #define CSL_MCBSP_XCERE1_XCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_XCERE1_XCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE10_MASK (0x00000400u) #define CSL_MCBSP_XCERE1_XCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_XCERE1_XCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE9_MASK (0x00000200u) #define CSL_MCBSP_XCERE1_XCE9_SHIFT (0x00000009u) #define CSL_MCBSP_XCERE1_XCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE8_MASK (0x00000100u) #define CSL_MCBSP_XCERE1_XCE8_SHIFT (0x00000008u) #define CSL_MCBSP_XCERE1_XCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE7_MASK (0x00000080u) #define CSL_MCBSP_XCERE1_XCE7_SHIFT (0x00000007u) #define CSL_MCBSP_XCERE1_XCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE6_MASK (0x00000040u) #define CSL_MCBSP_XCERE1_XCE6_SHIFT (0x00000006u) #define CSL_MCBSP_XCERE1_XCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE5_MASK (0x00000020u) #define CSL_MCBSP_XCERE1_XCE5_SHIFT (0x00000005u) #define CSL_MCBSP_XCERE1_XCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE4_MASK (0x00000010u) #define CSL_MCBSP_XCERE1_XCE4_SHIFT (0x00000004u) #define CSL_MCBSP_XCERE1_XCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE3_MASK (0x00000008u) #define CSL_MCBSP_XCERE1_XCE3_SHIFT (0x00000003u) #define CSL_MCBSP_XCERE1_XCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE2_MASK (0x00000004u) #define CSL_MCBSP_XCERE1_XCE2_SHIFT (0x00000002u) #define CSL_MCBSP_XCERE1_XCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE1_MASK (0x00000002u) #define CSL_MCBSP_XCERE1_XCE1_SHIFT (0x00000001u) #define CSL_MCBSP_XCERE1_XCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_XCE0_MASK (0x00000001u) #define CSL_MCBSP_XCERE1_XCE0_SHIFT (0x00000000u) #define CSL_MCBSP_XCERE1_XCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE1_RESETVAL (0x00000000u) /* RCERE2 */ #define CSL_MCBSP_RCERE2_RCE31_MASK (0x80000000u) #define CSL_MCBSP_RCERE2_RCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCERE2_RCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE30_MASK (0x40000000u) #define CSL_MCBSP_RCERE2_RCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_RCERE2_RCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE29_MASK (0x20000000u) #define CSL_MCBSP_RCERE2_RCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_RCERE2_RCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE28_MASK (0x10000000u) #define CSL_MCBSP_RCERE2_RCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_RCERE2_RCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE27_MASK (0x08000000u) #define CSL_MCBSP_RCERE2_RCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_RCERE2_RCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE26_MASK (0x04000000u) #define CSL_MCBSP_RCERE2_RCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_RCERE2_RCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE25_MASK (0x02000000u) #define CSL_MCBSP_RCERE2_RCE25_SHIFT (0x00000019u) #define CSL_MCBSP_RCERE2_RCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE24_MASK (0x01000000u) #define CSL_MCBSP_RCERE2_RCE24_SHIFT (0x00000018u) #define CSL_MCBSP_RCERE2_RCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE23_MASK (0x00800000u) #define CSL_MCBSP_RCERE2_RCE23_SHIFT (0x00000017u) #define CSL_MCBSP_RCERE2_RCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE22_MASK (0x00400000u) #define CSL_MCBSP_RCERE2_RCE22_SHIFT (0x00000016u) #define CSL_MCBSP_RCERE2_RCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE21_MASK (0x00200000u) #define CSL_MCBSP_RCERE2_RCE21_SHIFT (0x00000015u) #define CSL_MCBSP_RCERE2_RCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE20_MASK (0x00100000u) #define CSL_MCBSP_RCERE2_RCE20_SHIFT (0x00000014u) #define CSL_MCBSP_RCERE2_RCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE19_MASK (0x00080000u) #define CSL_MCBSP_RCERE2_RCE19_SHIFT (0x00000013u) #define CSL_MCBSP_RCERE2_RCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE18_MASK (0x00040000u) #define CSL_MCBSP_RCERE2_RCE18_SHIFT (0x00000012u) #define CSL_MCBSP_RCERE2_RCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE17_MASK (0x00020000u) #define CSL_MCBSP_RCERE2_RCE17_SHIFT (0x00000011u) #define CSL_MCBSP_RCERE2_RCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE16_MASK (0x00010000u) #define CSL_MCBSP_RCERE2_RCE16_SHIFT (0x00000010u) #define CSL_MCBSP_RCERE2_RCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE15_MASK (0x00008000u) #define CSL_MCBSP_RCERE2_RCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_RCERE2_RCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE14_MASK (0x00004000u) #define CSL_MCBSP_RCERE2_RCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_RCERE2_RCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE13_MASK (0x00002000u) #define CSL_MCBSP_RCERE2_RCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_RCERE2_RCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE12_MASK (0x00001000u) #define CSL_MCBSP_RCERE2_RCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_RCERE2_RCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE11_MASK (0x00000800u) #define CSL_MCBSP_RCERE2_RCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_RCERE2_RCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE10_MASK (0x00000400u) #define CSL_MCBSP_RCERE2_RCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_RCERE2_RCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE9_MASK (0x00000200u) #define CSL_MCBSP_RCERE2_RCE9_SHIFT (0x00000009u) #define CSL_MCBSP_RCERE2_RCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE8_MASK (0x00000100u) #define CSL_MCBSP_RCERE2_RCE8_SHIFT (0x00000008u) #define CSL_MCBSP_RCERE2_RCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE7_MASK (0x00000080u) #define CSL_MCBSP_RCERE2_RCE7_SHIFT (0x00000007u) #define CSL_MCBSP_RCERE2_RCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE6_MASK (0x00000040u) #define CSL_MCBSP_RCERE2_RCE6_SHIFT (0x00000006u) #define CSL_MCBSP_RCERE2_RCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE5_MASK (0x00000020u) #define CSL_MCBSP_RCERE2_RCE5_SHIFT (0x00000005u) #define CSL_MCBSP_RCERE2_RCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE4_MASK (0x00000010u) #define CSL_MCBSP_RCERE2_RCE4_SHIFT (0x00000004u) #define CSL_MCBSP_RCERE2_RCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE3_MASK (0x00000008u) #define CSL_MCBSP_RCERE2_RCE3_SHIFT (0x00000003u) #define CSL_MCBSP_RCERE2_RCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE2_MASK (0x00000004u) #define CSL_MCBSP_RCERE2_RCE2_SHIFT (0x00000002u) #define CSL_MCBSP_RCERE2_RCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE1_MASK (0x00000002u) #define CSL_MCBSP_RCERE2_RCE1_SHIFT (0x00000001u) #define CSL_MCBSP_RCERE2_RCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RCE0_MASK (0x00000001u) #define CSL_MCBSP_RCERE2_RCE0_SHIFT (0x00000000u) #define CSL_MCBSP_RCERE2_RCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE2_RESETVAL (0x00000000u) /* XCERE2 */ #define CSL_MCBSP_XCERE2_XCE31_MASK (0x80000000u) #define CSL_MCBSP_XCERE2_XCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCERE2_XCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE30_MASK (0x40000000u) #define CSL_MCBSP_XCERE2_XCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_XCERE2_XCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE29_MASK (0x20000000u) #define CSL_MCBSP_XCERE2_XCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_XCERE2_XCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE28_MASK (0x10000000u) #define CSL_MCBSP_XCERE2_XCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_XCERE2_XCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE27_MASK (0x08000000u) #define CSL_MCBSP_XCERE2_XCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_XCERE2_XCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE26_MASK (0x04000000u) #define CSL_MCBSP_XCERE2_XCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_XCERE2_XCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE25_MASK (0x02000000u) #define CSL_MCBSP_XCERE2_XCE25_SHIFT (0x00000019u) #define CSL_MCBSP_XCERE2_XCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE24_MASK (0x01000000u) #define CSL_MCBSP_XCERE2_XCE24_SHIFT (0x00000018u) #define CSL_MCBSP_XCERE2_XCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE23_MASK (0x00800000u) #define CSL_MCBSP_XCERE2_XCE23_SHIFT (0x00000017u) #define CSL_MCBSP_XCERE2_XCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE22_MASK (0x00400000u) #define CSL_MCBSP_XCERE2_XCE22_SHIFT (0x00000016u) #define CSL_MCBSP_XCERE2_XCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE21_MASK (0x00200000u) #define CSL_MCBSP_XCERE2_XCE21_SHIFT (0x00000015u) #define CSL_MCBSP_XCERE2_XCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE20_MASK (0x00100000u) #define CSL_MCBSP_XCERE2_XCE20_SHIFT (0x00000014u) #define CSL_MCBSP_XCERE2_XCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE19_MASK (0x00080000u) #define CSL_MCBSP_XCERE2_XCE19_SHIFT (0x00000013u) #define CSL_MCBSP_XCERE2_XCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE18_MASK (0x00040000u) #define CSL_MCBSP_XCERE2_XCE18_SHIFT (0x00000012u) #define CSL_MCBSP_XCERE2_XCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE17_MASK (0x00020000u) #define CSL_MCBSP_XCERE2_XCE17_SHIFT (0x00000011u) #define CSL_MCBSP_XCERE2_XCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE16_MASK (0x00010000u) #define CSL_MCBSP_XCERE2_XCE16_SHIFT (0x00000010u) #define CSL_MCBSP_XCERE2_XCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE15_MASK (0x00008000u) #define CSL_MCBSP_XCERE2_XCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_XCERE2_XCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE14_MASK (0x00004000u) #define CSL_MCBSP_XCERE2_XCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_XCERE2_XCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE13_MASK (0x00002000u) #define CSL_MCBSP_XCERE2_XCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_XCERE2_XCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE12_MASK (0x00001000u) #define CSL_MCBSP_XCERE2_XCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_XCERE2_XCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE11_MASK (0x00000800u) #define CSL_MCBSP_XCERE2_XCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_XCERE2_XCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE10_MASK (0x00000400u) #define CSL_MCBSP_XCERE2_XCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_XCERE2_XCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE9_MASK (0x00000200u) #define CSL_MCBSP_XCERE2_XCE9_SHIFT (0x00000009u) #define CSL_MCBSP_XCERE2_XCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE8_MASK (0x00000100u) #define CSL_MCBSP_XCERE2_XCE8_SHIFT (0x00000008u) #define CSL_MCBSP_XCERE2_XCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE7_MASK (0x00000080u) #define CSL_MCBSP_XCERE2_XCE7_SHIFT (0x00000007u) #define CSL_MCBSP_XCERE2_XCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE6_MASK (0x00000040u) #define CSL_MCBSP_XCERE2_XCE6_SHIFT (0x00000006u) #define CSL_MCBSP_XCERE2_XCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE5_MASK (0x00000020u) #define CSL_MCBSP_XCERE2_XCE5_SHIFT (0x00000005u) #define CSL_MCBSP_XCERE2_XCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE4_MASK (0x00000010u) #define CSL_MCBSP_XCERE2_XCE4_SHIFT (0x00000004u) #define CSL_MCBSP_XCERE2_XCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE3_MASK (0x00000008u) #define CSL_MCBSP_XCERE2_XCE3_SHIFT (0x00000003u) #define CSL_MCBSP_XCERE2_XCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE2_MASK (0x00000004u) #define CSL_MCBSP_XCERE2_XCE2_SHIFT (0x00000002u) #define CSL_MCBSP_XCERE2_XCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE1_MASK (0x00000002u) #define CSL_MCBSP_XCERE2_XCE1_SHIFT (0x00000001u) #define CSL_MCBSP_XCERE2_XCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_XCE0_MASK (0x00000001u) #define CSL_MCBSP_XCERE2_XCE0_SHIFT (0x00000000u) #define CSL_MCBSP_XCERE2_XCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE2_RESETVAL (0x00000000u) /* RCERE3 */ #define CSL_MCBSP_RCERE3_RCE31_MASK (0x80000000u) #define CSL_MCBSP_RCERE3_RCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_RCERE3_RCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE30_MASK (0x40000000u) #define CSL_MCBSP_RCERE3_RCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_RCERE3_RCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE29_MASK (0x20000000u) #define CSL_MCBSP_RCERE3_RCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_RCERE3_RCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE28_MASK (0x10000000u) #define CSL_MCBSP_RCERE3_RCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_RCERE3_RCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE27_MASK (0x08000000u) #define CSL_MCBSP_RCERE3_RCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_RCERE3_RCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE26_MASK (0x04000000u) #define CSL_MCBSP_RCERE3_RCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_RCERE3_RCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE25_MASK (0x02000000u) #define CSL_MCBSP_RCERE3_RCE25_SHIFT (0x00000019u) #define CSL_MCBSP_RCERE3_RCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE24_MASK (0x01000000u) #define CSL_MCBSP_RCERE3_RCE24_SHIFT (0x00000018u) #define CSL_MCBSP_RCERE3_RCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE23_MASK (0x00800000u) #define CSL_MCBSP_RCERE3_RCE23_SHIFT (0x00000017u) #define CSL_MCBSP_RCERE3_RCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE22_MASK (0x00400000u) #define CSL_MCBSP_RCERE3_RCE22_SHIFT (0x00000016u) #define CSL_MCBSP_RCERE3_RCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE21_MASK (0x00200000u) #define CSL_MCBSP_RCERE3_RCE21_SHIFT (0x00000015u) #define CSL_MCBSP_RCERE3_RCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE20_MASK (0x00100000u) #define CSL_MCBSP_RCERE3_RCE20_SHIFT (0x00000014u) #define CSL_MCBSP_RCERE3_RCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE19_MASK (0x00080000u) #define CSL_MCBSP_RCERE3_RCE19_SHIFT (0x00000013u) #define CSL_MCBSP_RCERE3_RCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE18_MASK (0x00040000u) #define CSL_MCBSP_RCERE3_RCE18_SHIFT (0x00000012u) #define CSL_MCBSP_RCERE3_RCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE17_MASK (0x00020000u) #define CSL_MCBSP_RCERE3_RCE17_SHIFT (0x00000011u) #define CSL_MCBSP_RCERE3_RCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE16_MASK (0x00010000u) #define CSL_MCBSP_RCERE3_RCE16_SHIFT (0x00000010u) #define CSL_MCBSP_RCERE3_RCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE15_MASK (0x00008000u) #define CSL_MCBSP_RCERE3_RCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_RCERE3_RCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE14_MASK (0x00004000u) #define CSL_MCBSP_RCERE3_RCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_RCERE3_RCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE13_MASK (0x00002000u) #define CSL_MCBSP_RCERE3_RCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_RCERE3_RCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE12_MASK (0x00001000u) #define CSL_MCBSP_RCERE3_RCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_RCERE3_RCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE11_MASK (0x00000800u) #define CSL_MCBSP_RCERE3_RCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_RCERE3_RCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE10_MASK (0x00000400u) #define CSL_MCBSP_RCERE3_RCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_RCERE3_RCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE9_MASK (0x00000200u) #define CSL_MCBSP_RCERE3_RCE9_SHIFT (0x00000009u) #define CSL_MCBSP_RCERE3_RCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE8_MASK (0x00000100u) #define CSL_MCBSP_RCERE3_RCE8_SHIFT (0x00000008u) #define CSL_MCBSP_RCERE3_RCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE7_MASK (0x00000080u) #define CSL_MCBSP_RCERE3_RCE7_SHIFT (0x00000007u) #define CSL_MCBSP_RCERE3_RCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE6_MASK (0x00000040u) #define CSL_MCBSP_RCERE3_RCE6_SHIFT (0x00000006u) #define CSL_MCBSP_RCERE3_RCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE5_MASK (0x00000020u) #define CSL_MCBSP_RCERE3_RCE5_SHIFT (0x00000005u) #define CSL_MCBSP_RCERE3_RCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE4_MASK (0x00000010u) #define CSL_MCBSP_RCERE3_RCE4_SHIFT (0x00000004u) #define CSL_MCBSP_RCERE3_RCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE3_MASK (0x00000008u) #define CSL_MCBSP_RCERE3_RCE3_SHIFT (0x00000003u) #define CSL_MCBSP_RCERE3_RCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE2_MASK (0x00000004u) #define CSL_MCBSP_RCERE3_RCE2_SHIFT (0x00000002u) #define CSL_MCBSP_RCERE3_RCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE1_MASK (0x00000002u) #define CSL_MCBSP_RCERE3_RCE1_SHIFT (0x00000001u) #define CSL_MCBSP_RCERE3_RCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RCE0_MASK (0x00000001u) #define CSL_MCBSP_RCERE3_RCE0_SHIFT (0x00000000u) #define CSL_MCBSP_RCERE3_RCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_RCERE3_RESETVAL (0x00000000u) /* XCERE3 */ #define CSL_MCBSP_XCERE3_XCE31_MASK (0x80000000u) #define CSL_MCBSP_XCERE3_XCE31_SHIFT (0x0000001Fu) #define CSL_MCBSP_XCERE3_XCE31_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE30_MASK (0x40000000u) #define CSL_MCBSP_XCERE3_XCE30_SHIFT (0x0000001Eu) #define CSL_MCBSP_XCERE3_XCE30_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE29_MASK (0x20000000u) #define CSL_MCBSP_XCERE3_XCE29_SHIFT (0x0000001Du) #define CSL_MCBSP_XCERE3_XCE29_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE28_MASK (0x10000000u) #define CSL_MCBSP_XCERE3_XCE28_SHIFT (0x0000001Cu) #define CSL_MCBSP_XCERE3_XCE28_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE27_MASK (0x08000000u) #define CSL_MCBSP_XCERE3_XCE27_SHIFT (0x0000001Bu) #define CSL_MCBSP_XCERE3_XCE27_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE26_MASK (0x04000000u) #define CSL_MCBSP_XCERE3_XCE26_SHIFT (0x0000001Au) #define CSL_MCBSP_XCERE3_XCE26_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE25_MASK (0x02000000u) #define CSL_MCBSP_XCERE3_XCE25_SHIFT (0x00000019u) #define CSL_MCBSP_XCERE3_XCE25_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE24_MASK (0x01000000u) #define CSL_MCBSP_XCERE3_XCE24_SHIFT (0x00000018u) #define CSL_MCBSP_XCERE3_XCE24_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE23_MASK (0x00800000u) #define CSL_MCBSP_XCERE3_XCE23_SHIFT (0x00000017u) #define CSL_MCBSP_XCERE3_XCE23_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE22_MASK (0x00400000u) #define CSL_MCBSP_XCERE3_XCE22_SHIFT (0x00000016u) #define CSL_MCBSP_XCERE3_XCE22_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE21_MASK (0x00200000u) #define CSL_MCBSP_XCERE3_XCE21_SHIFT (0x00000015u) #define CSL_MCBSP_XCERE3_XCE21_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE20_MASK (0x00100000u) #define CSL_MCBSP_XCERE3_XCE20_SHIFT (0x00000014u) #define CSL_MCBSP_XCERE3_XCE20_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE19_MASK (0x00080000u) #define CSL_MCBSP_XCERE3_XCE19_SHIFT (0x00000013u) #define CSL_MCBSP_XCERE3_XCE19_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE18_MASK (0x00040000u) #define CSL_MCBSP_XCERE3_XCE18_SHIFT (0x00000012u) #define CSL_MCBSP_XCERE3_XCE18_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE17_MASK (0x00020000u) #define CSL_MCBSP_XCERE3_XCE17_SHIFT (0x00000011u) #define CSL_MCBSP_XCERE3_XCE17_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE16_MASK (0x00010000u) #define CSL_MCBSP_XCERE3_XCE16_SHIFT (0x00000010u) #define CSL_MCBSP_XCERE3_XCE16_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE15_MASK (0x00008000u) #define CSL_MCBSP_XCERE3_XCE15_SHIFT (0x0000000Fu) #define CSL_MCBSP_XCERE3_XCE15_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE14_MASK (0x00004000u) #define CSL_MCBSP_XCERE3_XCE14_SHIFT (0x0000000Eu) #define CSL_MCBSP_XCERE3_XCE14_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE13_MASK (0x00002000u) #define CSL_MCBSP_XCERE3_XCE13_SHIFT (0x0000000Du) #define CSL_MCBSP_XCERE3_XCE13_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE12_MASK (0x00001000u) #define CSL_MCBSP_XCERE3_XCE12_SHIFT (0x0000000Cu) #define CSL_MCBSP_XCERE3_XCE12_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE11_MASK (0x00000800u) #define CSL_MCBSP_XCERE3_XCE11_SHIFT (0x0000000Bu) #define CSL_MCBSP_XCERE3_XCE11_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE10_MASK (0x00000400u) #define CSL_MCBSP_XCERE3_XCE10_SHIFT (0x0000000Au) #define CSL_MCBSP_XCERE3_XCE10_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE9_MASK (0x00000200u) #define CSL_MCBSP_XCERE3_XCE9_SHIFT (0x00000009u) #define CSL_MCBSP_XCERE3_XCE9_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE8_MASK (0x00000100u) #define CSL_MCBSP_XCERE3_XCE8_SHIFT (0x00000008u) #define CSL_MCBSP_XCERE3_XCE8_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE7_MASK (0x00000080u) #define CSL_MCBSP_XCERE3_XCE7_SHIFT (0x00000007u) #define CSL_MCBSP_XCERE3_XCE7_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE6_MASK (0x00000040u) #define CSL_MCBSP_XCERE3_XCE6_SHIFT (0x00000006u) #define CSL_MCBSP_XCERE3_XCE6_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE5_MASK (0x00000020u) #define CSL_MCBSP_XCERE3_XCE5_SHIFT (0x00000005u) #define CSL_MCBSP_XCERE3_XCE5_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE4_MASK (0x00000010u) #define CSL_MCBSP_XCERE3_XCE4_SHIFT (0x00000004u) #define CSL_MCBSP_XCERE3_XCE4_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE3_MASK (0x00000008u) #define CSL_MCBSP_XCERE3_XCE3_SHIFT (0x00000003u) #define CSL_MCBSP_XCERE3_XCE3_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE2_MASK (0x00000004u) #define CSL_MCBSP_XCERE3_XCE2_SHIFT (0x00000002u) #define CSL_MCBSP_XCERE3_XCE2_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE1_MASK (0x00000002u) #define CSL_MCBSP_XCERE3_XCE1_SHIFT (0x00000001u) #define CSL_MCBSP_XCERE3_XCE1_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_XCE0_MASK (0x00000001u) #define CSL_MCBSP_XCERE3_XCE0_SHIFT (0x00000000u) #define CSL_MCBSP_XCERE3_XCE0_RESETVAL (0x00000000u) #define CSL_MCBSP_XCERE3_RESETVAL (0x00000000u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotHwSetup.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_memprotHwSetup.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotHwSetup () * */ /* ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * * 16-Nov-2005 ds Updated the documentation * ============================================================================= */ #include <csl_memprot.h> #include <csl_memprotAux.h> /** ============================================================================ * @n@b CSL_memprotHwSetup * * @b Description * @n This function initializes the module registers with the appropriate * values provided through the HwSetup Data structure. * For information passed through the HwSetup Data structure refer * @a CSL_memprotHwSetup. * * @b Arguments * @verbatim hMemprot Handle to the memprot instance setup Pointer to harware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup successful. * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Hardware structure is not properly initialized * * Pre Condition * Both @a CSL_memprotInit() and @a CSL_memprotOpen() must be called * successfully in that order before this function can be called. The user * has to allocate space for & fill in the main setup structure appropriately * before calling this function. Ensure numpages is not set to > 32 for handles * for L1D/L1P. Ensure numpages is not > 64 for L2. * * Post Condition * @n 1. MEMPROT object structure is populated * @n 2. The status is returned in the status variable. If status * returned is * @li CSL_SOK Valid MEMPORT handle is returned * @li CSL_ESYS_INVPARAMS Invalid parameter * @li CSL_ESYS_BADHANDLE Invalid Handle * * @b Modifies * @n The hardware registers of MEMPORT. * * @b Example * @verbatim #define PAGE_ATTR 0xFFF0 CSL_MemprotObj mpL2Obj; CSL_MemprotHandle hmpL2; CSL_Status status; CSL_MemprotHwSetup L2MpSetup; Uint16 pageAttrTable[10] = {PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR, PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR,PAGE_ATTR}; Uint32 key[2] = {<KEY>}; // Initializing the module CSL_memprotInit(NULL); // Opening the Handle for the L2 hmpL2 = CSL_memprotOpen(&mpL2Obj, CSL_MEMPROT_L2, NULL, &status); L2MpSetup. memPageAttr = pageAttrTable; L2MpSetup.numPages = 10; L2MpSetup.key = key; // Do Setup for the L2 Memory protection/ CSL_memprotHwSetup (hmpL2, &L2MpSetup); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_memprotHwSetup, ".text:csl_section:memprot"); CSL_Status CSL_memprotHwSetup ( /* Handle to the memprot instance */ CSL_MemprotHandle hMemprot, /* Pointer to setup structure which contains the * information to program the memory protection module to a useful state. */ CSL_MemprotHwSetup *setup ) { CSL_Status status = CSL_SOK; Uint16 i; if (hMemprot == NULL) { status = CSL_ESYS_BADHANDLE; } else if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Unlock the module. This call anyways checks if the module is already locked/not */ if (setup->key != NULL) { CSL_memprotUnLock(hMemprot,setup->key); } /* Program memory page attribute registers */ for (i = 0;i < setup->numPages ;i++) { hMemprot->regs->MPPA[i] = setup->memPageAttr[i]; } /* Lock Module */ if (setup->key != NULL) { status = CSL_memprotLock(hMemprot,setup->key); } } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaHwSetup.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaHwSetup.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_emifaHwSetup.c * * @path $(CSLPATH)\src\emifa * * @desc File for functional layer of CSL API @a CSL_emifaHwSetup() * - The @a CSL_emifaHwSetup() function definition & it's associated * functions * */ /* ============================================================================= * Revision History * =============== * 12-May-2005 RM File Created. * * 08-Jul-2005 RM Changes made in accordance to the change in cslr_emifa.h * * 09-Sep-2005 NG Updation according to coding guidelines * * ============================================================================= */ #include <csl_emifa.h> /** ============================================================================ * @n@b CSL_emifaHwSetup * * @b Description * @n This function initializes the device registers with the appropriate values * provided through the HwSetup data structure. For information passed through * the HwSetup data structure refer @a CSL_EmifaHwSetup. * * @b Arguments * @verbatim hEmifa Pointer to the object that holds reference to the instance of EMIFA requested after the call setup Pointer to setup structure which contains the information to program EMIFA to a useful state @endverbatim * * Return Value CSL_Status * @li CSL_SOK - configuration successful * @li CSL_ESYS_FAIL - The external memory interface * instance is not available. * @li CSL_ESYS_INVPARAMS - Parameters are not valid * @li CSL_ESYS_BADHANDLE - Handle is not valid * * Pre Condition * @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called * successfully in order before calling this function. The user has to * allocate space for & fill in the main setup structure appropriately * before calling this function. * * Post Condition * @n EMIFA registers are configured according to the hardware setup parameters * * @b Modifies * @n EMIFA registers * * @b Example: * @verbatim CSL_EmifaHandle hEmifa; CSL_EmifaAsync asyncMem = CSL_EMIFA_ASYNCCFG_DEFAULTS; CSL_EmifaAsyncWait asyncWait = CSL_EMIFA_ASYNCWAIT_DEFAULTS; CSL_EmifaMemType value; CSL_EmifaHwSetup hwSetup ; value.ssel = 0; value.async = &asyncMem; value.sync = NULL; hwSetup.asyncWait = &asyncMem; hwSetup.cefg [0] = &value; hwSetup.ceCfg [1] = NULL; hwSetup.ceCfg [2] = NULL; hwSetup.ceCfg [3] = NULL; //Initialize the Emifa CSL //Open Emifa Module CSL_emifaHwSetup(hEmifa, &hwSetup); @endverbatim * * ============================================================================ */ #pragma CODE_SECTION (CSL_emifaHwSetup, ".text:csl_section:emifa"); CSL_Status CSL_emifaHwSetup( CSL_EmifaHandle hEmifa, CSL_EmifaHwSetup *setup ) { CSL_Status status = CSL_SOK; Uint32 mask, mask1, mask2; Uint8 loop; volatile Uint32 *ceCfgBaseAddr = 0; /* invalid parameter checking */ if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else if (hEmifa == NULL) { /* bad handle checking */ status = CSL_ESYS_BADHANDLE; } else { if (setup->asyncWait != NULL) { mask = ~((CSL_EMIFA_AWCC_AP_MASK) |(CSL_EMIFA_AWCC_TA_MASK) | (CSL_EMIFA_AWCC_MAX_EXT_WAIT_MASK)); hEmifa->regs->AWCC = (hEmifa->regs->AWCC & mask) | (CSL_FMK(EMIFA_AWCC_AP, setup->asyncWait->asyncRdyPol)) | (CSL_FMK(EMIFA_AWCC_TA, setup->asyncWait->turnArnd)) | (CSL_FMK(EMIFA_AWCC_MAX_EXT_WAIT, setup->asyncWait->maxExtWait)); } /* Configuring chip selects for synchronous or Asynchronous memory */ ceCfgBaseAddr = &(hEmifa->regs->CE2CFG); mask1 = ~((CSL_EMIFA_CE2CFG_SS_MASK) | (CSL_EMIFA_CE2CFG_BWEM_MASK) | (CSL_EMIFA_CE2CFG_AE_MASK) | (CSL_EMIFA_CE2CFG_W_SETUP_MASK) | (CSL_EMIFA_CE2CFG_W_STROBE_MASK) | (CSL_EMIFA_CE2CFG_W_HOLD_MASK) | (CSL_EMIFA_CE2CFG_R_SETUP_MASK) | (CSL_EMIFA_CE2CFG_R_STROBE_MASK) | (CSL_EMIFA_CE2CFG_R_HOLD_MASK) | (CSL_EMIFA_CE2CFG_ASIZE_MASK)); mask2 = ~((CSL_EMIFA_CE2CFG_RD_BE_EN_MASK) | (CSL_EMIFA_CE2CFG_CE_EXT_MASK) | (CSL_EMIFA_CE2CFG_R_ENABLE_MASK) | (CSL_EMIFA_CE2CFG_W_LTNCY_MASK) | (CSL_EMIFA_CE2CFG_R_LTNCY_MASK) | (CSL_EMIFA_CE2CFG_SBSIZE_MASK)); for (loop = 0; loop < NUMCHIPENABLE; loop++) { if (setup->ceCfg[loop] != NULL) { if ((setup->ceCfg[loop]->ssel == 0) && (setup->ceCfg[loop]->async != NULL)) { CSL_FINS(*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_SSEL, CSL_EMIFA_CE2CFG_SSEL_ASYNCMEM); *(ceCfgBaseAddr + loop) = (*(ceCfgBaseAddr + loop) & mask1) | (CSL_FMK(EMIFA_CE2CFG_SS, setup->ceCfg[loop]->async->selectStrobe)) | (CSL_FMK(EMIFA_CE2CFG_BWEM, setup->ceCfg[loop]->async->weMode)) | (CSL_FMK(EMIFA_CE2CFG_AE, setup->ceCfg[loop]->async->asyncRdyEn)) | (CSL_FMK(EMIFA_CE2CFG_W_SETUP, setup->ceCfg[loop]->async->wSetup)) | (CSL_FMK(EMIFA_CE2CFG_W_STROBE, setup->ceCfg[loop]->async->wStrobe)) | (CSL_FMK(EMIFA_CE2CFG_W_HOLD, setup->ceCfg[loop]->async->wHold)) | (CSL_FMK(EMIFA_CE2CFG_R_SETUP, setup->ceCfg[loop]->async->rSetup)) | (CSL_FMK(EMIFA_CE2CFG_R_STROBE, setup->ceCfg[loop]->async->rStrobe)) | (CSL_FMK(EMIFA_CE2CFG_R_HOLD, setup->ceCfg[loop]->async->rHold)) | (CSL_FMK(EMIFA_CE2CFG_ASIZE, setup->ceCfg[loop]->async->asize)); } else { if ((setup->ceCfg[loop]->ssel == 1) && (setup->ceCfg[loop]->sync != NULL)) { CSL_FINS(*(ceCfgBaseAddr + loop), EMIFA_CE2CFG_SSEL, CSL_EMIFA_CE2CFG_SSEL_SYNCMEM); *(ceCfgBaseAddr + loop) = (*(ceCfgBaseAddr + loop) & mask2)| (CSL_FMK(EMIFA_CE2CFG_RD_BE_EN, setup->ceCfg[loop]->sync->readByteEn)) | (CSL_FMK(EMIFA_CE2CFG_CE_EXT, setup->ceCfg[loop]->sync->chipEnExt)) | (CSL_FMK(EMIFA_CE2CFG_R_ENABLE, setup->ceCfg[loop]->sync->readEn)) | (CSL_FMK(EMIFA_CE2CFG_W_LTNCY, setup->ceCfg[loop]->sync->w_ltncy)) | (CSL_FMK(EMIFA_CE2CFG_R_LTNCY, setup->ceCfg[loop]->sync->r_ltncy)) | (CSL_FMK(EMIFA_CE2CFG_SBSIZE, setup->ceCfg[loop]->sync->sbsize)); } else { status = CSL_ESYS_FAIL; } } } } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_hpi.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_hpi.h * * @path $(CSLPATH)\inc * * @brief HPI functional layer API header file * */ /** * @mainpage HPI CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the HPI module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given HPI module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular HPI Module. The CSL developer should use his discretion designing * new APIs or extending the existing ones to cover these. * * @subsection Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 * */ /* ============================================================================= * Revision History * =============== * 06-Feb-2006 ds Removed CSL_HPI_QUERY_PID_REV, CSL_HPI_QUERY_PID_TYPE and * CSL_HPI_QUERY_PID_CLASS from the CSL_HpiHwStatusQuery * * ============================================================================= */ #ifndef _CSL_HPI_H_ #define _CSL_HPI_H_ #ifdef __cplusplus extern "C" { #endif #include <cslr.h> #include <soc.h> #include <csl_error.h> #include <csl_types.h> #include <csl.h> #include <cslr_hpi.h> /** * @brief Enumeration for queries passed to @a CSL_hpiGetHwStatus() * * This is used to get the status of different operations */ typedef enum { CSL_HPI_QUERY_HRDY = 1, /**< * @brief Query the current value of Host Fetch * @param (Uint32 *) */ CSL_HPI_QUERY_FETCH = 2, /**< * @brief Query the current value of HPI Reset * @param (Uint32 *) */ CSL_HPI_QUERY_HPI_RST = 3, /**< * @brief Query the current value of Half-word ordering status * @param (Uint32 *) */ CSL_HPI_QUERY_HWOB_STAT = 4 } CSL_HpiHwStatusQuery; /** * @brief Enumeration for commands passed to @a CSL_hpiHwControl() * * This is used to select the commands to control the operations * existing setup of HPI. The arguments to be passed with each * enumeration if any are specified next to the enumeration. */ typedef enum { /**< * @brief Sets the HPIC Host-to-DSP Interrupt. * @param (None) */ CSL_HPI_CMD_SET_DSP_INT = 0, /**< * @brief Reset the HPIC Host-to-DSP Interrupt. * @param (None) */ CSL_HPI_CMD_RESET_DSP_INT = 1, /**< * @brief Set the HPIC DSP-to-Host Interrupt. * @param (None) */ CSL_HPI_CMD_SET_HINT = 2, /**< * @brief Reset the HPIC DSP-to-Host Interrupt. * @param (None) */ CSL_HPI_CMD_RESET_HINT = 3 } CSL_HpiHwControlCmd; /** @brief Structure configures Host Port Interface Write & Read Address */ typedef struct { /** Host Port Interface Write Address */ Uint32 hpiaWrtAddr; /** Host Port Interface Read Address */ Uint32 hpiaReadAddr; } CSL_HpiAddrCfg; /** @brief Enumation for the control commands of HPI. */ typedef enum { /** Half-word Ordering Bit */ CSL_HPI_HWOB = 0x1, /** Host-to-DSP Interrupt */ CSL_HPI_DSP_INT = 0x2, /** DSP-to-Host Interrupt */ CSL_HPI_HINT = 0x4, /** Host Ready */ CSL_HPI_HRDY = 0x8, /** Host Fetch */ CSL_HPI_FETCH = 0x10, /** CPU Core Reset */ CSL_HPI_RESET = 0x40, /** HPI Reset */ CSL_HPI_HPI_RST = 0x80, /** Half-word ordering bit status */ CSL_HPI_HWOB_STAT = 0x100, /** Dual HPIA mode configuration bit */ CSL_HPI_DUAL_HPIA = 0x200, /** HPIA register select bit */ CSL_HPI_HPIA_RW_SEL = 0x800 } CSL_HpiCtrl; /** @brief The structure contains the HPI hardware setup */ typedef struct { /** Host port Interface control Register */ CSL_HpiCtrl hpiCtrl; /** Host port Interface Read & Write Address Register */ CSL_HpiAddrCfg hpiAddr; /** Emulation Mode parameter */ Uint32 emu; } CSL_HpiHwSetup; /** @brief The configuration structure which is to configure HPI. */ typedef struct { /** Power and Emulation Management Register */ volatile Uint32 PWREMU_MGMT; /** Host Port Interface Control Register */ volatile Uint32 HPIC; /** Host Port Interface Write Address Register */ volatile Uint32 HPIAW; /** Host Port Interface Read Address Register */ volatile Uint32 HPIAR; } CSL_HpiConfig; /** Default Values for Config structure */ #define CSL_HPI_CONFIG_DEFAULTS { \ CSL_HPI_PWREMU_MGMT_RESETVAL, \ CSL_HPI_HPIC_RESETVAL, \ CSL_HPI_HPIAW_RESETVAL, \ CSL_HPI_HPIAR_RESETVAL \ } /** @brief HPI specific context information. Present implementation of HPI * CSL doesn't have any context information. */ typedef struct { /** Context information of HPI CSL. * The below declaration is just a place-holder for future implementation. */ Uint32 contextInfo; } CSL_HpiContext; /** @brief HPI specific parameters. Present implementation of HPI CSL * doesn't have any module specific parameters. */ typedef struct { /** Bit mask to be used for module specific parameters. The below * declaration is just a place-holder for future implementation. */ CSL_BitMask32 flags; } CSL_HpiParam; /** @brief This structure contains the base-address information for the * peripheral instance of the HPI */ typedef struct { /** Base-address of the configuration registers of the peripheral */ CSL_HpiRegsOvly regs; } CSL_HpiBaseAddress; /** @brief This structure/object holds the context of the instance of HPI * opened using CSL_hpiOpen() function. Pointer to this object is * passed as HPI Handle to all HPI CSL APIs. CSL_hpiOpen() function * initializes this structure based on the parameters passed */ typedef struct CSL_HpiObj{ /** Pointer to the register overlay structure of the hpi */ CSL_HpiRegsOvly regs; /** Instance of hpi being referred by this object */ CSL_InstNum hpiNum; } CSL_HpiObj; /** @brief This data type is used to return the handle to the CSL of the HPI */ typedef struct CSL_HpiObj *CSL_HpiHandle; /******************************************************************************* * DSP HPI controller function declarations ******************************************************************************/ /** ============================================================================ * @n@b CSL_hpiInit * * @b Description * @n This is the initialization function for the hpi CSL. The function * must be called before calling any other API from this CSL. This * function is idem-potent. Currently, the function just return status * CSL_SOK, without doing anything. * * @b Arguments * @verbatim pContext Pointer to module-context. As HPI doesn't have any context based information user is expected to pass NULL. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Status status; ... status = CSL_hpiInit(NULL); ... @endverbatim * ============================================================================= */ extern CSL_Status CSL_hpiInit ( CSL_HpiContext *pContext ); /** ============================================================================ * @n@b CSL_hpiOpen * * @b Description * @n This function returns the handle to the HPI controller * instance. This handle is passed to all other CSL APIs. * * @b Arguments * @verbatim hpiObj Pointer to the object that holds reference to the instance of HPI requested after the call. hpiNum Instance of HPI to which a handle is requested. There is only one instance of the hpi available. So, the value for this parameter will be CSL_HPI always. pHpiParam Module specific parameters. status Status of the function call @endverbatim * * Return Value CSL_HpiHandle * @n Valid HPI handle will be returned if * status value is equal to CSL_SOK. * * Pre Condition * @n None * * Post Condition * @n 1. The status is returned in the status variable. If status * returned is * @li CSL_SOK - Valid HPI handle is returned * @li CSL_ESYS_FAIL - The HPI instance is invalid * @li CSL_ESYS_INVPARAMS - Invalid parameter * * 2. HPI object structure is populated * * @b Modifies * @n 1. The status variable * * 2. HPI object structure * * @b Example * @verbatim CSL_status status; CSL_HpiObj hpiObj; CSL_HpiHandle hHpi; ... hHpi = CSL_hpiOpen(&hpiObj, CSL_HPI, NULL, &status); ... @endverbatim * ============================================================================= */ extern CSL_HpiHandle CSL_hpiOpen ( CSL_HpiObj *hpiObj, CSL_InstNum hpiNum, CSL_HpiParam *pHpiParam, CSL_Status *status ); /** ============================================================================ * @n@b CSL_hpiGetBaseAddress * * @b Description * @n Function to get the base address of the peripheral instance. * This function is used for getting the base address of the peripheral * instance. This function will be called inside the CSL_hpiOpen() * function call. This function is open for re-implementing if the user * wants to modify the base address of the peripheral object to point to * a different location and there by allow CSL initiated write/reads into * peripheral. MMR's go to an alternate location. * * @b Arguments * @verbatim hpiNum Specifies the instance of the hpi to be opened. pHpiParam Module specific parameters. pBaseAddress Pointer to base address structure containing base address details. @endverbatim * * Return Value CSL_Status * @li CSL_OK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * @li CSL_ESYS_INVPARAMS Invalid parameter * * Pre Condition * @n None * * Post Condition * @n Base address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_HpiBaseAddress baseAddress; ... status = CSL_hpiGetBaseAddress(CSL_HPI, NULL, &baseAddress); ... @endverbatim * =========================================================================== */ extern CSL_Status CSL_hpiGetBaseAddress ( CSL_InstNum hpiNum, CSL_HpiParam *pHpiParam, CSL_HpiBaseAddress *pBaseAddress ); /** ============================================================================ * @n@b CSL_hpiClose * * @b Description * @n This function closes the specified instance of HPI. * * @b Arguments * @verbatim hHpi Handle to the HPI @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Close successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * Pre Condition * @n The HPI instance should be opened before this close operation. * * Post Condition * @n The HPI CSL APIs can not be called until the HPI CSL is reopened * again using CSL_hpiOpen(). * * @b Modifies * @n None * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_Status status; ... status = CSL_hpiClose(hHpi); @endverbatim * =========================================================================== */ extern CSL_Status CSL_hpiClose ( CSL_HpiHandle hHpi ); /** ============================================================================ * @n@b CSL_hpiHwSetup * * @b Description * @n It configures the hpi registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim hHpi Handle to the hpi hwSetup Pointer to harware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup successful * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVPARAMS - The parameter passed is * invalid * * Pre Condition * @n None * * Post Condition * @n HPI registers are configured according to the hardware setup * parameters. * * @b Modifies * @n HPI registers * * @b Example * @verbatim CSL_status status; CSL_HpiHwSetup myHwSetup; CSL_HpiHandle hHpi; myHwSetup.HPIC = hwSetup->hpiCtrl; ..... status = CSL_hpiHwSetup(hHpi, &hwSetup); @endverbatim * =========================================================================== */ extern CSL_Status CSL_hpiHwSetup ( CSL_HpiHandle hHpi, CSL_HpiHwSetup *hwSetup ); /** ============================================================================ * @n@b CSL_hpiHwControl * * @b Description * @n This function takes an input control command with an optional argument * and accordingly controls the operation/configuration of HPI. * * @b Arguments * @verbatim hHpi Handle to the HPI instance cmd The command to this API indicates the action to be taken on HPI. arg An optional argument. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Command successful. * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVCMD - Invalid command * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order * before calling CSL_hpiHwControl(). * * Post Condition * @n HPI registers are configured according to the command passed. * * @b Modifies * @n The hardware registers of HPI. * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_HpiHwControlCmd cmd; void arg; status = CSL_hpiHwControl(hHpi, cmd, &arg); @endverbatim * ============================================================================= */ extern CSL_Status CSL_hpiHwControl ( CSL_HpiHandle hHpi, CSL_HpiHwControlCmd cmd, void *arg ); /** ============================================================================ * @n@b CSL_hpiGetHwStatus * * @b Description * @n Gets the status of the different operations of HPI. * * @b Arguments * @verbatim hHpi Handle to the HPI instance query The query to this API of HPI which indicates the status to be returned. response Placeholder to return the status. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Query successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVQUERY - The Query passed is invalid * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order * before calling CSL_hpiGetHwStatus(). * * Post Condition * @n None * * @b Modifies * @n Third parameter response vlaue * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_HpiHwStatusQuery query; void reponse; status = CSL_hpiGetHwStatus(hHpi, query, &response); @endverbatim * ============================================================================= */ extern CSL_Status CSL_hpiGetHwStatus ( CSL_HpiHandle hHpi, CSL_HpiHwStatusQuery query, void *response ); /** ============================================================================ * @n@b CSL_hpiHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hHpi Handle to the HPI instance config Pointer to Config structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not properly initialized * Pre Condition * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in * order before calling CSL_hpiGetHwSetupRaw(). * * Post Condition * @n The registers of the specified HPI instance will be setup * according to input configuration structure values. * * @b Modifies * @n Hardware registers of the specified HPI instance. * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_HpiConfig config = CSL_HPI_CONFIG_DEFAULTS; CSL_Status status; status = CSL_hpiHwSetupRaw(hHpi, &config); @endverbatim * ============================================================================= */ extern CSL_Status CSL_hpiHwSetupRaw ( CSL_HpiHandle hHpi, CSL_HpiConfig *config ); /** ============================================================================ * @n@b CSL_hpiGetHwSetup * * @b Description * @n It retrives the hardware setup parameters of the hpi * specified by the given handle. * * @b Arguments * @verbatim hHpi Handle to the hpi hwSetup Pointer to the harware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Retrieving the hardware setup * parameters is successful * @li CSL_ESYS_BADHANDLE - The handle is passed is * invalid * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order * before calling CSL_hpiGetHwSetup(). * * Post Condition * @n The hardware setup structure is populated with the hardware setup * parameters * * @b Modifies * @n hwSetup variable * * @b Example * @verbatim CSL_HpiHandle hHpi; CSL_HpiHwSetup hwSetup; ... status = CSL_hpiGetHwSetup(hHpi, &hwSetup); ... @endverbatim * =========================================================================== */ extern CSL_Status CSL_hpiGetHwSetup( CSL_HpiHandle hHpi, CSL_HpiHwSetup *hwSetup ); #ifdef __cplusplus } #endif #endif /* _CSL_HPI_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_hpi.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_hpi.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for HPI */ #ifndef _CSLR_HPI_H_ #define _CSLR_HPI_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint8 RSVD0[4]; volatile Uint32 PWREMU_MGMT; volatile Uint8 RSVD1[40]; volatile Uint32 HPIC; volatile Uint32 HPIAW; volatile Uint32 HPIAR; } CSL_HpiRegs; /**************************************************************************\ * Overlay structure typedef definition \**************************************************************************/ typedef volatile CSL_HpiRegs *CSL_HpiRegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* PWREMU_MGMT */ #define CSL_HPI_PWREMU_MGMT_SOFT_MASK (0x00000002u) #define CSL_HPI_PWREMU_MGMT_SOFT_SHIFT (0x00000001u) #define CSL_HPI_PWREMU_MGMT_SOFT_RESETVAL (0x00000000u) /*----SOFT Tokens----*/ #define CSL_HPI_PWREMU_MGMT_SOFT_OFF (0x00000000u) #define CSL_HPI_PWREMU_MGMT_SOFT_ON (0x00000001u) #define CSL_HPI_PWREMU_MGMT_FREE_MASK (0x00000001u) #define CSL_HPI_PWREMU_MGMT_FREE_SHIFT (0x00000000u) #define CSL_HPI_PWREMU_MGMT_FREE_RESETVAL (0x00000000u) /*----FREE Tokens----*/ #define CSL_HPI_PWREMU_MGMT_FREE_OFF (0x00000000u) #define CSL_HPI_PWREMU_MGMT_FREE_ON (0x00000001u) #define CSL_HPI_PWREMU_MGMT_RESETVAL (0x00000000u) /* HPIC */ #define CSL_HPI_HPIC_HPIARWSEL_MASK (0x00000800u) #define CSL_HPI_HPIC_HPIARWSEL_SHIFT (0x0000000Bu) #define CSL_HPI_HPIC_HPIARWSEL_RESETVAL (0x00000000u) /*----HPIARWSEL Tokens----*/ #define CSL_HPI_HPIC_HPIARWSEL_HPIA_R (0x00000000u) #define CSL_HPI_HPIC_HPIARWSEL_HPIA_W (0x00000001u) #define CSL_HPI_HPIC_DUALHPIA_MASK (0x00000200u) #define CSL_HPI_HPIC_DUALHPIA_SHIFT (0x00000009u) #define CSL_HPI_HPIC_DUALHPIA_RESETVAL (0x00000000u) /*----DUALHPIA Tokens----*/ #define CSL_HPI_HPIC_DUALHPIA_DISABLE (0x00000000u) #define CSL_HPI_HPIC_DUALHPIA_ENABLE (0x00000001u) #define CSL_HPI_HPIC_HWOBSTAT_MASK (0x00000100u) #define CSL_HPI_HPIC_HWOBSTAT_SHIFT (0x00000008u) #define CSL_HPI_HPIC_HWOBSTAT_RESETVAL (0x00000000u) #define CSL_HPI_HPIC_HPIRST_MASK (0x00000080u) #define CSL_HPI_HPIC_HPIRST_SHIFT (0x00000007u) #define CSL_HPI_HPIC_HPIRST_RESETVAL (0x00000001u) #define CSL_HPI_HPIC_FETCH_MASK (0x00000010u) #define CSL_HPI_HPIC_FETCH_SHIFT (0x00000004u) #define CSL_HPI_HPIC_FETCH_RESETVAL (0x00000000u) #define CSL_HPI_HPIC_HRDY_MASK (0x00000008u) #define CSL_HPI_HPIC_HRDY_SHIFT (0x00000003u) #define CSL_HPI_HPIC_HRDY_RESETVAL (0x00000000u) #define CSL_HPI_HPIC_HINT_MASK (0x00000004u) #define CSL_HPI_HPIC_HINT_SHIFT (0x00000002u) #define CSL_HPI_HPIC_HINT_RESETVAL (0x00000000u) /*----HINT Tokens----*/ #define CSL_HPI_HPIC_HINT_DISABLE (0x00000001u) #define CSL_HPI_HPIC_HINT_ENABLE (0x00000001u) #define CSL_HPI_HPIC_DSPINT_MASK (0x00000002u) #define CSL_HPI_HPIC_DSPINT_SHIFT (0x00000001u) #define CSL_HPI_HPIC_DSPINT_RESETVAL (0x00000000u) /*----DSPINT Tokens----*/ #define CSL_HPI_HPIC_DSPINT_DISABLE (0x00000000u) #define CSL_HPI_HPIC_DSPINT_ENABLE (0x00000001u) #define CSL_HPI_HPIC_HWOB_MASK (0x00000001u) #define CSL_HPI_HPIC_HWOB_SHIFT (0x00000000u) #define CSL_HPI_HPIC_HWOB_RESETVAL (0x00000000u) /*----HWOB Tokens----*/ #define CSL_HPI_HPIC_HWOB_DISABLE (0x00000000u) #define CSL_HPI_HPIC_HWOB_ENABLE (0x00000001u) #define CSL_HPI_HPIC_RESETVAL (0x00000080u) /* HPIAW */ #define CSL_HPI_HPIAW_HPIAW_MASK (0xFFFFFFFFu) #define CSL_HPI_HPIAW_HPIAW_SHIFT (0x00000000u) #define CSL_HPI_HPIAW_HPIAW_RESETVAL (0x00000000u) #define CSL_HPI_HPIAW_RESETVAL (0x00000000u) /* HPIAR */ #define CSL_HPI_HPIAR_HPIAR_MASK (0xFFFFFFFFu) #define CSL_HPI_HPIAR_HPIAR_SHIFT (0x00000000u) #define CSL_HPI_HPIAR_HPIAR_RESETVAL (0x00000000u) #define CSL_HPI_HPIAR_RESETVAL (0x00000000u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcClose.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** @file csl_pllcClose.c * * @brief File for functional layer of CSL API @a CSL_pllcClose() * * @path \(CSLPATH)\src\pllc * */ /* ============================================================================ * Revision History * =============== * 10-Feb-2004 kpn CSL3X Upgradation. * ============================================================================ */ #include <csl_pllc.h> /** ============================================================================ * @n@b CSL_pllcClose * * @b Description * @n This function closes the specified instance of PLLC. * * @b Arguments * @verbatim hPllc Handle to the pllc @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Close successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * Pre Condition * @n None * * Post Condition * @n 1. PLLC instance is closed and its usage is * illegal until next open * * * @b Modifies * @n 1. PLLC object structure * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_status status; ... status = CSL_pllcClose(hPllc); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_pllcClose, ".text:csl_section:pllc"); CSL_Status CSL_pllcClose ( CSL_PllcHandle hPllc ) { CSL_Status status; if (hPllc != NULL) { hPllc->regs = (CSL_PllcRegsOvly)NULL; hPllc->pllcNum = (CSL_InstNum)-1; status = CSL_SOK; } else { status = CSL_ESYS_BADHANDLE; } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/edma/edma_sub_frame_xfer/src/Edma_sub_frame_xfer.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * * @file Edma_sub_frame_xfer.c * * @path $(CSLPATH)\example\edma\edma_sub_frame_xfer\src * * @desc Example of EDMA * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @n This illustrates Edma Sub frame transfer * This example do the following operations * - Initializes and Opens the edma module * - Sets up the Module * - Enables (Bits 0-15) the Shadow Region 0 * - Opens Channel 0 in context of Shadow region 0 * - Obtains a handles to parameters set 0 * - Sets up the param set * - Enables Channel and Initialize the data * - Manually triggers the Channel * - Polls on interrupt bit 0 and clears interrupt bit 0 * - Compares the transfered data * - Displays the result based on previous step * * ============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Edma_sub_frame_xfer.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================= * Revision History * =============== * 08-Feb-2006 ds File Created. * * ============================================================================= */ #include <stdio.h> #include <csl_edma3.h> #include <soc.h> /* Number of bytes to transfer */ #define NOF_BYTES_XFR 512 /* Globals */ Uint8 srcBuff1[NOF_BYTES_XFR]; Uint8 dstBuff1[NOF_BYTES_XFR]; Uint32 passStatus = 1; /* Forward declaration */ void edma_sub_frame_xfer (void); /* * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= */ void main(void) { /* Invoke example */ edma_sub_frame_xfer (); return; } /* * ============================================================================= * @func edma_sub_frame_xfer * * @arg * NONE * * @desc * This is the example routine which perform edma sub frame transfer * It implements following steps * - Initializes and Opens the edma module * - Sets up the Module * - Enables (Bits 0-15) the Shadow Region 0 * - Opens Channel 0 in context of Shadow region 0 * - Obtains a handles to parameters set 0 * - Sets up the param set * - Enables Channel and Initialize the data * - Manually triggers the Channel * - Polls on interrupt bit 0 and clears interrupt bit 0 * - Compares the transfered data * - Displays the result based on previous step * * @return * NONE * * ============================================================================= */ void edma_sub_frame_xfer (void) { CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ChannelObj chObj; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Status status; CSL_Edma3HwDmaChannelSetup dmahwSetup; volatile Uint32 loopIndex; printf ("Running Edma Example\n"); /* Module Initialization */ status = CSL_edma3Init(&context); if (status != CSL_SOK) { printf ("Edma module initialization failed\n"); return; } /* Module level open */ hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); if ( (hModule == NULL) || (status != CSL_SOK)) { printf ("Edma module open failed\n"); return; } /* Module setup */ dmahwSetup.paramNum = 0; dmahwSetup.que = CSL_EDMA3_QUE_0; hwSetup.dmaChaSetup = &dmahwSetup; hwSetup.qdmaChaSetup = NULL; status = CSL_edma3HwSetup(hModule,&hwSetup); if (status != CSL_SOK) { printf ("Hardware setup failed\n"); CSL_edma3Close (hModule); return; } /* DRAE enable(Bits 0-15) for the shadow region 5 */ regionAccess.region = CSL_EDMA3_REGION_5 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); if (status != CSL_SOK) { printf ("Edma region enable command failed\n"); return; } /* Channel 0 open in context of shadow region 5 */ chAttr.regionNum = CSL_EDMA3_REGION_5; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); if ((hChannel == NULL) || (status != CSL_SOK)) { printf ("Edma channel open failed\n"); return; } /* Obtain a handle to parameter set 0 */ hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); if (hParamBasic == NULL) { printf ("Edma get param handle for param entry 0 failed\n"); return; } /* Setup the first param set */ myParamSetup.option = CSL_EDMA3_OPT_MAKE (CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 0, CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_EN, \ CSL_EDMA3_SYNC_AB, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR ); myParamSetup.srcAddr = (Uint32)srcBuff1; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(20,12); myParamSetup.dstAddr = (Uint32)dstBuff1; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(40,20); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, 1); myParamSetup.cCnt = 1; status = CSL_edma3ParamSetup(hParamBasic, &myParamSetup); if (status != CSL_SOK) { printf("Edma parameter entry setup is failed\n"); return; } /* Enable channel */ status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \ NULL); if (status != CSL_SOK) { printf("Edma channel enable command is failed\n"); return; } /* Initialize data */ for (loopIndex = 0; loopIndex < 41; loopIndex++) { srcBuff1[loopIndex] = loopIndex; dstBuff1[loopIndex] = 0; } for (loopIndex = 41; loopIndex < NOF_BYTES_XFR; loopIndex++) { srcBuff1[loopIndex] = loopIndex + 12; dstBuff1[loopIndex] = 0; } /* Manually trigger the channel */ status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL); if (status != CSL_SOK) { printf("Edma channel set command is failed\n"); return; } regionIntr.region = CSL_EDMA3_REGION_5; regionIntr.intr = 0; regionIntr.intrh = 0; do { /* Poll on interrupt bit 0 */ CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr); } while (!(regionIntr.intr & 0x1)); /* Clear interrupt bit 0 */ status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \ &regionIntr); if (status != CSL_SOK) { printf("Edma clear interrupt bit 0 command is failed\n"); return; } /* Check transfer */ if(Verify_Transfer(20, 12, 1, 40, 20, 0, 0, srcBuff1, dstBuff1,TRUE) == FALSE) { passStatus = 0; } if (passStatus == 1) printf ("<<EXAMPLE PASSED>>: Edma Sub Frame Transfer Passed\n"); else { printf ("<<EXAMPLE FAILED>>: Edma Sub Frame Buffer Transfer Failed\n"); return; } /* Close channel */ status = CSL_edma3ChannelClose(hChannel); if (status != CSL_SOK) { printf("Edma channel close failed\n"); return; } /* Close edma module */ status = CSL_edma3Close(hModule); if (status != CSL_SOK) { printf("Edma module close failed\n"); return; } printf ("=============================================================\n"); return; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example2/src/Intc_example2.c

<filename>DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example2/src/Intc_example2.c /* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ========================================================================== */ /** =========================================================================== * @file Intc_example2.c * * @path $(CSLPATH)\c64plus\example\intc * * @desc Example of INTC * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @n This example demonstrating usage of the combiners in the Interrupt * controller with the help of the the timers. This example, * 1. Intializes Intc module * 2. Opens a handle for the Timer 0 onto CPU vector 12 * 3. Plugs timer event handler and enables the event * 4. Intializes and opens the timer module * 5. Sets up and starts the timer * 6. Wait for interrupt genaration, (count to become 20) * 7. Disables the timer event * 8. Close the Intc module * 9. Opens the combined event on CPU vector 12 * 10. Opens the timer event on the combiner vector * CSL_INTC_VECTID_COMBINE * 11. Enables the combined and timer events * 12. Waits for interrupt genaration, (count to become 20) * 13. Disables the timer and combined events * 14. Enable the timer and combined events * 15. Wait for interrupt genaration, (count to become 20) * 16. Displays the message * * ============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Intc_example2.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================ * Revision History * =============== * 29-Jun-2004 <NAME> File Created. * * 04-Aug-2005 ds Changed to support timer CSL * 11-Nov-2005 ds Changed to add powersaver clock for timer * 16-Dec-2005 ds Updated documentation * 28-Mar-2006 ds Added code to clear all the evnts * ============================================================================ */ #include <csl_intc.h> #include <csl_intcAux.h> #include <csl_tmr.h> #include <cslr_dev.h> #include <stdio.h> /* Intc variables decalarations */ CSL_IntcObj intcTimerObj; CSL_IntcObj intcCombObj; CSL_IntcHandle hIntcTimer; CSL_IntcHandle hIntcComb; CSL_IntcGlobalEnableState state; CSL_IntcEventHandlerRecord EventRecord; CSL_IntcParam vectId; CSL_IntcContext context; CSL_IntcEventHandlerRecord Record[1]; CSL_IntcEventHandlerRecord EventHandler[30]; /* Function forwards */ void eventTimerHandler(void *handle); void intc_example (void); /* Global variable declarations */ volatile int intrCnt=0; /* * ============================================================================ * @func main * * @desc * This is the main routine, which invokes the example * ============================================================================ */ void main(void) { Bool timer0En; printf ("Running Interrupt Example\n"); /* Unlock the control register */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the Powersaver clock for TIMER 0 */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER0CTL, ENABLE); do { timer0En = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TIMER0STAT); } while (timer0En != TRUE); printf("Powersaver clock for TIMER 0 is enabled\n"); intc_example (); return; } /* * ============================================================================= * @func intc_example * * @arg None * * @desc * This is the example for combiners in the interrupt comtroller. * It implements following steps * 1. Initalizes the intc CSL required with proper ISR * 2. Intializes Timer. * 3. Enables the timer event * 4. Waits for timer interrupt generate. * 5. Disables the timer event * 6. Closes the Intc module * 7. Opens the combined event on CPU vector 12 * 8. Opens the timer event on the combiner vector * CSL_INTC_VECTID_COMBINE * 9. Enables the combined and timer events * 10. Waits for interrupt genaration, (count to become 20) * 11. Disables the timer and combined events * 12. Enables the timer and combined events * 13. Waits for interrupt genaration, (count to become 20) * 14. Closes the timer module * 15. Closes the Intc module * * @return * None * * @eg * intc_example (); * ============================================================================= */ void intc_example (void) { CSL_TmrHandle hTmr; CSL_TmrObj TmrObj; CSL_Status status, intStat; CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS; CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_CONT; volatile Uint32 delay; Uint32 LoadValue = 100; Uint32 evtClr; Uint32 idx; CSL_BitMask32 evtEn; printf ("Demonstrating usage of the combiners in the Intc\n"); /* Init the interrupt controller initializes the CPU vector table, * dispatcher */ context.numEvtEntries = 1; context.eventhandlerRecord = Record; status = CSL_intcInit(&context); if (status != CSL_SOK) { printf("Intc initialization failed\n"); return; } /* Enable NMIs */ status = CSL_intcGlobalNmiEnable(); if (status != CSL_SOK) { printf("Intc global NMI enable failed\n"); return; } /* Enable global interrupts */ intStat = CSL_intcGlobalEnable(&state); if (intStat != CSL_SOK) { printf ("Intc global enable failed\n"); return; } /* Opening a handle for the Timer 0 onto CPU vector 12 */ vectId = CSL_INTC_VECTID_12; hIntcTimer = CSL_intcOpen (&intcTimerObj, CSL_INTC_EVENTID_TINTLO0, \ &vectId , NULL); if (hIntcTimer == NULL) { printf("Intc open failed\n"); return; } /* Plug Event handler */ EventRecord.handler = &eventTimerHandler; EventRecord.arg = hIntcTimer; status = CSL_intcPlugEventHandler(hIntcTimer,&EventRecord); if (status != CSL_SOK) { printf("Intc plug event handler failed\n"); return; } /* Checking the CSL_INTC_CMD_EVTENABLE, by enabling timer event */ status = CSL_intcHwControl(hIntcTimer, CSL_INTC_CMD_EVTENABLE,NULL); if (status != CSL_SOK) { printf("Intc CSL_INTC_CMD_EVTENABLE command failed\n"); return; } /* Initialize and Setup timer CSL module */ CSL_tmrInit(NULL); hTmr = CSL_tmrOpen(&TmrObj, CSL_TMR_0, NULL, &status); /* Setup timer */ CSL_tmrHwSetup(hTmr, &hwSetup); /* Stop the timer */ status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL); /* set the timer mode to unchained dual mode */ hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED; /* Setup timer */ CSL_tmrHwSetup(hTmr, &hwSetup); /* Load the period register */ CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void *)&LoadValue); /* Start the timer with auto reload */ CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, (void *)&TimeCountMode); /* Wait for interrupt genaration, (count to become 20) */ while (intrCnt < 20); intrCnt = 0; /* Checking the CSL_INTC_CMD_EVTDISABLE, by disabling timer event */ status = CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDISABLE,NULL); if (status != CSL_SOK) { printf("Intc CSL_INTC_CMD_EVTDISABLE command failed\n"); return; } /* Wait for long time, to check timer stop */ for (delay =0 ; delay < 10000; delay++); /* Check for timer counter value */ if (intrCnt != 0) while(1); /* Failed */ /* Close Intc CSL */ CSL_intcClose(hIntcTimer); /* Do the same stuff with an event that is on a combined with others. * Opening a handle for the Combiner 0 onto CPU vector 12 */ /* Open the combined event on CPU vector 12 */ vectId = CSL_INTC_VECTID_12; hIntcComb = CSL_intcOpen(&intcCombObj,CSL_INTC_EVENTID_EVT2, &vectId,NULL); if (hIntcComb == NULL) { printf("Intc combined event open failed \n"); return; } vectId = CSL_INTC_VECTID_COMBINE; hIntcTimer = CSL_intcOpen (&intcTimerObj, CSL_INTC_EVENTID_TINTLO0, \ &vectId , NULL); if (hIntcTimer == NULL) { printf("Intc open failed\n"); return; } /* Plug event handler */ EventRecord.handler = &eventTimerHandler; EventRecord.arg = hIntcTimer; status = CSL_intcPlugEventHandler(hIntcTimer, &EventRecord); if (status != CSL_SOK) { printf("Intc plug event handler failed\n"); return; } /* Enabling the combined event */ evtEn = CSL_INTC_EVENTID_TINTLO0; status = CSL_intcHwControl(hIntcComb,CSL_INTC_CMD_EVTENABLE, &evtEn); if (status != CSL_SOK) { printf("Enabling the combined event failed\n"); return; } /* Enabling timer event */ status = CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTENABLE,NULL); if (status != CSL_SOK) { printf("Enabling timer event failed\n"); return; } /* Wait for interrupt genaration, (count to become 20) */ while (intrCnt < 20); intrCnt = 0; /* Checking the CSL_INTC_CMD_EVTDISABLE by disabling timer event */ status = CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDISABLE,NULL); if (status != CSL_SOK) { printf("Disabling the combined event failed\n"); return; } /* Wait for a long time */ for (delay =0 ; delay < 10000; delay++); /* Check for timer counter value */ if (intrCnt != 0) while(1); /* Failed */ /* Now doing the same test with the Combined Event disabled/enabled */ intrCnt = 0; CSL_intcHwControl(hIntcComb,CSL_INTC_CMD_EVTDISABLE,NULL); /* Enabling timer event */ CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTENABLE,NULL); /* Wait for a long time, to check timer stop */ for (delay =0 ; delay < 10000; delay++); /* Check for timer counter value */ if (intrCnt != 0) while(1); /* Failed */ /* Enable the combined event */ CSL_intcHwControl(hIntcComb,CSL_INTC_CMD_EVTENABLE,NULL); /* Wait for interrupt genaration, (count to become 20) */ while (intrCnt < 20); printf ("Intc Example Done \n"); /* Clear the all events */ for (idx = 0; idx < 4; idx++) { evtClr = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTFLAG[idx]; ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[idx] = evtClr; } /* Close Intc */ CSL_tmrClose (hTmr); CSL_intcClose(hIntcTimer); CSL_intcClose(hIntcComb); } /* * ============================================================================= * @func eventTimerHandler * * @desc * This is the interrupt event handler for timer * * @arg handle * Pointer to timer handle * * * @eg * eventTimerHandler (); * ============================================================================= */ void eventTimerHandler ( void *handle ) { intrCnt++; if (intrCnt == 20) CSL_intcHwControl(hIntcTimer,CSL_INTC_CMD_EVTDISABLE,NULL); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnInit.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_pwrdwnInit.c * * @path $(CSLPATH)\src\pwrdwn * * @desc File for functional layer of CSL API CSL_pwrdwnInit () * */ /* ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created * ============================================================================= */ #include <csl_pwrdwn.h> /** * ============================================================================ * @brief Initializes the module * * CSL_pwrdwnInit(..) initializes the PWRDWN module. * This function is idempotent -- calling it several times would * have the same effect as calling it the first time. * This function initializes the CSL data structures, and doesn't * touches the hardware. * * @b Arguments * @verbatim pContext Pointer to module-context. As PWRDWN doesn't have any context based information user is expected to pass NULL. @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n None * * Post Condition * @n The CSL for PWRDWN is initialized * * @b Modifies * @n None * * Note: As PWRDWN doesn't have any context based information, the function * just returns CSL_SOK. User is expected to pass NULL. * * @b Example * @verbatim ... if (CSL_SOK != CSL_pwrdwnInit(NULL)) { return; } @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_pwrdwnInit, ".text:csl_section:pwrdwn"); CSL_Status CSL_pwrdwnInit ( CSL_PwrdwnContext *pContext ) { /* If the module is already initialized, then error is * returned as init done(CSL_EINITDONE). If the user * needs to force init more than once, then set the * global Context pointer to NULL and invoke CSL_pwrdwnInit() */ return CSL_SOK; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/common/csl_pwrdwnGetBaseAddress.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * provided * ============================================================================ */ /** ============================================================================ * @file csl_pwrdwnGetBaseAddress.c * * @path $(CSLPATH)\src\common * * @desc CSL Implementation of CSL_pwrdwnGetBaseAddress * * Note: This function is open for re-implementing if the user wants to modify * the base address of the peripheral object to point to a different location * there by allow CSL initiated write/reads into peripheral MMR's go to an * alternate location. Please refer documentation for more details. * * @author <NAME>. */ /* ============================================================================= * Revision History * ================ * 22-sep-2005 PSK updated according to code review comments. * 09-Aug-2006 NG Added condition to check the invalid parameter * ============================================================================= */ #include <soc.h> #include <csl_pwrdwn.h> /** =========================================================================== * @n@b CSL_pwrdwnGetBaseAddress * * @b Description * @n This function gets the base address of the given pwrdwn * instance. * * @b Arguments * @verbatim pwrdwnNum Peripheral instance numberd pPwrdwnParam Module specific parameters pBaseAddress Pointer to base address structure containing base address details @endverbatim * * Return Value CSL_Status * @li CSL_SOK Successful on getting the base * address of pwrdwn * @li CSL_ESYS_FAIL pwrdwn instance is not * available. * @li CSL_ESYS_INVPARAMS Invalid parameter * * Pre Condition * @n None * * Post Condition * @n Base address structure is populated * * @b Modifies * @n 1. The status variable * * 2. Base address structure is modified. * * @b Example: @verbatim CSL_PwrdwnHandle hPwrdwn; CSL_PwrdwnBaseAddress baseAddress; CSL_PwrdwnParam params; CSL_pwrdwnGetBaseAddress(CSL_PWRDWN, &params, &baseAddress) ; @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_pwrdwnGetBaseAddress, ".text:csl_section:pwrdwn"); CSL_Status CSL_pwrdwnGetBaseAddress ( CSL_InstNum pwrdwnNum, CSL_PwrdwnParam *pPwrdwnParam, CSL_PwrdwnBaseAddress *pBaseAddress ) { CSL_Status status = CSL_SOK; if (pBaseAddress == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (pwrdwnNum) { case CSL_PWRDWN: pBaseAddress->regs = (CSL_PdcRegsOvly)CSL_PWRDWN_PDC_REGS; pBaseAddress->l2pwrdwnRegs = (CSL_L2pwrdwnRegsOvly)CSL_PWRDWN_L2_REGS; break; default: pBaseAddress->regs = (CSL_PdcRegsOvly)NULL; pBaseAddress->l2pwrdwnRegs = (CSL_L2pwrdwnRegsOvly)NULL; status = CSL_ESYS_FAIL; } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrHwSetup.c

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** =========================================================================== * @file csl_tmrHwSetup.c * * @brief File for functional layer of CSL API CSL_tmrHwSetup() * * @path $(CSLPATH)\src\timer * * @desc The CSL_tmrHwSetup() function definition & it's associated * functions * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 1-Sept-2004 HMM File Created. * 29-Jul-2005 PSK Updted changes acooriding to revised timer spec. The number * convention TIM12, TIM34 are changed to TIMLO and TIMHI. * 01-Feb-2006 ds Updated According to TCI6482/C6455 UserGuide * ============================================================================ */ #include <csl_tmr.h> #include <csl_tmrAux.h> /** ============================================================================ * @n@b CSL_tmrHwSetup * * @b Description * @n It configures the timer instance registers as per the values passed * in the hardware setup structure. * * @b Arguments * @verbatim htmr Handle to the timer instance setup Pointer to hardware setup structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * Pre Condition * @n None * * Post Condition * @n The specified instance will be setup according to value passed * * @b Modifies * @n Hardware registers for the specified instance * * @b Example * @verbatim CSL_status status; CSL_tmrHwSetup hwSetup; ... status = CSL_tmrHwSetup(htmr, &hwSetup); ... @endverbatim * =========================================================================== */ #pragma CODE_SECTION(CSL_tmrHwSetup, ".text:csl_section:tmr"); CSL_Status CSL_tmrHwSetup ( CSL_TmrHandle hTmr, CSL_TmrHwSetup *hwSetup ) { CSL_Status status = CSL_SOK ; if (hTmr == NULL) { status = CSL_ESYS_BADHANDLE; } else if (hwSetup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Load the Period register's */ hTmr->regs->PRDLO = hwSetup->tmrTimerPeriodLo; hTmr->regs->PRDHI = hwSetup->tmrTimerPeriodHi; /* Load the counter register's */ hTmr->regs->TIMLO = hwSetup->tmrTimerCounterLo; hTmr->regs->TIMHI = hwSetup->tmrTimerCounterHi; /* Setup the TCR register configurations */ CSL_FINS(hTmr->regs->TCR, TMR_TCR_PWID_HI, hwSetup->tmrPulseWidthHi); CSL_FINS(hTmr->regs->TCR, TMR_TCR_CP_HI, hwSetup->tmrClockPulseHi); CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVOUTP_HI, hwSetup->tmrInvOutpHi); /* Setup the TCR register configurations */ CSL_FINS(hTmr->regs->TCR, TMR_TCR_TIEN_LO, hwSetup->tmrIpGateLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_CLKSRC_LO, hwSetup->tmrClksrcLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_PWID_LO, hwSetup->tmrPulseWidthLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_CP_LO, hwSetup->tmrClockPulseLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVINP_LO, hwSetup->tmrInvInpLo); CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVOUTP_LO, hwSetup->tmrInvOutpLo); /* Setup the TGCR register configurations */ CSL_FINS(hTmr->regs->TGCR, TMR_TGCR_PSCHI, hwSetup->tmrPreScalarCounterHi); /* set the operation mode */ CSL_FINS(hTmr->regs->TGCR, TMR_TGCR_TIMMODE, hwSetup->tmrTimerMode); } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/srio/csl_srioGetHwStatus.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** =========================================================================== * @file csl_srioGetHwStatus.c * * @brief File for functional layer of CSL API CSL_srioGetHwStatus() * * @path $(CSLPATH)\srio\src * * @desc The CSL_srioGetHwStatus() function definition and it's associated * functions * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 24-Aug-2005 PSK File Created. * ============================================================================ */ #include <csl_srio.h> #include <csl_srioAux.h> /** =========================================================================== * @n@b CSL_srioGetHwStatus * * @b Description * @n This function is used to get the value of various parameters of the * SRIO instance. The value returned depends on the query passed. * * @b Arguments * @verbatim hSrio Handle to the SRIO instance query Query to be performed response Pointer to buffer to return the data requested by the query passed @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Successful completion of the * query * * @li CSL_ESYS_BADHANDLE - Invalid handle * * @li CSL_ESYS_INVQUERY - Query command not supported * * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n None * * Post Condition * Data requested by the query is returned through the variable * "response" * * @b Modifies * @n The input arguement "response" is modified * * @b Example * @verbatim CSL_Status status; CSL_SrioHandle hSrio; CSL_SrioPidNumber response; ... Status=CSL_srioGetHwStatus(hSrio, CSL_SRIO_QUERY_PID_NUMBER, &response); ... @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_srioGetHwStatus, ".text:csl_section:srio"); CSL_Status CSL_srioGetHwStatus ( CSL_SrioHandle hSrio, CSL_SrioHwStatusQuery query, void *response ) { CSL_Status status = CSL_SOK; if (hSrio == NULL) { status = CSL_ESYS_BADHANDLE; } else if (response == NULL) { status = CSL_ESYS_INVPARAMS; } else { switch (query) { /* queries SRIO Peripheral Identification number */ case CSL_SRIO_QUERY_PID_NUMBER: CSL_srioGetPid(hSrio, (CSL_SrioPidNumber *)response); break; /* Gets global enable status */ case CSL_SRIO_QUERY_GBL_EN_STAT: CSL_srioGetGblEnStat(hSrio, (Uint32 *)response); break; /* Gets block enable status for all the blocks */ case CSL_SRIO_QUERY_BLK_EN_STAT: CSL_srioGetBlkEnStat(hSrio, (CSL_SrioBlkEn *)response); break; /* Get doorbell interrupts status */ case CSL_SRIO_QUERY_DOORBELL_INTR_STAT: CSL_srioGetDoorbellIntrStat(hSrio, (CSL_SrioPortData *)response); break; /* Get the LSU interrupts status */ case CSL_SRIO_QUERY_LSU_INTR_STAT: CSL_srioGetLsuIntrStat(hSrio, (Uint32 *)response); break; /* Gets Error, Reset, and Special Event interrupts status */ case CSL_SRIO_QUERY_ERR_RST_INTR_STAT: CSL_srioGetErrRstIntrStat(hSrio, (Uint32 *)response); break; /* Get status of LSU interrupts decode for DST 0 */ case CSL_SRIO_QUERY_LSU_INTR_DECODE_STAT: CSL_srioGetLsuIntrDecodeStat(hSrio, (Uint32 *)response); break; /* Get Error, Reset, and Special Event interrupts decode * status for DST 0 */ case CSL_SRIO_QUERY_ERR_INTR_DECODE_STAT: CSL_srioGetErrIntrDecodeStat(hSrio, (Uint32 *)response); break; /* Gets the status of the pending command of LSU * registers for a particular port */ case CSL_SRIO_QUERY_LSU_COMP_CODE_STAT: CSL_srioLsuCompCodeStat(hSrio, (CSL_SrioLsuCompStat *)response); break; /* Gets status of the command registers of LSU module * for a particular port */ case CSL_SRIO_QUERY_LSU_BSY_STAT: CSL_srioLsuBsyStat(hSrio, (CSL_SrioPortData *)response); break; /* Gets the type of device (Vendor specific) */ case CSL_SRIO_QUERY_DEV_ID_INFO: CSL_srioGetDevIdInfo(hSrio, (CSL_SrioDevInfo *)response); break; /* Gets vendor specific assembly information */ case CSL_SRIO_QUERY_ASSY_ID_INFO: CSL_srioGetAssyIdInfo(hSrio, (CSL_SrioAssyInfo *)response); break; /* Gets processing element features */ case CSL_SRIO_QUERY_PE_FEATURE: CSL_srioGetPeFeature(hSrio, (Uint32 *)response); break; /* Get source operations CAR status */ case CSL_SRIO_QUERY_SRC_OPERN_SUPPORT: CSL_srioGetSrcOpernSuppStat(hSrio, (Uint32 *)response); break; /* Get destination operations CAR status */ case CSL_SRIO_QUERY_DST_OPERN_SUPPORT: CSL_srioGetDstOpernSuppStat(hSrio, (Uint32 *)response); break; /* Get local configuration space base addresses */ case CSL_SRIO_QUERY_LCL_CFG_BAR: CSL_srioGetLclCfgBar(hSrio, (CSL_SrioLongAddress *)response); break; /* Get status of SP_LM_RESP register fields */ case CSL_SRIO_QUERY_SP_LM_RESP_STAT: CSL_srioGetSpLmRespStat(hSrio, (CSL_SrioPortData *)response); break; /* Get status of SP_ACKID_STAT register fields */ case CSL_SRIO_QUERY_SP_ACKID_STAT: CSL_srioGetSpAckIdStat(hSrio, (CSL_SrioPortData *)response); break; /* Get status of SP_ERR_STAT register fields */ case CSL_SRIO_QUERY_SP_ERR_STAT: CSL_srioGetSpErrStat(hSrio, (CSL_SrioPortData *)response); break; /* Gets SP_CTL register status fields */ case CSL_SRIO_QUERY_SP_CTL: CSL_srioGetSpCtlStat(hSrio, (CSL_SrioPortData *)response); break; /* Get the status of logical/transport layer errors */ case CSL_SRIO_QUERY_LGCL_TRNS_ERR_STAT: CSL_SrioGetLgclTrnsErrStat(hSrio, (Uint32 *)response); break; /* Get captured error info of logical/transport layer */ case CSL_SRIO_QUERY_LGCL_TRNS_ERR_CAPT: CSL_srioGetLgclTransErrCapt(hSrio, (CSL_SrioLogTrErrInfo *)response); break; /* Get status of port error detect CSR fields */ case CSL_SRIO_QUERY_SP_ERR_DET_STAT: CSL_srioGetSpErrDetStat(hSrio, (CSL_SrioPortData *)response); break; /* Get the port error captured information */ case CSL_SRIO_QUERY_PORT_ERR_CAPT: CSL_srioGetPortErrCapt(hSrio, (CSL_SrioPortErrCapt *)response); break; /* Get port control independent register fields status */ case CSL_SRIO_QUERY_SP_CTL_INDEP: CSL_srioGetSpCtlIndepStat(hSrio, (CSL_SrioPortData *)response); break; /* Get the port write capture information */ case CSL_SRIO_QUERY_PW_CAPTURE: CSL_srioGetPwCapt(hSrio, (CSL_SrioPortWriteCapt *)response); break; /* Reads the count of the number of transmission * errors that have occurred */ case CSL_SRIO_QUERY_ERR_RATE_CNTR_READ: CSL_srioErrRateCounterRead(hSrio, (CSL_SrioPortData *)response); break; /* Reads the peak value of the error rate counter */ case CSL_SRIO_QUERY_PEAK_ERR_RATE_READ: CSL_srioErrRatePeakRead(hSrio, (CSL_SrioPortData *)response); break; default: status = CSL_ESYS_INVQUERY; break; } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotOpen.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_memprotOpen.c * * @path $(CSLPATH)\src\memprot * * @desc File for functional layer of CSL API CSL_memprotOpen () * */ /* ============================================================================= * Revision History * =============== * 16-Nov-2005 ds updated the documentation * ============================================================================= */ #include <csl_memprot.h> /** =========================================================================== * @n@b CSL_memprotOpen * * @b Description * @n This function populates the peripheral data object for the instance * and returns a handle to the instance. * The open call sets up the data structures for the particular instance * of MEMPROT device.The device can be re-opened anytime after it has been * normally closed, if so required. The handle returned by this call is * input as an essential argument for rest of the APIs described * for this module. * * @b Arguments * @verbatim pMemprotObj Pointer to the MEMPROT instance object memprotNum Instance of the MEMPROT to be opened pMemprotParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * Return Value CSL_MemprotHandle * @n Valid MEMPROT instance handle will be returned if status value is equal to CSL_SOK. * * Pre Condition * Memory protection must be successfully initialized via @a CSL_memprotInit() * before calling this function. Memory for the @a CSL_MemprotObj must be * allocated outside this call. This object must be retained while usage of * this module.Depending on the module opened some inherant constraints need * to be kept in mind. When a handle for the Config block is opened the only * operation possible is a query for the fault Status. No other control * command/ query/ setup must be used. * When a handle for L1D/L1P is opened then too constraints wrt the number of * Memory pages must be kept in mind. * * Post Condition * @n 1. MEMPROT object structure is populated * @n 2. The status is returned in the status variable. If status * returned is * @li CSL_SOK Valid MEMPORT handle is returned * @li CSL_ESYS_FAIL The MEMPORT instance is invalid * @li CSL_ESYS_INVPARAMS Invalid parameter * * @b Modifies * @n 1. The status variable * @n 2. MEMPROT object structure * * @b Example * @verbatim CSL_MemprotObj mpL2Obj; CSL_MemprotHandle hmpL2; CSL_Status status; // Initializing the module CSL_memprotInit(NULL); // Opening the Handle for the L2 hmpL2 = CSL_memprotOpen(&mpL2Obj, CSL_MEMPROT_L2, NULL, &status); @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CSL_memprotOpen, ".text:csl_section:memprot"); CSL_MemprotHandle CSL_memprotOpen ( CSL_MemprotObj *pMemprotObj, CSL_InstNum memprotNum, CSL_MemprotParam *pMemprotParam, CSL_Status *pStatus ) { CSL_MemprotHandle hMemprot = (CSL_MemprotHandle)NULL; CSL_MemprotBaseAddress baseAddress; if (pStatus == NULL) { /* do nothing : already the module is initialized to NULL */ } else if (pMemprotObj == NULL) { *pStatus = CSL_ESYS_INVPARAMS; } else { *pStatus = CSL_memprotGetBaseAddress(memprotNum, pMemprotParam, &baseAddress); if (*pStatus == CSL_SOK) { pMemprotObj->regs = baseAddress.regs; pMemprotObj->modNum = (CSL_InstNum)memprotNum; hMemprot = (CSL_MemprotHandle)pMemprotObj; } else { pMemprotObj->regs = (CSL_MemprotRegsOvly)NULL; pMemprotObj->modNum = (CSL_InstNum)-1; } } return (hMemprot); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/cache/csl_cacheEnable.c

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_cacheEnable.c * * @path $(CSLPATH)\src\cache * * @desc File for functional layer of CSL API CACHE_enableCaching () * */ /* ============================================================================= * Revision History * =============== * 23-Mar-2004 <NAME> File Created * * ============================================================================= */ #include <csl_cache.h> #include <_csl_cache.h> /** ============================================================================ * @n@b CACHE_enableCaching * * @b Description * @n Enables caching for the specified memory range. * * @b Arguments * @verbatim mar EMIF range @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n Caching for the specified memory range is enabled * * @b Modifies * @n MAR register * * @b Example * @verbatim ... CACHE_enableCaching (CACHE_EMIFB_CE00); ... @endverbatim * ============================================================================ */ #pragma CODE_SECTION (CACHE_enableCaching, ".text:csl_section:cache"); void CACHE_enableCaching ( CE_MAR mar ) { ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->MAR[mar] = 1; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioClose.c

/* ========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * provided * ========================================================================== */ /** =========================================================================== * @file csl_gpioClose.c * * @path $(CSLPATH)\src\gpio * * @desc File for functional layer of CSL API CSL_gpioClose() * ============================================================================ */ /* ============================================================================ * Revision History * =============== * 10-Jun_2004 PGR file created * 07-Sep-2004 Nsr Updated function and documentation for CSL_gpioclose. * - Removed the include file, csl_resource.h. * 11-Oct-2004 Nsr renamed the local variable "st" as "status" * 28-Jul-2005 PSK Updated CSL source to support only ONE BANK. * bank "index" is removed. * 06-Mar-2006 ds Updated the documentation * ============================================================================ */ #include <csl_gpio.h> /** ============================================================================ * @n@b CSL_gpioClose * * @b Description * @n This function closes the specified instance of GPIO. * * @b Arguments * @verbatim hGpio Handle to the GPIO instance @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Close successful * @li CSL_ESYS_BADHANDLE - Invalid handle * * Pre Condition * @n Both CSL_gpioInit() and CSL_gpioOpen() must be called successfully in * order before calling CSL_gpioClose(). * * Post Condition * @n The GPIO CSL APIs can not be called until the GPIO CSL is reopened * again using CSL_gpioOpen(). * * @b Modifies * @n Obj structure values * * @b Example * @verbatim CSL_GpioHandle hGpio; CSL_Status status; ... status = CSL_gpioClose(hGpio); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_gpioClose, ".text:csl_section:gpio"); CSL_Status CSL_gpioClose ( CSL_GpioHandle hGpio ) { /* Indicate in the CSL global hGpio structure that the peripheral * has been unreserved */ CSL_Status status = CSL_SOK; if (hGpio != NULL) { hGpio->regs = (CSL_GpioRegsOvly)NULL; hGpio->gpioNum = (CSL_InstNum)-1; } else { status = CSL_ESYS_BADHANDLE; } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3HwChannelSetup.c

<filename>DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3HwChannelSetup.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_edma3HwChannelSetup.c * * @path $(CSLPATH)\src\edma * * @desc File for functional layer of CSL API CSL_edma3HwChannelSetup() * */ /* ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= */ #include <csl_edma3.h> #include <csl_edma3Aux.h> /** ============================================================================ * @n@b CSL_edma3HwChannelSetupParam * * @b Description * @n Sets up the channel to parameter entry mapping.This writes the * DCHMAP[]/QCHMAP appropriately. * * @b Arguments * @verbatim hEdma Channel Handle paramNum Parameter Entry @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Channel setup param successful * @li CSL_ESYS_BADHANDLE - The handle passed is * invalid * @li CSL_ESYS_INVPARAMS - The paameters passed is invalid * * Pre Condition * @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be * called successfully in that order before this API can be invoked * * Post Condition * @n Channel to parameter entry is configured * * @b Modifies * @n Edma registers * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; Uint16 paramNum; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); // Set the parameter entry number to channel paramNum = 100; CSL_edma3HwChannelSetupParam(hChannel,paramNum); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3HwChannelSetupParam, ".text:csl_section:edma3"); CSL_Status CSL_edma3HwChannelSetupParam ( CSL_Edma3ChannelHandle hEdma, Uint16 paramNum ) { CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else if (paramNum >= CSL_EDMA3_NUM_PARAMSETS) { status = CSL_ESYS_INVPARAMS; } else { /* CSL_edma3ChannelSetEvtQue(hCh,setup->que); */ if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH) { #if CSL_EDMA3_CHMAPEXIST CSL_FINS(hEdma->regs->DCHMAP[hEdma->chaNum], EDMA3CC_DCHMAP_PAENTRY, \ paramNum); #endif } else CSL_FINS(hEdma->regs->QCHMAP[hEdma->chaNum-CSL_EDMA3_NUM_DMACH], \ EDMA3CC_QCHMAP_PAENTRY,paramNum); } return (status); } /** ============================================================================ * @n@b CSL_edma3HwChannelSetupTriggerWord * * @b Description * @n Programs the QDMA channel triggerword.This writes the QCHMAP[] * appropriately. * * @b Arguments * @verbatim hEdma Channel Handle triggerWord Trigger Word @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Channel setup triggerword * successful * @li CSL_ESYS_BADHANDLE - The handle passed is * invalid * @li CSL_ESYS_INVPARAMS - The paameters passed is invalid * * Pre Condition * @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be * called successfully in that order before this API can be invoked * * Post Condition * @n Sets up the QDMA Channel to trigger Word * * @b Modifies * @n Edma registers * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_QCHA_0; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Sets up the QDMA Channel 0 trigger Word to the 3rd trigger word. CSL_edma3HwChannelSetupTriggerWord(hChannel,3); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3HwChannelSetupTriggerWord, ".text:csl_section:edma3"); CSL_Status CSL_edma3HwChannelSetupTriggerWord ( CSL_Edma3ChannelHandle hEdma, Uint8 triggerWord ) { CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else if (triggerWord > 7) { status = CSL_ESYS_INVPARAMS; } else if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH) { /* CSL_edma3ChannelSetEvtQue(hEdma,setup->que); */ status = CSL_ESYS_INVPARAMS; } else CSL_FINS(hEdma->regs->QCHMAP[hEdma->chaNum-CSL_EDMA3_NUM_DMACH], \ EDMA3CC_QCHMAP_TRWORD,triggerWord); return (status); } /** ============================================================================ * @n@b CSL_edma3HwChannelSetupQue * * @b Description * @n Programs the Channel to Queue mapping.This writes the DMAQNUM/QDAMQNUM * appropriately. * * @b Arguments * @verbatim hEdma Channel Handle evtQue Queue Setup @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Channel setup queue * successful * @li CSL_ESYS_BADHANDLE - The handle passed is * invalid * * Pre Condition * @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be * called successfully in that order before this API can be invoked * * Post Condition * @n Sets up the channel to Queue mapping * * @b Modifies * @n Edma registers * * @b Example * @verbatim CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Set up the channel to que mapping CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_3); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_edma3HwChannelSetupQue, ".text:csl_section:edma3"); CSL_Status CSL_edma3HwChannelSetupQue ( CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que evtQue ) { Uint32 _cha; Uint32 _qNumIndex; Uint32 _qchMap; CSL_Status status = CSL_SOK; if (hEdma == NULL) { status = CSL_ESYS_BADHANDLE; } else { if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH) { /* Extracting the Channel Number in case of QDMA */ _cha = hEdma->chaNum - CSL_EDMA3_NUM_DMACH; /* Channel to Event Queue mapping */ CSL_FINSR(hEdma->regs->QDMAQNUM,_cha * 4 + 2,_cha * 4,evtQue); } else { /* Finding out the relevant DMAQNUM register and the correct bit positions to write into */ _qNumIndex = hEdma->chaNum >> 3; _qchMap = hEdma->chaNum - (_qNumIndex * 8); CSL_FINSR(hEdma->regs->DMAQNUM[_qNumIndex], _qchMap * 4 + 2, \ _qchMap * 4, evtQue); } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/tcp2/tcp2_shared_mode/src/Tcp2_shared_mode_example.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file Tcp2_shared_mode_example.c * * @path $(CSLPATH)\example\tcp2\tcp2_shared_mode\src * * @desc Example file for the TCP2 CSL * ============================================================================ * @n Target Platform: EVM * ============================================================================ * * The example demonstrates the usage of the TCP2 CSL API for decoding the * input data in shared mode. * * ============================================================================ * @n Description * This is an example for the usage of the TCP2 CSL API in the shared * mode. * * @b Procedure * 1 - Sets up the TCP2 input configuration parameters * 2 - Configures the EDMA to transfer the input paramters, * systematics and parity data, apriori data on successful TCPXEVT * 3 - Configures the EDMA for the extrinsics transfer on TCPREVT. * 4 - Starts the turbo coprocessor and waits for the completion of the * processing * 5 - After the state indicates the extrinsics are read, the example exits * 6 - This demonstrates the usage only for the first sub frame of * a frame length = 51200 *============================================================================= * * The steps to run this example are as follows: * 1 - Open the Tcp2_shared_mode_example.pjt in the CCS studio * 2 - Build the example * 3 - Execute the .out file * */ /* ============================================================================= * Revision History * =============== * 23-May-2005 sd File Created. * 05-Aug-2005 sd Changes for EDMA CSL * 17-Dec-2005 sd Added clearing the EDMA error registers before enabling the * channel. * 05-Feb-2006 sd Changes according to the spec changes * 21-Feb-2006 ds Added clearing the EDMA error registers at end of the * example * 22-Mar-2006 ds Removed "mode" bit from TCP2_BaseParams structure * ============================================================================= */ #include <csl_tcp2.h> #include <csl_tcp2Aux.h> #include <csl_edma3.h> #include <stdio.h> #include <cslr_dev.h> /* defines */ /* To load the interleaver RAM*/ #define INTERLEAVER_LOAD_FLAG FALSE /* Maximum iterations of the TCP */ #define MAX_TCP_ITERATIONS 8 /* Maximum iterations of the TCP */ #define MIN_TCP_ITERATIONS 1 /* Output paramters read flag */ #define OUT_PARAM_READ_FLAG FALSE /* prolog size */ #define PROLOG_SIZE 32 /* CRC Polynomial */ #define CRC_POLY 0 /* CRC length */ #define CRC_LEN 0 /* EDMA PARAM size */ #define EDMA_PARAM_SIZE 0x20 /* Frame length of the TCP input data */ Uint32 frameLength = 51200; /* externs */ extern TCP2_TailData tailData []; extern TCP2_UserData sysParData []; extern TCP2_ExtrinsicData aprioriData []; extern TCP2_ExtrinsicData extrinsicData []; /* globals */ Uint8 extrinsicBuffer1 [51200]; Uint8 extrinsicBuffer2 [51200]; /* TCP input configuration structure */ TCP2_ConfigIc configIc [3]; /* EDMA CSL configuration structures */ CSL_Edma3Context context; CSL_Edma3ChannelObj ChObj, ChObj1; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelHandle hChannel, hChannel1; CSL_Edma3ParamHandle hParam[24]; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3ChannelAttr chParam, chParam1; CSL_Edma3ChannelErr chErrClear; /* EDMA PARAM indexes */ Uint32 txParamIndex = 0; Uint32 rxParamIndex = 20; /* forward declarations */ Uint16 tcp2_configEdma ( Uint32* inputRegs, Uint8* aprioriData, Uint8* extrinsicBuffer, Uint32 txDataLen, Uint32 aprioriTxlen, Uint32 rxDataLen, Bool endConfig ); /* * ============================================================================ * @func main () * * @desc * Example to show the usage of the TCP2 CSL API for shared mode * processing * * @b Arguments * @verbatim None @endverbatim * * Return Value None * * @b Procedure * 1 - Sets up the TCP2 input configuration parameters * 2 - Configures the EDMA to transfer the input paramters, * systematics and parity data, apriori data on successful TCPXEVT * 3 - Configures the EDMA for the extrinsics transfer on TCPREVT. * 4 - Starts the turbo coprocessor and waits for the completion of the * processing * 5 - After the state indicates the extrinsics are read, the example exits * * ============================================================================ */ void main ( void ) { TCP2_BaseParams configBase; /* base params to configure TCP2 */ TCP2_Params configParams [2]; /* holds all the input configuration parameters for TCP*/ TCP2_Params *tempParams; Uint32 frameLen = frameLength; Uint32 cnt; Uint32 txDataLen = 0, rxDataLen = 0, aprioriTxLen = 0; Uint32 extIndex, aprIndex; /* Enable the TCP2 in power saver */ CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TCPCTL, ENABLE); while (CSL_DEV_PERSTAT0_TCPSTAT_ENABLE != CSL_FEXT (((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TCPSTAT)); /* setup the base params */ configBase.frameLen = frameLen; configBase.inputSign = TCP2_INPUT_SIGN_POSITIVE; configBase.intFlag = INTERLEAVER_LOAD_FLAG; configBase.maxIter = MAX_TCP_ITERATIONS; configBase.maxStarEn = FALSE; configBase.standard = TCP2_STANDARD_3GPP; configBase.crcLen = 0; /* Disable CRC */ configBase.crcPoly = 0; /* not used */ configBase.minIter = MIN_TCP_ITERATIONS; configBase.numCrcPass = 0; /* default value */ configBase.outParmFlag = OUT_PARAM_READ_FLAG; configBase.outputOrder = TCP2_OUT_ORDER_0_31; configBase.prologRedEn = FALSE; configBase.prologSize = PROLOG_SIZE; configBase.rate = TCP2_RATE_1_3; configBase.snr = 0; /* disable SNR threshold checking */ configBase.map = TCP2_MAP_MAP1; /* assign the extrinsic scaling factors */ for (cnt = 0; cnt < 16; cnt++) configBase.extrScaling [cnt] = 0; /* setup the TCP configuration registers parmeters */ TCP2_genParams (&configBase, configParams); /* generate the configuration register values */ /* For the first sub frame */ TCP2_genIc (&configParams [0], tailData, &configIc [0]); /* for the middle sub frame */ tempParams = &configParams [0]; tempParams->mode = TCP2_MIDDLE_SF; TCP2_genIc (tempParams, tailData, &configIc [1]); /* For the last sub frame */ TCP2_genIc (&configParams [1], tailData, &configIc [2]); /* configure the Endian register */ TCP2_setInterEndian (CSL_TCP2_TCPEND_ENDIAN_INTR_32BITS); TCP2_setExtEndian (CSL_TCP2_TCPEND_ENDIAN_EXTR_32BITS); /* configure the sleep modes */ TCP2_setSlpzvdd (CSL_TCP2_TCPEND_SLPZVDD_EN_ENABLE); TCP2_setSlpzvss (CSL_TCP2_TCPEND_SLPZVSS_EN_ENABLE); /* Configure EDMA to write/read TCP data on app. events */ /* MAP 1 configuration */ /* set the index for extrinsics */ extIndex = 0; aprIndex = 0; /* for the first sub frame */ tempParams = &configParams [0]; txDataLen = tempParams->frameLen + tempParams->prologSize; if ((txDataLen % 2) !=0) txDataLen++; aprioriTxLen = tempParams->frameLen + tempParams->prologSize; if ((aprioriTxLen % 2) !=0) aprioriTxLen++; rxDataLen = tempParams->frameLen; if ((rxDataLen % 2) !=0) rxDataLen++; tcp2_configEdma ((Uint32*)&configIc [0], &aprioriData [aprIndex], &extrinsicBuffer1 [extIndex], txDataLen, aprioriTxLen, rxDataLen, TRUE); /* Enable Channel */ CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL); /* Enable Channel */ CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL); /* reset and start the TCP */ TCP2_reset (); TCP2_start (); /* wait for the status to indicate extrinsics to be read */ while (0x0B != TCP2_statTcpState ()); printf ("Reading the extrinsics \n"); /* wait for the status to indicate the extrinsics read complete */ while (0x01 == TCP2_statWaitExt ()); printf ("Reading the extrinsics complete \n"); /* Disable cahnnels and clear the EDMA event registers */ CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL); CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL); /* clear the EDMA error registers */ chErrClear.missed = TRUE; chErrClear.secEvt = TRUE; CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear); CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR, &chErrClear); printf ("Example complete \n"); } /* * ============================================================================= * @func tcp2_configEdma * @desc * Configures EDMA channels 30 and 31. * For channel 31 there are 3 param entries(0, 1 and 2) which are linked. * Link 0 transfers the TCP2 input configuration register values. * Link 1 transfer the systematics and parity data. * Link 2 transfers the apriori data * For channel 30 there is 1 param entry (3). * Link 3 transfers the extrinsic data. * * @expected result * * * @eg * tcp2_configEdma(); * ============================================================================= */ Uint16 tcp2_configEdma ( Uint32 *inputRegs, Uint8 *aprioriData, Uint8 *extrinsicBuffer, Uint32 txDataLen, Uint32 aprioriTxlen, Uint32 rxDataLen, Bool endConfig ) { volatile Uint16 count; CSL_Status chStatus, chStatus1; CSL_edma3Init(&context); CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&chStatus); /* Channel Configuration for TCPXEVT event */ /* Channel Open */ if (txParamIndex == 0){ /* open it only the first time */ chParam.regionNum = CSL_EDMA3_REGION_GLOBAL; chParam.chaNum = CSL_EDMA3_CHA_TCP2XEVT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chParam, &chStatus); if ((chStatus != CSL_SOK) || (hChannel == NULL)) { printf("Error in EDMA channel open function\n"); return 0; } /* Channel Setup for PaRAM entry 0 */ if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel, txParamIndex )){ printf("Error is EDMA channel setup for channel #31\n"); return 0; } if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel, CSL_EDMA3_QUE_0)) { printf("Error is EDMA channel setup for channel #31\n"); return 0; } } /* Setup EDMA to transmit the input configuration parameters */ hParam[txParamIndex] = CSL_edma3GetParamHandle (hChannel, txParamIndex, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)inputRegs; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, 0); myParamSetup.dstAddr = (Uint32)CSL_TCP2_CFG_REGS; myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE( ((txParamIndex+1) * EDMA_PARAM_SIZE), 0); /* offset to the next PARAM entry */ myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(sizeof (TCP2_ConfigIc), 1); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[txParamIndex], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #0\n"); return 0; } /* Setup link to transmit systematics and parity data using param */ txParamIndex++; hParam[txParamIndex] = CSL_edma3GetParamHandle (hChannel, txParamIndex, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_AB, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)sysParData; myParamSetup.dstAddr = (Uint32)CSL_TCP2_X0_MEM; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(8, 8); /* length of the systematic and parity data to be transferred */ myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(8, (txDataLen/2)); //txDataLen /* linking to the offset to the next PARAM entry */ myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE( ((txParamIndex+1) * EDMA_PARAM_SIZE), 0); myParamSetup.cCnt = 1; myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, 0); if (CSL_SOK != CSL_edma3ParamSetup (hParam[txParamIndex], &myParamSetup)) { printf("Error in EDMA PARAM setup for entry #1\n"); return 0; } txParamIndex++; /* Setup link to transmit apriori data using param */ hParam[txParamIndex] = CSL_edma3GetParamHandle (hChannel, txParamIndex, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)aprioriData; myParamSetup.dstAddr = (Uint32)CSL_TCP2_W1_MEM; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, 0); /* length of the apriori data to be transferred */ myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(aprioriTxlen, 1); myParamSetup.cCnt = 1; if (!endConfig) { myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( ((txParamIndex+1) * EDMA_PARAM_SIZE), 0); } else { myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( CSL_EDMA3_LINK_NULL, 0); } if (CSL_SOK != CSL_edma3ParamSetup (hParam[txParamIndex], &myParamSetup)) { /* * link this with the next transfer to be configured unless this * is the last iteration */ printf("Error in EDMA PARAM setup for entry #2\n"); return 0; } /* increment to the next PARAM index */ txParamIndex++; /* Receive Channel Open */ if (rxParamIndex == 20) { /* open the channel only once */ chParam1.regionNum = CSL_EDMA3_REGION_GLOBAL; chParam1.chaNum = CSL_EDMA3_CHA_TCP2REVT; hChannel1 = CSL_edma3ChannelOpen (&ChObj1, CSL_EDMA3, &chParam1, &chStatus1); if ((chStatus1 != CSL_SOK) | (hChannel1 == NULL)) { printf("Error in EDMA channel open function\n"); return 0; } /* Channel Setup */ if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel1, rxParamIndex)) { printf("Error is EDMA channel setup for channel #30\n"); return 0; } if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel1, CSL_EDMA3_QUE_0)) { printf("Error is EDMA channel setup for channel #30\n"); return 0; } } /* Channel Setup */ /* configure param entry 3 to read the extrinsics data */ hParam[rxParamIndex] = CSL_edma3GetParamHandle (hChannel1, rxParamIndex, &chStatus); myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0, CSL_EDMA3_TCC_NORMAL, CSL_EDMA3_FIFOWIDTH_NONE, FALSE,CSL_EDMA3_SYNC_A, CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)CSL_TCP2_W0_MEM; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (rxDataLen, 1); /* number of bytes of apriori data to be read */ myParamSetup.dstAddr = (Uint32)extrinsicBuffer; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE (0, 0); /* * link this with the next transfer to be configured unless this * is the last iteration */ if (!endConfig) { myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( ((rxParamIndex+1) * EDMA_PARAM_SIZE), 0); } else { myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ( CSL_EDMA3_LINK_NULL, 0); } myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE (0, 0); myParamSetup.cCnt = 1; if (CSL_SOK != CSL_edma3ParamSetup (hParam[rxParamIndex], &myParamSetup)) { printf("Error in EDMA paRam setup for entry #3\n"); return 0; } /* increment to the next PARAM index */ rxParamIndex++; return 1; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_version.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_version.h * * @path $(CSLPATH)\inc * * @desc This file contains the version number of different chips * */ /* ============================================================================= * Revision History * =============== * 25-Aug-2006 NG Updated for new chip c6454 for the release v03_00_10_02 * ============================================================================= */ #ifndef _CSL_VERSION_H_ #define _CSL_VERSION_H_ #ifdef __cplusplus extern "C" { #endif #include <tistdtypes.h> /* 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) */ #define CSL_VERSION_ID (0x03001002) #define CSL_VERSION_STR "@(#) CSL Revision: 3.00.10.02;" #ifdef c6482 #define CSL_CHIP_ID (0x6482) #define CSL_CHIP_STR "TMS320C6482 PG 1.0 (C6482)" #endif #ifdef c6455 #define CSL_CHIP_ID (0x6455) #define CSL_CHIP_STR "TMS320C6455 PG 1.0 (C6455)" #endif #ifdef c6454 #define CSL_CHIP_ID (0x6454) #define CSL_CHIP_STR "TMS320C6454 PG 1.0 (C6454)" #endif #ifdef c64xplus_intc #define CSL_CHIP_ID (0x64A) #define CSL_CHIP_STR "C64X PLUS" #endif /** @brief Retrieves the version ID */ Uint32 CSL_versionGetID ( void ); /** @brief Retrieves the version string */ const char * CSL_versionGetStr ( void ); #ifdef __cplusplus } #endif #endif /* _CSL_VERSION_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/edma/qdma_idma_link_xfer_gbl_reg/src/Qdma_idma_link_xfer_gbl_reg.c

/* =========================================================================== * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ========================================================================== */ /** =========================================================================== * * @file Qdma_link_xfer_gbl_reg.c * * @path $(CSLPATH)\example\edma\qdma_idma_link_xfer_gbl_reg\src * * @desc Example of EDMA * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @n This is an example of the CSL EDMA usage for the QDMA Channel * Initialization for a linked transfer. * This example do the following operations * 1. Initializes and Opens the edma module * 2. Sets up the Module and gets the module setup values * 3. Opens qdma channel0 in the global region. * 4. Maps channel to parameter entry 67 * 5. Gets param handle for 64, 65, 66 * 6. Links the param sets * - Parameter set 67 is linked 66 * - Parameter set 66 is linked 65 * - Parameter set 65 is linked 64 * 7. Initializes the parameter entries using IDMA and * 8. IDMA trigger the transfer * 9. Polls for IPR bit and clears the bit * 10. Compares the transfered data * 11. Displays the result based on step 10 * Note:- Parameter Set 64 is marked as static * * ============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Qdma_idma_link_xfer_gbl_reg.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================ * Revision History * =============== * 08-July-2005 <NAME> File Created. * 16-Dec-2005 ds Updated documentation * 27-Mar-2006 ds Added disable edma chhnel command * ============================================================================ */ #include <stdio.h> #include <csl_edma3.h> #include <soc.h> #include <csl_idma.h> /* Globals */ Uint8 srcBuff0[64]; Uint8 srcBuff1[64]; Uint8 srcBuff2[64]; Uint8 srcBuff3[64]; Uint8 dstBuff0[64]; Uint8 dstBuff1[64]; Uint8 dstBuff2[64]; Uint8 dstBuff3[64]; Uint32 passStatus = 1; #pragma DATA_ALIGN(myParamSetup, 32); CSL_Edma3ParamSetup myParamSetup[4]; /* Forward declarations */ void qdma_link_xfer_gbl_region (void); /* * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= */ void main(void) { /* Invoke example */ qdma_link_xfer_gbl_region (); return; } /* * ============================================================================= * @func qdma_link_xfer_gbl_region * * @arg * NONE * * @desc * This is the example routine which perform qdma link transfer where * channel is open in global region * It implements following steps * 1. Initializes and Opens the edma module * 2. Sets up the Module and gets the module setup values * 3. Opens qdma channel0 in the global region. * 4. Maps channel to parameter entry 67 * 5. Gets param handle for 64, 65, 66 * 6. Links the param sets * - Parameter set 67 is linked 66 * - Parameter set 66 is linked 65 * - Parameter set 65 is linked 64 * 7. Initializes the parameter entries using IDMA and * 8. IDMA trigger the transfer * 9. Polls for IPR bit and clears the bit * 10. Compares the transfered data * 11. Closes edma module and channel * * @return * NONE * * ============================================================================= */ void qdma_link_xfer_gbl_region (void) { CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParam64; CSL_Edma3ParamHandle hParam65; CSL_Edma3ParamHandle hParam66; CSL_Edma3ChannelObj ChObj; CSL_Edma3CmdIntr regionIntr; CSL_Edma3ChannelHandle hChannel; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Status status; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = \ CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; Uint32 loopIndex; /* Initialize data */ for (loopIndex = 0; loopIndex < 64; loopIndex++) { srcBuff0[loopIndex] = loopIndex; srcBuff1[loopIndex] = loopIndex; srcBuff2[loopIndex] = loopIndex; srcBuff3[loopIndex] = loopIndex; dstBuff0[loopIndex] = 0; dstBuff1[loopIndex] = 0; dstBuff2[loopIndex] = 0; dstBuff3[loopIndex] = 0; } /* Module Initialization */ status = CSL_edma3Init(&context); if (status != CSL_SOK) { printf ("Edma module initialization failed\n"); return; } /* Module Level Open */ hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); if ( (hModule == NULL) || (status != CSL_SOK)) { printf ("Edma module open failed\n"); return; } /* Module setup */ hwSetup.dmaChaSetup = NULL; hwSetup.qdmaChaSetup = &qdmahwSetup[0]; status = CSL_edma3HwSetup(hModule, &hwSetup); if (status != CSL_SOK) { printf ("Hardware setup failed\n"); CSL_edma3Close (hModule); return; } /* Channel open */ chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL; chAttr.chaNum = CSL_EDMA3_QCHA_0; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); if ((hChannel == NULL) || (status != CSL_SOK)) { printf ("Edma channel open failed\n"); return; } /* Change channel to parameter entry mapping */ status = CSL_edma3HwChannelSetupParam(hChannel, 67); if (status != CSL_SOK) { printf ("Edma channel to parameter entry mapping is failed\n"); return; } /* Obtain a handle to parameter set 66 */ hParam66 = CSL_edma3GetParamHandle(hChannel,66,&status); if (hParam66 == NULL) { printf ("Edma get param handle for param entry 66 failed\n"); return; } /* Obtain a handle to parameter set 65 */ hParam65 = CSL_edma3GetParamHandle(hChannel,65,&status); if (hParam65 == NULL) { printf ("Edma get param handle for param entry 65 failed\n"); return; } /* Obtain a handle to parameter set 64 */ hParam64 = CSL_edma3GetParamHandle(hChannel,64,&status); if (hParam64 == NULL) { printf ("Edma get param handle for param entry 64 failed\n"); return; } /* Parameter setup for 64, 65, 66 param entries */ myParamSetup[0].option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 3,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_EN, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup[0].srcAddr = (Uint32)srcBuff3; myParamSetup[0].aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1); myParamSetup[0].dstAddr = (Uint32)dstBuff3; myParamSetup[0] .srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup[0].linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE( CSL_EDMA3_LINK_NULL, \ 0); myParamSetup[0].srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup[0].cCnt = 1; myParamSetup[1].option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_DIS,\ 2,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup[1].srcAddr = (Uint32)srcBuff2; myParamSetup[1].aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1); myParamSetup[1].dstAddr = (Uint32)dstBuff2; myParamSetup[1] .srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup[1].linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParam64,0); myParamSetup[1].srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup[1].cCnt = 1; myParamSetup[2].option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_DIS,\ 1,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup[2].srcAddr = (Uint32)srcBuff1; myParamSetup[2].aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1); myParamSetup[2].dstAddr = (Uint32)dstBuff1; myParamSetup[2] .srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup[2].linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParam65,0); myParamSetup[2].srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup[2].cCnt = 1; myParamSetup[3].option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_DIS,\ 0,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup[3].srcAddr = (Uint32)srcBuff0; myParamSetup[3].aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1); myParamSetup[3].dstAddr = (Uint32)dstBuff0; myParamSetup[3].srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup[3].linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParam66,0); myParamSetup[3].srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup[3].cCnt = 1; /* Enable channel */ status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \ NULL); if (status != CSL_SOK) { printf("Edma channel enable command failed\n"); return; } /* Initialize the parameter entries using IDMA. Parameter entries are writtn * linearly start with parameter entry 64. As soon as the last word in * entry 67 is written the transfer gets triggered. */ IDMA0_init(IDMA_INT_EN); IDMA0_configArgs(0x00000000, (Uint32*)myParamSetup,(Uint32*)hParam64, 0); IDMA0_wait(); regionIntr.region = CSL_EDMA3_REGION_GLOBAL; /* Poll on IPR bit */ do { CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr); } while (!(regionIntr.intr & 0x8)); /* Clear interrupt */ status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \ &regionIntr); if (status != CSL_SOK) { printf("Edma interrrupt clear command failed\n"); return; } /* Check transfer by comparing the source and destination buffers */ if(Verify_Transfer( 64, 1, 1, 0, 0, 0, 0, srcBuff0, dstBuff0,TRUE) == FALSE) passStatus = 0; if(Verify_Transfer( 64, 1, 1, 0, 0, 0, 0, srcBuff1, dstBuff1,TRUE) == FALSE) passStatus = 0; if(Verify_Transfer( 64, 1, 1, 0, 0, 0, 0, srcBuff2, dstBuff2,TRUE) == FALSE) passStatus = 0; if(Verify_Transfer( 64, 1, 1, 0, 0, 0, 0, srcBuff3, dstBuff3,TRUE) == FALSE) passStatus = 0; if (passStatus == 1) printf ("<<EXAMPLE PASSED>>: Qdma Link Transfer Passed\n"); else { printf ("<<EXAMPLE FAILED>>: Qdma Link Transfer Failed\n"); return; } /* Disable the channel */ status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_DISABLE, \ NULL); /* Close channel */ status = CSL_edma3ChannelClose(hChannel); if (status != CSL_SOK) { printf("Edma channel close failed\n"); return; } /* Close edma module */ status = CSL_edma3Close(hModule); if (status != CSL_SOK) { printf("Edma module close failed\n"); return; } printf ("=============================================================\n"); return; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcOpen.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_intcOpen.c * * @brief File for functional layer of CSL API CSL_intcOpen() * * PATH $(CSLPATH)\src\intc */ /* ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= */ #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /** ============================================================================ * @n@b CSL_intcOpen * * @b Description * @n The API would reserve an interrupt-event for use. It returns * a valid handle to the event only if the event is not currently * allocated. The user could release the event after use by calling * CSL_intcClose(..) * * @b Arguments * @verbatim pIntcObj Pointer to the CSL-object allocated by the user eventId The event-id of the interrupt param Pointer to the Intc specific parameter pStatus Pointer for returning status of the function call @endverbatim * * Return Value CSL_IntcHandle * @n Valid INTC handle identifying the event * * Pre Condition * @n None * * Post Condition * @n 1. INTC object structure is populated * @n 2. The status is returned in the status variable. If status * returned is * @li CSL_SOK Valid intc handle is returned * @li CSL_ESYS_FAIL The open command failed * * @b Modifies * @n 1. The status variable * @n 2. INTC object structure * * @b Example: * @verbatim CSL_IntcObj intcObj20; CSL_IntcGlobalEnableState state; CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; context.numEvtEntries = 0; context.eventhandlerRecord = NULL; // Init Module CSL_intcInit(&context); // NMI Enable CSL_intcGlobalNmiEnable(); // Enable Global Interrupts intStat = CSL_intcGlobalEnable(&state); // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL); // Close handle CSL_IntcClose(hIntc20); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_intcOpen, ".text:csl_section:intc"); CSL_IntcHandle CSL_intcOpen ( CSL_IntcObj *intcObj, CSL_IntcEventId eventId, CSL_IntcParam *param, CSL_Status *status ) { CSL_IntcHandle hIntc = (CSL_IntcHandle)CSL_INTC_BADHANDLE; CSL_Status openStatus; Uint32 evtId; Uint32 _yCo; Uint32 _xCo; evtId = (Uint32)(eventId); _yCo = evtId >> 5; /* _yCo co-ordinate */ _xCo = 1 << (evtId & 0x1f); /* _xCo co-ordinate */ asm(" dint"); if (!(_CSL_intcAllocMask[_yCo] & _xCo)) { _CSL_intcAllocMask[_yCo] |= _xCo; /* set bit -> used */ hIntc = intcObj; } asm(" rint"); if (hIntc != (CSL_IntcHandle)CSL_INTC_BADHANDLE) { intcObj->eventId = eventId; intcObj->vectId = *((CSL_IntcVectId*)param); openStatus = CSL_SOK; /* Do the Mapping for the Event -> CPU Interrupt */ if (*((CSL_IntcVectId*)param) < ((Uint32)(CSL_INTC_VECTID_COMBINE))) { CSL_intcMapEventVector(eventId,*param); if (eventId < 4) { switch (eventId) { case 0: CSL_intcHookIsr(*((CSL_IntcVectId*)param), \ _CSL_intcEvent0Dispatcher); break; case 1: CSL_intcHookIsr(*((CSL_IntcVectId*)param), \ _CSL_intcEvent1Dispatcher); break; case 2: CSL_intcHookIsr(*((CSL_IntcVectId*)param), \ _CSL_intcEvent2Dispatcher); break; case 3: CSL_intcHookIsr(*((CSL_IntcVectId*)param), \ _CSL_intcEvent3Dispatcher); break; } } } } else openStatus = CSL_ESYS_FAIL; if (status) { *status = openStatus; } return hIntc; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_mcbspAux.h

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /* ============================================================================ * @file csl_mcbspAux.h * * @path $(CSLPATH)\inc * * @desc Header file for functional layer of CSL_mcbspAux * */ /* ============================================================================ * Revision History * =============== * 15-Feb-2005 NSR File Created from CSL_mcbspHwControl.c * And CSL_mcbspGetHwStatus.c. * 17-May-2005 RMathew - Removed CSL_mcbspIdleControl() and added inlines * for Transmit and receive interrupt mode commands and * queries * 27-Oct-2005 ds - Removed CSL_mcbspGetPid () * * 01-Feb-2006 ds - Removed CSL_mcbspGetTxIntMode (), * CSL_mcbspGetRxIntMode (), CSL_mcbspTxIntMode () and * CSL_mcbspRxIntMode () APIs * ============================================================================ */ #ifndef _CSL_MCBSPAUX_H_ #define _CSL_MCBSPAUX_H_ #include<csl_mcbsp.h> #ifdef __cplusplus extern "C" { #endif /* * Status Query Functions of mcbsp. */ /* ============================================================================ * @n@b CSL_mcbspGetCurRxBlk * * @b Description * @n This function gets the current Receive Block. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * Return Value None * * Pre Condition * @n Mcbsp must be initialized and opened properly * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetCurRxBlk (hMcbsp, response); @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_mcbspGetCurRxBlk ( CSL_McbspHandle hMcbsp, void *response ) { *(CSL_McbspBlock *)response = (CSL_McbspBlock) (CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_RCBLK)); } /* ============================================================================ * @n@b CSL_mcbspGetCurTxBlk * * @b Description * @n This function gets the current Transmit block. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * Return Value None * * Pre Condition * @n Mcbsp must be initialized and opened properly * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetCurTxBlk (hMcbsp, response); @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_mcbspGetCurTxBlk ( CSL_McbspHandle hMcbsp, void *response ) { *(CSL_McbspBlock *)response = (CSL_McbspBlock)(CSL_FEXT(hMcbsp->regs->MCR, MCBSP_MCR_XCBLK)); } /* ============================================================================ * @n@b CSL_mcbspGetDevStatus * * @b Description * @n This function gets the transmit and receive status conditions. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * Return Value None * * Pre Condition * @n Mcbsp must be initialized and opened properly * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetDevStatus (hMcbsp, response); @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_mcbspGetDevStatus ( CSL_McbspHandle hMcbsp, void *response ) { *(CSL_BitMask16*)response = (CSL_BitMask32) ((CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_RRDY)) | (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_XRDY) << (1)) | (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_RFULL) << (2)) | (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_XEMPTY) << (3)) | (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_RSYNCERR) << (4)) | (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_XSYNCERR) << (5))); } /* ============================================================================ * @n@b CSL_mcbspGetTxRstStat * * @b Description * @n This function gets the transmit reset state. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * Return Value None * * Pre Condition * @n Mcbsp must be initialized and opened properly * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetTxRstStat (hMcbsp, response); @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_mcbspGetTxRstStat ( CSL_McbspHandle hMcbsp, void *response ) { *(CSL_McbspRstStat *)response = (CSL_McbspRstStat)(CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_XRST)); } /* ============================================================================ * @n@b CSL_mcbspGetRxRstStat * * @b Description * @n This function gets the receive reset state. * * @b Arguments * @verbatim hMcbsp Handle to MCBSP instance response Placeholder to return status. @endverbatim * * Return Value None * * Pre Condition * @n Mcbsp must be initialized and opened properly * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_mcbspGetRxRstStat (hMcbsp, response); @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_mcbspGetRxRstStat ( CSL_McbspHandle hMcbsp, void *response ) { *(CSL_McbspRstStat *)response = (CSL_McbspRstStat) (CSL_FEXT(hMcbsp->regs->SPCR, MCBSP_SPCR_RRST)); } #ifdef __cplusplus } #endif #endif /* CSL_MCBSPAUX_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/cache/src/Cache_example.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in * the license agreement under which this software has been supplied. * ============================================================================ */ /** =========================================================================== * * @file Cache_example.c * * @path $(CSLPATH)\example\cache\src * * @desc Example of CACHE * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @n Usage of cache CSL API for the following operations * - Invalidate all L2 and L1D cache * - Write back invalidate all L2 and L1D cache * - Write back all L2 and L1D cache * - Invalidate the L2 and L1D cache * - Write back invalidate L2 and L1D cache * - Write back L2 and L1D cache * - L2 normal mode * - Freeze operation on L2 cache * * ============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Cache_example.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================ * Revision History * =============== * 26-Jul-2005 ds File Created. * 08-Feb-2006 ds Changed during testing on EVM. Added EMIFB CE0 as a * device memory and supported DDR2 CSL to initialize and * setup EMIFB(DDR2) location. * * ============================================================================ */ #include <stdio.h> #include <csl_cache.h> #include <_csl_cache.h> #include <csl_ddr2.h> #include <cslr_dev.h> /* L1 and L2 Caching Memory area */ #define CACHE_MEM (0xE0000000) /* Globals variables used for storing the cache data */ Uint32 temp; Uint32 Data_1; Uint32 Data_2; Uint32 Data_3; Uint32 Data_4; /* Foraward declarations */ void subExampleEndPrint(void); void exampleEndPrint (void); void init_ddr2 (void); void enableDdr2 (void); /* * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= */ void main(void) { Uint32 cacheExampleFail = 0; Uint16 loopCount; Uint16 count; CACHE_L2Size localSize[4]; /* Initialize the DDR2 module */ init_ddr2 (); /* make sure L1P is turned off */ CACHE_setL1pSize(CACHE_L1_0KCACHE); /* make sure that L1D is turned off */ CACHE_setL1dSize(CACHE_L1_0KCACHE); /* make sure that L2 is turned off */ CACHE_setL2Size(CACHE_0KCACHE); /* Array used for setting L2 cache size */ localSize[0] = CACHE_32KCACHE; localSize[1] = CACHE_64KCACHE; localSize[2] = CACHE_128KCACHE; localSize[3] = CACHE_256KCACHE; /* This loop is used to display the L2 cache size while performing different * operations on different L2 cache sizes */ for(loopCount = 0; loopCount <4; loopCount++) { switch(loopCount) { case 0: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 32K L2 cache.\n"); subExampleEndPrint(); break; case 1: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 64K L2 cache.\n"); subExampleEndPrint(); break; case 2: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 128K L2 cache.\n"); subExampleEndPrint(); break; case 3: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 256K L2 cache.\n"); subExampleEndPrint(); break; default: break; } for(count = 1; count <= 8; count++) { /* set a memory location */ *(Uint32*)CACHE_MEM = 0xABCDABCD; Data_2 = 0xa5a5a5a5; /* set Mar bit for CACHE_MEM */ CACHE_enableCaching(CACHE_EMIFB_CE00); /* turn on the L2 cache. */ CACHE_setL2Size( localSize[loopCount]); /* read (allocate into cache) */ Data_1 = *(Uint32*)CACHE_MEM; /* write (dirty the cache line) */ *(Uint32*)CACHE_MEM = Data_2; /* Read the data back (make sure it matches Data_2 */ Data_3 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_3) printf("CACHE: Data read from cache is not same as \ data written.\n"); switch(count) { /* Case #1 - invAllL2 */ case 1: /* Invalidate all the L2 cache */ CACHE_invAllL2(CACHE_WAIT); for( temp =0 ; temp < 1000; temp++) {} /* read, this data should match data_1 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_1 != Data_4) { printf("CACHE: Invalidate the All L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Invalidate the All L2 cache Passed.\n"); } break; /* Case #2 - wbInvAllL2 */ case 2: /* Writeback invalidate all the L2 cache */ CACHE_wbInvAllL2(CACHE_WAIT); for( temp =0 ; temp < 1000; temp++) {} /* read, this data should match data_2 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back invalidate All"); printf("L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back invalidate All"); printf("L2 cache Passed.\n"); } break; /* Case #3 wbAll */ case 3: /* Writeback all the L2 cache */ CACHE_wbAllL2(CACHE_WAIT); for( temp =0 ; temp < 1000; temp++) {} /* read, this data should match data_2 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_4){ printf("CACHE: Write back All L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back All L2 cache Passed.\n"); } break; /* Case #4 - invL2 */ case 4: /* Invalidate the L2 cache */ CACHE_invL2((Uint32*)CACHE_MEM, 4, CACHE_WAIT); /* read, this data should match data_1 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_1 != Data_4) { printf("CACHE: Invalidate the L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Invalidate the L2 cache Passed.\n"); } break; /* Case #5 - wbInv */ case 5: /* Writeback invalidate the L2 cache */ CACHE_wbInvL2((Uint32*)CACHE_MEM,1000, CACHE_WAIT); /* read, this data should match data_2 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back invalidate"); printf(" L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back invalidate"); printf("L2 cache Passed.\n"); } break; /* Case #6 wb */ case 6: /* Writeback L2 cache */ CACHE_wbL2((Uint32*)CACHE_MEM, 4, CACHE_WAIT); /* read, this data should match data_2 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back L2 cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back L2 cache Passed.\n"); } break; /* Case #6 wb */ case 7: /* Set L2 cache in normal mode */ CACHE_setL2Mode(CACHE_L2_NORMAL); /* read, this data should match data_3 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_3 != Data_4) { printf("CACHE: L2 Normal Mode Failed.\n"); cacheExampleFail++; } else { printf("CACHE: L2 Normal Mode Passed.\n"); } break; case 8: /* Writeback invalidate the cache */ CACHE_wbInvAllL2(CACHE_WAIT); /* freeze the cache */ if(CACHE_setL2Mode(CACHE_L2_FREEZE) != CACHE_L2_NORMAL) {} /* read, this would normally allocate space in the cache */ temp = *(Uint32*)CACHE_MEM; *(Uint32*)CACHE_MEM = 0xABCDABCD; /* write to external memory */ *(Uint32*)CACHE_MEM =0xA5A5A5A5; if(CACHE_setL2Mode(CACHE_L2_NORMAL) != CACHE_L2_FREEZE) {} Data_4 = *(Uint32*)CACHE_MEM; /* if the cache was frozen then the Data_4 should equal */ if(Data_4 != 0xA5A5A5A5) { printf("CACHE: Freeze operation on Cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Freeze operation on Cache Passed.\n"); } break; default: break; } /* L2 is turned off */ CACHE_setL2Size(CACHE_0KCACHE); /* disable caching for CE_00 */ *(Uint32*) 0x01848380 = 0; } } subExampleEndPrint(); /* Log the result.*/ if (cacheExampleFail > 0) { printf ("\nCACHE: Example on L2 cache FAILED. \ [Example Failed: %ld]\n", cacheExampleFail); } else { printf ("\nCACHE: Example on L2 cache PASSED\n"); } exampleEndPrint(); cacheExampleFail = 0; /*========================================================================* * L1D * *========================================================================*/ /* Array used for setting L1 cache size */ localSize[0] = (CACHE_L2Size)CACHE_L1_4KCACHE; localSize[1] = (CACHE_L2Size)CACHE_L1_8KCACHE; localSize[2] = (CACHE_L2Size)CACHE_L1_16KCACHE; localSize[3] = (CACHE_L2Size)CACHE_L1_32KCACHE; /* This loop is used to display the L1 cache size while performing different * operations on different L1 cache sizes */ for(loopCount = 0; loopCount <4; loopCount++) { switch(loopCount) { case 0: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 4K L1 cache.\n"); subExampleEndPrint(); break; case 1: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 8K L1 cache.\n"); subExampleEndPrint(); break; case 2: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 16K L1 cache.\n"); subExampleEndPrint(); break; case 3: printf("\n"); subExampleEndPrint(); printf("CACHE: Performing operations on 32K L1 cache.\n"); subExampleEndPrint(); break; default: break; } for(count = 1; count <= 6; count++) { /* set a memory location */ *(Uint32*)CACHE_MEM = 0xABCDABCD; Data_2 = 0xa5a5a5a5; /* set Mar bit for CACHE_MEM */ CACHE_enableCaching(CACHE_EMIFB_CE00); /* turn on the L1D cache. */ CACHE_setL1dSize( (CACHE_L1Size)localSize[loopCount]); /* read (allocate into cache) */ Data_1 = *(Uint32*)CACHE_MEM; /* write (dirty the cache line) */ *(Uint32*)CACHE_MEM = Data_2; /* Read the data back (make sure it matches Data_2) */ Data_3 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_3) printf("CACHE: Data read from cache is not same as \ data written.\n"); switch(count) { /* Case #1 - invAllL1D */ case 1: /* Invalidate all L1D cache */ CACHE_invAllL1d(CACHE_WAIT); /* read, this data should match data_1 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_1 != Data_4) { printf("CACHE: Invalidate All L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Invalidate All L1D cache Passed.\n"); } break; /* Case #2 - wbInvAllL1D */ case 2: /* Writeback invalidate all L1D cache */ CACHE_wbInvAllL1d(CACHE_WAIT); /* read, this data should match data_2 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back invalidate All"); printf("L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back invalidate All"); printf(" L1D cache Passed.\n"); } break; /* Case #3 wbAll */ case 3: /* Writeback all L1D cache */ CACHE_wbAllL1d(CACHE_WAIT); /* read, this data should match data_2 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back All L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back All L1D cache Passed.\n"); } break; /* Case #4 - invL1D */ case 4: /* Invalidate L1D cache */ CACHE_invL1d((Uint32*)CACHE_MEM,4, CACHE_WAIT); /* read, this data should match data_1 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_1 != Data_4) { printf("CACHE: Invalidate L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Invalidate L1D cache Passed.\n"); } break; /* Case #5 - wbInv */ case 5: /* Writeback invalidate L1D cache */ CACHE_wbInvL1d((Uint32*)CACHE_MEM,1000, CACHE_WAIT); /* read, this data should match data_2 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back invalidate"); printf("L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back invalidate"); printf("L1D cache Passed\n"); } break; /* Case #6 wb */ case 6: /* Writeback L1D cache */ CACHE_wbL1d((Uint32*)CACHE_MEM,1000, CACHE_WAIT); /* read, this data should match data_2 */ Data_4 = *(Uint32*)CACHE_MEM; if(Data_2 != Data_4) { printf("CACHE: Write back L1D cache Failed.\n"); cacheExampleFail++; } else { printf("CACHE: Write back L1D cache Passed.\n"); } break; default: break; } /* L1D is turned off */ CACHE_setL1dSize(CACHE_L1_0KCACHE); /* disable caching for CE_00 */ *(Uint32*) 0x01848380 = 0; } } subExampleEndPrint(); /* Log the result.*/ if (cacheExampleFail > 0) { printf ("\nCACHE: Example on L1 cache FAILED. \ [Example Failed: %ld]\n", cacheExampleFail); } else { printf ("\nCACHE: Example on L1 cache PASSED\n"); } exampleEndPrint(); } /* * ============================================================================ * @func init_ddr2 * * @desc * This function initialize and setup the DDR2 module * * @arg * None * * @return * None * ============================================================================ */ void init_ddr2 (void) { CSL_Ddr2Handle hDdr2; CSL_Ddr2Obj ddr2Obj; CSL_Status status; CSL_Ddr2HwSetup hwSetup ; CSL_Ddr2Timing1 tim1 = {0x23, 0x4,0x4, 0x4, 0x0B, 0x0F, 0x2,0x2}; CSL_Ddr2Timing2 tim2 = {0x2, 0x25, 0xDC, 0x2, 0x04}; CSL_Ddr2Settings set = CSL_DDR2_SETTING_DEFAULTS; /* setup the hardware parameters */ hwSetup.refreshRate = 0x0000073B; hwSetup.timing1Param = &tim1; hwSetup.timing2Param = &tim2; hwSetup.setParam = &set; /* Enable the DDR2 */ enableDdr2 (); /* Initialize DDR2 CSL module */ status = CSL_ddr2Init(NULL); if (status != CSL_SOK) { printf("DDR2 EMIF: Initialization error.\n"); printf("\tReason: CSL_ddr2Init [status = 0x%x].\n", status); return; } /* Opening the DDR2 instance */ hDdr2 = CSL_ddr2Open(&ddr2Obj, CSL_DDR2, NULL, &status); if ((status != CSL_SOK) || (hDdr2 == NULL)) { printf("DDR2 EMIF: Error opening the instance. [status = 0x%x, hDdr2 = \ 0x%x]\n", status, hDdr2); return; } /* Setting up configuration parameter using HwSetup */ status = CSL_ddr2HwSetup(hDdr2, &hwSetup); if (status != CSL_SOK) { printf("DDR2 EMIF: Error in HW Setup.\n"); printf("Read write operation fails\n"); return; } } /* * ============================================================================ * @func enableDdr2 * * @desc * This function enables the powerSaver for DDR2 module * * @arg * None * * @return * None * ============================================================================ */ void enableDdr2 (void) { /* Unlock the PERCFG0 register */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the ddr2 */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG1, DEV_PERCFG1_DDR2CTL, ENABLE); printf("Powersaver clock for DDR2 is enabled\n"); } void subExampleEndPrint (void) { printf ("*************************************************************\n"); } void exampleEndPrint (void) { printf ("=============================================================\n"); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/utopia2/csl_utopia2.c

<filename>DSP/TI-Header/csl_c6455_src/src/utopia2/csl_utopia2.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_utopia2.c * * @path $(CSLPATH)\src\utopia2 * * @desc This file contains the functions which are required to reset the * UTOPIA2. */ #include "csl_utopia2.h" /******************************************************************************\ * L O C A L S E C T I O N \******************************************************************************/ /* static macro declarations */ /* static typedef declarations */ /* static function declarations */ /* static variable definitions */ /* static function definitions */ /******************************************************************************\ * G L O B A L S E C T I O N \******************************************************************************/ /* global variable definitions */ CSL_Utopia2Regs *utopia2Regs = (CSL_Utopia2Regs *) CSL_UTOPIA2_0_REGS; /* global function definitions */ /** ============================================================================ * @n@b UTOPIA2_reset * * @b Description * @n This function resets UTOPIA2 Control Register and sets the Clock Detect * Register. * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n UTOPIA2 registers * * @b Example * @verbatim ... UTOPIA2_reset() ... @endverbatim * ============================================================================= */ void UTOPIA2_reset ( void ) { Uint32 cs; cs = _disable_interrupts(); utopia2Regs->UCR = UTOPIA2_UCR_DEFAULT; utopia2Regs->CDR = UTOPIA2_CDR_DEFAULT; _restore_interrupts(cs); } /* End of csl_utopia2.c */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_ddr2.h

<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_ddr2.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for DDR2 */ #ifndef _CSLR_DDR2_H_ #define _CSLR_DDR2_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint32 MIDR; volatile Uint32 DMCSTAT; volatile Uint32 SDCFG; volatile Uint32 SDRFC; volatile Uint32 SDTIM1; volatile Uint32 SDTIM2; volatile Uint8 RSVD0[8]; volatile Uint32 BPRIO; volatile Uint8 RSVD1[192]; volatile Uint32 DMCCTL; } CSL_Ddr2Regs; /**************************************************************************\ * Overlay structure typedef definition \**************************************************************************/ typedef volatile CSL_Ddr2Regs *CSL_Ddr2RegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* MIDR */ #define CSL_DDR2_MIDR_MOD_ID_MASK (0x3FFF0000u) #define CSL_DDR2_MIDR_MOD_ID_SHIFT (0x00000010u) #define CSL_DDR2_MIDR_MOD_ID_RESETVAL (0x00000031u) #define CSL_DDR2_MIDR_MJ_REV_MASK (0x0000FF00u) #define CSL_DDR2_MIDR_MJ_REV_SHIFT (0x00000008u) #define CSL_DDR2_MIDR_MJ_REV_RESETVAL (0x00000003u) #define CSL_DDR2_MIDR_MN_REV_MASK (0x000000FFu) #define CSL_DDR2_MIDR_MN_REV_SHIFT (0x00000000u) #define CSL_DDR2_MIDR_MN_REV_RESETVAL (0x0000000Fu) #define CSL_DDR2_MIDR_RESETVAL (0x0031030Fu) /* DMCSTAT */ #define CSL_DDR2_DMCSTAT_BE_MASK (0x80000000u) #define CSL_DDR2_DMCSTAT_BE_SHIFT (0x0000001Fu) #define CSL_DDR2_DMCSTAT_BE_RESETVAL (0x00000000u) /*----BE Tokens----*/ #define CSL_DDR2_DMCSTAT_BE_B_ENDIAN (0x00000001u) #define CSL_DDR2_DMCSTAT_BE_L_ENDIAN (0x00000000u) #define CSL_DDR2_DMCSTAT_IFRDY_MASK (0x00000004u) #define CSL_DDR2_DMCSTAT_IFRDY_SHIFT (0x00000002u) #define CSL_DDR2_DMCSTAT_IFRDY_RESETVAL (0x00000000u) /*----IFRDY Tokens----*/ #define CSL_DDR2_DMCSTAT_IFRDY_NOTREADY (0x00000000u) #define CSL_DDR2_DMCSTAT_IFRDY_READY (0x00000001u) #define CSL_DDR2_DMCSTAT_RESETVAL (0x40000000u) /* SDCFG */ #define CSL_DDR2_SDCFG_BOOT_UNLOCK_MASK (0x00800000u) #define CSL_DDR2_SDCFG_BOOT_UNLOCK_SHIFT (0x00000017u) #define CSL_DDR2_SDCFG_BOOT_UNLOCK_RESETVAL (0x00000000u) /*----BOOT_UNLOCK Tokens----*/ #define CSL_DDR2_SDCFG_BOOT_UNLOCK_LOCKED (0x00000000u) #define CSL_DDR2_SDCFG_BOOT_UNLOCK_UNLOCKED (0x00000001u) #define CSL_DDR2_SDCFG_DDR_DRIVE_MASK (0x00040000u) #define CSL_DDR2_SDCFG_DDR_DRIVE_SHIFT (0x00000012u) #define CSL_DDR2_SDCFG_DDR_DRIVE_RESETVAL (0x00000000u) /*----DDR_DRIVE Tokens----*/ #define CSL_DDR2_SDCFG_DDR_DRIVE_NORMAL (0x00000000u) #define CSL_DDR2_SDCFG_DDR_DRIVE_WEAK (0x00000001u) #define CSL_DDR2_SDCFG_TIMUNLOCK_MASK (0x00008000u) #define CSL_DDR2_SDCFG_TIMUNLOCK_SHIFT (0x0000000Fu) #define CSL_DDR2_SDCFG_TIMUNLOCK_RESETVAL (0x00000000u) /*----TIMUNLOCK Tokens----*/ #define CSL_DDR2_SDCFG_TIMUNLOCK_CLEAR (0x00000000u) #define CSL_DDR2_SDCFG_TIMUNLOCK_SET (0x00000001u) #define CSL_DDR2_SDCFG_NM_MASK (0x00004000u) #define CSL_DDR2_SDCFG_NM_SHIFT (0x0000000Eu) #define CSL_DDR2_SDCFG_NM_RESETVAL (0x00000000u) /*----NM Tokens----*/ #define CSL_DDR2_SDCFG_NM_32BIT (0x00000000u) #define CSL_DDR2_SDCFG_NM_16BIT (0x00000001u) #define CSL_DDR2_SDCFG_CL_MASK (0x00000E00u) #define CSL_DDR2_SDCFG_CL_SHIFT (0x00000009u) #define CSL_DDR2_SDCFG_CL_RESETVAL (0x00000005u) /*----CL Tokens----*/ #define CSL_DDR2_SDCFG_CL_TWO (0x00000002u) #define CSL_DDR2_SDCFG_CL_THREE (0x00000003u) #define CSL_DDR2_SDCFG_CL_FOUR (0x00000004u) #define CSL_DDR2_SDCFG_CL_FIVE (0x00000005u) #define CSL_DDR2_SDCFG_IBANK_MASK (0x00000070u) #define CSL_DDR2_SDCFG_IBANK_SHIFT (0x00000004u) #define CSL_DDR2_SDCFG_IBANK_RESETVAL (0x00000002u) /*----IBANK Tokens----*/ #define CSL_DDR2_SDCFG_IBANK_ONE (0x00000000u) #define CSL_DDR2_SDCFG_IBANK_TWO (0x00000001u) #define CSL_DDR2_SDCFG_IBANK_FOUR (0x00000002u) #define CSL_DDR2_SDCFG_IBANK_EIGHT (0x00000003u) #define CSL_DDR2_SDCFG_PAGESIZE_MASK (0x00000007u) #define CSL_DDR2_SDCFG_PAGESIZE_SHIFT (0x00000000u) #define CSL_DDR2_SDCFG_PAGESIZE_RESETVAL (0x00000000u) /*----PAGESIZE Tokens----*/ #define CSL_DDR2_SDCFG_PAGESIZE_256W_PAGE (0x00000000u) #define CSL_DDR2_SDCFG_PAGESIZE_512W_PAGE (0x00000001u) #define CSL_DDR2_SDCFG_PAGESIZE_1024W_PAGE (0x00000002u) #define CSL_DDR2_SDCFG_PAGESIZE_2048W_PAGE (0x00000003u) #define CSL_DDR2_SDCFG_RESETVAL (0x00530A20u) /* SDRFC */ #define CSL_DDR2_SDRFC_SR_MASK (0x80000000u) #define CSL_DDR2_SDRFC_SR_SHIFT (0x0000001Fu) #define CSL_DDR2_SDRFC_SR_RESETVAL (0x00000000u) /*----SR Tokens----*/ #define CSL_DDR2_SDRFC_SR_EXIT (0x00000000u) #define CSL_DDR2_SDRFC_SR_ENTER (0x00000001u) #define CSL_DDR2_SDRFC_REFRESH_RATE_MASK (0x0000FFFFu) #define CSL_DDR2_SDRFC_REFRESH_RATE_SHIFT (0x00000000u) #define CSL_DDR2_SDRFC_REFRESH_RATE_RESETVAL (0x00000753u) #define CSL_DDR2_SDRFC_RESETVAL (0x00000753u) /* SDTIM1 */ #define CSL_DDR2_SDTIM1_T_RFC_MASK (0xFE000000u) #define CSL_DDR2_SDTIM1_T_RFC_SHIFT (0x00000019u) #define CSL_DDR2_SDTIM1_T_RFC_RESETVAL (0x0000003Fu) #define CSL_DDR2_SDTIM1_T_RP_MASK (0x01C00000u) #define CSL_DDR2_SDTIM1_T_RP_SHIFT (0x00000016u) #define CSL_DDR2_SDTIM1_T_RP_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM1_T_RCD_MASK (0x00380000u) #define CSL_DDR2_SDTIM1_T_RCD_SHIFT (0x00000013u) #define CSL_DDR2_SDTIM1_T_RCD_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM1_T_WR_MASK (0x00070000u) #define CSL_DDR2_SDTIM1_T_WR_SHIFT (0x00000010u) #define CSL_DDR2_SDTIM1_T_WR_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM1_T_RAS_MASK (0x0000F800u) #define CSL_DDR2_SDTIM1_T_RAS_SHIFT (0x0000000Bu) #define CSL_DDR2_SDTIM1_T_RAS_RESETVAL (0x0000001Fu) #define CSL_DDR2_SDTIM1_T_RC_MASK (0x000007C0u) #define CSL_DDR2_SDTIM1_T_RC_SHIFT (0x00000006u) #define CSL_DDR2_SDTIM1_T_RC_RESETVAL (0x0000001Fu) #define CSL_DDR2_SDTIM1_T_RRD_MASK (0x00000038u) #define CSL_DDR2_SDTIM1_T_RRD_SHIFT (0x00000003u) #define CSL_DDR2_SDTIM1_T_RRD_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM1_T_WTR_MASK (0x00000003u) #define CSL_DDR2_SDTIM1_T_WTR_SHIFT (0x00000000u) #define CSL_DDR2_SDTIM1_T_WTR_RESETVAL (0x00000003u) #define CSL_DDR2_SDTIM1_RESETVAL (0x7FFFFFFBu) /* SDTIM2 */ #define CSL_DDR2_SDTIM2_T_ODT_MASK (0x01800000u) #define CSL_DDR2_SDTIM2_T_ODT_SHIFT (0x00000017u) #define CSL_DDR2_SDTIM2_T_ODT_RESETVAL (0x00000003u) #define CSL_DDR2_SDTIM2_T_SXNR_MASK (0x007F0000u) #define CSL_DDR2_SDTIM2_T_SXNR_SHIFT (0x00000010u) #define CSL_DDR2_SDTIM2_T_SXNR_RESETVAL (0x0000007Fu) #define CSL_DDR2_SDTIM2_T_SXRD_MASK (0x0000FF00u) #define CSL_DDR2_SDTIM2_T_SXRD_SHIFT (0x00000008u) #define CSL_DDR2_SDTIM2_T_SXRD_RESETVAL (0x000000FFu) #define CSL_DDR2_SDTIM2_T_RTP_MASK (0x000000E0u) #define CSL_DDR2_SDTIM2_T_RTP_SHIFT (0x00000005u) #define CSL_DDR2_SDTIM2_T_RTP_RESETVAL (0x00000007u) #define CSL_DDR2_SDTIM2_T_CKE_MASK (0x0000001Fu) #define CSL_DDR2_SDTIM2_T_CKE_SHIFT (0x00000000u) #define CSL_DDR2_SDTIM2_T_CKE_RESETVAL (0x0000001Fu) #define CSL_DDR2_SDTIM2_RESETVAL (0x01FFFFFFu) /* BPRIO */ #define CSL_DDR2_BPRIO_PRIO_RAISE_MASK (0x000000FFu) #define CSL_DDR2_BPRIO_PRIO_RAISE_SHIFT (0x00000000u) #define CSL_DDR2_BPRIO_PRIO_RAISE_RESETVAL (0x000000FFu) #define CSL_DDR2_BPRIO_RESETVAL (0x000000FFu) /* DMCCTL */ #define CSL_DDR2_DMCCTL_IFRESET_MASK (0x00000020u) #define CSL_DDR2_DMCCTL_IFRESET_SHIFT (0x00000005u) #define CSL_DDR2_DMCCTL_IFRESET_RESETVAL (0x00000001u) /*----IFRESET Tokens----*/ #define CSL_DDR2_DMCCTL_IFRESET_RELEASE (0x00000000u) #define CSL_DDR2_DMCCTL_IFRESET_ASSERT (0x00000001u) #define CSL_DDR2_DMCCTL_RL_MASK (0x00000007u) #define CSL_DDR2_DMCCTL_RL_SHIFT (0x00000000u) #define CSL_DDR2_DMCCTL_RL_RESETVAL (0x00000007u) #define CSL_DDR2_DMCCTL_RESETVAL (0x50006427u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_tcp2Aux.h

<filename>DSP/TI-Header/csl_c6455_src/inc/csl_tcp2Aux.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_tcp2Aux.h * * @path $(CSLPATH)\tcp2\inc * * @desc Auxiliary API header file for TCP CSL * */ /* ============================================================================= * Revision History * =============== * 26-Mar-2005 sd File Created. * 21-Jul-2005 sd Updated for the requirement changes * 15-Sep-2005 sd Changed TCP to TCP2 in all the names * 30-Jan-2006 sd Updated the descriptions for TCP2_normalCeil and TCP2_ceil * and chnages for the bit field names TCPEND register * ============================================================================= */ #ifndef _CSL_TCP2AUX_H_ #define _CSL_TCP2AUX_H_ #ifdef __cplusplus extern "C" { #endif #include <tistdtypes.h> #include <cslr_tcp2.h> #include <csl_tcp2.h> /** ============================================================================ * @n@b TCP2_normalCeil * * @b Description * @n Returns the value rounded to the nearest integer greater than or * equal to (val1/val2) * * @b Arguments @verbatim val1 Value to be augmented. val2 Value by which val1 must be divisible. @endverbatim * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 framelen = 51200; Uint32 numSubFrame; ... // to calculate the number of sub frames for SP mode numSubFrame = TCP2_normalCeil (framelen, TCP2_SUB_FRAME_SIZE_MAX); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_normalCeil ( Uint32 val1, Uint32 val2 ) { Uint32 x; /* x = ceil(val1/val2) */ /* val1 is increased (if necessary) to be a multiple of val2 */ x = (((val1) % (val2)) != 0) ? (((val1) / (val2)) + 1) : ((val1) / (val2)); return(x); } /** ============================================================================ * @n@b TCP2_ceil * * @b Description * @n Returns the value rounded to the nearest integer greater than or * equal to (val/(2^pwr2)). * * @b Arguments @verbatim val Value to be augmented. pwr2 The power of two by which val must be divisible. @endverbatim * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 val1 = 512; Uint32 val2 = 4; Uint32 val3; val3 = TCP2_ceil(val1, val2); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_ceil ( Uint32 val, Uint32 pwr2 ) { Uint32 x; /* x = ceil(val/ (2^pwr2)) */ /* val is increased (if necessary) to be a multiple of 2^pwr2 */ x = (((val) - (((val) >> (pwr2)) << (pwr2))) == 0) ? \ ((val) >> (pwr2)): (((val) >> (pwr2)) + 1); return(x); } /** ============================================================================ * @n@b TCP2_setExtScaling * * @b Description * @n This function formats individual bytes into a 32-bit word, which is * used to set the extrinsic configuration registers. * * @b Arguments @verbatim extrVal1 extrinsic scaling value 1 extrVal2 extrinsic scaling value 2 extrVal3 extrinsic scaling value 3 extrVal4 extrinsic scaling value 4 @endverbatim * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim TCP2_Params configParams; TCP2_IcConfig configIc configIc->ic12 = TCP2_setExtScaling (configParams->extrScaling [0], configParams->extrScaling [1], configParams->extrScaling [2], configParams->extrScaling [3]); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_setExtScaling ( Uint8 extrVal1, Uint8 extrVal2, Uint8 extrVal3, Uint8 extrVal4 ) { Uint32 icConfigVal; icConfigVal = (extrVal4 << 18) | (extrVal3 << 12) | (extrVal2 << 6) | (extrVal1); return icConfigVal; } /** ============================================================================ * @n@b TCP2_makeTailArgs * * @b Description * @n This function formats individual bytes into a 32-bit word, which is * used to set the tail bits configuration registers. * * @b Arguments @verbatim byte17_12 Byte to be placed in bits 17-12 of the 32-bit value byte11_6 Byte to be placed in bits 11-6 of the 32-bit value byte5_0 Byte to be placed in bits 5-0 of the 32-bit value @endverbatim * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim TCP2_Params configParams; TCP2_IcConfig configIc configIc.ic6 = TCP2_makeTailArgs (xabData[10], xabData[8], xabData[6]); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_makeTailArgs ( Uint8 byte17_12, Uint8 byte11_6, Uint8 byte5_0 ) { Uint32 x = 0; x = (byte17_12 << 12) | (byte11_6 << 6) | byte5_0; return(x); } /** ============================================================================ * @n@b TCP2_getAccessErr * * @b Description * @n This function returns the ACC bit value of the TCPERR register * indicating whether an invalid access has been made to the TCP during * operation. * @n 0 - no error * @n 1 - TCP rams (syst, parities, hard decisions, extrinsics, aprioris) * access is not allowed in state 1. This causes an error interrupt * to occur * * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getAccessErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getAccessErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_ACC); } /** ============================================================================ * @n@b TCP2_getErr * * @b Description * @n This function returns the ERR bit value of the TCPERR register * indicating whether an error has occurred during TCP operation. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_ERR); } /** ============================================================================ * @n@b TCP2_getTcpErrors * * @b Description * @n This function returns the TCPERR register value. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getTcpErrors ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getTcpErrors ( void ) { return (tcp2Regs->TCPERR); } /** ============================================================================ * @n@b TCP2_getFrameLenErr * * @b Description * @n This function returns a boolean value indicating whether an invalid * frame length has been programmed in the TCP during operation. * @n 0 - no error. * @n 1 - (SA mode) frame length < 40 or frame length > 20730. * - (SP mode) frame length < 256 or frame length > 20480 and f%256!=0 * for the first or middle subframes. * - (SP mode) if f<128 or f>20480 for the last subframe. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getFrameLenErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getFrameLenErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_F); } /** ============================================================================ * @n@b TCP2_getProlLenErr * * @b Description * @n This function returns the P bit value indicating whether an invalid * prolog length has been programmed into the TCP. * 0 - no error * 1 - Prolog length < 4 or > 48 * * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getProlLenErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getProlLenErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_P); } /** ============================================================================ * @n@b TCP2_getSubFrameErr * * @b Description * @n This function returns a boolean value indicating whether the sub-frame * length programmed into the TCP is invalid. * 0 - no error * 1 - sub-frame length > 20480 (SP mode) * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getSubFrameErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getSubFrameErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_SF); } /** ============================================================================ * @n@b TCP2_getRelLenErr * * @b Description * @n This function returns the R bit value indicating whether an invalid * reliability length has been programmed into the TCP. The reliability * length must be 40 < RL < 128 for SA Mode, or * SW_R must = 128 during First/Middle subframes of SP mode, and * SW_R must be > 64 in the Last subframe. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getRelLenErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getRelLenErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_R); } /** ============================================================================ * @n@b TCP2_getSnrErr * * @b Description * @n This function returns the SNR bit value indicating whether the SNR * threshold exceeded 100 (1) or not (0). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getSnrErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getSnrErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_SNR); } /** ============================================================================ * @n@b TCP2_getInterleaveErr * * @b Description * @n This function returns the INTER value bit indicating whether the TCP * was incorrectly programmed to receive an interleaver table. An * interleaver table can only be sent when operating in standalone mode. * This bit(1) indicates if an interleaver table was sent when in shared * processing mode. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getInterleaveErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getInterleaveErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_INT); } /** ============================================================================ * @n@b TCP2_getOutParmErr * * @b Description * @n This function returns the OP bit value (1) indicating whether the TCP was * programmed to transfer output parameters in shared processing mode. * The output parameters are only valid when operating in standalone mode. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getOutParmErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getOutParmErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_OP); } /** ============================================================================ * @n@b TCP2_getMaxMinErr * * @b Description * @n This function returns the MAXMINITER bit value indicating whether the * TCP was programmed with the minimum iterations value greater than the * maximum iterations. * 0 = no error, 1 = min_iter > max_iter * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getMaxMinErr ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getMaxMinErr ( void ) { return CSL_FEXT (tcp2Regs->TCPERR, TCP2_TCPERR_MAXMINITER); } /** ============================================================================ * @n@b TCP2_getNumIt * * @b Description * @n This function returns the number of decoded iterations of the TCP in * standalone processing mode. This function reads the output parameters * register. Alternatively, the EDMA can be used to transfer the output * parameters following the hard decisions (recommended). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 numIter; numIter = TCP2_getNumIt (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getNumIt ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT0, TCP2_TCPOUT0_FINAL_ITER); } /** ============================================================================ * @n@b TCP2_getSnrM1 * * @b Description * @n This function returns the 1st moment of SNR calculation. This function * reads the output parameters register. Alternatively, the EDMA can be * used to transfer the output parameters following the hard decisions * (recommended). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 snrM1; snrM1 = TCP2_getSnrM1 (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getSnrM1 ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT0, TCP2_TCPOUT0_SNR_M1); } /** ============================================================================ * @n@b TCP2_getSnrM2 * * @b Description * @n This function returns the 2nd moment of SNR calculation. This function * reads the output parameters register. Alternatively, the EDMA can be * used to transfer the output parameters following the hard decisions * (recommended). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 snrM2; snrM2 = TCP2_getSnrM2 (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getSnrM2 ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT1, TCP2_TCPOUT1_SNR_M2); } /** ============================================================================ * @n@b TCP2_getMap * * @b Description * @n This function returns the active MAP of the TCP. * 0 - MAP 0 is active * 1 - MAP 1 is active * This function reads the output parameters register. Alternatively, * the EDMA can be used to transfer the output parameters following the * hard decisions (recommended). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 activeMap; activeMap = TCP2_getMap (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getMap ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT1, TCP2_TCPOUT1_ACTIVE_MAP); } /** ============================================================================ * @n@b TCP2_getMap0Err * * @b Description * @n This function returns the number of re-encode errors for MAP 0. * This function reads the output parameters register. Alternatively, * the EDMA can be used to transfer the output parameters following the * hard decisions (recommended). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 map0Err; map0Err = TCP2_getMap0Err (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getMap0Err ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT2, TCP2_TCPOUT2_CNT_RE_MAP0); } /** ============================================================================ * @n@b TCP2_getMap1Err * * @b Description * @n This function returns the number of re-encode errors for MAP 1. * This function reads the output parameters register. Alternatively, * the EDMA can be used to transfer the output parameters following the * hard decisions (recommended). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 map1Err; map1Err = TCP2_getMap1Err (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getMap1Err ( void ) { return CSL_FEXT (tcp2CfgRegs->TCPOUT2, TCP2_TCPOUT2_CNT_RE_MAP1); } /** ============================================================================ * @n@b TCP2_statRun * * @b Description * @n This function returns a boolean status indicating whether the TCP MAP * decoder is in state 0 or state 1-8 (running or not). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim while (!TCP2_statRun()); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statRun ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_DEC_BUSY); } /** ============================================================================ * @n@b TCP2_statError * * @b Description * @n This function returns the ERR bit value indicating whether any TCP * error has occurred. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statError ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statError ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ERR); } /** ============================================================================ * @n@b TCP2_statWaitIc * * @b Description * @n This function returns the WIC bit status indicating whether the TCP * is waiting to receive new IC values. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitIc ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statWaitIc ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_WIC); } /** ============================================================================ * @n@b TCP2_statWaitInter * * @b Description * @n This function returns the WINT status indicating whether the TCP is * waiting to receive interleaver table data. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitInter ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statWaitInter ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_WINT); } /** ============================================================================ * @n@b TCP2_statWaitSysPar * * @b Description * @n This function returns the WSP bit status indicating whether the TCP * is waiting to receive systematic and parity data. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitSysPar ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statWaitSysPar ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_WSP); } /** ============================================================================ * @n@b TCP2_statWaitApriori * * @b Description * @n This function returns the WAP bit status indicating whether the TCP is * waiting to receive apriori data. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitApriori ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statWaitApriori ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_WAP); } /** ============================================================================ * @n@b TCP2_statWaitExt * * @b Description * @n This function returns the REXT bit status indicating whether the TCP * is waiting for extrinsic data to be read. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitExt ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statWaitExt ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_REXT); } /** ============================================================================ * @n@b TCP2_statWaitHardDec * * @b Description * @n This function returns the RHD bit status indicating whether the TCP * is waiting for the hard decisions data to be read. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitHardDec ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statWaitHardDec ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_RHD); } /** ============================================================================ * @n@b TCP2_statWaitOutParm * * @b Description * @n This function returns the ROP bit status indicating whether the TCP * is waiting for the output parameters to be read. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statWaitOutParm ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statWaitOutParm ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ROP); } /** ============================================================================ * @n@b TCP2_statEmuHalt * * @b Description * @n This function returns the emuhalt bit status indicating whether the * TCP is halted due to emulation. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statEmuHalt ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statEmuHalt ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_EMUHALT); } /** ============================================================================ * @n@b TCP2_statActMap * * @b Description * @n This function returns the active_map bit status indicating whether * the TCP MAP 0 is active (0) or the TCP MAP 1 is active (1). * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 activeMap; ..... activeMap = TCP2_statActMap (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statActMap ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ACTIVE_MAP); } /** ============================================================================ * @n@b TCP2_statActState * * @b Description * @n This function returns the active_state bit status indicating the * active TCP MAP decoder state. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 activeState; ..... activeState = TCP2_statActState (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statActState ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ACTIVE_STATE); } /** ============================================================================ * @n@b TCP2_statActIter * * @b Description * @n This function returns the active_iter bit status indicating the * active TCP iteration. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 activeIter; ..... activeIter = TCP2_statActIter (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statActIter ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_ACTIVE_ITER); } /** ============================================================================ * @n@b TCP2_statSnr * * @b Description * @n This function returns the snr_exceed bits, indicating whether the * TCP MAP 0 or MAP 1 passed the SNR criteria in a particular iteration. * 0 - All fail * 1 - MAP 1 failed * 2 - MAP 0 failed * 3 - All passed * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 snrExceed; ..... snrExceed = TCP2_statSnr (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statSnr ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_SNR_EXCEED); } /** ============================================================================ * @n@b TCP2_statCrc * * @b Description * @n This function returns the crc_pass bit boolean status indicating whether * the TCP passed CRC check. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_statCrc ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statCrc ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_CRC_PASS); } /** ============================================================================ * @n@b TCP2_statTcpState * * @b Description * @n This function returns the state of the TCP state machine for * the standalone mode or shared processing mode. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 tcpState; .... tcpState = TCP2_statTcpState (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_statTcpState ( void ) { return CSL_FEXT (tcp2Regs->TCPSTAT, TCP2_TCPSTAT_TCP_STATE); } /** ============================================================================ * @n@b TCP2_getExecStatus * * @b Description * @n This function returns the TCPSTAT register value. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim Uint32 tcpStatus; tcpStatus = TCP2_getExecStatus (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getExecStatus ( void ) { return (tcp2Regs->TCPSTAT); } /** ============================================================================ * @n@b TCP2_getExtEndian * * @b Description * @n This function returns the value programmed into the TCP_END register * for the extrinsics data indicating whether the data is in its native * 8-bit format ('1') or consists of values packed in little endian format * into 32-bit words ('0'). This should always be '0' for little endian * operation. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getExtEndian ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getExtEndian ( void ) { return CSL_FEXT (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_EXTR); } /** ============================================================================ * @n@b TCP2_getInterEndian * * @b Description * @n Returns the value programmed into the TCP_END register for the * interleaver table data indicating whether the data is in its native * 8-bit format ('1') or consists of values packed in little endian format * into 32-bit words ('0'). This should always be '0' for little endian * operation. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getInterEndian ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getInterEndian ( void ) { return CSL_FEXT (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_INTR); } /** ============================================================================ * @n@b TCP2_getSlpzvss * * @b Description * @n This function gets the configuration of the internal control of * the slpzvss. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getSlpzvss ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getSlpzvss ( void ) { return CSL_FEXT (tcp2Regs->TCPEND, TCP2_TCPEND_SLPZVSS_EN); } /** ============================================================================ * @n@b TCP2_getSlpzvdd * * @b Description * @n This function gets the configuration of the internal control of * the slpzvdd. * * @b Arguments * @n None * * Return Value Uint32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim if (TCP2_getSlpzvdd ()){ ... } @endverbatim * ============================================================================= */ CSL_IDEF_INLINE Uint32 TCP2_getSlpzvdd ( void ) { return CSL_FEXT (tcp2Regs->TCPEND, TCP2_TCPEND_SLPZVDD_EN); } /** ============================================================================ * @n@b TCP2_setExtEndian * * @b Description * @n This function programs TCP to view the format of the extrinsics data * as either native 8-bit format ('1') or values packed into 32-bit words * in little endian format ('0'). This should always be '0' for little * endian operation. * * @b Arguments @verbatim endianMode Endian setting for extrinsics data @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCPEND register bit for the extrinsics data is configured in the * mode passed. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setExtEndian (1); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_setExtEndian ( Uint32 endianMode ) { CSL_FINS (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_EXTR, endianMode); return; } /** ============================================================================ * @n@b TCP2_setInterEndian * * @b Description * @n This function programs TCP to view the format of the interleaver data * as either native 8-bit format ('1') or values packed into 32-bit words * in little endian format ('0'). This should always be '0' for little * endian operation. * * @b Arguments @verbatim endianMode Endian setting for interleaver data @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCPEND register bit for the interleaver data is configured in the * mode passed. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setInterEndian (1); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_setInterEndian ( Uint32 endianMode ) { CSL_FINS (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_INTR, endianMode); return; } /** ============================================================================ * @n@b TCP2_setNativeEndian * * @b Description * @n This function programs the TCP to view the format of all data as * native 8/16 bit format. This should only be used when running in * big endian mode. * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCPEND register configured to native mode for all data. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setNativeEndian (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_setNativeEndian ( void ) { CSL_FINST (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_INTR, NATIVE16); CSL_FINST (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_EXTR, NATIVE8); return; } /** ============================================================================ * @n@b TCP2_setPacked32Endian * * @b Description * @n This function programs the TCP to view the format of all data as * packed data in 32-bit words. This should always be used when running * in little endian mode and should be used in big endian mode only if * the CPU is formatting the data. * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCPEND register configured to packed 32 mode for all data. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setPacked32Endian (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_setPacked32Endian ( void ) { CSL_FINST (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_INTR, 32BITS); CSL_FINST (tcp2Regs->TCPEND, TCP2_TCPEND_ENDIAN_EXTR, 32BITS); return; } /** ============================================================================ * @n@b TCP2_start * * @b Description * @n This function starts the TCP by writing a 1 to the EXEINST field * of the TCPEXE register. See also TCP2_debug(), TCP2_debugStep() and * TCP2_debugComplete(). * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCP state machine starts executing. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_start (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_start ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, START); return; } /** ============================================================================ * @n@b TCP2_debug * * @b Description * @n This function puts the TCP into debug mode by writing '4h' to the * EXEINST field of the TCPEXE register. Normal initialization is * performed and TCP waits in MAP state 0 for Debug Step or Debug Complete * to be performed. See also TCP2_start(), TCP2_debugStep() and * TCP2_debugComplete() * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n EXEINST feild of the TCPEXE register is configured with the value passed. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_debug (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_debug ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, DEBUG0); return; } /** ============================================================================ * @n@b TCP2_debugStep * * @b Description * @n This function executes one MAP decode and waits in state 6 when the * TCP is in Debug mode, by writing '5h' to the EXEINST field of the * TCPEXE register. See also TCP2_start(), TCP2_debug() and * TCP2_debugComplete() * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n EXEINST feild of the TCPEXE register is configured with the value passed. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_debugStep (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_debugStep ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, DEBUG6); return; } /** ============================================================================ * @n@b TCP2_debugComplete * * @b Description * @n This function executes the remaing MAP decodes when the TCP is in * Debug mode, by writing '6h' to the EXEINST field of the TCPEXE register. * See also TCP2_start(), TCP2_debug() and TCP2_debugComplete() * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n EXEINST feild of the TCPEXE register is configured with the value passed. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_debugComplete (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_debugComplete ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, DEBUG); return; } /** ============================================================================ * @n@b TCP2_reset * * @b Description * @n This function performs a soft reset of all TCP registers except for * TCPEXE and TCPEND registers. * * @b Arguments * @n None * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n performs soft reset of TCP. * * @b Modifies * @n TCPEXE register * * @b Example * @verbatim TCP2_reset (); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_reset ( void ) { CSL_FINST (tcp2Regs->TCPEXE, TCP2_TCPEXE_EXECUTION_INSTR, SOFTRESET); return; } /** ============================================================================ * @n@b TCP2_setSlpzvdd * * @b Description * @n This function enables/disables the internal control of the slpzvdd. * * @b Arguments @verbatim slpzvddCtrl enable/disable configuration of the slpzvdd @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCPEND register configured with the value passed. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setSlpzvdd (1); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_setSlpzvdd ( Uint32 slpzvddCtrl ) { CSL_FINS (tcp2Regs->TCPEND, TCP2_TCPEND_SLPZVDD_EN, slpzvddCtrl); return; } /** ============================================================================ * @n@b TCP2_setSlpzvss * * @b Description * @n This function enables/disables the internal control of the slpzvss. * * @b Arguments @verbatim slpzvssCtrl enable/disable configuration of the slpzvss @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCPEND register configured with the value passed. * * @b Modifies * @n TCPEND register * * @b Example * @verbatim TCP2_setSlpzvss (1); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_setSlpzvss ( Uint32 slpzvssCtrl ) { CSL_FINS (tcp2Regs->TCPEND, TCP2_TCPEND_SLPZVSS_EN, slpzvssCtrl); return; } /** ============================================================================ * @n@b TCP2_getIcConfig * * @b Description * @n This function reads the input configuration values currently programmed * into the TCP. * * @b Arguments @verbatim config TCP configuration structure to hold the read values @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n config structure contains the TCP input configuration values. * * @b Modifies * @n None * * @b Example * @verbatim TCP2_getIcConfig (&config); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_getIcConfig ( TCP2_ConfigIc *config ) { Uint32 gie; gie = _disable_interrupts (); config->ic0 = tcp2CfgRegs->TCPIC0; config->ic1 = tcp2CfgRegs->TCPIC1; config->ic2 = tcp2CfgRegs->TCPIC2; config->ic3 = tcp2CfgRegs->TCPIC3; config->ic4 = tcp2CfgRegs->TCPIC4; config->ic5 = tcp2CfgRegs->TCPIC5; config->ic6 = tcp2CfgRegs->TCPIC6; config->ic7 = tcp2CfgRegs->TCPIC7; config->ic8 = tcp2CfgRegs->TCPIC8; config->ic9 = tcp2CfgRegs->TCPIC9; config->ic10 = tcp2CfgRegs->TCPIC10; config->ic11 = tcp2CfgRegs->TCPIC11; config->ic12 = tcp2CfgRegs->TCPIC12; config->ic13 = tcp2CfgRegs->TCPIC13; config->ic14 = tcp2CfgRegs->TCPIC14; config->ic15 = tcp2CfgRegs->TCPIC15; _restore_interrupts (gie); } /** ============================================================================ * @n@b TCP2_icConfig * * @b Description * @n Programs the TCP with the input configuration values passed in the * TCP2_ConfigIc structure. This is not the recommended means by which to * program the TCP, as it is more efficient to transfer the IC values using * the EDMA. * * @b Arguments @verbatim config TCP configuration structure containing the values to be programmed @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCP input configuration registers are programmed with the values passed. * * @b Modifies * @n None * * @b Example * @verbatim TCP2_ConfigIc configIc; configIc.ic0 = 0x00283300; configIc.ic1 = 0x00270000; configIc.ic2 = 0x00080118; configIc.ic3 = 0x00000011; configIc.ic4 = 0x00000100; configIc.ic5 = 0x00000000; configIc.ic6 = 0x00032c2f; configIc.ic7 = 0x00027831; configIc.ic8 = 0x00000000; configIc.ic9 = 0x00018430; configIc.ic10 = 0x0003bfcd; configIc.ic11 = 0x00000000; configIc.ic12 = 0x00820820; configIc.ic13 = 0x00820820; configIc.ic14 = 0x00820820; configIc.ic15 = 0x00820820; TCP2_icConfig (&config); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_icConfig ( TCP2_ConfigIc *config ) { Uint32 gie; gie = _disable_interrupts (); tcp2CfgRegs->TCPIC0 = config->ic0; tcp2CfgRegs->TCPIC1 = config->ic1; tcp2CfgRegs->TCPIC2 = config->ic2; tcp2CfgRegs->TCPIC3 = config->ic3; tcp2CfgRegs->TCPIC4 = config->ic4; tcp2CfgRegs->TCPIC5 = config->ic5; tcp2CfgRegs->TCPIC6 = config->ic6; tcp2CfgRegs->TCPIC7 = config->ic7; tcp2CfgRegs->TCPIC8 = config->ic8; tcp2CfgRegs->TCPIC9 = config->ic9; tcp2CfgRegs->TCPIC10 = config->ic10; tcp2CfgRegs->TCPIC11 = config->ic11; tcp2CfgRegs->TCPIC12 = config->ic12; tcp2CfgRegs->TCPIC13 = config->ic13; tcp2CfgRegs->TCPIC14 = config->ic14; tcp2CfgRegs->TCPIC15 = config->ic15; _restore_interrupts (gie); } /** ============================================================================ * @n@b TCP2_icConfigArgs * * @b Description * @n Programs the TCP with the input configuration values passed. This is * not the recommended means by which to program the TCP, as it is more * efficient to transfer the IC values using the EDMA. * * @b Arguments @verbatim ic0 TCP input configuration register 0 value ic1 TCP input configuration register 1 value ic2 TCP input configuration register 2 value ic3 TCP input configuration register 3 value ic4 TCP input configuration register 4 value ic5 TCP input configuration register 5 value ic6 TCP input configuration register 6 value ic7 TCP input configuration register 7 value ic8 TCP input configuration register 8 value ic9 TCP input configuration register 9 value ic10 TCP input configuration register 10 value ic11 TCP input configuration register 11 value ic12 TCP input configuration register 12 value ic13 TCP input configuration register 13 value ic14 TCP input configuration register 14 value ic15 TCP input configuration register 15 value @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n TCP input configuration registers are programmed with the values passed. * * @b Modifies * @n None * * @b Example * @verbatim Uint32 ic0, ic1, ic2, ic3, ic4, ic5, ic6, ic7, ic8, ic9 , ic10, ic11, ic12, ic13, ic14, ic15; ic0 = 0x00283300; ic1 = 0x00270000; ic2 = 0x00080118; ic3 = 0x00000011; ic4 = 0x00000100; ic5 = 0x00000000; ic6 = 0x00032c2f; ic7 = 0x00027831; ic8 = 0x00000000; ic9 = 0x00018430; ic10 = 0x0003bfcd; ic11 = 0x00000000; ic12 = 0x00820820; ic13 = 0x00820820; ic14 = 0x00820820; ic15 = 0x00820820; TCP2_icConfigArgs (ic0, ic1, ic2, ic3, ic4, ic5, ic6, ic7, ic8, ic9, ic10, ic11, ic12, ic13, ic14, ic15); @endverbatim * ============================================================================= */ CSL_IDEF_INLINE void TCP2_icConfigArgs ( Uint32 ic0, Uint32 ic1, Uint32 ic2, Uint32 ic3, Uint32 ic4, Uint32 ic5, Uint32 ic6, Uint32 ic7, Uint32 ic8, Uint32 ic9, Uint32 ic10, Uint32 ic11, Uint32 ic12, Uint32 ic13, Uint32 ic14, Uint32 ic15 ) { Uint32 gie; gie = _disable_interrupts (); tcp2CfgRegs->TCPIC0 = ic0; tcp2CfgRegs->TCPIC1 = ic1; tcp2CfgRegs->TCPIC2 = ic2; tcp2CfgRegs->TCPIC3 = ic3; tcp2CfgRegs->TCPIC4 = ic4; tcp2CfgRegs->TCPIC5 = ic5; tcp2CfgRegs->TCPIC6 = ic6; tcp2CfgRegs->TCPIC7 = ic7; tcp2CfgRegs->TCPIC8 = ic8; tcp2CfgRegs->TCPIC9 = ic9; tcp2CfgRegs->TCPIC10 = ic10; tcp2CfgRegs->TCPIC11 = ic11; tcp2CfgRegs->TCPIC12 = ic12; tcp2CfgRegs->TCPIC13 = ic13; tcp2CfgRegs->TCPIC14 = ic14; tcp2CfgRegs->TCPIC15 = ic15; _restore_interrupts (gie); } #ifdef __cplusplus } #endif #endif /* _CSL_TCP2AUX_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/cslr_memprot_L1D.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_memprot_L1D.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for MEMPROTL1D */ #ifndef _CSLR_MEMPROT_L1D_H_ #define _CSLR_MEMPROT_L1D_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint32 MPFAR; volatile Uint32 MPFSR; volatile Uint32 MPFCR; volatile Uint8 RSVD0[244]; volatile Uint32 MPLK0; volatile Uint32 MPLK1; volatile Uint32 MPLK2; volatile Uint32 MPLK3; volatile Uint32 MPLKCMD; volatile Uint32 MPLKSTAT; volatile Uint8 RSVD1[232]; volatile Uint32 MPPA[32]; } CSL_Memprotl1dRegs; typedef volatile CSL_Memprotl1dRegs *CSL_Memprotl1dRegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* MPFAR */ #define CSL_MEMPROTL1D_MPFAR_ADDR_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPFAR_ADDR_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPFAR_ADDR_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFAR_RESETVAL (0x00000000u) /* MPFSR */ #define CSL_MEMPROTL1D_MPFSR_FID_MASK (0x0000FE00u) #define CSL_MEMPROTL1D_MPFSR_FID_SHIFT (0x00000009u) #define CSL_MEMPROTL1D_MPFSR_FID_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_LOCAL_MASK (0x00000100u) #define CSL_MEMPROTL1D_MPFSR_LOCAL_SHIFT (0x00000008u) #define CSL_MEMPROTL1D_MPFSR_LOCAL_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_SR_MASK (0x00000020u) #define CSL_MEMPROTL1D_MPFSR_SR_SHIFT (0x00000005u) #define CSL_MEMPROTL1D_MPFSR_SR_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_SW_MASK (0x00000010u) #define CSL_MEMPROTL1D_MPFSR_SW_SHIFT (0x00000004u) #define CSL_MEMPROTL1D_MPFSR_SW_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_UR_MASK (0x00000004u) #define CSL_MEMPROTL1D_MPFSR_UR_SHIFT (0x00000002u) #define CSL_MEMPROTL1D_MPFSR_UR_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_UW_MASK (0x00000002u) #define CSL_MEMPROTL1D_MPFSR_UW_SHIFT (0x00000001u) #define CSL_MEMPROTL1D_MPFSR_UW_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPFSR_RESETVAL (0x00000000u) /* MPFCR */ #define CSL_MEMPROTL1D_MPFCR_MPFCLR_MASK (0x00000001u) #define CSL_MEMPROTL1D_MPFCR_MPFCLR_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPFCR_MPFCLR_RESETVAL (0x00000000u) /*----MPFCLR Tokens----*/ #define CSL_MEMPROTL1D_MPFCR_MPFCLR_CLEAR (0x00000001u) #define CSL_MEMPROTL1D_MPFCR_RESETVAL (0x00000000u) /* MPLK0 */ #define CSL_MEMPROTL1D_MPLK0_RESERVED_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPLK0_RESERVED_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLK0_RESERVED_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPLK0_RESETVAL (0x00000000u) /* MPLK1 */ #define CSL_MEMPROTL1D_MPLK1_RESERVED_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPLK1_RESERVED_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLK1_RESERVED_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPLK1_RESETVAL (0x00000000u) /* MPLK2 */ #define CSL_MEMPROTL1D_MPLK2_RESERVED_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPLK2_RESERVED_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLK2_RESERVED_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPLK2_RESETVAL (0x00000000u) /* MPLK3 */ #define CSL_MEMPROTL1D_MPLK3_RESERVED_MASK (0xFFFFFFFFu) #define CSL_MEMPROTL1D_MPLK3_RESERVED_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLK3_RESERVED_RESETVAL (0x00000000u) #define CSL_MEMPROTL1D_MPLK3_RESETVAL (0x00000000u) /* MPLKCMD */ #define CSL_MEMPROTL1D_MPLKCMD_KEYR_MASK (0x00000004u) #define CSL_MEMPROTL1D_MPLKCMD_KEYR_SHIFT (0x00000002u) #define CSL_MEMPROTL1D_MPLKCMD_KEYR_RESETVAL (0x00000000u) /*----KEYR Tokens----*/ #define CSL_MEMPROTL1D_MPLKCMD_KEYR_YES (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_KEYR_NO (0x00000000u) #define CSL_MEMPROTL1D_MPLKCMD_LOCK_MASK (0x00000002u) #define CSL_MEMPROTL1D_MPLKCMD_LOCK_SHIFT (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_LOCK_RESETVAL (0x00000000u) /*----LOCK Tokens----*/ #define CSL_MEMPROTL1D_MPLKCMD_LOCK_YES (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_LOCK_NO (0x00000000u) #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_MASK (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_RESETVAL (0x00000000u) /*----UNLOCK Tokens----*/ #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_YES (0x00000001u) #define CSL_MEMPROTL1D_MPLKCMD_UNLOCK_NO (0x00000000u) #define CSL_MEMPROTL1D_MPLKCMD_RESETVAL (0x00000000u) /* MPLKSTAT */ #define CSL_MEMPROTL1D_MPLKSTAT_LK_MASK (0x00000001u) #define CSL_MEMPROTL1D_MPLKSTAT_LK_SHIFT (0x00000000u) #define CSL_MEMPROTL1D_MPLKSTAT_LK_RESETVAL (0x00000000u) /*----LK Tokens----*/ #define CSL_MEMPROTL1D_MPLKSTAT_LK_YES (0x00000001u) #define CSL_MEMPROTL1D_MPLKSTAT_LK_NO (0x00000000u) #define CSL_MEMPROTL1D_MPLKSTAT_RESETVAL (0x00000000u) /* MPPA */ #define CSL_MEMPROTL1D_MPPA_AID5_MASK (0x00008000u) #define CSL_MEMPROTL1D_MPPA_AID5_SHIFT (0x0000000Fu) #define CSL_MEMPROTL1D_MPPA_AID5_RESETVAL (0x00000001u) /*----AID5 Tokens----*/ #define CSL_MEMPROTL1D_MPPA_AID5_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID5_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID4_MASK (0x00004000u) #define CSL_MEMPROTL1D_MPPA_AID4_SHIFT (0x0000000Eu) #define CSL_MEMPROTL1D_MPPA_AID4_RESETVAL (0x00000001u) /*----AID4 Tokens----*/ #define CSL_MEMPROTL1D_MPPA_AID4_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID4_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID3_MASK (0x00002000u) #define CSL_MEMPROTL1D_MPPA_AID3_SHIFT (0x0000000Du) #define CSL_MEMPROTL1D_MPPA_AID3_RESETVAL (0x00000001u) /*----AID3 Tokens----*/ #define CSL_MEMPROTL1D_MPPA_AID3_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID3_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID2_MASK (0x00001000u) #define CSL_MEMPROTL1D_MPPA_AID2_SHIFT (0x0000000Cu) #define CSL_MEMPROTL1D_MPPA_AID2_RESETVAL (0x00000001u) /*----AID2 Tokens----*/ #define CSL_MEMPROTL1D_MPPA_AID2_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID2_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID1_MASK (0x00000800u) #define CSL_MEMPROTL1D_MPPA_AID1_SHIFT (0x0000000Bu) #define CSL_MEMPROTL1D_MPPA_AID1_RESETVAL (0x00000001u) /*----AID1 Tokens----*/ #define CSL_MEMPROTL1D_MPPA_AID1_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID1_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_AID0_MASK (0x00000400u) #define CSL_MEMPROTL1D_MPPA_AID0_SHIFT (0x0000000Au) #define CSL_MEMPROTL1D_MPPA_AID0_RESETVAL (0x00000001u) /*----AID0 Tokens----*/ #define CSL_MEMPROTL1D_MPPA_AID0_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_AID0_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_ADX_MASK (0x00000200u) #define CSL_MEMPROTL1D_MPPA_ADX_SHIFT (0x00000009u) #define CSL_MEMPROTL1D_MPPA_ADX_RESETVAL (0x00000001u) /*----ADX Tokens----*/ #define CSL_MEMPROTL1D_MPPA_ADX_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_ADX_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_LOCAL_MASK (0x00000100u) #define CSL_MEMPROTL1D_MPPA_LOCAL_SHIFT (0x00000008u) #define CSL_MEMPROTL1D_MPPA_LOCAL_RESETVAL (0x00000001u) /*----LOCAL Tokens----*/ #define CSL_MEMPROTL1D_MPPA_LOCAL_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_LOCAL_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_SR_MASK (0x00000020u) #define CSL_MEMPROTL1D_MPPA_SR_SHIFT (0x00000005u) #define CSL_MEMPROTL1D_MPPA_SR_RESETVAL (0x00000001u) /*----SR Tokens----*/ #define CSL_MEMPROTL1D_MPPA_SR_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_SR_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_SW_MASK (0x00000010u) #define CSL_MEMPROTL1D_MPPA_SW_SHIFT (0x00000004u) #define CSL_MEMPROTL1D_MPPA_SW_RESETVAL (0x00000001u) /*----SW Tokens----*/ #define CSL_MEMPROTL1D_MPPA_SW_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_SW_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_UR_MASK (0x00000004u) #define CSL_MEMPROTL1D_MPPA_UR_SHIFT (0x00000002u) #define CSL_MEMPROTL1D_MPPA_UR_RESETVAL (0x00000001u) /*----UR Tokens----*/ #define CSL_MEMPROTL1D_MPPA_UR_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_UR_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_UW_MASK (0x00000002u) #define CSL_MEMPROTL1D_MPPA_UW_SHIFT (0x00000001u) #define CSL_MEMPROTL1D_MPPA_UW_RESETVAL (0x00000001u) /*----UW Tokens----*/ #define CSL_MEMPROTL1D_MPPA_UW_NO (0x00000000u) #define CSL_MEMPROTL1D_MPPA_UW_YES (0x00000001u) #define CSL_MEMPROTL1D_MPPA_RESETVAL (0x0000FFF6u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_pllcAux.h

<filename>DSP/TI-Header/csl_c6455_src/inc/csl_pllcAux.h /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** @file csl_pllcAux.h * * @brief API Auxilary header file for PLLC CSL. * * Path: \(CSLPATH)\inc */ /* ============================================================================ * Revision History * =============== * 10-Feb-2004 kpn File Created. * 25-Aug-2005 Tej File Modified. * 27-oct-2005 sd changes for multiplier configuration * 18-Jan-2006 sd Changes according to spec changes * ============================================================================ */ #ifndef _CSL_PPLCAUX_H_ #define _CSL_PLLCAUX_H_ #include <csl_pllc.h> #ifdef __cplusplus extern "C" { #endif /* * Status command functions of the pllc */ /** ============================================================================ * @n@b CSL_pllcGetStatus * * @b Description * @n Gets the Status of the pll controller. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance @endverbatim * * Return Value * @n CSL_BitMask32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 response; ... response = CSL_pllcGetStatus (hPllc); @endverbatim * ============================================================================ */ CSL_IDEF_INLINE CSL_BitMask32 CSL_pllcGetStatus ( CSL_PllcHandle hPllc ) { CSL_BitMask32 response; response = (CSL_BitMask32) hPllc->regs->PLLSTAT; return response; } /* * Status command functions of the pllc */ /** ============================================================================ * @n@b CSL_pllcGetSysClkStatus * * @b Description * @n Gets the System Clock ON/OFF Status of the pllc. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance @endverbatim * * Return Value * @n CSL_BitMask32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 response; ... response = CSL_pllcGetSysClkStatus (hPllc); @endverbatim * ============================================================================ */ CSL_IDEF_INLINE CSL_BitMask32 CSL_pllcGetSysClkStatus ( CSL_PllcHandle hPllc ) { CSL_BitMask32 response; response = (CSL_BitMask32) hPllc->regs->SYSTAT; return response; } /* * Status command functions of the pllc */ /** ============================================================================ * @n@b CSL_pllcGetResetStatus * * @b Description * @n Gets the Reset Type Status of the pllc. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance @endverbatim * * Return Value * @n CSL_BitMask32 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 response; ... response = CSL_pllcGetResetStatus (hPllc); @endverbatim * ============================================================================ */ CSL_IDEF_INLINE CSL_BitMask32 CSL_pllcGetResetStatus ( CSL_PllcHandle hPllc ) { CSL_BitMask32 response; response = (Uint32) hPllc->regs->RSTYPE; return response; } /* * Control command functions of the pllc */ /** ============================================================================ * @n@b CSL_pllcCommandCtrl * * @b Description * Controls the pllc operation. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc PLLCMD register status Status variable @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n pllc operation is controlled according to value set. * * @b Modifies * @n pllc PLLCMD register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 loadVal; CSL_Status status ... CSL_pllcCommandCtrl (hPllc, loadVal, &status); @endverbatim * ============================================================================ */ CSL_IDEF_INLINE void CSL_pllcCommandCtrl ( CSL_PllcHandle hPllc, CSL_BitMask32 loadVal, CSL_Status *status ) { if (hPllc->pllcNum == CSL_PLLC_1) { hPllc->regs->PLLCTL = (loadVal & 0xFFFF); loadVal = (loadVal & 0xFFFF0000)>>16; if (loadVal) hPllc->regs->PLLCMD = loadVal; } else if (hPllc->pllcNum == CSL_PLLC_2) { loadVal = (loadVal & 0xFFFF0000)>>16; if (loadVal) hPllc->regs->PLLCMD = loadVal; } else *status = CSL_ESYS_INVPARAMS; } /** ============================================================================ * @n@b CSL_pllcMultiplierCtrl * * @b Description * Controls the pllc Multiplier. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc PLLM register status Status variable @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n pllc multiplier is controlled accordingly. * * @b Modifies * @n pllc PLLM register. * * @b Example * @verbatim CSL_PllcHandle hPllc; Uint32 loadVal; CSL_Status status ... CSL_pllcMultiplierCtrl (hPllc, loadVal, &status); @endverbatim * ============================================================================ */ CSL_IDEF_INLINE void CSL_pllcMultiplierCtrl ( CSL_PllcHandle hPllc, Uint32 loadVal, CSL_Status *status ) { if (hPllc->pllcNum == CSL_PLLC_1) CSL_FINS (hPllc->regs->PLLM, PLLC_PLLM_PLLM, loadVal - 1); else *status = CSL_ESYS_INVPARAMS; } /** ============================================================================ * @n@b CSL_pllcSetPLLDivRatio * * @b Description * Sets the pllc Dividers ratios. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc divider registers status Status variable @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n pllc dividers ratios are set. * * @b Modifies * @n pllc divider registers. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcDivRatio loadVal; CSL_Status status; ... CSL_pllcSetPLLDivRatio (hPllc, loadVal, &status); @endverbatim * ============================================================================ */ CSL_IDEF_INLINE void CSL_pllcSetPLLDivRatio ( CSL_PllcHandle hPllc, CSL_PllcDivRatio loadVal, CSL_Status *status ) { switch (loadVal.divNum) { case CSL_PLLC_DIVSEL_PLLDIV1: if (hPllc->pllcNum == CSL_PLLC_2) { CSL_FINS (hPllc->regs->PLLDIV1, PLLC_PLLDIV1_RATIO, (Uint32)loadVal.divRatio - 1); } else *status = CSL_ESYS_INVPARAMS; break; case CSL_PLLC_DIVSEL_PLLDIV4: if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLDIV4, PLLC_PLLDIV4_RATIO, (Uint32)loadVal.divRatio - 1); } else *status = CSL_ESYS_INVPARAMS; break; case CSL_PLLC_DIVSEL_PLLDIV5: if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLDIV5, PLLC_PLLDIV5_RATIO, (Uint32)loadVal.divRatio - 1); } else *status = CSL_ESYS_INVPARAMS; break; default: *status = CSL_ESYS_INVPARAMS; break; } } /** ============================================================================ * @n@b CSL_pllcPLLDivCtrl * * @b Description * Controls the pllc dividers. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc dividers register. status Status variable @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n pllc dividers are controlled. * * @b Modifies * @n pllc dividers register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcDivideControl loadVal; CSL_Status status; ... CSL_pllcPLLDivCtrl (hPllc, loadVal, &status); @endverbatim * ============================================================================ */ CSL_IDEF_INLINE void CSL_pllcPLLDivCtrl ( CSL_PllcHandle hPllc, CSL_PllcDivideControl loadVal, CSL_Status *status ) { switch (loadVal.divNum) { case CSL_PLLC_DIVSEL_PLLDIV1: if (hPllc->pllcNum == CSL_PLLC_2) { CSL_FINS (hPllc->regs->PLLDIV1, PLLC_PLLDIV1_D1EN, (CSL_PllcDivCtrl)loadVal.divCtrl); } else *status = CSL_ESYS_INVPARAMS; break; case CSL_PLLC_DIVSEL_PLLDIV4: if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLDIV4, PLLC_PLLDIV4_D4EN, (CSL_PllcDivCtrl)loadVal.divCtrl); } else *status = CSL_ESYS_INVPARAMS; break; case CSL_PLLC_DIVSEL_PLLDIV5: if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLDIV5, PLLC_PLLDIV5_D5EN, (CSL_PllcDivCtrl)loadVal.divCtrl); } else *status = CSL_ESYS_INVPARAMS; break; default: *status = CSL_ESYS_INVPARAMS; break; } } #ifdef __cplusplus } #endif #endif /* _CSL_PLLCAUX_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_edma3.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_edma3.h * * @path $(CSLPATH)\inc * * @desc Header file for functional layer CSL of EDMA * */ /** @mainpage EDMA3 * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to detail the CSL APIs for the EDMA3 * Module. The CSL developer is expected to refer to this document * while designing APIs for the modules which use Edma module. Some of the * listed APIs may not be applicable to a given module. While other cases * this list of APIs may not be sufficient to cover all the features required * for a particular Module. The CSL developer should use his discretion * designing new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * -# EDMA: Enhanced Direct Memory Access * * @subsection References * -# CSL 3.x Technical Requirements Specifications Version 0.5, dated * May 14th, 2003 * -# EDMA Channel Controller Specification (Revision 3.0.2) * -# EDMA Transfer Controller Specification (Revision 3.0.1) * * @subsection Assumptions * The abbreviations EDMA, edma and Edma have been used throughout this * document to refer to Enhanced Direct Memory Access. */ /* ============================================================================= * Revision History * =============== * 29-May-2004 <NAME> File Created. * * ============================================================================= */ #ifndef _CSL_EDMA3_H_ #define _CSL_EDMA3_H_ #ifdef __cplusplus extern "C" { #endif #include <csl.h> #include <soc.h> #include <cslr_edma3cc.h> /* EDMA Symbols Defined */ /** Link to a Null Param set */ #define CSL_EDMA3_LINK_NULL 0xFFFF /** Link to a Null Param set */ #define CSL_EDMA3_LINK_DEFAULT 0xFFFF /** A synchronized transfer */ #define CSL_EDMA3_SYNC_A 0 /** AB synchronized transfer */ #define CSL_EDMA3_SYNC_AB 1 /** Normal Completion */ #define CSL_EDMA3_TCC_NORMAL 0 /** Early Completion */ #define CSL_EDMA3_TCC_EARLY 1 /** Only for ease */ #define CSL_EDMA3_FIFOWIDTH_NONE 0 /** 8 bit FIFO Width */ #define CSL_EDMA3_FIFOWIDTH_8BIT 0 /** 16 bit FIFO Width */ #define CSL_EDMA3_FIFOWIDTH_16BIT 1 /** 32 bit FIFO Width */ #define CSL_EDMA3_FIFOWIDTH_32BIT 2 /** 64 bit FIFO Width */ #define CSL_EDMA3_FIFOWIDTH_64BIT 3 /** 128 bit FIFO Width */ #define CSL_EDMA3_FIFOWIDTH_128BIT 4 /** 256 bit FIFO Width */ #define CSL_EDMA3_FIFOWIDTH_256BIT 5 /** Address Mode is incremental */ #define CSL_EDMA3_ADDRMODE_INCR 0 /** Address Mode is such it wraps around after reaching FIFO width */ #define CSL_EDMA3_ADDRMODE_CONST 1 /* Bitwise OR of the below symbols are used for setting the Memory attributes These are defined only if the Memory Protection feature exists */ #if CSL_EDMA3_MEMPROTECT /** User Execute permission */ #define CSL_EDMA3_MEMACCESS_UX 0x0001 /** User Write permission */ #define CSL_EDMA3_MEMACCESS_UW 0x0002 /** User Read permission */ #define CSL_EDMA3_MEMACCESS_UR 0x0004 /** Supervisor Execute permission */ #define CSL_EDMA3_MEMACCESS_SX 0x0008 /** Supervisor Write permission */ #define CSL_EDMA3_MEMACCESS_SW 0x0010 /** Supervisor Read permission */ #define CSL_EDMA3_MEMACCESS_SR 0x0020 /** External Allowed ID. Requests with PrivID >= '6' are permitted * if access type is allowed */ #define CSL_EDMA3_MEMACCESS_EXT 0x0200 /** Allowed ID '0' */ #define CSL_EDMA3_MEMACCESS_AID0 0x0400 /** Allowed ID '1' */ #define CSL_EDMA3_MEMACCESS_AID1 0x0800 /** Allowed ID '2' */ #define CSL_EDMA3_MEMACCESS_AID2 0x1000 /** Allowed ID '3' */ #define CSL_EDMA3_MEMACCESS_AID3 0x2000 /** Allowed ID '4' */ #define CSL_EDMA3_MEMACCESS_AID4 0x4000 /** Allowed ID '5' */ #define CSL_EDMA3_MEMACCESS_AID5 0x8000 #endif /** Intermediate transfer completion interrupt enable */ #define CSL_EDMA3_ITCINT_EN 1 /** Intermediate transfer completion interrupt disable */ #define CSL_EDMA3_ITCINT_DIS 0 /** Intermediate transfer completion chaining enable */ #define CSL_EDMA3_ITCCH_EN 1 /** Intermediate transfer completion chaining disable */ #define CSL_EDMA3_ITCCH_DIS 0 /** Transfer completion interrupt enable */ #define CSL_EDMA3_TCINT_EN 1 /** Transfer completion interrupt disable */ #define CSL_EDMA3_TCINT_DIS 0 /** Transfer completion chaining enable */ #define CSL_EDMA3_TCCH_EN 1 /** Transfer completion chaining disable */ #define CSL_EDMA3_TCCH_DIS 0 /** Enable Static */ #define CSL_EDMA3_STATIC_EN 1 /** Disable Static */ #define CSL_EDMA3_STATIC_DIS 0 /** Last trigger word in a QDMA parameter set */ #define CSL_EDMA3_TRIGWORD_DEFAULT 7 /** Trigger word option field */ #define CSL_EDMA3_TRIGWORD_OPT 0 /** Trigger word source */ #define CSL_EDMA3_TRIGWORD_SRC 1 /** Trigger word AB count */ #define CSL_EDMA3_TRIGWORD_A_B_CNT 2 /** Trigger word destination */ #define CSL_EDMA3_TRIGWORD_DST 3 /** Trigger word src and dst B index */ #define CSL_EDMA3_TRIGWORD_SRC_DST_BIDX 4 /** Trigger word B count reload */ #define CSL_EDMA3_TRIGWORD_LINK_BCNTRLD 5 /** Trigger word src and dst C index */ #define CSL_EDMA3_TRIGWORD_SRC_DST_CIDX 6 /** Trigger word C count */ #define CSL_EDMA3_TRIGWORD_CCNT 7 /** Used for creating the options entry in the parameter ram */ #define CSL_EDMA3_OPT_MAKE(itcchEn, tcchEn, itcintEn, tcintEn, tcc, tccMode, \ fwid, stat, syncDim, dam, sam) \ (Uint32)(\ CSL_FMKR(23,23,itcchEn) \ |CSL_FMKR(22,22,tcchEn) \ |CSL_FMKR(21,21,itcintEn) \ |CSL_FMKR(20,20,tcintEn) \ |CSL_FMKR(17,12,tcc) \ |CSL_FMKR(11,11,tccMode) \ |CSL_FMKR(10,8,fwid) \ |CSL_FMKR(3,3,stat) \ |CSL_FMKR(2,2,syncDim) \ |CSL_FMKR(1,1,dam) \ |CSL_FMKR(0,0,sam)) /** Used for creating the A,B Count entry in the parameter ram */ #define CSL_EDMA3_CNT_MAKE(aCnt,bCnt) \ (Uint32)(\ CSL_FMK(EDMA3CC_A_B_CNT_ACNT,aCnt) \ |CSL_FMK(EDMA3CC_A_B_CNT_BCNT,bCnt)\ ) /** Used for creating the link and B count reload entry in the parameter ram */ #define CSL_EDMA3_LINKBCNTRLD_MAKE(link,bCntRld) \ (Uint32)(\ CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK,(Uint32)link) \ |CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD,bCntRld)\ ) /** Used for creating the B index entry in the parameter ram */ #define CSL_EDMA3_BIDX_MAKE(src,dst) \ (Uint32)(\ CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX,(Uint32)dst) \ |CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX,(Uint32)src)\ ) /** Used for creating the C index entry in the parameter ram */ #define CSL_EDMA3_CIDX_MAKE(src,dst) \ (Uint32)(\ CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX,(Uint32)dst) \ |CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX,(Uint32)src)\ ) /** DMA Channel Setup */ #define CSL_EDMA3_DMACHANNELSETUP_DEFAULT { \ {CSL_EDMA3_QUE_0,0}, \ {CSL_EDMA3_QUE_0,1}, \ {CSL_EDMA3_QUE_0,2}, \ {CSL_EDMA3_QUE_0,3}, \ {CSL_EDMA3_QUE_0,4}, \ {CSL_EDMA3_QUE_0,5}, \ {CSL_EDMA3_QUE_0,6}, \ {CSL_EDMA3_QUE_0,7}, \ {CSL_EDMA3_QUE_0,8}, \ {CSL_EDMA3_QUE_0,9}, \ {CSL_EDMA3_QUE_0,10}, \ {CSL_EDMA3_QUE_0,11}, \ {CSL_EDMA3_QUE_0,12}, \ {CSL_EDMA3_QUE_0,13}, \ {CSL_EDMA3_QUE_0,14}, \ {CSL_EDMA3_QUE_0,15}, \ {CSL_EDMA3_QUE_0,16}, \ {CSL_EDMA3_QUE_0,17}, \ {CSL_EDMA3_QUE_0,18}, \ {CSL_EDMA3_QUE_0,19}, \ {CSL_EDMA3_QUE_0,20}, \ {CSL_EDMA3_QUE_0,21}, \ {CSL_EDMA3_QUE_0,22}, \ {CSL_EDMA3_QUE_0,23}, \ {CSL_EDMA3_QUE_0,24}, \ {CSL_EDMA3_QUE_0,25}, \ {CSL_EDMA3_QUE_0,26}, \ {CSL_EDMA3_QUE_0,27}, \ {CSL_EDMA3_QUE_0,28}, \ {CSL_EDMA3_QUE_0,29}, \ {CSL_EDMA3_QUE_0,30}, \ {CSL_EDMA3_QUE_0,31}, \ {CSL_EDMA3_QUE_0,32}, \ {CSL_EDMA3_QUE_0,33}, \ {CSL_EDMA3_QUE_0,34}, \ {CSL_EDMA3_QUE_0,35}, \ {CSL_EDMA3_QUE_0,36}, \ {CSL_EDMA3_QUE_0,37}, \ {CSL_EDMA3_QUE_0,38}, \ {CSL_EDMA3_QUE_0,39}, \ {CSL_EDMA3_QUE_0,40}, \ {CSL_EDMA3_QUE_0,41}, \ {CSL_EDMA3_QUE_0,42}, \ {CSL_EDMA3_QUE_0,43}, \ {CSL_EDMA3_QUE_0,44}, \ {CSL_EDMA3_QUE_0,45}, \ {CSL_EDMA3_QUE_0,46}, \ {CSL_EDMA3_QUE_0,47}, \ {CSL_EDMA3_QUE_0,48}, \ {CSL_EDMA3_QUE_0,49}, \ {CSL_EDMA3_QUE_0,50}, \ {CSL_EDMA3_QUE_0,51}, \ {CSL_EDMA3_QUE_0,52}, \ {CSL_EDMA3_QUE_0,53}, \ {CSL_EDMA3_QUE_0,54}, \ {CSL_EDMA3_QUE_0,55}, \ {CSL_EDMA3_QUE_0,56}, \ {CSL_EDMA3_QUE_0,57}, \ {CSL_EDMA3_QUE_0,58}, \ {CSL_EDMA3_QUE_0,59}, \ {CSL_EDMA3_QUE_0,60}, \ {CSL_EDMA3_QUE_0,61}, \ {CSL_EDMA3_QUE_0,62}, \ {CSL_EDMA3_QUE_0,63} \ } /** QDMA Channel Setup */ #define CSL_EDMA3_QDMACHANNELSETUP_DEFAULT { \ {CSL_EDMA3_QUE_0,64,CSL_EDMA3_TRIGWORD_DEFAULT}, \ {CSL_EDMA3_QUE_0,65,CSL_EDMA3_TRIGWORD_DEFAULT}, \ {CSL_EDMA3_QUE_0,66,CSL_EDMA3_TRIGWORD_DEFAULT}, \ {CSL_EDMA3_QUE_0,67,CSL_EDMA3_TRIGWORD_DEFAULT} \ } /** @brief Enumeration for System priorities * * This is used for Setting up the Que Priority level */ typedef enum { /** System priority level 0 */ CSL_EDMA3_QUE_PRI_0 = 0, /** System priority level 1 */ CSL_EDMA3_QUE_PRI_1 = 1, /** System priority level 2 */ CSL_EDMA3_QUE_PRI_2 = 2, /** System priority level 3 */ CSL_EDMA3_QUE_PRI_3 = 3, /** System priority level 4 */ CSL_EDMA3_QUE_PRI_4 = 4, /** System priority level 5 */ CSL_EDMA3_QUE_PRI_5 = 5, /** System priority level 6 */ CSL_EDMA3_QUE_PRI_6 = 6, /** System priority level 7 */ CSL_EDMA3_QUE_PRI_7 = 7 }CSL_Edma3QuePri; /** @brief Enumeration for EDMA Que Thresholds * * This is used for Setting up the Que thresholds */ typedef enum { /** EDMA Que Threshold 0 */ CSL_EDMA3_QUE_THR_0 = 0, /** EDMA Que Threshold 1 */ CSL_EDMA3_QUE_THR_1 = 1, /** EDMA Que Threshold 2 */ CSL_EDMA3_QUE_THR_2 = 2, /** EDMA Que Threshold 3 */ CSL_EDMA3_QUE_THR_3 = 3, /** EDMA Que Threshold 4 */ CSL_EDMA3_QUE_THR_4 = 4, /** EDMA Que Threshold 5 */ CSL_EDMA3_QUE_THR_5 = 5, /** EDMA Que Threshold 6 */ CSL_EDMA3_QUE_THR_6 = 6, /** EDMA Que Threshold 7 */ CSL_EDMA3_QUE_THR_7 = 7, /** EDMA Que Threshold 8 */ CSL_EDMA3_QUE_THR_8 = 8, /** EDMA Que Threshold 9 */ CSL_EDMA3_QUE_THR_9 = 9, /** EDMA Que Threshold 10 */ CSL_EDMA3_QUE_THR_10 = 10, /** EDMA Que Threshold 11 */ CSL_EDMA3_QUE_THR_11 = 11, /** EDMA Que Threshold 12 */ CSL_EDMA3_QUE_THR_12 = 12, /** EDMA Que Threshold 13 */ CSL_EDMA3_QUE_THR_13 = 13, /** EDMA Que Threshold 14 */ CSL_EDMA3_QUE_THR_14 = 14, /** EDMA Que Threshold 15 */ CSL_EDMA3_QUE_THR_15 = 15, /** EDMA Que Threshold 16 */ CSL_EDMA3_QUE_THR_16 = 16, /* EDMA Que Threshold Disable Errors */ CSL_EDMA3_QUE_THR_DISABLE = 17 }CSL_Edma3QueThr; /** MODULE Level Commands */ typedef enum { #if CSL_EDMA3_MEMPROTECT /** * @brief Programmation of MPPAG,MPPA[0-7] attributes * * @param (CSL_Edma3CmdRegion *) */ CSL_EDMA3_CMD_MEMPROTECT_SET, /** * @brief Clear Memory Fault * * @param (None) */ CSL_EDMA3_CMD_MEMFAULT_CLEAR, #endif /** * @brief Enables bits as specified in the argument passed in * DRAE/DRAEH. Please note:If bits are already set in * DRAE/DRAEH this Control command will cause additional bits * (as specified by the bitmask) to be set and does * @param (CSL_Edma3CmdDrae *) */ CSL_EDMA3_CMD_DMAREGION_ENABLE, /** * @brief Disables bits as specified in the argument passed in * DRAE/DRAEH * @param (CSL_Edma3CmdDrae *) */ CSL_EDMA3_CMD_DMAREGION_DISABLE, /** * @brief Enables bits as specified in the argument * passed in QRAE.Pleasenote:If bits are already set in * QRAE/QRAEH this Control command will cause additional bits * (as specified by the bitmask) to be set and does * @param (CSL_Edma3CmdQrae *) */ CSL_EDMA3_CMD_QDMAREGION_ENABLE, /** * @brief Disables bits as specified in the argument passed in QRAE * DRAE/DRAEH * @param (CSL_Edma3CmdQrae *) */ CSL_EDMA3_CMD_QDMAREGION_DISABLE, /** * @brief Programmation of QUEPRI register with the specified priority * DRAE/DRAEH * @param (CSL_Edma3CmdQuePri *) */ CSL_EDMA3_CMD_QUEPRIORITY_SET, /** * @brief Programmation of QUE Threshold levels * * @param (CSL_Edma3CmdQueThr *) */ CSL_EDMA3_CMD_QUETHRESHOLD_SET, /** * @brief Sets the EVAL bit in the EEVAL register * * @param (None) */ CSL_EDMA3_CMD_ERROR_EVAL, /** * @brief Clears specified (Bitmask)pending interrupt at Module/Region * Level * @param (CSL_Edma3CmdIntr *) */ CSL_EDMA3_CMD_INTRPEND_CLEAR, /** * @brief Enables specified interrupts(BitMask) at Module/Region Level * * @param (CSL_Edma3CmdIntr *) */ CSL_EDMA3_CMD_INTR_ENABLE, /** * @brief Disables specified interrupts(BitMask) at Module/Region * Level * @param (CSL_Edma3CmdIntr *) */ CSL_EDMA3_CMD_INTR_DISABLE, /** * @brief Interrupt Evaluation asserted for the Module/Region * * @param (Int *) */ CSL_EDMA3_CMD_INTR_EVAL, /** * @brief Clear the EDMA Controller Erorr * * @param (CSL_Edma3CtrlErrStat *) */ CSL_EDMA3_CMD_CTRLERROR_CLEAR , /** * @brief Pointer to an array of 3 elements, where element0 refers to * the EMR register to be cleared, element1 refers to the EMRH * register to be cleared, element2 refers to the QEMR register * to be cleared. * @param (CSL_BitMask32 *) */ CSL_EDMA3_CMD_EVENTMISSED_CLEAR } CSL_Edma3HwControlCmd; /** @brief MODULE Level Queries */ typedef enum { #if CSL_EDMA3_MEMPROTECT /** * @brief Return the Memory fault details * * @param (CSL_Edma3MemFaultStat *) */ CSL_EDMA3_QUERY_MEMFAULT, /** * @brief Return memory attribute of the specified region * * @param (CSL_Edma3CmdRegion *) */ CSL_EDMA3_QUERY_MEMPROTECT, #endif /** * @brief Return Controller Error * * @param (CSL_Edma3CtrlErrStat *) */ CSL_EDMA3_QUERY_CTRLERROR, /** * @brief Return pend status of specified interrupt * * @param (CSL_Edma3CmdIntr *) */ CSL_EDMA3_QUERY_INTRPEND, /** * @brief Returns Miss Status of all Channels * Pointer to an array of 3 elements, where element0 refers to * the EMR registr, element1 refers to the EMRH register, * element2 refers to the QEMR register * @param (CSL_BitMask32 *) */ CSL_EDMA3_QUERY_EVENTMISSED, /** * @brief Returns the Que status * * @param (CSL_Edma3QueStat *) */ CSL_EDMA3_QUERY_QUESTATUS, /** * @brief Returns the Channel Controller Active Status * * @param (CSL_Edma3ActivityStat *) */ CSL_EDMA3_QUERY_ACTIVITY, /** * @brief Returns the Channel Controller Information viz. * Configuration, Revision Id * @param (CSL_Edma3QueryInfo *) */ CSL_EDMA3_QUERY_INFO } CSL_Edma3HwStatusQuery; /** @brief CHANNEL Commands */ typedef enum { /** * @brief Enables specified Channel * * @param (None) */ CSL_EDMA3_CMD_CHANNEL_ENABLE, /** * @brief Disables specified Channel * * @param (None) */ CSL_EDMA3_CMD_CHANNEL_DISABLE, /** * @brief Manually sets the Channel Event,writes into ESR/ESRH * and not ER.NA for QDMA * @param (None) */ CSL_EDMA3_CMD_CHANNEL_SET, /** * @brief Manually clears the Channel Event, does not write into * ESR/ESRH or ER/ERH but the ECR/ECRH. NA for QDMA * @param (None) */ CSL_EDMA3_CMD_CHANNEL_CLEAR, /** * @brief In case of DMA channels clears SER/SERH(by writing into * SECR/SECRH if "secEvt" and "missed" are both TRUE) and * EMR/EMRH(by writing into EMCR/EMCRH if "missed" is TRUE). * In case of QDMA channels clears QSER(by writing into QSECR * if "ser" and "missed" are both TRUE) and QEMR(by writing * into QEMCR if "missed" is TRUE) * @param (CSL_Edma3ChannelErr *) */ CSL_EDMA3_CMD_CHANNEL_CLEARERR } CSL_Edma3HwChannelControlCmd; /** @brief CHANNEL Queries */ typedef enum { /** * @brief In case of DMA channels returns TRUE if ER/ERH is set, * In case of QDMA channels returns TRUE if QER is set * @param (Bool *) */ CSL_EDMA3_QUERY_CHANNEL_STATUS, /** * @brief In case of DMA channels,'missed' is set * to TRUE if EMR/EMRH is set, 'secEvt' is set to TRUE if * SER/SERH is set.In case of QDMA channels,'missed' is set to * TRUE if QEMR is set, 'secEvt' is set to TRUE if QSER is set. * It should be noted that if secEvt ONLY is set to TRUE it * may not be a valid error condition * @param (CSL_Edma3ChannelErr *) */ CSL_EDMA3_QUERY_CHANNEL_ERR } CSL_Edma3HwChannelStatusQuery; /** @brief Module specific context information. * This is a dummy handle. */ typedef void *CSL_Edma3Context; /** @brief Module Attributes specific information. * This is a dummy handle. */ typedef void *CSL_Edma3ModuleAttr; /** @brief This object contains the reference to the instance of Edma Module * opened using the @a CSL_edma3Open(). * * A pointer to this object is passed to all Edma Module level CSL APIs. */ typedef struct CSL_Edma3Obj { /** This is a pointer to the Edma Channel Controller registers of the module * requested */ CSL_Edma3ccRegsOvly regs; /** This is the instance of module number i.e CSL_EDMA3 */ CSL_InstNum instNum; } CSL_Edma3Obj; /** @brief EDMA handle */ typedef struct CSL_Edma3Obj *CSL_Edma3Handle; /** CSL Parameter Set Handle */ typedef volatile CSL_Edma3ccParamsetRegs *CSL_Edma3ParamHandle; /** @brief Edma ParamSetup Structure * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3ParamSetup(). * This structure is used to program the Param Set for EDMA/QDMA. * The macros can be used to assign values to the fields of the structure. * The setup structure should be setup using the macros provided OR * as per the bit descriptions in the user guide.. * */ typedef struct CSL_Edma3ParamSetup { /** Options */ Uint32 option; /** Specifies the source address */ Uint32 srcAddr; /** Lower 16 bits are A Count Upper 16 bits are B Count*/ Uint32 aCntbCnt; /** Specifies the destination address */ Uint32 dstAddr; /** Lower 16 bits are source b index Upper 16 bits are * destination b index */ Uint32 srcDstBidx; /** Lower 16 bits are link of the next param entry Upper 16 bits are * b count reload */ Uint32 linkBcntrld; /** Lower 16 bits are source c index Upper 16 bits are destination * c index */ Uint32 srcDstCidx; /** C count */ Uint32 cCnt; } CSL_Edma3ParamSetup; /** @brief Edma Object Structure * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3ChannelOpen() * The CSL_edma3ChannelOpen() updates all the members of the data structure * and returns the objects address as a @a #CSL_Edma3ChannelHandle. The * @a #CSL_Edma3ChannelHandle is used in all subsequent function calls. */ typedef struct CSL_Edma3ChannelObj { /** Pointer to the Edma Channel Controller module register * Overlay structure */ CSL_Edma3ccRegsOvly regs; /** Region number to which the channel belongs to */ Int region; /** EDMA instance whose channel is being requested */ Int edmaNum; /** Channel Number being requested */ Int chaNum; } CSL_Edma3ChannelObj; /** CSL Channel Handle * All channel level API calls must be made with this handle. */ typedef struct CSL_Edma3ChannelObj *CSL_Edma3ChannelHandle; #if CSL_EDMA3_MEMPROTECT /** @brief Edma Memory Protection Fault Error Status * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetMemoryFaultError() * / CSL_edma3GetHwStatus() with the relevant command. This is relevant only is * MPEXIST is present for a given device. */ typedef struct CSL_Edma3MemFaultStat { /** Memory Protection Fault Address */ Uint32 addr; /** Bit Mask of the Errors */ CSL_BitMask16 error; /** Faulted ID */ Uint16 fid; } CSL_Edma3MemFaultStat; #endif /** @brief Edma Controller Error Status. * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetControllerError() * /CSL_edma3GetHwStatus(). */ typedef struct CSL_Edma3CtrlErrStat { /** Bit Mask of the Que Threshold Errors */ CSL_BitMask16 error; /** Whether number of permissible outstanding Tcc's is exceeded */ Bool exceedTcc; } CSL_Edma3CtrlErrStat; /** @brief Edma Controller Information * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetInfo() * /CSL_edma3GetHwStatus(). */ typedef struct CSL_Edma3QueryInfo{ /** Revision/Periperhal id of the EDMA3 Channel Controller */ Uint32 revision; /** Channel Controller Configuration obtained from the CCCFG register */ Uint32 config; } CSL_Edma3QueryInfo; /** @brief Edma Channel Controller Activity Status * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetActivityStatus() * /CSL_edma3GetHwStatus(). */ typedef struct CSL_Edma3ActivityStat { /** Number of outstanding completion requests */ Uint16 outstandingTcc; /** BitMask of the que active in the Channel Controller */ CSL_BitMask16 queActive; /** Indicates if the Channel Controller is active at all */ Bool active; /** Indicates whether any QDMA events are active */ Bool qevtActive; /** Indicates whether any EDMA events are active */ Bool evtActive; /** Indicates whether the TR processing/submission logic is active*/ Bool trActive; } CSL_Edma3ActivityStat; /** @brief Edma Controller Que Status. * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetQueStatus() * /CSL_edma3GetHwStatus(). */ typedef struct CSL_Edma3QueStat { /** Input field: Event Que. This needs to be specified by the user * before invocation of the above API */ CSL_Edma3Que que; /** Output field: The number of valid entries in a queue has exceeded the * threshold specified in QWMTHRA has been exceeded */ Bool exceed; /** Output field: The most entries that have been in Que since reset/last * time the watermark was cleared */ Uint8 waterMark; /** Output field: Number of valid entries in Que N*/ Uint8 numVal; /** Output field: Start pointer/Head of the queue */ Uint8 startPtr; } CSL_Edma3QueStat; /** @brief Edma Control/Query Command Structure for querying region specific * attributes. * * An object of this type is allocated by the user and * its address is passed as a parameter to the * CSL_edma3GetHwStatus/CSL_edma3HwControl with the relevant command. */ typedef struct CSL_Edma3CmdRegion { /** Input field:- this field needs to be initialized by the user before * issuing the query/command */ Int region; /** Input/Output field:-this needs to be filled by the user in case * of issuing a COMMAND or it will be filled in by the CSL when * used with a QUERY */ CSL_BitMask32 regionVal; } CSL_Edma3CmdRegion; /** @brief Edma Control/Query Command Structure for querying qdma region access * enable attributes. * * An object of this type is allocated by the user and * its address is passed as a parameter to the * CSL_edma3GetHwStatus/CSL_edma3HwControl with the relevant command. */ typedef struct CSL_Edma3CmdQrae { /** this field needs to be initialized by the user before issuing * the query/command */ Int region; /** this needs to be filled by the user in case of issuing a * COMMAND or it will be filled in by the CSL when used with a QUERY */ CSL_BitMask32 qrae; } CSL_Edma3CmdQrae; /** @brief Edma Control/Query Control Command structure for issuing commands * for Interrupt related APIs * An object of this type is allocated by the user and * its address is passed to the Control API. */ typedef struct CSL_Edma3CmdIntr{ /** Input field:- this field needs to be initialized by the user before * issuing the query/command */ Int region; /** Input/Output field:- this needs to be filled by the user in case * of issuing a COMMAND or it will be filled in by the CSL when used with * a QUERY */ CSL_BitMask32 intr; /** Input/Output:- this needs to be filled by the user in case of issuing a * COMMAND or it will be filled in by the CSL when used with a QUERY */ CSL_BitMask32 intrh; } CSL_Edma3CmdIntr; /** @brief Edma Command Structure for setting region specific * attributes. * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetHwStatus * when */ typedef struct CSL_Edma3CmdDrae { /** this field needs to be initialiazed by the user before issuing * the command specifying the region for which attributes need to be set */ Int region; /** DRAE Setting for the region */ CSL_BitMask32 drae; /** DRAEH Setting for the region */ CSL_BitMask32 draeh; } CSL_Edma3CmdDrae; /** @brief Edma Command Structure used for setting Event Que priority level * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3HwControl API. */ typedef struct CSL_Edma3CmdQuePri { /** Specifies the Que that needs a priority change */ CSL_Edma3Que que; /** Que priority */ CSL_Edma3QuePri pri; } CSL_Edma3CmdQuePri; /** @brief Edma Command Structure used for setting Event Que threshold level * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3HwControl API. */ typedef struct CSL_Edma3CmdQueThr { /** Specifies the Que that needs a change in the threshold setting */ CSL_Edma3Que que; /** Que threshold setting */ CSL_Edma3QueThr threshold; } CSL_Edma3CmdQueThr; /** @brief This will have the base-address information for the module * instance */ typedef struct { /** Base-address of the peripheral registers */ CSL_Edma3ccRegsOvly regs; } CSL_Edma3ModuleBaseAddress; /** @brief Edma Channel parameter structure used for opening a channel */ typedef struct { /** Region Number */ Int regionNum; /** Channel number */ Int chaNum; } CSL_Edma3ChannelAttr; /** @brief Edma Channel Error . * * An object of this type is allocated by the user and * its address is passed as a parameter to the CSL_edma3GetChannelError() * /CSL_edma3GetHwStatus()/ CSL_edma3ChannelErrorClear() * /CSL_edma3HwChannelControl(). */ typedef struct CSL_Edma3ChannelErr { /** a TRUE indicates an event is missed on this channel. */ Bool missed; /** a TRUE indicates an event that no events on this channel will be * prioritized till this is cleared. This being TRUE does NOT necessarily * mean it is an error. ONLY if both missed and ser are set, this kind of * error need to be cleared. */ Bool secEvt; } CSL_Edma3ChannelErr; /** @brief QDMA Edma Channel Setup * * An array of such objects are allocated by the user and * address initialized in the CSL_Edma3HwSetup structure which is passed * CSL_edma3HwSetup() */ typedef struct CSL_Edma3HwQdmaChannelSetup { /** Que number for the channel */ CSL_Edma3Que que; /** Parameter set mapping for the channel. */ Uint16 paramNum; /** Trigger word for the QDMA channels. */ Uint8 triggerWord; } CSL_Edma3HwQdmaChannelSetup; /** @brief QDMA Edma Channel Setup * * An array of such objects are allocated by the user and * address initialized in the CSL_Edma3HwSetup structure which is passed * CSL_edma3HwSetup() */ typedef struct CSL_Edma3HwDmaChannelSetup { /** Que number for the channel */ CSL_Edma3Que que; #ifdef CSL_EDMA3_CHMAPEXIST /** Parameter set mapping for the channel. This may not be initialized * for Edma channels on devices that do not have CHMAPEXIST. */ Uint16 paramNum; #endif } CSL_Edma3HwDmaChannelSetup; /** @brief Edma Hw Setup Structure */ typedef struct { /** Edma Hw Channel setup */ CSL_Edma3HwDmaChannelSetup *dmaChaSetup; /** QEdma Hw Channel setup */ CSL_Edma3HwQdmaChannelSetup *qdmaChaSetup; } CSL_Edma3HwSetup; /**************************************************************************\ * EDMA global function declarations \**************************************************************************/ /* * ============================================================================= * @func CSL_edma3Init * * @desc * This is EDMA module's init function. This initializes the context Object * variables.Needs to be invoked before using EDMA module. * * @arg pContext * Context information for edma * * @ret CSL_Status * CSL_SOK - Always returns * * @eg * CSL_edma3Init (NULL); * ============================================================================= */ extern CSL_Status CSL_edma3Init ( CSL_Edma3Context *pContext ); /* *============================================================================ * @func CSL_edma3Open * * @desc * Returns a handle to the EDMA Module. This handle is further used * for invoking all module level control APIs.This call enables * the relocatability of code since the handle can be subsequently used for * Module level control commands rather than the usage of of the register * layer base address directly. * * @arg edmaObj * Pointer to the object to which a handle is returned. * * @arg edmaNum * Instance Number of the EDMA * * @arg param * Pointer to module specific parameters * * @arg status * pointer for returning status of the function call * * @ret CSL_Edma3Handle * Valid edma handle will be returned if status value is equal to * CSL_SOK * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); * * =========================================================================== */ extern CSL_Edma3Handle CSL_edma3Open ( CSL_Edma3Obj *edmaObj, CSL_InstNum edmaNum, CSL_Edma3ModuleAttr *attr, CSL_Status *status ); /* *============================================================================ * @func CSL_edma3Close * * @desc * The EDMA module handle is invalidated and in order to use the EDMA module * it needs to be opened again. * * @arg hEdma * Handle to the EDMA module * * @ret CSL_Status * CSL_SOK - Close successful * CSL_ESYS_BADHANDLE - Invalid handle * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Close Module CSL_edma3Close(hModule); * * =========================================================================== */ extern CSL_Status CSL_edma3Close ( CSL_Edma3Handle hEdma ); /* * ============================================================================= * @func CSL_edma3HwSetup * * @desc * Does a module level HW setup of EDMA. This programs the * Channel to Param mapping, Channel to Que map and the trigger * word (if applicable) of ALL channels (DMA, QDMA). * * @arg hMod * Edma Module Handle * * @arg setup * Pointer to hardware setup structure containing the setup parameters * of all DMA, QDMA channels. * * @ret CSL_Status * CSL_SOK - Hardware setup successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); ... * * =========================================================================== */ extern CSL_Status CSL_edma3HwSetup ( CSL_Edma3Handle hMod, CSL_Edma3HwSetup *setup ); /* * ============================================================================= * @func CSL_edma3GetHwSetup * * @desc * Obtains the module level HW setup of EDMA. This reads the * Channel to Param mapping.Channel to Que map and the trigger word * (if applicable) of ALL channels (DMA, QDMA) into the placeholder * provided by the user. * * @arg hMod * Edma Module Handle * * @arg setup * Pointer to the Module Setup structure * * @ret CSL_Status * CSL_SOK - Hardware setup successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Hardware structure is not * properly initialized * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup, gethwSetup; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Get Module Setup gethwSetup.dmaChaSetup = &getdmahwSetup[0]; gethwSetup.qdmaChaSetup = NULL; CSL_edma3GetHwSetup(hModule,&gethwSetup); ... * * =========================================================================== */ extern CSL_Status CSL_edma3GetHwSetup ( CSL_Edma3Handle hMod, CSL_Edma3HwSetup *setup ); /* * ============================================================================= * @func CSL_edma3HwControl * * @desc * Module level control commands are handled by this API. * * @arg hMod * Edma Module Handle * * @arg cmd * Module Command * * @arg cmdArg * Additional command arguments are passed to the API using this. * The CSL function type casts to the appropriate arguments type * depending on the cmd. * * @ret CSL_Status * CSL_SOK - Command execution successful. * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVCMD - Invalid command * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup, gethwSetup; CSL_Edma3CmdDrae regionAccess; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // DRAE Enable(Bits 0-15) for the Shadow Region 0. regionAccess.region = CSL_EDMA3_REGION_0 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); ... * * =========================================================================== */ extern CSL_Status CSL_edma3HwControl ( CSL_Edma3Handle hMod, CSL_Edma3HwControlCmd cmd, void *cmdArg ); /** ============================================================================ * @n@b CSL_edma3ccGetModuleBaseAddr * * @b Description * @n This function is used for getting the base-address of the peripheral * instance. This function will be called inside the @ CSL_edma3Open() * /CSL_edma3ChannelOpen() function call. * * Note: This function is open for re-implementing if the user wants to * modify the base address of the peripheral object to point to a different * location and there by allow CSL initiated write/reads into peripheral * MMR's go to an alternate location. * * @b Arguments * @verbatim edmaNum Specifies the instance of the edma to be opened. pAttr Module specific parameters. pBaseAddress Pointer to baseaddress structure containing base address details. @endverbatim * * Return Value CSL_Status * @li CSL_SOK Open call is successful * @li CSL_ESYS_FAIL The instance number is invalid. * * Pre Condition * @n None * * Post Condition * @n Base Address structure is populated * * @b Modifies * @li The status variable * @li Base address structure is modified. * * @b Example * @verbatim CSL_Status status; CSL_Edma3ModuleBaseAddress baseAddress; ... status = CSL_edma3ccGetModuleBaseAddr(CSL_EDMA3, NULL, &baseAddress); @endverbatim * =========================================================================== */ extern CSL_Status CSL_edma3ccGetModuleBaseAddr ( CSL_InstNum edmaNum, CSL_Edma3ModuleAttr *pAttr, CSL_Edma3ModuleBaseAddress *pBaseAddress ); /* * ============================================================================= * @n@b CSL_edma3GetHwStatus * * @desc * Module level queries to the EDMA module are handled through this API * * @arg hMod * Edma Module Handle * * @arg myQuery * Query to be performed. * * @arg response * Pointer to buffer to return the data requested by the query passed * * @arg CSL_Status * CSL_SOK - Successful completion of the query * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVQUERY - Query command not supported * * @eg * CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3QueryInfo info; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3Context context; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; CSL_Status status; Uint32 i,passStatus = 1; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // Query Module Info CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INFO,&info); ... * * =========================================================================== */ extern CSL_Status CSL_edma3GetHwStatus ( CSL_Edma3Handle hMod, CSL_Edma3HwStatusQuery myQuery, void *response ); /* *============================================================================ * @func CSL_edma3ChannelOpen * * @desc * Opens an EDMA channel to get access to the resources for a * particular channel. * * @arg edmaObj * Pointer to the EDMA Handle Object - to be allocated by the user * * @arg edmaNum * Instance Number of the EDMA * * @arg param * Channel specific parameters * * @arg status * Pointer to CSL Status * * @ret CSL_Edma3ChannelHandle * Valid edma channel handle will be returned if status value is * equal to CSL_SOK * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3ChannelAttr chAttr; CSL_Edma3ChannelHandle hChannel; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); ... * * =========================================================================== */ extern CSL_Edma3ChannelHandle CSL_edma3ChannelOpen ( CSL_Edma3ChannelObj *edmaObj, CSL_InstNum edmaNum, CSL_Edma3ChannelAttr *chAttr, CSL_Status *status ); /* *============================================================================ * @func CSL_edma3ChannelClose * * @desc * Closes (Invalidates) an EDMA channel (passed as handle) after it has * finished operating. The channel cannot be accessed any more. * * @arg hEdma * Channel Handle * * @ret CSL_Status * CSL_SOK - Close successful * CSL_ESYS_BADHANDLE - Invalid handle * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Close Module CSL_edma3Close(hModule); //Close channel CSL_edma3ChannelClose (hChannel); * * =========================================================================== */ extern CSL_Status CSL_edma3ChannelClose ( CSL_Edma3ChannelHandle hEdma ); /* * ============================================================================= * @func CSL_edma3ChannelSetupParam * * @desc * Does the Channel setup i.e the channel to param set mapping(if relevant) * * @arg hEdma * Channel Handle * * @arg paramNum * parameter set to be mapped to the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; Uint16 paramNum; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Set the parameter entry number to channel paramNum = 100; CSL_edma3HwChannelSetupParam(hChannel,paramNum); ... * * =========================================================================== */ extern CSL_Status CSL_edma3HwChannelSetupParam ( CSL_Edma3ChannelHandle hEdma, Uint16 paramNum ); /* * ============================================================================= * @func CSL_edma3ChannelSetupTriggerWord * * @desc * Sets up the channel trigger word.This is applicable only * for QDMA channels. * * @arg hEdma * Channel Handle * * @arg triggerWord * trigger word (0-7) for the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Sets up the QDMA Channel 0 trigger Word to the 3rd trigger word CSL_edma3HwChannelSetupTriggerWord(hChannel,3); ... * * =========================================================================== */ extern CSL_Status CSL_edma3HwChannelSetupTriggerWord ( CSL_Edma3ChannelHandle hEdma, Uint8 triggerWord ); /* * ============================================================================= * @func CSL_edma3ChannelSetupQue * * @desc * Does the Channel setup i.e the channel to que mapping * * @arg hEdma * Channel Handle * * @arg que * Queue to be mapped to the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3Que evtQue; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Set up the channel to que mapping CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_3); ... * * =========================================================================== */ extern CSL_Status CSL_edma3HwChannelSetupQue ( CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que que ); /* * ============================================================================= * @func CSL_edma3GetHwChannelSetupParam * * @desc * Obtains the current channel to parameter set mapping. * * @arg hEdma * Channel Handle * * @arg paramNum * parameter set currently mapped to the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; Uint16 paramNum; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the parameter entry number to which a channel is mapped to CSL_edma3GetHwChannelSetupParam(hChannel,&paramNum); ... * * =========================================================================== */ extern CSL_Status CSL_edma3GetHwChannelSetupParam ( CSL_Edma3ChannelHandle hEdma, Uint16 *paramNum ); /* * ============================================================================= * @func CSL_edma3GetHwChannelSetupTriggerWord * * @desc * Gets channel trigger word.This is applicable only for QDMA channels. * * @arg hEdma * Channel Handle * * @arg triggerWord * Trigger word setup in the (QDMA)channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3ChannelHandle hChannel; Uint8 triggerWord; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the trigger word programmed for a channel CSL_edma3GetHwChannelSetupTriggerWord(hChannel,&triggerWord); ... * * =========================================================================== */ extern CSL_Status CSL_edma3GetHwChannelSetupTriggerWord ( CSL_Edma3ChannelHandle hEdma, Uint8 *triggerWord ); /* * ============================================================================= * @func CSL_edma3GetHwChannelSetupQue * * @desc * Obtains the Channel setup i.e the channel to que mapping * * @arg hEdma * Channel Handle * * @arg que * Queue currently mapped to the channel * * @ret CSL_Status * CSL_SOK - Setup Param successful * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVPARAMS - Invalid parameter * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Edma3HwSetup hwSetup; CSL_Status status; CSL_Edma3Que evtQue; CSL_Edma3ChannelHandle hChannel; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Get the que to which a channel is mapped CSL_edma3GetHwChannelSetupQue(hChannel,&evtQue); ... * * =========================================================================== */ extern CSL_Status CSL_edma3GetHwChannelSetupQue ( CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que *que ); /* * ============================================================================= * @func CSL_edma3HwChannelControl * * @desc * Channel level control commands are handled by this API. * * @arg hCh * Channel Handle * * @arg cmd * Channel Command * * @arg cmdArg * Additional command arguments are passed to the API using this. * The CSL function type casts to the appropriate arguments type * depending on the cmd. * * @ret CSL_Status * CSL_SOK - Command execution successful. * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVCMD - Invalid command * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup; CSL_Edma3ChannelObj ChObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL); ... * * =========================================================================== */ extern CSL_Status CSL_edma3HwChannelControl ( CSL_Edma3ChannelHandle hCh, CSL_Edma3HwChannelControlCmd cmd, void *cmdArg ); /* * ============================================================================= * @n@b CSL_edma3GetHwChannelStatus * * @desc * Channel level queries to the EDMA module are handled through this API. * * @arg hCh * Channel Handle * * @arg myQuery * Channel query to be performed. * * @arg response * Pointer to buffer to return the data requested by the query passed * * @ret CSL_Status * CSL_SOK - Successful completion of the query * CSL_ESYS_BADHANDLE - Invalid handle * CSL_ESYS_INVQUERY - Query command not supported * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup; CSL_Edma3ChannelObj ChObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; Bool errStat; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Obtain Channel Error Status CSL_edma3GetHwChannelStatus(hChannel,CSL_EDMA3_QUERY_CHANNEL_ERR, \ errStat); ... * * =========================================================================== */ extern CSL_Status CSL_edma3GetHwChannelStatus ( CSL_Edma3ChannelHandle hCh, CSL_Edma3HwChannelStatusQuery myQuery, void *response ); /* * ============================================================================= * @n@b CSL_edma3GetParamHandle * * @desc * Returns the handle to the requested parameter set. * * @arg hEdma * Channel Handle * * @arg paramNum * Param set number desired * * @arg status * Pointer to the placeholder for the status * * @ret CSL_Edma3ParamHandle * Valid param handle will be returned if status value * is equal to CSL_SOK. * * @eg * CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3HwSetup hwSetup; CSL_Edma3ChannelObj ChObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Obtain a handle to parameter entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL); ... * * =========================================================================== */ extern CSL_Edma3ParamHandle CSL_edma3GetParamHandle ( CSL_Edma3ChannelHandle hEdma, Int16 paramNum, CSL_Status *status ); /* * ============================================================================= * @n@b CSL_edma3ParamSetup * * @desc * Configures a EDMA Parameter Set. * * @arg hParam * Handle to the Parameter Set * * @arg pSetup * Pointer to the CSL_Edma3ParamSetup * * @ret CSL_Status * CSL_SOK - Command execution successful * CSL_ESYS_BADHANDLE - The handle passed is * invalid * CSL_ESYS_INVPARAMS - The parameter passed is invalid * * @eg * CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamPing; CSL_Edma3ChannelObj ChObj; CSL_Edma3QueryInfo info; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; CSL_Status status; Uint32 i, passStatus = 1; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); // DRAE Enable(Bits 0-15) for the Shadow Region 0. regionAccess.region = CSL_EDMA3_REGION_0 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); // Interrupt Enable (Bits 0-11) for the Shadow Region 0. regionIntr.region = CSL_EDMA3_REGION_0 ; regionIntr.intr = 0x0FFF ; regionIntr.intrh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Obtain a handle to parameter entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL); // Setup the first param Entry (Ping buffer) myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCHEN_DIS, \ CSL_EDMA3_TCCHEN_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 0,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff1; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1); myParamSetup.dstAddr = (Uint32)dstBuff1; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup.cCnt = 1; CSL_edma3ParamSetup(hParamBasic,&myParamSetup); ... * * =========================================================================== */ extern CSL_Status CSL_edma3ParamSetup ( CSL_Edma3ParamHandle hParam, CSL_Edma3ParamSetup *pSetup ); /* * ============================================================================= * @n@b CSL_edma3ParamWriteWord * * @desc * Writes specified word at the specified parameter set offset. * * @arg hParam * Handle to the Parameter Set * * @arg wordOffset * Word Offset at which the specified word is to be written * * @arg word * Word itself that needs to be written * * @ret CSL_Status * CSL_SOK - Param Write Word successful * * @eg * CSL_Edma3Handle hModule; CSL_Edma3HwSetup hwSetup,gethwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamPing; CSL_Edma3ChannelObj ChObj; CSL_Edma3QueryInfo info; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdQrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = CSL_EDMA3_DMACHANNELSETUP_DEFAULT; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = CSL_EDMA3_QDMACHANNELSETUP_DEFAULT; CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH]; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmahwSetup[0];; CSL_edma3HwSetup(hModule,&hwSetup); // DRAE Enable(Bits 0-15) for the Shadow Region 0. regionAccess.region = CSL_EDMA3_REGION_0 ; regionAccess.qrae = 0x000F ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_QDMAREGION_ENABLE, \ &regionAccess); // Interrupt Enable (Bits 0-11) for the Shadow Region 0. regionIntr.region = CSL_EDMA3_REGION_0 ; regionIntr.intr = 0x0FFF ; regionIntr.intrh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE, &regionIntr); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = CSL_EDMA3_CHA_DSPINT; hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status); // Obtain a handle to parameter entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL); // Setup the first param Entry (Ping buffer) myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCHEN_DIS, \ CSL_EDMA3_TCCHEN_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 0,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_EN, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff1; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1); myParamSetup.dstAddr = (Uint32)dstBuff1; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup.cCnt = 1; CSL_edma3ParamSetup(hParamBasic,&myParamSetup); // Enable Channel CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL); // Write trigger word CSL_edma3ParamWriteWord(hParamBasic,7,myParamSetup.cCnt); ... * * =========================================================================== */ extern CSL_Status CSL_edma3ParamWriteWord ( CSL_Edma3ParamHandle hParamHndl, Uint16 wordOffset, Uint32 word ); #ifdef __cplusplus } #endif #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/inc/csl_error.h

/* ========================================================================== * Copyright (c) Texas Instruments Inc 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * provided * ========================================================================== */ /* ---- File: <csl_error.h> ---- */ #ifndef _CSL_ERROR_H_ #define _CSL_ERROR_H_ /* Below Error codes are Global across all CSL Modules. */ #define CSL_SOK (1) /* Success */ #define CSL_ESYS_FAIL (-1) /* Generic failure */ #define CSL_ESYS_INUSE (-2) /* Peripheral resource is already in use */ #define CSL_ESYS_XIO (-3) /* Encountered a shared I/O(XIO) pin conflict */ #define CSL_ESYS_OVFL (-4) /* Encoutered CSL system resource overflow */ #define CSL_ESYS_BADHANDLE (-5) /* Handle passed to CSL was invalid */ #define CSL_ESYS_INVPARAMS (-6) /* invalid parameters */ #define CSL_ESYS_INVCMD (-7) /* invalid command */ #define CSL_ESYS_INVQUERY (-8) /* invalid query */ #define CSL_ESYS_NOTSUPPORTED (-9) /* action not supported */ /* Peripheral IDs */ #define CSL_MCBSP_ID (7) #define CSL_GPIO_ID (8) /* Error codes individual to various modules. */ /* Error code for DMA, individual error would be assigned as * eg: #define CSL_E<Peripheral name>_<error code> CSL_EDMA_FIRST - 1 */ #define CSL_EPWM_FIRST -( ((CSL_PWM_ID + 1) << 5 ) + 1 ) #define CSL_EPWM_LAST -( (CSL_PWM_ID + 1) << 6 ) #define CSL_EUART_FIRST -( ((CSL_UART_ID + 1) << 5 ) + 1 ) #define CSL_EUART_LAST -( (CSL_UART_ID + 1) << 6 ) #define CSL_ESPI_FIRST -( ((CSL_SPI_ID + 1) << 5 ) + 1 ) #define CSL_ESPI_LAST -( (CSL_SPI_ID + 1) << 6 ) #define CSL_EATA_FIRST -( ((CSL_ATA_ID + 1) << 5 ) + 1 ) #define CSL_EATA_LAST -( (CSL_ATA_ID + 1) << 6 ) #define CSL_EMMCSD_FIRST -( ((CSL_MMCSD_ID + 1) << 5 ) + 1 ) #define CSL_EMMCSD_LAST -( (CSL_MMCSD_ID + 1) << 6 ) #define CSL_EVLYNQ_FIRST -( ((CSL_VLYNQ_ID + 1) << 5 ) + 1 ) #define CSL_EVLYNQ_LAST -( (CSL_VLYNQ_ID + 1) << 6 ) #define CSL_EMCBSP_FIRST -( ((CSL_MCBSP_ID + 1) << 5 ) + 1 ) #define CSL_EMCBSP_LAST -( (CSL_MCBSP_ID + 1) << 6 ) #define CSL_EI2C_FIRST -( ((CSL_I2C_ID + 1) << 5 ) + 1 ) #define CSL_EI2C_LAST -( (CSL_I2C_ID + 1) << 6 ) #define CSL_EGPIO_FIRST -( ((CSL_GPIO_ID + 1) << 5 ) + 1 ) #define CSL_EGPIO_LAST -( (CSL_GPIO_ID + 1) << 6 ) #define CSL_EMS_FIRST -( ((CSL_MS_ID + 1) << 5 ) + 1 ) #define CSL_EMS_LAST -( (CSL_MS_ID + 1) << 6 ) #define CSL_EINTC_FIRST -( ((CSL_INTC_ID + 1) << 5 ) + 1 ) #define CSL_EINTC_LAST -( (CSL_INTC_ID + 1) << 6 ) #define CSL_EEMIF_FIRST -( ((CSL_EMIF_ID + 1) << 5 ) + 1 ) #define CSL_EEMIF_LAST -( (CSL_EMIF_ID + 1) << 6 ) #define CSL_EPLLC_FIRST -( ((CSL_PLLC_ID + 1) << 5 ) + 1 ) #define CSL_EPLLC_LAST -( (CSL_PLLC_ID + 1) << 6 ) #define CSL_EDDR_FIRST -( ((CSL_DDR_ID + 1) << 5 ) + 1 ) #define CSL_EDDR_LAST -( (CSL_DDR_ID + 1) << 6 ) #define CSL_EEDMA_FIRST -( ((CSL_EDMA_ID + 1) << 5 ) + 1 ) #define CSL_EEDMA_LAST -( (CSL_EDMA_ID + 1) << 6 ) #endif /* _CSL_ERROR_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/FB_W2100_SCU_MEA256/Stimulation.c

<filename>DSP/FB_W2100_SCU_MEA256/Stimulation.c /* * Stimulation.c * * Created on: 14.05.2018 * Author: jesinger */ #include "Device_lib.h" #include "Stimulation.h" #include <math.h> void UploadBiphaseRect(int channel, int segment, int amplitude, int duration, int repeats) { int vectors_used; vectors_used = 0; ClearChannel(channel, segment); vectors_used += AddDataPoint(channel, duration, 0x8000 + amplitude); vectors_used += AddDataPoint(channel, duration, 0x8000 - amplitude); AddLoop(channel, vectors_used, repeats); vectors_used = 0; ClearChannel(channel+1, segment); vectors_used += AddDataPoint(channel+1, duration, 0x0119); // bit 1,3,4 and 8 vectors_used += AddDataPoint(channel+1, duration, 0x0019); // bit 1,3,4 AddLoop(channel+1, vectors_used, repeats); } void UploadSine(int channel, int segment, int amplitude, int period, int repeats, int stepsize) { int yold = 0; int duration = 0; int datapoints = 0; volatile int i; int y; int vectors_used; vectors_used = 0; ClearChannel(channel, segment); for (i = 0; i < period; i++) { y = amplitude * sin((((double)i)/period)*2*3.1415); // y = -(Amplitude *i)/Period; if (abs(y - yold) > stepsize) { vectors_used += AddDataPoint(channel, duration, yold+0x8000); datapoints++; yold = y; duration = 1; // 20 us } else { duration++; } } vectors_used += AddDataPoint(channel, duration, yold+0x8000); AddLoop(channel, vectors_used, repeats); // Create Sideband Information ClearChannel(channel+1, segment); vectors_used = 0; vectors_used += AddDataPoint(channel+1, period, 0x0019); AddLoop(channel+1, vectors_used, repeats); // AddDataPoint(Channel+1, 10, 0x0009); // keep Electrode connected to ground after stimulation } void AddLoop(int channel, int vectors, int repeats) { Uint32 ChannelReg = STG_DATA_MEMORY + channel * REGISTER_OFFSET; Uint32 LoopVector; if (repeats > 1) { LoopVector = 0x10000000 | (repeats << 16) | vectors; WRITE_REGISTER(ChannelReg, LoopVector); } } void SetSegment(int channel, int segment) { Uint32 SegmentReg = STG_MEMPOINT_CC_BASE + (channel * MEMPOINT_OFFSET); WRITE_REGISTER(SegmentReg, segment); } void ClearChannel(int channel, int segment) { Uint32 ClearReg = STG_MEMPOINT_WP_BASE + (channel * MEMPOINT_OFFSET); // SetSegment(channel, segment); WRITE_REGISTER(ClearReg, 0); // Any write to this register clears the channeldata } int AddDataPoint(int channel, int duration, int value) { int vectors_used = 0; int Vector; Uint32 ChannelReg = STG_DATA_MEMORY + channel * REGISTER_OFFSET; if (duration > 1000) { Vector = 0x04000000 | (((duration / 1000) - 1) << 16) | (value & 0xffff); WRITE_REGISTER(ChannelReg, Vector); // Write Datapoint to STG Memory duration %= 1000; vectors_used++; } if (duration > 0) { Vector = ((duration - 1) << 16) | (value & 0xffff); WRITE_REGISTER(ChannelReg, Vector); // Write Datapoint to STG Memory vectors_used++; } return vectors_used; } void SetupTrigger() { int i; WRITE_REGISTER(TRIGGER_CTRL_HS1, 0x1); // Enable Trigger Packets for (i = 0; i < TIGGER_PER_HS; i++) { WRITE_REGISTER(TRIGGER_ID_HS1+i, 0x0); // Setup Trigger WRITE_REGISTER(STG_TRIGGER_CONFIG+i, (4 << 1) | 1); WRITE_REGISTER(STG_TRIGGER_REPEAT+i, 1); // Trigger Repeat: only once } // WRITE_REGISTER(0x9104, 0x00020100); // DAC1 to Trigger1, DAC2 to Trigger2, DAC3 to Trigger3 // WRITE_REGISTER(0x9108, 0x00020100); // SBS1 to Trigger1, SBS2 to Trigger2, SBS3 to Trigger3 }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cHwSetup.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_i2cHwSetup.c * * @brief File for functional layer of CSL API @a CSL_i2cHwSetup() * * @path $(CSLPATH)\i2c\src * * Description * - The @a CSL_i2cHwSetup() function definition & it's associated * functions * * Modification 1 * - Modified on: 28/5/2004 * - Reason: created the sources * * @date 28th May, 2004 * @author <NAME>. * ============================================================================ */ #include <csl_i2c.h> /** ============================================================================ * @n@b CSL_i2cHwSetup * * @b Description * @n This function initializes the device registers with the appropriate * values provided through the HwSetup Data structure. This function needs * to be called only if the HwSetup Structure was not previously passed * through the Open call. After the Setup is completed, the device is ready * for operation.For information passed through the HwSetup Data structure * refer @a CSL_i2cHwSetup. * @b Arguments * @verbatim hI2c Handle to the I2C setup Pointer to setup structure which contains the information to program I2C to a useful state @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Hardware setup Successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Invalid parameter * * Pre Condition * @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully * in that order before this function can be called. The user has to * allocate space for & fill in the main setup structure appropriately * before calling this function. * * Post Condition * @n The registers of the specified I2C instance will be setup * according to value passed. * * @b Modifies * @n Hardware registers of the specified I2C instance. * * @b Example * @verbatim CSL_i2cHandle hI2c; CSL_i2cHwSetup hwSetup = CSL_I2C_HWSETUP_DEFAULTS; ... CSL_i2cHwSetup(hI2c, &hwSetup); ... @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_i2cHwSetup, ".text:csl_section:i2c"); CSL_Status CSL_i2cHwSetup ( CSL_I2cHandle hI2c, CSL_I2cHwSetup *setup ) { CSL_Status status = CSL_SOK; if (hI2c == NULL) { status = CSL_ESYS_BADHANDLE; } else if (setup == NULL) { status = CSL_ESYS_INVPARAMS; } else { /* Set the mode(Master/Slave), direction(Transmitter/Receiver), * addressing mode(7-bit or 10-bit, free run mode, free data * format and start byte mode. */ hI2c->regs->ICMDR = ((hI2c->regs->ICMDR & 0x3807) | (CSL_FMK(I2C_ICMDR_MST,setup->mode) | CSL_FMK(I2C_ICMDR_NACKMOD, setup->ackMode) | CSL_FMK(I2C_ICMDR_TRX, setup->dir) | CSL_FMK(I2C_ICMDR_XA, setup->addrMode) | CSL_FMK(I2C_ICMDR_FREE, setup->runMode) | CSL_FMK(I2C_ICMDR_STB, setup->sttbyteen) | CSL_FMK(I2C_ICMDR_FDF, setup->freeDataFormat) | CSL_FMK(I2C_ICMDR_RM, setup->repeatMode) | CSL_FMK(I2C_ICMDR_DLB, setup->loopBackMode) | CSL_FMK(I2C_ICMDR_IRS, setup->resetMode))); /* set Backward Compatibility Mode */ hI2c->regs->ICEMDR = (hI2c->regs->ICEMDR & 0x1) | (CSL_FMK(I2C_ICEMDR_BCM, setup->bcm)); /* Set the own address of the given instance */ CSL_FINS(hI2c->regs->ICOAR, I2C_ICOAR_OADDR, setup->ownaddr); /* The interrupt status is set into the interrupt enable register */ hI2c->regs->ICIMR = setup->inten ; /* Set up the prescalar value */ CSL_FINS(hI2c->regs->ICPSC, I2C_ICPSC_IPSC, setup->clksetup->prescalar); /* Set the clock low value */ CSL_FINS(hI2c->regs->ICCLKL, I2C_ICCLKL_ICCL, setup->clksetup->clklowdiv); /* Set the clock high value */ CSL_FINS(hI2c->regs->ICCLKH, I2C_ICCLKH_ICCH, setup->clksetup->clkhighdiv); } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example1/src/Intc_example1.c

<filename>DSP/TI-Header/csl_c64xplus_intc/example/c64xplus/intc/intc_example1/src/Intc_example1.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file Intc_example.c * * @path $(CSLPATH)\example\c64xplus\intc\intc_example1\src * * @desc Example of INTC * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @n The example shows how to use INTC CSL with EDMA module. * This is an example of the CSL Interrupt Controller usage. * A event object is opened and is simply hooked up to a CPU vector. * An event hnadler is associaed with it. This example, * 1. Initalizes the intc CSL required with proper ISR * 2. Intializes and opens EDMA * 3. Associates EDMA event handler with the INTC routine * CSL_intcPlugEventHandler () * 4. Enables the edma interrupt * 5. Waits for edma interrupt generate. * 6. Compares the transferred data * 7. Displays the messages based on step 6 * *============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Intc_example1.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================= * Revision History * =============== * 30-Jun-2004 <NAME> File Created * 22-Jul-2005 ds changed to support edma3 csl * 16-Dec-2005 ds Updated documentation * 28-Mar-2006 ds Added code to clear all the evnts * ============================================================================= */ #include <stdio.h> #include <csl_edma3.h> #include <csl_intc.h> #include <soc.h> /* Pragma to edma tcc handler table */ #pragma DATA_SECTION(TccHandlerTable,".testMem"); /* Global variable to Edma Tcc handler table */ typedef void (* EdmaTccHandler)(void); EdmaTccHandler TccHandlerTable[64]; /* Macro for tcc handler table */ #define InvokeHandle(num) TccHandlerTable[num]() /* Funtion forwards, for which registers individual event handlers in a table */ void EdmaEventHook(Uint16 , EdmaTccHandler); void eventEdmaHandler(void *); /* Function forwards */ void tcc1Fxn(); void intc_example (void); /* Intc variable declarartion */ CSL_IntcContext intcContext; CSL_IntcEventHandlerRecord EventHandler[30]; CSL_IntcObj intcObjEdma; CSL_IntcHandle hIntcEdma; CSL_IntcGlobalEnableState state; CSL_IntcEventHandlerRecord EventRecord; CSL_IntcParam vectId; /* Global variable declarations */ Uint8 srcBuff[512]; Uint8 dstBuff[512]; volatile Uint32 intFlag = 0; CSL_Edma3Handle hModule; /* * ============================================================================= * @func main * * @desc * This is the main routine,which invokes the example * ============================================================================= */ void main() { printf ("Running Interrupt Example\n"); intc_example (); return; } /* * ============================================================================= * @func intc_example * * @arg None * * @desc * This is an example of the CSL Interrupt Controller usage. * A event object is opened and is simply hooked up to a CPU vector. * An event hnadler is associaed with it. * 1. Initalizes the intc CSL required with proper ISR * 2. Intializes and opens EDMA * 3. Associates EDMA event handler with the INTC routine * CSL_intcPlugEventHandler () * 4. Enables the edma interrupt * 5. Waits for edma interrupt generate. * 6. Compares the transferred data * 7. Closes the edma module and edma channel. * 8. Closes the Intc module * * @return * None * * @eg * intc_example (); * ============================================================================= */ void intc_example (void) { CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ChannelObj chObj; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Status status; Uint32 loopIndex; Uint32 passStatus = 1; Uint32 evtClr; CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \ CSL_EDMA3_DMACHANNELSETUP_DEFAULT; /* Initialize Data Buffers */ for (loopIndex = 0; loopIndex < 512;loopIndex++) { srcBuff[loopIndex] = loopIndex; dstBuff[loopIndex] = 0; } /* Edma CSL initialization */ CSL_edma3Init(&context); /* Intc module initialization */ intcContext.eventhandlerRecord = EventHandler; intcContext.numEvtEntries = 10; status = CSL_intcInit(&intcContext); if (status != CSL_SOK) { printf("Intc initialization failed\n"); return; } /* Enable NMIs */ status = CSL_intcGlobalNmiEnable(); if (status != CSL_SOK) { printf("Intc global NMI enable failed\n"); return; } /* Enable global interrupts */ status = CSL_intcGlobalEnable(&state); if (status != CSL_SOK) { printf ("Intc global enable failed\n"); return; } /* Opening intc module */ vectId = CSL_INTC_VECTID_4; hIntcEdma = CSL_intcOpen (&intcObjEdma, CSL_INTC_EVENTID_EDMA3CC_INT1, \ &vectId , NULL); if (hIntcEdma == NULL) { printf("Intc open failed\n"); return; } /* Opening a edma module */ hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); /* Edma module setup */ hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = NULL; CSL_edma3HwSetup(hModule,&hwSetup); /* Setup the DRAE Masks * DRAE Enable(Bits 0-15) for the Shadow Region 1. */ regionAccess.region = CSL_EDMA3_REGION_1 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); /* Edma channel open */ chAttr.regionNum = CSL_EDMA3_REGION_1; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj,CSL_EDMA3,&chAttr,&status); /* Parameter Set Setup */ hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 1,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1); myParamSetup.dstAddr = (Uint32)dstBuff; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,1); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0); myParamSetup.cCnt = 1; CSL_edma3ParamSetup(hParamBasic,&myParamSetup); /* Association of an EDMA event handler with the INTC routine */ EventRecord.handler = &eventEdmaHandler; EventRecord.arg = (void*)(hModule); status = CSL_intcPlugEventHandler(hIntcEdma,&EventRecord); if (status != CSL_SOK) { printf("Intc plug event handler failed\n"); return; } /* Enabling event edma */ status = CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL); if (status != CSL_SOK) { printf("Intc CSL_INTC_CMD_EVTENABLE command failed\n"); return; } /* Hook up the EDMA Event with an completion code function handler */ EdmaEventHook(1, tcc1Fxn); /* Enable Interrupts */ regionIntr.region = CSL_EDMA3_REGION_1 ; regionIntr.intr = 0x2 ; regionIntr.intrh = 0x0 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr); /* Enable Channel :- though not required for a manual trigger */ status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \ NULL); /* Manually trigger the channel */ status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL); /* Wait for generation of interrut */ while (!intFlag); /* Verify destination buffer to be equal to the source buffer */ for (loopIndex = 0; loopIndex < 256; loopIndex++) if (srcBuff[loopIndex] != dstBuff[loopIndex]) passStatus = 0; if (passStatus != 0) { printf ("<<Example Passed>>: Interrupt example passed\n"); } else { printf ("<<Example Failed>>: Interrupt example failed\n"); return; } /* Clear the all events */ for (loopIndex = 0; loopIndex < 4; loopIndex++) { evtClr = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTFLAG[loopIndex]; ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[loopIndex] = evtClr; } /* Close handles */ CSL_edma3ChannelClose(hChannel); CSL_edma3Close(hModule); CSL_intcClose (hIntcEdma); return; } /* * ============================================================================= * @func tcc1Fxn * @desc * This is the Interrupt service routine * * @arg None * * @eg * tcc1Fxn (); * * * ============================================================================= */ void tcc1Fxn(void) { intFlag = 1; } /* * ============================================================================= * @func EdmaEventHook * * @arg * tcc - Tcc number * fxn - Pointer to function which points to edma isr * * @desc * This is the interrupt handler routine for edma interrupt * * @return * NONE * * ============================================================================= */ void EdmaEventHook ( Uint16 tcc, EdmaTccHandler fxn ) { TccHandlerTable[tcc] = (fxn); } /* * ============================================================================= * @func eventEdmaHandler * * @desc * This is the event handler for edma * * @arg handle * Pointer to edma handle * * * @eg * eventEdmaHandler (); * ============================================================================= */ void eventEdmaHandler ( void *handle ) { CSL_BitMask32 mask; CSL_BitMask32 maskVal; CSL_Edma3CmdIntr regionIntr; Uint32 tcc; Uint32 intr; Uint32 intrh; Int region; CSL_Edma3Handle hModule = (CSL_Edma3Handle)handle; regionIntr.region = CSL_EDMA3_REGION_GLOBAL; CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr); intr = regionIntr.intr; intrh = regionIntr.intrh; mask = 1; tcc = 0; while (intr) { maskVal = mask << tcc; if (regionIntr.intr & maskVal) { InvokeHandle(tcc); intr &= ~maskVal; } tcc++; } mask = 1; tcc = 0; while (intrh) { maskVal = mask << tcc; if (intrh & maskVal) { InvokeHandle((tcc+32)); intrh &= ~maskVal; } tcc++; } CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&regionIntr); CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr); if ((regionIntr.intr !=0)||(regionIntr.intrh !=0)) { region = CSL_EDMA3_REGION_GLOBAL; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_EVAL,&region); } }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcInit.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_intcInit.c * * @brief File for functional layer of CSL API CSL_intcInit() * * PATH $(CSLPATH)\src\intc */ /* ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= */ #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /** ============================================================================ * @n@b CSL_intcInit * * @b Description * @n This is the initialization function for the INTC. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't affect * the H/W. * * @b Arguments * @verbatim pContext Pointer to module-context structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Always returns * * Pre Condition * @n This function should be called before using any of the CSL INTC APIs. * The context should be initialized such that numEvtEntries is equal to * the number of records capable of being held in the eventhandlerRecord * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; CSL_IntcEventHandlerRecord recordTable[10]; context.numEvtEntries = 10; context.eventhandlerRecord = &recordTable; // Init Module ... if (CSL_intcInit(&context) != CSL_SOK) { exit; } @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_intcInit, ".text:csl_section:intc"); CSL_Status CSL_intcInit ( CSL_IntcContext *pContext ) { Uint16 i; asm(" dint"); if (pContext != NULL) { _CSL_intcEventOffsetMap = pContext->offsetResv; _CSL_intcAllocMask = pContext->eventAllocMask; _CSL_intcNumEvents = pContext->numEvtEntries; for (i = 0; i < ((CSL_INTC_EVENTID_CNT + 31) / 32); i++) _CSL_intcAllocMask[i] = 0; for (i = 0; i < CSL_INTC_EVENTID_CNT ; i++) _CSL_intcEventOffsetMap[i] = CSL_INTC_MAPPED_NONE; if (pContext->eventhandlerRecord != NULL) { _CSL_intcEventHandlerRecord = pContext->eventhandlerRecord; for (i = 0; i < _CSL_intcNumEvents; i++) _CSL_intcEventHandlerRecord[i].handler = CSL_INTC_EVTHANDLER_NONE; } } _CSL_intcIvpSet(); _CSL_intcCpuIntrTable.nmiIsr = _CSL_intcNmiDummy; _CSL_intcCpuIntrTable.isr4 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr5 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr6 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr7 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr8 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr9 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr10 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr11 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr12 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr13 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr14 = _CSL_intcDispatcher; _CSL_intcCpuIntrTable.isr15 = _CSL_intcDispatcher; asm(" rint"); return CSL_SOK; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspHwControl.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_mcbspHwControl.c * * @path $(CSLPATH)\src\mcbsp * * @desc File for functional layer of CSL API CSL_mcbspHwControl() * */ /* ============================================================================= * Revision History * ================ * June 29,2004 <NAME> - Created * * July 26, 2005 ds - Removed control cmd CSL_MCBSP_CMD_IO_MODE_CONTROL * * Feb 01, 2006 ds - Removed CSL_MCBSP_CMD_TX_INT_MODE and * CSL_MCBSP_CMD_RX_INT_MODE control commands * ============================================================================= */ #include <csl_mcbsp.h> #include <_csl_mcbsp.h> #include <csl_mcbspAux.h> /** ============================================================================ * @n@b CSL_mcbspHwControl * * @b Description * @n This function takes an input control command with an optional argument * and accordingly controls the operation/configuration of MCBSP. * * @b Arguments * @verbatim hMcbsp MCBSP handle returned by successful 'open' cmd Control command arg Optional argument as per the control command @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Command successful * @li CSL_ESYS_INVCMD - The Command passed is invalid * @li CSL_ESYS_BADHANDLE - The handle passed is invalid * @li CSL_ESYS_INVPARAMS - The parameter is invalid * * Pre Condition * @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully * in that order before CSL_mcbspHwControl() can be called. * * Post Condition * @n Mcbsp registers are configured according to the command passed * * @b Modifies * @n MCBSP registers * * @b Example * @verbatim CSL_Status status; CSL_BitMask16 ctrlMask; CSL_McbspHandle hMcbsp; ... // MCBSP object defined and HwSetup structure defined and initialized ... // Init successfully done ... // Open successfully done ... // HwSetup sucessfully done ... // MCBSP SRG and Frame sync taken out of reset ... ctrlMask = CSL_MCBSP_CTRL_RX_ENABLE | CSL_MCBSP_CTRL_TX_ENABLE; status = CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask); ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_mcbspHwControl, ".text:csl_section:mcbsp"); CSL_Status CSL_mcbspHwControl ( CSL_McbspHandle hMcbsp, CSL_McbspControlCmd cmd, void *arg ) { CSL_Status status = CSL_SOK; CSL_McbspBlkAssign *blkAsg; CSL_McbspChanControl *ch; CSL_McbspChType *chan; CSL_BitMask16 *ctrl; if(hMcbsp == NULL) { status=CSL_ESYS_BADHANDLE; } else if(((cmd <= CSL_MCBSP_CMD_RESET_CONTROL) && \ (cmd != CSL_MCBSP_CMD_RESET))&& \ (arg == NULL)) { status=CSL_ESYS_INVPARAMS; } else { switch(cmd) { case CSL_MCBSP_CMD_ASSIGN_BLOCK: blkAsg = (CSL_McbspBlkAssign *)arg; _CSL_mcbspBlockAssign(hMcbsp, blkAsg->partition, blkAsg->block); break; case CSL_MCBSP_CMD_CHANNEL_CONTROL: ch = (CSL_McbspChanControl *)arg; _CSL_mcbspChannelControl(hMcbsp, (ch->channelNo & 0xf), \ (CSL_McbspBlock)(ch->channelNo >> 4),\ ch->operation); break; case CSL_MCBSP_CMD_CLEAR_FRAME_SYNC: chan = (CSL_McbspChType *)arg; _CSL_mcbspClearFrmSyncErr(hMcbsp,*chan); break; case CSL_MCBSP_CMD_RESET: _CSL_mcbspRegReset(hMcbsp); break; case CSL_MCBSP_CMD_RESET_CONTROL: ctrl = (CSL_BitMask16 *)arg; _CSL_mcbspResetCtrl(hMcbsp, *ctrl); break; default: status = CSL_ESYS_INVCMD; break; } } return (status); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455/example/edma/edma_interrupt/src/Edma_interrupt_example.c

<filename>DSP/TI-Header/csl_c6455/example/edma/edma_interrupt/src/Edma_interrupt_example.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * * @file Edma_interrupt_example.c * * @path $(CSLPATH)\example\edma\edma_interrupt\src * * @desc Example of EDMA * * ============================================================================ * @n Target Platform: EVM * ============================================================================ * @n Example Description * @n This is an example of the CSL EDMA usage along with interrupts * in the context of a shadow region and illustrates a sample EDMA * interrupt handler implementation. This example, * 1. Initializes the CSL EDMA module * 2. Intializes and Sets up the Intc Module for EDMA module * 3. Opens and Sets up Edma module to default values * 4. Opens EDMA channel 0 in the region 1 * 5. Sets up the EDMA PARAM using CSL_edma3ParamSetup() API * 6. Enable the Edma interupt and Channel * 7. Manually triggers the channel 0 * 8. Waits for EDMA transfer to complete * 9. Does the data comparision to ensure the transffered data is proper * or not and * 10. Displays the messages based on step 9 * * ============================================================================= * * Procedure to run the example * @verbatim * 1. Configure the CCS setup to work with the emulator being used * 2. Please refer CCS manual for setup configuration and loading * proper GEL file * 3. Launch CCS window * 4. Open project Edma_interrupt_example.pjt * 5. Build the project and load the .out file of the project. * * @endverbatim * */ /* ============================================================================= * Revision History * =============== * 08-Jul-2005 <NAME> File Created * 16-Dec-2005 ds Updated documentation * 28-Mar-2006 ds Added code to disable the region 1 access at * the end of example * ============================================================================ */ #include <stdio.h> #include <csl_edma3.h> #include <csl_intc.h> #include <soc.h> #include <edmaCommon.h> /* Intc declaration */ CSL_IntcContext intcContext; CSL_IntcEventHandlerRecord EventHandler[30]; CSL_IntcObj intcObjEdma; CSL_IntcHandle hIntcEdma; CSL_IntcGlobalEnableState state; CSL_IntcEventHandlerRecord EventRecord; CSL_IntcParam vectId; /* Globals */ Uint8 srcBuff[512]; Uint8 dstBuff[512]; volatile Uint32 intFlag = 0; Uint32 passStatus = 1; /* Edma handle */ CSL_Edma3Handle hModule; /* Forward declaration */ void tcc1Fxn(void); void edma_interrupt_example (void); /* * ============================================================================= * @func main * * @desc * This is the main routine for the file. * * ============================================================================= */ void main(void) { /* Invoking a example */ edma_interrupt_example (); return; } /* * ============================================================================= * @func edma_interrupt_example * * @arg * NONE * * @desc * This is the example routine which perform edma interrupt. * It implements following steps * 1. Intializes and Opens the Edma and Intc module. * 2. Sets up the interrupt for the edma Regoin1. * 3. Sets up the edma module using the API csl_edma3Hwsetup () * 4. Enables the edma region1 using CSL_EDMA3_CMD_DMAREGION_ENABLE. * 5. Opens the channel 0 and get the param handle. * 6. Sets up the edma param entry * 7. Enables the edma interrupt using CSL_EDMA3_CMD_INTR_ENABLE. * 8. Enables the channel using CSL_EDMA3_CMD_CHANNEL_ENABLE * 9. Manually trigger the channel using CSL_EDMA3_CMD_CHANNEL_SET. * 10. Waits for transfer to complete. * 11. Compares the data in the destination buffer is proper or not. * 12. Closes the edma module and channel. * * @return * NONE * * ============================================================================= */ void edma_interrupt_example (void) { CSL_Edma3HwSetup hwSetup; CSL_Edma3Obj edmaObj; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ChannelObj chObj; CSL_Edma3CmdIntr regionIntr; CSL_Edma3CmdDrae regionAccess; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ParamSetup myParamSetup; CSL_Edma3Context context; CSL_Edma3ChannelAttr chAttr; CSL_Status status; CSL_Edma3HwDmaChannelSetup dmahwSetup; Uint32 loopIndex; /* Initialize data buffers */ for (loopIndex = 0; loopIndex < 512; loopIndex++) { srcBuff[loopIndex] = loopIndex; dstBuff[loopIndex] = 0; } /* Module initialization */ status = CSL_edma3Init(&context); if (status != CSL_SOK) { printf ("Edma module initialization failed\n"); return; } /* Intc module initialization */ intcContext.eventhandlerRecord = EventHandler; intcContext.numEvtEntries = 10; CSL_intcInit(&intcContext); /* Enable NMIs */ CSL_intcGlobalNmiEnable(); /* Enable global interrupts */ CSL_intcGlobalEnable(&state); /* Opening a intc handle for edma event */ vectId = CSL_INTC_VECTID_4; hIntcEdma = CSL_intcOpen (&intcObjEdma, CSL_INTC_EVENTID_EDMA3CC_INT1, \ &vectId , NULL); /* Edma module open */ hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); if ( (hModule == NULL) || (status != CSL_SOK)) { printf ("Edma module open failed\n"); return; } /* Edma module setup */ dmahwSetup.paramNum = 0; dmahwSetup.que = CSL_EDMA3_QUE_0; hwSetup.dmaChaSetup = &dmahwSetup; hwSetup.qdmaChaSetup = NULL; status = CSL_edma3HwSetup(hModule,&hwSetup); if (status != CSL_SOK) { printf ("Hardware setup failed\n"); CSL_edma3Close (hModule); return; } /* Setup the DRAE masks * DRAE enable(Bits 0-15) for the shadow region 1. */ regionAccess.region = CSL_EDMA3_REGION_1 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \ &regionAccess); if (status != CSL_SOK) { printf("Edma region enable command failed\n"); return; } /* Channel open */ chAttr.regionNum = CSL_EDMA3_REGION_1; chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); if ( (hChannel == NULL) || (status != CSL_SOK)) { printf ("Edma channel open failed\n"); return; } /* Get the parameter handle */ hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); if (hParamBasic == NULL) { printf("Edma get param handle failed\n"); return; } /* Edma parameter entry Setup */ myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 1,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(512,1); myParamSetup.dstAddr = (Uint32)dstBuff; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (CSL_EDMA3_LINK_NULL, 1); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0); myParamSetup.cCnt = 1; status = CSL_edma3ParamSetup(hParamBasic,&myParamSetup); if (status != CSL_SOK) { printf ("Edma param setup failed\n"); return; } /* Association of an EDMA event handler with the INTC routine */ EventRecord.handler = &eventEdmaHandler; EventRecord.arg = (void*)(hModule); CSL_intcPlugEventHandler(hIntcEdma,&EventRecord); /* Enabling event edma */ CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL); /* Hook up the EDMA event with an completion code function handler */ EdmaEventHook(1, tcc1Fxn); /* Enable interrupts */ regionIntr.region = CSL_EDMA3_REGION_1 ; regionIntr.intr = 0x2 ; regionIntr.intrh = 0x0 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr); if (status != CSL_SOK) { printf ("Edma interrupt enable command failed\n"); return; } /* Manually trigger the channel */ status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL); if (status != CSL_SOK) { printf ("Edma channel set command failed\n"); return; } /* Wait for completion */ while (!intFlag); /* Disable the region 1 access */ regionAccess.region = CSL_EDMA3_REGION_1 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_DISABLE, \ &regionAccess); /* Verify destination buffer to be equal to the source buffer */ if(Verify_Transfer(512, 1, 1, 0, 0, 0, 0, srcBuff, dstBuff,TRUE) == FALSE) passStatus = 0; if (passStatus == 1) printf ("<<EXAMPLE PASSED>>: Edma Interrupt Example Passed\n"); printf ("=============================================================\n"); /* Channel close */ status = CSL_edma3ChannelClose(hChannel); if (status != CSL_SOK) { printf ("Edma channle close failed\n"); return; } /* Edma module close */ status = CSL_edma3Close(hModule); if (status != CSL_SOK) { printf ("Edma module close failed\n"); return; } return; } /* * ============================================================================= * @func tcc1Fxn * * @arg * NONE * * @desc * This is the interrupt service routine for edma interrupt * * @return * NONE * * ============================================================================= */ void tcc1Fxn(void) { intFlag = 1; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/cfg/csl_cfgOpen.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_cfgOpen.c * * @path $(CSLPATH)\src\cfg * * @desc File for functional layer of CSL API CSL_cfgOpen() * */ /* ============================================================================= * Revision History * =============== * 11-Apr-2005 Brn Updated the file for doxygen compatibiliy * * 16-Nov-2005 ds Updated the documentation * * 31-Jan-2006 ds Supported to use the CSL_cfgGetBaseAddress() API * ============================================================================= */ #include <csl_cfg.h> /** =========================================================================== * @n@b CSL_cfgOpen * * @b Description * @n This function populates the peripheral data object for the instance * and returns a handle to the instance. * The open call sets up the data structures for the particular instance * of CFG device. The device can be re-opened anytime after it has * been normally closed, if so required. The handle returned by this call * is input as an essential argument for rest of the APIs described for * this module. * * @b Arguments * @verbatim pCfgObj Pointer to the CFG instance object cfgNum Instance of the CFG to be opened. pCfgParam Pointer to module specific parameters pStatus pointer for returning status of the function call @endverbatim * * Return Value CSL_CfgHandle * @n Valid CFG instance handle will be returned if status value is * equal to CSL_SOK. * * Pre Condition * @n CSL_cfgInit() has to be called before this function get called * * Post Condition * @n CSL_cfgInit has to be called before calling this function. * Post Condition * 1. The status is returned in the status variable. If status returned is * - CSL_SOK - Valid CFG handle is returned. * - CSL_ESYS_FAIL - The CFG instance is invalid. * - CSL_ESYS_INVPARAMS - The Obj structure passed is invalid * 2. CFG object structure is populated. * * * @b Modifies * @n 1. The status variable * 2. CFG object structure * * @b Example * @verbatim CSL_status status; CSL_CfgObj cfgObj; CSL_CfgHandle hCfg; ... hCfg = CSL_cfgOpen (&cfgObj, CSL_MEMPROT_CONFIG, NULL, &status); @endverbatim * =========================================================================== */ #pragma CODE_SECTION (CSL_cfgOpen, ".text:csl_section:cfg"); CSL_CfgHandle CSL_cfgOpen ( CSL_CfgObj *pCfgObj, CSL_InstNum cfgNum, CSL_CfgParam *pCfgParam, CSL_Status *pStatus ) { CSL_CfgHandle hCfg = (CSL_CfgHandle)NULL; CSL_CfgBaseAddress baseAddress; if (pStatus == NULL) { /* do nothing : already the module is initialized to NULL */ } else if (pCfgObj == NULL) { *pStatus = CSL_ESYS_INVPARAMS; } else { *pStatus = CSL_cfgGetBaseAddress(cfgNum, pCfgParam, &baseAddress); if (*pStatus == CSL_SOK) { pCfgObj->regs = baseAddress.regs; pCfgObj->cfgNum = (CSL_InstNum)cfgNum; hCfg = (CSL_CfgHandle)pCfgObj; } else { pCfgObj->regs = (CSL_CfgRegsOvly)NULL; pCfgObj->cfgNum = (CSL_InstNum)-1; } } return (hCfg); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiOpen.c

<filename>DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiOpen.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_hpiOpen.c * * @path $(CSLPATH)\src\hpi * * @brief File for functional layer of CSL API @a CSL_hpiOpen() * */ #include <csl_hpi.h> /** ============================================================================ * @n@b CSL_hpiOpen * * @b Description * @n This function returns the handle to the HPI controller * instance. This handle is passed to all other CSL APIs. * * @b Arguments * @verbatim hpiObj Pointer to the object that holds reference to the instance of HPI requested after the call. hpiNum Instance of HPI to which a handle is requested. There is only one instance of the hpi available. So, the value for this parameter will be CSL_HPI always. pHpiParam Module specific parameters. status Status of the function call @endverbatim * * Return Value CSL_HpiHandle * @n Valid HPI handle will be returned if * status value is equal to CSL_SOK. * * Pre Condition * @n None * * Post Condition * @n 1. The status is returned in the status variable. If status * returned is * @li CSL_SOK - Valid HPI handle is returned * @li CSL_ESYS_FAIL - The HPI instance is invalid * @li CSL_ESYS_INVPARAMS - Invalid parameter * * 2. HPI object structure is populated * * @b Modifies * @n 1. The status variable * * 2. HPI object structure * * @b Example * @verbatim CSL_status status; CSL_HpiObj hpiObj; CSL_HpiHandle hHpi; ... hHpi = CSL_hpiOpen(&hpiObj, CSL_HPI, NULL, &status); ... @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_hpiOpen, ".text:csl_section:hpi"); CSL_HpiHandle CSL_hpiOpen ( CSL_HpiObj *pHpiObj, CSL_InstNum hpiNum, CSL_HpiParam *pHpiParam, CSL_Status *pStatus ) { CSL_HpiHandle hHpi = (CSL_HpiHandle)NULL; CSL_HpiBaseAddress baseAddress; if (pStatus == NULL) { /* do nothing : module handle is already initialized to NULL */ } else if (pHpiObj == NULL) { *pStatus = CSL_ESYS_INVPARAMS; } else { *pStatus = CSL_hpiGetBaseAddress (hpiNum, pHpiParam, &baseAddress); if (*pStatus == CSL_SOK) { pHpiObj->regs = baseAddress.regs; pHpiObj->hpiNum = (CSL_InstNum) hpiNum; hHpi = (CSL_HpiHandle) pHpiObj; } else { pHpiObj->regs = (CSL_HpiRegsOvly)NULL; pHpiObj->hpiNum = (CSL_InstNum)-1; } } return (hHpi); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcClose.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** * @file csl_intcClose.c * * @brief File for functional layer of CSL API CSL_intcClose() * * PATH $(CSLPATH)\src\intc */ /* ============================================================================= * Revision History * =============== * 12-Jun-2004 <NAME> File Created * * 16-Mar-2005 brn modified for doxygen documentation * ============================================================================= */ #include <csl_intc.h> #include <_csl_intc.h> #include <csl_intcAux.h> /** ============================================================================ * @n@b CSL_intcClose * * @b Description * @n This intc Handle can no longer be used to access the event. The event is * de-allocated and further access to the event resources are possible only * after opening the event object again. * * @b Arguments * @verbatim hIntc Handle identifying the event @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Close successful * @li CSL_INTC_BADHANDLE - The handle passed is invalid * * Pre Condition * @n Functions CSL_intcInit() and CSL_intcOpen() have to be called in that * order successfully before calling this function. * * Post Condition * @n The intc CSL APIs can not be called until the intc CSL is reopened * again using CSL_intcOpen() * * @b Modifies * @n None * * @b Example * @verbatim CSL_IntcContext context; CSL_Status intStat; CSL_IntcParam vectId; CSL_IntcObj intcObj20; CSL_IntcHandle hIntc20; CSL_IntcEventHandlerRecord recordTable[10]; context.numEvtEntries = 10; context.eventhandlerRecord = &recordTable; // Init Module ... if (CSL_intcInit(&context) != CSL_SOK) { exit; // Opening a handle for the Event 20 at vector id 4 vectId = CSL_INTC_VECTID_4; hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId, \ NULL); // Close handle CSL_IntcClose(hIntc20); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_intcClose, ".text:csl_section:intc"); CSL_Status CSL_intcClose ( CSL_IntcHandle hIntc ) { CSL_Status closeStatus = CSL_ESYS_BADHANDLE; Uint32 evt; Uint32 x; Uint32 y; if (hIntc != (CSL_IntcHandle) CSL_INTC_BADHANDLE) { evt = (Uint32)(hIntc->eventId); y = evt >> 5; x = 1 << (evt & 0x1f); asm(" dint"); _CSL_intcAllocMask[y] &= ~x; /* clear bit -> unused */ if (_CSL_intcEventOffsetMap[hIntc->eventId] != CSL_INTC_MAPPED_NONE) { _CSL_intcEventHandlerRecord [_CSL_intcEventOffsetMap[hIntc->eventId]].handler = CSL_INTC_EVTHANDLER_NONE; _CSL_intcEventOffsetMap[hIntc->eventId] = CSL_INTC_MAPPED_NONE; } hIntc = (CSL_IntcHandle) CSL_INTC_BADHANDLE; asm(" rint"); closeStatus = CSL_SOK; } return closeStatus; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/inc/csl_ddr2Aux.h

<filename>DSP/TI-Header/csl_c6455_src/inc/csl_ddr2Aux.h<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied. * ============================================================================ */ /** ============================================================================ * @file csl_ddr2Aux.h * * @path $(CSLPATH)\inc * * @desc Header file for functional layer of CSL * - The defines inline function definitions * */ /* ============================================================================= * Revision History * =============== * 11-Apr-2005 RM File Created. * * 05-Oct-2005 NG Updation done according to new register layer * * ============================================================================= */ #ifndef _CSL_DDR2AUX_H_ #define _CSL_DDR2AUX_H_ #include <csl_ddr2.h> #ifdef __cplusplus extern "C" { #endif /** * Status query functions of the DDR2 EMIF */ /** ============================================================================ * @n@b CSL_ddr2GetRevId * * @b Description * @n Gets the the current value of Rev ID value of DDR2 external memory * interface * * @b Arguments * @verbatim hDdr2 Handle to the external memory interface instance status Revision status structure * @endverbatim * * Return Value * None * * Pre Condition * @n None * * Post Condition * @n assigns the current value of the revision status of DDR2 external * @n memory interface to the rev status structure parameter passed as * parameter * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; CSL_Ddr2ModIdRev status; CSL_ddr2GetRevId(hDdr2, status); ... @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_ddr2GetRevId ( CSL_Ddr2Handle hDdr2, CSL_Ddr2ModIdRev *status ) { status->modId = (Uint16)CSL_FEXT(hDdr2->regs->MIDR, DDR2_MIDR_MOD_ID); status->majRev = (Uint8)CSL_FEXT(hDdr2->regs->MIDR, DDR2_MIDR_MJ_REV); status->minRev = (Uint8)CSL_FEXT(hDdr2->regs->MIDR, DDR2_MIDR_MN_REV); } /** ============================================================================ * @n@b CSL_ddr2GetEndian * * @b Description * @n Gets the the current endian of DDR2 emif from the SDRAM Status register * * @b Arguments * @verbatim hDdr2 Handle to the external memory interface instance response holds the endian of DDR2 after function call * @endverbatim * * Return Value * None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; Bool *response; CSL_ddr2GetEndian(hDdr2, response); ... @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_ddr2GetEndian ( CSL_Ddr2Handle hDdr2, Uint8 *response ) { *(response) = (Uint8)CSL_FEXT(hDdr2->regs->DMCSTAT, DDR2_DMCSTAT_BE); } /** ============================================================================ * @n@b CSL_ddr2GetIFRDY * * @b Description * @n Gets the the current IFRDY status of DDR2 emif from the SDRAM * Status register * * @b Arguments * @verbatim hDdr2 Handle to the external memory interface instance response holds IFRDY status after function call * @endverbatim * * Return Value * @n None * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; Bool *response; CSL_ddr2GetIFRDY(hDdr2, response); ... @endverbatim * ============================================================================ */ CSL_IDEF_INLINE void CSL_ddr2GetIFRDY ( CSL_Ddr2Handle hDdr2, Uint8 *response ) { *(response) = (Uint8)CSL_FEXT(hDdr2->regs->DMCSTAT, DDR2_DMCSTAT_IFRDY); } /** ============================================================================ * @n@b CSL_ddr2GetRefreshRate * * @b Description * @n Gets the refresh rate information of the DDR2 external memory interface * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 external memory interface instance * @endverbatim * * Return Value Uint16 * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; Uint16 rate; rate = CSL_ddr2GetRefreshRate(hDdr2); ... @endverbatim * ============================================================================ */ CSL_IDEF_INLINE Uint16 CSL_ddr2GetRefreshRate ( CSL_Ddr2Handle hDdr2 ) { Uint16 rate; rate = (Uint16) CSL_FEXT(hDdr2->regs->SDRFC, DDR2_SDRFC_REFRESH_RATE); return rate; } /** ============================================================================ * @n@b CSL_ddr2GetSlfRfrsh * * @b Description * @n Gets the DDR2 EMIF self refresh status * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 external memory interface instance * @endverbatim * * Return Value CSL_Ddr2SelfRefresh * * Pre Condition * @n None * * Post Condition * @n None * * @b Modifies * @n None * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; CSL_Ddr2SelfRefresh ddrStatus; ddrStatus = CSL_ddr2GetSlfRfrsh(hDdr2); ... @endverbatim * =========================================================================== */ CSL_IDEF_INLINE CSL_Ddr2SelfRefresh CSL_ddr2GetSlfRfrsh ( CSL_Ddr2Handle hDdr2 ) { CSL_Ddr2SelfRefresh status; status = (CSL_Ddr2SelfRefresh)CSL_FEXT(hDdr2->regs->SDRFC, DDR2_SDRFC_SR); return status; } /** * Control command functions external memory interface */ /** ============================================================================ * @n@b CSL_ddr2Selfrefresh * * @b Description * This API sets or clears the sr bit in Refresh Control register according * to the arg passed * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 EMIF instance val Value to refresh @endverbatim * * Return Value * None * * Pre Condition * @n 1) CSL_ddr2Init () and CSL_ddr2Open should be successfully called. * * Post Condition * @n 1) Setting the bit places DDR2 EMIF into self refresh state * 2) Clearing the bit takes it out of self refresh state * * @b Modifies * @n sr bit in SDRAM Refresh Control register * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; void *arg; (CSL_Ddr2SelfRefresh) *arg = CSL_DDR2_SELF_REFRESH_ENABLE; ... CSL_ddr2Selfrefresh(hDdr2, arg); ... @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_ddr2Selfrefresh ( CSL_Ddr2Handle hDdr2, CSL_Ddr2SelfRefresh val ) { CSL_FINS(hDdr2->regs->SDRFC, DDR2_SDRFC_SR, val); } /** ============================================================================ * @n@b CSL_ddr2RefreshRate * * @b Description * This API sets the refresh rate value with the value of arg passed as * parameter * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 EMIF instance val refresh rate value @endverbatim * * Return Value * None * * Pre Condition * @n CSL_ddr2Init () and CSL_ddr2Open should be successfully called. * * Post Condition * @n DDR2 refresh rate will be set with the argument passed * * @b Modifies * @n SDRAM Refresh control register * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; void *arg; (Uint16) *arg = 0x00010; ... CSL_ddr2RefreshRate(hDdr2, arg); ... @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_ddr2RefreshRate ( CSL_Ddr2Handle hDdr2, Uint16 refRate ) { CSL_FINS(hDdr2->regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, refRate); } /** ============================================================================ * @n@b CSL_ddr2PrioRaise * * @b Description * This API writes the arg passed into the pr_old_count field of VBUSM * Burst Priority register. * * @b Arguments * @verbatim hDdr2 Handle to the DDR2 EMIF val Value to raise priority value @endverbatim * * Return Value * None * * Pre Condition * @n CSL_ddr2Init () and CSL_ddr2Open should be successfully called. * * Post Condition * @n None * * @b Modifies * @n VBUSM Burst Priority register * * @b Example * @verbatim CSL_Ddr2Handle hDdr2; void *arg; (Uint8) *arg = 0x00010; ... CSL_ddr2PrioRaise(hDdr2, arg); ... @endverbatim * =========================================================================== */ CSL_IDEF_INLINE void CSL_ddr2PrioRaise ( CSL_Ddr2Handle hDdr2, Uint8 val ) { CSL_FINS(hDdr2->regs->BPRIO, DDR2_BPRIO_PRIO_RAISE, val); } #ifdef __cplusplus } #endif #endif /* _CSL_DDR2AUX_H_ */

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcHwSetupRaw.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * ============================================================================ */ /** @file csl_pllcHwSetupRaw.c * * @brief File for functional layer of CSL API @a CSL_pllcHwSetupRaw() * * Path: \(CSLPATH)\src\pllc * */ /* ============================================================================ * Revision History * =============== * 10-Feb-2004 kpn File Created. * 25-Aug-2005 Tej File Modified. * 17-Jan-2006 sd Changes according to spec changes * ============================================================================ */ #include <csl_pllc.h> /** ============================================================================ * @n@b CSL_pllcHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hpllc Handle to the PLLC instance config Pointer to config structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not properly initialized * * Pre Condition * @n None * * Post Condition * @n The registers of the specified PLLC instance will be setup * according to input configuration structure values. * * @b Modifies * @n Hardware registers of the specified PLLC instance. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcConfig config = CSL_PLLC_CONFIG_DEFAULTS; CSL_Status status; ... status = CSL_pllcHwSetupRaw (hPllc, &config); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_pllcHwSetupRaw, ".text:csl_section:pllc"); CSL_Status CSL_pllcHwSetupRaw ( CSL_PllcHandle hPllc, CSL_PllcConfig *config ) { CSL_Status status = CSL_SOK; volatile Uint32 loopCount; if (hPllc == NULL) { status = CSL_ESYS_BADHANDLE; } else if (config == NULL) { status = CSL_ESYS_INVPARAMS; } else { loopCount = 65000; /* Set PLLCTL, PLLENSRC bit to 0 first to modify PLLEN bit */ if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLENSRC, CSL_PLLC_PLLCTL_PLLENSRC_REGBIT); /* Ensure that PLLCTL is not in the PLL Mode */ CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLEN, CSL_PLLC_PLLCTL_PLLEN_BYPASS); CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLRST, CSL_PLLC_PLLCTL_PLLRST_YES); /* Ensure that PLLCTL is not in the Power-Down state */ CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLPWRDN, CSL_PLLC_PLLCTL_PLLPWRDN_NO); /* PLL Multiplier Control register */ hPllc->regs->PLLM = config->PLLM; /* PLL Pre-Divider Control register */ hPllc->regs->PREDIV = config->PREDIV; /* PLL Controller Divider 4 register */ hPllc->regs->PLLDIV4 = config->PLLDIV4; /* PLL Controller Divider 5 register */ hPllc->regs->PLLDIV5 = config->PLLDIV5; } /* PLL Controller Divider 1 register if instance is 2 */ if (hPllc->pllcNum == CSL_PLLC_2) { hPllc->regs->PLLDIV1 = config->PLLDIV1; } /* Set GOSET bit to change/set the dividers */ CSL_FINS (hPllc->regs->PLLCMD, PLLC_PLLCMD_GOSET, CSL_PLLC_PLLCMD_GOSET_SET); while (CSL_FEXT (hPllc->regs->PLLSTAT, PLLC_PLLSTAT_GOSTAT)) { /* Poll for divide-ratio change and clock alignment to complete */ } if (hPllc->pllcNum == CSL_PLLC_1) { CSL_FINS (hPllc->regs->PLLCTL, PLLC_PLLCTL_PLLRST, CSL_PLLC_PLLCTL_PLLRST_NO); /* Wait for 4 cycles of the slowest of the CLKIN/OSCIN * Introducing some arbitrary delay. */ loopCount = 65000; while (loopCount--) { asm(" NOP"); } /* PLL Control register */ hPllc->regs->PLLCTL = config->PLLCTL; } } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/FB_Example/main.c

#include <stdio.h> #include <string.h> #include <cslr_pllc.h> #include <cslr_gpio.h> #include <cslr_emifa.h> #include <cslr_ddr2.h> #include <cslr_dev.h> #include <cslr_intc.h> #include <cslr_chip.h> #include <cslr_edma3cc.h> #include <cslr_tmr.h> #include <soc.h> #include <math.h> #include <c6x.h> extern void intcVectorTable(void); #include "main.h" #include "version.h" #include "MEA21_lib.h" char dsp_version[] = "(>)"SW_STRING"(<)"; CSL_GpioRegsOvly gpioRegs = (CSL_GpioRegsOvly)CSL_GPIO_0_REGS; void timer_setup() { CSL_TmrRegsOvly tmr1Regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; // clear TIM12 register CSL_FINST(tmr1Regs->TIMLO,TMR_TIMLO_TIMLO,RESETVAL); CSL_FINS(tmr1Regs->TCR, TMR_TCR_CLKSRC_LO, 0); // select 32 bit unchained mode and take the timer out of reset CSL_FINS(tmr1Regs->TGCR, TMR_TGCR_TIMMODE, 1); // 32bit unchained CSL_FINST(tmr1Regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); } void timer_setperiod(int period) { CSL_TmrRegsOvly tmr1Regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; CSL_FINST(tmr1Regs->TCR, TMR_TCR_ENAMODE_LO, DISABLE); CSL_FINS(tmr1Regs->PRDLO,TMR_PRDLO_PRDLO, period); CSL_FINST(tmr1Regs->TIMLO,TMR_TIMLO_TIMLO,RESETVAL); CSL_FINS(tmr1Regs->TCR, TMR_TCR_ENAMODE_LO, 2); // continous mode } void main() { static int count = 0; int count_test1; int count_test2; static int value = 0; volatile int i; int StimAmplitude; int StimPeriod; int StimRepeats; int StimStepsize; MEA21_init(); // Communication betwen USB and DSP via i2c //init_i2c(); //IER |= 0x20; // enable CPUINT5 (i2c) WRITE_REGISTER(DSP_INDATA_CTRL, DSPINDATACTRL_VALUE); // Enable Irq and HS1 Data #ifdef USE_SIMULATOR timer_setup(); timer_setperiod(1000); IER |= 0x80; // enable CPUINT7 (timer) #else timer_setup(); timer_setperiod(13653332); // 10 Hz timer frequency, blink LED with 5 Hz IER |= 0x80; // enable CPUINT7 (timer) #endif WRITE_REGISTER(0x318, 0x1); // set AUX 1 as output threshold = READ_REGISTER(0x1000); deadtime = READ_REGISTER(0x1004); StimAmplitude = READ_REGISTER(0x1008); StimPeriod = READ_REGISTER(0x100c); StimRepeats = READ_REGISTER(0x1010); StimStepsize = READ_REGISTER(0x1014); // WRITE_REGISTER(0x9200, 0x10000000; // Inititialze STG Memory, use only one segment WRITE_REGISTER(0x9200, 0x20000000); // Inititialze STG Memory, use 256 segments #ifndef USE_SIMULATOR while (READ_REGISTER(0x9200) & 0x30000000); // wait for segment initialization to finish #endif WRITE_REGISTER(0x0310, 0x0); // set AUX 1 to value 0 WRITE_REGISTER(0x0310, 0x1); // set AUX 1 to value one SetSegment(0, 0); // select Segment 0 for DAC 1 SetSegment(1, 0); // select Segment 0 for Sideband 1 UploadSine(0, StimAmplitude, StimPeriod, StimRepeats, StimStepsize); SetSegment(0, 1); // select Segment 1 for DAC 1 SetSegment(1, 1); // select Segment 0 for Sideband 1 UploadSine(0, StimAmplitude/2, StimPeriod, StimRepeats, StimStepsize); WRITE_REGISTER(0x0310, 0x0); // set AUX 1 to value 0 SetupTrigger(); while(1) { WRITE_REGISTER(0x002C, 0x700 + 1*value); for (i = 0; i < 100000; i++); value = 1 - value; // switch on/off } } void UploadSine(int Channel, int Amplitude, int Period, int Repeats, int Stepsize) { int yold = 0; int duration = 0; int datapoints = 0; volatile int i; int y; int vectors_used; vectors_used = 0; ClearChannel(Channel); for (i = 0; i < Period; i++) { y = Amplitude * sin((((double)i)/Period)*2*3.1415); // y = -(Amplitude *i)/Period; if (abs(y - yold) > Stepsize) { vectors_used += AddDataPoint(Channel, duration, yold+0x8000); datapoints++; yold = y; duration = 1; // 20 us } else { duration++; } } vectors_used += AddDataPoint(Channel, duration, yold+0x8000); AddLoop(Channel, vectors_used, Repeats); // Create Sideband Information ClearChannel(Channel+1); vectors_used = 0; vectors_used += AddDataPoint(Channel+1, Period, 0x0019); AddLoop(Channel+1, vectors_used, Repeats); // AddDataPoint(Channel+1, 10, 0x0009); // keep Electrode connected to ground after stimulation } void AddLoop(int Channel, int Vectors, int Repeats) { Uint32 ChannelReg; Uint32 LoopVector; ChannelReg = 0x9f20 + Channel*4; if (Repeats > 1) { LoopVector = 0x10000000 | (Repeats << 16) | Vectors; WRITE_REGISTER(ChannelReg, LoopVector); } } void SetSegment(int Channel, int Segment) { Uint32 SegmentReg = 0x9200 + Channel*0x20; WRITE_REGISTER(SegmentReg, Segment); // Any write to this register clears the Channeldata } void ClearChannel(int Channel) { Uint32 ClearReg = 0x920c + Channel*0x20; WRITE_REGISTER(ClearReg, 0); // Any write to this register clears the Channeldata } int AddDataPoint(int Channel, int duration, int value) { int vectors_used = 0; int Vector; Uint32 ChannelReg = 0x9f20 + Channel*4; if (duration > 1000) { Vector = 0x04000000 | (((duration / 1000) - 1) << 16) | (value & 0xffff); WRITE_REGISTER(ChannelReg, Vector); // Write Datapoint to STG Memory duration %= 1000; vectors_used++; } if (duration > 0) { Vector = ((duration - 1) << 16) | (value & 0xffff); WRITE_REGISTER(ChannelReg, Vector); // Write Datapoint to STG Memory vectors_used++; } return vectors_used; } void SetupTrigger() { WRITE_REGISTER(0x0200, 0x1); // Enable Trigger Packets WRITE_REGISTER(0x0204, 0x0); // Setup Trigger WRITE_REGISTER(0x0208, 0x0); // Setup Trigger WRITE_REGISTER(0x020c, 0x0); // Setup Trigger WRITE_REGISTER(0x0210, 0x0); // Setup Trigger WRITE_REGISTER(0x0218, 0x0); // Setup Trigger WRITE_REGISTER(0x021c, 0x0); // Setup Trigger WRITE_REGISTER(0x0220, 0x0); // Setup Trigger WRITE_REGISTER(0x0224, 0x0); // Setup Trigger WRITE_REGISTER(0x0228, 0x0); // Setup Trigger WRITE_REGISTER(0x022c, 0x0); // Setup Trigger WRITE_REGISTER(0x9190, 1); // Trigger 1 Repeat WRITE_REGISTER(0x9194, 1); // Trigger 2 Repeat WRITE_REGISTER(0x9198, 1); // Trigger 3 Repeat WRITE_REGISTER(0x9104, 0x00020100); // DAC1 to Trigger1, DAC2 to Trigger2, DAC3 to Trigger3 WRITE_REGISTER(0x9108, 0x00020100); // SBS1 to Trigger1, SBS2 to Trigger2, SBS3 to Trigger3 } // Mask: Set to 1 for each bit which is to be modified // Value: New Value for modified bits void ModifyRegister(Uint32 reg, Uint32 Mask, Uint32 Value) { Uint32 Temp; Temp = READ_REGISTER(reg); Temp &= ~Mask; Temp |= (Value & Mask); WRITE_REGISTER(reg, Temp); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspHwSetupRaw.c

<filename>DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspHwSetupRaw.c<gh_stars>0 /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file csl_mcbspHwSetupRaw.c * * @path $(CSLPATH)\src\mcbsp * * @desc File for functional layer of CSL API CSL_mcbspHwSetupRaw() * */ /* ============================================================================= * Revision History * =============== * 15-Feb-2005 NSR File Created. * * 04-Jul-2005 ds - Register naming convention used for * multichannel registers are changed according * the changes in cslr_mcbsp.h * 21-Sep-2005 ds - Removed the DXR and DRR register from config * data structure * ============================================================================= */ #include <csl_mcbsp.h> /** ============================================================================ * @n@b CSL_mcbspHwSetupRaw * * @b Description * @n This function initializes the device registers with the register-values * provided through the Config Data structure. * * @b Arguments * @verbatim hMcbsp Handle to the Mcbsp instance config Pointer to config structure @endverbatim * * Return Value CSL_Status * @li CSL_SOK - Configuration successful * @li CSL_ESYS_BADHANDLE - Invalid handle * @li CSL_ESYS_INVPARAMS - Configuration is not * properly initialized * * Pre Condition * @n Both CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully * in that order before this function can be called. * * Post Condition * @n The registers of the specified MCBSP instance will be configured * according to value passed. * * @b Modifies * @n Hardware registers of the specified MCBSP instance. * * @b Example * @verbatim CSL_McbspHandle hMcbsp; CSL_McbspConfig config; CSL_Status status; config.SPCR = 0x02008000; config.RCR = 0x010001A0; config.XCR = 0x010001A0; config.SRGR = 0x200F010F; config.PCR = 0x00000A00; // Init Successfully done CSL_mcbspInit (NULL); // Open Successfully done hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL, &status); status = CSL_mcbspHwSetupRaw (hMcbsp, &config); @endverbatim * ============================================================================= */ #pragma CODE_SECTION (CSL_mcbspHwSetupRaw, ".text:csl_section:mcbsp"); CSL_Status CSL_mcbspHwSetupRaw ( CSL_McbspHandle hMcbsp, CSL_McbspConfig *config ) { CSL_Status status = CSL_SOK; if (hMcbsp == NULL) { status = CSL_ESYS_BADHANDLE; } else if (config == NULL ) { status = CSL_ESYS_INVPARAMS; } else{ hMcbsp->regs->SPCR = config->SPCR; hMcbsp->regs->RCR = config->RCR ; hMcbsp->regs->XCR = config->XCR ; hMcbsp->regs->SRGR = config->SRGR; hMcbsp->regs->MCR = config->MCR ; hMcbsp->regs->RCERE0 = config->RCERE0; hMcbsp->regs->XCERE0 = config->XCERE0; hMcbsp->regs->PCR = config->PCR ; hMcbsp->regs->RCERE1 = config->RCERE1; hMcbsp->regs->XCERE1 = config->XCERE1; hMcbsp->regs->RCERE2 = config->RCERE2; hMcbsp->regs->XCERE2 = config->XCERE2; hMcbsp->regs->RCERE3 = config->RCERE3; hMcbsp->regs->XCERE3 = config->XCERE3; } return status; }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c64xplus_intc_src/inc/cslr_intc.h

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ * @file cslr_intc.h * * @path $(CSLPATH)\inc * * @desc This file contains the Register Descriptions for INTC */ #ifndef _CSLR_INTC_H_ #define _CSLR_INTC_H_ #include <cslr.h> #include <tistdtypes.h> /**************************************************************************\ * Register Overlay Structure \**************************************************************************/ typedef struct { volatile Uint32 EVTFLAG[4]; volatile Uint8 RSVD0[16]; volatile Uint32 EVTSET[4]; volatile Uint8 RSVD1[16]; volatile Uint32 EVTCLR[4]; volatile Uint8 RSVD2[48]; volatile Uint32 EVTMASK[4]; volatile Uint8 RSVD3[16]; volatile Uint32 MEVTFLAG[4]; volatile Uint8 RSVD4[16]; volatile Uint32 EXPMASK[4]; volatile Uint8 RSVD5[16]; volatile Uint32 MEXPFLAG[4]; volatile Uint8 RSVD6[20]; volatile Uint32 INTMUX1; volatile Uint32 INTMUX2; volatile Uint32 INTMUX3; volatile Uint8 RSVD7[112]; volatile Uint32 INTXSTAT; volatile Uint32 INTXCLR; volatile Uint32 INTDMASK; } CSL_IntcRegs; /**************************************************************************\ * Overlay structure typedef definition \**************************************************************************/ typedef volatile CSL_IntcRegs *CSL_IntcRegsOvly; /**************************************************************************\ * Field Definition Macros \**************************************************************************/ /* EVTFLAG */ #define CSL_INTC_EVTFLAG_EF31_MASK (0x80000000u) #define CSL_INTC_EVTFLAG_EF31_SHIFT (0x0000001Fu) #define CSL_INTC_EVTFLAG_EF31_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF30_MASK (0x40000000u) #define CSL_INTC_EVTFLAG_EF30_SHIFT (0x0000001Eu) #define CSL_INTC_EVTFLAG_EF30_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF29_MASK (0x20000000u) #define CSL_INTC_EVTFLAG_EF29_SHIFT (0x0000001Du) #define CSL_INTC_EVTFLAG_EF29_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF28_MASK (0x10000000u) #define CSL_INTC_EVTFLAG_EF28_SHIFT (0x0000001Cu) #define CSL_INTC_EVTFLAG_EF28_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF27_MASK (0x08000000u) #define CSL_INTC_EVTFLAG_EF27_SHIFT (0x0000001Bu) #define CSL_INTC_EVTFLAG_EF27_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF26_MASK (0x04000000u) #define CSL_INTC_EVTFLAG_EF26_SHIFT (0x0000001Au) #define CSL_INTC_EVTFLAG_EF26_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF25_MASK (0x02000000u) #define CSL_INTC_EVTFLAG_EF25_SHIFT (0x00000019u) #define CSL_INTC_EVTFLAG_EF25_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF24_MASK (0x01000000u) #define CSL_INTC_EVTFLAG_EF24_SHIFT (0x00000018u) #define CSL_INTC_EVTFLAG_EF24_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF23_MASK (0x00800000u) #define CSL_INTC_EVTFLAG_EF23_SHIFT (0x00000017u) #define CSL_INTC_EVTFLAG_EF23_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF22_MASK (0x00400000u) #define CSL_INTC_EVTFLAG_EF22_SHIFT (0x00000016u) #define CSL_INTC_EVTFLAG_EF22_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF21_MASK (0x00200000u) #define CSL_INTC_EVTFLAG_EF21_SHIFT (0x00000015u) #define CSL_INTC_EVTFLAG_EF21_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF20_MASK (0x00100000u) #define CSL_INTC_EVTFLAG_EF20_SHIFT (0x00000014u) #define CSL_INTC_EVTFLAG_EF20_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF19_MASK (0x00080000u) #define CSL_INTC_EVTFLAG_EF19_SHIFT (0x00000013u) #define CSL_INTC_EVTFLAG_EF19_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF18_MASK (0x00040000u) #define CSL_INTC_EVTFLAG_EF18_SHIFT (0x00000012u) #define CSL_INTC_EVTFLAG_EF18_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF17_MASK (0x00020000u) #define CSL_INTC_EVTFLAG_EF17_SHIFT (0x00000011u) #define CSL_INTC_EVTFLAG_EF17_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF16_MASK (0x00010000u) #define CSL_INTC_EVTFLAG_EF16_SHIFT (0x00000010u) #define CSL_INTC_EVTFLAG_EF16_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF15_MASK (0x00008000u) #define CSL_INTC_EVTFLAG_EF15_SHIFT (0x0000000Fu) #define CSL_INTC_EVTFLAG_EF15_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF14_MASK (0x00004000u) #define CSL_INTC_EVTFLAG_EF14_SHIFT (0x0000000Eu) #define CSL_INTC_EVTFLAG_EF14_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF13_MASK (0x00002000u) #define CSL_INTC_EVTFLAG_EF13_SHIFT (0x0000000Du) #define CSL_INTC_EVTFLAG_EF13_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF12_MASK (0x00001000u) #define CSL_INTC_EVTFLAG_EF12_SHIFT (0x0000000Cu) #define CSL_INTC_EVTFLAG_EF12_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF11_MASK (0x00000800u) #define CSL_INTC_EVTFLAG_EF11_SHIFT (0x0000000Bu) #define CSL_INTC_EVTFLAG_EF11_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF10_MASK (0x00000400u) #define CSL_INTC_EVTFLAG_EF10_SHIFT (0x0000000Au) #define CSL_INTC_EVTFLAG_EF10_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF9_MASK (0x00000200u) #define CSL_INTC_EVTFLAG_EF9_SHIFT (0x00000009u) #define CSL_INTC_EVTFLAG_EF9_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF8_MASK (0x00000100u) #define CSL_INTC_EVTFLAG_EF8_SHIFT (0x00000008u) #define CSL_INTC_EVTFLAG_EF8_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF7_MASK (0x00000080u) #define CSL_INTC_EVTFLAG_EF7_SHIFT (0x00000007u) #define CSL_INTC_EVTFLAG_EF7_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF6_MASK (0x00000040u) #define CSL_INTC_EVTFLAG_EF6_SHIFT (0x00000006u) #define CSL_INTC_EVTFLAG_EF6_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF5_MASK (0x00000020u) #define CSL_INTC_EVTFLAG_EF5_SHIFT (0x00000005u) #define CSL_INTC_EVTFLAG_EF5_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF4_MASK (0x00000010u) #define CSL_INTC_EVTFLAG_EF4_SHIFT (0x00000004u) #define CSL_INTC_EVTFLAG_EF4_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF3_MASK (0x00000008u) #define CSL_INTC_EVTFLAG_EF3_SHIFT (0x00000003u) #define CSL_INTC_EVTFLAG_EF3_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF2_MASK (0x00000004u) #define CSL_INTC_EVTFLAG_EF2_SHIFT (0x00000002u) #define CSL_INTC_EVTFLAG_EF2_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF1_MASK (0x00000002u) #define CSL_INTC_EVTFLAG_EF1_SHIFT (0x00000001u) #define CSL_INTC_EVTFLAG_EF1_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_EF0_MASK (0x00000001u) #define CSL_INTC_EVTFLAG_EF0_SHIFT (0x00000000u) #define CSL_INTC_EVTFLAG_EF0_RESETVAL (0x00000000u) #define CSL_INTC_EVTFLAG_RESETVAL (0x00000000u) /* EVTSET */ #define CSL_INTC_EVTSET_ES31_MASK (0x80000000u) #define CSL_INTC_EVTSET_ES31_SHIFT (0x0000001Fu) #define CSL_INTC_EVTSET_ES31_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES30_MASK (0x40000000u) #define CSL_INTC_EVTSET_ES30_SHIFT (0x0000001Eu) #define CSL_INTC_EVTSET_ES30_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES29_MASK (0x20000000u) #define CSL_INTC_EVTSET_ES29_SHIFT (0x0000001Du) #define CSL_INTC_EVTSET_ES29_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES28_MASK (0x10000000u) #define CSL_INTC_EVTSET_ES28_SHIFT (0x0000001Cu) #define CSL_INTC_EVTSET_ES28_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES27_MASK (0x08000000u) #define CSL_INTC_EVTSET_ES27_SHIFT (0x0000001Bu) #define CSL_INTC_EVTSET_ES27_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES26_MASK (0x04000000u) #define CSL_INTC_EVTSET_ES26_SHIFT (0x0000001Au) #define CSL_INTC_EVTSET_ES26_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES25_MASK (0x02000000u) #define CSL_INTC_EVTSET_ES25_SHIFT (0x00000019u) #define CSL_INTC_EVTSET_ES25_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES24_MASK (0x01000000u) #define CSL_INTC_EVTSET_ES24_SHIFT (0x00000018u) #define CSL_INTC_EVTSET_ES24_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES23_MASK (0x00800000u) #define CSL_INTC_EVTSET_ES23_SHIFT (0x00000017u) #define CSL_INTC_EVTSET_ES23_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES22_MASK (0x00400000u) #define CSL_INTC_EVTSET_ES22_SHIFT (0x00000016u) #define CSL_INTC_EVTSET_ES22_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES21_MASK (0x00200000u) #define CSL_INTC_EVTSET_ES21_SHIFT (0x00000015u) #define CSL_INTC_EVTSET_ES21_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES20_MASK (0x00100000u) #define CSL_INTC_EVTSET_ES20_SHIFT (0x00000014u) #define CSL_INTC_EVTSET_ES20_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES19_MASK (0x00080000u) #define CSL_INTC_EVTSET_ES19_SHIFT (0x00000013u) #define CSL_INTC_EVTSET_ES19_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES18_MASK (0x00040000u) #define CSL_INTC_EVTSET_ES18_SHIFT (0x00000012u) #define CSL_INTC_EVTSET_ES18_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES17_MASK (0x00020000u) #define CSL_INTC_EVTSET_ES17_SHIFT (0x00000011u) #define CSL_INTC_EVTSET_ES17_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES16_MASK (0x00010000u) #define CSL_INTC_EVTSET_ES16_SHIFT (0x00000010u) #define CSL_INTC_EVTSET_ES16_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES15_MASK (0x00008000u) #define CSL_INTC_EVTSET_ES15_SHIFT (0x0000000Fu) #define CSL_INTC_EVTSET_ES15_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES14_MASK (0x00004000u) #define CSL_INTC_EVTSET_ES14_SHIFT (0x0000000Eu) #define CSL_INTC_EVTSET_ES14_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES13_MASK (0x00002000u) #define CSL_INTC_EVTSET_ES13_SHIFT (0x0000000Du) #define CSL_INTC_EVTSET_ES13_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES12_MASK (0x00001000u) #define CSL_INTC_EVTSET_ES12_SHIFT (0x0000000Cu) #define CSL_INTC_EVTSET_ES12_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES11_MASK (0x00000800u) #define CSL_INTC_EVTSET_ES11_SHIFT (0x0000000Bu) #define CSL_INTC_EVTSET_ES11_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES10_MASK (0x00000400u) #define CSL_INTC_EVTSET_ES10_SHIFT (0x0000000Au) #define CSL_INTC_EVTSET_ES10_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES9_MASK (0x00000200u) #define CSL_INTC_EVTSET_ES9_SHIFT (0x00000009u) #define CSL_INTC_EVTSET_ES9_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES8_MASK (0x00000100u) #define CSL_INTC_EVTSET_ES8_SHIFT (0x00000008u) #define CSL_INTC_EVTSET_ES8_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES7_MASK (0x00000080u) #define CSL_INTC_EVTSET_ES7_SHIFT (0x00000007u) #define CSL_INTC_EVTSET_ES7_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES6_MASK (0x00000040u) #define CSL_INTC_EVTSET_ES6_SHIFT (0x00000006u) #define CSL_INTC_EVTSET_ES6_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES5_MASK (0x00000020u) #define CSL_INTC_EVTSET_ES5_SHIFT (0x00000005u) #define CSL_INTC_EVTSET_ES5_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES4_MASK (0x00000010u) #define CSL_INTC_EVTSET_ES4_SHIFT (0x00000004u) #define CSL_INTC_EVTSET_ES4_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES3_MASK (0x00000008u) #define CSL_INTC_EVTSET_ES3_SHIFT (0x00000003u) #define CSL_INTC_EVTSET_ES3_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES2_MASK (0x00000004u) #define CSL_INTC_EVTSET_ES2_SHIFT (0x00000002u) #define CSL_INTC_EVTSET_ES2_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES1_MASK (0x00000002u) #define CSL_INTC_EVTSET_ES1_SHIFT (0x00000001u) #define CSL_INTC_EVTSET_ES1_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_ES0_MASK (0x00000001u) #define CSL_INTC_EVTSET_ES0_SHIFT (0x00000000u) #define CSL_INTC_EVTSET_ES0_RESETVAL (0x00000000u) #define CSL_INTC_EVTSET_RESETVAL (0x00000000u) /* EVTCLR */ #define CSL_INTC_EVTCLR_EC31_MASK (0x80000000u) #define CSL_INTC_EVTCLR_EC31_SHIFT (0x0000001Fu) #define CSL_INTC_EVTCLR_EC31_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC30_MASK (0x40000000u) #define CSL_INTC_EVTCLR_EC30_SHIFT (0x0000001Eu) #define CSL_INTC_EVTCLR_EC30_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC29_MASK (0x20000000u) #define CSL_INTC_EVTCLR_EC29_SHIFT (0x0000001Du) #define CSL_INTC_EVTCLR_EC29_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC28_MASK (0x10000000u) #define CSL_INTC_EVTCLR_EC28_SHIFT (0x0000001Cu) #define CSL_INTC_EVTCLR_EC28_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC27_MASK (0x08000000u) #define CSL_INTC_EVTCLR_EC27_SHIFT (0x0000001Bu) #define CSL_INTC_EVTCLR_EC27_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC26_MASK (0x04000000u) #define CSL_INTC_EVTCLR_EC26_SHIFT (0x0000001Au) #define CSL_INTC_EVTCLR_EC26_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC25_MASK (0x02000000u) #define CSL_INTC_EVTCLR_EC25_SHIFT (0x00000019u) #define CSL_INTC_EVTCLR_EC25_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC24_MASK (0x01000000u) #define CSL_INTC_EVTCLR_EC24_SHIFT (0x00000018u) #define CSL_INTC_EVTCLR_EC24_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC23_MASK (0x00800000u) #define CSL_INTC_EVTCLR_EC23_SHIFT (0x00000017u) #define CSL_INTC_EVTCLR_EC23_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC22_MASK (0x00400000u) #define CSL_INTC_EVTCLR_EC22_SHIFT (0x00000016u) #define CSL_INTC_EVTCLR_EC22_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC21_MASK (0x00200000u) #define CSL_INTC_EVTCLR_EC21_SHIFT (0x00000015u) #define CSL_INTC_EVTCLR_EC21_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC20_MASK (0x00100000u) #define CSL_INTC_EVTCLR_EC20_SHIFT (0x00000014u) #define CSL_INTC_EVTCLR_EC20_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC19_MASK (0x00080000u) #define CSL_INTC_EVTCLR_EC19_SHIFT (0x00000013u) #define CSL_INTC_EVTCLR_EC19_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC18_MASK (0x00040000u) #define CSL_INTC_EVTCLR_EC18_SHIFT (0x00000012u) #define CSL_INTC_EVTCLR_EC18_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC17_MASK (0x00020000u) #define CSL_INTC_EVTCLR_EC17_SHIFT (0x00000011u) #define CSL_INTC_EVTCLR_EC17_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC16_MASK (0x00010000u) #define CSL_INTC_EVTCLR_EC16_SHIFT (0x00000010u) #define CSL_INTC_EVTCLR_EC16_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC15_MASK (0x00008000u) #define CSL_INTC_EVTCLR_EC15_SHIFT (0x0000000Fu) #define CSL_INTC_EVTCLR_EC15_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC14_MASK (0x00004000u) #define CSL_INTC_EVTCLR_EC14_SHIFT (0x0000000Eu) #define CSL_INTC_EVTCLR_EC14_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC13_MASK (0x00002000u) #define CSL_INTC_EVTCLR_EC13_SHIFT (0x0000000Du) #define CSL_INTC_EVTCLR_EC13_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC12_MASK (0x00001000u) #define CSL_INTC_EVTCLR_EC12_SHIFT (0x0000000Cu) #define CSL_INTC_EVTCLR_EC12_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC11_MASK (0x00000800u) #define CSL_INTC_EVTCLR_EC11_SHIFT (0x0000000Bu) #define CSL_INTC_EVTCLR_EC11_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC10_MASK (0x00000400u) #define CSL_INTC_EVTCLR_EC10_SHIFT (0x0000000Au) #define CSL_INTC_EVTCLR_EC10_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC9_MASK (0x00000200u) #define CSL_INTC_EVTCLR_EC9_SHIFT (0x00000009u) #define CSL_INTC_EVTCLR_EC9_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC8_MASK (0x00000100u) #define CSL_INTC_EVTCLR_EC8_SHIFT (0x00000008u) #define CSL_INTC_EVTCLR_EC8_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC7_MASK (0x00000080u) #define CSL_INTC_EVTCLR_EC7_SHIFT (0x00000007u) #define CSL_INTC_EVTCLR_EC7_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC6_MASK (0x00000040u) #define CSL_INTC_EVTCLR_EC6_SHIFT (0x00000006u) #define CSL_INTC_EVTCLR_EC6_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC5_MASK (0x00000020u) #define CSL_INTC_EVTCLR_EC5_SHIFT (0x00000005u) #define CSL_INTC_EVTCLR_EC5_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC4_MASK (0x00000010u) #define CSL_INTC_EVTCLR_EC4_SHIFT (0x00000004u) #define CSL_INTC_EVTCLR_EC4_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC3_MASK (0x00000008u) #define CSL_INTC_EVTCLR_EC3_SHIFT (0x00000003u) #define CSL_INTC_EVTCLR_EC3_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC2_MASK (0x00000004u) #define CSL_INTC_EVTCLR_EC2_SHIFT (0x00000002u) #define CSL_INTC_EVTCLR_EC2_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC1_MASK (0x00000002u) #define CSL_INTC_EVTCLR_EC1_SHIFT (0x00000001u) #define CSL_INTC_EVTCLR_EC1_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_EC0_MASK (0x00000001u) #define CSL_INTC_EVTCLR_EC0_SHIFT (0x00000000u) #define CSL_INTC_EVTCLR_EC0_RESETVAL (0x00000000u) #define CSL_INTC_EVTCLR_RESETVAL (0x00000000u) /* EVTMASK */ #define CSL_INTC_EVTMASK_EM31_MASK (0x80000000u) #define CSL_INTC_EVTMASK_EM31_SHIFT (0x0000001Fu) #define CSL_INTC_EVTMASK_EM31_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM30_MASK (0x40000000u) #define CSL_INTC_EVTMASK_EM30_SHIFT (0x0000001Eu) #define CSL_INTC_EVTMASK_EM30_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM29_MASK (0x20000000u) #define CSL_INTC_EVTMASK_EM29_SHIFT (0x0000001Du) #define CSL_INTC_EVTMASK_EM29_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM28_MASK (0x10000000u) #define CSL_INTC_EVTMASK_EM28_SHIFT (0x0000001Cu) #define CSL_INTC_EVTMASK_EM28_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM27_MASK (0x08000000u) #define CSL_INTC_EVTMASK_EM27_SHIFT (0x0000001Bu) #define CSL_INTC_EVTMASK_EM27_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM26_MASK (0x04000000u) #define CSL_INTC_EVTMASK_EM26_SHIFT (0x0000001Au) #define CSL_INTC_EVTMASK_EM26_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM25_MASK (0x02000000u) #define CSL_INTC_EVTMASK_EM25_SHIFT (0x00000019u) #define CSL_INTC_EVTMASK_EM25_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM24_MASK (0x01000000u) #define CSL_INTC_EVTMASK_EM24_SHIFT (0x00000018u) #define CSL_INTC_EVTMASK_EM24_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM23_MASK (0x00800000u) #define CSL_INTC_EVTMASK_EM23_SHIFT (0x00000017u) #define CSL_INTC_EVTMASK_EM23_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM22_MASK (0x00400000u) #define CSL_INTC_EVTMASK_EM22_SHIFT (0x00000016u) #define CSL_INTC_EVTMASK_EM22_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM21_MASK (0x00200000u) #define CSL_INTC_EVTMASK_EM21_SHIFT (0x00000015u) #define CSL_INTC_EVTMASK_EM21_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM20_MASK (0x00100000u) #define CSL_INTC_EVTMASK_EM20_SHIFT (0x00000014u) #define CSL_INTC_EVTMASK_EM20_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM19_MASK (0x00080000u) #define CSL_INTC_EVTMASK_EM19_SHIFT (0x00000013u) #define CSL_INTC_EVTMASK_EM19_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM18_MASK (0x00040000u) #define CSL_INTC_EVTMASK_EM18_SHIFT (0x00000012u) #define CSL_INTC_EVTMASK_EM18_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM17_MASK (0x00020000u) #define CSL_INTC_EVTMASK_EM17_SHIFT (0x00000011u) #define CSL_INTC_EVTMASK_EM17_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM16_MASK (0x00010000u) #define CSL_INTC_EVTMASK_EM16_SHIFT (0x00000010u) #define CSL_INTC_EVTMASK_EM16_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM15_MASK (0x00008000u) #define CSL_INTC_EVTMASK_EM15_SHIFT (0x0000000Fu) #define CSL_INTC_EVTMASK_EM15_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM14_MASK (0x00004000u) #define CSL_INTC_EVTMASK_EM14_SHIFT (0x0000000Eu) #define CSL_INTC_EVTMASK_EM14_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM13_MASK (0x00002000u) #define CSL_INTC_EVTMASK_EM13_SHIFT (0x0000000Du) #define CSL_INTC_EVTMASK_EM13_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM12_MASK (0x00001000u) #define CSL_INTC_EVTMASK_EM12_SHIFT (0x0000000Cu) #define CSL_INTC_EVTMASK_EM12_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM11_MASK (0x00000800u) #define CSL_INTC_EVTMASK_EM11_SHIFT (0x0000000Bu) #define CSL_INTC_EVTMASK_EM11_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM10_MASK (0x00000400u) #define CSL_INTC_EVTMASK_EM10_SHIFT (0x0000000Au) #define CSL_INTC_EVTMASK_EM10_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM9_MASK (0x00000200u) #define CSL_INTC_EVTMASK_EM9_SHIFT (0x00000009u) #define CSL_INTC_EVTMASK_EM9_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM8_MASK (0x00000100u) #define CSL_INTC_EVTMASK_EM8_SHIFT (0x00000008u) #define CSL_INTC_EVTMASK_EM8_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM7_MASK (0x00000080u) #define CSL_INTC_EVTMASK_EM7_SHIFT (0x00000007u) #define CSL_INTC_EVTMASK_EM7_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM6_MASK (0x00000040u) #define CSL_INTC_EVTMASK_EM6_SHIFT (0x00000006u) #define CSL_INTC_EVTMASK_EM6_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM5_MASK (0x00000020u) #define CSL_INTC_EVTMASK_EM5_SHIFT (0x00000005u) #define CSL_INTC_EVTMASK_EM5_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM4_MASK (0x00000010u) #define CSL_INTC_EVTMASK_EM4_SHIFT (0x00000004u) #define CSL_INTC_EVTMASK_EM4_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM3_MASK (0x00000008u) #define CSL_INTC_EVTMASK_EM3_SHIFT (0x00000003u) #define CSL_INTC_EVTMASK_EM3_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM2_MASK (0x00000004u) #define CSL_INTC_EVTMASK_EM2_SHIFT (0x00000002u) #define CSL_INTC_EVTMASK_EM2_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM1_MASK (0x00000002u) #define CSL_INTC_EVTMASK_EM1_SHIFT (0x00000001u) #define CSL_INTC_EVTMASK_EM1_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_EM0_MASK (0x00000001u) #define CSL_INTC_EVTMASK_EM0_SHIFT (0x00000000u) #define CSL_INTC_EVTMASK_EM0_RESETVAL (0x00000000u) #define CSL_INTC_EVTMASK_RESETVAL (0x00000000u) /* MEVTFLAG */ #define CSL_INTC_MEVTFLAG_MEVT31_MASK (0x80000000u) #define CSL_INTC_MEVTFLAG_MEVT31_SHIFT (0x0000001Fu) #define CSL_INTC_MEVTFLAG_MEVT31_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT30_MASK (0x40000000u) #define CSL_INTC_MEVTFLAG_MEVT30_SHIFT (0x0000001Eu) #define CSL_INTC_MEVTFLAG_MEVT30_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT29_MASK (0x20000000u) #define CSL_INTC_MEVTFLAG_MEVT29_SHIFT (0x0000001Du) #define CSL_INTC_MEVTFLAG_MEVT29_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT28_MASK (0x10000000u) #define CSL_INTC_MEVTFLAG_MEVT28_SHIFT (0x0000001Cu) #define CSL_INTC_MEVTFLAG_MEVT28_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT27_MASK (0x08000000u) #define CSL_INTC_MEVTFLAG_MEVT27_SHIFT (0x0000001Bu) #define CSL_INTC_MEVTFLAG_MEVT27_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT26_MASK (0x04000000u) #define CSL_INTC_MEVTFLAG_MEVT26_SHIFT (0x0000001Au) #define CSL_INTC_MEVTFLAG_MEVT26_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT25_MASK (0x02000000u) #define CSL_INTC_MEVTFLAG_MEVT25_SHIFT (0x00000019u) #define CSL_INTC_MEVTFLAG_MEVT25_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT24_MASK (0x01000000u) #define CSL_INTC_MEVTFLAG_MEVT24_SHIFT (0x00000018u) #define CSL_INTC_MEVTFLAG_MEVT24_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT23_MASK (0x00800000u) #define CSL_INTC_MEVTFLAG_MEVT23_SHIFT (0x00000017u) #define CSL_INTC_MEVTFLAG_MEVT23_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT22_MASK (0x00400000u) #define CSL_INTC_MEVTFLAG_MEVT22_SHIFT (0x00000016u) #define CSL_INTC_MEVTFLAG_MEVT22_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT21_MASK (0x00200000u) #define CSL_INTC_MEVTFLAG_MEVT21_SHIFT (0x00000015u) #define CSL_INTC_MEVTFLAG_MEVT21_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT20_MASK (0x00100000u) #define CSL_INTC_MEVTFLAG_MEVT20_SHIFT (0x00000014u) #define CSL_INTC_MEVTFLAG_MEVT20_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT19_MASK (0x00080000u) #define CSL_INTC_MEVTFLAG_MEVT19_SHIFT (0x00000013u) #define CSL_INTC_MEVTFLAG_MEVT19_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT18_MASK (0x00040000u) #define CSL_INTC_MEVTFLAG_MEVT18_SHIFT (0x00000012u) #define CSL_INTC_MEVTFLAG_MEVT18_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT17_MASK (0x00020000u) #define CSL_INTC_MEVTFLAG_MEVT17_SHIFT (0x00000011u) #define CSL_INTC_MEVTFLAG_MEVT17_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT16_MASK (0x00010000u) #define CSL_INTC_MEVTFLAG_MEVT16_SHIFT (0x00000010u) #define CSL_INTC_MEVTFLAG_MEVT16_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT15_MASK (0x00008000u) #define CSL_INTC_MEVTFLAG_MEVT15_SHIFT (0x0000000Fu) #define CSL_INTC_MEVTFLAG_MEVT15_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT14_MASK (0x00004000u) #define CSL_INTC_MEVTFLAG_MEVT14_SHIFT (0x0000000Eu) #define CSL_INTC_MEVTFLAG_MEVT14_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT13_MASK (0x00002000u) #define CSL_INTC_MEVTFLAG_MEVT13_SHIFT (0x0000000Du) #define CSL_INTC_MEVTFLAG_MEVT13_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT12_MASK (0x00001000u) #define CSL_INTC_MEVTFLAG_MEVT12_SHIFT (0x0000000Cu) #define CSL_INTC_MEVTFLAG_MEVT12_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT11_MASK (0x00000800u) #define CSL_INTC_MEVTFLAG_MEVT11_SHIFT (0x0000000Bu) #define CSL_INTC_MEVTFLAG_MEVT11_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT10_MASK (0x00000400u) #define CSL_INTC_MEVTFLAG_MEVT10_SHIFT (0x0000000Au) #define CSL_INTC_MEVTFLAG_MEVT10_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT9_MASK (0x00000200u) #define CSL_INTC_MEVTFLAG_MEVT9_SHIFT (0x00000009u) #define CSL_INTC_MEVTFLAG_MEVT9_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT8_MASK (0x00000100u) #define CSL_INTC_MEVTFLAG_MEVT8_SHIFT (0x00000008u) #define CSL_INTC_MEVTFLAG_MEVT8_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT7_MASK (0x00000080u) #define CSL_INTC_MEVTFLAG_MEVT7_SHIFT (0x00000007u) #define CSL_INTC_MEVTFLAG_MEVT7_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT6_MASK (0x00000040u) #define CSL_INTC_MEVTFLAG_MEVT6_SHIFT (0x00000006u) #define CSL_INTC_MEVTFLAG_MEVT6_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT5_MASK (0x00000020u) #define CSL_INTC_MEVTFLAG_MEVT5_SHIFT (0x00000005u) #define CSL_INTC_MEVTFLAG_MEVT5_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT4_MASK (0x00000010u) #define CSL_INTC_MEVTFLAG_MEVT4_SHIFT (0x00000004u) #define CSL_INTC_MEVTFLAG_MEVT4_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT3_MASK (0x00000008u) #define CSL_INTC_MEVTFLAG_MEVT3_SHIFT (0x00000003u) #define CSL_INTC_MEVTFLAG_MEVT3_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT2_MASK (0x00000004u) #define CSL_INTC_MEVTFLAG_MEVT2_SHIFT (0x00000002u) #define CSL_INTC_MEVTFLAG_MEVT2_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT1_MASK (0x00000002u) #define CSL_INTC_MEVTFLAG_MEVT1_SHIFT (0x00000001u) #define CSL_INTC_MEVTFLAG_MEVT1_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT0_MASK (0x00000001u) #define CSL_INTC_MEVTFLAG_MEVT0_SHIFT (0x00000000u) #define CSL_INTC_MEVTFLAG_MEVT0_RESETVAL (0x00000000u) #define CSL_INTC_MEVTFLAG_RESETVAL (0x00000000u) /* EXPMASK */ #define CSL_INTC_EXPMASK_XM31_MASK (0x80000000u) #define CSL_INTC_EXPMASK_XM31_SHIFT (0x0000001Fu) #define CSL_INTC_EXPMASK_XM31_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM30_MASK (0x40000000u) #define CSL_INTC_EXPMASK_XM30_SHIFT (0x0000001Eu) #define CSL_INTC_EXPMASK_XM30_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM29_MASK (0x20000000u) #define CSL_INTC_EXPMASK_XM29_SHIFT (0x0000001Du) #define CSL_INTC_EXPMASK_XM29_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM28_MASK (0x10000000u) #define CSL_INTC_EXPMASK_XM28_SHIFT (0x0000001Cu) #define CSL_INTC_EXPMASK_XM28_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM27_MASK (0x08000000u) #define CSL_INTC_EXPMASK_XM27_SHIFT (0x0000001Bu) #define CSL_INTC_EXPMASK_XM27_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM26_MASK (0x04000000u) #define CSL_INTC_EXPMASK_XM26_SHIFT (0x0000001Au) #define CSL_INTC_EXPMASK_XM26_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM25_MASK (0x02000000u) #define CSL_INTC_EXPMASK_XM25_SHIFT (0x00000019u) #define CSL_INTC_EXPMASK_XM25_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM24_MASK (0x01000000u) #define CSL_INTC_EXPMASK_XM24_SHIFT (0x00000018u) #define CSL_INTC_EXPMASK_XM24_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM23_MASK (0x00800000u) #define CSL_INTC_EXPMASK_XM23_SHIFT (0x00000017u) #define CSL_INTC_EXPMASK_XM23_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM22_MASK (0x00400000u) #define CSL_INTC_EXPMASK_XM22_SHIFT (0x00000016u) #define CSL_INTC_EXPMASK_XM22_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM21_MASK (0x00200000u) #define CSL_INTC_EXPMASK_XM21_SHIFT (0x00000015u) #define CSL_INTC_EXPMASK_XM21_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM20_MASK (0x00100000u) #define CSL_INTC_EXPMASK_XM20_SHIFT (0x00000014u) #define CSL_INTC_EXPMASK_XM20_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM19_MASK (0x00080000u) #define CSL_INTC_EXPMASK_XM19_SHIFT (0x00000013u) #define CSL_INTC_EXPMASK_XM19_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM18_MASK (0x00040000u) #define CSL_INTC_EXPMASK_XM18_SHIFT (0x00000012u) #define CSL_INTC_EXPMASK_XM18_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM17_MASK (0x00020000u) #define CSL_INTC_EXPMASK_XM17_SHIFT (0x00000011u) #define CSL_INTC_EXPMASK_XM17_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM16_MASK (0x00010000u) #define CSL_INTC_EXPMASK_XM16_SHIFT (0x00000010u) #define CSL_INTC_EXPMASK_XM16_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM15_MASK (0x00008000u) #define CSL_INTC_EXPMASK_XM15_SHIFT (0x0000000Fu) #define CSL_INTC_EXPMASK_XM15_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM14_MASK (0x00004000u) #define CSL_INTC_EXPMASK_XM14_SHIFT (0x0000000Eu) #define CSL_INTC_EXPMASK_XM14_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM13_MASK (0x00002000u) #define CSL_INTC_EXPMASK_XM13_SHIFT (0x0000000Du) #define CSL_INTC_EXPMASK_XM13_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM12_MASK (0x00001000u) #define CSL_INTC_EXPMASK_XM12_SHIFT (0x0000000Cu) #define CSL_INTC_EXPMASK_XM12_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM11_MASK (0x00000800u) #define CSL_INTC_EXPMASK_XM11_SHIFT (0x0000000Bu) #define CSL_INTC_EXPMASK_XM11_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM10_MASK (0x00000400u) #define CSL_INTC_EXPMASK_XM10_SHIFT (0x0000000Au) #define CSL_INTC_EXPMASK_XM10_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM9_MASK (0x00000200u) #define CSL_INTC_EXPMASK_XM9_SHIFT (0x00000009u) #define CSL_INTC_EXPMASK_XM9_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM8_MASK (0x00000100u) #define CSL_INTC_EXPMASK_XM8_SHIFT (0x00000008u) #define CSL_INTC_EXPMASK_XM8_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM7_MASK (0x00000080u) #define CSL_INTC_EXPMASK_XM7_SHIFT (0x00000007u) #define CSL_INTC_EXPMASK_XM7_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM6_MASK (0x00000040u) #define CSL_INTC_EXPMASK_XM6_SHIFT (0x00000006u) #define CSL_INTC_EXPMASK_XM6_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM5_MASK (0x00000020u) #define CSL_INTC_EXPMASK_XM5_SHIFT (0x00000005u) #define CSL_INTC_EXPMASK_XM5_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM4_MASK (0x00000010u) #define CSL_INTC_EXPMASK_XM4_SHIFT (0x00000004u) #define CSL_INTC_EXPMASK_XM4_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM3_MASK (0x00000008u) #define CSL_INTC_EXPMASK_XM3_SHIFT (0x00000003u) #define CSL_INTC_EXPMASK_XM3_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM2_MASK (0x00000004u) #define CSL_INTC_EXPMASK_XM2_SHIFT (0x00000002u) #define CSL_INTC_EXPMASK_XM2_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM1_MASK (0x00000002u) #define CSL_INTC_EXPMASK_XM1_SHIFT (0x00000001u) #define CSL_INTC_EXPMASK_XM1_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_XM0_MASK (0x00000001u) #define CSL_INTC_EXPMASK_XM0_SHIFT (0x00000000u) #define CSL_INTC_EXPMASK_XM0_RESETVAL (0x00000001u) #define CSL_INTC_EXPMASK_RESETVAL (0xFFFFFFFFu) /* MEXPFLAG */ #define CSL_INTC_MEXPFLAG_MEXP31_MASK (0x80000000u) #define CSL_INTC_MEXPFLAG_MEXP31_SHIFT (0x0000001Fu) #define CSL_INTC_MEXPFLAG_MEXP31_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP30_MASK (0x40000000u) #define CSL_INTC_MEXPFLAG_MEXP30_SHIFT (0x0000001Eu) #define CSL_INTC_MEXPFLAG_MEXP30_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP29_MASK (0x20000000u) #define CSL_INTC_MEXPFLAG_MEXP29_SHIFT (0x0000001Du) #define CSL_INTC_MEXPFLAG_MEXP29_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP28_MASK (0x10000000u) #define CSL_INTC_MEXPFLAG_MEXP28_SHIFT (0x0000001Cu) #define CSL_INTC_MEXPFLAG_MEXP28_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP27_MASK (0x08000000u) #define CSL_INTC_MEXPFLAG_MEXP27_SHIFT (0x0000001Bu) #define CSL_INTC_MEXPFLAG_MEXP27_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP26_MASK (0x04000000u) #define CSL_INTC_MEXPFLAG_MEXP26_SHIFT (0x0000001Au) #define CSL_INTC_MEXPFLAG_MEXP26_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP25_MASK (0x02000000u) #define CSL_INTC_MEXPFLAG_MEXP25_SHIFT (0x00000019u) #define CSL_INTC_MEXPFLAG_MEXP25_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP24_MASK (0x01000000u) #define CSL_INTC_MEXPFLAG_MEXP24_SHIFT (0x00000018u) #define CSL_INTC_MEXPFLAG_MEXP24_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP23_MASK (0x00800000u) #define CSL_INTC_MEXPFLAG_MEXP23_SHIFT (0x00000017u) #define CSL_INTC_MEXPFLAG_MEXP23_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP22_MASK (0x00400000u) #define CSL_INTC_MEXPFLAG_MEXP22_SHIFT (0x00000016u) #define CSL_INTC_MEXPFLAG_MEXP22_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP21_MASK (0x00200000u) #define CSL_INTC_MEXPFLAG_MEXP21_SHIFT (0x00000015u) #define CSL_INTC_MEXPFLAG_MEXP21_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP20_MASK (0x00100000u) #define CSL_INTC_MEXPFLAG_MEXP20_SHIFT (0x00000014u) #define CSL_INTC_MEXPFLAG_MEXP20_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP19_MASK (0x00080000u) #define CSL_INTC_MEXPFLAG_MEXP19_SHIFT (0x00000013u) #define CSL_INTC_MEXPFLAG_MEXP19_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP18_MASK (0x00040000u) #define CSL_INTC_MEXPFLAG_MEXP18_SHIFT (0x00000012u) #define CSL_INTC_MEXPFLAG_MEXP18_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP17_MASK (0x00020000u) #define CSL_INTC_MEXPFLAG_MEXP17_SHIFT (0x00000011u) #define CSL_INTC_MEXPFLAG_MEXP17_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP16_MASK (0x00010000u) #define CSL_INTC_MEXPFLAG_MEXP16_SHIFT (0x00000010u) #define CSL_INTC_MEXPFLAG_MEXP16_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP15_MASK (0x00008000u) #define CSL_INTC_MEXPFLAG_MEXP15_SHIFT (0x0000000Fu) #define CSL_INTC_MEXPFLAG_MEXP15_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP14_MASK (0x00004000u) #define CSL_INTC_MEXPFLAG_MEXP14_SHIFT (0x0000000Eu) #define CSL_INTC_MEXPFLAG_MEXP14_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP13_MASK (0x00002000u) #define CSL_INTC_MEXPFLAG_MEXP13_SHIFT (0x0000000Du) #define CSL_INTC_MEXPFLAG_MEXP13_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP12_MASK (0x00001000u) #define CSL_INTC_MEXPFLAG_MEXP12_SHIFT (0x0000000Cu) #define CSL_INTC_MEXPFLAG_MEXP12_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP11_MASK (0x00000800u) #define CSL_INTC_MEXPFLAG_MEXP11_SHIFT (0x0000000Bu) #define CSL_INTC_MEXPFLAG_MEXP11_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP10_MASK (0x00000400u) #define CSL_INTC_MEXPFLAG_MEXP10_SHIFT (0x0000000Au) #define CSL_INTC_MEXPFLAG_MEXP10_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP9_MASK (0x00000200u) #define CSL_INTC_MEXPFLAG_MEXP9_SHIFT (0x00000009u) #define CSL_INTC_MEXPFLAG_MEXP9_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP8_MASK (0x00000100u) #define CSL_INTC_MEXPFLAG_MEXP8_SHIFT (0x00000008u) #define CSL_INTC_MEXPFLAG_MEXP8_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP7_MASK (0x00000080u) #define CSL_INTC_MEXPFLAG_MEXP7_SHIFT (0x00000007u) #define CSL_INTC_MEXPFLAG_MEXP7_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP6_MASK (0x00000040u) #define CSL_INTC_MEXPFLAG_MEXP6_SHIFT (0x00000006u) #define CSL_INTC_MEXPFLAG_MEXP6_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP5_MASK (0x00000020u) #define CSL_INTC_MEXPFLAG_MEXP5_SHIFT (0x00000005u) #define CSL_INTC_MEXPFLAG_MEXP5_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP4_MASK (0x00000010u) #define CSL_INTC_MEXPFLAG_MEXP4_SHIFT (0x00000004u) #define CSL_INTC_MEXPFLAG_MEXP4_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP3_MASK (0x00000008u) #define CSL_INTC_MEXPFLAG_MEXP3_SHIFT (0x00000003u) #define CSL_INTC_MEXPFLAG_MEXP3_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP2_MASK (0x00000004u) #define CSL_INTC_MEXPFLAG_MEXP2_SHIFT (0x00000002u) #define CSL_INTC_MEXPFLAG_MEXP2_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP1_MASK (0x00000002u) #define CSL_INTC_MEXPFLAG_MEXP1_SHIFT (0x00000001u) #define CSL_INTC_MEXPFLAG_MEXP1_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP0_MASK (0x00000001u) #define CSL_INTC_MEXPFLAG_MEXP0_SHIFT (0x00000000u) #define CSL_INTC_MEXPFLAG_MEXP0_RESETVAL (0x00000000u) #define CSL_INTC_MEXPFLAG_RESETVAL (0x00000000u) /* INTMUX1 */ #define CSL_INTC_INTMUX1_INTSEL7_MASK (0x7F000000u) #define CSL_INTC_INTMUX1_INTSEL7_SHIFT (0x00000018u) #define CSL_INTC_INTMUX1_INTSEL7_RESETVAL (0x00000007u) #define CSL_INTC_INTMUX1_INTSEL6_MASK (0x007F0000u) #define CSL_INTC_INTMUX1_INTSEL6_SHIFT (0x00000010u) #define CSL_INTC_INTMUX1_INTSEL6_RESETVAL (0x00000006u) #define CSL_INTC_INTMUX1_INTSEL5_MASK (0x00007F00u) #define CSL_INTC_INTMUX1_INTSEL5_SHIFT (0x00000008u) #define CSL_INTC_INTMUX1_INTSEL5_RESETVAL (0x00000005u) #define CSL_INTC_INTMUX1_INTSEL4_MASK (0x0000007Fu) #define CSL_INTC_INTMUX1_INTSEL4_SHIFT (0x00000000u) #define CSL_INTC_INTMUX1_INTSEL4_RESETVAL (0x00000004u) #define CSL_INTC_INTMUX1_RESETVAL (0x07060504u) /* INTMUX2 */ #define CSL_INTC_INTMUX2_INTSEL11_MASK (0x7F000000u) #define CSL_INTC_INTMUX2_INTSEL11_SHIFT (0x00000018u) #define CSL_INTC_INTMUX2_INTSEL11_RESETVAL (0x0000000Bu) #define CSL_INTC_INTMUX2_INTSEL10_MASK (0x007F0000u) #define CSL_INTC_INTMUX2_INTSEL10_SHIFT (0x00000010u) #define CSL_INTC_INTMUX2_INTSEL10_RESETVAL (0x0000000Au) #define CSL_INTC_INTMUX2_INTSEL9_MASK (0x00007F00u) #define CSL_INTC_INTMUX2_INTSEL9_SHIFT (0x00000008u) #define CSL_INTC_INTMUX2_INTSEL9_RESETVAL (0x00000009u) #define CSL_INTC_INTMUX2_INTSEL8_MASK (0x0000007Fu) #define CSL_INTC_INTMUX2_INTSEL8_SHIFT (0x00000000u) #define CSL_INTC_INTMUX2_INTSEL8_RESETVAL (0x00000008u) #define CSL_INTC_INTMUX2_RESETVAL (0x0B0A0908u) /* INTMUX3 */ #define CSL_INTC_INTMUX3_INTSEL15_MASK (0x7F000000u) #define CSL_INTC_INTMUX3_INTSEL15_SHIFT (0x00000018u) #define CSL_INTC_INTMUX3_INTSEL15_RESETVAL (0x0000000Fu) #define CSL_INTC_INTMUX3_INTSEL14_MASK (0x007F0000u) #define CSL_INTC_INTMUX3_INTSEL14_SHIFT (0x00000010u) #define CSL_INTC_INTMUX3_INTSEL14_RESETVAL (0x0000000Eu) #define CSL_INTC_INTMUX3_INTSEL13_MASK (0x00007F00u) #define CSL_INTC_INTMUX3_INTSEL13_SHIFT (0x00000008u) #define CSL_INTC_INTMUX3_INTSEL13_RESETVAL (0x0000000Du) #define CSL_INTC_INTMUX3_INTSEL12_MASK (0x0000007Fu) #define CSL_INTC_INTMUX3_INTSEL12_SHIFT (0x00000000u) #define CSL_INTC_INTMUX3_INTSEL12_RESETVAL (0x0000000Cu) #define CSL_INTC_INTMUX3_RESETVAL (0x0F0E0D0Cu) /* INTXSTAT */ #define CSL_INTC_INTXSTAT_SYSINT_MASK (0xFF000000u) #define CSL_INTC_INTXSTAT_SYSINT_SHIFT (0x00000018u) #define CSL_INTC_INTXSTAT_SYSINT_RESETVAL (0x00000000u) /*----SYSINT Tokens----*/ #define CSL_INTC_INTXSTAT_SYSINT_NUM0 (0x00000000u) #define CSL_INTC_INTXSTAT_SYSINT_NUM1 (0x00000001u) #define CSL_INTC_INTXSTAT_SYSINT_NUM2 (0x00000002u) #define CSL_INTC_INTXSTAT_SYSINT_NUM3 (0x00000003u) #define CSL_INTC_INTXSTAT_SYSINT_NUM4 (0x00000004u) #define CSL_INTC_INTXSTAT_SYSINT_NUM5 (0x00000005u) #define CSL_INTC_INTXSTAT_SYSINT_NUM6 (0x00000006u) #define CSL_INTC_INTXSTAT_SYSINT_NUM7 (0x00000007u) #define CSL_INTC_INTXSTAT_SYSINT_NUM8 (0x00000008u) #define CSL_INTC_INTXSTAT_SYSINT_NUM9 (0x00000009u) #define CSL_INTC_INTXSTAT_SYSINT_NUM10 (0x0000000Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM11 (0x0000000Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM12 (0x0000000Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM13 (0x0000000Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM14 (0x0000000Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM15 (0x0000000Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM16 (0x00000010u) #define CSL_INTC_INTXSTAT_SYSINT_NUM17 (0x00000011u) #define CSL_INTC_INTXSTAT_SYSINT_NUM18 (0x00000012u) #define CSL_INTC_INTXSTAT_SYSINT_NUM19 (0x00000013u) #define CSL_INTC_INTXSTAT_SYSINT_NUM20 (0x00000014u) #define CSL_INTC_INTXSTAT_SYSINT_NUM21 (0x00000015u) #define CSL_INTC_INTXSTAT_SYSINT_NUM22 (0x00000016u) #define CSL_INTC_INTXSTAT_SYSINT_NUM23 (0x00000017u) #define CSL_INTC_INTXSTAT_SYSINT_NUM24 (0x00000018u) #define CSL_INTC_INTXSTAT_SYSINT_NUM25 (0x00000019u) #define CSL_INTC_INTXSTAT_SYSINT_NUM26 (0x0000001Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM27 (0x0000001Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM28 (0x0000001Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM29 (0x0000001Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM30 (0x0000001Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM31 (0x0000001Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM32 (0x00000020u) #define CSL_INTC_INTXSTAT_SYSINT_NUM33 (0x00000021u) #define CSL_INTC_INTXSTAT_SYSINT_NUM34 (0x00000022u) #define CSL_INTC_INTXSTAT_SYSINT_NUM35 (0x00000023u) #define CSL_INTC_INTXSTAT_SYSINT_NUM36 (0x00000024u) #define CSL_INTC_INTXSTAT_SYSINT_NUM37 (0x00000025u) #define CSL_INTC_INTXSTAT_SYSINT_NUM38 (0x00000026u) #define CSL_INTC_INTXSTAT_SYSINT_NUM39 (0x00000027u) #define CSL_INTC_INTXSTAT_SYSINT_NUM40 (0x00000028u) #define CSL_INTC_INTXSTAT_SYSINT_NUM41 (0x00000029u) #define CSL_INTC_INTXSTAT_SYSINT_NUM42 (0x0000002Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM43 (0x0000002Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM44 (0x0000002Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM45 (0x0000002Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM46 (0x0000002Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM47 (0x0000002Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM48 (0x00000030u) #define CSL_INTC_INTXSTAT_SYSINT_NUM49 (0x00000031u) #define CSL_INTC_INTXSTAT_SYSINT_NUM50 (0x00000032u) #define CSL_INTC_INTXSTAT_SYSINT_NUM51 (0x00000033u) #define CSL_INTC_INTXSTAT_SYSINT_NUM52 (0x00000034u) #define CSL_INTC_INTXSTAT_SYSINT_NUM53 (0x00000035u) #define CSL_INTC_INTXSTAT_SYSINT_NUM54 (0x00000036u) #define CSL_INTC_INTXSTAT_SYSINT_NUM55 (0x00000037u) #define CSL_INTC_INTXSTAT_SYSINT_NUM56 (0x00000038u) #define CSL_INTC_INTXSTAT_SYSINT_NUM57 (0x00000039u) #define CSL_INTC_INTXSTAT_SYSINT_NUM58 (0x0000003Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM59 (0x0000003Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM60 (0x0000003Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM61 (0x0000003Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM62 (0x0000003Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM63 (0x0000003Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM64 (0x00000040u) #define CSL_INTC_INTXSTAT_SYSINT_NUM65 (0x00000041u) #define CSL_INTC_INTXSTAT_SYSINT_NUM66 (0x00000042u) #define CSL_INTC_INTXSTAT_SYSINT_NUM67 (0x00000043u) #define CSL_INTC_INTXSTAT_SYSINT_NUM68 (0x00000044u) #define CSL_INTC_INTXSTAT_SYSINT_NUM69 (0x00000045u) #define CSL_INTC_INTXSTAT_SYSINT_NUM70 (0x00000046u) #define CSL_INTC_INTXSTAT_SYSINT_NUM71 (0x00000047u) #define CSL_INTC_INTXSTAT_SYSINT_NUM72 (0x00000048u) #define CSL_INTC_INTXSTAT_SYSINT_NUM73 (0x00000049u) #define CSL_INTC_INTXSTAT_SYSINT_NUM74 (0x0000004Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM75 (0x0000004Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM76 (0x0000004Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM77 (0x0000004Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM78 (0x0000004Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM79 (0x0000004Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM80 (0x00000050u) #define CSL_INTC_INTXSTAT_SYSINT_NUM81 (0x00000051u) #define CSL_INTC_INTXSTAT_SYSINT_NUM82 (0x00000052u) #define CSL_INTC_INTXSTAT_SYSINT_NUM83 (0x00000053u) #define CSL_INTC_INTXSTAT_SYSINT_NUM84 (0x00000054u) #define CSL_INTC_INTXSTAT_SYSINT_NUM85 (0x00000055u) #define CSL_INTC_INTXSTAT_SYSINT_NUM86 (0x00000056u) #define CSL_INTC_INTXSTAT_SYSINT_NUM87 (0x00000057u) #define CSL_INTC_INTXSTAT_SYSINT_NUM88 (0x00000058u) #define CSL_INTC_INTXSTAT_SYSINT_NUM89 (0x00000059u) #define CSL_INTC_INTXSTAT_SYSINT_NUM90 (0x0000005Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM91 (0x0000005Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM92 (0x0000005Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM93 (0x0000005Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM94 (0x0000005Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM95 (0x0000005Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM96 (0x00000060u) #define CSL_INTC_INTXSTAT_SYSINT_NUM97 (0x00000061u) #define CSL_INTC_INTXSTAT_SYSINT_NUM98 (0x00000062u) #define CSL_INTC_INTXSTAT_SYSINT_NUM99 (0x00000063u) #define CSL_INTC_INTXSTAT_SYSINT_NUM100 (0x00000064u) #define CSL_INTC_INTXSTAT_SYSINT_NUM101 (0x00000065u) #define CSL_INTC_INTXSTAT_SYSINT_NUM102 (0x00000066u) #define CSL_INTC_INTXSTAT_SYSINT_NUM103 (0x00000067u) #define CSL_INTC_INTXSTAT_SYSINT_NUM104 (0x00000068u) #define CSL_INTC_INTXSTAT_SYSINT_NUM105 (0x00000069u) #define CSL_INTC_INTXSTAT_SYSINT_NUM106 (0x0000006Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM107 (0x0000006Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM108 (0x0000006Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM109 (0x0000006Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM110 (0x0000006Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM111 (0x0000006Fu) #define CSL_INTC_INTXSTAT_SYSINT_NUM112 (0x00000070u) #define CSL_INTC_INTXSTAT_SYSINT_NUM113 (0x00000071u) #define CSL_INTC_INTXSTAT_SYSINT_NUM114 (0x00000072u) #define CSL_INTC_INTXSTAT_SYSINT_NUM115 (0x00000073u) #define CSL_INTC_INTXSTAT_SYSINT_NUM116 (0x00000074u) #define CSL_INTC_INTXSTAT_SYSINT_NUM117 (0x00000075u) #define CSL_INTC_INTXSTAT_SYSINT_NUM118 (0x00000076u) #define CSL_INTC_INTXSTAT_SYSINT_NUM119 (0x00000077u) #define CSL_INTC_INTXSTAT_SYSINT_NUM120 (0x00000078u) #define CSL_INTC_INTXSTAT_SYSINT_NUM121 (0x00000079u) #define CSL_INTC_INTXSTAT_SYSINT_NUM122 (0x0000007Au) #define CSL_INTC_INTXSTAT_SYSINT_NUM123 (0x0000007Bu) #define CSL_INTC_INTXSTAT_SYSINT_NUM124 (0x0000007Cu) #define CSL_INTC_INTXSTAT_SYSINT_NUM125 (0x0000007Du) #define CSL_INTC_INTXSTAT_SYSINT_NUM126 (0x0000007Eu) #define CSL_INTC_INTXSTAT_SYSINT_NUM127 (0x0000007Fu) #define CSL_INTC_INTXSTAT_CPUINT_MASK (0x00FF0000u) #define CSL_INTC_INTXSTAT_CPUINT_SHIFT (0x00000010u) #define CSL_INTC_INTXSTAT_CPUINT_RESETVAL (0x00000000u) /*----CPUINT Tokens----*/ #define CSL_INTC_INTXSTAT_CPUINT_NUM0 (0x00000000u) #define CSL_INTC_INTXSTAT_CPUINT_NUM1 (0x00000001u) #define CSL_INTC_INTXSTAT_CPUINT_NUM2 (0x00000002u) #define CSL_INTC_INTXSTAT_CPUINT_NUM3 (0x00000003u) #define CSL_INTC_INTXSTAT_CPUINT_NUM4 (0x00000004u) #define CSL_INTC_INTXSTAT_CPUINT_NUM5 (0x00000005u) #define CSL_INTC_INTXSTAT_CPUINT_NUM6 (0x00000006u) #define CSL_INTC_INTXSTAT_CPUINT_NUM7 (0x00000007u) #define CSL_INTC_INTXSTAT_CPUINT_NUM8 (0x00000008u) #define CSL_INTC_INTXSTAT_CPUINT_NUM9 (0x00000009u) #define CSL_INTC_INTXSTAT_CPUINT_NUM10 (0x0000000Au) #define CSL_INTC_INTXSTAT_CPUINT_NUM11 (0x0000000Bu) #define CSL_INTC_INTXSTAT_CPUINT_NUM12 (0x0000000Cu) #define CSL_INTC_INTXSTAT_CPUINT_NUM13 (0x0000000Du) #define CSL_INTC_INTXSTAT_CPUINT_NUM14 (0x0000000Eu) #define CSL_INTC_INTXSTAT_CPUINT_NUM15 (0x0000000Fu) #define CSL_INTC_INTXSTAT_RESERVED_MASK (0x0000FFFEu) #define CSL_INTC_INTXSTAT_RESERVED_SHIFT (0x00000001u) #define CSL_INTC_INTXSTAT_RESERVED_RESETVAL (0x00000000u) #define CSL_INTC_INTXSTAT_DROP_MASK (0x00000001u) #define CSL_INTC_INTXSTAT_DROP_SHIFT (0x00000000u) #define CSL_INTC_INTXSTAT_DROP_RESETVAL (0x00000000u) /*----DROP Tokens----*/ #define CSL_INTC_INTXSTAT_DROP_NO (0x00000000u) #define CSL_INTC_INTXSTAT_DROP_YES (0x00000001u) #define CSL_INTC_INTXSTAT_RESETVAL (0x00000000u) /* INTXCLR */ #define CSL_INTC_INTXCLR_RESERVED_MASK (0xFFFFFFFEu) #define CSL_INTC_INTXCLR_RESERVED_SHIFT (0x00000001u) #define CSL_INTC_INTXCLR_RESERVED_RESETVAL (0x00000000u) #define CSL_INTC_INTXCLR_CLR_MASK (0x00000001u) #define CSL_INTC_INTXCLR_CLR_SHIFT (0x00000000u) #define CSL_INTC_INTXCLR_CLR_RESETVAL (0x00000000u) #define CSL_INTC_INTXCLR_RESETVAL (0x00000000u) /* INTDMASK */ #define CSL_INTC_INTDMASK_IDM15_MASK (0x00008000u) #define CSL_INTC_INTDMASK_IDM15_SHIFT (0x0000000Fu) #define CSL_INTC_INTDMASK_IDM15_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM14_MASK (0x00004000u) #define CSL_INTC_INTDMASK_IDM14_SHIFT (0x0000000Eu) #define CSL_INTC_INTDMASK_IDM14_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM13_MASK (0x00002000u) #define CSL_INTC_INTDMASK_IDM13_SHIFT (0x0000000Du) #define CSL_INTC_INTDMASK_IDM13_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM12_MASK (0x00001000u) #define CSL_INTC_INTDMASK_IDM12_SHIFT (0x0000000Cu) #define CSL_INTC_INTDMASK_IDM12_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM11_MASK (0x00000800u) #define CSL_INTC_INTDMASK_IDM11_SHIFT (0x0000000Bu) #define CSL_INTC_INTDMASK_IDM11_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM10_MASK (0x00000400u) #define CSL_INTC_INTDMASK_IDM10_SHIFT (0x0000000Au) #define CSL_INTC_INTDMASK_IDM10_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM9_MASK (0x00000200u) #define CSL_INTC_INTDMASK_IDM9_SHIFT (0x00000009u) #define CSL_INTC_INTDMASK_IDM9_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM8_MASK (0x00000100u) #define CSL_INTC_INTDMASK_IDM8_SHIFT (0x00000008u) #define CSL_INTC_INTDMASK_IDM8_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM7_MASK (0x00000080u) #define CSL_INTC_INTDMASK_IDM7_SHIFT (0x00000007u) #define CSL_INTC_INTDMASK_IDM7_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM6_MASK (0x00000040u) #define CSL_INTC_INTDMASK_IDM6_SHIFT (0x00000006u) #define CSL_INTC_INTDMASK_IDM6_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM5_MASK (0x00000020u) #define CSL_INTC_INTDMASK_IDM5_SHIFT (0x00000005u) #define CSL_INTC_INTDMASK_IDM5_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_IDM4_MASK (0x00000010u) #define CSL_INTC_INTDMASK_IDM4_SHIFT (0x00000004u) #define CSL_INTC_INTDMASK_IDM4_RESETVAL (0x00000000u) #define CSL_INTC_INTDMASK_RESETVAL (0x00000000u) #endif

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/FB_W2100_SCU_MEA256/Device_lib.c

// use sprc234 (Version: 03.00.10.02) for the CSL include files #include <stdio.h> #include <string.h> #include <cslr_pllc.h> #include <cslr_gpio.h> #include <cslr_emifa.h> #include <cslr_ddr2.h> #include <cslr_dev.h> #include <cslr_intc.h> #include <cslr_chip.h> #include <cslr_edma3cc.h> #include <cslr_cache.h> #include <cslr_tmr.h> #include <soc.h> #include <c6x.h> #include "Device_config.h" #include "Device_lib.h" typedef volatile CSL_DevRegs *CSL_DevRegsOvly; extern void intcVectorTable(void); void init_cache(); void init_gpio(); void init_pll1(); void init_pll2(); void init_emifa(); void init_ddr2(); void init_irq(); void init_timer(); void init_dma(int indata_channels); void init_qdma(int indata_channels); Uint32 MeaData[MAX_DATAPOINTS_PER_FRAME]; #pragma DATA_ALIGN(MeaData, 8); Uint32 MonitorData[MONITOR_ARRAY]; Uint32 ChannelsPerSweepConfigured; /* Globals */ CSL_DevRegsOvly devRegs = (CSL_DevRegsOvly)CSL_DEV_REGS; void MEA21_init() { init_gpio(); init_pll1(); init_ddr2(); init_emifa(); init_cache(); WRITE_REGISTER(DSP_INDATA_CTRL0, DSPINDATACTRL0_CLEAR_FIFO | DSPINDATACTRL0_RESET_FIFO); // Disable all Data Channels and Clear Fifo WRITE_REGISTER(MAILBOX_CTRL, 0x100); // enable DSP Mailbox interrupts init_irq(); } void MEA21_enableData() { int i; WRITE_REGISTER(DSP_INDATA_CONFIG0, INDATA_CONFIG0_VALUE); // Enable Data Sources WRITE_REGISTER(DSP_INDATA_CONFIG1, INDATA_CONFIG1_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG2, INDATA_CONFIG2_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG3, INDATA_CONFIG3_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG4, INDATA_CONFIG4_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG5, INDATA_CONFIG5_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG6, INDATA_CONFIG6_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG7, INDATA_CONFIG7_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG8, INDATA_CONFIG8_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIG9, INDATA_CONFIG9_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGa, INDATA_CONFIGa_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGb, INDATA_CONFIGb_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGc, INDATA_CONFIGc_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGd, INDATA_CONFIGd_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGe, INDATA_CONFIGe_VALUE); WRITE_REGISTER(DSP_INDATA_CONFIGf, INDATA_CONFIGf_VALUE); for (i = 0; i < 5000; i++) { ChannelsPerSweepConfigured = READ_REGISTER(DSP_INDATA_CHANNELS); // should be the same number as CHANNELS_PER_FRAME if (ChannelsPerSweepConfigured) break; // a non-zero value indicated the FPGA has finished configuration } if (ChannelsPerSweepConfigured > MAX_DATAPOINTS_PER_FRAME) { // You should increase MAX_DATAPOINTS_PER_FRAME if this condition is true ChannelsPerSweepConfigured = MAX_DATAPOINTS_PER_FRAME; } init_timer(); init_dma(ChannelsPerSweepConfigured); init_qdma(ChannelsPerSweepConfigured); WRITE_REGISTER(DSP_INDATA_CTRL0, DSPINDATACTRL0_INT_ENABLE | DSPINDATACTRL0_CLEAR_FIFO | DSPINDATACTRL0_RESET_FIFO); // Enable Irq SetMonitorSize(MONITOR_ARRAY); } void init_timer() { Bool timerRdy; // enable timer 0 // Unlock the control register CSL_FINST(((CSL_DevRegs *)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); CSL_FINST(((CSL_DevRegs *)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER0CTL, ENABLE); do { timerRdy = (Bool) CSL_FEXT(((CSL_DevRegs *)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TIMER0STAT); } while (!timerRdy); // enable timer 1 // Unlock the control register CSL_FINST(((CSL_DevRegs *)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); CSL_FINST(((CSL_DevRegs *)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER1CTL, ENABLE); do { timerRdy = (Bool) CSL_FEXT(((CSL_DevRegs *)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_TIMER1STAT); } while (!timerRdy); CSL_TmrRegsOvly tmr1Regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; // clear TIM12 register CSL_FINST(tmr1Regs->TIMLO,TMR_TIMLO_TIMLO,RESETVAL); CSL_FINS(tmr1Regs->TCR, TMR_TCR_CLKSRC_LO, 0); // select 32 bit unchained mode and take the timer out of reset CSL_FINS(tmr1Regs->TGCR, TMR_TGCR_TIMMODE, 1); // 32bit unchained CSL_FINST(tmr1Regs->TGCR, TMR_TGCR_TIMLORS, RESET_OFF); } void init_gpio() { CSL_GpioRegsOvly gpioRegs = (CSL_GpioRegsOvly)CSL_GPIO_0_REGS; Bool gpioEn; /* Unlock the control register */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK); /* Enable the GPIO */ CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_GPIOCTL, ENABLE); do { gpioEn = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_GPIOSTAT); } while (gpioEn != CSL_DEV_PERSTAT0_GPIOSTAT_ENABLE); CSL_FINS(gpioRegs->DIR, GPIO_DIR_DIR2 , CSL_GPIO_DIR_DIR_OUT); // LED CSL_FINS(gpioRegs->DIR, GPIO_DIR_DIR15, CSL_GPIO_DIR_DIR_OUT); // LED CSL_FINS(gpioRegs->OUT_DATA, GPIO_OUT_DATA_OUT2, 1); // LED CSL_FINS(gpioRegs->OUT_DATA, GPIO_OUT_DATA_OUT15, 0); // LED CSL_FINS(gpioRegs->DIR, GPIO_DIR_DIR4 , CSL_GPIO_DIR_DIR_IN); // FPGA Data available CSL_FINS(gpioRegs->DIR, GPIO_DIR_DIR6 , CSL_GPIO_DIR_DIR_IN); // Mailbox IRQ /* Enable Interrupts for GP[4] */ CSL_FINS(gpioRegs->SET_RIS_TRIG, GPIO_SET_RIS_TRIG_SETRIS4, CSL_GPIO_SET_RIS_TRIG_SETRIS_ENABLE); /* Enable Interrupts for GP[6] */ CSL_FINS(gpioRegs->SET_RIS_TRIG, GPIO_SET_RIS_TRIG_SETRIS6, CSL_GPIO_SET_RIS_TRIG_SETRIS_ENABLE); CSL_FINST(gpioRegs->BINTEN, GPIO_BINTEN_EN, ENABLE); } void init_cache() { ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PCFG = CSL_CACHE_L1PCFG_MODE_32K; ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DCFG = CSL_CACHE_L1DCFG_MODE_32K; } void init_pll1() { // input Clock is 51.2 MHz // max device clock is 850 MHz volatile int i; CSL_PllcRegsOvly pllRegs = (CSL_PllcRegsOvly)CSL_PLLC_1_REGS; CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLENSRC, REGBIT); CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLEN, BYPASS); // wait 4 cycles for (i = 0; i < 4; i++); CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLRST, YES); CSL_FINS(pllRegs->PREDIV, PLLC_PREDIV_RATIO, 0); // Prediv by 1 CSL_FINS(pllRegs->PLLM, PLLC_PLLM_PLLM, 15); // Multiply by 16 -> 51.2 * 16 = 819.2 MHz CSL_FINS(pllRegs->PLLDIV4, PLLC_PLLDIV4_RATIO, 7); // 7: divide by 16 -> 51.2 MHz (Max: 166 MHz) CSL_FINS(pllRegs->PLLDIV5, PLLC_PLLDIV5_RATIO, 2); // 2: divide by 3 -> 273.06 MHz (Max: 333 MHz) // CSL_FINST(pllRegs->ALNCTL, PLLC_ALNCTL_ALN4, YES); // Align SYSCLK4, default, do not change // CSL_FINST(pllRegs->ALNCTL, PLLC_ALNCTL_ALN5, YES); // Align SYSCLK5, default, do not change CSL_FINST(pllRegs->PLLCMD, PLLC_PLLCMD_GOSET, SET); // while (CSL_FEXT(pllRegs->PLLSTAT, PLLC_PLLSTAT_GOSTAT) == CSL_PLLC_PLLSTAT_GOSTAT_INPROG); // wait for PLL reset (128 * CLKIN1 cycle time) -> 2.5 us for (i = 0; i < 2000; i++); CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLRST, NO); // wait for PLL lock time (2000 * CLKIN1 cycle time) -> 96.9 us for (i = 0; i < 20000; i++); CSL_FINST(pllRegs->PLLCTL, PLLC_PLLCTL_PLLEN, PLL); } void init_pll2() { // input Clock is 25.6 MHz // PLLOUT is 250 .. 533 MHz // DDR2 clock is fixed to PLLOUT/2 // PLLM is fixed to x20 -> 25.6 MHz -> 512 MHz PLLOUT -> 256 MHz DDR2 Clock // SYSLK1 is 50 or 125 MHz when EMAC is used } // we want ARDY pin is active-low (strobe period extended when ARDY is low) // Requirement for the Xilinx async Interface: // T_SETUP: >= 3x 38.4 MHz cycles (> 78.125 ns) (2 cycles should be ok?) // T_STROBE: > 2x 38.4 MHz cycles (> 52.083 ns) (+ ARDY; ARDY must be asserted and deasserted for 2 cycles) // T_HOLD: >= 1x 38.4 MHz cycle (> 26.042 ns) // Clock for EMIFA is AECLKIN, which is 38.4 MHz void init_emifa() { CSL_EmifaRegsOvly emifaRegs = (CSL_EmifaRegsOvly)CSL_EMIFA_0_REGS; CSL_FINST(devRegs->PERCFG1, DEV_PERCFG1_EMIFACTL, ENABLE); CSL_FINS(emifaRegs->BPRIO, EMIFA_BPRIO_PRIO_RAISE, 0xfe); // see SPRZ234N Silicon Errata CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_SSEL, ASYNCMEM); // CE2 (0xa0000000) uses ASYNC interface CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_SS, SSMDIS); // Disable Select Strobe Mode CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_BWEM, WESDIS); // Disable WE Strobe Mode CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_AE, ARDYEN); // enable ARDY Pin CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_SETUP, 2); // 3 cycles @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_STROBE, 1); // 2 cycles @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_HOLD, 0); // 1 cycle @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_SETUP, 2); // 3 cycles @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_STROBE, 1); // 2 cycles @38.4 MHz CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_HOLD, 0); // 1 cycle @38.4 MHz CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_ASIZE, 32BIT); // enable ARDY Pin CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_SSEL, SYNCMEM); // CE3 (0xb0000000) uses SYNC interface CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_RD_BE_EN, SET); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_CE_EXT, CLR); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_R_ENABLE, SET); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_W_LTNCY, ONECYCLE); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_R_LTNCY, THREECYCLE); CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_SBSIZE, 32BIT); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_SSEL, SYNCMEM); // CE4 (0xc0000000) uses SYNC interface to stream Stimulus data CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_RD_BE_EN, SET); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_CE_EXT, CLR); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_R_ENABLE, SET); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_W_LTNCY, ONECYCLE); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_R_LTNCY, THREECYCLE); CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_SBSIZE, 32BIT); CSL_FINS(emifaRegs->AWCC, EMIFA_AWCC_AP, 0); // define polarity of ARDY pin: active low CSL_FINS(emifaRegs->AWCC, EMIFA_AWCC_TA, 7); // Turn Around cycles CSL_FINS(emifaRegs->AWCC, EMIFA_AWCC_MAX_EXT_WAIT, 0xff); // Maximum Extended Wait cycles; 106.25 us @ AECLK of 38.4 MHz } void init_ddr2() { CSL_Ddr2RegsOvly ddr2Regs = (CSL_Ddr2RegsOvly)CSL_DDR2_0_REGS; CSL_FINST(devRegs->PERCFG1, DEV_PERCFG1_DDR2CTL, ENABLE); CSL_FINS(ddr2Regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, 3200); // 256 MHz * 200 us / 16 = 3200 CSL_FINST(ddr2Regs->DMCCTL, DDR2_DMCCTL_IFRESET, RELEASE); CSL_FINS(ddr2Regs->BPRIO, DDR2_BPRIO_PRIO_RAISE, 0xfe); // see SPRZ234N Silicon Errata CSL_FINS(ddr2Regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, 3200); // 256 MHz * 200 us / 16 = 3200 CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_BOOT_UNLOCK, UNLOCKED); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_DDR_DRIVE, NORMAL); // default is NORMAL CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_BOOT_UNLOCK, LOCKED); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_TIMUNLOCK, SET); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_NM, 16BIT); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_CL, FIVE); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_IBANK, EIGHT); CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_PAGESIZE, 1024W_PAGE); CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RFC, 49); // 195 ns * 256 MHz = 49.92 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RP, 3); // 12.5 ns * 256 MHz = 3.2 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RCD, 3); // 12.5 ns * 256 MHz = 3.2 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_WR, 3); // 15.0 ns * 256 MHz = 3.84 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RAS, 11); // 45.0 ns * 256 MHz = 11.52 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RC, 14); // 57.5 ns * 256 MHz = 14.72 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_RRD, 3); // 11.5 ns * 256 MHz = 3.06 CSL_FINS(ddr2Regs->SDTIM1, DDR2_SDTIM1_T_WTR, 3); // 7.5 ns * 256 MHz = 1.92 CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_ODT, 2); // 2 cycles CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_SXNR, 52); // 205 ns * 256 MHz = 52.48 CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_SXRD,199); // 200 cycles CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_RTP, 1); // 7.5 ns * 256 MHz = 1.92 CSL_FINS(ddr2Regs->SDTIM2, DDR2_SDTIM2_T_CKE, 2); // 3 cycles CSL_FINS(ddr2Regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, 1997); // 256 MHz * 7.8 us = 1996.8 CSL_FINS(ddr2Regs->DMCCTL, DDR2_DMCCTL_RL, 6); // CAS Latency + 1 CSL_FINST(ddr2Regs->SDCFG, DDR2_SDCFG_TIMUNLOCK, CLEAR); } void init_irq() { CSL_IntcRegsOvly intcRegs = (CSL_IntcRegsOvly)CSL_INTC_0_REGS; // map GP[6] event (Mailbox write) to cpu int 8 CSL_FINS(intcRegs->INTMUX2, INTC_INTMUX2_INTSEL8, CSL_INTC_EVENTID_GPINT6); // set ISTP to point to the vector table address ISTP = (unsigned int)intcVectorTable; // clear all interrupts, bits 4 thru 15 ICR = 0xFFF0; // enable the bits for non maskable interrupt and CPUINT6 and CPUINT8 */ IER |= 0x02; IER |= 0x40; // enable CPUINT6 (DMA completion) IER |= 0x100; // enable CPUINT8 (Mailbox write) // enable interrupts, set GIE bit _enable_interrupts(); } void init_dma(int indata_channels) { CSL_IntcRegsOvly intcRegs = (CSL_IntcRegsOvly)CSL_INTC_0_REGS; CSL_Edma3ccRegsOvly edma3ccRegs = (CSL_Edma3ccRegsOvly)CSL_EDMA3CC_0_REGS; volatile CSL_Edma3ccParamsetRegs *ParmsetGPINT4RLD = &edma3ccRegs->PARAMSET[CSL_EDMA3_CHA_GPINT3]; // inbound data reload set volatile CSL_Edma3ccParamsetRegs *ParmsetGPINT4 = &edma3ccRegs->PARAMSET[CSL_EDMA3_CHA_GPINT4]; // inbound data volatile CSL_Edma3ccParamsetRegs *ParmsetGPINT5 = &edma3ccRegs->PARAMSET[CSL_EDMA3_CHA_GPINT5]; // outbound data CSL_FINS(edma3ccRegs->DCHMAP[52], EDMA3CC_DCHMAP_PAENTRY, 52); // Map event 52 to parameter set 52 CSL_FINS(edma3ccRegs->DMAQNUM[6], EDMA3CC_DMAQNUM_E4, 0); // Use Q0 for event 52 CSL_FINS(edma3ccRegs->DCHMAP[53], EDMA3CC_DCHMAP_PAENTRY, 53); // Map event 53 to parameter set 53 CSL_FINS(edma3ccRegs->DMAQNUM[6], EDMA3CC_DMAQNUM_E5, 0); // Use Q0 for event 53 memset((void *)ParmsetGPINT4RLD, 0, sizeof(CSL_Edma3ccParamsetRegs)); memset((void *)ParmsetGPINT5, 0, sizeof(CSL_Edma3ccParamsetRegs)); CSL_FINST(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_TCINTEN, ENABLE); CSL_FINST(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_STATIC, NORMAL); CSL_FINS(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_TCC, 52); // Use a TCC of 52 for event 52 CSL_FINS(ParmsetGPINT4RLD->SRC, EDMA3CC_SRC_SRC, 0xb0000000); CSL_FINS(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_FWID, 2); CSL_FINST(ParmsetGPINT4RLD->OPT, EDMA3CC_OPT_SAM, CONST); CSL_FINS(ParmsetGPINT4RLD->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 4*indata_channels); CSL_FINS(ParmsetGPINT4RLD->A_B_CNT, EDMA3CC_A_B_CNT_BCNT, FRAMES_PER_LOOP); CSL_FINS(ParmsetGPINT4RLD->SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 4*indata_channels); CSL_FINS(ParmsetGPINT4RLD->DST, EDMA3CC_DST_DST, (Uint32)&MeaData); CSL_FINS(ParmsetGPINT4RLD->LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_LINK, CSL_EDMA3_CHA_GPINT3 << 5); // CSL_FINS(ParmsetGPINT4RLD->LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_BCNTRLD, FRAMES_PER_LOOP); CSL_FINS(ParmsetGPINT4RLD->CCNT, EDMA3CC_CCNT_CCNT, 1); memcpy((void *)ParmsetGPINT4, (void *)ParmsetGPINT4RLD, sizeof(CSL_Edma3ccParamsetRegs)); CSL_FINST(ParmsetGPINT5->OPT, EDMA3CC_OPT_TCINTEN, ENABLE); CSL_FINST(ParmsetGPINT5->OPT, EDMA3CC_OPT_STATIC, STATIC); CSL_FINS(ParmsetGPINT5->OPT, EDMA3CC_OPT_TCC, 53); // Use a TCC of 53 for event 53 CSL_FINS(ParmsetGPINT5->SRC, EDMA3CC_SRC_SRC, (Uint32)&MonitorData); CSL_FINS(ParmsetGPINT5->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 0); CSL_FINS(ParmsetGPINT5->A_B_CNT, EDMA3CC_A_B_CNT_BCNT, 1); CSL_FINS(ParmsetGPINT5->DST, EDMA3CC_DST_DST, 0xb0000000); CSL_FINS(ParmsetGPINT5->LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_LINK, 0xffff); CSL_FINS(ParmsetGPINT5->CCNT, EDMA3CC_CCNT_CCNT, 1); CSL_FINST(edma3ccRegs->EMCRH, EDMA3CC_EMCRH_E52, CLEAR); // clear missed events) CSL_FINST(edma3ccRegs->EMCRH, EDMA3CC_EMCRH_E53, CLEAR); // clear missed events) CSL_FINST(edma3ccRegs->SECRH, EDMA3CC_SECRH_E52, CLEAR); // clear secondary events) CSL_FINST(edma3ccRegs->SECRH, EDMA3CC_SECRH_E53, CLEAR); // clear secondary events) // CSL_FINST(edma3ccRegs->ESRH, EDMA3CC_ESRH_E52, SET); // Manual Trigger CSL_FINST(edma3ccRegs->EESRH, EDMA3CC_EESRH_E52, SET); // enable event CSL_FINST(edma3ccRegs->ICRH, EDMA3CC_ICRH_I52, CLEAR); // clear pending interrupts CSL_FINST(edma3ccRegs->IESRH, EDMA3CC_IESRH_I52, SET); // Enable interrupt for event 52 // map DMA global completion interrupt to cpu int6 CSL_FINS(intcRegs->INTMUX1, INTC_INTMUX1_INTSEL6, CSL_INTC_EVENTID_EDMA3CC_GINT); } void init_qdma(int indata_channels) { CSL_Edma3ccRegsOvly edma3ccRegs = (CSL_Edma3ccRegsOvly)CSL_EDMA3CC_0_REGS; volatile CSL_Edma3ccParamsetRegs *ParmsetQDMA = &edma3ccRegs->PARAMSET[10]; // QDMA CSL_FINS(edma3ccRegs->QCHMAP[0], EDMA3CC_QCHMAP_PAENTRY, 10); // Map QDMA 0 to parameter set 10 CSL_FINS(edma3ccRegs->QCHMAP[0], EDMA3CC_QCHMAP_TRWORD, 3); // Define Trigger Word for QDMA 10, 3: DST CSL_FINS(edma3ccRegs->QDMAQNUM, EDMA3CC_QDMAQNUM_E0, 0); // Use Q0 for QDMA 0 CSL_FINST(edma3ccRegs->QEECR, EDMA3CC_QEECR_E0, CLEAR); // disable QDMA 0 event memset((void *)ParmsetQDMA, 0, sizeof(CSL_Edma3ccParamsetRegs)); CSL_FINST(ParmsetQDMA->OPT, EDMA3CC_OPT_TCINTEN, ENABLE); CSL_FINST(ParmsetQDMA->OPT, EDMA3CC_OPT_STATIC, STATIC); CSL_FINST(ParmsetQDMA->OPT, EDMA3CC_OPT_SYNCDIM, ABSYNC); CSL_FINS(ParmsetQDMA->OPT, EDMA3CC_OPT_TCC, 10); // Use a TCC of 10 for QDMA 10 CSL_FINS(ParmsetQDMA->SRC, EDMA3CC_SRC_SRC, (Uint32)&MeaData); CSL_FINS(ParmsetQDMA->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 4*indata_channels); CSL_FINS(ParmsetQDMA->A_B_CNT, EDMA3CC_A_B_CNT_BCNT, FRAMES_PER_LOOP/DOWNSAMPLE); CSL_FINS(ParmsetQDMA->SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 4*indata_channels*DOWNSAMPLE); // use only every DOWNSAMPLE. Frame from Source CSL_FINS(ParmsetQDMA->SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 4*indata_channels); // Destination is continous CSL_FINS(ParmsetQDMA->LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_LINK, 0xffff); CSL_FINS(ParmsetQDMA->CCNT, EDMA3CC_CCNT_CCNT, 1); CSL_FINST(edma3ccRegs->QEMCR, EDMA3CC_QEMCR_E0, CLEAR); // clear missed events CSL_FINST(edma3ccRegs->QSECR, EDMA3CC_QSECR_E0, CLEAR); // clear secondary events CSL_FINST(edma3ccRegs->ICR, EDMA3CC_ICR_I10, CLEAR); // clear pending interrupts CSL_FINST(edma3ccRegs->QEESR, EDMA3CC_QEESR_E0, SET); // enable QDMA event // CSL_FINS(ParmsetQDMA->DST, EDMA3CC_DST_DST, (Uint32)MatlabPointer); // write trigger word, start transfer // while (CSL_FEXT(edma3ccRegs->IPR, EDMA3CC_IPR_I10) == 0); // wait for completion // CSL_FINST(edma3ccRegs->ICR, EDMA3CC_ICR_I10, CLEAR); // clear pending interrupts } void timer_setperiod(int period) { CSL_TmrRegsOvly tmr1Regs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS; CSL_FINST(tmr1Regs->TCR, TMR_TCR_ENAMODE_LO, DISABLE); CSL_FINS(tmr1Regs->PRDLO,TMR_PRDLO_PRDLO, period); CSL_FINST(tmr1Regs->TIMLO,TMR_TIMLO_TIMLO,RESETVAL); CSL_FINS(tmr1Regs->TCR, TMR_TCR_ENAMODE_LO, 2); // continous mode } void SetMonitorSize(int datapoints) { CSL_Edma3ccRegsOvly edma3ccRegs = (CSL_Edma3ccRegsOvly)CSL_EDMA3CC_0_REGS; volatile CSL_Edma3ccParamsetRegs *ParmsetGPINT5 = &edma3ccRegs->PARAMSET[CSL_EDMA3_CHA_GPINT5]; // outbound data CSL_FINS(ParmsetGPINT5->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 0); WRITE_REGISTER(DSP_OUTDATA_THR, datapoints); WRITE_REGISTER(DSP_OUTDATA_CTRL, 3); // Disable all Data Channels and Clear Fifo CSL_FINS(ParmsetGPINT5->A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 4*datapoints); }

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/dat/_csl_dat.c

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /* ============================================================================ * @file _csl_dat.c * * @path $(CSLPATH)\src\dst * * @desc This file defines section information * */ /* ============================================================================= * Revision History * =============== * 16-Jul-2004 <NAME> File Created. * * ============================================================================= */ #include <csl_dat.h> #include <_csl_dat.h> #pragma DATA_SECTION (_CSL_datStateStruct, ".bss:csl_section:dat"); CSL_DatStateStruct _CSL_datStateStruct;

adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback

DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtGetHwStatus.c

<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/src/bwmngmt/csl_bwmngmtGetHwStatus.c /* ============================================================================ * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * * Use of this software is controlled by the terms and conditions found * in the license agreement under which this software has been supplied * priovided * ============================================================================ */ /** =========================================================================== * @file csl_bwmngmtGetHwStatus.c * * @brief File for functional layer of CSL API @a CSL_bwmngmtGetHwStatus() * * @path $(CSLPATH)\bwmngmt\src * * Description * - The @a CSL_bwmngmtGetHwStatus() function definition & it's associated * functions * * @date 17 Mar, 2006 * @author PSK * ============================================================================= */ /* ============================================================================= * Revision History * =============== * 17-Mar-2006 PSK file created * ============================================================================= */ #include <csl_bwmngmt.h> /** ============================================================================ * @n@b CSL_bwmngmtGetHwStatus * * @b Description * @n Gets the status of the different operations of BWMNGMT. Not Implemented. * For future use. * @b Arguments * @verbatim hBwmngmt Handle to the BWMNGMT instance myQuery The query to this API of BWMNGMT which indicates the status to be returned response Placeholder to return the status @endverbatim * * Return Value CSL_Status * CSL_SOK - Always returns * * * Pre Condition * Both CSL_bwmngmtInit() and CSL_bwmngmtOpen() must * be called successfully in that order before this function can be called * * Post Condition * None * @b Modifies * None * @b Examples: * @verbatim CSL_BwmngmtHandle hBwmngmt; CSL_BwmngmtHwStatusQuery query; void response; // Init Successfully done ... // Open Successfully done ... ... status = CSL_bwmngmtGetHwStatus(hBwmngmt, query, &response); ... @endverbatim * * =========================================================================== */ #pragma CODE_SECTION (CSL_bwmngmtGetHwStatus, ".text:csl_section:bwmngmt"); CSL_Status CSL_bwmngmtGetHwStatus ( /* pointer to the object that holds reference to the * instance of BWMNGMT requested after the call */ CSL_BwmngmtHandle hBwmngmt, /* pointer to setup structure which contains the * information to program BWMNGMT to a useful state */ CSL_BwmngmtHwStatusQuery myQuery, void *response ) { return CSL_SOK; }