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module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire cout_temp[3:0];
genvar i;
assign cout = cout_temp[3];
generate
begin
for (i = 0; i <= 3; i = i + 1) begin : bcd_loop
if (i == 0)
bcd_fadd u_bcd_fadd (
.a(a[4*i+3:4*i]),
.b(b[4*i+3:4*i]),
.cin(cin),
.cout(cout_temp[i]),
.sum(sum[4*i+3:4*i])
);
else
bcd_fadd u_bcd_fadd (
.a(a[4*i+3:4*i]),
.b(b[4*i+3:4*i]),
.cin(cout_temp[i-1]),
.cout(cout_temp[i]),
.sum(sum[4*i+3:4*i])
);
end
end
endgenerate
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
);
assign out = a | b | c;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
);
assign out = a | b | c;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~a & ~d) | (~b & ~c) | (a & c & d) | (b & c & d);
endmodule
| 7.203305
|
module hex_sr #(
parameter LENGTH = 40
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk;
wire recirc;
wire [5:0] data_in;
wire [5:0] data_out;
assign clk = io_in[0];
assign recirc = io_in[1];
assign data_in = io_in[7:2];
assign io_out[7:2] = data_out;
assign io_out[1:0] = 2'b0;
genvar i;
generate
for (i = 0; i < 6; i = i + 1)
sr_recirc #(
.LENGTH(LENGTH)
) sr0 (
clk,
recirc,
data_in[i],
data_out[i]
);
endgenerate
endmodule
| 6.700309
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = ((~a) & (~d)) | ((~a) & (~b) & (~c)) | ((~b) & (~c)) | ((~a) & b & c) | (a & c & d);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~b & c) | a;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (a | ~b) & (c | ~d) & (a | c);
endmodule
| 7.203305
|
module ring_osc (
input nrst,
output osc
);
// We count for 1 scan_clk period which expected at 166uS (6KHz).
// If the delay of one inverter is 20ps and the ring is 150 inverters long,
// then the ring period is 6nS (2*150inv*20pS/inv)
// This is 166MHz so expect a count of 166*166 nominally.
// For more time resolution make scan_clk slower but that requires more
// counter depth.
// scan clk slowing can be done externally to the TT IC or with the clk div.
localparam NUM_INVERTERS = 150; // must be an even number
// setup loop of inverters
// http://svn.clairexen.net/handicraft/2015/ringosc/ringosc.v
wire [NUM_INVERTERS-1:0] delay_in, delay_out;
wire osc_out;
inv_with_delay idelay[NUM_INVERTERS-1:0] (
.A(delay_in),
.Y(delay_out)
);
assign delay_in = {delay_out[NUM_INVERTERS-2:0], osc_out};
nand2_with_delay nand2_with_delay (
.A(nrst),
.B(delay_out[NUM_INVERTERS-1]),
.Y(osc_out)
);
assign osc = osc_out;
endmodule
| 7.339557
|
module ring_with_counter #(
parameter WIDTH = 24
) (
input nrst,
ring_en,
count_en,
output [WIDTH-1:0] count
);
wire [WIDTH:0] value;
wire rst, count_en_s0, count_en_s1, osc, nosc_buf;
genvar i;
ring_osc ring_osc (
.nrst(ring_en),
.osc (osc)
);
inv_with_delay inv_r (
.A(nrst),
.Y(rst)
);
// logic in this module should minimize loading the ring, so buffer the ring output
inv_with_delay inv_b (
.A(osc),
.Y(nosc_buf)
);
// synchronize the counter enable time to the ring oscillator frequency
// so metastability doesnt corrupt the count. note: we count on the ring frequency domain
rdffe ds0 (
.clk(nosc_buf),
.rst(rst),
.en (1'b1),
.d (count_en),
.q (count_en_s0)
);
rdffe ds1 (
.clk(nosc_buf),
.rst(rst),
.en (1'b1),
.d (count_en_s0),
.q (count_en_s1)
);
// Count down toward zero from (signed)-1
assign value[0] = nosc_buf;
generate
for (i = 1; i < WIDTH; i = i + 1)
sdffe dcg (
.clk(value[i-1]),
.pre(rst),
.en (count_en_s1),
.d (~value[i]),
.q (value[i])
);
endgenerate
// value[WIDTH] is the overflow bit. Make it sticky.
// This bit should never be cleared if the measurement is designed correctly.
sdffe dcg (
.clk(value[WIDTH-1]),
.pre(rst),
.en (count_en_s1),
.d (1'b0),
.q (value[WIDTH])
);
assign count[WIDTH-1:0] = value[WIDTH:1];
endmodule
| 8.101785
|
module ericsmi_speed_test (
input [7:0] io_in,
output [7:0] io_out
);
parameter WIDTH = 24;
localparam COUNTER_WIDTH = 23; // TinyTapeout is small, so find a value that fits by trial and error
wire force_trig, fired, count_en;
wire [2:0] sel;
wire [2:0] trig_q;
wire [1:0] ring_en;
wire [WIDTH-1:0] value0, value1;
wire [COUNTER_WIDTH-1:0] count0, count1;
wire clk = io_in[0];
wire nrst = io_in[1];
wire trig = io_in[2];
assign sel[2:0] = io_in[5:3];
assign ring_en[1:0] = io_in[7:6];
assign force_trig = &sel; // force the oscillators and counters to run to test their operation
// not really a controlled measurement. Only for debug.
inv_with_delay inv_r (
.A(nrst),
.Y(rst)
);
// Enable the counters for one clk period upon trig rising edge.
// Asserting nrst arms the measurements. Clear nrst before fire.
rdffe dt0 (
.clk(clk),
.rst(rst),
.en (1'b1),
.d (trig),
.q (trig_q[0])
);
rdffe dt1 (
.clk(clk),
.rst(rst),
.en (1'b1),
.d (trig_q[0]),
.q (trig_q[1])
);
rdffe dt2 (
.clk(clk),
.rst(rst),
.en (1'b1),
.d ((trig_q[0] & ~trig_q[1])),
.q (trig_q[2])
);
rdffe dt3 (
.clk(clk),
.rst(rst),
.en (1'b1),
.d (trig_q[2] | fired),
.q (fired)
);
assign count_en = force_trig | trig_q[2];
ring_with_counter #(
.WIDTH(COUNTER_WIDTH)
) ring0 (
.nrst(nrst),
.ring_en(ring_en[0]),
.count_en(count_en),
.count(count0[COUNTER_WIDTH-1:0])
);
assign value0[WIDTH-1:0] = {
{WIDTH - COUNTER_WIDTH{count0[COUNTER_WIDTH-1]}}, count0[COUNTER_WIDTH-1:0]
};
ring_with_counter #(
.WIDTH(COUNTER_WIDTH)
) ring1 (
.nrst(nrst),
.ring_en(ring_en[1]),
.count_en(count_en),
.count(count1[COUNTER_WIDTH-1:0])
);
assign value1[WIDTH-1:0] = {
{WIDTH - COUNTER_WIDTH{count1[COUNTER_WIDTH-1]}}, count1[COUNTER_WIDTH-1:0]
};
wire [7:0] status;
// when force_trigger is asserted put the status byte on the output, everything is free running.
assign status[7:0] = {
1'b1,
fired,
value1[COUNTER_WIDTH-1], // overflow
value0[COUNTER_WIDTH-1], // overflow
value1[COUNTER_WIDTH-2],
value0[COUNTER_WIDTH-2],
value1[16], // 16=Ceiling@Log2[166*166]+1
value0[16]
};
assign io_out[7:0] = sel[2:0] == 3'b000 ? 8'd0 :
sel[2:0] == 3'b001 ? {value0[7:0]} :
sel[2:0] == 3'b010 ? {value0[15:8]} :
sel[2:0] == 3'b011 ? {value0[23:16]} :
sel[2:0] == 3'b100 ? {value1[7:0]} :
sel[2:0] == 3'b101 ? {value1[15:8]} :
sel[2:0] == 3'b110 ? {value1[23:16]} :
status[7:0] ;
endmodule
| 7.216753
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~a & b & ~c & ~d) | (a & ~b & ~c & ~d) | (~a & ~b & ~c & d) | (a & b & ~c & d)
| (~a & b & c & d) | (a & ~b & c & d) | (~a & ~b & c & ~d) | (a & b & c & ~d);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case ({
a, b, c, d
})
4'b0000, 4'b1100, 4'b0101, 4'b1001, 4'b0011, 4'b1111, 4'b0110, 4'b1010: out = 1'b0;
4'b0100, 4'b1000, 4'b0001, 4'b1101, 4'b0111, 4'b1011, 4'b0010, 4'b1110: out = 1'b1;
default: out = 1'bx;
endcase
end
endmodule
| 7.203305
|
module edge_detect (
input reset,
input clk,
input sig,
input pol,
output out
);
reg sigin;
reg siglast;
assign out = reset ? 1'b0 : (pol ? ((!siglast) && sigin) : (siglast && (!sigin)));
always @(posedge clk) begin
{siglast, sigin} <= {sigin, sig};
//sigin <= sig;
//siglast <= sigin;
end
endmodule
| 7.114144
|
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = (c) & (~b | d) & (~a | d); // De Morgan
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = (c) & (~b | d) & (~a | d);
endmodule
| 7.203305
|
module cpldcpu_TrainLED2top (
input [7:0] io_in,
output [7:0] io_out
);
// Instance 1
TrainLED2 TrainLED2_top1 (
.clk (io_in[0]),
.rst (io_in[1]),
.din (io_in[2]),
.dout(io_out[0]),
.led1(io_out[1]),
.led2(io_out[2]),
.led3(io_out[3])
);
endmodule
| 6.621708
|
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1] & x[3]) | (x[1] & x[2] & ~x[3]);
endmodule
| 7.203305
|
module top_module (
input [4:1] x,
output f
);
assign f = (x[1] | x[3]) & (~x[1] | x[2]) & (~x[1] | ~x[3]);
endmodule
| 7.203305
|
module cpldcpu_MCPU5plus (
input [7:0] io_in,
output [7:0] io_out
);
MCPU5plus MCPU5plus_top (
.clk(io_in[0]),
.rst(io_in[1]),
.inst_in(io_in[7:2]),
.cpu_out(io_out[7:0])
);
endmodule
| 7.203908
|
module MCPU5plus (
inst_in,
cpu_out,
rst,
clk
);
input [5:0] inst_in;
output [7:0] cpu_out;
input rst;
input clk;
localparam OP_BCC = 2'b00; //00IIII
localparam OP_STA = 3'b101; //101RRR
localparam OP_JMPA = 6'b111010; //111010
reg [8:0] accu; // accu(6) is carry !
reg [7:0] pc;
reg [7:0] regfile[0:8];
reg iflag;
integer i;
//handle register file writes (STA)
always @(*) if ((inst_in[5:3] == OP_STA) && ~rst && ~clk) regfile[inst_in[2:0]] <= accu;
always @(posedge clk)
if (rst) begin
accu <= 0;
pc <= 0;
iflag <= 0;
end else begin
// PC
if ((inst_in[5:4] == OP_BCC) && ~accu[8]) // conditional branch (BCC)
pc <= pc + (iflag ? {inst_in[3:0], accu[3:0]} : {{4{inst_in[3]}}, inst_in[3:0]});
else pc <= pc + 1'b1;
// ALU path + carry flag
casex (inst_in)
6'b00????: accu[8] <= 1'b0; // BCC #imm4
6'b01????:
accu[7:0] <= iflag ? { inst_in[3:0], accu[3:0]}: {{4{inst_in[3]}}, inst_in[3:0]} ; // LDI #simm4
6'b100???: accu[8:0] <= {1'b0, regfile[inst_in[2:0]]} + {1'b0, accu[7:0]}; // ADD reg8
6'b101???: ; // STA reg8
6'b110???: accu[7:0] <= regfile[inst_in[2:0]]; // LDA reg8
6'b11100?: accu[8:0] <= {~inst_in[0] & accu[8], ~accu[7:0]} + inst_in[0]; // NEG / NOT
6'b111010: ; // Free
6'b111011: ; // OUT
6'b1111??: ; // Free imm2
endcase
// Flags
casex (inst_in)
6'b01????: iflag <= 1'b1; // LDI #simm4
default: iflag <= 1'b0; // all others
endcase
end
assign cpu_out = clk ? {pc[7:0]} : accu[7:0];
endmodule
| 6.722184
|
module top_module (
input [4:1] x,
output f
);
assign f = (~x[2] & ~x[4]) | (~x[1] & x[3]) | (x[2] & x[3] & x[4]);
endmodule
| 7.203305
|
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1] & x[3]) | (~x[2] & ~x[4]) | (x[2] & x[3] & x[4]);
endmodule
| 7.203305
|
module top_module (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
parameter S = 0, S1 = 1, S11 = 2, S110 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, Count = 8, Wait = 9;
assign B3_next = state[B2];
assign S_next = ((~d) && (state[S] || state[S1] || state[S110])) || (ack && state[Wait]);
assign S1_next = d && state[S];
assign Count_next = ((~done_counting) && state[Count]) || (state[B3]);
assign Wait_next = (done_counting && state[Count]) || ((~ack) && state[Wait]);
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = state[B0] || state[B1] || state[B2] || state[B3];
endmodule
| 7.203305
|
module shake_hand (
clk_send,
clk_recv,
rst_n_send,
rst_n_recv,
din,
dout
);
input clk_send, clk_recv, rst_n_send, rst_n_recv;
input [7:0] din;
output [7:0] dout;
wire [7:0] w_data;
wire ready, ack;
shake_hand_send u1 (
.din (din),
.clk (clk_send),
.rst_n(rst_n_send),
.ack (ack),
.dout (w_data),
.ready(ready)
);
shake_hand_recv u2 (
.din (w_data),
.clk (clk_recv),
.rst_n(rst_n_recv),
.ready(ready),
.dout (dout),
.ack (ack)
);
endmodule
| 6.663953
|
module and_gate (
in1,
in2,
out
);
input in1;
input in2;
output out;
assign out = in1 & in2;
endmodule
| 8.887051
|
module nand_gate (
in1,
in2,
out
);
input in1;
input in2;
output out;
wire tmp; // define a `tmp` wire for the output of the `and_gate` module
and_gate my_and_gate (
.in1(in1), // <- `in1` of `nand_gate` is fed as input to an `and_gate` module
.in2(in2), // <- `in2` of `nand_gate` is fed as input to an `and_gate` module
.out(tmp) // <- the output of `nand_gate` drives the local wire `tmp`
);
not_gate my_not_gate (
.in (tmp), // <- `tmp` is fed as input to an `not_gate` module
.out(out) // <- the output of the module drives the local output `out`
);
endmodule
| 9.197784
|
module that tests the equality between three 2-bit buses can be constructed
// by instantiating twice another module that tests the equality of three bits.
//
module three_equal(
a,
b,
c,
equal
);
input a;
input b;
input c;
output equal;
assign equal = (a == b) & (b == c);
endmodule
| 8.52491
|
module three_buses_equal (
in1,
in2,
in3,
out
);
input [1:0] in1;
input [1:0] in2;
input [1:0] in3;
output out;
wire [1:0] same;
three_equal three_equal0 (
.a(in1[0]),
.b(in2[0]),
.c(in3[0]),
.equal(same[0])
);
three_equal three_equal1 (
.a(in1[1]),
.b(in2[1]),
.c(in3[1]),
.equal(same[1])
);
assign out = same[0] & same[1];
endmodule
| 6.800408
|
module top_module (
input clk,
input in,
input areset,
output out
); //
parameter A = 4'b0001;
parameter B = 4'b0010;
parameter C = 4'b0100;
parameter D = 4'b1000;
reg [3:0] c_state;
reg [3:0] n_state;
reg r_out;
assign out = r_out;
always @(posedge clk or posedge areset) begin
if (areset) begin
c_state <= A;
end else begin
c_state <= n_state;
end
end
always @(*) begin
case (c_state)
A: n_state = in ? B : A;
B: n_state = in ? B : C;
C: n_state = in ? D : A;
D: n_state = in ? B : C;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) begin
r_out <= 0;
end else begin
case (n_state)
D: r_out <= 1;
default: r_out <= 0;
endcase
end
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = ~(a ^ b);
endmodule
| 7.203305
|
module miniPIC (
inout wire [7:0] port_a_pins,
inout wire [7:0] port_b_pins,
inout wire [7:0] port_c_pins,
input wire clk,
input wire resetN
);
initial begin
$display("\nNo simulation results--only checking that example compiles and elaborates\n");
$finish;
end
wire [11:0] instruct_reg, program_data;
wire [10:0] program_counter, program_address;
wire [ 7:0] tmr0_reg, status_reg, fsr_reg, w_reg, option_reg,
reg_file_out, port_a, port_b, port_c, trisa,
trisb, trisc, data_bus, alu_a, alu_b;
wire [6:0] reg_file_addr;
wire [3:0] alu_opcode;
wire [1:0] alu_a_sel, alu_b_sel;
wire reg_file_sel, special_reg_sel, reg_file_enable,
w_reg_enable, zero_enable, carry_enable, skip,
isoption, istris, polarity, carry, zero;
pc_stack pcs ( // module instance with named port connections
.program_counter(program_counter),
.program_address(program_address),
.clk(clk),
.resetN(resetN),
.instruct_reg(instruct_reg),
.data_bus(data_bus),
.status_reg(status_reg)
);
prom prom (
.dout(program_data),
.clk(clk),
.address(program_address)
);
instruction_decode decoder (
.alu_opcode(alu_opcode),
.alu_a_sel(alu_a_sel),
.alu_b_sel(alu_b_sel),
.w_reg_enable(w_reg_enable),
.reg_file_sel(reg_file_sel),
.zero_enable(zero_enable),
.carry_enable(carry_enable),
.polarity(polarity),
.option(isoption),
.tris(istris),
.instruct_reg(instruct_reg)
);
register_files regs (
.dout(reg_file_out),
.tmr0_reg(tmr0_reg),
.status_reg(status_reg),
.fsr_reg(fsr_reg),
.port_a(port_a),
.port_b(port_b),
.port_c(port_c),
.trisa(trisa),
.trisb(trisb),
.trisc(trisc),
.option_reg(option_reg),
.w_reg(w_reg),
.instruct_reg(instruct_reg),
.program_data(program_data),
.port_a_pins(port_a_pins),
.data_bus(data_bus),
.address(reg_file_addr),
.clk(clk),
.resetN(resetN),
.skip(skip),
.reg_file_sel(reg_file_sel),
.zero_enable(zero_enable),
.carry_enable(carry_enable),
.w_reg_enable(w_reg_enable),
.reg_file_enable(reg_file_enable),
.zero(zero),
.carry(carry),
.special_reg_sel(special_reg_sel),
.isoption(isoption),
.istris(istris)
);
alu alu (
.y(data_bus),
.carry_out(carry),
.zero_out(zero),
.a(alu_a),
.b(alu_b),
.opcode(alu_opcode),
.carry_in(status_reg[0])
);
glue_logic glue (
.port_b_pins(port_b_pins),
.port_c_pins(port_c_pins),
.alu_a(alu_a),
.alu_b(alu_b),
.reg_file_addr(reg_file_addr),
.reg_file_enable(reg_file_enable),
.special_reg_sel(special_reg_sel),
.skip(skip),
.instruct_reg(instruct_reg),
.program_counter(program_counter),
.port_a(port_a),
.port_b(port_b),
.port_c(port_c),
.data_bus(data_bus),
.fsr_reg(fsr_reg),
.tmr0_reg(tmr0_reg),
.status_reg(status_reg),
.w_reg(w_reg),
.reg_file_out(reg_file_out),
.alu_a_sel(alu_a_sel),
.alu_b_sel(alu_b_sel),
.reg_file_sel(reg_file_sel),
.polarity(polarity),
.zero(zero)
);
endmodule
| 8.259641
|
modules
module alu (
output reg [ 7:0] y,
output reg carry_out,
output reg zero_out,
input [ 7:0] a,
input [ 7:0] b,
input [ 3:0] opcode,
input carry_in
);
endmodule
| 7.212646
|
module glue_logic (
output reg [ 7:0] port_b_pins,
output reg [ 7:0] port_c_pins,
output reg [ 7:0] alu_a,
output reg [ 7:0] alu_b,
output reg [ 6:0] reg_file_addr,
output reg reg_file_enable,
output reg special_reg_sel,
output reg skip,
input [11:0] instruct_reg,
input [10:0] program_counter,
input [ 7:0] port_a,
input [ 7:0] port_b,
input [ 7:0] port_c,
input [ 7:0] data_bus,
input [ 7:0] fsr_reg,
input [ 7:0] tmr0_reg,
input [ 7:0] status_reg,
input [ 7:0] w_reg,
input [ 7:0] reg_file_out,
input [ 1:0] alu_a_sel,
input [ 1:0] alu_b_sel,
input reg_file_sel,
input polarity,
input zero
);
endmodule
| 7.766993
|
module register_files (
output wire [ 7:0] dout,
output reg [ 7:0] tmr0_reg,
output reg [ 7:0] status_reg,
output reg [ 7:0] fsr_reg,
output reg [ 7:0] port_a,
output reg [ 7:0] port_b,
output reg [ 7:0] port_c,
output reg [ 7:0] trisa,
output reg [ 7:0] trisb,
output reg [ 7:0] trisc,
output reg [ 7:0] option_reg,
output reg [ 7:0] w_reg,
output reg [11:0] instruct_reg,
input [11:0] program_data,
input [ 7:0] port_a_pins,
input [ 7:0] data_bus,
input [ 6:0] address,
input clk,
input resetN,
input skip,
input reg_file_sel,
input zero_enable,
input carry_enable,
input w_reg_enable,
input reg_file_enable,
input zero,
input carry,
input special_reg_sel,
input isoption,
input istris
);
endmodule
| 6.605344
|
module top_module (
input in1,
input in2,
input in3,
output out
);
wire w1 = in1 ~^ in2;
assign out = w1 ^ in3;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = ~(a ^ b);
endmodule
| 7.203305
|
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102
|
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102
|
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102
|
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102
|
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102
|
module top_module (
input c,
input d,
output reg [3:0] mux_in
);
always @(*) begin
case ({
c, d
})
2'b00: mux_in = 4'b0100;
2'b01: mux_in = 4'b0001;
2'b10: mux_in = 4'b0101;
2'b11: mux_in = 4'b1001;
default: mux_in = 4'bx;
endcase
end
// assign mux_in[0] = c + d;
// assign mux_in[1] = 1'b0;
// assign mux_in[2] = c&d;
// assign mux_in[3] = ~d;
endmodule
| 7.203305
|
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 1'b0;
assign mux_in[2] = ~d;
assign mux_in[3] = c & d;
endmodule
| 7.203305
|
module davidsiaw_stackcalc (
input wire [7:0] io_in,
output wire [7:0] io_out
);
stack_cpu cpu (
.io_in (io_in),
.io_out(io_out)
);
endmodule
| 7.15061
|
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk) q <= d;
endmodule
| 7.203305
|
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) q <= d;
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
if (reset) q <= 8'b0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk) begin
if (reset) q <= 8'b0000_0000;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
if (reset) q <= 8'h34;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
if (reset) q <= 8'h34;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output reg [7:0] q
);
always @(negedge clk) begin
if (reset) q <= 8'h34;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 8'd0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 8'b0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
if (~resetn) q <= 0;
else begin
if (byteena[0]) q[7:0] <= d[7:0];
else q[7:0] <= q[7:0];
if (byteena[1]) q[15:8] <= d[15:8];
else q[15:8] <= q[15:8];
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
always @(posedge clk) begin
if (!resetn) q <= 16'b0;
else
case (byteena)
2'b01: q[7:0] <= d[7:0];
2'b10: q[15:8] <= d[15:8];
2'b11: q[15:0] <= d[15:0];
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
always @(posedge clk) begin
if (!resetn) q <= 0;
else begin
q[15:8] <= byteena[1] ? d[15:8] : q[15:8];
q[7:0] <= byteena[0] ? d[7:0] : q[7:0];
end
end
endmodule
| 7.203305
|
module top_module (
input d,
input ena,
output q
);
always @(*) begin
if (ena) q <= d;
else q <= q;
end
endmodule
| 7.203305
|
module top_module (
input d,
input ena,
output q
);
always @(*) begin
if (ena) q <= d;
end
endmodule
| 7.203305
|
module top_module (
input d,
input ena,
output reg q
);
always @(*) begin
if (ena) q = d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q
);
always @(posedge clk or posedge ar) begin
if (ar) q <= 0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q
);
always @(posedge clk or posedge ar) begin
if (ar) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output reg q
);
always @(posedge clk or posedge ar) begin
if (ar) q <= 0;
else q <= d;
end
endmodule
| 7.203305
|
module aramsey118_freq_counter #(
parameter DEPTH = 200
) (
input wire [7:0] io_in,
output wire [7:0] io_out
);
// Precalculate the boundaries
localparam integer freq_0 = $ceil(DEPTH * 0.0); // not used, here for completeness
localparam integer freq_1 = $ceil(DEPTH * 0.1);
localparam integer freq_2 = $ceil(DEPTH * 0.2);
localparam integer freq_3 = $ceil(DEPTH * 0.3);
localparam integer freq_4 = $ceil(DEPTH * 0.4);
localparam integer freq_5 = $ceil(DEPTH * 0.5);
localparam integer freq_6 = $ceil(DEPTH * 0.6);
localparam integer freq_7 = $ceil(DEPTH * 0.7);
localparam integer freq_8 = $ceil(DEPTH * 0.8);
localparam integer freq_9 = $ceil(DEPTH * 0.9);
wire clk = io_in[0];
wire reset = io_in[1];
wire sig = io_in[2];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
assign io_out[7] = sig;
wire [$clog2(DEPTH)-1:0] avg;
reg sig_d1;
reg diff;
reg [3:0] digit;
always @(posedge clk) begin
// if reset, set counter to 0
if (reset) begin
sig_d1 <= 0;
diff <= 0;
digit <= 0;
end else begin
sig_d1 <= sig;
diff <= (sig ^ sig_d1);
if ((avg <= $unsigned(freq_1))) begin
digit <= 0;
end else if ((avg > $unsigned(freq_1)) && (avg <= $unsigned(freq_2))) begin
digit <= 1;
end else if ((avg > $unsigned(freq_2)) && (avg <= $unsigned(freq_3))) begin
digit <= 2;
end else if ((avg > $unsigned(freq_3)) && (avg <= $unsigned(freq_4))) begin
digit <= 3;
end else if ((avg > $unsigned(freq_4)) && (avg <= $unsigned(freq_5))) begin
digit <= 4;
end else if ((avg > $unsigned(freq_5)) && (avg <= $unsigned(freq_6))) begin
digit <= 5;
end else if ((avg > $unsigned(freq_6)) && (avg <= $unsigned(freq_7))) begin
digit <= 6;
end else if ((avg > $unsigned(freq_7)) && (avg <= $unsigned(freq_8))) begin
digit <= 7;
end else if ((avg > $unsigned(freq_8)) && (avg <= $unsigned(freq_9))) begin
digit <= 8;
end else begin
digit <= 9;
end
end
end
// instantiate segment display
seg7 seg7 (
.counter (digit),
.segments(led_out)
);
// instantiate moving average
moving_avg #(
.DEPTH(DEPTH)
) moving_avg (
.data_i(diff),
.reset,
.clk,
.avg_o (avg)
);
endmodule
| 7.292513
|
module top_module (
input clk,
input d,
input r, // synchronous reset
output q
);
always @(posedge clk) begin
if (r) q <= 0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
input r, // synchronous reset
output reg q
);
always @(posedge clk) begin
if (r) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
input r, // synchronous reset
output reg q
);
always @(posedge clk) begin
if (r) q <= 0;
else q <= d;
end
endmodule
| 7.203305
|
module thunderbird_taillight_ctrl #(
parameter MAX_COUNT = 1000,
parameter SYSTEM_FREQ = 6250,
parameter HZ = 8
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire left = io_in[2];
wire right = io_in[3];
wire haz = io_in[4];
wire [5:0] lights = state;
assign io_out[7:0] = {2'b00, lights};
wire div;
divider #(
.SYSTEM_FREQ(SYSTEM_FREQ),
.HZ (HZ)
) divider_i (
.clk (clk),
.reset (reset),
.divider(div)
);
localparam IDLE = 6'b000_000;
localparam L3 = 6'b111_000;
localparam L2 = 6'b011_000;
localparam L1 = 6'b001_000;
localparam R3 = 6'b000_111;
localparam R2 = 6'b000_110;
localparam R1 = 6'b000_100;
localparam LR3 = 6'b111_111;
reg [5:0] state, next_state;
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
end else begin
if (div) begin
state <= next_state;
end
end
end
always @(*) begin
next_state = state;
case (state)
IDLE: begin
case (1'b1)
haz | (left & right): next_state = LR3;
left: next_state = L1;
right: next_state = R1;
default: next_state = IDLE;
endcase
end
L1: next_state = haz ? LR3 : L2;
L2: next_state = haz ? LR3 : L3;
L3: next_state = haz ? LR3 : IDLE;
R1: next_state = haz ? LR3 : R2;
R2: next_state = haz ? LR3 : R3;
R3: next_state = haz ? LR3 : IDLE;
LR3: next_state = IDLE;
default: next_state = state;
endcase
end
endmodule
| 7.32233
|
module divider #(
parameter SYSTEM_FREQ = 6250,
parameter HZ = 8
) (
input clk,
input reset,
output divider
);
localparam CYCLES = SYSTEM_FREQ / HZ;
reg [$clog2(CYCLES) -1:0] cnt;
always @(posedge clk) begin
if (reset) begin
cnt <= 0;
end else begin
cnt <= cnt + 1;
/* verilator lint_off WIDTH */
if (cnt >= (CYCLES - 1)) begin
cnt <= 0;
end
/* verilator lint_on WIDTH */
end
end
assign divider = cnt == 0;
endmodule
| 7.259052
|
module definition indicates that the behavior of
// the module is as if `body` is executed each time that any signal of the `sensitivity_list`
// is modified.
//
// Any wire, input, or output assigned in an `always` construct *must* be defined as `reg`.
// For inputs and outputs, this is done by adding the keyword `reg` in the signal definition.
// For intermediate wires, this is done by replacing the keyword `wire` by `reg`.
//
//
// The following module implements an AND gate.
//
module and_behavior(
a,
b,
c
);
input a;
input b;
output reg c; // <- `c` is defined as `reg` because it is driven inside of a `always` construct
always @(a, b) begin // <- this `always` construct is sensitive to changes of `a` and `b`
c = a & b; // <- when `a` or `b` changes, `c` is updated accordingly; `c` implicitly keeps its value when `a` and `b` stay constant
end
endmodule
| 8.346621
|
module implements a NAND gate.
//
module nand_behavior(
a,
b,
c
);
input a;
input b;
output c; // <- `c` is not a `reg` here because it is not driven inside an `always` construct
reg tmp; // <- `tmp` must be defined as `reg` because it is driven inside an `always` construct
always @(a, b) begin
tmp = a & b;
end
assign c = ~tmp;
endmodule
| 6.904081
|
module LSFR (
clk,
rst_n,
load,
initial_num,
dout
);
input clk, rst_n;
input load;
input [3:0] initial_num;
output reg [3:0] dout;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) dout <= 4'd0;
else if (load) dout <= initial_num;
else begin
dout[0] <= dout[2] ^ dout[3];
dout[1] <= dout[0];
dout[2] <= dout[1];
dout[3] <= dout[2];
end
end
endmodule
| 7.298481
|
module LSFR_tb ();
reg clk, rst_n;
reg load;
reg [3:0] initial_num;
wire [3:0] dout;
initial begin
clk = 0;
load = 0;
initial_num = 4'b1010;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
#10 load = 1;
#10 load = 0;
end
always #2 clk <= ~clk;
LSFR dut (
.clk(clk),
.rst_n(rst_n),
.load(load),
.initial_num(initial_num),
.dout(dout)
);
endmodule
| 6.619622
|
module top_module (
input clk,
input in,
input reset,
output out
); //
parameter A = 4'b0001;
parameter B = 4'b0010;
parameter C = 4'b0100;
parameter D = 4'b1000;
reg [3:0] c_state;
reg [3:0] n_state;
reg r_out;
assign out = r_out;
always @(posedge clk) begin
if (reset) begin
c_state <= A;
end else begin
c_state <= n_state;
end
end
always @(*) begin
case (c_state)
A: n_state = in ? B : A;
B: n_state = in ? B : C;
C: n_state = in ? D : A;
D: n_state = in ? B : C;
endcase
end
always @(posedge clk) begin
if (reset) begin
r_out <= 0;
end else begin
case (n_state)
D: r_out <= 1;
default: r_out <= 0;
endcase
end
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire int1, int2;
assign int1 = a & b;
assign int2 = c & d;
assign out = int1 | int2;
assign out_n = ~out;
endmodule
| 7.203305
|
module interconnections
*
* NOTE: The modules in this example do not contain functionality.
* The purpose of the example is to illustrate connections between
* module instances.
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Sutherland HDL, Inc. *** ALL RIGHTS RESERVED ***
* www.sutherland-hdl.com
*
* Used with permission in the book, "SystemVerilog for Design"
* By Stuart Sutherland, Simon Davidmann, and Peter Flake.
* Book copyright: 2003, Kluwer Academic Publishers, Norwell, MA, USA
* www.wkap.il, ISBN: 0-4020-7530-8
*
* Revision History:
* 1.00 15 Dec 2003 -- original code, as included in book
* 1.01 10 Jul 2004 -- cleaned up comments, added expected results
* to output messages
*
* Caveat: Expected results displayed for this code example are based
* on an interpretation of the SystemVerilog 3.1 standard by the code
* author or authors. At the time of writing, official SystemVerilog
* validation suites were not available to validate the example.
*
* RIGHT TO USE: This code example, or any portion thereof, may be
* used and distributed without restriction, provided that this entire
* comment block is included with the example.
*
* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
* USE OF THIS CODE.
*********************************************************************/
`default_nettype none // turn off implicit net declarations
module top (input wire clock, resetN, test_mode);
wire [15:0] data, address, program_address, jump_address;
wire [ 7:0] instruction, next_instruction;
wire [ 3:0] slave_instruction;
wire slave_request, slave_ready;
wire bus_request, bus_grant;
wire mem_read, mem_write;
wire data_ready;
initial begin
$display("\nNo simulation results--just checking that example compiles and elaborates\n");
$finish;
end
processor proc1 (
// main_bus ports
.data(data),
.address(address),
.slave_instruction(slave_instruction),
.slave_request(slave_request),
.bus_grant(bus_grant),
.mem_read(mem_read),
.mem_write(mem_write),
.bus_request(bus_request),
.slave_ready(slave_ready),
// other ports
.jump_address(jump_address),
.instruction(instruction),
.clock(clock),
.resetN(resetN),
.test_mode(test_mode)
);
slave slave1 (
// main_bus ports
.data(data),
.address(address),
.bus_request(bus_request),
.slave_ready(slave_ready),
.mem_read(mem_read),
.mem_write(mem_write),
.slave_instruction(slave_instruction),
.slave_request(slave_request),
.bus_grant(bus_grant),
.data_ready(data_ready),
// other ports
.clock(clock),
.resetN(resetN)
);
instruction_reg ir (
// main_bus ports
// other ports
.program_address(program_address),
.instruction(instruction),
.jump_address(jump_address),
.next_instruction(next_instruction),
.clock(clock),
.resetN(resetN)
);
dual_port_ram ram (
// main_bus ports
.data(data),
.data_ready(data_ready),
.address(address),
.mem_read(mem_read),
.mem_write(mem_write),
// other ports
.program_address(program_address),
.data_b(next_instruction)
);
test_generator test_gen(
// main_bus ports
.data(data),
.address(address),
.mem_read(mem_read),
.mem_write(mem_write),
// other ports
.clock(clock),
.resetN(resetN),
.test_mode(test_mode)
);
endmodule
| 7.823612
|
module slave (
// main_bus ports
inout wire [15:0] data,
inout wire [15:0] address,
output reg bus_request,
output reg slave_ready,
output wire mem_read,
output wire mem_write,
input wire [ 3:0] slave_instruction,
input wire slave_request,
input wire bus_grant,
input wire data_ready,
// other ports
input wire clock,
input wire resetN
);
//... // module functionality code
endmodule
| 6.668462
|
module dual_port_ram (
// main_bus ports
inout wire [15:0] data,
output wire data_ready,
input wire [15:0] address,
input tri0 mem_read,
input tri0 mem_write,
// other ports
input wire [15:0] program_address,
output reg [ 7:0] data_b
);
//... // module functionality code
endmodule
| 8.55547
|
module instruction_reg (
// main_bus ports
// other ports
output reg [15:0] program_address,
output reg [ 7:0] instruction,
input wire [15:0] jump_address,
input wire [ 7:0] next_instruction,
input wire clock,
input wire resetN
);
//... // module functionality code
endmodule
| 7.263632
|
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire a_and_b;
wire c_and_d;
assign a_and_b = a & b;
assign c_and_d = c & d;
assign out = a_and_b | c_and_d;
assign out_n = ~out;
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
output out
);
assign out = in1 && (!in2);
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) begin
out <= in ^ out;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) begin
out <= in ^ out;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
output reg out
);
always @(posedge clk) begin
out <= out ^ in;
end
endmodule
| 7.203305
|
module gatecat_logic_cell (
input CLK,
input cfg_mode,
input [1:0] cfg_strb,
input [3:0] cfg_data,
input T,
L,
R,
B,
output Q
);
parameter has_ff = 1'b0;
// config storage
wire [7:0] cfg;
generate
genvar ii, jj;
for (ii = 0; ii < 2; ii = ii + 1'b1)
for (jj = 0; jj < 4; jj = jj + 1'b1)
sky130_fd_sc_hd__dlxtn_1 cfg_lat_i (
.D(cfg_data[jj]),
.GATE_N(cfg_strb[ii]),
.Q(cfg[ii*4+jj])
);
endgenerate
wire i0, i1;
// I input muxes
wire i0a, i0b;
sky130_fd_sc_hd__nand2_1 i0muxa0 (
.A(T),
.B(cfg[0]),
.Y(i0a)
);
sky130_fd_sc_hd__mux2i_1 i0muxa1 (
.A0(R),
.A1(L),
.S (cfg[0]),
.Y (i0b)
);
sky130_fd_sc_hd__mux2i_1 i0muxb (
.A0(i0a),
.A1(i0b),
.S (cfg[1]),
.Y (i0)
);
wire i1a, i1b;
sky130_fd_sc_hd__and2_1 i1muxa0 (
.A(cfg[2]),
.B(L),
.X(i1a)
);
sky130_fd_sc_hd__mux2i_1 i1muxa1 (
.A0(B),
.A1(R),
.S (cfg[2]),
.Y (i1b)
);
sky130_fd_sc_hd__mux2i_1 i1muxb (
.A0(i1a),
.A1(i1b),
.S (cfg[3]),
.Y (i1)
);
// S input mux
wire s0s, s0, s0a, s0b;
sky130_fd_sc_hd__nand2_1 s0muxa0 (
.A(T),
.B(cfg[4]),
.Y(s0a)
);
sky130_fd_sc_hd__mux2i_1 s0muxa1 (
.A0(R),
.A1(L),
.S (cfg[4]),
.Y (s0b)
);
sky130_fd_sc_hd__mux2i_1 s0muxb (
.A0(s0a),
.A1(s0b),
.S (cfg[5]),
.Y (s0s)
);
// S invert
sky130_fd_sc_hd__xnor2_1 sinv (
.A(s0s),
.B(cfg[6]),
.Y(s0)
);
// The logic element
wire muxo_n;
sky130_fd_sc_hd__mux2i_1 lmux (
.A0(i0),
.A1(i1),
.S (s0),
.Y (muxo_n)
);
// The DFF
generate
if (has_ff) begin : dff
wire dffo_n;
sky130_fd_sc_hd__dfsbp_1 dff (
.D(muxo_n),
.SET_B(~cfg_mode),
.CLK(CLK),
.Q(dffo_n)
);
// The final output mux
sky130_fd_sc_hd__mux2i_1 ffsel (
.A0(muxo_n),
.A1(dffo_n),
.S (cfg[7]),
.Y (Q)
);
end else begin
sky130_fd_sc_hd__inv_1 linv (
.A(muxo_n),
.Y(Q)
);
end
endgenerate
endmodule
| 6.648182
|
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
if (L) Q <= r_in;
else Q <= q_in;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
if (L) Q <= r_in;
else Q <= q_in;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
Q <= L ? r_in : q_in;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
always @(posedge clk) begin
if (L) Q <= R;
else begin
if (E) Q <= w;
else Q <= Q;
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input w,
R,
E,
L,
output reg Q
);
reg a;
always @(posedge clk) begin
case ({
E, L
})
2'b01: Q <= R;
2'b10: Q <= w;
2'b11: Q <= R;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
wire mux_out;
wire D;
multiplexer multiplexer_u0 (
.a (Q),
.b (w),
.sel(E),
.o (mux_out)
);
multiplexer multiplexer_u1 (
.a (mux_out),
.b (R),
.sel(L),
.o (D)
);
FF FF_u0 (
.clk(clk),
.d (D),
.q (Q)
);
endmodule
| 7.203305
|
module multiplexer (
input a,
b,
sel,
output o
);
assign o = sel ? b : a;
endmodule
| 7.049663
|
module top_module (
input clk,
input x,
output z
);
reg [2:0] Q;
always @(posedge clk) begin
Q[0] <= Q[0] ^ x;
Q[1] <= ~Q[1] & x;
Q[2] <= ~Q[2] | x;
end
assign z = ~(|Q);
endmodule
| 7.203305
|
module top_module (
input clk,
input x,
output z
);
reg q1, q2, q3;
always @(posedge clk) begin
q1 <= x ^ q1;
end
always @(posedge clk) begin
q2 <= x & ~q2;
end
always @(posedge clk) begin
q3 <= x | ~q3;
end
assign z = ~(q1 | q2 | q3);
endmodule
| 7.203305
|
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