code
stringlengths 35
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| score
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|---|---|
module top_module (
input in1,
input in2,
output out
);
assign out = in1 & (~in2);
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = ~(in1 ^ in2) ^ in3;
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = (in1 ~^ in2) ^ in3;
endmodule
| 7.203305
|
module tt2_tholin_multiplier (
input [7:0] io_in,
output [7:0] io_out
);
wire s_A0 = io_in[0];
wire s_A1 = io_in[1];
wire s_A2 = io_in[2];
wire s_A3 = io_in[3];
wire s_B0 = io_in[4];
wire s_B1 = io_in[5];
wire s_B2 = io_in[6];
wire s_B3 = io_in[7];
wire s_R0;
wire s_R1;
wire s_R2;
wire s_R3;
wire s_R4;
wire s_R5;
wire s_R6;
wire s_R7;
assign io_out[0] = s_R0;
assign io_out[1] = s_R1;
assign io_out[2] = s_R2;
assign io_out[3] = s_R3;
assign io_out[4] = s_R4;
assign io_out[5] = s_R5;
assign io_out[6] = s_R6;
assign io_out[7] = s_R7;
main CIRCUIT_0 (
.A0(s_A0),
.A1(s_A1),
.A2(s_A2),
.A3(s_A3),
.B0(s_B0),
.B1(s_B1),
.B2(s_B2),
.B3(s_B3),
.R0(s_R0),
.R1(s_R1),
.R2(s_R2),
.R3(s_R3),
.R4(s_R4),
.R5(s_R5),
.R6(s_R6),
.R7(s_R7)
);
endmodule
| 6.97729
|
module top_module (
input a,
b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = ~(a ^ b);
assign out_anotb = a & (~b);
endmodule
| 7.203305
|
module top_module (
input a,
b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = a ~^ b;
assign out_anotb = a & (~b);
endmodule
| 7.203305
|
module has a 4-bit input bus as input, and a 7-bit output bus as output.
//
module example_bus(
a,
b
);
input [3:0] a; // <- `a` is 4-bit bus
output [6:0] b; // <- `b` is 7-bit bus
endmodule
| 7.988239
|
module is thus a 3-bit buffer.
//
module buffer3(
in,
out
);
input [2:0] in;
output [2:0] out;
assign out = in; // <- this line performs 3 connections
endmodule
| 8.339893
|
modules checks if its two input buses are identical.
//
module same_buses(
in1,
in2,
all_equal
);
input [3:0] in1;
input [3:0] in2;
output all_equal;
wire [3:0] equal;
assign equal[0] = in1[0] == in2[0];
assign equal[1] = in1[1] == in2[1];
assign equal[2] = in1[2] == in2[2];
assign equal[3] = in1[3] == in2[3];
assign all_equal = equal[0] & equal[1] & equal[2] & equal[3];
endmodule
| 6.607486
|
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena
);
reg cnt_ena = 0;
reg [2:0] cnt;
always @(posedge clk) begin
if (reset) begin
cnt <= 0;
cnt_ena <= 1;
end else begin
if (cnt == 4 - 1) begin
cnt_ena <= 0;
cnt <= cnt;
end else begin
cnt <= cnt + 1;
end
end
end
assign shift_ena = cnt_ena;
endmodule
| 7.203305
|
module mod3 (
clk,
rst_n,
din,
dout
);
input clk, rst_n, din;
output reg dout;
parameter idle = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;
reg [1:0] state, next_state;
always @(posedge clk or negedge rst_n)
if (~rst_n) begin
state <= idle;
end else state <= next_state;
always @(posedge clk or negedge rst_n)
if (~rst_n) dout <= 1'b0;
else begin
if (state == s3) dout <= 1'b1;
else dout <= 1'b0;
end
always @(din or state) begin
case (state)
idle: begin
if (din) next_state <= s1;
else next_state <= idle;
end
s1: begin
if (din) next_state <= s2;
else next_state <= s1;
end
s2: begin
if (din) next_state <= s3;
else next_state <= s2;
end
s3: begin
if (din) next_state <= s1;
else next_state <= idle;
end
default: state <= idle;
endcase
end
endmodule
| 7.36043
|
module top_module (
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = k ? OFF : ON;
endcase
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if (reset) begin
state <= OFF;
end else begin
state <= next_state;
end
end
// Output logic
assign out = (state == ON);
endmodule
| 7.203305
|
module DUAL_FIFO (
clk,
rst_n,
in_data,
out_data,
fifo_empty,
fifo_full,
wr_en,
rd_en
);
parameter Data_Depth = 256;
parameter Data_Width = 8;
parameter Add_Depth = 8; //256的bit位数
input clk, rst_n, wr_en;
input [Data_Width-1:0] in_data;
output wire [Data_Width-1:0] out_data;
output fifo_empty, fifo_full, rd_en;
//定义fifo_mem
reg[Data_Width-1:0] fifo_mem[Data_Depth];
reg[Add_Depth-1:0] wr_addr;
reg[Add_Depth-1:0] rd_addr;
reg[Add_Depth:0] counts; //计数的位数
always @(posedge clk) begin
if (!rst_n) begin
integer i;
for (i = 0; i < Data_Depth; i = i + 1) begin
fifo_mem[i] = 'b0;
end
end else if (wr_en && !fifo_full) begin
fifo_mem[wr_addr] <= in_data;
end
end
always @(posedge clk) begin //写入的计数
if (!rst_n) begin
wr_addr <= 'b0;
end else if (wr_en && !fifo_full) begin
wr_addr <= (wr_addr == Data_Depth - 1) ? 'b0 : wr_addr + 1'b1;
end
end
always @(posedge clk) begin
if (!rst_n) begin
rd_addr <= 'b0;
end else if (rd_en && !fifo_empty) begin
rd_addr <= (rd_addr == Data_Depth - 1) ? 'b0 : rd_addr + 1'b1;
end
end
always @(posedge clk) begin
if (!rst_n) begin
counts <= 'b0;
end else if (wr_en && !fifo_full && !rd_en) begin
counts <= counts + 1'b1;
end else if (rd_en && !fifo_empty && !wr_en) begin
counts <= counts - 1'b1;
end
end
assign out_data = fifo_mem[rd_addr];
assign fifo_empty = counts == 'b0;
assign fifo_full = counts == Data_Depth;
endmodule
| 7.935951
|
module AdderSub (
sum_diff,
carry,
A,
B,
select
);
output [3:0] sum_diff;
output carry;
input [3:0] A, B;
input select;
wire w0, w1, w2, w3;
wire B0, B1, B2, B3;
xor x0 (B0, B[0], select);
xor x1 (B1, B[1], select);
xor x2 (B2, B[2], select);
xor x3 (B3, B[3], select);
assign {w0, sum_diff[0]} = A[0] + B0 + select;
assign {w1, sum_diff[1]} = A[1] + B1 + w0;
assign {w2, sum_diff[2]} = A[2] + B2 + w1;
assign {w3, sum_diff[3]} = A[3] + B3 + w2;
assign carry = w3 + select;
endmodule
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|
module top_module (
input in,
output out
);
assign out = ~in; //~ : bitwise negation operator
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = ~in;
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module alu1 (
output [3:0] s,
input [3:0] a,
input [3:0] b
);
xor xor1 (x1, a[3], b[3]);
fa fa1 (
s[0],
w1,
a[0],
b[0],
x1
);
fa fa2 (
s[1],
w2,
a[1],
b[1],
w1
);
fa fa3 (
s[2],
s[3],
a[2],
b[2],
w2
);
endmodule
| 7.4996
|
module alu2 (
output [3:0] s,
output eqzero,
input [3:0] a,
input [3:0] b
);
xor xor1 (x1, a[3], b[3]);
fa fa1 (
s[0],
w1,
a[0],
b[0],
x1
);
fa fa2 (
s[1],
w2,
a[1],
b[1],
w1
);
fa fa3 (
s[2],
s[3],
a[2],
b[2],
w2
);
nor nor1 (eqzero, s[0], s[1], s[2], s[3]);
endmodule
| 6.924433
|
module alu1 (
output [3:0] s,
output overflow,
input [3:0] a,
input [3:0] b,
input inca,
input incb
);
wire [3:0] k;
xor xor1 (x1, a[3], b[3]);
fa fa1 (
k[0],
w1,
a[0],
b[0],
x1
);
fa fa2 (
k[1],
w2,
a[1],
b[1],
w1
);
fa fa3 (
k[2],
k[3],
a[2],
b[2],
w2
);
increment inc1 (
s,
overflow,
k,
inca,
incb
);
endmodule
| 7.4996
|
module alu1 (
output [3:0] s,
output overflow,
output gr,
output ls,
input [3:0] a,
input [3:0] b,
input inca,
input incb
);
wire [3:0] k;
xor xor1 (x1, a[3], b[3]);
fa fa1 (
k[0],
w1,
a[0],
b[0],
x1
);
fa fa2 (
k[1],
w2,
a[1],
b[1],
w1
);
fa fa3 (
k[2],
k[3],
a[2],
b[2],
w2
);
increment inc1 (
s,
overflow,
k,
inca,
incb
);
grless grless1 (
gr,
ls,
a,
b
);
endmodule
| 7.4996
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
| 7.203305
|
module tt2_tholin_multiplexed_counter (
input [7:0] io_in,
output [7:0] io_out
);
wire s_A;
wire s_B;
wire s_C;
wire s_CLK = io_in[0];
wire s_D;
wire s_E;
wire s_F;
wire s_G;
wire s_RST = io_in[1];
wire s_SEL;
assign io_out[0] = s_A;
assign io_out[1] = s_B;
assign io_out[2] = s_C;
assign io_out[3] = s_D;
assign io_out[4] = s_E;
assign io_out[5] = s_F;
assign io_out[6] = s_G;
assign io_out[7] = s_SEL;
main CIRCUIT_0 (
.A (s_A),
.B (s_B),
.C (s_C),
.CLK(s_CLK),
.D (s_D),
.E (s_E),
.F (s_F),
.G (s_G),
.RST(s_RST),
.SEL(s_SEL)
);
endmodule
| 6.97729
|
module github_com_proppy_tt02_xls_counter (
input wire [7:0] io_in,
output wire [7:0] io_out
);
wire rdy = 1;
wire vld;
user_module counter0 (
io_in[0],
io_in[1],
rdy,
io_out,
vld
);
endmodule
| 7.341325
|
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
always @(*) begin
if (~x3 & ~x2 & ~x1) f = 1'b0;
else if (~x3 & ~x2 & x1) f = 1'b0;
else if (x3 & ~x2 & ~x1) f = 1'b0;
else if (x3 & x2 & ~x1) f = 1'b0;
else f = 1'b1;
end
endmodule
| 7.203305
|
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = ((~x1) & x2 & (~x3)) | (x1 & x2 & (~x3)) | (x1 & (~x2) & x3) | (x1 & x2 & x3);
endmodule
| 7.203305
|
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
assign z = 1'b1 ? (A == B) : (A != B);
endmodule
| 7.203305
|
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
assign z = (A == B) ? 1'b1 : 1'b0;
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
assign z = (~x & ~y) | (x & y);
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
assign z = x ~^ y;
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
wire z1, z2, z3, z4;
IA IA_u0 (
.x(x),
.y(y),
.z(z1)
);
IB IB_u0 (
.x(x),
.y(y),
.z(z2)
);
IA IA_u1 (
.x(x),
.y(y),
.z(z3)
);
IB IB_u1 (
.x(x),
.y(y),
.z(z4)
);
assign z = (z1 | z2) ^ (z3 & z4);
endmodule
| 7.203305
|
module IA (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.865739
|
module top_module (
input x,
input y,
output z
);
wire z_A_1;
wire z_A_2;
wire z_B_1;
wire z_B_2;
A ia1 (
.x(x),
.y(y),
.z(z_A_1)
);
A ia2 (
.x(x),
.y(y),
.z(z_A_2)
);
B ib1 (
.x(x),
.y(y),
.z(z_B_1)
);
B ib2 (
.x(x),
.y(y),
.z(z_B_2)
);
assign z = (z_A_1 | z_B_1) ^ (z_A_2 & z_B_2);
endmodule
| 7.203305
|
module A
module A (
input x,
input y,
output z);
assign z = (x ^ y) & x;
endmodule
| 8.261177
|
module B
module B ( input x, input y, output z );
assign z = x ~^ y;
endmodule
| 8.891839
|
module jleightcap_top (
input wire [7:0] io_in
, output wire [7:0] io_out
);
top _top (
.clk(io_in[0])
, .rst(io_in[1])
, .instr(io_in[7:2])
, .io_out(io_out)
);
endmodule
| 7.906323
|
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = (ring & ~vibrate_mode);
assign motor = (ring & vibrate_mode);
endmodule
| 7.203305
|
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ring & (~vibrate_mode);
assign motor = ring & vibrate_mode;
endmodule
| 7.203305
|
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode & too_cold;
assign aircon = ~mode & too_hot;
assign fan = heater | aircon | fan_on;
endmodule
| 7.203305
|
module top_module (
input [2:0] in,
output [1:0] out
);
assign out = in[2] + in[1] + in[0];
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = {in[3] & in[2], in[2] & in[1], in[1] & in[0]};
assign out_any = {in[3] | in[2], in[2] | in[1], in[1] | in[0]};
assign out_different = {in[0] ^ in[3], in[3] ^ in[2], in[2] ^ in[1], in[1] ^ in[0]};
endmodule
| 7.203305
|
module top_module (
input [2:0] in,
output [1:0] out
);
assign out[1] = (in[2] & in[1] | in[2] & in[0] | in[1] & in[0]);
assign out[0] = (~in[2])&(~in[1])&(in[0]) | (~in[2])&(in[1])&(~in[0]) | (in[2])&(~in[1])&(~in[0]) | (in[2])&(in[1])&(in[0]);
endmodule
| 7.203305
|
module krasin_3_bit_8_channel_pwm_driver (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire pset = io_in[1];
wire [2:0] addr = io_in[4:2];
wire [2:0] level = io_in[7:5];
wire [7:0] pwm_out;
assign io_out[7:0] = pwm_out;
// This register is used to determine if the execution just started and we need to reset.
// It's a bullshit implementation and will most likely not work. I am curious to test it anyway.
// The idea is that initially this register has a somewhat random value. If it does not match what we expect,
// we're in a reset mode and set this register to the expected state + reset all other registers.
// This is not a great way, as it does not guarantee anything, but I already use all input pins and
// like to live dangerously.
reg [8:0] reset_canary = 0;
// 3-bit PWM counter that goes from 0 to 7.
reg [2:0] counter;
function is_reset(input [8:0] a);
begin
is_reset = (a != 8'b01010101);
end
endfunction
// PWM level for channel0.
// 0 means always off.
// 1 means that PWM will be on for just 1 clock cycle and then off for the other 6, giving 1/7 on average.
// 6 means 6/7 on.
// 7 means always on.
reg [2:0] pwm0_level;
// The rest of the channels.
reg [2:0] pwm1_level;
reg [2:0] pwm2_level;
reg [2:0] pwm3_level;
reg [2:0] pwm4_level;
reg [2:0] pwm5_level;
reg [2:0] pwm6_level;
reg [2:0] pwm7_level;
function is_on(input [3:0] level, input [3:0] counter);
begin
is_on = (counter < level);
end
endfunction // is_on
assign pwm_out[0] = is_on(pwm0_level, counter);
assign pwm_out[1] = is_on(pwm1_level, counter);
assign pwm_out[2] = is_on(pwm2_level, counter);
assign pwm_out[3] = is_on(pwm3_level, counter);
assign pwm_out[4] = is_on(pwm4_level, counter);
assign pwm_out[5] = is_on(pwm5_level, counter);
assign pwm_out[6] = is_on(pwm6_level, counter);
assign pwm_out[7] = is_on(pwm7_level, counter);
// external clock is 1000Hz.
always @(posedge clk) begin
// if reset, set counter and pwm levels to 0
if (is_reset(reset_canary)) begin
reset_canary = 8'b01010101;
counter <= 0;
pwm0_level <= 0;
pwm1_level <= 0;
pwm2_level <= 0;
pwm3_level <= 0;
pwm4_level <= 0;
pwm5_level <= 0;
pwm6_level <= 0;
pwm7_level <= 0;
end else begin // if (is_reset(reset_canary))
if (counter == 6) begin
// Roll over.
counter <= 0;
end else begin
// increment counter
counter <= counter + 1'b1;
end
if (pset) begin
case (addr)
0: pwm0_level <= level;
1: pwm1_level <= level;
2: pwm2_level <= level;
3: pwm3_level <= level;
4: pwm4_level <= level;
5: pwm5_level <= level;
6: pwm6_level <= level;
7: pwm7_level <= level;
endcase
end // if (set)
end
end // always @ (posedge clk)
endmodule
| 7.687409
|
module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = {(in[3] & in[2]), (in[2] & in[1]), (in[1] & in[0])};
assign out_any = {(in[3] | in[2]), (in[2] | in[1]), (in[1] | in[0])};
assign out_different = {(in[0] ^ in[3]), (in[3] ^ in[2]), (in[2] ^ in[1]), (in[1] ^ in[0])};
endmodule
| 7.203305
|
module top_module (
// input [3:0] in,
// output [2:0] out_both,
// output [3:1] out_any,
// output [3:0] out_different
// );
// // Use bitwise operators and part-select to do the entire calculation in one line of code
// // in[3:1] is this vector: in[3] in[2] in[1]
// // in[2:0] is this vector: in[2] in[1] in[0]
// // Bitwise-OR produces a 3 bit vector. | | |
// // Assign this 3-bit result to out_any[3:1]: o_a[3] o_a[2] o_a[1]
// // Thus, each output bit is the OR of the input bit and its neighbour to the right:
// // e.g., out_any[1] = in[1] | in[0];
// // Notice how this works even for long vectors.
// assign out_any = in[3:1] | in[2:0];
// assign out_both = in[2:0] & in[3:1];
// // XOR 'in' with a vector that is 'in' rotated to the right by 1 position: {in[0], in[3:1]}
// // The rotation is accomplished by using part selects[] and the concatenation operator{}.
// assign out_different = in ^ {in[0], in[3:1]};
// endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
parameter IDLE = 0, SEQ_0 = 1, SEQ_1 = 2, SEQ_2 = 3;
parameter SHIFT = 4, COUNT = 5, DONE = 6;
reg [2:0] cstate, nstate;
reg shift_end;
reg [2:0] cnt;
always @(posedge clk) begin
if (reset) begin
cstate <= IDLE;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
IDLE: nstate = data ? SEQ_0 : IDLE;
SEQ_0: nstate = data ? SEQ_1 : IDLE;
SEQ_1: nstate = data ? SEQ_1 : SEQ_2;
SEQ_2: nstate = data ? SHIFT : IDLE;
SHIFT: nstate = shift_end ? COUNT : SHIFT;
COUNT: nstate = done_counting ? DONE : COUNT;
DONE: nstate = ack ? IDLE : DONE;
endcase
end
always @(posedge clk) begin
if (reset) begin
cnt <= 3'b000;
shift_end <= 0;
end else begin
if (shift_ena) begin
if (cnt == 2) begin
shift_end <= 1;
end else begin
cnt <= cnt + 1;
end
end else begin
shift_end <= 0;
cnt <= 3'b000;
end
end
end
assign shift_ena = (cstate == SHIFT);
assign counting = (cstate == COUNT);
assign done = (cstate == DONE);
endmodule
| 7.203305
|
module:send part
//author:WangFW
//date:2020-5-2
module shake_hand_send(clk,rst_n,ack,din,dout,ready);
input clk,rst_n;
input ack;
input [7:0] din;
output reg [7:0] dout;
output reg ready;
reg ack_d1,ack_d2;
reg [1:0] state,next_state;
parameter idle=2'b00,send=2'b01,ack_active=2'b10,ack_check=2'b11;
reg [7:0] data_buf;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
ack_d1<=1'b0;
ack_d2<=1'b0;
end
else
begin
ack_d1<=ack;
ack_d2<=ack_d1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
dout<=8'd0;
ready<=1'b0;
state<=idle;
end
else
begin
case(state)
idle:begin
ready<=1'b0;
state<=send;
end
send:begin
ready<=1'b1;
state<=ack_active;
end
ack_active:begin
if(ack_d2==1'b1)
begin
dout<=din;
ready<=1'b0;
state<=ack_check;
end
else
state<=ack_active;
end
ack_check:begin
if(ack_d2==1'b0)
state<=send;
else
state<=ack_check;
end
default:state<=idle;
endcase
end
end
endmodule
| 6.750339
|
module shake_hand_send_tb ();
reg clk, rst_n;
reg ack;
reg [7:0] din;
wire ready;
wire [7:0] dout;
initial begin
clk = 0;
rst_n = 1;
ack = 0;
din = 8'd0;
#10 rst_n = 0;
#10 rst_n = 1;
#10 din = 8'b1010_1010;
#10 ack = 1'b1;
#10 ack = 1'b0;
end
always #2 clk <= ~clk;
shake_hand_send dut (
.clk (clk),
.rst_n(rst_n),
.din (din),
.ack (ack),
.dout (dout),
.ready(ready)
);
endmodule
| 6.619686
|
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: next_state = f(state, in)
assign next_state = in ? ((state == C) ? D : B) : (((state == C) | (state == A)) ? A : C);
// Output logic: out = f(state) for a Moore state machine
assign out = (state == D);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = a & b; // & : Bit-wise and operator
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = a && b;
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305
|
module pulse2 (
signal,
clock
);
input clock;
output signal;
reg signal;
always @(posedge clock) begin
signal = 1'b1;
#5 signal = 1'b0;
end
endmodule
| 6.524618
|
module pulse3 (
signal,
clock
);
input clock;
output signal;
reg signal;
always @(negedge clock) begin
signal = 1'b1;
#15 signal = 1'b0;
#15 signal = 1'b1;
end
endmodule
| 6.545395
|
module top_module (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
assign out_both = in[99:1] & in[98:0];
assign out_any = in[99:1] | in[98:0];
assign out_different = {in[0], in[99:1]} ^ in[99:0];
endmodule
| 7.203305
|
module cchan_fp8_multiplier (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire [2:0] ctrl = io_in[3:1];
wire [3:0] data = io_in[7:4];
// wire [6:0] led_out;
// assign io_out[6:0] = led_out;
// wire [5:0] seed_input = io_in[7:2];
reg [8:0] operand1;
reg [8:0] operand2;
// For now we're commenting this out and leaving the results unbuffered.
// reg [8:0] result_out;
// assign io_out = result_out;
always @(posedge clk) begin
if (!ctrl[0]) begin // if first CTRL bit is off, we're in STORE mode
if (!ctrl[1]) begin // second CTRL bit controls whether it's the first or second operand
if (!ctrl[2]) begin // third CTRL bit controls whether it's the upper or lower half
operand1[3:0] <= data;
end else begin
operand1[7:4] <= data;
end
end else begin
if (!ctrl[2]) begin
operand2[3:0] <= data;
end else begin
operand2[7:4] <= data;
end
end
end else begin // if first CTRL bit is on, this is reserved.
// TODO
// if (!ctrl[1] && !ctrl[2]) begin
// result_out[7:0] <= 0;
// end
end
end
// Compute result_out in terms of operand1, operand2
fp8mul mul1 (
.sign1(operand1[7]),
.exp1(operand1[6:3]),
.mant1(operand1[2:0]),
.sign2(operand2[7]),
.exp2(operand2[6:3]),
.mant2(operand2[2:0]),
.sign_out(io_out[7]),
.exp_out(io_out[6:3]),
.mant_out(io_out[2:0])
);
endmodule
| 7.207859
|
module fp8mul (
input sign1,
input [3:0] exp1,
input [2:0] mant1,
input sign2,
input [3:0] exp2,
input [2:0] mant2,
output sign_out,
output [3:0] exp_out,
output [2:0] mant_out
);
parameter EXP_BIAS = 7;
wire isnan = (sign1 == 1 && exp1 == 0 && mant1 == 0) || (sign2 == 1 && exp2 == 0 && mant2 == 0);
wire [7:0] full_mant = ({exp1 != 0, mant1} * {exp2 != 0, mant2});
wire overflow_mant = full_mant[7];
wire [6:0] shifted_mant = overflow_mant ? full_mant[6:0] : {full_mant[5:0], 1'b0};
// is the mantissa overflowing up to the next exponent?
wire roundup = (exp1 + exp2 + overflow_mant < 1 + EXP_BIAS) && (shifted_mant[6:0] != 0)
|| (shifted_mant[6:4] == 3'b111 && shifted_mant[3]);
wire underflow = (exp1 + exp2 + overflow_mant) < 1 - roundup + EXP_BIAS;
wire is_zero = exp1 == 0 || exp2 == 0 || isnan || underflow;
// note: you can't use negative numbers reliably. just keep things positive during compares.
wire [4:0] exp_out_tmp = (exp1 + exp2 + overflow_mant + roundup) < EXP_BIAS ? 0 : (exp1 + exp2 + overflow_mant + roundup - EXP_BIAS);
assign exp_out = exp_out_tmp > 15 ? 4'b1111 : (is_zero) ? 0 : exp_out_tmp[3:0]; // Exponent bias is 7
assign mant_out = exp_out_tmp > 15 ? 3'b111 : (is_zero || roundup) ? 0 : (shifted_mant[6:4] + (shifted_mant[3:0] > 8 || (shifted_mant[3:0] == 8 && shifted_mant[4])));
assign sign_out = ((sign1 ^ sign2) && !(is_zero)) || isnan;
endmodule
| 7.084548
|
module top_module (
input [99:0] in,
output reg [98:0] out_both,
output reg [99:1] out_any,
output reg [99:0] out_different
);
integer i;
always @(*) begin
for (i = 98; i >= 0; i = i - 1) begin
out_both[i] = in[i+1] & in[i];
end
for (i = 99; i >= 1; i = i - 1) begin
out_any[i] = in[i] | in[i-1];
end
for (i = 99; i >= 0; i = i - 1) begin
if (i == 99) out_different[i] = in[0] ^ in[i];
else out_different[i] = in[i+1] ^ in[i];
end
end
endmodule
| 7.203305
|
module top_module (
input a,
b,
sel,
output out
);
assign out = sel ? b : a;
endmodule
| 7.203305
|
module top_module (
input a,
b,
sel,
output out
);
assign out = sel ? b : a;
endmodule
| 7.203305
|
module tt2_tholin_diceroll (
input [7:0] io_in,
output [7:0] io_out
);
wire CLK = io_in[0];
wire RST = io_in[1];
wire ROLL = io_in[2];
wire [7:0] LEDS;
assign io_out[7:0] = LEDS;
dice dice (
.CLK (CLK),
.RST (RST),
.ROLL(ROLL),
.LEDS(LEDS)
);
endmodule
| 7.397118
|
module top_module (
input [99:0] a,
b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
c,
d,
e,
f,
g,
h,
i,
input [ 3:0] sel,
output [15:0] out
);
always @(*) begin
case (sel)
4'd0: out = a;
4'd1: out = b;
4'd2: out = c;
4'd3: out = d;
4'd4: out = e;
4'd5: out = f;
4'd6: out = g;
4'd7: out = h;
4'd8: out = i;
default: out = 16'hffff;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
c,
d,
e,
f,
g,
h,
i,
input [3:0] sel,
output reg [15:0] out
);
always @(*) begin
case (sel)
4'b0000: out = a;
4'b0001: out = b;
4'b0010: out = c;
4'b0011: out = d;
4'b0100: out = e;
4'b0101: out = f;
4'b0110: out = g;
4'b0111: out = h;
4'b1000: out = i;
default: out = 16'hffff;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| 7.203305
|
module top_module (
input [255:0] in,
input [7:0] sel,
output reg out
);
integer i;
always @(*) begin
out = 1'b0;
for (i = 0; i <= 255; i = i + 1) begin
if (sel == i) out = in[i];
end
end
endmodule
| 7.203305
|
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = {in[{sel, 2'b11}], in[{sel, 2'b10}], in[{sel, 2'b01}], in[{sel, 2'b00}]};
endmodule
| 7.203305
|
module top_module (
input [1023:0] in,
input [7:0] sel,
output reg [3:0] out
);
integer i;
always @(*) begin
out = 4'b0000;
for (i = 0; i <= 255; i = i + 1) begin
if (sel == i) out = {in[4*i+3], in[4*i+2], in[4*i+1], in[4*i]};
end
end
endmodule
| 7.203305
|
module top_module (
input a,
b,
output cout,
sum
);
assign cout = a & b;
assign sum = a ^ b;
endmodule
| 7.203305
|
module top_module (
input a,
b,
output cout,
sum
);
assign {cout, sum} = a + b;
endmodule
| 7.203305
|
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.203305
|
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign cout = (a & b) | (a & cin) | (b & cin);
assign sum = a ^ b ^ cin;
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
wire [2:0] new_cin;
assign new_cin = {cout[1:0], cin};
assign cout = (a & b) | (a & new_cin) | (b & new_cin);
assign sum = a ^ b ^ new_cin;
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
genvar i;
generate
begin
for (i = 0; i <= 2; i = i + 1) begin : adder_loop
if (i == 0)
adder1 u_adder1 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(cout[0])
);
else
adder1 u_adder1 (
.a(a[i]),
.b(b[i]),
.cin(cout[i-1]),
.sum(sum[i]),
.cout(cout[i])
);
end
end
endgenerate
endmodule
| 7.203305
|
module adder1 (
input a,
input b,
input cin,
output cout,
output sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.322982
|
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
wire [3:0] cin, cout;
assign cin = {cout[2:0], 1'b0};
assign cout = (x & y) | (x & cin) | (y & cin);
assign sum = {cout[3], x ^ y ^ cin};
endmodule
| 7.203305
|
module user_module_341164910646919762 (
input wire [7:0] io_in,
output wire [7:0] io_out
);
wire clk = io_in[0];
wire output_select = io_in[1];
wire gold_out;
gold_code_module_341164910646919762 gold_code_generator (
.clk(clk),
.loadn(io_in[3]),
.b_load({io_in[7:4], io_in[2:1]}),
.gold(gold_out)
);
wire [7:0] io_out_fibonacci;
wire fib_clk;
wire fib_rstn;
// Buffers to fix slew failures
sky130_fd_sc_hd__buf_2 fib_clk_buf (
.A(clk),
.X(fib_clk),
.VPWR(1'b1),
.VGND(1'b0)
);
sky130_fd_sc_hd__buf_2 fib_rstn_buf (
.A(io_in[2]),
.X(fib_rstn),
.VPWR(1'b1),
.VGND(1'b0)
);
fibonacci_module_341164910646919762 #(
.DIGITS(7)
) fibonacci_inst (
.clk(fib_clk),
.rstn(fib_rstn),
.io_out(io_out_fibonacci)
);
assign io_out[7] = output_select ? gold_out : io_out_fibonacci[7];
assign io_out[6:0] = io_out_fibonacci[6:0];
endmodule
| 6.857392
|
module_341164910646919762
module gold_code_module_341164910646919762
(
input wire clk,
input wire loadn,
input wire [5:0] b_load,
output wire gold
);
reg [12:0] a;
reg [6:0] b_async;
reg [5:0] b_sync;
wire [12:0] b = {b_async, b_sync};
always @(posedge clk or negedge loadn) begin
a <= {a[0] ^ a[1] ^ a[3] ^ a[4], a[12:1]};
b_async <= {b[0] ^ b[4] ^ b[5] ^ b[7] ^ b[9] ^ b[10], b[12:7]};
if (!loadn) begin
a <= {1'b1, 12'b0};
b_async <= {1'b0, 1'b1, 5'b0};
end
end
always @(posedge clk) b_sync <= loadn ? b[6:1] : b_load;
assign gold = a[0] ^ b[0];
endmodule
| 7.129824
|
module_341164910646919762
module fibonacci_module_341164910646919762
#(
parameter DIGITS = 7
)
(
input wire clk,
input wire rstn,
output wire [7:0] io_out
);
wire [3:0] digit;
wire lsb_marker;
fibonacci_341164910646919762 #(.DIGITS(DIGITS)) fib
(.clk(clk), .rstn(rstn), .digit(digit),
.lsb_marker(lsb_marker));
wire [7:0] seven_segment_out;
seven_segment_341164910646919762 seven_segment_encoder
(.digit(digit), .dot(lsb_marker), .seven_segment(seven_segment_out));
assign io_out = clk ? seven_segment_out : 8'b0;
endmodule
| 7.129824
|
module_341164910646919762
module fibonacci_341164910646919762
#(
parameter DIGITS = 7
)
(
input wire clk,
input wire rstn,
output wire [3:0] digit,
output wire lsb_marker
);
localparam WIDTH = 4 * DIGITS;
reg [WIDTH-1:0] a;
assign digit = a[3:0];
reg [WIDTH-1:0] b;
reg carry;
wire [3:0] digit_sum;
wire cout;
reg [DIGITS-1:0] lsb_control;
wire lsb_marker_prev;
assign lsb_marker_prev = lsb_control[DIGITS-1];
assign lsb_marker = lsb_control[0];
adder4_341164910646919762 adder
(.a(a[3:0]), .b(b[3:0]), .cin(carry),
.sum(digit_sum), .cout(cout));
always @(posedge clk or negedge rstn) begin
a <= {b[3:0], a[WIDTH-1:4]};
b <= {digit_sum, b[WIDTH-1:4]};
carry <= lsb_marker_prev ? 1'b0 : cout;
lsb_control <= {lsb_control[DIGITS-2:0], lsb_control[DIGITS-1]};
if (!rstn) begin
a <= 1'b0;
b <= 1'b1;
carry <= 1'b0;
lsb_control <= 1'b1;
end
end
endmodule
| 7.129824
|
module adder4_341164910646919762 (
input wire [3:0] a,
input wire [3:0] b,
input wire cin,
output wire [3:0] sum,
output wire cout
);
wire [3:0] adder_cin;
wire [3:0] adder_cout;
assign cout = adder_cout[3];
assign adder_cin = {adder_cout[2:0], cin};
sky130_fd_sc_hd__fa_1 adder[3:0] (
.A(a),
.B(b),
.CIN(adder_cin),
.COUT(adder_cout),
.SUM(sum),
.VPWR(1'b1),
.VGND(1'b0)
);
endmodule
| 7.315542
|
module constants;
wire [2:0] a;
wire [3:0] b;
wire [4:0] c;
assign a = 3'b000; // The three bits of `a` are set to 0.
assign b = 4'hc; // `b` is set to 12, thus `b == 4'b1100`
assign c = 5'd13; // `c` is set to 13, thus `c == 5'b01101`
wire d;
wire [4:0] e;
assign d = |(b & 4'b0011); // `d` is here equal to 0
assign e = {(5) {1'b1}} ^ c; // `e` is here equal to 5'b10010
endmodule
| 6.857409
|
module constants_underscore;
wire [7:0] a;
wire [7:0] b;
wire same;
assign a = 8'b00010111;
assign b = 8'b0001_0111;
assign same = a == b; // `same` is here equal to 1
endmodule
| 7.113009
|
module shake_hand_recv (
clk,
rst_n,
ready,
din,
dout,
ack
);
input clk, rst_n;
input ready;
input [7:0] din;
output reg [7:0] dout;
output reg ack;
reg ready_d1, ready_d2;
parameter idle = 2'b00, recv = 2'b01, active = 2'b10, reset = 2'b11;
reg [1:0] state, next_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ready_d1 <= 1'b0;
ready_d2 <= 1'b0;
end else begin
ready_d1 <= ready;
ready_d2 <= ready_d1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dout <= 8'd0;
ack <= 1'b0;
state <= idle;
end else begin
case (state)
idle: begin
ack <= 1'b0;
state <= recv;
end
recv: begin
ack <= 1'b1;
state <= active;
end
active: begin
if (ready_d2 == 1'b1) begin
ack <= 1'b0;
dout <= din;
state <= reset;
end else state <= active;
end
reset: begin
if (ready_d2 == 1'b0) begin
state <= recv;
end else state <= reset;
end
default: state <= idle;
endcase
end
end
endmodule
| 6.719216
|
module shake_hand_recv_tb ();
reg clk, rst_n;
reg ready;
reg [7:0] din;
wire [7:0] dout;
wire ack;
initial begin
clk = 0;
rst_n = 1;
ready = 0;
din = 8'd0;
#10 rst_n = 0;
#10 rst_n = 1;
#10 din = 7'b1010_1010;
ready = 1;
#10 din = 8'd0;
#10 ready = 0;
end
always #2 clk <= ~clk;
shake_hand_recv dut (
.clk (clk),
.rst_n(rst_n),
.din (din),
.ready(ready),
.dout (dout),
.ack (ack)
);
endmodule
| 6.719216
|
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = (state[A] & (~in)) | (state[C] & (~in));
assign next_state[B] = in & (state[A] | state[B] | state[D]);
assign next_state[C] = (state[B] & (~in)) | (state[D] & (~in));
assign next_state[D] = in & state[C];
// Output logic:
assign out = state[D];
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack
);
parameter IDLE = 0, SEQ_0 = 1, SEQ_1 = 2, SEQ_2 = 3;
parameter SHIFT = 4, COUNT = 5, DONE = 6;
reg [2:0] cstate, nstate;
reg shift_end;
reg count_end;
reg shift_ena;
reg [2:0] shift_cnt;
reg [3:0] o_count;
reg [9:0] count_cnt;
assign count = o_count;
always @(posedge clk) begin
if (reset) begin
cstate <= IDLE;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
IDLE: nstate = data ? SEQ_0 : IDLE;
SEQ_0: nstate = data ? SEQ_1 : IDLE;
SEQ_1: nstate = data ? SEQ_1 : SEQ_2;
SEQ_2: nstate = data ? SHIFT : IDLE;
SHIFT: nstate = shift_end ? COUNT : SHIFT;
COUNT: nstate = count_end ? DONE : COUNT;
DONE: nstate = ack ? IDLE : DONE;
endcase
end
always @(posedge clk) begin
if (reset) begin
shift_cnt <= 3'b000;
shift_end <= 0;
end else begin
if (shift_ena) begin
if (shift_cnt == 2) begin
shift_end <= 1;
end else begin
shift_cnt <= shift_cnt + 1;
end
end else begin
shift_end <= 0;
shift_cnt <= 3'b000;
end
end
end
always @(posedge clk) begin
if (reset) begin
o_count <= 4'b000;
count_cnt <= 10'b0;
count_end <= 0;
end else begin
if (shift_ena) begin
o_count <= {o_count[2:0], data};
end else begin
if (counting) begin
if (count_cnt == 999 - 1 && o_count == 0) begin
count_end <= 1;
end else begin
if (count_cnt == 999) begin
count_cnt <= 10'b0;
o_count <= o_count - 1;
end else begin
count_cnt <= count_cnt + 1;
end
end
end else begin
count_cnt <= 10'b0;
count_end <= 0;
end
end
end
end
assign shift_ena = (cstate == SHIFT);
assign counting = (cstate == COUNT);
assign done = (cstate == DONE);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = ~(a | b); //NOR gate using bitwise OR and NOT operators
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = ~(a || b);
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
wire and1 = p2a && p2b;
wire and2 = p2c && p2d;
assign p2y = and1 || and2;
wire and3 = p1a && p1c && p1b;
wire and4 = p1f && p1e && p1d;
assign p1y = and3 || and4;
endmodule
| 7.203305
|
module ex0701;
reg clk, reset, x;
wire m1, m2;
mealy mealy1 (
m1,
x,
clk,
reset
);
moore moore1 (
m2,
x,
clk,
reset
);
initial begin
$display("Time X Mealy Moore");
//initial values
clk = 1;
reset = 0;
x = 0;
//input signal changing
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#20 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#30 $finish;
end // initial
always #5 clk = ~clk;
always @(posedge clk) begin
$display("%4d %4b %4b %5b", $time, x, m1, m2);
end // always at positive edge clocking changing
endmodule
| 7.064091
|
module top_module (
input signed [7:0] a,
input signed [7:0] b,
output signed [7:0] s,
output overflow
);
assign s = a + b;
assign overflow = (a[7] & b[7] & ~s[7]) | (~a[7] & ~b[7] & s[7]);
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
// assign s = ...
// assign overflow = ...
assign s = a + b;
assign overflow = (a[7] == b[7] && s[7] != a[7]) ? 1 : 0;
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire [3:0] cout_fadd;
bcd_fadd bcd_fadd_u0[3:0] (
.a(a),
.b(b),
.cin({cout_fadd[2:0], cin}),
.cout(cout_fadd),
.sum(sum)
);
assign cout = cout_fadd[3];
endmodule
| 7.203305
|
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