code
stringlengths 35
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| score
float64 6.5
11.5
|
|---|---|
module top_module (
input clk,
input x,
output reg z
);
reg q1;
reg q2;
reg q3;
initial z = 1;
always @(posedge clk) begin
q1 = x ^ q1;
q2 = x & (~q2);
q3 = x | (~q3);
z = ~(q1 | q2 | q3);
end
endmodule
| 7.203305
|
module wren6991_whisk_tt2_io_wrapper (
input wire [7:0] io_in,
output wire [7:0] io_out
);
// Global signals
wire io_clk = io_in[0];
wire io_rst_n = io_in[1];
// SPI memory interface
wire io_mem_sdi = io_in[2];
wire io_mem_csn;
wire io_mem_sck;
wire io_mem_sdo;
assign io_out[0] = io_mem_csn;
assign io_out[1] = io_mem_sck;
assign io_out[2] = io_mem_sdo;
wire io_retime_mem_out = io_in[4];
wire [1:0] io_retime_mem_in = io_in[6:5];
wire io_retime_ioport_out = io_in[7];
// IO port (shift register interface)
wire io_ioport_sdi = io_in[3];
wire io_ioport_sck;
wire io_ioport_sdo;
wire io_ioport_latch_i;
wire io_ioport_latch_o;
assign io_out[3] = io_ioport_sck;
assign io_out[4] = io_ioport_sdo;
assign io_out[5] = io_ioport_latch_i;
assign io_out[6] = io_ioport_latch_o;
// Be a good neighbour
assign io_out[7] = 1'b0;
whisk_top top_u (
.io_clk (io_clk),
.io_rst_n(io_rst_n),
.io_mem_sdi(io_mem_sdi),
.io_mem_csn(io_mem_csn),
.io_mem_sck(io_mem_sck),
.io_mem_sdo(io_mem_sdo),
.io_retime_mem_out (io_retime_mem_out),
.io_retime_mem_in (io_retime_mem_in),
.io_retime_ioport_out(io_retime_mem_out),
.io_ioport_sdi (io_ioport_sdi),
.io_ioport_sck (io_ioport_sck),
.io_ioport_sdo (io_ioport_sdo),
.io_ioport_latch_i(io_ioport_latch_i),
.io_ioport_latch_o(io_ioport_latch_o)
);
endmodule
| 8.058249
|
module whisk_top (
input wire io_clk,
input wire io_rst_n,
input wire io_mem_sdi,
output wire io_mem_csn,
output wire io_mem_sck,
output wire io_mem_sdo,
input wire io_retime_mem_out,
input wire [1:0] io_retime_mem_in,
input wire io_retime_ioport_out,
input wire io_ioport_sdi,
output wire io_ioport_sck,
output wire io_ioport_sdo,
output wire io_ioport_latch_i,
output wire io_ioport_latch_o
);
// ----------------------------------------------------------------------------
// Clock/reset wrangling
// Don't buffer the clock -- seems like the scripts define a clock on io_in[0]?
wire clk = io_clk;
// Synchronise reset removal to clk
reg [1:0] reset_sync;
wire rst_n = reset_sync[1];
always @(posedge clk or negedge io_rst_n) begin
if (!io_rst_n) begin
reset_sync <= 2'd00;
end else begin
reset_sync <= ~(~reset_sync << 1);
end
end
// ----------------------------------------------------------------------------
// Processor instantiation
wire mem_sck_en_next;
wire mem_sdo_next;
wire mem_csn_next;
wire mem_sdi_prev;
wire ioport_sck_en_next;
wire ioport_sdo_next;
wire ioport_sdi_prev;
wire ioport_latch_i_next;
wire ioport_latch_o_next;
whisk_cpu cpu (
.clk (clk),
.rst_n(rst_n),
.mem_sck_en_next(mem_sck_en_next),
.mem_sdo_next (mem_sdo_next),
.mem_csn_next (mem_csn_next),
.mem_sdi_prev (mem_sdi_prev),
.ioport_sck_en_next (ioport_sck_en_next),
.ioport_sdo_next (ioport_sdo_next),
.ioport_sdi_prev (ioport_sdi_prev),
.ioport_latch_i_next(ioport_latch_i_next),
.ioport_latch_o_next(ioport_latch_o_next)
);
// ----------------------------------------------------------------------------
// Serdes (IO registers)
whisk_spi_serdes mem_serdes_u (
.clk (clk),
.rst_n(rst_n),
.sdo (mem_sdo_next),
.sck_en(mem_sck_en_next),
.csn (mem_csn_next),
.sdi (mem_sdi_prev),
.padout_sck(io_mem_sck),
.padout_csn(io_mem_csn),
.padout_sdo(io_mem_sdo),
.padin_sdi (io_mem_sdi),
.padin_retime_mem_out(io_retime_mem_out),
.padin_retime_mem_in (io_retime_mem_in),
);
whisk_ioport_serdes io_serdes_u (
.clk (clk),
.rst_n(rst_n),
.sdo (ioport_sdo_next),
.sck_en (ioport_sck_en_next),
.latch_i(ioport_latch_i_next),
.latch_o(ioport_latch_o_next),
.sdi (ioport_sdi_prev),
.padout_sdo (io_ioport_sdo),
.padout_sck (io_ioport_sck),
.padout_latch_i(io_ioport_latch_i),
.padout_latch_o(io_ioport_latch_o),
.padin_sdi (io_ioport_sdi),
.padin_retime_ioport_out(io_retime_ioport_out)
);
endmodule
| 8.83903
|
module whisk_regfile #(
parameter W = 16,
parameter N = 6
) (
input wire clk,
input wire [$clog2(N)-1:0] rd,
output wire rd_q,
input wire rd_wen,
input wire rd_d,
input wire [$clog2(N)-1:0] rs,
output wire rs_q,
output wire rs_q_next,
input wire [$clog2(N)-1:0] rt,
output wire rt_q,
);
localparam N_PADDED = 1 << $clog2(N);
wire [N-1:0] d;
wire [N-1:0] d;
wire [W-1:0] q [N_PADDED-1:0];
assign rd_q = q[rd][0];
assign rs_q = q[rs][0];
assign rs_q_next = q[rs][1];
assign rt_q = q[rt][0];
genvar g;
generate
for (g = 0; g < N_PADDED; g = g + 1) begin: loop_gprs
if (g >= N) begin: gpr_tieoff
assign q[g] = {W{1'b0}};
end else begin: gpr_shifter
// Recirculate unless register is addressed as rd.
wire qr;
assign d[g] = rd_wen && rd == g ? rd_d : qr;
whisk_shiftreg_right #(
.W (W)
) reg_u (
.clk (clk),
.dl (d[g]),
.qr (qr),
.q_all (q[g])
);
end
end
endgenerate
endmodule
| 6.525576
|
module whisk_shiftreg_leftright #(
parameter W = 16
) (
input wire clk,
input wire l_nr,
input wire dl,
input wire dr,
output wire ql,
output wire qr,
output wire [W-1:0] q_all
);
wire [W+1:0] chain_q;
assign chain_q[0] = dr;
assign chain_q[W+1] = dl;
assign qr = chain_q[1];
assign ql = chain_q[W];
assign q_all = chain_q[W:1];
genvar g;
generate
for (g = 1; g < W + 1; g = g + 1) begin : shift_stage
// Shift-to-left means select the input to your right, and vice versa.
whisk_flop_scanmux flop_u (
.clk(clk),
.sel(l_nr),
.d ({chain_q[g-1], chain_q[g+1]}),
.q (chain_q[g])
);
end
endgenerate
endmodule
| 8.92904
|
module whisk_shiftreg_right #(
parameter W = 16
) (
input wire clk,
input wire dl,
output wire qr,
output reg [W-1:0] q_all
);
always @(posedge clk) begin
q_all <= {dl, q_all[W-1:1]};
end
assign qr = q_all[0];
endmodule
| 8.92904
|
module top_module (
input clk,
input j,
input k,
output Q
);
always @(posedge clk) begin
case ({
j, k
})
2'b00: Q <= Q;
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= ~Q;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input j,
input k,
output Q
);
always @(posedge clk) begin
case ({
j, k
})
2'b00: Q <= Q;
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= ~Q;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input j,
input k,
output reg Q
);
always @(posedge clk) begin
case ({
j, k
})
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= ~Q;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] in_temp;
integer i;
always @(posedge clk) begin
in_temp <= in;
for (i = 0; i < 8; i++) begin
if ((in_temp[i] == 0) & (in[i] == 1)) pedge[i] <= 1;
else pedge[i] <= 0;
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] shift_in;
always @(posedge clk) begin
shift_in <= in;
end
always @(posedge clk) begin
pedge <= (in ^ shift_in) & in;
end
endmodule
| 7.203305
|
module top_module(
// input clk,
// input [7:0] in,
// output reg [7:0] pedge);
// reg [7:0] d_last;
// always @(posedge clk) begin
// d_last <= in; // Remember the state of the previous cycle
// pedge <= in & ~d_last; // A positive edge occurred if input was 0 and is now 1.
// end
// endmodule
| 8.298556
|
module top_module (
input clk,
input [7:0] in,
output reg [7:0] pedge
);
reg [7:0] in_last;
always @(posedge clk) begin
in_last <= in;
pedge <= (~in_last) & in;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] in_last;
always @(posedge clk) begin
in_last <= in;
anyedge <= in ^ in_last;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
reg [7:0] in_dly;
always @(posedge clk) begin
in_dly <= in;
anyedge <= in ^ in_dly;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
reg [7:0] in_last;
always @(posedge clk) begin
in_last <= in;
anyedge <= in_last ^ in;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] in_last; //the input in last clk
always @(posedge clk) begin
in_last <= in;
if (reset) out <= 0;
else begin
out <= out | (in_last & ~in);
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] in_dly;
always @(posedge clk) begin
in_dly <= in;
end
always @(posedge clk) begin
if (reset) out <= 32'd0;
else if (~in & in_dly) out <= ~in & in_dly | out;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
reg [31:0] in_last;
always @(posedge clk) begin
in_last <= in;
if (reset) out <= 0;
else if (in != in_last) out <= in_last & (~in) | out;
end
endmodule
| 7.203305
|
module add_341521390605697619 #(
parameter WIDTH = 8
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [ WIDTH:0] c
);
assign c = a + b;
endmodule
| 8.101373
|
module top_module (
input clk,
input d,
output q
);
reg [1:0] status;
always @(posedge clk) begin
status[0] <= d;
end
always @(negedge clk) begin
status[1] <= d;
end
assign q = (clk) ? status[0] : status[1];
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
output q
);
reg q_pos;
reg q_neg;
always @(posedge clk) begin
q_pos <= d;
end
always @(negedge clk) begin
q_neg <= d;
end
assign q = clk ? q_pos : q_neg;
// 01 00 11 01 00 11 10 d
// 00 00 11 00 00 11 11 pos
// 1 10 01 11 10 01 10 neg
// 10 10 10 10 10 10 10 clk
// 01 00 11 01 00 ..
// 0 10 01 10 10 01 11 goal
endmodule
| 7.203305
|
module top_module(
// input clk,
// input d,
// output q);
// reg p, n;
// // A positive-edge triggered flip-flop
// always @(posedge clk)
// p <= d ^ n;
// // A negative-edge triggered flip-flop
// always @(negedge clk)
// n <= d ^ p;
// // Why does this work?
// // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
// // After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.
// // At each (positive or negative) clock edge, p and n FFs alternately
// // load a value that will cancel out the other and cause the new value of d to remain.
// assign q = p ^ n;
// // Can't synthesize this.
// /*always @(posedge clk, negedge clk) begin
// q <= d;
// end*/
// endmodule
| 8.298556
|
module top_module (
input clk,
input d,
output q
);
reg q0;
reg q1;
assign q = clk ? q0 : q1;
// q: posedge
always @(posedge clk) begin
q0 <= d;
end
// p:negedge
always @(negedge clk) begin
q1 <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
if (reset | (q == 4'b1111)) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0;
else q <= q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else q = q + 1;
end
endmodule
| 7.203305
|
modules both implement the function "if a is 0, copy x to the output, otherwise copy y."
// The two modules have exactly the same behavior, despite their different implementation styles.
//
module mux_struct(
a,
x,
y,
o
);
input a;
input x;
input y;
output o;
assign o = (~a & x) | (a & y);
endmodule
| 8.726371
|
module mux_beh (
a,
x,
y,
o
);
input a;
input x;
input y;
output reg o;
always @(a, x, y) begin
if (a) begin
o = y;
end else begin
o = x;
end
end
endmodule
| 6.796122
|
module.
// In combinational designs, the sensitivity list will *always* contain *all* the variables that
// are used as inputs (i.e. the ones that are not assigned any value) inside of the `always` body.
// The sensitivity list impacts the behavior that is described by the `always` construct. Improperly setting
// the sensitivity list therefore generally causes unwanted and erreneous logic to be deduced.
//
//
// To generate combinational logic, the following *must* also be true:
//
// "ALL VARIABLES SET WITHIN AN ALWAYS BLOCK MUST BE SET IN ALL POSSIBLE EXECUTION PATHS"
//
// In the above example, this property is satisfied because `o` is set to some value no matter what
// the actual values of `a`, `x`, and `y` are.
//
//
// The following example does not satisfy the property and thus corresponds to a non-combinational circuit!
//
module bad_example(
a,
b,
c
);
input a;
input b;
output reg c;
always @(a, b) begin
if (a & b) begin
c = 1'b1; // `c` is only set if `(a & b)` is 1.
end
end
endmodule
| 8.386903
|
module or_1 (
a,
b,
c
);
input a;
input b;
output c;
assign c = a | b;
endmodule
| 7.059688
|
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter A = 4'b0001;
parameter B = 4'b0010;
parameter C = 4'b0100;
parameter D = 4'b1000;
reg [3:0] cstate;
reg [3:0] nstate;
reg o_fr1, o_fr2, o_fr3, o_dfr;
assign fr1 = o_fr1;
assign fr2 = o_fr2;
assign fr3 = o_fr3;
assign dfr = o_dfr;
always @(posedge clk) begin
if (reset) begin
cstate <= A;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (s)
3'b000: nstate = A;
3'b001: nstate = B;
3'b011: nstate = C;
3'b111: nstate = D;
endcase
end
always @(posedge clk) begin
if (reset) begin
o_fr1 <= 1;
o_fr2 <= 1;
o_fr3 <= 1;
o_dfr <= 1;
end else begin
case (nstate)
A: begin
o_fr1 <= 1;
o_fr2 <= 1;
o_fr3 <= 1;
o_dfr <= 1;
end
B: begin
o_fr1 <= 1;
o_fr2 <= 1;
o_fr3 <= 0;
if (cstate == C || cstate == D) o_dfr <= 1;
else if (cstate == A) o_dfr <= 0;
end
C: begin
o_fr1 <= 1;
o_fr2 <= 0;
o_fr3 <= 0;
if (cstate == D) o_dfr <= 1;
else if (cstate == A || cstate == B) o_dfr <= 0;
end
D: begin
o_fr1 <= 0;
o_fr2 <= 0;
o_fr3 <= 0;
o_dfr <= 0;
end
endcase
end
end
endmodule
| 7.203305
|
module REG #(
parameter NUM = 16
) (
//INPUT
input clk,
rst,
input [NUM-1 : 0] IN,
//OUTPUT
output reg [NUM-1 : 0] OUT
);
always @(posedge clk or posedge rst) begin
if (rst) begin
OUT <= 0;
end else begin
OUT <= IN;
end
end
endmodule
| 8.670389
|
module top_module (
input a,
b,
sel,
output out
);
assign out = sel ? b : a;
endmodule
| 7.203305
|
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
assign out = ({8{sel}} & a) | ({8{~sel}} & b);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
//For synthesizing hardware, two types of always blocks are relevant:
// Combinational: always @(*)
// Clocked: always @(posedge clk)
//Combinational always blocks are equivalent to assign statements,
// If you explicitly specify the sensitivity list and miss a signal, the synthesized hardware will still behave as though (*) was specified,
//but the simulation will not and not match the hardware's behaviour.
//why is above??
//A note on wire vs. reg: The left-hand-side of an assign statement must be a net type (e.g., wire),
//while the left-hand-side of a procedural assignment (in an always block) must be a variable type (e.g., reg). These types (wire vs. reg) have nothing to do with what hardware is synthesized,
assign out_assign = a && b;
always @(*) begin
out_alwaysblock = a && b;
end
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
);
wire [7:0] int1, int2;
//condition ? if_true : if_false
assign int1 = (a < b) ? a : b;
assign int2 = (int1 < c) ? int1 : c;
assign min = (int2 < d) ? int2 : d;
endmodule
| 7.203305
|
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'd0;
else q <= q + 4'd1;
end
endmodule
| 7.203305
|
module top_module (
input a,
b,
output cout,
sum
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
mod_a instance_1 (
a,
b,
out
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
);
assign out = a & (~b) & (~c) | c | b & (~c);
endmodule
| 7.203305
|
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0
); // Module body starts after module declaration
//Notice that the declaration of a vector places the dimensions before the name of the vector, which is unusual
//compared to C syntax. However, the part select has the dimensions after the vector name as you would expect.
//declaring something "input" or "output" automatically declares it as a wire
assign outv = vec;
assign o0 = vec[0];
assign o1 = vec[1];
assign o2 = vec[2];
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module mux_latch (
input [3:0] data,
input [1:0] valid,
input flag,
output reg valid_data
);
initial begin
valid_data = 1'b0;
end
always @(*) begin
case (valid)
2'b00: begin
if (flag) valid_data = data[0];
else valid_data = 0;
end
2'b01: begin
if (flag) valid_data = data[1];
else valid_data = 0;
end
2'b10: begin
if (flag) valid_data = data[2];
else valid_data = 0;
end
2'b11: begin
if (flag) valid_data = data[3];
else valid_data = 0;
end
default: valid_data = 0;
endcase
end
endmodule
| 6.607052
|
module simple_sync_seq (
clk,
t,
x,
y,
q0,
q1
);
input clk;
input t, x;
output y, q0, q1;
wire q0, t1, q1, notq1;
assign t1 = x ^ q0;
assign y = ~(x & notq1);
t_trigger t_trigger1 (
.clk(clk),
.x (t),
.q (q0)
);
t_trigger t_trigger2 (
.clk(clk),
.x(t1),
.q(q1),
.notq(notq1)
);
endmodule
| 7.529254
|
module here
module full_adder(sum, cout, x, y, cin);
input x, y, cin;
output sum, cout;
assign sum = x^y^cin;
assign cout = (x & y)| (y & cin) | (cin & x);
endmodule
| 7.007263
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
q <= reset ? 0 : q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Asynchronous reset to state B
input in,
output out
); //
parameter A = 0, B = 1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case (state)
A: next_state = (in == 1) ? A : B;
B: next_state = (in == 1) ? B : A;
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if (areset) state <= B;
else state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = (state == B);
endmodule
| 7.203305
|
module top_module (
input a,
b,
output cout,
sum
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
);
assign out = a | b | c;
endmodule
| 7.203305
|
module top_module (
input a,
b,
sel,
output out
);
assign out = sel ? b : a;
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else begin
for (int i = 0; i < $bits(q); i++) begin
if (i == 0) begin
q[i] <= q[i+1] ^ 1'b0;
end else if (i == 511) begin
q[i] <= q[i-1] ^ 1'b0;
end else begin
q[i] <= q[i-1] ^ q[i+1];
end
end
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
always @(posedge clk) begin
if (load) q <= data; // Load the DFFs with a value.
else begin
// At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
// and its right neighbour. Since the operation is the same for every
// bit position, it can be written as a single operation on vectors.
// The shifts are accomplished using part select and concatenation operators.
// left right
// neighbour neighbour
q <= q[511:1] ^ {q[510:0], 1'b0};
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk, posedge areset) begin
if (areset) begin
q <= 0;
end else begin
if (load) begin
q <= data;
end else begin
if (ena) begin
// shift
q <= q >> 1;
end
end
end
end
endmodule
| 7.203305
|
module splitter (
input [31:0] A,
output [ 7:0] O1,
output [ 7:0] O2,
output [ 7:0] O3,
output [ 7:0] O4
);
assign O1 = A[31:24];
assign O2 = A[23:16];
assign O3 = A[15:8];
assign O4 = A[7:0];
endmodule
| 7.230286
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module top_module (
output one
);
// Insert your code here
assign one = 1'b1;
endmodule
| 7.203305
|
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 1'o2;
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output reg walk_left,
output reg walk_right
);
initial begin
walk_left = 1;
walk_right = 0;
end
always @(posedge clk) begin
if (areset) begin
walk_left = 1;
walk_right = 0;
end else begin
if (walk_left) begin
if (bump_left) begin
walk_left = 0;
walk_right = 1;
end
end else begin
if (bump_right) begin
walk_left = 1;
walk_right = 0;
end
end
end
end
endmodule
| 7.203305
|
module top_module (
//designing a 7458 chip
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
wire and3_wire_a, and3_wire_b, and2_wire_c, and2_wire_d;
assign and3_wire_a = p1a && p1b && p1c;
assign and3_wire_b = p1d && p1e && p1f;
assign and2_wire_c = p2a && p2b;
assign and2_wire_d = p2c && p2d;
assign p1y = and3_wire_a || and3_wire_b;
assign p2y = and2_wire_c || and2_wire_d;
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) begin
out <= out ^ in;
end
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.203305
|
module four_bit_ring_counter (
input clock,
input reset,
output [3:0] q
);
reg [3:0] a;
always @(posedge clock)
if (reset) a = 4'b0001;
else begin
a <= a << 1; // Notice the blocking assignment
a[0] <= a[3];
end
assign q = a;
endmodule
| 6.509172
|
module and2 (
input a,
input b,
output c
);
assign c = a & b;
endmodule
| 8.35921
|
module and2 (
input a,
input b,
output c
);
assign c = a & b;
endmodule
| 8.35921
|
module drive7seg (
input [9:0] SW,
output [7:0] AN,
output CA,
output CB,
output CC,
output CD,
output CE,
output CF,
output CG,
output DP
);
assign CA = SW[0];
assign CB = SW[1];
assign CC = SW[2];
assign CD = SW[3];
assign CE = SW[4];
assign CF = SW[5];
assign CG = SW[6];
assign DP = SW[7];
assign AN[7:2] = 6'b0;
assign AN[1] = SW[8];
assign AN[0] = SW[9];
endmodule
| 6.563067
|
modules for Lab 6.
// Reminder, the idea is that your design will need to take in
// 2x 4bit numbers, add them together, and then display the
// result of the addition to a 7-segment digit.
`timescale 1ns / 1ps
module drive7seg(
input [7:0] SW,
output [7:0] AN,
output CA,
output CB,
output CC,
output CD,
output CE,
output CF,
output CG,
output DP
);
wire a0, a1, a2, a3, b0, b1, b2, b3;
assign a0=SW[0];
assign a1=SW[1];
assign a2=SW[2];
assign a3=SW[3];
assign b0=SW[4];
assign b1=SW[5];
assign b2=SW[6];
assign b3=SW[7];
wire s3,s2,s1,s0, c_in, c_out;
add_4_bits fa(a3,a2,a1,a0, b3,b2,b1,b0, c_in, c_out, s3,s2,s1,s0);
wire da,db,dc,dd,de,df,dg;
generate_7seg_bits gen1(s3,s2,s1,s0, da,db,dc,dd,de,df,dg);
//connect driver bits to the 7-seg LEDs
// reminder, 7seg leds are active LOW
assign CA=da;
assign CB=db;
assign CC=dc;
assign CD=dd;
assign CE=de;
assign CF=df;
assign CG=dg;
//Which digit are you driving? only #0, reminder, active LOW
assign AN[7:1]=7'b111_1111;
assign AN[0]=1'b0;
endmodule
| 6.707447
|
module from previous class discussion
// https://github.com/ntmoore/phys332_fall21/blob/main/10-13-2bit-adder.v
module fulladder(
input a,
input b,
input c_in,
output c_out,
output sum
);
assign c_out = (a & b) | (a & c_in) | (b & c_in);
assign sum = (~a & ~b & c) | (~a & b & ~c) | (a & b & c) | (a & ~b & ~c);
endmodule
| 7.772401
|
module add_4_bits (
input a3,
input a2,
input a1,
input a0,
input b3,
input b2,
input b1,
input b0,
input c_in,
output c_out,
output s3,
output s2,
output s1,
output s0
);
endmodule
| 6.812817
|
module implement_clocks (
input CLK100MHZ,
output [7:8] JA,
output [1:0] LED
);
wire CLK_100HZ;
// the brigntnesses on these two pins should differ
assign LED[0] = 1'b1;
assign LED[1] = CLK_100HZ;
// sending oth clocks to the PMOD pins on the lower JA header
assign JA[7] = CLK_100MHZ;
assign JA[8] = CLK_100HZ;
create_100HZ_clock gate0 (
CLK100MHZ,
CLK_100HZ
);
endmodule
| 6.959204
|
module test_two_bit_adder (
input [3:0] SW,
output [2:0] LED
);
two_bit_adder add_2 (
SW[3:2],
SW[1:0],
LED[2:0]
);
endmodule
| 8.002488
|
module two_bit_adder (
input [1:0] a,
input [1:0] b,
output [2:0] sum
);
wire a1, a0, b1, b0;
assign a[1] = a1;
assign a[0] = a0;
assign b[1] = b1;
assign b[0] = b0;
wire s1, s0, cout;
assign sum[2] = cout;
assign sum[1] = s1;
assign sum[0] = s0;
wire c_mid; // intermedite wire
fulladder add0 (
a0,
b0,
0,
c_mid,
s0
);
fulladder add1 (
a1,
b1,
c_mid,
cout,
s1
);
endmodule
| 6.650749
|
module fulladder (
input a,
input b,
input c_in,
output c_out,
output sum
);
assign c_out = (a & b) | (a & c_in) | (b & c_in);
assign sum = (~a & ~b & c_in) | (~a & b & ~c_in) | (a & b & c_in) | (a & ~b & ~c_in);
endmodule
| 7.454465
|
module you'd like to test look like? See below
// for a top-level modeule that serves to send signals to a 7-segment display driver (partically finished).
//
// This is a possible way to organize the modules for Lab 6.
// Reminder, the idea is that your design will need to take in
// 2x 4bit numbers, add them together, and then display the
// result of the addition to a 7-segment digit.
`timescale 1ns / 1ps
module test_7seg(
input [3:0] SW,
output [7:0] AN,
output CA,
output CB,
output CC,
output CD,
output CE,
output CF,
output CG,
output DP,
output [3:0] LED // for debugging
);
// input 4-bit numbers to be added
wire n3,n2,n1,n0;
assign n0=SW[0];
assign n1=SW[1];
assign n2=SW[2];
assign n3=SW[3];
assign LED[3:0]=SW[3:0]; //debug
assign DP=1'b1; // active low, turn off
wire da,db,dc,dd,de,df,dg;
generate_7seg_bits gen1(n3,n2,n1,n0, da,db,dc,dd,de,df,dg);
//connect driver bits to the 7-seg LEDs
// reminder, 7seg leds are active LOW
assign CA=~da;
assign CB=~db;
assign CC=~dc;
assign CD=~dd;
assign CE=~de;
assign CF=~df;
assign CG=~dg;
//Which digit are you driving? only #0, reminder, active LOW
assign AN[7:1]=7'b111_1111;
assign AN[0]=1'b0;
endmodule
| 7.275539
|
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) begin
out <= in ^ out;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right
); //
// parameter LEFT=0, RIGHT=1, ...
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
0: next_state = bump_left ? 1 : 0;
1: next_state = bump_right ? 0 : 1;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= 0;
else begin
state <= next_state;
end
end
// Output logic
assign walk_left = (state == 0);
assign walk_right = (state == 1);
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
assign p2y = (p2a & p2b) | (p2c & p2d);
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
reg [7:0] temp;
initial begin
temp = 'h00;
end
always @(posedge clk) begin
temp <= in;
anyedge <= temp ^ in;
end
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
wire cc[100:0];
always @(*) begin
cc[0] = cin;
for (int i = 0; i < 100; i = i + 1) begin
sum[i] = a[i] ^ b[i] ^ cc[i];
cc[i+1] = (a[i] & b[i]) | ((a[i] | b[i]) & cc[i]);
end
end
assign cout = cc[100];
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
assign sum[0] = a[0] ^ b[0] ^ cin;
assign cout[0] = a[0] & b[0] | a[0] & cin | b[0] & cin;
always @(*) begin
for (int i = 1; i <= 99; i++) begin
cout[i] = a[i] & b[i] | a[i] & cout[i-1] | b[i] & cout[i-1];
sum[i] = a[i] ^ b[i] ^ cout[i-1];
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
if (reset | (q == 4'b1001)) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305
|
module clean_rst (
input clk,
input rsti,
output reg rsto
);
reg rstt;
always @(posedge clk, posedge rsti) begin
rstt <= (rsti) ? 1 : 0;
rsto <= (rsti) ? 1 : rstt;
end
endmodule
| 6.743082
|
module fulladder (
a,
b,
cin,
sum,
cout
); //module最后需要加;
input a, b, cin;
output sum, cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 7.454465
|
module 100bits_adder(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
integer i;
assign cout[0]=(a[0]&b[0])|(a[0]&cin)|(b[0]&cin);
assign sum[0] =a[0]^b[0]^cin;
always @(*)
begin
for(i=1;i<100;i++)
begin
cout[i] = (a[i]&b[i])|(a[i]&cout[i-1])|(b[i]&cout[i-1]);
sum[i]=a[i]^b[i]^cout[i-1];
end
end
endmodule
| 6.685577
|
module 100bits_adder(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
fulladder adder0 (a[0],b[0],cin,sum[0],cout[0]);
genvar i;
generate
for(i=1;i<100;i++)
begin: adder //for begin之后需要写名字
fulladder adder1(a[i],b[i],cout[i-1],sum[i],cout[i]);
end
endgenerate //利用generate-for语句来循环例化子模块，compile的时候会把所有例化的子模块展开。
//gengrate使用时需要先定义genvar，使用for循环时需要为for循环取名，写在begin后面！！！
endmodule
| 6.685577
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (~(ue[0] || (ue[3] && load)));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = '0;
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = '1;
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module adc (
rst,
comp,
out,
data,
clk
);
reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0;
wire [12:0] \$1 ;
wire [12:0] \$2 ;
wire [12:0] \$4 ;
wire [12:0] \$5 ;
input clk;
wire clk;
input comp;
wire comp;
wire [11:0] dac_data;
wire dac_out;
output [11:0] data;
reg [11:0] data = 12'h000;
reg [11:0] \data$next ;
output out;
wire out;
input rst;
wire rst;
assign \$2 = data - 1'h1;
assign \$5 = data + 1'h1;
always @(posedge clk) data <= \data$next ;
dac dac (
.clk (clk),
.data(dac_data),
.out (dac_out),
.rst (rst)
);
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin
end
(* full_case = 32'd1 *)
casez (comp)
1'h1: \data$next = \$2 [11:0];
default: \data$next = \$5 [11:0];
endcase
casez (rst)
1'h1: \data$next = 12'h000;
endcase
end
assign \$1 = \$2 ;
assign \$4 = \$5 ;
assign dac_data = data;
assign out = dac_out;
endmodule
| 6.819663
|
module adc_uart (
rst,
tx_o,
data,
ready,
valid,
clk
);
reg \$auto$verilog_backend.cc:2083:dump_module$3 = 0;
wire \$1 ;
wire [8:0] \$10 ;
wire [7:0] \$3 ;
wire [6:0] \$4 ;
wire [8:0] \$7 ;
wire [7:0] \$8 ;
input clk;
wire clk;
input [11:0] data;
wire [11:0] data;
reg [11:0] data_reg = 12'h000;
reg [11:0] \data_reg$next ;
reg [ 2:0] fsm_state = 3'h0;
reg [ 2:0] \fsm_state$next ;
reg [ 3:0] nibble;
output ready;
reg ready;
input rst;
wire rst;
output tx_o;
wire tx_o;
reg [7:0] uart_data;
wire uart_ready;
wire uart_tx_o;
reg uart_valid;
input valid;
wire valid;
assign \$10 = \$8 - 4'ha;
always @(posedge clk) data_reg <= \data_reg$next ;
always @(posedge clk) fsm_state <= \fsm_state$next ;
assign \$1 = nibble < 4'ha;
assign \$4 = nibble + 6'h30;
assign \$3 = +\$4 ;
assign \$8 = nibble + 7'h41;
uart uart (
.clk (clk),
.data (uart_data),
.ready(uart_ready),
.rst (rst),
.tx_o (uart_tx_o),
.valid(uart_valid)
);
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin
end
(* full_case = 32'd1 *)
casez (\$1 )
1'h1: uart_data = \$3 ;
default: uart_data = \$10 [7:0];
endcase
casez (fsm_state)
3'h0:
/* empty */;
3'h1:
/* empty */;
3'h2:
/* empty */;
3'h3:
/* empty */;
3'h4: uart_data = 8'h0a;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin
end
ready = 1'h0;
casez (fsm_state)
3'h0: ready = uart_ready;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin
end
\data_reg$next = data_reg;
casez (fsm_state)
3'h0: \data_reg$next = data;
endcase
casez (rst)
1'h1: \data_reg$next = 12'h000;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin
end
\fsm_state$next = fsm_state;
casez (fsm_state)
3'h0:
casez (valid)
1'h1: \fsm_state$next = 3'h1;
endcase
3'h1:
casez (uart_ready)
1'h1: \fsm_state$next = 3'h2;
endcase
3'h2:
casez (uart_ready)
1'h1: \fsm_state$next = 3'h3;
endcase
3'h3:
casez (uart_ready)
1'h1: \fsm_state$next = 3'h4;
endcase
3'h4:
casez (uart_ready)
1'h1: \fsm_state$next = 3'h0;
endcase
endcase
casez (rst)
1'h1: \fsm_state$next = 3'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin
end
nibble = 4'h0;
casez (fsm_state)
3'h0:
/* empty */;
3'h1: nibble = data_reg[11:8];
3'h2: nibble = data_reg[7:4];
3'h3: nibble = data_reg[3:0];
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin
end
uart_valid = 1'h0;
casez (fsm_state)
3'h0:
/* empty */;
3'h1: uart_valid = 1'h1;
3'h2: uart_valid = 1'h1;
3'h3: uart_valid = 1'h1;
3'h4: uart_valid = 1'h1;
endcase
end
assign \$7 = \$10 ;
assign tx_o = uart_tx_o;
endmodule
| 7.011497
|
module 100_bits_BCD_adder(a,b,cin,cout,sum);
input [99:0]a;
input [99:0]b;
input cin;
output cout;
output [99:0]sum;
wire [99:0] carry;
bcd_fadd fadd1 (a[3:0],b[3:0],cin,carry[0],sum[3:0]);
genvar i;
generate
for (i=1;i<100;i++)
begin:bcd_fadd
bcd_fadd fadd2 (a[4*i+3:4*i],b[4*i+3:4*i],carry[i-1],carry[i],sum[4*i+3:4*i]);
end
endgenerate
assign cout = carry[99];
endmodule
| 6.687264
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0;
else if (q >= 4'd9) q <= 4'b0;
else q <= q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (q == 9) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output [3:0] q
);
initial q <= 1;
always @(posedge clk) begin
if (reset | (q == 10)) q <= 1;
else q <= q + 1;
end
endmodule
| 7.203305
|
module seq_det (
input x,
clk,
rst,
output y
);
parameter idle = 3'b000, s1 = 3'b001, s10 = 3'b010, s101 = 3'b011, s1010 = 3'b100;
reg [2:0] state, next_state;
always @(*) begin
case (state)
idle : next_state = x ? s1 : idle ;
s1 : next_state = x ? s1 : s10 ;
s10 : next_state = x ? s101 : idle ;
s101 : next_state = x ? s1 : s1010 ;
s1010: next_state = x ? s101 : idle ;
default : next_state = idle;
endcase
end
always @(posedge clk) begin
if (rst) state <= idle;
else begin
state <= next_state;
end
end
assign y = (state == s1010);
endmodule
| 8.25521
|
module seq_det2 (
input x,
clk,
rst,
output y
);
parameter idle = 3'b000, s1 = 3'b001, s10 = 3'b010, s101 = 3'b011;
reg [1:0] state, next_state;
always @(*) begin
case (state)
idle : next_state = x ? s1 : idle ;
s1 : next_state = x ? s1 : s10 ;
s10 : next_state = x ? s101 : idle ;
s101 : next_state = x ? s1 : s10 ;
default : next_state = idle;
endcase
end
always @(posedge clk) begin
if (rst) state <= idle;
else begin
state <= next_state;
end
end
assign y = (state == s101) && x;
endmodule
| 6.630976
|
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