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module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a mod_a_u1 (
out1,
out2,
a,
b,
c,
d
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a u_mod_a (
out1,
out2,
a,
b,
c,
d
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a mod_a_u1 (
.in1 (a),
.in2 (b),
.in3 (c),
.in4 (d),
.out1(out1),
.out2(out2)
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a u_mod_a (
.out1(out1),
.out2(out2),
.in1 (a),
.in2 (b),
.in3 (c),
.in4 (d)
);
endmodule
| 7.203305
|
module asic_multiplier_wrapper (
input [7:0] io_in,
output [7:0] io_out
);
// Instantiate the multiplier
asic_multiplier asic_multiplier_top (
.clk (io_in[0]),
.reset (io_in[1]),
.i_factor_a (io_in[4:2]),
.i_factor_b (io_in[7:5]),
.o_segments (io_out[6:0]),
.o_lsb_digit(io_out[7])
);
endmodule
| 6.523357
|
module top_module (
input clk,
input d,
output q
);
wire q1;
wire q2;
my_dff u_my_dff_1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff u_my_dff_2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff u_my_dff_3 (
.clk(clk),
.d (q2),
.q (q)
);
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
output q
);
wire q1;
wire q2;
my_dff my_dff_u1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff my_dff_u2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff my_dff_u3 (
.clk(clk),
.d (q2),
.q (q)
);
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire [7:0] q1, q2, q3;
my_dff8 my_dff8_u1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff8 my_dff8_u2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff8 my_dff8_u3 (
.clk(clk),
.d (q2),
.q (q3)
);
always @(*)
if (sel == 2'b00) q = d;
else if (sel == 2'b01) q = q1;
else if (sel == 2'b10) q = q2;
else if (sel == 2'b11) q = q3;
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output reg [7:0] q
);
wire [7:0] q1;
wire [7:0] q2;
wire [7:0] q3;
my_dff8 u_my_dff8_1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff8 u_my_dff8_2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff8 u_my_dff8_3 (
.clk(clk),
.d (q2),
.q (q3)
);
always @(*) begin
case (sel)
2'b00: q = d;
2'b01: q = q1;
2'b10: q = q2;
2'b11: q = q3;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire [16:0] a_lower = a[15:0];
wire [16:0] a_higher = a[31:16];
wire [16:0] b_lower = b[15:0];
wire [16:0] b_higher = b[31:16];
wire cout1;
wire cout2;
wire [15:0] sum_lower;
wire [15:0] sum_higher;
add16 add16_u1 (
.a(a_lower),
.b(b_lower),
.cin(1'b0),
.cout(cout1),
.sum(sum_lower)
); // lower bit
add16 add16_u2 (
.a(a_higher),
.b(b_higher),
.cin(cout1),
.cout(cout2),
.sum(sum_higher)
); // higher bit
assign sum = {sum_higher, sum_lower};
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout_1;
wire cout_2;
add16 u_add16_1 (
.a(a[15:0]),
.b(b[15:0]),
.cin(1'b0),
.sum(sum[15:0]),
.cout(cout_1)
);
add16 u_add16_2 (
.a(a[31:16]),
.b(b[31:16]),
.cin(cout_1),
.sum(sum[31:16]),
.cout(cout_2)
);
endmodule
| 7.203305
|
module tomkeddie_top_tto_a #(
parameter CLOCK_RATE = 1000
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire uart_tx_pin0;
wire uart_tx_pin1;
wire uart_tx_pin2;
assign io_out[0] = uart_tx_pin0;
assign io_out[1] = uart_tx_pin1;
assign io_out[2] = uart_tx_pin2;
// instatiate lcd
uart_tx uart_tx (
.clk(clk),
.reset(reset),
.tx_pin0(uart_tx_pin0),
.tx_pin1(uart_tx_pin1),
.tx_pin2(uart_tx_pin2)
);
endmodule
| 6.88019
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
); //
wire [16:0] a_lower = a[15:0];
wire [16:0] a_higher = a[31:16];
wire [16:0] b_lower = b[15:0];
wire [16:0] b_higher = b[31:16];
wire cout1;
wire cout2;
wire [15:0] sum_lower;
wire [15:0] sum_higher;
add16 add16_u1 (
.a(a_lower),
.b(b_lower),
.cin(1'b0),
.cout(cout1),
.sum(sum_lower)
); // lower bit
add16 add16_u2 (
.a(a_higher),
.b(b_higher),
.cin(cout1),
.cout(cout2),
.sum(sum_higher)
); // higher bit
assign sum = {sum_higher, sum_lower};
endmodule
| 7.203305
|
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
// Full adder module here
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.640243
|
module mm21_SPIMaster (
input clock,
input reset,
output tx_ready,
input tx_valid,
input [7:0] tx_byte,
// whether or not to reset CS after sending data
input tx_clear_cs,
output sclk,
output mosi,
output n_cs
);
localparam STATE_IDLE = 2'd0, STATE_CS_ASSERT = 2'd1, STATE_TX = 2'd2, STATE_CS_DEASSERT = 2'd3;
localparam TX_COUNTER_MAX = 3'h7;
// number of cycles-1 to wait after asserting / before deasserting CS
localparam CS_COUNTER_MAX = 4'd10;
reg [1:0] state;
reg [7:0] tx_byte_reg;
reg sclk_mask;
reg mosi_mask;
reg tx_ready_reg;
reg [2:0] tx_counter_reg;
reg n_cs_reg;
reg tx_clear_cs_reg;
reg [3:0] cs_delay_counter;
assign tx_ready = tx_ready_reg;
assign sclk = ~clock & sclk_mask;
assign mosi = tx_byte_reg[7] & mosi_mask;
assign n_cs = n_cs_reg;
always @(posedge clock) begin
if (reset) begin
state <= STATE_IDLE;
tx_byte_reg <= 8'h0;
sclk_mask <= 1'b0;
mosi_mask <= 1'b0;
tx_ready_reg <= 1'b0;
tx_counter_reg <= 3'd0;
n_cs_reg <= 1'b1;
tx_clear_cs_reg <= 1'b1;
cs_delay_counter <= 4'd0;
end else begin
if (state == STATE_IDLE) begin
tx_ready_reg <= 1'b1;
if (tx_valid == 1'b1) begin
tx_byte_reg <= tx_byte;
tx_clear_cs_reg <= tx_clear_cs;
tx_ready_reg <= 1'b0;
n_cs_reg <= 1'b0;
if (n_cs_reg == 1'b1) begin
// CS is not asserted: assert it first
state <= STATE_CS_ASSERT;
end else begin
// CS is already asserted: transition to TX
state <= STATE_TX;
sclk_mask <= 1'b1;
mosi_mask <= 1'b1;
end
end
end else if (state == STATE_CS_ASSERT) begin
// assert CS before transitioning to TX
if (cs_delay_counter == CS_COUNTER_MAX) begin
cs_delay_counter <= 4'd0;
state <= STATE_TX;
sclk_mask <= 1'b1;
mosi_mask <= 1'b1;
end else begin
cs_delay_counter <= cs_delay_counter + 4'd1;
end
end else if (state == STATE_TX) begin
tx_byte_reg <= {tx_byte_reg[6:0], 1'b0};
if (tx_counter_reg == TX_COUNTER_MAX) begin
tx_counter_reg <= 3'd0;
sclk_mask <= 1'b0;
mosi_mask <= 1'b0;
// check if CS needs to be reset
if (tx_clear_cs_reg == 1'b1) begin
state <= STATE_CS_DEASSERT;
end else begin
state <= STATE_IDLE;
end
end else begin
tx_counter_reg <= tx_counter_reg + 3'd1;
end
end else if (state == STATE_CS_DEASSERT) begin
// wait before deasserting CS and transitioning to idle
if (cs_delay_counter == CS_COUNTER_MAX) begin
if (n_cs_reg == 1'b0) begin
cs_delay_counter <= 4'd0;
n_cs_reg <= 1'b1;
end else begin
cs_delay_counter <= 4'd0;
state <= STATE_IDLE;
end
end else begin
cs_delay_counter <= cs_delay_counter + 4'd1;
end
end
end
end
endmodule
| 6.983741
|
module mm21_LEDColor (
input [2:0] row_idx,
input [2:0] col_idx,
input [5:0] pixel_offset,
output [7:0] pixel
);
wire [2:0] red;
wire [2:0] green;
wire [1:0] blue;
wire is_diagonal;
wire [5:0] green_sum;
wire [5:0] blue_sum;
assign green_sum = {3'd0, col_idx} + pixel_offset;
assign blue_sum = {3'd0, row_idx} + pixel_offset;
// generate moving diagonal
assign is_diagonal = ((row_idx + col_idx) == pixel_offset[2:0]) ? 1'b1 : 1'b0;
// generate white when on diagonal, otherwise moving blend of green/blue
assign red = (is_diagonal == 1'b1) ? 3'd7 : 3'd0;
assign green = (is_diagonal == 1'b1) ? 3'd7 : green_sum[2:0];
assign blue = (is_diagonal == 1'b1) ? 2'd3 : blue_sum[1:0];
assign pixel = {red, 5'd0} | {3'd0, green, 2'd0} | {6'd0, blue};
endmodule
| 7.158683
|
module mm21_LEDMatrixDriver (
input clock,
input reset,
output sclk,
output mosi,
output n_cs
);
localparam STATE_RESET_FRAME_INDEX = 1'd0, STATE_SEND_PIXELS = 1'd1;
// command to reset frame index
localparam CMD_RESET_FRAME_INDEX = 8'h26;
localparam PIXEL_MAX = 6'h3f;
reg [0:0] state;
reg [1:0] state_rfi;
reg [1:0] state_sp;
reg [5:0] pixel_counter;
reg [5:0] pixel_offset;
reg tx_valid;
reg tx_clear_cs;
wire tx_ready;
wire [7:0] tx_byte;
wire [2:0] row_idx;
wire [2:0] col_idx;
wire [7:0] pixel;
assign tx_byte = (state == STATE_RESET_FRAME_INDEX) ? CMD_RESET_FRAME_INDEX : pixel;
assign row_idx = pixel_counter[5:3];
assign col_idx = pixel_counter[2:0];
mm21_SPIMaster spi_master_inst (
.clock(clock),
.reset(reset),
.tx_ready(tx_ready),
.tx_valid(tx_valid),
.tx_byte(tx_byte),
.tx_clear_cs(tx_clear_cs),
.sclk(sclk),
.mosi(mosi),
.n_cs(n_cs)
);
mm21_LEDColor led_color_inst (
.row_idx(row_idx),
.col_idx(col_idx),
.pixel_offset(pixel_offset),
.pixel(pixel)
);
always @(posedge clock) begin
if (reset) begin
state <= STATE_RESET_FRAME_INDEX;
pixel_counter <= 6'h0;
pixel_offset <= 6'h0;
tx_valid <= 1'b0;
tx_clear_cs <= 1'b0;
end else begin
if (state == STATE_RESET_FRAME_INDEX) begin
if (tx_ready == 1'b1) begin
// send command to reset frame index
tx_valid <= 1'b1;
tx_clear_cs <= 1'b1;
end else if (tx_valid == 1'b1) begin
// TX accepted, transition to next state
state <= STATE_SEND_PIXELS;
tx_valid <= 1'b0;
end
end else if (state == STATE_SEND_PIXELS) begin
if (tx_ready == 1'b1) begin
// send pixel data
tx_valid <= 1'b1;
if (pixel_counter == PIXEL_MAX) begin
// sending last pixel, so clear CS after
tx_clear_cs <= 1'b1;
end else begin
tx_clear_cs <= 1'b0;
end
end else if (tx_valid == 1'b1) begin
// TX accepted, transition to next state
tx_valid <= 1'b0;
if (pixel_counter == PIXEL_MAX) begin
// sending last pixel
state <= STATE_RESET_FRAME_INDEX;
pixel_counter <= 6'h0;
pixel_offset <= pixel_offset + 6'h1;
end else begin
pixel_counter <= pixel_counter + 6'h1;
end
end
end
end
end
endmodule
| 6.718054
|
module mm21_SevenSeg (
input clock,
input reset,
output up,
output right,
output down,
output left
);
localparam COUNTER_MAX = 8'hff;
// counter to increment upon every clock
reg [7:0] counter;
// state to increment upon every counter wrap
reg [1:0] state;
// set outputs using combinational logic based on state
assign up = (state == 2'd0) ? 1'b1 : 1'b0;
assign right = (state == 2'd1) ? 1'b1 : 1'b0;
assign down = (state == 2'd2) ? 1'b1 : 1'b0;
assign left = (state == 2'd3) ? 1'b1 : 1'b0;
always @(posedge clock) begin
if (reset) begin
counter <= 8'h0;
state <= 2'h0;
end else begin
// increment counter upon clock cycle
counter <= counter + 8'd1;
// increment state upon counter wrap
if (counter == COUNTER_MAX) begin
state <= state + 2'd1;
end
end
end
endmodule
| 6.82882
|
module mm21_LEDMatrixTop (
input [7:0] io_in,
output [7:0] io_out
);
wire clock;
wire reset_async;
wire reset_sync;
// LED matrix wires
wire sclk;
wire mosi;
wire n_cs;
// 7-seg wires
wire up;
wire right;
wire down;
wire left;
assign clock = io_in[0];
assign reset_async = io_in[1];
// drive LED matrix
assign io_out[0] = sclk;
assign io_out[1] = mosi;
assign io_out[5] = n_cs;
// use lower 7-seg LEDs for animation
assign io_out[6] = up;
assign io_out[2] = right;
assign io_out[3] = down;
assign io_out[4] = left;
assign io_out[7] = 1'b1;
mm21_AsyncReset async_reset_inst (
.clock(clock),
.reset_async(reset_async),
.reset_sync(reset_sync)
);
mm21_LEDMatrixDriver ledmatrix_driver_inst (
.clock(clock),
.reset(reset_sync),
.sclk(sclk),
.mosi(mosi),
.n_cs(n_cs)
);
mm21_SevenSeg sevenseg_inst (
.clock(clock),
.reset(reset_sync),
.up(up),
.right(right),
.down(down),
.left(left)
);
endmodule
| 6.718054
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
); //
wire cout_1;
wire cout_2;
add16 u_add16_1 (
.a(a[15:0]),
.b(b[15:0]),
.cin(1'b0),
.sum(sum[15:0]),
.cout(cout_1)
);
add16 u_add16_2 (
.a(a[31:16]),
.b(b[31:16]),
.cin(cout_1),
.sum(sum[31:16]),
.cout(cout_2)
);
endmodule
| 7.203305
|
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
// Full adder module heredasdsa
assign {cout, sum} = a + b + cin;
endmodule
| 6.640243
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire [16:0] a_lower = a[15:0];
wire [16:0] a_higher = a[31:16];
wire [16:0] b_lower = b[15:0];
wire [16:0] b_higher = b[31:16];
wire cout1, cout2, cout3;
wire [15:0] sum_lower;
wire [15:0] sum_higher_0;
wire [15:0] sum_higher_1;
wire [15:0] sum_higher;
// lower bit
add16 add16_u1 (
.a(a_lower),
.b(b_lower),
.cin(1'b0),
.cout(cout1),
.sum(sum_lower)
);
// higher bit, carry = 0
add16 add16_u2 (
.a(a_higher),
.b(b_higher),
.cin(1'b0),
.cout(cout2),
.sum(sum_higher_0)
);
// higher bit, carry = 1
add16 add16_u3 (
.a(a_higher),
.b(b_higher),
.cin(1'b1),
.cout(cout3),
.sum(sum_higher_1)
);
assign sum_higher = (cout1 ? sum_higher_1 : sum_higher_0);
assign sum = {sum_higher, sum_lower};
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire select_flag;
wire [15:0] sum_high_0;
wire [15:0] sum_high_1;
add16 u_add16_lo (
.a(a[15:0]),
.b(b[15:0]),
.cin(1'b0),
.sum(sum[15:0]),
.cout(select_flag)
);
add16 u_add16_hi0 (
.a (a[31:16]),
.b (b[31:16]),
.cin(1'b0),
.sum(sum_high_0[15:0])
);
add16 u_add16_hi1 (
.a (a[31:16]),
.b (b[31:16]),
.cin(1'b1),
.sum(sum_high_1[15:0])
);
assign sum[31:16] = select_flag ? sum_high_1 : sum_high_0;
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout1, cout2;
wire [31:0] exc_b;
assign exc_b = sub ? ~b : b; // XOR
add16 add16_u1 (
.a(a[15:0]),
.b(exc_b[15:0]),
.cin(sub),
.sum(sum[15:0]),
.cout(cout1)
);
add16 add16_u2 (
.a(a[31:16]),
.b(exc_b[31:16]),
.cin(cout1),
.sum(sum[31:16]),
.cout(cout2)
);
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] result
);
wire [31:0] c;
wire cout_1;
assign c = sub ? ~b : b;
add16 add16_1 (
.a(a[15:0]),
.b(c[15:0]),
.cin(sub),
.sum(result[15:0]),
.cout(cout_1)
);
add16 add16_2 (
.a (a[31:16]),
.b (c[31:16]),
.cin(cout_1),
.sum(result[31:16])
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
// assign
assign out_assign = a & b;
// always
always @(*) begin
out_alwaysblock = a & b;
end
endmodule
| 7.203305
|
module yubex_egg_timer (
input [7:0] io_in,
output reg [7:0] io_out
);
wire clk;
localparam clk_frequency = 14'd10000; // frequency in Hz
wire rst;
wire start;
assign clk = io_in[0];
assign rst = io_in[1];
assign start = io_in[2];
reg [1:0] state;
localparam idle = 2'b00;
localparam waiting = 2'b01;
localparam alarm = 2'b10;
reg [13:0] clk_cycle_cnt;
reg [ 5:0] second_cnt;
reg [ 4:0] minute_cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= idle;
end else begin
case (state)
idle: begin
if (start == 1'b1) state <= waiting;
else state <= idle;
end
waiting: begin
if (second_cnt == 6'b0 && minute_cnt == 5'b0 && clk_cycle_cnt == 14'b0) state <= alarm;
else state <= waiting;
end
alarm: begin
if (start == 1'b0) state <= idle;
else state <= alarm;
end
default: state <= idle;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
minute_cnt <= 5'b1;
second_cnt <= 6'd59;
clk_cycle_cnt <= clk_frequency - 1;
end else begin
if (state == idle) begin
//load wait time from io_in
minute_cnt <= io_in[7:3] - 1;
second_cnt <= 6'd59;
clk_cycle_cnt <= clk_frequency - 1;
end
if (state == waiting) begin
if (clk_cycle_cnt == 14'b0) begin
clk_cycle_cnt <= clk_frequency - 1;
if (second_cnt == 6'b0) begin
second_cnt <= 6'd59;
if (minute_cnt != 5'b0) begin
minute_cnt <= minute_cnt - 1;
end
end else begin
second_cnt <= second_cnt - 1;
end
end else begin
clk_cycle_cnt <= clk_cycle_cnt - 1;
end
end
end
end
// 7 segment display
always @(posedge clk or posedge rst) begin
if (rst) begin
io_out <= 8'b0;
end else begin
case (state)
idle: begin
io_out <= 8'b01000000;
end
waiting: begin
io_out[6:0] <= 7'b0;
if (clk_cycle_cnt == 14'b0) io_out[7] <= ~io_out[7];
end
alarm: begin
io_out <= 8'b11110111;
end
default: ;
endcase
end
end
endmodule
| 7.569101
|
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
reg [3:0] o_q = 4'b0;
assign q = o_q;
always @(posedge clk) begin
if (shift_ena) begin
o_q <= {o_q[2:0], data};
end else if (count_ena) begin
o_q <= o_q - 1'b1;
end else begin
o_q <= o_q;
end
end
endmodule
| 7.203305
|
module and_gate ( // This module implements a 2-input AND gate
a,
b,
c
);
input a;
input b;
output c;
assign c = a & b; // `c` is driven by `a & b`
endmodule
| 9.274676
|
module and3_gate ( // This module implements a 3-input AND gate
in1,
in2,
in3,
out
);
// input in1;
// input in2;
// input in3;
input in1, in2, in3;
output out;
assign out = in1 & in2 & in3;
endmodule
| 8.910591
|
module nand_gate ( // This module implements a 2-input NAND gate
a,
b,
c
);
input a;
input b;
output c;
assign c = ~(a & b);
endmodule
| 9.287559
|
module two_of_three ( // The output of this module is 1 iff 2 of its inputs are equal to 1.
a,
b,
c,
out
);
input a;
input b;
input c;
output out;
assign out = (a & (b ^ c)) | (~a & b & c);
endmodule
| 7.244658
|
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A = 0 ;
parameter B = 1 ;
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
// Fill in reset logic
present_state <= B ;
out <= 1 ;
end else begin
case (present_state)
// Fill in state transition logic
A : next_state = in ? A : B ;
B : next_state = in ? B : A ;
endcase
// State flip-flops
present_state = next_state;
case (present_state)
// Fill in output logic
A : out = 0 ;
B : out = 1 ;
endcase
end
end
endmodule
| 6.89453
|
module sync_fifo_ver2 (
clk,
rst_n,
wr,
rd,
din,
dout,
full,
empty
);
input clk, rst_n;
input wr, rd;
input [7:0] din;
output [7:0] dout;
reg [7:0] dout;
output full, empty;
reg full, empty;
reg [7:0] mem[15:0];
reg [3:0] wp, rp;
always @(posedge clk or negedge rst_n)
if (!rst_n) wp <= 0;
else begin
if (!full && wr) wp <= wp + 1'b1;
end
always @(posedge clk) if (!full && wr) mem[wp] <= din;
always @(posedge clk or negedge rst_n)
if (!rst_n) rp <= 0;
else begin
if (!empty && rd) rp <= rp + 1'b1;
end
always @(posedge clk) if (!empty && rd) dout <= mem[rp];
always @(posedge clk or negedge rst_n)
if (!rst_n) full <= 1'b0;
else begin
if ((!rd && wr) && ((wp == rp - 1'b1) || ((rp == 4'h0) && (wp == 4'hf)))) full <= 1'b1;
else if (full && rd) full <= 1'b0;
else full <= 1'b0;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) empty <= 1'b0;
else begin
if ((!wr && rd) && ((rp == wp - 1'b1) || ((rp == 4'hf) && (wp == 4'h0)))) empty <= 1'b1;
else if (empty && wr) empty <= 1'b0;
else empty <= 1'b0;
end
endmodule
| 6.509696
|
module sync_fifo_ver2_tb ();
reg clk, rst_n, wr, rd;
reg [7:0] din;
wire [7:0] dout;
wire full, empty;
reg [7:0] temp = 0;
initial begin
clk = 0;
rst_n = 1;
wr = 0;
rd = 0;
#10 rst_n = 0;
#10 rst_n = 1;
push(1);
push(2);
push(3);
push(4);
push(5);
push(6);
push(7);
push(8);
push(9);
push(10);
push(11);
push(12);
push(13);
push(14);
push(15);
push(16);
push(17);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
end
always #2 clk <= ~clk;
sync_fifo_ver2 dut (
.clk(clk),
.rst_n(rst_n),
.wr(wr),
.rd(rd),
.din(din),
.full(full),
.empty(empty),
.dout(dout)
);
task push(input [7:0] data);
if (full) $display("The FIFO has been full! Data:%d cannot been push!", data);
else begin
$display("Push:%d", data);
din <= data;
wr <= 1;
@(posedge clk);
#3 wr = 0;
end
endtask
task pop(output [7:0] data);
if (empty) $display("The FIFO has been empty! Data cannot been poped!");
else begin
rd = 1;
@(posedge clk);
#3 rd = 0;
data = dout;
$display("------Poped:",, data);
end
endtask
endmodule
| 6.509696
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = !(a || b);
endmodule
| 7.203305
|
module f4 (
output [3:0] s,
input [3:0] a,
input [3:0] b
);
and and1 (s[0], a[0], b[0]);
and and2 (s[1], a[1], b[1]);
and and3 (s[2], a[2], b[2]);
and and4 (s[3], a[3], b[3]);
endmodule
| 6.784298
|
module f4 (output [3:0] s,
input [3:0] chave, //definida apenas por 0000 ou 0001
input [3:0] a,
input [3:0] b);
wire [3:0] w1;
wire [3:0] w2;
wire [3:0] w3;
wire [3:0] w4;
wire [3:0] w5;
rand and1 (w1,a,b);
ror or1 (w2,a,b);
rnot not1 (w3,chave);
rand and2 (w4,w1,chave);
rand and3 (w5,w2,w3);
ror or2 (s,w4,w5);
endmodule
| 6.842475
|
module f4 (output [3:0] s,
input [3:0] chave, //definida apenas por 0000 ou 0001
input [3:0] grupo, //definida da mesma forma que a chave
input [3:0] a,
input [3:0] b);
wire [3:0] w1;
wire [3:0] w2;
wire [3:0] w3;
wire [3:0] w4;
wire [3:0] w5;
wire [3:0] w6;
wire [3:0] w7;
wire [3:0] w8;
wire [3:0] w9;
wire [3:0] w10;
wire [3:0] w11;
wire [3:0] w12;
wire [3:0] w13;
wire [3:0] w14;
//parte de cima
rand and1 (w1,a,b);
ror or1 (w2,a,b);
//seletor chave
rnot not1 (w3,chave);
//parte de baixo
rnand nand1 (w4,a,b);
rnor nor1 (w5,a,b);
//mux1
rand and2 (w6,w1,chave);
rand and3 (w7,w2,w3);
rand and4 (w8,w4,w3);
rand and5 (w9,w5,chave);
//saidas mux1
ror or2 (w10,w6,w7);
ror or3 (w11,w8,w9);
//mux2
rnot not2 (w12,grupo);
rand and6 (w13,w10,grupo);
rand and7 (w14,w11,w12);
//saida
ror or4 (s,w13,w14);
endmodule
| 6.842475
|
module circ (
output s,
input chave,
input grupo,
input a,
input b
);
xor xor1 (w1, a, b);
xnor xnor1 (w2, a, b);
or or1 (w3, a, b);
nor nor1 (w4, a, b);
not not1 (m1, chave);
//mux1
and and1 (m2, w1, m1);
and and2 (m3, w2, chave);
and and3 (m4, w3, m1);
and and5 (m5, w4, chave);
or or2 (m6, m2, m3);
or or3 (m7, m4, m5);
//mux2
not not2 (w5, grupo);
and and6 (m6, w5);
and and7 (m7, grupo);
or or4 (s, m6, m7);
endmodule
| 8.388756
|
module testcirc;
reg a, b, chave, grupo;
wire s;
circ circ1 (
s,
chave,
grupo,
a,
b
);
initial begin
a = 0;
b = 0;
chave = 0;
grupo = 0;
end
initial begin
$display("Eduardo Botelho de Andrade - 427395");
$display("Test LU's module");
$display("Chave: 0 = OR / 1 = AND");
$monitor("x = %b , y = %b , s = %b - chave = %b , grupo = %b", a, b, s, chave, grupo);
#1 chave = 1;
grupo = 1; //seletor de operao
#1 b = 1;
#1 a = 1;
b = 0;
#1 b = 1;
end
endmodule
| 8.149214
|
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
| 7.203305
|
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
// assign
assign out_assign = a ^ b;
// always @(*)
always @(*) begin
out_always_comb = a ^ b;
end
// always @(posedge clk)
always @(posedge clk) begin
out_always_ff <= a ^ b;
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
// assign
assign out_assign = (sel_b1 & sel_b2) ? b : a;
// always
always @(*) begin
if (sel_b1 & sel_b2) out_always = b;
else out_always = a;
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) begin
if (sel_b1 & sel_b2) out_always = b;
else out_always = a;
end
endmodule
| 7.203305
|
module zoechip #(
parameter MAX_COUNT = 1000
) (
input [7:0] io_in,
output [7:0] io_out
);
wire A, B, C, D, F, G, M;
assign io_out = {1'b0, D, B, G, F, M, C, A};
wire Z = io_in[0];
wire O = io_in[1];
wire E = io_in[2];
wire f = io_in[3];
assign A = Z + O + E;
assign B = O + E + f;
assign C = Z + O + f;
assign D = Z + O + E + f;
assign F = E + Z;
assign G = E + Z;
assign M = f;
endmodule
| 6.878561
|
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
else shut_off_computer = 0;
end
always @(*) begin
if (~arrived) keep_driving = ~gas_tank_empty;
else keep_driving = 0;
end
endmodule
| 7.203305
|
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
else shut_off_computer = 0;
end
always @(*) begin
if (arrived | gas_tank_empty) keep_driving = 0;
else keep_driving = 1;
end
endmodule
| 7.203305
|
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: out = data0;
3'b001: out = data1;
3'b010: out = data2;
3'b011: out = data3;
3'b100: out = data4;
3'b101: out = data5;
default: out = 4'b0000;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
4'd0: out = data0;
4'd1: out = data1;
4'd2: out = data2;
4'd3: out = data3;
4'd4: out = data4;
4'd5: out = data5;
default: out = 0;
endcase
end
endmodule
| 7.203305
|
module mbikovitsky_top #(
parameter CLOCK_HZ = 625,
parameter BAUD = 78,
parameter ROM_WORDS = 4
) (
input [7:0] io_in,
output [7:0] io_out
);
localparam LFSR_BITS = 5;
wire clk = io_in[0];
wire mode_cpu = reset_lfsr & reset_taps;
assign io_out = mode_cpu ? cpu_io_out[7:0] : segments;
//
// LFSR
//
wire reset_lfsr = io_in[1];
wire reset_taps = io_in[2];
wire [LFSR_BITS-1:0] data_in = io_in[3+LFSR_BITS-1:3];
wire [7:0] segments;
seven_segment seven_segment (
.value_i(lfsr_out),
.segments_o(segments)
);
wire [LFSR_BITS-1:0] lfsr_out;
lfsr #(
.BITS (LFSR_BITS),
.TICKS(CLOCK_HZ)
) lfsr (
.clk(clk),
.reset_lfsr_i(reset_lfsr),
.initial_state_i(data_in),
.reset_taps_i(reset_taps),
.taps_i(data_in),
.state_o(lfsr_out)
);
//
// CPU
//
wire cpu_reset = (!mode_cpu) || (mode_cpu && io_in[3]);
wire mem_reset = (!mode_cpu) || (mode_cpu && io_in[4]);
wire uart_reset = (!mode_cpu) || (mode_cpu && io_in[6]);
wire uart_rx = io_in[5];
CPU cpu (
.clk(clk),
.reset(cpu_reset),
.instruction(instruction),
.next_instruction_addr_o(next_instruction_addr),
.memory_we_o(memory_we),
.memory_i(cpu_io_out),
.memory_o(cpu_memory_out)
);
wire [15:0] instruction;
wire [14:0] next_instruction_addr;
wire memory_we;
wire [15:0] cpu_memory_out;
// All memory reads and writes always go to (cpu_io_out), regardless
// of the address output by the CPU.
// I/O output
reg [15:0] cpu_io_out;
always @(posedge clk) begin
if (mem_reset) begin
cpu_io_out <= 0;
end else begin
if (!cpu_reset && memory_we) begin
cpu_io_out <= cpu_memory_out;
end
end
end
// PROM
reg [16-1:0] prom[ROM_WORDS];
assign instruction = prom[next_instruction_addr[$clog2(ROM_WORDS)-1:0]];
// UART to fill the PROM
UART #(
.CLOCK_HZ(CLOCK_HZ),
.BAUD(BAUD)
) uart (
.reset(uart_reset),
.clk(clk),
.rx_i(uart_rx),
.rx_data_o(rx_data),
.rx_ready_o(rx_ready),
.rx_ack_i(1'b1)
);
wire [ 7:0] rx_data;
wire rx_ready;
reg [$clog2(ROM_WORDS)-1:0] uart_write_address;
reg [ 0:0] uart_state;
localparam UART_RECEIVE_LOW = 2'd0, UART_RECEIVE_HIGH = 2'd1;
always @(posedge clk) begin
if (uart_reset) begin
uart_write_address <= 0;
uart_state <= UART_RECEIVE_LOW;
end else begin
case (uart_state)
UART_RECEIVE_LOW: begin
if (rx_ready) begin
prom[uart_write_address][7:0] <= rx_data;
uart_state <= UART_RECEIVE_HIGH;
end
end
UART_RECEIVE_HIGH: begin
if (rx_ready) begin
prom[uart_write_address][15:8] <= rx_data;
uart_state <= UART_RECEIVE_LOW;
if (uart_write_address == ROM_WORDS - 1) begin
uart_write_address <= 0;
end else begin
uart_write_address <= uart_write_address + 1;
end
end
end
endcase
end
end
endmodule
| 6.931629
|
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
case (in)
4'b0000, 4'b0001, 4'b0011, 4'b0101, 4'b0111, 4'b1001, 4'b1011, 4'b1101, 4'b1111: pos = 2'b00;
4'b0010, 4'b0110, 4'b1010, 4'b1110: pos = 2'b01;
4'b0100, 4'b1100: pos = 2'b10;
4'b1000: pos = 2'b11;
default: pos = 2'bx;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
if (in[0] == 1) pos = 2'd0;
else if (in[1] == 1) pos = 2'd1;
else if (in[2] == 1) pos = 2'd2;
else if (in[3] == 1) pos = 2'd3;
else pos = 2'd0;
end
endmodule
| 7.203305
|
module top_module (
// input [3:0] in,
// output reg [1:0] pos
// );
// always @(*) begin // Combinational always block
// case (in)
// 4'h0: pos = 2'h0; // I like hexadecimal because it saves typing.
// 4'h1: pos = 2'h0;
// 4'h2: pos = 2'h1;
// 4'h3: pos = 2'h0;
// 4'h4: pos = 2'h2;
// 4'h5: pos = 2'h0;
// 4'h6: pos = 2'h1;
// 4'h7: pos = 2'h0;
// 4'h8: pos = 2'h3;
// 4'h9: pos = 2'h0;
// 4'ha: pos = 2'h1;
// 4'hb: pos = 2'h0;
// 4'hc: pos = 2'h2;
// 4'hd: pos = 2'h0;
// 4'he: pos = 2'h1;
// 4'hf: pos = 2'h0;
// default: pos = 2'b0; // Default case is not strictly necessary because all 16 combinations are covered.
// endcase
// end
// // There is an easier way to code this. See the next problem (always_casez).
// endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'b0000_0000, 8'b????_???1: pos = 3'b000;
8'b????_??10: pos = 3'b001;
8'b????_?100: pos = 3'b010;
8'b????_1000: pos = 3'b011;
8'b???1_0000: pos = 3'b100;
8'b??10_0000: pos = 3'b101;
8'b?100_0000: pos = 3'b110;
8'b1000_0000: pos = 3'b111;
default: pos = 3'bxxx;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'bzzzz_zzz1: pos = 8'd0;
8'bzzzz_zz1z: pos = 8'd1;
8'bzzzz_z1zz: pos = 8'd2;
8'bzzzz_1zzz: pos = 8'd3;
8'bzzz1_zzzz: pos = 8'd4;
8'bzz1z_zzzz: pos = 8'd5;
8'bz1zz_zzzz: pos = 8'd6;
8'b1zzz_zzzz: pos = 8'd7;
default: pos = 8'd0;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
// set default value before case statement
always @(*) begin
left = 1'b0;
down = 1'b0;
right = 1'b0;
up = 1'b0;
case (scancode)
16'he06b: left = 1'b1;
16'he072: down = 1'b1;
16'he074: right = 1'b1;
16'he075: up = 1'b1;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
left = 0;
down = 0;
right = 0;
up = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he075: up = 1;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
);
// assign intermediate_result1 = compare? true: false;
wire [7:0] min1;
wire [7:0] min2;
assign min1 = (a < b) ? a : b;
assign min2 = (c < d) ? c : d;
assign min = (min1 < min2) ? min1 : min2;
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
b,
c,
d,
output reg [7:0] min
); //
// assign intermediate_result1 = compare? true: false;
reg [7:0] min_1;
reg [7:0] min_2;
always @(*) begin
min_1 = (a < b) ? a : b;
min_2 = (c < d) ? c : d;
min = (min_1 < min_2) ? min_1 : min_2;
end
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output parity
);
// even partity
assign parity = ^in;
endmodule
| 7.203305
|
module top_module (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
// reduction
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305
|
module SPIController (
// System Interfaces
input wire clk,
input wire rst,
// SPI Bus Interfaces
output reg CS0,
output reg CS1,
output reg SPICLK,
output reg MOSI,
input wire MISO,
// Input Signals
input wire Addr15, // Sampled on Phase 01
input wire Read_notWrite, // Sampled on Phase 16
input wire Addr, // Sampled on Phase 18[bit0/LSB], 20[bit1], ..., 44[bit13], 46[bit14/MSB], bit 15 not sampled (see Addr15)
input wire Data, // Sampled on Phase 50[bit0/LSB], 52[bit1], ..., 78[bit14], 80[bit15/MSB]
// Timing Output Signals
output reg ShiftAddr, // Asserted when the Address should be shifted
output reg ShiftDataRead, // Asserted when the data register collecting data read from memory should be shifted
output reg ShiftDataWrite, // Asserted when the data regsiter providing data to be written to memory should be shifted
output reg PresetCarry, // Asserted the clock before data motion starts
output reg EndOfPhase, //
output reg PrepOutput
);
// SPI sequencer
reg [6:0] SPIphase;
always @(posedge clk) begin
if (rst) SPIphase <= 0;
else if (SPIphase == 83) SPIphase <= 0;
else SPIphase <= SPIphase + 1;
end
// SPI bus signal generator
always @(posedge clk) begin
if (SPIphase <= 1) begin
CS0 <= 1;
CS1 <= 1;
SPICLK <= 0;
MOSI <= 0;
end else begin
CS0 <= CSreg;
CS1 <= !CSreg;
if (SPIphase <= 81) SPICLK <= SPIphase[0];
else SPICLK <= 0;
if (SPIphase <= 13) MOSI <= 0;
else if (SPIphase <= 15) MOSI <= 1;
else if (SPIphase <= 17) begin
if (SPIphase[0] == 0) MOSI <= Read_notWrite;
end else if (SPIphase <= 47) begin
if (SPIphase[0] == 0) MOSI <= Addr;
end else if (SPIphase <= 49) MOSI <= 0;
else begin
if (Read_notWrite) MOSI <= 0;
else begin
if (SPIphase[0] == 0) MOSI <= Data;
end
end
end
end
// Generate Address Shift Enable Signals
always @(posedge clk) begin
ShiftAddr <= ((SPIphase >= 18) && (SPIphase <= 48) && (SPIphase[0] == 0));
ShiftDataRead <= ((SPIphase >= 51) && (SPIphase <= 81) && (SPIphase[0] == 1) && Read_notWrite);
ShiftDataWrite <= ((SPIphase >= 50) && (SPIphase <= 80) && (SPIphase[0] == 0) && !Read_notWrite);
PresetCarry <= (SPIphase == 17);
EndOfPhase <= (SPIphase == 83);
PrepOutput <= (SPIphase == 49);
end
reg CSreg;
always @(posedge clk) begin
if (SPIphase == 1) CSreg <= Addr15;
end
endmodule
| 7.271463
|
module top_module (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305
|
module async_fifo_ver1 (
rst_n,
wr_clk,
wr_en,
din,
rd_clk,
rd_en,
dout,
empty,
full
);
input rst_n;
input wr_clk, wr_en;
input rd_clk, rd_en;
input [`data_width-1:0] din;
output full, empty;
wire full, empty;
output [`data_width-1:0] dout;
reg [`data_width-1:0] dout;
//The RAM for store data
reg [`data_width-1:0] mem [`data_depth-1:0];
//The address poniter and adress of ram
reg [`addr_width:0] wr_ptr, rd_ptr;
wire [`addr_width-1:0] wr_ram, rd_ram;
//the reg used for compare
wire [`addr_width:0] wr_ptr_gray;
reg [`addr_width:0] wr_ptr_gray_reg1;
reg [`addr_width:0] wr_ptr_gray_reg2;
wire [`addr_width:0] rd_ptr_gray;
reg [`addr_width:0] rd_ptr_gray_reg1;
reg [`addr_width:0] rd_ptr_gray_reg2;
//--------------------The process of writing data---------------------------------
always @(posedge wr_clk) if (wr_en && (~full)) mem[wr_ram] <= din;
always @(posedge wr_clk or negedge rst_n)
if (!rst_n) wr_ptr <= 0;
else begin
if (wr_en && (~full)) wr_ptr <= wr_ptr + 1'b1;
else wr_ptr <= wr_ptr;
end
assign wr_ram = wr_ptr[`addr_width-1:0];
//--------------------The process of reading data--------------------------------
always @(posedge rd_clk) if ((~empty) && rd_en) dout <= mem[rd_ram];
always @(posedge rd_clk or negedge rst_n)
if (!rst_n) rd_ptr <= 0;
else begin
if ((~empty) && rd_en) rd_ptr <= rd_ptr + 1'b1;
else rd_ptr <= rd_ptr;
end
assign rd_ram = rd_ptr[`addr_width-1:0];
//--------------------The gray code of read to write domian------------------------
always @(posedge wr_clk) begin
rd_ptr_gray_reg1 <= rd_ptr_gray;
rd_ptr_gray_reg2 <= rd_ptr_gray_reg1;
end
assign rd_ptr_gray = (rd_ptr >> 1) ^ rd_ptr;
//-------------------The gray code of write to read domian--------------------------
always @(posedge rd_clk) begin
wr_ptr_gray_reg1 <= wr_ptr_gray;
wr_ptr_gray_reg2 <= wr_ptr_gray_reg1;
end
assign wr_ptr_gray = (wr_ptr >> 1) ^ wr_ptr;
//--------------------The generate of flag of full and empty------------------------
assign empty = (rd_ptr_gray == wr_ptr_gray_reg2);
assign full=(wr_ptr_gray=={~(rd_ptr_gray_reg2[`addr_width-:2]),rd_ptr_gray_reg2[`addr_width-2:0]});
endmodule
| 6.722882
|
module async_fifo_ver1_tb ();
reg rst_n, wr_clk, wr_en, rd_clk, rd_en;
reg [`data_width-1:0] din;
wire full, empty;
wire [`data_width-1:0] dout;
reg [`data_width-1:0] temp = 0;
initial begin
rst_n = 1;
wr_clk = 0;
wr_en = 0;
rd_clk = 0;
rd_en = 0;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #4 wr_clk <= ~wr_clk;
always #8 rd_clk <= ~rd_clk;
async_fifo_ver1 dut (
.rst_n(rst_n),
.wr_clk(wr_clk),
.wr_en(wr_en),
.rd_clk(rd_clk),
.rd_en(rd_en),
.din(din),
.full(full),
.empty(empty),
.dout(dout)
);
initial begin
#30 push(1);
push(2);
push(3);
push(4);
push(5);
push(6);
push(7);
push(8);
push(9);
push(10);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
end
task push(input [`data_width-1:0] data);
if (full) $display("---Cannot push %d: Buffer Full---", data);
else begin
$display("Push",, data);
din = data;
wr_en = 1;
@(posedge wr_clk);
#1 wr_en = 0;
end
endtask
task pop(output [`data_width-1:0] data);
if (empty) $display("---Cannot Pop: Buffer Empty---");
else begin
rd_en = 1;
@(posedge rd_clk);
#1 rd_en = 0;
data = dout;
$display("------Poped:",, data);
end
endtask
endmodule
| 6.722882
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
parameter IDLE = 3'b000;
parameter S0 = 3'b001;
parameter S1 = 3'b010;
parameter S2 = 3'b011;
parameter S3 = 3'b100;
reg [2:0] cstate, nstate;
always @(posedge clk) begin
if (reset) begin
cstate <= IDLE;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
IDLE: nstate = data ? S0 : IDLE;
S0: nstate = data ? S1 : IDLE;
S1: nstate = data ? S1 : S2;
S2: nstate = data ? S3 : IDLE;
S3: nstate = S3;
endcase
end
assign start_shifting = (cstate == S3);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = k ? OFF : ON;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) begin
state <= OFF;
end else begin
state <= next_state;
end
end
// Output logic
assign out = (state == ON);
endmodule
| 7.203305
|
module nand_with_wire (
a,
b,
c
);
input a;
input b;
output c;
wire tmp;
assign tmp = a & b;
assign c = ~tmp;
endmodule
| 6.611817
|
module delay_time (
clk,
rst_n,
in_data,
out_data
);
input clk, rst_n, in_data;
output out_data;
reg [2:0] cnt_ctrl; //打两拍
always @(posedge clk) begin
cnt_ctrl <= {cnt_ctrl[1:0], in_data};
end
/* always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt_ctrl <= 3'b0;
end
else begin
cnt_ctrl <= {cnt_ctrl[1:0],in_data};
end
end */
assign out_data = cnt_ctrl[2];
endmodule
| 6.676482
|
module BCD_Adder (
Sum,
Carry_out,
Addend,
Augend,
Carry_in
);
output [3:0] Sum;
output Carry_out;
input [3:0] Addend, Augend;
input Carry_in;
wire [3:0] z, z1;
wire k;
assign {k, z} = Addend + Augend + Carry_in;
assign Carry_out = (z[1] && z[3]) || (z[2] && z[3]) || k;
assign z1[0] = 0;
assign z1[1] = Carry_out;
assign z1[2] = Carry_out;
assign z1[3] = 0;
assign Sum = z + z1;
endmodule
| 7.619207
|
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
assign w = a; //assign statements are executed in parallel
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire w1 = a && b;
wire w2 = c && d;
assign out = w1 || w2;
assign out_n = !(w1 || w2);
endmodule
| 7.203305
|
module fa4bit (
output [2:0] s,
output carryout,
input [3:0] a,
input [3:0] b,
input carryin
);
or or1 (sinal, a[3], b[3]);
fa fa1 (
s[0],
w1,
a[0],
b[0],
sinal
);
fa fa2 (
s[1],
w2,
a[1],
b[1],
w1
);
fa fa3 (
s[2],
carryout,
a[2],
b[2],
w2
);
endmodule
| 7.14019
|
module fs4bit (
output [2:0] s,
output carryout,
input [3:0] a,
input [3:0] b,
input carryin
);
or or1 (sinal, a[3], b[3]);
fs fs1 (
s[0],
w1,
a[0],
b[0],
sinal
);
fs fs2 (
s[1],
w2,
a[1],
b[1],
w1
);
fs fs3 (
s[2],
carryout,
a[2],
b[2],
w2
);
endmodule
| 7.263759
|
module different (
output s,
input [3:0] a,
input [3:0] b
);
xor xor1 (w1, a[0], b[0]);
xor xor2 (w2, a[1], b[1]);
xor xor3 (w3, a[2], b[2]);
xor xor4 (w4, a[3], b[3]);
or or1 (s, w1, w2, w3, w4);
endmodule
| 6.956141
|
module top_module (
input [99:0] in,
output [99:0] out
);
reg [7:0] cnt;
always @(*) begin
for (cnt = 8'd0; cnt < 100; cnt = cnt + 1) begin
out[cnt] = in[99-cnt];
end
end
endmodule
| 7.203305
|
module top_module (
// input [99:0] in,
// output reg [99:0] out
// );
// always @(*) begin
// for (int i=0;i<$bits(out);i++) // $bits() is a system function that returns the width of a signal.
// out[i] = in[$bits(out)-i-1]; // $bits(out) is 100 because out is 100 bits wide.
// end
// endmodule
| 7.203305
|
module top_module (
input [99:0] in,
output reg [99:0] out
);
integer i;
always @(*) begin
for (i = 0; i <= 99; i = i + 1) begin
out[i] = in[99-i];
end
end
endmodule
| 7.203305
|
module mixer (
input clk,
input write_data,
input [5:0] data,
input voice0_out,
input voice1_out,
output [3:0] out
);
reg [5:0] voice_volumes;
always @(posedge clk) begin
if (write_data) voice_volumes <= data;
end
wire [2:0] voice0_volume = voice_volumes[2:0];
wire [2:0] voice1_volume = voice_volumes[5:3];
wire [2:0] scaled_voice0_out = voice0_out ? voice0_volume : 3'h00;
wire [2:0] scaled_voice1_out = voice1_out ? voice1_volume : 3'h00;
assign out = scaled_voice0_out + scaled_voice1_out;
endmodule
| 6.918526
|
module yupferris_bitslam (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire addr_data_sel = io_in[1];
wire write_addr = ~addr_data_sel;
wire write_data = addr_data_sel;
wire [5:0] addr_data = io_in[7:2];
wire [5:0] data = addr_data;
reg [2:0] addr;
always @(posedge clk) begin
if (write_addr) addr <= addr_data[2:0];
end
wire voice_select = addr[1];
wire mixer_select = addr[2];
wire voice0_select = ~voice_select & ~mixer_select;
wire voice1_select = voice_select & ~mixer_select;
wire voice0_out;
voice voice0 (
.clk(clk),
.addr(addr[0]),
.write_data(write_data & voice0_select),
.data(data),
.out(voice0_out)
);
wire voice1_out;
voice voice1 (
.clk(clk),
.addr(addr[0]),
.write_data(write_data & voice1_select),
.data(data),
.out(voice1_out)
);
wire [3:0] mixer_out;
mixer mixer (
.clk(clk),
.write_data(write_data & mixer_select),
.data(data),
.voice0_out(voice0_out),
.voice1_out(voice1_out),
.out(mixer_out)
);
assign io_out = {4'h00, mixer_out};
endmodule
| 6.800173
|
module top_module (
input [254:0] in,
output [ 7:0] out
);
always @(*) begin
out = 0;
for (int i = 0; i < $bits(in); i = i + 1) begin
if (in[i] == 1) out = out + 1;
end
end
endmodule
| 7.203305
|
module top_module (
input [254:0] in,
output reg [7:0] out
);
integer count;
always @(*) begin : count_b
integer i;
count = 0;
for (i = 0; i <= 254; i = i + 1) begin
if (in[i]) count = count + 1;
end
out = {count[7:0]};
end
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
genvar i;
generate
begin
for (i = 0; i <= 99; i = i + 1) begin : adder_loop
if (i == 0)
adder1 u_adder1 (
.a(a[i]),
.b(b[i]),
.cin(cin),
.sum(sum[i]),
.cout(cout[i])
);
else
adder1 u_adder1 (
.a(a[i]),
.b(b[i]),
.cin(cout[i-1]),
.sum(sum[i]),
.cout(cout[i])
);
end
end
endgenerate
endmodule
| 7.203305
|
module adder1 (
input a,
input b,
input cin,
output sum,
output cout
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.322982
|
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
wire [99:0] new_cin;
assign new_cin = {cout[98:0], cin};
always @(*) begin
for (int i = 0; i < $bits(cout); i = i + 1) begin
sum[i] = a[i] ^ b[i] ^ new_cin[i];
cout[i] = (a[i] & b[i]) | (a[i] & new_cin[i]) | (b[i] & new_cin[i]);
end
end
endmodule
| 7.203305
|
module github_com_proppy_tt02_xls_popcount (
input wire [7:0] io_in,
output wire [7:0] io_out
);
user_module user_module0 (
io_in,
io_out
);
endmodule
| 7.341325
|
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
genvar i;
wire [99:0] cout_temp;
// generate circular instance
generate
begin
for (i = 0; i <= 99; i = i + 1) begin : bcd_add_loop
if (i == 0)
bcd_fadd u_bcd_fadd (
.a(a[4*i+3:4*i]),
.b(b[4*i+3:4*i]),
.cin(cin),
.sum(sum[4*i+3:4*i]),
.cout(cout_temp[i])
);
else
bcd_fadd u_bcd_fadd (
.a(a[4*i+3:4*i]),
.b(b[4*i+3:4*i]),
.cin(cout_temp[i-1]),
.sum(sum[4*i+3:4*i]),
.cout(cout_temp[i])
);
end
end
endgenerate
assign cout = cout_temp[99];
endmodule
| 7.203305
|
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] fadd_cin;
wire [99:0] fadd_cout;
assign fadd_cin = {fadd_cout[98:0], cin};
generate
genvar i;
for (i = 0; i < 8'd100; i = i + 1) begin : BCD_loop
bcd_fadd bcd_fadd_u0 (
.a(a[(i*4+3):(i*4)]),
.b(b[(i*4+3):(i*4)]),
.cin(fadd_cin[i]),
.cout(fadd_cout[i]),
.sum(sum[(i*4+3):(i*4)])
);
end
endgenerate
assign cout = fadd_cout[99];
endmodule
| 7.203305
|
module top_module(
// input [399:0] a, b,
// input cin,
// output cout,
// output [399:0] sum );
// wire [99:0] fadd_cin;
// wire [99:0] fadd_cout;
// assign fadd_cin = {fadd_cout[98:0], cin};
// bcd_fadd bcd_fadd_u0 [99:0](
// .a(a),
// .b(b),
// .cin(fadd_cin),
// .cout(fadd_cout),
// .sum(sum)
// );
// assign cout = fadd_cout[99];
// endmodule
| 6.631647
|
module rc5_top (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire ir = io_in[2];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
wire valid;
wire [5:0] command;
wire control;
reg control_d;
localparam [5:0] RC5_INCR_VOLUME = 16;
localparam [5:0] RC5_DECR_VOLUME = 17;
rc5 rc5 (
.i_clk(clk),
.i_rst(reset),
.i_rc5(ir),
.o_valid (valid),
.o_command(command),
.o_control(control)
);
reg [3:0] counter;
always @(posedge clk) begin
if (reset) begin
counter <= 0;
control_d <= 1'b0;
end else begin
if (valid) begin
control_d <= control;
if (control != control_d) begin
if (command == RC5_INCR_VOLUME) begin
counter <= counter + 1;
end else if (command == RC5_DECR_VOLUME) begin
counter <= counter - 1;
end
end
end
end
end
// instantiate segment display
seg7 seg7 (
.counter (counter),
.segments(led_out)
);
endmodule
| 6.522639
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module top_module (
output out
);
assign out = 1'b0;
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
output out
);
assign out = ~(in1 | in2);
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
output out
);
assign out = in1 & ~(in2);
endmodule
| 7.203305
|
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