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module fullsubtractor4 (
diff,
bout,
a,
b,
bin
);
input [3:0] a, b;
output [3:0] diff;
input bin;
output bout;
wire w1, w2, w3;
fullsubtractor1 L0 (
diff[0],
w1,
a[0],
b[0],
bin
);
fullsubtractor1 L1 (
diff[1],
w2,
a[1],
b[1],
w1
);
fullsubtractor1 L2 (
diff[2],
w3,
a[2],
b[2],
w2
);
fullsubtractor1 L3 (
diff[3],
bout,
a[3],
b[3],
w3
);
endmodule
| 6.741456
|
module fullsubtractor1_tb;
wire diff, bout;
reg a, b, bin;
fullsubtractor1 m1 (
diff,
bout,
a,
b,
bin
);
initial begin
a = 0;
b = 0;
bin = 0;
#20 a = 0;
b = 0;
bin = 1;
#20 a = 0;
b = 1;
bin = 0;
#20 a = 0;
b = 1;
bin = 1;
#20 a = 1;
b = 0;
bin = 0;
#20 a = 1;
b = 0;
bin = 1;
#20 a = 1;
b = 1;
bin = 0;
#20 a = 1;
b = 1;
bin = 1;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
| 6.741456
|
module fourbit (
e,
a,
b,
c,
d
);
output e;
input a, b, c, d;
four_bit_majority_function g (
e,
a,
b,
c,
d
);
endmodule
| 7.275509
|
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_5 (s0, n4, C0);
or OR3_6 (C1, n1, n2, n3);
and AND2_7 (n5, a1, b1);
and AND2_8 (n6, a1, C1);
and AND2_9 (n7, b1, C1);
xor XOR2_10 (n8, a1, b1);
xor XOR2_11 (s1, n8, C1);
or OR3_12 (C2, n5, n6, n7);
and AND2_13 (n9, a2, b2);
and AND2_14 (n10, a2, C2);
and AND2_15 (n11, b2, C2);
xor XOR2_16 (n12, a2, b2);
xor XOR2_17 (s2, n12, C2);
or OR3_18 (C3, n9, n10, n11);
and AND2_19 (n13, a3, b3);
and AND2_20 (n14, a3, C3);
and AND2_21 (n15, b3, C3);
xor XOR2_22 (n16, a3, b3);
xor XOR2_23 (s3, n16, C3);
or OR3_24 (Cout, n13, n14, n15);
endmodule
| 6.968492
|
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_5 (s0, n4, C0);
or OR3_6 (C1, n1, n2, n3);
not NOT1_1 (n17, C1);
xor XOR2_1 (n18, C1, n17);
or OR2_1 (n19, n17, n18);
and AND2_7 (n5, a1, b1);
and AND2_8 (n6, a1, n19);
and AND2_9 (n7, b1, n19);
xor XOR2_10 (n8, a1, b1);
xor XOR2_11 (s1, n8, n19);
or OR3_12 (C2, n5, n6, n7);
and AND2_13 (n9, a2, b2);
and AND2_14 (n10, a2, C2);
and AND2_15 (n11, b2, C2);
xor XOR2_16 (n12, a2, b2);
xor XOR2_17 (s2, n12, C2);
or OR3_18 (C3, n9, n10, n11);
and AND2_19 (n13, a3, b3);
and AND2_20 (n14, a3, C3);
and AND2_21 (n15, b3, C3);
xor XOR2_22 (n16, a3, b3);
xor XOR2_23 (s3, n16, C3);
or OR3_24 (Cout, n13, n14, n15);
endmodule
| 6.968492
|
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_5 (s0, n4, C0);
or OR3_6 (C1, n1, n2, n3);
and AND2_7 (n5, a1, b1);
and AND2_8 (n6, a1, C1);
and AND2_9 (n7, b1, C1);
xor XOR2_10 (n8, a1, b1);
xor XOR2_11 (s1, n8, C1);
or OR3_12 (C2, n5, n6, n7);
not NOT1_1 (n17, C2);
xor XOR2_1 (n18, C2, n17);
or OR2_1 (n19, n17, n18);
and AND2_13 (n9, a2, b2);
and AND2_14 (n10, a2, n19);
and AND2_15 (n11, b2, n19);
xor XOR2_16 (n12, a2, b2);
xor XOR2_17 (s2, n12, n19);
or OR3_18 (C3, n9, n10, n11);
and AND2_19 (n13, a3, b3);
and AND2_20 (n14, a3, C3);
and AND2_21 (n15, b3, C3);
xor XOR2_22 (n16, a3, b3);
xor XOR2_23 (s3, n16, C3);
or OR3_24 (Cout, n13, n14, n15);
endmodule
| 6.968492
|
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_5 (s0, n4, C0);
or OR3_6 (C1, n1, n2, n3);
and AND2_1 (n17, n1, n2);
xor XOR2_1 (n18, C1, n17);
and AND2_7 (n5, a1, b1);
and AND2_8 (n6, a1, n18);
and AND2_9 (n7, b1, n18);
xor XOR2_10 (n8, a1, b1);
xor XOR2_11 (s1, n8, n18);
or OR3_12 (C2, n5, n6, n7);
and AND2_13 (n9, a2, b2);
and AND2_14 (n10, a2, C2);
and AND2_15 (n11, b2, C2);
xor XOR2_16 (n12, a2, b2);
xor XOR2_17 (s2, n12, C2);
or OR3_18 (C3, n9, n10, n11);
and AND2_19 (n13, a3, b3);
and AND2_20 (n14, a3, C3);
and AND2_21 (n15, b3, C3);
xor XOR2_22 (n16, a3, b3);
xor XOR2_23 (s3, n16, C3);
or OR3_24 (Cout, n13, n14, n15);
endmodule
| 6.968492
|
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_5 (s0, n4, C0);
or OR3_6 (C1, n1, n2, n3);
and AND2_7 (n5, a1, b1);
and AND2_8 (n6, a1, C1);
and AND2_9 (n7, b1, C1);
xor XOR2_10 (n8, a1, b1);
xor XOR2_11 (s1, n8, C1);
or OR3_12 (C2, n5, n6, n7);
and AND2_1 (n17, n5, n6);
xor XOR2_1 (n18, C2, n17);
and AND2_13 (n9, a2, b2);
and AND2_14 (n10, a2, n18);
and AND2_15 (n11, b2, n18);
xor XOR2_16 (n12, a2, b2);
xor XOR2_17 (s2, n12, n18);
or OR3_18 (C3, n9, n10, n11);
and AND2_19 (n13, a3, b3);
and AND2_20 (n14, a3, C3);
and AND2_21 (n15, b3, C3);
xor XOR2_22 (n16, a3, b3);
xor XOR2_23 (s3, n16, C3);
or OR3_24 (Cout, n13, n14, n15);
endmodule
| 6.968492
|
module D_flip_flop (
output reg Q,
input D,
clk
);
initial Q = 0;
always @(posedge clk) Q <= D;
endmodule
| 7.315668
|
module shift_register (
output [3:0] Q,
input D,
clk
);
D_flip_flop G1 (
Q[0],
D,
clk
);
D_flip_flop G2 (
Q[1],
Q[0],
clk
);
D_flip_flop G3 (
Q[2],
Q[1],
clk
);
D_flip_flop G4 (
Q[3],
Q[2],
clk
);
endmodule
| 6.854847
|
module syncdown (
output reg [3:0] count,
input clk,
rst
);
always @(posedge clk or posedge rst) begin
if (rst) count <= 0;
else if (clk) count <= count - 1;
else count <= 0;
end
endmodule
| 6.911046
|
module syncup (
output reg [3:0] count,
input clk,
rst
);
always @(posedge clk or posedge rst) begin
if (rst) count <= 0;
else if (clk) count <= count + 1; //negate the one for down counter
else count <= 0;
end
endmodule
| 6.625624
|
module four_bit_ripple_adder (
a,
b,
sum,
cout
);
input [3:0] a, b;
wire [2:0] c;
output [3:0] sum;
output cout;
full_adder fa1 (
a[0],
b[0],
0,
sum[0],
c[0]
);
full_adder fa2 (
a[1],
b[1],
c[0],
sum[1],
c[1]
);
full_adder fa3 (
a[2],
b[2],
c[1],
sum[2],
c[2]
);
full_adder fa4 (
a[3],
b[3],
c[2],
sum[3],
cout
);
endmodule
| 7.174086
|
module SW_Reg_4col (
clk,
WE,
AddrIn,
DataIn,
AddrOut,
DataOut
);
input clk;
input [10:0] AddrOut;
input [8:0] AddrIn;
input [31:0] DataIn;
input WE;
output [7:0] DataOut;
reg [8:0] dump;
reg [7:0] reg_file[0:351];
assign DataOut = reg_file[dump];
always @(posedge clk) begin
dump <= AddrOut;
if (WE) begin
reg_file[AddrIn*4+3] <= DataIn[31:24];
reg_file[AddrIn*4+2] <= DataIn[23:16];
reg_file[AddrIn*4+1] <= DataIn[15:8];
reg_file[AddrIn*4] <= DataIn[7:0];
end
end
endmodule
| 6.973656
|
module Control #(
parameter R_Q = 64
) (
//INPUT
input clk,
input rst,
//OUTPUT
output action,
output repair_period,
output reg MQ_active,
output reg subtract
);
reg [15:0] delay;
reg [ 2:0] state;
reg [ 5:0] repair_time;
localparam SCHEDULING = 16'b0000_0000_0100_0000; //64
localparam IDLE = 16'b0000_0001_0000_0000; //256 for test
////////////////////////////////////////////////////
// delay(cycles) state fun
//-------------------------------------------------
// 64 000 scheduling
//
// R_Q 001 margin-time
//
// 1 010 subtract
//
// remain_cycles 011 idle and repair-time
//
// R_Q 111 margin-time
//
// * repair-time is used for detecting the missed tasks in the ready and main queues and remove them.
// ** margin-time is used to seperate the scheduling period from IDLE interval.
// *** remain cycles is equiled to 65536-(other state' cycles)
////////////////////////////////////////////////////
assign action = (rst) ? 1'b0 : ~|state;
assign repair_period = (repair_time != 0);
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= 2;
subtract <= 0;
repair_time <= 0;
MQ_active <= 1;
delay <= IDLE;
end else begin
case (state)
3'b000: //scheduling
if (delay == 0) begin
delay <= R_Q;
state <= 3'b001;
end else begin
delay <= delay - 1;
end
3'b001: //wait for write all data to insertion cell
if (delay == 0) begin
state <= 3'b010;
subtract <= 1;
end else delay <= delay - 1;
3'b010: //subtract
begin
delay <= IDLE;
state <= 3'b011;
repair_time <= R_Q / 2;
subtract <= 0;
MQ_active <= 1;
end
3'b011: //idle
if (delay == 0) begin
delay <= R_Q;
state <= 3'b111;
MQ_active <= 0;
end else begin
delay <= delay - 1;
if (repair_period) repair_time <= repair_time - 1;
end
3'b111: //wait for write all data to insertion cell
if (delay == 0) begin
delay <= SCHEDULING;
state <= 3'b000;
end else delay <= delay - 1;
endcase
end
end
endmodule
| 7.002104
|
module four_fft (
a,
b,
c,
d,
A,
Ai,
B,
Bi,
C,
Ci,
D,
Di
);
input [3:0] a;
input [3:0] b;
input [3:0] c;
input [3:0] d;
output [5:0] A;
output [5:0] Ai;
output [5:0] B;
output [5:0] Bi;
output [5:0] C;
output [5:0] Ci;
output [5:0] D;
output [5:0] Di;
assign A = a + b + c + d;
assign Ai = 0;
assign B = a - c;
assign Bi = d - b;
assign C = a + c - b - d;
assign Ci = 0;
assign D = a - c;
assign Di = b - d;
endmodule
| 6.978127
|
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[0] && in[1] && in[2] && in[3];
assign out_or = in[0] || in[1] || in[2] || in[3];
assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];
endmodule
| 7.203305
|
module sub_task #(
parameter W = 42
) (
input clk,
rst,
input subtract_en,
input [(W)-1:0] RT_in,
output reg [(W)-1:0] RT_out
);
integer RP_MISS;
wire check_miss = (RT_in[31:16] < RT_in[15:0]); //relative deadline < execution time
always @(posedge subtract_en, posedge rst) begin
if (rst) begin
RP_MISS = 0;
end else if (RT_in[W-1]) begin
RT_out[15:0] = RT_in[15:0];
RT_out[31:16] = (RT_in[31:16] != 0) ? RT_in[31:16] - 1 : RT_in[31:16]; //deadline
RP_MISS = (check_miss) ? RP_MISS + 1 : RP_MISS;
RT_out[40:32] = RT_in[40:32]; //other
RT_out[W-1] = (check_miss | RT_out[31:16] == 0) ? 1'b0 : 1'b1;
end else RT_out = RT_in;
end
endmodule
| 6.607089
|
module Scheduler_main #(
parameter W = 42,
R_Q = 64,
CORE = 16
) (
//INPUT
input clk,
rst,
input wr,
input [W-2:0] task_in,
//OUTPUT
output CTRL_RP,
output CTRL_subtract,
output CTRL_MQ_active, //output for testbench
output v_exch,
output [W-2:0] task_exch
);
wire [(W*CORE)-1:0] RT_out, RT_cores;
wire CTRL_action;
/*********** Cores ************/
//this module is used just for simulations and it is not for synthesizing.
Cores #(
.W(W),
.N(CORE)
) Cores (
.clk (clk),
.rst (rst),
.subtract_en(CTRL_subtract),
.RT_in (RT_out),
.RT_out(RT_cores)
);
/********* Scheduler **********/
Scheduler #(W, R_Q, CORE) Scheduler (
.clk (clk),
.rst (rst),
.CTRL_subtract (CTRL_subtract),
.wr (wr),
.CTRL_action (CTRL_action),
.task_in (task_in),
.running_tasks_in((rst) ? 0 : RT_cores),
.CTRL_RP (CTRL_RP),
.v_exch (v_exch),
.task_exch (task_exch),
.running_tasks_out(RT_out)
);
/************ CTRL ************/
Control #(R_Q) CTRL (
.clk(clk),
.rst(rst),
.repair_period(CTRL_RP),
.action (CTRL_action),
.MQ_active (CTRL_MQ_active),
.subtract (CTRL_subtract)
);
endmodule
| 6.565705
|
module associative_array;
//array declaration
int a_array[*];
int index;
initial begin
//allocating array and assigning value to it
repeat (3) begin
a_array[index] = index * 2;
index = index + 4;
end
//num() ¨CAssociative array method
$display("\tNumber of entries in a_array is %0d", a_array.num());
$display("--- Associative array a_array entries and Values are ---");
foreach (a_array[i]) $display("\ta_array[%0d] \t = %0d", i, a_array[i]);
$display("--------------------------------------------------------");
//first()-Associative array method
a_array.first(index);
$display("\First entry is \t a_array[%0d] = %0d", index, a_array[index]);
//last()-Associative array method
a_array.last(index);
$display("\Last entry is \t a_array[%0d] = %0d", index, a_array[index]);
end
endmodule
| 7.07465
|
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
genvar i;
wire [98:0] con_vect;
one_bit_FA FA1 (
a[0],
b[0],
cin,
con_vect[0],
sum[0]
);
one_bit_FA FA2 (
a[99],
b[99],
con_vect[98],
cout,
sum[99]
);
//this is a generte block
//The loop generate construct provides an easy and concise method to create multiple instances
//of module items such as module instances, assign statements, assertions, interface instances
//In essence generate block is a special type of for loop with the loop index variable of datatype genvar.
generate
for (i = 1; i < 99; i = i + 1) begin : Full_adder_block
one_bit_FA FA (
a[i],
b[i],
con_vect[i-1],
con_vect[i],
sum[i]
);
end
endgenerate
endmodule
| 7.203305
|
module one_bit_FA (
input a,
b,
input cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule
| 7.125037
|
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*) begin
case (code)
8'h45: begin
out = 0;
valid = 1;
end
8'h16: begin
out = 1;
valid = 1;
end
8'h1e: begin
out = 2;
valid = 1;
end
8'h26: begin
out = 3;
valid = 1;
end
8'h25: begin
out = 4;
valid = 1;
end
8'h2e: begin
out = 5;
valid = 1;
end
8'h36: begin
out = 6;
valid = 1;
end
8'h3d: begin
out = 7;
valid = 1;
end
8'h3e: begin
out = 8;
valid = 1;
end
8'h46: begin
out = 9;
valid = 1;
end
default: begin
valid = 0;
out = 0;
end
endcase
end
endmodule
| 7.203305
|
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: out = data0;
3'b001: out = data1;
3'b010: out = data2;
3'b011: out = data3;
3'b100: out = data4;
3'b101: out = data5;
default: out = 4'b0000;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [254:0] in,
output [ 7:0] out
);
//A "population count" circuit counts the number of '1's in an input vector.
integer i;
reg [7:0] counter;
always @(in) begin
counter = 0;
for (i = 0; i < 255; i = i + 1) begin
if (in[i] == 1'b1) counter = counter + 1'b1;
end
out = counter;
end
endmodule
| 7.203305
|
module top_module (
//clocking signal cannot be referenced anywhere in the always block
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset) begin
//this is an active high asynchronous reset
if (areset == 1'b1) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[3] && in[2] && in[1] && in[0];
assign out_or = in[3] || in[2] || in[1] || in[0];
assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = c & (~b | ~c | d) & (~a | ~c | d);
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output reg [7:0] q
);
wire [7:0] con1, con2, con3;
my_dff8 d_flop1 (
.clk(clk),
.d (d),
.q (con1)
);
my_dff8 d_flop2 (
.clk(clk),
.d (con1),
.q (con2)
);
my_dff8 d_flop3 (
.clk(clk),
.d (con2),
.q (con3)
);
always @(*) begin
case (sel)
0: q = d;
1: q = con1;
2: q = con2;
3: q = con3;
endcase
/*if(sel==2'b00)
q=d;
else if( sel == 2'b01)
q = con1;
else if( sel == 2'b10)
q = con2;
else if( sel == 2'b11)
q = con3;
*/
end
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
input in3,
output out
);
wire wire1;
assign wire1 = ~(in1 ^ in2);
assign out = wire1 ^ in3;
endmodule
| 7.203305
|
module D_FF (
q,
d,
clk,
clear,
preset
);
output q;
input d, clk, clear, preset;
reg q;
always @(posedge clk) begin
if (!clear) q <= 1'b0;
else if (!preset) q <= 1'b1;
else q <= d;
end
endmodule
| 7.143509
|
module JK_FF (
q,
j,
k,
clk,
reset
);
output q;
input j, k, clk, reset;
reg q;
always @(posedge clk) begin
if (!reset) q <= 1'b0;
else if ({j, k} == 2'b00) q <= q;
else if ({j, k} == 2'b01) q <= 1'b0;
else if ({j, k} == 2'b10) q <= 1'b1;
else q <= ~q;
end
endmodule
| 6.715426
|
module Mealy_Zero_Dector (
y_out,
x_in,
clock,
reset
);
output y_out;
input x_in, clock, reset;
reg y_out;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
reg [1:0] state, next_state;
always @(posedge clock, negedge reset) begin
if (!reset) state <= S0;
else state <= next_state;
end
always @(state, x_in) begin
case (state)
S0: begin
y_out = 0;
if (x_in) next_state = S1;
else next_state = S0;
end
S1: begin
y_out = !x_in;
if (x_in) next_state = S3;
else next_state = S0;
end
S2: begin
y_out = !x_in;
if (!x_in) next_state = S0;
else next_state = S2;
end
S3: begin
y_out = !x_in;
if (x_in) next_state = S2;
else next_state = S0;
end
endcase
end
endmodule
| 6.74177
|
module Mealy_Zero_Dector_tb;
reg t_x_in, t_clock, t_reset;
wire t_y_out;
Mealy_Zero_Dector UUT (
t_y_out,
t_x_in,
t_clock,
t_reset
);
initial #200 $finish;
initial begin
t_clock = 0;
forever #5 t_clock = ~t_clock;
end
initial
fork
t_reset = 0;
#2 t_reset = 1;
#87 t_reset = 0;
#89 t_reset = 1;
#10 t_x_in = 1;
#30 t_x_in = 0;
#40 t_x_in = 1;
#50 t_x_in = 0;
#52 t_x_in = 1;
#54 t_x_in = 0;
#80 t_x_in = 1;
#100 t_x_in = 0;
#120 t_x_in = 1;
join
//initial $monitor("t_y_out = %b, t_x_in = %b, t_clock = %b, t_reset = %b", t_y_out, t_x_in, t_clock, t_reset);
//code to generate vcd file from verilog taken from
//https://iverilog.fandom.com/wiki/GTKWAVE
initial begin
$dumpfile("5-27.vcd");
$dumpvars(0, Mealy_Zero_Dector_tb);
end
endmodule
| 6.74177
|
module D_flipflop (
q,
d,
clk,
reset
);
output q;
input d, clk, reset;
reg q;
always @(posedge clk, negedge reset) begin
if (!reset) q <= 1'b0;
else q <= d;
end
endmodule
| 7.12701
|
module D_flipflop (
Q,
D,
Clk,
Rst
);
output Q;
input D, Clk, Rst;
reg Q;
always @(posedge Clk, negedge Rst)
if (!Rst) Q <= 1'b0;
else Q <= D;
endmodule
| 7.12701
|
module mux_2x1 (
y,
s,
d
);
output y;
input s;
input [1:0] d;
wire not_s, d0_out, d1_out;
not (not_s, s);
nand (d0_out, not_s, d[0]);
nand (d1_out, s, d[1]);
nand (y, d0_out, d1_out);
endmodule
| 6.925133
|
module ex_5_35 (
z,
x,
y,
Clk,
Rst
);
output z;
input x, y, Clk, Rst;
wire Qa, Qb, Da, Db;
assign Da = ~x & y | x & Qa;
assign Db = x & Qa | ~x & Qb;
assign z = Qb;
D_flipflop a (
Qa,
Da,
Clk,
Rst
);
D_flipflop b (
Qb,
Db,
Clk,
Rst
);
endmodule
| 6.793018
|
module ex_5_35 (
z,
x,
y,
clk,
rst
);
output z;
input x, y, clk, rst;
reg z;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
parameter I0 = 2'b00, I1 = 2'b01, I2 = 2'b10, I3 = 2'b11;
reg [1:0] state, next_state;
//current state logic
always @(posedge clk, negedge rst) begin
if (!rst) begin
state <= S0;
next_state <= S0;
end else state <= next_state;
end
//next state logic
always @(state, x, y) begin
case (state)
S0: begin
case ({
x, y
})
I0, I2, I3: begin
z = 0;
next_state = S0;
end
I1: begin
z = 0;
next_state = S2;
end
endcase
end
S1: begin
case ({
x, y
})
I0: begin
z = 1;
next_state = S1;
end
I1: begin
z = 1;
next_state = S3;
end
I2, I3: begin
z = 1;
next_state = S0;
end
endcase
end
S2: begin
case ({
x, y
})
I0: begin
z = 0;
next_state = S0;
end
I1: begin
z = 0;
next_state = S2;
end
I2, I3: begin
z = 0;
next_state = S3;
end
endcase
end
S3: begin
case ({
x, y
})
I0: begin
z = 1;
next_state = S1;
end
I1, I2, I3: begin
z = 1;
next_state = S3;
end
endcase
end
endcase
end
endmodule
| 6.793018
|
module fig_25 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101, g = 3'b110;
reg [2:0] state, next_state;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= a;
else state <= next_state;
end
// next state and output logic
always @(state, x) begin
case (state)
a: begin
y = 0;
if (x) next_state = b;
else next_state = a;
end
b: begin
y = 0;
if (x) next_state = d;
else next_state = c;
end
c: begin
y = 0;
if (x) next_state = d;
else next_state = a;
end
d:
if (x) begin
y = 1;
next_state = f;
end else begin
y = 0;
next_state = e;
end
e:
if (x) begin
y = 1;
next_state = f;
end else begin
y = 0;
next_state = a;
end
f:
if (x) begin
y = 1;
next_state = f;
end else begin
y = 0;
next_state = g;
end
g:
if (x) begin
y = 1;
next_state = f;
end else begin
y = 0;
next_state = a;
end
default: begin
y = 0;
next_state = a;
end
endcase
end
endmodule
| 7.262002
|
module fig_26 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100;
reg [2:0] state, next_state;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= a;
else state <= next_state;
end
// next state and output logic
always @(state, x) begin
case (state)
a: begin
y = 0;
if (x) next_state = b;
else next_state = a;
end
b: begin
y = 0;
if (x) next_state = d;
else next_state = c;
end
c: begin
y = 0;
if (x) next_state = d;
else next_state = a;
end
d:
if (x) begin
y = 1;
next_state = d;
end else begin
y = 0;
next_state = e;
end
e:
if (x) begin
y = 1;
next_state = d;
end else begin
y = 0;
next_state = a;
end
default: begin
y = 0;
next_state = a;
end
endcase
end
endmodule
| 7.540456
|
module ex_5_38_a (
out,
x,
clk,
rst
);
output [1:0] out;
input x, clk, rst;
reg [1:0] out, state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
// next state logic
always @(state, x) begin
case (state)
S0: begin
out = S0;
if (x) next_state = S2;
else next_state = S0;
end
S1: begin
out = S1;
if (x) next_state = S0;
else next_state = S1;
end
S2: begin
out = S2;
if (x) next_state = S3;
else next_state = S2;
end
S3: begin
out = S3;
if (x) next_state = S1;
else next_state = S3;
end
endcase
end
endmodule
| 7.107596
|
module ex_5_38_b (
out,
x,
clk,
rst
);
output [1:0] out;
input x, clk, rst;
reg [1:0] out, state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
// next state logic
always @(state, x) begin
case (state)
S0: begin
out = S0;
if (x) next_state = S3;
else next_state = S0;
end
S1: begin
out = S1;
if (x) next_state = S0;
else next_state = S1;
end
S2: begin
out = S2;
if (x) next_state = S1;
else next_state = S2;
end
S3: begin
out = S3;
if (x) next_state = S2;
else next_state = S3;
end
endcase
end
endmodule
| 6.887892
|
module ex_5_39 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y, state, next_state;
parameter S0 = 1'b0, S1 = 1'b1;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
// next state logic
always @(state, x) begin
case (state)
S0:
if (x == 1) begin
y = 1;
next_state = S1;
end else if (x == 0) begin
y = 0;
next_state = S0;
end
S1:
if (x == 1) begin
y = 0;
next_state = S1;
end else if (x == 0) begin
y = 1;
next_state = S1;
end
endcase
end
endmodule
| 7.649654
|
module ex_5_40 (
out,
E,
F,
clk,
rst
);
output [1:0] out;
input E, F, clk, rst;
reg [1:0] out, state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
// next state logic
always @(state, E, F) begin
case (state)
S0: begin
out = S0;
if (E == 0) next_state = S0;
else if ({E, F} == 2'b11) next_state = S3;
else if ({E, F} == 2'b10) next_state = S1;
end
S1: begin
out = S1;
if (E == 0) next_state = S1;
else if ({E, F} == 2'b11) next_state = S0;
else if ({E, F} == 2'b10) next_state = S2;
end
S2: begin
out = S2;
if (E == 0) next_state = S2;
else if ({E, F} == 2'b11) next_state = S1;
else if ({E, F} == 2'b10) next_state = S3;
end
S3: begin
out = S3;
if (E == 0) next_state = S3;
else if ({E, F} == 2'b11) next_state = S2;
else if ({E, F} == 2'b10) next_state = S0;
end
endcase
end
endmodule
| 6.863803
|
module ex_5_41 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100;
reg [2:0] state, next_state;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
// next state logic
always @(state, x_in) begin
case (state)
S0:
if (x_in == 1) begin
y_out = 1;
next_state = S4;
end else if (x_in == 0) begin
y_out = 0;
next_state = S3;
end
S1:
if (x_in == 1) begin
y_out = 1;
next_state = S4;
end else if (x_in == 0) begin
y_out = 0;
next_state = S1;
end
S2:
if (x_in == 1) begin
y_out = 1;
next_state = S0;
end else if (x_in == 0) begin
y_out = 0;
next_state = S2;
end
S3:
if (x_in == 1) begin
y_out = 1;
next_state = S2;
end else if (x_in == 0) begin
y_out = 0;
next_state = S1;
end
S4:
if (x_in == 1) begin
y_out = 0;
next_state = S3;
end else if (x_in == 0) begin
y_out = 0;
next_state = S2;
end
default: begin
y_out = 0;
next_state = S0;
end
endcase
end
endmodule
| 8.155915
|
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086
|
module ex_5_43 (
out,
clk,
rst
);
output [2:0] out;
input clk, rst;
reg [2:0] out, state, next_state;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100,
S5 = 3'b101, S6 = 3'b110, S7 = 3'b111;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
// next state logic
always @(state) begin
case (state)
S0: begin
out = S0;
next_state = S1;
end
S1: begin
out = S1;
next_state = S2;
end
S2: begin
out = S2;
next_state = S3;
end
S3: begin
out = S3;
next_state = S4;
end
S4: begin
out = S4;
next_state = S5;
end
S5: begin
out = S5;
next_state = S6;
end
S6: begin
out = S6;
next_state = S7;
end
S7: begin
out = S7;
next_state = S0;
end
endcase
end
endmodule
| 7.134347
|
module ex_5_44 (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 6.536317
|
module ex_5_44_tb;
reg d, clk, rst;
wire q;
ex_5_44 UUT (
q,
d,
clk,
rst
);
initial #100 $finish;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
fork
rst = 1;
#1 rst = 0;
#10 rst = 1;
#10 d = 1;
#30 d = 0;
#40 rst = 0;
#46 rst = 1;
#50 d = 1;
join
initial begin
$dumpfile("5-44.vcd");
$dumpvars(0, ex_5_44_tb);
end
endmodule
| 6.609506
|
module ex_5_45 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
// next state logic
always @(state, x) begin
case (state)
S0: begin
y = 0;
if (x == 1) next_state = S1;
else if (x == 0) next_state = S0;
end
S1: begin
y = 0;
if (x == 1) next_state = S2;
else if (x == 0) next_state = S0;
end
S2: begin
y = 0;
if (x == 1) next_state = S3;
else if (x == 0) next_state = S0;
end
S3: begin
y = 1;
if (x == 1) next_state = S3;
else if (x == 0) next_state = S0;
end
endcase
end
endmodule
| 7.734839
|
module ex_5_46 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
reg [2:0] state, next_state;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
// present state logic
always @(posedge clk) begin
if (!rst) state <= S0;
else state <= next_state;
end
//next state logic
always @(state, x_in) begin
case (state)
S0: begin
y_out = 0;
if (x_in) next_state = S1;
else next_state = S0;
end
S1: begin
y_out = 1;
next_state = S2;
end
S2: begin
y_out = 1;
next_state = S3;
end
S3: begin
y_out = 1;
next_state = S4;
end
S4: begin
y_out = 0;
next_state = S5;
end
S5: begin
y_out = 0;
next_state = S0;
end
default: begin
y_out = 0;
next_state = S0;
end
endcase
end
endmodule
| 7.408872
|
module ex_5_47 (
out,
run,
clk,
rst
);
output [3:0] out;
input run, clk, rst;
reg [3:0] out;
reg [3:0] state, next_state;
parameter S0 = 4'b0000, S2 = 4'b0010, S4 = 4'b0100, S6 = 4'b0110,
S8 = 4'b1000, S10 = 4'b1010, S12 = 4'b1100, S14 = 4'b1110;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
//next state logic
always @(state, run) begin
case (state)
S0: begin
out = S0;
if (run) next_state = S2;
else next_state = S0;
end
S2: begin
out = S2;
if (run) next_state = S4;
else next_state = S2;
end
S4: begin
out = S4;
if (run) next_state = S6;
else next_state = S4;
end
S6: begin
out = S6;
if (run) next_state = S8;
else next_state = S6;
end
S8: begin
out = S8;
if (run) next_state = S10;
else next_state = S8;
end
S10: begin
out = S10;
if (run) next_state = S12;
else next_state = S10;
end
S12: begin
out = S12;
if (run) next_state = S14;
else next_state = S12;
end
S14: begin
out = S14;
if (run) next_state = S0;
else next_state = S14;
end
default: begin
out = S0;
next_state = S0;
end
endcase
end
endmodule
| 7.464571
|
module ex_5_48 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
reg [1:0] state, next_state;
parameter a = 2'b00, b = 2'b01, c = 2'b10, d = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= a;
else state <= next_state;
end
//next state logic
always @(state, x) begin
case (state)
a:
if (x) begin
y = 0;
next_state = c;
end else begin
y = 1;
next_state = b;
end
b:
if (x) begin
y = 1;
next_state = d;
end else begin
y = 0;
next_state = c;
end
c:
if (x) begin
y = 1;
next_state = d;
end else begin
y = 0;
next_state = b;
end
d:
if (x) begin
y = 0;
next_state = a;
end else begin
y = 1;
next_state = c;
end
endcase
end
endmodule
| 7.430051
|
module ex_5_49 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
reg [1:0] state, next_state;
parameter a = 2'b00, b = 2'b01, c = 2'b10, d = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= a;
else state <= next_state;
end
//next state logic
always @(state, x) begin
case (state)
a: begin
y = 0;
if (x) next_state = c;
else next_state = b;
end
b: begin
y = 1;
if (x) next_state = d;
else next_state = c;
end
c: begin
y = 1;
if (x) next_state = d;
else next_state = b;
end
d: begin
y = 0;
if (x) next_state = a;
else next_state = c;
end
endcase
end
endmodule
| 7.30666
|
module ex_5_50 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
reg [2:0] state, next_state;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
//next state logic
always @(state, x_in) begin
case (state)
S0: begin
y_out = 0;
if (x_in) next_state = S1;
else next_state = S0;
end
S1: begin
y_out = 0;
if (x_in) next_state = S2;
else next_state = S1;
end
S2: begin
y_out = 1;
if (x_in) next_state = S3;
else next_state = S2;
end
S3: begin
y_out = 1;
if (x_in) next_state = S4;
else next_state = S3;
end
S4: begin
y_out = 0;
next_state = S0;
end
default: begin
y_out = 0;
next_state = S0;
end
endcase
end
endmodule
| 7.684029
|
module ex_5_53 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
//present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
//next state logic
always @(state, x_in) begin
case (state)
S0:
if (x_in) begin
y_out = 0;
next_state = S1;
end else begin
y_out = 1;
next_state = S0;
end
S1:
if (x_in) begin
y_out = 0;
next_state = S2;
end else begin
y_out = 0;
next_state = S1;
end
S2:
if (x_in) begin
y_out = 1;
next_state = S3;
end else begin
y_out = 0;
next_state = S2;
end
S3:
if (x_in) begin
y_out = 0;
next_state = S1;
end else begin
y_out = 1;
next_state = S0;
end
endcase
end
endmodule
| 7.034911
|
module ex_5_53 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out, out;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
//present state logic
always @(posedge clk, negedge rst) begin
if (!rst) begin
state <= S0;
y_out <= 1;
end else begin
state <= next_state;
y_out <= out;
end
end
//next state logic
always @(state, x_in) begin
case (state)
S0:
if (x_in) begin
out = 0;
next_state = S1;
end else begin
out = 1;
next_state = S0;
end
S1:
if (x_in) begin
out = 0;
next_state = S2;
end else begin
out = 0;
next_state = S1;
end
S2:
if (x_in) begin
out = 1;
next_state = S3;
end else begin
out = 0;
next_state = S2;
end
S3:
if (x_in) begin
out = 0;
next_state = S1;
end else begin
out = 1;
next_state = S0;
end
endcase
end
endmodule
| 7.034911
|
module ex_5_54 (
y_out,
x1,
x2,
clk,
rst
);
output y_out;
input x1, x2, clk, rst;
reg y_out, state, next_state;
parameter S0 = 1'b0, S1 = 1'b1;
//present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
//next state logic
always @(state, x1, x2) begin
case (state)
S0: begin
y_out = 0;
case ({
x1, x2
})
2'b00, 2'b11: next_state = S1;
default: next_state = S0;
endcase
end
S1: begin
y_out = 1;
next_state = S0;
end
endcase
end
endmodule
| 8.012166
|
module ex_5_57 (
out,
clk,
rst
);
output [2:0] out;
input clk, rst;
reg [2:0] out;
always @(posedge clk, negedge rst) begin
if (!rst) out = 3'b000;
else if (out >= 3'b110) out = 3'b000;
else out = out + 2;
end
endmodule
| 6.914828
|
module ex_5_58 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
//present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
//next state logic
always @(state, x_in) begin
case (state)
S0:
if (x_in) begin
y_out = 0;
next_state = S1;
end else begin
y_out = 0;
next_state = S0;
end
S1:
if (x_in) begin
y_out = 0;
next_state = S2;
end else begin
y_out = 0;
next_state = S0;
end
S2:
if (x_in) begin
y_out = 1;
next_state = S3;
end else begin
y_out = 0;
next_state = S0;
end
S3:
if (x_in) begin
y_out = 1;
next_state = S3;
end else begin
y_out = 0;
next_state = S0;
end
endcase
end
endmodule
| 7.269246
|
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086
|
module ex_5_60 (
out,
clk,
rst
);
output [3:0] out;
input clk, rst;
reg [3:0] out;
always @(posedge clk, negedge rst) begin
if (!rst) out = 4'b000;
else if (out >= 4'b1001) out = 4'b0000;
else out = out + 1;
end
endmodule
| 6.51768
|
module assign_example;
reg [3:0] a;
wire [3:0] b;
wire [3:0] not_a;
assign b = a;
assign not_a = ~a;
initial begin
a = 4'b0000;
end
always #1 begin
$display("a\t%02d (%b)", a, a);
$display("b\t%02d (%b)", b, b);
$display("not_a\t%02d (%b)\n", not_a, not_a);
a = a + 1;
end
endmodule
| 6.591792
|
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); // I have no idea what are c_load and c_d...
always @(posedge clk) begin
if (reset) Q <= 1;
else if (q == 12 && enable) begin
Q <= 1;
end else if (~enable) begin
Q <= Q;
end else begin
Q <= Q + 1;
end
end
assign c_enable = enable;
assign c_load = (reset | (Q == 12 && enable));
assign c_d = c_load ? 1 : 0;
reg [3:0] q;
count4 the_counter (
clk,
c_enable,
c_load,
c_d,
q
);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk, posedge areset) begin
if (areset) q <= 0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
2'b00: begin
next_state = in ? B : A;
out = 0;
end
2'b01: begin
next_state = in ? B : C;
out = 0;
end
2'b10: begin
next_state = in ? D : A;
out = 0;
end
2'b11: begin
next_state = in ? B : C;
out = 1;
end
endcase
end
// Output logic: out = f(state) for a Moore state machine
endmodule
| 7.203305
|
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR
); // Q
always @(posedge KEY[0]) begin
LEDR[0] <= KEY[1] == 1 ? SW[0] : LEDR[2];
LEDR[1] <= KEY[1] == 1 ? SW[1] : LEDR[0];
LEDR[2] <= KEY[1] == 1 ? SW[2] : LEDR[2] ^ LEDR[1];
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = c & d | ~a & ~b & c;
assign out_pos = ~(~c | ~a & b & c & ~d | a & c & ~d);
endmodule
| 7.203305
|
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = in[sel*4+:4]; // bit slicing in verilog 2001
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
// 2's complement for a binary number is found by inverting the numbers and adding 1
// i.e: 2's complement of 0011 is : 1100+0001 = 1101
//
// Also remember that MSB of the 2's complement number represents the sign. i.e if MSB is one then the number is -ve
// i.e: 1101 = -8 + 4 + 0 + 1 = -3
//
// If 2 = 0010 then -2 = 1101 + 1 = 1110
// Also 2+(-2) = 1111 (This property holds for all the numbers)
//
// While adding two 2's complement numbers, overflow can be detected two ways:
// 1. If carry out and crry-on to MSB are different then overflow occured
// 2. If both numbers are +ve and result is-ve or vise versa, overflow occurs
assign s = a + b;
assign overflow = (a[7] & b[7] & ~s[7]) | (~a[7] & ~b[7] & s[7]);
endmodule
| 7.203305
|
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output [0:0] io_occupancy,
input clk,
input reset
);
wire [0:0] _zz_5_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire [32:0] _zz_2_;
wire [32:0] _zz_3_;
reg [32:0] _zz_4_;
assign _zz_5_ = _zz_2_[0 : 0];
always @(*) begin
_zz_1_ = 1'b0;
pushPtr_willIncrement = 1'b0;
if (pushing) begin
_zz_1_ = 1'b1;
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
popPtr_willClear = 1'b0;
if (io_flush) begin
pushPtr_willClear = 1'b1;
popPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = 1'b1;
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
popPtr_willIncrement = 1'b0;
if (popping) begin
popPtr_willIncrement = 1'b1;
end
end
assign popPtr_willOverflowIfInc = 1'b1;
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
assign ptrMatch = 1'b1;
assign empty = (ptrMatch && (!risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (!full);
always @(*) begin
if ((!empty)) begin
io_pop_valid = 1'b1;
io_pop_payload_error = _zz_5_[0];
io_pop_payload_inst = _zz_2_[32 : 1];
end else begin
io_pop_valid = io_push_valid;
io_pop_payload_error = io_push_payload_error;
io_pop_payload_inst = io_push_payload_inst;
end
end
assign _zz_2_ = _zz_3_;
assign io_occupancy = (risingOccupancy && ptrMatch);
assign _zz_3_ = _zz_4_;
always @(posedge clk) begin
if (reset) begin
risingOccupancy <= 1'b0;
end else begin
if ((pushing != popping)) begin
risingOccupancy <= pushing;
end
if (io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
always @(posedge clk) begin
if (_zz_1_) begin
_zz_4_ <= {io_push_payload_inst, io_push_payload_error};
end
end
endmodule
| 7.046487
|
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = ~(in1 ^ in2) ^ in3;
endmodule
| 7.203305
|
module top_module ();
reg clk;
dut clock (clk);
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
/*
initial begin
clk = 1'b0;
end
always begin
#5
clk = ~clk;
end
*/
endmodule
| 6.627149
|
module top_module (
output reg A,
output reg B
); //
// generate input patterns here
initial begin
A = 1'b0;
B = 1'b0;
#10;
A = 1'b1;
#5 B = 1'b1;
#5 A = 1'b0;
#20 B = 1'b0;
end
endmodule
| 7.203305
|
module top_module ();
reg [1:0] in;
initial begin
in = 2'b00;
#10 in = 2'b01;
#10 in = 2'b10;
#10 in = 2'b11;
end
wire out;
andgate u_and (
in,
out
);
endmodule
| 6.627149
|
module top_module ();
reg clk;
reg in;
reg [2:0] s;
wire out;
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
in = 1'b0;
s = 3'd2;
#10;
in = 1'b0;
s = 3'd6;
#10;
in = 1'b1;
s = 3'd2;
#10;
in = 1'b0;
s = 3'd7;
#10;
in = 1'b1;
s = 3'd0;
#30;
in = 1'b0;
s = 3'd0;
end
q7 u_q7 (
clk,
in,
s,
out
);
endmodule
| 6.627149
|
module top_module ();
reg clk;
reg reset;
reg t;
wire q;
initial begin
clk = 0;
reset = 0;
t = 0;
#3;
reset = 1'b1;
#10;
reset = 1'b0;
end
always begin
#5 clk = ~clk;
end
always @(posedge clk) begin
if (reset) begin
t <= 1'b0;
end else begin
t <= 1'b1;
end
end
tff u_tff (
clk,
reset,
t,
q
);
endmodule
| 6.627149
|
module mips_signal_extend (
inmediate_data,
extend_data
);
input [15:0] inmediate_data;
output [31:0] extend_data;
assign extend_data = {{(16) {inmediate_data[15]}}, inmediate_data};
endmodule
| 6.591839
|
module top_module (
input clk,
input reset, // 高电平有效
input in,
output reg disc,
output reg flag,
output reg err
);
reg [63:0] one_num;
reg last;
initial begin
disc = 0;
flag = 0;
err = 0;
one_num = 0;
last = 0;
end
always @(posedge clk) begin
if (last == 0) begin
one_num = 0;
end
if (in) begin
one_num = one_num + 1;
if (one_num > 6) err = 1;
last = 1;
end else begin
if (disc) disc = 0;
else if (flag) begin
flag = 0;
one_num = 0;
end else if (err) begin
err = 0;
one_num = 0;
end else begin
if (one_num == 5) disc = 1;
else if (one_num == 6) flag = 1;
else if (one_num >= 7) err = 1;
one_num = 0;
end
end
end
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
| 7.203305
|
modules
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALUSystem(
input[1:0] RF_OutASel,
input[1:0] RF_OutBSel,
input[1:0] RF_FunSel,
input[3:0] RF_RegSel,
input[3:0] ALU_FunSel,
input[1:0] ARF_OutCSel,
input[1:0] ARF_OutDSel,
input[1:0] ARF_FunSel,
input[2:0] ARF_RegSel,
input IR_LH,
input IR_Enable,
input[1:0] IR_Funsel,
input Mem_WR,
input Mem_CS,
input[1:0] MuxASel,
input[1:0] MuxBSel,
input MuxCSel,
input Clock
);
wire[7:0] AOut,BOut; //Register file out
wire[7:0] ALUOut; //ALU out
wire[3:0] ALUOutFlag; //ALU out flag
wire[7:0] ARF_COut, Address; //ARF out
wire[7:0] MemoryOut;
wire[15:0] IROut;
wire[7:0] MuxAOut, MuxBOut, MuxCOut;
// wire [7:0] irout8;
// assign irout8 = IROut[7:0];
registerFile registerFile(MuxAOut, RF_OutASel, RF_OutBSel, RF_FunSel, RF_RegSel,Clock, AOut,BOut);
muxc muxC(ARF_COut, AOut, MuxCSel, MuxCOut);
alu ALU(MuxCOut, BOut, ALU_FunSel, ALUOut, ALUOutFlag);
Memory MEM(Address, ALUOut, Mem_WR, Mem_CS,Clock,MemoryOut);
addressRegisterFile ARF(MuxBOut, ARF_OutCSel, ARF_OutDSel, ARF_FunSel, ARF_RegSel, Clock,ARF_COut, Address);
mux muxB(8'bxxxxxxxx,IROut[7:0], MemoryOut,ALUOut,MuxBSel,MuxBOut );
registerIR IR(MemoryOut, IR_LH, IR_Enable, IR_Funsel, Clock, IROut);
mux muxA(IROut[7:0], MemoryOut,ARF_COut,ALUOut,MuxASel,MuxAOut );
endmodule
| 6.685557
|
module Memory (
input wire [7:0] address,
input wire [7:0] data,
input wire wr,
input wire cs,
input wire clock,
output reg [7:0] o
);
reg [7:0] RAM_DATA[0:255];
initial $readmemh("RAM.mem", RAM_DATA);
always @(*) begin
o = ~wr && ~cs ? RAM_DATA[address] : 8'hz;
end
always @(posedge clock) begin
if (wr && ~cs) begin
RAM_DATA[address] <= data;
end
end
endmodule
| 7.051739
|
module funcRegister8 (
CLK,
E,
Din,
Dout,
FunSel
);
input CLK;
input E;
input [7:0] Din; // Data input for load
output reg [7:0] Dout;
input [1:0] FunSel;
always @(posedge CLK) begin
if (E) begin // Enable is on
case (FunSel)
2'b00: Dout <= Dout - 1; // decrement
2'b01: Dout <= Dout + 1; // increment
2'b10: Dout <= Din; // load
2'b11: Dout <= 8'b00000000; // clear
default: begin
end
endcase // switch case end
end // if end
else // Enable is off
Dout = Dout; // retain value
end // always end
endmodule
| 7.306831
|
module funcRegister16 (
CLK,
E,
Din,
Dout,
FunSel
);
input CLK;
input E;
input [15:0] Din; // Data input for load
output reg [15:0] Dout;
input [1:0] FunSel;
always @(posedge CLK) begin
if (E) begin // Enable is on
case (FunSel)
2'b00: Dout <= Dout - 1; // decrement
2'b01: Dout <= Dout + 1; // increment
2'b10: Dout <= Din; // load
2'b11: Dout <= 16'b0000000000000000; // clear
default: begin
end
endcase // switch case end
end // if end
else // Enable is off
Dout = Dout; // retain value
end // always end
endmodule
| 7.635491
|
module registerFile (
Data_in,
OutASel,
OutBSel,
FunSel,
RegSel,
CLK,
Data_out_A,
Data_out_B
);
input CLK;
input [1:0] OutASel;
input [1:0] OutBSel;
input [1:0] FunSel;
input [3:0] RegSel;
input [7:0] Data_in; // Data input for load
output wire [7:0] Data_out_A; // data out A
output wire [7:0] Data_out_B; // data out B
wire [7:0] temp0, temp1, temp2, temp3;
funcRegister8 reg1 (
CLK,
~RegSel[0],
Data_in,
temp0,
FunSel
);
funcRegister8 reg2 (
CLK,
~RegSel[1],
Data_in,
temp1,
FunSel
);
funcRegister8 reg3 (
CLK,
~RegSel[2],
Data_in,
temp2,
FunSel
);
funcRegister8 reg4 (
CLK,
~RegSel[3],
Data_in,
temp3,
FunSel
);
mux MUX1 (
temp3,
temp2,
temp1,
temp0,
OutASel,
Data_out_A
);
mux MUX2 (
temp3,
temp2,
temp1,
temp0,
OutBSel,
Data_out_B
);
endmodule
| 6.674499
|
module addressRegisterFile (
Data_in,
OutCSel,
OutDSel,
FunSel,
RegSel,
CLK,
Data_out_C,
Data_out_D
);
input CLK;
input [1:0] OutCSel;
input [1:0] OutDSel;
input [1:0] FunSel;
input [2:0] RegSel;
input [7:0] Data_in; // Data input for load
output [7:0] Data_out_C; // data out A
output [7:0] Data_out_D; // data out B
wire [7:0] temp1, temp2, temp3;
funcRegister8 PC (
CLK,
~RegSel[0],
Data_in,
temp1,
FunSel
);
funcRegister8 AR (
CLK,
~RegSel[1],
Data_in,
temp2,
FunSel
);
funcRegister8 SP (
CLK,
~RegSel[2],
Data_in,
temp3,
FunSel
);
mux MUX1 (
temp1,
temp1,
temp2,
temp3,
OutCSel,
Data_out_C
);
mux MUX2 (
temp1,
temp1,
temp2,
temp3,
OutDSel,
Data_out_D
);
endmodule
| 6.628698
|
module registerIR (
IRin,
LowHigh,
Enable,
FunSel,
CLK,
IRout
);
input [7:0] IRin;
input LowHigh;
input Enable;
input [1:0] FunSel;
input CLK;
output reg [15:0] IRout;
always @(posedge CLK) begin
if (Enable) begin // Enable is on
case (FunSel)
2'b00: IRout <= IRout - 1; // decrement
2'b01: IRout <= IRout + 1; // increment
2'b10: begin
if (LowHigh) IRout[7:0] = IRin;
else IRout[15:8] = IRin;
end
2'b11: IRout <= 16'b0000000000000000; // clear
default: begin
end
endcase // switch case end
end // if end
end // always end
endmodule
| 6.910474
|
module mux (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
input [1:0] sel,
output [7:0] out
);
assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);
endmodule
| 7.422932
|
module muxc (
input [7:0] a,
input [7:0] b,
input [0:0] sel,
output [7:0] out
);
assign out = (sel) ? b : a;
endmodule
| 9.429976
|
module Project1Test ();
//Input Registers of ALUSystem
reg [1:0] RF_OutASel;
reg [1:0] RF_OutBSel;
reg [1:0] RF_FunSel;
reg [3:0] RF_RegSel;
reg [3:0] ALU_FunSel;
reg [1:0] ARF_OutCSel;
reg [1:0] ARF_OutDSel;
reg [1:0] ARF_FunSel;
reg [2:0] ARF_RegSel;
reg IR_LH;
reg IR_Enable;
reg [1:0] IR_Funsel;
reg Mem_WR;
reg Mem_CS;
reg [1:0] MuxASel;
reg [1:0] MuxBSel;
reg MuxCSel;
reg Clock;
//Test Bench Connection of ALU System
ALUSystem _ALUSystem (
.RF_OutASel(RF_OutASel),
.RF_OutBSel(RF_OutBSel),
.RF_FunSel(RF_FunSel),
.RF_RegSel(RF_RegSel),
.ALU_FunSel(ALU_FunSel),
.ARF_OutCSel(ARF_OutCSel),
.ARF_OutDSel(ARF_OutDSel),
.ARF_FunSel(ARF_FunSel),
.ARF_RegSel(ARF_RegSel),
.IR_LH(IR_LH),
.IR_Enable(IR_Enable),
.IR_Funsel(IR_Funsel),
.Mem_WR(Mem_WR),
.Mem_CS(Mem_CS),
.MuxASel(MuxASel),
.MuxBSel(MuxBSel),
.MuxCSel(MuxCSel),
.Clock(Clock)
);
//Test Vector Variables
reg [31:0] VectorNum, Errors, TotalLine;
reg [34:0] TestVectors[10000:0];
reg Reset, Operation;
//Clock Signal Generation
always begin
Clock = 1;
#5;
Clock = 0;
#5; // 10ns period
end
//Read Test Bench Values
initial begin
$readmemb("TestBench.mem", TestVectors); // Read vectors
VectorNum = 0;
Errors = 0;
TotalLine = 0;
Reset = 0; // Initialize
end
// Apply test vectors on rising edge of clock
always @(posedge Clock) begin
#1;
{Operation, RF_OutASel, RF_OutBSel, RF_FunSel,
RF_RegSel, ALU_FunSel, ARF_OutCSel, ARF_OutDSel,
ARF_FunSel, ARF_RegSel, IR_LH, IR_Enable, IR_Funsel,
Mem_WR, Mem_CS, MuxASel, MuxBSel, MuxCSel} = TestVectors[VectorNum];
end
// Check results on falling edge of clk
always @(negedge Clock)
if (~Reset) // skip during reset
begin
$display("");
$display("");
$display("Input Values:");
$display("Operation: %b", Operation);
$display("Register File: OutASel: %b, OutBSel: %b, FunSel: %b, Regsel: %b", RF_OutASel,
RF_OutBSel, RF_FunSel, RF_RegSel);
$display("ALU FunSel: %b", ALU_FunSel);
$display("Addres Register File: OutCSel: %b, OutDSel: %b, FunSel: %b, Regsel: %b",
ARF_OutCSel, ARF_OutDSel, ARF_FunSel, ARF_RegSel);
$display("Instruction Register: LH: %b, Enable: %b, FunSel: %b", IR_LH, IR_Enable, IR_Funsel);
$display("Memory: WR: %b, CS: %b", Mem_WR, Mem_CS);
$display("MuxASel: %b, MuxBSel: %b, MuxCSel: %b", MuxASel, MuxBSel, MuxCSel);
$display("");
$display("Ouput Values:");
$display("Register File: AOut: %b, BOut: %b", _ALUSystem.AOut, _ALUSystem.BOut);
$display("ALUOut: %b, ALUOutFlag: %b, ALUOutFlags: Z:%b, C:%b, N:%b, O:%b,",
_ALUSystem.ALUOut, _ALUSystem.ALUOutFlag, _ALUSystem.ALUOutFlag[3],
_ALUSystem.ALUOutFlag[2], _ALUSystem.ALUOutFlag[1], _ALUSystem.ALUOutFlag[0]);
$display("Address Register File: COut: %b, DOut (Address): %b", _ALUSystem.ARF_COut,
_ALUSystem.Address);
$display("Memory Out: %b", _ALUSystem.MemoryOut);
$display("Instruction Register: IROut: %b", _ALUSystem.IROut);
$display("MuxAOut: %b, MuxBOut: %b, MuxCOut: %b", _ALUSystem.MuxAOut, _ALUSystem.MuxBOut,
_ALUSystem.MuxCOut);
// increment array index and read next testvector
VectorNum = VectorNum + 1;
if (TestVectors[VectorNum] === 35'bx) begin
$display("%b tests completed.", VectorNum);
$finish; // End simulation
end
end
endmodule
| 7.239416
|
module register_8_bitTestBench ();
reg [0:0] E;
reg [7:0] I;
reg [1:0] FunSel;
reg clock = 1;
wire [7:0] Q;
always #5 clock = ~clock;
funcRegister8 uut (
.CLK(clock),
.E(E),
.Din(I),
.Dout(Q),
.FunSel(FunSel)
);
initial begin
#0 FunSel = 2'b11; // load
I = 8'b00000000;
E = 1;
#10 FunSel = 2'b11; // load
I = 8'b00000000;
E = 1;
#20 FunSel = 2'b10; // load
I = 8'b00000010;
E = 1;
#30 FunSel = 2'b01; // load
I = 8'b00000100;
E = 1;
#40 FunSel = 2'b00; // load
I = 8'b00010000;
E = 1;
end
endmodule
| 6.528516
|
module aluTestBench();
reg [7:0] A;
reg [7:0] B;
reg [3:0] FunSel;
wire [7:0] OutAlu;
wire[3:0] ZCNO;
alu uut( .A(A), .B(B), .FunSel(FunSel), .OutAlu(OutAlu), .ZCNO(ZCNO));
initial begin
A = 8'b01111111;
B = 8'b01111111;
#0 FunSel = 4'b0100; // load
#10FunSel = 4'b0101; // load
#20 FunSel = 4'b0110; // load
#30 FunSel = 4'b0111; // load
#40 FunSel = 4'b0110; // load
#50 FunSel = 4'b0101; // load
end
endmodule
| 6.606495
|
module register_fileTestBench ();
reg [7:0] I;
reg [1:0] OutASel;
reg [1:0] OutBSel;
reg [1:0] FunSel;
reg [3:0] RegSel;
reg clock = 1;
wire [7:0] OutA;
wire [7:0] OutB;
always #5 clock = ~clock;
registerFile uut (
.Data_in(I),
.OutASel(OutASel),
.OutBSel(OutBSel),
.FunSel(FunSel),
.RegSel(RegSel),
.CLK(clock),
.Data_out_A(OutA),
.Data_out_B(OutB)
);
initial begin
#0 I = 8'b00000000;
OutASel = 2'b11;
OutBSel = 2'b11;
FunSel = 2'b11;
RegSel = 4'b0000;
#10 I = 8'b00000000;
OutASel = 2'b11;
OutBSel = 2'b11;
FunSel = 2'b11;
RegSel = 4'b0000;
#20 I = 8'b00000010;
OutASel = 2'b01;
OutBSel = 2'b01;
FunSel = 2'b10;
RegSel = 4'b1111;
#30 I = 8'b00000001;
OutASel = 2'b11;
OutBSel = 2'b11;
FunSel = 2'b01;
RegSel = 4'b0000;
#40 I = 8'b00000001;
OutASel = 2'b11;
OutBSel = 2'b11;
FunSel = 2'b00;
RegSel = 4'b1111;
end
endmodule
| 6.605344
|
module addressRegisterFileTestBench ();
reg [7:0] I;
reg [1:0] OutCSel;
reg [1:0] OutDSel;
reg [1:0] FunSel;
reg [3:0] RegSel;
reg clock = 1;
wire [7:0] Data_out_C;
wire [7:0] Data_out_D;
always #5 clock = ~clock;
addressRegisterFile uut (
.Data_in(I),
.OutCSel(OutCSel),
.OutDSel(OutDSel),
.FunSel(FunSel),
.RegSel(RegSel),
.CLK(clock),
.Data_out_C(Data_out_C),
.Data_out_D(Data_out_D)
);
initial begin
#0 I = 8'b00000000;
OutCSel = 2'b11;
OutDSel = 2'b11;
FunSel = 2'b11;
RegSel = 4'b0000;
#10 I = 8'b00000000;
OutCSel = 2'b11;
OutDSel = 2'b11;
FunSel = 2'b11;
RegSel = 4'b0000;
#20 I = 8'b00000010;
OutCSel = 2'b01;
OutDSel = 2'b01;
FunSel = 2'b10;
RegSel = 4'b1111;
#30 I = 8'b00000001;
OutCSel = 2'b11;
OutDSel = 2'b11;
FunSel = 2'b01;
RegSel = 4'b0000;
#40 I = 8'b00000001;
OutCSel = 2'b11;
OutDSel = 2'b11;
FunSel = 2'b00;
RegSel = 4'b1111;
end
endmodule
| 6.628698
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (~(jnez && (!ZF)));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = '0;
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = '1;
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
always @(*) begin
case ({
x3, x2, x1
})
3'b000: f = 0;
3'b001: f = 0;
3'b010: f = 1;
3'b011: f = 1;
3'b100: f = 0;
3'b101: f = 1;
3'b110: f = 0;
3'b111: f = 1;
endcase
end
endmodule
| 7.203305
|
modules
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALUSystem(
input[1:0] RF_OutASel,
input[1:0] RF_OutBSel,
input[1:0] RF_FunSel,
input[3:0] RF_RegSel,
input[3:0] ALU_FunSel,
input[1:0] ARF_OutCSel,
input[1:0] ARF_OutDSel,
input[1:0] ARF_FunSel,
input[2:0] ARF_RegSel,
input IR_LH,
input IR_Enable,
input[1:0] IR_Funsel,
input Mem_WR,
input Mem_CS,
input[1:0] MuxASel,
input[1:0] MuxBSel,
input MuxCSel,
input Clock
);
wire[7:0] AOut,BOut; //Register file out
wire[7:0] ALUOut; //ALU out
wire[3:0] ALUOutFlag; //ALU out flag
wire[7:0] ARF_COut, Address; //ARF out
wire[7:0] MemoryOut;
wire[15:0] IROut;
wire[7:0] MuxAOut, MuxBOut, MuxCOut;
registerFile registerFile(MuxAOut, RF_OutASel, RF_OutBSel, RF_FunSel, RF_RegSel,Clock, AOut,BOut);
muxc muxC(ARF_COut, AOut, MuxCSel, MuxCOut);
alu ALU(MuxCOut, BOut, ALU_FunSel, ALUOut, ALUOutFlag);
Memory MEM(Address, ALUOut, Mem_WR, Mem_CS,Clock,MemoryOut);
addressRegisterFile ARF(MuxBOut, ARF_OutCSel, ARF_OutDSel, ARF_FunSel, ARF_RegSel, Clock,ARF_COut, Address);
mux muxB(8'bxxxxxxxx ,IROut[7:0], MemoryOut ,ALUOut,MuxBSel,MuxBOut);
registerIR IR(MemoryOut, IR_LH, IR_Enable, IR_Funsel, Clock, IROut);
mux muxA(IROut[7:0], MemoryOut,ARF_COut,ALUOut,MuxASel,MuxAOut );
endmodule
| 6.685557
|
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