code
stringlengths 35
6.69k
| score
float64 6.5
11.5
|
|---|---|
module top_module (
input in1,
input in2,
output out
);
assign out = ~in2 & in1;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = (~{{24{IR[23]}}, IR[23:16]});
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = '0;
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = '1;
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{(~IR[23])}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input a,
b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = ~(a ^ b);
assign out_anotb = a & ~b;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {(~{24{IR[23]}}), IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, (~IR[23:16])};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module FadderTB;
reg [3:0] A;
reg [3:0] B;
wire [3:0] S;
wire CO;
Fadder fa (
A,
B,
S,
CO
);
initial begin
A = 0;
B = 0;
#100;
A <= 4'b0110;
B <= 4'b0011;
#200 A <= 4'b1011;
B <= 4'b0110;
#100;
end
initial begin
$dumpfile("fadder.vcd");
$dumpvars(0, FadderTB);
$monitor($time, ": %b %b => %b %b", A, B, S, CO);
end
endmodule
| 6.539572
|
module Adder_TB ();
reg [15:0] A;
reg [15:0] B;
wire [15:0] CLA_s;
wire [15:0] RCA_s;
wire Cout1;
wire Cout2;
reg Cin;
CLA_16bit CLA (
A,
B,
Cin,
CLA_s,
Cout2
);
RCA_16bit RCA (
A,
B,
Cin,
RCA_s,
Cout1
);
initial begin
#100 A = 16'b0;
B = 16'b0;
Cin = 1'b0;
#600 A = 16'b0001001101100100;
B = 16'b0000000000000001;
Cin = 1'b0;
#600 A = 16'b0000000000001000;
B = 16'b0000000100000000;
Cin = 1'b0;
#600 A = 16'b0000000000000010;
B = 16'b0000000100001111;
Cin = 1'b0; //2+16
#600 A = 16'b1111111111111110;
B = 16'b1111111111111111;
Cin = 1'b0;
#600 A = 16'b0000000000000101;
B = 16'b0000000000000101;
Cin = 1'b0;
#600 A = 16'b0000000000001101;
B = 16'b0000000000001101;
Cin = 1'b0;
#600 A = 16'b0000000000000101;
B = 16'b0000000000000101;
Cin = 1'b0;
#600 A = 16'b0000001111111111;
B = 16'b0000000000000001;
Cin = 1'b0;
#600 A = 16'b0000000000000001;
B = 16'b1111111111111111;
Cin = 1'b0;
#600 A = 16'b0000000000000000;
B = 16'b1111111111111111;
Cin = 1'b0;
end
initial #9000 $finish;
initial $dumpvars;
endmodule
| 6.640746
|
module FullAdder (
S,
Co,
x,
y,
Ci
);
input x, y, Ci;
output S, Co;
wire s1, d1, d2;
xor #(20) g1 (s1, x, y);
and #(10) g2 (d1, x, y);
and #(10) g3 (d2, Ci, s1);
xor #(20) g4 (S, Ci, s1);
or #(15) g5 (Co, d1, d2);
endmodule
| 7.610141
|
module CLA_4bit (
S,
PP,
GG,
A,
B,
Cin
);
input [3:0] A;
input [3:0] B;
input Cin;
output PP, GG;
output [3:0] S;
wire Cout;
wire [3:1] C;
wire [0:3] P;
wire [0:3] G;
//G
and #(10) g0 (G[0], A[0], B[0]);
and #(10) g1 (G[1], A[1], B[1]);
and #(10) g2 (G[2], A[2], B[2]);
and #(10) g3 (G[3], A[3], B[3]);
//P
xor #(20) p0 (P[0], A[0], B[0]);
xor #(20) p1 (P[1], A[1], B[1]);
xor #(20) p2 (P[2], A[2], B[2]);
xor #(20) p3 (P[3], A[3], B[3]);
and #(25) pp (PP, P[3], P[2], P[1], P[0]);
//C1
wire tmp1;
and #(10) c11 (tmp1, P[0], Cin);
or #(15) c12 (C[1], G[0], tmp1);
//C2
wire tmp2;
wire tmp3;
and #(10) c21 (tmp2, P[1], G[0]);
and #(10) c22 (tmp3, P[1], tmp1);
or #(20) c23 (C[2], tmp2, tmp3, G[1]);
//C3
wire tmp4;
wire tmp5;
wire tmp6;
and #(10) c31 (tmp4, P[2], G[1]);
and #(10) c32 (tmp5, P[2], tmp2);
and #(20) c33 (tmp6, P[2], tmp3);
or #(25) c34 (C[3], tmp4, tmp5, tmp6, G[2]);
//Cout
wire tmp7;
wire tmp8;
wire tmp9;
wire tmp10;
and #(10) c41 (tmp7, P[3], G[2]);
and #(10) c42 (tmp8, P[3], tmp4);
and #(10) c43 (tmp9, P[3], tmp5);
and #(10) c44 (tmp10, P[3], tmp6);
or #(30) c45 (Cout, tmp7, tmp8, tmp9, tmp10, G[3]);
or #(20) gg (GG, tmp7, tmp8, tmp9, G[3]);
/// Making Sums
xor #(20) s0 (S[0], P[0], Cin);
xor #(20) s1 (S[1], P[1], C[1]);
xor #(20) s2 (S[2], P[2], C[2]);
xor #(20) s3 (S[3], P[3], C[3]);
endmodule
| 7.044807
|
module RCA_16bit (
A,
B,
Cin,
S,
Cout
);
input [15:0] A;
input [15:0] B;
input Cin;
output [15:0] S;
output Cout;
wire [15:1] carry;
FullAdder f0 (
S[0],
carry[1],
A[0],
B[0],
Cin
);
FullAdder f1 (
S[1],
carry[2],
A[1],
B[1],
carry[1]
);
FullAdder f2 (
S[2],
carry[3],
A[2],
B[2],
carry[2]
);
FullAdder f3 (
S[3],
carry[4],
A[3],
B[3],
carry[3]
);
FullAdder f4 (
S[4],
carry[5],
A[4],
B[4],
carry[4]
);
FullAdder f5 (
S[5],
carry[6],
A[5],
B[5],
carry[5]
);
FullAdder f6 (
S[6],
carry[7],
A[6],
B[6],
carry[6]
);
FullAdder f7 (
S[7],
carry[8],
A[7],
B[7],
carry[7]
);
FullAdder f8 (
S[8],
carry[9],
A[8],
B[8],
carry[8]
);
FullAdder f9 (
S[9],
carry[10],
A[9],
B[9],
carry[9]
);
FullAdder f10 (
S[10],
carry[11],
A[10],
B[10],
carry[10]
);
FullAdder f11 (
S[11],
carry[12],
A[11],
B[11],
carry[11]
);
FullAdder f12 (
S[12],
carry[13],
A[12],
B[12],
carry[12]
);
FullAdder f13 (
S[13],
carry[14],
A[13],
B[13],
carry[13]
);
FullAdder f14 (
S[14],
carry[15],
A[14],
B[14],
carry[14]
);
FullAdder f15 (
S[15],
Cout,
A[15],
B[15],
carry[15]
);
endmodule
| 6.672591
|
module CLA_16bit (
A,
B,
Cin,
S,
Cout
);
input [15:0] A;
input [15:0] B;
input Cin;
output [15:0] S;
output [3:0] PP, GG;
output Cout;
wire [3:1] C;
wire [3:0] temp;
wire temp1, temp2;
CLA_4bit oh (
temp[3:0],
temp1,
temp2,
PP[3:0],
GG[3:0],
Cin
);
CLA_4bit F0_3 (
S[3:0],
PP[0],
GG[0],
A[3:0],
B[3:0],
Cin
);
CLA_4bit F4_7 (
S[7:4],
PP[1],
GG[1],
A[7:4],
B[7:4],
temp[0]
);
CLA_4bit F8_11 (
S[11:8],
PP[2],
GG[2],
A[11:8],
B[11:8],
temp[1]
);
CLA_4bit F12_15 (
S[15:12],
PP[3],
GG[3],
A[15:12],
B[15:12],
temp[2]
);
endmodule
| 7.235091
|
module aha_4bit_fas (
A,
B,
Sel,
C4,
S
);
input [3:0] A, B;
input Sel;
output [3:0] S;
output C4;
wire [2:0] C;
aha_full_adder_subtractor as0 (
A[0],
B[0],
Sel,
Sel,
C[0],
S[0]
);
aha_full_adder_subtractor as1 (
A[1],
B[1],
Sel,
C[0],
C[1],
S[1]
);
aha_full_adder_subtractor as2 (
A[2],
B[2],
Sel,
C[1],
C[2],
S[2]
);
aha_full_adder_subtractor as3 (
A[3],
B[3],
Sel,
C[2],
C4,
S[3]
);
endmodule
| 7.044934
|
module Compare1 (
A,
B,
Equal,
Alarger,
Blarger
);
input A, B;
output Equal, Alarger, Blarger;
assign Equal = (A & B) | (~A & ~B);
assign Alarger = (A & ~B);
assign Blarger = (~A & B);
endmodule
| 6.708831
|
module Compare4 (
A4,
B4,
Equal,
Alarger,
Blarger
);
input [3:0] A4, B4;
output Equal, Alarger, Blarger;
wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, Bl0, Bl1, Bl2, Bl3;
Compare1 cp0 (
A4[0],
B4[0],
e0,
Al0,
Bl0
);
Compare1 cp1 (
A4[1],
B4[1],
e1,
Al1,
Bl1
);
Compare1 cp2 (
A4[2],
B4[2],
e2,
Al2,
Bl2
);
Compare1 cp3 (
A4[3],
B4[3],
e3,
Al3,
Bl3
);
assign Equal = (e0 & e1 & e2 & e3);
assign Alarger = (Al3 | (Al2 & e3) | (Al1 & e3 & e2) | (Al0 & e3 & e2 & e1));
assign Blarger = (~Alarger & ~Equal);
endmodule
| 6.723645
|
module Bit4Adder (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire w1, w2, w3;
FullAdder FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
FullAdder FA_2 (
a[3],
b[3],
w2,
sum[3],
w3
);
FullAdder FA_3 (
a[4],
b[4],
w3,
sum[4],
cout
);
endmodule
| 7.608783
|
module Bit4Adder2 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire w1, w2, w3;
FullAdder FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
FullAdder FA_2 (
a[3],
b[3],
w2,
sum[3],
w3
);
FullAdder FA_3 (
a[4],
b[4],
w3,
sum[4],
cout
);
endmodule
| 7.467509
|
module Bit4Adder3 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire w1, w2, w3;
FullAdder FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
FullAdder FA_2 (
a[3],
b[3],
w2,
sum[3],
w3
);
FullAdder FA_3 (
a[4],
b[4],
w3,
sum[4],
cout
);
endmodule
| 7.647062
|
module Bit4Adder4 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire w1, w2, w3;
FullAdder5 FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder5 FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
FullAdder5 FA_2 (
a[3],
b[3],
w2,
sum[3],
w3
);
FullAdder5 FA_3 (
a[4],
b[4],
w3,
sum[4],
cout
);
endmodule
| 7.465193
|
module fourbitadderbase3 (
in1,
in2,
out,
Cout,
Cin
);
input wire [7:0] in1;
input wire [7:0] in2;
input wire Cin;
output reg [7:0] out;
output reg Cout;
reg [3:0] Carry;
always @(in1, in2, Cin) begin
{Carry[0], out[1], out[0]} = {in1[1], in1[0]} + {in2[1], in2[0]} + Cin;
{Carry[1], out[3], out[2]} = {in1[3], in1[2]} + {in2[3], in2[2]} + Carry[0];
{Carry[2], out[5], out[4]} = {in1[5], in1[4]} + {in2[5], in2[4]} + Carry[1];
{Carry[3], out[7], out[6]} = {in1[7], in1[6]} + {in2[7], in2[6]} + Carry[2];
Cout = Carry[3];
//////here we have to make sure if any 2bits aren`t 11 and if is there any, we have to make it 0 or 1 depends on 3 or 4 it is going to be and give a carry to the next 2.
if ({out[1], out[0]} == 2'b11) begin
if ({out[3], out[2]} == 2'b11) begin
{out[3], out[2]} = 2'b00;
if ({out[5], out[4]} == 2'b11) begin
{out[5], out[4]} = 2'b00;
if ({out[7], out[6]} == 2'b11) begin
{out[7], out[6]} = 2'b00;
Cout = 1'b1;
end
{out[7], out[6]} = {out[7], out[6]} + 2'b01;
end
{out[5], out[4]} = {out[5], out[4]} + 2'b01;
end
{out[3], out[2]} = {out[3], out[2]} + 2'b01;
{out[1], out[0]} = 2'b00;
end
if ({out[3], out[2]} == 2'b11) begin
if ({out[5], out[4]} == 2'b11) begin
{out[5], out[4]} = 2'b00;
if ({out[7], out[6]} == 2'b11) begin
{out[7], out[6]} = 2'b00;
Cout = 1'b1;
end
{out[7], out[6]} = {out[7], out[6]} + 2'b01;
end
{out[5], out[4]} = {out[5], out[4]} + 2'b01;
{out[3], out[2]} = 2'b00;
end
if ({out[5], out[4]} == 2'b11) begin
if ({out[7], out[6]} == 2'b11) begin
{out[7], out[6]} = 2'b00;
Cout = 1'b1;
end
{out[7], out[6]} = {out[7], out[6]} + 2'b01;
{out[5], out[4]} = 2'b00;
end
if ({out[7], out[6]} == 2'b11) begin
{out[7], out[6]} = 2'b00;
Cout = 1'b1;
end
end
endmodule
| 6.508802
|
module adder4 (
S,
Cout,
A,
B,
Cin
);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Cout;
assign {Cout, S} = A + B + Cin;
endmodule
| 6.582965
|
module four_bit_comparator( input[3:0]A, input[3:0]B, output E, G, L);
assign G = ( A > B ) ? 1’b1 : 1’b0;
assign L = ( A < B ) ? 1’b1 : 1’b0;
assign E = ( A == B ) ? 1’b1 : 1’b0;
endmodule
| 6.507806
|
module four_bit_comparator(a,b,lt,gt,eq);
input [3:0]a, b;
output reg lt,gt,eq;
always @(*)
begin
if(a>b)
begin
gt = 1'b1;
lt = 1'b0;
eq = 1'b0;
end
else if(a<b)
begin
gt = 1'b0;
lt = 1'b1;
eq = 1'b0'
end
else
begin
eq = 1'b1;
gt = 1'b0;
lt = 1'b0;
end
end
endmodule
| 6.507806
|
module counter4bit (
a0,
a1,
a2,
a3,
modern,
rst,
clk1
);
input rst, clk1;
output reg a0;
output reg a1;
output reg a2;
output reg a3;
output reg [3:0] modern;
always @(posedge clk1) begin
if (rst) begin
modern = 0;
a3 = 0;
a2 = 0;
a1 = 0;
a0 = 1'b0;
end else begin
a3 = ((a0 & a1 & a2) ^ a3);
a2 = ((a0 & a1) ^ a2);
a1 = (a1 ^ a0);
a0 = (~a0);
modern = modern + 1;
end
end
endmodule
| 6.667356
|
module four_bit_counter (
out0,
out1,
out2,
out3,
clock,
reset
);
input clock, reset;
output out0, out1, out2, out3;
single_counter count0 (
out0,
clock,
reset
);
single_counter count1 (
out1,
out0,
reset
);
single_counter count2 (
out2,
out1,
reset
);
single_counter count3 (
out3,
out2,
reset
);
endmodule
| 6.701443
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else q <= q + 4'd1;
end
endmodule
| 7.203305
|
module fullAdder4bit (
X,
Y,
Cin,
Sum,
Cout
);
input [3:0] X, Y;
input Cin;
output [3:0] Sum;
output Cout;
wire C1, C2, C3;
fullAdder FA1 (
X[0],
Y[0],
Cin,
Sum[0],
C1
);
fullAdder FA2 (
X[1],
Y[1],
C1,
Sum[1],
C2
);
fullAdder FA3 (
X[2],
Y[2],
C2,
Sum[2],
C3
);
fullAdder FA4 (
X[3],
Y[3],
C3,
Sum[3],
Cout
);
endmodule
| 6.80696
|
module lecture8_1 (
input Clk,
input [3:0] D,
input reset,
input load,
output reg [3:0] Q
);
always @(posedge Clk)
if (reset) begin
Q <= 4'b0;
end else if (load) begin
Q <= D;
end
endmodule
| 6.667771
|
module lecture8_2 (
input Clk,
input ShiftIn,
input [3:0] ParallelIn,
input load,
input ShiftEn,
output ShiftOut,
output [3:0] RegContent
);
reg [3:0] shift_reg;
always @(posedge Clk)
if (load) shift_reg <= ParallelIn;
else if (ShiftEn) shift_reg <= {shift_reg[2:0], ShiftIn};
assign ShiftOut = shift_reg[3];
assign RegContent = shift_reg;
endmodule
| 7.012012
|
module fa1 (
input a,
input b,
input cin,
output s,
output cout
);
assign s = a ^ b ^ cin;
assign cout = a & b | b & cin | cin & a;
endmodule
| 7.791179
|
module ha1 (
input a,
input b,
output s,
output cout
);
assign s = a ^ b;
assign cout = a & b;
endmodule
| 8.130409
|
module 4bit_Adder(Sum ,C_out,A , B , C_in );
input [3:0] A,B;
input C_in;
output [3:0] Sum;
output C_out;
wire C1,C2,C3;
Adder bit1 (Sum[0], C1, A[0], B[0],C_in);
Adder bit2 (Sum[1], C2, A[1], B[1],C1 );
Adder bit3 (Sum[2], C3, A[2], B[2],C2 );
Adder bit4 (Sum[3], C_out, A[3], B[3],C3 );
endmodule
| 7.434718
|
module for adder_subtracter
module adder_subtractor (result,carry,overflow,a,b,control);
output [3:0] result;
output carry;
output overflow;
input [3:0] a;
input [3:0] b;
input control;
wire [2:0] c;
wire [3:0] b_;
ones_compliment OC1(.b_(b_),.b(b),.control(control));
// 4 instances of individual full adder blocks
FA FA0 (.s(result[0]),.co(c[0]),.a(a[0]),.b_(b_[0]),.ci(control));
FA FA1 (.s(result[1]),.co(c[1]),.a(a[1]),.b_(b_[1]),.ci(c[0]));
FA FA2 (.s(result[2]),.co(c[2]),.a(a[2]),.b_(b_[2]),.ci(c[1]));
FA FA3 (.s(result[3]),.co(carry),.a(a[3]),.b_(b_[3]),.ci(c[2]));
//Checking for overflow
xor(overflow,carry,c[2]);
endmodule
| 7.769809
|
module adder4bit (
A,
B,
Ci,
S,
Co
);
input [3:0] A, B;
input Ci;
output [3:0] S;
output Co;
wire [3:0] A, B, S;
wire Ci, Co;
wire [2:0] C;
adder1bit u1 (
A[0],
B[0],
Ci,
S[0],
C[0]
);
adder1bit u2 (
A[1],
B[1],
C[0],
S[1],
C[1]
);
adder1bit u3 (
A[2],
B[2],
C[1],
S[2],
C[2]
);
adder1bit u4 (
A[3],
B[3],
C[2],
S[3],
Co
);
endmodule
| 6.983906
|
module adderInterface (
A,
B,
Ci,
S,
Co
);
input [3:0] A, B;
input Ci;
output [3:0] S;
output Co;
wire [3:0] B;
wire [3:0] A, S;
wire Ci, Co;
adder4bit u (
A,
B,
Ci,
S,
Co
);
endmodule
| 7.444178
|
module sub1bit (
A,
B,
bi,
d,
bo
);
input A, B, bi;
output d, bo;
assign d = (A ^ B) ^ bi;
assign bo = ((~A) & B) | ((~(A ^ B)) & bi);
endmodule
| 7.091868
|
module sub4bit (
A,
B,
bi,
d,
bo
);
input [3:0] A, B;
input bi;
output [3:0] d;
output bo;
wire [3:0] A, B, d;
wire bi, bo;
wire [2:0] bout;
sub1bit u1 (
A[0],
B[0],
bi,
d[0],
bout[0]
);
sub1bit u2 (
A[1],
B[1],
bout[0],
d[1],
bout[1]
);
sub1bit u3 (
A[2],
B[2],
bout[1],
d[2],
bout[2]
);
sub1bit u4 (
A[3],
B[3],
bout[2],
d[3],
bo
);
endmodule
| 7.553426
|
module sub4bitInterface (
A,
B,
bi,
d,
bo
);
input [3:0] A, B;
input bi;
output [3:0] d;
output bo;
wire [3:0] B;
wire [3:0] A, d;
wire bi, bo;
sub4bit(
A, B, bi, d, bo
);
endmodule
| 7.768678
|
module CLA_4 (
input Cin,
input [3:0] A,
B,
output [3:0] Sum,
Generate,
Propogate
);
wire [3:0] Carry, g, p;
assign Sum = (A ^ B ^ Carry);
assign g = (A & B);
assign p = (A ^ B);
assign Generate = g;
assign Propogate = p;
assign Carry[0] = Cin;
assign Carry[1] = ((Cin & p[0]) | g[0]);
assign Carry[2] = ((Cin & p[0] & p[1]) | (g[0] & p[1]) | g[1]);
assign Carry[3] = ((Cin & p[0] & p[1] & p[2]) | (g[0] & p[1] & p[2]) | (g[1] & p[2]) | g[2]);
endmodule
| 6.766102
|
module CLA_tb ();
reg [3:0] A;
reg [3:0] B;
reg Cin;
wire [3:0] S;
wire Cout;
initial begin
A = 0;
B = 0;
Cin = 0;
#10 A = 4'd10;
B = 4'd5;
#20 B = 4'd6;
#10 Cin = 1;
#30 A = 4'd4;
B = 4'd3;
#20 Cin = 0;
end
Carry_Lookahead_Adder uut (
.A (A),
.B (B),
.Cin (Cin),
.S (S),
.Cout(Cout)
);
endmodule
| 7.173384
|
module four_bit_comparator (
A,
B,
EQ,
AGB,
ALB
);
input wire [3:0] A, B;
output reg EQ, AGB, ALB;
always @(A, B) begin
if (A == B) begin
EQ <= 1;
AGB <= 0;
ALB <= 0;
end else if (A > B) begin
EQ <= 0;
AGB <= 1;
ALB <= 0;
end else begin
EQ <= 0;
AGB <= 0;
ALB <= 1;
end
end
endmodule
| 6.507806
|
module tb_4bit_comparator ();
reg [3:0] A, B;
wire EQ, AGB, ALB;
four_bit_comparator test_fourbit_comp (
A,
B,
EQ,
AGB,
ALB
);
initial begin
A = 4'b0000;
B = 4'b0000;
#250 A = 4'b0001;
B = 4'b1000;
#250 A = 4'b0110;
B = 4'b1000;
#250 A = 4'b1011;
B = 4'b1010;
#250 A = 4'b0110;
B = 4'b1010;
#250 A = 4'b0100;
B = 4'b1110;
end
endmodule
| 6.996506
|
module gf2m #(
parameter DIGITAL = 4,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
parameter ITERATION_NUMBER = DATA_WIDTH / DIGITAL;
parameter IDLE = 1'b0;
parameter CAL = 1'b1;
reg state;
reg [12:0] counter;
wire [DATA_WIDTH - 1 : 0] wire_t_i_j;
serial serial_8_bit (
.b(b),
.a(a),
.g(g),
.t_i1_j1(t_i_j),
.t_i_j(wire_t_i_j)
);
always @(posedge clk or negedge rst) begin : proc_counter
if (~rst) begin
counter <= 0;
end else begin
case (state)
IDLE: begin
counter <= 6'd0;
end
CAL: begin
if (counter < ITERATION_NUMBER) counter <= counter + 1;
else counter <= 6'd0;
end
default: /* default */;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_t_i_j
if (~rst) begin
t_i_j <= 0;
end else begin
case (state)
IDLE: t_i_j <= 0;
CAL: t_i_j <= wire_t_i_j;
default: t_i_j <= 0;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_done
if (~rst) begin
done <= 0;
end else begin
case (state)
IDLE: done <= 0;
CAL: begin
if (counter < ITERATION_NUMBER) done <= 0;
else done <= 1'b1;
end
default: done <= 0;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_state
if (~rst) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin : IDLE_STATE
if (start) state <= CAL;
else state <= state;
end
CAL: begin : CAL_STATE
if (counter < ITERATION_NUMBER) state <= CAL;
else state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule
| 7.196913
|
module adder4 (
A,
B,
cin,
S,
cout
);
input [3:0] A, B;
input cin;
output [3:0] S;
output cout;
wire c1, c2, c3;
// 4 instantiated 1-bit Full Adders
FullAdder fa0 (
A[0],
B[0],
cin,
c1,
S[0]
);
FullAdder fa1 (
A[1],
B[1],
c1,
c2,
S[1]
);
FullAdder fa2 (
A[2],
B[2],
c2,
c3,
S[2]
);
FullAdder fa3 (
A[3],
B[3],
c3,
cout,
S[3]
);
endmodule
| 6.582965
|
module odd_parity (
data,
parity
);
input [3:0] data;
output parity;
assign parity = ~(^data);
endmodule
| 7.307593
|
module odd_parity_tb ();
reg [3:0] data;
wire parity;
odd_parity op (
data,
parity
);
initial begin
data = 4'b1100;
#20 data = 4'b1011;
end
endmodule
| 6.654713
|
module parity_checker_odd (
parity,
data,
out
);
input parity;
input [3:0] data;
output reg out; //high if matched else low
wire tmp;
assign tmp = ^data;
initial begin
if (tmp == parity) out = 1;
else out = 0;
end
endmodule
| 7.037994
|
module RCA_4bit (
input a0,
b0,
a1,
b1,
a2,
b2,
a3,
b3,
cin,
output s0,
s1,
s2,
s3,
cout
);
wire cout1;
full_adder full_adder0 (
a0,
b0,
cin,
s0,
cout1
);
full_adder full_adder1 (
a1,
b1,
cout1,
s1,
cout1
);
full_adder full_adder2 (
a2,
b2,
cout1,
s2,
cout1
);
full_adder full_adder3 (
a3,
b3,
cout1,
s3,
cout
);
endmodule
| 7.437004
|
module fulladder (
sum,
cout,
A,
B,
cin
);
input A, B, cin;
output sum, cout;
wire w1, w2, w3;
xor x1 (w1, A, B);
xor x2 (sum, w1, cin);
and a1 (w2, A, B);
and a2 (w3, w1, cin);
or o1 (cout, w2, w3);
endmodule
| 7.454465
|
module ripplecarry (
sum,
cout,
a,
b,
cin
);
input [3:0] a, b;
output [3:0] sum;
input cin;
output cout;
wire w1, w2, w3;
fulladder f0 (
sum[0],
w1,
a[0],
b[0],
cin
);
fulladder f1 (
sum[1],
w2,
a[1],
b[1],
w1
);
fulladder f2 (
sum[2],
w3,
a[2],
b[2],
w2
);
fulladder f3 (
sum[3],
cout,
a[3],
b[3],
w3
);
endmodule
| 7.963357
|
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 0;
else if (load) q <= data;
else if (ena) begin
q[3] <= 0;
q[2] <= q[3];
q[1] <= q[2];
q[0] <= q[1];
end else q <= q;
end
endmodule
| 7.203305
|
module S4MUX (
flush,
stall,
x,
y
);
input flush, stall;
input [3:0] x;
output [3:0] y;
assign y = ((flush || stall) == 1) ? 0 : x;
endmodule
| 7.180465
|
module fulladder (
sum,
cout,
a,
b,
cin
);
output sum, cout;
input a, b, cin;
wire s1, c1, c2;
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, cin);
and (c2, s1, cin);
xor (cout, c2, c1);
endmodule
| 7.454465
|
module fulladder4 (
s,
co4,
a,
b,
ci0
);
output [3:0] s;
output co4;
input [3:0] a, b;
input ci0;
wire co1, co2, co3;
fulladder fa0 (
s[0],
co1,
a[0],
b[0],
ci0
);
fulladder fa1 (
s[1],
co2,
a[1],
b[1],
co1
);
fulladder fa2 (
s[2],
co3,
a[2],
b[2],
co2
);
fulladder fa3 (
s[3],
co4,
a[3],
b[3],
co3
);
endmodule
| 6.856614
|
module comp_tb;
reg [3:0] A;
reg [3:0] B;
reg Cin;
wire E;
wire G;
wire L;
integer index;
comp f (
A,
B,
E,
L,
G
);
initial begin
for (index = 0; index < 16 * 16; index += 1) begin
A = index / 16;
B = index % 16;
#10;
end
end
initial begin
$dumpfile("comp_tb.vcd");
$dumpvars(0, comp_tb);
$monitor($time, ": %b %b => %b %b %b", A, B, E, G, L);
end
endmodule
| 6.589976
|
module _inv (
a,
y
);
input a;
output y;
assign y = ~a;
endmodule
| 7.171978
|
module _and2 (
a,
b,
y
);
input a, b;
output y;
assign y = a & b;
endmodule
| 7.898927
|
module _nor2 (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a | b);
endmodule
| 8.033837
|
module _dff (
clk,
d,
q,
q_bar
);
input clk, d;
output q, q_bar;
wire clk_bar, w_q;
_inv U0_inv (
.a(clk),
.y(clk_bar)
);
_dlatch U1_dlatch (
.clk(clk_bar),
.d(d),
.q(w_q),
.q_bar()
);
_dlatch U2_dlatch (
.clk(clk),
.d(w_q),
.q(q),
.q_bar(q_bar)
);
endmodule
| 6.748574
|
module _dff_r (
clk,
reset_n,
d,
q
);
input clk, reset_n, d;
output q;
wire w_d;
_and2 U0_and2 (
.a(d),
.b(reset_n),
.y(w_d)
);
_dff U1_dff (
.clk(clk),
.d(w_d),
.q(q),
.q_bar()
);
endmodule
| 6.625574
|
module _dff_3_r (
clk,
reset_n,
d,
q
);
input clk, reset_n;
input [2:0] d;
output [2:0] q;
_dff_r U0_dff_r (
clk,
reset_n,
d[0],
q[0]
);
_dff_r U1_dff_r (
clk,
reset_n,
d[1],
q[1]
);
_dff_r U2_dff_r (
clk,
reset_n,
d[2],
q[2]
);
endmodule
| 7.635159
|
module _dff_4_r (
clk,
reset_n,
d,
q
);
input clk, reset_n;
input [3:0] d;
output [3:0] q;
_dff_r U0_dff_r (
clk,
reset_n,
d[0],
q[0]
);
_dff_r U1_dff_r (
clk,
reset_n,
d[1],
q[1]
);
_dff_r U2_dff_r (
clk,
reset_n,
d[2],
q[2]
);
_dff_r U3_dff_r (
clk,
reset_n,
d[3],
q[3]
);
endmodule
| 7.354482
|
module _dff_4 (
clk,
d,
q
);
input clk;
input [3:0] d;
output [3:0] q;
_dff U0_dff (
.clk(clk),
.d(d[0]),
.q(q[0]),
.q_bar()
);
_dff U1_dff (
.clk(clk),
.d(d[1]),
.q(q[1]),
.q_bar()
);
_dff U2_dff (
.clk(clk),
.d(d[2]),
.q(q[2]),
.q_bar()
);
_dff U3_dff (
.clk(clk),
.d(d[3]),
.q(q[3]),
.q_bar()
);
endmodule
| 6.946474
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output reg [15:0] q
);
assign ena = {
q[11:8] == 9 && q[3:0] == 9 && q[7:4] == 9, q[3:0] == 9 && q[7:4] == 9, q[3:0] == 9
};
BCD_counter inst_1 (
clk,
reset || q[3:0] == 9,
1,
q[3:0]
);
BCD_counter inst_2 (
clk,
reset || q[3:0] == 9 && q[7:4] == 9,
ena[1],
q[7:4]
);
BCD_counter inst_3 (
clk,
reset || q[11:8] == 9 && q[3:0] == 9 && q[7:4] == 9,
ena[2],
q[11:8]
);
BCD_counter inst_4 (
clk,
reset || q[15:12] == 9 && q[11:8] == 9 && q[3:0] == 9 && q[7:4] == 9,
ena[3],
q[15:12]
);
endmodule
| 7.203305
|
module BCD_counter (
input clk,
input reset, // Synchronous active-high reset
input en,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (en) q <= q + 4'd1;
else q <= q;
end
endmodule
| 6.772334
|
module fa_1 (
a,
b,
ci,
s,
co
);
input a, b, ci;
output s, co;
assign {co, s} = a + b + ci;
endmodule
| 6.900613
|
module fa_4 (
A,
B,
Cin,
S,
Co
);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Co;
wire [2:0] c;
fa_1 a0 (
A[0],
B[0],
Cin,
S[0],
c[0]
);
fa_1 a1 (
A[1],
B[1],
c[0],
S[1],
c[1]
);
fa_1 a2 (
A[2],
B[2],
c[1],
S[2],
c[2]
);
fa_1 a3 (
A[3],
B[3],
c[2],
S[3],
Co
);
endmodule
| 7.659597
|
module t1 (N1,N2,N3,N19);
input N1,N2,N3;
output N19;
N16 = NAND(N1, N2)
N19 = NOR(N16, N3)
endmodule
| 7.526928
|
module
module mux2 (in0,in1,select,out);
input in0,in1,select;
output out;
wire s0,w0,w1;
not n1 (s0,select);
and a1 (w0,s0,in0);
and a2 (w1,select,in1);
or g3 (out,w0,w1);
endmodule
| 7.450008
|
module decoder (
i,
en,
y
);
input [1:0] i;
input en;
output reg [3:0] y;
always @(*) begin
if (en == 0) y = 4'bzzzz; //active low enable
else begin
case (i)
2'b00: y = 4'b0001;
2'b01: y = 4'b0010;
2'b10: y = 4'b0100;
2'b11: y = 4'b1000;
default: y = 4'bzzzz;
endcase
end
end
endmodule
| 7.018254
|
module mux (
in,
sel,
out
);
input [3:0] in;
input [1:0] sel;
output reg out;
always @(*) begin
case (sel)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
end
endmodule
| 7.741587
|
module mux (
in,
sel,
out
);
input [3:0] in;
input [1:0] sel;
output out;
assign out=~sel[1]&~sel[0]&in[0] |
~sel[1]&sel[0]&in[1]| sel[1]&~sel[0]&in[2]| sel[1]&sel[0]&in[3];
endmodule
| 7.741587
|
module m4x2_pEncoder (
x,
y,
v,
D
);
input wire [3:0] D;
output wire x, y, v;
assign x = D[2] || D[3];
assign y = D[3] || (D[1] && ~D[2]);
assign v = D[0] || D[1] || D[2] || D[3];
endmodule
| 7.447387
|
module m4to1_MUX_RTL (
out,
Sin,
A,
B,
C,
D
);
input wire A, B, C, D;
input wire [1:0] Sin;
output wire out;
assign out= ((~Sin[0])&&(~Sin[1])&&A ) || ((Sin[0])&&(~Sin[1])&&B) || ((~Sin[0])&&(Sin[1])&&C) || ((Sin[0])&&(Sin[1])&&D);
endmodule
| 7.525697
|
module m4to1_MUX_Behavior (
out,
Sin,
A,
B,
C,
D
);
input wire A, B, C, D;
input wire [1:0] Sin;
output reg out;
always @(Sin, A, B, C, D) begin
if (Sin == 2'b00) out = A;
else if (Sin == 2'b01) out = B;
else if (Sin == 2'b10) out = C;
else out = D;
end
endmodule
| 7.464429
|
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= (~'b010000);
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module MUX (
i,
s,
y
);
input [3:0] i;
input [1:0] s;
output y;
reg y;
always @(s or i) begin
case (s)
2'b00: y = i[0];
2'b01: y = i[1];
2'b10: y = i[2];
2'b11: y = i[3];
default: y = 0;
endcase
end
endmodule
| 6.699278
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= '0;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module decode_4_16 (
output reg [15:0] d_out,
input [3:0] d_in,
input wire clk
);
initial begin
d_out <= 16'b0;
end
always @(clk) begin
case (d_in)
0: d_out <= 16'h1;
1: d_out <= 16'h2;
2: d_out <= 16'h4;
3: d_out <= 16'h8;
4: d_out <= 16'h10;
5: d_out <= 16'h20;
6: d_out <= 16'h40;
7: d_out <= 16'h80;
8: d_out <= 16'h100;
9: d_out <= 16'h200;
10: d_out <= 16'h400;
11: d_out <= 16'h800;
12: d_out <= 16'h1000;
13: d_out <= 16'h2000;
14: d_out <= 16'h4000;
default: d_out <= 16'h0;
endcase
end
endmodule
| 6.642878
|
module mux4_1 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] s,
output reg [3:0] y
);
always @(*) begin
case (s)
2'b00: y = I0;
2'b01: y = I1;
2'b10: y = I2;
2'b11: y = I3;
endcase
end
endmodule
| 7.631991
|
module compressor4to2 (
x1,
x2,
x3,
x4,
Cin,
Sum,
Carry,
Cout
);
input x1, x2, x3, x4, Cin;
output Sum, Carry, Cout;
wire w1, w2;
xor (w1, x1, x2); //2 input xor
xor (w2, x3, x4, w1); //3 input xor
xor (Sum, w2, Cin);
mux2to1 func1 (
Cout,
x1,
x3,
w1
);
mux2to1 func2 (
Carry,
x4,
Cin,
w2
);
endmodule
| 7.200933
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= '1;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module Test;
reg [3:0] in;
wire [1:0] out;
encoder enc (
in,
out
);
initial begin
$dumpfile("encoder.vcd");
$dumpvars(0, Test);
$display("in \t out");
$monitor("%b \t %b ", in, out);
in = 4'b0001;
#10 in = 4'b0010;
#10 in = 4'b0100;
#10 in = 4'b1000;
#10 $finish;
end
endmodule
| 7.37486
|
module test;
reg [3:0] in;
wire [1:0] out;
enc e (
in,
out
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, test);
$display("in3\tin2\tin2\tin0\to1\to0");
$monitor("%b\t%b\t%b\t%b\t%b\t%b", in[3], in[2], in[1], in[0], out[1], out[0]);
in = 4'b0001;
#10 in = 4'b0010;
#10 in = 4'b0100;
#10 in = 4'b1000;
#10 $finish;
end
endmodule
| 6.635152
|
module adder4 (
input [3:0] A,
input [3:0] B,
output [4:0] SUM
);
wire c1, c2, c3;
full_adder a1 (
.a(A[0]),
.b(B[0]),
.c(1'b0),
.sum(SUM[0]),
.carry(c1)
);
full_adder a2 (
.a(A[1]),
.b(B[1]),
.c(c1),
.sum(SUM[1]),
.carry(c2)
);
full_adder a3 (
.a(A[2]),
.b(B[2]),
.c(c2),
.sum(SUM[2]),
.carry(c3)
);
full_adder a4 (
.a(A[3]),
.b(B[3]),
.c(c3),
.sum(SUM[3]),
.carry(SUM[4])
);
endmodule
| 6.582965
|
module alu (
a,
b,
opcode,
y
);
input [31:0] a;
input [31:0] b;
input [3:0] opcode;
output [31:0] y;
reg [31:0] y;
always @(a or b or opcode) begin
case (opcode)
4'd0: y = a + b;
4'd1: y = a - b;
4'd2: y = ~a;
4'd3: y = a & b;
4'd4: y = a | b;
4'd5: y = ~(a & b);
4'd6: y = ~(a | b);
4'd7: y = a ^ b;
4'd8: y = ~(a ^ b);
4'd9: y = a;
4'd10: y = 32'b0;
4'd11: y = 32'b1;
4'd12: y = a + 1;
4'd13: y = a - 1;
4'd14: y = b + 1;
4'd15: y = b - 1;
default: y = 32'bx;
endcase
end
endmodule
| 6.634214
|
module test;
wire [31:0] y;
reg [31:0] a = 32'd12;
reg [31:0] b = 32'd15;
reg [3:0] opcode;
integer i = 0;
alu a1 (
a,
b,
opcode,
y
);
initial begin
$dumpfile("4_alu.vcd");
$dumpvars(0, test);
opcode = 4'd0;
for (i = 0; i < 16; i++) begin
#5 opcode = opcode + 1;
end
#5 $finish;
end
always @(a, b, opcode)
$strobe(
"At time = (%0t),a = (%h),b = (%h),opcode = (%d),y = (%h)", $time, a, b, opcode, y
);
endmodule
| 6.964054
|
module fourbitALU (
input [3:0] a,
input [3:0] b,
input [1:0] c,
output [3:0] y,
output z
);
wire [2:0] e;
onebitALU alu1 (
y[0],
e[0],
a[0],
b[0],
1'b0,
c[0],
c[1]
);
onebitALU alu2 (
y[1],
e[1],
a[1],
b[1],
e[0],
c[0],
c[1]
);
onebitALU alu3 (
y[2],
e[2],
a[2],
b[2],
e[1],
c[0],
c[1]
);
onebitALU alu4 (
y[3],
z,
a[3],
b[3],
e[2],
c[0],
c[1]
);
endmodule
| 7.741673
|
module asyncdown (
output reg [3:0] count,
input clk,
rst
);
always @(rst) count = 0;
always @(posedge clk) count[0] = ~count[0];
always @(posedge count[0]) count[1] = ~count[1];
always @(posedge count[1]) count[2] = ~count[2];
always @(posedge count[2]) count[3] = ~count[3];
endmodule
| 6.894613
|
module asyncdown_tb ();
reg clk, rst;
wire [3:0] count;
asyncdown m1 (
count,
clk,
rst
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
clk = 0;
rst = 1;
#20 rst = 0;
#150 $stop;
end
always #5 clk = ~clk;
endmodule
| 6.607107
|
module asyncup_tb ();
reg clk, rst;
wire [3:0] count;
asyncup m1 (
count,
clk,
rst
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
clk = 0;
rst = 1;
#20 rst = 0;
#200 $stop;
end
always #5 clk = ~clk;
endmodule
| 6.632004
|
module asyncupdown (
output reg [3:0] count,
input clk,
rst,
status
);
initial count = 0;
always @(posedge clk & status) begin
if (rst) count = 0;
else count[0] = ~count[0];
end
always @(posedge count[0] & status) begin
if (rst) count = 0;
else count[1] = ~count[1];
end
always @(posedge count[1] & status) begin
if (rst) count = 0;
else count[2] = ~count[2];
end
always @(posedge count[2] & status) begin
if (rst) count = 0;
else count[3] = ~count[3];
end
//upcount
always @(posedge clk & ~status) begin
if (rst) count = 0;
else count[0] = ~count[0];
end
always @(negedge count[0] & ~status) begin
if (rst) count = 0;
else count[1] = ~count[1];
end
always @(negedge count[1] & ~status) begin
if (rst) count = 0;
else count[2] = ~count[2];
end
always @(negedge count[2] & ~status) begin
if (rst) count = 0;
else count[3] = ~count[3];
end
endmodule
| 6.828497
|
module fulladder1 (
output sum,
cout,
input a,
b,
cin
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
| 6.715059
|
module fulladder4 (
sum,
cout,
a,
b,
cin
);
input [3:0] a, b;
output [3:0] sum;
input cin;
output cout;
wire w1, w2, w3;
fulladder1 L0 (
sum[0],
w1,
a[0],
b[0],
cin
);
fulladder1 L1 (
sum[1],
w2,
a[1],
b[1],
w1
);
fulladder1 L2 (
sum[2],
w3,
a[2],
b[2],
w2
);
fulladder1 L3 (
sum[3],
cout,
a[3],
b[3],
w3
);
endmodule
| 6.856614
|
module fulladder4_tb ();
wire cout;
wire [3:0] sum;
reg [3:0] a, b;
reg cin;
fulladder4 m1 (
sum,
cout,
a,
b,
cin
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 2;
b = 3;
cin = 0;
#20 a = 5;
b = 3;
#20 a = 4;
b = 10;
#20 a = 7;
b = 8;
#20 $stop;
end
endmodule
| 7.193042
|
module fullsubtractor1 (
output diff,
bout,
input a,
b,
bin
);
assign diff = a ^ b ^ bin;
assign bout = ~a & (b ^ bin) | b & bin;
endmodule
| 6.741456
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.