code
stringlengths 35
6.69k
| score
float64 6.5
11.5
|
|---|---|
module decoder_4X16_tb;
reg [ 3:0] in;
wire [15:0] f;
//Instantiate UUT
decoder_4X16 UUT (
f,
1'b1,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initial $monitor("in = %b, output = %b", in, f);
endmodule
| 7.346161
|
module octal_priority_encoder (
v,
x,
y,
z,
d
);
output reg v, x, y, z;
input [7:0] d;
always @(d) begin
casex (d)
8'b00000000: {x, y, z, v} = 4'bxxx0;
8'b00000001: {x, y, z, v} = 4'b0001;
8'b0000001x: {x, y, z, v} = 4'b0011;
8'b000001xx: {x, y, z, v} = 4'b0101;
8'b00001xxx: {x, y, z, v} = 4'b0111;
8'b0001xxxx: {x, y, z, v} = 4'b1001;
8'b001xxxxx: {x, y, z, v} = 4'b1011;
8'b01xxxxxx: {x, y, z, v} = 4'b1101;
8'b1xxxxxxx: {x, y, z, v} = 4'b1111;
endcase
end
endmodule
| 6.633031
|
module octal_priority_encoder_tb;
reg [7:0] in;
//reg en;
wire v, x, y, z;
//Instantiate UUT
octal_priority_encoder UUT (
v,
x,
y,
z,
in
);
//stimulus block
initial begin
in = 8'b00000000;
#10 in = 8'b00000001;
#10 in = 8'b00000010;
#10 in = 8'b00000110;
#10 in = 8'b00001010;
#10 in = 8'b00010010;
#10 in = 8'b00100010;
#10 in = 8'b01000110;
#10 in = 8'b10000010;
end
initial $monitor("in = %b, x = %b, y = %b, z = %b, v = %b", in, x, y, z, v);
endmodule
| 6.633031
|
module mux_2x1 (
y,
s,
d
);
output y;
input s;
input [1:0] d;
wire not_s, d0_out, d1_out;
not (not_s, s);
nand (d0_out, not_s, d[0]);
nand (d1_out, s, d[1]);
nand (y, d0_out, d1_out);
endmodule
| 6.925133
|
module mux_8x1 (
y,
s,
d
);
output y;
input [2:0] s;
input [7:0] d;
wire not_s0, not_s1, not_s2, d0_out, d1_out, d2_out, d3_out, d4_out, d5_out, d6_out, d7_out;
not (not_s0, s[0]);
not (not_s1, s[1]);
not (not_s2, s[2]);
nand (d0_out, not_s2, not_s1, not_s0, d[0]);
nand (d1_out, not_s2, not_s1, s[0], d[1]);
nand (d2_out, not_s2, s[1], not_s0, d[2]);
nand (d3_out, not_s2, s[1], s[0], d[3]);
nand (d4_out, s[2], not_s1, not_s0, d[4]);
nand (d5_out, s[2], not_s1, s[0], d[5]);
nand (d6_out, s[2], s[1], not_s0, d[6]);
nand (d7_out, s[2], s[1], s[0], d[7]);
nand (y, d0_out, d1_out, d2_out, d3_out, d4_out, d5_out, d6_out, d7_out);
endmodule
| 7.358788
|
module mux_16x1_tb;
reg [15:0] in;
reg [3:0] s;
wire y;
//Instantiate UUT
mux_16x1 UUT (
y,
s,
in
);
//stimulus block
initial begin
in = 16'b0101010101010101;
s = 4'b0000;
repeat (15) #10 s = s + 1'b1;
end
initial $monitor("in = %b, s = %b, y = %b", in, s, y);
endmodule
| 6.514733
|
module mux_8x1_tb;
reg [7:0] in;
reg [2:0] s;
wire y;
//Instantiate UUT
mux_8x1 UUT (
y,
s,
in
);
//stimulus block
initial begin
in = 8'b01010101;
s = 3'b000;
repeat (7) #10 s = s + 1'b1;
end
initial $monitor("in = %b, s = %b, y = %b", in, s, y);
endmodule
| 6.648973
|
module mux_2x1_tb;
reg [1:0] in;
reg s;
wire y;
//Instantiate UUT
mux_2x1 UUT (
y,
s,
in
);
//stimulus block
initial begin
in = 2'b01;
s = 1'b0;
#10 s = 1'b1;
end
initial $monitor("in = %b, s = %b, y = %b", in, s, y);
endmodule
| 6.688183
|
module grey_code_convertor (
A,
B,
C,
D,
w,
x,
y,
z
);
output A, B, C, D;
input w, x, y, z;
//A = w
//B = w'x + wx' = w XOR x
//C = x'y + xy' = x XOR y
//D = y'z + yz' = y XOR z
assign A = w;
assign B = w ^ x;
assign C = x ^ y;
assign D = y ^ z;
endmodule
| 6.618179
|
module grey_code_convertor_tb;
reg [3:0] in;
wire [3:0] f;
//Instantiate UUT
grey_code_convertor UUT (
f[3],
f[2],
f[1],
f[0],
in[3],
in[2],
in[1],
in[0]
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initial $monitor("wxyz = %b, ABCD = %b", in, f);
endmodule
| 6.618179
|
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
// simple way: assign sum = x + y;
wire [2:0] cout;
fa fa1 (
x[0],
y[0],
0,
cout[0],
sum[0]
);
fa fa2 (
x[1],
y[1],
cout[0],
cout[1],
sum[1]
);
fa fa3 (
x[2],
y[2],
cout[1],
cout[2],
sum[2]
);
fa fa4 (
x[3],
y[3],
cout[2],
sum[4],
sum[3]
);
endmodule
| 7.203305
|
module fa (
input a,
b,
cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = a & b | a & cin | b & cin;
endmodule
| 7.001699
|
module top_module (
input in1,
input in2,
output out
);
assign out = in1 & ~in2;
endmodule
| 7.203305
|
module assignment_example;
reg [3:0] a_block;
reg [3:0] b_block;
reg [3:0] a_nonblock;
reg [3:0] b_nonblock;
initial begin
// initialize all our variables to start
a_block = 4'd1;
b_block = 4'd2;
a_nonblock = 4'd1;
b_nonblock = 4'd2;
// blocking assignments, b = a, a = b
b_block = a_block;
a_block = b_block;
// nonblocking assignments, b <= a, a <= b
b_nonblock <= a_nonblock;
a_nonblock <= b_nonblock;
// show the blocking result
$display("A Blocking: %d", a_block);
$display("B Blocking: %d\n", b_block);
// on the first clock cycle, show the nonblocking result
#0 $display("A Nonblocking (cycle 0): %d", a_nonblock);
#0 $display("B Nonblocking (cycle 0): %d\n", b_nonblock);
// on the second clock cycle, show the nonblocking result again
#1 $display("A Nonblocking (cycle 1): %d", a_nonblock);
#1 $display("B Nonblocking (cycle 1): %d", b_nonblock);
end
endmodule
| 6.793602
|
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 4'b0;
else if (load) q <= data;
else if (ena) q <= {1'b0, q[3:1]};
end
endmodule
| 7.203305
|
module ripple_carry_adder (
x,
y,
s,
c
);
input [3:0] x, y;
output [3:0] s;
output c;
wire w1, w2, w3;
fulladder u1 (
x[0],
y[0],
1'b0,
s[0],
w1
);
fulladder u2 (
x[1],
y[1],
w1,
s[1],
w2
);
fulladder u3 (
x[2],
y[2],
w2,
s[2],
w3
);
fulladder u4 (
x[3],
y[3],
w3,
s[3],
c
);
endmodule
| 7.682509
|
module fulladder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
assign s = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 7.454465
|
module fourbitadder (
SW,
LEDR
);
input [8:0] SW;
output [9:0] LEDR;
wire c_1;
wire c_2;
wire c_3;
fulladder FA0 (
.a (SW[4]),
.b (SW[0]),
.c_i(SW[8]),
.s (LEDR[0]),
.c_o(c_1)
);
fulladder FA1 (
.a (SW[5]),
.b (SW[1]),
.c_i(c_1),
.s (LEDR[1]),
.c_o(c_2)
);
fulladder FA2 (
.a (SW[6]),
.b (SW[2]),
.c_i(c_2),
.s (LEDR[2]),
.c_o(c_3)
);
fulladder FA3 (
.a (SW[7]),
.b (SW[3]),
.c_i(c_3),
.s (LEDR[3]),
.c_o(LEDR[9])
);
endmodule
| 6.575476
|
module fulladder (
a,
b,
c_i,
s,
c_o
);
input a, b, c_i;
output s, c_o;
assign s = (a ^ b) ^ c_i;
assign c_o = b & ~(a ^ b) | c_i & (a ^ b);
endmodule
| 7.454465
|
module
module full_adder(sum, cout, x, y, cin);
input x, y, cin;
output sum, cout;
assign sum = x^y^cin;
assign cout = (x & y)| (y & cin) | (cin & x);
endmodule
| 6.534742
|
module fourBit_Rot (
A,
rotamt,
Yleft,
Yright
);
parameter N = 4;
input [(N-1):0] A;
input [1:0] rotamt;
output reg [(N-1):0] Yleft, Yright;
// Left rotate
always @(A or rotamt) begin
case (rotamt)
2'b00: // 0_bit rotation
Yleft <= A;
2'b01: // 1_bit rotation
Yleft <= {A[(N-2):0], A[(N-1)]};
2'b10: // 2_bit rotation
Yleft <= {A[(N-3):0], A[(N-1):(N-2)]};
2'b11: // 3_bit rotation
Yleft <= {A[(N-4):0], A[(N-1):(N-3)]};
default: Yleft <= A;
endcase
end
// Right rotate
always @(A or rotamt) begin
case (rotamt)
2'b00: // 0_bit rotation
Yright <= A;
2'b01: // 1_bit rotation
Yright <= {A[0], A[(N-1):1]};
2'b10: // 2_bit rotation
Yright <= {A[1:0], A[(N-1):2]};
2'b11: // 3_bit rotation
Yright <= {A[2:0], A[(N-1):3]};
default: Yright <= A;
endcase
end
endmodule
| 7.337098
|
module fourBit_Rot_tb ();
//Declare test variables
parameter N = 4;
reg [(N-1):0] A;
reg [1:0] rotamt;
reg [1:0] patterns[0:3];
wire [(N-1):0] Yleft, Yright;
integer i;
//Instantiate the design with testbench variables
fourBit_Rot funct (
.A(A),
.rotamt(rotamt),
.Yleft(Yleft),
.Yright(Yright)
);
//4-bit Rotator Test
initial begin
patterns[0] = 2'b00;
patterns[1] = 2'b01;
patterns[2] = 2'b10;
patterns[3] = 2'b11;
for (i = 0; i < 4; i = i + 1) begin
A <= 4'b0110;
rotamt <= patterns[i];
#1
case (rotamt)
2'b00: begin
if (Yleft !== A) begin
$display("Error: 0_bit left rotation!!! -> %b", Yleft);
$stop;
end else $display("0_bit left rotation passed.");
if (Yright !== A) begin
$display("Error: 0_bit right rotation!!! -> %b", Yright);
$stop;
end else $display("0_bit right rotation passed.");
end
2'b01: begin
if (Yleft !== 4'b1100) begin
$display("Error: 1_bit left rotation!!! -> %b", Yleft);
$stop;
end else $display("1_bit left rotation passed.");
if (Yright !== 4'b0011) begin
$display("Error: 1_bit right rotation!!! -> %b", Yright);
$stop;
end else $display("1_bit right rotation passed.");
end
2'b10: begin
if (Yleft !== 4'b1001) begin
$display("Error: 2_bit left rotation!!! -> %b", Yleft);
$stop;
end else $display("2_bit left rotation passed.");
if (Yright !== 4'b1001) begin
$display("Error: 2_bit right rotation!!! -> %b", Yright);
$stop;
end else $display("2_bit right rotation passed.");
end
2'b11: begin
if (Yleft !== 4'b0011) begin
$display("Error: 3_bit left rotation!!! -> %b", Yleft);
$stop;
end else $display("3_bit left rotation passed.");
if (Yright !== 4'b1100) begin
$display("Error: 3_bit right rotation!!! -> %b", Yright);
$stop;
end else $display("3_bit right rotation passed.");
end
endcase
end
end
endmodule
| 7.190049
|
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (q == 9 && slowena) q <= 0;
else if (~slowena) q <= q;
else q <= q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
if (reset == 1'b1) begin
q <= 8'h34;
end else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire cout1, cout2, cout3;
bcd_fadd A (
a[3:0],
b[3:0],
cin,
cout1,
sum[3:0]
);
bcd_fadd B (
a[7:4],
b[7:4],
cout1,
cout2,
sum[7:4]
);
bcd_fadd C (
a[11:8],
b[11:8],
cout2,
cout3,
sum[11:8]
);
bcd_fadd D (
a[15:12],
b[15:12],
cout3,
cout,
sum[15:12]
);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = k ? OFF : ON;
endcase
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if (reset) state <= OFF;
else state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = (state == ON);
endmodule
| 7.203305
|
module gray (
input Clk,
input Reset,
input En,
output reg [2:0] Output,
output reg Overflow
);
initial begin
Output <= 0;
Overflow <= 0;
end
always @(posedge Clk) begin
if (Reset == 1) begin
Output <= 0;
Overflow <= 0;
end else begin
if (En == 1) begin
case (Output)
3'b000: begin
Output <= 3'b001;
end
3'b001: begin
Output <= 3'b011;
end
3'b010: begin
Output <= 3'b110;
end
3'b011: begin
Output <= 3'b010;
end
3'b100: begin
Output <= 0;
Overflow <= 1;
end
3'b101: begin
Output <= 100;
end
3'b110: begin
Output <= 3'b111;
end
3'b111: begin
Output <= 3'b101;
end
endcase
end else begin
end
end
end
endmodule
| 6.553837
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
// assign out = a ^ b ^ c ^ d;
assign out = a & ~b & ~c & ~d | ~a & b & ~c & ~d | ~a & ~b & c & ~d | ~a & ~b & ~c & d | ~a & b & c & d | a & ~b & c & d | a & b & ~c & d | a & b & c & ~d;
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if (reset) q <= 5'h01;
else begin
q[4] <= 1'b0 ^ q[0];
q[3] <= q[4];
q[2] <= q[3] ^ q[0];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output reg [4:0] q
);
reg [4:0] q_next; // q_next is not a register
// Convenience: Create a combinational block of logic that computes
// what the next value should be. For shorter code, I first shift
// all of the values and then override the two bit positions that have taps.
// A logic synthesizer creates a circuit that behaves as if the code were
// executed sequentially, so later assignments override earlier ones.
// Combinational always block: Use blocking assignments.
always @(*) begin
q_next = q[4:1]; // Shift all the bits. This is incorrect for q_next[4] and q_next[2]
q_next[4] = q[0]; // Give q_next[4] and q_next[2] their correct assignments
q_next[2] = q[3] ^ q[0];
end
// This is just a set of DFFs. I chose to compute the connections between the
// DFFs above in its own combinational always block, but you can combine them if you wish.
// You'll get the same circuit either way.
// Edge-triggered always block: Use non-blocking assignments.
always @(posedge clk) begin
if (reset) q <= 5'h1;
else q <= q_next;
end
endmodule
| 7.203305
|
module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| 7.203305
|
module MUX (
in,
selector,
out
);
input wire [3:0] in;
input wire [1:0] selector;
output wire out;
assign out = ~selector[1]&(~selector[0])&in[0] | (~selector[1]&(selector[0])&in[1]) | (selector[1]&(~selector[0])&in[2]) | (selector[1]&(selector[0])&in[3]);
endmodule
| 8.295116
|
module Encoder (
in,
out
);
input wire [3:0] in;
output reg [1:0] out;
always @(in) begin
case (in)
4'b0001: out = {1'b0, 1'b0};
4'b0010: out = {1'b0, 1'b1};
4'b0100: out = {1'b1, 1'b0};
4'b1000: out = {1'b1, 1'b1};
default: out = {1'b0, 1'b0};
endcase
end
endmodule
| 7.458619
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~a & ~b & (~c | ~d)) | (~a & b & (c | ~d)) | (a & b & c & d) | (a & ~b & (~c | d));
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a | (~b & c);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a ^ b ^ c ^ d;
endmodule
| 7.203305
|
module Name>
//
// Type: <Sequential or Combinational, etc.>
//
// Purpose: <Specific Function Description>
//
//
// Details:
// - Design Logic;
// -Variable setting.
//
// Release History:
// - Version 1.0 20/03/19: Create;
// - Version 1.1 20/03/19: Add Specific Description.
//
// Notes:
// - <Problems>;
// - <Optimization Method>;
// - <Other Useful Info>.
//**********************************************************
module template(input_variable_a, input_variable_b, output_variable_a, clk, rst_n)
input input_variable_a; // <Specific Description>
input input_variable_b; // <Specific Description>
output output_variable_a; // <Specific Description>
parameter IDLE <= 1'b0;
wire input_variable_a;
wire input_variable_b;
reg temp; // All the output signals should use reg
assign output_variable_a = temp;
//
// This always part controls the signal temp, which is ...
//
always @ (posedge clk) begin // One always part only controls one output signal
if (rst_n) begin // Both spaces are two <space>, and there is one <space> between "if" and the brackets. Don't use <Tab>.
temp <= IDLE;
end
else
case (input_variable_a) // Don't use casex, x and z
1'b0: temp <= 1'b0; // <Reason>
1'b1: temp <= 1'b0; // <Reason>
default: temp <= IDLE; // Don't forget default
endcase
end
end
endmodule
| 8.458575
|
module Name>
//
// Type: <Sequential or Combinational, etc.>
//
// Purpose: <Specific Function Description>
//
//
// Details:
// - Design Logic;
// -Variable setting.
//
// Release History:
// - Version 1.0 20/03/19: Create;
// - Version 1.1 20/03/19: Add Specific Description;
// - Version 1.2 20/03/20: Fix some errors.
//
// Notes:
// - <Problems>;
// - <Optimization Method>;
// - <Other Useful Info>.
//**********************************************************
module template(input_variable_a, input_variable_b, output_variable_a, clk, rst_n)
input input_variable_a; // <Specific Description>
input input_variable_b; // <Specific Description>
output output_variable_a; // <Specific Description>
parameter IDLE <= 1'b0;
wire input_variable_a;
wire input_variable_b;
reg temp; // All the output signals should use reg
assign output_variable_a = temp;
//
// This always part controls the signal temp, which is ...
//
always @ (posedge clk) begin // One always part only controls one output signal
if (rst_n) begin // Both spaces are two <space>, and there is one <space> between "if" and the brackets. Don't use <Tab>.
temp <= IDLE;
end
else begin
case (input_variable_a) // Don't use casex, x and z
1'b0: temp <= 1'b0; // <Reason>
1'b1: temp <= 1'b1; // <Reason>
default: temp <= IDLE; // Don't forget default
endcase
end
end
endmodule
| 8.458575
|
module Name>
//
// Type: <Sequential or Combinational, etc.>
//
// Purpose: <Specific Function Description>
//
//
// Details:
// - Design Logic;
// -Variable setting.
//
// Release History:
// - Version 1.0 20/03/19: Create;
// - Version 1.1 20/03/19: Add Specific Description;
// - Version 1.2 20/03/20: Fix some errors;
// - Version 1.3 20/04/12: Edit.
//
// Notes:
// - <Problems>;
// - <Optimization Method>;
// - <Other Useful Info>.
//**********************************************************
module template(
input wire clk, // <Specific Description>
input wire rst_n, // <Specific Description>
input wire input_variable_a, // <Specific Description>
input wire input_variable_b, // <Specific Description>
output reg output_variable_a // <Specific Description>
);
parameter IDLE <= 1'b0; // <Specific Description>
wire input_variable_a; // <Specific Description>
wire input_variable_b; // <Specific Description>
//
// This always part controls the signal output_variable_a, which is ...
//
always @ ( posedge clk ) begin // One always part only controls one output signal
if ( rst_n ) begin // Both spaces are two <space>, and there is one <space> between "if" and the brackets. Don't use <Tab>.
output_variable_a <= IDLE;
end
else begin
case ( input_variable_a ) // Don't use casex, x and z
1'b0: output_variable_a <= 1'b0; // <Reason>
1'b1: output_variable_a <= 1'b1; // <Reason>
default: output_variable_a <= IDLE; // Don't forget default
endcase
end
end
// assign
endmodule
| 8.458575
|
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// 1. A mux coded as (~sel & a) | (sel & b) does not work for vectors.
// This is because these are bitwise operators, and sel is only a 1 bit wide quantity,
// which leaves the upper bits of a and b zeroed. It is possible to code it using
// the replication operator, but this is somewhat difficult to read:
// ( {8{~sel}} & a ) | ( {8{sel}} & b )
// 2. The simulation waveform shows that when sel = 1, a should be selected. This
// is flipped in the suggested code.
assign out = sel ? a : b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
); //
wire and_out;
andgate inst1 (
and_out,
a,
b,
c,
1,
1
);
assign out = ~and_out;
endmodule
| 7.203305
|
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
wire [7:0] out1, out2;
mux2 mux0 (
sel[0],
a,
b,
out1
);
mux2 mux1 (
sel[0],
c,
d,
out2
);
mux2 mux2 (
sel[1],
out1,
out2,
out
);
endmodule
| 7.203305
|
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
result_is_zero = (out == 0);
end
endmodule
| 7.203305
|
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
);
// A combinational always block.
always @(*) begin
out = 0; // To avoid latches, give the outputs a default assignment
valid = 1; // then override them in the case statement. This is less
// code than assigning a value to every variable for every case.
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'h26: out = 3; // 8'd26 is 8'h1a
8'h25: out = 4;
8'h2e: out = 5;
8'h36: out = 6;
8'h3d: out = 7;
8'h3e: out = 8;
8'h46: out = 9;
default: valid = 0;
endcase
end
endmodule
| 7.203305
|
module uart_loopback_top (
input sys_clk, //ⲿ50Mʱ
input sys_rst_n, //ⲿλźţЧ
input key0,
input uart_rxd, //UARTն˿
output uart_txd, //UARTͶ˿
output led_1
);
//parameter define
parameter CLK_FREQ = 12000000; //ϵͳʱƵ
parameter UART_BPS = 115200; //崮ڲ
//wire define
wire uart_recv_done; //UART
wire [7:0] uart_recv_data; //UART
wire uart_send_en; //UARTʹ
wire [7:0] uart_send_data; //UART
wire uart_tx_busy; //UARTæ״̬־
//*****************************************************
//** main code
//*****************************************************
// //ڽģ
// uart_recv #(
// .CLK_FREQ (CLK_FREQ), //ϵͳʱƵ
// .UART_BPS (UART_BPS)) //ôڽղ
// u_uart_recv(
// .sys_clk (sys_clk),
// .sys_rst_n (sys_rst_n),
// .uart_rxd (uart_rxd),
// .uart_done (uart_recv_done),
// .uart_data (uart_recv_data)
// );
//ڷģ
uart_send #(
.CLK_FREQ(CLK_FREQ), //ϵͳʱƵ
.UART_BPS(UART_BPS)
) //ôڷͲ
u_uart_send (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.uart_en (uart_send_en),
.uart_din (uart_send_data),
.uart_tx_busy(uart_tx_busy),
.uart_txd (uart_txd)
);
// //ڻģ
// uart_loop u_uart_loop(
// .sys_clk (sys_clk),
// .sys_rst_n (sys_rst_n),
// .recv_done (uart_recv_done), //һ֡ɱ־ź
// .recv_data (uart_recv_data), //յ
// .tx_busy (uart_tx_busy), //æ״̬־
// .send_en (uart_send_en), //ʹź
// .send_data (uart_send_data) //
// );
uart_test u_uart_test (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.key (key0),
.led (led_1),
.tx_busy (uart_tx_busy), //æ״̬־
.send_en (uart_send_en), //ʹź
.send_data(uart_send_data) //
);
endmodule
| 7.36109
|
module uart_test (
input sys_clk, //ϵͳʱ
input sys_rst_n, //ϵͳλ͵ƽЧ
input key,
output reg led,
input tx_busy,
output reg send_en, //ʹź
output reg [7:0] send_data //
);
//reg define
reg recv_done_d0;
reg recv_done_d1;
reg tx_ready;
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
send_en <= 1'b0;
send_data <= 8'd0;
end else begin
if (key == 1'b0) begin
led = ~led;
send_en <= 1'b1; //߷ʹźҪDZش
//if(recv_done_flag) begin
send_data <= 8'hff;
//end
end else send_en <= 1'b0;
end
end
endmodule
| 7.21207
|
module uart_send (
input sys_clk, //ϵͳʱ
input sys_rst_n, //ϵͳλ͵ƽЧ
input uart_en, //ʹź
input [7:0] uart_din, //
output uart_tx_busy, //æ״̬־
output reg uart_txd //UARTͶ˿
);
//parameter define
parameter CLK_FREQ = 50000000; //ϵͳʱƵ
parameter UART_BPS = 9600; //ڲ
localparam BPS_CNT = CLK_FREQ / UART_BPS; //ΪõָʣϵͳʱӼBPS_CNT
//reg define
reg uart_en_d0;
reg uart_en_d1;
reg [15:0] clk_cnt; //ϵͳʱӼ
reg [ 3:0] tx_cnt; //ݼ
reg tx_flag; //̱־ź
reg [ 7:0] tx_data; //Ĵ淢
//wire define
wire en_flag;
//*****************************************************
//** main code
//*****************************************************
//ڴڷиæ״̬־
assign uart_tx_busy = tx_flag;
//uart_enأõһʱڵź
assign en_flag = (~uart_en_d1) & uart_en_d0;
//Էʹźuart_enӳʱ
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
uart_en_d0 <= 1'b0;
uart_en_d1 <= 1'b0;
end else begin
uart_en_d0 <= uart_en;
uart_en_d1 <= uart_en_d0;
end
end
//źen_flagʱ,Ĵ͵ݣ뷢
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
tx_flag <= 1'b0;
tx_data <= 8'd0;
end else if (en_flag) begin //ʹ
tx_flag <= 1'b1; //뷢̣־λtx_flag
tx_data <= uart_din; //Ĵ͵
end //ֹͣλʱֹͣ
else if ((tx_cnt == 4'd9) && (clk_cnt == BPS_CNT - (BPS_CNT / 16))) begin
tx_flag <= 1'b0; //̽־λtx_flag
tx_data <= 8'd0;
end else begin
tx_flag <= tx_flag;
tx_data <= tx_data;
end
end
//뷢̺ϵͳʱӼ
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) clk_cnt <= 16'd0;
else if (tx_flag) begin //ڷ
if (clk_cnt < BPS_CNT - 1) clk_cnt <= clk_cnt + 1'b1;
else clk_cnt <= 16'd0; //ϵͳʱӼһں
end else clk_cnt <= 16'd0; //̽
end
//뷢̺ݼ
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) tx_cnt <= 4'd0;
else if (tx_flag) begin //ڷ
if (clk_cnt == BPS_CNT - 1) //ϵͳʱӼһ
tx_cnt <= tx_cnt + 1'b1; //ʱݼ1
else tx_cnt <= tx_cnt;
end else tx_cnt <= 4'd0; //̽
end
//ݷݼuartͶ˿ڸֵ
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) uart_txd <= 1'b1;
else if (tx_flag)
case (tx_cnt)
4'd0: uart_txd <= 1'b0; //ʼλ
4'd1: uart_txd <= tx_data[0]; //λλ
4'd2: uart_txd <= tx_data[1];
4'd3: uart_txd <= tx_data[2];
4'd4: uart_txd <= tx_data[3];
4'd5: uart_txd <= tx_data[4];
4'd6: uart_txd <= tx_data[5];
4'd7: uart_txd <= tx_data[6];
4'd8: uart_txd <= tx_data[7]; //λλ
4'd9: uart_txd <= 1'b1; //ֹͣλ
default: ;
endcase
else uart_txd <= 1'b1; //ʱͶ˿Ϊߵƽ
end
endmodule
| 7.549648
|
module top_module (
input a,
input b,
output q
);
// This is a combinational circuit with one gate. The truth table
// can be found by looking at the simulation waveforms.
assign q = a & b;
endmodule
| 7.203305
|
module top_module (
input clk,
input a,
input b,
output q,
output state
);
always @(posedge clk) begin
if (a == b) state <= a;
end
assign q = a ^ b ^ state;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = ~(a ^ b ^ c ^ d); // Fix me
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b & (d | c) | a & (c | d); // Fix me
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b | c; // Fix me
endmodule
| 7.203305
|
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case (c)
4'd0: q = b;
4'd1: q = e;
4'd2: q = a;
4'd3: q = d;
default: q = 4'hf;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [ 2:0] a,
output [15:0] q
);
always @(*) begin
case (a)
0: q = 16'h1232;
1: q = 16'haee0;
2: q = 16'h27d4;
3: q = 16'h5a0e;
4: q = 16'h2066;
5: q = 16'h64ce;
6: q = 16'hc526;
7: q = 16'h2f19;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input a,
output q
);
always @(posedge clk) begin
q <= ~a;
end
endmodule
| 7.203305
|
module top_module (
input clock,
input a,
output p,
output q
);
always @(*) begin
if (clock) begin
p = a;
end
end
always @(negedge clock) begin
q <= p;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input a,
output [3:0] q
);
always @(posedge clk) begin
if (a) q <= 4'd4;
else begin
if (q == 4'd6) q <= 0;
else q <= q + 1;
end
end
endmodule
| 7.203305
|
module mips_unsignal_extend (
inmediate_data,
unsig_extend_data
);
input [15:0] inmediate_data;
output [31:0] unsig_extend_data;
//assign unsig_extend_data = unsig_extend_data;
assign unsig_extend_data = {16'b0000000000000000, inmediate_data};
endmodule
| 6.998683
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output reg walk_left,
output reg walk_right,
output reg aaah,
output reg digging
);
reg walk_temp[1:0];
reg [63:0] dropping_time;
reg is_alive;
initial begin
walk_left = 1;
walk_right = 0;
aaah = 0;
digging = 0;
dropping_time = 0;
is_alive = 1;
end
always @(posedge clk) begin
if (areset) begin
walk_left = 1;
walk_right = 0;
aaah = 0;
digging = 0;
dropping_time = 0;
end else begin
if (is_alive) begin
if (ground == 0) begin
if (digging) begin
aaah = 1;
digging = 0;
end
if (aaah == 0) begin
walk_temp[0] = walk_left;
walk_temp[1] = walk_right;
aaah = 1;
digging = 0;
end
walk_left = 0;
walk_right = 0;
end else begin
if (aaah == 1) begin
walk_left = walk_temp[0];
walk_right = walk_temp[1];
aaah = 0;
end else begin
if (dig) begin
digging = 1;
walk_temp[0] = walk_left;
walk_temp[1] = walk_right;
walk_left = 0;
walk_right = 0;
end
if (digging == 0) begin
if (walk_left) begin
if (bump_left) begin
walk_left = 0;
walk_right = 1;
end
end else begin
if (bump_right) begin
walk_left = 1;
walk_right = 0;
end
end
end
end
end
if (aaah) begin
dropping_time = dropping_time + 1;
end else begin
if (dropping_time > 20) begin
is_alive = 0;
dropping_time = 0;
end
end
end
if (is_alive == 0) begin
walk_left = 0;
walk_right = 0;
digging = 0;
aaah = 0;
end
end
end
endmodule
| 7.203305
|
module top_module (
input [99:0] in,
output [99:0] out
);
integer i;
always @(*) begin
for (i = 0; i < 100; i++) begin
out[i] = in[99-i];
end
end
endmodule
| 7.203305
|
module ln4017 (
cp0,
cp1,
mr,
out_q,
q59_n
);
input cp0;
input cp1;
input mr;
output [9:0] out_q;
reg [9:0] out_d;
output q59_n;
always @(posedge mr) out_d <= 10'b1;
always @(posedge cp0) begin
if (!cp1 & !mr) begin
out_d[9:1] <= out_d[8:0];
out_d[0] <= out_d[9];
end
end
always @(negedge cp0) begin
if (cp1 & !mr) begin
out_d[9:1] <= out_d[8:0];
out_d[0] <= out_d[9];
end
end
assign q59_n = ~|out_d[9:5];
assign out_q = out_d;
endmodule
| 6.670254
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = (~IR[13:11]);
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = '0;
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = '1;
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module test_fifo (
rst_n,
w_clk,
w_en,
din,
r_clk,
r_en,
empty,
full,
dout
);
input rst_n;
input w_clk;
input w_en;
input [7:0] din;
input r_clk;
input r_en;
output empty;
output full;
output reg [7:0] dout;
reg [7:0] mem[7:0];
reg [3:0] w_ptr, r_ptr;
wire [2:0] w_addr, r_addr;
wire [3:0] w_ptr_gray, r_ptr_gray;
reg [3:0] w_r_d1, w_r_d2, r_w_d1, r_w_d2;
//the write process
always @(posedge w_clk or rst_n) begin
if (!rst_n) begin
w_ptr <= 4'd0;
end else begin
if ((!full) && w_en) w_ptr <= w_ptr + 1'b1;
else w_ptr <= w_ptr;
end
end
assign w_addr = w_ptr[2:0];
always @(posedge w_clk) begin
if ((!full) && w_en) mem[w_addr] <= din;
end
//the read process
always @(posedge r_clk or rst_n) begin
if (!rst_n) r_ptr <= 4'd0;
else begin
if ((!empty) && r_en) r_ptr <= r_ptr + 1'b1;
else r_ptr <= r_ptr;
end
end
assign r_addr = r_ptr[2:0];
always @(posedge r_clk) begin
if ((!empty) && r_en) dout <= mem[r_addr];
end
//the generation of empty or full flag
assign w_ptr_gray = w_ptr ^ (w_ptr >> 1);
always @(posedge r_clk or negedge rst_n) begin
if (!rst_n) begin
w_r_d1 <= 4'd0;
w_r_d2 <= 4'd0;
end else begin
w_r_d1 <= w_ptr_gray;
w_r_d2 <= w_r_d1;
end
end
assign empty = (w_r_d2 == r_ptr_gray);
assign r_ptr_gray = r_ptr ^ (r_ptr >> 1);
always @(posedge w_clk or negedge rst_n) begin
if (!rst_n) begin
r_w_d1 <= 4'd0;
r_w_d2 <= 4'd0;
end else begin
r_w_d1 <= r_ptr_gray;
r_w_d2 <= r_w_d1;
end
end
assign full=(r_w_d2[3]!=w_ptr_gray[3])&&(r_w_d2[2]!=w_ptr_gray[2])&&(r_w_d2[1:0]==w_ptr_gray[1:0]);
endmodule
| 6.798472
|
module test_fifo_tb ();
reg rst_n, wr_clk, wr_en, rd_clk, rd_en;
reg [`data_width-1:0] din;
wire full, empty;
wire [`data_width-1:0] dout;
reg [`data_width-1:0] temp = 0;
initial begin
rst_n = 1;
wr_clk = 0;
wr_en = 0;
rd_clk = 0;
rd_en = 0;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #5 wr_clk <= ~wr_clk;
always #16 rd_clk <= ~rd_clk;
test_fifo dut (
.rst_n(rst_n),
.w_clk(wr_clk),
.w_en (wr_en),
.r_clk(rd_clk),
.r_en (rd_en),
.din (din),
.full (full),
.empty(empty),
.dout (dout)
);
initial begin
#30 push(1);
push(2);
push(3);
push(4);
push(5);
push(6);
push(7);
push(8);
push(9);
push(10);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
#30 push(99);
push(100);
push(101);
push(102);
#30 pop(temp);
//push(100);
pop(temp);
end
task push(input [`data_width-1:0] data);
if (full) $display("---Cannot push %d: Buffer Full---", data);
else begin
$display("Push",, data);
din = data;
wr_en = 1;
@(posedge wr_clk);
#1 wr_en = 0;
end
endtask
task pop(output [`data_width-1:0] data);
if (empty) $display("---Cannot Pop: Buffer Empty---");
else begin
rd_en = 1;
@(posedge rd_clk);
#1 rd_en = 0;
data = dout;
$display("------Poped:",, data);
end
endtask
endmodule
| 6.552139
|
module top_module (
input [254:0] in,
output [ 7:0] out
);
integer i;
always @(*) begin
out = 8'b0;
for (i = 0; i < 255; i++) begin
if (in[i]) out = out + 1;
else out = out;
end
end
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (~(memory ? 6 : RD)), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = '0, Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = '1, Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
integer i;
always @(*) begin
sum[0] = a[0] ^ b[0] ^ cin;
cout[0] = (a[0] & b[0]) | (a[0] & cin) | (b[0] & cin);
for (i = 1; i < 100; i++) begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
cout[i] = (a[i] & b[i]) | (a[i] & cout[i-1]) | (b[i] & cout[i-1]);
end
end
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? (~6) : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? '0 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? '1 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : (~RD)), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : '0), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : '1), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = ((!memory) ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (0 ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (1 ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module used to change from one clock to anothor clock, glitch-free
// Author:WangFW
//Date:2020-8-5
module clock_change(clk1,clk0,rst_n,sel,clkout);
input clk1;
input clk0;
input rst_n;
input sel;
output clkout;
reg q1_p;
reg q1_n;
reg q0_p;
reg q0_n;
always @(negedge clk1 or negedge rst_n)
begin
if(!rst_n)
begin
q1_p<=1'b0;
q1_n<=1'b1;
end
else
begin
q1_p<=sel&&q0_n;
q1_n<=~(sel&&q0_n);
end
end
always @(negedge clk0 or negedge rst_n)
begin
if(!rst_n)
begin
q0_p<=1'b0;
q0_n<=1'b1;
end
else
begin
q0_p<=q1_n&&(~sel);
q0_n<=~(q1_n&&(~sel));
end
end
assign clkout=(clk1&&q1_p)||(clk0&&q0_p);
endmodule
| 6.601567
|
module clk_change_tb ();
reg clk1;
reg clk0;
reg sel;
reg rst_n;
wire clkout;
initial begin
clk1 = 0;
clk0 = 0;
sel = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
#50 sel = 1;
#50 sel = 0;
end
always #2 clk1 <= ~clk1;
always #4 clk0 <= ~clk0;
clock_change dut (
.clk1(clk1),
.clk0(clk0),
.rst_n(rst_n),
.sel(sel),
.clkout(clkout)
);
endmodule
| 7.065421
|
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] cout_temp;
bcd_fadd u_bcd_fadd (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.cout(cout_temp[0]),
.sum(sum[3:0])
);
generate
genvar i;
for (i = 1; i < 100; i = i + 1) begin : block1
bcd_fadd u_bcd_fadd (
.a(a[4*i+3 : 4*i]),
.b(b[4*i+3 : 4*i]),
.cin(cout_temp[i-1]),
.cout(cout_temp[i]),
.sum(sum[4*i+3 : 4*i])
);
end
endgenerate
assign cout = cout_temp[99];
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = (~RS);
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = '0;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = '1;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module async_clock_change (
clk1,
clk0,
rst_n,
sel,
clkout
);
input clk1;
input clk0;
input rst_n;
input sel;
output clkout;
reg q1;
reg q2_p, q2_n;
reg q3;
reg q4_p, q4_n;
always @(posedge clk1 or negedge rst_n) begin
if (!rst_n) begin
q1 <= 1'b0;
end else begin
q1 <= sel && (q4_n);
end
end
always @(negedge clk1 or negedge rst_n) begin
if (!rst_n) begin
q2_p <= 1'b0;
q2_n <= 1'b1;
end else begin
q2_p <= q1;
q2_n <= ~q1;
end
end
always @(posedge clk0 or negedge rst_n) begin
if (!rst_n) begin
q3 <= 1'b0;
end else begin
q3 <= (~sel) && (q2_n);
end
end
always @(negedge clk0 or negedge rst_n) begin
if (!rst_n) begin
q4_p <= 1'b0;
q4_n <= 1'b1;
end else begin
q4_p <= q3;
q4_n <= ~q3;
end
end
assign clkout = (q2_p && clk1) || (q4_p && clk0);
endmodule
| 7.7791
|
module async_clock_change_tb ();
reg clk1;
reg clk0;
reg sel;
reg rst_n;
wire clkout;
initial begin
clk1 = 0;
clk0 = 0;
sel = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
#50 sel = 1;
#50 sel = 0;
end
always #2 clk1 <= ~clk1;
always #5 clk0 <= ~clk0;
async_clock_change dut (
.clk1(clk1),
.clk0(clk0),
.rst_n(rst_n),
.sel(sel),
.clkout(clkout)
);
endmodule
| 7.7791
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = (~{{24{IR[15]}}, IR[15:8]});
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = '0;
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = '1;
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module edge_det_tb ();
reg clk, rstn, dat_i;
wire edge_rising, edge_falling, edge_both;
reg clk_i;
initial begin
clk = 0;
rstn = 1;
dat_i = 0;
clk_i = 0;
#10 rstn = 0;
#10 rstn = 1;
end
always #4 clk <= ~clk;
always #2 clk_i <= ~clk_i;
always @(posedge clk_i) dat_i <= {$random} % 2;
edge_det dut (
.clk(clk),
.rstn(rstn),
.dat_i(dat_i),
.edge_rising(edge_rising),
.edge_falling(edge_falling),
.edge_both(edge_both)
);
endmodule
| 7.041456
|
module top_module (
output out
);
assign out = 0;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{(~IR[15])}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module hs1_tb ();
reg clk;
reg rst_n;
wire [2:0] dout;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clk <= ~clk;
hs1 dut (
.clk (clk),
.rst_n(rst_n),
.dout (dout)
);
endmodule
| 6.549126
|
module top_module (
input in1,
input in2,
output out
);
assign out = ~(in1 | in2);
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {(~{24{IR[15]}}), IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, (~IR[15:8])};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module gray_bin (
gray,
bin
);
parameter length = 4;
input [length-1:0] gray;
output [length-1:0] bin;
reg [length-1:0] bin;
integer i;
always @(gray) begin
bin[length-1] = gray[length-1];
for (i = length - 2; i >= 0; i = i - 1) bin[i] = bin[i+1] ^ gray[i];
end
endmodule
| 6.68942
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.