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data2/json/DLP/1000256.json

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+{
+  "ticketNumber" : "1000256",
+  "reporterName" : "David ks",
+  "rankPoints" : "560",
+  "resolutionStatus" : "",
+  "ticketName" : "【TDA2EX】usecase 's chains_vipSingleCam_Display",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Other Parts Discussed in Thread: TDA2EG-17, TDA2 Dear all, I am a beginner , I have a question About Tda2ex Vision_SDK V03.08 The sensor I use is VID_SENSOR_SAT0088_OV1063X My Pinmux is set up . I cannot detect my ub96x version , Didn’t register him in I2c? Are there relevant documents to help understand this part of the problem? Or tell me how to solve it ! ----------------------------------------(About Key program)-------------------------------------------------- (Bsputils_ub960.c Func Name:BspUtils_appGetUb96xVersion) retVal = Bsp_deviceRead8( UB960_ACCESSIBLE_FROM_I2C_INST, //1 gSlaveAliases[instId].slaveAddr,//0x3D &tempAddr, //0xF5 &tempData, //0x00 (UInt32) 1U); ******************************************************************************************************* (bsp_deviceI2c.c Func Name :Bsp_deviceRead8) retVal = GIO_submit( gBspDevObj.i2cHndl[i2cInstId], How to register or be assigned?? Is this the problem? (UInt32) IOM_WRITE, &i2cParams, &i2cParams.bufLen, NULL); ------------------------------------------------------------------------------------------------------- My log is ------------------------------------------------------------------------------------------------------ [IPU1-0] 28.636399 s: i2cMdSubmitChan: i2c transfer Timeout IRQ not received [IPU1-0] 28.637802 s: src/bsp_deviceI2c.c @ Line 352: [IPU1-0] 28.637894 s: Nrtos I2C4: DEV 0x3d: RD 0xf5 ... ERROR !!! [IPU1-0] 28.638260 s: src/bsp_deviceI2c.c @ Line 420: [IPU1-0] 28.638351 s: I2C4: Error timeout 5002 ms!!! [IPU1-0] 28.638443 s: Updated UB964 to 2 Lanes !!! [IPU1-0] 28.638504 s: BspUtils_appGetUb96xVersion [IPU1-0] 33.638382 s: [IPU1-0] 33.638626 s: i2cMdSubmitChan: i2c transfer Timeout IRQ not received [IPU1-0] 33.640029 s: src/bsp_deviceI2c.c @ Line 352: [IPU1-0] 33.640120 s: Nrtos I2C4: DEV 0x3d: RD 0xf5 ... ERROR !!! [IPU1-0] 33.640395 s: src/bsp_deviceI2c.c @ Line 420: [IPU1-0] 33.640486 s: I2C4: Error timeout 5001 ms!!! [IPU1-0] 38.640395 s: [IPU1-0] 38.640669 s: i2cMdSubmitChan: i2c transfer Timeout IRQ not received [IPU1-0] 38.642072 s: src/bsp_deviceI2c.c @ Line 588: [IPU1-0] 38.642164 s: I2C4: DEV 0x3d: WR 0x01 = 0x03 ... ERROR !!! [IPU1-0] 38.642255 s: src/bsp_deviceI2c.c @ Line 610: [IPU1-0] 38.642347 s: I2C4: Error timeout 5002 ms!!! [IPU1-0] 38.642438 s: src/bsputils_ub960.c @ Line 1321: [IPU1-0] 38.642530 s: Could not configure UB960 !!! ------------------------------------------------------------------------------------ THANK YOU!!!><",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi David, Please refer to your board schematic to figure out ub960 i2c address. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, This is my I2c setting, Is there something wrong? Thanks!!",
+    "imageList" : [ "Data/input/1000256/png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "TDA2eg-17 datasheet",
+    "imageList" : [ "Data/input/1000256/PNG" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi David, this tells that ub96x is connected over i2c4 lines, but not what is the i2c client address.. On EVM, we typically use 0x30 or 0x3D addresses, but it really depends on two inputs lines to the ub96x. Depending on these two lines, i2c address is decided. Please check your schematic and ub96x data sheet to understand and to know i2c address for ub96x. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, ----------------------------------------------------------------- Q1: Our image camera uses the serdes interface The receiver of the serdes interface is UB962 TDA2 used on the circuit diagram is connected to ub962 using i2c4 The address we use is 0x3d \"We want to know how to control ub962 through i2c4\" How to control him through i2c4 I want to ask about the process(flow) on the software Start with these actions of poweron/inital and so on EX. setting pinmux What are the other steps to do? Are there any related documents? ----------------------------------------------------------------- Q2: It seems to be controlled through gio_submit How to use it Whether to do the corresponding registration?, etc. ----------------------------------------------------------------- Thank you very much!!",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Can you please look into VidSensor_create API in the file vision_sdk\\apps\\src\\rtos\\video_sensor\\src\\ov10635\\vid_sensor_ov10635.c? This file is the one, which configures ub96x devices for the sensor. It uses API BspUtils_appInitUb960 to configure them, which is implemented inside PDK. You would have to change this API in PDK to change i2c instance. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, Because I still haven't solved this problem,Can you tell me some more details? Is it necessary to set something in Bsp_deviceI2cInit? Or other places? Can you give an example of the setting process? To solve the problem of why we cannot detect the UB964 version? According to my information above Thank you for your help>< David",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, Second question, where can these objects be set? Does this require us to set? Please help me with these two questions Thank you!! David",
+    "imageList" : [ "Data/input/1000256/GIF" ]
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, I'm afraid I didn't explain it carefully enough, so I added something like this picture explain(The text in the picture) Or is it related to this parameter, something needs to be registered during initialization? l Thanks David",
+    "imageList" : [ "Data/input/1000256/GIF", "Data/input/1000256/GIF" ]
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, If I have insufficient information, please let me know, and I will try to explain it clearly. Mainly I want to know why it can't be detected in get Version (our version is ub962) Maybe where is not set up? According to the question I said above Please help ! Thanks you...!! David",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, Can this part tell me clearly? I may know the general direction but I don’t know the details (Regarding what I described above) Can you point me in some direction, Please! Thank you very much!! David",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi David, I am sorry i am not getting the issue.. If not video_sensor layer, you could directly try writing to SERDES register from the usecase. There are i2c APIs, that can be used to write directly from the usecase itself. Also which i2c instance are you using? If it is not allocated/enabled, you might have to add it to Linux dtb files. But before all of these, are you trying to enable this SERDES for the first time? I mean, is it brought up from HW perspective? Rgds, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, Can you tell me in detail about the settings of the software layer that need to be done (Settings), and where? For example, which parameter in the table or which parameter needs to be initialized or set. According to my description above, what else needs to be set at the software layer? (ex. bsp_deviceI2c.c Func: Bsp_deviceI2cInit need setting?) (If the software layer is not set) Thanks a lot!! David",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, like this, About Bsp_deviceRead8 UB960_ACCESSIBLE_FROM_I2C_INST, //4 gSlaveAliases[instId].slaveAddr,//0x3D &tempAddr, //0xF5 &tempData, //0x00 (UInt32) 1U); ----------------------------------------- Where is the software layer in the front that needs to be set? (\"Probably\" is about not setting it before) but I'm not sure where Can you tell me some details that I didn't notice At present, the parameters passed out here should be no problem (except for the first parameter is uncertain) Thanks! David",
+    "imageList" : [ "Data/input/1000256/GIF" ]
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, Because I am confused about some software layers I want to confirm whether the software layer is set up first Regarding the questions I mentioned above, can you help me understand better? (Software layer) Thanks a lot!! David",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi David, I am sorry i could not get the question. I guess you just want to configure SERDES and camera. You could actually completely bypass software layer for it. You could use direct i2c APIs to write to SERDES/Camera register from the usecase. When you generate the usecase, it will generate usecase_priv.c file and usecase.c file. You could add an function in usecase.c file to write to these i2c clients. For I2C, you could use APIs like Bsp_deviceWrite8,Bsp_deviceWrite16 to write to 8bit and 16bit address/value pair. These APIs does not require i2c handle, it just needs i2c instance id, slave address, register and value.. We just need to make sure that the i2c instance that you want to use is allocated to M4 driver. and initialized in the PDK. For that, can you see and update Board API Bsp_boardGetI2cData and include this i2c instance on M4? Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, I have used Bsp_deviceWrite8 here to get UB96X Version According to the first parameter Mainly we want to ask How to set up the instance i2c and how to connect to the real I2C4 (pre-work) Thanks! David",
+    "imageList" : [ "Data/input/1000256/GIF" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hello David, Do you mean which instance id to be used for i2c4 ? Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, Because I have some doubts about the software layer Our DEVICE uses i2C4 to connect to ub962 then, I mean we use Bsp_deviceRead8 Get Version But It did not detect the version of ub962 --------------------------------------------------------------------- Bsp_deviceRead8 ( UB960_ACCESSIBLE_FROM_I2C_INST, //4 (-> The previous steps or initialization did not do the setting or connection, which caused the error that the device could not be detected version?) gSlaveAliases[instId].slaveAddr, //0x3D &tempAddr, //0xF5 &tempData, //0x00 (UInt32) 1U); Thanks >< David",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi David, Is ub962 powered on? or anything on board required to power on ub962? or is there any other mux available in between to enable i2c transactions? Do you have any other device also connected on i2c4? Can try probing this device? Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, Ub962 seems to be powered on ,and nor other mux enanle i2c No other devices also use i2c4 Are there any initialization places that need to be set?(About how to setting of linking ub962) and other questions I am looking at bsp_deviceI2c.c Func:Bsp_deviceI2cInit(void) The parameters in gBspDevObj.i2cHndl[i2cInstId] , Where is this parameter set? and  ioParams.packets = &(gBspDevObj.i2cIomPacket[i2cInstId][0]); Why are all the parameters I printed out empty? (Paramters :addr , size ,arg , cmd , status ,misc) Thanks! David",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi David, I dont understand \"About how to setting of linking ub962\" ?? Please check the Bsp_deviceI2cInit, this API sets the i2cHandle at around line number 163. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Brijesh, \"Please check the Bsp_deviceI2cInit, this API sets the i2cHandle at around line number 163.\"  I watched this ,but I have some confusion , Can you tell me about \"where\" the parameters are set (inside)? I have tried to track the code(inside),But I don’t know how to look inside Can you tell me some hints and how to see it(Setting parameters) (inside :gBspDevObj.i2cHndl[i2cInstId] = GIO_handle(&gBspDevObj.i2cGioStruct[i2cInstId]);) Thanks a lot! David",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Parameters are set in GIO_construct. I would suggest to put breakpoint on this API and see the code flow. Rgds, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1000341.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1000341",
+  "reporterName" : "Pingjiao Lee",
+  "rankPoints" : "30",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: TDA2SXBTQABCRQ1",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 1. How many watchdog timers in TDA2SXBTQABCRQ1 and where? 2. The MPU has its own watchdog timer that is different from watchdog timer in the PRCM? 3.IPU and DSP use the watchdog in the PRCM? If so, how to distinguish the error output by watchdog? 4. The following picture is from TDA2 technical reference manual chapter 18.4.6. When T is not within threshold low to threshold high, the output alert maybe do not be asserted to 1, like the blue arrow in the picture. Why? thank you!",
+  "imageList" : [ "Data/input/1000341/png" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "1. 2 watchdog timers. 1x system watchdog and 1x MPU watchdog timer. 2. yes. 3. One watchdog timer can only be used by either IPU or DSP. You can also use GP Timer as watchdog timer. 4. Alert (Temp too high) is generated first when the temp goes above the high threshold and the next alert (Temp is safe) is generated only when the temp goes below the low threshold. In between this two events is where you have to do thermal management to lower the temp to avoid thermal shutdown.",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1000532.json

@@ -0,0 +1,106 @@
+{
+  "ticketNumber" : "1000532",
+  "reporterName" : "Asher Farooqui",
+  "rankPoints" : "1821",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2EXEVM: Communication with another SPI slave",
+  "rankName" : "Expert",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, Can you please give some directions on how to share the TDA2 SPI Master (there are 4 SPI Modules that can be Master where each module has support for 4 Slaves (4 CS))? There is an API in Utils_mcspi.c that I am looking at as a reference. Upon boots, the Radar SDK initializes 4 SPI instances using channel 0 (CS0) to set up SPI communications with the 4 attached AWRs. My questions are as follows: 1. Why is it not necessary to call Utils_mcspiOpen() during AWR Init? 2. Why static Utils_mcspiDeviceCommObj gUtils_mcspiDeviceCommObj[UTILS_MCSPI_NUM_DEVICES]; where UTILS_MCSPI_NUM_DEVICES = 8? I thought there are 4 SPI modules only. 3. In my application where I share SPI Module0 using CS1 to communicate with my slave device, I called the Utils_mcspiOpen() specifying the deviceId = 0, mcSpiDevInstNum = 0, mcSpiChannelNum = 1. This resulted in a crash during boot. Debugged into it said the FIFO has already been in use. 4. The thought in calling Utils_mcspiOpen() was because the SPI 4 instances have already been initialized during AWRs setup. I assume I need to call Open() before calling Utils_mcspiRead()/Write(). Thank you in advance,",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, Each McSPI can support up to 4 Master but only 1 Slave. 1. SPI is needed for configuration so as long as it is called before radar configuration step, it is fine. 2. UTILS_MCSPI_NUM_DEVICES is just a number to limit the total number of external devices which can be connected to SPIx, not number of SPI modules. It is just a number we picked. Each McSPI as master can connect up to 4 devices. 3. deviceId is the index of the radar devices, not mcspi instance id. If you already have one radar with CS0 on McSPI1 (mcspi instance 0), this would be deviceId =1. 4. _Init() then _open() to get handle. After that, use the handle to call read/write. Regards, Stanley",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Asher Farooqui",
+    "rankPoints" : "1821",
+    "rankName" : "Expert",
+    "date" : "",
+    "userId" : "/members/6193894",
+    "content" : "Hi Stanley, Thanks for the clarifications. Got a bit further. We need a bit more clarity to get this working. 1. is mcSpiChannelNum in Utils_mcspiOpen() the same as ChipSelect? If not, don't I need to specify the CS# on the mcSpi module? 2. I now called Utils_mcspiInit(1) and then called Utils_mcspiOpen(1, 0, 1, edmaHandle) to get a valid SPI handle. This resulted in a UTILS_MCSPI: McSPI GIO Create Failed!! on the console. After it crashed. 3. So looks like we still don't completely understand the API usage. Thanks,",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Asher Farooqui",
+    "rankPoints" : "1821",
+    "rankName" : "Expert",
+    "date" : "",
+    "userId" : "/members/6193894",
+    "content" : "Any Suggestions?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi Asher, I am not sure I follow what you are trying to implement here. Are you using radar driver in SDK? If yes, radar SPI driver is implemented in ~/pdk_xx_xx_xx_xx/packages/ti/drv/vps/src/devices/radar_ar12xx/src/bspdrv_ar12xxMcspiCfgPriv.c. Only Utils_mcspiInit() is called from use case to add the McSPI instace to GIO device and configure crossbar for interrupt. The instance will be opened later by radar SPI driver in PDK. To configure radar, we use radar APIs from rl_sensor.c in ~/mmwave_dfp/ti/control/mmwavelink/src/rl_sensor.c, which has the callback hooked to radar SPI driver. We don't directly call McSPI APIs from use case since SPI protocol is implemented by radar link layer. Regards, Stanley",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "In addition, please note that Utils_mcspiInit(UInt32 mcSpiInstNum) where mcSpiInstNum = 0 (McSPI1), 1 (McSPI2), 2...",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Khai Trinh",
+    "rankPoints" : "4140",
+    "rankName" : "Genius",
+    "date" : "",
+    "userId" : "/members/5835029",
+    "content" : "Hi Stanley, Sorry for the confusion. Let me start this over again. We would like to use (configure) one of the 4 mcSPI modules on the TDA2 to communicate with a SPI slave device. Please provide steps on how that can be done. We went thru the utils_mcspi.c in radar SDK thinking that that's the API we should be using as awr12xx configuration is using that utils API to configure AWR. We read the TDA2 datasheet and it indicated that each MCSPI module can support 4 slave. Is this not the case? I think you briefly stated that \"Each McSPI can support up to 4 Master but only 1 Slave\". Does that mean we cannot use SPI to talk to our external device over SPI? If this is true, then case close. SPI is not the solution. If mcSPI module can be used, then please provide instructions on how to add a SPI slave to an mcSPI module using chip select knowing that each mcSPI module is a Master to each slave AWR. Thanks, --Khai",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Khai Trinh said: We read the TDA2 datasheet and it indicated that each MCSPI module can support 4 slave. Is this not the case? What I meant was when McSPI is the master, it can support up to 4 slave devices with 4 CSn. So, yes, each McSPI module as master can connect to 4 slaves. Which external SPI slave device are you connecting to? Radar or something else? If it is radar, why don't you use our radar SPI driver? Regards, Stanley",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Khai Trinh",
+    "rankPoints" : "4140",
+    "rankName" : "Genius",
+    "date" : "",
+    "userId" : "/members/5835029",
+    "content" : "Another SPI slave device. Please provide step-by-step instructions on how to configure it. i have tried Uitls_mcSPI.c API. If you go back to my questions below: Thanks for the clarifications. Got a bit further. We need a bit more clarity to get this working. 1. is mcSpiChannelNum in Utils_mcspiOpen() the same as ChipSelect? If not, don't I need to specify the CS# on the mcSpi module? 2. I now called Utils_mcspiInit(1) and then called Utils_mcspiOpen(1, 0, 1, edmaHandle) to get a valid SPI handle. This resulted in a UTILS_MCSPI: McSPI GIO Create Failed!! on the console. After it crashed. 3. So looks like we still don't completely understand the API usage. Thanks, --Khai You gave some hint on i",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Khai Trinh",
+    "rankPoints" : "4140",
+    "rankName" : "Genius",
+    "date" : "",
+    "userId" : "/members/5835029",
+    "content" : "Hi Stanley, Just want to follow on this topic. Can you please advice... The current setup in the SDK is each mcSPI module is a Master on processor side with an AWR as a slave. So 4 mcSPI modules pairing with 4 AWR slaves. That part I don't have to do anything. It's all working as is. Now I need to add another SPI slave device to 1 of the 4 Master. So we need to configure a ChipSelect on the Master side. How that can be done thru the Utils_mcSPI.c API is really my question. I have tried a few things I described above without any luck. If you have an answer, please describe it here so I can try it out. For something like this, a conf call can be much more productive. Thanks,",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, Ok. It makes more sense now. 1. You don't have to call Utils_mcspiInit(instId) again because each instance only needs to be initialized once. Since you are using one of the instances which is used by radar, it is already called in ChainsCommon_ar12xxInit(). Make sure you open SPI channel only after ChainsCommon_ar12xxInit(). 2. FIFO mode can be enabled on only one channel per McSPI instance. Utils_mcspiOpen() keeps track of it in its scope. However, Radar driver enables FIFO mode in its own open call outside of Utils_mscpiOpen(). For your use case to work, you have to disable FIFO mode in Utils_mcspiOpen(). You can change the below line in Utils_mcspiOpen() to 1 to disable FIFO mode. static UInt32 fifoEnabled[UTILS_MCSPI_NUM_MCSPI_INST] = {1U, 1U, 1U, 1U}; Please give this a try and see if it works. Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1000797.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1000797",
+  "reporterName" : "QI Jang",
+  "rankPoints" : "60",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2HV: TI support of QEMU for TDA2 APP",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hi there, 1. Does QEMU support TDA2 APP? I have been searching for some time but in QEMU says that if the TDA2 machine is not listed than is very unlikely to be supported. 2. Is there any emulator support to test app without a board? I need it for testing. The board can be damaged by a quick test. 3. Can I convert my Application Image back to ELF? In my opinion, it is converted to ELF -> Application Image(RPRC) using the following command. ``` out2rprc.exe <App_In_name(elf or coff)> <App_out_name> ``` Please let me know if it supported. Any guidance would be appreciated. Regards,",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, 1. No. We don't have QEMU support on TDA2. 2. No. We don't have emulator for TDA2. 3. No. We don't have utility to covert AppImage back to multiple Elf files. Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1001310.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1001310",
+  "reporterName" : "Wu YiTing",
+  "rankPoints" : "470",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2EVM5777: How to use I2C high speed mode?",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi expert, We have a requirement to use I2C5 to communicate between TDA2 SOC and MCU. I checked the Source code and found the I2C API path. Would this API support high speed mode and is easy to apply on the vision sdk? If it is not applicable, is there any other sample code? C:\\PROCESSOR_SDK_VISION_03_05_00_00\\ti_components\\drivers\\pdk_01_10_01_06\\packages\\ti\\drv\\stw_lld\\i2clld\\src\\lld_hsi2c.c",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, The supported i2c bus speed is 100Khz and 400Khz for this I2C driver. It doesn't support HS mode. We don't have example i2c driver for HS mode. However, the I2C hardware on TDA2 is capable of running HS mode. Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1001510.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1001510",
+  "reporterName" : "QI Jang",
+  "rankPoints" : "60",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2HV: CLANG and LLVM build support",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hello Does the tda processor support \"clang\" builds? If applying, where should I edit it?",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Vineet Roy",
+    "rankPoints" : "37435",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/1643173",
+    "content" : "Hi, Not supported and no plans to add it for TDA2. Note : There is a plan to add support for TDA4 devices in next release Regards Vineet",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1001590.json

@@ -0,0 +1,43 @@
+{
+  "ticketNumber" : "1001590",
+  "reporterName" : "Ahmed Anwar",
+  "rankPoints" : "260",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: Problems with the TIDL library import tool",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello, I am trying to use TIDL library on TDA2PX EVM to run DNNs on EVE and DSP cores. I am using TensorFlow as a framework. I am following the user guide with the title \" TI Deep learning Library on TDAx \" - November 2019. The user guide states that \" TIDL supports slim based tensorflow models \". Does TIDL library supports only slim based TensorFlow models ? Does it mean that I can not import models trained in TensorFlow, not TensorFlow slim? I have tried to import MobileNet V2 from TensorFlow Keras applications using the TIDL library, but I get error mesages saying that \"Pad Layer is not supported by TIDL and cannot be merged into any TIDL layer\". Moreover, I need to know where I can find the file \"optimize_for_inference.py\". Thanks, Ahmed Anwar",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi Ahmed, >> Does it mean that I can not import models trained in TensorFlow, not TensorFlow slim? Yes, TIDL on TDA2 can import only TensorFlow slim models. On TDA4 we support TensorFlow models also. >> but I get error mesages saying that \"Pad Layer is not supported by TIDL and cannot be merged into any TIDL layer\" This is because of Pad layer is not supported, refer to datasheet for all the supported layers >> I need to know where I can find the file \"optimize_for_inference.py\" This is available in \"tensorflow/python/tools\" folder Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hello Praveen, Thank you for your reply. I have a question regarding the TensorFlow slim models. In the user guide, there is an example of a Keras/TensorFlow model which can be found here. This example uses Keras from TensorFlow, not TensorFlow slim, to build a simple CNN, which can be used as an input to the TIDL import tool. Does this mean that I can use Keras from TensorFlow, not TensorFlow slim, to build a CNN and use it as an input to the TIDL import tool ? I just need to understand this point better, as most of my development is already in Keras/TensorFlow, and the example that I mentioned also uses Keras/TensorFlow. However, based on your reply, \"TIDL on TDA2 can import only TensorFlow slim models\". Would you please illustrate how this example uses Keras/TensorFlow if only TensorFlow slim models are supported on TDA2 ? Thanks, Ahmed Anwar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Yes, We have limited layers support for Tesnsoflow in TDA2, where as most of the layers are supported with Caffe/Tensorflow slim models. Please refer to below comment in the user guide section 3.6.5. \" We have developed/defined TIDL library layers based on the layer types Caffe framework. Most of our test cases (Layer level and network level) and demos are based caffe framework. With respect to Tensorflow, we have validated two pre-trained models from tensorflow github (Slim based Mobilenet V1 and Googlenet/inceptionetV1), this covers most of the CNN layers (Convolution, Max Pooling , Average pooling, Batch norm, Fully connected layer, softmax, Relu, Relu6, concate etc). \" Thanks, Praveen",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1002851.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1002851",
+  "reporterName" : "Pablo Trevisani",
+  "rankPoints" : "50",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2E: Counting an external signal edge",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2E Other Parts Discussed in Thread: MMWCAS-DSP-EVM Hello. I need to count the rise or falling edges of an external clock signal which frequency is up to 300 kHz using the TDA2xx on the MMWCAS-DSP-EVM board (I just use the Ethernet peripheral so I can unmount lot of components if necessary). As you can imagine using an interrupt approach is not reliable at such high frequency, so, I intend to use a counter module that directly writes into a register the number of time the specific edge arrives. I took a look into \"Timers\" chapter inside TRM document (SPRUI29G) but it seams there is no way to increment the counter register using an external source. Could somebody provide me some guide? Which other module can I use to reach my goal? Thanks in advice, Pablo.",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, You can refer to TRM Ch 28 PWM which has eCAP to capture input signal. However, you have to check if EVM has exposed any pin which is routed to eCAP. https://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/PWM.html Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1004827.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1004827",
+  "reporterName" : "Antoine Chapuis1",
+  "rankPoints" : "3615",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA4VM: Linux OS memory size",
+  "rankName" : "Expert",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hello Jacinto team, My customer is considering TDA4 for its Automotive Vision application, and they are asking me about the size that Linux OS takes on theTDA4 SoC: from previous experience with TDA2, they know Linux took ~1Gb of Flash memory. Do you know what is the memory requirement for Linux OS on TDA4 ? Best regards, Antoine",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Keerthy J",
+    "rankPoints" : "132000",
+    "rankName" : "TI__Guru***",
+    "date" : "",
+    "userId" : "/members/1025801",
+    "content" : "Hi Antoine, This is the output of free command on our latest 7.3 Linux SDK. So ~1 GB with Linux. ~3GB is free out of total 4GB DDR on board. If no other questions please click verify answer. Best Regards, Keerthy",
+    "imageList" : [ "Data/input/1004827/png" ]
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1005296.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1005296",
+  "reporterName" : "Anyong Jiang",
+  "rankPoints" : "110",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: how to use Image pyramid algorithm link in vision sdk for tda2",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 I want to use Image pyramid algorithm link in vision sdk for tda2, this algorithm link is supported on M4, but the comment for this algorithm link in algorithmLink.h says: \"Image pyramid algorithm link. Only valid for TDA3x\" typedef enum { ALGORITHM_LINK_IPU_ALG_DMA_SWMS = 0, /**< Alg to DMA based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_OBJECT_DRAW = 1, /**< Alg to draw rectangles on the image (Needed by PD) */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB = 2, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB1 = 3, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_HW_CRC = 4, /**< CRC for checking Frame Freeze Detect on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_IMG_PYRAMID = 5, /**< Image pyramid algorithm link. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_SCENE_OBSTRUCTION_DETECT = 6, /** < Alg to perform SCENE obstruction detection */ ALGORITHM_LINK_IPU_ALG_DEWARP = 7, /**< Plugin to that supports DeWarpping of images, depends on SIMCOP/TDA3x*/ ALGORITHM_LINK_IPU_ALG_RADAR_PROCESS = 8, /**< Alg to perform radar processing */ ALGORITHM_LINK_IPU_ALG_RVC_DIAGNOSTIC = 9, /**< Plugin to support Robust RVC diagnostics register only for TDA2xx */ ALGORITHM_LINK_IPU_ALG_OPENVX = 10, /**< Pluging to support OpenVX */ ALGORITHM_LINK_IPU_ALG_TIDLPREPROC = 11, /**< Alg to do TIDL Pre Process */ ALGORITHM_LINK_IPU_ALG_VPE_SWMS = 12, /**< Alg to VPE based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB2 = 13, /**< AEWB for ISS running on IPU1-0 in SRV demo. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_OPENVX_TIDL = 14, /**< Pluging to support OpenVX TIDL */ ALGORITHM_LINK_IPU_ALG_MAXNUM = 15, /**< Should be the last value of this enumeration. * Will be used by Link/driver for validating the input parameters. */ ALGORITHM_LINK_IPU_ALG_FORCE32BITS = 0x7FFFFFFF /**< This should be the last value after the max enumeration value. * This is to make sure enum size defaults to 32 bits always regardless * of compiler. */ } AlgorithmLink_IpuAlgorithmId; I don't know why this link is not valid for tda2x. If I want to use this LINK for tda2x , how to do ? thanks",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "This is duplicate of below thread, so closing this thread. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1005297/tda2sx-how-to-use-image-pyramid-algorithm-link-in-vision-sdk-for-tda2 Regards, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1005297.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1005297",
+  "reporterName" : "Anyong Jiang",
+  "rankPoints" : "110",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: how to use Image pyramid algorithm link in vision sdk for tda2",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 I want to use Image pyramid algorithm link in vision sdk for tda2, this algorithm link is supported on M4, but the comment for this algorithm link in algorithmLink.h says: \"Image pyramid algorithm link. Only valid for TDA3x\" typedef enum { ALGORITHM_LINK_IPU_ALG_DMA_SWMS = 0, /**< Alg to DMA based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_OBJECT_DRAW = 1, /**< Alg to draw rectangles on the image (Needed by PD) */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB = 2, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB1 = 3, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_HW_CRC = 4, /**< CRC for checking Frame Freeze Detect on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_IMG_PYRAMID = 5, /**< Image pyramid algorithm link. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_SCENE_OBSTRUCTION_DETECT = 6, /** < Alg to perform SCENE obstruction detection */ ALGORITHM_LINK_IPU_ALG_DEWARP = 7, /**< Plugin to that supports DeWarpping of images, depends on SIMCOP/TDA3x*/ ALGORITHM_LINK_IPU_ALG_RADAR_PROCESS = 8, /**< Alg to perform radar processing */ ALGORITHM_LINK_IPU_ALG_RVC_DIAGNOSTIC = 9, /**< Plugin to support Robust RVC diagnostics register only for TDA2xx */ ALGORITHM_LINK_IPU_ALG_OPENVX = 10, /**< Pluging to support OpenVX */ ALGORITHM_LINK_IPU_ALG_TIDLPREPROC = 11, /**< Alg to do TIDL Pre Process */ ALGORITHM_LINK_IPU_ALG_VPE_SWMS = 12, /**< Alg to VPE based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB2 = 13, /**< AEWB for ISS running on IPU1-0 in SRV demo. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_OPENVX_TIDL = 14, /**< Pluging to support OpenVX TIDL */ ALGORITHM_LINK_IPU_ALG_MAXNUM = 15, /**< Should be the last value of this enumeration. * Will be used by Link/driver for validating the input parameters. */ ALGORITHM_LINK_IPU_ALG_FORCE32BITS = 0x7FFFFFFF /**< This should be the last value after the max enumeration value. * This is to make sure enum size defaults to 32 bits always regardless * of compiler. */ } AlgorithmLink_IpuAlgorithmId; I don't know why this link is not valid for tda2x. If I want to use this LINK for tda2x , how to do ? thanks",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, It was initially implemented using resizer, which is available on TDA3x. But could you please if it internally uses VPE driver? Then it can even be enabled on TDA2x. Regards, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1005841.json

@@ -0,0 +1,70 @@
+{
+  "ticketNumber" : "1005841",
+  "reporterName" : "Ahmed Anwar",
+  "rankPoints" : "260",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: TIDL Import Tool and Inference on the TDA2Px EVM",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Hello, I am trying to run custom deep learning models on the TDA2Px EVM. As I understand, in order to run Deep Learning models on the board, TIDL library is used. The TIDL import tool generates binary files that represent the network and parameters of the model. What I also understand from this step is that the tool translates the input model from a framework like TensoFlow to a format that can be executed on DSP and EVE cores. When I tried to understand how to use the generated files for inference on the board, I found section 3.3.4 (Building the Test Application Executable through GMAKE) in the TIDL library which discusses how to load the .out files of the sample test application on the DSP and EVE cores using Code Compuser Studio (CCS). I want to understand these points: - What is the link between the TIDL import tool output binary files and building the .out files (dsp_test_dl_algo.out and dsp_test_dl_algo.out) for inference on the board ? The user guide states that for building the sample test application project I should execute the command (gmake CORE=dsp all) for DSP and (gmake CORE=eve all) for EVE. What about a different custom model ? What changes should I make and how to link the translated model by the TIDL import tool in order to build the (dsp_test_dl_algo.out and eve_test_dl_algo.out) files for my custom model? - Is there a way to run the .out files on the board without using CCS ? I want to run the models on the board using only a terminal, is it possible ? - Is there a specific OS that should be installed on an SD card for booting the board to run TIDL applications ? - I am facing some issues for setting a stable workflow for model deployment on TDA2PX EVM. I usually have custom trained deep learning models in TensorFlow and I am trying to deploy those models on the TDA2Px EVM. If there are any documentations or tutorials in addition to the provided user guides, please let me know. Thanks, Ahmed Anwar",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi Ahmed Anwar, 1. There is no dependency on \"TIDL import tool output binary files\" for building the .out files, these bin files are input which you need to specify in the infer config file. 2. Yes, you can run TIDL on the board without CCS, for that refer to TIDL OD usecase in the Vision SDK. 3. No, just follow the steps in Vision SDK user guide. 4. Refer to TIDL usecases section in the Vision SDK user guide. Overall, you can run TIDL on the board without CCS by using TIDL usecases, I would recommend to run the existing usecase as is first and once it is working then replace the \"params\" and \"net\" binary files in the SD card with your bin files and run. You can also refer to below e2e thread to import and run our pre-trained SSD model in the TIDL OD usecase. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/689617/tda2-how-to-run-ssd-based-tidl-od-use-case-in-vision-sdk-with-pre-trained-model Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hi Praveen, Thank you for your reply. I would like to understand these points: - What is the usage of the .out files (dsp_test_dl_algo.out and dsp_test_dl_algo.out) ? As I understand, I need only the network and parameters .bin files for running a model on the board using TIDL usecases.Would you please let me know what the usage of the .out files is ? Do I need them or just I need the .bin files ? - In the Vision SDK TIDL User Guide, in section 5 \"Build and Run TIDL Object detect use case\", these statements are present: \"The TIDL Object detect use case is enabled and runs on TDA2XX SoC only.\" \"Build the Vision SDK for TDA2XX BIOS configuration choosing the ‘MAKECONFIG?=tda2xx_evm_bios_all’ in the Rules.make.\" \"Please refer to the ‘VisionSDK_UserGuide_TDA2xx.pdf’ for steps on building and running the Vision SDK.\" I am using TDA2PX, not TDA2XX. Does this mean that I can not run TIDL models and usecases on TDA2PX ? If TDA2PX supports TIDL usecases, should I follow \"VisionSDK_UserGuide_TDA2xx.pdf\" as stated or \"VisionSDK_UserGuide_TDA2px.pdf’\" ? Thanks, Ahmed Anwar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi, >> What is the usage of the .out files (dsp_test_dl_algo.out and dsp_test_dl_algo.out) ? These .out files are required to when you connect the board to CCS and run TIDL on CCS based setup, but if you want to run TIDL without CCS then these .out files are not required. >> I am using TDA2PX, not TDA2XX. Does this mean that I can not run TIDL models and usecases on TDA2PX ? No, you can run TIDL models and usecases on TDA2PX, please refer to \"VisionSDK_UserGuide_TDA2px.pdf\" file. FYI, many customers were successfully able to run TIDL usecases on TDA2PX, you can search in the e2e for those threads as reference. I have shared few threads https://e2e.ti.com/support/processors-group/processors/f/processors-forum/867915/tidl_od-usecase-on-tda2px?tisearch=e2e-sitesearch&keymatch=TDA2PX# https://e2e.ti.com/support/processors-group/processors/f/processors-forum/714606/linux-tda2pxevm-issue-in-running-vision-sdk-demo-application-on-tda2px?tisearch=e2e-sitesearch&keymatch=TDA2PX# Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Kirollos Henry",
+    "rankPoints" : "90",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6674902",
+    "content" : "Does That mean I Can't Run TIDL use cases on Vision SDK Linux or in other words I must use the \"MAKECONFIG?=tda2Px_evm_bios_all\" configration but I can't use the \"MAKECONFIG?=tda2xx_evm_linux_all\" configuration? Thanks, Kirollos Henry",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "You can but you have to set OPENVX_INCLUDE=y in ~/vision_sdk/apps/configs/tda2px_evm_linux_all/cfg.mk.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Kirollos Henry",
+    "rankPoints" : "90",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6674902",
+    "content" : "Thank you so much I was able to Solve that issue Best Regards, Kirollos Henry",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1006960.json

@@ -0,0 +1,115 @@
+{
+  "ticketNumber" : "1006960",
+  "reporterName" : "Pierre Hsieh",
+  "rankPoints" : "875",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SG: TDA2 LCD2 BT656 signal",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Hi Sir : TDA2 output BT.656 signal, when converted to BT.601 signal. Hsync will output all the time. If Vsync is low and Hsync is low, how do I set it?",
+  "imageList" : [ "Data/input/1006960/jpg" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Do you mean, you dont want hsync to be toggling when vsync is low? If this is the case, you could treat DE signal as inverted hsync. DE will toggle only during active video portion. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Pierre Hsieh",
+    "rankPoints" : "875",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6160032",
+    "content" : "Hi Brijesh : The hardware only has Hsync and Vsync and PCLK and ATA [7:0] pins, no DE output. The image had the output I wanted.",
+    "imageList" : [ "Data/input/1006960/Hsync.png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi Pierre Hsieh, hsync will toggle during vsync, this cannot be changed. In this case, you need to use DE line. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Pierre Hsieh",
+    "rankPoints" : "875",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6160032",
+    "content" : "Hi Brijesh : I cannot modify the BT656 configuration of TDA2 to output the desired signal?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi Pierre Hsieh, Hsync is supposed to toggle even during vsync inactive period.. This behavior cannot be changed. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Pierre Hsieh",
+    "rankPoints" : "875",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6160032",
+    "content" : "Hi Brijesh : BT.656 does not have a DE Line specification. How can I convert to BT.601 with DE Line?",
+    "imageList" : [ "Data/input/1006960/png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi Pierre Hsieh, BT656 does not even output hsync and vsync, so we cannot use hsync/vsync signals for BT656. We have to use discrete sync output mode in order to get sync signals. and when we enable discrete sync signals, we will also get DE signal. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Pierre Hsieh",
+    "rankPoints" : "875",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6160032",
+    "content" : "Hi Brijesh : This TDA2 hardware configuration, Display Subsystem DPI2 output BT.656, only output Data and PCLK signal lines. Analyze Bt.656, there will still be H Active in V Blanking. TDA2 can output on BT.656, the V Blanking signal is only H Blanking?",
+    "imageList" : [ "Data/input/1006960/png", "Data/input/1006960/Hsync_5F00_Blank.png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi Pierre Hsieh, When you say BT656, it is embedded sync output format, and in this format, DSS does not output sync signals, so there will not be any hsync or vsync signals in bt656 output. So can you check if you are configuring DSS for discrete sync output? Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Pierre Hsieh",
+    "rankPoints" : "875",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6160032",
+    "content" : "Hi Brijesh : BT.605 does not have Hsync and Vsync, so I converted it to BT601 using FPGA. I used FPGA to convert TDA2 output BT.656 signal into BT.601 signal. I found that VBlanking has a HActive signal for BT.601 signal.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi Pierre Hsieh, ok, in this case, you need to change FPGA. FPGA should out hsync correctly. This is not DSS question. Regards, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1008079.json

@@ -0,0 +1,79 @@
+{
+  "ticketNumber" : "1008079",
+  "reporterName" : "zhangsc sunchuan",
+  "rankPoints" : "340",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SG: How can output yuv422 format in the display",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SG Hi ,expert: My system has three overlay in the display,like this : 1,VID1: BGRA32_8888 2.VID2: YUV420SP 3.GFX: BGRA32_8888 general, TDA2s use the rgb888 output to display, and my system is work ok,Now I want to use the yuv422( YUYV) to the display, I see the \"dssm2mwb\" link ,I found this link may need \"sync\" link and then use buftype of \"SYSTEM_BUFFER_TYPE_VIDEO_FRAME_CONTAINER\". I have the question as follow: 1,sync need 3 overlay framerate is same,but my system is not satisfy and overlay has different display framesrate, so i think this solution may not very well . 2,Is There other solution to yuv422 display output thanks!",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, do you mean yuv422 over embedded sync output interface? Rgds, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "zhangsc sunchuan",
+    "rankPoints" : "340",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6356068",
+    "content" : "no, I mean if i use sync link ,if one of queue has no video ,sync will no send cmd to process ,so I think this solution is not suit. Now I want to checkout the problem: 1,VID1: BGRA32_8888 ->YUYV 2.VID2: YUV420SP 3.GFX: BGRA32_8888 ->YUYV overlay like this,the display can work? 2) Is there some usecase of yuv422 output I can refer",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "hi, #1, in this case, you would require to change sync link to support this feature. Currently it is not supported. sync link does not output if one of the input is not available. #2, do you mean to use 3 video pipelines, each with different data type? yes, display will work with this combination #3, where yuv422 do you require? Is it at the output of capture link or input to the display link? Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "zhangsc sunchuan",
+    "rankPoints" : "340",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6356068",
+    "content" : "output in the dispaly link , if i dont want to use \"sync\",I will do as follow: change RGBA328888 to YUYV format and it will make 3 video pipeline dataformat to 1,VID1: YUYV 2.VID2: YUV420SP 3.GFX: YUYV is the display link support \"YUYV\" and \"YUV420sp\" format output.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Yes, display link supports both of these formats. Rgds, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "zhangsc sunchuan",
+    "rankPoints" : "340",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6356068",
+    "content" : "I use capture_dsswb link ,and set vout format BT656 and DISPC_VP1_CONTROL.TDMENABLE = 0x1: TDM enabled DISPC_VP1_CONTROL. TDMPARALLELMODE = 0x0: 8-bit parallel output interface selected DISPC_VP1_CONTROL. TDMCYCLEFORMAT = 0x2: 2 cycles for 1 pixel DISPC_DATA1_CYCLE1 = 0x8 DISPC_DATA1_CYCLE2 = 0x8 DISPC_DATA1_CYCLE3 = 0x0 but my capture_dsswb has no video data,so I think writeback pipeline do not well work. how can I use writeback?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, these two things are different and independent. could you help me with what exactly you are trying to enable? - are the three input video pipelines enabled? - why are you enabling TDM for BT656 output? - why are you enabling dss wb path? Regards, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1011115.json

@@ -0,0 +1,34 @@
+{
+  "ticketNumber" : "1011115",
+  "reporterName" : "Victor Cheng1",
+  "rankPoints" : "390",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA4VM: TDA4 RTOS SDK network utilities",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi, In TDA4 RTOS SDK, do we have something similar as the TDA2.TDA3's network_rx, network_tx tools ? I saw that we have some ETHFW demo involving Plex media server but I just need a simple client/server example app that is able to save a file on PC over ethernet. regards, Victor",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Vineet Roy",
+    "rankPoints" : "37435",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/1643173",
+    "content" : "Hi Victor, No simple utility on RTOS of the kind you are looking for. Can you spell out your requirement : Do you want to stream a file from your EVM to your PC ? or do you want to use the CPSW 9G as a switch and connect multiple devices over it ? Regards Vineet",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Victor Cheng1",
+    "rankPoints" : "390",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6500211",
+    "content" : "Hi Vineet, I actually implemented the tool since it didn't exist on TDA4. The ticket can be closed. Thanks. regards, Victor",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1012640.json

@@ -0,0 +1,52 @@
+{
+  "ticketNumber" : "1012640",
+  "reporterName" : "Daniel Cheng1",
+  "rankPoints" : "4430",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: TDA2SXBU PMIC Selection",
+  "rankName" : "Genius",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Expert, Could TDA2SXBU PMIC Select TPS659039-O9039A387? If TDA2SXBU PMIC could not select TPS659039-O9039A387,do you have any suggestions? Thanks Daniel",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Vineet Roy",
+    "rankPoints" : "37435",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/1643173",
+    "content" : "Hi Daniel, Sorry for the delay. Is this issue still open ? Regards Vineet",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Daniel Cheng1",
+    "rankPoints" : "4430",
+    "rankName" : "Genius",
+    "date" : "",
+    "userId" : "/members/6328202",
+    "content" : "Hi Vineet Issue is still open. Could you help me? Thanks Daniel",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Vineet Roy",
+    "rankPoints" : "37435",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/1643173",
+    "content" : "Hi Daniel, Will take a look at this internally and get back. Regards Vineet",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "kcastille",
+    "rankPoints" : "46962",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/17783",
+    "content" : "Vineet, We recommend the PMIC that is implemented on the TDA2 EVM. Regards, Kyle",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1013160.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1013160",
+  "reporterName" : "gg yang",
+  "rankPoints" : "1005",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: Tda2s SPI slave mode reception problem",
+  "rankName" : "Expert",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hello, expert Tda2s is SPI slave mode. If the master sends a 1MHz clock and sends 140 bytes every 20ms, it will get stuck after receiving several times. If it sends 32 bytes every time, it will not get stuck. If it sends 32 bytes every 10ms, it will still receive several times of data and it will get stuck. dmesg1.txt   146 root      0:00 [kworker/0:1H]\r\n  148 root      0:00 cat /proc/kmsg\r\n  149 root      0:00 ps\r\nroot@dra7xx-evm:/app# \r\nroot@dra7xx-evm:/app# \r\nroot@dra7xx-evm:/app# \r\nroot@dra7xx-evm:/app# \r\nroot@dra7xx-evm:/app# ./spi_rev_tool_32 -D  /dev/spidev1.0  -s 1000000 -b 8\r\n[   36.808325] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0\r\n[   36.809212] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0\r\n[   36.810092] spidev spi1.0: setup mode 0, 8 bits/w, 1000000 Hz max --> 0\r\n<7>[   36.808304] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal\r\n<4>[   36.808325] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0\r\n<7>[   36.809182] spidev spi1.0: spi mode 0\r\n<7>[   36.809198] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal\r\n<4>[   36.809212] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0\r\n<7>[   36.810065] spidev spi1.0: 8 bits per word\r\n<7>[   36.810079] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal\r\n<4>[   36.810092] spidev spi1.0: setup mode 0, 8 bits/w, 1000000 Hz max --> 0\r\n<7>[   36.810946] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz\r\n<7>[   36.810973] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal\r\nRX | 4D 56 00 00 10 9A 00 00  | MV...?.\r\nRX | 01 01 00 00 00 00 00 00  | ........\r\nRX | 00 00 00 00 00 00 00 00  | ........\r\nRX | 00 00 00 00 00 00 00 00  | ........\r\nRX | 00 00 00 00 00 00 00 00  | ........\r\nRX | 00 00 00 00 00 00 00 00  | ........\r\nRX | 00 00 00 00 00 00 00 00  | ........\r\nRX | 00 00 00 00 00 00 00 00  | ........\r\n<7>[   36.826262] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal\r\n<7>[   36.826462] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz\r\n<7>[   36.826487] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal\r\n<7>[   36.827021] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal\r\n<7>[   36.827126] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz\r\n<7>[   36.827149] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal\r\n I add printing when I can't receive hand data, it's stuck in SPI_ transfer_ one_ message()---->master-transfer_ one(). How to find the problem? The problem of the master side has been ruled out, and the measurement SPI CLK CS is normal.",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, Our Linux SDK doesn't support SPI slave mode. It has not been validated on TDA2 EVM. Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1013431.json

@@ -0,0 +1,61 @@
+{
+  "ticketNumber" : "1013431",
+  "reporterName" : "Kirollos Henry",
+  "rankPoints" : "90",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: roscore run error on my TDA2Px-EVM due to python version",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Hi all, I am trying to run ROS on my TDA2Px-EVM so, I have done this clone: git clone git://arago-project.org/git/projects/oe-layersetup.git tisdk Then this configuration and build: ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-06.03.00.106-config.txt cd build . conf/setenv export TOOLCHAIN_PATH_ARMV7=$HOME/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf export TOOLCHAIN_PATH_ARMV8=$HOME/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu MACHINE=dra7xx-evm bitbake arago-base-tisdk-image This Arago project was running just fine. Then I went to the meta-ros layer and created that file in recipes-core/images: require recipes-core/images/arago-base-tisdk-image.bb export IMAGE_BASENAME = \"ros-base-image\" DESCRIPTION = \"An image with packagegroup-ros-world installed\" IMAGE_INSTALL = \"packagegroup-core-boot ${CORE_IMAGE_EXTRA_INSTALL}\" IMAGE_LINGUAS = \" \" LICENSE = \"MIT\" inherit core-image IMAGE_ROOTFS_SIZE = \"8192\" IMAGE_INSTALL += \"packagegroup-ros-world\" And named that file ros-base-image.bb Then I ran that build command: MACHINE=dra7xx-evm bitbake ros-base-image This build finished with no errors And I also was able to boot the board with no issues When the board Started I exported these variables: export ROS_ROOT=/opt/ros export ROS_DISTRO=indigo export ROS_PACKAGE_PATH=/opt/ros/indigo/share export PATH=$PATH:/opt/ros/indigo/bin export LD_LIBRARY_PATH=/opt/ros/indigo/lib export PYTHONPATH=/opt/ros/indigo/lib/python3.5/site-packages export ROS_MASTER_URI=http://localhost:11311 export CMAKE_PREFIX_PATH=/opt/ros/indigo touch /opt/ros/indigo/.catkin When I try to run roscore I got an error no module named xmlrpc as if it is trying to run for python2 and not python3 although the one installed is python3 I spent a couple of days trying to solve this but I am always having same error. And also I was not able to follow that guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf Because my machine is running on ubuntu 18 and this guide required ubuntu 14 host machine Thank you so much. Best regards, Kirollos Henry I have done this clone: git clone git://arago-project.org/git/projects/oe-layersetup.git tisdk Then this configuration and build: ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-06.03.00.106-config.txt cd build . conf/setenv export TOOLCHAIN_PATH_ARMV7=$HOME/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf export TOOLCHAIN_PATH_ARMV8=$HOME/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu MACHINE=dra7xx-evm bitbake arago-base-tisdk-image This Arago project was running just fine. Then I went to the meta-ros layer and created that file in recipes-core/images: require recipes-core/images/arago-base-tisdk-image.bb export IMAGE_BASENAME = \"ros-base-image\" DESCRIPTION = \"An image with packagegroup-ros-world installed\" IMAGE_INSTALL = \"packagegroup-core-boot ${CORE_IMAGE_EXTRA_INSTALL}\" IMAGE_LINGUAS = \" \" LICENSE = \"MIT\" inherit core-image IMAGE_ROOTFS_SIZE = \"8192\" IMAGE_INSTALL += \"packagegroup-ros-world\" And named that file ros-base-image.bb Then I ran that build command: MACHINE=dra7xx-evm bitbake ros-base-image This build finished with no errors And I also was able to boot the board with no issues When the board Started I exported these variables: export ROS_ROOT=/opt/ros export ROS_DISTRO=indigo export ROS_PACKAGE_PATH=/opt/ros/indigo/share export PATH=$PATH:/opt/ros/indigo/bin export LD_LIBRARY_PATH=/opt/ros/indigo/lib export PYTHONPATH=/opt/ros/indigo/lib/python3.5/site-packages export ROS_MASTER_URI=http://localhost:11311 export CMAKE_PREFIX_PATH=/opt/ros/indigo touch /opt/ros/indigo/.catkin When I try to run roscore I got an error no module named xmlrpc as if it is trying to run for python2 and not python3 although the one installed is python3 I spent a couple of days trying to solve this but I am always having same error. And also I was not able to follow that guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf Because my machine is running on ubuntu 18 and this guide required ubuntu 14 host machine Thank you so much. Best regards, Kirollos Henry I have done this clone: git clone git://arago-project.org/git/projects/oe-layersetup.git tisdk Then this configuration and build: ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-06.03.00.106-config.txt cd build . conf/setenv export TOOLCHAIN_PATH_ARMV7=$HOME/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf export TOOLCHAIN_PATH_ARMV8=$HOME/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu MACHINE=dra7xx-evm bitbake arago-base-tisdk-image This Arago project was running just fine. Then I went to the meta-ros layer and created that file in recipes-core/images: require recipes-core/images/arago-base-tisdk-image.bb export IMAGE_BASENAME = \"ros-base-image\" DESCRIPTION = \"An image with packagegroup-ros-world installed\" IMAGE_INSTALL = \"packagegroup-core-boot ${CORE_IMAGE_EXTRA_INSTALL}\" IMAGE_LINGUAS = \" \" LICENSE = \"MIT\" inherit core-image IMAGE_ROOTFS_SIZE = \"8192\" IMAGE_INSTALL += \"packagegroup-ros-world\" And named that file ros-base-image.bb Then I ran that build command: MACHINE=dra7xx-evm bitbake ros-base-image This build finished with no errors And I also was able to boot the board with no issues When the board Started I exported these variables: export ROS_ROOT=/opt/ros export ROS_DISTRO=indigo export ROS_PACKAGE_PATH=/opt/ros/indigo/share export PATH=$PATH:/opt/ros/indigo/bin export LD_LIBRARY_PATH=/opt/ros/indigo/lib export PYTHONPATH=/opt/ros/indigo/lib/python3.5/site-packages export ROS_MASTER_URI=http://localhost:11311 export CMAKE_PREFIX_PATH=/opt/ros/indigo touch /opt/ros/indigo/.catkin When I try to run roscore I got an error no module named xmlrpc as if it is trying to run for python2 and not python3 although the one installed is python3 I spent a couple of days trying to solve this but I am always having same error. And also I was not able to follow that guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf Because my machine is running on ubuntu 18 and this guide required ubuntu 14 host machine Thank you so much. Best regards, Kirollos Henry",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Keerthy J",
+    "rankPoints" : "132000",
+    "rankName" : "TI__Guru***",
+    "date" : "",
+    "userId" : "/members/1025801",
+    "content" : "Hi Kirollos, We will get back to you in couple of days. Thanks for your patience. Best Regards, Keerthy",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Karthik Ramanan",
+    "rankPoints" : "113800",
+    "rankName" : "TI__Guru**",
+    "date" : "",
+    "userId" : "/members/1166748",
+    "content" : "Kirollos, There are two main questions in your post. -1- Issue with running roscore with an updated image \"ros-base-image\" that you have created - the issue with xmlrpc. Unfortunately, this issue is very custom to your changes and you will have to debug this issue by yourself. Note that ROS integration is not a default on the SDK and we are quite unfamiliar with this error and will need more debug on the specific changes that you have done at your end. -2- And also I was not able to follow that guide: Sorry, what are you not able to follow in this guide? Yes, the SDK is dependent on Ubuntu 14.04 and it is recommended that you use the mentioned version to recreate the SDK successfully. Regards Karthik",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Kirollos Henry",
+    "rankPoints" : "90",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6674902",
+    "content" : "Hello Karthik, I want to know how much disk space is required to build yocto file system using this guide as I started building it by commenting the host check part in the script but I reached only 20% and took about 100GB of my disk space. I want to know how much disk space I have to free for this. Best regards, Kirollos Henry",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Karthik Ramanan",
+    "rankPoints" : "113800",
+    "rankName" : "TI__Guru**",
+    "date" : "",
+    "userId" : "/members/1166748",
+    "content" : "Hi Kirollos, 20% competion and 100GB of disk space doesn't sound quite right. But usually a single build needs about 150GB-200GB of disk space for the full build. Regards Karthik",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Kirollos Henry",
+    "rankPoints" : "90",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6674902",
+    "content" : "Hi Karthik, Thank you so much I was able to run roscore after some changes on the board using the steps I have previously done",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1013586.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1013586",
+  "reporterName" : "Kirollos Henry",
+  "rankPoints" : "90",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: Installing ROS on TDA2PXEVM after building Yocto filesystem",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Hello all, I have built Yocto filesystem on my TDA2Px using this guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf I want to know how can I add ROS layer and build Yocto again with ROS installed and have ROS running on my TDA2Px-EVM. Or in other word how can I customize a ROS layer or is there any guide for that? Thank you, Best Regards, Kirollos Henry",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Karthik Ramanan",
+    "rankPoints" : "113800",
+    "rankName" : "TI__Guru**",
+    "date" : "",
+    "userId" : "/members/1166748",
+    "content" : "Kirollos, It seems like you have made progress on the ROS image already: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1013431/tda2pxevm-roscore-run-error-on-my-tda2px-evm-due-to-python-version. There is no guide for integrating ROS with TDA2Px - most of our experiments with ROS were experimental and since both TI SDK and ROS were moving quite a bit we didn't snapshot a stable version and document the same. Lets continue discussion on the newer thread. Closing this one for now. Regards Karthik",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1014661.json

@@ -0,0 +1,34 @@
+{
+  "ticketNumber" : "1014661",
+  "reporterName" : "Daniel Cheng1",
+  "rankPoints" : "4430",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SA: Is there a Code Composer Studio(CCS) project existing to build the \"VISION SDK/project\" on OS (Linux/or windows) Platform ?",
+  "rankName" : "Genius",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SA Other Parts Discussed in Thread: TDA2 Hi Expert, My platform is TDA2 I want to confirm again. Is there a Code Composer Studio(CCS) project existing to build the \"VISION SDK/project\" on OS (Linux/or windows) Platform ? Thanks Daniel",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Daniel Cheng1",
+    "rankPoints" : "4430",
+    "rankName" : "Genius",
+    "date" : "",
+    "userId" : "/members/6328202",
+    "content" : "Hi Expert Is there any update? Thanks Daniel",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, No, we use commend line and makefile to build Vision SDK. CCS build takes longer time than command-line build/makefile build. Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1015551.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1015551",
+  "reporterName" : "Neal Zhu",
+  "rankPoints" : "2470",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: pressure test script / software",
+  "rankName" : "Expert",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi At present, we are preparing to do tda2sx ddr3l pressure test,Do you have tda2 ddr3l pressure test script / software? If there is no script, what should I do for stress testing?If we want to develop stress testing software, how to raise the corresponding software requirements? Please help me give some advice. Thank you!",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Kevin S",
+    "rankPoints" : "27155",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/1251368",
+    "content" : "Hi, There is nothing provided outside of what may exist in the SDKs. What operating system does your application use? Thanks, Kevin",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1015553.json

@@ -0,0 +1,115 @@
+{
+  "ticketNumber" : "1015553",
+  "reporterName" : "Mladen Knezic",
+  "rankPoints" : "180",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2P-ACD: Custom calibration tool for 2D SRV",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Hi all, I am trying to make a custom calibration tool for 2D surround view in Python with OpenCV that would match the existing one developed in Matlab. So far, I managed to implement the same workflow and to obtain the parameters of initial perspective metrices for 4 cameras with stitched bird view as shown in the image below. As can be seen, the bird view image is decent. However, when I provide the obtained perspective matrices (scaled to match Q11.20 format that I believe is used in GeometricAlignment and Sythesis algorithms), I get the result which is not even comparable to the one shown above, i.e., everything is distorted. This indicates that matrix parameters are wrong or incorrectly interpreted. To confirm that the perspective matrix coefficients are correct I used the same values in another framework (Octave) and I get nice bird view for each camera (I provide a view for front camera below). The question is what I am doing wrong and why I do not get (at least to some extent) correct bird view on the target? Best regards, Mladen",
+  "imageList" : [ "Data/input/1015553/jpg", "Data/input/1015553/bmp" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Mladen Knezic",
+    "rankPoints" : "180",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6015685",
+    "content" : "Just an additional note. I also tried to use perspective matrix generated by the tool for provided sample images in both Python and Octave. All I got is also distorted indicating that the TI tool does not provide the matrix coefficients expected by OpenCV warpPerspective() and Octave imperspectivewarp().",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Do-Kyoung Kwon",
+    "rankPoints" : "2860",
+    "rankName" : "TI__Intellectual",
+    "date" : "",
+    "userId" : "/members/758416",
+    "content" : "Did you compare bin files from your python with the bin files from TI tool?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Mladen Knezic",
+    "rankPoints" : "180",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6015685",
+    "content" : "Hi Do-Kyoung Kwon, I am not sure what bin files are you referring to. Currently, I am trying to get initial perspective matrices that would be comparable with the one obtained from TI tool. So far I found out that OpenCV and Octave functions returns forward mapped homographies, however, the SV algorithm is based on back-mapping. Therefore, I tried to use inverse matrices, but it seems that it does not work either. Now I suspect it has something with translating the image center to 0 instead of (width/2, height/2).",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Do-Kyoung Kwon",
+    "rankPoints" : "2860",
+    "rankName" : "TI__Intellectual",
+    "date" : "",
+    "userId" : "/members/758416",
+    "content" : "Oh.. I now realized that you are working on SRV on TDA2. I thought you are working on SRV on TDA4.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Mladen Knezic",
+    "rankPoints" : "180",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6015685",
+    "content" : "Right. It is 2D surround view running on C66.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Do-Kyoung Kwon",
+    "rankPoints" : "2860",
+    "rankName" : "TI__Intellectual",
+    "date" : "",
+    "userId" : "/members/758416",
+    "content" : "I think image center could be a reason. There might be no issue with perspective matrices give that you got the right reconstruction for the upper part of SRV. But it seems hard to say without debugging.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Mladen Knezic",
+    "rankPoints" : "180",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6015685",
+    "content" : "Actually, I got the right reconstruction on all 4 views as you can see in the first image (this is an output from Python tool). The issue arises when I provide the obtained matrices to the usecase (GeometricAlignment link) or to the Surroundview.exe tool for further perspective matrices tuning. It seems that those initial matrices are not in the form expected by the current implementation. I will also check for the image centers, but anyway, thank you for your time.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Do-Kyoung Kwon",
+    "rankPoints" : "2860",
+    "rankName" : "TI__Intellectual",
+    "date" : "",
+    "userId" : "/members/758416",
+    "content" : "Great to hear that you resolve the issue.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Mladen Knezic",
+    "rankPoints" : "180",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6015685",
+    "content" : "No, the issue is still unresolved. I am chasing the way to adjust the perspective matrices to match the required format.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Mladen Knezic",
+    "rankPoints" : "180",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6015685",
+    "content" : "I figured this out. Image centers are just one side of the coin. Input images relative to output view orientation should be considered as well. Obviously, a rule for feature points (corners selected in reference image and input images) correspondence I used in my custom tool is different from the one in the TI tool, so I had to add some rotations to the input images (and output results) to match them. It is very specific to my case, but it would be informative if you could share somewhere in the documentation how the corners selected in the tool on reference image corresponds to the corners selected on the input images for each camera view.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Do-Kyoung Kwon",
+    "rankPoints" : "2860",
+    "rankName" : "TI__Intellectual",
+    "date" : "",
+    "userId" : "/members/758416",
+    "content" : "Great! Thanks for the suggestion, too!",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1015697.json

@@ -0,0 +1,151 @@
+{
+  "ticketNumber" : "1015697",
+  "reporterName" : "David ks",
+  "rankPoints" : "560",
+  "resolutionStatus" : "",
+  "ticketName" : "How to burn the sd card file to emmc Tda2ex-17 (SDK V03.08)",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Other Parts Discussed in Thread: TDA2, SYSBIOS Dear all, I'm just a beginner As shown in the title! Currently only use sd card to boot I’m not sure about the creation process and other settings like uenv-emmc.txt May I ask which document is talking about how to burn the emmc part? I don’t know the first thing to know and what to do at the beginning Although there are many related issues But is there a detailed document for reference? The part about burning into emmc! Can anyone give me some suggestions on the above issues ===================================================================== And how to enter terminal like => root@dra7xx-evm:~# Beacuse I put sd card into board and starting My log starts directly here ------------------------------------------------ TDA2Ex SBL Boot DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed TI EVM PAD Config Completed DDR Config Completed App Image Download Begins SD Boot - file open completed successfully MPU CPU0 Image Load Completed IPU1 CPU0 Image Load Completed IPU1 CPU1 Image Load Completed IPU2 CPU0 and CPU1 Image Load Completed .....................etc -------------------------------------------------------------- I’m not sure how to get in root@dra7xx-evm:~# Which paragraph may I have missed The above are some of my questions. Please help me . VERY THANKS!!",
+  "imageList" : [ "Data/input/1015697/GIF" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear all, Please tell me if there is something unclear Thanks!",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear all, By the way , when I was in Bulid The different settings are MAKECONFIG=tda2xx_evm_linux_all => MAKECONFIG=tda2ex_evm_bios_all",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear all, Is it because we are a custom board? Because some related settings are not done and directly with your EV setting to run, so there is no way to run to => root@dra7xx-evm:~# Is it? What can I do about those related settings? Are there other documents or suggestions?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear all, 【Supplement】 And my VisionSDK_Linux_UserGuide.pdf did 4 .3 steps But the log does not show anything Next However I did VisionSDK_UserGuide_TDA2Ex.pdf\nSome later steps gmake -s sbl and gmake -s appimage\nGenerate MLO and appimage to overwrite the original MLO (without apimage) Have Log ------------------------------------------------ TDA2Ex SBL Boot DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed etc.... --------------------------------------------- But VisionSDK_Linux_UserGuide.pdf did 4 .3 steps Why is there no system log?? Is there a problem? Because we are a custom board, what should I pay attention to and set?  ",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "If you set MAKECONFIG=tda2ex_evm_bios_all and build \"gmake -s sbl\", the MLO is for the baremetal bootloader for TI-RTOS (SYSBIOS). For Linux, you should set MAKECONFIG=tda2xx_evm_linux_all. However, sbl build is only for RTOS, not Linux. To build the bootloader (spl/u-boot) for Linux, you have to build from linux u-boot on Ubuntu PC. VisionSDK_Linux_UserGuide.pdf has all the steps documented. You have to follow the steps from the beginning to set up Linux build environment. Regards, Stanley",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Stanley, Step1 !!! I did the steps above in the document (VisionSDK_Linux_UserGuide.pdf) And my MAKECONFIG is tda2ex_evm_linux_all I have done step 4.2,Then burn it into the SD card When I put it in our coustom board, \"\"\" there is no log \"\"\" =================================================================== Step2 !!! Then I did another thing I will overwrite the MLO and put in appimage built by the window => tda2ex_evm_bios_all  (These two files are completed under the window ) But there is a log out Like this ------------------------------------------------ TDA2Ex SBL Boot DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed etc.... --------------------------------------------- ============================================================================== The key problem is!! when I was in step 1!!! Why did I complete 4.2 and put the sd card into our costom board and there is no log display???? Why did I do the second experiment but it works like this(Step2 !!!) ? Is there something wrong?? I have followed VisionSDK_Linux_UserGuide.pdf, but the 4.3 step is still unsuccessful Thanks!!!!!",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "One possibility is that Linux u-boot SPL (MLO) got stuck since you were booting the MLO for EVM on the custom board. Do you have JTAG to connect the device and check what is going on with debugger? You can use Lauterbach JTAG with Trace32 or XDS560v2 JTAG with CCS to debug. Regards, Stanley",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear, Q1. So it may be the relationship of the custom board? Because it doesn’t match with MLO?? =============================================================== Q2.in addition ,If Q1 is right I want to ask, is it because some need to be set according to our board? Is there any direction to tell me what needs to be modified? ============================================================= I will learn about the debug method and try it out Please tell me these two answers Thanks!!",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Q1: Yes Q2: You have to identify what is different between your board and EVM. For example, if DDR is different, you have to update EMIF configuration or the access to DDR may not work. There are other things like Pin mux, PMIC, and etic. Regards, Stanley",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Thank you!!",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Stanley, I want to check some places Please help me with these problems ================================================================ Q1 : Would like to ask how to determine if MLO has been executed? Q2: Where is the TDA uart port set? I also suspect that the port may be wrong, so I want to check Q3: Where is the MLO log printed? And where is the MLO source code ?? And where it started to run?? Q4: Where is the ROM code??, I want to know how the process of booting to MLO to display log is Q5: Is there any clear information about the boot process (part of the program)? ================================================================= If there is something wrong with the question I asked, please let me know Thank you !",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Stanley, But the DDR of my RTOS is the same as LINUX DDR RTOS can see log but LINUX does not Just changed MLO, any other suggestions? Thanks!",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Stanley, Can you help me this issue? Thanks!",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "David ks",
+    "rankPoints" : "560",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6496878",
+    "content" : "Dear Stanley, But the DDR of my RTOS is the same as LINUX DDR RTOS can see log but LINUX does not Just changed MLO, have any other suggestions? and I I opened another thread e2e.ti.com/.../3799935 Thanks!",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Could you download the pre-built binaries from the below link? http://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/latest/index_FDS.html boot-dra7xx-evm.tar.gz will include the MLO and u-boot. Can you try this on your board first?",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1015916.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1015916",
+  "reporterName" : "Joe Hsien",
+  "rankPoints" : "220",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA4 capture output YUV420 format",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Other Parts Discussed in Thread: TDA2 We use TDA4 and connect YUV422 camera. TDA2 can set capture input format YUV422 and capture output format YUV420. Can TDA4 set capture input format YUV422 and capture output format YUV420 ?",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, No, VIP module in TDA2x can convert YUV422 to YUV420, but CSIRX cannot convert YUV422 to YUV420. You will require to use some other module like LDC or DSS for this conversion. Regards, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1016368.json

@@ -0,0 +1,79 @@
+{
+  "ticketNumber" : "1016368",
+  "reporterName" : "chen poca",
+  "rankPoints" : "30",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2HF: About import tool sampleInData",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2HF Hello， I have two questions about import configuration parameters: (1).does sampleInData support video input or multiple images ? (2).if sampleInData support,how to set and how to prepare the video and images? and other question about caffe-jacinto quantize test: I test the imagenet_jacintonet11v2_iter_160000.caffemodel and set quantize: true in deploy.prototxt, save the output of pool5, and then remove quantize: true only,save the output of pool5 again, the results are same.\"quantize: true\" doesn't seem to work.So if quantize: true does work,What happens to the output? Thanks, chen poca",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi Chen poca, 1. You can set \"numSampleInData\" variable in the import config file and set \"numFrames\" variable in the infer config file for running multiple images. 2. You can concatenate multiple images to prepare the multiple image input The test results with and without quantize are available here in \"caffe_jacinto_models\\trained\\image_classification\\imagenet_jacintonet11v2\" folder in the github (https://github.com/tidsp/caffe-jacinto-models), please refer to \"run.log\" in \"test_quantize\" and \"test\" folders. Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "chen poca",
+    "rankPoints" : "30",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6407428",
+    "content" : "hello, thank you for your replying. my reason to setting numSampleInData variable >1 is for import process not for inference.if numSampleInData>1,can I set sampleInData to multiple images?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Yes",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "chen poca",
+    "rankPoints" : "30",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6407428",
+    "content" : "so how to set multiple image to the sample InData ？using the txt file to list image path？or concatenate multiple images to one .y file？",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Concatenate multiple images to one .y file",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "chen poca",
+    "rankPoints" : "30",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6407428",
+    "content" : "Sorry for the late reply and thank you for your answer.I have another question,if using multiple images to the sampleInData,would this improve the effect and generalization ability of the quantization?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "No",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1016451.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1016451",
+  "reporterName" : "Kirollos Henry",
+  "rankPoints" : "90",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: Connect TDAPx-EVM to the internet",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello all, I have TDAPx-EVM board and I was able to build Yocto file system and boot the board using the built yocto file system. I want to connect it to the internet, after connecting it to an Ethernet cable there is still no internet connection, so I want to know is anything I have to configure or what should I do to have and internet connection on my TDAPx-EVM Thank You, Best regards, Kirollos Henry",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, Could you share the log from boot to linux kernel and the log from \"ifconfig\"? Did you change Linux kernel default config used by TDA2 SDK? Ethernet should be enabled already from the default config. Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1019218.json

@@ -0,0 +1,160 @@
+{
+  "ticketNumber" : "1019218",
+  "reporterName" : "Arseniy Yakovlev",
+  "rankPoints" : "350",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: 8 cameras FPS question",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello. I have a usecase with 8 cameras. Image from 4 of them handled by EVE1 and EVE2 algolinks. Image: EVE1 and EVE1 each have an algolink which is [do EVELIB_memcopyDMA2D, do some logic (attachment text file) , do EVELIB_memcopyDMA2D again]. We have FPS around 23-24 with this program, but the EVE1/EVE2 load is 3.5-4.5% according to printStatistics function. It stays same even if i \"disable\" the algolink completely by removing anything from it. The question is - why FPS is low and do we have any ways to improve it? logic.txt void filter ( __vptr_uint8  iptr   //input block\r\n                    , __vptr_uint8  optr       //output block\r\n                    , unsigned int width       //block width\r\n                    ) {\r\n\r\n __vector Vin1;\r\n __vector Vin2;\r\n __vector Vout1;\r\n __vector Vout2;\r\n __vector Vec1;\r\n __agen Ag;\r\n Ag = 0;\r\n Vec1               = -1;\r\n\r\n for (int I1 = 0; I1 < width/VCOP_SIMD_WIDTH/2; I1++) {\r\n  __agen Ag1;\r\n   Ag1                = I1*VCOP_SIMD_WIDTH*2;\r\n   (Vin1,Vin2)        = (iptr)[Ag1].deinterleave();\r\n   Vout1              = Vin1 << Vec1;\r\n   Vout2              = Vin2 << Vec1;\r\n   (optr)[Ag1].interleave()        = (Vout1,Vout2);\r\n }",
+  "imageList" : [ "Data/input/1019218/jpg" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, It looks like you are using vision sdk. so can you press 'p' on the console and share the complete console log? It will help us to understand which link is slowing down entire chain. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Arseniy Yakovlev",
+    "rankPoints" : "350",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/4940400",
+    "content" : "Hello. According to statistics the most latency-heavy links are ISSM2MISP, ALG_ISS_AEWB and DISPLAY. How can i optimize them? I guess i can try to use AEWB2 instead of AEWB, i hear that it is better for 4+ cameras systems. What about other links? Full statics in attached file. Thanks for quick response. 8371.stats.txt [IPU1-0]    183.640120 s:\r\n[IPU1-0]    183.640212 s:  CPU [IPU1-0 ] Statistics,\r\n[IPU1-0]    183.640273 s:  *************************\r\n[IPU1-0]    183.640334 s:\r\n[IPU1-0]    183.640456 s:  LOAD: CPU: 40.3% HWI: 5.8%, SWI:1.4%, Low Power: 24.3%\r\n[IPU1-0]    183.640761 s:\r\n[IPU1-0]    183.640822 s:  LOAD: TSK: SYSTEM              : 1.8%\r\n[IPU1-0]    183.640913 s:  LOAD: TSK: IPC_IN_0            : 0.3%\r\n[IPU1-0]    183.641005 s:  LOAD: TSK: IPC_IN_1            : 0.4%\r\n[IPU1-0]    183.641127 s:  LOAD: TSK: IPC_OUT_0           : 0.6%\r\n[IPU1-0]    183.641218 s:  LOAD: TSK: IPC_OUT_1           : 0.6%\r\n[IPU1-0]    183.641462 s:  LOAD: TSK: MERGE0              : 0.6%\r\n[IPU1-0]    183.641584 s:  LOAD: TSK: SELECT0             : 0.8%\r\n[IPU1-0]    183.641676 s:  LOAD: TSK: SELECT1             : 0.2%\r\n[IPU1-0]    183.641767 s:  LOAD: TSK: DISPLAY0            : 0.3%\r\n[IPU1-0]    183.641889 s:  LOAD: TSK: ISSCAPTURE          : 1.8%\r\n[IPU1-0]    183.648020 s:  LOAD: TSK: ISSM2MISP           : 8.7%\r\n[IPU1-0]    183.648173 s:  LOAD: TSK: ALGORITHM0          : 9.1%\r\n[IPU1-0]    183.648264 s:  LOAD: TSK: STAT_COLL           : 3.8%\r\n[IPU1-0]    183.648356 s:  LOAD: TSK: MISC                : 4.1%\r\n[IPU1-0]    183.648630 s:\r\n[IPU1-0]    183.648691 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023\r\n[IPU1-0]    183.648783 s:\r\n[IPU1-0]    183.648813 s:  SYSTEM: Sempahores Objects,    6 of 1050 free\r\n[IPU1-0]    183.648905 s:  SYSTEM: Task Objects      ,    3 of  100 free\r\n[IPU1-0]    183.651131 s:  SYSTEM: Clock Objects     ,   93 of  100 free\r\n[IPU1-0]    183.651253 s:  SYSTEM: Hwi Objects       ,   87 of  100 free\r\n[IPU1-0]    183.653754 s:\r\n[IPU1-0]    183.653815 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 152352 B (148 KB)\r\n[IPU1-0]    183.655035 s:  SYSTEM: Heap = SR_OCMC              @ 0x00000000, Total size = 0 B (0 KB), Free size = 0 B (0 KB)\r\n[IPU1-0]    183.655218 s:  SYSTEM: Heap = SR_DDR_CACHED        @ 0x88503000, Total size = 905957376 B (863 MB), Free size = 795453440 B (758 MB)\r\n[IPU1-0]    183.655493 s:  SYSTEM: Heap = SR_DDR_NON_CACHED    @ 0xbf000000, Total size = 129152 B (0 MB), Free size = 117632 B (0 MB)\r\n[IPU1-0]    183.655676 s:\r\n[IPU1-0]    183.655706 s:\r\n[IPU1-0]    183.655737 s:  CPU [IPU1-1 ] Statistics,\r\n[IPU1-0]    183.655798 s:  *************************\r\n[IPU1-0]    183.655859 s:\r\n[IPU1-0]    183.655920 s:  LOAD: CPU: 47.7% HWI: 1.1%, SWI:1.1%, Low Power: 26.4%\r\n[IPU1-0]    183.656072 s:\r\n[IPU1-0]    183.656194 s:  LOAD: TSK: MISC                : 45.5%\r\n[IPU1-0]    183.656255 s:\r\n[IPU1-0]    183.656316 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1016\r\n[IPU1-0]    183.656469 s:\r\n[IPU1-0]    183.656530 s:  SYSTEM: Sempahores Objects,  432 of 1050 free\r\n[IPU1-0]    183.656621 s:  SYSTEM: Task Objects      ,   38 of  100 free\r\n[IPU1-0]    183.656713 s:  SYSTEM: Clock Objects     ,   99 of  100 free\r\n[IPU1-0]    183.656804 s:  SYSTEM: Hwi Objects       ,   98 of  100 free\r\n[IPU1-0]    183.656896 s:\r\n[IPU1-0]    183.656926 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 655360 B (640 KB), Free size = 646744 B (631 KB)\r\n[IPU1-0]    183.657079 s:\r\n[IPU1-0]    183.657140 s:\r\n[IPU1-0]    183.657170 s:  CPU [DSP1   ] Statistics,\r\n[IPU1-0]    183.657231 s:  *************************\r\n[IPU1-0]    183.657292 s:\r\n[IPU1-0]    183.657323 s:  LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%, Low Power: 87.6%\r\n[IPU1-0]    183.657536 s:\r\n[IPU1-0]    183.657628 s:  LOAD: TSK: MISC                : 0.2%\r\n[IPU1-0]    183.657689 s:\r\n[IPU1-0]    183.657750 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1016\r\n[IPU1-0]    183.657841 s:\r\n[IPU1-0]    183.657872 s:  SYSTEM: Sempahores Objects,  456 of 1050 free\r\n[IPU1-0]    183.657963 s:  SYSTEM: Task Objects      ,   92 of  100 free\r\n[IPU1-0]    183.658055 s:  SYSTEM: Clock Objects     ,   99 of  100 free\r\n[IPU1-0]    183.658146 s:  SYSTEM: Hwi Objects       ,  100 of  100 free\r\n[IPU1-0]    183.658238 s:\r\n[IPU1-0]    183.658268 s:  SYSTEM: Heap = LOCAL_L2             @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)\r\n[IPU1-0]    183.658726 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 524288 B (512 KB), Free size = 518328 B (506 KB)\r\n[IPU1-0]    183.659549 s:\r\n[IPU1-0]    183.659641 s:\r\n[IPU1-0]    183.659671 s:  CPU [DSP2   ] Statistics,\r\n[IPU1-0]    183.659732 s:  *************************\r\n[IPU1-0]    183.659793 s:\r\n[IPU1-0]    183.659824 s:  LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%, Low Power: 87.7%\r\n[IPU1-0]    183.659976 s:\r\n[IPU1-0]    183.660037 s:  LOAD: TSK: MISC                : 0.2%\r\n[IPU1-0]    183.660129 s:\r\n[IPU1-0]    183.660159 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1016\r\n[IPU1-0]    183.660251 s:\r\n[IPU1-0]    183.660281 s:  SYSTEM: Sempahores Objects,  456 of 1050 free\r\n[IPU1-0]    183.660434 s:  SYSTEM: Task Objects      ,   92 of  100 free\r\n[IPU1-0]    183.660556 s:  SYSTEM: Clock Objects     ,   99 of  100 free\r\n[IPU1-0]    183.660647 s:  SYSTEM: Hwi Objects       ,  100 of  100 free\r\n[IPU1-0]    183.660739 s:\r\n[IPU1-0]    183.660769 s:  SYSTEM: Heap = LOCAL_L2             @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)\r\n[IPU1-0]    183.660922 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 524288 B (512 KB), Free size = 518328 B (506 KB)\r\n[IPU1-0]    183.661105 s:\r\n[IPU1-0]    183.661135 s:\r\n[IPU1-0]    183.661166 s:  CPU [EVE1   ] Statistics,\r\n[IPU1-0]    183.661227 s:  *************************\r\n[IPU1-0]    183.661288 s:\r\n[IPU1-0]    183.661349 s:  LOAD: CPU: 3.2% HWI: 0.7%, SWI:0.1%, Low Power: 76.5%\r\n[IPU1-0]    183.661562 s:\r\n[IPU1-0]    183.661623 s:  LOAD: TSK: SYSTEM_TSK_MULTI_MBX: 2.1%\r\n[IPU1-0]    183.661745 s:  LOAD: TSK: MISC                : 0.3%\r\n[IPU1-0]    183.661806 s:\r\n[IPU1-0]    183.661867 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1016\r\n[IPU1-0]    183.661959 s:\r\n[IPU1-0]    183.661989 s:  SYSTEM: Sempahores Objects,  456 of 1050 free\r\n[IPU1-0]    183.662081 s:  SYSTEM: Task Objects      ,   93 of  100 free\r\n[IPU1-0]    183.662172 s:  SYSTEM: Clock Objects     ,   97 of  100 free\r\n[IPU1-0]    183.662264 s:  SYSTEM: Hwi Objects       ,   99 of  100 free\r\n[IPU1-0]    183.662355 s:\r\n[IPU1-0]    183.662447 s:  SYSTEM: Heap = LOCAL_L2             @ 0x40020000, Total size = 22528 B (22 KB), Free size = 22528 B (22 KB)\r\n[IPU1-0]    183.662630 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 255472 B (249 KB)\r\n[IPU1-0]    183.662782 s:\r\n[IPU1-0]    183.662813 s:\r\n[IPU1-0]    183.662874 s:  CPU [EVE2   ] Statistics,\r\n[IPU1-0]    183.662935 s:  *************************\r\n[IPU1-0]    183.662996 s:\r\n[IPU1-0]    183.663026 s:  LOAD: CPU: 3.7% HWI: 0.9%, SWI:0.1%, Low Power: 89.1%\r\n[IPU1-0]    183.663179 s:\r\n[IPU1-0]    183.663209 s:  LOAD: TSK: SYSTEM_TSK_MULTI_MBX: 2.4%\r\n[IPU1-0]    183.664155 s:  LOAD: TSK: MISC                : 0.3%\r\n[IPU1-0]    183.664277 s:\r\n[IPU1-0]    183.664307 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1016\r\n[IPU1-0]    183.664521 s:\r\n[IPU1-0]    183.664551 s:  SYSTEM: Sempahores Objects,  456 of 1050 free\r\n[IPU1-0]    183.664643 s:  SYSTEM: Task Objects      ,   93 of  100 free\r\n[IPU1-0]    183.664734 s:  SYSTEM: Clock Objects     ,   97 of  100 free\r\n[IPU1-0]    183.664826 s:  SYSTEM: Hwi Objects       ,   99 of  100 free\r\n[IPU1-0]    183.664917 s:\r\n[IPU1-0]    183.664948 s:  SYSTEM: Heap = LOCAL_L2             @ 0x40020000, Total size = 22528 B (22 KB), Free size = 22528 B (22 KB)\r\n[IPU1-0]    183.665131 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 255472 B (249 KB)\r\n[IPU1-0]    183.665283 s:\r\n[IPU1-0]    183.665680 s:\r\n[IPU1-0]    183.665741 s:  UTILS_PRCM_STATS:  Current Temperature,\r\n[IPU1-0]    183.665802 s:\r\n[IPU1-0]    183.665832 s:   Voltage Rail         ||   Curr Temp Min - Max\r\n[IPU1-0]    183.665985 s:  ---------------------------------------------------------\r\n[IPU1-0]    183.666107 s:      PMHAL_PRCM_VD_MPU ||     [36.400 , 36.800]\r\n[IPU1-0]    183.666198 s:     PMHAL_PRCM_VD_CORE ||     [37.200 , 37.600]\r\n[IPU1-0]    183.666320 s:    PMHAL_PRCM_VD_IVAHD ||     [37.200 , 37.600]\r\n[IPU1-0]    183.666534 s:   PMHAL_PRCM_VD_DSPEVE ||     [35.600 , 36.  0]\r\n[IPU1-0]    183.666656 s:      PMHAL_PRCM_VD_GPU ||     [36.400 , 36.800]\r\n[IPU1-0]    183.666778 s:\r\n[IPU1-0]    183.666809 s: ============================================================================\r\n[IPU1-0]    183.666931 s: Name      | Bus (mV)  | Res (mOhm) | Shunt (uV)  | Current (mA) | Power (mW)\r\n[IPU1-0]    183.667022 s: ----------------------------------------------------------------------------\r\n[IPU1-0]    183.669462 s:  UTILS_PRCM_STATS: Reading the regulator data failed\r\n[IPU1-0]    183.669554 s:  UTILS_PRCM_STATS: PM INA226 Power Read Failed !!\r\n[IPU1-0]    183.669828 s:\r\n[IPU1-0]    183.669859 s:  Statistics Collector,\r\n[IPU1-0]    183.669920 s:\r\n[IPU1-0]    183.669981 s:        STATISTIC          Avg Data        Peak Data\r\n[IPU1-0]    183.670042 s:        COLLECTOR          MB/s            MB/s\r\n[IPU1-0]    183.670133 s:  --------------------------------------------------\r\n[IPU1-0]    183.670225 s:  SCI_EMIF1 RD+WR      |     23.392640     94.215952\r\n[IPU1-0]    183.670316 s:  SCI_EMIF2 RD+WR      |     12.879614     84.437461\r\n[IPU1-0]    183.670530 s:  SCI_EMIF1 RD ONLY    |     14.171932     52.574551\r\n[IPU1-0]    183.670652 s:  SCI_EMIF1 WR ONLY    |      9.223919     42.197945\r\n[IPU1-0]    183.670774 s:  SCI_EMIF2 RD ONLY    |      8.592815     46.805568\r\n[IPU1-0]    183.670865 s:  SCI_EMIF2 WR ONLY    |      4.299391     37.632008\r\n[IPU1-0]    183.670987 s:  SCI_MA_MPU_P1        |      0.000000      0.000000\r\n[IPU1-0]    183.671079 s:  SCI_MA_MPU_P2        |      0.000000      0.000000\r\n[IPU1-0]    183.671201 s:  SCI_DSS              |      0.000000      0.000000\r\n[IPU1-0]    183.671292 s:  SCI_IPU1             |      9.584755     14.295081\r\n[IPU1-0]    183.671475 s:  SCI_VIP1_P1          |      0.000000      0.000000\r\n[IPU1-0]    183.671597 s:  SCI_VIP1_P2          |      0.000000      0.000000\r\n[IPU1-0]    183.671689 s:  SCI_VPE_P1           |      0.000000      0.000000\r\n[IPU1-0]    183.671780 s:  SCI_VPE_P2           |      0.000000      0.000000\r\n[IPU1-0]    183.671902 s:  SCI_DSP1_MDMA        |      0.048405      0.473948\r\n[IPU1-0]    183.671994 s:  SCI_DSP1_EDMA        |      0.000000      0.000000\r\n[IPU1-0]    183.672817 s:  SCI_DSP2_MDMA        |      0.048405      0.473853\r\n[IPU1-0]    183.672970 s:  SCI_DSP2_EDMA        |      0.000000      0.000000\r\n[IPU1-0]    183.673061 s:  SCI_EVE1_TC0         |      2.013945      5.283185\r\n[IPU1-0]    183.673183 s:  SCI_EVE1_TC1         |      0.000000      0.000000\r\n[IPU1-0]    183.673275 s:  SCI_EVE2_TC0         |      2.013703      5.329868\r\n[IPU1-0]    183.673702 s:  SCI_EVE2_TC1         |      0.000000      0.000000\r\n[IPU1-0]    183.673824 s:  SCI_EDMA_TC0_RD      |      0.000000      0.000000\r\n[IPU1-0]    183.673915 s:  SCI_EDMA_TC0_WR      |      0.000000      0.000000\r\n[IPU1-0]    183.674037 s:  SCI_EDMA_TC1_RD      |      0.000000      0.000000\r\n[IPU1-0]    183.674129 s:  SCI_EDMA_TC1_WR      |      0.000000      0.000000\r\n[IPU1-0]    183.674220 s:  SCI_VIP2_P1          |      0.000000      0.000000\r\n[IPU1-0]    183.674342 s:  SCI_VIP2_P2          |      0.000000      0.000000\r\n[IPU1-0]    183.674495 s:  SCI_IVA              |      0.000000      0.000000\r\n[IPU1-0]    183.674617 s:  SCI_GPU_P1           |      0.000000      0.000000\r\n[IPU1-0]    183.674739 s:  SCI_GPU_P2           |      0.000000      0.000000\r\n[IPU1-0]    183.674830 s:  SCI_GMAC_SW          |      0.000000      0.000000\r\n[IPU1-0]    183.674922 s:  SCI_OCMC_RAM1        |      0.000000      0.000000\r\n[IPU1-0]    183.675044 s:  SCI_OCMC_RAM2        |      0.000000      0.000000\r\n[IPU1-0]    183.675135 s:  SCI_OCMC_RAM3        |      0.000000      0.000000\r\n[IPU1-0]    183.675227 s:  SCI_ISS_RT           |      0.000000      0.000000\r\n[IPU1-0]    183.675349 s:  SCI_ISS_NRT1         |      0.000000      0.000000\r\n[IPU1-0]    183.675532 s:  SCI_ISS_NRT2         |      0.000000      0.000000\r\n[IPU1-0]    183.675623 s:  SCI_CAL              |      0.000000      0.000000\r\n[IPU1-0]    183.775452 s:\r\n[IPU1-0]    183.775544 s:\r\n[IPU1-0]    183.775635 s:\r\n[IPU1-0]    183.775696 s:  ### CPU [IPU1-0], LinkID [ 87],\r\n[IPU1-0]    183.775757 s:\r\n[IPU1-0]    183.775818 s:  [ ISSCAPTURE ] Link Statistics,\r\n[IPU1-0]    183.775879 s:  ******************************\r\n[IPU1-0]    183.775940 s:\r\n[IPU1-0]    183.775971 s:  Elapsed time       = 3026 msec\r\n[IPU1-0]    183.776062 s:\r\n[IPU1-0]    183.776093 s:  Get Full Buf Cb    = 192.0 fps\r\n[IPU1-0]    183.776184 s:  Put Empty Buf Cb   =  92.53 fps\r\n[IPU1-0]    183.776245 s:  Driver/Notify Cb   = 240.25 fps\r\n[IPU1-0]    183.776337 s:\r\n[IPU1-0]    183.776367 s:  Input Statistics,\r\n[IPU1-0]    183.776489 s:\r\n[IPU1-0]    183.776550 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    183.776611 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    183.776703 s:  --------------------------------------------------\r\n[IPU1-0]    183.776794 s:   0 |  25.77      0. 0      0. 0          25.77\r\n[IPU1-0]    183.776916 s:   1 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    183.777069 s:   2 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    183.777191 s:   3 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    183.777343 s:   4 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    183.777526 s:   5 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    183.777679 s:   6 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    183.777832 s:   7 |  23.13      0. 0      0. 0          23.13\r\n[IPU1-0]    183.777954 s:\r\n[IPU1-0]    183.777984 s:  Output Statistics,\r\n[IPU1-0]    183.778045 s:\r\n[IPU1-0]    183.778076 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    183.778167 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    183.779174 s:  ---------------------------------------------\r\n[IPU1-0]    183.779296 s:   0 |  0     26.10     0. 0      0. 0\r\n[IPU1-0]    183.779479 s:   1 |  0     23.79     0. 0      0. 0\r\n[IPU1-0]    183.779631 s:   2 |  0     23.79     0. 0      0. 0\r\n[IPU1-0]    183.779753 s:   3 |  0     23.79     0. 0      0. 0\r\n[IPU1-0]    183.779875 s:   4 |  0     23.79     0. 0      0. 0\r\n[IPU1-0]    183.779997 s:   5 |  0     23.79     0. 0      0. 0\r\n[IPU1-0]    183.780119 s:   6 |  0     23.79     0. 0      0. 0\r\n[IPU1-0]    183.780241 s:   7 |  0     23.13     0. 0      0. 0\r\n[IPU1-0]    183.780333 s:\r\n[IPU1-0]    183.780455 s:  [ ISSCAPTURE ] LATENCY,\r\n[IPU1-0]    183.780516 s:  ********************\r\n[IPU1-0]    183.780577 s:\r\n[IPU1-0]    183.780638 s:  CPU [  IPU1-0], LinkID [ 43], Link Statistics not available !\r\n[IPU1-0]    183.780790 s:\r\n[IPU1-0]    183.780851 s:  ### CPU [IPU1-0], LinkID [  1],\r\n[IPU1-0]    183.780912 s:\r\n[IPU1-0]    183.780973 s:  [ IPC_OUT_1 ] Link Statistics,\r\n[IPU1-0]    183.781034 s:  ******************************\r\n[IPU1-0]    183.781095 s:\r\n[IPU1-0]    183.781126 s:  Elapsed time       = 3027 msec\r\n[IPU1-0]    183.781187 s:\r\n[IPU1-0]    183.781248 s:  New data Recv      =  46.91 fps\r\n[IPU1-0]    183.781309 s:  Release data Recv  =  33.36 fps\r\n[IPU1-0]    183.781461 s:  Driver/Notify Cb   =  66.73 fps\r\n[IPU1-0]    183.781553 s:\r\n[IPU1-0]    183.781583 s:  Input Statistics,\r\n[IPU1-0]    183.781644 s:\r\n[IPU1-0]    183.781675 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    183.781766 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    183.781858 s:  --------------------------------------------------\r\n[IPU1-0]    183.781919 s:   0 |  23.78      0. 0      0. 0          23.78\r\n[IPU1-0]    183.782071 s:   1 |  23.12      0. 0      0. 0          23.12\r\n[IPU1-0]    183.782193 s:\r\n[IPU1-0]    183.782254 s:  Output Statistics,\r\n[IPU1-0]    183.784542 s:\r\n[IPU1-0]    183.784633 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    183.785121 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    183.785213 s:  ---------------------------------------------\r\n[IPU1-0]    183.786128 s:   0 |  0     23.78     0. 0      0. 0\r\n[IPU1-0]    183.786280 s:   1 |  0     23.12     0. 0      0. 0\r\n[IPU1-0]    183.787073 s:\r\n[IPU1-0]    183.787134 s:  [ IPC_OUT_1 ] LATENCY,\r\n[IPU1-0]    183.787195 s:  ********************\r\n[IPU1-0]    183.788781 s:  Local Link Latency     : Avg =      7 us, Min =      0 us, Max =     91 us,\r\n[IPU1-0]    183.788934 s:  Source to Link Latency : Avg =    148 us, Min =     91 us, Max =    396 us,\r\n[IPU1-0]    183.789056 s:\r\n[IPU1-0]    184.289971 s:\r\n[IPU1-0]    184.290032 s:  ### CPU [  EVE2], LinkID [ 10],\r\n[IPU1-0]    184.290123 s:\r\n[IPU1-0]    184.290154 s:  [ IPC_IN_0 ] Link Statistics,\r\n[IPU1-0]    184.290245 s:  ******************************\r\n[IPU1-0]    184.290306 s:\r\n[IPU1-0]    184.290337 s:  Elapsed time       = 3537 msec\r\n[IPU1-0]    184.290489 s:\r\n[IPU1-0]    184.290550 s:  Get Full Buf Cb    =  41.56 fps\r\n[IPU1-0]    184.290611 s:  Put Empty Buf Cb   =  46.93 fps\r\n[IPU1-0]    184.290703 s:  Driver/Notify Cb   =  50.32 fps\r\n[IPU1-0]    184.290764 s:\r\n[IPU1-0]    184.290794 s:  Input Statistics,\r\n[IPU1-0]    184.290855 s:\r\n[IPU1-0]    184.290916 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    184.290977 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    184.291069 s:  --------------------------------------------------\r\n[IPU1-0]    184.291160 s:   0 |  23.74      0. 0      0. 0          23.74\r\n[IPU1-0]    184.291282 s:   1 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    184.291496 s:\r\n[IPU1-0]    184.291526 s:  Output Statistics,\r\n[IPU1-0]    184.291587 s:\r\n[IPU1-0]    184.291648 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    184.291709 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    184.291770 s:  ---------------------------------------------\r\n[IPU1-0]    184.291862 s:   0 |  0     23.74     0. 0      0. 0\r\n[IPU1-0]    184.291984 s:   1 |  0     23.46     0. 0      0. 0\r\n[IPU1-0]    184.292106 s:\r\n[IPU1-0]    184.292136 s:  [ IPC_IN_0 ] LATENCY,\r\n[IPU1-0]    184.292197 s:  ********************\r\n[IPU1-0]    184.292258 s:  Local Link Latency     : Avg =     25 us, Min =      0 us, Max =    153 us,\r\n[IPU1-0]    184.292380 s:  Source to Link Latency : Avg =    455 us, Min =    305 us, Max =    732 us,\r\n[IPU1-0]    184.292563 s:\r\n[IPU1-0]    184.292685 s:\r\n[IPU1-0]    184.292716 s:  ### CPU [  EVE2], LinkID [ 49],\r\n[IPU1-0]    184.292807 s:\r\n[IPU1-0]    184.292838 s:  [ ALG_BAYERINPLACE ] Link Statistics,\r\n[IPU1-0]    184.292929 s:  ******************************\r\n[IPU1-0]    184.292990 s:\r\n[IPU1-0]    184.293021 s:  Elapsed time       = 3539 msec\r\n[IPU1-0]    184.293082 s:\r\n[IPU1-0]    184.293143 s:  New data Recv      =  41.25 fps\r\n[IPU1-0]    184.293204 s:\r\n[IPU1-0]    184.293265 s:  Input Statistics,\r\n[IPU1-0]    184.293295 s:\r\n[IPU1-0]    184.293356 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    184.294241 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    184.294363 s:  --------------------------------------------------\r\n[IPU1-0]    184.294668 s:   0 |  23.73      0. 0      0. 0          23.73\r\n[IPU1-0]    184.294973 s:   1 |  23.45      0. 0      0. 0          23.45\r\n[IPU1-0]    184.295125 s:\r\n[IPU1-0]    184.295156 s:  Output Statistics,\r\n[IPU1-0]    184.295217 s:\r\n[IPU1-0]    184.295247 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    184.295339 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    184.295583 s:  ---------------------------------------------\r\n[IPU1-0]    184.295674 s:   0 |  0     23.73     0. 0      0. 0\r\n[IPU1-0]    184.295796 s:   1 |  0     23.45     0. 0      0. 0\r\n[IPU1-0]    184.295918 s:\r\n[IPU1-0]    184.295949 s:  [ ALG_BAYERINPLACE ] LATENCY,\r\n[IPU1-0]    184.296010 s:  ********************\r\n[IPU1-0]    184.305008 s:  Local Link Latency     : Avg =     19 us, Min =      0 us, Max =    122 us,\r\n[IPU1-0]    184.305160 s:  Source to Link Latency : Avg =    642 us, Min =    488 us, Max =    945 us,\r\n[IPU1-0]    184.305282 s:\r\n[IPU1-0]    184.305587 s:\r\n[IPU1-0]    184.305648 s:  ### CPU [  EVE2], LinkID [  0],\r\n[IPU1-0]    184.305709 s:\r\n[IPU1-0]    184.305770 s:  [ IPC_OUT_0 ] Link Statistics,\r\n[IPU1-0]    184.305831 s:  ******************************\r\n[IPU1-0]    184.305892 s:\r\n[IPU1-0]    184.305923 s:  Elapsed time       = 3551 msec\r\n[IPU1-0]    184.306014 s:\r\n[IPU1-0]    184.306045 s:  New data Recv      =  41.39 fps\r\n[IPU1-0]    184.306228 s:  Release data Recv  =  34.7 fps\r\n[IPU1-0]    184.306319 s:  Driver/Notify Cb   =  37.45 fps\r\n[IPU1-0]    184.306380 s:\r\n[IPU1-0]    184.306502 s:  Input Statistics,\r\n[IPU1-0]    184.306563 s:\r\n[IPU1-0]    184.306624 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    184.306685 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    184.313975 s:  --------------------------------------------------\r\n[IPU1-0]    184.314097 s:   0 |  23.65      0. 0      0. 0          23.65\r\n[IPU1-0]    184.314219 s:   1 |  23.37      0. 0      0. 0          23.37\r\n[IPU1-0]    184.314341 s:\r\n[IPU1-0]    184.314737 s:  Output Statistics,\r\n[IPU1-0]    184.314829 s:\r\n[IPU1-0]    184.314860 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    184.314921 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    184.315012 s:  ---------------------------------------------\r\n[IPU1-0]    184.315104 s:   0 |  0     23.65     0. 0      0. 0\r\n[IPU1-0]    184.315317 s:   1 |  0     23.37     0. 0      0. 0\r\n[IPU1-0]    184.315531 s:\r\n[IPU1-0]    184.315592 s:  [ IPC_OUT_0 ] LATENCY,\r\n[IPU1-0]    184.317879 s:  ********************\r\n[IPU1-0]    184.317971 s:  Local Link Latency     : Avg =     20 us, Min =      0 us, Max =    122 us,\r\n[IPU1-0]    184.318611 s:  Source to Link Latency : Avg =    848 us, Min =    671 us, Max =   1220 us,\r\n[IPU1-0]    184.319160 s:\r\n[IPU1-0]    184.822180 s:\r\n[IPU1-0]    184.822241 s:  ### CPU [IPU1-0], LinkID [ 10],\r\n[IPU1-0]    184.822332 s:\r\n[IPU1-0]    184.822363 s:  [ IPC_IN_0 ] Link Statistics,\r\n[IPU1-0]    184.822515 s:  ******************************\r\n[IPU1-0]    184.822607 s:\r\n[IPU1-0]    184.822637 s:  Elapsed time       = 4068 msec\r\n[IPU1-0]    184.822698 s:\r\n[IPU1-0]    184.822759 s:  Get Full Buf Cb    = 183.38 fps\r\n[IPU1-0]    184.822820 s:  Put Empty Buf Cb   =  46.95 fps\r\n[IPU1-0]    184.822912 s:  Driver/Notify Cb   =  74.48 fps\r\n[IPU1-0]    184.822973 s:\r\n[IPU1-0]    184.823034 s:  Input Statistics,\r\n[IPU1-0]    184.823064 s:\r\n[IPU1-0]    184.823125 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    184.823186 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    184.823278 s:  --------------------------------------------------\r\n[IPU1-0]    184.823369 s:   0 |  23.84      0. 0      0. 0          23.84\r\n[IPU1-0]    184.823552 s:   1 |  23.59      0. 0      0. 0          23.59\r\n[IPU1-0]    184.823705 s:\r\n[IPU1-0]    184.823735 s:  Output Statistics,\r\n[IPU1-0]    184.823796 s:\r\n[IPU1-0]    184.823827 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    184.823918 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    184.823979 s:  ---------------------------------------------\r\n[IPU1-0]    184.824071 s:   0 |  0     23.84     0. 0      0. 0\r\n[IPU1-0]    184.824193 s:   1 |  0     23.59     0. 0      0. 0\r\n[IPU1-0]    184.824284 s:\r\n[IPU1-0]    184.824345 s:  [ IPC_IN_0 ] LATENCY,\r\n[IPU1-0]    184.824406 s:  ********************\r\n[IPU1-0]    184.824528 s:  Local Link Latency     : Avg =     19 us, Min =      0 us, Max =     92 us,\r\n[IPU1-0]    184.824650 s:  Source to Link Latency : Avg =   1117 us, Min =    854 us, Max =   1708 us,\r\n[IPU1-0]    184.824772 s:\r\n[IPU1-0]    184.824864 s:\r\n[IPU1-0]    184.824925 s:  ### CPU [IPU1-0], LinkID [  0],\r\n[IPU1-0]    184.824986 s:\r\n[IPU1-0]    184.825047 s:  [ IPC_OUT_0 ] Link Statistics,\r\n[IPU1-0]    184.825108 s:  ******************************\r\n[IPU1-0]    184.825169 s:\r\n[IPU1-0]    184.825199 s:  Elapsed time       = 4073 msec\r\n[IPU1-0]    184.825260 s:\r\n[IPU1-0]    184.825321 s:  New data Recv      =  47.63 fps\r\n[IPU1-0]    184.826023 s:  Release data Recv  =  24.30 fps\r\n[IPU1-0]    184.826145 s:  Driver/Notify Cb   =  57.45 fps\r\n[IPU1-0]    184.826236 s:\r\n[IPU1-0]    184.826267 s:  Input Statistics,\r\n[IPU1-0]    184.826328 s:\r\n[IPU1-0]    184.826358 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    184.826755 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    184.826846 s:  --------------------------------------------------\r\n[IPU1-0]    184.826938 s:   0 |  23.81      0. 0      0. 0          23.81\r\n[IPU1-0]    184.827090 s:   1 |  23.81      0. 0      0. 0          23.81\r\n[IPU1-0]    184.827212 s:\r\n[IPU1-0]    184.827243 s:  Output Statistics,\r\n[IPU1-0]    184.827304 s:\r\n[IPU1-0]    184.827334 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    184.827487 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    184.827578 s:  ---------------------------------------------\r\n[IPU1-0]    184.827670 s:   0 |  0     23.81     0. 0      0. 0\r\n[IPU1-0]    184.827792 s:   1 |  0     23.81     0. 0      0. 0\r\n[IPU1-0]    184.827914 s:\r\n[IPU1-0]    184.827944 s:  [ IPC_OUT_0 ] LATENCY,\r\n[IPU1-0]    184.828005 s:  ********************\r\n[IPU1-0]    184.828066 s:  Local Link Latency     : Avg =      8 us, Min =      0 us, Max =    122 us,\r\n[IPU1-0]    184.828188 s:  Source to Link Latency : Avg =    150 us, Min =     91 us, Max =    458 us,\r\n[IPU1-0]    184.828310 s:\r\n[IPU1-0]    185.327578 s:\r\n[IPU1-0]    185.327731 s:  ### CPU [  EVE1], LinkID [ 10],\r\n[IPU1-0]    185.327822 s:\r\n[IPU1-0]    185.327853 s:  [ IPC_IN_0 ] Link Statistics,\r\n[IPU1-0]    185.327914 s:  ******************************\r\n[IPU1-0]    185.327975 s:\r\n[IPU1-0]    185.328036 s:  Elapsed time       = 4576 msec\r\n[IPU1-0]    185.328097 s:\r\n[IPU1-0]    185.328127 s:  Get Full Buf Cb    =  45.89 fps\r\n[IPU1-0]    185.328219 s:  Put Empty Buf Cb   =  47.20 fps\r\n[IPU1-0]    185.328310 s:  Driver/Notify Cb   =  50.26 fps\r\n[IPU1-0]    185.328371 s:\r\n[IPU1-0]    185.328402 s:  Input Statistics,\r\n[IPU1-0]    185.328524 s:\r\n[IPU1-0]    185.328585 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    185.328676 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    185.328737 s:  --------------------------------------------------\r\n[IPU1-0]    185.328829 s:   0 |  23.60      0. 0      0. 0          23.60\r\n[IPU1-0]    185.328951 s:   1 |  23.60      0. 0      0. 0          23.60\r\n[IPU1-0]    185.329103 s:\r\n[IPU1-0]    185.329134 s:  Output Statistics,\r\n[IPU1-0]    185.329195 s:\r\n[IPU1-0]    185.329225 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    185.329317 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    185.329378 s:  ---------------------------------------------\r\n[IPU1-0]    185.329713 s:   0 |  0     23.60     0. 0      0. 0\r\n[IPU1-0]    185.329835 s:   1 |  0     23.60     0. 0      0. 0\r\n[IPU1-0]    185.329957 s:\r\n[IPU1-0]    185.330018 s:  [ IPC_IN_0 ] LATENCY,\r\n[IPU1-0]    185.330079 s:  ********************\r\n[IPU1-0]    185.330110 s:  Local Link Latency     : Avg =     23 us, Min =      0 us, Max =     31 us,\r\n[IPU1-0]    185.330232 s:  Source to Link Latency : Avg =    454 us, Min =    275 us, Max =    732 us,\r\n[IPU1-0]    185.330354 s:\r\n[IPU1-0]    185.330537 s:\r\n[IPU1-0]    185.330598 s:  ### CPU [  EVE1], LinkID [ 49],\r\n[IPU1-0]    185.330689 s:\r\n[IPU1-0]    185.330720 s:  [ ALG_BAYERINPLACE ] Link Statistics,\r\n[IPU1-0]    185.330781 s:  ******************************\r\n[IPU1-0]    185.330842 s:\r\n[IPU1-0]    185.331665 s:  Elapsed time       = 4578 msec\r\n[IPU1-0]    185.331757 s:\r\n[IPU1-0]    185.331787 s:  New data Recv      =  45.65 fps\r\n[IPU1-0]    185.331879 s:\r\n[IPU1-0]    185.331909 s:  Input Statistics,\r\n[IPU1-0]    185.331970 s:\r\n[IPU1-0]    185.332001 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    185.332092 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    185.332306 s:  --------------------------------------------------\r\n[IPU1-0]    185.332397 s:   0 |  23.59      0. 0      0. 0          23.59\r\n[IPU1-0]    185.332611 s:   1 |  23.59      0. 0      0. 0          23.59\r\n[IPU1-0]    185.332763 s:\r\n[IPU1-0]    185.332885 s:  Output Statistics,\r\n[IPU1-0]    185.332946 s:\r\n[IPU1-0]    185.333007 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    185.333068 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    185.333160 s:  ---------------------------------------------\r\n[IPU1-0]    185.333221 s:   0 |  0     23.59     0. 0      0. 0\r\n[IPU1-0]    185.333343 s:   1 |  0     23.59     0. 0      0. 0\r\n[IPU1-0]    185.341517 s:\r\n[IPU1-0]    185.341578 s:  [ ALG_BAYERINPLACE ] LATENCY,\r\n[IPU1-0]    185.341639 s:  ********************\r\n[IPU1-0]    185.341700 s:  Local Link Latency     : Avg =     17 us, Min =      0 us, Max =    122 us,\r\n[IPU1-0]    185.341822 s:  Source to Link Latency : Avg =    609 us, Min =    518 us, Max =    946 us,\r\n[IPU1-0]    185.342066 s:\r\n[IPU1-0]    185.342188 s:\r\n[IPU1-0]    185.342249 s:  ### CPU [  EVE1], LinkID [  0],\r\n[IPU1-0]    185.342310 s:\r\n[IPU1-0]    185.342371 s:  [ IPC_OUT_0 ] Link Statistics,\r\n[IPU1-0]    185.342493 s:  ******************************\r\n[IPU1-0]    185.342676 s:\r\n[IPU1-0]    185.342737 s:  Elapsed time       = 4590 msec\r\n[IPU1-0]    185.342798 s:\r\n[IPU1-0]    185.342829 s:  New data Recv      =  45.75 fps\r\n[IPU1-0]    185.342920 s:  Release data Recv  =  24.61 fps\r\n[IPU1-0]    185.342981 s:  Driver/Notify Cb   =  27.88 fps\r\n[IPU1-0]    185.343073 s:\r\n[IPU1-0]    185.343103 s:  Input Statistics,\r\n[IPU1-0]    185.343164 s:\r\n[IPU1-0]    185.357896 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    185.358018 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    185.358110 s:  --------------------------------------------------\r\n[IPU1-0]    185.358171 s:   0 |  23.52      0. 0      0. 0          23.52\r\n[IPU1-0]    185.358323 s:   1 |  23.52      0. 0      0. 0          23.52\r\n[IPU1-0]    185.359116 s:\r\n[IPU1-0]    185.359177 s:  Output Statistics,\r\n[IPU1-0]    185.359238 s:\r\n[IPU1-0]    185.359269 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    185.359360 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    185.359513 s:  ---------------------------------------------\r\n[IPU1-0]    185.359604 s:   0 |  0     23.52     0. 0      0. 0\r\n[IPU1-0]    185.359726 s:   1 |  0     23.52     0. 0      0. 0\r\n[IPU1-0]    185.359848 s:\r\n[IPU1-0]    185.359909 s:  [ IPC_OUT_0 ] LATENCY,\r\n[IPU1-0]    185.359970 s:  ********************\r\n[IPU1-0]    185.360031 s:  Local Link Latency     : Avg =     20 us, Min =      0 us, Max =    122 us,\r\n[IPU1-0]    185.360123 s:  Source to Link Latency : Avg =    797 us, Min =    671 us, Max =   1220 us,\r\n[IPU1-0]    185.360245 s:\r\n[IPU1-0]    185.859574 s:\r\n[IPU1-0]    185.859665 s:  ### CPU [IPU1-0], LinkID [ 11],\r\n[IPU1-0]    185.859757 s:\r\n[IPU1-0]    185.859787 s:  [ IPC_IN_1 ] Link Statistics,\r\n[IPU1-0]    185.859848 s:  ******************************\r\n[IPU1-0]    185.859909 s:\r\n[IPU1-0]    185.859970 s:  Elapsed time       = 5107 msec\r\n[IPU1-0]    185.860031 s:\r\n[IPU1-0]    185.860062 s:  Get Full Buf Cb    = 183.27 fps\r\n[IPU1-0]    185.860153 s:  Put Empty Buf Cb   =  46.99 fps\r\n[IPU1-0]    185.860214 s:  Driver/Notify Cb   =  79.30 fps\r\n[IPU1-0]    185.860306 s:\r\n[IPU1-0]    185.860336 s:  Input Statistics,\r\n[IPU1-0]    185.860397 s:\r\n[IPU1-0]    185.860428 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    185.860641 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    185.860733 s:  --------------------------------------------------\r\n[IPU1-0]    185.860824 s:   0 |  23.69      0. 0      0. 0          23.69\r\n[IPU1-0]    185.860946 s:   1 |  23.69      0. 0      0. 0          23.69\r\n[IPU1-0]    185.861099 s:\r\n[IPU1-0]    185.861129 s:  Output Statistics,\r\n[IPU1-0]    185.861190 s:\r\n[IPU1-0]    185.861221 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    185.861282 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    185.861373 s:  ---------------------------------------------\r\n[IPU1-0]    185.861678 s:   0 |  0     23.69     0. 0      0. 0\r\n[IPU1-0]    185.861831 s:   1 |  0     23.69     0. 0      0. 0\r\n[IPU1-0]    185.861953 s:\r\n[IPU1-0]    185.861983 s:  [ IPC_IN_1 ] LATENCY,\r\n[IPU1-0]    185.862044 s:  ********************\r\n[IPU1-0]    185.862105 s:  Local Link Latency     : Avg =     24 us, Min =      0 us, Max =    122 us,\r\n[IPU1-0]    185.862227 s:  Source to Link Latency : Avg =   1105 us, Min =    854 us, Max =   1617 us,\r\n[IPU1-0]    185.862349 s:\r\n[IPU1-0]    185.862410 s:  CPU [  IPU1-0], LinkID [ 38], Link Statistics not available !\r\n[IPU1-0]    185.863203 s:\r\n[IPU1-0]    185.863264 s:  ### CPU [IPU1-0], LinkID [ 88],\r\n[IPU1-0]    185.863356 s:\r\n[IPU1-0]    185.863386 s:  [ ISSM2MISP ] Link Statistics,\r\n[IPU1-0]    185.863569 s:  ******************************\r\n[IPU1-0]    185.863630 s:\r\n[IPU1-0]    185.863661 s:  Elapsed time       = 5114 msec\r\n[IPU1-0]    185.863752 s:\r\n[IPU1-0]    185.863783 s:  New data Recv      = 179.89 fps\r\n[IPU1-0]    185.863874 s:  Get Full Buf Cb    =  61.0 fps\r\n[IPU1-0]    185.863935 s:  Driver/Notify Cb   = 189.47 fps\r\n[IPU1-0]    185.864027 s:\r\n[IPU1-0]    185.864057 s:  Input Statistics,\r\n[IPU1-0]    185.864118 s:\r\n[IPU1-0]    185.864149 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    185.864240 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    185.864301 s:  --------------------------------------------------\r\n[IPU1-0]    185.864393 s:   0 |  25.22      0. 0      0. 0          25.22\r\n[IPU1-0]    185.864576 s:   1 |  23.66      0. 0      0. 0          23.66\r\n[IPU1-0]    185.864728 s:   2 |  23.66      0. 0      0. 0          23.46\r\n[IPU1-0]    185.864881 s:   3 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    185.865003 s:   4 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    185.865155 s:   5 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    185.865277 s:   6 |  23.46      0. 0      0. 0          23.46\r\n[IPU1-0]    185.865399 s:   7 |  23.26      0. 0      0. 0          23.26\r\n[IPU1-0]    185.865613 s:\r\n[IPU1-0]    185.865643 s:  Output Statistics,\r\n[IPU1-0]    185.865704 s:\r\n[IPU1-0]    185.865735 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    185.865826 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    185.865887 s:  ---------------------------------------------\r\n[IPU1-0]    185.865979 s:   0 |  0     25.22     0. 0      0. 0\r\n[IPU1-0]    185.866101 s:   0 |  1     13.10    12.12      0. 0\r\n[IPU1-0]    185.866223 s:   0 |  2      0. 0    25.22      0. 0\r\n[IPU1-0]    185.866345 s:   0 |  3      0. 0    25.22      0. 0\r\n[IPU1-0]    185.866711 s:   1 |  0     23.66     0. 0      0. 0\r\n[IPU1-0]    185.866833 s:   1 |  1     12.90    10.75      0. 0\r\n[IPU1-0]    185.867778 s:   1 |  2      0. 0    23.66      0. 0\r\n[IPU1-0]    185.867931 s:   1 |  3      0. 0    23.66      0. 0\r\n[IPU1-0]    185.868053 s:   2 |  0     23.46     0. 0      0. 0\r\n[IPU1-0]    185.868175 s:   2 |  1     12.51    10.95      0. 0\r\n[IPU1-0]    185.868297 s:   2 |  2      0. 0    23.46      0. 0\r\n[IPU1-0]    185.868419 s:   2 |  3      0. 0    23.46      0. 0\r\n[IPU1-0]    185.868632 s:   3 |  0     23.46     0. 0      0. 0\r\n[IPU1-0]    185.868754 s:   3 |  1     12.31    11.14      0. 0\r\n[IPU1-0]    185.868876 s:   3 |  2      0. 0    23.46      0. 0\r\n[IPU1-0]    185.868998 s:   3 |  3      0. 0    23.46      0. 0\r\n[IPU1-0]    185.869120 s:   4 |  0     23.46     0. 0      0. 0\r\n[IPU1-0]    185.869242 s:   4 |  1     12.12    11.34      0. 0\r\n[IPU1-0]    185.869364 s:   4 |  2      0. 0    23.46      0. 0\r\n[IPU1-0]    185.869547 s:   4 |  3      0. 0    23.46      0. 0\r\n[IPU1-0]    185.869669 s:   5 |  0     23.46     0. 0      0. 0\r\n[IPU1-0]    185.869791 s:   5 |  1     11.92    11.53      0. 0\r\n[IPU1-0]    185.869913 s:   5 |  2      0. 0    23.46      0. 0\r\n[IPU1-0]    185.870035 s:   5 |  3      0. 0    23.46      0. 0\r\n[IPU1-0]    185.870157 s:   6 |  0     23.46     0. 0      0. 0\r\n[IPU1-0]    185.870279 s:   6 |  1     11.53    11.92      0. 0\r\n[IPU1-0]    185.870402 s:   6 |  2      0. 0    23.46      0. 0\r\n[IPU1-0]    185.870585 s:   6 |  3      0. 0    23.46      0. 0\r\n[IPU1-0]    185.870707 s:   7 |  0     23.26     0. 0      0. 0\r\n[IPU1-0]    185.870829 s:   7 |  1     11.34    11.92      0. 0\r\n[IPU1-0]    185.870951 s:   7 |  2      0. 0    23.26      0. 0\r\n[IPU1-0]    185.871073 s:   7 |  3      0. 0    23.26      0. 0\r\n[IPU1-0]    185.871195 s:\r\n[IPU1-0]    185.871225 s:  [ ISSM2MISP ] LATENCY,\r\n[IPU1-0]    185.871286 s:  ********************\r\n[IPU1-0]    185.871347 s:  Local Link Latency     : Avg =   4449 us, Min =   4270 us, Max =   6436 us,\r\n[IPU1-0]    185.872293 s:  Source to Link Latency : Avg =  19367 us, Min =   4575 us, Max =  39438 us,\r\n[IPU1-0]    185.872445 s:\r\n[IPU1-0]    185.872659 s:\r\n[IPU1-0]    185.872689 s:  ### CPU [IPU1-0], LinkID [ 49],\r\n[IPU1-0]    185.872781 s:\r\n[IPU1-0]    185.872811 s:  [ ALG_ISS_AEWB ] Link Statistics,\r\n[IPU1-0]    185.872903 s:  ******************************\r\n[IPU1-0]    185.872964 s:\r\n[IPU1-0]    185.872994 s:  Elapsed time       = 5116 msec\r\n[IPU1-0]    185.873086 s:\r\n[IPU1-0]    185.873116 s:  New data Recv      =   7.3 fps\r\n[IPU1-0]    185.873177 s:\r\n[IPU1-0]    185.873238 s:  Input Statistics,\r\n[IPU1-0]    185.873269 s:\r\n[IPU1-0]    185.873330 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    185.873391 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    185.873543 s:  --------------------------------------------------\r\n[IPU1-0]    185.873635 s:   0 |  12.50      0. 0      0. 0          12.50\r\n[IPU1-0]    185.873787 s:\r\n[IPU1-0]    185.873818 s:  Output Statistics,\r\n[IPU1-0]    185.873879 s:\r\n[IPU1-0]    185.873909 s:  CH | Out | Out     | Out Drop | Out User Drop\r\n[IPU1-0]    185.874001 s:     | ID  | FPS     | FPS      | FPS\r\n[IPU1-0]    185.874062 s:  ---------------------------------------------\r\n[IPU1-0]    185.874153 s:   0 |  0     12.50     0. 0      0. 0\r\n[IPU1-0]    185.874275 s:\r\n[IPU1-0]    185.874306 s:  [ ALG_ISS_AEWB ] LATENCY,\r\n[IPU1-0]    185.874367 s:  ********************\r\n[IPU1-0]    185.874428 s:  Local Link Latency     : Avg =  10299 us, Min =     61 us, Max = 152199 us,\r\n[IPU1-0]    185.874611 s:  Source to Link Latency : Avg = 210994 us, Min =  19551 us, Max = 590099 us,\r\n[IPU1-0]    185.874733 s:\r\n[IPU1-0]    185.874794 s:  CPU [  IPU1-0], LinkID [ 44], Link Statistics not available !\r\n[IPU1-0]    185.874977 s:\r\n[IPU1-0]    185.875007 s:  ### CPU [IPU1-0], LinkID [ 77],\r\n[IPU1-0]    185.875099 s:\r\n[IPU1-0]    185.875129 s:  [ DISPLAY ] Link Statistics,\r\n[IPU1-0]    185.875190 s:  ******************************\r\n[IPU1-0]    185.875251 s:\r\n[IPU1-0]    185.875282 s:  Elapsed time       = 5082 msec\r\n[IPU1-0]    185.875373 s:\r\n[IPU1-0]    185.875404 s:  New data Recv      =  23.41 fps\r\n[IPU1-0]    185.875556 s:  Driver/Notify Cb   =  60.1 fps\r\n[IPU1-0]    185.875648 s:\r\n[IPU1-0]    185.875678 s:  Input Statistics,\r\n[IPU1-0]    185.875739 s:\r\n[IPU1-0]    185.875770 s:  CH | In Recv | In Drop | In User Drop | In Process\r\n[IPU1-0]    185.875861 s:     | FPS     | FPS     | FPS          | FPS\r\n[IPU1-0]    185.876746 s:  --------------------------------------------------\r\n[IPU1-0]    185.876868 s:   0 |  23.61      0. 0      0. 0          23.61\r\n[IPU1-0]    185.877020 s:\r\n[IPU1-0]    185.877051 s:  [ DISPLAY ] LATENCY,\r\n[IPU1-0]    185.877112 s:  ********************\r\n[IPU1-0]    185.877173 s:  Local Link Latency     : Avg =     46 us, Min =     30 us, Max =    427 us,\r\n[IPU1-0]    185.877295 s:  Source to Link Latency : Avg =  31501 us, Min =   7015 us, Max =  43463 us,\r\n[IPU1-0]    185.877417 s:\r\n[IPU1-0]    185.877539 s:  Display UnderFlow Count = 0\r\n[IPU1-0]    185.877600 s:\r\n[IPU1-0]    186.377508 s:",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, What's the resolution you are using? What is the opp you are using? Yes, ISP could be the main culprit. It is taking around 4.5m to process a frame. 8 camera would take around 36ms, so cannot process 8CH @30fps. [IPU1-0] 185.871347 s: Local Link Latency : Avg = 4449 us, Min = 4270 us, Max = 6436 us, Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Arseniy Yakovlev",
+    "rankPoints" : "350",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/4940400",
+    "content" : "Resolution is 1280x960. Sensor is IMX224. So, its not possible to have 30fps x 8 cams? Even with AEWB2? Can you expand the \"opp\"?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, It is not about AEWB2. AEWB is SW algorithm. Even if it is running slower, ISP should be able to process. But somehow it takes 4.5ms to process frame. This is slightly higher. Depending on the device you are using, you might be able to increase isp frequency and that should allow your to run 8Channel of 1280x960 resolution. Please refer to TRM for more details. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Arseniy Yakovlev",
+    "rankPoints" : "350",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/4940400",
+    "content" : "Thanks for info. We use tda2pxevm. My collegue said that we already have it at OPP_PLUS mode. Which is high ISP frequency i think. I have one more question related to this task. Sometimes we get < Utils_mbxSendCmd(): Msg Alloc Falied (0) > error with this UC (and some other tda2 UCes with 8cam system). Can it be caused by slow frame processing?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Yes, it is caused due to slow processing. Message Box are in limited numbers, so if link is running slowed, it would just pile up the queues and could run out. I am not sure if opp_plus has higher isp frequency, could you please check in datasheet/TRM? Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Arseniy Yakovlev",
+    "rankPoints" : "350",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/4940400",
+    "content" : "Hello. \"TDA2Px ADAS applications processor 23mm package (ACD package) silicon revision 1.0 datasheet (Rev. F)\" has Table 5-4 Our frequencies are: IPU1_0 IPU1_1 DSP1 DSP2 EVE1 EVE2 IVA 212 212 1000 1000 900 900 532 For some reason i cannot get ISP frequency with Utils_prcmPrintAllCPUFrequency() built-in function, but all other values are matches up with table.",
+    "imageList" : [ "Data/input/1019218/png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Yes, i think ISP is still running at around 355MHz, even in OPP_Plus. Which boot are you using? Are you using uboot or SBL? Can you search on e2e forum? you could find how this can be changed.. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Arseniy Yakovlev",
+    "rankPoints" : "350",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/4940400",
+    "content" : "Hello. I didnt found any function or register which can give me access to ISP frequency in TRM or VisionSDK_ApiGuide. Is it actually possible?Can you provide any info? Thanks.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Can you please refer to file ti_components\\drivers\\pdk_01_10_02_07\\packages\\ti\\boot\\sbl_auto\\sbl_lib\\src\\tda2xx\\sbl_lib_tda2xx_prcm_dpll.c. This file in SBL sets up the isp clock. I dont see opp_plus, but there is opp_high mode. but i am not sure if isp clock is increased here. You could also refer to below e2e thread. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/763222/tda2p-abz-maximum-isp-throughput/2822349#2822349 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/864523/tda2pxevm-pdk_sw-the-performance-of-m2msimcopldcvtnf Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Arseniy Yakovlev",
+    "rankPoints" : "350",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/4940400",
+    "content" : "Hello. I have OppPlus option in my sbl_lib_tda2xx_prcm_dpll.c file: sbl_lib_tda2xx_prcm_dpll.c /*\n *  Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/\n *\n *  Redistribution and use in source and binary forms, with or without\n *  modification, are permitted provided that the following conditions\n *  are met:\n *\n *    Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *\n *    Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the\n *    distribution.\n *\n *    Neither the name of Texas Instruments Incorporated nor the names of\n *    its contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n *  \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n/**\n *  \\file     sbl_lib_tda2xx_prcm_dpll.c\n *\n *  \\brief    This file contains the structure for all DPLL Divider elements for\n *            TDA2xx SOC family. This also contains some related macros.\n */\n\n/* ========================================================================== */\n/*                             Include Files                                  */\n/* ========================================================================== */\n\n#include <stdint.h>\n#include <ti/csl/csl_types.h>\n#include <ti/csl/soc.h>\n#include <ti/boot/sbl_auto/sbl_lib/sbl_lib.h>\n#include <ti/boot/sbl_auto/sbl_lib/sbl_lib_board.h>\n#include <ti/boot/sbl_auto/sbl_lib/sbl_lib_config.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* ========================================================================== */\n/*                           Macros & Typedefs                                */\n/* ========================================================================== */\n\n/* None */\n\n/* ========================================================================== */\n/*                         Structures and Enums                               */\n/* ========================================================================== */\n\n/* None */\n\n/* ========================================================================== */\n/*                 Internal Function Declarations                             */\n/* ========================================================================== */\n\n/* None */\n\n/* ========================================================================== */\n/*                            Global Variables                                */\n/* ========================================================================== */\n\n/* Arrays given below are defined for 20 MHz */\nstatic pmhalPrcmPllPostDivValue_t dpllMpuPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n};\n#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_DRA72x)\nstatic pmhalPrcmPllPostDivValue_t dpllMpuPostDivCfgOppOd_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n};\n#endif\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmPllPostDivValue_t dpllMpuPostDivCfgOppHigh_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n};\n#endif\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmPllPostDivValue_t dpllCorePostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2,  2 },  /* Div_m2_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_H12, 4 },  /* Div_h12_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H13, 62},  /* Div_h13_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H14, 5 },  /* Div_h14_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H21, 6 },  /* Div_h21_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H22, 5 },  /* Div_h22_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H23, 4 },  /* Div_h23_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H24, 1 }   /* Div_h24_clkcfg */\n};\nstatic pmhalPrcmPllPostDivValue_t dpllCorePostDivCfgOppHigh_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2,  2 },  /* Div_m2_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_H12, 4 },  /* Div_h12_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H13, 62},  /* Div_h13_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H14, 5 },  /* Div_h14_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H21, 4 },  /* Div_h21_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H22, 5 },  /* Div_h22_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H23, 4 },  /* Div_h23_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H24, 1 }   /* Div_h24_clkcfg */\n};\n#else\nstatic pmhalPrcmPllPostDivValue_t dpllCorePostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2,  2 },  /* Div_m2_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_H12, 4 },  /* Div_h12_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H13, 62},  /* Div_h13_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H14, 5 },  /* Div_h14_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H22, 5 },  /* Div_h22_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H23, 4 },  /* Div_h23_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H24, 1 }   /* Div_h24_clkcfg */\n};\n#endif\n\nstatic pmhalPrcmPllPostDivValue_t dpllPerPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2,  4},  /* Div_m2_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_M3,  1},  /* Div_m3_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_H11, 3},  /* Div_h11_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H12, 4},  /* Div_h12_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H13, 4},  /* Div_h13_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H14, 2}   /* Div_h14_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllDspPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_M3, 3}  /* Div_m3_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllEvePostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 2} /* Div_m2_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllIvaPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 3} /* Div_m2_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllGpuPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 2} /* Div_m2_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllDdrPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2,  2},  /* Div_m2_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_H11, 8}   /* Div_h11_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllGmacPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2,  4 },  /* Div_m2_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_M3,  10},  /* Div_m3_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_H11, 40},  /* Div_h11_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H12, 8 },  /* Div_h12_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H13, 10}   /* Div_h13_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllAbePostDivCfgAllOpp_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_M3, 1}  /* Div_m3_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllUsbPostDivCfgAllOpp_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 2} /* Div_m2_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllPcieRefPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 15}, /* Div_m2_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllDspPostDivCfgOppOd_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_M3, 3}  /* Div_m3_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllIvaPostDivCfgOppOd_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 2}, /* Div_m2_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllGpuPostDivCfgOppOd_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 2} /* Div_m2_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllEvePostDivCfgOppHigh_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 2}, /* Div_m2_clkcfg */\n};\n\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmPllPostDivValue_t dpllEvePostDivCfgOppPlus_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n};\n#endif\n\nstatic pmhalPrcmPllPostDivValue_t dpllIvaPostDivCfgOppHigh_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 2}, /* Div_m2_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllVideo1PostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_H11, 13} /* Div_h11_clkcfg */\n};\n\nstatic pmhalPrcmPllPostDivValue_t dpllHdmiPostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1} /* Div_m2_clkcfg */\n};\n\n#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX)\nstatic pmhalPrcmPllPostDivValue_t dpllVideo2PostDivCfgOppNom_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2,  5 },  /* Div_m2_clkcfg  */\n    {PMHAL_PRCM_DPLL_POST_DIV_H11, 10},  /* Div_h11_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H12, 10},  /* Div_h12_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H13, 10},  /* Div_h13_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_H14, 10}   /* Div_h14_clkcfg */\n};\n#endif\n\n#if defined (SOC_TDA2XX)\nstatic pmhalPrcmPllPostDivValue_t dpllDspPostDivCfgOppHigh_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_M3, 3}  /* Div_m3_clkcfg */\n};\n#endif\n\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmPllPostDivValue_t dpllDspPostDivCfgOppHigh_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n    {PMHAL_PRCM_DPLL_POST_DIV_M3, 1}  /* Div_m3_clkcfg */\n};\n#endif\n\n#if defined (SOC_TDA2XX)\nstatic pmhalPrcmPllPostDivValue_t dpllMpuPostDivCfgOppLow_20[] =\n{\n    {PMHAL_PRCM_DPLL_POST_DIV_M2, 1}, /* Div_m2_clkcfg */\n};\n#endif\n\nstatic pmhalPrcmDpllConfig_t      dpllCoreCfgOppNom_20 =\n{\n    266,\n    4,\n    0,\n    dpllCorePostDivCfgOppNom_20,\n    (sizeof (dpllCorePostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\n#if defined (SOC_TDA2PX)\n/* DPLL Core is still configured at NOM freq. The post div H21 is configured,\n   based on different OPP used for ISP clock. */\nstatic pmhalPrcmDpllConfig_t      dpllCoreCfgOppHigh_20 =\n{\n    266,\n    4,\n    0,\n    dpllCorePostDivCfgOppHigh_20,\n    (sizeof (dpllCorePostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n\nstatic pmhalPrcmDpllConfig_t      dpllPerCfgOppNom_20 =\n{\n    96,\n    4,\n    0,\n    dpllPerPostDivCfgOppNom_20,\n    (sizeof (dpllPerPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllDspCfgOppNom_20 =\n{\n    150,\n    4,\n    0,\n    dpllDspPostDivCfgOppNom_20,\n    (sizeof (dpllDspPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllEveCfgOppNom_20 =\n{\n    214,\n    3,\n    0,\n    dpllEvePostDivCfgOppNom_20,\n    (sizeof (dpllEvePostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllIvaCfgOppNom_20 =\n{\n    233,\n    3,\n    0,\n    dpllIvaPostDivCfgOppNom_20,\n    (sizeof (dpllIvaPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllGpuCfgOppNom_20 =\n{\n    170,\n    3,\n    0,\n    dpllGpuPostDivCfgOppNom_20,\n    (sizeof (dpllGpuPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllGmacCfgOppNom_20 =\n{\n    250,\n    4,\n    0,\n    dpllGmacPostDivCfgOppNom_20,\n    (sizeof (dpllGmacPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllAbeCfgAllOpp_20 =\n{\n    200,\n    9,\n    0,\n    dpllAbePostDivCfgAllOpp_20,\n    (sizeof (dpllAbePostDivCfgAllOpp_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllUsbCfgAllOpp_20 =\n{\n    27,\n    0,\n    0,\n    dpllUsbPostDivCfgAllOpp_20,\n    (sizeof (dpllUsbPostDivCfgAllOpp_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllPcieRefCfgOppNom_20 =\n{\n    750,                                  /* Multiplier */\n    9,                                    /* Divider */\n    0,                                    /* DutyCycleCorrector */\n    dpllPcieRefPostDivCfgOppNom_20,\n    (sizeof (dpllPcieRefPostDivCfgOppNom_20) /\n     sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllDspCfgOppOd_20 =\n{\n    175,\n    4,\n    0,\n    dpllDspPostDivCfgOppOd_20,\n    (sizeof (dpllDspPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllIvaCfgOppOd_20 =\n{\n    172,\n    3,\n    0,\n    dpllIvaPostDivCfgOppOd_20,\n    (sizeof (dpllIvaPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllGpuCfgOppOd_20 =\n{\n    200,\n    3,\n    0,\n    dpllGpuPostDivCfgOppOd_20,\n    (sizeof (dpllGpuPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllEveCfgOppHigh_20 =\n{\n    260,\n    3,\n    0,\n    dpllEvePostDivCfgOppHigh_20,\n    (sizeof (dpllEvePostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t      dpllEveCfgOppPlus_20 =\n{\n    180,\n    3,\n    0,\n    dpllEvePostDivCfgOppPlus_20,\n    (sizeof (dpllEvePostDivCfgOppPlus_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n\nstatic pmhalPrcmDpllConfig_t      dpllIvaCfgOppHigh_20 =\n{\n    266,\n    4,\n    0,\n    dpllIvaPostDivCfgOppHigh_20,\n    (sizeof (dpllIvaPostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllVideo1CfgOppNom_20 =\n{\n    1637,                                 /* Multiplier */\n    39,                                   /* Divider */\n    0,                                    /* DutyCycleCorrector */\n    dpllVideo1PostDivCfgOppNom_20,\n    (sizeof (dpllVideo1PostDivCfgOppNom_20) /\n     sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllHdmiCfgOppNom_20 =\n{\n    1188,\n    15,\n    0,\n    dpllHdmiPostDivCfgOppNom_20,\n    (sizeof (dpllHdmiPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\n#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t      dpllVideo2CfgOppNom_20 =\n{\n    297,                                  /* Multiplier */\n    7,                                    /* Divider */\n    0,                                    /* DutyCycleCorrector */\n    dpllVideo2PostDivCfgOppNom_20,\n    (sizeof (dpllVideo2PostDivCfgOppNom_20) /\n     sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n\n#if defined (SOC_TDA2XX)\nstatic pmhalPrcmDpllConfig_t      dpllDspCfgOppHigh_20 =\n{\n    187,\n    4,\n    0,\n    dpllDspPostDivCfgOppHigh_20,\n    (sizeof (dpllDspPostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t      dpllDspCfgOppHigh_20 =\n{\n    187,\n    4,\n    0,\n    dpllDspPostDivCfgOppHigh_20,\n    (sizeof (dpllDspPostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllDspCfgOppHighHppPackage_20 =\n{\n    170,\n    3,\n    0,\n    dpllDspPostDivCfgOppHigh_20,\n    (sizeof (dpllDspPostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllDspCfgOppPlus_20 =\n{\n    500,\n    9,\n    0,\n    dpllDspPostDivCfgOppHigh_20,\n    (sizeof (dpllDspPostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n\n#if defined (SOC_TDA2XX)\nstatic pmhalPrcmDpllConfig_t      dpllMpuCfgOppLow_20 =\n{\n    250,\n    9,\n    0,\n    dpllMpuPostDivCfgOppLow_20,\n    (sizeof (dpllMpuPostDivCfgOppLow_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n\n#if defined (SOC_TDA2XX)\n/* TDA2xx DDR Phy Clk is configured at 532 */\nstatic pmhalPrcmDpllConfig_t      dpllDdrCfgOppNom_20 =\n{\n    266,\n    4,\n    0,\n    dpllDdrPostDivCfgOppNom_20,\n    (sizeof (dpllDdrPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#else\n/* TDA2Ex and TDA2Px DDR Phy Clk is configured at 666 */\nstatic pmhalPrcmDpllConfig_t      dpllDdrCfgOppNom_20 =\n{\n    333,\n    4,\n    0,\n    dpllDdrPostDivCfgOppNom_20,\n    (sizeof (dpllDdrPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n\n#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t      dpllMpuCfgOppNom_20 =\n{\n#if defined (SOC_DRA75x)\n    /* DRA74x/DRA75x OPP NOM is 1000 MHz MPU_CLK */\n    500,\n#else\n    /* TDA2xx OPP NOM is 750 MHz MPU_CLK */\n    375,\n#endif\n    9,\n    0,\n    dpllMpuPostDivCfgOppNom_20,\n    (sizeof (dpllMpuPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\nstatic pmhalPrcmDpllConfig_t      dpllMpuCfgOppOd_20 =\n{\n    294,\n    4,\n    0,\n    dpllMpuPostDivCfgOppOd_20,\n    (sizeof (dpllMpuPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#else\nstatic pmhalPrcmDpllConfig_t      dpllMpuCfgOppNom_20 =\n{\n#if defined (SOC_DRA72x)\n    /* DRA72x OPP NOM is 1000 MHz MPU_CLK */\n    500,\n#else\n    /* TDA2Ex OPP NOM is 800 MHz MPU_CLK */\n    400,\n#endif\n    9,\n    0,\n    dpllMpuPostDivCfgOppNom_20,\n    (sizeof (dpllMpuPostDivCfgOppNom_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n\n#if defined (SOC_DRA72x)\nstatic pmhalPrcmDpllConfig_t      dpllMpuCfgOppOd_20 =\n{\n    294,\n    4,\n    0,\n    dpllMpuPostDivCfgOppOd_20,\n    (sizeof (dpllMpuPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n#endif\n\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t      dpllMpuCfgOppHigh_20 =\n{\n    375,\n    4,\n    0,\n    dpllMpuPostDivCfgOppHigh_20,\n    (sizeof (dpllMpuPostDivCfgOppHigh_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n#if defined (SOC_TDA2EX) || defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t      dpllGpuCfgOppHigh_20 =\n{\n    266,\n    4,\n    0,\n    dpllGpuPostDivCfgOppOd_20,\n    (sizeof (dpllGpuPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t      dpllGpuCfgOppPlus_20 =\n{\n    266,\n    3,\n    0,\n    dpllGpuPostDivCfgOppOd_20,\n    (sizeof (dpllGpuPostDivCfgOppOd_20) / sizeof (pmhalPrcmPllPostDivValue_t)),\n    0\n};\n#endif\n\n\nstatic pmhalPrcmDpllConfig_t     *pDpllAbeCfg_20[] =\n{\n    &dpllAbeCfgAllOpp_20,\n    &dpllAbeCfgAllOpp_20,\n    &dpllAbeCfgAllOpp_20,\n    &dpllAbeCfgAllOpp_20,\n    &dpllAbeCfgAllOpp_20\n};\n\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t     *pDpllCoreCfg_20[] =\n{\n    &dpllCoreCfgOppNom_20,\n    &dpllCoreCfgOppNom_20,\n    &dpllCoreCfgOppNom_20,\n    &dpllCoreCfgOppHigh_20,\n    &dpllCoreCfgOppHigh_20\n};\n#else\nstatic pmhalPrcmDpllConfig_t     *pDpllCoreCfg_20[] =\n{\n    &dpllCoreCfgOppNom_20,\n    &dpllCoreCfgOppNom_20,\n    &dpllCoreCfgOppNom_20,\n    &dpllCoreCfgOppNom_20,\n    &dpllCoreCfgOppNom_20\n};\n#endif\n\nstatic pmhalPrcmDpllConfig_t     *pDpllDdrCfg_20[] =\n{\n    &dpllDdrCfgOppNom_20,\n    &dpllDdrCfgOppNom_20,\n    &dpllDdrCfgOppNom_20,\n    &dpllDdrCfgOppNom_20,\n    &dpllDdrCfgOppNom_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllGmacCfg_20[] =\n{\n    &dpllGmacCfgOppNom_20,\n    &dpllGmacCfgOppNom_20,\n    &dpllGmacCfgOppNom_20,\n    &dpllGmacCfgOppNom_20,\n    &dpllGmacCfgOppNom_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllIvaCfg_20[] =\n{\n    &dpllIvaCfgOppNom_20,\n    &dpllIvaCfgOppNom_20,\n    &dpllIvaCfgOppOd_20,\n    &dpllIvaCfgOppHigh_20,\n    &dpllIvaCfgOppHigh_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllPcieRefCfg_20[] =\n{\n    &dpllPcieRefCfgOppNom_20,\n    &dpllPcieRefCfgOppNom_20,\n    &dpllPcieRefCfgOppNom_20,\n    &dpllPcieRefCfgOppNom_20,\n    &dpllPcieRefCfgOppNom_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllPerCfg_20[] =\n{\n    &dpllPerCfgOppNom_20,\n    &dpllPerCfgOppNom_20,\n    &dpllPerCfgOppNom_20,\n    &dpllPerCfgOppNom_20,\n    &dpllPerCfgOppNom_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllUsbCfg_20[] =\n{\n    &dpllUsbCfgAllOpp_20,\n    &dpllUsbCfgAllOpp_20,\n    &dpllUsbCfgAllOpp_20,\n    &dpllUsbCfgAllOpp_20,\n    &dpllUsbCfgAllOpp_20\n};\n\n#if defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t     *pDpllEveCfgHppPackage_20[] =\n{\n    &dpllEveCfgOppNom_20,\n    &dpllEveCfgOppNom_20,\n    &dpllEveCfgOppHigh_20,\n    &dpllEveCfgOppHigh_20,\n    &dpllEveCfgOppPlus_20\n};\n#endif\n\nstatic pmhalPrcmDpllConfig_t     *pDpllEveCfg_20[] =\n{\n    &dpllEveCfgOppNom_20,\n    &dpllEveCfgOppNom_20,\n    &dpllEveCfgOppHigh_20,\n    &dpllEveCfgOppHigh_20,\n    &dpllEveCfgOppHigh_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllVideo1Cfg_20[] =\n{\n    &dpllVideo1CfgOppNom_20,\n    &dpllVideo1CfgOppNom_20,\n    &dpllVideo1CfgOppNom_20,\n    &dpllVideo1CfgOppNom_20,\n    &dpllVideo1CfgOppNom_20\n};\n\n#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t     *pDpllVideo2Cfg_20[] =\n{\n    &dpllVideo2CfgOppNom_20,\n    &dpllVideo2CfgOppNom_20,\n    &dpllVideo2CfgOppNom_20,\n    &dpllVideo2CfgOppNom_20,\n    &dpllVideo2CfgOppNom_20\n};\n#endif\n\nstatic pmhalPrcmDpllConfig_t     *pDpllHdmiCfg_20[] =\n{\n    &dpllHdmiCfgOppNom_20,\n    &dpllHdmiCfgOppNom_20,\n    &dpllHdmiCfgOppNom_20,\n    &dpllHdmiCfgOppNom_20,\n    &dpllHdmiCfgOppNom_20\n};\n/* Configuration for DPLL DSP */\n#if defined (SOC_TDA2XX)\nstatic pmhalPrcmDpllConfig_t     *pDpllDspCfg_20[] =\n{\n    &dpllDspCfgOppNom_20,\n    &dpllDspCfgOppNom_20,\n    &dpllDspCfgOppOd_20,\n    &dpllDspCfgOppHigh_20,\n    &dpllDspCfgOppHigh_20\n};\n\n#elif defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t     *pDpllDspCfg_20[] =\n{\n    &dpllDspCfgOppNom_20,\n    &dpllDspCfgOppNom_20,\n    &dpllDspCfgOppOd_20,\n    &dpllDspCfgOppHigh_20,\n    &dpllDspCfgOppHigh_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllDspCfgHppPackage_20[] =\n{\n    &dpllDspCfgOppNom_20,\n    &dpllDspCfgOppNom_20,\n    &dpllDspCfgOppOd_20,\n    &dpllDspCfgOppHighHppPackage_20,\n    &dpllDspCfgOppPlus_20\n};\n\n#else\nstatic pmhalPrcmDpllConfig_t     *pDpllDspCfg_20[] =\n{\n    &dpllDspCfgOppNom_20,\n    &dpllDspCfgOppNom_20,\n    &dpllDspCfgOppOd_20,\n    &dpllDspCfgOppOd_20,\n    &dpllDspCfgOppOd_20\n};\n#endif\n\n/* Configuration for DPLL GPU */\n#if defined (SOC_TDA2XX)\nstatic pmhalPrcmDpllConfig_t     *pDpllGpuCfg_20[] =\n{\n    &dpllGpuCfgOppNom_20,\n    &dpllGpuCfgOppNom_20,\n    &dpllGpuCfgOppOd_20,\n    &dpllGpuCfgOppOd_20,\n    &dpllGpuCfgOppOd_20\n};\n#elif defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t     *pDpllGpuCfg_20[] =\n{\n    &dpllGpuCfgOppNom_20,\n    &dpllGpuCfgOppNom_20,\n    &dpllGpuCfgOppOd_20,\n    &dpllGpuCfgOppHigh_20,\n    &dpllGpuCfgOppHigh_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllGpuCfgHppPackage_20[] =\n{\n    &dpllGpuCfgOppNom_20,\n    &dpllGpuCfgOppNom_20,\n    &dpllGpuCfgOppOd_20,\n    &dpllGpuCfgOppHigh_20,\n    &dpllGpuCfgOppPlus_20\n};\n#else\nstatic pmhalPrcmDpllConfig_t     *pDpllGpuCfg_20[] =\n{\n    &dpllGpuCfgOppNom_20,\n    &dpllGpuCfgOppNom_20,\n    &dpllGpuCfgOppOd_20,\n    &dpllGpuCfgOppHigh_20,\n    &dpllGpuCfgOppHigh_20\n};\n#endif\n\n/* Configuration for DPLL MPU */\n#if defined (SOC_TDA2XX)\nstatic pmhalPrcmDpllConfig_t     *pDpllMpuCfg_23x23Package_20[] =\n{\n    &dpllMpuCfgOppLow_20,\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppOd_20,\n    &dpllMpuCfgOppOd_20,\n    &dpllMpuCfgOppOd_20\n};\nstatic pmhalPrcmDpllConfig_t     *pDpllMpuCfg_17x17Package_20[] =\n{\n    &dpllMpuCfgOppLow_20,\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppNom_20\n};\n#elif defined (SOC_TDA2PX)\nstatic pmhalPrcmDpllConfig_t     *pDpllMpuCfg_23x23Package_20[] =\n{\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppOd_20,\n    &dpllMpuCfgOppOd_20,\n    &dpllMpuCfgOppOd_20\n};\n\nstatic pmhalPrcmDpllConfig_t     *pDpllMpuCfgHppPackage_20[] =\n{\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppOd_20,\n    &dpllMpuCfgOppHigh_20,\n    &dpllMpuCfgOppHigh_20\n};\n\n#else\nstatic pmhalPrcmDpllConfig_t     *pDpllMpuCfg_23x23Package_20[] =\n{\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppNom_20,\n#if defined (SOC_DRA72x)\n    &dpllMpuCfgOppOd_20,\n    &dpllMpuCfgOppOd_20,\n    &dpllMpuCfgOppOd_20\n#else\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppNom_20,\n    &dpllMpuCfgOppNom_20\n#endif\n};\n#endif\n\n/* ========================================================================== */\n/*                          Function Declarations                             */\n/* ========================================================================== */\n\nint32_t SBLLibGetDpllStructure(uint32_t                dpllId,\n                               uint32_t                sysClk,\n                               uint32_t                opp,\n                               pmhalPrcmDpllConfig_t **dpllCfg)\n{\n#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX)\n    uint32_t siliconPackageType;\n#endif\n    int32_t  retVal = STW_SOK;\n\n    if (PMHAL_PRCM_SYSCLK_20_MHZ == sysClk)\n    {\n        switch (dpllId)\n        {\n            case PMHAL_PRCM_DPLL_ABE:\n                *dpllCfg = pDpllAbeCfg_20[opp];\n                break;\n            case PMHAL_PRCM_DPLL_CORE:\n                *dpllCfg = pDpllCoreCfg_20[opp];\n                break;\n            case PMHAL_PRCM_DPLL_DDR:\n                *dpllCfg = pDpllDdrCfg_20[opp];\n                break;\n            case PMHAL_PRCM_DPLL_GMAC:\n                *dpllCfg = pDpllGmacCfg_20[opp];\n                break;\n            case PMHAL_PRCM_DPLL_GPU:\n#if defined (SOC_TDA2PX)\n                siliconPackageType = SBLLibGetSiliconPackageType();\n                if (SBLLIB_SILICON_PACKAGE_TYPE_23X23_HPP == siliconPackageType)\n                {\n                    *dpllCfg = pDpllGpuCfgHppPackage_20[opp];\n                }\n                else\n                {\n                    *dpllCfg = pDpllGpuCfg_20[opp];\n                }\n#else\n                *dpllCfg = pDpllGpuCfg_20[opp];\n#endif\n                break;\n            case PMHAL_PRCM_DPLL_IVA:\n                *dpllCfg = pDpllIvaCfg_20[opp];\n                break;\n            case PMHAL_PRCM_DPLL_PCIE_REF:\n                *dpllCfg = pDpllPcieRefCfg_20[opp];\n                break;\n            case PMHAL_PRCM_DPLL_PER:\n                *dpllCfg = pDpllPerCfg_20[opp];\n                break;\n            case PMHAL_PRCM_DPLL_USB:\n                *dpllCfg = pDpllUsbCfg_20[opp];\n                break;\n            case PMHAL_PRCM_DPLL_DSP:\n#if defined (SOC_TDA2PX)\n                siliconPackageType = SBLLibGetSiliconPackageType();\n                if (SBLLIB_SILICON_PACKAGE_TYPE_23X23_HPP == siliconPackageType)\n                {\n                    *dpllCfg = pDpllDspCfgHppPackage_20[opp];\n                }\n                else\n                {\n                    *dpllCfg = pDpllDspCfg_20[opp];\n                }\n#else\n                *dpllCfg = pDpllDspCfg_20[opp];\n#endif\n                break;\n            case PMHAL_PRCM_DPLL_EVE:\n#if defined (SOC_TDA2PX)\n                siliconPackageType = SBLLibGetSiliconPackageType();\n                if (SBLLIB_SILICON_PACKAGE_TYPE_23X23_HPP == siliconPackageType)\n                {\n                    *dpllCfg = pDpllEveCfgHppPackage_20[opp];\n                }\n                else\n                {\n                    *dpllCfg = pDpllEveCfg_20[opp];\n                }\n#else\n                *dpllCfg = pDpllEveCfg_20[opp];\n#endif\n                break;\n            case PMHAL_PRCM_DPLL_MPU:\n#if defined (SOC_TDA2XX)\n                siliconPackageType = SBLLibGetSiliconPackageType();\n                if (SBLLIB_SILICON_PACKAGE_TYPE_17X17 == siliconPackageType)\n                {\n                    *dpllCfg = pDpllMpuCfg_17x17Package_20[opp];\n                }\n                else\n                {\n                    *dpllCfg = pDpllMpuCfg_23x23Package_20[opp];\n                }\n#elif defined (SOC_TDA2PX)\n                siliconPackageType = SBLLibGetSiliconPackageType();\n                if (SBLLIB_SILICON_PACKAGE_TYPE_23X23_HPP == siliconPackageType)\n                {\n                    *dpllCfg = pDpllMpuCfgHppPackage_20[opp];\n                }\n                else\n                {\n                    *dpllCfg = pDpllMpuCfg_23x23Package_20[opp];\n                }\n#else\n                *dpllCfg = pDpllMpuCfg_23x23Package_20[opp];\n#endif\n                break;\n            case PMHAL_PRCM_VIDEOPLL_VIDEO1:\n                *dpllCfg = pDpllVideo1Cfg_20[opp];\n                break;\n#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX)\n            case PMHAL_PRCM_VIDEOPLL_VIDEO2:\n                *dpllCfg = pDpllVideo2Cfg_20[opp];\n                break;\n#endif\n            case PMHAL_PRCM_VIDEOPLL_HDMI:\n                *dpllCfg = pDpllHdmiCfg_20[opp];\n                break;\n            default:\n                retVal = STW_EFAIL;\n                break;\n        }\n    }\n    else\n    {\n        retVal = STW_EFAIL;\n    }\n\n    return retVal;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n Can you check my values and say if they are correct? I will try to understand if it affects ISP clock. Thanks.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Looks fine, can you with this change? Please note this will work only if you are using SBL. Rgds, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "I think you are using DPLL_CORE clock, so, can you try reducing H21 divisor value in below? static pmhalPrcmPllPostDivValue_t dpllCorePostDivCfgOppHigh_20[] = { {PMHAL_PRCM_DPLL_POST_DIV_M2, 2 }, /* Div_m2_clkcfg */ {PMHAL_PRCM_DPLL_POST_DIV_H12, 4 }, /* Div_h12_clkcfg */ {PMHAL_PRCM_DPLL_POST_DIV_H13, 62}, /* Div_h13_clkcfg */ {PMHAL_PRCM_DPLL_POST_DIV_H14, 5 }, /* Div_h14_clkcfg */ {PMHAL_PRCM_DPLL_POST_DIV_H21, 4 }, /* Div_h21_clkcfg */ {PMHAL_PRCM_DPLL_POST_DIV_H22, 5 }, /* Div_h22_clkcfg */ {PMHAL_PRCM_DPLL_POST_DIV_H23, 4 }, /* Div_h23_clkcfg */ {PMHAL_PRCM_DPLL_POST_DIV_H24, 1 } /* Div_h24_clkcfg */ }; Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Arseniy Yakovlev",
+    "rankPoints" : "350",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/4940400",
+    "content" : "Hello. Yes we are using SBL. Divisor values {PMHAL_PRCM_DPLL_POST_DIV_H21, 2} or {PMHAL_PRCM_DPLL_POST_DIV_H21, 1} give no visible difference in links latency. Are there any other values or combinations of values that i should try? Thanks.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hello, Can you please check the clock source for the ISP? Depending on it, we would have to change the divisor value. Regards, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1021421.json

@@ -0,0 +1,205 @@
+{
+  "ticketNumber" : "1021421",
+  "reporterName" : "Wu BoHan",
+  "rankPoints" : "315",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: RGB Interlaced output on LCD1",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, SYSCONFIG Hi Expert, I'm developing a custom tda2sx board on TI-RTOS Vision SDK v03.05. I need RGB888 Interlaced output on LCD1. I tried changing the scan format in chains_common.c. The following is my setting: static Void ChainsCommon_SetDctrlConfig pVInfo->mInfo.scanFormat = SYSTEM_SF_INTERLACED; pVInfo->mInfo.standard = SYSTEM_STD_576I; pVInfo->mInfo.pixelClock = 13500U; pVInfo->mInfo.vBackPorch = 19U; pVInfo->mInfo.vSyncLen = 3U; pVInfo->mInfo.vFrontPorch = 2U; pVInfo->mInfo.hBackPorch = 138U; pVInfo->mInfo.hSyncLen = 126U; pVInfo->mInfo.hFrontPorch = 24U; pVInfo->mInfo.fps = 50U; But no matter how I change the configuration, vout clk and sync remain the same. Always the following result CLK: 27.xMHz Hsync: 32.xkHz Vsync: 50 Are my settings correct, or are there other steps? My query is related to the thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/803192/rtos-tda2p-abz-working-of-adv7393-on-tda2px Could you please give some suggestions here? Thanks in advance.",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Interlaced and pixel clock are two different things. There is a separate interface for setting up clock, please use it to change the clock. Also vsync rate can remain same, depending on timing parameter. So could you please share your exact requirement? Rgds, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, My requirement is below: CLK：13.5 MHz Hsync：15.625 kHz Vsync：50 I tried to change pVInfo->mInfo, but it did not affect the result. pVInfo->mInfo.width = displayWidth; // 576 pVInfo->mInfo.height = displayHeight; // 720 pVInfo->mInfo.pixelClock = 13500U; But the CLK output is always 27MHz. Please tell me how to configure the \"separate interface for setting the clock\"? Thanks in advance.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "You could change the pixel clock using this API Bsp_platformSetVencClkSrc. Please change clock to 13.5MHz here. Rgds, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, According to your suggestion, the current output is as follows: CLK: 13.5 MHz Hsync: 15.625 kHz Vsync: 25 Hz How can I adjust Vsync to 50?? In addition, I will confirm with you again that the tda2 series can achieve RGB888 Interlaced output on LCD1? Thanks in advance.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "ok, atleast clock is correct now, 13.5Mhz We need to now configure DSS to output interlaced resolution. can you please check if interlaced output is set in the config/control register for the LCD you are using? Rgds, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, a. Can you tell me which registers should be checked for interlaced output? b. My configuration is as follows, why do I need to check? pVInfo->mInfo.width = displayWidth; // 576 pVInfo->mInfo.height = displayHeight; // 720 pVInfo->mInfo.scanFormat = SYSTEM_SF_INTERLACED; pVInfo->mInfo.standard = SYSTEM_STD_576I; c. Please answer me, can tda2 series achieve RGB888 Interlaced output on LCD1? Thanks in advance.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Wu BoHan said: a. Can you tell me which registers should be checked for interlaced output? Can you check DISPC_CONFIG. OUTPUTMODE_ENABLE (bit25) for the LCD output that you are using? This must be set to 1 for interlaced output Wu BoHan said: b. My configuration is as follows, why do I need to check? pVInfo->mInfo.width = displayWidth; // 576 pVInfo->mInfo.height = displayHeight; // 720 pVInfo->mInfo.scanFormat = SYSTEM_SF_INTERLACED; pVInfo->mInfo.standard = SYSTEM_STD_576I; This looks to be correct. Wu BoHan said: c. Please answer me, can tda2 series achieve RGB888 Interlaced output on LCD1? Weil, possible, but not validated. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, Brijesh Jadav said: Can you check DISPC_CONFIG. OUTPUTMODE_ENABLE (bit25) for the LCD output that you are using? This must be set to 1 for interlaced output I checked DISPC_CONFIG1(0x5800 1044) and the result was 0x0040 0c04. OUTPUTMODEENABLE (bit 22) 0x1: Interlace mode selected How should I check or set the next step? thanks.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Can you please run gel file from pdk_xx_xx_xx_xx\\packages\\ti\\drv\\vps\\docs\\tda2xx\\TDA2xx_Dss_RegDump.gel from IPU core? and share the output. This will tell us if the register is setup correctly. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, The results of run gel are as follows: [IPU1-0] 29.388702 s: DSS_DISPC_REVISION = 0x51 [IPU1-0] 29.388824 s: DSS_DISPC_SYSCONFIG = 0x1 [IPU1-0] 29.388916 s: DSS_DISPC_SYSSTATUS = 0x1 [IPU1-0] 29.389068 s: DSS_DISPC_IRQSTATUS = 0x0 [IPU1-0] 29.389190 s: DSS_DISPC_IRQENABLE = 0x4662 [IPU1-0] 29.389373 s: DSS_DISPC_CONTROL1 = 0x329 [IPU1-0] 29.389556 s: DSS_DISPC_CONFIG1 = 0x400c04 [IPU1-0] 29.389800 s: DSS_DISPC_DEFAULT_COLOR0 = 0x0 [IPU1-0] 29.390197 s: DSS_DISPC_DEFAULT_COLOR1 = 0x0 [IPU1-0] 29.390319 s: DSS_DISPC_TRANS_COLOR0 = 0x0 [IPU1-0] 29.390502 s: DSS_DISPC_TRANS_COLOR1 = 0x0 [IPU1-0] 29.390624 s: DSS_DISPC_LINE_STATUS = 0x16 [IPU1-0] 29.390776 s: DSS_DISPC_LINE_NUMBER = 0x23b [IPU1-0] 29.390898 s: DSS_DISPC_TIMING_H1 = 0x4400b3e [IPU1-0] 29.391356 s: DSS_DISPC_TIMING_V1 = 0x1300202 [IPU1-0] 29.391661 s: DSS_DISPC_POL_FREQ1 = 0x7000 [IPU1-0] 29.391844 s: DSS_DISPC_DIVISOR1 = 0x10001 [IPU1-0] 29.391966 s: DSS_DISPC_GLOBAL_ALPHA = 0xffffffff [IPU1-0] 29.416610 s: DSS_DISPC_SIZE_TV = 0x0 [IPU1-0] 29.416732 s: DSS_DISPC_SIZE_LCD1 = 0x23f02cf [IPU1-0] 29.416946 s: DSS_DISPC_GFX_BA0 = 0x84d95800 [IPU1-0] 29.417190 s: DSS_DISPC_GFX_BA1 = 0x84d95da0 [IPU1-0] 29.417312 s: DSS_DISPC_GFX_POSITION = 0x0 [IPU1-0] 29.417525 s: DSS_DISPC_GFX_SIZE = 0x0 [IPU1-0] 29.417647 s: DSS_DISPC_GFX_ATTRIBUTES = 0xe0000a1 [IPU1-0] 29.417830 s: DSS_DISPC_GFX_BUF_THRESHOLD = 0x4ff04f8 [IPU1-0] 29.417952 s: DSS_DISPC_GFX_BUF_SIZE_STATUS = 0x500 [IPU1-0] 29.418349 s: DSS_DISPC_GFX_ROW_INC = 0x1 [IPU1-0] 29.418471 s: DSS_DISPC_GFX_PIXEL_INC = 0x1 [IPU1-0] 29.418593 s: DSS_DISPC_GFX_TABLE_BA = 0x0 [IPU1-0] 29.418745 s: DSS_DISPC_VID1_BA0 = 0x84c33000 [IPU1-0] 29.418867 s: DSS_DISPC_VID1_BA1 = 0x84c332d0 [IPU1-0] 29.418989 s: DSS_DISPC_VID1_POSITION = 0x0 [IPU1-0] 29.419172 s: DSS_DISPC_VID1_SIZE = 0x0 [IPU1-0] 29.419325 s: DSS_DISPC_VID1_ATTRIBUTES = 0x2008401 [IPU1-0] 29.419447 s: DSS_DISPC_VID1_BUF_THRESHOLD = 0x7ff07f8 [IPU1-0] 29.419569 s: DSS_DISPC_VID1_BUF_SIZE_STATUS = 0x800 [IPU1-0] 29.419691 s: DSS_DISPC_VID1_ROW_INC = 0x1 [IPU1-0] 29.419813 s: DSS_DISPC_VID1_PIXEL_INC = 0x1 [IPU1-0] 29.419935 s: DSS_DISPC_VID1_FIR = 0x4000400 [IPU1-0] 29.420148 s: DSS_DISPC_VID1_PICTURE_SIZE = 0x0 [IPU1-0] 29.420270 s: DSS_DISPC_VID1_CONV_COEF0 = 0x0 [IPU1-0] 29.420453 s: DSS_DISPC_VID1_CONV_COEF1 = 0x0 [IPU1-0] 29.420575 s: DSS_DISPC_VID1_CONV_COEF2 = 0x0 [IPU1-0] 29.420728 s: DSS_DISPC_VID1_CONV_COEF3 = 0x0 [IPU1-0] 29.420850 s: DSS_DISPC_VID1_CONV_COEF4 = 0x0 [IPU1-0] 29.420972 s: DSS_DISPC_VID2_POSITION = 0x0 [IPU1-0] 29.426096 s: DSS_DISPC_VID2_SIZE = 0x0 [IPU1-0] 29.426188 s: DSS_DISPC_VID2_ATTRIBUTES = 0x6008400 [IPU1-0] 29.426432 s: DSS_DISPC_VID2_BUF_THRESHOLD = 0x7ff07f8 [IPU1-0] 29.426523 s: DSS_DISPC_VID2_BUF_SIZE_STATUS = 0x800 [IPU1-0] 29.426584 s: DSS_DISPC_VID2_ROW_INC = 0x1 [IPU1-0] 29.426676 s: DSS_DISPC_VID2_PIXEL_INC = 0x1 [IPU1-0] 29.426737 s: DSS_DISPC_VID2_FIR = 0x4000400 [IPU1-0] 29.426798 s: DSS_DISPC_VID2_PICTURE_SIZE = 0x0 [IPU1-0] 29.426859 s: DSS_DISPC_VID2_CONV_COEF0 = 0x0 [IPU1-0] 29.426950 s: DSS_DISPC_VID2_CONV_COEF1 = 0x0 [IPU1-0] 29.427011 s: DSS_DISPC_VID2_CONV_COEF2 = 0x0 [IPU1-0] 29.427286 s: DSS_DISPC_VID2_CONV_COEF3 = 0x0 [IPU1-0] 29.427347 s: DSS_DISPC_VID2_CONV_COEF4 = 0x0 [IPU1-0] 29.427438 s: DSS_DISPC_DATA1_CYCLE1 = 0x0 [IPU1-0] 29.427499 s: DSS_DISPC_DATA1_CYCLE2 = 0x0 [IPU1-0] 29.427560 s: DSS_DISPC_DATA1_CYCLE3 = 0x0 [IPU1-0] 29.427621 s: DSS_DISPC_CPR1_COEF_R = 0x0 [IPU1-0] 29.427774 s: DSS_DISPC_CPR1_COEF_G = 0x0 [IPU1-0] 29.427896 s: DSS_DISPC_CPR1_COEF_B = 0x0 [IPU1-0] 29.428018 s: DSS_DISPC_GFX_PRELOAD = 0x100 [IPU1-0] 29.428597 s: DSS_DISPC_VID1_PRELOAD = 0x100 [IPU1-0] 29.428719 s: DSS_DISPC_VID2_PRELOAD = 0x100 [IPU1-0] 29.428841 s: DSS_DISPC_CONTROL2 = 0x300 [IPU1-0] 29.428963 s: DSS_DISPC_GFX_POSITION2 = 0x0 [IPU1-0] 29.429421 s: DSS_DISPC_VID1_POSITION2 = 0x0 [IPU1-0] 29.429543 s: DSS_DISPC_VID2_POSITION2 = 0x0 [IPU1-0] 29.429665 s: DSS_DISPC_VID3_POSITION2 = 0x0 [IPU1-0] 29.429878 s: DSS_DISPC_VID3_ATTRIBUTES = 0xa008400 [IPU1-0] 29.430458 s: DSS_DISPC_VID3_CONV_COEF0 = 0x0 [IPU1-0] 29.430580 s: DSS_DISPC_VID3_CONV_COEF1 = 0x0 [IPU1-0] 29.430702 s: DSS_DISPC_VID3_CONV_COEF2 = 0x0 [IPU1-0] 29.430885 s: DSS_DISPC_VID3_CONV_COEF3 = 0x0 [IPU1-0] 29.431007 s: DSS_DISPC_VID3_CONV_COEF4 = 0x0 [IPU1-0] 29.444915 s: DSS_DISPC_VID3_BUF_SIZE_STATUS = 0x800 [IPU1-0] 29.445312 s: DSS_DISPC_VID3_BUF_THRESHOLD = 0x7ff07f8 [IPU1-0] 29.445495 s: DSS_DISPC_VID3_FIR = 0x4000400 [IPU1-0] 29.445617 s: DSS_DISPC_VID3_PICTURE_SIZE = 0x0 [IPU1-0] 29.445739 s: DSS_DISPC_VID3_PIXEL_INC = 0x1 [IPU1-0] 29.445861 s: DSS_DISPC_VID3_POSITION = 0x0 [IPU1-0] 29.446013 s: DSS_DISPC_VID3_PRELOAD = 0x100 [IPU1-0] 29.446440 s: DSS_DISPC_VID3_ROW_INC = 0x1 [IPU1-0] 29.446562 s: DSS_DISPC_VID3_SIZE = 0x0 [IPU1-0] 29.446715 s: DSS_DISPC_DEFAULT_COLOR2 = 0x0 [IPU1-0] 29.446837 s: DSS_DISPC_TRANS_COLOR2 = 0x0 [IPU1-0] 29.446959 s: DSS_DISPC_CPR2_COEF_B = 0x0 [IPU1-0] 29.447355 s: DSS_DISPC_CPR2_COEF_G = 0x0 [IPU1-0] 29.447477 s: DSS_DISPC_CPR2_COEF_R = 0x0 [IPU1-0] 29.447660 s: DSS_DISPC_DATA2_CYCLE1 = 0x0 [IPU1-0] 29.447782 s: DSS_DISPC_DATA2_CYCLE2 = 0x0 [IPU1-0] 29.447935 s: DSS_DISPC_DATA2_CYCLE3 = 0x0 [IPU1-0] 29.448179 s: DSS_DISPC_SIZE_LCD2 = 0x0 [IPU1-0] 29.448301 s: DSS_DISPC_TIMING_H2 = 0x0 [IPU1-0] 29.448423 s: DSS_DISPC_TIMING_V2 = 0x0 [IPU1-0] 29.448545 s: DSS_DISPC_POL_FREQ2 = 0x0 [IPU1-0] 29.448697 s: DSS_DISPC_DIVISOR2 = 0x40001 [IPU1-0] 29.448819 s: DSS_DISPC_WB_ATTRIBUTES = 0x8000 [IPU1-0] 29.448941 s: DSS_DISPC_WB_CONV_COEF0 = 0x0 [IPU1-0] 29.464497 s: DSS_DISPC_WB_CONV_COEF1 = 0x0 [IPU1-0] 29.464588 s: DSS_DISPC_WB_CONV_COEF2 = 0x0 [IPU1-0] 29.464863 s: DSS_DISPC_WB_CONV_COEF3 = 0x0 [IPU1-0] 29.464924 s: DSS_DISPC_WB_CONV_COEF4 = 0x0 [IPU1-0] 29.464985 s: DSS_DISPC_WB_BUF_SIZE_STATUS = 0x800 [IPU1-0] 29.465107 s: DSS_DISPC_WB_BUF_THRESHOLD = 0x7ff07f8 [IPU1-0] 29.465168 s: DSS_DISPC_WB_FIR = 0x4000400 [IPU1-0] 29.465229 s: DSS_DISPC_WB_PICTURE_SIZE = 0x0 [IPU1-0] 29.465320 s: DSS_DISPC_WB_PIXEL_INC = 0x1 [IPU1-0] 29.465381 s: DSS_DISPC_WB_ROW_INC = 0x1 [IPU1-0] 29.465442 s: DSS_DISPC_WB_SIZE = 0x0 [IPU1-0] 29.465503 s: DSS_DISPC_VID1_BA_UV0 = 0x84b35a00 [IPU1-0] 29.465564 s: DSS_DISPC_VID1_BA_UV1 = 0x84b35cd0 [IPU1-0] 29.465656 s: DSS_DISPC_CONFIG2 = 0x0 [IPU1-0] 29.465717 s: DSS_DISPC_VID1_ATTRIBUTES2 = 0x0 [IPU1-0] 29.465778 s: DSS_DISPC_VID2_ATTRIBUTES2 = 0x0 [IPU1-0] 29.465869 s: DSS_DISPC_VID3_ATTRIBUTES2 = 0x0 [IPU1-0] 29.465930 s: DSS_DISPC_GAMMA_TABLE0 = 0x0 [IPU1-0] 29.465991 s: DSS_DISPC_GAMMA_TABLE2 = 0x0 [IPU1-0] 29.466296 s: DSS_DISPC_VID1_FIR2 = 0x4000400 [IPU1-0] 29.466418 s: DSS_DISPC_VID2_FIR2 = 0x4000400 [IPU1-0] 29.466540 s: DSS_DISPC_VID3_FIR2 = 0x4000400 [IPU1-0] 29.466662 s: DSS_DISPC_WB_FIR2 = 0x4000400 [IPU1-0] 29.466784 s: DSS_DISPC_GLOBAL_BUFFER = 0x246d2240 [IPU1-0] 29.466937 s: DSS_DISPC_DIVISOR = 0x10001 [IPU1-0] 29.467364 s: DSS_DISPC_WB_ATTRIBUTES2 = 0x0 [IPU1-0] 29.467516 s: DSS_DISPC_DEFAULT_COLOR3 = 0x0 [IPU1-0] 29.467638 s: DSS_DISPC_TRANS_COLOR3 = 0x0 [IPU1-0] 29.467760 s: DSS_DISPC_CPR3_COEF_B = 0x0 [IPU1-0] 29.467882 s: DSS_DISPC_CPR3_COEF_G = 0x0 [IPU1-0] 29.468004 s: DSS_DISPC_CPR3_COEF_R = 0x0 [IPU1-0] 29.468462 s: DSS_DISPC_DATA3_CYCLE1 = 0x0 [IPU1-0] 29.468584 s: DSS_DISPC_DATA3_CYCLE2 = 0x0 [IPU1-0] 29.468706 s: DSS_DISPC_DATA3_CYCLE3 = 0x0 [IPU1-0] 29.468919 s: DSS_DISPC_SIZE_LCD3 = 0x0 [IPU1-0] 29.493747 s: DSS_DISPC_DIVISOR3 = 0x40001 [IPU1-0] 29.493869 s: DSS_DISPC_POL_FREQ3 = 0x0 [IPU1-0] 29.494387 s: DSS_DISPC_TIMING_H3 = 0x0 [IPU1-0] 29.494509 s: DSS_DISPC_TIMING_V3 = 0x0 [IPU1-0] 29.494631 s: DSS_DISPC_CONTROL3 = 0x300 [IPU1-0] 29.494845 s: DSS_DISPC_CONFIG3 = 0x0 [IPU1-0] 29.494967 s: DSS_DISPC_BA0_FLIPIMMEDIATE_EN = 0x0 [IPU1-0] 29.495424 s: DSS_DISPC_DISABLE_MSTANDBY_ENHANCEMENT = 0x1 [IPU1-0] 29.495546 s: DSS_DISPC_GLOBAL_MFLAG_ATTRIBUTE = 0x6 [IPU1-0] 29.495668 s: DSS_DISPC_GFX_MFLAG_THRESHOLD = 0x0 [IPU1-0] 29.495790 s: DSS_DISPC_VID1_MFLAG_THRESHOLD = 0x0 [IPU1-0] 29.495912 s: DSS_DISPC_VID2_MFLAG_THRESHOLD = 0x0 [IPU1-0] 29.496370 s: DSS_DISPC_VID3_MFLAG_THRESHOLD = 0x0 [IPU1-0] 29.496492 s: DSS_DISPC_WB_MFLAG_THRESHOLD = 0x0 How should I check or set the next step? thanks.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, I think the issue can be due to below register, it should be set to half of frame size. It should be set (288-1) for the field display. Can you try with this change? 9.416732 s: DSS_DISPC_SIZE_LCD1 = 0x23f02cf Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, I directly modify the DSS_DISPC_SIZE_LCD1 register to 0x11f02c. The Vsync output is 50Hz, but it is not continuous. As shown below: a. Is there an API to modify DSS_DISPC_SIZE_LCD1? b. In addition, Vsync is not continuous, how to fix it? thanks.",
+    "imageList" : [ "Data/input/1021421/jpg" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, What do you mean by vsync is not continuous? Also can you confirm that DSS_DISPC_SIZE_LCD1 is set to 0x11d02cf? Also how about the vertical timing? We would have to make vertical timing also half. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, I modify the DSS_DISPC_SIZE_LCD1 register is set to 0x11d02cf. The vertical timing is shown below: Why is there no Vsync at the position marked by the green line? thanks.",
+    "imageList" : [ "Data/input/1021421/jpg" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Did you also change the timing? I think you need to halve the virtual timing. I guess driver will set full vertical timing, so can make all timing to half in timing_v register? Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, Brijesh Jadav said: so can make all timing to half in timing_v register? The timing_v register is DISPC_TIMING_V1 (0x5800 1068)? My configuration is as follows: static Void ChainsCommon_SetDctrlConfig pVInfo->mInfo.vBackPorch = 19U; pVInfo->mInfo.vSyncLen = 3U; pVInfo->mInfo.vFrontPorch = 2U; pVInfo->mInfo.hBackPorch = 138U; pVInfo->mInfo.hSyncLen = 126U; pVInfo->mInfo.hFrontPorch = 24U; Wu BoHan said: [IPU1-0] 29.390898 s: DSS_DISPC_TIMING_H1 = 0x4400b3e [IPU1-0] 29.391356 s: DSS_DISPC_TIMING_V1 = 0x1300202 VBP[31:20]: 0x013 → 19 VFP[19:8]: 0x002 → 2 VSW[7:0]: 0x02 → 2 HBP[31:20]: 0x044 → 68 HFP[19:8]: 0x00b → 11 HSW[7:0]: 0x3e → 62 Do I need to halve the virtual timing? Is there an API to using? thanks.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, vsync cannot vary so much. Once the timing is provided, atleast, it will be periodic. so are you sure that you are measuring vsync? Is DSS really configured for discrete sync output? And also is the pinmux for the vsync output setup correctly? Regarding timing, for PAL resolution, there would be 312 lines per field. You are programming 286 + 19 + 2 + 3 lines, which is 310 lines.. It is slightly short, but even with this timing, you should get vsync period consistent. vsync cannot vary so much.. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, Brijesh Jadav said: Is DSS really configured for discrete sync output? How can I check the configuration and results? thanks.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Wu BoHan said: How can I check the configuration and results? I meant the pinmux, pixel clock etc. are you sure that the pinmux is correct? Can you also probe pixel clock and make sure it is correct? Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu BoHan",
+    "rankPoints" : "315",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6162313",
+    "content" : "Hi, When I tried changing the scan format in chains_common.c. The following is my setting: static Void ChainsCommon_SetDctrlConfig pVInfo->mInfo.scanFormat = SYSTEM_SF_INTERLACED; pVInfo->mInfo.standard = SYSTEM_STD_576I; Assertion occurs during execution: [IPU1-0] 5.807478 s: CAPTURE: Create in progress !!! [IPU1-0] 5.807692 s: CAPTURE: VIP1 Slice1 PortB capture mode is [ 8-bit] !!! [IPU1-0] 5.862044 s: CAPTURE: Create Done !!! [IPU1-0] 5.862441 s: DISPLAY: Create in progress !!! [IPU1-0] 5.862746 s: dispcore/src/vpscore_dss.c @ Line 1412: [IPU1-0] 5.862868 s: Format(interlaced/progressive) conversion is not supported [IPU1-0] 5.862959 s: dispdrv/src/vpsdrv_displayCore.c @ Line 304: [IPU1-0] 5.863020 s: Set DSS parameter failed [IPU1-0] 5.863081 s: Assertion @ Line: 459 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! [IPU1-0] 5.863600 s: Assertion @ Line: 459 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! Assertion points to the following: Int32 DisplayLink_drvDisplayCreate(DisplayLink_Obj *pObj) status = FVID2_control( pObj->displayHndl, IOCTL_VPS_DISP_SET_DSS_PARAMS, &pObj->dssPrms, NULL); What should I do? thanks.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, It looks like your output format is set to interlaced format, but input is in progressive. Could you please make sure to set both of them to interlaced? I think on TDA3x, we had support for setting up output to NTSC/PAL resolution, which are interlaced resolution. Could you please check display settings for these modes in the vision sdk and make similar changes for TDA2x? For TDA3x, on display settings, we can select output to DAC and select the resolution to NTSC/PAL. Entire usecase will then work and output on NTSC/PAL resolution. Regards, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1024368.json

@@ -0,0 +1,151 @@
+{
+  "ticketNumber" : "1024368",
+  "reporterName" : "Wu YiTing",
+  "rankPoints" : "470",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: How to use VIP to receive 576I image?",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TVP5158, TVP5154, TDA2 Hi expert, Our company uses a custom board with SDK0305. The requirement is to receive 720*576I 4CH standard images. Q1:How can I make VIP capture receive 25 frame? If possible, Please provide suggestions for modification. Q2:I saw the 1CH TVP5158 driver in the SDK, Can I use TVP5158 driver to receive TVP5154? If possible, can I change it to 4CH? Q3:I am curious about the 25fps or 50field that Capture will receive?",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi, Wu YiTing said: Q1:How can I make VIP capture receive 25 frame? If possible, Please provide suggestions for modification. fps is controlled by your pixel clock, so as long as pixel clock is correct, VIP would be able to capture 25fps. Wu YiTing said: Q2:I saw the 1CH TVP5158 driver in the SDK, Can I use TVP5158 driver to receive TVP5154? If possible, can I change it to 4CH? Yes, you can, but you would require to bring it up. Wu YiTing said: Q3:I am curious about the 25fps or 50field that Capture will receive? Capture will receive individual fields and so it will also store field and give callbacks on fields capture. Application would have to merge them and create frames out of them. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "fps is controlled by your pixel clock, so as long as pixel clock is correct, VIP would be able to capture 25fps. -> I measured the TVP5154 to be 27MHZ. Is this standard? In fact, we have TP2824 decoder pixcel clock output is 37.125MHZ, can VIP receive it correctly? Yes, you can, but you would require to bring it up. -> I have tried to use TVP5158 driver to receive TVP5154 images but it fails. Can you guide me to achieve it? Capture will receive individual fields and so it will also store field and give callbacks on fields capture. Application would have to merge them and create frames out of them. -> So the Capture driver will merge the fields into Frames, and then send the New data to the Capture link, right? Then I print the Capture link information and see that it should be 25fps, right?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Wu YiTing said: -> I measured the TVP5154 to be 27MHZ. Is this standard? In fact, we have TP2824 decoder pixcel clock output is 37.125MHZ, can VIP receive it correctly? Yes, it should be fine, as long as HS and VS are correct. Wu YiTing said: -> So the Capture driver will merge the fields into Frames, and then send the New data to the Capture link, right? No, driver or link will not merge the fields. It has to be done in the application. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "No, driver or link will not merge the fields. It has to be done in the application. -> Does TI provide an application for merging?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "I have tried to use TVP5158 driver to receive TVP5154 images but it fails. Do I need to modify some VIP settings in these files? I use PROCESSOR_SDK_VISION_03_05_00_00 The following are my setup steps Step1: Select usecase C:\\PROCESSOR_SDK_VISION_03_05_00_00\\vision_sdk\\apps\\src\\rtos\\usecases\\vip_single_cam_view Step2: Make sure that Pinmux is configured correctly Step3: Select CHAINS_CAPTURE_SRC_VIDDEC_TVP5158 Step4: captureOutWidth 720, captureOutHeight 576 Step5: Chain_Create Step6: Chain_Start Step7: Initialize TVP5154 7-1// Write to all decoders 0XFE, 0X0F 7-2// write 0x00 to register 0x7F ==> initialize 5154 0X7F, 0X00 vip_single_cam_view.rar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "This is the result of Capture link to Display link and then through HDMI 720P. Camera -> TVP5154 -> TDA2 -> HDMI pixcel clock 27MHZ Display link only received 1fps Camera -> TP2824 -> TDA2 -> HDMI pixcel clock 74.25MHZ Display link received 50fps and image is cropped Camera to monitor The yellow sticker indicates that the image is cropped after passing through TDA2",
+    "imageList" : [ "Data/input/1024368/png", "Data/input/1024368/png", "Data/input/1024368/jpeg" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "By the way TP2824 hardware: Output BT656. embedded 720*576I",
+    "imageList" : [ "Data/input/1024368/PNG" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Daniel Cheng1",
+    "rankPoints" : "4430",
+    "rankName" : "Genius",
+    "date" : "",
+    "userId" : "/members/6328202",
+    "content" : "Hi Brijesh Could you help to update? Thanks for your kindly help Daniel",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Wu YiTing said: -> Does TI provide an application for merging? No, It has to be done in the application. Wu YiTing said: Do I need to modify some VIP settings in these files? No this should work fine. Just make sure to configure VIP in single channel mode, since this use case might be configuring it in multi-channel mode. Wu YiTing said: Camera -> TVP5154 -> TDA2 -> HDMI pixcel clock 27MHZ Display link only received 1fps Are you configuring VIP in embedded sync format or discrete sync? can you first check if VIP is configured correctly by looking into register? Then check if VIP is detecting size correctly. Then check for fps. fps might be low because your link might.be returning frames in time. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "No, It has to be done in the application. -> I found the use case vip_single_rvc_cam_view_crcvpe VPE seems to be able to field merge this can be achieved? Are you configuring VIP in embedded sync format or discrete sync? can you first check if VIP is configured correctly by looking into register? Then check if VIP is detecting size correctly. Then check for fps. fps might be low because your link might.be returning frames in time. -> I use the default setting of TVP5158, which I think is embedded sync format, i will check the VIP size.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Wu YiTing said: -> I found the use case vip_single_rvc_cam_view_crcvpe VPE seems to be able to field merge this can be achieved? Yes, VPE can be used to convert field to frames, but please note it will make 60field -> 60frames. There is a DeInterlacer module in VPE, which can convert field to frames. Now if you want just 30frames/sec, then you could drop/ignore alternate frames at the output of VPE. Regards, Brijesh",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "How can I check if the Filed image is cropped? I think the size of the 576i field should be 720*288. There will be 50 fields per second. Can I check from the image?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "Yes, VPE can be used to convert field to frames, but please note it will make 60field -> 60frames. There is a DeInterlacer module in VPE, which can convert field to frames. Now if you want just 30frames/sec, then you could drop/ignore alternate frames at the output of VPE. -> Have you implemented field merge with VPE?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Wu YiTing",
+    "rankPoints" : "470",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6461167",
+    "content" : "Hi Brijesh, Please help me understand pInprms->dataFormat, pOutprms->dataFormat, my VIP input format is YUV422I, but why I have to set the following to see the correct color picture \"indata formate = SYSTEM_DF_YUV422P outdata formate = SYSTEM_DF_YUV422I_YUYV\"",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Brijesh Jadav",
+    "rankPoints" : "400895",
+    "rankName" : "TI__Guru****",
+    "date" : "",
+    "userId" : "/members/1838755",
+    "content" : "Hi Wu YiTing, Wu YiTing said: There will be 50 fields per second. Can I check from the image? You could save image and check it out. I dont see any other way. But before that, can you please check if captured image size reported by VIP is correct? Wu YiTing said: -> Have you implemented field merge with VPE? No, please refer to existing usease Wu YiTing said: Please help me understand pInprms->dataFormat, pOutprms->dataFormat, my VIP input format is YUV422I, but why I have to set the following to see the correct color picture \"indata formate = SYSTEM_DF_YUV422P outdata formate = SYSTEM_DF_YUV422I_YUYV\" Input data format here means the format that VIP is receiving data. Here, YUV422P means, it is receiving YUV422 data. Output data format is storage format, so data is stored as YUV422 in UYVY format. Regards, Brijesh",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1024518.json

@@ -0,0 +1,106 @@
+{
+  "ticketNumber" : "1024518",
+  "reporterName" : "Ahmed Anwar",
+  "rankPoints" : "260",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: Mismatch between TIDL host emulation tool and target board TDA2Px EVM File I/O use case",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Hi, I used TIDL import tool to convert a TensorFlow model, then I used the host emulation tool to check the output of the model after conversion. I found that the output is acceptable after quantization. Then, I used TIDL file I/O use case to check the output on the board and compare it to the output of the host emulation tool. However, I find a great mismatch between the two outputs. The output from the target is mostly zeros, which is completely different from the host emulation tool output. I searched on the forum, but did not find a systematic way to debug the cause of this difference. I specify the following parameters in the TIDLCFG.TXT file: inputWidth=128\r\ninputHeight=32\r\ninputFile=IN.bin\r\noutputFile=OUT.bin\r\nnetFileName=NET.bin\r\nparamFileName=PRM.bin Would you please let me know what is the cause of this issue, or how to appropriately debug it ? Thanks, Ahmed Anwar",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi Ahmed Anwar, In the TIDL file I/O use case, which core did you select to run TIDL? Kindly check with both the cores and isolate if this issue is specific to any core (EVE/DSP) ? Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hi Praveen, I checked both cores. The problem is the same whether I choose EVE or DSP. The output is completely different from the host emulation tool output, with the majority of zero values. Thanks, Ahmed Anwar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hi Praveen, I noticed that the output file size from the File I/O use case on TDA2PX EVM is not equal to the output file size from the host emulation tool. The output file size from the host emulation tool = 96 bytes. This size is correct and was expected, as I have 96 values in the output of my model, and if each value is represented by 1 byte, so the output file size should be 96 bytes. When I read this 96 byte file as int8, the output is reasonable, and I was expecting to find the same output with the same size on target. However, the output file size from the File I/O use case = 4.1 KB, which is not equal to the 96 byte file I get from the host emulation tool. Would you please explain how I get different file sizes from the host emulation tool and File I/O use case, given that I use the same model and input files? And if you have any idea about this mismatch problem in general, please let me know. Thanks, Ahmed Anwar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi Ahmed Anwar, You are getting output file size of 4.1KB (which is 128x32) because FILE I/O usecase dumps output considering it as segmentation application, so it writes output data considering input dimension. If your application is not segmentation, then you may need to provide the output dimension to the usecase and dump the actual output of 96 bytes, for this you need to modify the dump code in the usecase and for this modified code please refer to last post in the below thread. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/874558/tda2-ti-vision-sdk---tidl---verifying-that-inceptionv1-works-with-tidl/3240125#3240125 Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hi Praveen, Thank you for your reply. I will try to edit the dumping code in the use case based on the post you provided. Until I modify the code, I have this question, by which I try to figure out if the correct 96 bytes are present within the 4096 bytes or not: Does the 4096 byte output (32 * 128) have the actual 96 output ? When the use case dumps 4096 values, does it dump my actual 96 values (Which are the output of the model) and dumps also other values to complete the 4096 bytes ? If this is the case, I need to understand these points: How can I get the actual 96 byte output of the 4096 bytes ? Is there an offset to start extracting the actual output from ? Are the wrongly dumped bytes (other than the correct 96 bytes) all zeros ? If not, how there values are determined, if the actual model has only 96 bytes output ? Would you please answer my question till I modify the code and test the use case after modification ? Thanks, Ahmed Anwar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hi Praveen, I changed the use case code based on the post you provided, and rebuilt the SDK. The output file size is now correct. However, the output is not correct and does not match the host emulation tool output. Most of the values are zeros, which is completely different from the host emulation tool output. Would you please help me in identifying the cause of this mismatch ? Thanks, Ahmed Anwar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hi Praveen, I also have a question regarding that the File I/O use case is used for segmentation. My application is not segmentation, does this make an issue ? I added the output height and width to the use case code as you said, but the output is not correct. Is it ok to use the File I/O use case with a model which is not used for segmentation ? Thanks, Ahmed Anwar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi Ahemd Anwar, Could you please provide some details about your application. Also, kindly confirm that you had updated \"dmaPrm.srcPitch[0]\" and \"dmaPrm.destPitch[0]\" with outWidth as these can effect the offset in output buffer. Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hi Praveen, My application is classification. I confirm that I updated \"dmaPrm.srcPitch[0]\" and \"dmaPrm.destPitch[0]\" with outWidth. Thanks, Ahmed Anwar",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ahmed Anwar",
+    "rankPoints" : "260",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6638795",
+    "content" : "Hi Praveen, Is there a difference between the way of execution of the host emulation tool and the File I/O use case on target ? I need to understand this, as it is supposed to be the same, and it is supposed to get on target the same output that I get using the host emulation tool. I think that getting good results using the host emulation tool means that the conversion and quantization are done in a good way, and that I can go on with deploying the model to the board. I need to understand if there is differences between the source code that runs the host emulation tool and the File I/O use case, as they produce different results. Thanks, Ahmed Anwar",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1027878.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1027878",
+  "reporterName" : "buaawkp",
+  "rankPoints" : "1345",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2HG: [Opengl] -- the cube usage in fbo",
+  "rankName" : "Expert",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 hi: I have a question about the usage of cubemap in fbo; the simple code as bellow: { glGenFramebuffers(1, &fboID); glBindFramebuffer(GL_FRAMEBUFFER,fboID); glGenTextures(1, &cubemapID); glBindTexture(GL_TEXTURE_CUBE_MAP, cubemapID); for (unsigned int i = 0; i < 6; ++i) { glTexImage2D(GL_TEXTURE_CUBE_MAP_POSITIVE_X + i, 0, GL_RGB, 256, 256, 0, GL_RGB, GL_UNSIGNED_BYTE, nullptr); } glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MIN_FILTER, GL_LINEAR); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MAG_FILTER, GL_LINEAR); glUniform.. //update the uniform variable glViewport(0, 0, 256, 256); for (unsigned int i = 0; i < 6; ++i) { glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_CUBE_MAP_POSITIVE_X + i, cubemapID, 0); if (glCheckFramebufferStatus(GL_FRAMEBUFFER) != GL_FRAMEBUFFER_COMPLETE) { printf(\"glCheckFramebufferStatus error!\\n\"); } glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT); renderCube(); } } when i test the code, it works well on windows, but when i move it to the tda2 platform, the question is comming, sometimes the effiect is black , or is white, or white and black , or other colors, it's change every time. how is this? and how to resolved it? thanks",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, Can you try and see if this works:     // Setup texture for cubemap\r\n    glGenTextures(1, &textureCubeMap);\r\n    char buffer0[CUBEMAP_TEX_LEN * CUBEMAP_TEX_LEN * 6];\r\n\r\n    glBindTexture(GL_TEXTURE_CUBE_MAP, textureCubeMap);\r\n    memset((void *)buffer0, 0x50, CUBEMAP_TEX_LEN*CUBEMAP_TEX_LEN*6);\r\n    for(GLuint i = 0; i < 6; i++)\r\n    {\r\n            glTexImage2D(\r\n                            GL_TEXTURE_CUBE_MAP_POSITIVE_X + i,\r\n                            0, GL_RGBA8, CUBEMAP_TEX_LEN, CUBEMAP_TEX_LEN,\r\n                            0, GL_RGBA, GL_UNSIGNED_BYTE, (char *)buffer0\r\n                        );\r\n    }\r\n\r\n    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MAG_FILTER, GL_LINEAR);\r\n    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MIN_FILTER, GL_LINEAR);\r\n    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE);\r\n    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE);\r\n    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_R, GL_CLAMP_TO_EDGE);\r\n\r\n    // Setup Framebuffer for cubemap\r\n    glGenFramebuffers(1, &fbCubeMap);\r\n    \r\n    \r\n    // Rendering part\r\n    GLint current_fbo;\r\n    glGetIntegerv(GL_FRAMEBUFFER_BINDING, &current_fbo);\r\n    glBindFramebuffer(GL_FRAMEBUFFER, fbCubeMap);\r\n    \r\n    // Render to cubemap\r\n    for (int i = 0; i < 6; i++)\r\n\t{\r\n        glFramebufferTexture2D(GL_FRAMEBUFFER,\r\n\t\t    GL_COLOR_ATTACHMENT0,\r\n\t\t    GL_TEXTURE_CUBE_MAP_POSITIVE_X + i,\r\n\t\t    textureCubeMap,\r\n\t\t    0);\r\n\t    glClear(GL_COLOR_BUFFER_BIT|GL_DEPTH_BUFFER_BIT);\r\n\t    //.... draw/render to cube map surface\r\n\t}\r\n\t\r\n\t// Bind the original frame buffer\r\n\tglBindFramebuffer(GL_FRAMEBUFFER, current_fbo);\r\n\t\r\n\t// Use cubemap texture\r\n\tglBindTexture(GL_TEXTURE_CUBE_MAP, textureCubeMap);\r\n\r\n    //... draw to the final framebuffer using cubemap\r\n    // In the shader code, use samplerCube to sample texture\r\n    // e.g:\r\n    // uniform samplerCube skybox;\r\n    // ...\r\n    // vec4 colorval = texture(skybox, direction);\r\n    \r\n\r\n    \r\n    \r\n\t    \r\n\r\n\r\n\r\n    \r\n\r\n\r\n If it still doesn't work, can you try and use glGetError to check for any errors? Regards Hemant",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1028256.json

@@ -0,0 +1,43 @@
+{
+  "ticketNumber" : "1028256",
+  "reporterName" : "lluo",
+  "rankPoints" : "340",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: Is Reshape/Permute layer supported on TDA2X with CaffeImportTool?",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi ! When convert shufflenetv2 caffemodel to tidl bin/param using REL.TIDL.01.01.03.00, it failed. EEROR LOG: TIDL returned with error code : -1100, refer to interface header file for error code details Error at line: 1578 : in file .\\.\\src\\tidl_tb.c, of function : test_ti_dl_ivison End of config list found ! But I check that reshape layer and permute layer work well in SSD model. So how can I make separate reshape layer and permute layer work ?",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi, Reshape, Permute layers are supported only in the context of SSD network. They are not supported as standalone layers. Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "lluo",
+    "rankPoints" : "340",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/5927174",
+    "content" : "Hi Praveen Thanks for you replay. So currently, channel shuffle can not work on TIDL(both tda2 / 4). These requirements will be supported in the futures?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi, It can work on TDA4 TIDL but not in TDA2 TIDL, please note that both are different code bases and TDA4 can support much more netwroks and frame works compare to TIDL on TDA2 , please try with TIDL on TDA4 (https://www.ti.com/tool/download/PROCESSOR-SDK-RTOS-J721E/08.00.00.12). Thanks, Praveen",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1028549.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1028549",
+  "reporterName" : "Kirollos Henry",
+  "rankPoints" : "90",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: Is there a way to build yocto but not thud on TDA2Px-EVM to build python3 Tensorflow-lite",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello all, I Have TDA2Px-EVM board and I was able to build yocto file system on using this guide: http://software-dl.ti.com/processor-sdk-linux/esd/docs/06_00_00_07/linux/Overview_Building_the_SDK.html I was also able to customize the image as i have added some layers like meta-ros, meta-scipy and I was also able to create custom layer to install and build some libraries, packages and package groups. I was installing some python packages and the changes I made to the image allowed me to install most of the needed python3 packages using pip3. I am currently facing a problem in installing tensorflow or tensorflow-lite when I added meta-tensorflow-lite layer https://github.com/NobuoTsukamoto/meta-tensorflow-lite/ and appended to my image recipe IMAGE_INSTALL += \" python3-tensorflow-lite \" I have got \"ERROR: Layer meta-tensorflow-lite is not compatible with the core layer which only supports these series: thud\" So I am currently facing a problem as processor sdk 6.x are all based on thud and this distro is not supported in the tensorflow-lite meta layer and When I tried to build a different version of processor SDK there was a toolchain error \"ERROR: Failed to parse external Linaro toolchain version from: gcc version 8.3.0 \" as probably the other versions of processor SDK doesn't support \"dra7xx-evm\". My problem shortly is there any way to build yocto file system on TDA2Px-EVM based on another yocto distro rather than thud or is there a way to build and install python3 tensorflow or tensorflow-lite on TDA2Px-EVM using the built and working yocto with this version of processor SDK. Thanks in Advance. Best regards, Kirollos Henry",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Karthik Ramanan",
+    "rankPoints" : "113800",
+    "rankName" : "TI__Guru**",
+    "date" : "",
+    "userId" : "/members/1166748",
+    "content" : "Hi Kirollos, Apologies for the delay in the response to this. Kirollos Henry said: is there any way to build yocto file system on TDA2Px-EVM based on another yocto distro rather than thud The short answer is no, thud is the last release with a completely validated offering with DRA7/TDA2. You will have to take care of the migration at your end. Kirollos Henry said: is there a way to build and install python3 tensorflow or tensorflow-lite on TDA2Px-EVM using the built and working yocto with this version of processor SDK. I dont think anyone in TI has spent time on this problem, therefore we are unable to provide you with any further instructions. Regards Karthik",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1030393.json

@@ -0,0 +1,70 @@
+{
+  "ticketNumber" : "1030393",
+  "reporterName" : "lluo",
+  "rankPoints" : "340",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: Is Conv with no relue supported In TDA2?",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi I get some accuracy problems with caffemodel importing. Here is my steps: a) Use tidl_model_import.out.exe convert regnet.prototxt/caffemodel to tidl_param/bin b) Compare each layer's output : onnx vs trace_dump_idx_wxh.y c) I find the first conv layer(with bn & relu) matched well(error < 1%) d) But conv_layer with no relu(which are inputs of eltwise_layer) cannot match original model layer's outputs I put a snapshot below : conv layers in green rect match, but conv layer without relu in red circle not match. regnet_import.zip So, is relu strictedly demanded to place after conv layer? Or this is just bugs in import tool? I upload my model and tools for analysis.",
+  "imageList" : [ "Data/input/1030393/png" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi, Can you share the import output log to check the issue ? Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "lluo",
+    "rankPoints" : "340",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/5927174",
+    "content" : "Hi Praveen Thanks for your replay! I uploaded LOG.txt. Geroge. 6675.LOG.txt  .\\tidl_model_import.out.exe .\\ONNX_Reg200M_CIFAR\\tidl_import.txt\r\nCaffe Network File : ONNX_Reg200M_CIFAR\\trained\\regnetx200mf_cifar_Relu96.prototxt\r\nCaffe Model File   : ONNX_Reg200M_CIFAR\\trained\\regnetx200mf_cifar_Relu96.caffemodel\r\nTIDL Network File  : ONNX_Reg200M_CIFAR\\model\\tidl_net_reg200cifar_relu96.bin\r\nTIDL Model File    : ONNX_Reg200M_CIFAR\\model\\tidl_param_reg200cifar_relu96.bin\r\nName of the Network : REG200MCIFAR-ONNX\r\nNum Inputs :               1\r\n Num of Layer Detected :  71\r\n  0, TIDL_DataLayer                , data                                      0,  -1 ,  1 ,   x ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  0 ,       0 ,       0 ,       0 ,       0 ,       1 ,       3 ,      32 ,      32 ,         0 ,\r\n  1, TIDL_ConvolutionLayer         , Conv_0                                    1,   1 ,  1 ,   0 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  1 ,       1 ,       3 ,      32 ,      32 ,       1 ,      32 ,      32 ,      32 ,    884736 ,\r\n  2, TIDL_ConvolutionLayer         , Conv_2                                    1,   1 ,  1 ,   1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  2 ,       1 ,      32 ,      32 ,      32 ,       1 ,      24 ,      32 ,      32 ,    786432 ,\r\n  3, TIDL_ConvolutionLayer         , Conv_4                                    1,   1 ,  1 ,   2 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  3 ,       1 ,      24 ,      32 ,      32 ,       1 ,      24 ,      16 ,      16 ,    442368 ,\r\n  4, TIDL_ConvolutionLayer         , Conv_6                                    1,   1 ,  1 ,   3 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  4 ,       1 ,      24 ,      16 ,      16 ,       1 ,      24 ,      16 ,      16 ,    147456 ,\r\n  5, TIDL_ConvolutionLayer         , Conv_7                                    1,   1 ,  1 ,   1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  5 ,       1 ,      32 ,      32 ,      32 ,       1 ,      24 ,      16 ,      16 ,    196608 ,\r\n  6, TIDL_EltWiseLayer             , Add_8                                     1,   2 ,  1 ,   4 ,  5 ,  x ,  x ,  x ,  x ,  x ,  x ,  6 ,       1 ,      24 ,      16 ,      16 ,       1 ,      24 ,      16 ,      16 ,      6144 ,\r\n  7, TIDL_BatchNormLayer           , Relu_9                                    1,   1 ,  1 ,   6 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  7 ,       1 ,      24 ,      16 ,      16 ,       1 ,      24 ,      16 ,      16 ,      6144 ,\r\n  8, TIDL_ConvolutionLayer         , Conv_10                                   1,   1 ,  1 ,   7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  8 ,       1 ,      24 ,      16 ,      16 ,       1 ,      56 ,      16 ,      16 ,    344064 ,\r\n  9, TIDL_ConvolutionLayer         , Conv_12                                   1,   1 ,  1 ,   8 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  9 ,       1 ,      56 ,      16 ,      16 ,       1 ,      56 ,      16 ,      16 ,   1032192 ,\r\n 10, TIDL_ConvolutionLayer         , Conv_14                                   1,   1 ,  1 ,   9 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 10 ,       1 ,      56 ,      16 ,      16 ,       1 ,      56 ,      16 ,      16 ,    802816 ,\r\n 11, TIDL_ConvolutionLayer         , Conv_15                                   1,   1 ,  1 ,   7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 11 ,       1 ,      24 ,      16 ,      16 ,       1 ,      56 ,      16 ,      16 ,    344064 ,\r\n 12, TIDL_EltWiseLayer             , Add_16                                    1,   2 ,  1 ,  10 , 11 ,  x ,  x ,  x ,  x ,  x ,  x , 12 ,       1 ,      56 ,      16 ,      16 ,       1 ,      56 ,      16 ,      16 ,     14336 ,\r\n 13, TIDL_BatchNormLayer           , Relu_17                                   1,   1 ,  1 ,  12 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 13 ,       1 ,      56 ,      16 ,      16 ,       1 ,      56 ,      16 ,      16 ,     14336 ,\r\n 14, TIDL_ConvolutionLayer         , Conv_18                                   1,   1 ,  1 ,  13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 14 ,       1 ,      56 ,      16 ,      16 ,       1 ,     152 ,      16 ,      16 ,   2179072 ,\r\n 15, TIDL_ConvolutionLayer         , Conv_20                                   1,   1 ,  1 ,  14 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 15 ,       1 ,     152 ,      16 ,      16 ,       1 ,     152 ,       8 ,       8 ,    700416 ,\r\n 16, TIDL_ConvolutionLayer         , Conv_22                                   1,   1 ,  1 ,  15 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 16 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,   1478656 ,\r\n 17, TIDL_ConvolutionLayer         , Conv_23                                   1,   1 ,  1 ,  13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 17 ,       1 ,      56 ,      16 ,      16 ,       1 ,     152 ,       8 ,       8 ,    544768 ,\r\n 18, TIDL_EltWiseLayer             , Add_24                                    1,   2 ,  1 ,  16 , 17 ,  x ,  x ,  x ,  x ,  x ,  x , 18 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,      9728 ,\r\n 19, TIDL_BatchNormLayer           , Relu_25                                   1,   1 ,  1 ,  18 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 19 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,      9728 ,\r\n 20, TIDL_ConvolutionLayer         , Conv_26                                   1,   1 ,  1 ,  19 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 20 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,   1478656 ,\r\n 21, TIDL_ConvolutionLayer         , Conv_28                                   1,   1 ,  1 ,  20 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 21 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,    700416 ,\r\n 22, TIDL_ConvolutionLayer         , Conv_30                                   1,   1 ,  1 ,  21 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 22 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,   1478656 ,\r\n 23, TIDL_EltWiseLayer             , Add_31                                    1,   2 ,  1 ,  22 , 19 ,  x ,  x ,  x ,  x ,  x ,  x , 23 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,      9728 ,\r\n 24, TIDL_BatchNormLayer           , Relu_32                                   1,   1 ,  1 ,  23 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 24 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,      9728 ,\r\n 25, TIDL_ConvolutionLayer         , Conv_33                                   1,   1 ,  1 ,  24 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 25 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,   1478656 ,\r\n 26, TIDL_ConvolutionLayer         , Conv_35                                   1,   1 ,  1 ,  25 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 26 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,    700416 ,\r\n 27, TIDL_ConvolutionLayer         , Conv_37                                   1,   1 ,  1 ,  26 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 27 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,   1478656 ,\r\n 28, TIDL_EltWiseLayer             , Add_38                                    1,   2 ,  1 ,  27 , 24 ,  x ,  x ,  x ,  x ,  x ,  x , 28 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,      9728 ,\r\n 29, TIDL_BatchNormLayer           , Relu_39                                   1,   1 ,  1 ,  28 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 29 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,      9728 ,\r\n 30, TIDL_ConvolutionLayer         , Conv_40                                   1,   1 ,  1 ,  29 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 30 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,   1478656 ,\r\n 31, TIDL_ConvolutionLayer         , Conv_42                                   1,   1 ,  1 ,  30 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 31 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,    700416 ,\r\n 32, TIDL_ConvolutionLayer         , Conv_44                                   1,   1 ,  1 ,  31 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 32 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,   1478656 ,\r\n 33, TIDL_EltWiseLayer             , Add_45                                    1,   2 ,  1 ,  32 , 29 ,  x ,  x ,  x ,  x ,  x ,  x , 33 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,      9728 ,\r\n 34, TIDL_BatchNormLayer           , Relu_46                                   1,   1 ,  1 ,  33 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 34 ,       1 ,     152 ,       8 ,       8 ,       1 ,     152 ,       8 ,       8 ,      9728 ,\r\n 35, TIDL_ConvolutionLayer         , Conv_47                                   1,   1 ,  1 ,  34 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 35 ,       1 ,     152 ,       8 ,       8 ,       1 ,     368 ,       8 ,       8 ,   3579904 ,\r\n 36, TIDL_ConvolutionLayer         , Conv_49                                   1,   1 ,  1 ,  35 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 36 ,       1 ,     368 ,       8 ,       8 ,       1 ,     368 ,       4 ,       4 ,    423936 ,\r\n 37, TIDL_ConvolutionLayer         , Conv_51                                   1,   1 ,  1 ,  36 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 37 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 38, TIDL_ConvolutionLayer         , Conv_52                                   1,   1 ,  1 ,  34 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 38 ,       1 ,     152 ,       8 ,       8 ,       1 ,     368 ,       4 ,       4 ,    894976 ,\r\n 39, TIDL_EltWiseLayer             , Add_53                                    1,   2 ,  1 ,  37 , 38 ,  x ,  x ,  x ,  x ,  x ,  x , 39 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 40, TIDL_BatchNormLayer           , Relu_54                                   1,   1 ,  1 ,  39 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 40 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 41, TIDL_ConvolutionLayer         , Conv_55                                   1,   1 ,  1 ,  40 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 41 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 42, TIDL_ConvolutionLayer         , Conv_57                                   1,   1 ,  1 ,  41 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 42 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,    423936 ,\r\n 43, TIDL_ConvolutionLayer         , Conv_59                                   1,   1 ,  1 ,  42 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 43 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 44, TIDL_EltWiseLayer             , Add_60                                    1,   2 ,  1 ,  43 , 40 ,  x ,  x ,  x ,  x ,  x ,  x , 44 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 45, TIDL_BatchNormLayer           , Relu_61                                   1,   1 ,  1 ,  44 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 45 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 46, TIDL_ConvolutionLayer         , Conv_62                                   1,   1 ,  1 ,  45 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 46 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 47, TIDL_ConvolutionLayer         , Conv_64                                   1,   1 ,  1 ,  46 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 47 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,    423936 ,\r\n 48, TIDL_ConvolutionLayer         , Conv_66                                   1,   1 ,  1 ,  47 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 48 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 49, TIDL_EltWiseLayer             , Add_67                                    1,   2 ,  1 ,  48 , 45 ,  x ,  x ,  x ,  x ,  x ,  x , 49 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 50, TIDL_BatchNormLayer           , Relu_68                                   1,   1 ,  1 ,  49 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 50 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 51, TIDL_ConvolutionLayer         , Conv_69                                   1,   1 ,  1 ,  50 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 51 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 52, TIDL_ConvolutionLayer         , Conv_71                                   1,   1 ,  1 ,  51 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 52 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,    423936 ,\r\n 53, TIDL_ConvolutionLayer         , Conv_73                                   1,   1 ,  1 ,  52 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 53 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 54, TIDL_EltWiseLayer             , Add_74                                    1,   2 ,  1 ,  53 , 50 ,  x ,  x ,  x ,  x ,  x ,  x , 54 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 55, TIDL_BatchNormLayer           , Relu_75                                   1,   1 ,  1 ,  54 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 55 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 56, TIDL_ConvolutionLayer         , Conv_76                                   1,   1 ,  1 ,  55 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 56 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 57, TIDL_ConvolutionLayer         , Conv_78                                   1,   1 ,  1 ,  56 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 57 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,    423936 ,\r\n 58, TIDL_ConvolutionLayer         , Conv_80                                   1,   1 ,  1 ,  57 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 58 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 59, TIDL_EltWiseLayer             , Add_81                                    1,   2 ,  1 ,  58 , 55 ,  x ,  x ,  x ,  x ,  x ,  x , 59 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 60, TIDL_BatchNormLayer           , Relu_82                                   1,   1 ,  1 ,  59 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 60 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 61, TIDL_ConvolutionLayer         , Conv_83                                   1,   1 ,  1 ,  60 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 61 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 62, TIDL_ConvolutionLayer         , Conv_85                                   1,   1 ,  1 ,  61 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 62 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,    423936 ,\r\n 63, TIDL_ConvolutionLayer         , Conv_87                                   1,   1 ,  1 ,  62 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 63 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 64, TIDL_EltWiseLayer             , Add_88                                    1,   2 ,  1 ,  63 , 60 ,  x ,  x ,  x ,  x ,  x ,  x , 64 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 65, TIDL_BatchNormLayer           , Relu_89                                   1,   1 ,  1 ,  64 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 65 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 66, TIDL_ConvolutionLayer         , Conv_90                                   1,   1 ,  1 ,  65 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 66 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 67, TIDL_ConvolutionLayer         , Conv_92                                   1,   1 ,  1 ,  66 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 67 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,    423936 ,\r\n 68, TIDL_ConvolutionLayer         , Conv_94                                   1,   1 ,  1 ,  67 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 68 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,   2166784 ,\r\n 69, TIDL_EltWiseLayer             , Add_95                                    1,   2 ,  1 ,  68 , 65 ,  x ,  x ,  x ,  x ,  x ,  x , 69 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\n 70, TIDL_BatchNormLayer           , Relu_96                                   1,   1 ,  1 ,  69 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 70 ,       1 ,     368 ,       4 ,       4 ,       1 ,     368 ,       4 ,       4 ,      5888 ,\r\nTotal Giga Macs : 0.0567\r\n已复制         1 个文件。\r\n\r\nProcessing config file .\\tempDir\\qunat_stats_config.txt !\r\n  0, TIDL_DataLayer                ,  0,  -1 ,  1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  0 ,    0 ,    0 ,    0 ,    0 ,    1 ,    3 ,   32 ,   32 ,\r\n  1, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  0 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  1 ,    1 ,    3 ,   32 ,   32 ,    1 ,   32 ,   32 ,   32 ,\r\n  2, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  2 ,    1 ,   32 ,   32 ,   32 ,    1 ,   24 ,   32 ,   32 ,\r\n  3, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  2 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  3 ,    1 ,   24 ,   32 ,   32 ,    1 ,   24 ,   16 ,   16 ,\r\n  4, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  3 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  4 ,    1 ,   24 ,   16 ,   16 ,    1 ,   24 ,   16 ,   16 ,\r\n  5, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  5 ,    1 ,   32 ,   32 ,   32 ,    1 ,   24 ,   16 ,   16 ,\r\n  6, TIDL_EltWiseLayer             ,  1,   2 ,  1 ,  4 ,  5 ,  x ,  x ,  x ,  x ,  x ,  x ,  6 ,    1 ,   24 ,   16 ,   16 ,    1 ,   24 ,   16 ,   16 ,\r\n  7, TIDL_BatchNormLayer           ,  1,   1 ,  1 ,  6 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  7 ,    1 ,   24 ,   16 ,   16 ,    1 ,   24 ,   16 ,   16 ,\r\n  8, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  8 ,    1 ,   24 ,   16 ,   16 ,    1 ,   56 ,   16 ,   16 ,\r\n  9, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  8 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  9 ,    1 ,   56 ,   16 ,   16 ,    1 ,   56 ,   16 ,   16 ,\r\n 10, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  9 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 10 ,    1 ,   56 ,   16 ,   16 ,    1 ,   56 ,   16 ,   16 ,\r\n 11, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 11 ,    1 ,   24 ,   16 ,   16 ,    1 ,   56 ,   16 ,   16 ,\r\n 12, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 10 , 11 ,  x ,  x ,  x ,  x ,  x ,  x , 12 ,    1 ,   56 ,   16 ,   16 ,    1 ,   56 ,   16 ,   16 ,\r\n 13, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 12 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 13 ,    1 ,   56 ,   16 ,   16 ,    1 ,   56 ,   16 ,   16 ,\r\n 14, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 14 ,    1 ,   56 ,   16 ,   16 ,    1 ,  152 ,   16 ,   16 ,\r\n 15, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 14 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 15 ,    1 ,  152 ,   16 ,   16 ,    1 ,  152 ,    8 ,    8 ,\r\n 16, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 15 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 16 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 17, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 17 ,    1 ,   56 ,   16 ,   16 ,    1 ,  152 ,    8 ,    8 ,\r\n 18, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 16 , 17 ,  x ,  x ,  x ,  x ,  x ,  x , 18 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 19, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 18 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 19 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 20, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 19 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 20 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 21, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 20 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 21 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 22, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 21 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 22 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 23, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 22 , 19 ,  x ,  x ,  x ,  x ,  x ,  x , 23 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 24, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 23 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 24 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 25, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 24 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 25 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 26, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 25 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 26 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 27, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 26 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 27 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 28, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 27 , 24 ,  x ,  x ,  x ,  x ,  x ,  x , 28 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 29, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 28 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 29 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 30, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 29 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 30 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 31, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 30 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 31 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 32, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 31 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 32 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 33, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 32 , 29 ,  x ,  x ,  x ,  x ,  x ,  x , 33 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 34, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 33 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 34 ,    1 ,  152 ,    8 ,    8 ,    1 ,  152 ,    8 ,    8 ,\r\n 35, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 34 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 35 ,    1 ,  152 ,    8 ,    8 ,    1 ,  368 ,    8 ,    8 ,\r\n 36, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 35 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 36 ,    1 ,  368 ,    8 ,    8 ,    1 ,  368 ,    4 ,    4 ,\r\n 37, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 36 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 37 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 38, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 34 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 38 ,    1 ,  152 ,    8 ,    8 ,    1 ,  368 ,    4 ,    4 ,\r\n 39, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 37 , 38 ,  x ,  x ,  x ,  x ,  x ,  x , 39 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 40, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 39 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 40 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 41, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 40 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 41 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 42, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 41 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 42 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 43, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 42 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 43 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 44, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 43 , 40 ,  x ,  x ,  x ,  x ,  x ,  x , 44 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 45, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 44 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 45 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 46, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 45 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 46 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 47, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 46 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 47 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 48, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 47 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 48 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 49, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 48 , 45 ,  x ,  x ,  x ,  x ,  x ,  x , 49 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 50, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 49 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 50 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 51, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 50 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 51 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 52, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 51 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 52 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 53, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 52 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 53 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 54, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 53 , 50 ,  x ,  x ,  x ,  x ,  x ,  x , 54 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 55, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 54 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 55 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 56, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 55 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 56 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 57, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 56 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 57 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 58, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 57 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 58 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 59, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 58 , 55 ,  x ,  x ,  x ,  x ,  x ,  x , 59 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 60, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 59 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 60 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 61, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 60 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 61 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 62, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 61 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 62 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 63, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 62 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 63 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 64, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 63 , 60 ,  x ,  x ,  x ,  x ,  x ,  x , 64 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 65, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 64 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 65 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 66, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 65 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 66 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 67, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 66 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 67 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 68, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 67 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 68 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 69, TIDL_EltWiseLayer             ,  1,   2 ,  1 , 68 , 65 ,  x ,  x ,  x ,  x ,  x ,  x , 69 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 70, TIDL_BatchNormLayer           ,  1,   1 ,  1 , 69 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 70 ,    1 ,  368 ,    4 ,    4 ,    1 ,  368 ,    4 ,    4 ,\r\n 71, TIDL_DataLayer                ,  0,   1 , -1 , 70 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  0 ,    1 ,  368 ,    4 ,    4 ,    0 ,    0 ,    0 ,    0 ,\r\nLayer ID    ,inBlkWidth  ,inBlkHeight ,inBlkPitch  ,outBlkWidth ,outBlkHeight,outBlkPitch ,numInChs    ,numOutChs   ,numProcInChs,numLclInChs ,numLclOutChs,numProcItrs ,numAccItrs  ,numHorBlock ,numVerBlock ,inBlkChPitch,outBlkChPitc,alignOrNot\r\n      1           40           34           40           32           32           32            3           32            3            1            8            1            3            1            1         1360         1024            1\r\n      2           32           32           32           32           32           32           32           24           32            7            8            1            5            1            1         1024         1024            1\r\n      3           40           36           40           16           16           16            8            8            8            4            8            1            2            1            1         1440          256            1\r\n      4           16           16           16           16           16           16           24           24           24            8            8            1            3            1            1          256          256            1\r\n      5           32           32           32           16           16           16           32           24           32            7            8            1            5            1            1         1024          256            1\r\n      8           16           16           16           16           16           16           24           56           24            8            8            1            3            1            1          256          256            1\r\n      9           24           18           24           16           16           16            8            8            8            4            8            1            2            1            1          432          256            1\r\n     10           16           16           16           16           16           16           56           56           56            8            8            1            7            1            1          256          256            1\r\n     11           16           16           16           16           16           16           24           56           24            8            8            1            3            1            1          256          256            1\r\n     14           16           16           16           16           16           16           56          152           56            8            8            1            7            1            1          256          256            1\r\n     15           40           20           40           16            8           16            8            8            8            4            8            1            2            1            1          800          128            1\r\n     16           16            8           16           16            8           16          152          152          152            8            8            1           19            1            1          128          128            1\r\n     17           32           16           32           16            8           16           56          152           56            8            8            1            7            1            1          512          128            1\r\n     20           16            8           16      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          16            8            8            8            4            8            1            2            1            1          240          128            1\r\n     27           16            8           16           16            8           16          152          152          152            8            8            1           19            1            1          128          128            1\r\n     30           16            8           16           16            8           16          152          152          152            8            8            1           19            1            1          128          128            1\r\n     31           24           10           24           16            8           16            8            8            8            4            8            1            2            1            1          240          128            1\r\n     32           16            8           16           16            8           16          152          152          152            8            8            1           19            1            1          128          128            1\r\n     35           16            8           16           16            8           16          152          368          152            8            8            1           19            1            1          128          128            1\r\n     36           40           12           40           16            4           16            8            8            8            4            8            1            2            1            1          480           64            1\r\n     37           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     38           32            8           32           16            4           16          152          368          152            8            8            1           19            1            1          256           64            1\r\n     41           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     42           24            6           24           16            4           16            8            8            8            4            8            1            2            1            1          144           64            1\r\n     43           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     46           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     47           24            6           24           16            4           16            8            8            8            4            8            1            2            1            1          144           64            1\r\n     48           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     51           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     52           24            6           24           16            4           16            8            8            8            4            8            1            2            1            1          144           64            1\r\n     53           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     56           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     57           24            6           24           16            4           16            8            8            8            4            8            1            2            1            1          144           64            1\r\n     58           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     61           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     62           24            6           24           16            4           16            8            8            8            4            8            1            2            1            1          144           64            1\r\n     63           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     66           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n     67           24            6           24           16            4           16            8            8            8            4            8            1            2            1            1          144           64            1\r\n     68           16            4           16           16            4           16          368          368          368            8            8            1           46            1            1           64           64            1\r\n\r\nProcessing Frame Number : 0\r\n\r\n Layer    1 : Out Q :      239 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.88,     1.17, Sparsity : -32.41\r\n Layer    2 : Out Q :      324 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.79,     0.88, Sparsity : -12.50\r\n Layer    3 : Out Q :      212 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.44,     0.44, Sparsity :   0.00\r\n Layer    4 : Out Q :       95 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.15,     0.15, Sparsity :   0.00\r\n Layer    5 : Out Q :      142 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.20,     0.22, Sparsity : -12.50\r\n Layer    6 : Out Q :       87 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer    7 : Out Q :      175 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer    8 : Out Q :      452 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.34,     0.34, Sparsity :   0.00\r\n Layer    9 : Out Q :      544 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.03,     1.03, Sparsity :   0.00\r\n Layer   10 : Out Q :      239 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.80,     0.80, Sparsity :   0.00\r\n Layer   11 : Out Q :      148 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.34,     0.34, Sparsity :   0.00\r\n Layer   12 : Out Q :      139 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.03,     0.03, Sparsity :   0.00\r\n Layer   13 : Out Q :      279 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   14 : Out Q :      512 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.18,     2.18, Sparsity :   0.00\r\n Layer   15 : Out Q :      570 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.70,     0.70, Sparsity :   0.00\r\n Layer   16 : Out Q :      236 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.48,     1.48, Sparsity :   0.00\r\n Layer   17 : Out Q :      235 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.54,     0.54, Sparsity :   0.00\r\n Layer   18 : Out Q :      124 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.02,     0.02, Sparsity :   0.00\r\n Layer   19 : Out Q :      249 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   20 : Out Q :      621 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.48,     1.48, Sparsity :   0.00\r\n Layer   21 : Out Q :      670 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.70,     0.70, Sparsity :   0.00\r\n Layer   22 : Out Q :      267 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.48,     1.48, Sparsity :   0.00\r\n Layer   23 : Out Q :      131 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.02,     0.02, Sparsity :   0.00\r\n Layer   24 : Out Q :      263 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   25 : Out Q :      680 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.48,     1.48, Sparsity :   0.00\r\n Layer   26 : Out Q :      271 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.70,     0.70, Sparsity :   0.00\r\n Layer   27 : Out Q :      224 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.48,     1.48, Sparsity :   0.00\r\n Layer   28 : Out Q :      158 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.02,     0.02, Sparsity :   0.00\r\n Layer   29 : Out Q :      317 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   30 : Out Q :      884 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.48,     1.48, Sparsity :   0.00\r\n Layer   31 : Out Q :      665 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.70,     0.70, Sparsity :   0.00\r\n Layer   32 : Out Q :      556 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.48,     1.48, Sparsity :   0.00\r\n Layer   33 : Out Q :      150 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.02,     0.02, Sparsity :   0.00\r\n Layer   34 : Out Q :      301 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   35 : Out Q :      870 , TIDL_ConvolutionLayer, PASSED  #MMACs =     3.58,     3.58, Sparsity :   0.00\r\n Layer   36 : Out Q :      409 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.42,     0.42, Sparsity :   0.00\r\n Layer   37 : Out Q :      230 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   38 : Out Q :      199 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.89,     0.89, Sparsity :   0.00\r\n Layer   39 : Out Q :      175 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   40 : Out Q :      351 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   41 : Out Q :     1196 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   42 : Out Q :      483 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.42,     0.42, Sparsity :   0.00\r\n Layer   43 : Out Q :      220 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   44 : Out Q :      158 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   45 : Out Q :      320 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   46 : Out Q :     1105 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   47 : Out Q :      459 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.42,     0.42, Sparsity :   0.00\r\n Layer   48 : Out Q :      137 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   49 : Out Q :      136 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   50 : Out Q :      287 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   51 : Out Q :     1024 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   52 : Out Q :      631 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.42,     0.42, Sparsity :   0.00\r\n Layer   53 : Out Q :      178 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   54 : Out Q :      109 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   55 : Out Q :      219 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   56 : Out Q :     1488 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   57 : Out Q :      450 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.42,     0.42, Sparsity :   0.00\r\n Layer   58 : Out Q :      143 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   59 : Out Q :      106 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   60 : Out Q :      213 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   61 : Out Q :     1198 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   62 : Out Q :      556 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.42,     0.42, Sparsity :   0.00\r\n Layer   63 : Out Q :      150 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   64 : Out Q :      102 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   65 : Out Q :      205 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   66 : Out Q :     1259 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   67 : Out Q :      749 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.42,     0.42, Sparsity :   0.00\r\n Layer   68 : Out Q :      181 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.17,     2.17, Sparsity :   0.00\r\n Layer   69 : Out Q :      103 , TIDL_EltWiseLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00\r\n Layer   70 : Out Q :      207 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "lluo",
+    "rankPoints" : "340",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/5927174",
+    "content" : "Hi Praveen Is there any updates? lluo",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi IIuo, I have looked at the log you shared, it looks okay to me, this configurations is supported on TDA2. Please follow steps mentioned in section 3.8 (Matching TIDL inference result) in the TIDL user guide. BTW, what is the TIDL release version that you are using? Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "lluo",
+    "rankPoints" : "340",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/5927174",
+    "content" : "Hi Praveen I have been using REL.TIDL.01.01.03.00 . And the model & tools has been uploaded in regnet_import.zip. I will follow user guide to check my model on REL.TIDL.01.02.00.00 later.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi, Please check with REL.TIDL.01.02.00.00 and let us know. Thanks, Praveen",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1030453.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1030453",
+  "reporterName" : "Chieh Hung Chuang",
+  "rankPoints" : "110",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2EG-17: Can a thread share works to dual core?",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2EG-17 Hello this article: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/692229/linux-tda2-hao-can-i-use-2-a15 said that \"You can think as a single A15 core with CPU clock/frequency doubled\" for dual core. But this article: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/862271/tda2hg-why-the-a15-usage-just-50-can-not-up-to-90 said one thread can only run in one core. So it means multi-threads will be separated to dual core automatically, but one thread can't. Is it? Thanks. BR, Jeff",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Keerthy J",
+    "rankPoints" : "132000",
+    "rankName" : "TI__Guru***",
+    "date" : "",
+    "userId" : "/members/1025801",
+    "content" : "Jeff, One thread can be scheduled only on one CPU. - Keerthy",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1030791.json

@@ -0,0 +1,43 @@
+{
+  "ticketNumber" : "1030791",
+  "reporterName" : "YuMei Hung",
+  "rankPoints" : "80",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: PROCESSOR_SDK_VISION_03_05 tidl_OD usecase layer limitations ?",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Hi I tried to use tidl_model_import.out to get bin file. I used stats_tool_out.bin and trace_dump_0_512x512.y file to check test image detection result. Test image showed model can detect object. test image detection result: But I ran on tdasx, it cannot detect any object. I suspect tdasx cannot run too many layers model. The number of layersGroupId are 157 and number of parameters are 3.5M. Do tdasx have any limitations about layers or parameters count? thanks yumei",
+  "imageList" : [ "Data/input/1030791/png" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi Yumei, Below are the SSD limitations listed in the TIDL datasheet : – Only Caffe-Jacinto based SSD network is validated. – Reshape, Permute layers are supported only in the context of SSD network. – “share_location” has to be true – Tested with 4 and 5 heads. – SaveOutputParameter is ignored in TIDL inference. – code_type is only tested with CENTER_SIZE. Please try the suggestions mentioned in the below thread in OD use case to get the detections in the output : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/689617/tda2-how-to-run-ssd-based-tidl-od-use-case-in-vision-sdk-with-pre-trained-model Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "YuMei Hung",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6475547",
+    "content" : "Hi Praveen I confused about Tested with 4 and 5 heads. Did it mean about 4 and 5 anchor box result? Thanks, yumei",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Yes",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1032151.json

@@ -0,0 +1,43 @@
+{
+  "ticketNumber" : "1032151",
+  "reporterName" : "lluo",
+  "rankPoints" : "340",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2PXEVM: How can I extract two CNN output tensors on TIDL (TDA2)",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi sir! My network have two (maybe more) output layers (CxHxW) : Cx56x56 & Cx28x28. How can I get two outputs from TDIL?",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi IIuo, Sorry for the delay. This is not supported in TIDL on TDA2. Thanks, Praveen",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "lluo",
+    "rankPoints" : "340",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/5927174",
+    "content" : "Hi Praveen I proposed a method to solve this problem ： using Transpose Conv and Concat. Step 1. I add a Transposed Conv layer with 4x4 kernel, stride 2 to the small size layer (for upsampling : Cx28x28 -> Cx56x56) Step 2. I fill filter manually to make Transposed Conv layer working as insert 0 between original output elements [e11 e12 -> [ e11 0 e12 0 e21 e22] 0 0 0 0 e21 0 e22 0 0 0 0 0 ] Step 3. I use Concat layer to get my output tensor : 2Cx56x56 So I can simply add stride =1 / 2 to decode different output tensor. Those works have been tested on Caffe. Hope that can help others.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Thanks for sharing.",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1032376.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1032376",
+  "reporterName" : "Pierre Hsieh",
+  "rankPoints" : "875",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SG: TDA2_Crash_PVR_K_and_Kerne",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Hi Sir: Our company has a TDA2 product. Now the system will crash. The attachment is the log when the crash. Is there any direction to solve the problem? The product in this problem has the function of using MLO to perform DDR tests. There is no problem with the DDR test at present. The same firmware does not have this problem with other hardware. Is there any way to test MMU units? 0880.Crash_Log.txt  [HOST] [IPU2  ]    822.653327 s: [CAMERATASK]Front CAM(PCB ID 0) recover from reset!\r\n\r\n[  820.074848] PVR_K:(Error): SGXOSTimer() detected SGX lockup (0x80f tasks)\r\n[  820.082059] PVR_K: HWRecoveryResetSGX: SGX Hardware Recovery triggered\r\n[  820.089034] PVR_K: SGX debug (SGX_DDK sgxddk MAIN@3699939)\r\n[  820.094942] PVR_K:(Error): SGX Register Base Address (Linear):   0xf3640000\r\n[  820.102134] PVR_K:(Error): SGX Register Base Address (Physical): 0x56000000\r\n[  820.109550] PVR_K: Running SGXREG Debug Scripts:\r\n[  820.114371] PVR_K: (HYD)\r\n[  820.117285] PVR_K: \t(SGXREG) 0x00004000 : 0x00000001\r\n[  820.122519] PVR_K: \t(SGXREG) 0x00004004 : 0x0000000A\r\n[  820.127886] PVR_K: \t(SGXREG) 0x00004008 : 0x0000000F\r\n[  820.133110] PVR_K: \t(SGXREG) 0x00004024 : 0x00000005\r\n[  820.138473] PVR_K: \t(SGXREG) 0x00004118 : 0x00000018\r\n[  820.143707] PVR_K: \t(SGXREG) 0x0000412C : 0x20000000\r\n[  820.149071] PVR_K: \t(SGXREG) 0x00004404 : 0x00000000\r\n[  820.154305] PVR_K: \t(SGXREG) 0x00004C04 : 0x00080000\r\n[  820.159670] PVR_K: \t(SGXREG) 0x00004C08 : 0x00000000\r\n[  820.164981] PVR_K: \t(SGXREG) 0x00004C74 : 0x00000000\r\n[  820.170239] PVR_K: \t(SGXREG) 0x00004C78 : 0x00000000\r\n[  820.175571] PVR_K: \t(SGXREG) 0x00004CA8 : 0x00000000\r\n[  820.180851] PVR_K: (P0)\r\n[  820.183524] PVR_K: \t(SGXREG) 0x00008000 : 0x002AAAAA\r\n[  820.188904] PVR_K: \t(SGXREG) 0x00008004 : 0x0A8A8AAA\r\n[  820.194107] PVR_K: \t(SGXREG) 0x00008008 : 0x0102AA87\r\n[  820.199472] PVR_K: \t(SGXREG) 0x00008118 : 0x000000A8\r\n[  820.204657] PVR_K: \t(SGXREG) 0x0000812C : 0x243C2F80\r\n [HOST] [IPU2  ]    822.863630 s: src/bsp_deviceI2c.c @ Line 667[  820.210480] PVR_K: \t(SGXREG) 0x000084E4 : 0x00062014\r\n: \r\n\r\n [HOST] [IPU2  ]    822.863722 s:  I2C3: DEV 0x3c: ERROR !![  820.220562] PVR_K: \t(SGXREG) 0x00008658 : 0x00000000\r\n! \r\n\r\n [HOST] [IPU2  ]    822.863813 s: src/bsp_deviceI2c.c @ Lin[  820.231193] PVR_K: \t(SGXREG) 0x00008A74 : 0x0E208200\r\ne 689: \r\n\r\n [HOST] [IPU2  ]    822.863905 s:  I2C3: Error timeout[  820.241685] PVR_K: \t(SGXREG) 0x00008BA4 : 0x00000001\r\n 0 ms!!!\r\n\r\n [HOST] [IPU2  ]    822.863996 s: Err!!  ,oToHal_I2c_[  820.252317] PVR_K: \t(SGXREG) 0x00008C04 : 0x000D2000\r\nWrite @ Line 80: \r\n\r\n [HOST] [IPU2  ]    822.864179 s: AddrSize i[  820.262838] PVR_K: \t(SGXREG) 0x00008C08 : 0xF15A6010\r\ns 0, regValue= 0x09, 0x01, ...\r\n\r\n [HOST] [IPU2  ]    822.864271 [  820.273492] PVR_K: \t(SGXREG) 0x00008C74 : 0x00000000\r\ns: Err!!  ,oToHal_I2c_Write @ Line 145: \r\n\r\n [HOST] [IPU2  ]    8[  820.283996] PVR_K: \t(SGXREG) 0x00008C78 : 0x00000007\r\n22.864362 s: oToHal_I2c_Write Fail\r\n\r\n [HOST] [IPU2  ]    822.864[  820.294648] PVR_K: \t(SGXREG) 0x00008CB4 : 0x00000000\r\n850 s: src/bsp_deviceI2c.c @ Line 478: \r\n\r\n [HOST] [IPU2  ]    82[  820.305156] PVR_K: \t(SGXREG) 0x00008E04 : 0x00000000\r\n2.864942 s:  I2C3: DEV 0x3c: RD ERROR !!!\r\n\r\n [HOST] [IPU2  ]    [  820.315793] PVR_K: \t(SGXREG) 0x00008624 : 0x00000000\r\n822.865033 s: src/bsp_deviceI2c.c @ Line 504: \r\n\r\n [HOST] [IPU2  [  820.326290] PVR_K: \t(SGXREG) 0x00008628 : 0x00000000\r\n]    822.865186 s:  I2C3: Error timeout 1 ms!!!\r\n\r\n [HOST] [IPU2 [  820.336968] PVR_K: \t(SGXREG) 0x00008630 : 0x00000000\r\n ]    822.865277 s: Err!!  ,oToHal_I2c_Read @ Line 230: \r\n\r\n [HOS[  820.347442] PVR_K: \t(SGXREG) 0x00008664 : 0x00000000\r\nT] [IPU2  ]    822.865399 s: AddrSize is 0, regValue= 0x09, 0x01[  820.358094] PVR_K: \t(SGXREG) 0x00008734 : 0x00000000\r\n, ...\r\n\r\n [HOST] [IPU2  ]    822.865460 s: Err!!  ,oToHal_I2c_Rea[  820.368598] PVR_K: \t(SGXREG) 0x00008AA4 : 0xAAAAAAAA\r\nd @ Line 311: \r\n\r\n [HOST] [IPU2  ]    822.865552 s: oToHal_I2c_Re[  820.379257] PVR_K: \t(SGXREG) 0x00008AA8 : 0xAAAAAAAA\r\nad Fail\r\n\r\n [HOST] [IPU2  ]    822.865613 s: Error Stauts Code is[  820.389782] PVR_K: \t(SGXREG) 0x00008B08 : 0x0001C8E5\r\n 1, Cal checksum = 23, read checksum = 0\r\n\r\n [HOST] [IPU2  ]    8[  820.400419] PVR_K: \t(SGXREG) 0x00008B14 : 0x0000D88A\r\n22.865704 s: ERROR: _oToDevice_Isx019_GET_VERSIONMODEL : -1\r\n\r\n[  820.411280] PVR_K: \t(SGXREG) 0x00008B0C : 0x0001C1C2\r\n [HOST] [IPU2  ]    823.065698 s: src/bsp_deviceI2c.c @ Line 667[  820.421434] PVR_K: \t(SGXREG) 0x00008B18 : 0x0001A54E\r\n: \r\n\r\n [HOST] [IPU2  ]    823.065790 s:  I2C3: DEV 0x3c: ERROR !![  820.431905] PVR_K: \t(SGXREG) 0x00008B10 : 0x0001080F\r\n! \r\n\r\n [HOST] [IPU2  ]    823.065881 s: src/bsp_deviceI2c.c @ Lin[  820.442567] PVR_K: \t(SGXREG) 0x00008B1C : 0x00010000\r\ne 689: \r\n\r\n [HOST] [IPU2  ]    823.065942 s:  I2C3: Error timeout[  820.453056] PVR_K: \t(SGXREG) 0x00008B80 : 0xAAAAAAAA\r\n 0 ms!!!\r\n\r\n [HOST] [IPU2  ]    823.066034 s: Err!!  ,oToHal_I2c_[  820.463741] PVR_K: \t(SGXREG) 0x00008B84 : 0xAAAAAAAA\r\nWrite @ Line 80: \r\n\r\n [HOST] [IPU2  ]    823.066186 s: AddrSize i[  820.474208] PVR_K: \t(SGXREG) 0x00008B88 : 0x0001D6C8\r\ns 0, regValue= 0x09, 0x01, ...\r\n\r\n [HOST] [IPU2  ]    823.066278 [  820.484909] PVR_K: \t(SGXREG) 0x00008B94 : 0x0000DE05\r\ns: Err!!  ,oToHal_I2c_Write @ Line 145: \r\n\r\n [HOST] [IPU2  ]    8[  820.495366] PVR_K: \t(SGXREG) 0x00008B8C : 0x0001A4E3\r\n23.066369 s: oToHal_I2c_Write Fail\r\n\r\n [HOST] [IPU2  ]    823.066[  820.506086] PVR_K: \t(SGXREG) 0x00008B98 : 0x0001A4C4\r\n857 s: src/bsp_deviceI2c.c @ Line 478: \r\n\r\n [HOST] [IPU2  ]    82[  820.516525] PVR_K: \t(SGXREG) 0x00008B90 : 0x00010000\r\n3.066949 s:  I2C3: DEV 0x3c: RD ERROR !!!\r\n\r\n [HOST] [IPU2  ]    [  820.527184] PVR_K: \t(SGXREG) 0x00008B9C : 0x00010000\r\n823.067040 s: src/bsp_deviceI2c.c @ Line 504: \r\n\r\n [HOST] [IPU2  [  820.537677] PVR_K: (P1)\r\n]    823.067193 s:  I2C3: Error timeout 1 ms!!!\r\n\r\n [HOST] [IPU2 [  820.545773] PVR_K: \t(SGXREG) 0x0000C000 : 0x002AAAAA\r\n ]    823.067284 s: Err!!  ,oToHal_I2c_Read @ Line 230: \r\n\r\n [HOS[  820.556307] PVR_K: \t(SGXREG) 0x0000C004 : 0x0A8A8AAA\r\nT] [IPU2  ]    823.067376 s: AddrSize is 0, regValue= 0x09, 0x01[  820.566964] PVR_K: \t(SGXREG) 0x0000C008 : 0x01000001\r\n, ...\r\n\r\n [HOST] [IPU2  ]    823.067467 s: Err!!  ,oToHal_I2c_Rea[  820.577459] PVR_K: \t(SGXREG) 0x0000C118 : 0x000000A8\r\nd @ Line 311: \r\n\r\n [HOST] [IPU2  ]    823.067559 s: oToHal_I2c_Re[  820.588162] PVR_K: \t(SGXREG) 0x0000C12C : 0x043C2F80\r\nad Fail\r\n\r\n [HOST] [IPU2  ]    823.067589 s: Error Stauts Code is[  820.598628] PVR_K: \t(SGXREG) 0x0000C4E4 : 0x00052C16\r\n 1, Cal checksum = 23, read checksum = 0\r\n\r\n [HOST] [IPU2  ]    8[  820.609386] PVR_K: \t(SGXREG) 0x0000C658 : 0x00000000\r\n23.067711 s: ERROR: _oToDevice_Isx019_GET_VERSIONMODEL : -1\r\n\r\n [[  820.620075] PVR_K: \t(SGXREG) 0x0000CA74 : 0x0E208200\r\nHOST] [IPU2  ]    823.267705 s: src/bsp_deviceI2c.c @ Line 667: [  820.630453] PVR_K: \t(SGXREG) 0x0000CBA4 : 0x00000001\r\n\r\n\r\n [HOST] [IPU2  ]    823.267797 s:  I2C3: DEV 0x3c: ERROR !!! [  820.640940] PVR_K: \t(SGXREG) 0x0000CC04 : 0x00080000\r\n\r\n\r\n [HOST] [IPU2  ]    823.267888 s: src/bsp_deviceI2c.c @ Line [  820.651593] PVR_K: \t(SGXREG) 0x0000CC08 : 0x00000000\r\n689: \r\n\r\n [HOST] [IPU2  ]    823.267980 s:  I2C3: Error timeout 0[  820.662087] PVR_K: \t(SGXREG) 0x0000CC74 : 0x00000000\r\n ms!!!\r\n\r\n [HOST] [IPU2  ]    823.268071 s: Err!!  ,oToHal_I2c_Wr[  820.672792] PVR_K: \t(SGXREG) 0x0000CC78 : 0x00000007\r\nite @ Line 80: \r\n\r\n [HOST] [IPU2  ]    823.268224 s: AddrSize is [  820.683270] PVR_K: \t(SGXREG) 0x0000CCB4 : 0x00000000\r\n0, regValue= 0x09, 0x01, ...\r\n\r\n [HOST] [IPU2  ]    823.268315 s:[  820.693908] PVR_K: \t(SGXREG) 0x0000CE04 : 0x00000000\r\n Err!!  ,oToHal_I2c_Write @ Line 145: \r\n\r\n [HOST] [IPU2  ]    823[  820.704404] PVR_K: \t(SGXREG) 0x0000C624 : 0x00000000\r\n.268376 s: oToHal_I2c_Write Fail\r\n\r\n [HOST] [IPU2  ]    823.26889[  820.715119] PVR_K: \t(SGXREG) 0x0000C628 : 0x00000000\r\n5 s: src/bsp_deviceI2c.c @ Line 478: \r\n\r\n [HOST] [IPU2  ]    823.[  820.725567] PVR_K: \t(SGXREG) 0x0000C630 : 0x00000000\r\n268986 s:  I2C3: DEV 0x3c: RD ERROR !!!\r\n\r\n [HOST] [IPU2  ]    82[  820.736218] PVR_K: \t(SGXREG) 0x0000C664 : 0x00000000\r\n3.269352 s: src/bsp_deviceI2c.c @ Line 504: \r\n\r\n [HOST] [IPU2  ] [  820.746720] PVR_K: \t(SGXREG) 0x0000C734 : 0x00000000\r\n   823.269474 s:  I2C3: Error timeout 1 ms!!!\r\n\r\n [HOST] [IPU2  ][  820.757372] PVR_K: \t(SGXREG) 0x0000CAA4 : 0xAAAAAAAA\r\n    823.269566 s: Err!!  ,oToHal_I2c_Read @ Line 230: \r\n\r\n [HOST][  820.767868] PVR_K: \t(SGXREG) 0x0000CAA8 : 0xAAAAAAAA\r\n [IPU2  ]    823.269627 s: AddrSize is 0, regValue= 0x09, 0x01, [  820.778544] PVR_K: \t(SGXREG) 0x0000CB08 : 0x000100E4\r\n...\r\n\r\n [HOST] [IPU2  ]    823.269718 s: Err!!  ,oToHal_I2c_Read [  820.789058] PVR_K: \t(SGXREG) 0x0000CB14 : 0x000110C8\r\n@ Line 311: \r\n\r\n [HOST] [IPU2  ]    823.269810 s: oToHal_I2c_Read[  820.799689] PVR_K: \t(SGXREG) 0x0000CB0C : 0x0001C246\r\n Fail\r\n\r\n [HOST] [IPU2  ]    823.269871 s: Error Stauts Code is 1[  820.810187] PVR_K: \t(SGXREG) 0x0000CB18 : 0x0001A570\r\n, Cal checksum = 23, read checksum = 0\r\n\r\n [HOST] [IPU2  ]    823[  820.820879] PVR_K: \t(SGXREG) 0x0000CB10 : 0x00010000\r\n.269962 s: ERROR: _oToDevice_Isx019_GET_VERSIONMODEL : -1\r\n\r\n [HO[  820.831341] PVR_K: \t(SGXREG) 0x0000CB1C : 0x00010000\r\nST] [IPU2  ]    823.270054 s: [CAMERATASK]Get Left CAM(PCB ID 3)[  820.842002] PVR_K: \t(SGXREG) 0x0000CB80 : 0xAAAAAAAA\r\n Ver string failed but image is ok!\r\n\r\n[  820.852489] PVR_K: \t(SGXREG) 0x0000CB84 : 0xAAAAAAAA\r\n[  820.860854] PVR_K: \t(SGXREG) 0x0000CB88 : 0x000110A5\r\n[  820.866459] PVR_K: \t(SGXREG) 0x0000CB94 : 0x00011A99\r\n[  820.871619] PVR_K: \t(SGXREG) 0x0000CB8C : 0x0001A548\r\n[  820.876987] PVR_K: \t(SGXREG) 0x0000CB98 : 0x0001A56C\r\n[  820.882181] PVR_K: \t(SGXREG) 0x0000CB90 : 0x00010000\r\n[  820.887424] PVR_K: \t(SGXREG) 0x0000CB9C : 0x00010000\r\n[  820.892480] PVR_K: SGX Register Dump:\r\n[  820.896269] PVR_K: (P0) EUR_CR_CORE_ID:          01191201\r\n[  820.901721] PVR_K: (P0) EUR_CR_CORE_REVISION:    00010106\r\n[  820.907249] PVR_K: (P0) EUR_CR_EVENT_STATUS:     243C2F80\r\n[  820.912702] PVR_K: (P0) EUR_CR_EVENT_STATUS2:    000000A8\r\n[  820.918249] PVR_K: (P0) EUR_CR_BIF_CTRL:         00000000\r\n[  820.923701] PVR_K: (P0) EUR_CR_BIF_BANK0:        00000007\r\n[  820.929254] PVR_K: (P0) EUR_CR_BIF_INT_STAT:     000D2000\r\n[  820.934705] PVR_K: (P0) EUR_CR_BIF_FAULT:        F15A6010\r\n[  820.940232] PVR_K: (P0) EUR_CR_BIF_MEM_REQ_STAT: 00000000\r\n[  820.945688] PVR_K: (P0) EUR_CR_CLKGATECTL:       002AAAAA\r\n[  820.951111] PVR_K: (P1) EUR_CR_EVENT_STATUS:     043C2F80\r\n[  820.956679] PVR_K: (P1) EUR_CR_EVENT_STATUS2:    000000A8\r\n[  820.962103] PVR_K: (P1) EUR_CR_BIF_CTRL:         00000000\r\n[  820.967647] PVR_K: (P1) EUR_CR_BIF_BANK0:        00000007\r\n[  820.973071] PVR_K: (P1) EUR_CR_BIF_INT_STAT:     00080000\r\n[  820.978615] PVR_K: (P1) EUR_CR_BIF_FAULT:        00000000\r\n[  820.984069] PVR_K: (P1) EUR_CR_BIF_MEM_REQ_STAT: 00000001\r\n[  820.989616] PVR_K: (P1) EUR_CR_CLKGATECTL:       002AAAAA\r\n[  820.995051] PVR_K: Checking EDM memory context (index = 7, PD = 0xac332000)\r\n[  821.002070] PVR_K: Found MMU context for page fault 0xf15a6000\r\n[  821.008092] PVR_K: GPU memory context is for PID=109 (modprobe)\r\n[  821.014066] PVR_K: No PDE found\r\n[  821.017356] PVR_K: Checking TA memory context (index = 0, PD = 0xad93d000)\r\n[  821.024289] PVR_K: Found MMU context for page fault 0xf15a6000\r\n[  821.030264] PVR_K: GPU memory context is for PID=151 (oTobrite_apps.o)\r\n[  821.036862] PVR_K: No PDE found\r\n[  821.040019] PVR_K: Checking 3D memory context (index = 0, PD = 0xad93d000)\r\n[  821.047073] PVR_K: Found MMU context for page fault 0xf15a6000\r\n[  821.052933] PVR_K: GPU memory context is for PID=151 (oTobrite_apps.o)\r\n[  821.059612] PVR_K: No PDE found\r\n[  821.062769] PVR_K: Checking PTLA memory context (index = 0, PD = 0xad93d000)\r\n[  821.069970] PVR_K: Found MMU context for page fault 0xf15a6000\r\n[  821.075839] PVR_K: GPU memory context is for PID=151 (oTobrite_apps.o)\r\n[  821.082465] PVR_K: No PDE found\r\n[  821.085755] PVR_K:  Host Ctl flags= 0000000c\r\n[  821.090043] PVR_K: SGX Host control:\r\n[  821.093663] PVR_K: \t(HC-0) 0x00000001 0x00000000 0x00000000 0x00000004\r\n[  821.100363] PVR_K: \t(HC-10) 0x00000002 0x0000000A 0x0004A666 0x00000000\r\n[  821.107041] PVR_K: \t(HC-20) 0x00000000 0x00000007 0x00000000 0x00000000\r\n[  821.113685] PVR_K: \t(HC-30) 0x000A3691 0x1EE73970 0x00000000 0x00000000\r\n[  821.120496] PVR_K: \t(HC-40) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.127151] PVR_K: \t(HC-50) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.133822] PVR_K: \t(HC-60) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.140599] PVR_K: \t(HC-70) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.147277] PVR_K: \t(HC-80) 0x00000000 0x00000000 0x00041BA3 0xAA2E7800\r\n[  821.153919] PVR_K: SGX TA/3D control:\r\n[  821.157746] PVR_K: \t(T3C-0) 0xF4003000 0xF40031A0 0xF4002000 0x00000000\r\n[  821.164392] PVR_K: \t(T3C-10) 0x00000000 0x00000002 0x00000000 0x00000000\r\n[  821.171248] PVR_K: \t(T3C-20) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.177990] PVR_K: \t(T3C-30) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.184770] PVR_K: \t(T3C-40) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.191635] PVR_K: \t(T3C-50) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.198400] PVR_K: \t(T3C-60) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.205234] PVR_K: \t(T3C-70) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.211993] PVR_K: \t(T3C-80) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.218845] PVR_K: \t(T3C-90) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.225613] PVR_K: \t(T3C-A0) 0x00000000 0x00000000 0x00000000 0xF4156420\r\n[  821.232345] PVR_K: \t(T3C-B0) 0xF4002C60 0xF4000000 0xAC332000 0x00000000\r\n[  821.239226] PVR_K: \t(T3C-C0) 0x00000000 0xF412C000 0xF4002C60 0xF411E8C0\r\n[  821.245971] PVR_K: \t(T3C-D0) 0xF400FF80 0x00000000 0x00000000 0xF4156420\r\n[  821.252730] PVR_K: \t(T3C-E0) 0xF41214A0 0x0010122E 0x0010122E 0x00000000\r\n[  821.259592] PVR_K: \t(T3C-F0) 0x00000000 0x00000000 0x00000000 0x00000000\r\n[  821.266358] PVR_K: \t(T3C-100) 0x00000000 0x00000000 0x00000000 0x000001FE\r\n[  821.273176] PVR_K: \t(T3C-110) 0x00000022 0x00000000 0x00000000 0x00000000\r\n[  821.280144] PVR_K: \t(T3C-120) 0x00000021 0x00005608 0x00005608 0x00000000\r\n[  821.287026] PVR_K: \t(T3C-130) 0xF2016010 0xF2016014 0xF2016034 0xF2016030\r\n[  821.293873] PVR_K: \t(T3C-140) 0xF4004000 0xF400F820 0xF4002020 0xF411D000\r\n[  821.300823] PVR_K: \t(T3C-150) 0xF411D000 0x00000000 0x00000000 0x00000097\r\n [HOST] [IPU2  ]    823.966266 s: src/bsp_deviceI2c.c @ Line 580[  821.307821] PVR_K: \t(T3C-160) 0x00000097 0x00000000 0x00000000 0x00000000\r\n: \r\n\r\n...\r\n\r\n [HOST] [HOST  ]    835.890837 s: [eth_monitor]: init:1, BMCR:0x2100, BMSR:0x5, PHY_PktCnt:1067423, Linux_PktCnt:1067340\r\n\r\n[  833.328622] Unable to handle kernel paging request at virtual address c4e1b590\r\n[  833.335878] pgd = ed2f6b80\r\n[  833.338592] [c4e1b590] *pgd=80000080007003, *pmd=00000000\r\n[  833.344025] Internal error: Oops: 206 [#1] PREEMPT ARM\r\n[  833.349181] Modules linked in: cmemk(O) memcache(O) rpmsg_proto virtio_rpmsg_bus omap_remoteproc remoteproc virtio_ring virtio bc_example(O) pvrsrvkm(O)\r\n[  833.362956] CPU: 0 PID: 213 Comm: oTobrite_apps.o Tainted: G           O    4.4.84+ #3\r\n[  833.370903] Hardware name: Generic DRA74X (Flattened Device Tree)\r\n[  833.377020] task: edd9d600 ti: ed926000 task.ti: ed926000\r\n[  833.382443] PC is at ksize+0x30/0xac\r\n[  833.386034] LR is at __alloc_skb+0x80/0x16c\r\n[  833.390232] pc : [<c00fd600>]    lr : [<c049d4ec>]    psr: a00b0013\r\n[  833.390232] sp : ed927d90  ip : ed927da8  fp : ed927da4\r\n[  833.401756] r10: 80827f82  r9 : 00000001  r8 : 00000001\r\n[  833.407000] r7 : 00000000  r6 : 024000c0  r5 : 00000780  r4 : c4e1b57c\r\n[  833.413551] r3 : c084e484  r2 : a00b0013  r1 : eff63080  r0 : 006c495f\r\n[  833.420103] Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user\r\n[  833.427265] Control: 30c53c7d  Table: ad2f6b80  DAC: fffffffd\r\n[  833.433032] Process oTobrite_apps.o (pid: 213, stack limit = 0xed926208)\r\n[  833.439758] Stack: (0xed927d90 to 0xed928000)\r\n[  833.444130] 7d80:                                     c2670a80 00000780 ed927dd4 ed927da8\r\n[  833.452342] 7da0: c049d4ec c00fd5dc ffffffff 00000000 ed929600 000005b4 00000000 00000000\r\n[  833.460553] 7dc0: ed9296d4 c2670c00 ed927dfc ed927dd8 c04f0b70 c049d478 000005b4 ed927ec4\r\n[  833.468763] 7de0: 00000000 000005b4 ed927ec4 ed929600 ed927e74 ed927e00 c04f17cc c04f0b20\r\n[  833.476975] 7e00: 000005b4 ed927e10 c0055d84 c005de9c edd9e100 00000001 00000000 00000000\r\n[  833.485184] 7e20: ed926000 c0055ce4 00000000 00000000 000005b4 001394f0 ed927e6c 000005b4\r\n[  833.493395] 7e40: 00000059 c45dd049 ed927eb4 ed929600 00000000 c2a37000 00000121 c000fba4\r\n[  833.501605] 7e60: ed926000 00000000 ed927e94 ed927e78 c0519534 c04f1258 c012a1d4 c012a150\r\n[  833.509816] 7e80: ed927ea4 00000000 ed927ea4 ed927e98 c0492334 c0519504 ed927f8c ed927ea8\r\n[  833.518027] 7ea0: c04931e4 c0492324 ed927ecc ed926000 ed927f54 fffffff7 00000001 b39d9080\r\n[  833.526237] 7ec0: 00153640 00000000 00000000 00000001 001394f0 0001a150 ed927ebc 00000001\r\n[  833.534447] 7ee0: 00000000 00000000 00000000 00000015 ed929600 00000000 ed927f34 ed927f08\r\n[  833.542657] 7f00: c0495d84 c0039030 00000064 ed929600 00000000 00000008 c2a37000 82d72cf0\r\n[  833.550867] 7f20: 00000001 00000000 ed927f6c ed927f38 c0497b44 c0495c58 ed927f54 ed927f48\r\n[  833.559077] 7f40: c012a1d4 c012a150 00000008 00000001 00000015 82d72cf0 00000008 00000001\r\n[  833.567286] 7f60: ed927fa4 ed927f70 c04933f0 c010e9a0 00000008 00000040 82d73664 00000000\r\n[  833.575496] 7f80: ed927fa4 ed927f90 c049322c c0493130 00000000 00000000 00000000 ed927fa8\r\n[  833.583707] 7fa0: c000fa00 c0493218 00000040 82d73664 0000003a b39d9080 00153640 00000000\r\n[  833.591918] 7fc0: 00000040 82d73664 00000000 00000121 00000000 82d72f90 00000000 bebf0bf8\r\n[  833.600128] 7fe0: 00000000 82d72cd0 00000000 b6f25170 800f0030 0000003a e1a04000 e3a00012\r\n[  833.608335] Backtrace: \r\n[  833.610799] [<c00fd5d0>] (ksize) from [<c049d4ec>] (__alloc_skb+0x80/0x16c)\r\n[  833.617786]  r5:00000780 r4:c2670a80\r\n[  833.621394] [<c049d46c>] (__alloc_skb) from [<c04f0b70>] (sk_stream_alloc_skb+0x5c/0x188)\r\n[  833.629601]  r10:c2670c00 r9:ed9296d4 r8:00000000 r7:00000000 r6:000005b4 r5:ed929600\r\n[  833.637493]  r4:00000000 r3:ffffffff\r\n[  833.641095] [<c04f0b14>] (sk_stream_alloc_skb) from [<c04f17cc>] (tcp_sendmsg+0x580/0xab4)\r\n[  833.649389]  r7:ed929600 r6:ed927ec4 r5:000005b4 r4:00000000\r\n[  833.655100] [<c04f124c>] (tcp_sendmsg) from [<c0519534>] (inet_sendmsg+0x3c/0x70)\r\n[  833.662610]  r10:00000000 r9:ed926000 r8:c000fba4 r7:00000121 r6:c2a37000 r5:00000000\r\n[  833.670500]  r4:ed929600\r\n[  833.673050] [<c05194f8>] (inet_sendmsg) from [<c0492334>] (sock_sendmsg+0x1c/0x2c)\r\n[  833.680646]  r4:00000000\r\n[  833.683194] [<c0492318>] (sock_sendmsg) from [<c04931e4>] (SyS_sendto+0xc0/0xe8)\r\n[  833.690620] [<c0493124>] (SyS_sendto) from [<c049322c>] (SyS_send+0x20/0x28)\r\n[  833.697694]  r6:00000000 r5:82d73664 r4:00000040\r\n[  833.702350] [<c049320c>] (SyS_send) from [<c000fa00>] (ret_fast_syscall+0x0/0x34)\r\n[  833.709864] Code: e1a00620 e5934000 e0800180 e0844100 (e5940014) \r\n[  833.715985] ---[ end trace 6d56e50ec7025b94 ]---\r\n [HOST] [DSP1  ]    836.388275 s: [DSP] more frames 4",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, Could you explain what application you are running? Could you also describe more details about how the crash occurred? Does it always crash with the same error log? We never have any issue with MMU (for A15, M4, or DSP) on this device so I don't think you need to run any MMU test. Or, is the MMU unit you referring to something different than memory management unit? Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1033627.json

@@ -0,0 +1,196 @@
+{
+  "ticketNumber" : "1033627",
+  "reporterName" : "user6426230",
+  "rankPoints" : "80",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA4VM: Off-screen rendering problem: 0x506 GL_INVALID_FRAMEBUFFER_OPERATION",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Use off-screen rendering on TDA4 to report 0x506 error GL_INVALID_FRAMEBUFFER_OPERATION. QNX system, SDK version 7.3~ The same off-screen rendering is OK on TDA2 based on Linux system 3.7 and 3.8SDK. You said that TDA4 is supported, and the below is to implement the basic code. Help analyze it. If you need to provide other supplements, please point out~ code show as below: //initialization void SvEglRenderBase::InitFrameBufferOpt() { //Create frame buffer object: FBO glGenFramebuffers(1, &m_nSvTopviewFbo); glGetIntegerv(GL_FRAMEBUFFER_BINDING, &m_nSvDefaultFbo); glBindFramebuffer(GL_FRAMEBUFFER, m_nSvTopviewFbo); int nTestId; glGetIntegerv(GL_FRAMEBUFFER_BINDING, &nTestId); //Create offline render texture glGenTextures(1, &m_nSvTopviewTexture); glBindTexture(GL_TEXTURE_2D, m_nSvTopviewTexture); glTexImage2D(GL_TEXTURE_2D, 0, GL_RGB, SV_2D_LUT_WIDTH, SV_2D_LUT_HEIGHT, 0, GL_RGB, GL_UNSIGNED_BYTE, NULL); //Setting Texture Parameters: Interpolation method. The interpolation methods of the farthest and nearest can be set differently. glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR); glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_LINEAR); //Binding 2D texture to default texture is generally used to break the previous texture binding relationship //and restore the texture binding state of OpenGL to the default state. glBindTexture(GL_TEXTURE_2D, 0); //Bind textrue to FBO glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D, m_nSvTopviewTexture, 0); glBindFramebuffer(GL_FRAMEBUFFER, m_nSvDefaultFbo); //Create frame buffer object: FBO glGenFramebuffers(1, &m_nSvPart3dFbo); //Create offline render texture glGenTextures(1, &m_nSvPart3dTexture); //If 3D off-screen rendering is required, depth Buffer is required here glGenRenderbuffers(1, &m_nSvPart3dDepthId); //Bind FBO: To use FBO, it must be bind firstly. Make it the current rendering buffer. glBindFramebuffer(GL_FRAMEBUFFER, m_nSvPart3dFbo); //Create offline render texture: Texture must be created befroe it is bind to FBO glBindTexture(GL_TEXTURE_2D, m_nSvPart3dTexture); glTexImage2D(GL_TEXTURE_2D, 0, GL_RGB, SV_3D_VIEW_WIDTH, SV_3D_VIEW_HEIGHT,0, GL_RGB, GL_UNSIGNED_BYTE, NULL); //Setting Texture Parameters: Interpolation method. The interpolation methods of the farthest and nearest can be set differently. glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR); glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_LINEAR); //Binding 2D texture to default texture is generally used to break the previous texture binding relationship //and restore the texture binding state of OpenGL to the default state. glBindTexture(GL_TEXTURE_2D, 0); //Bind textrue to FBO glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D, m_nSvPart3dTexture, 0); glBindRenderbuffer(GL_RENDERBUFFER, m_nSvPart3dDepthId); glRenderbufferStorage(GL_RENDERBUFFER, GL_DEPTH_COMPONENT16, SV_3D_VIEW_WIDTH, SV_3D_VIEW_HEIGHT); glFramebufferRenderbuffer(GL_FRAMEBUFFER, GL_DEPTH_ATTACHMENT, GL_RENDERBUFFER, m_nSvPart3dDepthId); glBindRenderbuffer(GL_RENDERBUFFER, 0); glBindFramebuffer(GL_FRAMEBUFFER, m_nSvDefaultFbo); //Type 0 in TDA4 //Type 0 in TDA4 //Type 0 in TDA4 //Type 0 in TDA4 GLenum eErrStatus = glCheckFramebufferStatus(GL_FRAMEBUFFER); printf(\"[AVM] glCheckFramebufferStatus complete eErrStatus = 0x%x.\\n\",eErrStatus); if(eErrStatus != GL_FRAMEBUFFER_COMPLETE) { switch(eErrStatus) { case GL_FRAMEBUFFER_COMPLETE: printf(\"[AVM] Framebuffer complete.\\n\"); break; case GL_FRAMEBUFFER_INCOMPLETE_ATTACHMENT: printf(\"[AVM] [ERROR] Framebuffer incomplete: Attachment is NOT complete.\\n\"); break; case GL_FRAMEBUFFER_INCOMPLETE_MISSING_ATTACHMENT: printf(\"[AVM] [ERROR] Framebuffer incomplete: No image is attached to FBO.\\n\"); break; case GL_FRAMEBUFFER_INCOMPLETE_DIMENSIONS: printf(\"[AVM] [ERROR] Framebuffer incomplete: Attached images have different dimensions.\\n\"); break; case GL_FRAMEBUFFER_UNSUPPORTED: printf(\"[AVM] [ERROR] Unsupported by FBO implementation.\\n\"); break; default: printf(\"[AVM] [ERROR] Unknow error.\\n\"); break; } } } //Rendering and drawing glBindFramebuffer(GL_FRAMEBUFFER, m_pEGLRenderBase->m_nSvTopviewFbo); DrawOffline1(); DrawOffline2(); DrawOffline3(); glBindFramebuffer(GL_FRAMEBUFFER, m_pEGLRenderBase->m_nSvDefaultFbo); DrawAll(); //Report 0x506 error here GL_INVALID_FRAMEBUFFER_OPERATION GLenum nErrId = glGetError(); if (nErrId != GL_NO_ERROR Help analyze it. If you need to provide other supplements, please point out~ Please~ Thanks~",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Compared with the SDK of TDA2 3.07 version, the differences are: FBO is used outside TDA4: Why does TDA4 use FBO in the outermost rendering? In appEglBindFrameBufferl, the off-screen rendering is initialized and the FBO is bound, then render_renderFrame is called to render, and finally appEglSwap But TDA2 does not use FBO here, and directly calls render_renderFrame to render, and then System_eglSwap. The appEglBindFrameBuffer function in TDA4 is as follows, FBO is used inside. void appEglBindFrameBuffer(void *eglWindow, app_egl_tex_prop_t *prop) { int32_t texFound; int32_t texIndex; uint32_t i; PFNGLEGLIMAGETARGETTEXTURE2DOESPROC glEGLImageTargetTexture2DOES; PFNGLCLIPCONTROLEXTPROC glClipControlEXT; app_egl_obj_t *obj = (app_egl_obj_t*)eglWindow; app_egl_tex_obj_t *tex_obj; glEGLImageTargetTexture2DOES = (PFNGLEGLIMAGETARGETTEXTURE2DOESPROC)eglGetProcAddress(\"glEGLImageTargetTexture2DOES\"); glClipControlEXT = (PFNGLCLIPCONTROLEXTPROC)eglGetProcAddress(\"glClipControlEXT\"); texIndex = -1; texFound = 0; for(i = 0; i < APP_EGL_MAX_RENDER_TEXTURES; i++) { tex_obj = &obj->texRender[i]; if(tex_obj->isAlloc && tex_obj->dmaBufFd == prop->dmaBufFd[0] && tex_obj->dmaBufFdOffset == prop->dmaBufFdOffset[0] ) { texIndex = i; texFound = 1; break; } } if(!texFound) { /* find free slot amd create texture */ for(i = 0; i < APP_EGL_MAX_RENDER_TEXTURES; i++) { tex_obj = &obj->texRender[i]; if(!tex_obj->isAlloc) { int32_t status; status = appEglWindowSetupRenderTex(obj, prop, i); if(status==0) { texIndex = i; texFound = 1; } break; } } } if(texFound) { tex_obj = &obj->texRender[texIndex]; glActiveTexture(GL_TEXTURE2); glBindTexture(GL_TEXTURE_2D, tex_obj->tex); //appEglCheckEglError(\"glBindTexture\", EGL_TRUE); glEGLImageTargetTexture2DOES(GL_TEXTURE_2D, (GLeglImageOES)tex_obj->img); //appEglCheckEglError(\"glEGLImageTargetTexture2DOES\", EGL_TRUE); glBindFramebuffer(GL_FRAMEBUFFER, tex_obj->fboId); // appEglCheckEglError(\"glBindFramebuffer\", EGL_TRUE); glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0,GL_TEXTURE_2D, tex_obj->tex, 0); //appEglCheckEglError(\"glFramebufferTexture2D\", EGL_TRUE); GLenum fbstatus = glCheckFramebufferStatus(GL_FRAMEBUFFER); if (fbstatus != GL_FRAMEBUFFER_COMPLETE) printf(\"EGL: ERROR: Frambuffer complete check failed 0x%x\\n\", fbstatus); } /* Binding FBO: move the origin to upper left */ glClipControlEXT(GL_UPPER_LEFT_EXT, GL_NEGATIVE_ONE_TO_ONE_EXT); }",
+    "imageList" : [ "Data/input/1033627/png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, The below code snippet works on TDA4 Linux. Can you please try this out? If it still doesn't work, you may have to contact QNX.      \r\n        // Store the current frame buffer \r\n        glGetIntegerv(GL_FRAMEBUFFER_BINDING, &current_fbo);\r\n        glActiveTexture(GL_TEXTURE0 + 15);\r\n        glGenTextures(1, &offscreen_fbo_texture);\r\n        glBindTexture(GL_TEXTURE_2D, offscreen_fbo_texture);\r\n        glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_NEAREST);\r\n        glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);\r\n        glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE);\r\n        glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE);\r\n        glTexImage2D(GL_TEXTURE_2D, 0, GL_RGBA, width, height, 0, GL_RGBA, GL_UNSIGNED_BYTE, NULL);\r\n        glActiveTexture(GL_TEXTURE0);\r\n        glBindTexture(GL_TEXTURE_2D, 0);\r\n\r\n        /* Depth buffer */\r\n        glGenRenderbuffers(1, &offscreen_fbo_depth);\r\n        glBindRenderbuffer(GL_RENDERBUFFER, offscreen_fbo_depth);\r\n        glRenderbufferStorage(GL_RENDERBUFFER, GL_DEPTH_COMPONENT16, width, height);\r\n        glBindRenderbuffer(GL_RENDERBUFFER, 0);\r\n\r\n        /* Framebuffer to link everything together */\r\n        glGenFramebuffers(1, &offscreen_fbo);\r\n        glBindFramebuffer(GL_FRAMEBUFFER, offscreen_fbo);\r\n        glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D, offscreen_fbo_texture, 0);\r\n        glFramebufferRenderbuffer(GL_FRAMEBUFFER, GL_DEPTH_ATTACHMENT, GL_RENDERBUFFER, offscreen_fbo_depth);\r\n\r\n        if ((status = glCheckFramebufferStatus(GL_FRAMEBUFFER)) != GL_FRAMEBUFFER_COMPLETE) {\r\n                fprintf(stderr, \"glCheckFramebufferStatus returned error %d\", status);\r\n                return -1;\r\n        }\r\n        \r\n        // Bind back original frame buffer\r\n        glBindFramebuffer(GL_FRAMEBUFFER, current_fbo);\r\n        \r\n        // To draw to offscreen fbo, bind offscreen_fbo\r\n        glBindFramebuffer(GL_FRAMEBUFFER, offscreen_fbo);\r\n        // ....\r\n        // Draw to Offscreen FBO\r\n        // ....",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, The reason why TDA4 uses FBO for rendering is because of how the display works. The display in case of TDA2 was driven by EGL and thus the swap. In case of TDA4, the display is being driven by R5. The GPU rendered buffer is passed on to display node that takes care of displaying the buffer. This is why we need off screen buffer on TDA4. Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Okay, thank you very much for your prompt and detailed reply. I understand the reason why TDA4 adopts FBO. Now back to the problem: The rendering process in TDA4: ... ... 1. texYuv[i] = appEglWindowGetTexYuv(pEglWindowObj, &texProp[i]); ... ... 2. appEglBindFrameBuffer(glSrvParams->eglWindowObj, &renderTexProp); FBO is used in this function glGenTextures(1, &tex_obj->tex); glBindTexture(GL_TEXTURE_2D, tex_obj->tex); glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR); glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_LINEAR); glGenFramebuffers(1, &tex_obj->fboId); glBindFramebuffer(GL_FRAMEBUFFER, tex_obj->fboId); GLuint rboDepthStencil; glGenRenderbuffers(1, &rboDepthStencil); glBindRenderbuffer(GL_RENDERBUFFER, rboDepthStencil); glRenderbufferStorage(GL_RENDERBUFFER, GL_DEPTH24_STENCIL8_OES, prop->width, prop->height); glFramebufferRenderbuffer(GL_FRAMEBUFFER, GL_DEPTH_ATTACHMENT, GL_RENDERBUFFER, rboDepthStencil); glFramebufferRenderbuffer(GL_FRAMEBUFFER, GL_STENCIL_ATTACHMENT, GL_RENDERBUFFER, rboDepthStencil); glActiveTexture(GL_TEXTURE2); glBindTexture(GL_TEXTURE_2D, tex_obj->tex); glEGLImageTargetTexture2DOES(GL_TEXTURE_2D, (GLeglImageOES)tex_obj->img); glBindFramebuffer(GL_FRAMEBUFFER, tex_obj->fboId); glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0,GL_TEXTURE_2D, tex_obj->tex, 0); ... ... 3. render_renderFrame(&glSrvParams->render3DSRVObj,glSrvParams->eglWindowObj,texYuv); Here is the texture unit texYuv that has been bound in step 1. Now the problem is here: if I use a new FBO in render_renderFrame (not the same as tex_obj->fboId in appEglBindFrameBuffer in step 2), Here it will report 0x506 GL_INVALID_FRAMEBUFFER_OPERATION error, so nothing can be drawn. The reason why I use a new FBO here is that I want to draw A first, then draw B, and finally display it as a new texture after processing. My usage is as described before, here is the wrong method I used? Or is there any other way to achieve what I want? 4. glFinish(); glBindFramebuffer(GL_FRAMEBUFFER, 0); appEglSwap(glSrvParams->eglWindowObj); Looking forward to your prompt reply, thank you~",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Thank you for your reply. I will experiment with the method you mentioned in the render_renderFrame function. It doesn't feel much different from my previous usage. Just one more step of glActiveTexture(GL_TEXTURE0 + 15) operation. And yours here seems to be the opposite of mine: // Bind back original frame buffer glBindFramebuffer(GL_FRAMEBUFFER, current_fbo); //here current_fbo is equivalent to 0, that is, glBindFramebuffer(GL_FRAMEBUFFER, 0); // To draw to offscreen fbo, bind offscreen_fbo glBindFramebuffer(GL_FRAMEBUFFER, offscreen_fbo); //offscreen_fbo here is not equal to 0 // .... // Draw to Offscreen FBO // .... Here at the end do not use glBindFramebuffer(GL_FRAMEBUFFER, 0), and then draw the offscreen_fbo_texture? According to my thoughts: // To draw to offscreen fbo, bind offscreen_fbo glBindFramebuffer(GL_FRAMEBUFFER, offscreen_fbo); DrawA(); DrawB(); DrawC(); // Bind back original frame buffer glBindFramebuffer(GL_FRAMEBUFFER, 0); //Draw offscreen_fbo_texture Draw(offscreen_fbo_texture); If there is progress, I will communicate with you in time.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "I verified it according to your method today, but it still doesn’t work, and an error is still reported: GL: after render_renderFrame() glError (0x506) The screen is always black. I feel that the crux of the problem lies in: As you said before, in the case of TDA4, the display is driven by R5, so TDA4 uses FBO for rendering outside. In this way, we can no longer create and use other FBOs in render_renderFrame(). What needs to be solved now is: TDA4 uses FBO outside, How to create and use other FBOs in render_renderFrame()?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, Can you refer to this code: appEglWindowSetupRenderTex in vision_apps/utils/opengl/src/a72/app_gl_egl_utils_qnx.c This will show you how to set up render target. You can use this code as a reference or modify it as needed. Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "what I want to do is this: Create 2 framebuffers, let’s call them fb1 and fb2. Render the scene to fb2 normally. Render fb2 to fb1 with one post-processing effect. Render fb1 to the default framebuffer (we’ll call it fb0) with another post-processing effect.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, This works for me. Please look at an example implementation in offscreen.cpp. Shaders and header are included as well. offscreen.cppoffscreen.hoffscreen.fshoffscreen.vsh Let us assume that fb0 is the one that is being currently used. Let this be the framebuffer that is being used by default. Our target is to keep this as the final frame buffer that goes to the R5 for display. Now, let us create a second offscreen buffer and render surround view to it. For this, we will create and manage the framebuffer inside render.cpp and not change anything outside that. Include offscreen.h in render.cpp and make the following changes: In render_init function, add this (you can add after car_init):     if(offscreen_init(&offscreen_fbo, width, height) != 0)\r\n    {\r\n            offscreen_fbo = 0;\r\n            printf(\"offscreen_init failed. Cannot run in offscreen mode.\");\r\n    }; Please define offscren_fbo (to be returned by offscreen_init) and define width and height as per your screen resolution and requirements. Now, in render_renderFrame, at the very beginning, save the default fbo and use the framebuffer initialized above. At the end of the function, switch to default fb and render the offscreen texture to final framebuffer void render_renderFrame(render_state_t *pObj, void *pEglObj, GLuint *texYuv)\r\n{\r\n        GLint default_fbo;\r\n\r\n        glGetIntegerv(GL_FRAMEBUFFER_BINDING, &default_fbo);\r\n\r\n        // srv_param_offscreen is used to enable and disable offscreen processing\r\n        if((srv_param_offscreen == true) && (offscreen_fbo !=0 ))\r\n        {\r\n                offscreen_render = true;\r\n                glBindFramebuffer(GL_FRAMEBUFFER, offscreen_fbo);\r\n        }\r\n        else\r\n        {\r\n                offscreen_render = false;\r\n        }\r\n        \r\n        /// The rest of the SRV code can stay unmodified.\r\n        // After srv_draw and car_draw for all viewports are done,\r\n        // we can switch back to original fb\r\n        \r\n        // This piece of code below remains unchanged\r\n        glClear(GL_COLOR_BUFFER_BIT);\r\n        {\r\n            for(int i = 0; i < num_viewports; i++)\r\n            {\r\n                //..... surround view rendering code .....\r\n                // ...\r\n                // ...\r\n            }\r\n        }\r\n        \r\n        // Add the below lines to switch to original fb and draw the\r\n        // offscreen texture to final frame buffer\r\n        if(offscreen_render == true)\r\n        {\r\n                glFinish();\r\n                glBindFramebuffer(GL_FRAMEBUFFER, default_fbo);\r\n                glViewport(0, 0, width, height);\r\n                offscreen_draw(width, height);\r\n        }\r\n        \r\n        //... frame count/fps code stays as is\r\n}\r\n\r\n You can modify offscreen shaders and code to include any post processing. This example adds only one extra framebuffer. Once you get this working, you can have a second one as needed. This code works on linux. If you face any issues on QNX, please check with QNX. Hope this helps. Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Thank you very much for your reply. This method really works. But introduced a new problem: splash screen, the screen keeps flickering If you remove this, the display will be normal and there will be no flickering.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "This sounds like the texture may not be rendered to. Just for experiment, can you change glFinish to glReadPixels and see if the flickering goes away? Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Thank you for your prompt reply, I feel that dawn is coming soon, and now only the splash screen problem is left First of all, the rendering was successful, but the total splash screen; Annotated the glFinish function inside render_renderFrame (reserved by glFinish outside render_renderFrame), the screen still flickers. After the appEglSwap and appPerfStatsHwaUpdateLoad functions outside render_renderFrame, call the glReadPixels function, which does not take effect, and the saved images are all black. (The saved screen is also black when it is not flickering). In addition, by the way, why must TDA4 GPU rendering be used: screen -c /usr/lib/graphics/jacinto7/graphics.conf.dss_on_r5",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, You need to try glReadPixels before glBindFramebuffer(GL_FRAMEBUFFER, default_fbo); in the example above. I would also recommend reaching out to QNX regarding this flicker and the screen command. Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "After verification: changing glFinish to glReadPixels, the flickering phenomenon still exists.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "I see such instructions elsewhere: OpenGL ES double-buffered drawing causes a splash screen. In fact, double buffering is used to solve the splash screen problem. But there is a situation that makes double-buffering drawing will cause a splash screen problem: in a process (due to certain restrictions, only one On-screen Surface can be applied for), two different locations need to be displayed at the same time. This situation will lead to the following problems (A and B represent Buffers that need to be displayed in different positions. A0 represents the 0th frame of A Buffer) Time\\screen on(up-screen Buffer) off(off-screen Buffer) T1 A0 B0 A1 B0 T2 (upper screen swap) A1 B0 A0 B0 T3 A1 B0 A0 B1 T4 (upper screen swap) A0 B1 A1 B0 -From T3 to T4, this time period will cause a flickering screen. Because double buffering is used to swap on the screen, swapping the data of on and off (in fact, the content pointed to by the pointer is changed). Therefore, when T4 is on the screen, the A position, the corresponding off-screen Buffer is old. solution This provides a solution: after swap, update the off-screen (off) Buffer. Details are as follows: Time\\screen on off T1 A0 B0 A1 B0 T2 (upper screen) A1 B0 A0 B0 T2 (update) A1 B0 A1 B0 T3 A1 B0 A1 B1 T4 (upper screen) A1 B1 A1 B0 T4 (update) A1 B1 A1 B1 -As shown above, after each swap, update the off-screen data. In this way, when you go to the screen again, it will not cause a splash screen. In the example you provided, how to update off-screen data?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "After verification: changing glFinish to glReadPixels, the flickering phenomenon still exists. But the image saved by glReadPixels is normal.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "I found this function, Is it possible to use the solution? GLenum glClientWaitSync( GLsync sync, GLbitfield flags, GLuint64 timeout);",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, Possibly - you may have to create sync objects to synchronize rendering - we haven't tried this in this case but worth trying. glFinish should have synchronized. It is not very efficient and as you mentioned, ideally, you want to have double buffering with synchronization. Did you get a chance to ask QNX about this? Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Thanks~ But this actually has nothing to do with the operating system. We have also tested the Linux system, and there will be such a splash screen problem. It feels related to TDA4, because we are OK on TDA2. I feel that the crux of this problem lies in: how to synchronize double buffering? Maybe I don’t have enough knowledge in this area, can you provide some demo reference?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Let us continue discussion here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1039081/tda4vm-create-2-framebuffers-but-introduced-a-new-problem-splash-screen-the-screen-keeps-flickering Can we close this one?",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1033681.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1033681",
+  "reporterName" : "Likhith C",
+  "rankPoints" : "270",
+  "resolutionStatus" : "",
+  "ticketName" : "CCSTUDIO: Using CCS scripting with Lauterbach debugger.",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: CCSTUDIO Other Parts Discussed in Thread: TDA2 Hi, I have a TDA2XX-EVM on which i'm loading and running few binaries of different cores. Here i'm using Spectrum Digital XDS560V2 STM USB Emulator. Also i'm using scripts to launch ccxml, load and run binaries. But i need to use Lauterbach debugger instead of this spectrum digital debugger. But i could'nt find any example scripts with respect to Lauterbach debugger. Can anyone please tell me or send me a reference links that specifies the use of Lauterbach debugger for my TDA2XX regards, Likhith",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Richard Woodruff",
+    "rankPoints" : "17765",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/23259",
+    "content" : "-0- Which TDA2 chip are you using? Does it have a single A15 or a dual-A15? I do have TRACE32 CMMs which are converted versions of GELs which I use. Typically these are shared via TI-CDDS. If you have access I could upload there. If you tell exactly which CPU you have I can see about uploading a subset here. -1- Lauterbach on their website (and in their release images) has simplified scripts which allow running code on TDA2 systems. It might be one of these is sufficient for whatever you are trying to run. https://www.lauterbach.com/scripts/hardware/arm~tda2x~vayu_evm/hardware-arm-tda2x-vayu_evm_20200205093516_all_files.zip https://www.lauterbach.com/scripts/hardware/arm~dra72x~j6_eco_evm/hardware-arm-dra72x-j6_eco_evm_20200205093452_all_files.zip https://www.lauterbach.com/scripts/hardware/arm~dra7xx/hardware-arm-dra7xx_20200205093452_all_files.zip Regards, Richard W.",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1035356.json

@@ -0,0 +1,34 @@
+{
+  "ticketNumber" : "1035356",
+  "reporterName" : "Joe Hsien",
+  "rankPoints" : "220",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2EXEVM: TDA2 DSP2 XDC ASSERT",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2EXEVM Other Parts Discussed in Thread: SYSBIOS We run our algorithm on DSP2. Sometimes DSP2 will have XDC Assert message and then DSP2 will crash. How can we solve it? Log: [DSP2 ] 11173.232111 s: ### XDC ASSERT - ERROR CALLBACK START ### [DSP2 ] 11173.232141 s: [DSP2 ] 11173.232202 s: assertion failure: A_badContext: bad calling context. See GateMutex API doc for details. [DSP2 ] 11173.232233 s: [DSP2 ] 11173.232233 s: ### XDC ASSERT - ERROR CALLBACK END ###",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Joe Hsien",
+    "rankPoints" : "220",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/5203556",
+    "content" : "Have any update?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, Please refer to BIOS API doc for GateMutex. Or, you can find the source under ~/bios_6_46_06_00/packages/ti/sysbios/gates/GateMutex.c. You are hitting the below error where GateMutex_enter() is called in HWI or SWI context. /*\r\n *  ======== GateMutex_enter ========\r\n *  Returns FIRST_ENTER when it gets the gate, returns NESTED_ENTER\r\n *  on nested calls.\r\n *\r\n *  During startup, Task_self returns NULL.  So all calls to the \r\n *  GateMutex_enter look like it is a nested call, so nothing done.\r\n *  Then the leave's will do nothing either. \r\n */\r\nIArg GateMutex_enter(GateMutex_Object *obj)\r\n{\r\n    Semaphore_Handle sem;\r\n\r\n    /* make sure we're not calling from Hwi or Swi context */\r\n    Assert_isTrue(((BIOS_getThreadType() == BIOS_ThreadType_Task) ||\r\n                   (BIOS_getThreadType() == BIOS_ThreadType_Main)),\r\n                   GateMutex_A_badContext);\r\n\r\n    if (obj->owner != Task_self()) {\r\n        sem = GateMutex_Instance_State_sem(obj);\r\n        Semaphore_pend(sem, BIOS_WAIT_FOREVER);\r\n\r\n        obj->owner = Task_self();\r\n\r\n        return (FIRST_ENTER);\r\n    }\r\n\r\n    return (NESTED_ENTER);\r\n} Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1037669.json

@@ -0,0 +1,52 @@
+{
+  "ticketNumber" : "1037669",
+  "reporterName" : "Ruiqi Chen",
+  "rankPoints" : "30",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2HG: tda2 anti-aliasing",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2HG hello: usecase: render a model, but the alias is obvious, so i need to use the anti-aliasing. when the egl chooseconfig, i add the EGL_SAMPLE_BUFFERS, 1 and EGL_SAMPLES,4 to the attribs, it works better, but not enough, so i change the EGL_SAMPLES, 8, the result is eglCreateContex failed! it seems doesn't support. do you have other methods? thanks ~",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, That is correct. 8 is not supported. 4 is the max value for EGL_SAMPLES. Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ruiqi Chen",
+    "rankPoints" : "30",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6697107",
+    "content" : "how about TDA4, the max value?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, TDA4VMid also supports upto 4 - but of course, you will need to keep overall performance in mind. Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Ruiqi Chen",
+    "rankPoints" : "30",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6697107",
+    "content" : "got it, thank you~",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1038392.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1038392",
+  "reporterName" : "Allen35065",
+  "rankPoints" : "3245",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: Memory access error when EVE read address more than 512MB DDR",
+  "rankName" : "Expert",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi expert, Customer used 512MB on TDA2 before while they increased DDR3 to 1GB recently. After modified EMIF and DMM configuration in gel file, we could access 0xB5000000 on DSP and ARM in CCS memory watch page. But on EVE, it reported error as below. Could you please suggest what we need to do to make EVE access correct? Thank you.",
+  "imageList" : [ "Data/input/1038392/jpg" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, You have to update the EVE MMU mapping in GEL file. The max page size per entry in EVE MMU is only 16MB. Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1038421.json

@@ -0,0 +1,115 @@
+{
+  "ticketNumber" : "1038421",
+  "reporterName" : "user3378603",
+  "rankPoints" : "1000",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2EVM5777： How to correctly connect SOC and EMMC when resetting TPS659039",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2E, TDA2 Hello, Question 1: We measured that the SOC PORZ port was continuously pulled down, and the system was not powered on normally. We need TI experts to help analyze the cause of the failure? Figure 2 is a schematic diagram of the hardware schematic design. The RTC_PORZ, RTC_ISO, PORZ of the PMIC and the external reset IC are connected together; the PORZ reset of the PMIC passes through the A device and the RSTOUTn of the PMIC passes through the B device, combined into an AND gate circuit, and the gate output Connect the reset port of EMMC. Question 2: When the connection between PMIC PORZ and A device is disconnected, the system is powered on normally. Figure 1. The yellow line is the waveform we measured at the PORZ reset port of the PMIC, and the pink line is the waveform measured at the reset port of the EMMC. As shown by the pink line, there is a 5ms pull-up level before EMMC reset. We are worried that it will affect the startup of EMMC. Is it necessary to eliminate it through the AND gate? Model of PMIC: TPS659039 SOC model: TDA2E",
+  "imageList" : [ "Data/input/1038421/jpg", "Data/input/1038421/jpg" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Robert Eschler",
+    "rankPoints" : "40020",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/391542",
+    "content" : "Is the block diagram trying to show customer hardware implementation or TI EVM implementation? The diagram is not correct, as the PMIC does not have PORz, RTC_PORz, RTC_ISO signals. These are signals on the processor, which is NOT identified in the diagram. Also the processor does not have reset out signal, that is on the PMIC. Certainly you can't have a reset output from the processor feeding back into the reset input of the PMIC, as that could create a loop where stuck in reset. TI's EVM correctly implements this reset structure. The PMIC reset output feeds the reset inputs of the processor. The processor's reset output (nRSTOUT) is sourced into the PMICs nWARMRESET input.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user3378603",
+    "rankPoints" : "1000",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/3378603",
+    "content" : "Hi Robert, Robert Eschler said: Is the block diagram trying to show customer hardware implementation or TI EVM implementation? The block diagram is updated as follows，Can you confirm if there is any problem with the design? Robert Eschler said: Certainly you can't have a reset output from the processor feeding back into the reset input of the PMIC, According to the TPS659039 specification, the NRESWARM port of TPS659039 is connected to the RETOUTn of SOC，RETOUTn is the Warm reset output of SOC",
+    "imageList" : [ "Data/input/1038421/webwxgetmsgimg.jpg" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Robert Eschler",
+    "rankPoints" : "40020",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/391542",
+    "content" : "The block diagram still cannot be correct, as SoC does not support a reset out. Should this be from PMIC? If you compare with TI EVM, the RESET OUT of PMIC is AND-gate with reset supervisor. Why not replicate the EVM logic, as it is tested/validated? Also - BufferA does not serve any purpose, as any time SoC is reset, nRSTOUT is asserted. Only BufferB is required to reset eMMC device.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user3378603",
+    "rankPoints" : "1000",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/3378603",
+    "content" : "Robert Eschler said: BufferA does not serve any purpose According to the TDA2 specification, Buffer A is needed. In our block diagram, buffer A and buffer B form an AND gate Robert Eschler said: The block diagram still cannot be correct, as SoC does not support a reset out. Should this be from PMIC? YES,Update as shown below",
+    "imageList" : [ "Data/input/1038421/jpg", "Data/input/1038421/jpg" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Robert Eschler",
+    "rankPoints" : "40020",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/391542",
+    "content" : "Can you please clarify in the TDA2 specification where it states buffer A + buffer B (AND-gate) is required for eMMC Reset? PMIC RESET_OUT should connect directly to SoC's reset input(s). It can be AND-gate with supervisor output, but does not need to be routed through supervisor.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user3378603",
+    "rankPoints" : "1000",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/3378603",
+    "content" : "Robert Eschler said: Can you please clarify in the TDA2 specification where it states buffer A + buffer B (AND-gate) is required for eMMC Reset? Sorry，I don’t understand what you mean. I want to eliminate the waveform measured by the RSTN reset pin of EMMC when it is powered on, as shown in the red box in the figure below： Initially ，we wanted to achieve the reset architecture as shown in the figure below and the red box truth table results, but the current reset architecture design seems to be problematic, the PORZ pin of the SOC has been pulled low, so I want to confirm whether our reset architecture design correct?",
+    "imageList" : [ "Data/input/1038421/png_2D00_320x240.png", "Data/input/1038421/png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Robert Eschler",
+    "rankPoints" : "40020",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/391542",
+    "content" : "Have you tried a configuration like modified image below? I don't think the issue is with the AND-gate on nRSTOUT. Also - from the waveform, it looks like the logic levels are very low and are just now turning on (with power supplies). Once the power levels and input thresholds are met, the logic starts working as expected. Maybe try an pull-down resistor (or similar) to eliminate the early pulse.",
+    "imageList" : [ "Data/input/1038421/Untitled.jpg" ]
+  }, {
+    "contentId" : "",
+    "userName" : "user3378603",
+    "rankPoints" : "1000",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/3378603",
+    "content" : "If the reset pin of EMMC remains in this state after power-on, will there be any hidden dangers?",
+    "imageList" : [ "Data/input/1038421/png_2D00_320x240.png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Robert Eschler",
+    "rankPoints" : "40020",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/391542",
+    "content" : "The eMMC is getting a valid reset pulse (low then high), and it appears the final high is full scale (1.8V). I don't see any issue with the final reset. I'm still not clear on the smaller pulse, but again - could be from power just reaching valid logic levels.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user3378603",
+    "rankPoints" : "1000",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/3378603",
+    "content" : "I checked the relevant design in the DEMO board, the version is： 516582H_VAYU_EVM_13NOV2015_H As shown in the figure, the DEMO board does not use the AND gate mentioned in the manual, but only uses a buffer. I want to confirm whether the design can also meet the requirements of TDA2?",
+    "imageList" : [ "Data/input/1038421/jpg", "Data/input/1038421/png", "Data/input/1038421/png", "Data/input/1038421/png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "Robert Eschler",
+    "rankPoints" : "40020",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/391542",
+    "content" : "The AND-gate you are referring only affects the eMMC (or other peripherals), and does not affect the TDA2. The PORz circuit for the TDA2 should not include RSTOUTn, as it is reset output of TDA2.",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1038804.json

@@ -0,0 +1,43 @@
+{
+  "ticketNumber" : "1038804",
+  "reporterName" : "Cherry Zhou",
+  "rankPoints" : "22235",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2EXEVM: How to use remote service on TDA2",
+  "rankName" : "Mastermind",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 The customer would like to get serializer and deserializer‘s register information in usecase code, but that information is on another core, so he intends to use remote service to get the information which is on another core. The customer would like to know how to use remote service function on TDA2, and could you you please offer an example? Thanks. Best Regards, Cherry Zhou",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Cherry Zhou",
+    "rankPoints" : "22235",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/6760322",
+    "content" : "Hi, The latest update as follows: The customer also would like to have an example about how to use remote service function based on TDA2 SDK. Thanks again! Best Regards, Cherry Zhou",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Cherry Zhou",
+    "rankPoints" : "22235",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/6760322",
+    "content" : "Hi, May I know is there any update? Thanks! Best Regards, Cherry Zhou",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi Cherry, Could you give some details about the customer system? What OS is used on A15? Which core will have the SerDes driver? Which core does need to get the register info via remote calls? Regards, Stanley",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1039081.json

@@ -0,0 +1,106 @@
+{
+  "ticketNumber" : "1039081",
+  "reporterName" : "user6426230",
+  "rankPoints" : "80",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA4VM: Create 2 framebuffers， But introduced a new problem: splash screen, the screen keeps flickering",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 background: Based on TDA4, SDK7.03, QNX system, to achieve off-screen rendering problem: what I want to do is this: Create 2 framebuffers, let’s call them fb1 and fb2. Render the scene to fb2 normally. Render fb2 to fb1 with one post-processing effect. Render fb1 to the default framebuffer (we’ll call it fb0) with another post-processing effect. This method really works. But introduced a new problem: splash screen, the screen keeps flickering. After verification: changing glFinish to glReadPixels, the flickering phenomenon still exists. But the image saved by glReadPixels is normal. The specific implementation is as follows:",
+  "imageList" : [ "Data/input/1039081/png" ],
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, Thank you for creating a new thread. I will close the other one and let us use this one. For reference: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1033627/tda4vm-off-screen-rendering-problem-0x506-gl_invalid_framebuffer_operation The fact that glReadPixels on the offscreen buffer returns normal expected image, we need to think if the display node is somehow showing the wrong buffer. Do we know if there is a timing involved? Some suggestions and questions: 1. Have you tried glReadPixels on the final FB? Does this look okay? 2. Instead of any post processing, can we do a simple glClear (of different colors) to fb0, fb1 and fb2 And can we switch colors for each to see what is ending up on the display. 3. As a separate experiment, continue with normal rendering processing but do a glClear of alternating colors on fb0 Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "OK, I will start experimenting now, and I will tell you immediately if there is a conclusion, it is expected in three hours. But this is done to verify: the two Buffers are constantly switching or?",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "In order to better verify, compare and analyze the result data, FB1 was rendered red by me; FB2 was rendered blue by me; FB0 was finally rendered (including the content on FB1 and FB2 and other textures such as the car model drawn normally) After verification, the image results saved by FB0, FB1, and FB2 are all completely OK. [AVM] FB0 Width=1920, Height=720, Format=0x80e1 (GL_BGRA=0x80e1, GL_BGR=0x80e0), Type=0x1401... [AVM] FB1 Width=560, Height=720, Format=0x80e1 (GL_BGRA=0x80e1, GL_BGR=0x80e0), Type=0x1401... [AVM] FB2 Width=1280, Height=960, Format=0x80e1 (GL_BGRA=0x80e1, GL_BGR=0x80e0), Type=0x1401... FB0 is the default FB of external TDA4: 1920*720 format GL_BGRA (GL_BGRA_EXT), save the image OK FB1 is an FB created internally by myself: 560*720 format GL_BGRA (GL_BGRA_EXT), save the image OK FB2 is another FB created internally by myself: 1280*960 format GL_BGRA (GL_BGRA_EXT), save the image OK The specific video and the results, I will let Fredy forward it to you，Here is just a screenshot",
+    "imageList" : [ "Data/input/1039081/png" ]
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Let me add the setting parameters of Display Node. Is there a problem with these parameter settings, especially the two parameters opMode and pipeId (Can you explain what is the meaning of setting different values for these two parameters? I will also do verification at the same time, See the impact of these different values): display_params.opMode = TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE; display_params.pipeId = 2; display_params.outWidth = SV_DISPLAY_WIDTH; display_params.outHeight = SV_DISPLAY_HEIGHT; display_params.posX = 0; display_params.posY = 0; obj->disp_config = vxCreateUserDataObject(obj->context, \"tivx_display_params_t\", sizeof(tivx_display_params_t), &display_params); status = vxGetStatus((vx_reference)obj->disp_config); obj->displayObj.disp_node = tivxDisplayNode(obj->graph, obj->disp_config, obj->out_img); vxSetNodeTarget(obj->displayObj.disp_node, VX_TARGET_STRING, TIVX_TARGET_DISPLAY1); vxSetReferenceName((vx_reference)obj->displayObj.disp_node, \"Display_node\");",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Share the latest research information: it has a certain relationship with the screen parameter settings. Change the opMode parameter of the display node from TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE to TIVX_KERNEL_DISPLAY_BUFFER_COPY_MODE, the splash screen problem is solved, but the rendering slows down. In other words: using TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE will render faster, but the screen will flick; using TIVX_KERNEL_DISPLAY_BUFFER_COPY_MODE will not flicker, but the rendering will be slower. But this is not enough, rendering is too slow. TDA2 also uses the TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE parameter, which renders quickly without flickering. I still feel that there is a problem, you can continue to research in this direction, and I will continue to research at the same time.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Hello, Thank you for confirming that and sorry for not getting back sooner. We of course need the zero copy mode. Because the copy mode is working fine, I tend to agree that it could be the display side of things that could be out of sync. I will check this internally and get back. In the meanwhile, if there are any updates, please let us know. Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Thanks for the reply. But how to solve this problem? Need help urgently~ Please~ Another more urgent problem is encountered: After AVM is started (GPU rendering), it may cause communication blocking between its own process and the processes of other modules. This is a newly discovered problem.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Hemant Hariyani",
+    "rankPoints" : "8385",
+    "rankName" : "TI__Expert",
+    "date" : "",
+    "userId" : "/members/4658",
+    "content" : "Just to rule something out - can you confirm that you have a glFinish at \"each\" stage of the offscreen and on screen rendering. With three frame buffers, this would mean three glFinish (at least for verifying - ideally, glFinish at the very end should be fine). I am trying to replicate this behavior here on Linux and also discussing with display experts. Regards Hemant",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "I confirm that there is glFinish in \"every\" phase. This problem of off-screen rendering causing splash screen is one of the problems; Another newly discovered problem is that after AVM rendering, it will affect the IPC process communication. This is also explained in another e2e post of mine. Please help and solve it. Thank you, and look forward to your prompt reply.",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "user6426230",
+    "rankPoints" : "80",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6426230",
+    "content" : "Hello, is there any progress now? It's anxious, please. Thanks~",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1040319.json

@@ -0,0 +1,34 @@
+{
+  "ticketNumber" : "1040319",
+  "reporterName" : "Victor Cheng1",
+  "rankPoints" : "390",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA4VM: Does TDA4 ISP support RGB-IR sensor ?",
+  "rankName" : "Intellectual",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 The TDA2/TDA3 vision SDK 3.8 has the demosaicing function implemented on c66x . Was wondering if the TDA4 ISP is flexible enough to avoid using the DSP for such pixel intensive task. regards, Victor",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Mayank Mangla",
+    "rankPoints" : "24525",
+    "rankName" : "TI__Mastermind",
+    "date" : "",
+    "userId" : "/members/13914",
+    "content" : "Hi Victor, There are 2 kinds of RGB-Ir sensors 1. 2x2 CFA : This type is natively supported by TDA4 ISP. Any 2x2 CFA is supported. 2. 4x4 CFA : This requires a pre-processing step similar to what was done on TDA2P and TDA3. Regards, Mayank",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Victor Cheng1",
+    "rankPoints" : "390",
+    "rankName" : "Intellectual",
+    "date" : "",
+    "userId" : "/members/6500211",
+    "content" : "Thanks !",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1041010.json

@@ -0,0 +1,25 @@
+{
+  "ticketNumber" : "1041010",
+  "reporterName" : "Joseph Jubran",
+  "rankPoints" : "10",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2P-ABZ: Does this board support Deep learning accelaration (TIDL)?",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 I'm trying to figure out if our boards will get any speedup from going through the TIDL conversion, on one hand https://training.ti.com/overview-ti-deep-learning-tda2-and-tda3-adas-platforms this link this claim accleration, on the other hand in the TIDL userguide , https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/07_00_00_11/exports/docs/tidl_j7_01_02_00_09/ti_dl/docs/user_guide_html/md_tidl_overview.html, it lists only TD4 as deep learning accelerated. Can anyone shed some info?",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Praveen Eppa1",
+    "rankPoints" : "17580",
+    "rankName" : "TI__Genius",
+    "date" : "",
+    "userId" : "/members/6019814",
+    "content" : "Hi Joseph, TDA2 and TDA3 are old generation boards which can do TIDL conversion, but on these boards there is no active TIDL development and limited support. TDA4 is our new generation more capable device with active TIDL development and also supports huge variety of DL networks with different frameworks. We would suggest to evaluate TDA4 for DL acceleration. Thanks, Praveen",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}

data2/json/DLP/1042093.json

@@ -0,0 +1,34 @@
+{
+  "ticketNumber" : "1042093",
+  "reporterName" : "Dmitry Trots",
+  "rankPoints" : "71",
+  "resolutionStatus" : "",
+  "ticketName" : "TDA2SX: NDK Change static IP configuration",
+  "rankName" : "Prodigy",
+  "replies" : "",
+  "views" : "",
+  "queryText" : "Part Number: TDA2SX Hi, TI Experts! We use TDA2X custom board with PROCESSOR_SDK_RADAR_03_07_00_00 and set up IP configuration in PROCESSOR_SDK_RADAR_03_07_00_00\\vision_sdk\\links_fw\\src\\rtos\\bios_app_common\\tda2xx\\cfg\\NDK_config.cfg Can we change static IP configuration in our application at runtime? Can you advice any examples? Best Regards, Dmitry",
+  "imageList" : null,
+  "partNumber" : "NA",
+  "allResponseList" : [ {
+    "contentId" : "",
+    "userName" : "Stanley Liu",
+    "rankPoints" : "50045",
+    "rankName" : "TI__Guru",
+    "date" : "",
+    "userId" : "/members/22243",
+    "content" : "Hi, Please refer to the below thread. https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/681655/ccs-msp432e401y-how-does-the-udpecho-sample-code-configure-static-ip Regards, Stanley",
+    "imageList" : null
+  }, {
+    "contentId" : "",
+    "userName" : "Dmitry Trots",
+    "rankPoints" : "71",
+    "rankName" : "Prodigy",
+    "date" : "",
+    "userId" : "/members/6696047",
+    "content" : "Thanks a lot!",
+    "imageList" : null
+  } ],
+  "tags" : [ ],
+  "fourmType" : "processors-forum"
+}