asahu-synaptics commited on
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1 Parent(s): a3d92be

Update app.py

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  1. app.py +2 -2
app.py CHANGED
@@ -231,8 +231,8 @@ with gr.Blocks(css=custom_css) as demo:
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  SR100 includes the following on-chip SRAM memories:<br>
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  - 1536 kB of Virtual Memory SRAM (VMEM) for high-speed operations.<br>
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  - 1536 kB of Low Power SRAM (LPMEM) for images, audio, and other less-performance-critical data.<br><br>
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- The amount of memory allocated to the model is customizable. Any memory not allocated to the model is usable by the application.<br><br>
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- For the best performance, ensure that the Arena cache size is smaller than the available VMEM to ensure it fits and runs optimally.
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  </p>
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  """, elem_id="memory_note"
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  )
 
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  SR100 includes the following on-chip SRAM memories:<br>
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  - 1536 kB of Virtual Memory SRAM (VMEM) for high-speed operations.<br>
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  - 1536 kB of Low Power SRAM (LPMEM) for images, audio, and other less-performance-critical data.<br><br>
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+ The amount of memory allocated to the model is customizable. Any memory not allocated to the model is usable by the application.<br>
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+ Ensure that the Arena cache size is smaller than the available VMEM to ensure it fits and runs optimally.
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  </p>
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  """, elem_id="memory_note"
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  )