Question: why vdd is connected to well of pmos?
Answer: When Logic 1 (5V) is applied to gate terminal of NMOS and source is at 0V (Logic 0), transistor is ON since Vgs=5V–0V=5V, source is connected to drain; output load is 0V. ... Similarly PMOS is good at passing logic 1, but pass weak logic 0. Therefore PMOS source is connected to VDD and NMOS source to VSS.