1 Oscillator Enable bit (Timer1 configured for higher power operation)#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)// CONFIG4L#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)#pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))// CONFIG5L#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)#pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)#pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)#pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)// CONFIG5H#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)// CONFIG6L#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)#pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)#pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)#pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)// CONFIG6H#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)// CONFIG7L#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)// CONFIG7H#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)#define _XTAL_FREQ 20000000#include xc.h #include "delays.h"void interrupt high_priority ISR(){ if(TMR0IF) { ClrWdt(); TMR0H = 179; TMR0L = 180; TMR0IF = 0; LATC6 ^= 1; }}void main(void){ ClrWdt(); SWDTEN = 1; INTCON = 0xE0; INTCON2 = 0x74; IPEN = 1; T0CON = 0x87; TMR0H = 179; TMR0L = 180; TRISC = 0; LATC = 0; delay_ms(2000); LATC7 = 1; TMR0IE = 0; while(1);}Como podem ver, todos os #pragma sao responsaveis por direcionar o compilador a gerar o codigo pros bits de configuracao (essa parte nao fica junto com a memoria de programa). Explicando o importante, configurei meu PIC para rodar com Clock externo (HS) a 20 MHz, informado ao compilador em Hertz pelo #define _XTAL_FREQ 20000000. Meu prescaler do WDT ficou em 256, pois 256 x 4 ms = 1024 ms, ou