Repository: pytorch
Issue: triton.codegen_upcast_to_fp32 breaks bitcast/bitwise ops
Labels: triaged,module: type promotion,oncall: pt2,module: inductor

### 🐛 Describe the bug

It seems, that after using a .view(int_dtype) on a float tensor, 
triton.codegen_upcast_to_fp32 (enabled by default) attempts to recast that bitcast int back to a fp32 float.

ablation: inductor

short reproducer:
```python
import torch

@torch.compile(options={"triton.codegen_upcast_to_fp32": False})
def round_down_to_pow2(tensor: torch.Tensor) -> torch.Tensor:
    dtype = tensor.dtype
    tensor_int = tensor.view(torch.int16)
    y = (tensor_int & 0)
    return y.view(dtype)

@torch.compile(options={"triton.codegen_upcast_to_fp32": True})
def round_down_to_pow2_fp32(tensor: torch.Tensor) -> torch.Tensor:
    dtype = tensor.dtype
    tensor_int = tensor.view(torch.int16)
    y = (tensor_int & 0)
    return y.view(dtype)

tensor = torch.tensor(0.5, dtype=torch.bfloat16, device="cuda")
round_down_to_pow2(tensor)
print("non-upcast: success")
#the following fails
round_down_to_pow2_fp32(tensor)
print("upcast: success")
```

original code:
```python
import torch
import triton.language as tl

def compute_exp_only_mask(total_bits, mantissa_bits):
    """Compute a single exponent only mask to clear both the sign and mantissa bits."""
    mantissa_mask = ~(-1 + (1 << mantissa_bits))
    sign_mask = -1 + (1 << (-1 + total_bits))
    return mantissa_mask & sign_mask

def compute_exponent_shift(total_bits, mantissa_bits):
    """Compute the bit position of the exponent for floating-point formats."""
    return mantissa_bits

#use signed int for https://github.com/pytorch/pytorch/issues/58734
DTYPE_MAPPING = {
    torch.float64: {
        'float_dtype': tl.float64,
        'int_dtype': tl.uint64,
        'int_dtype_native': torch.int64,
        'bit_mask': compute_exp_only_mask(64, 52),
        'exponent_shift': compute_exponent_shift(64, 52),
    },
    torch.float32: {
        'float_dtype': tl.float32,
        'int_dtype': tl.uint32,
        'int_dtype_native': torch.int32,
        'bit_mask': compute_exp_only_mask(32, 23),
        'exponent_shift': compute_exponent_shift(32, 23),
    },
    torch.float16: {
        'float_dtype': tl.float16,
        'int_dtype': tl.uint16,
        'int_dtype_native': torch.int16,
        'bit_mask': compute_exp_only_mask(16, 10),
        'exponent_shift': compute_exponent_shift(16, 10),
    },
    torch.bfloat16: {
        'float_dtype': tl.bfloat16,
        'int_dtype': tl.uint16,
        'int_dtype_native': torch.int16,
        'bit_mask': compute_exp_only_mask(16, 7),
        'exponent_shift': compute_exponent_shift(16, 7),
    },
    torch.float8_e4m3fn: {
        'float_dtype': tl.float8e4nv,
        'int_dtype': tl.uint8,
        'int_dtype_native': torch.uint8,
        'bit_mask': compute_exp_only_mask(8, 3),
        'exponent_shift': compute_exponent_shift(8, 3),
    },
    torch.float8_e4m3fnuz: {
        'float_dtype': tl.float8e4b8,
        'int_dtype': tl.uint8,
        'int_dtype_native': torch.uint8,
        'bit_mask': compute_exp_only_mask(8, 3),
        'exponent_shift': compute_exponent_shift(8, 3),
    },
    torch.float8_e5m2: {
        'float_dtype': tl.float8e5,
        'int_dtype': tl.uint8,
        'int_dtype_native': torch.uint8,
        'bit_mask': compute_exp_only_mask(8, 2),
        'exponent_shift': compute_exponent_shift(8, 2),
    },
    torch.float8_e5m2fnuz: {
        'float_dtype': tl.float8e5b16,
        'int_dtype': tl.uint8,
        'int_dtype_native': torch.uint8,
        'bit_mask': compute_exp_only_mask(8, 2),
        'exponent_shift': compute_exponent_shift(8, 2),
    },
}

@torch.compile(options={"triton.codegen_upcast_to_fp32": False})
def round_down_to_pow2(tensor: torch.Tensor) -> torch.Tensor:
    dtype = tensor.dtype
    mapping = DTYPE_MAPPING[dtype]
    int_dtype = mapping['int_dtype_native']
    bit_mask = mapping['bit_mask']
    tensor_int = tensor.view(int_dtype)
    y = (tensor_int & bit_mask)
    return y.view(dtype)

@torch.compile(options={"triton.codegen_upcast_to_fp32": False})
def round_down_down_to_pow2(tensor: torch.Tensor) -> torch.Tensor:
    dtype = tensor.dtype
    mapping = DTYPE_MAPPING[dtype]
    int_dtype = mapping['int_dtype_native']
    bit_mask = mapping['bit_mask']
    exponent_shift = mapping['exponent_shift']
    tensor_int = tensor.view(int_dtype)
    rounded_bits = (tensor_int & bit_mask)
    exponent = rounded_bits >> exponent_shift
    # exponent = torch.where(exponent > 0, -1 + exponent, exponent) << exponent_shift
    exponent = exponent - (exponent > 0).to(dtype=exponent.dtype)
    y = exponent << exponent_shift
    return y.view(dtype)

@torch.compile(options={"triton.codegen_upcast_to_fp32": True})
def round_down_to_pow2_fp32(tensor: torch.Tensor) -> torch.Tensor:
    dtype = tensor.dtype
    mapping = DTYPE_MAPPING[dtype]
    int_dtype = mapping['int_dtype_native']
    bit_mask = mapping['bit_mask']
    tensor_int = tensor.view(int_dtype)
    y = (tensor_int & bit_mask)
    return y.view(dtype)

@torch.compile(options={"triton.codegen_upcast_to_fp32": True})
def round_down_down_to_pow2_fp32(tensor: torch.Tensor) -> torch.Tensor:
    dtype = tensor.dtype
    mapping = DTYPE_MAPPING[dtype]
    int_dtype = mapping['int_dtype_native']
    bit_mask = mapping['bit_mask']
    exponent_shift = mapping['exponent_shift']
    tensor_int = tensor.view(int_dtype)
    rounded_bits = (tensor_int & bit_mask)
    exponent = rounded_bits >> exponent_shift
    # exponent = torch.where(exponent > 0, -1 + exponent, exponent) << exponent_shift
    exponent = exponent - (exponent > 0).to(dtype=exponent.dtype)
    y = exponent << exponent_shift
    return y.view(dtype)

tensor = torch.tensor(0.5, dtype=torch.bfloat16, device="cuda")
round_down_to_pow2(tensor)
round_down_down_to_pow2(tensor)
print("non-upcast: success")
#the following fails
round_down_to_pow2_fp32(tensor)
round_down_down_to_pow2_fp32(tensor)
print("upcast: success")
```

tlparse:
[dedicated_log_torch_trace_ooo_n_47.log](https://github.com/user-attachments/files/18243852/dedicated_log_torch_trace_ooo_n_47.log)

### Error logs

```python
torch._dynamo.exc.BackendCompilerFailed: backend='inductor' raised:
CompilationError: at 10:11:
def triton_poi_fused_bitwise_and_0(in_ptr0, out_ptr1, xnumel, XBLOCK : tl.constexpr):
    xnumel = 1
    xoffset = tl.program_id(0) * XBLOCK
    xindex = xoffset + tl.arange(0, XBLOCK)[:]
    xmask = tl.full([XBLOCK], True, tl.int1)
    tmp0 = tl.load(in_ptr0 + (0)).to(tl.float32)
    tmp1 = tl.broadcast_to(tmp0, [XBLOCK])
    tmp2 = tmp1.to(tl.bfloat16).to(tl.int16, bitcast=True).to(tl.float32)
    tmp3 = tl.full([1], 32640, tl.int16)
    tmp4 = tmp2 & tmp3
           ^
IncompatibleTypeErrorImpl('invalid operands of type triton.language.float32 and triton.language.float32')
```

### Versions

Collecting environment information...
PyTorch version: 2.6.0.dev20241127+cu124
Is debug build: False
CUDA used to build PyTorch: 12.4
ROCM used to build PyTorch: N/A

OS: Arch Linux (x86_64)
GCC version: (GCC) 14.2.1 20240910
Clang version: 18.1.8
CMake version: version 3.30.3
Libc version: glibc-2.40

Python version: 3.11.10 (main, Sep  9 2024, 22:11:19) [Clang 18.1.8 ] (64-bit runtime)
Python platform: Linux-6.6.43-273-tkg-bore-x86_64-with-glibc2.40
Is CUDA available: True
CUDA runtime version: 12.6.68
CUDA_MODULE_LOADING set to: LAZY
GPU models and configuration: 
GPU 0: NVIDIA RTX 6000 Ada Generation
GPU 1: NVIDIA RTX 6000 Ada Generation

Nvidia driver version: 560.35.03
cuDNN version: Probably one of the following:
/usr/lib/libcudnn.so.9.2.1
/usr/lib/libcudnn_adv.so.9.2.1
/usr/lib/libcudnn_cnn.so.9.2.1
/usr/lib/libcudnn_engines_precompiled.so.9.2.1
/usr/lib/libcudnn_engines_runtime_compiled.so.9.2.1
/usr/lib/libcudnn_graph.so.9.2.1
/usr/lib/libcudnn_heuristic.so.9.2.1
/usr/lib/libcudnn_ops.so.9.2.1
HIP runtime version: N/A
MIOpen runtime version: N/A
Is XNNPACK available: True

CPU:
Architecture:                         x86_64
CPU op-mode(s):                       32-bit, 64-bit
Address sizes:                        46 bits physical, 48 bits virtual
Byte Order:                           Little Endian
CPU(s):                               24
On-line CPU(s) list:                  0-23
Vendor ID:                            GenuineIntel
Model name:                           12th Gen Intel(R) Core(TM) i9-12900K
CPU family:                           6
Model:                                151
Thread(s) per core:                   2
Core(s) per socket:                   16
Socket(s):                            1
Stepping:                             2
CPU(s) scaling MHz:                   24%
CPU max MHz:                          5300.0000
CPU min MHz:                          800.0000
BogoMIPS:                             6374.40
Flags:                                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid rdseed adx smap clflushopt clwb intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves split_lock_detect user_shstk avx_vnni dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req hfi vnmi umip pku ospke waitpkg gfni vaes vpclmulqdq tme rdpid movdiri movdir64b fsrm md_clear serialize pconfig arch_lbr ibt flush_l1d arch_capabilities
Virtualization:                       VT-x
L1d cache:                            640 KiB (16 instances)
L1i cache:                            768 KiB (16 instances)
L2 cache:                             14 MiB (10 instances)
L3 cache:                             30 MiB (1 instance)
NUMA node(s):                         1
NUMA node0 CPU(s):                    0-23
Vulnerability Gather data sampling:   Not affected
Vulnerability Itlb multihit:          Not affected
Vulnerability L1tf:                   Not affected
Vulnerability Mds:                    Not affected
Vulnerability Meltdown:               Not affected
Vulnerability Mmio stale data:        Not affected
Vulnerability Reg file data sampling: Mitigation; Clear Register File
Vulnerability Retbleed:               Not affected
Vulnerability Spec rstack overflow:   Not affected
Vulnerability Spec store bypass:      Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1:             Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:             Mitigation; Enhanced / Automatic IBRS; IBPB conditional; RSB filling; PBRSB-eIBRS SW sequence; BHI BHI_DIS_S
Vulnerability Srbds:                  Not affected
Vulnerability Tsx async abort:        Not affected

Versions of relevant libraries:
[pip3] numpy==2.1.3
[pip3] nvidia-cublas-cu12==12.4.5.8
[pip3] nvidia-cuda-cupti-cu12==12.4.127
[pip3] nvidia-cuda-nvrtc-cu12==12.4.127
[pip3] nvidia-cuda-runtime-cu12==12.4.127
[pip3] nvidia-cudnn-cu12==9.1.0.70
[pip3] nvidia-cufft-cu12==11.2.1.3
[pip3] nvidia-curand-cu12==10.3.5.147
[pip3] nvidia-cusolver-cu12==11.6.1.9
[pip3] nvidia-cusparse-cu12==12.3.1.170
[pip3] nvidia-cusparselt-cu12==0.6.2
[pip3] nvidia-nccl-cu12==2.21.5
[pip3] nvidia-nvjitlink-cu12==12.4.127
[pip3] nvidia-nvtx-cu12==12.4.127
[pip3] pytorch-triton==3.2.0+git35c6c7c6
[pip3] torch==2.6.0.dev20241127+cu124
[pip3] torch-optimi==0.2.1
[pip3] torch-xla==2.5.0
[pip3] torchaudio==2.5.1
[pip3] torchvision==0.20.1
[pip3] triton==3.1.0
[pip3] triton-nightly==3.0.0.post20240716052845
[conda] No relevant packages


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