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1.05M
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`timescale 1ns / 1ps
`timescale 1ns / 1ps
module ymplayer(
input clk50,
input rst,
// sound
output reg speaker_left,
output reg speaker_right,
// switches
input [3:0] sw_sel, //
input send_data, // 1=Send music over UART, 0=stop
// UART wires
input uart_rx,
output uart_tx,
output [7:0] led
);
wire locked, rst_clk, rst_clk50;
// Send data
reg [9:0] send_data_shr;
wire send_data_s = &send_data_shr;
always @(posedge clk50)
send_data_shr <= { send_data_shr[8:0], send_data };
wire E, Q, clk_dac;
clocks u_clocks(
.rst ( rst ),
.clk50 ( clk50 ),
.locked ( locked ),
.divide_more( send_data_s ),
//.clk_cpu( clk ),
.clk_dac( clk_dac ),
.clk_dac_sel( sw_sel[1] ),
.E ( E ),
.Q ( Q )
);
wire cpu_rw;
wire AVMA;
//wire BS, BA, BUSY, LIC;
wire clk_per = E; // mc6809i
wire cpu_rst_req;
rst_sync u_rst1(
.rst_in ( rst|(~locked)|cpu_rst_req ),
.clk ( Q ),
.rst_out( rst_clk )
);
/*
rst_sync u_rst2(
.rst_in ( rst_clk ),
.clk ( clk_dac ),
.rst_out( rst_fast )
);
*/
rst_sync u_rst50(
.rst_in ( rst|(~locked) ),
.clk ( clk50 ),
.rst_out( rst_clk50 )
);
wire [7:0] cpu_data_in, cpu_data_out;
wire [15:0] cpu_addr;
wire [7:0]jt_data_out;
wire jt_sample;
// JT51
`ifndef NOJT
wire signed [15:0] direct_l, direct_r;
jt51 u_jt51(
.clk ( clk_per ),
.rst ( rst_clk ),
.cs_n ( jt_cs_n ), // chip select
.wr_n ( cpu_rw ), // write
.a0 ( cpu_addr[0] ),
.d_in ( cpu_data_out ), // data in
.d_out ( jt_data_out ), // data out
.irq_n ( jt_irq_n ),
// uso salidas exactas para el DAC
.sample ( jt_sample ),
.xleft ( direct_l ),
.xright ( direct_r )
);
wire [15:0] inter_l, inter_r;
jt51_interpol i_jt51_interpol (
.clk (clk50 ),
.rst (rst ),
.sample_in (jt_sample ),
.left_in (direct_l ),
.right_in (direct_r ),
.left_other (16'd0 ),
.right_other(16'd0 ),
.out_l (inter_l ),
.out_r (inter_r ),
.sample_out (fir_sample )
);
reg [15:0] dacin_l, dacin_r;
always @(posedge clk_dac)
if( sw_sel[2] ) begin
dacin_l <= inter_l;
dacin_r <= inter_r;
end
else begin
dacin_l <= direct_l;
dacin_r <= direct_r;
end
wire dac2_l, dac2_r;
wire dacmist_l, dacmist_r;
speaker u_speaker(
.clk100 ( clk_dac ),
.left_in ( dacin_l ),
.right_in ( dacin_r ),
.left_out ( dacmist_l ),
.right_out ( dacmist_r )
);
always @(posedge clk_per)
if( sw_sel[3] ) begin
speaker_left <= dac2_l;
speaker_right<= dac2_r;
end
else begin
speaker_left<= dacmist_l;
speaker_right<=dacmist_r;
end
jt51_dac2 i_jt51_dac2_l (.clk(clk_dac), .rst(rst), .din(dacin_l), .dout(dac2_l));
jt51_dac2 i_jt51_dac2_r (.clk(clk_dac), .rst(rst), .din(dacin_r), .dout(dac2_r));
`else
wire jt_irq_n = 1'b1;
wire [15:0] dacin_l = 16'd0, dacin_r=16'd0;
`endif
parameter RAM_MSB = 10; // 10 for Contra;
wire [7:0] ROM_data_out, RAM_data;
wire fsm_wr;
wire [ 7:0] fsm_data;
wire [14:0] fsm_addr;
wire rom_prog;
//synthesis attribute box_type ram32 "black_box"
ram32 ROM( // 32kb
.clka ( clk_per ),
.dina ( fsm_data ),
.wea ( fsm_wr ),
.douta ( ROM_data_out ),
.addra ( rom_prog ? fsm_addr : cpu_addr[14:0])
);
//synthesis attribute box_type ram2 "black_box"
ram2 RAM( // 2kb
.clka ( clk_per ),
.dina ( cpu_data_out ),
.douta ( RAM_data ),
.addra ( cpu_addr[RAM_MSB:0] ),
.ena ( RAM_cs ),
.wea ( ~cpu_rw )
);
wire [7:0] sound_latch;
wire clear_irq;
assign led = rom_prog ? fsm_addr[14:7] : sound_latch;
fsm_control fsm_ctrl(
.clk ( clk50 ),
.clk_cpu ( E ),
.rst ( rst_clk50 ),
// Sound
.sound_latch(sound_latch),
.jt_left ( dacin_l ),
.jt_right ( dacin_r ),
.jt_sample ( jt_sample ),
.irq ( irq ),
.clear_irq ( clear_irq ),
// Programming
.cpu_rst ( cpu_rst_req),
.rom_prog ( rom_prog ),
.rom_wr ( fsm_wr ),
.rom_addr ( fsm_addr ),
.rom_data ( fsm_data ),
// UART wires
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx )
);
reg cpu_vma;
always @(negedge E)
cpu_vma <= AVMA;
bus_manager #(RAM_MSB) bus_mng(
// .rst50 ( rst_clk50 ),
// .clk50 ( clk50 ),
// .clk_per ( clk_per ),
.game_sel ( sw_sel[0] ),
.ROM_data_out ( ROM_data_out ),
.RAM_data ( RAM_data ),
.sound_latch ( sound_latch ),
.clear_irq ( clear_irq ),
// .cpu_data_out ( cpu_data_out ),
.jt_data_out ( jt_data_out ),
//
.cpu_data_in ( cpu_data_in ),
.cpu_rw ( cpu_rw ),
.addr ( cpu_addr ),
.cpu_vma ( cpu_vma ),
.RAM_cs ( RAM_cs ),
.opm_cs_n ( jt_cs_n )
);
`ifndef NOCPU
wire cpu_firq_n = sw_sel[0] ? jt_irq_n : 1'b1;
mc6809i cpu_good(
.D ( cpu_data_in ),
.DOut ( cpu_data_out ),
.ADDR ( cpu_addr ),
.RnW ( cpu_rw ),
// .BS ( BS ),
// .BA ( BA ),
.nIRQ ( ~irq ),
.nFIRQ ( cpu_firq_n ),
.nNMI ( 1'b1 ),
.AVMA ( AVMA ),
// .BUSY ( BUSY ),
// .LIC ( LIC ),
.nRESET ( ~rst_clk ),
.nHALT ( 1'b1 ),
.nDMABREQ( 1'b1 ),
.E ( E ),
.Q ( Q )
);
`endif
endmodule
|
`include "senior_defines.vh"
module mac_scale
(input wire signed [39:0] to_scaling,
input wire [2:0] c_scalefactor,
output wire scale_overflow,
output reg [39:0] from_scaling);
reg scale_pos_overflow;
reg scale_neg_overflow;
assign scale_overflow = scale_neg_overflow | scale_pos_overflow;
// Mux for scaling
always@(*) begin
scale_pos_overflow = 0;
scale_neg_overflow = 0;
case (c_scalefactor)
3'b000: begin
from_scaling=to_scaling; // *1
end
3'b001: begin
from_scaling=to_scaling << 1; // *2
scale_pos_overflow = ~to_scaling[39] & to_scaling[38];
scale_neg_overflow = to_scaling[39] & ~to_scaling[38];
end
3'b010: begin
from_scaling=to_scaling << 2; // *4
scale_pos_overflow = ~to_scaling[39] & (|to_scaling[38:37]);
scale_neg_overflow = to_scaling[39] & ~(&to_scaling[38:37]);
end
3'b011: begin
from_scaling={to_scaling[39],to_scaling[39:1]}; // *0.5
end
3'b100: begin
from_scaling={{2{to_scaling[39]}},to_scaling[39:2]}; // *0.25
end
3'b101: begin
from_scaling={{3{to_scaling[39]}},to_scaling[39:3]}; // *0.125
end
3'b110: begin
from_scaling={{4{to_scaling[39]}},to_scaling[39:4]}; // *0.0625
end
3'b111: begin
from_scaling=to_scaling << 16; // *2^16
scale_pos_overflow = ~to_scaling[39] & (|to_scaling[38:23]);
scale_neg_overflow = to_scaling[39] & ~(&to_scaling[38:23]);
end
endcase
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file FifoCore32w8r.v when simulating
// the core, FifoCore32w8r. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module FifoCore32w8r(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full,
prog_empty
);
input rst;
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
output prog_full;
output prog_empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(511),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(512),
.C_PROG_EMPTY_TYPE(1),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(384),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(383),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(11),
.C_RD_DEPTH(2048),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(11),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.PROG_EMPTY(prog_empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9234_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [63:0] adc_data;
input adc_or;
// channel interface
output [63:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9234_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// THIS FILE IS AUTOGENERATED BY wb_intercon_gen
// ANY MANUAL CHANGES WILL BE LOST
module wb_intercon
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_iwmb_adr_i,
input [31:0] wb_iwmb_dat_i,
input [3:0] wb_iwmb_sel_i,
input wb_iwmb_we_i,
input wb_iwmb_cyc_i,
input wb_iwmb_stb_i,
input [2:0] wb_iwmb_cti_i,
input [1:0] wb_iwmb_bte_i,
output [31:0] wb_iwmb_dat_o,
output wb_iwmb_ack_o,
output wb_iwmb_err_o,
output wb_iwmb_rty_o,
input [31:0] wb_dwmb_adr_i,
input [31:0] wb_dwmb_dat_i,
input [3:0] wb_dwmb_sel_i,
input wb_dwmb_we_i,
input wb_dwmb_cyc_i,
input wb_dwmb_stb_i,
input [2:0] wb_dwmb_cti_i,
input [1:0] wb_dwmb_bte_i,
output [31:0] wb_dwmb_dat_o,
output wb_dwmb_ack_o,
output wb_dwmb_err_o,
output wb_dwmb_rty_o,
output [31:0] wb_uart_adr_o,
output [31:0] wb_uart_dat_o,
output [3:0] wb_uart_sel_o,
output wb_uart_we_o,
output wb_uart_cyc_o,
output wb_uart_stb_o,
output [2:0] wb_uart_cti_o,
output [1:0] wb_uart_bte_o,
input [31:0] wb_uart_dat_i,
input wb_uart_ack_i,
input wb_uart_err_i,
input wb_uart_rty_i,
output [31:0] wb_ram_adr_o,
output [31:0] wb_ram_dat_o,
output [3:0] wb_ram_sel_o,
output wb_ram_we_o,
output wb_ram_cyc_o,
output wb_ram_stb_o,
output [2:0] wb_ram_cti_o,
output [1:0] wb_ram_bte_o,
input [31:0] wb_ram_dat_i,
input wb_ram_ack_i,
input wb_ram_err_i,
input wb_ram_rty_i,
output [31:0] wb_rom_adr_o,
output [31:0] wb_rom_dat_o,
output [3:0] wb_rom_sel_o,
output wb_rom_we_o,
output wb_rom_cyc_o,
output wb_rom_stb_o,
output [2:0] wb_rom_cti_o,
output [1:0] wb_rom_bte_o,
input [31:0] wb_rom_dat_i,
input wb_rom_ack_i,
input wb_rom_err_i,
input wb_rom_rty_i,
output [31:0] wb_fw_interface_adr_o,
output [31:0] wb_fw_interface_dat_o,
output [3:0] wb_fw_interface_sel_o,
output wb_fw_interface_we_o,
output wb_fw_interface_cyc_o,
output wb_fw_interface_stb_o,
output [2:0] wb_fw_interface_cti_o,
output [1:0] wb_fw_interface_bte_o,
input [31:0] wb_fw_interface_dat_i,
input wb_fw_interface_ack_i,
input wb_fw_interface_err_i,
input wb_fw_interface_rty_i);
wire [31:0] wb_m2s_iwmb_ram_adr;
wire [31:0] wb_m2s_iwmb_ram_dat;
wire [3:0] wb_m2s_iwmb_ram_sel;
wire wb_m2s_iwmb_ram_we;
wire wb_m2s_iwmb_ram_cyc;
wire wb_m2s_iwmb_ram_stb;
wire [2:0] wb_m2s_iwmb_ram_cti;
wire [1:0] wb_m2s_iwmb_ram_bte;
wire [31:0] wb_s2m_iwmb_ram_dat;
wire wb_s2m_iwmb_ram_ack;
wire wb_s2m_iwmb_ram_err;
wire wb_s2m_iwmb_ram_rty;
wire [31:0] wb_m2s_iwmb_rom_adr;
wire [31:0] wb_m2s_iwmb_rom_dat;
wire [3:0] wb_m2s_iwmb_rom_sel;
wire wb_m2s_iwmb_rom_we;
wire wb_m2s_iwmb_rom_cyc;
wire wb_m2s_iwmb_rom_stb;
wire [2:0] wb_m2s_iwmb_rom_cti;
wire [1:0] wb_m2s_iwmb_rom_bte;
wire [31:0] wb_s2m_iwmb_rom_dat;
wire wb_s2m_iwmb_rom_ack;
wire wb_s2m_iwmb_rom_err;
wire wb_s2m_iwmb_rom_rty;
wire [31:0] wb_m2s_iwmb_uart_adr;
wire [31:0] wb_m2s_iwmb_uart_dat;
wire [3:0] wb_m2s_iwmb_uart_sel;
wire wb_m2s_iwmb_uart_we;
wire wb_m2s_iwmb_uart_cyc;
wire wb_m2s_iwmb_uart_stb;
wire [2:0] wb_m2s_iwmb_uart_cti;
wire [1:0] wb_m2s_iwmb_uart_bte;
wire [31:0] wb_s2m_iwmb_uart_dat;
wire wb_s2m_iwmb_uart_ack;
wire wb_s2m_iwmb_uart_err;
wire wb_s2m_iwmb_uart_rty;
wire [31:0] wb_m2s_iwmb_fw_interface_adr;
wire [31:0] wb_m2s_iwmb_fw_interface_dat;
wire [3:0] wb_m2s_iwmb_fw_interface_sel;
wire wb_m2s_iwmb_fw_interface_we;
wire wb_m2s_iwmb_fw_interface_cyc;
wire wb_m2s_iwmb_fw_interface_stb;
wire [2:0] wb_m2s_iwmb_fw_interface_cti;
wire [1:0] wb_m2s_iwmb_fw_interface_bte;
wire [31:0] wb_s2m_iwmb_fw_interface_dat;
wire wb_s2m_iwmb_fw_interface_ack;
wire wb_s2m_iwmb_fw_interface_err;
wire wb_s2m_iwmb_fw_interface_rty;
wire [31:0] wb_m2s_dwmb_uart_adr;
wire [31:0] wb_m2s_dwmb_uart_dat;
wire [3:0] wb_m2s_dwmb_uart_sel;
wire wb_m2s_dwmb_uart_we;
wire wb_m2s_dwmb_uart_cyc;
wire wb_m2s_dwmb_uart_stb;
wire [2:0] wb_m2s_dwmb_uart_cti;
wire [1:0] wb_m2s_dwmb_uart_bte;
wire [31:0] wb_s2m_dwmb_uart_dat;
wire wb_s2m_dwmb_uart_ack;
wire wb_s2m_dwmb_uart_err;
wire wb_s2m_dwmb_uart_rty;
wire [31:0] wb_m2s_dwmb_ram_adr;
wire [31:0] wb_m2s_dwmb_ram_dat;
wire [3:0] wb_m2s_dwmb_ram_sel;
wire wb_m2s_dwmb_ram_we;
wire wb_m2s_dwmb_ram_cyc;
wire wb_m2s_dwmb_ram_stb;
wire [2:0] wb_m2s_dwmb_ram_cti;
wire [1:0] wb_m2s_dwmb_ram_bte;
wire [31:0] wb_s2m_dwmb_ram_dat;
wire wb_s2m_dwmb_ram_ack;
wire wb_s2m_dwmb_ram_err;
wire wb_s2m_dwmb_ram_rty;
wire [31:0] wb_m2s_dwmb_rom_adr;
wire [31:0] wb_m2s_dwmb_rom_dat;
wire [3:0] wb_m2s_dwmb_rom_sel;
wire wb_m2s_dwmb_rom_we;
wire wb_m2s_dwmb_rom_cyc;
wire wb_m2s_dwmb_rom_stb;
wire [2:0] wb_m2s_dwmb_rom_cti;
wire [1:0] wb_m2s_dwmb_rom_bte;
wire [31:0] wb_s2m_dwmb_rom_dat;
wire wb_s2m_dwmb_rom_ack;
wire wb_s2m_dwmb_rom_err;
wire wb_s2m_dwmb_rom_rty;
wire [31:0] wb_m2s_dwmb_fw_interface_adr;
wire [31:0] wb_m2s_dwmb_fw_interface_dat;
wire [3:0] wb_m2s_dwmb_fw_interface_sel;
wire wb_m2s_dwmb_fw_interface_we;
wire wb_m2s_dwmb_fw_interface_cyc;
wire wb_m2s_dwmb_fw_interface_stb;
wire [2:0] wb_m2s_dwmb_fw_interface_cti;
wire [1:0] wb_m2s_dwmb_fw_interface_bte;
wire [31:0] wb_s2m_dwmb_fw_interface_dat;
wire wb_s2m_dwmb_fw_interface_ack;
wire wb_s2m_dwmb_fw_interface_err;
wire wb_s2m_dwmb_fw_interface_rty;
wb_mux
#(.num_slaves (4),
.MATCH_ADDR ({32'h20000000, 32'h00000000, 32'h40000000, 32'he0000000}),
.MATCH_MASK ({32'hffff8000, 32'hffff8000, 32'hffffffe0, 32'hffffff80}))
wb_mux_iwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_iwmb_adr_i),
.wbm_dat_i (wb_iwmb_dat_i),
.wbm_sel_i (wb_iwmb_sel_i),
.wbm_we_i (wb_iwmb_we_i),
.wbm_cyc_i (wb_iwmb_cyc_i),
.wbm_stb_i (wb_iwmb_stb_i),
.wbm_cti_i (wb_iwmb_cti_i),
.wbm_bte_i (wb_iwmb_bte_i),
.wbm_dat_o (wb_iwmb_dat_o),
.wbm_ack_o (wb_iwmb_ack_o),
.wbm_err_o (wb_iwmb_err_o),
.wbm_rty_o (wb_iwmb_rty_o),
.wbs_adr_o ({wb_m2s_iwmb_ram_adr, wb_m2s_iwmb_rom_adr, wb_m2s_iwmb_uart_adr, wb_m2s_iwmb_fw_interface_adr}),
.wbs_dat_o ({wb_m2s_iwmb_ram_dat, wb_m2s_iwmb_rom_dat, wb_m2s_iwmb_uart_dat, wb_m2s_iwmb_fw_interface_dat}),
.wbs_sel_o ({wb_m2s_iwmb_ram_sel, wb_m2s_iwmb_rom_sel, wb_m2s_iwmb_uart_sel, wb_m2s_iwmb_fw_interface_sel}),
.wbs_we_o ({wb_m2s_iwmb_ram_we, wb_m2s_iwmb_rom_we, wb_m2s_iwmb_uart_we, wb_m2s_iwmb_fw_interface_we}),
.wbs_cyc_o ({wb_m2s_iwmb_ram_cyc, wb_m2s_iwmb_rom_cyc, wb_m2s_iwmb_uart_cyc, wb_m2s_iwmb_fw_interface_cyc}),
.wbs_stb_o ({wb_m2s_iwmb_ram_stb, wb_m2s_iwmb_rom_stb, wb_m2s_iwmb_uart_stb, wb_m2s_iwmb_fw_interface_stb}),
.wbs_cti_o ({wb_m2s_iwmb_ram_cti, wb_m2s_iwmb_rom_cti, wb_m2s_iwmb_uart_cti, wb_m2s_iwmb_fw_interface_cti}),
.wbs_bte_o ({wb_m2s_iwmb_ram_bte, wb_m2s_iwmb_rom_bte, wb_m2s_iwmb_uart_bte, wb_m2s_iwmb_fw_interface_bte}),
.wbs_dat_i ({wb_s2m_iwmb_ram_dat, wb_s2m_iwmb_rom_dat, wb_s2m_iwmb_uart_dat, wb_s2m_iwmb_fw_interface_dat}),
.wbs_ack_i ({wb_s2m_iwmb_ram_ack, wb_s2m_iwmb_rom_ack, wb_s2m_iwmb_uart_ack, wb_s2m_iwmb_fw_interface_ack}),
.wbs_err_i ({wb_s2m_iwmb_ram_err, wb_s2m_iwmb_rom_err, wb_s2m_iwmb_uart_err, wb_s2m_iwmb_fw_interface_err}),
.wbs_rty_i ({wb_s2m_iwmb_ram_rty, wb_s2m_iwmb_rom_rty, wb_s2m_iwmb_uart_rty, wb_s2m_iwmb_fw_interface_rty}));
wb_mux
#(.num_slaves (4),
.MATCH_ADDR ({32'h40000000, 32'h20000000, 32'h00000000, 32'he0000000}),
.MATCH_MASK ({32'hffffffe0, 32'hffff8000, 32'hffff8000, 32'hffffff80}))
wb_mux_dwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_dwmb_adr_i),
.wbm_dat_i (wb_dwmb_dat_i),
.wbm_sel_i (wb_dwmb_sel_i),
.wbm_we_i (wb_dwmb_we_i),
.wbm_cyc_i (wb_dwmb_cyc_i),
.wbm_stb_i (wb_dwmb_stb_i),
.wbm_cti_i (wb_dwmb_cti_i),
.wbm_bte_i (wb_dwmb_bte_i),
.wbm_dat_o (wb_dwmb_dat_o),
.wbm_ack_o (wb_dwmb_ack_o),
.wbm_err_o (wb_dwmb_err_o),
.wbm_rty_o (wb_dwmb_rty_o),
.wbs_adr_o ({wb_m2s_dwmb_uart_adr, wb_m2s_dwmb_ram_adr, wb_m2s_dwmb_rom_adr, wb_m2s_dwmb_fw_interface_adr}),
.wbs_dat_o ({wb_m2s_dwmb_uart_dat, wb_m2s_dwmb_ram_dat, wb_m2s_dwmb_rom_dat, wb_m2s_dwmb_fw_interface_dat}),
.wbs_sel_o ({wb_m2s_dwmb_uart_sel, wb_m2s_dwmb_ram_sel, wb_m2s_dwmb_rom_sel, wb_m2s_dwmb_fw_interface_sel}),
.wbs_we_o ({wb_m2s_dwmb_uart_we, wb_m2s_dwmb_ram_we, wb_m2s_dwmb_rom_we, wb_m2s_dwmb_fw_interface_we}),
.wbs_cyc_o ({wb_m2s_dwmb_uart_cyc, wb_m2s_dwmb_ram_cyc, wb_m2s_dwmb_rom_cyc, wb_m2s_dwmb_fw_interface_cyc}),
.wbs_stb_o ({wb_m2s_dwmb_uart_stb, wb_m2s_dwmb_ram_stb, wb_m2s_dwmb_rom_stb, wb_m2s_dwmb_fw_interface_stb}),
.wbs_cti_o ({wb_m2s_dwmb_uart_cti, wb_m2s_dwmb_ram_cti, wb_m2s_dwmb_rom_cti, wb_m2s_dwmb_fw_interface_cti}),
.wbs_bte_o ({wb_m2s_dwmb_uart_bte, wb_m2s_dwmb_ram_bte, wb_m2s_dwmb_rom_bte, wb_m2s_dwmb_fw_interface_bte}),
.wbs_dat_i ({wb_s2m_dwmb_uart_dat, wb_s2m_dwmb_ram_dat, wb_s2m_dwmb_rom_dat, wb_s2m_dwmb_fw_interface_dat}),
.wbs_ack_i ({wb_s2m_dwmb_uart_ack, wb_s2m_dwmb_ram_ack, wb_s2m_dwmb_rom_ack, wb_s2m_dwmb_fw_interface_ack}),
.wbs_err_i ({wb_s2m_dwmb_uart_err, wb_s2m_dwmb_ram_err, wb_s2m_dwmb_rom_err, wb_s2m_dwmb_fw_interface_err}),
.wbs_rty_i ({wb_s2m_dwmb_uart_rty, wb_s2m_dwmb_ram_rty, wb_s2m_dwmb_rom_rty, wb_s2m_dwmb_fw_interface_rty}));
wb_arbiter
#(.num_masters (2))
wb_arbiter_uart
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_uart_adr, wb_m2s_dwmb_uart_adr}),
.wbm_dat_i ({wb_m2s_iwmb_uart_dat, wb_m2s_dwmb_uart_dat}),
.wbm_sel_i ({wb_m2s_iwmb_uart_sel, wb_m2s_dwmb_uart_sel}),
.wbm_we_i ({wb_m2s_iwmb_uart_we, wb_m2s_dwmb_uart_we}),
.wbm_cyc_i ({wb_m2s_iwmb_uart_cyc, wb_m2s_dwmb_uart_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_uart_stb, wb_m2s_dwmb_uart_stb}),
.wbm_cti_i ({wb_m2s_iwmb_uart_cti, wb_m2s_dwmb_uart_cti}),
.wbm_bte_i ({wb_m2s_iwmb_uart_bte, wb_m2s_dwmb_uart_bte}),
.wbm_dat_o ({wb_s2m_iwmb_uart_dat, wb_s2m_dwmb_uart_dat}),
.wbm_ack_o ({wb_s2m_iwmb_uart_ack, wb_s2m_dwmb_uart_ack}),
.wbm_err_o ({wb_s2m_iwmb_uart_err, wb_s2m_dwmb_uart_err}),
.wbm_rty_o ({wb_s2m_iwmb_uart_rty, wb_s2m_dwmb_uart_rty}),
.wbs_adr_o (wb_uart_adr_o),
.wbs_dat_o (wb_uart_dat_o),
.wbs_sel_o (wb_uart_sel_o),
.wbs_we_o (wb_uart_we_o),
.wbs_cyc_o (wb_uart_cyc_o),
.wbs_stb_o (wb_uart_stb_o),
.wbs_cti_o (wb_uart_cti_o),
.wbs_bte_o (wb_uart_bte_o),
.wbs_dat_i (wb_uart_dat_i),
.wbs_ack_i (wb_uart_ack_i),
.wbs_err_i (wb_uart_err_i),
.wbs_rty_i (wb_uart_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_ram
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_ram_adr, wb_m2s_dwmb_ram_adr}),
.wbm_dat_i ({wb_m2s_iwmb_ram_dat, wb_m2s_dwmb_ram_dat}),
.wbm_sel_i ({wb_m2s_iwmb_ram_sel, wb_m2s_dwmb_ram_sel}),
.wbm_we_i ({wb_m2s_iwmb_ram_we, wb_m2s_dwmb_ram_we}),
.wbm_cyc_i ({wb_m2s_iwmb_ram_cyc, wb_m2s_dwmb_ram_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_ram_stb, wb_m2s_dwmb_ram_stb}),
.wbm_cti_i ({wb_m2s_iwmb_ram_cti, wb_m2s_dwmb_ram_cti}),
.wbm_bte_i ({wb_m2s_iwmb_ram_bte, wb_m2s_dwmb_ram_bte}),
.wbm_dat_o ({wb_s2m_iwmb_ram_dat, wb_s2m_dwmb_ram_dat}),
.wbm_ack_o ({wb_s2m_iwmb_ram_ack, wb_s2m_dwmb_ram_ack}),
.wbm_err_o ({wb_s2m_iwmb_ram_err, wb_s2m_dwmb_ram_err}),
.wbm_rty_o ({wb_s2m_iwmb_ram_rty, wb_s2m_dwmb_ram_rty}),
.wbs_adr_o (wb_ram_adr_o),
.wbs_dat_o (wb_ram_dat_o),
.wbs_sel_o (wb_ram_sel_o),
.wbs_we_o (wb_ram_we_o),
.wbs_cyc_o (wb_ram_cyc_o),
.wbs_stb_o (wb_ram_stb_o),
.wbs_cti_o (wb_ram_cti_o),
.wbs_bte_o (wb_ram_bte_o),
.wbs_dat_i (wb_ram_dat_i),
.wbs_ack_i (wb_ram_ack_i),
.wbs_err_i (wb_ram_err_i),
.wbs_rty_i (wb_ram_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_rom
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_rom_adr, wb_m2s_dwmb_rom_adr}),
.wbm_dat_i ({wb_m2s_iwmb_rom_dat, wb_m2s_dwmb_rom_dat}),
.wbm_sel_i ({wb_m2s_iwmb_rom_sel, wb_m2s_dwmb_rom_sel}),
.wbm_we_i ({wb_m2s_iwmb_rom_we, wb_m2s_dwmb_rom_we}),
.wbm_cyc_i ({wb_m2s_iwmb_rom_cyc, wb_m2s_dwmb_rom_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_rom_stb, wb_m2s_dwmb_rom_stb}),
.wbm_cti_i ({wb_m2s_iwmb_rom_cti, wb_m2s_dwmb_rom_cti}),
.wbm_bte_i ({wb_m2s_iwmb_rom_bte, wb_m2s_dwmb_rom_bte}),
.wbm_dat_o ({wb_s2m_iwmb_rom_dat, wb_s2m_dwmb_rom_dat}),
.wbm_ack_o ({wb_s2m_iwmb_rom_ack, wb_s2m_dwmb_rom_ack}),
.wbm_err_o ({wb_s2m_iwmb_rom_err, wb_s2m_dwmb_rom_err}),
.wbm_rty_o ({wb_s2m_iwmb_rom_rty, wb_s2m_dwmb_rom_rty}),
.wbs_adr_o (wb_rom_adr_o),
.wbs_dat_o (wb_rom_dat_o),
.wbs_sel_o (wb_rom_sel_o),
.wbs_we_o (wb_rom_we_o),
.wbs_cyc_o (wb_rom_cyc_o),
.wbs_stb_o (wb_rom_stb_o),
.wbs_cti_o (wb_rom_cti_o),
.wbs_bte_o (wb_rom_bte_o),
.wbs_dat_i (wb_rom_dat_i),
.wbs_ack_i (wb_rom_ack_i),
.wbs_err_i (wb_rom_err_i),
.wbs_rty_i (wb_rom_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_fw_interface
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_fw_interface_adr, wb_m2s_dwmb_fw_interface_adr}),
.wbm_dat_i ({wb_m2s_iwmb_fw_interface_dat, wb_m2s_dwmb_fw_interface_dat}),
.wbm_sel_i ({wb_m2s_iwmb_fw_interface_sel, wb_m2s_dwmb_fw_interface_sel}),
.wbm_we_i ({wb_m2s_iwmb_fw_interface_we, wb_m2s_dwmb_fw_interface_we}),
.wbm_cyc_i ({wb_m2s_iwmb_fw_interface_cyc, wb_m2s_dwmb_fw_interface_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_fw_interface_stb, wb_m2s_dwmb_fw_interface_stb}),
.wbm_cti_i ({wb_m2s_iwmb_fw_interface_cti, wb_m2s_dwmb_fw_interface_cti}),
.wbm_bte_i ({wb_m2s_iwmb_fw_interface_bte, wb_m2s_dwmb_fw_interface_bte}),
.wbm_dat_o ({wb_s2m_iwmb_fw_interface_dat, wb_s2m_dwmb_fw_interface_dat}),
.wbm_ack_o ({wb_s2m_iwmb_fw_interface_ack, wb_s2m_dwmb_fw_interface_ack}),
.wbm_err_o ({wb_s2m_iwmb_fw_interface_err, wb_s2m_dwmb_fw_interface_err}),
.wbm_rty_o ({wb_s2m_iwmb_fw_interface_rty, wb_s2m_dwmb_fw_interface_rty}),
.wbs_adr_o (wb_fw_interface_adr_o),
.wbs_dat_o (wb_fw_interface_dat_o),
.wbs_sel_o (wb_fw_interface_sel_o),
.wbs_we_o (wb_fw_interface_we_o),
.wbs_cyc_o (wb_fw_interface_cyc_o),
.wbs_stb_o (wb_fw_interface_stb_o),
.wbs_cti_o (wb_fw_interface_cti_o),
.wbs_bte_o (wb_fw_interface_bte_o),
.wbs_dat_i (wb_fw_interface_dat_i),
.wbs_ack_i (wb_fw_interface_ack_i),
.wbs_err_i (wb_fw_interface_err_i),
.wbs_rty_i (wb_fw_interface_rty_i));
endmodule
|
`timescale 1ns / 1ps
module dmix_t;
// ins
reg rst;
reg clk;
parameter TCLK = 40;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg signal;
reg sck;
parameter TCLK_SCK = 80;
reg mosi;
reg ss;
parameter TclkSPDIF = 40; // 24.576MHz == 192Khz * 32 bit * 2 (biphase)
nkmdhpa uut(
.rst(rst),
.clk245760_pad(clk),
.spdif_i(signal),
.csr_sck(sck),
.csr_mosi(mosi),
.csr_ss(ss));
task recv_rawbit;
input b;
begin
signal = b;
#(TclkSPDIF);//*6);
end
endtask
task recv_B;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_M;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
end
end
endtask
task recv_W;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_bmcbit;
input b;
begin
if(signal) begin
if(b) begin
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(0);
recv_rawbit(0);
end
end else begin
if(b) begin
recv_rawbit(1);
recv_rawbit(0);
end else begin
recv_rawbit(1);
recv_rawbit(1);
end
end
end
endtask
task recv_bmcbyte;
input [7:0] byte;
begin
recv_bmcbit(byte[0]);
recv_bmcbit(byte[1]);
recv_bmcbit(byte[2]);
recv_bmcbit(byte[3]);
recv_bmcbit(byte[4]);
recv_bmcbit(byte[5]);
recv_bmcbit(byte[6]);
recv_bmcbit(byte[7]);
end
endtask
task recv_bmcctl;
begin
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
end
endtask
task recv_subframe;
input [23:0] data;
begin
recv_bmcbyte(data[7:0]);
recv_bmcbyte(data[15:8]);
recv_bmcbyte(data[23:16]);
recv_bmcctl();
end
endtask
task spi_cycle;
input [7:0] data;
begin
#(TCLK_SCK/2);
ss = 0;
#(TCLK_SCK/2);
mosi = data[7];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[6];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[5];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[4];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[3];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[2];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[1];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[0];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
#(TCLK_SCK/2);
ss = 1;
#(TCLK_SCK/2);
end
endtask
`define USE_CAPTURE
`define PROGCMD_LEN 112
reg [7:0] progcmd [(`PROGCMD_LEN-1):0];
initial $readmemh("progcmd.memh", progcmd);
reg replay_capture;
initial replay_capture = 1'b0;
integer i;
reg [22:0] counter;
initial begin
$dumpfile("nkmdhpa_t.lxt");
$dumpvars(0, uut);
rst = 1'b0;
signal = 0;
counter = 0;
mosi = 1'b0;
ss = 1'b1;
#(100);
rst = 1'b1;
#(200);
rst = 1'b0;
#(1500);
for (i = 0; i < `PROGCMD_LEN; i = i + 1) begin
spi_cycle(progcmd[i]);
end
#(100);
$display("--- NKMD dbgin");
#(TCLK*3);
spi_cycle({4'b1_11_0, 4'h6});
spi_cycle(8'h00); // offset
spi_cycle(8'h01);
spi_cycle(8'h02);
spi_cycle(8'h03);
spi_cycle(8'h04);
spi_cycle(8'h05);
spi_cycle(8'h06);
spi_cycle(8'h07);
spi_cycle(8'h08);
spi_cycle(8'h09);
spi_cycle(8'h0a);
spi_cycle(8'h0b);
spi_cycle(8'h0c);
spi_cycle(8'h0d);
spi_cycle(8'h0e);
spi_cycle(8'h0f);
spi_cycle(8'h10);
#(TCLK*3);
$display("--- NKMD rst => 0");
#(TCLK*3);
spi_cycle({4'b1_01_0, 4'h4});
spi_cycle(8'h00); // offset
spi_cycle(8'h00); // data
#(TCLK*3);
replay_capture = 1'b1;
#(30000);
$finish(2);
end
`ifndef USE_CAPTURE
always begin
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
$finish(2);
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
if (counter > 512)
$finish(2);
end
`else
reg [31:0] capture [262143:0];
integer capture_iter;
initial $readmemh("spdif_capture3", capture);
initial capture_iter = 0;
always begin
if (replay_capture) begin
signal = capture[capture_iter][2];
capture_iter = capture_iter + 1;
if (capture_iter > 262143)
$finish(2);
end
#(5);
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_2_V
`define SKY130_FD_SC_MS__A221O_2_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_2_V
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module watchdog(
input nLDS, RW,
input A23I, A22I,
input [21:17] M68K_ADDR_U,
//input [12:1] M68K_ADDR_L,
input WDCLK,
output nHALT,
output nRESET,
input nRST
);
reg [3:0] WDCNT;
initial
WDCNT <= 4'b0000;
// IMPORTANT:
// nRESET is an open-collector output on B1, so that the 68k can drive it (RESET instruction)
// The line has a 4.7k pullup (schematics page 1)
// nRESET changes state on posedge nBNKB (posedge mclk), but takes a slightly variable amount of time to
// return high after it is released. Low during 8 frames, released during 8 frames.
assign nRESET = nRST & ~WDCNT[3];
assign nHALT = nRESET;
// $300001 (LDS)
// 0011000xxxxxxxxxxxxxxxx1
// MAME says 00110001xxxxxxxxxxxxxxx1 but NEO-B1 doesn't have A16
assign WDRESET = &{nRST, ~|{nLDS, RW, A23I, A22I}, M68K_ADDR_U[21:20], ~|{M68K_ADDR_U[19:17]}};
always @(posedge WDCLK or posedge WDRESET or posedge ~nRST)
begin
if (WDRESET)
begin
WDCNT <= 4'b0000;
end
else if (!nRST)
begin
WDCNT <= 4'b1110; // DEBUG - Used to speed up simulation
//WDCNT <= 4'b1000; // Correct value
end
else
WDCNT <= WDCNT + 1'b1;
end
endmodule
|
//% @file fifo_over_ufc_tb.v
//% @brief test bench of FIFO I/O via Aurora 64B66B UFC interface
//% @author Yuan Mei
//%
`timescale 1ns / 1ps
module fifo_over_ufc_tb
#(
parameter FIFO_DATA_WIDTH = 32,
parameter AURORA_DATA_WIDTH = 64
)
();
reg clk;
reg reset;
wire a_tx_req;
wire [7:0] a_tx_ms;
reg a_tx_tready;
wire [AURORA_DATA_WIDTH-1:0] a_tx_tdata;
wire a_tx_tvalid;
wire [AURORA_DATA_WIDTH-1:0] a_rx_tdata;
reg a_rx_tvalid;
wire fifo_clk;
wire [FIFO_DATA_WIDTH-1:0] tx_fifo_q;
wire tx_fifo_wren;
reg tx_fifo_full;
reg [FIFO_DATA_WIDTH-1:0] rx_fifo_q;
wire rx_fifo_rden;
reg rx_fifo_empty;
wire err;
fifo_over_ufc #(.FIFO_DATA_WIDTH(FIFO_DATA_WIDTH), .AURORA_DATA_WIDTH(AURORA_DATA_WIDTH))
uut
(
.RESET(reset),
.AURORA_USER_CLK(clk),
.AURORA_TX_REQ(a_tx_req),
.AURORA_TX_MS(a_tx_ms),
.AURORA_TX_TREADY(a_tx_tready),
.AURORA_TX_TDATA(a_tx_tdata),
.AURORA_TX_TVALID(a_tx_tvalid),
.AURORA_RX_TDATA(a_rx_tdata),
.AURORA_RX_TVALID(a_rx_tvalid),
.FIFO_CLK(fifo_clk),
.TX_FIFO_Q(tx_fifo_q),
.TX_FIFO_WREN(tx_fifo_wren),
.TX_FIFO_FULL(tx_fifo_full),
.RX_FIFO_Q(rx_fifo_q),
.RX_FIFO_RDEN(rx_fifo_rden),
.RX_FIFO_EMPTY(rx_fifo_empty),
.ERR(err)
);
//initial begin
//$dumpfile("fifo_over_ufc.vcd");
//$dumpvars(0, fifo_over_ufc);
//end
initial begin
clk = 0;
reset = 0;
#16 reset = 1;
#26 reset = 0;
#200 reset = 1;
#10 reset = 0;
end
always #5 clk = ~clk;
initial begin
rx_fifo_empty = 1;
a_rx_tvalid = 0;
tx_fifo_full = 0;
#46 rx_fifo_empty = 0;
#120 rx_fifo_empty = 1;
#40 a_rx_tvalid = 1;
#10 a_rx_tvalid = 0; tx_fifo_full = 1;
end
// emulate Aurora UFC interface
reg [1:0] state;
localparam S0 = 2'h0;
localparam S1 = 2'h1;
localparam S2 = 2'h2;
localparam S3 = 2'h3;
always @ (posedge clk or posedge reset) begin
if (reset) begin
state <= S0;
a_tx_tready <= 1;
end
else begin
a_tx_tready <= 1;
case (state)
S0: begin
state <= S0;
if (a_tx_req == 1) begin
state <= S1;
a_tx_tready <= 0;
end
end
S1: begin
state <= S2;
a_tx_tready <= 0;
end
S2: begin
state <= S3;
a_tx_tready <= 1;
end
S3: begin
state <= S3;
a_tx_tready <= 1;
if (a_tx_tvalid == 1) begin
state <= S0;
end
end
default: begin
state <= S0;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_16_V
`define SKY130_FD_SC_HS__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_16 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_M_V
`define SKY130_FD_SC_LP__BUFLP_M_V
/**
* buflp: Buffer, Low Power.
*
* Verilog wrapper for buflp with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buflp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_m (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_M_V
|
/*
* TOP2049 Open Source programming suite
*
* Atmel AT89S5X DIP40
* FPGA bottomhalf implementation
*
* Copyright (c) 2010 Guido
* Copyright (c) 2010 Michael Buesch <m@bues.ch>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
/* The runtime ID and revision. */
`define RUNTIME_ID 16'h0005
`define RUNTIME_REV 16'h01
module at89s5xdip40(data, ale, write, read, osc_in, zif);
inout [7:0] data;
input ale;
input write;
input read;
input osc_in; /* 24MHz oscillator */
inout [48:1] zif;
/* Interface to the microcontroller */
wire read_oe; /* Read output-enable */
reg [7:0] address; /* Cached address value */
reg [7:0] read_data; /* Cached read data */
wire low, high; /* Constant lo/hi */
/* Programmer context */
reg [1:0] prog_busy;
reg [3:0] prog_command;
reg [3:0] prog_state;
reg [3:0] prog_count;
reg prog_err;
/* DUT signals */
reg [7:0] dut_data;
reg [13:0] dut_addr;
reg dut_p26;
reg dut_p27;
reg dut_p33;
reg dut_p36;
reg dut_p37;
reg dut_psen;
reg dut_prog;
reg dut_vpp;
reg dut_rst;
wire dut_clock;
assign low = 0;
assign high = 1;
initial begin
prog_busy <= 0;
prog_command <= 0;
prog_state <= 0;
prog_err <= 0;
prog_count <= 0;
dut_data <= 0;
dut_addr <= 0;
dut_p26 <= 0;
dut_p27 <= 0;
dut_p33 <= 0;
dut_p36 <= 0;
dut_p37 <= 0;
dut_psen <= 0;
dut_prog <= 0;
dut_vpp <= 0;
dut_rst <= 0;
end
/* The delay counter. Based on the 24MHz input clock. */
reg [15:0] delay_count;
wire osc;
assign dut_clock=osc;
IBUF osc_ibuf(.I(osc_in), .O(osc));
always @(posedge osc) begin
if (delay_count == 0) begin
if (prog_busy[0] != prog_busy[1]) begin
/* busy0 != busy1 indicates that a command is running.
* Continue executing it... */
case (prog_command)
1: begin /* Set P3.2 after init */
dut_prog <= 1;
prog_busy[1] <= prog_busy[0];
end
2: begin /* clear P3.2 before shutdown */
dut_prog <= 0;
prog_busy[1] <= prog_busy[0];
end
3: begin /* do nPROG pulsep with wait for ready */
case (prog_state)
0: begin /* raise dut_prog */
dut_prog <= 1;
prog_state <= 1;
delay_count <= 48;/*2us (48 tcl) wait*/
prog_err <= 0;
end
1: begin /* pulse */
delay_count <= 24;/* each 1us */
dut_prog <= 0;
prog_state <= 2;
end
2: begin /* raise dut_prog */
dut_prog <= 1;
prog_state <= 3;
prog_count <= 12;
delay_count <= 48;/*2us (48 tcl) wait*/
end
3: begin /* wait for ready (zif[14]) == 1 */
if (zif[14] == 0) begin
delay_count <= 80; /* each 3330ns */
prog_count <= prog_count - 1;
if (prog_count == 0) begin
prog_err <= 1;
prog_state <= 4;
end
end
else begin
prog_state <= 4;
end
end
4: begin /* finish */
prog_state <= 0;
prog_busy[1] <= prog_busy[0];
end
endcase
end
4: begin /* do nPROG pulsep */
case (prog_state)
0: begin
dut_prog <= 1;
prog_state <= 1;
delay_count <= 48;/*48tcy, 2us*/
prog_err <= 0;
end
1: begin /* pulse */
delay_count <= 24; /* 1us each */
dut_prog <= 0;
prog_state <= 2;
end
2: begin
dut_prog <= 1;
prog_state <= 3;
delay_count <= 48;/*48tcy, 2us*/
end
3: begin
prog_busy[1] <= prog_busy[0];
prog_state <= 0;
end
endcase
end
5: begin /* set dut_vpp */
dut_vpp <= 1;
prog_busy[1] <= prog_busy[0];
end
6: begin /* clear dut_vpp */
dut_vpp <= 0;
prog_busy[1] <= prog_busy[0];
end
endcase
end
end else begin
delay_count <= delay_count - 1;
end
end
always @(posedge write) begin
case (address)
8'h10: begin
/* Data write */
dut_data <= data;
end
8'h11: begin
/* Address LSB write */
dut_addr[7:0] <= data;
end
8'h12: begin
/* Address MSB write */
dut_addr[13:8] <= data[5:0];
end
8'h13: begin
/* Run a command. */
prog_command <= data;
prog_busy[0] <= ~prog_busy[1];
end
8'h16: begin
/* Set P26, P27, P33, P36, P37, dut_psen, dut_rst */
dut_p26 <= data[0];
dut_p27 <= data[1];
dut_p33 <= data[2];
dut_p36 <= data[3];
dut_p37 <= data[4];
dut_psen <= data[5];
dut_rst <= data[6];
end
endcase
end
always @(negedge read) begin
case (address)
8'h10: begin
/* Data read */
read_data[7] <= zif[36];
read_data[6] <= zif[37];
read_data[5] <= zif[38];
read_data[4] <= zif[39];
read_data[3] <= zif[40];
read_data[2] <= zif[41];
read_data[1] <= zif[42];
read_data[0] <= zif[43];
end
8'h12: begin
/* Read status */
read_data[0] <= (prog_busy[0] != prog_busy[1]);
read_data[1] <= prog_err;
end
8'hFD: read_data <= `RUNTIME_ID & 16'hFF;
8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF;
8'hFF: read_data <= `RUNTIME_REV;
endcase
end
always @(negedge ale) begin
address <= data;
end
assign read_oe = !read && address[4];
bufif0(zif[1], low, low);
bufif0(zif[2], low, low);
bufif0(zif[3], low, low);
bufif0(zif[4], low, low);
bufif0(zif[5], dut_addr[0], dut_p26);
bufif0(zif[6], dut_addr[1], dut_p26);
bufif0(zif[7], dut_addr[2], dut_p26);
bufif0(zif[8], dut_addr[3], dut_p26);
bufif0(zif[9], dut_addr[4], dut_p26);
bufif0(zif[10], dut_addr[5], dut_p26);
bufif0(zif[11], dut_addr[6], dut_p26);
bufif0(zif[12], dut_addr[7], dut_p26);
bufif0(zif[13], dut_rst, low); /*Reset*/
bufif0(zif[14], low, high); /* P3.0 */
bufif0(zif[15], low, low); /* P3.1 */
bufif0(zif[16], low, low); /* P3.2 */
bufif0(zif[17], dut_p33, low); /* P3.3 */
bufif0(zif[18], low, low); /* P3.4 */
bufif0(zif[19], low, low); /* P3.5 */
bufif0(zif[20], dut_p36, low); /* P3.6 */
bufif0(zif[21], dut_p37, low); /* P3.7 */
bufif0(zif[22], low, high); /* XTAL2 */
bufif0(zif[23], dut_clock, low); /* XTAL1 */
bufif0(zif[24], low, low); /* GND */
bufif0(zif[25], dut_addr[8], dut_p26); /* P2.0 */
bufif0(zif[26], dut_addr[9], dut_p26); /* P2.1 */
bufif0(zif[27], dut_addr[10], dut_p26); /* P2.2 */
bufif0(zif[28], dut_addr[11], dut_p26); /* P2.3 */
bufif0(zif[29], dut_addr[12], dut_p26); /* P2.4 */
bufif0(zif[30], dut_addr[13], dut_p26); /* P2.5 */
bufif0(zif[31], dut_p26, low); /* P2.6 */
bufif0(zif[32], dut_p27, low); /* P2.7 */
bufif0(zif[33], dut_psen, low); /* !PSEN */
bufif0(zif[34], dut_prog, low); /* !PROG */
bufif0(zif[35], low, dut_vpp); /* VPP/Reset */
bufif0(zif[36], dut_data[7], !(!dut_p26 && dut_p27));
bufif0(zif[37], dut_data[6], !(!dut_p26 && dut_p27));
bufif0(zif[38], dut_data[5], !(!dut_p26 && dut_p27));
bufif0(zif[39], dut_data[4], !(!dut_p26 && dut_p27));
bufif0(zif[40], dut_data[3], !(!dut_p26 && dut_p27));
bufif0(zif[41], dut_data[2], !(!dut_p26 && dut_p27));
bufif0(zif[42], dut_data[1], !(!dut_p26 && dut_p27));
bufif0(zif[43], dut_data[0], !(!dut_p26 && dut_p27));
bufif0(zif[44], high, low); /* VCC */
bufif0(zif[45], low, low);
bufif0(zif[46], low, low);
bufif0(zif[47], low, low);
bufif0(zif[48], low, low);
bufif1(data[0], read_data[0], read_oe);
bufif1(data[1], read_data[1], read_oe);
bufif1(data[2], read_data[2], read_oe);
bufif1(data[3], read_data[3], read_oe);
bufif1(data[4], read_data[4], read_oe);
bufif1(data[5], read_data[5], read_oe);
bufif1(data[6], read_data[6], read_oe);
bufif1(data[7], read_data[7], read_oe);
endmodule
|
`include "Global_Macros.v"
module Write_Back(
clk_i,
rst_i,
gbl_stl_i,
wait_to_fill_pipe_i,
control_signal_i,
p_i,
dat_i,
eff_adr_i,
mem_stl_i,
a_o,
x_o,
y_o,
mem_w_enb_o,
mem_w_cnt_o,
mem_w_adr_o,
mem_w_dat_o
`ifdef DEBUG
,debug_o
`endif
);
//Input signals :
input wire clk_i;
input wire rst_i;
input wire gbl_stl_i;
input wire wait_to_fill_pipe_i;
input wire [`execut_cntrl_o_width - 1:0] control_signal_i;
input wire [7:0] p_i;
input wire [15:0] dat_i;
input wire [15:0] eff_adr_i;
input wire mem_stl_i;
//Output signals :
output wire [7:0] a_o;
output wire [7:0] x_o;
output wire [7:0] y_o;
output reg mem_w_enb_o;
output reg [1:0] mem_w_cnt_o;
output reg [15:0] mem_w_adr_o;
output reg [23:0] mem_w_dat_o;
`ifdef DEBUG
output wire [`WRB_DBG_WIDTH - 1:0] debug_o;
`endif
//Internal registers :
reg [7:0] a_reg;
reg [7:0] x_reg;
reg [7:0] y_reg;
//Assignments :
assign a_o = a_reg;
assign x_o = x_reg;
assign y_o = y_reg;
`ifdef DEBUG
assign debug_o = mem_w_adr_o;
`endif
//Blocks :
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
mem_w_cnt_o <= `ONE;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
end
else
begin
mem_w_enb_o <= `cntrl_wb_mem_wr;
mem_w_cnt_o <= ( `cntrl_wb_mem_wr_cnt == `ONE ) ? 2'h0 :
( `cntrl_wb_mem_wr_cnt == `TWO ) ? 2'h1 : 2'h2;
mem_w_dat_o <= {p_i, dat_i};
mem_w_adr_o <= eff_adr_i;
end
end
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
a_reg <= 8'h0;
x_reg <= 8'h0;
y_reg <= 8'h0;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
end
else
begin
a_reg <= (`cntrl_wb_ra_ld == 1'h1) ? dat_i[7:0] : a_reg;
x_reg <= (`cntrl_wb_rx_ld == 1'h1) ? dat_i[7:0] : x_reg;
y_reg <= (`cntrl_wb_ry_ld == 1'h1) ? dat_i[7:0] : y_reg;
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
|
//--------------------------------------------------------------------------------
//-- Filename: FLOW_CONTROLLER.v
//--
//-- Description: FLOW CONTROLLER Module
//--
//-- The module controls the TLP sending rates to ensure that the TLP
//-- TX buffer and RX buffer in the PCIE core do not overflow.
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module FLOW_CONTROLLER(
clk,
rst_n,
init_rst_i,
mrd_start_i,
mrd_len_i,
//mrd_cur_rd_count_i,
mrd_tlp_sent_i,
cpld_data_size_i,
cfg_rd_comp_bound_i,
rd_metering_i,
mwr_start_i,
trn_tbuf_av_i,
mrd_start_fc_o,
mwr_start_fc_o
);
// Set when the PCIe CORE was generated
parameter MAX_REQUEST_SIZE = 128;
parameter MAX_PAYLOAD_SIZE = 256;
parameter CPLH_CREDITS = 36;
parameter CPLD_CREDITS = 154;
parameter TRANSMIT_TLP_BUFFERD = 29;
parameter LIMIT_FC_MAX_NP = 18;
input clk;
input rst_n , init_rst_i;
input mrd_start_i;
input [10:0] mrd_len_i; // Memory Read Size Command (DWs)
//input [15:0] mrd_cur_rd_count_i;
input [31:0] mrd_tlp_sent_i;
input mwr_start_i;
input [31:0] cpld_data_size_i;
input cfg_rd_comp_bound_i; // Programmed RCB = 0=64B or 1=128B
input rd_metering_i; // enable send rate control
input [5:0] trn_tbuf_av_i;
output mrd_start_fc_o;
output mwr_start_fc_o;
reg mrd_start_fc_o;
reg mwr_start_fc_o;
wire [31:0] NPs_send = mrd_tlp_sent_i;
wire [26:0] NPs_recv = cpld_data_size_i >> 5;
wire [26:0] NPs_pending = NPs_send[26:0] - NPs_recv;
always @ ( posedge clk ) begin
if( !rst_n ) begin
mrd_start_fc_o <= 1'b0;
mwr_start_fc_o <= 1'b0;
end
else begin
if(init_rst_i) begin
mrd_start_fc_o <= 1'b0;
mwr_start_fc_o <= 1'b0;
end
if( rd_metering_i ) begin
`ifdef SIMULATION
if( NPs_pending > 0 )
mrd_start_fc_o <= 1'b0;
else
mrd_start_fc_o <= mrd_start_i;
`else
if ( ( NPs_pending < LIMIT_FC_MAX_NP + 5 ) && ( trn_tbuf_av_i > 1'b1 ) )
mrd_start_fc_o <= mrd_start_i;
else
mrd_start_fc_o <= 1'b0;
`endif
end
else
mrd_start_fc_o <= mrd_start_i;
if( trn_tbuf_av_i > 1'b1 )
mwr_start_fc_o <= mwr_start_i;
else
mwr_start_fc_o <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFXTP_PP_SYMBOL_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_PP_SYMBOL_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// altera message_off 10036
module altera_mem_if_ddr3_phy_0001_new_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
pll_dqs_ena_clk,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_oct_ena,
dqs_enable_ctrl,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
ddio_phy_dq,
read_capture_clk,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter DQS_ENABLE_CTRL_WIDTH = "";
parameter ALTDQDQS_INPUT_FREQ = "";
parameter ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = "";
parameter ALTDQDQS_DQS_PHASE_SETTING = "";
parameter ALTDQDQS_DQS_PHASE_SHIFT = "";
parameter ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = "";
parameter FAST_SIM_MODEL = "";
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam HALF_AFI_DATA_WIDTH = AFI_DATA_WIDTH / 2;
localparam HALF_AFI_DQS_WIDTH = AFI_DQS_WIDTH / 2;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input phy_ddio_addr_cmd_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
input [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
input [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [DQS_ENABLE_CTRL_WIDTH-1:0] dqs_enable_ctrl;
input [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
input [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output [DOUBLE_MEM_DQ_WIDTH-1:0] ddio_phy_dq;
output [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input scc_upd;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire hr_clk = pll_afi_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_int = phy_ddio_dq;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_int = phy_ddio_wrdata_en;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_int = phy_ddio_wrdata_mask;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_int = phy_ddio_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_int = phy_ddio_oct_ena;
altera_mem_if_ddr3_phy_0001_addr_cmd_pads uaddr_cmd_pads(
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk),
.phy_ddio_addr_cmd_clk (phy_ddio_addr_cmd_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_reset_n (phy_mem_reset_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
wire [HALF_AFI_DQS_WIDTH-1:0] phy_ddio_oe_l;
wire [HALF_AFI_DQS_WIDTH-1:0] phy_ddio_oe_h;
assign phy_ddio_oe_l = phy_ddio_wrdata_en_int[HALF_AFI_DQS_WIDTH-1:0];
assign phy_ddio_oe_h = phy_ddio_wrdata_en_int[AFI_DQS_WIDTH-1:HALF_AFI_DQS_WIDTH];
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
wire dqs_busout;
// The phy_ddio_dq_int bus is the write data for all DQS groups in one
// AFI cycle. The bus is ordered by time slow and subordered by
// DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
// The following extracts write data targeting the current DQS
// group.
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t0 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t1 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t2 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t3 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)];
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t0;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t1;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t2;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t3;
assign phy_ddio_wrdata_mask_t0 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+0*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+0*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t1 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+1*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+1*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t2 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+2*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+2*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t3 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+3*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+3*NUM_OF_DQDQS_WITH_DM)];
altera_mem_if_ddr3_phy_0001_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (1'b0),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (hr_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.strobe_ena_clock_in (pll_dqs_ena_clk),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dq [(2*DQDQS_DATA_WIDTH*(i+1)-1) : 2*DQDQS_DATA_WIDTH*i]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in ({phy_ddio_wrdata_mask_t3, phy_ddio_wrdata_mask_t2, phy_ddio_wrdata_mask_t1, phy_ddio_wrdata_mask_t0}),
.write_data_in ({phy_ddio_dq_t3, phy_ddio_dq_t2, phy_ddio_dq_t1, phy_ddio_dq_t0}),
.write_oe_in ({ {DQDQS_DATA_WIDTH{phy_ddio_oe_h[i]}}, {DQDQS_DATA_WIDTH{phy_ddio_oe_l[i]}} }),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena ({phy_ddio_dqs_en_int[i+NUM_OF_DQDQS], phy_ddio_dqs_en_int[i]}),
.oct_ena_in ({phy_ddio_oct_ena_int[i+NUM_OF_DQDQS], phy_ddio_oct_ena_int[i]}),
.capture_strobe_ena ({dqs_enable_ctrl[i+NUM_OF_DQDQS], dqs_enable_ctrl[i]}),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.dll_delayctrl_in (dll_phy_delayctrl)
);
defparam ubidir_dq_dqs.ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = FAST_SIM_MODEL;
assign read_capture_clk[i] = ~dqs_busout;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Boston University
// Engineer: Schuyler Eldridge; Zafar M. Takhirov
//
// Create Date: 13:00:22 04/12/2011
// Design Name: EC311/EC551 Support Files
// Module Name: vga_controller_640_60
// Project Name: N/A
// Target Devices: Spartan 6 Family
// Tool versions: XILINX ISE 1x.x
// Description:
//
// Dependencies: none
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_controller_640_60 (rst,pixel_clk,HS,VS,hcounter,vcounter,blank);
input rst, pixel_clk; // global reset, pixel clock
output reg HS, VS, blank; // sync controls, blank indicator
output reg [10:0] hcounter, vcounter; // pixel coordinates
/*
parameter HMAX = 800; // maxium value for the horizontal pixel counter
parameter VMAX = 525; // maxium value for the vertical pixel counter
parameter HLINES = 640; // total number of visible columns
parameter HFP = 648; // value for the horizontal counter where front porch ends
parameter HSP = 744; // value for the horizontal counter where the synch pulse ends
parameter VLINES = 480; // total number of visible lines
parameter VFP = 482; // value for the vertical counter where the frone proch ends
parameter VSP = 484; // value for the vertical counter where the synch pulse ends
parameter SPP = 0; // value for the porch synchronization pulse
*/
parameter HMAX = 800; // maxium value for the horizontal pixel counter
parameter HLINES = 640; // total number of visible columns
parameter HFP = 648; // value for the horizontal counter where front porch ends
parameter HSP = 744; // value for the horizontal counter where the synch pulse ends
parameter VMAX = 525; // maxium value for the vertical pixel counter
parameter VLINES = 480; // total number of visible lines
parameter VFP = 482; // value for the vertical counter where the frone proch ends
parameter VSP = 484; // value for the vertical counter where the synch pulse ends
parameter SPP = 0; // value for the porch synchronization pulse
wire video_enable; // valid region indicator
initial begin
hcounter = 0;
vcounter = 0;
end
// create a "blank" indicator
always@(posedge pixel_clk)begin
blank <= ~video_enable;
end
// Create a horizontal beam trace (horizontal time):
always@(posedge pixel_clk, posedge rst)begin
if(rst == 1) hcounter <= 0;
else if (hcounter == HMAX) hcounter <= 0;
else hcounter <= hcounter + 1'b1;
end
// Create a vertical beam trace (vertical time):
always@(posedge pixel_clk, posedge rst)begin
if(rst == 1) vcounter <=0;
else if(hcounter == HMAX) begin
if(vcounter == VMAX) vcounter <= 0;
else vcounter <= vcounter + 1'b1;
end
end
// Check if between horizontal porches,
// if not send horizontal porch synchronization pulse
always@(posedge pixel_clk)begin
if(hcounter >= HFP && hcounter < HSP) HS <= SPP;
else HS <= ~SPP;
end
// Check if between vertical porches,
// if not send vertical porch synchronization pulse
always@(posedge pixel_clk)begin
if(vcounter >= VFP && vcounter < VSP) VS <= SPP;
else VS <= ~SPP;
end
// create a video enabled region
assign video_enable = (hcounter < HLINES && vcounter < VLINES) ? 1'b1 : 1'b0;
endmodule
|
`timescale 1ns / 100ps
`define EIC_DIRECT_CHANNELS 20
`define EIC_SENSE_CHANNELS 20
`include "mfp_eic_core.vh"
module test_eicAhb;
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_ahb_lite_eic eic
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.signal ( signal ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
/*
module mfp_ahb_lite_eic
(
//ABB-Lite side
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0 ] HPROT, // ignored
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output reg [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian, // ignored
//Interrupt side
input [ `EIC_CHANNELS-1 : 0 ] signal,
//CPU side
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present
);
*/
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
ahbPhaseFst(`EIC_REG_EICR << 2, WRITE, HSIZE_X32, St_x); //enable eic
ahbPhase (`EIC_REG_EISMSK_0 << 2, WRITE, HSIZE_X32, 32'h01); //any logical change for irq 1, 2 (pins 0, 1)
ahbPhase (`EIC_REG_EIMSK_0 << 2, WRITE, HSIZE_X32, 32'h05); //enable irq 1, 2 (pins 0, 1)
ahbPhase (`EIC_REG_EIMSK_1 << 2, WRITE, HSIZE_X32, 32'h03); //enable irq 33 (pin 32)
ahbPhase (`EIC_REG_EICR << 2, READ, HSIZE_X32, 32'h01); //enable irq 33 (pin 32)
ahbPhase (`EIC_REG_EISMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_1 << 2, READ, HSIZE_X32, St_x);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
ahbPhase (`EIC_REG_EIFR_1 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFRC_1 << 2, WRITE, HSIZE_X32, St_x); //clear irq 33 (pin 32)
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01);
delay();
ahbPhase (`EIC_REG_EIFR_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01); //set EIFR word0
delay();
ahbPhase (`EIC_REG_EIFRS_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h04); //set EIFR bit3
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
ahbPhaseLst(`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
delay();
end
$stop;
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_3_0_7vx.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : <CoreName>_pcie_3_0_7vx.v //
// Description : Instantiates PCIe Top Level and GT top level and connects //
// them via PIPE interface. //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_3_0_7vx.v //
// gt_top.v //
// pcie_tx_elec_idle_filter_7vx.v //
// pipe_clock.v //
// pipe_reset.v //
// qpll_reset.v //
// * Generate GTHE2_CHANNEL for every lane. //
// pipe_user.v //
// pipe_rate.v //
// pipe_sync.v //
// pipe_drp.v //
// pipe_eq.v //
// rxeq_scan.v //
// gt_wrapper.v //
// GTHE2_CHANNEL //
// GTHE2_COMMON //
// * Generate GTHE2_COMMON for every quad. //
// qpll_drp.v //
// qpll_wrapper.v //
// pcie_top.v //
// pcie_init_ctrl.v //
// pcie_tlp_tph_tbl_7vx.v //
// pcie_7vx.v //
// PCIE_3_0 //
// pcie_bram_7vx.v //
// pcie_bram_7vx_rep.v //
// pcie_bram_7vx_rep_8k.v //
// pcie_bram_7vx_req.v //
// pcie_bram_7vx_8k.v //
// pcie_bram_7vx_cpl.v //
// pcie_bram_7vx_8k.v //
// pcie_bram_7vx_16k.v //
// pcie_pipe_pipeline.v //
// pcie_pipe_lane.v //
// pcie_pipe_misc.v //
// tandem_cpler.v //
// tandem_cpler_ctl_arb.v //
// PIO_RX_ENGINE.v //
// PIO_TX_ENGINE.v //
// PIO_INTR_CTRL.v //
// Fast_PCIe_config_top.v //
// pr_loader.v //
// PIO_FPC.v //
// PIO_TO_CTRL_FPC.v //
// PIO_EP_FPC.v //
// PIO_EP_MA_FPC.v //
// PIO_TX_ENG_FPC.v //
// PIO_RX_ENG_FPC.v //
// icap_access.v //
// data_transfer.v //
// fastConfigFIFO.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_3_0_7vx # (
parameter integer TCQ = 100,
parameter component_name = "pcie3_7x_v3_0",
// The following parameters can be changed to configure the link to a different width/speed.
// See Product Guide for details: Table "Data Width and Clock Frequency Settings for the Client Interfaces"
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4, // Maximum Link Speed
parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8, // Maximum Link Width
parameter integer USER_CLK2_FREQ = 4, // AXI Client Interface Frequency
parameter C_DATA_WIDTH = 256, // AXI Client Interface Width
parameter integer PIPE_PIPELINE_STAGES = 0, // PIPE Interface pipeline: 0-None, 1- single pipeline, 2-double pipeline
parameter PIPE_SIM = "FALSE", // No effect in RTL using this parameter.
parameter PIPE_SIM_MODE = "FALSE", // Use this paramter to control PIPE mode simulation logic; in-side this module
//GT Parameters
parameter REF_CLK_FREQ = 0, // Reference Clock Frequency
parameter PCIE_EXT_CLK = "TRUE",
parameter PCIE_EXT_GT_COMMON = "FALSE",
parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP
parameter PCIE_DRP = "FALSE", // PCIe DRP
parameter TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE",
parameter PCIE_TXBUF_EN = "FALSE",
parameter PCIE_GT_DEVICE = "GTH",
parameter integer PCIE_CHAN_BOND = 0,
parameter PCIE_CHAN_BOND_EN = "FALSE",
parameter PCIE_USE_MODE = "2.0",
parameter PCIE_LPM_DFE = "LPM",
parameter integer PCIE_LINK_SPEED = 3,
parameter integer KEEP_WIDTH = (C_DATA_WIDTH/32),
parameter TX_MARGIN_FULL_0 = 7'b1001111,
parameter TX_MARGIN_FULL_1 = 7'b1001110,
parameter TX_MARGIN_FULL_2 = 7'b1001101,
parameter TX_MARGIN_FULL_3 = 7'b1001100,
parameter TX_MARGIN_FULL_4 = 7'b1000011,
parameter TX_MARGIN_LOW_0 = 7'b1000101,
parameter TX_MARGIN_LOW_1 = 7'b1000110,
parameter TX_MARGIN_LOW_2 = 7'b1000011,
parameter TX_MARGIN_LOW_3 =7'b1000010,
parameter TX_MARGIN_LOW_4 =7'b1000000,
// PCIe 3_0 Core parameters
parameter ARI_CAP_ENABLE = "FALSE",
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_CC_PARITY_CHK = "FALSE",
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE",
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h2FFFF,
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE",
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RC_STRADDLE = "FALSE",
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RQ_PARITY_CHK = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1,
parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE",
parameter [8:0] LL_ACK_TIMEOUT = 9'h000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000,
parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000,
parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000,
parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000,
parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA,
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE",
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE",
parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [3:0] PF0_ARI_CAP_VER = 4'h1,
parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR0_CONTROL = 3'h4,
parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF0_BAR1_CONTROL = 3'h0,
parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR2_CONTROL = 3'h4,
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR3_CONTROL = 3'h0,
parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR4_CONTROL = 3'h4,
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR5_CONTROL = 3'h0,
parameter [7:0] PF0_BIST_REGISTER = 8'h00,
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF0_CLASS_CODE = 24'h000000,
parameter [15:0] PF0_VENDOR_ID = 16'h10EE,
parameter [15:0] PF0_DEVICE_ID = 16'h0007,
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE",
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE",
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0,
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE",
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE",
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000,
parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF0_TPHR_CAP_ENABLE = "FALSE",
parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF0_TPHR_CAP_VER = 4'h1,
parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF1_TPHR_CAP_ENABLE = "FALSE",
parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF1_TPHR_CAP_VER = 4'h1,
parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF2_TPHR_CAP_ENABLE = "FALSE",
parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF2_TPHR_CAP_VER = 4'h1,
parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF3_TPHR_CAP_ENABLE = "FALSE",
parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF3_TPHR_CAP_VER = 4'h1,
parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF4_TPHR_CAP_ENABLE = "FALSE",
parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF4_TPHR_CAP_VER = 4'h1,
parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF5_TPHR_CAP_ENABLE = "FALSE",
parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF5_TPHR_CAP_VER = 4'h1,
parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF0_DPA_CAP_VER = 4'h1,
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF0_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1,
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7,
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000,
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000,
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000,
parameter [3:0] PF0_LTR_CAP_VER = 4'h1,
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF0_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00,
parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000,
parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF0_PB_CAP_VER = 4'h1,
parameter [7:0] PF0_PM_CAP_ID = 8'h01,
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00,
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE",
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE",
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE",
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE",
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3,
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE",
parameter PF0_RBAR_CAP_ENABLE = "FALSE",
parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0,
parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF0_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF0_RBAR_NUM = 3'h1,
parameter [7:0] PF0_REVISION_ID = 8'h00,
parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF0_SUBSYSTEM_VENDOR_ID = 16'h0000,
parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000,
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter PF0_TPHR_CAP_ENABLE = "TRUE",
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h300,
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'b10,
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1,
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000,
parameter [3:0] PF0_VC_CAP_VER = 4'h1,
parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR0_CONTROL = 3'h4,
parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF1_BAR1_CONTROL = 3'h0,
parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR2_CONTROL = 3'h4,
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR3_CONTROL = 3'h0,
parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR4_CONTROL = 3'h4,
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR5_CONTROL = 3'h0,
parameter [7:0] PF1_BIST_REGISTER = 8'h00,
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF1_CLASS_CODE = 24'h000000,
parameter [15:0] PF1_DEVICE_ID = 16'h0000,
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000,
parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF1_DPA_CAP_VER = 4'h1,
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF1_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1,
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF1_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00,
parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000,
parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF1_PB_CAP_VER = 4'h1,
parameter [7:0] PF1_PM_CAP_ID = 8'h01,
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3,
parameter PF1_RBAR_CAP_ENABLE = "FALSE",
parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0,
parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF1_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF1_RBAR_NUM = 3'h1,
parameter [7:0] PF1_REVISION_ID = 8'h00,
parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000,
parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter PF1_TPHR_CAP_ENABLE = "TRUE",
parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h300,
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'b10,
parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF1_TPHR_CAP_VER = 4'h1,
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE",
parameter PL_DISABLE_SCRAMBLING = "FALSE",
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE",
parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE",
parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE",
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02,
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1,
parameter PL_EQ_BYPASS_PHASE23 = "FALSE",
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE",
parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3400,
parameter integer PL_N_FTS_COMCLK_GEN1 = 255,
parameter integer PL_N_FTS_COMCLK_GEN2 = 255,
parameter integer PL_N_FTS_COMCLK_GEN3 = 255,
parameter integer PL_N_FTS_GEN1 = 255,
parameter integer PL_N_FTS_GEN2 = 255,
parameter integer PL_N_FTS_GEN3 = 255,
parameter PL_UPSTREAM_FACING = "TRUE",
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC,
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00ABE,
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE",
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h000061A8,
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0,
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064,
parameter SIM_VERSION = "1.0",
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SRIOV_CAP_ENABLE = "FALSE",
parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20,
parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h3211620,
parameter [11:0] TL_CREDITS_CD = 12'h3E0,
parameter [7:0] TL_CREDITS_CH = 8'h20,
parameter [11:0] TL_CREDITS_NPD = 12'h028,
parameter [7:0] TL_CREDITS_NPH = 8'h20,
parameter [11:0] TL_CREDITS_PD = 12'h198,
parameter [7:0] TL_CREDITS_PH = 8'h20,
parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE",
parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
parameter TL_LEGACY_MODE_ENABLE = "FALSE",
parameter TL_PF_ENABLE_REG = "FALSE",
parameter TL_TAG_MGMT_ENABLE = "TRUE",
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50,
parameter integer VF0_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF0_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF0_PM_CAP_ID = 8'h01,
parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3,
parameter integer VF1_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF1_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF1_PM_CAP_ID = 8'h01,
parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3,
parameter integer VF2_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF2_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF2_PM_CAP_ID = 8'h01,
parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3,
parameter integer VF3_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF3_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF3_PM_CAP_ID = 8'h01,
parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3,
parameter integer VF4_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF4_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF4_PM_CAP_ID = 8'h01,
parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3,
parameter integer VF5_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF5_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF5_PM_CAP_ID = 8'h01,
parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3,
parameter IMPL_TARGET = "HARD",
parameter NO_DECODE_LOGIC = "FALSE",
parameter COMPLETION_SPACE = "16KB",
// Tandem PROM/PCIe Parameters
parameter PCIE_FAST_CONFIG = "NONE", // NONE, TANDEM_PROM, TANDEM_PCIE
//Parameters below are used during GU Customization. Do not change.
parameter gen_x0y0_ucf = "FALSE",
parameter gen_x0y1_ucf = "FALSE",
parameter gen_x0y2_ucf = "FALSE",
parameter gen_x0y3_ucf = "FALSE",
parameter pcie_blk_locn = 0,
parameter silicon_revision = "GES",
parameter xlnx_ref_board = 0,
parameter MSI_EN = "TRUE",
parameter MSIX_EN = "FALSE",
parameter SHARED_LOGIC_IN_CORE = "FALSE",
parameter TX_FC_IF = "FALSE",
parameter CFG_FC_IF = "FALSE",
parameter CFG_EXT_IF = "FALSE",
parameter CFG_STATUS_IF = "FALSE",
parameter PER_FUNC_STATUS_IF = "FALSE",
parameter CFG_MGMT_IF = "FALSE",
parameter RCV_MSG_IF = "FALSE",
parameter CFG_TX_MSG_IF = "FALSE",
parameter CFG_CTL_IF = "FALSE",
parameter EXT_STARTUP_PRIMITIVE = "FALSE",
parameter EXT_PIPE_INTERFACE = "FALSE"
) (
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn,
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp,
// Rx
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn,
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock & GT COMMON Sharing Interface //
//----------------------------------------------------------------------------------------------------------------//
// Shared Logic Internal
output int_pclk_out_slave,
output int_pipe_rxusrclk_out,
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] int_rxoutclk_out,
output int_dclk_out,
output int_userclk1_out,
output int_userclk2_out,
output int_oobclk_out,
output [1:0] int_qplllock_out,
output [1:0] int_qplloutclk_out,
output [1:0] int_qplloutrefclk_out,
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] int_pclk_sel_slave,
// Shared Logic External Clock
input pipe_pclk_in,
input pipe_rxusrclk_in,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxoutclk_in,
input pipe_dclk_in,
input pipe_userclk1_in,
input pipe_userclk2_in,
input pipe_oobclk_in,
input pipe_mmcm_lock_in,
output pipe_txoutclk_out,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxoutclk_out,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_pclk_sel_out,
output pipe_gen3_out,
// Shared Logic External GT COMMON
input [11:0] qpll_drp_crscode,
input [17:0] qpll_drp_fsm,
input [1:0] qpll_drp_done,
input [1:0] qpll_drp_reset,
input [1:0] qpll_qplllock,
input [1:0] qpll_qplloutclk,
input [1:0] qpll_qplloutrefclk,
output qpll_qplld,
output [1:0] qpll_qpllreset,
output qpll_drp_clk,
output qpll_drp_rst_n,
output qpll_drp_ovrd,
output qpll_drp_gen3,
output qpll_drp_start,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk,
output reg user_reset,
output user_lnk_up,
output user_app_rdy,
input s_axis_rq_tlast,
input [C_DATA_WIDTH-1:0] s_axis_rq_tdata,
input [59:0] s_axis_rq_tuser,
input [KEEP_WIDTH-1:0] s_axis_rq_tkeep,
output [3:0] s_axis_rq_tready,
input s_axis_rq_tvalid,
output [C_DATA_WIDTH-1:0] m_axis_rc_tdata,
output [74:0] m_axis_rc_tuser,
output m_axis_rc_tlast,
output [KEEP_WIDTH-1:0] m_axis_rc_tkeep,
output m_axis_rc_tvalid,
input [21:0] m_axis_rc_tready,
output [C_DATA_WIDTH-1:0] m_axis_cq_tdata,
output [84:0] m_axis_cq_tuser,
output m_axis_cq_tlast,
output [KEEP_WIDTH-1:0] m_axis_cq_tkeep,
output m_axis_cq_tvalid,
input [21:0] m_axis_cq_tready,
input [C_DATA_WIDTH-1:0] s_axis_cc_tdata,
input [32:0] s_axis_cc_tuser,
input s_axis_cc_tlast,
input [KEEP_WIDTH-1:0] s_axis_cc_tkeep,
input s_axis_cc_tvalid,
output [3:0] s_axis_cc_tready,
output [3:0] pcie_rq_seq_num,
output pcie_rq_seq_num_vld,
output [5:0] pcie_rq_tag,
output pcie_rq_tag_vld,
output [1:0] pcie_tfc_nph_av,
output [1:0] pcie_tfc_npd_av,
input pcie_cq_np_req,
output [5:0] pcie_cq_np_req_count,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------------------------------------//
// EP and RP //
//----------------------------------------------------------------------------------------------------------------//
output cfg_phy_link_down,
output [1:0] cfg_phy_link_status,
output [3:0] cfg_negotiated_width,
output [2:0] cfg_current_speed,
output [2:0] cfg_max_payload,
output [2:0] cfg_max_read_req,
output [7:0] cfg_function_status,
output [5:0] cfg_function_power_state,
output [11:0] cfg_vf_status,
output [17:0] cfg_vf_power_state,
output [1:0] cfg_link_power_state,
// Management Interface
input [18:0] cfg_mgmt_addr,
input cfg_mgmt_write,
input [31:0] cfg_mgmt_write_data,
input [3:0] cfg_mgmt_byte_enable,
input cfg_mgmt_read,
output [31:0] cfg_mgmt_read_data,
output cfg_mgmt_read_write_done,
input cfg_mgmt_type1_cfg_reg_access,
// Error Reporting Interface
output cfg_err_cor_out,
output cfg_err_nonfatal_out,
output cfg_err_fatal_out,
// output cfg_local_error,
output cfg_ltr_enable,
output [5:0] cfg_ltssm_state,
output [1:0] cfg_rcb_status,
output [1:0] cfg_dpa_substate_change,
output [1:0] cfg_obff_enable,
output cfg_pl_status_change,
output [1:0] cfg_tph_requester_enable,
output [5:0] cfg_tph_st_mode,
output [5:0] cfg_vf_tph_requester_enable,
output [17:0] cfg_vf_tph_st_mode,
output cfg_msg_received,
output [7:0] cfg_msg_received_data,
output [4:0] cfg_msg_received_type,
input cfg_msg_transmit,
input [2:0] cfg_msg_transmit_type,
input [31:0] cfg_msg_transmit_data,
output cfg_msg_transmit_done,
output [7:0] cfg_fc_ph,
output [11:0] cfg_fc_pd,
output [7:0] cfg_fc_nph,
output [11:0] cfg_fc_npd,
output [7:0] cfg_fc_cplh,
output [11:0] cfg_fc_cpld,
input [2:0] cfg_fc_sel,
input [2:0] cfg_per_func_status_control,
output [15:0] cfg_per_func_status_data,
input [2:0] cfg_per_function_number,
input cfg_per_function_output_request,
output cfg_per_function_update_done,
input [15:0] cfg_subsys_vend_id,
input [63:0] cfg_dsn,
input cfg_power_state_change_ack,
output cfg_power_state_change_interrupt,
input cfg_err_cor_in,
input cfg_err_uncor_in,
output [1:0] cfg_flr_in_process,
input [1:0] cfg_flr_done,
output [5:0] cfg_vf_flr_in_process,
input [5:0] cfg_vf_flr_done,
input cfg_link_training_enable,
output cfg_ext_read_received,
output cfg_ext_write_received,
output [9:0] cfg_ext_register_number,
output [7:0] cfg_ext_function_number,
output [31:0] cfg_ext_write_data,
output [3:0] cfg_ext_write_byte_enable,
input [31:0] cfg_ext_read_data,
input cfg_ext_read_data_valid,
// Interrupt Interface Signals
input [3:0] cfg_interrupt_int,
input [1:0] cfg_interrupt_pending,
output cfg_interrupt_sent,
output [1:0] cfg_interrupt_msi_enable,
output [5:0] cfg_interrupt_msi_vf_enable,
output [5:0] cfg_interrupt_msi_mmenable,
output cfg_interrupt_msi_mask_update,
output [31:0] cfg_interrupt_msi_data,
input [3:0] cfg_interrupt_msi_select,
input [31:0] cfg_interrupt_msi_int,
input [63:0] cfg_interrupt_msi_pending_status,
output cfg_interrupt_msi_sent,
output cfg_interrupt_msi_fail,
output [1:0] cfg_interrupt_msix_enable,
output [1:0] cfg_interrupt_msix_mask,
output [5:0] cfg_interrupt_msix_vf_enable,
output [5:0] cfg_interrupt_msix_vf_mask,
input [31:0] cfg_interrupt_msix_data,
input [63:0] cfg_interrupt_msix_address,
input cfg_interrupt_msix_int,
output cfg_interrupt_msix_sent,
output cfg_interrupt_msix_fail,
input [2:0] cfg_interrupt_msi_attr,
input cfg_interrupt_msi_tph_present,
input [1:0] cfg_interrupt_msi_tph_type,
input [8:0] cfg_interrupt_msi_tph_st_tag,
input [2:0] cfg_interrupt_msi_function_number,
output cfg_hot_reset_out,
input cfg_config_space_enable,
input cfg_req_pm_transition_l23_ready,
//----------------------------------------------------------------------------------------------------------------//
// RP Only //
//----------------------------------------------------------------------------------------------------------------//
input cfg_hot_reset_in,
input [7:0] cfg_ds_port_number,
input [7:0] cfg_ds_bus_number,
input [4:0] cfg_ds_device_number,
input [2:0] cfg_ds_function_number,
//----------------------------------------------------------------------------------------------------------------//
// 6. TPH Interface //
//----------------------------------------------------------------------------------------------------------------//
input [4:0] user_tph_stt_address,
input [2:0] user_tph_function_num,
output [31:0] user_tph_stt_read_data,
output user_tph_stt_read_data_valid,
input user_tph_stt_read_enable,
//----------------------------------------------------------------------------------------------------------------//
// 7. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire sys_clk,
input wire sys_reset,
input pipe_mmcm_rst_n,
//--------------TRANSCEIVER_DEBUG---------------------------------
input [ 2:0] pipe_txprbssel,
input [ 2:0] pipe_rxprbssel,
input pipe_txprbsforceerr,
input pipe_rxprbscntreset,
input [ 2:0] pipe_loopback,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxprbserr,
output [4:0] pipe_rst_fsm,
output [11:0] pipe_qrst_fsm,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*5)-1:0] pipe_rate_fsm,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*6)-1:0] pipe_sync_fsm_tx,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_sync_fsm_rx,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_drp_fsm,
output pipe_rst_idle,
output pipe_qrst_idle,
output pipe_rate_idle,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_eyescandataerror,
output [PL_LINK_CAP_MAX_LINK_WIDTH*3-1:0] pipe_rxstatus,
output [PL_LINK_CAP_MAX_LINK_WIDTH*15-1:0] pipe_dmonitorout,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_cpll_lock,
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] pipe_qpll_lock,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxpmaresetdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxbufstatus,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphaligndone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphinitdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txdlysresetdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxphaligndone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxdlysresetdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxsyncdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxdisperr,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxnotintable,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxcommadet,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] gt_ch_drp_rdy,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_0,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_1,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_2,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_3,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_4,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_5,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_6,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_7,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_8,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_9,
output [31:0] pipe_debug,
//---- PIPE Ports to Core Top Level for PIPE Mode Simulation with 3rd Party IP/BFM/Xilinx BFM ------------------------
input [25:0] common_commands_in,
input [83:0] pipe_rx_0_sigs,
input [83:0] pipe_rx_1_sigs,
input [83:0] pipe_rx_2_sigs,
input [83:0] pipe_rx_3_sigs,
input [83:0] pipe_rx_4_sigs,
input [83:0] pipe_rx_5_sigs,
input [83:0] pipe_rx_6_sigs,
input [83:0] pipe_rx_7_sigs,
output [16:0] common_commands_out,
output [69:0] pipe_tx_0_sigs,
output [69:0] pipe_tx_1_sigs,
output [69:0] pipe_tx_2_sigs,
output [69:0] pipe_tx_3_sigs,
output [69:0] pipe_tx_4_sigs,
output [69:0] pipe_tx_5_sigs,
output [69:0] pipe_tx_6_sigs,
output [69:0] pipe_tx_7_sigs,
//--------------Channel DRP---------------------------------
output ext_ch_gt_drpclk,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdi,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdo,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy,
//----------------------------------------------------------------------------------------------------------------//
// 9. Tandem PROM/PCIE ICAP Primitive Ports //
//----------------------------------------------------------------------------------------------------------------//
input icap_clk,
input icap_csib,
input icap_rdwrb,
input [31:0] icap_i,
output [31:0] icap_o,
output pcie_drp_rdy,
output [15:0] pcie_drp_do,
input pcie_drp_clk,
input pcie_drp_en,
input pcie_drp_we,
input [10:0] pcie_drp_addr,
input [15:0] pcie_drp_di,
//----------------------------------------------------------------------------------------------------------------//
// 10. Tandem PROM/PCIE STARTUP primitive Ports //
//----------------------------------------------------------------------------------------------------------------//
// This input should be used when the startup block is generated exteranl to the PCI Express Core
input startup_eos_in, // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive.
// These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core.
output startup_cfgclk, // 1-bit output: Configuration main clock output
output startup_cfgmclk, // 1-bit output: Configuration internal oscillator clock output
output startup_eos, // 1-bit output: Active high output signal indicating the End Of Startup
output startup_preq, // 1-bit output: PROGRAM request to fabric output
input startup_clk, // 1-bit input: User start-up clock input
input startup_gsr, // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
input startup_gts, // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
input startup_keyclearb, // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
input startup_pack, // 1-bit input: PROGRAM acknowledge input
input startup_usrcclko, // 1-bit input: User CCLK input
input startup_usrcclkts, // 1-bit input: User CCLK 3-state enable input
input startup_usrdoneo, // 1-bit input: User DONE pin output control
input startup_usrdonets // 1-bit input: User DONE 3-state enable output
);
localparam integer USER_CLK_FREQ = ((PL_LINK_CAP_MAX_LINK_SPEED == 3'h4) ? 5 : 4);
localparam [1:0] CRM_USER_CLK_FREQ = ((USER_CLK2_FREQ == 4) ? 2'b10: ((USER_CLK2_FREQ == 3) ? 2'b01 : 2'b00));
localparam [1:0] AXISTEN_IF_WIDTH = (C_DATA_WIDTH == 256) ? 2'b10 : ((C_DATA_WIDTH == 128) ? 2'b01 : 2'b00);
localparam CRM_CORE_CLK_FREQ_500 = ((PL_LINK_CAP_MAX_LINK_SPEED == 3'h4) ? "TRUE" : "FALSE");
localparam INTERFACE_SPEED = ((PL_LINK_CAP_MAX_LINK_SPEED == 3'h4) ? "500 MHZ" : "250 MHZ");
localparam ENABLE_FAST_SIM_TRAINING = "TRUE";
wire drp_clk_wire;
wire drp_en_wire;
wire drp_we_wire;
wire [10:0] drp_addr_wire;
wire [15:0] drp_di_wire;
wire drp_rdy_wire;
wire [15:0] drp_do_wire;
wire dt_654524_drp_clk;
wire dt_654524_drp_en;
wire dt_654524_drp_we;
wire [10:0] dt_654524_drp_addr;
wire [15:0] dt_654524_drp_di;
wire cfg_local_error;
wire rec_clk;
wire pipe_clk;
wire core_clk;
wire [15:0] cfg_vend_id = PF0_VENDOR_ID;
wire [15:0] cfg_dev_id = PF0_DEVICE_ID;
wire [7:0] cfg_rev_id = PF0_REVISION_ID;
// wire [15:0] cfg_subsys_vend_id = PF0_SUBSYSTEM_VENDOR_ID;
wire [15:0] cfg_subsys_id = PF0_SUBSYSTEM_ID;
// PIPE Interface Wires
wire pipe_tx_reset;
wire pipe_rx0_polarity;
wire pipe_rx1_polarity;
wire pipe_rx2_polarity;
wire pipe_rx3_polarity;
wire pipe_rx4_polarity;
wire pipe_rx5_polarity;
wire pipe_rx6_polarity;
wire pipe_rx7_polarity;
wire pipe_tx0_compliance;
wire pipe_tx1_compliance;
wire pipe_tx2_compliance;
wire pipe_tx3_compliance;
wire pipe_tx4_compliance;
wire pipe_tx5_compliance;
wire pipe_tx6_compliance;
wire pipe_tx7_compliance;
wire pipe_rx0_data_valid;
wire pipe_rx1_data_valid;
wire pipe_rx2_data_valid;
wire pipe_rx3_data_valid;
wire pipe_rx4_data_valid;
wire pipe_rx5_data_valid;
wire pipe_rx6_data_valid;
wire pipe_rx7_data_valid;
wire pipe_tx0_elec_idle;
wire pipe_tx1_elec_idle;
wire pipe_tx2_elec_idle;
wire pipe_tx3_elec_idle;
wire pipe_tx4_elec_idle;
wire pipe_tx5_elec_idle;
wire pipe_tx6_elec_idle;
wire pipe_tx7_elec_idle;
wire pipe_rx0_start_block;
wire pipe_rx1_start_block;
wire pipe_rx2_start_block;
wire pipe_rx3_start_block;
wire pipe_rx4_start_block;
wire pipe_rx5_start_block;
wire pipe_rx6_start_block;
wire pipe_rx7_start_block;
wire pipe_tx_deemph;
wire pipe_tx_rcvr_det;
wire [1:0] pipe_tx_rate;
wire [2:0] pipe_tx_margin;
wire pipe_tx_swing;
wire [5:0] pipe_tx_eqfs;
wire [5:0] pipe_tx_eqlf;
wire [1:0] pipe_rx0_eqcontrol;
wire [1:0] pipe_rx1_eqcontrol;
wire [1:0] pipe_rx2_eqcontrol;
wire [1:0] pipe_rx3_eqcontrol;
wire [1:0] pipe_rx4_eqcontrol;
wire [1:0] pipe_rx5_eqcontrol;
wire [1:0] pipe_rx6_eqcontrol;
wire [1:0] pipe_rx7_eqcontrol;
wire [1:0] pipe_tx0_char_is_k;
wire [1:0] pipe_tx1_char_is_k;
wire [1:0] pipe_tx2_char_is_k;
wire [1:0] pipe_tx3_char_is_k;
wire [1:0] pipe_tx4_char_is_k;
wire [1:0] pipe_tx5_char_is_k;
wire [1:0] pipe_tx6_char_is_k;
wire [1:0] pipe_tx7_char_is_k;
wire [1:0] pipe_tx0_eqcontrol;
wire [1:0] pipe_tx1_eqcontrol;
wire [1:0] pipe_tx2_eqcontrol;
wire [1:0] pipe_tx3_eqcontrol;
wire [1:0] pipe_tx4_eqcontrol;
wire [1:0] pipe_tx5_eqcontrol;
wire [1:0] pipe_tx6_eqcontrol;
wire [1:0] pipe_tx7_eqcontrol;
wire [1:0] pipe_tx0_powerdown;
wire [1:0] pipe_tx1_powerdown;
wire [1:0] pipe_tx2_powerdown;
wire [1:0] pipe_tx3_powerdown;
wire [1:0] pipe_tx4_powerdown;
wire [1:0] pipe_tx5_powerdown;
wire [1:0] pipe_tx6_powerdown;
wire [1:0] pipe_tx7_powerdown;
wire [1:0] pipe_rx0_syncheader;
wire [1:0] pipe_rx1_syncheader;
wire [1:0] pipe_rx2_syncheader;
wire [1:0] pipe_rx3_syncheader;
wire [1:0] pipe_rx4_syncheader;
wire [1:0] pipe_rx5_syncheader;
wire [1:0] pipe_rx6_syncheader;
wire [1:0] pipe_rx7_syncheader;
wire [2:0] pipe_rx0_eqpreset;
wire [2:0] pipe_rx1_eqpreset;
wire [2:0] pipe_rx2_eqpreset;
wire [2:0] pipe_rx3_eqpreset;
wire [2:0] pipe_rx4_eqpreset;
wire [2:0] pipe_rx5_eqpreset;
wire [2:0] pipe_rx6_eqpreset;
wire [2:0] pipe_rx7_eqpreset;
wire [31:0] pipe_tx0_data;
wire [31:0] pipe_tx1_data;
wire [31:0] pipe_tx2_data;
wire [31:0] pipe_tx3_data;
wire [31:0] pipe_tx4_data;
wire [31:0] pipe_tx5_data;
wire [31:0] pipe_tx6_data;
wire [31:0] pipe_tx7_data;
wire [3:0] pipe_rx0_eq_txpreset;
wire [3:0] pipe_rx1_eq_txpreset;
wire [3:0] pipe_rx2_eq_txpreset;
wire [3:0] pipe_rx3_eq_txpreset;
wire [3:0] pipe_rx4_eq_txpreset;
wire [3:0] pipe_rx5_eq_txpreset;
wire [3:0] pipe_rx6_eq_txpreset;
wire [3:0] pipe_rx7_eq_txpreset;
wire [3:0] pipe_tx0_eqpreset;
wire [3:0] pipe_tx1_eqpreset;
wire [3:0] pipe_tx2_eqpreset;
wire [3:0] pipe_tx3_eqpreset;
wire [3:0] pipe_tx4_eqpreset;
wire [3:0] pipe_tx5_eqpreset;
wire [3:0] pipe_tx6_eqpreset;
wire [3:0] pipe_tx7_eqpreset;
wire [5:0] pipe_rx0_eq_lffs;
wire [5:0] pipe_rx1_eq_lffs;
wire [5:0] pipe_rx2_eq_lffs;
wire [5:0] pipe_rx3_eq_lffs;
wire [5:0] pipe_rx4_eq_lffs;
wire [5:0] pipe_rx5_eq_lffs;
wire [5:0] pipe_rx6_eq_lffs;
wire [5:0] pipe_rx7_eq_lffs;
wire [5:0] pipe_tx0_eqdeemph;
wire [5:0] pipe_tx1_eqdeemph;
wire [5:0] pipe_tx2_eqdeemph;
wire [5:0] pipe_tx3_eqdeemph;
wire [5:0] pipe_tx4_eqdeemph;
wire [5:0] pipe_tx5_eqdeemph;
wire [5:0] pipe_tx6_eqdeemph;
wire [5:0] pipe_tx7_eqdeemph;
wire [7:0] pipe_rx_slide;
wire pipe_rx0_elec_idle;
wire pipe_rx1_elec_idle;
wire pipe_rx2_elec_idle;
wire pipe_rx3_elec_idle;
wire pipe_rx4_elec_idle;
wire pipe_rx5_elec_idle;
wire pipe_rx6_elec_idle;
wire pipe_rx7_elec_idle;
wire pipe_rx0_eqdone;
wire pipe_rx1_eqdone;
wire pipe_rx2_eqdone;
wire pipe_rx3_eqdone;
wire pipe_rx4_eqdone;
wire pipe_rx5_eqdone;
wire pipe_rx6_eqdone;
wire pipe_rx7_eqdone;
wire pipe_rx0_eq_adapt_done;
wire pipe_rx1_eq_adapt_done;
wire pipe_rx2_eq_adapt_done;
wire pipe_rx3_eq_adapt_done;
wire pipe_rx4_eq_adapt_done;
wire pipe_rx5_eq_adapt_done;
wire pipe_rx6_eq_adapt_done;
wire pipe_rx7_eq_adapt_done;
wire pipe_rx0_eq_lffs_sel;
wire pipe_rx1_eq_lffs_sel;
wire pipe_rx2_eq_lffs_sel;
wire pipe_rx3_eq_lffs_sel;
wire pipe_rx4_eq_lffs_sel;
wire pipe_rx5_eq_lffs_sel;
wire pipe_rx6_eq_lffs_sel;
wire pipe_rx7_eq_lffs_sel;
wire pipe_rx0_phy_status;
wire pipe_rx1_phy_status;
wire pipe_rx2_phy_status;
wire pipe_rx3_phy_status;
wire pipe_rx4_phy_status;
wire pipe_rx5_phy_status;
wire pipe_rx6_phy_status;
wire pipe_rx7_phy_status;
wire pipe_rx0_valid;
wire pipe_rx1_valid;
wire pipe_rx2_valid;
wire pipe_rx3_valid;
wire pipe_rx4_valid;
wire pipe_rx5_valid;
wire pipe_rx6_valid;
wire pipe_rx7_valid;
wire pipe_tx0_eqdone;
wire pipe_tx1_eqdone;
wire pipe_tx2_eqdone;
wire pipe_tx3_eqdone;
wire pipe_tx4_eqdone;
wire pipe_tx5_eqdone;
wire pipe_tx6_eqdone;
wire pipe_tx7_eqdone;
wire [17:0] pipe_rx0_eq_new_txcoeff;
wire [17:0] pipe_rx1_eq_new_txcoeff;
wire [17:0] pipe_rx2_eq_new_txcoeff;
wire [17:0] pipe_rx3_eq_new_txcoeff;
wire [17:0] pipe_rx4_eq_new_txcoeff;
wire [17:0] pipe_rx5_eq_new_txcoeff;
wire [17:0] pipe_rx6_eq_new_txcoeff;
wire [17:0] pipe_rx7_eq_new_txcoeff;
wire [17:0] pipe_tx0_eqcoeff;
wire [17:0] pipe_tx1_eqcoeff;
wire [17:0] pipe_tx2_eqcoeff;
wire [17:0] pipe_tx3_eqcoeff;
wire [17:0] pipe_tx4_eqcoeff;
wire [17:0] pipe_tx5_eqcoeff;
wire [17:0] pipe_tx6_eqcoeff;
wire [17:0] pipe_tx7_eqcoeff;
wire [1:0] pipe_rx0_char_is_k;
wire [1:0] pipe_rx1_char_is_k;
wire [1:0] pipe_rx2_char_is_k;
wire [1:0] pipe_rx3_char_is_k;
wire [1:0] pipe_rx4_char_is_k;
wire [1:0] pipe_rx5_char_is_k;
wire [1:0] pipe_rx6_char_is_k;
wire [1:0] pipe_rx7_char_is_k;
wire [2:0] pipe_rx0_status;
wire [2:0] pipe_rx1_status;
wire [2:0] pipe_rx2_status;
wire [2:0] pipe_rx3_status;
wire [2:0] pipe_rx4_status;
wire [2:0] pipe_rx5_status;
wire [2:0] pipe_rx6_status;
wire [2:0] pipe_rx7_status;
wire [31:0] pipe_rx0_data;
wire [31:0] pipe_rx1_data;
wire [31:0] pipe_rx2_data;
wire [31:0] pipe_rx3_data;
wire [31:0] pipe_rx4_data;
wire [31:0] pipe_rx5_data;
wire [31:0] pipe_rx6_data;
wire [31:0] pipe_rx7_data;
wire [7:0] pipe_rx_syncdone;
wire sys_or_hot_rst;
wire user_lnk_up_int;
reg user_reset_int;
// Wire Declaration for Inputs that are issolated in Tandem configuration
wire cfg_mgmt_write_wire;
wire cfg_mgmt_read_wire;
wire [2:0] cfg_per_func_status_control_wire;
wire cfg_per_function_output_request_wire;
wire [63:0] cfg_dsn_wire;
wire cfg_power_state_change_ack_wire;
wire cfg_err_cor_in_wire;
wire cfg_err_uncor_in_wire;
wire [1:0] cfg_flr_done_wire;
wire [5:0] cfg_vf_flr_done_wire;
wire cfg_link_training_enable_wire;
wire cfg_ext_read_data_valid_wire;
wire [1:0] cfg_interrupt_pending_wire;
wire [3:0] cfg_interrupt_msi_select_wire;
wire [63:0] cfg_interrupt_msi_pending_status_wire;
wire cfg_config_space_enable_wire;
wire cfg_req_pm_transition_l23_ready_wire;
wire cfg_hot_reset_in_wire;
wire [7:0] cfg_ds_port_number_wire;
wire [7:0] cfg_ds_bus_number_wire;
wire [4:0] cfg_ds_device_number_wire;
wire [2:0] cfg_ds_function_number_wire;
wire [4:0] user_tph_stt_address_wire;
wire [2:0] user_tph_function_num_wire;
wire user_tph_stt_read_enable_wire;
// Wire Declaration for Outputs that are issolated in Tandem configuration
wire cfg_phy_link_down_wire;
wire [1:0] cfg_phy_link_status_wire;
wire [5:0] cfg_ltssm_state_wire;
wire cfg_hot_reset_out_wire;
// Wire Declarations for tandem_cplr to pcie_top connections
wire [C_DATA_WIDTH-1:0] s_axis_cc_tdata_wire;
wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_wire;
wire s_axis_cc_tlast_wire;
wire s_axis_cc_tvalid_wire;
wire [32:0] s_axis_cc_tuser_wire;
wire [3:0] s_axis_cc_tready_wire;
wire s_axis_rq_tlast_wire;
wire [C_DATA_WIDTH-1:0] s_axis_rq_tdata_wire;
wire [59:0] s_axis_rq_tuser_wire;
wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_wire;
wire [3:0] s_axis_rq_tready_wire;
wire s_axis_rq_tvalid_wire;
wire cfg_msg_transmit_done_wire;
wire cfg_msg_transmit_wire;
wire [2:0] cfg_msg_transmit_type_wire;
wire [31:0] cfg_msg_transmit_data_wire;
wire [5:0] pcie_rq_tag_wire;
wire pcie_rq_tag_vld_wire;
wire [1:0] pcie_tfc_nph_av_wire;
wire [1:0] pcie_tfc_npd_av_wire;
wire [3:0] pcie_rq_seq_num_wire;
wire pcie_rq_seq_num_vld_wire;
wire [7:0] cfg_fc_ph_wire;
wire [7:0] cfg_fc_nph_wire;
wire [7:0] cfg_fc_cplh_wire;
wire [11:0] cfg_fc_pd_wire;
wire [11:0] cfg_fc_npd_wire;
wire [11:0] cfg_fc_cpld_wire;
wire [2:0] cfg_fc_sel_wire;
wire [C_DATA_WIDTH-1:0] m_axis_cq_tdata_wire;
wire m_axis_cq_tlast_wire;
wire m_axis_cq_tvalid_wire;
wire [84:0] m_axis_cq_tuser_wire;
wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep_wire;
wire [21:0] m_axis_cq_tready_wire;
wire pcie_cq_np_req_wire;
wire [5:0] pcie_cq_np_req_count_wire;
wire [C_DATA_WIDTH-1:0] m_axis_rc_tdata_wire;
wire m_axis_rc_tlast_wire;
wire m_axis_rc_tvalid_wire;
wire [74:0] m_axis_rc_tuser_wire;
wire [KEEP_WIDTH-1:0] m_axis_rc_tkeep_wire;
wire [21:0] m_axis_rc_tready_wire;
wire cfg_msg_received_wire;
wire [4:0] cfg_msg_received_type_wire;
wire [7:0] cfg_msg_received_data_wire;
wire [3:0] cfg_interrupt_int_wire;
wire [31:0] cfg_interrupt_msi_int_wire;
wire cfg_interrupt_msix_int_wire;
wire [C_DATA_WIDTH-1:0] s_axis_cc_tdata_cplr;
wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_cplr;
wire s_axis_cc_tlast_cplr;
wire s_axis_cc_tvalid_cplr;
wire [32:0] s_axis_cc_tuser_cplr;
wire m_axis_cq_tready_cplr;
wire s_axis_rq_tlast_cplr;
wire [C_DATA_WIDTH-1:0] s_axis_rq_tdata_cplr;
wire [59:0] s_axis_rq_tuser_cplr;
wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_cplr;
wire s_axis_rq_tvalid_cplr;
wire cfg_msg_transmit_cplr;
wire [2:0] cfg_msg_transmit_type_cplr;
wire [31:0] cfg_msg_transmit_data_cplr;
wire [2:0] cfg_fc_sel_cplr;
wire pcie_cq_np_req_cplr;
wire m_axis_rc_tready_cplr;
wire mmcm_lock;
// user_app_rdy signals which control the issolation muxes
wire user_app_rdy_req;
// Variables and Parameters for Pipe mode Simulation
wire [7:0] pipe_rxeq_user_en ;
wire [143:0] pipe_rxeq_user_txcoeff ;
generate
if(PIPE_SIM_MODE=="FALSE") begin
assign pipe_rxeq_user_en = 8'h00 ;
assign pipe_rxeq_user_txcoeff = 144'h0 ;
assign pipe_rx0_data_valid = 1'b0;
assign pipe_rx1_data_valid = 1'b0;
assign pipe_rx2_data_valid = 1'b0;
assign pipe_rx3_data_valid = 1'b0;
assign pipe_rx4_data_valid = 1'b0;
assign pipe_rx5_data_valid = 1'b0;
assign pipe_rx6_data_valid = 1'b0;
assign pipe_rx7_data_valid = 1'b0;
assign pipe_rx0_start_block = 1'b0;
assign pipe_rx1_start_block = 1'b0;
assign pipe_rx2_start_block = 1'b0;
assign pipe_rx3_start_block = 1'b0;
assign pipe_rx4_start_block = 1'b0;
assign pipe_rx5_start_block = 1'b0;
assign pipe_rx6_start_block = 1'b0;
assign pipe_rx7_start_block = 1'b0;
assign pipe_rx0_syncheader = 2'b0;
assign pipe_rx1_syncheader = 2'b0;
assign pipe_rx2_syncheader = 2'b0;
assign pipe_rx3_syncheader = 2'b0;
assign pipe_rx4_syncheader = 2'b0;
assign pipe_rx5_syncheader = 2'b0;
assign pipe_rx6_syncheader = 2'b0;
assign pipe_rx7_syncheader = 2'b0;
end
else begin
assign pipe_rxeq_user_en = 8'hff;
assign pipe_rxeq_user_txcoeff = {8{6'd00,6'd30,6'd10}} ;
end
endgenerate
//------------------------------------------------------------------------------------------------------------------//
// Convert incoming reset from AXI required active High //
// to active low as that is what is required by GT and PCIe Block //
//------------------------------------------------------------------------------------------------------------------//
wire sys_rst_n;
wire PIPE_MMCM_LOCK_IN_wire;
assign sys_rst_n = !sys_reset;
assign PIPE_MMCM_LOCK_IN_wire = pipe_mmcm_lock_in;
assign user_lnk_up_int = (cfg_phy_link_status_wire == 2'b11) ? 1'b1 : 1'b0;
assign sys_or_hot_rst = !sys_rst_n || cfg_hot_reset_out_wire;
//------------------------------------------------------------------------------------------------------------------//
// Generate user_reset //
// Once user reset output of PCIE and Phy Layer is active, de-assert reset //
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise //
//------------------------------------------------------------------------------------------------------------------//
always @(posedge user_clk or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (cfg_phy_link_status_wire[1] && !cfg_phy_link_down_wire) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset <= #TCQ 1'b1;
end else begin
user_reset <= #TCQ user_reset_int;
end
end
pcie3_7x_0_pcie_top #(
.TCQ ( TCQ ),
.PIPE_SIM_MODE (PIPE_SIM_MODE ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.ARI_CAP_ENABLE ( ARI_CAP_ENABLE ),
.AXISTEN_IF_CC_ALIGNMENT_MODE ( AXISTEN_IF_CC_ALIGNMENT_MODE ),
.AXISTEN_IF_CC_PARITY_CHK ( AXISTEN_IF_CC_PARITY_CHK ),
.AXISTEN_IF_CQ_ALIGNMENT_MODE ( AXISTEN_IF_CQ_ALIGNMENT_MODE ),
.AXISTEN_IF_ENABLE_CLIENT_TAG ( AXISTEN_IF_ENABLE_CLIENT_TAG ),
.AXISTEN_IF_ENABLE_MSG_ROUTE ( AXISTEN_IF_ENABLE_MSG_ROUTE ),
.AXISTEN_IF_ENABLE_RX_MSG_INTFC ( AXISTEN_IF_ENABLE_RX_MSG_INTFC ),
.AXISTEN_IF_RC_ALIGNMENT_MODE ( AXISTEN_IF_RC_ALIGNMENT_MODE ),
.AXISTEN_IF_RC_STRADDLE ( AXISTEN_IF_RC_STRADDLE ),
.AXISTEN_IF_RQ_ALIGNMENT_MODE ( AXISTEN_IF_RQ_ALIGNMENT_MODE ),
.AXISTEN_IF_RQ_PARITY_CHK ( AXISTEN_IF_RQ_PARITY_CHK ),
.AXISTEN_IF_WIDTH ( AXISTEN_IF_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CRM_CORE_CLK_FREQ_500 ( CRM_CORE_CLK_FREQ_500 ),
.CRM_USER_CLK_FREQ ( CRM_USER_CLK_FREQ ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.GEN3_PCS_AUTO_REALIGN ( GEN3_PCS_AUTO_REALIGN ),
.GEN3_PCS_RX_ELECIDLE_INTERNAL ( GEN3_PCS_RX_ELECIDLE_INTERNAL ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_CPL_FC_UPDATE_TIMER ( LL_CPL_FC_UPDATE_TIMER ),
.LL_CPL_FC_UPDATE_TIMER_OVERRIDE ( LL_CPL_FC_UPDATE_TIMER_OVERRIDE ),
.LL_FC_UPDATE_TIMER ( LL_FC_UPDATE_TIMER ),
.LL_FC_UPDATE_TIMER_OVERRIDE ( LL_FC_UPDATE_TIMER_OVERRIDE ),
.LL_NP_FC_UPDATE_TIMER ( LL_NP_FC_UPDATE_TIMER ),
.LL_NP_FC_UPDATE_TIMER_OVERRIDE ( LL_NP_FC_UPDATE_TIMER_OVERRIDE ),
.LL_P_FC_UPDATE_TIMER ( LL_P_FC_UPDATE_TIMER ),
.LL_P_FC_UPDATE_TIMER_OVERRIDE ( LL_P_FC_UPDATE_TIMER_OVERRIDE ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTR_TX_MESSAGE_MINIMUM_INTERVAL ( LTR_TX_MESSAGE_MINIMUM_INTERVAL ),
.LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE ( LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE ),
.LTR_TX_MESSAGE_ON_LTR_ENABLE ( LTR_TX_MESSAGE_ON_LTR_ENABLE ),
.PF0_AER_CAP_ECRC_CHECK_CAPABLE ( PF0_AER_CAP_ECRC_CHECK_CAPABLE ),
.PF0_AER_CAP_ECRC_GEN_CAPABLE ( PF0_AER_CAP_ECRC_GEN_CAPABLE ),
.PF0_AER_CAP_NEXTPTR ( PF0_AER_CAP_NEXTPTR ),
.PF0_ARI_CAP_NEXTPTR ( PF0_ARI_CAP_NEXTPTR ),
.PF0_ARI_CAP_NEXT_FUNC ( PF0_ARI_CAP_NEXT_FUNC ),
.PF0_ARI_CAP_VER ( PF0_ARI_CAP_VER ),
.PF0_BAR0_APERTURE_SIZE ( PF0_BAR0_APERTURE_SIZE ),
.PF0_BAR0_CONTROL ( PF0_BAR0_CONTROL ),
.PF0_BAR1_APERTURE_SIZE ( PF0_BAR1_APERTURE_SIZE ),
.PF0_BAR1_CONTROL ( PF0_BAR1_CONTROL ),
.PF0_BAR2_APERTURE_SIZE ( PF0_BAR2_APERTURE_SIZE ),
.PF0_BAR2_CONTROL ( PF0_BAR2_CONTROL ),
.PF0_BAR3_APERTURE_SIZE ( PF0_BAR3_APERTURE_SIZE ),
.PF0_BAR3_CONTROL ( PF0_BAR3_CONTROL ),
.PF0_BAR4_APERTURE_SIZE ( PF0_BAR4_APERTURE_SIZE ),
.PF0_BAR4_CONTROL ( PF0_BAR4_CONTROL ),
.PF0_BAR5_APERTURE_SIZE ( PF0_BAR5_APERTURE_SIZE ),
.PF0_BAR5_CONTROL ( PF0_BAR5_CONTROL ),
.PF0_BIST_REGISTER ( PF0_BIST_REGISTER ),
.PF0_CAPABILITY_POINTER ( PF0_CAPABILITY_POINTER ),
.PF0_CLASS_CODE ( PF0_CLASS_CODE ),
.PF0_DEVICE_ID ( PF0_DEVICE_ID ),
.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE ( PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE ),
.PF0_DEV_CAP2_LTR_SUPPORT ( PF0_DEV_CAP2_LTR_SUPPORT ),
.PF0_DEV_CAP2_OBFF_SUPPORT ( PF0_DEV_CAP2_OBFF_SUPPORT ),
.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT ( PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT ),
.PF0_DEV_CAP_ENDPOINT_L0S_LATENCY ( PF0_DEV_CAP_ENDPOINT_L0S_LATENCY ),
.PF0_DEV_CAP_ENDPOINT_L1_LATENCY ( PF0_DEV_CAP_ENDPOINT_L1_LATENCY ),
.PF0_DEV_CAP_EXT_TAG_SUPPORTED ( PF0_DEV_CAP_EXT_TAG_SUPPORTED ),
.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.PF0_DEV_CAP_MAX_PAYLOAD_SIZE ( PF0_DEV_CAP_MAX_PAYLOAD_SIZE ),
.PF0_DPA_CAP_NEXTPTR ( PF0_DPA_CAP_NEXTPTR ),
.VF0_ARI_CAP_NEXTPTR ( VF0_ARI_CAP_NEXTPTR ),
.VF1_ARI_CAP_NEXTPTR ( VF1_ARI_CAP_NEXTPTR ),
.VF2_ARI_CAP_NEXTPTR ( VF2_ARI_CAP_NEXTPTR ),
.VF3_ARI_CAP_NEXTPTR ( VF3_ARI_CAP_NEXTPTR ),
.VF4_ARI_CAP_NEXTPTR ( VF4_ARI_CAP_NEXTPTR ),
.VF5_ARI_CAP_NEXTPTR ( VF5_ARI_CAP_NEXTPTR ),
.VF0_TPHR_CAP_DEV_SPECIFIC_MODE ( VF0_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF0_TPHR_CAP_ENABLE ( VF0_TPHR_CAP_ENABLE ),
.VF0_TPHR_CAP_INT_VEC_MODE ( VF0_TPHR_CAP_INT_VEC_MODE ),
.VF0_TPHR_CAP_NEXTPTR ( VF0_TPHR_CAP_NEXTPTR ),
.VF0_TPHR_CAP_ST_MODE_SEL ( VF0_TPHR_CAP_ST_MODE_SEL ),
.VF0_TPHR_CAP_ST_TABLE_LOC ( VF0_TPHR_CAP_ST_TABLE_LOC ),
.VF0_TPHR_CAP_ST_TABLE_SIZE ( VF0_TPHR_CAP_ST_TABLE_SIZE ),
.VF0_TPHR_CAP_VER ( VF0_TPHR_CAP_VER ),
.VF1_TPHR_CAP_DEV_SPECIFIC_MODE ( VF1_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF1_TPHR_CAP_ENABLE ( VF1_TPHR_CAP_ENABLE ),
.VF1_TPHR_CAP_INT_VEC_MODE ( VF1_TPHR_CAP_INT_VEC_MODE ),
.VF1_TPHR_CAP_NEXTPTR ( VF1_TPHR_CAP_NEXTPTR ),
.VF1_TPHR_CAP_ST_MODE_SEL ( VF1_TPHR_CAP_ST_MODE_SEL ),
.VF1_TPHR_CAP_ST_TABLE_LOC ( VF1_TPHR_CAP_ST_TABLE_LOC ),
.VF1_TPHR_CAP_ST_TABLE_SIZE ( VF1_TPHR_CAP_ST_TABLE_SIZE ),
.VF1_TPHR_CAP_VER ( VF1_TPHR_CAP_VER ),
.VF2_TPHR_CAP_DEV_SPECIFIC_MODE ( VF2_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF2_TPHR_CAP_ENABLE ( VF2_TPHR_CAP_ENABLE ),
.VF2_TPHR_CAP_INT_VEC_MODE ( VF2_TPHR_CAP_INT_VEC_MODE ),
.VF2_TPHR_CAP_NEXTPTR ( VF2_TPHR_CAP_NEXTPTR ),
.VF2_TPHR_CAP_ST_MODE_SEL ( VF2_TPHR_CAP_ST_MODE_SEL ),
.VF2_TPHR_CAP_ST_TABLE_LOC ( VF2_TPHR_CAP_ST_TABLE_LOC ),
.VF2_TPHR_CAP_ST_TABLE_SIZE ( VF2_TPHR_CAP_ST_TABLE_SIZE ),
.VF2_TPHR_CAP_VER ( VF2_TPHR_CAP_VER ),
.VF3_TPHR_CAP_DEV_SPECIFIC_MODE ( VF3_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF3_TPHR_CAP_ENABLE ( VF3_TPHR_CAP_ENABLE ),
.VF3_TPHR_CAP_INT_VEC_MODE ( VF3_TPHR_CAP_INT_VEC_MODE ),
.VF3_TPHR_CAP_NEXTPTR ( VF3_TPHR_CAP_NEXTPTR ),
.VF3_TPHR_CAP_ST_MODE_SEL ( VF3_TPHR_CAP_ST_MODE_SEL ),
.VF3_TPHR_CAP_ST_TABLE_LOC ( VF3_TPHR_CAP_ST_TABLE_LOC ),
.VF3_TPHR_CAP_ST_TABLE_SIZE ( VF3_TPHR_CAP_ST_TABLE_SIZE ),
.VF3_TPHR_CAP_VER ( VF3_TPHR_CAP_VER ),
.VF4_TPHR_CAP_DEV_SPECIFIC_MODE ( VF4_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF4_TPHR_CAP_ENABLE ( VF4_TPHR_CAP_ENABLE ),
.VF4_TPHR_CAP_INT_VEC_MODE ( VF4_TPHR_CAP_INT_VEC_MODE ),
.VF4_TPHR_CAP_NEXTPTR ( VF4_TPHR_CAP_NEXTPTR ),
.VF4_TPHR_CAP_ST_MODE_SEL ( VF4_TPHR_CAP_ST_MODE_SEL ),
.VF4_TPHR_CAP_ST_TABLE_LOC ( VF4_TPHR_CAP_ST_TABLE_LOC ),
.VF4_TPHR_CAP_ST_TABLE_SIZE ( VF4_TPHR_CAP_ST_TABLE_SIZE ),
.VF4_TPHR_CAP_VER ( VF4_TPHR_CAP_VER ),
.VF5_TPHR_CAP_DEV_SPECIFIC_MODE ( VF5_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF5_TPHR_CAP_ENABLE ( VF5_TPHR_CAP_ENABLE ),
.VF5_TPHR_CAP_INT_VEC_MODE ( VF5_TPHR_CAP_INT_VEC_MODE ),
.VF5_TPHR_CAP_NEXTPTR ( VF5_TPHR_CAP_NEXTPTR ),
.VF5_TPHR_CAP_ST_MODE_SEL ( VF5_TPHR_CAP_ST_MODE_SEL ),
.VF5_TPHR_CAP_ST_TABLE_LOC ( VF5_TPHR_CAP_ST_TABLE_LOC ),
.VF5_TPHR_CAP_ST_TABLE_SIZE ( VF5_TPHR_CAP_ST_TABLE_SIZE ),
.VF5_TPHR_CAP_VER ( VF5_TPHR_CAP_VER ),
.PF0_DPA_CAP_SUB_STATE_CONTROL ( PF0_DPA_CAP_SUB_STATE_CONTROL ),
.PF0_DPA_CAP_SUB_STATE_CONTROL_EN ( PF0_DPA_CAP_SUB_STATE_CONTROL_EN ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ),
.PF0_DPA_CAP_VER ( PF0_DPA_CAP_VER ),
.PF0_DSN_CAP_NEXTPTR ( PF0_DSN_CAP_NEXTPTR ),
.PF0_EXPANSION_ROM_APERTURE_SIZE ( PF0_EXPANSION_ROM_APERTURE_SIZE ),
.PF0_EXPANSION_ROM_ENABLE ( PF0_EXPANSION_ROM_ENABLE ),
.PF0_INTERRUPT_LINE ( PF0_INTERRUPT_LINE ),
.PF0_INTERRUPT_PIN ( PF0_INTERRUPT_PIN ),
.PF0_LINK_CAP_ASPM_SUPPORT ( PF0_LINK_CAP_ASPM_SUPPORT ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 ),
.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG ( PF0_LINK_STATUS_SLOT_CLOCK_CONFIG ),
.PF0_LTR_CAP_MAX_NOSNOOP_LAT ( PF0_LTR_CAP_MAX_NOSNOOP_LAT ),
.PF0_LTR_CAP_MAX_SNOOP_LAT ( PF0_LTR_CAP_MAX_SNOOP_LAT ),
.PF0_LTR_CAP_NEXTPTR ( PF0_LTR_CAP_NEXTPTR ),
.PF0_LTR_CAP_VER ( PF0_LTR_CAP_VER ),
.PF0_MSIX_CAP_NEXTPTR ( PF0_MSIX_CAP_NEXTPTR ),
.PF0_MSIX_CAP_PBA_BIR ( PF0_MSIX_CAP_PBA_BIR ),
.PF0_MSIX_CAP_PBA_OFFSET ( PF0_MSIX_CAP_PBA_OFFSET ),
.PF0_MSIX_CAP_TABLE_BIR ( PF0_MSIX_CAP_TABLE_BIR ),
.PF0_MSIX_CAP_TABLE_OFFSET ( PF0_MSIX_CAP_TABLE_OFFSET ),
.PF0_MSIX_CAP_TABLE_SIZE ( PF0_MSIX_CAP_TABLE_SIZE ),
.PF0_MSI_CAP_MULTIMSGCAP ( PF0_MSI_CAP_MULTIMSGCAP ),
.PF0_MSI_CAP_NEXTPTR ( PF0_MSI_CAP_NEXTPTR ),
.PF0_PB_CAP_NEXTPTR ( PF0_PB_CAP_NEXTPTR ),
.PF0_PB_CAP_SYSTEM_ALLOCATED ( PF0_PB_CAP_SYSTEM_ALLOCATED ),
.PF0_PB_CAP_VER ( PF0_PB_CAP_VER ),
.PF0_PM_CAP_ID ( PF0_PM_CAP_ID ),
.PF0_PM_CAP_NEXTPTR ( PF0_PM_CAP_NEXTPTR ),
.PF0_PM_CAP_PMESUPPORT_D0 ( PF0_PM_CAP_PMESUPPORT_D0 ),
.PF0_PM_CAP_PMESUPPORT_D1 ( PF0_PM_CAP_PMESUPPORT_D1 ),
.PF0_PM_CAP_PMESUPPORT_D3HOT ( PF0_PM_CAP_PMESUPPORT_D3HOT ),
.PF0_PM_CAP_SUPP_D1_STATE ( PF0_PM_CAP_SUPP_D1_STATE ),
.PF0_PM_CAP_VER_ID ( PF0_PM_CAP_VER_ID ),
.PF0_PM_CSR_NOSOFTRESET ( PF0_PM_CSR_NOSOFTRESET ),
.PF0_RBAR_CAP_ENABLE ( PF0_RBAR_CAP_ENABLE ),
.PF0_RBAR_CAP_INDEX0 ( PF0_RBAR_CAP_INDEX0 ),
.PF0_RBAR_CAP_INDEX1 ( PF0_RBAR_CAP_INDEX1 ),
.PF0_RBAR_CAP_INDEX2 ( PF0_RBAR_CAP_INDEX2 ),
.PF0_RBAR_CAP_NEXTPTR ( PF0_RBAR_CAP_NEXTPTR ),
.PF0_RBAR_CAP_SIZE0 ( PF0_RBAR_CAP_SIZE0 ),
.PF0_RBAR_CAP_SIZE1 ( PF0_RBAR_CAP_SIZE1 ),
.PF0_RBAR_CAP_SIZE2 ( PF0_RBAR_CAP_SIZE2 ),
.PF0_RBAR_CAP_VER ( PF0_RBAR_CAP_VER ),
.PF0_RBAR_NUM ( PF0_RBAR_NUM ),
.PF0_REVISION_ID ( PF0_REVISION_ID ),
.PF0_SRIOV_BAR0_APERTURE_SIZE ( PF0_SRIOV_BAR0_APERTURE_SIZE ),
.PF0_SRIOV_BAR0_CONTROL ( PF0_SRIOV_BAR0_CONTROL ),
.PF0_SRIOV_BAR1_APERTURE_SIZE ( PF0_SRIOV_BAR1_APERTURE_SIZE ),
.PF0_SRIOV_BAR1_CONTROL ( PF0_SRIOV_BAR1_CONTROL ),
.PF0_SRIOV_BAR2_APERTURE_SIZE ( PF0_SRIOV_BAR2_APERTURE_SIZE ),
.PF0_SRIOV_BAR2_CONTROL ( PF0_SRIOV_BAR2_CONTROL ),
.PF0_SRIOV_BAR3_APERTURE_SIZE ( PF0_SRIOV_BAR3_APERTURE_SIZE ),
.PF0_SRIOV_BAR3_CONTROL ( PF0_SRIOV_BAR3_CONTROL ),
.PF0_SRIOV_BAR4_APERTURE_SIZE ( PF0_SRIOV_BAR4_APERTURE_SIZE ),
.PF0_SRIOV_BAR4_CONTROL ( PF0_SRIOV_BAR4_CONTROL ),
.PF0_SRIOV_BAR5_APERTURE_SIZE ( PF0_SRIOV_BAR5_APERTURE_SIZE ),
.PF0_SRIOV_BAR5_CONTROL ( PF0_SRIOV_BAR5_CONTROL ),
.PF0_SRIOV_CAP_INITIAL_VF ( PF0_SRIOV_CAP_INITIAL_VF ),
.PF0_SRIOV_CAP_NEXTPTR ( PF0_SRIOV_CAP_NEXTPTR ),
.PF0_SRIOV_CAP_TOTAL_VF ( PF0_SRIOV_CAP_TOTAL_VF ),
.PF0_SRIOV_CAP_VER ( PF0_SRIOV_CAP_VER ),
.PF0_SRIOV_FIRST_VF_OFFSET ( PF0_SRIOV_FIRST_VF_OFFSET ),
.PF0_SRIOV_FUNC_DEP_LINK ( PF0_SRIOV_FUNC_DEP_LINK ),
.PF0_SRIOV_SUPPORTED_PAGE_SIZE ( PF0_SRIOV_SUPPORTED_PAGE_SIZE ),
.PF0_SRIOV_VF_DEVICE_ID ( PF0_SRIOV_VF_DEVICE_ID ),
.PF0_SUBSYSTEM_ID ( PF0_SUBSYSTEM_ID ),
.PF0_TPHR_CAP_DEV_SPECIFIC_MODE ( PF0_TPHR_CAP_DEV_SPECIFIC_MODE ),
.PF0_TPHR_CAP_ENABLE ( PF0_TPHR_CAP_ENABLE ),
.PF0_TPHR_CAP_INT_VEC_MODE ( PF0_TPHR_CAP_INT_VEC_MODE ),
.PF0_TPHR_CAP_NEXTPTR ( PF0_TPHR_CAP_NEXTPTR ),
.PF0_TPHR_CAP_ST_MODE_SEL ( PF0_TPHR_CAP_ST_MODE_SEL ),
.PF0_TPHR_CAP_ST_TABLE_LOC ( PF0_TPHR_CAP_ST_TABLE_LOC ),
.PF0_TPHR_CAP_ST_TABLE_SIZE ( PF0_TPHR_CAP_ST_TABLE_SIZE ),
.PF0_TPHR_CAP_VER ( PF0_TPHR_CAP_VER ),
.PF0_VC_CAP_NEXTPTR ( PF0_VC_CAP_NEXTPTR ),
.PF0_VC_CAP_VER ( PF0_VC_CAP_VER ),
.PF1_AER_CAP_ECRC_CHECK_CAPABLE ( PF1_AER_CAP_ECRC_CHECK_CAPABLE ),
.PF1_AER_CAP_ECRC_GEN_CAPABLE ( PF1_AER_CAP_ECRC_GEN_CAPABLE ),
.PF1_AER_CAP_NEXTPTR ( PF1_AER_CAP_NEXTPTR ),
.PF1_ARI_CAP_NEXTPTR ( PF1_ARI_CAP_NEXTPTR ),
.PF1_ARI_CAP_NEXT_FUNC ( PF1_ARI_CAP_NEXT_FUNC ),
.PF1_BAR0_APERTURE_SIZE ( PF1_BAR0_APERTURE_SIZE ),
.PF1_BAR0_CONTROL ( PF1_BAR0_CONTROL ),
.PF1_BAR1_APERTURE_SIZE ( PF1_BAR1_APERTURE_SIZE ),
.PF1_BAR1_CONTROL ( PF1_BAR1_CONTROL ),
.PF1_BAR2_APERTURE_SIZE ( PF1_BAR2_APERTURE_SIZE ),
.PF1_BAR2_CONTROL ( PF1_BAR2_CONTROL ),
.PF1_BAR3_APERTURE_SIZE ( PF1_BAR3_APERTURE_SIZE ),
.PF1_BAR3_CONTROL ( PF1_BAR3_CONTROL ),
.PF1_BAR4_APERTURE_SIZE ( PF1_BAR4_APERTURE_SIZE ),
.PF1_BAR4_CONTROL ( PF1_BAR4_CONTROL ),
.PF1_BAR5_APERTURE_SIZE ( PF1_BAR5_APERTURE_SIZE ),
.PF1_BAR5_CONTROL ( PF1_BAR5_CONTROL ),
.PF1_BIST_REGISTER ( PF1_BIST_REGISTER ),
.PF1_CAPABILITY_POINTER ( PF1_CAPABILITY_POINTER ),
.PF1_CLASS_CODE ( PF1_CLASS_CODE ),
.PF1_DEVICE_ID ( PF1_DEVICE_ID ),
.PF1_DEV_CAP_MAX_PAYLOAD_SIZE ( PF1_DEV_CAP_MAX_PAYLOAD_SIZE ),
.PF1_DPA_CAP_NEXTPTR ( PF1_DPA_CAP_NEXTPTR ),
.PF1_DPA_CAP_SUB_STATE_CONTROL ( PF1_DPA_CAP_SUB_STATE_CONTROL ),
.PF1_DPA_CAP_SUB_STATE_CONTROL_EN ( PF1_DPA_CAP_SUB_STATE_CONTROL_EN ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ),
.PF1_DPA_CAP_VER ( PF1_DPA_CAP_VER ),
.PF1_DSN_CAP_NEXTPTR ( PF1_DSN_CAP_NEXTPTR ),
.PF1_EXPANSION_ROM_APERTURE_SIZE ( PF1_EXPANSION_ROM_APERTURE_SIZE ),
.PF1_EXPANSION_ROM_ENABLE ( PF1_EXPANSION_ROM_ENABLE ),
.PF1_INTERRUPT_LINE ( PF1_INTERRUPT_LINE ),
.PF1_INTERRUPT_PIN ( PF1_INTERRUPT_PIN ),
.PF1_MSIX_CAP_NEXTPTR ( PF1_MSIX_CAP_NEXTPTR ),
.PF1_MSIX_CAP_PBA_BIR ( PF1_MSIX_CAP_PBA_BIR ),
.PF1_MSIX_CAP_PBA_OFFSET ( PF1_MSIX_CAP_PBA_OFFSET ),
.PF1_MSIX_CAP_TABLE_BIR ( PF1_MSIX_CAP_TABLE_BIR ),
.PF1_MSIX_CAP_TABLE_OFFSET ( PF1_MSIX_CAP_TABLE_OFFSET ),
.PF1_MSIX_CAP_TABLE_SIZE ( PF1_MSIX_CAP_TABLE_SIZE ),
.PF1_MSI_CAP_MULTIMSGCAP ( PF1_MSI_CAP_MULTIMSGCAP ),
.PF1_MSI_CAP_NEXTPTR ( PF1_MSI_CAP_NEXTPTR ),
.PF1_PB_CAP_NEXTPTR ( PF1_PB_CAP_NEXTPTR ),
.PF1_PB_CAP_SYSTEM_ALLOCATED ( PF1_PB_CAP_SYSTEM_ALLOCATED ),
.PF1_PB_CAP_VER ( PF1_PB_CAP_VER ),
.PF1_PM_CAP_ID ( PF1_PM_CAP_ID ),
.PF1_PM_CAP_NEXTPTR ( PF1_PM_CAP_NEXTPTR ),
.PF1_PM_CAP_VER_ID ( PF1_PM_CAP_VER_ID ),
.PF1_RBAR_CAP_ENABLE ( PF1_RBAR_CAP_ENABLE ),
.PF1_RBAR_CAP_INDEX0 ( PF1_RBAR_CAP_INDEX0 ),
.PF1_RBAR_CAP_INDEX1 ( PF1_RBAR_CAP_INDEX1 ),
.PF1_RBAR_CAP_INDEX2 ( PF1_RBAR_CAP_INDEX2 ),
.PF1_RBAR_CAP_NEXTPTR ( PF1_RBAR_CAP_NEXTPTR ),
.PF1_RBAR_CAP_SIZE0 ( PF1_RBAR_CAP_SIZE0 ),
.PF1_RBAR_CAP_SIZE1 ( PF1_RBAR_CAP_SIZE1 ),
.PF1_RBAR_CAP_SIZE2 ( PF1_RBAR_CAP_SIZE2 ),
.PF1_RBAR_CAP_VER ( PF1_RBAR_CAP_VER ),
.PF1_RBAR_NUM ( PF1_RBAR_NUM ),
.PF1_REVISION_ID ( PF1_REVISION_ID ),
.PF1_SRIOV_BAR0_APERTURE_SIZE ( PF1_SRIOV_BAR0_APERTURE_SIZE ),
.PF1_SRIOV_BAR0_CONTROL ( PF1_SRIOV_BAR0_CONTROL ),
.PF1_SRIOV_BAR1_APERTURE_SIZE ( PF1_SRIOV_BAR1_APERTURE_SIZE ),
.PF1_SRIOV_BAR1_CONTROL ( PF1_SRIOV_BAR1_CONTROL ),
.PF1_SRIOV_BAR2_APERTURE_SIZE ( PF1_SRIOV_BAR2_APERTURE_SIZE ),
.PF1_SRIOV_BAR2_CONTROL ( PF1_SRIOV_BAR2_CONTROL ),
.PF1_SRIOV_BAR3_APERTURE_SIZE ( PF1_SRIOV_BAR3_APERTURE_SIZE ),
.PF1_SRIOV_BAR3_CONTROL ( PF1_SRIOV_BAR3_CONTROL ),
.PF1_SRIOV_BAR4_APERTURE_SIZE ( PF1_SRIOV_BAR4_APERTURE_SIZE ),
.PF1_SRIOV_BAR4_CONTROL ( PF1_SRIOV_BAR4_CONTROL ),
.PF1_SRIOV_BAR5_APERTURE_SIZE ( PF1_SRIOV_BAR5_APERTURE_SIZE ),
.PF1_SRIOV_BAR5_CONTROL ( PF1_SRIOV_BAR5_CONTROL ),
.PF1_SRIOV_CAP_INITIAL_VF ( PF1_SRIOV_CAP_INITIAL_VF ),
.PF1_SRIOV_CAP_NEXTPTR ( PF1_SRIOV_CAP_NEXTPTR ),
.PF1_SRIOV_CAP_TOTAL_VF ( PF1_SRIOV_CAP_TOTAL_VF ),
.PF1_SRIOV_CAP_VER ( PF1_SRIOV_CAP_VER ),
.PF1_SRIOV_FIRST_VF_OFFSET ( PF1_SRIOV_FIRST_VF_OFFSET ),
.PF1_SRIOV_FUNC_DEP_LINK ( PF1_SRIOV_FUNC_DEP_LINK ),
.PF1_SRIOV_SUPPORTED_PAGE_SIZE ( PF1_SRIOV_SUPPORTED_PAGE_SIZE ),
.PF1_SRIOV_VF_DEVICE_ID ( PF1_SRIOV_VF_DEVICE_ID ),
.PF1_SUBSYSTEM_ID ( PF1_SUBSYSTEM_ID ),
.PF1_TPHR_CAP_DEV_SPECIFIC_MODE ( PF1_TPHR_CAP_DEV_SPECIFIC_MODE ),
.PF1_TPHR_CAP_ENABLE ( PF1_TPHR_CAP_ENABLE ),
.PF1_TPHR_CAP_INT_VEC_MODE ( PF1_TPHR_CAP_INT_VEC_MODE ),
.PF1_TPHR_CAP_NEXTPTR ( PF1_TPHR_CAP_NEXTPTR ),
.PF1_TPHR_CAP_ST_MODE_SEL ( PF1_TPHR_CAP_ST_MODE_SEL ),
.PF1_TPHR_CAP_ST_TABLE_LOC ( PF1_TPHR_CAP_ST_TABLE_LOC ),
.PF1_TPHR_CAP_ST_TABLE_SIZE ( PF1_TPHR_CAP_ST_TABLE_SIZE ),
.PF1_TPHR_CAP_VER ( PF1_TPHR_CAP_VER ),
.PL_DISABLE_EI_INFER_IN_L0 ( PL_DISABLE_EI_INFER_IN_L0 ),
.PL_DISABLE_GEN3_DC_BALANCE ( PL_DISABLE_GEN3_DC_BALANCE ),
.PL_DISABLE_SCRAMBLING ( PL_DISABLE_SCRAMBLING ),
.PL_DISABLE_UPCONFIG_CAPABLE ( PL_DISABLE_UPCONFIG_CAPABLE ),
.PL_EQ_ADAPT_DISABLE_COEFF_CHECK ( PL_EQ_ADAPT_DISABLE_COEFF_CHECK ),
.PL_EQ_ADAPT_DISABLE_PRESET_CHECK ( PL_EQ_ADAPT_DISABLE_PRESET_CHECK ),
.PL_EQ_ADAPT_ITER_COUNT ( PL_EQ_ADAPT_ITER_COUNT ),
.PL_EQ_ADAPT_REJECT_RETRY_COUNT ( PL_EQ_ADAPT_REJECT_RETRY_COUNT ),
.PL_EQ_BYPASS_PHASE23 ( PL_EQ_BYPASS_PHASE23 ),
.PL_EQ_SHORT_ADAPT_PHASE ( PL_EQ_SHORT_ADAPT_PHASE ),
.PL_LANE0_EQ_CONTROL ( PL_LANE0_EQ_CONTROL ),
.PL_LANE1_EQ_CONTROL ( PL_LANE1_EQ_CONTROL ),
.PL_LANE2_EQ_CONTROL ( PL_LANE2_EQ_CONTROL ),
.PL_LANE3_EQ_CONTROL ( PL_LANE3_EQ_CONTROL ),
.PL_LANE4_EQ_CONTROL ( PL_LANE4_EQ_CONTROL ),
.PL_LANE5_EQ_CONTROL ( PL_LANE5_EQ_CONTROL ),
.PL_LANE6_EQ_CONTROL ( PL_LANE6_EQ_CONTROL ),
.PL_LANE7_EQ_CONTROL ( PL_LANE7_EQ_CONTROL ),
.PL_LINK_CAP_MAX_LINK_SPEED ( PL_LINK_CAP_MAX_LINK_SPEED ),
.PL_LINK_CAP_MAX_LINK_WIDTH ( PL_LINK_CAP_MAX_LINK_WIDTH ),
.PL_N_FTS_COMCLK_GEN1 ( PL_N_FTS_COMCLK_GEN1 ),
.PL_N_FTS_COMCLK_GEN2 ( PL_N_FTS_COMCLK_GEN2 ),
.PL_N_FTS_COMCLK_GEN3 ( PL_N_FTS_COMCLK_GEN3 ),
.PL_N_FTS_GEN1 ( PL_N_FTS_GEN1 ),
.PL_N_FTS_GEN2 ( PL_N_FTS_GEN2 ),
.PL_N_FTS_GEN3 ( PL_N_FTS_GEN3 ),
// synthesis translate_off
.PL_SIM_FAST_LINK_TRAINING ( ENABLE_FAST_SIM_TRAINING ),
// synthesis translate_on
.PL_UPSTREAM_FACING ( PL_UPSTREAM_FACING ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML1_ENTRY_DELAY ( PM_ASPML1_ENTRY_DELAY ),
.PM_ENABLE_SLOT_POWER_CAPTURE ( PM_ENABLE_SLOT_POWER_CAPTURE ),
.PM_L1_REENTRY_DELAY ( PM_L1_REENTRY_DELAY ),
.PM_PME_SERVICE_TIMEOUT_DELAY ( PM_PME_SERVICE_TIMEOUT_DELAY ),
.PM_PME_TURNOFF_ACK_DELAY ( PM_PME_TURNOFF_ACK_DELAY ),
.SIM_VERSION ( SIM_VERSION ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SRIOV_CAP_ENABLE ( SRIOV_CAP_ENABLE ),
.TL_COMPL_TIMEOUT_REG0 ( TL_COMPL_TIMEOUT_REG0 ),
.TL_COMPL_TIMEOUT_REG1 ( TL_COMPL_TIMEOUT_REG1 ),
.TL_CREDITS_CD ( TL_CREDITS_CD ),
.TL_CREDITS_CH ( TL_CREDITS_CH ),
.TL_CREDITS_NPD ( TL_CREDITS_NPD ),
.TL_CREDITS_NPH ( TL_CREDITS_NPH ),
.TL_CREDITS_PD ( TL_CREDITS_PD ),
.TL_CREDITS_PH ( TL_CREDITS_PH ),
.TL_ENABLE_MESSAGE_RID_CHECK_ENABLE ( TL_ENABLE_MESSAGE_RID_CHECK_ENABLE ),
.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE ( TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE ),
.TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE ( TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE ),
.TL_LEGACY_MODE_ENABLE ( TL_LEGACY_MODE_ENABLE ),
.TL_PF_ENABLE_REG ( TL_PF_ENABLE_REG ),
.TL_TAG_MGMT_ENABLE ( TL_TAG_MGMT_ENABLE ),
.VF0_CAPABILITY_POINTER ( VF0_CAPABILITY_POINTER ),
.VF0_MSIX_CAP_PBA_BIR ( VF0_MSIX_CAP_PBA_BIR ),
.VF0_MSIX_CAP_PBA_OFFSET ( VF0_MSIX_CAP_PBA_OFFSET ),
.VF0_MSIX_CAP_TABLE_BIR ( VF0_MSIX_CAP_TABLE_BIR ),
.VF0_MSIX_CAP_TABLE_OFFSET ( VF0_MSIX_CAP_TABLE_OFFSET ),
.VF0_MSIX_CAP_TABLE_SIZE ( VF0_MSIX_CAP_TABLE_SIZE ),
.VF0_MSI_CAP_MULTIMSGCAP ( VF0_MSI_CAP_MULTIMSGCAP ),
.VF0_PM_CAP_ID ( VF0_PM_CAP_ID ),
.VF0_PM_CAP_NEXTPTR ( VF0_PM_CAP_NEXTPTR ),
.VF0_PM_CAP_VER_ID ( VF0_PM_CAP_VER_ID ),
.VF1_MSIX_CAP_PBA_BIR ( VF1_MSIX_CAP_PBA_BIR ),
.VF1_MSIX_CAP_PBA_OFFSET ( VF1_MSIX_CAP_PBA_OFFSET ),
.VF1_MSIX_CAP_TABLE_BIR ( VF1_MSIX_CAP_TABLE_BIR ),
.VF1_MSIX_CAP_TABLE_OFFSET ( VF1_MSIX_CAP_TABLE_OFFSET ),
.VF1_MSIX_CAP_TABLE_SIZE ( VF1_MSIX_CAP_TABLE_SIZE ),
.VF1_MSI_CAP_MULTIMSGCAP ( VF1_MSI_CAP_MULTIMSGCAP ),
.VF1_PM_CAP_ID ( VF1_PM_CAP_ID ),
.VF1_PM_CAP_NEXTPTR ( VF1_PM_CAP_NEXTPTR ),
.VF1_PM_CAP_VER_ID ( VF1_PM_CAP_VER_ID ),
.VF2_MSIX_CAP_PBA_BIR ( VF2_MSIX_CAP_PBA_BIR ),
.VF2_MSIX_CAP_PBA_OFFSET ( VF2_MSIX_CAP_PBA_OFFSET ),
.VF2_MSIX_CAP_TABLE_BIR ( VF2_MSIX_CAP_TABLE_BIR ),
.VF2_MSIX_CAP_TABLE_OFFSET ( VF2_MSIX_CAP_TABLE_OFFSET ),
.VF2_MSIX_CAP_TABLE_SIZE ( VF2_MSIX_CAP_TABLE_SIZE ),
.VF2_MSI_CAP_MULTIMSGCAP ( VF2_MSI_CAP_MULTIMSGCAP ),
.VF2_PM_CAP_ID ( VF2_PM_CAP_ID ),
.VF2_PM_CAP_NEXTPTR ( VF2_PM_CAP_NEXTPTR ),
.VF2_PM_CAP_VER_ID ( VF2_PM_CAP_VER_ID ),
.VF3_MSIX_CAP_PBA_BIR ( VF3_MSIX_CAP_PBA_BIR ),
.VF3_MSIX_CAP_PBA_OFFSET ( VF3_MSIX_CAP_PBA_OFFSET ),
.VF3_MSIX_CAP_TABLE_BIR ( VF3_MSIX_CAP_TABLE_BIR ),
.VF3_MSIX_CAP_TABLE_OFFSET ( VF3_MSIX_CAP_TABLE_OFFSET ),
.VF3_MSIX_CAP_TABLE_SIZE ( VF3_MSIX_CAP_TABLE_SIZE ),
.VF3_MSI_CAP_MULTIMSGCAP ( VF3_MSI_CAP_MULTIMSGCAP ),
.VF3_PM_CAP_ID ( VF3_PM_CAP_ID ),
.VF3_PM_CAP_NEXTPTR ( VF3_PM_CAP_NEXTPTR ),
.VF3_PM_CAP_VER_ID ( VF3_PM_CAP_VER_ID ),
.VF4_MSIX_CAP_PBA_BIR ( VF4_MSIX_CAP_PBA_BIR ),
.VF4_MSIX_CAP_PBA_OFFSET ( VF4_MSIX_CAP_PBA_OFFSET ),
.VF4_MSIX_CAP_TABLE_BIR ( VF4_MSIX_CAP_TABLE_BIR ),
.VF4_MSIX_CAP_TABLE_OFFSET ( VF4_MSIX_CAP_TABLE_OFFSET ),
.VF4_MSIX_CAP_TABLE_SIZE ( VF4_MSIX_CAP_TABLE_SIZE ),
.VF4_MSI_CAP_MULTIMSGCAP ( VF4_MSI_CAP_MULTIMSGCAP ),
.VF4_PM_CAP_ID ( VF4_PM_CAP_ID ),
.VF4_PM_CAP_NEXTPTR ( VF4_PM_CAP_NEXTPTR ),
.VF4_PM_CAP_VER_ID ( VF4_PM_CAP_VER_ID ),
.VF5_MSIX_CAP_PBA_BIR ( VF5_MSIX_CAP_PBA_BIR ),
.VF5_MSIX_CAP_PBA_OFFSET ( VF5_MSIX_CAP_PBA_OFFSET ),
.VF5_MSIX_CAP_TABLE_BIR ( VF5_MSIX_CAP_TABLE_BIR ),
.VF5_MSIX_CAP_TABLE_OFFSET ( VF5_MSIX_CAP_TABLE_OFFSET ),
.VF5_MSIX_CAP_TABLE_SIZE ( VF5_MSIX_CAP_TABLE_SIZE ),
.VF5_MSI_CAP_MULTIMSGCAP ( VF5_MSI_CAP_MULTIMSGCAP ),
.VF5_PM_CAP_ID ( VF5_PM_CAP_ID ),
.VF5_PM_CAP_NEXTPTR ( VF5_PM_CAP_NEXTPTR ),
.VF5_PM_CAP_VER_ID ( VF5_PM_CAP_VER_ID ),
.IMPL_TARGET ( IMPL_TARGET ),
.NO_DECODE_LOGIC ( NO_DECODE_LOGIC ),
.INTERFACE_SPEED ( INTERFACE_SPEED ),
.COMPLETION_SPACE ( COMPLETION_SPACE )
) pcie_top_i (
.core_clk ( core_clk ), // I
.rec_clk ( rec_clk ), // I
.user_clk ( user_clk ), // I
.pipe_clk ( pipe_clk ), // I
.phy_rdy ( phy_rdy ), // I
.mmcm_lock ( mmcm_lock ), // I
.s_axis_rq_tlast ( s_axis_rq_tlast_wire ), // I
.s_axis_rq_tdata ( s_axis_rq_tdata_wire ), // I
.s_axis_rq_tuser ( s_axis_rq_tuser_wire ), // I
.s_axis_rq_tkeep ( s_axis_rq_tkeep_wire ), // I
.s_axis_rq_tready ( s_axis_rq_tready_wire ), // O
.s_axis_rq_tvalid ( s_axis_rq_tvalid_wire ), // I
.m_axis_rc_tdata ( m_axis_rc_tdata_wire ), // O
.m_axis_rc_tuser ( m_axis_rc_tuser_wire ), // O
.m_axis_rc_tlast ( m_axis_rc_tlast_wire ), // O
.m_axis_rc_tkeep ( m_axis_rc_tkeep_wire ), // O
.m_axis_rc_tvalid ( m_axis_rc_tvalid_wire ), // O
.m_axis_rc_tready ( m_axis_rc_tready_wire ), // I
.m_axis_cq_tdata ( m_axis_cq_tdata_wire ), // O
.m_axis_cq_tuser ( m_axis_cq_tuser_wire ), // O
.m_axis_cq_tlast ( m_axis_cq_tlast_wire ), // O
.m_axis_cq_tkeep ( m_axis_cq_tkeep_wire ), // O
.m_axis_cq_tvalid ( m_axis_cq_tvalid_wire ), // O
.m_axis_cq_tready ( m_axis_cq_tready_wire ), // I
.s_axis_cc_tdata ( s_axis_cc_tdata_wire ), // I
.s_axis_cc_tuser ( s_axis_cc_tuser_wire ), // I
.s_axis_cc_tlast ( s_axis_cc_tlast_wire ), // I
.s_axis_cc_tkeep ( s_axis_cc_tkeep_wire ), // I
.s_axis_cc_tvalid ( s_axis_cc_tvalid_wire ), // I
.s_axis_cc_tready ( s_axis_cc_tready_wire ), // O
.pcie_rq_seq_num ( pcie_rq_seq_num_wire ), // O
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld_wire ), // O
.pcie_rq_tag ( pcie_rq_tag_wire ), // O
.pcie_rq_tag_vld ( pcie_rq_tag_vld_wire ), // O
.pcie_tfc_nph_av ( pcie_tfc_nph_av_wire ), // O
.pcie_tfc_npd_av ( pcie_tfc_npd_av_wire ), // O
.pcie_cq_np_req ( pcie_cq_np_req_wire ), // I
.pcie_cq_np_req_count ( pcie_cq_np_req_count_wire ), // O
.cfg_mgmt_addr ( cfg_mgmt_addr ), // I
.cfg_mgmt_write ( cfg_mgmt_write_wire ), // I
.cfg_mgmt_write_data ( cfg_mgmt_write_data ), // I
.cfg_mgmt_byte_enable ( cfg_mgmt_byte_enable ), // I
.cfg_mgmt_read ( cfg_mgmt_read_wire ), // I
.cfg_mgmt_read_data ( cfg_mgmt_read_data ), // O
.cfg_mgmt_read_write_done ( cfg_mgmt_read_write_done ), // O
.cfg_mgmt_type1_cfg_reg_access ( cfg_mgmt_type1_cfg_reg_access ),// I
.cfg_phy_link_down ( cfg_phy_link_down_wire ), // O
.cfg_phy_link_status ( cfg_phy_link_status_wire ), // O
.cfg_negotiated_width ( cfg_negotiated_width ), // O
.cfg_current_speed ( cfg_current_speed ), // O
.cfg_max_payload ( cfg_max_payload ), // O
.cfg_max_read_req ( cfg_max_read_req ), // O
.cfg_function_status ( cfg_function_status ), // O
.cfg_function_power_state ( cfg_function_power_state ), // O
.cfg_vf_status ( cfg_vf_status ), // O
.cfg_vf_power_state ( cfg_vf_power_state ), // O
.cfg_link_power_state ( cfg_link_power_state ), // O
.cfg_err_cor_out ( cfg_err_cor_out ), // O
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), // O
.cfg_err_fatal_out ( cfg_err_fatal_out ), // O
.cfg_local_error ( cfg_local_error ), // O
.cfg_ltr_enable ( cfg_ltr_enable ), // O
.cfg_ltssm_state ( cfg_ltssm_state_wire ), // O
.cfg_rcb_status ( cfg_rcb_status ), // O
.cfg_dpa_substate_change ( cfg_dpa_substate_change ), // O
.cfg_obff_enable ( cfg_obff_enable ), // O
.cfg_pl_status_change ( cfg_pl_status_change ), // O
.cfg_tph_requester_enable ( cfg_tph_requester_enable ), // O
.cfg_tph_st_mode ( cfg_tph_st_mode ), // O
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), // O
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), // O
.cfg_msg_received ( cfg_msg_received_wire ), // O
.cfg_msg_received_data ( cfg_msg_received_data_wire ), // O
.cfg_msg_received_type ( cfg_msg_received_type_wire ), // O
.cfg_msg_transmit ( cfg_msg_transmit_wire ), // I
.cfg_msg_transmit_type ( cfg_msg_transmit_type_wire ), // I
.cfg_msg_transmit_data ( cfg_msg_transmit_data_wire ), // I
.cfg_msg_transmit_done ( cfg_msg_transmit_done_wire ), // O
.cfg_fc_ph ( cfg_fc_ph_wire ), // O
.cfg_fc_pd ( cfg_fc_pd_wire ), // O
.cfg_fc_nph ( cfg_fc_nph_wire ), // O
.cfg_fc_npd ( cfg_fc_npd_wire ), // O
.cfg_fc_cplh ( cfg_fc_cplh_wire ), // O
.cfg_fc_cpld ( cfg_fc_cpld_wire ), // O
.cfg_fc_sel ( cfg_fc_sel_wire ), // I
.cfg_per_func_status_control ( cfg_per_func_status_control_wire ), // I
.cfg_per_func_status_data ( cfg_per_func_status_data ), // O
.cfg_per_function_number ( cfg_per_function_number ), // I
.cfg_per_function_output_request ( cfg_per_function_output_request_wire ), // I
.cfg_per_function_update_done ( cfg_per_function_update_done ), // O
.cfg_dsn ( cfg_dsn_wire ), // I
.cfg_power_state_change_ack ( cfg_power_state_change_ack_wire ), // I
.cfg_power_state_change_interrupt ( cfg_power_state_change_interrupt ), // O
.cfg_err_cor_in ( cfg_err_cor_in_wire ), // I
.cfg_err_uncor_in ( cfg_err_uncor_in_wire ), // I
.cfg_flr_in_process ( cfg_flr_in_process ), // O
.cfg_flr_done ( cfg_flr_done_wire ), // I
.cfg_vf_flr_in_process ( cfg_vf_flr_in_process ), // O
.cfg_vf_flr_done ( cfg_vf_flr_done_wire ), // I
.cfg_link_training_enable ( cfg_link_training_enable_wire ), // I
.cfg_interrupt_int ( cfg_interrupt_int_wire ), // I
.cfg_interrupt_pending ( cfg_interrupt_pending_wire ), // I
.cfg_interrupt_sent ( cfg_interrupt_sent ), // O
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), // O
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), // O
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), // O
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), // O
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), // O
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select_wire ), // I
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int_wire ), // I
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status_wire ),// I
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), // O
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), // O
.cfg_interrupt_msix_enable ( cfg_interrupt_msix_enable ), // O
.cfg_interrupt_msix_mask ( cfg_interrupt_msix_mask ), // O
.cfg_interrupt_msix_vf_enable ( cfg_interrupt_msix_vf_enable ), // O
.cfg_interrupt_msix_vf_mask ( cfg_interrupt_msix_vf_mask ), // O
.cfg_interrupt_msix_data ( cfg_interrupt_msix_data ), // I
.cfg_interrupt_msix_address ( cfg_interrupt_msix_address ), // I
.cfg_interrupt_msix_int ( cfg_interrupt_msix_int_wire ), // I
.cfg_interrupt_msix_sent ( cfg_interrupt_msix_sent ), // O
.cfg_interrupt_msix_fail ( cfg_interrupt_msix_fail ), // O
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), // I
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), // I
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), // I
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), // I
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), // I
.cfg_ext_read_received ( cfg_ext_read_received ), // O
.cfg_ext_write_received ( cfg_ext_write_received ), // O
.cfg_ext_register_number ( cfg_ext_register_number ), // O
.cfg_ext_function_number ( cfg_ext_function_number ), // O
.cfg_ext_write_data ( cfg_ext_write_data ), // O
.cfg_ext_write_byte_enable ( cfg_ext_write_byte_enable ), // O
.cfg_ext_read_data ( cfg_ext_read_data ), // I
.cfg_ext_read_data_valid ( cfg_ext_read_data_valid_wire ), // I
.cfg_dev_id ( cfg_dev_id ), // I
.cfg_vend_id ( cfg_vend_id ), // I
.cfg_rev_id ( cfg_rev_id ), // I
.cfg_subsys_id ( cfg_subsys_id ), // I
.cfg_subsys_vend_id ( cfg_subsys_vend_id ), // I
.cfg_hot_reset_out ( cfg_hot_reset_out_wire ), // O
.cfg_config_space_enable ( cfg_config_space_enable_wire ), // I
.cfg_req_pm_transition_l23_ready ( cfg_req_pm_transition_l23_ready_wire ), // I
.cfg_hot_reset_in ( cfg_hot_reset_in_wire ), // I
.cfg_ds_port_number ( cfg_ds_port_number_wire ), // I
.cfg_ds_bus_number ( cfg_ds_bus_number_wire ), // I
.cfg_ds_device_number ( cfg_ds_device_number_wire ), // I
.cfg_ds_function_number ( cfg_ds_function_number_wire ), // I
.user_tph_stt_address ( user_tph_stt_address_wire ), // I
.user_tph_function_num ( user_tph_function_num_wire ), // I
.user_tph_stt_read_data ( user_tph_stt_read_data ), // O
.user_tph_stt_read_data_valid ( user_tph_stt_read_data_valid ), // O
.user_tph_stt_read_enable ( user_tph_stt_read_enable_wire ), // I
.drp_rdy ( drp_rdy_wire ), // O
.drp_do ( drp_do_wire ), // O
.drp_clk ( drp_clk_wire ), // I
.drp_en ( drp_en_wire ), // I
.drp_we ( drp_we_wire ), // I
.drp_addr ( drp_addr_wire ), // I
.drp_di ( drp_di_wire ), // I
.pipe_tx_reset_gt ( pipe_tx_reset ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance ),
.pipe_tx0_data_valid_gt ( ),
.pipe_tx1_data_valid_gt ( ),
.pipe_tx2_data_valid_gt ( ),
.pipe_tx3_data_valid_gt ( ),
.pipe_tx4_data_valid_gt ( ),
.pipe_tx5_data_valid_gt ( ),
.pipe_tx6_data_valid_gt ( ),
.pipe_tx7_data_valid_gt ( ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle ),
.pipe_tx0_start_block_gt ( ),
.pipe_tx1_start_block_gt ( ),
.pipe_tx2_start_block_gt ( ),
.pipe_tx3_start_block_gt ( ),
.pipe_tx4_start_block_gt ( ),
.pipe_tx5_start_block_gt ( ),
.pipe_tx6_start_block_gt ( ),
.pipe_tx7_start_block_gt ( ),
.pipe_tx_deemph_gt ( pipe_tx_deemph ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det ),
.pipe_tx_rate_gt ( pipe_tx_rate ),
.pipe_tx_margin_gt ( pipe_tx_margin ),
.pipe_tx_swing_gt ( pipe_tx_swing ),
.pipe_tx_eqfs_gt ( pipe_tx_eqfs ),
.pipe_tx_eqlf_gt ( pipe_tx_eqlf ),
.pipe_rx0_eqcontrol_gt ( pipe_rx0_eqcontrol ),
.pipe_rx1_eqcontrol_gt ( pipe_rx1_eqcontrol ),
.pipe_rx2_eqcontrol_gt ( pipe_rx2_eqcontrol ),
.pipe_rx3_eqcontrol_gt ( pipe_rx3_eqcontrol ),
.pipe_rx4_eqcontrol_gt ( pipe_rx4_eqcontrol ),
.pipe_rx5_eqcontrol_gt ( pipe_rx5_eqcontrol ),
.pipe_rx6_eqcontrol_gt ( pipe_rx6_eqcontrol ),
.pipe_rx7_eqcontrol_gt ( pipe_rx7_eqcontrol ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k ),
.pipe_tx0_eqcontrol_gt ( pipe_tx0_eqcontrol ),
.pipe_tx1_eqcontrol_gt ( pipe_tx1_eqcontrol ),
.pipe_tx2_eqcontrol_gt ( pipe_tx2_eqcontrol ),
.pipe_tx3_eqcontrol_gt ( pipe_tx3_eqcontrol ),
.pipe_tx4_eqcontrol_gt ( pipe_tx4_eqcontrol ),
.pipe_tx5_eqcontrol_gt ( pipe_tx5_eqcontrol ),
.pipe_tx6_eqcontrol_gt ( pipe_tx6_eqcontrol ),
.pipe_tx7_eqcontrol_gt ( pipe_tx7_eqcontrol ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown ),
.pipe_tx0_syncheader_gt ( ),
.pipe_tx1_syncheader_gt ( ),
.pipe_tx2_syncheader_gt ( ),
.pipe_tx3_syncheader_gt ( ),
.pipe_tx4_syncheader_gt ( ),
.pipe_tx5_syncheader_gt ( ),
.pipe_tx6_syncheader_gt ( ),
.pipe_tx7_syncheader_gt ( ),
.pipe_rx0_eqpreset_gt ( pipe_rx0_eqpreset ),
.pipe_rx1_eqpreset_gt ( pipe_rx1_eqpreset ),
.pipe_rx2_eqpreset_gt ( pipe_rx2_eqpreset ),
.pipe_rx3_eqpreset_gt ( pipe_rx3_eqpreset ),
.pipe_rx4_eqpreset_gt ( pipe_rx4_eqpreset ),
.pipe_rx5_eqpreset_gt ( pipe_rx5_eqpreset ),
.pipe_rx6_eqpreset_gt ( pipe_rx6_eqpreset ),
.pipe_rx7_eqpreset_gt ( pipe_rx7_eqpreset ),
.pipe_tx0_data_gt ( pipe_tx0_data ),
.pipe_tx1_data_gt ( pipe_tx1_data ),
.pipe_tx2_data_gt ( pipe_tx2_data ),
.pipe_tx3_data_gt ( pipe_tx3_data ),
.pipe_tx4_data_gt ( pipe_tx4_data ),
.pipe_tx5_data_gt ( pipe_tx5_data ),
.pipe_tx6_data_gt ( pipe_tx6_data ),
.pipe_tx7_data_gt ( pipe_tx7_data ),
.pipe_rx0_eqlp_txpreset_gt ( pipe_rx0_eq_txpreset ),
.pipe_rx1_eqlp_txpreset_gt ( pipe_rx1_eq_txpreset ),
.pipe_rx2_eqlp_txpreset_gt ( pipe_rx2_eq_txpreset ),
.pipe_rx3_eqlp_txpreset_gt ( pipe_rx3_eq_txpreset ),
.pipe_rx4_eqlp_txpreset_gt ( pipe_rx4_eq_txpreset ),
.pipe_rx5_eqlp_txpreset_gt ( pipe_rx5_eq_txpreset ),
.pipe_rx6_eqlp_txpreset_gt ( pipe_rx6_eq_txpreset ),
.pipe_rx7_eqlp_txpreset_gt ( pipe_rx7_eq_txpreset ),
.pipe_tx0_eqpreset_gt ( pipe_tx0_eqpreset ),
.pipe_tx1_eqpreset_gt ( pipe_tx1_eqpreset ),
.pipe_tx2_eqpreset_gt ( pipe_tx2_eqpreset ),
.pipe_tx3_eqpreset_gt ( pipe_tx3_eqpreset ),
.pipe_tx4_eqpreset_gt ( pipe_tx4_eqpreset ),
.pipe_tx5_eqpreset_gt ( pipe_tx5_eqpreset ),
.pipe_tx6_eqpreset_gt ( pipe_tx6_eqpreset ),
.pipe_tx7_eqpreset_gt ( pipe_tx7_eqpreset ),
.pipe_rx0_eqlp_lffs_gt ( pipe_rx0_eq_lffs ),
.pipe_rx1_eqlp_lffs_gt ( pipe_rx1_eq_lffs ),
.pipe_rx2_eqlp_lffs_gt ( pipe_rx2_eq_lffs ),
.pipe_rx3_eqlp_lffs_gt ( pipe_rx3_eq_lffs ),
.pipe_rx4_eqlp_lffs_gt ( pipe_rx4_eq_lffs ),
.pipe_rx5_eqlp_lffs_gt ( pipe_rx5_eq_lffs ),
.pipe_rx6_eqlp_lffs_gt ( pipe_rx6_eq_lffs ),
.pipe_rx7_eqlp_lffs_gt ( pipe_rx7_eq_lffs ),
.pipe_tx0_eqdeemph_gt ( pipe_tx0_eqdeemph ),
.pipe_tx1_eqdeemph_gt ( pipe_tx1_eqdeemph ),
.pipe_tx2_eqdeemph_gt ( pipe_tx2_eqdeemph ),
.pipe_tx3_eqdeemph_gt ( pipe_tx3_eqdeemph ),
.pipe_tx4_eqdeemph_gt ( pipe_tx4_eqdeemph ),
.pipe_tx5_eqdeemph_gt ( pipe_tx5_eqdeemph ),
.pipe_tx6_eqdeemph_gt ( pipe_tx6_eqdeemph ),
.pipe_tx7_eqdeemph_gt ( pipe_tx7_eqdeemph ),
.pipe_rx_slide_gt ( pipe_rx_slide ),
.pipe_rx0_data_valid_gt ( pipe_rx0_data_valid ),
.pipe_rx1_data_valid_gt ( pipe_rx1_data_valid ),
.pipe_rx2_data_valid_gt ( pipe_rx2_data_valid ),
.pipe_rx3_data_valid_gt ( pipe_rx3_data_valid ),
.pipe_rx4_data_valid_gt ( pipe_rx4_data_valid ),
.pipe_rx5_data_valid_gt ( pipe_rx5_data_valid ),
.pipe_rx6_data_valid_gt ( pipe_rx6_data_valid ),
.pipe_rx7_data_valid_gt ( pipe_rx7_data_valid ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle ),
.pipe_rx0_eqdone_gt ( pipe_rx0_eqdone ),
.pipe_rx1_eqdone_gt ( pipe_rx1_eqdone ),
.pipe_rx2_eqdone_gt ( pipe_rx2_eqdone ),
.pipe_rx3_eqdone_gt ( pipe_rx3_eqdone ),
.pipe_rx4_eqdone_gt ( pipe_rx4_eqdone ),
.pipe_rx5_eqdone_gt ( pipe_rx5_eqdone ),
.pipe_rx6_eqdone_gt ( pipe_rx6_eqdone ),
.pipe_rx7_eqdone_gt ( pipe_rx7_eqdone ),
.pipe_rx0_eqlp_adaptdone_gt ( pipe_rx0_eq_adapt_done ),
.pipe_rx1_eqlp_adaptdone_gt ( pipe_rx1_eq_adapt_done ),
.pipe_rx2_eqlp_adaptdone_gt ( pipe_rx2_eq_adapt_done ),
.pipe_rx3_eqlp_adaptdone_gt ( pipe_rx3_eq_adapt_done ),
.pipe_rx4_eqlp_adaptdone_gt ( pipe_rx4_eq_adapt_done ),
.pipe_rx5_eqlp_adaptdone_gt ( pipe_rx5_eq_adapt_done ),
.pipe_rx6_eqlp_adaptdone_gt ( pipe_rx6_eq_adapt_done ),
.pipe_rx7_eqlp_adaptdone_gt ( pipe_rx7_eq_adapt_done ),
.pipe_rx0_eqlp_lffs_sel_gt ( pipe_rx0_eq_lffs_sel ),
.pipe_rx1_eqlp_lffs_sel_gt ( pipe_rx1_eq_lffs_sel ),
.pipe_rx2_eqlp_lffs_sel_gt ( pipe_rx2_eq_lffs_sel ),
.pipe_rx3_eqlp_lffs_sel_gt ( pipe_rx3_eq_lffs_sel ),
.pipe_rx4_eqlp_lffs_sel_gt ( pipe_rx4_eq_lffs_sel ),
.pipe_rx5_eqlp_lffs_sel_gt ( pipe_rx5_eq_lffs_sel ),
.pipe_rx6_eqlp_lffs_sel_gt ( pipe_rx6_eq_lffs_sel ),
.pipe_rx7_eqlp_lffs_sel_gt ( pipe_rx7_eq_lffs_sel ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status ),
.pipe_rx0_start_block_gt ( pipe_rx0_start_block ),
.pipe_rx1_start_block_gt ( pipe_rx1_start_block ),
.pipe_rx2_start_block_gt ( pipe_rx2_start_block ),
.pipe_rx3_start_block_gt ( pipe_rx3_start_block ),
.pipe_rx4_start_block_gt ( pipe_rx4_start_block ),
.pipe_rx5_start_block_gt ( pipe_rx5_start_block ),
.pipe_rx6_start_block_gt ( pipe_rx6_start_block ),
.pipe_rx7_start_block_gt ( pipe_rx7_start_block ),
.pipe_rx0_valid_gt ( pipe_rx0_valid ),
.pipe_rx1_valid_gt ( pipe_rx1_valid ),
.pipe_rx2_valid_gt ( pipe_rx2_valid ),
.pipe_rx3_valid_gt ( pipe_rx3_valid ),
.pipe_rx4_valid_gt ( pipe_rx4_valid ),
.pipe_rx5_valid_gt ( pipe_rx5_valid ),
.pipe_rx6_valid_gt ( pipe_rx6_valid ),
.pipe_rx7_valid_gt ( pipe_rx7_valid ),
.pipe_tx0_eqdone_gt ( pipe_tx0_eqdone ),
.pipe_tx1_eqdone_gt ( pipe_tx1_eqdone ),
.pipe_tx2_eqdone_gt ( pipe_tx2_eqdone ),
.pipe_tx3_eqdone_gt ( pipe_tx3_eqdone ),
.pipe_tx4_eqdone_gt ( pipe_tx4_eqdone ),
.pipe_tx5_eqdone_gt ( pipe_tx5_eqdone ),
.pipe_tx6_eqdone_gt ( pipe_tx6_eqdone ),
.pipe_tx7_eqdone_gt ( pipe_tx7_eqdone ),
.pipe_rx0_eqlp_new_txcoef_forpreset_gt ( pipe_rx0_eq_new_txcoeff ),
.pipe_rx1_eqlp_new_txcoef_forpreset_gt ( pipe_rx1_eq_new_txcoeff ),
.pipe_rx2_eqlp_new_txcoef_forpreset_gt ( pipe_rx2_eq_new_txcoeff ),
.pipe_rx3_eqlp_new_txcoef_forpreset_gt ( pipe_rx3_eq_new_txcoeff ),
.pipe_rx4_eqlp_new_txcoef_forpreset_gt ( pipe_rx4_eq_new_txcoeff ),
.pipe_rx5_eqlp_new_txcoef_forpreset_gt ( pipe_rx5_eq_new_txcoeff ),
.pipe_rx6_eqlp_new_txcoef_forpreset_gt ( pipe_rx6_eq_new_txcoeff ),
.pipe_rx7_eqlp_new_txcoef_forpreset_gt ( pipe_rx7_eq_new_txcoeff ),
.pipe_tx0_eqcoeff_gt ( pipe_tx0_eqcoeff ),
.pipe_tx1_eqcoeff_gt ( pipe_tx1_eqcoeff ),
.pipe_tx2_eqcoeff_gt ( pipe_tx2_eqcoeff ),
.pipe_tx3_eqcoeff_gt ( pipe_tx3_eqcoeff ),
.pipe_tx4_eqcoeff_gt ( pipe_tx4_eqcoeff ),
.pipe_tx5_eqcoeff_gt ( pipe_tx5_eqcoeff ),
.pipe_tx6_eqcoeff_gt ( pipe_tx6_eqcoeff ),
.pipe_tx7_eqcoeff_gt ( pipe_tx7_eqcoeff ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k ),
.pipe_rx0_syncheader_gt ( pipe_rx0_syncheader ),
.pipe_rx1_syncheader_gt ( pipe_rx1_syncheader ),
.pipe_rx2_syncheader_gt ( pipe_rx2_syncheader ),
.pipe_rx3_syncheader_gt ( pipe_rx3_syncheader ),
.pipe_rx4_syncheader_gt ( pipe_rx4_syncheader ),
.pipe_rx5_syncheader_gt ( pipe_rx5_syncheader ),
.pipe_rx6_syncheader_gt ( pipe_rx6_syncheader ),
.pipe_rx7_syncheader_gt ( pipe_rx7_syncheader ),
.pipe_rx0_status_gt ( pipe_rx0_status ),
.pipe_rx1_status_gt ( pipe_rx1_status ),
.pipe_rx2_status_gt ( pipe_rx2_status ),
.pipe_rx3_status_gt ( pipe_rx3_status ),
.pipe_rx4_status_gt ( pipe_rx4_status ),
.pipe_rx5_status_gt ( pipe_rx5_status ),
.pipe_rx6_status_gt ( pipe_rx6_status ),
.pipe_rx7_status_gt ( pipe_rx7_status ),
.pipe_rx0_data_gt ( pipe_rx0_data ),
.pipe_rx1_data_gt ( pipe_rx1_data ),
.pipe_rx2_data_gt ( pipe_rx2_data ),
.pipe_rx3_data_gt ( pipe_rx3_data ),
.pipe_rx4_data_gt ( pipe_rx4_data ),
.pipe_rx5_data_gt ( pipe_rx5_data ),
.pipe_rx6_data_gt ( pipe_rx6_data ),
.pipe_rx7_data_gt ( pipe_rx7_data ),
.pipe_rx_syncdone_gt ( pipe_rx_syncdone )
);
pcie3_7x_0_gt_top #(
.TCQ ( TCQ ),
.PL_LINK_CAP_MAX_LINK_WIDTH ( PL_LINK_CAP_MAX_LINK_WIDTH ),
.PL_LINK_CAP_MAX_LINK_SPEED ( PL_LINK_CAP_MAX_LINK_SPEED ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK2_FREQ ( USER_CLK2_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
// synthesis translate_off
.PL_SIM_FAST_LINK_TRAINING ( ENABLE_FAST_SIM_TRAINING ),
// synthesis translate_on
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_EXT_GT_COMMON ( PCIE_EXT_GT_COMMON ),
.EXT_CH_GT_DRP ( EXT_CH_GT_DRP ),
.TX_MARGIN_FULL_0 ( TX_MARGIN_FULL_0 ),
.TX_MARGIN_FULL_1 ( TX_MARGIN_FULL_1 ),
.TX_MARGIN_FULL_2 ( TX_MARGIN_FULL_2 ),
.TX_MARGIN_FULL_3 ( TX_MARGIN_FULL_3 ),
.TX_MARGIN_FULL_4 ( TX_MARGIN_FULL_4 ),
.TX_MARGIN_LOW_0 ( TX_MARGIN_LOW_0 ),
.TX_MARGIN_LOW_1 ( TX_MARGIN_LOW_1 ),
.TX_MARGIN_LOW_2 ( TX_MARGIN_LOW_2 ),
.TX_MARGIN_LOW_3 ( TX_MARGIN_LOW_3 ),
.TX_MARGIN_LOW_4 ( TX_MARGIN_LOW_4 ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND ),
.PCIE_CHAN_BOND_EN ( PCIE_CHAN_BOND_EN ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_LPM_DFE ( PCIE_LPM_DFE ),
.PCIE_LINK_SPEED ( PCIE_LINK_SPEED )
) gt_top_i(
//------------------------------------------------------------------------------------//
// Pipe Per-Link Signals //
//------------------------------------------------------------------------------------//
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det ),
.pipe_tx_reset ( pipe_tx_reset ),
.pipe_tx_rate ( pipe_tx_rate ),
.pipe_tx_deemph ( pipe_tx_deemph ),
.pipe_tx_margin ( pipe_tx_margin ),
.pipe_tx_swing ( pipe_tx_swing ),
.pipe_txeq_fs ( pipe_tx_eqfs ),
.pipe_txeq_lf ( pipe_tx_eqlf ),
.pipe_rxslide ( pipe_rx_slide ),
.pipe_rxsync_done ( pipe_rx_syncdone ),
.cfg_ltssm_state ( cfg_ltssm_state_wire ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k ),
.pipe_rx0_data ( pipe_rx0_data ),
.pipe_rx0_valid ( pipe_rx0_valid ),
.pipe_rx0_chanisaligned ( ),
.pipe_rx0_status ( pipe_rx0_status ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle ),
.pipe_rx0_polarity ( pipe_rx0_polarity ),
.pipe_tx0_compliance ( pipe_tx0_compliance ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k ),
.pipe_tx0_data ( pipe_tx0_data ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown ),
.pipe_tx0_eqcontrol ( pipe_tx0_eqcontrol ),
.pipe_tx0_eqpreset ( pipe_tx0_eqpreset ),
.pipe_tx0_eqdeemph ( pipe_tx0_eqdeemph ),
.pipe_tx0_eqdone ( pipe_tx0_eqdone ),
.pipe_tx0_eqcoeff ( pipe_tx0_eqcoeff ),
.pipe_rx0_eqcontrol ( pipe_rx0_eqcontrol ),
.pipe_rx0_eqpreset ( pipe_rx0_eqpreset ),
.pipe_rx0_eq_lffs ( pipe_rx0_eq_lffs ),
.pipe_rx0_eq_txpreset ( pipe_rx0_eq_txpreset ),
.pipe_rx0_eq_new_txcoeff ( pipe_rx0_eq_new_txcoeff ),
.pipe_rx0_eq_lffs_sel ( pipe_rx0_eq_lffs_sel ),
.pipe_rx0_eq_adapt_done ( pipe_rx0_eq_adapt_done ),
.pipe_rx0_eqdone ( pipe_rx0_eqdone ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k ),
.pipe_rx1_data ( pipe_rx1_data ),
.pipe_rx1_valid ( pipe_rx1_valid ),
.pipe_rx1_chanisaligned ( ),
.pipe_rx1_status ( pipe_rx1_status ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle ),
.pipe_rx1_polarity ( pipe_rx1_polarity ),
.pipe_tx1_compliance ( pipe_tx1_compliance ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k ),
.pipe_tx1_data ( pipe_tx1_data ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown ),
.pipe_tx1_eqcontrol ( pipe_tx1_eqcontrol ),
.pipe_tx1_eqpreset ( pipe_tx1_eqpreset ),
.pipe_tx1_eqdeemph ( pipe_tx1_eqdeemph ),
.pipe_tx1_eqdone ( pipe_tx1_eqdone ),
.pipe_tx1_eqcoeff ( pipe_tx1_eqcoeff ),
.pipe_rx1_eqcontrol ( pipe_rx1_eqcontrol ),
.pipe_rx1_eqpreset ( pipe_rx1_eqpreset ),
.pipe_rx1_eq_lffs ( pipe_rx1_eq_lffs ),
.pipe_rx1_eq_txpreset ( pipe_rx1_eq_txpreset ),
.pipe_rx1_eq_new_txcoeff ( pipe_rx1_eq_new_txcoeff ),
.pipe_rx1_eq_lffs_sel ( pipe_rx1_eq_lffs_sel ),
.pipe_rx1_eq_adapt_done ( pipe_rx1_eq_adapt_done ),
.pipe_rx1_eqdone ( pipe_rx1_eqdone ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k ),
.pipe_rx2_data ( pipe_rx2_data ),
.pipe_rx2_valid ( pipe_rx2_valid ),
.pipe_rx2_chanisaligned ( ),
.pipe_rx2_status ( pipe_rx2_status ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle ),
.pipe_rx2_polarity ( pipe_rx2_polarity ),
.pipe_tx2_compliance ( pipe_tx2_compliance ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k ),
.pipe_tx2_data ( pipe_tx2_data ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown ),
.pipe_tx2_eqcontrol ( pipe_tx2_eqcontrol ),
.pipe_tx2_eqpreset ( pipe_tx2_eqpreset ),
.pipe_tx2_eqdeemph ( pipe_tx2_eqdeemph ),
.pipe_tx2_eqdone ( pipe_tx2_eqdone ),
.pipe_tx2_eqcoeff ( pipe_tx2_eqcoeff ),
.pipe_rx2_eqcontrol ( pipe_rx2_eqcontrol ),
.pipe_rx2_eqpreset ( pipe_rx2_eqpreset ),
.pipe_rx2_eq_lffs ( pipe_rx2_eq_lffs ),
.pipe_rx2_eq_txpreset ( pipe_rx2_eq_txpreset ),
.pipe_rx2_eq_new_txcoeff ( pipe_rx2_eq_new_txcoeff ),
.pipe_rx2_eq_lffs_sel ( pipe_rx2_eq_lffs_sel ),
.pipe_rx2_eq_adapt_done ( pipe_rx2_eq_adapt_done ),
.pipe_rx2_eqdone ( pipe_rx2_eqdone ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k ),
.pipe_rx3_data ( pipe_rx3_data ),
.pipe_rx3_valid ( pipe_rx3_valid ),
.pipe_rx3_chanisaligned ( ),
.pipe_rx3_status ( pipe_rx3_status ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle ),
.pipe_rx3_polarity ( pipe_rx3_polarity ),
.pipe_tx3_compliance ( pipe_tx3_compliance ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k ),
.pipe_tx3_data ( pipe_tx3_data ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown ),
.pipe_tx3_eqcontrol ( pipe_tx3_eqcontrol ),
.pipe_tx3_eqpreset ( pipe_tx3_eqpreset ),
.pipe_tx3_eqdeemph ( pipe_tx3_eqdeemph ),
.pipe_tx3_eqdone ( pipe_tx3_eqdone ),
.pipe_tx3_eqcoeff ( pipe_tx3_eqcoeff ),
.pipe_rx3_eqcontrol ( pipe_rx3_eqcontrol ),
.pipe_rx3_eqpreset ( pipe_rx3_eqpreset ),
.pipe_rx3_eq_lffs ( pipe_rx3_eq_lffs ),
.pipe_rx3_eq_txpreset ( pipe_rx3_eq_txpreset ),
.pipe_rx3_eq_new_txcoeff ( pipe_rx3_eq_new_txcoeff ),
.pipe_rx3_eq_lffs_sel ( pipe_rx3_eq_lffs_sel ),
.pipe_rx3_eq_adapt_done ( pipe_rx3_eq_adapt_done ),
.pipe_rx3_eqdone ( pipe_rx3_eqdone ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k ),
.pipe_rx4_data ( pipe_rx4_data ),
.pipe_rx4_valid ( pipe_rx4_valid ),
.pipe_rx4_chanisaligned ( ),
.pipe_rx4_status ( pipe_rx4_status ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle ),
.pipe_rx4_polarity ( pipe_rx4_polarity ),
.pipe_tx4_compliance ( pipe_tx4_compliance ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k ),
.pipe_tx4_data ( pipe_tx4_data ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown ),
.pipe_tx4_eqcontrol ( pipe_tx4_eqcontrol ),
.pipe_tx4_eqpreset ( pipe_tx4_eqpreset ),
.pipe_tx4_eqdeemph ( pipe_tx4_eqdeemph ),
.pipe_tx4_eqdone ( pipe_tx4_eqdone ),
.pipe_tx4_eqcoeff ( pipe_tx4_eqcoeff ),
.pipe_rx4_eqcontrol ( pipe_rx4_eqcontrol ),
.pipe_rx4_eqpreset ( pipe_rx4_eqpreset ),
.pipe_rx4_eq_lffs ( pipe_rx4_eq_lffs ),
.pipe_rx4_eq_txpreset ( pipe_rx4_eq_txpreset ),
.pipe_rx4_eq_new_txcoeff ( pipe_rx4_eq_new_txcoeff ),
.pipe_rx4_eq_lffs_sel ( pipe_rx4_eq_lffs_sel ),
.pipe_rx4_eq_adapt_done ( pipe_rx4_eq_adapt_done ),
.pipe_rx4_eqdone ( pipe_rx4_eqdone ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k ),
.pipe_rx5_data ( pipe_rx5_data ),
.pipe_rx5_valid ( pipe_rx5_valid ),
.pipe_rx5_chanisaligned ( ),
.pipe_rx5_status ( pipe_rx5_status ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle ),
.pipe_rx5_polarity ( pipe_rx5_polarity ),
.pipe_tx5_compliance ( pipe_tx5_compliance ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k ),
.pipe_tx5_data ( pipe_tx5_data ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown ),
.pipe_tx5_eqcontrol ( pipe_tx5_eqcontrol ),
.pipe_tx5_eqpreset ( pipe_tx5_eqpreset ),
.pipe_tx5_eqdeemph ( pipe_tx5_eqdeemph ),
.pipe_tx5_eqdone ( pipe_tx5_eqdone ),
.pipe_tx5_eqcoeff ( pipe_tx5_eqcoeff ),
.pipe_rx5_eqcontrol ( pipe_rx5_eqcontrol ),
.pipe_rx5_eqpreset ( pipe_rx5_eqpreset ),
.pipe_rx5_eq_lffs ( pipe_rx5_eq_lffs ),
.pipe_rx5_eq_txpreset ( pipe_rx5_eq_txpreset ),
.pipe_rx5_eq_new_txcoeff ( pipe_rx5_eq_new_txcoeff ),
.pipe_rx5_eq_lffs_sel ( pipe_rx5_eq_lffs_sel ),
.pipe_rx5_eq_adapt_done ( pipe_rx5_eq_adapt_done ),
.pipe_rx5_eqdone ( pipe_rx5_eqdone ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k ),
.pipe_rx6_data ( pipe_rx6_data ),
.pipe_rx6_valid ( pipe_rx6_valid ),
.pipe_rx6_chanisaligned ( ),
.pipe_rx6_status ( pipe_rx6_status ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle ),
.pipe_rx6_polarity ( pipe_rx6_polarity ),
.pipe_tx6_compliance ( pipe_tx6_compliance ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k ),
.pipe_tx6_data ( pipe_tx6_data ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown ),
.pipe_tx6_eqcontrol ( pipe_tx6_eqcontrol ),
.pipe_tx6_eqpreset ( pipe_tx6_eqpreset ),
.pipe_tx6_eqdeemph ( pipe_tx6_eqdeemph ),
.pipe_tx6_eqdone ( pipe_tx6_eqdone ),
.pipe_tx6_eqcoeff ( pipe_tx6_eqcoeff ),
.pipe_rx6_eqcontrol ( pipe_rx6_eqcontrol ),
.pipe_rx6_eqpreset ( pipe_rx6_eqpreset ),
.pipe_rx6_eq_lffs ( pipe_rx6_eq_lffs ),
.pipe_rx6_eq_txpreset ( pipe_rx6_eq_txpreset ),
.pipe_rx6_eq_new_txcoeff ( pipe_rx6_eq_new_txcoeff ),
.pipe_rx6_eq_lffs_sel ( pipe_rx6_eq_lffs_sel ),
.pipe_rx6_eq_adapt_done ( pipe_rx6_eq_adapt_done ),
.pipe_rx6_eqdone ( pipe_rx6_eqdone ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k ),
.pipe_rx7_data ( pipe_rx7_data ),
.pipe_rx7_valid ( pipe_rx7_valid ),
.pipe_rx7_chanisaligned ( ),
.pipe_rx7_status ( pipe_rx7_status ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle ),
.pipe_rx7_polarity ( pipe_rx7_polarity ),
.pipe_tx7_compliance ( pipe_tx7_compliance ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k ),
.pipe_tx7_data ( pipe_tx7_data ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown ),
.pipe_tx7_eqcontrol ( pipe_tx7_eqcontrol ),
.pipe_tx7_eqpreset ( pipe_tx7_eqpreset ),
.pipe_tx7_eqdeemph ( pipe_tx7_eqdeemph ),
.pipe_tx7_eqdone ( pipe_tx7_eqdone ),
.pipe_tx7_eqcoeff ( pipe_tx7_eqcoeff ),
.pipe_rx7_eqcontrol ( pipe_rx7_eqcontrol ),
.pipe_rx7_eqpreset ( pipe_rx7_eqpreset ),
.pipe_rx7_eq_lffs ( pipe_rx7_eq_lffs ),
.pipe_rx7_eq_txpreset ( pipe_rx7_eq_txpreset ),
.pipe_rx7_eq_new_txcoeff ( pipe_rx7_eq_new_txcoeff ),
.pipe_rx7_eq_lffs_sel ( pipe_rx7_eq_lffs_sel ),
.pipe_rx7_eq_adapt_done ( pipe_rx7_eq_adapt_done ),
.pipe_rx7_eqdone ( pipe_rx7_eqdone ),
// Manual PCIe Equalization Control
.pipe_rxeq_user_en ( pipe_rxeq_user_en[PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ),
.pipe_rxeq_user_txcoeff ( pipe_rxeq_user_txcoeff[18*PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ),
.pipe_rxeq_user_mode ( {PL_LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.drp_rdy ( drp_rdy_wire ),
.drp_do ( drp_do_wire ),
.drp_clk ( dt_654524_drp_clk ),
.drp_en ( dt_654524_drp_en ),
.drp_we ( dt_654524_drp_we ),
.drp_addr ( dt_654524_drp_addr ),
.drp_di ( dt_654524_drp_di ),
// PCI Express signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//---------- PIPE Clock & Reset Ports ------------------
.pipe_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.rec_clk ( rec_clk ),
.pipe_pclk ( pipe_clk ),
.core_clk ( core_clk ),
.user_clk ( user_clk ),
.phy_rdy ( phy_rdy ),
.mmcm_lock ( mmcm_lock ),
.pipe_mmcm_rst_n ( pipe_mmcm_rst_n),
// ---------- Shared Logic Internal------------------
.INT_PCLK_OUT_SLAVE ( int_pclk_out_slave ),
.INT_RXUSRCLK_OUT ( int_pipe_rxusrclk_out ),
.INT_RXOUTCLK_OUT ( int_rxoutclk_out ),
.INT_DCLK_OUT ( int_dclk_out ),
.INT_USERCLK1_OUT ( int_userclk1_out ),
.INT_USERCLK2_OUT ( int_userclk2_out),
.INT_OOBCLK_OUT ( int_oobclk_out),
.INT_QPLLLOCK_OUT ( int_qplllock_out ),
.INT_QPLLOUTCLK_OUT ( int_qplloutclk_out ),
.INT_QPLLOUTREFCLK_OUT ( int_qplloutrefclk_out ),
.INT_PCLK_SEL_SLAVE ( int_pclk_sel_slave ),
// ---------- Shared Logic External------------------
//External GT COMMON Ports
.qpll_drp_crscode ( qpll_drp_crscode ),
.qpll_drp_fsm ( qpll_drp_fsm ),
.qpll_drp_done ( qpll_drp_done ),
.qpll_drp_reset ( qpll_drp_reset ),
.qpll_qplllock ( qpll_qplllock ),
.qpll_qplloutclk ( qpll_qplloutclk ),
.qpll_qplloutrefclk ( qpll_qplloutrefclk ),
.qpll_qplld ( qpll_qplld ),
.qpll_qpllreset ( qpll_qpllreset ),
.qpll_drp_clk ( qpll_drp_clk ),
.qpll_drp_rst_n ( qpll_drp_rst_n ),
.qpll_drp_ovrd ( qpll_drp_ovrd ),
.qpll_drp_gen3 ( qpll_drp_gen3),
.qpll_drp_start ( qpll_drp_start ),
//External Clock Ports
.PIPE_PCLK_IN ( pipe_pclk_in ),
.PIPE_RXUSRCLK_IN ( pipe_rxusrclk_in ),
.PIPE_RXOUTCLK_IN ( pipe_rxoutclk_in ),
.PIPE_DCLK_IN ( pipe_dclk_in ),
.PIPE_USERCLK1_IN ( pipe_userclk1_in ),
.PIPE_USERCLK2_IN ( pipe_userclk2_in ),
.PIPE_OOBCLK_IN ( pipe_oobclk_in ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN_wire ),
.PIPE_TXOUTCLK_OUT ( pipe_txoutclk_out ),
.PIPE_RXOUTCLK_OUT ( pipe_rxoutclk_out ),
.PIPE_PCLK_SEL_OUT ( pipe_pclk_sel_out ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT_wire ),
//----------TRANSCEIVER DEBUG EOU------------------
.ext_ch_gt_drpclk (ext_ch_gt_drpclk),
.ext_ch_gt_drpaddr (ext_ch_gt_drpaddr),
.ext_ch_gt_drpen (ext_ch_gt_drpen),
.ext_ch_gt_drpdi (ext_ch_gt_drpdi),
.ext_ch_gt_drpwe (ext_ch_gt_drpwe),
.ext_ch_gt_drpdo (ext_ch_gt_drpdo),
.ext_ch_gt_drprdy (ext_ch_gt_drprdy),
//---------- PRBS/Loopback Ports -----------------------
.PIPE_TXPRBSSEL ( pipe_txprbssel ),
.PIPE_RXPRBSSEL ( pipe_rxprbssel ),
.PIPE_TXPRBSFORCEERR ( pipe_txprbsforceerr ),
.PIPE_RXPRBSCNTRESET ( pipe_rxprbscntreset ),
.PIPE_LOOPBACK ( pipe_loopback),
.PIPE_RXPRBSERR ( pipe_rxprbserr),
//---------- Transceiver Debug FSM Ports ---------------------------------
.PIPE_RST_FSM (pipe_rst_fsm),
.PIPE_QRST_FSM (pipe_qrst_fsm),
.PIPE_RATE_FSM (pipe_rate_fsm ),
.PIPE_SYNC_FSM_TX (pipe_sync_fsm_tx ),
.PIPE_SYNC_FSM_RX (pipe_sync_fsm_rx ),
.PIPE_DRP_FSM (pipe_drp_fsm ),
.PIPE_RST_IDLE (pipe_rst_idle ),
.PIPE_QRST_IDLE (pipe_qrst_idle ),
.PIPE_RATE_IDLE (pipe_rate_idle ),
.PIPE_EYESCANDATAERROR ( pipe_eyescandataerror ),
.PIPE_RXSTATUS ( pipe_rxstatus ),
.PIPE_DMONITOROUT ( pipe_dmonitorout ),
.PIPE_CPLL_LOCK ( pipe_cpll_lock ),
.PIPE_QPLL_LOCK ( pipe_qpll_lock ),
.PIPE_RXPMARESETDONE ( pipe_rxpmaresetdone ),
.PIPE_RXBUFSTATUS ( pipe_rxbufstatus ),
.PIPE_TXPHALIGNDONE ( pipe_txphaligndone ),
.PIPE_TXPHINITDONE ( pipe_txphinitdone ),
.PIPE_TXDLYSRESETDONE ( pipe_txdlysresetdone ),
.PIPE_RXPHALIGNDONE ( pipe_rxphaligndone ),
.PIPE_RXDLYSRESETDONE ( pipe_rxdlysresetdone ),
.PIPE_RXSYNCDONE ( pipe_rxsyncdone ),
.PIPE_RXDISPERR ( pipe_rxdisperr ),
.PIPE_RXNOTINTABLE ( pipe_rxnotintable ),
.PIPE_RXCOMMADET ( pipe_rxcommadet ),
//---------- JTAG Ports --------------------------------
.PIPE_JTAG_RDY (gt_ch_drp_rdy),
//---------- Debug Ports -------------------------------
.PIPE_DEBUG_0 (pipe_debug_0 ),
.PIPE_DEBUG_1 (pipe_debug_1 ),
.PIPE_DEBUG_2 (pipe_debug_2 ),
.PIPE_DEBUG_3 (pipe_debug_3 ),
.PIPE_DEBUG_4 (pipe_debug_4 ),
.PIPE_DEBUG_5 (pipe_debug_5 ),
.PIPE_DEBUG_6 (pipe_debug_6 ),
.PIPE_DEBUG_7 (pipe_debug_7 ),
.PIPE_DEBUG_8 (pipe_debug_8 ),
.PIPE_DEBUG_9 (pipe_debug_9 ),
.PIPE_DEBUG (pipe_debug)
);
assign pipe_gen3_out = 1'b0;
assign common_commands_out = 17'b0;
assign pipe_tx_0_sigs = 70'b0;
assign pipe_tx_1_sigs = 70'b0;
assign pipe_tx_2_sigs = 70'b0;
assign pipe_tx_3_sigs = 70'b0;
assign pipe_tx_4_sigs = 70'b0;
assign pipe_tx_5_sigs = 70'b0;
assign pipe_tx_6_sigs = 70'b0;
assign pipe_tx_7_sigs = 70'b0;
// Assign as passthrough if not tandem configuration
// Input assigned passthroughs
assign icap_o = 32'h0000_0000;
assign cfg_mgmt_write_wire = cfg_mgmt_write;
assign cfg_mgmt_read_wire = cfg_mgmt_read;
assign cfg_per_func_status_control_wire = cfg_per_func_status_control;
assign cfg_per_function_output_request_wire = cfg_per_function_output_request;
assign cfg_dsn_wire = cfg_dsn;
assign cfg_power_state_change_ack_wire = cfg_power_state_change_ack;
assign cfg_err_cor_in_wire = cfg_err_cor_in;
assign cfg_err_uncor_in_wire = cfg_err_uncor_in;
assign cfg_flr_done_wire = cfg_flr_done;
assign cfg_vf_flr_done_wire = cfg_vf_flr_done;
assign cfg_link_training_enable_wire = cfg_link_training_enable;
assign cfg_ext_read_data_valid_wire = cfg_ext_read_data_valid;
assign cfg_interrupt_pending_wire = cfg_interrupt_pending;
assign cfg_interrupt_msi_select_wire = cfg_interrupt_msi_select;
assign cfg_interrupt_msi_pending_status_wire = cfg_interrupt_msi_pending_status;
assign cfg_config_space_enable_wire = cfg_config_space_enable;
assign cfg_req_pm_transition_l23_ready_wire = cfg_req_pm_transition_l23_ready;
assign cfg_hot_reset_in_wire = cfg_hot_reset_in;
assign cfg_ds_port_number_wire = cfg_ds_port_number;
assign cfg_ds_bus_number_wire = cfg_ds_bus_number;
assign cfg_ds_device_number_wire = cfg_ds_device_number;
assign cfg_ds_function_number_wire = cfg_ds_function_number;
assign user_tph_stt_address_wire = user_tph_stt_address;
assign user_tph_function_num_wire = user_tph_function_num;
assign user_tph_stt_read_enable_wire = user_tph_stt_read_enable;
// Output assigned passthroughs
assign cfg_phy_link_down = cfg_phy_link_down_wire;
assign cfg_phy_link_status = cfg_phy_link_status_wire;
assign cfg_ltssm_state = cfg_ltssm_state_wire;
assign cfg_hot_reset_out = cfg_hot_reset_out_wire;
assign pcie_drp_rdy = drp_rdy_wire;
assign pcie_drp_do = drp_do_wire;
// Input assigned passthroughs
assign drp_clk_wire = pcie_drp_clk;
assign drp_en_wire = pcie_drp_en;
assign drp_we_wire = pcie_drp_we;
assign drp_addr_wire = pcie_drp_addr;
assign drp_di_wire = pcie_drp_di;
// Passthrough for tandem_cplr outputs
assign s_axis_cc_tdata_wire = s_axis_cc_tdata;
assign s_axis_cc_tkeep_wire = s_axis_cc_tkeep;
assign s_axis_cc_tlast_wire = s_axis_cc_tlast;
assign s_axis_cc_tvalid_wire = s_axis_cc_tvalid;
assign s_axis_cc_tuser_wire = s_axis_cc_tuser;
assign s_axis_cc_tready = s_axis_cc_tready_wire;
assign m_axis_cq_tdata = m_axis_cq_tdata_wire;
assign m_axis_cq_tlast = m_axis_cq_tlast_wire;
assign m_axis_cq_tvalid = m_axis_cq_tvalid_wire;
assign m_axis_cq_tuser = m_axis_cq_tuser_wire;
assign m_axis_cq_tkeep = m_axis_cq_tkeep_wire;
assign m_axis_cq_tready_wire = m_axis_cq_tready;
assign s_axis_rq_tdata_wire = s_axis_rq_tdata;
assign s_axis_rq_tkeep_wire = s_axis_rq_tkeep;
assign s_axis_rq_tlast_wire = s_axis_rq_tlast;
assign s_axis_rq_tvalid_wire = s_axis_rq_tvalid;
assign s_axis_rq_tuser_wire = s_axis_rq_tuser;
assign s_axis_rq_tready = s_axis_rq_tready_wire;
assign m_axis_rc_tdata = m_axis_rc_tdata_wire;
assign m_axis_rc_tlast = m_axis_rc_tlast_wire;
assign m_axis_rc_tvalid = m_axis_rc_tvalid_wire;
assign m_axis_rc_tuser = m_axis_rc_tuser_wire;
assign m_axis_rc_tkeep = m_axis_rc_tkeep_wire;
assign m_axis_rc_tready_wire = m_axis_rc_tready;
assign cfg_msg_transmit_done = cfg_msg_transmit_done_wire;
assign cfg_msg_transmit_wire = cfg_msg_transmit;
assign cfg_msg_transmit_type_wire = cfg_msg_transmit_type;
assign cfg_msg_transmit_data_wire = cfg_msg_transmit_data;
assign pcie_rq_tag = pcie_rq_tag_wire;
assign pcie_rq_tag_vld = pcie_rq_tag_vld_wire;
assign pcie_tfc_nph_av = pcie_tfc_nph_av_wire;
assign pcie_tfc_npd_av = pcie_tfc_npd_av_wire;
assign pcie_rq_seq_num = pcie_rq_seq_num_wire;
assign pcie_rq_seq_num_vld = pcie_rq_seq_num_vld_wire;
assign cfg_fc_ph = cfg_fc_ph_wire;
assign cfg_fc_nph = cfg_fc_nph_wire;
assign cfg_fc_cplh = cfg_fc_cplh_wire;
assign cfg_fc_pd = cfg_fc_pd_wire;
assign cfg_fc_npd = cfg_fc_npd_wire;
assign cfg_fc_cpld = cfg_fc_cpld_wire;
assign cfg_fc_sel_wire = cfg_fc_sel;
assign pcie_cq_np_req_count = pcie_cq_np_req_count_wire;
assign pcie_cq_np_req_wire = pcie_cq_np_req;
assign cfg_msg_received = cfg_msg_received_wire;
assign cfg_msg_received_type = cfg_msg_received_type_wire;
assign cfg_msg_received_data = cfg_msg_received_data_wire;
assign cfg_interrupt_int_wire = cfg_interrupt_int;
assign cfg_interrupt_msi_int_wire = cfg_interrupt_msi_int;
assign cfg_interrupt_msix_int_wire = cfg_interrupt_msix_int;
assign user_app_rdy = 1'b1;
assign startup_cfgclk = 1'b0;
assign startup_cfgmclk = 1'b0;
assign startup_eos = 1'b0;
assign startup_preq = 1'b0;
// Generate user_lnk_up
assign user_lnk_up = user_lnk_up_int;
//----------------------------------------------------------------------------------------------------------------//
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:22:18 05/13/2015
// Design Name:
// Module Name: MemoryManagerUnit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MemoryManagerUnit(
input clk, //very slow clock
input clk_50M,
input[14:0] MemAddr,
input MemWrite,
input MemRead,
input SaveHalf,
input LoadHalf,
input[31:0] MemWriteData,
input ChipSelect,
output[31:0] MemReadData,
output reg MemOK,
output hsync, //ÐÐͬ²½ÐźÅ
output vsync, //³¡Í¬²½ÐźÅ
output vga_r,
output vga_g,
output vga_b
);
/*
reg clk;
reg clk_50M;
initial begin
clk = 0;
clk_50M = 0;
end
always#10 begin
clk_50M = ~clk_50M;
end
always#10 begin
clk = ~clk;
end
*/
parameter width = 40;
parameter height = 25;
parameter screenBase = 14'h3000;
initial begin
MemOK <= 0;
end
always @(posedge clk) begin
MemOK <= (MemRead | MemWrite) & ChipSelect;
end
wire[14:0] ZBadr;
wire[15:0] outB;
Memory Mem (
.clk(clk_50M),
.adrA(MemAddr),
.adrB(ZBadr),
.we(MemWrite&ChipSelect),
.data(MemWriteData),
.sh(SaveHalf),
.lh(LoadHalf),
.outA(MemReadData),
.outB(outB)
);
reg[15:0] ZBcode;
wire [9:0] xpos,ypos;
wire valid;
vga_dis vga (
.clk(clk_50M), //input
.rst_n(1'b1),
.ZBcode(ZBcode),
.valid(valid), //output
.xpos(xpos[9:0]),
.ypos(ypos[9:0]),
.hsync(hsync),
.vsync(vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
wire[14:0] offset;
assign ZBadr = screenBase+offset;
wire[14:0] lineBase;
assign lineBase = ypos[9:4]*width;
assign offset =(xpos[9:4]== width-1)?(
(ypos[3:0]==4'hf)?(
(ypos[9:4]==height-1)? 10'd0 : (lineBase + xpos[9:4] +1)
) : lineBase
) : (lineBase + xpos[9:4] + 1);
always @(posedge clk_50M) begin
if(xpos[3:0] == 4'he && valid) begin
ZBcode <= outB;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
`define SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
|
`timescale 1ns / 1ps
module regfile_16x32b_4rd_2wr_tb;
// Inputs
reg clk;
reg rst;
reg [3:0] rdport1_ctrl_add;
reg [3:0] rdport2_ctrl_add;
reg [3:0] rdport3_ctrl_add;
reg [3:0] rdport4_ctrl_add;
reg [3:0] wrport1_ctrl_add;
reg [31:0] wrport1_data_in;
reg wrport1_wren;
reg [3:0] wrport2_ctrl_add;
reg [31:0] wrport2_data_in;
reg wrport2_wren;
// Outputs
wire [31:0] rdport1_data_out;
wire [31:0] rdport2_data_out;
wire [31:0] rdport3_data_out;
wire [31:0] rdport4_data_out;
// Variables
integer i = 0;
// Instantiate the Unit Under Test (UUT)
regfile_16x32b_4rd_2wr uut (
.clk(clk),
.rst(rst),
.rdport1_ctrl_add(rdport1_ctrl_add),
.rdport1_data_out(rdport1_data_out),
.rdport2_ctrl_add(rdport2_ctrl_add),
.rdport2_data_out(rdport2_data_out),
.rdport3_ctrl_add(rdport3_ctrl_add),
.rdport3_data_out(rdport3_data_out),
.rdport4_ctrl_add(rdport4_ctrl_add),
.rdport4_data_out(rdport4_data_out),
.wrport1_ctrl_add(wrport1_ctrl_add),
.wrport1_data_in(wrport1_data_in),
.wrport1_wren(wrport1_wren),
.wrport2_ctrl_add(wrport2_ctrl_add),
.wrport2_data_in(wrport2_data_in),
.wrport2_wren(wrport2_wren)
);
task expectRead;
input [31:0] exp_out0;
input [31:0] exp_out1;
input [31:0] exp_out2;
input [31:0] exp_out3;
if ((rdport1_data_out !== exp_out0) || (rdport2_data_out !== exp_out1) || (rdport3_data_out !== exp_out2) || (rdport4_data_out !== exp_out3)) begin
$display("TEST FAILED");
$display("At time %0d rdport1_ctrl_add=%0d, rdport1_data_out=%0d, rdport2_ctrl_add=%0d, rdport2_data_out=%0d, rdport3_ctrl_add=%0d, rdport3_data_out=%0d, rdport4_ctrl_add=%0d, rdport4_data_out=%0d ",
$time,
rdport1_ctrl_add, rdport1_data_out,
rdport2_ctrl_add, rdport2_data_out,
rdport3_ctrl_add, rdport3_data_out,
rdport4_ctrl_add, rdport4_data_out);
$display("rdport1_data_out, rdport2_data_out, rdport3_data_out, rdport4_data_out should be %0d, %0d, %0d, %0d",
exp_out0, exp_out1, exp_out2, exp_out3 );
$finish;
end
else begin
$display("At time %0d rdport1_ctrl_add=%0d, rdport1_data_out=%0d, rdport2_ctrl_add=%0d, rdport2_data_out=%0d, rdport3_ctrl_add=%0d, rdport3_data_out=%0d, rdport4_ctrl_add=%0d, rdport4_data_out=%0d ",
$time,
rdport1_ctrl_add, rdport1_data_out,
rdport2_ctrl_add, rdport2_data_out,
rdport3_ctrl_add, rdport3_data_out,
rdport4_ctrl_add, rdport4_data_out);
end
endtask
// Clock and sync reset stimulus
initial begin
clk = 1'b0;
rst = 1'b1;
// hold sync reset for next 2 cc
repeat(4) #10 clk = ~clk;
// deassert reset
rst = 1'b0;
// clock forever
forever #10 clk = ~clk;
end
// Stimulus
initial begin
// Initialize Inputs
rdport1_ctrl_add = 0;
rdport2_ctrl_add = 0;
rdport3_ctrl_add = 0;
rdport4_ctrl_add = 0;
wrport1_ctrl_add = 0;
wrport1_data_in = 0;
wrport1_wren = 0;
wrport2_ctrl_add = 0;
wrport2_data_in = 0;
wrport2_wren = 0;
// wait for reset to deassert
@(negedge rst);
// write to first 8 registers using port 1 and last 8 registers using port 2
// write values 16x1, 16x2, 16x3..16x8 by wr port 1 to the first 8 registers
// write values 16x9, 16x10, 16x11..16x16 by wr port 2 to the next 8 registers
for( i = 0; i < 8 ; i = i+1)
begin
wrport1_ctrl_add = i;
wrport1_data_in = (i+1)*16;
wrport2_ctrl_add = i + 8;
wrport2_data_in = (i+9)*16;
wrport1_wren = 1;
wrport2_wren = 1;
// wait for negative clock edge
@(negedge clk);
end
// Deassert write enables
wrport1_wren = 0;
wrport2_wren = 0;
// Read back all 16 registers using 4 read ports
// with per port reading 4 registers
// RDP1(R0-R3), RDP2(R4-R7), RDP3(R8-R11), RDP4(R12-R15)
for( i = 0; i < 4 ; i = i+1)
begin
rdport1_ctrl_add = i;
rdport2_ctrl_add = i+4;
rdport3_ctrl_add = i+8;
rdport4_ctrl_add = i+12;
// wait for negative clock edge
@(negedge clk);
expectRead( 16*(i+1), 16*(i+5), 16*(i+9), 16*(i+13));
end
// Test write collision: write to same register
// simulataneously from two write ports with different values.
// only write by first write port should go through while
// the write by second port should be ignored
wrport1_ctrl_add = 10;
wrport1_data_in = 100;
wrport2_ctrl_add =10;
wrport2_data_in = 1000;
wrport1_wren = 1;
wrport2_wren = 1;
// wait for negative clock edge
@(negedge clk);
wrport1_wren = 0;
wrport2_wren = 0;
// read same register using all 4 read ports
// to check which of the two collision writes
// went through. this also verifies if we can
// simulataneously read from same register using
// all 4 ports
rdport1_ctrl_add = 10;
rdport2_ctrl_add = 10;
rdport3_ctrl_add = 10;
rdport4_ctrl_add = 10;
@(negedge clk);
expectRead( 100, 100, 100, 100);
$display("TEST PASSED");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_PP_V |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 45,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 161,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "45"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.866669"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "161"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.90900000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "45"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "161"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//on screen display controller
module userio_osd
(
input clk, // 28MHz clock
input clk7_en,
input clk7n_en,
input reset, //reset
input c1, //clk28m domain clock enable
input c3,
input sol, //start of video line
input sof, //start of video frame
input varbeamen,
input [7:0] osd_ctrl, //keycode for OSD control (Amiga keyboard codes + additional keys coded as values > 80h)
input _scs, //SPI enable
input sdi, //SPI data in
output sdo, //SPI data out
input sck, //SPI clock
output osd_blank, //osd overlay, normal video blank output
output osd_pixel, //osd video pixel
output reg osd_enable = 0, //osd enable
output reg key_disable = 0, // keyboard disable
output reg [1:0] lr_filter = 0,
output reg [1:0] hr_filter = 0,
output reg [6:0] memory_config = 7'b0_00_01_01,
output reg [4:0] chipset_config = 0,
output reg [3:0] floppy_config = 0,
output reg [1:0] scanline = 0,
output reg [1:0] dither = 0,
output reg [2:0] ide_config = 0, //enable hard disk support
output reg [3:0] cpu_config = 0,
output reg [1:0] autofire_config = 0,
output reg cd32pad = 0,
output reg usrrst=1'b0,
output reg cpurst=1'b1,
output reg cpuhlt=1'b1,
output wire fifo_full,
// host
output reg host_cs,
output wire [ 24-1:0] host_adr,
output reg host_we,
output reg [ 2-1:0] host_bs,
output wire [ 16-1:0] host_wdat,
input wire [ 16-1:0] host_rdat,
input wire host_ack
);
//local signals
reg [10:0] horbeam; //horizontal beamcounter
reg [8:0] verbeam; //vertical beamcounter
reg [7:0] osdbuf [0:2048-1]; //osd video buffer
wire osdframe; //true if beamcounters within osd frame
reg [7:0] bufout; //osd buffer read data
reg [10:0] wraddr; //osd buffer write address
wire [7:0] wrdat; //osd buffer write data
wire wren; //osd buffer write enable
reg [3:0] highlight; //highlighted line number
reg invert; //invertion of highlighted line
reg [5:0] vpos;
reg vena;
reg [6:0] t_memory_config = 7'b0_00_01_01;
reg [2:0] t_ide_config = 0;
reg [3:0] t_cpu_config = 0;
reg [4:0] t_chipset_config = 0;
//--------------------------------------------------------------------------------------
// memory configuration select signal
//--------------------------------------------------------------------------------------
// configuration changes only while reset is active
always @(posedge clk)
if (clk7_en) begin
if (reset)
begin
chipset_config <= t_chipset_config;
ide_config <= t_ide_config;
cpu_config[1:0] <= t_cpu_config[1:0];
memory_config[5:0] <= t_memory_config[5:0];
end
end
always @(posedge clk) begin
if (clk7_en) begin
cpu_config[3:2] <= t_cpu_config[3:2];
memory_config[6] <= #1 t_memory_config[6];
end
end
//--------------------------------------------------------------------------------------
//OSD video generator
//--------------------------------------------------------------------------------------
//osd local horizontal beamcounter
always @(posedge clk)
if (sol && !c1 && !c3)
horbeam <= 11'd0;
else
horbeam <= horbeam + 11'd1;
//osd local vertical beamcounter
always @(posedge clk)
if (clk7_en) begin
if (sof)
verbeam <= 9'd0;
else if (sol)
verbeam <= verbeam + 9'd1;
end
always @(posedge clk)
if (clk7_en) begin
if (sol)
vpos[5:0] <= verbeam[5:0];
end
//--------------------------------------------------------------------------------------
//generate osd video frame
//horizontal part..
wire hframe_normal;
wire hframe_varbeam;
wire hframe;
assign hframe_normal = (horbeam[7] & horbeam[8] & horbeam[9] & ~horbeam[10]) | (~horbeam[8] & ~horbeam[9] & horbeam[10]) | (~horbeam[7] & horbeam[8] & ~horbeam[9] & horbeam[10]);
assign hframe_varbeam = ~horbeam[10] & ~horbeam[9];
//assign hframe = varbeamen ? hframe_varbeam : hframe_normal;
assign hframe = hframe_normal;
//vertical part..
reg vframe;
always @(posedge clk)
if (clk7_en) begin
if (!verbeam[8] && verbeam[7] && !verbeam[6])
vframe <= 1;
else if (verbeam[0])
vframe <= 0;
end
always @(posedge clk)
if (clk7_en) begin
if (sol)
vena <= vframe;
end
// combine..
reg osd_enabled;
always @(posedge clk)
if (clk7_en) begin
if (sof)
osd_enabled <= osd_enable;
end
assign osdframe = vframe & hframe & osd_enabled;
always @(posedge clk)
if (clk7_en) begin
if (~highlight[3] && verbeam[5:3]==highlight[2:0] && !verbeam[6])
invert <= 1;
else if (verbeam[0])
invert <= 0;
end
//--------------------------------------------------------------------------------------
//assign osd blank and pixel outputs
assign osd_pixel = invert ^ (vena & bufout[vpos[2:0]]);
assign osd_blank = osdframe;
//--------------------------------------------------------------------------------------
//video buffer
//--------------------------------------------------------------------------------------
//dual ported osd video buffer
//video buffer is 1024*8
//this buffer should be a single blockram
always @(posedge clk) begin//input part
if (clk7_en) begin
if (wren)
osdbuf[wraddr[10:0]] <= wrdat[7:0];
end
end
always @(posedge clk)//output part
bufout[7:0] <= osdbuf[{vpos[5:3],horbeam[8]^horbeam[7],~horbeam[7],horbeam[6:1]}];
//--------------------------------------------------------------------------------------
//interface to host
//--------------------------------------------------------------------------------------
wire rx;
wire cmd;
reg wrcmd; // spi write command
wire vld;
reg vld_d;
wire spi_invalidate;
wire [7:0] rddat;
//instantiate spi interface
userio_osd_spi spi0
(
.clk(clk),
.clk7_en(clk7_en),
.clk7n_en(clk7n_en),
._scs(_scs),
.sdi(sdi),
.sdo(sdo),
.sck(sck),
.in(rddat),
.out(wrdat),
.rx(rx),
.cmd(cmd),
.vld(vld)
);
always @ (posedge clk) begin
if (clk7_en) begin
vld_d <= #1 vld;
end
end
assign spi_invalidate = ~vld && vld_d;
// !!! OLD !!! OSD SPI commands:
// 8'b00000000 NOP
// 8'b001H0NNN write data to osd buffer line <NNN> (H - highlight)
// 8'b0100--KE enable OSD display (E) and disable Amiga keyboard (K)
// 8'b1000000B reset Minimig (B - reset to bootloader)
// 8'b100001AA set autofire rate
// 8'b1001---S set cpu speed
// 8'b1010--SS set scanline mode
// 8'b1011-SMC set hard disk config (C - enable HDC, M - enable Master HDD, S - enable Slave HDD)
// 8'b1100FF-S set floppy speed and drive number
// 8'b1101-EAN set chipset features (N - ntsc, A - OCS A1000, E - ECS)
// 8'b1110HHLL set interpolation filter (H - Hires, L - Lores)
// 8'b111100CC set memory configuration (S - Slow, C - Chip, F - Fast)
// 8'b111101SS set memory configuration (S - Slow, C - Chip, F - Fast)
// 8'b111110FF set memory configuration (S - Slow, C - Chip, F - Fast)
// 8'b111111TT set cpu type TT=00-68000, 01-68010, 11-68020
// OSD SPI commands
//
// 8'b0_000_0000 NOP
// write regs
// 8'b0_000_1000 | XXXXXRBC || reset control | R - reset, B - reset to bootloader, C - reset control block
// 8'b0_001_1000 | XXXXXXXX || clock control | unused
// 8'b0_010_1000 | XXXXXXKE || osd control | K - disable Amiga keyboard, E - enable OSD
// 8'b0_000_0100 | XXXXEANT || chipset config | E - ECS, A - OCS A1000, N - NTSC, T - turbo
// 8'b0_001_0100 | XXXXXSTT || cpu config | S - CPU speed, TT - CPU type (00=68k, 01=68k10, 10=68k20)
// 8'b0_010_0100 | XXFFSSCC || memory config | FF - fast, CC - chip, SS - slow
// 8'b0_011_0100 | XXHHLLSS || video config | HH - hires interp. filter, LL - lowres interp. filter, SS - scanline mode
// 8'b0_100_0100 | XXXXXFFS || floppy config | FF - drive number, S - floppy speed
// 8'b0_101_0100 | XXXXXSMC || harddisk config | S - enable slave HDD, M - enable master HDD, C - enable HDD controler
// 8'b0_110_0100 | XXXXXXAA || joystick config | AA - autofire rate
// 8'b0_000_1100 | XXXXXAAA_AAAAAAAA B,B,... || write OSD buffer, AAAAAAAAAAA - 11bit OSD buffer address, B - variable number of bytes
// 8'b0_001_1100 | A_A_A_A B,B,... || write system memory, A - 32 bit memory address, B - variable number of bytes
// 8'b1_000_1000 read RTL version
// commands
localparam [5:0]
SPI_RESET_CTRL_ADR = 6'b0_000_10,
SPI_CLOCK_CTRL_ADR = 6'b0_001_10,
SPI_OSD_CTRL_ADR = 6'b0_010_10,
SPI_CHIP_CFG_ADR = 6'b0_000_01,
SPI_CPU_CFG_ADR = 6'b0_001_01,
SPI_MEMORY_CFG_ADR = 6'b0_010_01,
SPI_VIDEO_CFG_ADR = 6'b0_011_01,
SPI_FLOPPY_CFG_ADR = 6'b0_100_01,
SPI_HARDDISK_CFG_ADR = 6'b0_101_01,
SPI_JOYSTICK_CFG_ADR = 6'b0_110_01,
SPI_OSD_BUFFER_ADR = 6'b0_000_11,
SPI_MEM_WRITE_ADR = 6'b0_001_11,
SPI_VERSION_ADR = 6'b1_000_10,
SPI_MEM_READ_ADR = 6'b1_001_11;
// get command
reg [5:0] cmd_dat = 6'h00;
always @ (posedge clk) begin
if (clk7_en) begin
if (rx && cmd) cmd_dat <= #1 wrdat[7:2];
//else if (spi_invalidate) cmd_dat <= #1 8'h00; // TODO!
end
end
// data byte counter
reg [2:0] dat_cnt = 3'h0;
always @ (posedge clk) begin
if (clk7_en) begin
if (rx && cmd)
dat_cnt <= #1 3'h0;
else if (rx && (dat_cnt != 4))
dat_cnt <= #1 dat_cnt + 3'h1;
end
end
// reg selects
reg spi_reset_ctrl_sel = 1'b0;
reg spi_clock_ctrl_sel = 1'b0;
reg spi_osd_ctrl_sel = 1'b0;
reg spi_chip_cfg_sel = 1'b0;
reg spi_cpu_cfg_sel = 1'b0;
reg spi_memory_cfg_sel = 1'b0;
reg spi_video_cfg_sel = 1'b0;
reg spi_floppy_cfg_sel = 1'b0;
reg spi_harddisk_cfg_sel = 1'b0;
reg spi_joystick_cfg_sel = 1'b0;
reg spi_osd_buffer_sel = 1'b0;
reg spi_mem_write_sel = 1'b0;
reg spi_version_sel = 1'b0;
reg spi_mem_read_sel = 1'b0;
always @ (*) begin
spi_reset_ctrl_sel = 1'b0;
spi_clock_ctrl_sel = 1'b0;
spi_osd_ctrl_sel = 1'b0;
spi_chip_cfg_sel = 1'b0;
spi_cpu_cfg_sel = 1'b0;
spi_memory_cfg_sel = 1'b0;
spi_video_cfg_sel = 1'b0;
spi_floppy_cfg_sel = 1'b0;
spi_harddisk_cfg_sel = 1'b0;
spi_joystick_cfg_sel = 1'b0;
spi_osd_buffer_sel = 1'b0;
spi_mem_write_sel = 1'b0;
spi_version_sel = 1'b0;
spi_mem_read_sel = 1'b0;
case (cmd_dat)
SPI_RESET_CTRL_ADR : spi_reset_ctrl_sel = 1'b1;
SPI_CLOCK_CTRL_ADR : spi_clock_ctrl_sel = 1'b1;
SPI_OSD_CTRL_ADR : spi_osd_ctrl_sel = 1'b1;
SPI_CHIP_CFG_ADR : spi_chip_cfg_sel = 1'b1;
SPI_CPU_CFG_ADR : spi_cpu_cfg_sel = 1'b1;
SPI_MEMORY_CFG_ADR : spi_memory_cfg_sel = 1'b1;
SPI_VIDEO_CFG_ADR : spi_video_cfg_sel = 1'b1;
SPI_FLOPPY_CFG_ADR : spi_floppy_cfg_sel = 1'b1;
SPI_HARDDISK_CFG_ADR : spi_harddisk_cfg_sel = 1'b1;
SPI_JOYSTICK_CFG_ADR : spi_joystick_cfg_sel = 1'b1;
SPI_OSD_BUFFER_ADR : spi_osd_buffer_sel = 1'b1;
SPI_MEM_WRITE_ADR : spi_mem_write_sel = 1'b1;
SPI_VERSION_ADR : spi_version_sel = 1'b1;
SPI_MEM_READ_ADR : spi_mem_read_sel = 1'b1;
default: begin
spi_reset_ctrl_sel = 1'b0;
spi_clock_ctrl_sel = 1'b0;
spi_osd_ctrl_sel = 1'b0;
spi_chip_cfg_sel = 1'b0;
spi_cpu_cfg_sel = 1'b0;
spi_memory_cfg_sel = 1'b0;
spi_video_cfg_sel = 1'b0;
spi_floppy_cfg_sel = 1'b0;
spi_harddisk_cfg_sel = 1'b0;
spi_joystick_cfg_sel = 1'b0;
spi_osd_buffer_sel = 1'b0;
spi_mem_write_sel = 1'b0;
spi_version_sel = 1'b0;
spi_mem_read_sel = 1'b0;
end
endcase
end
// 8'b0_000_1000 | XXXXHRBC || reset control | H - CPU halt, R - reset, B - reset to bootloader, C - reset control block
// 8'b0_001_1000 | XXXXXXXX || clock control | unused
// 8'b0_010_1000 | XXXXXXKE || osd control | K - disable Amiga keyboard, E - enable OSD
// 8'b0_000_0100 | XXXGEANT || chipset config | G - AGA, E - ECS, A - OCS A1000, N - NTSC, T - turbo
// 8'b0_001_0100 | XXXXKCTT || cpu config | K - fast kickstart enable, C - CPU cache enable, TT - CPU type (00=68k, 01=68k10, 10=68k20)
// 8'b0_010_0100 | XHFFSSCC || memory config | H - HRTmon, FF - fast, SS - slow, CC - chip
// 8'b0_011_0100 | DDHHLLSS || video config | DD - dither, HH - hires interp. filter, LL - lowres interp. filter, SS - scanline mode
// 8'b0_100_0100 | XXXXXFFS || floppy config | FF - drive number, S - floppy speed
// 8'b0_101_0100 | XXXXXSMC || harddisk config | S - enable slave HDD, M - enable master HDD, C - enable HDD controler
// 8'b0_110_0100 | XXXXXCAA || joystick config | C - CD32pad mode, AA - autofire rate
// 8'b0_000_1100 | XXXXXAAA_AAAAAAAA B,B,... || write OSD buffer, AAAAAAAAAAA - 11bit OSD buffer address, B - variable number of bytes
// 8'b0_001_1100 | A_A_A_A B,B,... || write system memory, A - 32 bit memory address, B - variable number of bytes
// 8'b1_000_1000 read RTL version
// write regs
always @ (posedge clk) begin
if (clk7_en) begin
if (rx && !cmd) begin
if (spi_reset_ctrl_sel) begin if (dat_cnt == 0) {cpuhlt, cpurst, usrrst} <= #1 wrdat[2:0]; end
// if (spi_clock_ctrl_sel) begin if (dat_cnt == 0) end
if (spi_osd_ctrl_sel) begin if (dat_cnt == 0) {key_disable, osd_enable} <= #1 wrdat[1:0]; end
if (spi_chip_cfg_sel) begin if (dat_cnt == 0) t_chipset_config <= #1 wrdat[4:0]; end
if (spi_cpu_cfg_sel) begin if (dat_cnt == 0) t_cpu_config <= #1 wrdat[3:0]; end
if (spi_memory_cfg_sel) begin if (dat_cnt == 0) t_memory_config <= #1 wrdat[6:0]; end
if (spi_video_cfg_sel) begin if (dat_cnt == 0) {dither, hr_filter, lr_filter, scanline} <= #1 wrdat[7:0]; end
if (spi_floppy_cfg_sel) begin if (dat_cnt == 0) floppy_config <= #1 wrdat[3:0]; end
if (spi_harddisk_cfg_sel) begin if (dat_cnt == 0) t_ide_config <= #1 wrdat[2:0]; end
//if (spi_joystick_cfg_sel) begin if (dat_cnt == 0) {cd32pad, autofire_config} <= #1 wrdat[2:0]; end
if (spi_joystick_cfg_sel) begin if (dat_cnt == 0) {autofire_config} <= #1 wrdat[1:0]; end
// if (spi_osd_buffer_sel) begin if (dat_cnt == 3) highlight <= #1 wrdat[3:0]; end
// if (spi_mem_write_sel) begin if (dat_cnt == 0) end
// if (spi_version_sel) begin if (dat_cnt == 0) end
// if (spi_mem_read_sel) begin if (dat_cnt == 0) end
end
end
end
//// resets - temporary TODO!
//assign usrrst = rx && !cmd && spi_reset_ctrl_sel && (dat_cnt == 0);
//assign bootrst = rx && !cmd && spi_reset_ctrl_sel && wrdat[0] && (dat_cnt == 0);
// OSD buffer write
reg wr_en_r = 1'b0;
always @ (posedge clk) begin
if (clk7_en) begin
if (rx && (dat_cnt == 3) && spi_osd_buffer_sel)
wr_en_r <= #1 1'b1;
else if (rx && cmd)
wr_en_r <= #1 1'b0;
end
end
assign wren = wr_en_r && rx && !cmd;
// address counter and buffer write control (write line <NNN> command)
always @ (posedge clk) begin
if (clk7_en) begin
if (rx && !cmd && (spi_osd_buffer_sel || spi_mem_read_sel) && (dat_cnt == 3))
wraddr[10:0] <= {wrdat[2:0],8'b0000_0000};
else if (rx) //increment for every data byte that comes in
wraddr[10:0] <= wraddr[10:0] + 11'd1;
end
end
// highlight - TODO remove!
always @ (posedge clk) begin
if (clk7_en) begin
if (~osd_enable)
highlight <= #1 4'b1000;
else if (rx && !cmd && spi_osd_buffer_sel && (dat_cnt == 3) && wrdat[4])
highlight <= #1 wrdat[3:0];
end
end
// memory write
reg mem_toggle = 1'b0, mem_toggle_d = 1'b0;
always @ (posedge clk) begin
if (clk7_en) begin
if (cmd) begin
mem_toggle <= #1 1'b0;
mem_toggle_d <= #1 1'b0;
end else if (rx && !cmd && spi_mem_write_sel && (dat_cnt == 4)) begin
mem_toggle <= #1 ~mem_toggle;
mem_toggle_d <= #1 mem_toggle;
end
end
end
reg [ 8-1:0] mem_dat_r;
always @ (posedge clk) begin
if (clk7_en) begin
if (rx && !cmd && spi_mem_write_sel && !mem_toggle) mem_dat_r <= #1 wrdat[7:0];
end
end
wire wr_fifo_empty;
wire wr_fifo_full;
assign fifo_full = wr_fifo_full;
reg wr_fifo_rd_en;
sync_fifo #(
.FD (4),
.DW (16)
) wr_fifo (
.clk (clk),
.clk7_en (clk7_en),
.rst (reset/* || cmd*/), // TODO possible problem (cmd)!
.fifo_in ({mem_dat_r, wrdat}),
.fifo_out (host_wdat),
.fifo_wr_en (rx && !cmd && mem_toggle),
.fifo_rd_en (wr_fifo_rd_en),
.fifo_full (wr_fifo_full),
.fifo_empty (wr_fifo_empty)
);
reg [2-1:0] wr_state = 2'b00;
localparam ST_WR_IDLE = 2'b00;
localparam ST_WR_WRITE = 2'b10;
localparam ST_WR_WAIT = 2'b11;
always @ (posedge clk) begin
if (clk7_en) begin
if (reset || cmd)
wr_state <= #1 ST_WR_IDLE;
else begin
case (wr_state)
ST_WR_IDLE: begin
wr_fifo_rd_en <= #1 1'b0;
host_cs <= #1 1'b0;
host_we <= #1 1'b0;
host_bs <= #1 2'b00;
wr_fifo_rd_en <= #1 1'b0;
if (!wr_fifo_empty && !wr_fifo_rd_en) wr_state <= #1 ST_WR_WRITE;
end
ST_WR_WRITE: begin
host_cs <= #1 1'b1;
host_we <= #1 1'b1;
host_bs <= #1 2'b11;
if (host_ack) begin
wr_fifo_rd_en <= #1 1'b1;
wr_state <= #1 ST_WR_IDLE;
end
end
ST_WR_WAIT: begin
host_cs <= #1 1'b0;
host_we <= #1 1'b0;
host_bs <= #1 2'b00;
wr_state <= #1 ST_WR_IDLE;
wr_fifo_rd_en <= #1 1'b0;
end
endcase
end
end
end
reg [ 8-1:0] mem_page;
reg [24-1:0] mem_cnt;
wire [32-1:0] mem_adr;
always @ (posedge clk) begin
if (clk7_en) begin
if (rx && !cmd && spi_mem_write_sel) begin
case (dat_cnt)
0 : mem_cnt [ 7: 0] <= #1 wrdat[7:0];
1 : mem_cnt [15: 8] <= #1 wrdat[7:0];
2 : mem_cnt [23:16] <= #1 wrdat[7:0];
3 : mem_page[ 7: 0] <= #1 wrdat[7:0];
endcase
end else if (wr_fifo_rd_en) mem_cnt [23:0] <= #1 mem_cnt + 24'd2;
end
end
assign mem_adr = {mem_page, mem_cnt};
assign host_adr = mem_adr[23:0];
// rtl version
`include "minimig_version.vh"
reg [8-1:0] rtl_ver;
always @ (*) begin
case (dat_cnt[2:0])
2'b00 : rtl_ver = BETA_FLAG;
2'b01 : rtl_ver = MAJOR_VER;
2'b10 : rtl_ver = MINOR_VER;
default : rtl_ver = SEPARATOR;
endcase
end
// read data
assign rddat = (spi_version_sel) ? rtl_ver :
(spi_mem_read_sel) ? 8'd00 : osd_ctrl;
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = { COx, CIx };
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cin (
.I0(CI),
.I1(1'b1),
.CI(1'b0),
.CO(CIx)
);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_i (
.I0(AA[i]),
.I1(BB[i]),
.CI(C[i]),
.O(Y[i]),
.CO(COx[i])
);
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cout (
.I0(1'b0),
.I1(1'b0),
.CI(COx[i]),
.O(CO[i])
);
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
genvar g;
integer i;
reg [31:0] v;
reg [31:0] gen_pre_PLUSPLUS = 32'h0;
reg [31:0] gen_pre_MINUSMINUS = 32'h0;
reg [31:0] gen_post_PLUSPLUS = 32'h0;
reg [31:0] gen_post_MINUSMINUS = 32'h0;
reg [31:0] gen_PLUSEQ = 32'h0;
reg [31:0] gen_MINUSEQ = 32'h0;
reg [31:0] gen_TIMESEQ = 32'h0;
reg [31:0] gen_DIVEQ = 32'h0;
reg [31:0] gen_MODEQ = 32'h0;
reg [31:0] gen_ANDEQ = 32'h0;
reg [31:0] gen_OREQ = 32'h0;
reg [31:0] gen_XOREQ = 32'h0;
reg [31:0] gen_SLEFTEQ = 32'h0;
reg [31:0] gen_SRIGHTEQ = 32'h0;
reg [31:0] gen_SSRIGHTEQ = 32'h0;
generate
for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1;
for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1;
for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1;
for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1;
for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1;
for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1;
`ifndef verilator //UNSUPPORTED
for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1;
for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1;
for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1;
for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1;
for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1;
for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1;
for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1;
for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1;
for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1;
`endif
endgenerate
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 3) begin
`ifdef TEST_VERBOSE
$write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS);
$write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS);
$write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS);
$write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS);
$write("gen_PLUSEQ %b\n", gen_PLUSEQ);
$write("gen_MINUSEQ %b\n", gen_MINUSEQ);
$write("gen_TIMESEQ %b\n", gen_TIMESEQ);
$write("gen_DIVEQ %b\n", gen_DIVEQ);
$write("gen_MODEQ %b\n", gen_MODEQ);
$write("gen_ANDEQ %b\n", gen_ANDEQ);
$write("gen_OREQ %b\n", gen_OREQ);
$write("gen_XOREQ %b\n", gen_XOREQ);
$write("gen_SLEFTEQ %b\n", gen_SLEFTEQ);
$write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ);
$write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ);
`endif
if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop;
if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop;
if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop;
`ifndef verilator //UNSUPPORTED
if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop;
if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop;
if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop;
if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop;
if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop;
if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop;
if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop;
if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
`endif
v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
`ifndef verilator //UNSUPPORTED
v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop;
v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop;
v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop;
v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 14
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_14_top,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_us_1,axi_dwidth_converter_v2_1_14_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_us_1,axi_dwidth_converter_v2_1_14_top,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C\
_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_14_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
-- ============================================================================
-- FILE NAME : bus_master_mux.v
-- DESCRIPTION : ×ÜÏßÖ÷¿Ø¶à·¸´ÓÃÆ÷ʵÏÖ
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ͨÓÃÍ·Îļþ **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** Ä£¿éÍ·Îļþ **********/
`include "bus.h"
/********** Ä£¿é **********/
module bus_master_mux (
/********** ÊäÈëÊä³öÐźŠ**********/
// 0ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m0_addr, // µØÖ·
input wire m0_as_, // µØַѡͨ
input wire m0_rw, // ¶Á/д
input wire [`WordDataBus] m0_wr_data, // дÈëµÄÊý¾Ý
input wire m0_grnt_, // ¸³Óè×ÜÏß
// 1ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m1_addr, // µØÖ·
input wire m1_as_, // µØַѡͨ
input wire m1_rw, // ¶Á/д
input wire [`WordDataBus] m1_wr_data, // дÈëµÄÊý¾Ý
input wire m1_grnt_, // ¸³Óè×ÜÏß
// 3ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m2_addr, // µØÖ·
input wire m2_as_, // µØַѡͨ
input wire m2_rw, // ¶Á/д
input wire [`WordDataBus] m2_wr_data, // дÈëµÄÊý¾Ý
input wire m2_grnt_, // ¸³Óè×ÜÏß
// 3ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m3_addr, // µØÖ·
input wire m3_as_, // µØַѡͨ
input wire m3_rw, // ¶Á/д
input wire [`WordDataBus] m3_wr_data, // дÈëµÄÊý¾Ý
input wire m3_grnt_, // ¸³Óè×ÜÏß
/********** ¹²ÏíÐźÅ×ÜÏß´ÓÊô **********/
output reg [`WordAddrBus] s_addr, // µØÖ·
output reg s_as_, // µØַѡͨ
output reg s_rw, // ¶Á/д
output reg [`WordDataBus] s_wr_data // дÈëµÄÊý¾Ý
);
/********** ×ÜÏßÖ÷¿Ø¶à·¸´ÓÃÆ÷ **********/
always @(*) begin
/* Ñ¡Ôñ³ÖÓÐ×ÜÏßʹÓÃȨµÄÖ÷¿Ø */
if (m0_grnt_ == `ENABLE_) begin // 0ºÅ×ÜÏß×Ü¿Ø
s_addr = m0_addr;
s_as_ = m0_as_;
s_rw = m0_rw;
s_wr_data = m0_wr_data;
end else if (m1_grnt_ == `ENABLE_) begin // 1ºÅ×ÜÏß×Ü¿Ø
s_addr = m1_addr;
s_as_ = m1_as_;
s_rw = m1_rw;
s_wr_data = m1_wr_data;
end else if (m2_grnt_ == `ENABLE_) begin // 2ºÅ×ÜÏß×Ü¿Ø
s_addr = m2_addr;
s_as_ = m2_as_;
s_rw = m2_rw;
s_wr_data = m2_wr_data;
end else if (m3_grnt_ == `ENABLE_) begin // 3ºÅ×ÜÏß×Ü¿Ø
s_addr = m3_addr;
s_as_ = m3_as_;
s_rw = m3_rw;
s_wr_data = m3_wr_data;
end else begin // ĬÈÏÖµ
s_addr = `WORD_ADDR_W'h0;
s_as_ = `DISABLE_;
s_rw = `READ;
s_wr_data = `WORD_DATA_W'h0;
end
end
endmodule
|
//`include"DataPath.v"
//`include"Controller.v"
module CPU(input clk,rst);
wire[1:0] stackContrl,pcContrl;
wire[5:0] cntrlInstruc;
DataPath dp(clk,rst,RdOrR2,AluOrMem,RFWE,MWE,stackContrl,pcContrl,Zero,Cout,cntrlInstruc);
Controller cntrl(clk,rst,RdOrR2,AluOrMem,RFWE,MWE,stackContrl,pcContrl,Zero,Cout,cntrlInstruc);
endmodule
module CPUTB();
initial begin
$dumpfile("CPUTB.vcd");
$dumpvars;
end
//integer outfile,regFile;
integer i,ramOut;
reg clk,rst;
parameter delta = 10;
initial begin clk = 0; forever #delta clk = ~clk; end
CPU UUT(clk,rst);
initial begin
ramOut = $fopen("ramModified.bin") | 1;
//regFile = $fopen("regsOut.bin") | 1;
rst=0;
#1 rst=1;
#(1+delta) rst=0;
for(i=0;i<500;i=i+1)
begin
//#(2*delta) $fdisplay(regFile, "%8d,%8d,%8d,%8d,%8d,%8d,%8d,%8d,%4d",UUT.dp.RF.registers[0],UUT.dp.RF.registers[1],UUT.dp.RF.registers[2],UUT.dp.RF.registers[3],UUT.dp.RF.registers[4],UUT.dp.RF.registers[5],UUT.dp.RF.registers[6],UUT.dp.RF.registers[7],UUT.dp.Alu.Zero);
#(2*delta) $display("%8d,%8d,%8d,%8d,%8d,%8d,%8d,%8d",UUT.dp.RF.registers[0],UUT.dp.RF.registers[1],UUT.dp.RF.registers[2],UUT.dp.RF.registers[3],UUT.dp.RF.registers[4],UUT.dp.RF.registers[5],UUT.dp.RF.registers[6],UUT.dp.RF.registers[7]);
end
for(i=0;i<256;i=i+1)
begin
$fdisplay(ramOut, "%8b", UUT.dp.Mem.data[i]);
end
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pipe_eq.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_eq.v
// Description : PIPE Equalization Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Equalization Module ------------------------------------------
module pcie_7x_v1_11_0_pipe_eq #
(
parameter PCIE_SIM_MODE = "FALSE",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_RXEQ_MODE_GEN3 = 1
)
(
//---------- Input -------------------------------------
input EQ_CLK,
input EQ_RST_N,
input EQ_GEN3,
input [ 1:0] EQ_TXEQ_CONTROL,
input [ 3:0] EQ_TXEQ_PRESET,
input [ 3:0] EQ_TXEQ_PRESET_DEFAULT,
input [ 5:0] EQ_TXEQ_DEEMPH_IN,
input [ 1:0] EQ_RXEQ_CONTROL,
input [ 2:0] EQ_RXEQ_PRESET,
input [ 5:0] EQ_RXEQ_LFFS,
input [ 3:0] EQ_RXEQ_TXPRESET,
input EQ_RXEQ_USER_EN,
input [17:0] EQ_RXEQ_USER_TXCOEFF,
input EQ_RXEQ_USER_MODE,
//---------- Output ------------------------------------
output EQ_TXEQ_DEEMPH,
output [ 4:0] EQ_TXEQ_PRECURSOR,
output [ 6:0] EQ_TXEQ_MAINCURSOR,
output [ 4:0] EQ_TXEQ_POSTCURSOR,
output [17:0] EQ_TXEQ_DEEMPH_OUT,
output EQ_TXEQ_DONE,
output [ 5:0] EQ_TXEQ_FSM,
output [17:0] EQ_RXEQ_NEW_TXCOEFF,
output EQ_RXEQ_LFFS_SEL,
output EQ_RXEQ_ADAPT_DONE,
output EQ_RXEQ_DONE,
output [ 5:0] EQ_RXEQ_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2;
//---------- Internal Signals --------------------------
reg [18:0] txeq_preset = 19'd0;
reg txeq_preset_done = 1'd0;
reg [ 1:0] txeq_txcoeff_cnt = 2'd0;
reg [ 2:0] rxeq_preset = 3'd0;
reg rxeq_preset_valid = 1'd0;
reg [ 3:0] rxeq_txpreset = 4'd0;
reg [17:0] rxeq_txcoeff = 18'd0;
reg [ 2:0] rxeq_cnt = 3'd0;
reg [ 5:0] rxeq_fs = 6'd0;
reg [ 5:0] rxeq_lf = 6'd0;
reg rxeq_new_txcoeff_req = 1'd0;
//---------- Output Registers --------------------------
reg [18:0] txeq_txcoeff = 19'd0;
reg txeq_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg [17:0] rxeq_new_txcoeff = 18'd0;
reg rxeq_lffs_sel = 1'd0;
reg rxeq_adapt_done_reg = 1'd0;
reg rxeq_adapt_done = 1'd0;
reg rxeq_done = 1'd0;
reg [ 5:0] fsm_rx = 6'd0;
//---------- RXEQ Eye Scan Module Output ---------------
wire rxeqscan_lffs_sel;
wire rxeqscan_preset_done;
wire [17:0] rxeqscan_new_txcoeff;
wire rxeqscan_new_txcoeff_done;
wire rxeqscan_adapt_done;
//---------- FSM ---------------------------------------
localparam FSM_TXEQ_IDLE = 6'b000001;
localparam FSM_TXEQ_PRESET = 6'b000010;
localparam FSM_TXEQ_TXCOEFF = 6'b000100;
localparam FSM_TXEQ_REMAP = 6'b001000;
localparam FSM_TXEQ_QUERY = 6'b010000;
localparam FSM_TXEQ_DONE = 6'b100000;
localparam FSM_RXEQ_IDLE = 6'b000001;
localparam FSM_RXEQ_PRESET = 6'b000010;
localparam FSM_RXEQ_TXCOEFF = 6'b000100;
localparam FSM_RXEQ_LF = 6'b001000;
localparam FSM_RXEQ_NEW_TXCOEFF_REQ = 6'b010000;
localparam FSM_RXEQ_DONE = 6'b100000;
//---------- TXEQ Presets Look-up Table ----------------
// TXPRECURSOR = Coefficient range between 0 and 20 units
// TXMAINCURSOR = Coefficient range between 29 and 80 units
// TXPOSTCURSOR = Coefficient range between 0 and 31 units
//------------------------------------------------------
// Actual Full Swing (FS) = 80
// Actual Low Frequency (LF) = 29
// Advertise Full Swing (FS) = 40
// Advertise Low Frequency (LF) = 15
//------------------------------------------------------
// Pre-emphasis = 20 log [80 - (2 * TXPRECURSOR)] / 80], assuming no de-emphasis
// Main-emphasis = 80 - (TXPRECURSOR + TXPOSTCURSOR)
// De-emphasis = 20 log [80 - (2 * TXPOSTCURSOR)] / 80], assuming no pre-emphasis
//------------------------------------------------------
// Note: TXMAINCURSOR calculated internally in GT
//------------------------------------------------------
localparam TXPRECURSOR_00 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_00 = 7'd60;
localparam TXPOSTCURSOR_00 = 6'd20; // -6.0 +/- 1 dB
localparam TXPRECURSOR_01 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_01 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_01 = 6'd13; // -3.5 +/- 1 dB
localparam TXPRECURSOR_02 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_02 = 7'd64;
localparam TXPOSTCURSOR_02 = 6'd16; // -4.4 +/- 1.5 dB
localparam TXPRECURSOR_03 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_03 = 7'd70;
localparam TXPOSTCURSOR_03 = 6'd10; // -2.5 +/- 1 dB
localparam TXPRECURSOR_04 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_04 = 7'd80;
localparam TXPOSTCURSOR_04 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_05 = 6'd8; // -1.9 +/- 1 dB
localparam TXMAINCURSOR_05 = 7'd72;
localparam TXPOSTCURSOR_05 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_06 = 6'd10; // -2.5 +/- 1 dB
localparam TXMAINCURSOR_06 = 7'd70;
localparam TXPOSTCURSOR_06 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_07 = 6'd8; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_07 = 7'd56;
localparam TXPOSTCURSOR_07 = 6'd16; // -6.0 +/- 1 dB
localparam TXPRECURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_08 = 7'd60;
localparam TXPOSTCURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXPRECURSOR_09 = 6'd13; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_09 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_09 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_10 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_10 = 7'd56; // added 1 to compensate decimal
localparam TXPOSTCURSOR_10 = 6'd25; // 9.5 +/- 1 dB, updated for coefficient rules
//---------- Input FF ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
txeq_control_reg1 <= 2'd0;
txeq_preset_reg1 <= 4'd0;
txeq_deemph_reg1 <= 6'd1;
rxeq_control_reg1 <= 2'd0;
rxeq_preset_reg1 <= 3'd0;
rxeq_lffs_reg1 <= 6'd0;
rxeq_txpreset_reg1 <= 4'd0;
rxeq_user_en_reg1 <= 1'd0;
rxeq_user_txcoeff_reg1 <= 18'd0;
rxeq_user_mode_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
txeq_control_reg2 <= 2'd0;
txeq_preset_reg2 <= 4'd0;
txeq_deemph_reg2 <= 6'd1;
rxeq_control_reg2 <= 2'd0;
rxeq_preset_reg2 <= 3'd0;
rxeq_lffs_reg2 <= 6'd0;
rxeq_txpreset_reg2 <= 4'd0;
rxeq_user_en_reg2 <= 1'd0;
rxeq_user_txcoeff_reg2 <= 18'd0;
rxeq_user_mode_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= EQ_GEN3;
txeq_control_reg1 <= EQ_TXEQ_CONTROL;
txeq_preset_reg1 <= EQ_TXEQ_PRESET;
txeq_deemph_reg1 <= EQ_TXEQ_DEEMPH_IN;
rxeq_control_reg1 <= EQ_RXEQ_CONTROL;
rxeq_preset_reg1 <= EQ_RXEQ_PRESET;
rxeq_lffs_reg1 <= EQ_RXEQ_LFFS;
rxeq_txpreset_reg1 <= EQ_RXEQ_TXPRESET;
rxeq_user_en_reg1 <= EQ_RXEQ_USER_EN;
rxeq_user_txcoeff_reg1 <= EQ_RXEQ_USER_TXCOEFF;
rxeq_user_mode_reg1 <= EQ_RXEQ_USER_MODE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
txeq_control_reg2 <= txeq_control_reg1;
txeq_preset_reg2 <= txeq_preset_reg1;
txeq_deemph_reg2 <= txeq_deemph_reg1;
rxeq_control_reg2 <= rxeq_control_reg1;
rxeq_preset_reg2 <= rxeq_preset_reg1;
rxeq_lffs_reg2 <= rxeq_lffs_reg1;
rxeq_txpreset_reg2 <= rxeq_txpreset_reg1;
rxeq_user_en_reg2 <= rxeq_user_en_reg1;
rxeq_user_txcoeff_reg2 <= rxeq_user_txcoeff_reg1;
rxeq_user_mode_reg2 <= rxeq_user_mode_reg1;
end
end
//---------- TXEQ Preset -------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- Select TXEQ Preset ----------------
case (EQ_TXEQ_PRESET_DEFAULT)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd0;
end
else
begin
if (fsm_tx == FSM_TXEQ_PRESET)
begin
//---------- Select TXEQ Preset ----------------
case (txeq_preset_reg2)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd1;
end
else
begin
txeq_preset <= txeq_preset;
txeq_preset_done <= 1'd0;
end
end
end
//---------- TXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ----------------------------
FSM_TXEQ_IDLE :
begin
case (txeq_control_reg2)
//---------- Idle ------------------------------
2'd0 :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Process TXEQ Preset ---------------
2'd1 :
begin
fsm_tx <= FSM_TXEQ_PRESET;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Coefficient -----------------------
2'd2 :
begin
fsm_tx <= FSM_TXEQ_TXCOEFF;
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= 2'd1;
txeq_done <= 1'd0;
end
//---------- Query -----------------------------
2'd3 :
begin
fsm_tx <= FSM_TXEQ_QUERY;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
//---------- Process TXEQ Preset -------------------
FSM_TXEQ_PRESET :
begin
fsm_tx <= (txeq_preset_done ? FSM_TXEQ_DONE : FSM_TXEQ_PRESET);
txeq_txcoeff <= txeq_preset;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Latch Link Partner TX Coefficient -----
FSM_TXEQ_TXCOEFF :
begin
fsm_tx <= ((txeq_txcoeff_cnt == 2'd2) ? FSM_TXEQ_REMAP : FSM_TXEQ_TXCOEFF);
//---------- Shift in extra bit for TXMAINCURSOR
if (txeq_txcoeff_cnt == 2'd1)
txeq_txcoeff <= {1'd0, txeq_deemph_reg2, txeq_txcoeff[18:7]};
else
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= txeq_txcoeff_cnt + 2'd1;
txeq_done <= 1'd0;
end
//---------- Remap to GT TX Coefficient ------------
FSM_TXEQ_REMAP :
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff << 1; // Multiply by 2x
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Query TXEQ Coefficient ----------------
FSM_TXEQ_QUERY:
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Done ----------------------------------
FSM_TXEQ_DONE :
begin
fsm_tx <= ((txeq_control_reg2 == 2'd0) ? FSM_TXEQ_IDLE : FSM_TXEQ_DONE);
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ----------------------------
FSM_RXEQ_IDLE :
begin
case (rxeq_control_reg2)
//---------- Process RXEQ Preset ---------------
2'd1 :
begin
fsm_rx <= FSM_RXEQ_PRESET;
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient --------
2'd2 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Phase2/3 Bypass (reuse logic from rxeq_control = 2 ----
2'd3 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
//---------- Process RXEQ Preset -------------------
FSM_RXEQ_PRESET :
begin
fsm_rx <= (rxeqscan_preset_done ? FSM_RXEQ_DONE : FSM_RXEQ_PRESET);
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd1;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Shift-in Link Partner TX Coefficient and Preset
FSM_RXEQ_TXCOEFF :
begin
fsm_rx <= ((rxeq_cnt == 3'd2) ? FSM_RXEQ_LF : FSM_RXEQ_TXCOEFF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Read Low Frequency (LF) Value ---------
FSM_RXEQ_LF :
begin
fsm_rx <= ((rxeq_cnt == 3'd7) ? FSM_RXEQ_NEW_TXCOEFF_REQ : FSM_RXEQ_LF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= ((rxeq_cnt == 3'd7) ? rxeq_lffs_reg2 : rxeq_lf);
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient ------------
FSM_RXEQ_NEW_TXCOEFF_REQ :
begin
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
if (rxeqscan_new_txcoeff_done)
begin
fsm_rx <= FSM_RXEQ_DONE;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeqscan_lffs_sel ? {14'd0, rxeqscan_new_txcoeff[3:0]} : rxeqscan_new_txcoeff;
rxeq_lffs_sel <= rxeqscan_lffs_sel;
rxeq_adapt_done_reg <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXEQ_NEW_TXCOEFF_REQ;
rxeq_new_txcoeff_req <= 1'd1;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
end
//---------- RXEQ Done -----------------------------
FSM_RXEQ_DONE :
begin
fsm_rx <= ((rxeq_control_reg2 == 2'd0) ? FSM_RXEQ_IDLE : FSM_RXEQ_DONE);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= rxeq_lffs_sel;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeq_adapt_done;
rxeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Module ----------------------------------------------
pcie_7x_v1_11_0_rxeq_scan #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE),
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3)
)
rxeq_scan_i
(
//---------- Input -------------------------------------
.RXEQSCAN_CLK (EQ_CLK),
.RXEQSCAN_RST_N (EQ_RST_N),
.RXEQSCAN_CONTROL (rxeq_control_reg2),
.RXEQSCAN_FS (rxeq_fs),
.RXEQSCAN_LF (rxeq_lf),
.RXEQSCAN_PRESET (rxeq_preset),
.RXEQSCAN_PRESET_VALID (rxeq_preset_valid),
.RXEQSCAN_TXPRESET (rxeq_txpreset),
.RXEQSCAN_TXCOEFF (rxeq_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_REQ (rxeq_new_txcoeff_req),
//---------- Output ------------------------------------
.RXEQSCAN_PRESET_DONE (rxeqscan_preset_done),
.RXEQSCAN_NEW_TXCOEFF (rxeqscan_new_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_DONE (rxeqscan_new_txcoeff_done),
.RXEQSCAN_LFFS_SEL (rxeqscan_lffs_sel),
.RXEQSCAN_ADAPT_DONE (rxeqscan_adapt_done)
);
//---------- PIPE EQ Output ----------------------------------------------------
assign EQ_TXEQ_DEEMPH = txeq_txcoeff[0];
assign EQ_TXEQ_PRECURSOR = gen3_reg2 ? txeq_txcoeff[ 4: 0] : 5'h00;
assign EQ_TXEQ_MAINCURSOR = gen3_reg2 ? txeq_txcoeff[12: 6] : 7'h00;
assign EQ_TXEQ_POSTCURSOR = gen3_reg2 ? txeq_txcoeff[17:13] : 5'h00;
assign EQ_TXEQ_DEEMPH_OUT = {1'd0, txeq_txcoeff[18:14], txeq_txcoeff[12:7], 1'd0, txeq_txcoeff[5:1]}; // Divide by 2x
assign EQ_TXEQ_DONE = txeq_done;
assign EQ_TXEQ_FSM = fsm_tx;
assign EQ_RXEQ_NEW_TXCOEFF = rxeq_user_en_reg2 ? rxeq_user_txcoeff_reg2 : rxeq_new_txcoeff;
assign EQ_RXEQ_LFFS_SEL = rxeq_user_en_reg2 ? rxeq_user_mode_reg2 : rxeq_lffs_sel;
assign EQ_RXEQ_ADAPT_DONE = rxeq_adapt_done;
assign EQ_RXEQ_DONE = rxeq_done;
assign EQ_RXEQ_FSM = fsm_rx;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:36:10 11/21/2015
// Design Name: Datapath1
// Module Name: C:/Users/Ariel/Documents/finalArquitectura/TestDatapathPart1/DatapathPart1/DatapathTest.v
// Project Name: DatapathPart1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Datapath1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DatapathTestFinal;
// Inputs
reg clock;
reg resetGral;
// Outputs
wire ALUzero;
wire ALUOverflow;
// Instantiate the Unit Under Test (UUT)
Datapath1 uut (
.clock(clock),
.resetGral(resetGral),
.ALUzero(ALUzero),
.ALUOverflow(ALUOverflow)
);
initial begin
// Initialize Inputs
clock = 0;
resetGral = 1;
// Wait 100 ns for global reset to finish
#100;
resetGral=0;
// Add stimulus here
end
always begin
clock = ~clock;
#1;
end
endmodule
|
`include "constants.vh"
`default_nettype none
module exunit_mul
(
input wire clk,
input wire reset,
input wire [`DATA_LEN-1:0] ex_src1,
input wire [`DATA_LEN-1:0] ex_src2,
input wire dstval,
input wire [`SPECTAG_LEN-1:0] spectag,
input wire specbit,
input wire src1_signed,
input wire src2_signed,
input wire sel_lohi,
input wire issue,
input wire prmiss,
input wire [`SPECTAG_LEN-1:0] spectagfix,
output wire [`DATA_LEN-1:0] result,
output wire rrf_we,
output wire rob_we, //set finish
output wire kill_speculative
);
reg busy;
assign rob_we = busy;
assign rrf_we = busy & dstval;
assign kill_speculative = ((spectag & spectagfix) != 0) && specbit && prmiss;
always @ (posedge clk) begin
if (reset) begin
busy <= 0;
end else begin
busy <= issue;
end
end
multiplier bob
(
.src1(ex_src1),
.src2(ex_src2),
.src1_signed(src1_signed),
.src2_signed(src2_signed),
.sel_lohi(sel_lohi),
.result(result)
);
endmodule // exunit_mul
`default_nettype wire
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ef_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ef_e.v,v 1.1 2004/04/06 10:50:31 wig Exp $
// $Date: 2004/04/06 10:50:31 $
// $Log: inst_ef_e.v,v $
// Revision 1.1 2004/04/06 10:50:31 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , wilfried.gaensheimer@micronas.com
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ef_e
//
// No `defines in this module
module inst_ef_e
//
// Generated module inst_ef
//
(
cp_laddro,
cp_lcmd,
cpu_scani,
cpu_scano,
int23,
int24,
int25,
int26,
int27,
nreset,
nreset_s,
tap_reset_n,
tap_reset_n_o
);
// Generated Module Inputs:
input [7:0] cpu_scani;
input int23;
input int24;
input int25;
input int26;
input int27;
input nreset;
input nreset_s;
input tap_reset_n;
// Generated Module Outputs:
output [31:0] cp_laddro;
output [6:0] cp_lcmd;
output [7:0] cpu_scano;
output tap_reset_n_o;
// Generated Wires:
wire [31:0] cp_laddro;
wire [6:0] cp_lcmd;
wire [7:0] cpu_scani;
wire [7:0] cpu_scano;
wire int23;
wire int24;
wire int25;
wire int26;
wire int27;
wire nreset;
wire nreset_s;
wire tap_reset_n;
wire tap_reset_n_o;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ef_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DIODE_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_BLACKBOX_V
|
module TopLevel(clk,
key_in,
switch_in,
switch_second,
type_in,
s_out,
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RW,
LCD_RS,
LCD_DATA
);
input [3:0] key_in;
input clk;// 50Mhz clock signal
input switch_in; // switch of settime of countdowner
input [15:0] switch_second; // set time of countdowner
input type_in; // 7seg display timer or countdowner;
output [63:0] s_out;
wire [63:0] seg_o;
assign s_out = ~seg_o;
output LCD_ON, LCD_BLON, LCD_EN, LCD_RW, LCD_RS;
output [7:0] LCD_DATA;
assign LCD_ON = 1;
assign LCD_BLON = 1;
wire [1:0] lcd_func;
wire [7:0] lcd_data;
assign LCD_RS = lcd_func[1];
assign LCD_RW = lcd_func[0];
assign LCD_DATA = lcd_data;
wire [31:0] second;
wire [31:0] second_tmp;
wire [31:0] second_countdown;
wire [2:0] key_press;
reg slow_clk;
integer slow_clk_counter;
initial begin
slow_clk <= 0;
slow_clk_counter <= 0;
end
always@(negedge clk) begin
if (slow_clk_counter == 9) begin
slow_clk_counter <= 0;
slow_clk <= ~slow_clk;
end else begin
slow_clk_counter <= slow_clk_counter + 1;
end
end
Timer timer(slow_clk, key_press, second);
Settime settime(switch_in, switch_second, clk, second_tmp);
// I use key_press as well becasue I am lazy.....
Countdowner countdowner(slow_clk, second_tmp, key_press, second_countdown);
Display7seg display7seg(second, second_countdown, type_in, seg_o);
wire [127:0] show_time;
ShowTime showTime(second, show_time);
LCDDisplay lcdDisplay(slow_clk, key_press, show_time, LCD_EN, lcd_func, lcd_data);
// I remember TA said press means 1 to 0. Need some try.
ButtonSignal buttonSignal(slow_clk, key_in, key_press);
endmodule
|
/*
Onboard devices:
$00 RW - 8 leds
$01 RW - High 7seg led
$02 RW - Low 7seg led
$03 RW - 0RGB0RGB 2 leds
$04 R- - SSSSKKKK switches and keys
Timer:
$08 RW - IRQ | IEN | XXX | XXX | XXX | XXX | XXX | RUN
$09 RW - Prescaler 24-16 bits
$0A RW - Prescaler 15-8 bits
$0B RW - Prescaler 7-0 bits
IRQ - R- interrupt line status
IEN - RW enable interrupt
RUN - RW start/stop timer
*/
module simpleio (
input wire clk,
input wire rst,
input wire [3:0] AD,
input wire [7:0] DI,
output reg [7:0] DO,
input wire rw,
input wire cs,
output wire irq,
input wire clk_in,
// physical connections
output reg [7:0] leds,
output reg [7:0] led7hi,
output reg [7:0] led7lo,
output reg [2:0] rgb1,
output reg [2:0] rgb2,
input wire [3:0] switches,
input wire [3:0] keys
);
reg [23:0] timer_cnt;
reg [23:0] timer_prescaler;
reg [7:0] timer_mode;
reg timer_eq_flag;
assign irq = timer_mode[7] & timer_mode[6];
always @ (posedge clk_in) begin
if (rst) begin
timer_cnt <= 0;
timer_eq_flag <= 0;
end else begin
if (timer_mode[0]) begin
if (timer_cnt == timer_prescaler) begin
timer_eq_flag <= 1;
timer_cnt <= 0;
end else begin
timer_cnt <= timer_cnt + 1'b1;
if (timer_mode[7]) timer_eq_flag <= 0;
end
end
end
end
always @ (posedge clk) begin
if (rst) begin
leds <= 8'b11111111;
rgb1 <= 8'b111;
rgb2 <= 8'b111;
led7hi <= 0;
led7lo <= 0;
timer_mode <= 0;
timer_prescaler <= 0;
end else begin
if (timer_eq_flag) timer_mode[7] <= 1;
if (cs) begin
if (rw) begin
case (AD[3:0])
4'b0000: DO <= ~leds;
4'b0001: DO <= led7hi;
4'b0010: DO <= led7lo;
4'b0011: begin
DO[6:4] <= ~rgb1;
DO[2:0] <= ~rgb2;
end
4'b0100: DO <= {switches, ~keys};
4'b1000: begin
DO <= timer_mode;
timer_mode[7] <= 0;
end
4'b1001: DO <= timer_mode[0]?timer_cnt[23:16]:timer_prescaler[23:16];
4'b1010: DO <= timer_mode[0]?timer_cnt[15:8]:timer_prescaler[15:8];
4'b1011: DO <= timer_mode[0]?timer_cnt[7:0]:timer_prescaler[7:0];
endcase
end else begin
case (AD[3:0])
4'b0000: leds <= ~DI;
4'b0001: led7hi <= DI;
4'b0010: led7lo <= DI;
4'b0011: begin
rgb1 <= ~DI[6:4];
rgb2 <= ~DI[2:0];
end
4'b1000: timer_mode[6:0] <= DI[6:0];
4'b1001: timer_prescaler[23:16] <= DI;
4'b1010: timer_prescaler[15:8] <= DI;
4'b1011: timer_prescaler[7:0] <= DI;
endcase
end
end
end
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 15:29:45 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/fir_bp_lr/fir_bp_lr_stub.v
// Design : fir_bp_lr
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.1" *)
module fir_bp_lr(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [15:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [39:0]m_axis_data_tdata;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_SYMBOL_V
/**
* udp_dff$NSR_pp$PG: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND power
* pins.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$NSR_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
input SET ,
//# {{clocks|Clocking}}
input CLK_N,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:30:54 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n3162, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, shift_value_SHT2_EWR_4_, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n524, n525, n526,
n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n547,
n550, n555, n558, n563, n566, n567, n568, n569, n570, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n830, n831, n835, n838, n839, n842, n844,
n846, n851, n852, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, DP_OP_297J37_122_8400_n143, DP_OP_297J37_122_8400_n142,
DP_OP_297J37_122_8400_n141, DP_OP_297J37_122_8400_n140,
DP_OP_297J37_122_8400_n139, DP_OP_297J37_122_8400_n138,
DP_OP_297J37_122_8400_n137, DP_OP_297J37_122_8400_n136, n933, n934,
n935, n936, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n966, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1229, n1230, n1231, n1232, n1233,
n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243,
n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253,
n1254, n1255, n1256, n1257, n1258, n1259, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2356, n2357, n2358,
n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368,
n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378,
n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388,
n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398,
n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408,
n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418,
n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428,
n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438,
n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448,
n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458,
n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468,
n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478,
n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488,
n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498,
n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508,
n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518,
n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590,
n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2622,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2781, n2782, n2783, n2784, n2785, n2786,
n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796,
n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806,
n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816,
n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826,
n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836,
n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846,
n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856,
n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866,
n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876,
n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886,
n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896,
n2897, n2898, n2899, n2900, n2901, n2902, n2904, n2905, n2906, n2907,
n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917,
n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927,
n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937,
n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947,
n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957,
n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967,
n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977,
n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987,
n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997,
n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007,
n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017,
n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027,
n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037,
n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048,
n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058,
n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068,
n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078,
n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088,
n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098,
n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108,
n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118,
n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128,
n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138,
n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148,
n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158,
n3159, n3160, n3161;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:8] intDX_EWSW;
wire [31:13] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [16:0] Raw_mant_NRM_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [7:2] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [3:1] LZD_output_NRM2_EW;
wire [30:0] DMP_SFG;
wire [25:2] DmP_mant_SFG_SWR;
wire [15:12] DmP_mant_SFG_SWR_signed;
wire [25:12] Raw_mant_SGF;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX2TS inst_ShiftRegister_Q_reg_3_ ( .D(n927), .CK(clk), .RN(n3028), .Q(
Shift_reg_FLAGS_7[3]), .QN(n2683) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n825), .CK(clk), .RN(n2757),
.QN(n2682) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n824), .CK(clk), .RN(n3015),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n823), .CK(clk), .RN(n3011),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_3_ ( .D(n811), .CK(clk), .RN(n961), .Q(
DMP_EXP_EWSW[3]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n809), .CK(clk), .RN(n2769), .Q(
DMP_EXP_EWSW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n808), .CK(clk), .RN(n2765), .Q(
DMP_EXP_EWSW[6]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_9_ ( .D(n805), .CK(clk), .RN(n3008), .Q(
DMP_EXP_EWSW[9]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n804), .CK(clk), .RN(n3014), .Q(
DMP_EXP_EWSW[10]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n803), .CK(clk), .RN(n3014), .Q(
DMP_EXP_EWSW[11]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_12_ ( .D(n802), .CK(clk), .RN(n2757), .Q(
DMP_EXP_EWSW[12]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_14_ ( .D(n800), .CK(clk), .RN(n3005), .Q(
DMP_EXP_EWSW[14]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_15_ ( .D(n799), .CK(clk), .RN(n3005), .Q(
DMP_EXP_EWSW[15]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n798), .CK(clk), .RN(n3033), .Q(
DMP_EXP_EWSW[16]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n797), .CK(clk), .RN(n3006), .Q(
DMP_EXP_EWSW[17]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n796), .CK(clk), .RN(n1597), .Q(
DMP_EXP_EWSW[18]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_19_ ( .D(n795), .CK(clk), .RN(n3007), .Q(
DMP_EXP_EWSW[19]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_20_ ( .D(n794), .CK(clk), .RN(n3007), .Q(
DMP_EXP_EWSW[20]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n792), .CK(clk), .RN(n3008), .Q(
DMP_EXP_EWSW[22]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n790), .CK(clk), .RN(n963), .Q(
DMP_EXP_EWSW[24]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n788), .CK(clk), .RN(n3019), .Q(
DMP_EXP_EWSW[26]) );
DFFRX2TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n787), .CK(clk), .RN(n3019), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n783), .CK(clk), .RN(n1617), .Q(
OP_FLAG_EXP) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n782), .CK(clk), .RN(n3003), .Q(
ZERO_FLAG_EXP), .QN(n2684) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n780), .CK(clk), .RN(n3016), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n779), .CK(clk), .RN(n3016), .Q(
DMP_SHT2_EWSW[0]), .QN(n2698) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n777), .CK(clk), .RN(n3016), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n776), .CK(clk), .RN(n3016), .Q(
DMP_SHT2_EWSW[1]), .QN(n2652) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n774), .CK(clk), .RN(n3030), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n961), .Q(
DMP_SHT2_EWSW[2]), .QN(n2692) );
DFFRX4TS R_532 ( .D(n772), .CK(clk), .RN(n960), .Q(DMP_SFG[2]), .QN(n1242)
);
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n771), .CK(clk), .RN(n1594), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n770), .CK(clk), .RN(n1594), .Q(
DMP_SHT2_EWSW[3]), .QN(n2693) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n768), .CK(clk), .RN(n3015), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n765), .CK(clk), .RN(n2769), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n764), .CK(clk), .RN(n2769), .Q(
DMP_SHT2_EWSW[5]), .QN(n2694) );
DFFRX4TS R_95 ( .D(n763), .CK(clk), .RN(n2769), .Q(DMP_SFG[5]), .QN(n2634)
);
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n762), .CK(clk), .RN(n2765), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n761), .CK(clk), .RN(n2765), .Q(
DMP_SHT2_EWSW[6]), .QN(n2688) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n759), .CK(clk), .RN(n3018), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n758), .CK(clk), .RN(n3018), .Q(
DMP_SHT2_EWSW[7]), .QN(n2690) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n756), .CK(clk), .RN(n3033), .Q(
DMP_SHT1_EWSW[8]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n755), .CK(clk), .RN(n1617), .Q(
DMP_SHT2_EWSW[8]), .QN(n2689) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n754), .CK(clk), .RN(n3015), .Q(
DMP_SFG[8]), .QN(n2629) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n753), .CK(clk), .RN(n3008), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n750), .CK(clk), .RN(n3014), .Q(
DMP_SHT1_EWSW[10]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n749), .CK(clk), .RN(n3014), .Q(
DMP_SHT2_EWSW[10]), .QN(n2638) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n747), .CK(clk), .RN(n3014), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n746), .CK(clk), .RN(n3014), .Q(
DMP_SHT2_EWSW[11]), .QN(n2637) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n744), .CK(clk), .RN(n3014), .Q(
DMP_SHT1_EWSW[12]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n743), .CK(clk), .RN(n3014), .Q(
DMP_SHT2_EWSW[12]), .QN(n2636) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n741), .CK(clk), .RN(n2764), .Q(
DMP_SHT1_EWSW[13]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n2763), .Q(
DMP_SHT2_EWSW[13]), .QN(n2635) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n739), .CK(clk), .RN(n2766), .Q(
DMP_SFG[13]), .QN(n2696) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n738), .CK(clk), .RN(n3005), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n737), .CK(clk), .RN(n3005), .Q(
DMP_SHT2_EWSW[14]), .QN(n2644) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n735), .CK(clk), .RN(n3005), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n734), .CK(clk), .RN(n3005), .Q(
DMP_SHT2_EWSW[15]), .QN(n2643) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n733), .CK(clk), .RN(n3005), .Q(
DMP_SFG[15]), .QN(n2714) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n732), .CK(clk), .RN(n3005), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n731), .CK(clk), .RN(n3005), .Q(
DMP_SHT2_EWSW[16]), .QN(n2642) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n729), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n728), .CK(clk), .RN(n3006), .Q(
DMP_SHT2_EWSW[17]), .QN(n2641) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n727), .CK(clk), .RN(n1596), .Q(
DMP_SFG[17]), .QN(n2738) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n726), .CK(clk), .RN(n3033), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n725), .CK(clk), .RN(n1596), .Q(
DMP_SHT2_EWSW[18]), .QN(n2657) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n724), .CK(clk), .RN(n3033), .Q(
DMP_SFG[18]), .QN(n2712) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n723), .CK(clk), .RN(n3007), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n722), .CK(clk), .RN(n3007), .Q(
DMP_SHT2_EWSW[19]), .QN(n2656) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n721), .CK(clk), .RN(n1597), .Q(
DMP_SFG[19]), .QN(n2737) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n720), .CK(clk), .RN(n3007), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n719), .CK(clk), .RN(n3007), .Q(
DMP_SHT2_EWSW[20]), .QN(n2655) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n718), .CK(clk), .RN(n3007), .Q(
DMP_SFG[20]), .QN(n2700) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n717), .CK(clk), .RN(n3007), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n716), .CK(clk), .RN(n3007), .Q(
DMP_SHT2_EWSW[21]), .QN(n2654) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n714), .CK(clk), .RN(n3008), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n713), .CK(clk), .RN(n3008), .Q(
DMP_SHT2_EWSW[22]), .QN(n2653) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n712), .CK(clk), .RN(n3008), .Q(
DMP_SFG[22]), .QN(n2702) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n710), .CK(clk), .RN(n957), .Q(
DMP_SHT2_EWSW[23]), .QN(n2651) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n709), .CK(clk), .RN(n957), .Q(
DMP_SFG[23]), .QN(n2709) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n708), .CK(clk), .RN(n958), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n706), .CK(clk), .RN(n963), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n705), .CK(clk), .RN(n957), .Q(
DMP_SHT2_EWSW[24]), .QN(n2650) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n704), .CK(clk), .RN(n957), .Q(
DMP_SFG[24]), .QN(n2708) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n703), .CK(clk), .RN(n957), .Q(
DMP_exp_NRM_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n699), .CK(clk), .RN(n963), .Q(
DMP_SFG[25]), .QN(n2658) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n698), .CK(clk), .RN(n964), .Q(
DMP_exp_NRM_EW[2]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n697), .CK(clk), .RN(n963), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n696), .CK(clk), .RN(n3019), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n695), .CK(clk), .RN(n3019), .Q(
DMP_SHT2_EWSW[26]), .QN(n2649) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n694), .CK(clk), .RN(n3019), .Q(
DMP_SFG[26]), .QN(n2707) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n693), .CK(clk), .RN(n963), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n692), .CK(clk), .RN(n963), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n691), .CK(clk), .RN(n3019), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n690), .CK(clk), .RN(n3019), .Q(
DMP_SHT2_EWSW[27]), .QN(n2648) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n689), .CK(clk), .RN(n3019), .Q(
DMP_SFG[27]), .QN(n2706) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n688), .CK(clk), .RN(n3019), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n687), .CK(clk), .RN(n3019), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n686), .CK(clk), .RN(n3020), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n685), .CK(clk), .RN(n3020), .Q(
DMP_SHT2_EWSW[28]), .QN(n2647) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n684), .CK(clk), .RN(n3020), .Q(
DMP_SFG[28]), .QN(n2705) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n683), .CK(clk), .RN(n3020), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n682), .CK(clk), .RN(n3020), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1248) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n681), .CK(clk), .RN(n3021), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n679), .CK(clk), .RN(n3020), .Q(
DMP_SFG[29]), .QN(n2704) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n3020), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n677), .CK(clk), .RN(n3020), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n676), .CK(clk), .RN(n3021), .Q(
DMP_SHT1_EWSW[30]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n675), .CK(clk), .RN(n3021), .Q(
DMP_SHT2_EWSW[30]), .QN(n2640) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n674), .CK(clk), .RN(n3021), .Q(
DMP_SFG[30]), .QN(n2703) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n673), .CK(clk), .RN(n3021), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n671), .CK(clk), .RN(n2757), .Q(
DmP_EXP_EWSW[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n669), .CK(clk), .RN(n2756), .Q(
DmP_EXP_EWSW[1]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n668), .CK(clk), .RN(n3032), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n667), .CK(clk), .RN(n3030), .Q(
DmP_EXP_EWSW[2]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_4_ ( .D(n663), .CK(clk), .RN(n3004), .Q(
DmP_EXP_EWSW[4]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_7_ ( .D(n657), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_8_ ( .D(n655), .CK(clk), .RN(n1593), .Q(
DmP_EXP_EWSW[8]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_10_ ( .D(n651), .CK(clk), .RN(n1593), .Q(
DmP_EXP_EWSW[10]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_11_ ( .D(n649), .CK(clk), .RN(n2769), .Q(
DmP_EXP_EWSW[11]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_12_ ( .D(n647), .CK(clk), .RN(n2771), .Q(
DmP_EXP_EWSW[12]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n643), .CK(clk), .RN(n2769), .Q(
DmP_EXP_EWSW[14]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n641), .CK(clk), .RN(n2765), .Q(
DmP_EXP_EWSW[15]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n639), .CK(clk), .RN(n2771), .Q(
DmP_EXP_EWSW[16]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_18_ ( .D(n635), .CK(clk), .RN(n2768), .Q(
DmP_EXP_EWSW[18]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n633), .CK(clk), .RN(n961), .Q(
DmP_EXP_EWSW[19]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n627), .CK(clk), .RN(n961), .Q(
DmP_EXP_EWSW[22]) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n618), .CK(clk), .RN(n2754), .Q(
ZERO_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n617), .CK(clk), .RN(n3032), .Q(
ZERO_FLAG_SHT2), .QN(n2646) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n616), .CK(clk), .RN(n2760), .Q(
ZERO_FLAG_SFG), .QN(n2711) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n615), .CK(clk), .RN(n3009), .Q(
ZERO_FLAG_NRM) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n611), .CK(clk), .RN(n2758), .Q(
OP_FLAG_SHT2), .QN(n2687) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n609), .CK(clk), .RN(n3002), .Q(
SIGN_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n608), .CK(clk), .RN(n3002), .Q(
SIGN_FLAG_SHT2), .QN(n2645) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n607), .CK(clk), .RN(n3002), .Q(
SIGN_FLAG_SFG), .QN(n2710) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n606), .CK(clk), .RN(n3002), .Q(
SIGN_FLAG_NRM) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n585), .CK(clk), .RN(n3012), .Q(
Raw_mant_NRM_SWR[1]), .QN(n2639) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n577), .CK(clk), .RN(n3030), .Q(
Raw_mant_NRM_SWR[0]), .QN(n2628) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n570), .CK(clk), .RN(n3004), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n532), .CK(clk), .RN(n3004), .Q(
DmP_mant_SFG_SWR[17]), .QN(n2733) );
DFFSX1TS R_8 ( .D(n3112), .CK(clk), .SN(n3009), .Q(n2990) );
DFFSX4TS R_25 ( .D(n2746), .CK(clk), .SN(n3030), .Q(n2981) );
DFFSX4TS R_23 ( .D(n2576), .CK(clk), .SN(n1594), .Q(n2983) );
DFFSX4TS R_28 ( .D(n2745), .CK(clk), .SN(n1596), .Q(n2978) );
DFFSX4TS R_26 ( .D(n2576), .CK(clk), .SN(n1597), .Q(n2980) );
DFFSX1TS R_66 ( .D(n3067), .CK(clk), .SN(n2762), .Q(n2973) );
DFFSX1TS R_77 ( .D(n3046), .CK(clk), .SN(n1601), .Q(n2968) );
DFFSX1TS R_83 ( .D(n3042), .CK(clk), .SN(n1615), .Q(n2967) );
DFFSX1TS R_85 ( .D(n3063), .CK(clk), .SN(n2763), .Q(n2966) );
DFFSX1TS R_87 ( .D(n3062), .CK(clk), .SN(n2763), .Q(n2965) );
DFFRX4TS R_533 ( .D(n2976), .CK(clk), .RN(n1617), .Q(n2977) );
DFFSX1TS R_141 ( .D(n3049), .CK(clk), .SN(n2768), .Q(n2958) );
DFFSX1TS R_142 ( .D(n3048), .CK(clk), .SN(n2768), .Q(n2957) );
DFFSX1TS R_145 ( .D(n3087), .CK(clk), .SN(n2756), .Q(n2956) );
DFFSX1TS R_146 ( .D(n3086), .CK(clk), .SN(n2756), .Q(n2955) );
DFFSX1TS R_157 ( .D(n3054), .CK(clk), .SN(n2766), .Q(n2950) );
DFFSX1TS R_172 ( .D(n3073), .CK(clk), .SN(n2759), .Q(n2943) );
DFFSX1TS R_174 ( .D(n3072), .CK(clk), .SN(n2759), .Q(n2942) );
DFFSX1TS R_185 ( .D(n3058), .CK(clk), .SN(n2763), .Q(n2937) );
DFFSX1TS R_188 ( .D(n3070), .CK(clk), .SN(n2759), .Q(n2936) );
DFFSX4TS R_203 ( .D(n2744), .CK(clk), .SN(n3013), .Q(n2927) );
DFFSX4TS R_201 ( .D(n2576), .CK(clk), .SN(n1594), .Q(n2929) );
DFFSX4TS R_206 ( .D(n2661), .CK(clk), .SN(n3013), .Q(n2924) );
DFFSX4TS R_204 ( .D(n3037), .CK(clk), .SN(n3013), .Q(n2926) );
DFFSX4TS R_209 ( .D(n3040), .CK(clk), .SN(n3013), .Q(n2918) );
DFFSX4TS R_207 ( .D(n2576), .CK(clk), .SN(n3012), .Q(n2920) );
DFFSX4TS R_215 ( .D(n3041), .CK(clk), .SN(n3012), .Q(n2915) );
DFFSX4TS R_213 ( .D(n3036), .CK(clk), .SN(n3013), .Q(n2917) );
DFFSX1TS R_220 ( .D(n3107), .CK(clk), .SN(n2749), .Q(n2913) );
DFFSX1TS R_222 ( .D(n3106), .CK(clk), .SN(n2749), .Q(n2912) );
DFFRXLTS R_236 ( .D(n3092), .CK(clk), .RN(n1616), .Q(n2904) );
DFFRXLTS R_240 ( .D(n3095), .CK(clk), .RN(n1616), .Q(n2901) );
DFFRX1TS R_257 ( .D(n2998), .CK(clk), .RN(n2767), .Q(n2897) );
DFFSX2TS R_267 ( .D(n3093), .CK(clk), .SN(n2770), .Q(n2895) );
DFFSX2TS R_279 ( .D(n2628), .CK(clk), .SN(n3161), .Q(n2891) );
DFFSX2TS R_328 ( .D(n2997), .CK(clk), .SN(n2764), .Q(n2881) );
DFFSX2TS R_338 ( .D(n1574), .CK(clk), .SN(n2766), .Q(n2876) );
DFFRX1TS R_382 ( .D(n3066), .CK(clk), .RN(n2762), .Q(n2858) );
DFFSX2TS R_398 ( .D(n3057), .CK(clk), .SN(n2764), .Q(n2850) );
DFFSX1TS R_407 ( .D(n3075), .CK(clk), .SN(n3006), .Q(n2844) );
DFFSX1TS R_405 ( .D(n3077), .CK(clk), .SN(n2760), .Q(n2846) );
DFFRX1TS R_417 ( .D(Raw_mant_NRM_SWR[6]), .CK(clk), .RN(n2766), .Q(n2837) );
DFFSX1TS R_421 ( .D(n3043), .CK(clk), .SN(n1601), .Q(n2834) );
DFFSX1TS R_419 ( .D(n3045), .CK(clk), .SN(n1588), .Q(n2836) );
DFFSX1TS R_420 ( .D(n3044), .CK(clk), .SN(n1601), .Q(n2835) );
DFFSX1TS R_424 ( .D(n3050), .CK(clk), .SN(n2767), .Q(n2831) );
DFFSX1TS R_422 ( .D(n3052), .CK(clk), .SN(n2767), .Q(n2833) );
DFFSX1TS R_423 ( .D(n3051), .CK(clk), .SN(n2767), .Q(n2832) );
DFFSX4TS R_426 ( .D(n3056), .CK(clk), .SN(n3011), .Q(n2829) );
DFFSX2TS R_427 ( .D(n3055), .CK(clk), .SN(n3011), .Q(n2828) );
DFFSX1TS R_428 ( .D(n3084), .CK(clk), .SN(n3010), .Q(n2827) );
DFFSX1TS R_429 ( .D(n3083), .CK(clk), .SN(n3012), .Q(n2826) );
DFFSX1TS R_430 ( .D(n3082), .CK(clk), .SN(n3010), .Q(n2825) );
DFFSX1TS R_431 ( .D(n3081), .CK(clk), .SN(n3010), .Q(n2824) );
DFFSX4TS R_436 ( .D(n3103), .CK(clk), .SN(n1596), .Q(n2822) );
DFFSX2TS R_437 ( .D(n3102), .CK(clk), .SN(n1596), .Q(n2821) );
DFFSX1TS R_376_RW_0 ( .D(DmP_mant_SHT1_SW[14]), .CK(clk), .SN(n3006), .Q(
n2862) );
DFFSX1TS R_297_RW_0 ( .D(DmP_mant_SHT1_SW[19]), .CK(clk), .SN(n2773), .Q(
n2887) );
DFFSX1TS R_289_RW_0 ( .D(DmP_mant_SHT1_SW[13]), .CK(clk), .SN(n2767), .Q(
n2889) );
DFFSX1TS R_242_RW_0 ( .D(DmP_mant_SHT1_SW[3]), .CK(clk), .SN(n2767), .Q(
n2900) );
DFFSX1TS R_238_RW_0 ( .D(DmP_mant_SHT1_SW[2]), .CK(clk), .SN(n2773), .QN(
n971) );
DFFSX2TS R_473 ( .D(n846), .CK(clk), .SN(n3161), .Q(n2803) );
DFFSX2TS R_478 ( .D(n3079), .CK(clk), .SN(n3006), .Q(n2799) );
DFFSX2TS R_479 ( .D(n3078), .CK(clk), .SN(n2760), .Q(n2798) );
DFFSX2TS R_480 ( .D(n1103), .CK(clk), .SN(n2768), .Q(n2797) );
DFFSX2TS R_482 ( .D(n3047), .CK(clk), .SN(n2768), .Q(n2796) );
DFFSX4TS R_489 ( .D(n3001), .CK(clk), .SN(n1597), .Q(n2790) );
DFFSX4TS R_488 ( .D(n3113), .CK(clk), .SN(n1596), .Q(n2791) );
DFFSX1TS R_496 ( .D(n839), .CK(clk), .SN(n2762), .Q(n2787) );
DFFSX1TS R_500 ( .D(n838), .CK(clk), .SN(n2755), .Q(n2785) );
DFFRX1TS R_503 ( .D(n2985), .CK(clk), .RN(n1618), .Q(n2784) );
DFFSX2TS R_504 ( .D(n835), .CK(clk), .SN(n3161), .Q(n2783) );
DFFSX1TS R_506 ( .D(Raw_mant_NRM_SWR[7]), .CK(clk), .SN(n2763), .Q(n2782) );
DFFSX2TS R_509 ( .D(n1661), .CK(clk), .SN(n3029), .Q(n2781) );
DFFSX1TS R_514 ( .D(n1243), .CK(clk), .SN(n1601), .Q(n2778) );
DFFSX1TS R_518 ( .D(n1573), .CK(clk), .SN(n2768), .Q(n2777) );
DFFSX1TS R_525 ( .D(n2741), .CK(clk), .SN(n3030), .Q(n2774) );
DFFSX1TS R_522 ( .D(Raw_mant_NRM_SWR[1]), .CK(clk), .SN(n1617), .Q(n2775) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n827), .CK(clk), .RN(n2759),
.Q(Shift_amount_SHT1_EWR[0]), .QN(n2664) );
DFFSX2TS R_72 ( .D(n3157), .CK(clk), .SN(n2748), .Q(n2971) );
DFFSX2TS R_76 ( .D(n3155), .CK(clk), .SN(n2748), .Q(n2969) );
DFFSX2TS R_103 ( .D(n3114), .CK(clk), .SN(n2751), .Q(n2961) );
DFFSX2TS R_107 ( .D(n1211), .CK(clk), .SN(n2751), .Q(n2959) );
DFFSX2TS R_150 ( .D(n3119), .CK(clk), .SN(n2752), .Q(n2953) );
DFFSX2TS R_154 ( .D(n3151), .CK(clk), .SN(n3003), .Q(n2951) );
DFFSX2TS R_162 ( .D(n3153), .CK(clk), .SN(n3003), .Q(n2948) );
DFFSX2TS R_171 ( .D(n3149), .CK(clk), .SN(n2749), .Q(n2944) );
DFFSX2TS R_178 ( .D(n3123), .CK(clk), .SN(n2752), .Q(n2940) );
DFFSX2TS R_182 ( .D(n3145), .CK(clk), .SN(n2750), .Q(n2938) );
DFFSX2TS R_192 ( .D(n3117), .CK(clk), .SN(n2752), .Q(n2934) );
DFFSX2TS R_196 ( .D(n3143), .CK(clk), .SN(n982), .Q(n2932) );
DFFSX2TS R_200 ( .D(n3139), .CK(clk), .SN(n982), .Q(n2930) );
DFFSX2TS R_315 ( .D(n3125), .CK(clk), .SN(n2753), .Q(n2884) );
DFFSX2TS R_342 ( .D(n3129), .CK(clk), .SN(n2750), .Q(n2874) );
DFFSX2TS R_354 ( .D(n3137), .CK(clk), .SN(n2750), .Q(n2870) );
DFFSX2TS R_366 ( .D(n3131), .CK(clk), .SN(n982), .Q(n2867) );
DFFSX2TS R_370 ( .D(n3141), .CK(clk), .SN(n982), .Q(n2865) );
DFFSX2TS R_374 ( .D(n3127), .CK(clk), .SN(n2753), .Q(n2863) );
DFFSX2TS R_380 ( .D(n3135), .CK(clk), .SN(n2750), .Q(n2860) );
DFFSX2TS R_387 ( .D(n3133), .CK(clk), .SN(n2771), .Q(n2856) );
DFFSX2TS R_395 ( .D(n3147), .CK(clk), .SN(n964), .Q(n2852) );
DFFSX2TS R_404 ( .D(n3121), .CK(clk), .SN(n2773), .Q(n2847) );
DFFSX2TS R_70 ( .D(n3158), .CK(clk), .SN(n2748), .Q(n2972) );
DFFSX2TS R_74 ( .D(n3156), .CK(clk), .SN(n3003), .Q(n2970) );
DFFSX2TS R_101 ( .D(n3115), .CK(clk), .SN(n2751), .Q(n2962) );
DFFSX2TS R_105 ( .D(n3116), .CK(clk), .SN(n2751), .Q(n2960) );
DFFSX2TS R_148 ( .D(n1324), .CK(clk), .SN(n2752), .Q(n2954) );
DFFSX2TS R_152 ( .D(n3152), .CK(clk), .SN(n3003), .Q(n2952) );
DFFSX2TS R_169 ( .D(n3150), .CK(clk), .SN(n2749), .Q(n2945) );
DFFSX2TS R_180 ( .D(n3146), .CK(clk), .SN(n982), .Q(n2939) );
DFFSX2TS R_190 ( .D(n3118), .CK(clk), .SN(n2753), .Q(n2935) );
DFFSX2TS R_194 ( .D(n3144), .CK(clk), .SN(n982), .Q(n2933) );
DFFSX2TS R_198 ( .D(n3140), .CK(clk), .SN(n982), .Q(n2931) );
DFFSX2TS R_313 ( .D(n3126), .CK(clk), .SN(n2753), .Q(n2885) );
DFFSX2TS R_340 ( .D(n3130), .CK(clk), .SN(n2750), .Q(n2875) );
DFFSX2TS R_352 ( .D(n3138), .CK(clk), .SN(n2750), .Q(n2871) );
DFFSX2TS R_364 ( .D(n3132), .CK(clk), .SN(n982), .Q(n2868) );
DFFSX2TS R_368 ( .D(n3142), .CK(clk), .SN(n982), .Q(n2866) );
DFFSX2TS R_372 ( .D(n3128), .CK(clk), .SN(n2753), .Q(n2864) );
DFFSX2TS R_378 ( .D(n3136), .CK(clk), .SN(n3032), .Q(n2861) );
DFFSX2TS R_385 ( .D(n3134), .CK(clk), .SN(n3021), .Q(n2857) );
DFFSX2TS R_393 ( .D(n3148), .CK(clk), .SN(n3007), .Q(n2853) );
DFFSX2TS R_402 ( .D(n3122), .CK(clk), .SN(n3002), .Q(n2848) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n620), .CK(clk), .RN(n3031), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n619), .CK(clk), .RN(n3003), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n815), .CK(clk), .RN(n3002), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n613), .CK(clk), .RN(n1596), .Q(
zero_flag) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n700), .CK(clk), .RN(n964), .QN(n2725) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n640), .CK(clk), .RN(n2765), .Q(
DmP_mant_SHT1_SW[15]) );
DFFSX2TS R_454 ( .D(n1103), .CK(clk), .SN(n3030), .Q(n2816) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n822), .CK(clk), .RN(n2748), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n821), .CK(clk), .RN(n2748), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n820), .CK(clk), .RN(n2748), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n819), .CK(clk), .RN(n2748), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n818), .CK(clk), .RN(n2748), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n817), .CK(clk), .RN(n3002), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n816), .CK(clk), .RN(n3002), .Q(
final_result_ieee[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n658), .CK(clk), .RN(n2761), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS inst_ShiftRegister_Q_reg_2_ ( .D(n926), .CK(clk), .RN(n3028), .Q(
Shift_reg_FLAGS_7[2]), .QN(n2659) );
DFFSX2TS R_396 ( .D(n1103), .CK(clk), .SN(n2764), .Q(n2851) );
DFFSX2TS R_410 ( .D(n2922), .CK(clk), .SN(n2759), .Q(n2842) );
DFFSX2TS R_469 ( .D(n842), .CK(clk), .SN(n2755), .Q(n2806) );
DFFSX2TS R_492 ( .D(n851), .CK(clk), .SN(n2756), .Q(n2788) );
DFFSX2TS R_512 ( .D(n1349), .CK(clk), .SN(n1594), .Q(n2779) );
DFFSX2TS R_390 ( .D(n3064), .CK(clk), .SN(n2764), .Q(n2854) );
DFFSX2TS R_460 ( .D(n1345), .CK(clk), .SN(n3029), .Q(n2811) );
DFFSX2TS R_467 ( .D(n1345), .CK(clk), .SN(n2755), .Q(n2807) );
DFFSX2TS R_490 ( .D(n3089), .CK(clk), .SN(n2756), .Q(n2789) );
DFFSX2TS R_510 ( .D(n3088), .CK(clk), .SN(n1594), .QN(n975) );
DFFSX2TS R_425 ( .D(n1608), .CK(clk), .SN(n3011), .Q(n2830) );
DFFSX2TS R_483 ( .D(n1608), .CK(clk), .SN(n2768), .Q(n2795) );
DFFSX2TS R_389 ( .D(n3065), .CK(clk), .SN(n2764), .Q(n2855) );
DFFSX2TS R_453 ( .D(n1608), .CK(clk), .SN(n2760), .Q(n2817) );
DFFSX2TS R_451 ( .D(n2984), .CK(clk), .SN(n2760), .Q(n2819) );
DFFSX2TS R_452 ( .D(n3071), .CK(clk), .SN(n2760), .Q(n2818) );
DFFSX1TS R_413 ( .D(n3100), .CK(clk), .SN(n1597), .Q(n2840) );
DFFSX1TS R_415 ( .D(n3098), .CK(clk), .SN(n1596), .Q(n2838) );
DFFSX1TS R_412 ( .D(n3101), .CK(clk), .SN(n1597), .Q(n2841) );
DFFSX2TS R_456 ( .D(n3074), .CK(clk), .SN(n3013), .Q(n2815) );
DFFSX2TS R_462 ( .D(n844), .CK(clk), .SN(n3029), .Q(n2809) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n574), .CK(clk), .RN(n2770), .Q(
Raw_mant_NRM_SWR[3]), .QN(n2741) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n778), .CK(clk), .RN(n3016), .Q(
DMP_SFG[0]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n563), .CK(clk), .RN(n2757), .Q(
DmP_mant_SFG_SWR[4]), .QN(n2993) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n599), .CK(clk), .RN(n1589), .Q(
Raw_mant_NRM_SWR[16]), .QN(n2994) );
DFFSX4TS R_487 ( .D(n3116), .CK(clk), .SN(n3006), .Q(n2792) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n581), .CK(clk), .RN(n2761), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1661) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n573), .CK(clk), .RN(n2758), .Q(
LZD_output_NRM2_EW[3]), .QN(n1404) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n576), .CK(clk), .RN(n2758), .Q(
DmP_mant_SFG_SWR[2]), .QN(n2672) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n584), .CK(clk), .RN(n2758), .Q(
LZD_output_NRM2_EW[2]), .QN(n1403) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n550), .CK(clk), .RN(n2770), .Q(
DmP_mant_SFG_SWR[10]), .QN(n2728) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n572), .CK(clk), .RN(n2751), .Q(
LZD_output_NRM2_EW[1]), .QN(n2735) );
DFFSX4TS R_438 ( .D(n3096), .CK(clk), .SN(n2771), .Q(n2820) );
DFFRX4TS R_214 ( .D(Raw_mant_SGF[17]), .CK(clk), .RN(n1589), .Q(n2916) );
DFFSX4TS R_164 ( .D(n2947), .CK(clk), .SN(n2766), .Q(n3059) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n872), .CK(clk), .RN(n3023),
.Q(intDY_EWSW[17]), .QN(n2674) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n569), .CK(clk), .RN(n2757), .Q(
Raw_mant_NRM_SWR[5]), .QN(n2677) );
DFFRX4TS R_208 ( .D(Raw_mant_SGF[18]), .CK(clk), .RN(n1588), .Q(n2919) );
DFFSX4TS R_360 ( .D(n3096), .CK(clk), .SN(n3006), .Q(n2869), .QN(n1536) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n915), .CK(clk), .RN(n3025), .Q(
intDX_EWSW[8]) );
DFFRX4TS R_205 ( .D(Raw_mant_SGF[20]), .CK(clk), .RN(n3015), .Q(n2925) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n930), .CK(clk), .RN(n3028), .Q(
Shift_reg_FLAGS_7_6), .QN(n2715) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n589), .CK(clk), .RN(n3008), .Q(
n1391), .QN(n2813) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n931), .CK(clk), .RN(
n3028), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2720) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n895), .CK(clk), .RN(n3027),
.Q(intDX_EWSW[28]) );
DFFRX4TS R_202 ( .D(Raw_mant_SGF[23]), .CK(clk), .RN(n2764), .Q(n2928) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n867), .CK(clk), .RN(n3024),
.Q(intDY_EWSW[22]), .QN(n2669) );
DFFRX4TS R_24 ( .D(Raw_mant_SGF[22]), .CK(clk), .RN(n2771), .Q(n2982) );
DFFSX4TS R_486 ( .D(n3000), .CK(clk), .SN(n2770), .Q(n2793) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n580), .CK(clk), .RN(n2770), .Q(
Raw_mant_NRM_SWR[10]), .QN(n2627) );
DFFRX4TS R_464 ( .D(n583), .CK(clk), .RN(n2761), .Q(DmP_mant_SFG_SWR[8]),
.QN(n2946) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n664), .CK(clk), .RN(n3033), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1593), .Q(
DMP_SFG[3]), .QN(n2996) );
DFFSX4TS R_475 ( .D(n1600), .CK(clk), .SN(n1593), .Q(n2802) );
DFFRX4TS R_476 ( .D(n3080), .CK(clk), .RN(n961), .Q(n2801) );
DFFSX4TS R_11 ( .D(n2576), .CK(clk), .SN(n3031), .Q(n2988) );
DFFRX4TS R_27 ( .D(Raw_mant_SGF[25]), .CK(clk), .RN(n3004), .Q(n2979) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n582), .CK(clk), .RN(n2761), .Q(
Raw_mant_NRM_SWR[8]), .QN(n2663) );
DFFRX4TS R_12 ( .D(Raw_mant_SGF[19]), .CK(clk), .RN(n3030), .Q(n2987) );
DFFSX4TS Ready_reg_Q_reg_0_ ( .D(n3035), .CK(clk), .SN(n1616), .QN(ready) );
DFFSRHQX4TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n612), .CK(clk), .SN(1'b1), .RN(
n1589), .Q(OP_FLAG_SHT1) );
DFFSRHQX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n605), .CK(clk), .SN(1'b1),
.RN(n3031), .Q(SIGN_FLAG_SHT1SHT2) );
DFFRHQX2TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n701), .CK(clk), .RN(n1589), .Q(
n2622) );
DFFSRHQX4TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n680), .CK(clk), .SN(1'b1), .RN(
n1616), .Q(DMP_SHT2_EWSW[29]) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n575), .CK(clk), .RN(n1616), .Q(
Raw_mant_NRM_SWR[2]) );
DFFRHQX4TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n586), .CK(clk), .RN(n1615), .Q(
n2619) );
DFFRHQX8TS R_458_IP ( .D(n610), .CK(clk), .RN(n1615), .Q(n3034) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n752), .CK(clk), .RN(n3008), .Q(
DMP_SHT2_EWSW[9]), .QN(n2699) );
DFFRX4TS R_92 ( .D(n566), .CK(clk), .RN(n2754), .Q(DmP_mant_SFG_SWR[6]),
.QN(n2665) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n601), .CK(clk), .RN(n2771), .Q(
Raw_mant_NRM_SWR[14]), .QN(n2921) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n876), .CK(clk), .RN(n3023),
.Q(intDY_EWSW[13]), .QN(n2679) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n890), .CK(clk), .RN(n3018), .Q(
left_right_SHT2), .QN(n1591) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n3028), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n2718) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n892), .CK(clk), .RN(n1588),
.Q(intDX_EWSW[31]), .QN(n2697) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n628), .CK(clk), .RN(n961), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX4TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n891), .CK(clk), .RN(n3016), .Q(
intAS) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n623), .CK(clk), .RN(n3018), .Q(
DmP_EXP_EWSW[25]), .QN(n2685) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n567), .CK(clk), .RN(n2757), .Q(
Raw_mant_NRM_SWR[7]), .QN(n2740) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n666), .CK(clk), .RN(n1593), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n858), .CK(clk), .RN(n3016),
.Q(intDY_EWSW[31]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n644), .CK(clk), .RN(n2765), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n924), .CK(clk), .RN(n3028), .Q(
Shift_reg_FLAGS_7[0]), .QN(n2723) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n828), .CK(clk), .RN(n2749), .Q(
shift_value_SHT2_EWR_4_), .QN(n2671) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n932), .CK(clk), .RN(
n3028), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2719) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n928), .CK(clk), .RN(n3028), .Q(
n3162), .QN(n2742) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n662), .CK(clk), .RN(n3015), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX4TS R_336 ( .D(DmP_mant_SHT1_SW[19]), .CK(clk), .RN(n2773), .Q(n2877)
);
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n632), .CK(clk), .RN(n960), .Q(
DmP_mant_SHT1_SW[19]) );
DFFSX4TS R_13 ( .D(n3039), .CK(clk), .SN(n3033), .Q(n2986) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n864), .CK(clk), .RN(n3024),
.Q(intDY_EWSW[25]), .QN(n2680) );
DFFRHQX4TS R_1 ( .D(n536), .CK(clk), .RN(n1589), .Q(n2618) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n646), .CK(clk), .RN(n3030), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n648), .CK(clk), .RN(n2769), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n652), .CK(clk), .RN(n2769), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n626), .CK(clk), .RN(n960), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n634), .CK(clk), .RN(n1617), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n636), .CK(clk), .RN(n3010), .Q(
DmP_mant_SHT1_SW[17]), .QN(n1413) );
DFFSX2TS R_520 ( .D(n1103), .CK(clk), .SN(n2768), .Q(n2776) );
DFFSX2TS R_330 ( .D(n1103), .CK(clk), .SN(n2760), .Q(n2879) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n650), .CK(clk), .RN(n1593), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n654), .CK(clk), .RN(n1593), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX4TS R_399 ( .D(n925), .CK(clk), .RN(n3028), .Q(n2999), .QN(n2724) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n929), .CK(clk), .RN(n3028), .Q(
Shift_reg_FLAGS_7_5), .QN(n2722) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n3015), .Q(
DMP_SHT2_EWSW[4]), .QN(n2691) );
DFFRX4TS R_93 ( .D(n766), .CK(clk), .RN(n3015), .Q(DMP_SFG[4]), .QN(n2632)
);
DFFRX4TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n736), .CK(clk), .RN(n1588), .Q(
DMP_SFG[14]), .QN(n2739) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n529), .CK(clk), .RN(n1618), .Q(
DmP_mant_SFG_SWR[20]), .QN(n2731) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n530), .CK(clk), .RN(n1618), .Q(
DmP_mant_SFG_SWR[19]), .QN(n2726) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n531), .CK(clk), .RN(n3004), .Q(
DmP_mant_SFG_SWR[18]), .QN(n2732) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n558), .CK(clk), .RN(n3004), .Q(
DmP_mant_SFG_SWR[9]), .QN(n2666) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n533), .CK(clk), .RN(n3004), .Q(
DmP_mant_SFG_SWR[16]), .QN(n2734) );
DFFSX2TS R_10 ( .D(n3111), .CK(clk), .SN(n2763), .Q(n2989) );
DFFRX4TS R_56 ( .D(n555), .CK(clk), .RN(n2757), .Q(DmP_mant_SFG_SWR[5]),
.QN(n2667) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n528), .CK(clk), .RN(n1616), .Q(
DmP_mant_SFG_SWR[21]), .QN(n2730) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n871), .CK(clk), .RN(n3023),
.Q(intDY_EWSW[18]), .QN(n2681) );
DFFSX4TS R_58 ( .D(n2975), .CK(clk), .SN(n2759), .Q(n3061), .QN(n2686) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n863), .CK(clk), .RN(n3024),
.Q(intDY_EWSW[26]), .QN(n2676) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n860), .CK(clk), .RN(n3024),
.Q(intDY_EWSW[29]), .QN(n2678) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n918), .CK(clk), .RN(n3025),
.Q(n1581) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n866), .CK(clk), .RN(n3024),
.Q(n1579) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n534), .CK(clk), .RN(n2755),
.Q(n2617) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n904), .CK(clk), .RN(n3026),
.Q(n1577) );
DFFSHQX8TS R_54 ( .D(n2995), .CK(clk), .SN(n1617), .Q(n1575) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n3013),
.Q(n1573) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n865), .CK(clk), .RN(n3024),
.Q(intDY_EWSW[24]), .QN(n2668) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n862), .CK(clk), .RN(n3024),
.Q(intDY_EWSW[27]), .QN(n2673) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n869), .CK(clk), .RN(n3023),
.Q(n1571) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n874), .CK(clk), .RN(n3023),
.Q(n1569) );
DFFRHQX8TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n748), .CK(clk), .RN(n3015), .Q(
n1567) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n887), .CK(clk), .RN(n3022),
.Q(n1564) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n886), .CK(clk), .RN(n3022),
.Q(n1562) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n898), .CK(clk), .RN(n3027),
.Q(n1561) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n912), .CK(clk), .RN(n3025),
.Q(n1560) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n879), .CK(clk), .RN(n3022),
.Q(n1557) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n861), .CK(clk), .RN(n3024),
.Q(intDY_EWSW[28]), .QN(n2670) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n751), .CK(clk), .RN(n3008), .Q(
DMP_SFG[9]), .QN(n2630) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n757), .CK(clk), .RN(n982), .Q(
DMP_SFG[7]), .QN(n2633) );
DFFRX1TS R_323 ( .D(Raw_mant_NRM_SWR[5]), .CK(clk), .RN(n1588), .Q(n2882) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n625), .CK(clk), .RN(n3018), .Q(
DmP_EXP_EWSW[23]), .QN(n2721) );
DFFRHQX4TS R_35 ( .D(n610), .CK(clk), .RN(n1588), .Q(n1553) );
DFFSX4TS R_485 ( .D(n3097), .CK(clk), .SN(n2770), .Q(n2794) );
DFFSX4TS R_400 ( .D(n2849), .CK(clk), .SN(n1589), .Q(n2992), .QN(n2747) );
DFFSX2TS R_272 ( .D(n3105), .CK(clk), .SN(n2766), .Q(n2893) );
DFFSX2TS R_91 ( .D(n3090), .CK(clk), .SN(n2756), .Q(n1375) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_17_ ( .D(n637), .CK(clk), .RN(n3012), .Q(
n1539) );
DFFRX4TS R_265 ( .D(DmP_mant_SHT1_SW[3]), .CK(clk), .RN(n1615), .QN(n1537)
);
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n3023),
.Q(n1534) );
DFFSX1TS R_98 ( .D(n3094), .CK(clk), .SN(n3161), .Q(n2963) );
DFFRX4TS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n604), .CK(clk), .RN(n3002), .Q(
final_result_ieee[31]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n742), .CK(clk), .RN(n3014), .Q(
DMP_SFG[12]), .QN(n2695) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n888), .CK(clk), .RN(n3021),
.Q(n1388) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n906), .CK(clk), .RN(n3026),
.Q(n1386) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n896), .CK(clk), .RN(n3027),
.Q(n1382) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n859), .CK(clk), .RN(n3027),
.Q(n1378) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n877), .CK(clk), .RN(n3023),
.Q(n1376) );
DFFSX4TS R_176 ( .D(n3124), .CK(clk), .SN(n2752), .Q(n2941) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n920), .CK(clk), .RN(n3025),
.Q(n1372) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n922), .CK(clk), .RN(n3024),
.Q(n1371) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n901), .CK(clk), .RN(n3027),
.Q(n1369) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n883), .CK(clk), .RN(n3022),
.Q(n1367) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n897), .CK(clk), .RN(n3027),
.Q(n1364) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n910), .CK(clk), .RN(n3026),
.Q(n1362) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n916), .CK(clk), .RN(n3025),
.Q(n1360) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n900), .CK(clk), .RN(n3027),
.Q(n1357) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_0_ ( .D(n814), .CK(clk), .RN(n3016), .Q(
DMP_EXP_EWSW[0]) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n3160), .CK(clk), .RN(n1589),
.Q(n1349) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n917), .CK(clk), .RN(n3025),
.Q(n1348) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n884), .CK(clk), .RN(n3022),
.Q(n1346) );
DFFRHQX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n830), .CK(clk), .RN(n2754),
.Q(n1343) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n881), .CK(clk), .RN(n3022),
.Q(n1341) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n902), .CK(clk), .RN(n3026),
.Q(n1331) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n894), .CK(clk), .RN(n3027),
.Q(n1330) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n889), .CK(clk), .RN(n3021),
.Q(n1328) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n907), .CK(clk), .RN(n3026),
.Q(n1327) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n885), .CK(clk), .RN(n3022),
.Q(n1325) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n868), .CK(clk), .RN(n3023),
.Q(n1322) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n875), .CK(clk), .RN(n3023),
.Q(n1320) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n908), .CK(clk), .RN(n3026),
.Q(n1317) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n781), .CK(clk), .RN(n3002), .Q(
SIGN_FLAG_EXP) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n806), .CK(clk), .RN(n3015), .Q(
DMP_EXP_EWSW[8]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n810), .CK(clk), .RN(n3004), .Q(
DMP_EXP_EWSW[4]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_6_ ( .D(n659), .CK(clk), .RN(n2761), .Q(
DmP_EXP_EWSW[6]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n785), .CK(clk), .RN(n3021), .Q(
DMP_EXP_EWSW[29]) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_5_ ( .D(n661), .CK(clk), .RN(n3004), .Q(n1309) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n813), .CK(clk), .RN(n3016), .Q(n1308) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_13_ ( .D(n801), .CK(clk), .RN(n2773), .Q(
n1306) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_7_ ( .D(n807), .CK(clk), .RN(n964), .Q(n1305)
);
DFFRX4TS EXP_STAGE_DmP_Q_reg_13_ ( .D(n645), .CK(clk), .RN(n2765), .Q(
DmP_EXP_EWSW[13]) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n911), .CK(clk), .RN(n3026),
.Q(n1298) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n921), .CK(clk), .RN(n3025),
.Q(n1296) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n913), .CK(clk), .RN(n3025),
.Q(n1294) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n568), .CK(clk), .RN(n2754), .Q(
Raw_mant_NRM_SWR[6]), .QN(n2675) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n665), .CK(clk), .RN(n3033), .Q(
DmP_EXP_EWSW[3]) );
DFFSX2TS R_406 ( .D(n3076), .CK(clk), .SN(n2760), .Q(n2845) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n923), .CK(clk), .RN(n3024),
.Q(n1286) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n899), .CK(clk), .RN(n3027),
.Q(n1284) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n919), .CK(clk), .RN(n3025),
.Q(n1278) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n880), .CK(clk), .RN(n3022),
.Q(n1277) );
DFFRX4TS R_224 ( .D(n3069), .CK(clk), .RN(n2762), .Q(n2910) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n905), .CK(clk), .RN(n3026),
.Q(n1273) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n579), .CK(clk), .RN(n2751),
.Q(n1266) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n873), .CK(clk), .RN(n3023),
.Q(n1264) );
DFFSX4TS R_233 ( .D(n852), .CK(clk), .SN(n1594), .Q(n934) );
DFFSX2TS R_381 ( .D(n1066), .CK(clk), .SN(n2764), .Q(n2859) );
DFFSX2TS R_223 ( .D(n1066), .CK(clk), .SN(n2763), .Q(n2911) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_21_ ( .D(n629), .CK(clk), .RN(n960), .Q(
DmP_EXP_EWSW[21]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n621), .CK(clk), .RN(n3018), .Q(
DmP_EXP_EWSW[27]) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n909), .CK(clk), .RN(n3026),
.Q(n1253) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n903), .CK(clk), .RN(n3026),
.Q(n1251) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n600), .CK(clk), .RN(n2761),
.Q(n1249) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n914), .CK(clk), .RN(n3025),
.Q(n1297) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n602), .CK(clk), .RN(n3015),
.Q(n1243) );
DFFRX2TS R_534 ( .D(n1241), .CK(clk), .RN(n960), .Q(n1655) );
DFFSX4TS R_537 ( .D(n2006), .CK(clk), .SN(n964), .Q(n1238) );
DFFSX2TS R_538 ( .D(n2013), .CK(clk), .SN(n963), .Q(n1237) );
DFFSX2TS R_539 ( .D(n2014), .CK(clk), .SN(n963), .Q(n1236) );
DFFSX2TS R_540 ( .D(n2012), .CK(clk), .SN(n964), .Q(n1235) );
DFFSX2TS R_541 ( .D(n2070), .CK(clk), .SN(n963), .Q(n1234) );
DFFSX2TS R_542 ( .D(n2069), .CK(clk), .SN(n963), .Q(n1233) );
DFFSX4TS R_546 ( .D(n2009), .CK(clk), .SN(n958), .Q(n1229) );
DFFSX2TS R_544 ( .D(n2011), .CK(clk), .SN(n958), .Q(n1231) );
DFFSX2TS R_548 ( .D(n1607), .CK(clk), .SN(n2748), .Q(n1227) );
DFFSX2TS R_549 ( .D(n1607), .CK(clk), .SN(n2749), .Q(n1226) );
DFFSX2TS R_550 ( .D(n985), .CK(clk), .SN(n1596), .Q(n1225) );
DFFSX2TS R_551 ( .D(n1607), .CK(clk), .SN(n2752), .Q(n1224) );
DFFSX2TS R_552 ( .D(n985), .CK(clk), .SN(n3003), .Q(n1223) );
DFFSX4TS R_554 ( .D(n1538), .CK(clk), .SN(n2771), .Q(n1222), .QN(n936) );
DFFRXLTS R_228 ( .D(n3088), .CK(clk), .RN(n2754), .Q(n2907) );
DFFRX4TS R_557 ( .D(n1814), .CK(clk), .RN(n2767), .Q(n1221) );
DFFSX4TS R_558 ( .D(n1263), .CK(clk), .SN(n3161), .Q(n1220) );
DFFRX4TS R_559 ( .D(n1611), .CK(clk), .RN(n2755), .Q(n1219) );
DFFRX4TS R_561 ( .D(n1610), .CK(clk), .RN(n2757), .Q(n1218) );
DFFSX4TS R_562 ( .D(n981), .CK(clk), .SN(n1601), .Q(n1217) );
DFFSX2TS R_564 ( .D(n981), .CK(clk), .SN(n2763), .Q(n1216), .QN(n1215) );
DFFRX2TS R_461 ( .D(n1243), .CK(clk), .RN(n2766), .Q(n2810) );
DFFSX1TS R_158 ( .D(n3053), .CK(clk), .SN(n2766), .Q(n2949) );
DFFSX2TS R_566 ( .D(n2994), .CK(clk), .SN(n2764), .Q(n1214) );
DFFSX2TS R_567 ( .D(n2677), .CK(clk), .SN(n2756), .Q(n1213) );
DFFSX4TS R_568 ( .D(n3154), .CK(clk), .SN(n3161), .Q(n1212) );
DFFSX2TS R_571 ( .D(n2740), .CK(clk), .SN(n2766), .Q(n1208) );
DFFRX2TS R_574 ( .D(DmP_mant_SHT1_SW[20]), .CK(clk), .RN(n2773), .Q(n1204),
.QN(n1203) );
DFFSX2TS R_576 ( .D(DmP_mant_SHT1_SW[16]), .CK(clk), .SN(n2767), .Q(n1201),
.QN(n1200) );
DFFRX4TS R_579 ( .D(DmP_mant_SHT1_SW[22]), .CK(clk), .RN(n2770), .Q(n1197)
);
DFFSX2TS R_583 ( .D(n1598), .CK(clk), .SN(n2759), .Q(n1193) );
DFFSX4TS R_584 ( .D(n1464), .CK(clk), .SN(n3161), .Q(n1192) );
DFFRX2TS R_586 ( .D(n1345), .CK(clk), .RN(n1588), .Q(n1190), .QN(n1189) );
DFFSX4TS R_588 ( .D(n2675), .CK(clk), .SN(n2768), .Q(n1187) );
DFFSX1TS R_271 ( .D(n2914), .CK(clk), .SN(n3010), .Q(n2894) );
DFFRX2TS R_578 ( .D(DmP_mant_SHT1_SW[12]), .CK(clk), .RN(n2769), .Q(n1198)
);
DFFRX2TS R_581 ( .D(DmP_mant_SHT1_SW[10]), .CK(clk), .RN(n2767), .Q(n1195)
);
DFFSX1TS R_349 ( .D(n2997), .CK(clk), .SN(n1601), .Q(n2872) );
DFFRX2TS R_573 ( .D(DmP_mant_SHT1_SW[7]), .CK(clk), .RN(n1601), .Q(n1205) );
DFFRX2TS R_582 ( .D(DmP_mant_SHT1_SW[8]), .CK(clk), .RN(n2762), .Q(n1194) );
DFFRX2TS R_575 ( .D(DmP_mant_SHT1_SW[16]), .CK(clk), .RN(n2762), .Q(n1202)
);
DFFRX1TS R_319 ( .D(Raw_mant_NRM_SWR[3]), .CK(clk), .RN(n2755), .Q(n2883) );
DFFSX4TS R_335 ( .D(n2997), .CK(clk), .SN(n1601), .Q(n2878) );
DFFSX2TS R_591 ( .D(n1250), .CK(clk), .SN(n2763), .Q(n1183) );
DFFRX2TS R_592 ( .D(n1249), .CK(clk), .RN(n2754), .Q(n1182) );
DFFSX2TS R_593 ( .D(n1244), .CK(clk), .SN(n3009), .Q(n1181) );
DFFRXLTS R_499 ( .D(Raw_mant_NRM_SWR[16]), .CK(clk), .RN(n2754), .Q(n2786)
);
DFFSX2TS R_408 ( .D(n2923), .CK(clk), .SN(n2759), .Q(n2843) );
DFFRHQX4TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n537), .CK(clk), .RN(n2754),
.Q(n2616) );
DFFSX4TS R_585 ( .D(n3104), .CK(clk), .SN(n2764), .Q(n1191) );
DFFRHQX4TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n745), .CK(clk), .RN(n3014), .Q(
n1584) );
DFFRX2TS R_511 ( .D(n1599), .CK(clk), .RN(n3031), .QN(n1381) );
DFFRHQX4TS R_94 ( .D(n547), .CK(clk), .RN(n2761), .Q(n1542) );
DFFSX4TS R_577 ( .D(n1612), .CK(clk), .SN(n3012), .Q(n1199) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n775), .CK(clk), .RN(n3016), .Q(
DMP_SFG[1]), .QN(n2812) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n786), .CK(clk), .RN(n3020), .Q(
n1350) );
DFFSX4TS R_543 ( .D(n2068), .CK(clk), .SN(n3029), .Q(n1232) );
DFFSX4TS R_457 ( .D(n1608), .CK(clk), .SN(n1594), .Q(n2814) );
DFFSX2TS R_96 ( .D(n2964), .CK(clk), .SN(n3009), .Q(n3091) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n3159), .CK(clk), .RN(n3031),
.Q(n1299) );
DFFSX4TS R_433 ( .D(n3108), .CK(clk), .SN(n3029), .Q(n2823), .QN(n1602) );
DFFRX4TS R_587 ( .D(n1600), .CK(clk), .RN(n2755), .Q(n1188) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n826), .CK(clk), .RN(n3004),
.QN(n2727) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_20_ ( .D(n631), .CK(clk), .RN(n2755), .Q(
n1276) );
DFFSX2TS R_545 ( .D(n2010), .CK(clk), .SN(n958), .Q(n1230) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n784), .CK(clk), .RN(n3021), .Q(
DMP_EXP_EWSW[30]) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n878), .CK(clk), .RN(n3022),
.Q(n953) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n882), .CK(clk), .RN(n3022),
.Q(n951) );
DFFSX2TS R_293_RW_0 ( .D(DmP_mant_SHT1_SW[17]), .CK(clk), .SN(n2773), .Q(
n2888) );
DFFSX2TS R_471 ( .D(n1345), .CK(clk), .SN(n2749), .Q(n2805) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n730), .CK(clk), .RN(n3005), .Q(
DMP_SFG[16]), .QN(n2713) );
DFFRX4TS R_580 ( .D(DmP_mant_SHT1_SW[18]), .CK(clk), .RN(n2755), .Q(n1196)
);
DFFSX2TS R_305_RW_0 ( .D(DmP_mant_SHT1_SW[21]), .CK(clk), .SN(n1597), .QN(
n1665) );
DFFRX4TS R_572 ( .D(DmP_mant_SHT1_SW[14]), .CK(clk), .RN(n2765), .Q(n1207),
.QN(n1206) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n893), .CK(clk), .RN(n3027),
.Q(n1578) );
DFFRHQX4TS R_459 ( .D(n610), .CK(clk), .RN(n1617), .Q(n1549) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n526), .CK(clk), .RN(n1615), .Q(
DmP_mant_SFG_SWR[23]), .QN(n2729) );
DFFRHQX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n707), .CK(clk), .RN(n958), .Q(
n1283) );
DFFRHQX4TS R_465 ( .D(n2976), .CK(clk), .RN(n1617), .Q(n1566) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n603), .CK(clk), .RN(n3030),
.Q(n1582) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n702), .CK(clk), .RN(n958), .Q(
n1270) );
DFFSHQX2TS R_466 ( .D(n2808), .CK(clk), .SN(n1618), .Q(n3060) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n715), .CK(clk), .RN(n1588), .Q(
DMP_SFG[21]), .QN(n2736) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n587), .CK(clk), .RN(n2758),
.Q(n1301) );
DFFRX2TS R_163 ( .D(n760), .CK(clk), .RN(n2765), .QN(n2662) );
DFFRHQX4TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n831), .CK(clk), .RN(n2757),
.Q(n1547) );
DFFSX4TS R_590 ( .D(n1263), .CK(clk), .SN(n3006), .Q(n1184), .QN(n935) );
DFFRX2TS R_346 ( .D(DmP_mant_SHT1_SW[9]), .CK(clk), .RN(n2759), .Q(n2873) );
DFFSX2TS R_477 ( .D(n1854), .CK(clk), .SN(n3031), .Q(n2800) );
DFFSX2TS R_570 ( .D(n2998), .CK(clk), .SN(n2766), .Q(n1210), .QN(n1209) );
DFFSX2TS R_309_RW_0 ( .D(DmP_mant_SHT1_SW[9]), .CK(clk), .SN(n1601), .Q(
n2886) );
DFFSX1TS R_248_RW_0 ( .D(DmP_mant_SHT1_SW[11]), .CK(clk), .SN(n2773), .Q(
n2899) );
DFFSX1TS R_61 ( .D(n3068), .CK(clk), .SN(n2759), .Q(n2974) );
DFFRX1TS R_261 ( .D(n2997), .CK(clk), .RN(n2757), .Q(n2896) );
DFFRX1TS R_273 ( .D(n1066), .CK(clk), .RN(n2765), .Q(n2892) );
DFFRX2TS R_472 ( .D(n1573), .CK(clk), .RN(n2770), .Q(n2804) );
DFFRHQX4TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n525), .CK(clk), .RN(n1615),
.Q(n1333) );
DFFSX2TS R_232_RW_0 ( .D(DmP_mant_SHT1_SW[20]), .CK(clk), .SN(n2771), .Q(
n2906) );
DFFRHQX2TS R_2 ( .D(n2991), .CK(clk), .RN(n3033), .Q(n1303) );
DFFSX1TS R_226_RW_0 ( .D(DmP_mant_SHT1_SW[7]), .CK(clk), .SN(n2773), .Q(
n2909) );
DFFSX1TS R_414 ( .D(n3099), .CK(clk), .SN(n3006), .Q(n2839) );
DFFSX2TS R_230_RW_0 ( .D(n1613), .CK(clk), .SN(n2771), .QN(n1663) );
DFFSX1TS R_227 ( .D(n1066), .CK(clk), .SN(n3009), .Q(n2908) );
DFFRHQX4TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n535), .CK(clk), .RN(n2754),
.Q(n1545) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n672), .CK(clk), .RN(n1616),
.Q(DMP_exp_NRM2_EW[7]) );
DFFRX2TS R_329 ( .D(DmP_mant_SHT1_SW[11]), .CK(clk), .RN(n2761), .Q(n2880)
);
DFFSX1TS R_235 ( .D(n1066), .CK(clk), .SN(n3161), .Q(n2905) );
DFFSX2TS R_252 ( .D(n3085), .CK(clk), .SN(n2763), .Q(n2898) );
DFFSX2TS R_536 ( .D(n2007), .CK(clk), .SN(n964), .Q(n1239) );
DFFSX2TS R_535 ( .D(n2008), .CK(clk), .SN(n964), .Q(n1240) );
DFFRX1TS R_285 ( .D(DmP_mant_SHT1_SW[4]), .CK(clk), .RN(n1615), .Q(n2890) );
DFFSX1TS R_239 ( .D(n1066), .CK(clk), .SN(n3161), .Q(n2902) );
DFFSX4TS R_547 ( .D(n985), .CK(clk), .SN(n2768), .QN(n933) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n660), .CK(clk), .SN(1'b1),
.RN(n1615), .Q(DmP_mant_SHT1_SW[5]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n670), .CK(clk), .RN(n1618), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n524), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[25]), .QN(n2701) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_21_ ( .D(n793), .CK(clk), .RN(n3008), .Q(
n1307) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_2_ ( .D(n812), .CK(clk), .RN(n1618), .Q(
DMP_EXP_EWSW[2]) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_9_ ( .D(n653), .CK(clk), .RN(n1593), .Q(n1313) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n578), .CK(clk), .RN(n3012), .QN(
n2660) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n630), .CK(clk), .RN(n2749), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n614), .CK(clk), .RN(n2749), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFSRHQX2TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n711), .CK(clk), .SN(1'b1), .RN(
n1618), .Q(DMP_SHT1_EWSW[23]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n638), .CK(clk), .RN(n2770), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n656), .CK(clk), .RN(n1593), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n642), .CK(clk), .RN(n2769), .Q(
DmP_mant_SHT1_SW[14]) );
CLKMX2X2TS U940 ( .A(DmP_mant_SHT1_SW[9]), .B(n1313), .S0(n2590), .Y(n652)
);
NAND2X4TS U941 ( .A(n3095), .B(n1599), .Y(n3083) );
CLKINVX2TS U942 ( .A(n956), .Y(n957) );
BUFX8TS U943 ( .A(n1814), .Y(n1263) );
CLKMX2X4TS U944 ( .A(Raw_mant_SGF[12]), .B(n1582), .S0(n2566), .Y(n603) );
CLKINVX2TS U945 ( .A(n959), .Y(n960) );
CLKINVX3TS U946 ( .A(n962), .Y(n963) );
MXI2X1TS U947 ( .A(n2602), .B(n2723), .S0(n2604), .Y(n924) );
INVX2TS U948 ( .A(n962), .Y(n964) );
CLKMX2X3TS U949 ( .A(Data_Y[9]), .B(n1277), .S0(n2595), .Y(n880) );
NAND3X2TS U950 ( .A(n2443), .B(n2442), .C(n2441), .Y(n3105) );
NAND2X4TS U951 ( .A(n1599), .B(n1544), .Y(n3108) );
BUFX3TS U952 ( .A(n3009), .Y(n2754) );
CLKINVX2TS U953 ( .A(n956), .Y(n958) );
INVX2TS U954 ( .A(n959), .Y(n961) );
MX2X4TS U955 ( .A(n2540), .B(LZD_output_NRM2_EW[3]), .S0(n2724), .Y(n573) );
AOI2BB2X2TS U956 ( .B0(n1787), .B1(n1154), .A0N(n1153), .A1N(n1152), .Y(
n3068) );
OAI22X1TS U957 ( .A0(n2326), .A1(n2308), .B0(Shift_reg_FLAGS_7_6), .B1(n2684), .Y(n782) );
NAND2X6TS U958 ( .A(n2997), .B(DmP_mant_SHT1_SW[20]), .Y(n3098) );
NAND3X4TS U959 ( .A(n2181), .B(n2180), .C(n2179), .Y(n798) );
NAND3X2TS U960 ( .A(n2126), .B(n2125), .C(n2124), .Y(n649) );
AND2X4TS U961 ( .A(n1362), .B(n1533), .Y(n1291) );
NAND2X1TS U962 ( .A(n2328), .B(n1386), .Y(n2122) );
NAND2X2TS U963 ( .A(n2155), .B(n1317), .Y(n2107) );
NAND2X1TS U964 ( .A(n2608), .B(n1350), .Y(n2022) );
NAND2X1TS U965 ( .A(n2170), .B(DMP_EXP_EWSW[0]), .Y(n2016) );
NAND2XLTS U966 ( .A(n2724), .B(LZD_output_NRM2_EW[2]), .Y(n1478) );
NAND2XLTS U967 ( .A(n3000), .B(n1020), .Y(n1019) );
NAND2X2TS U968 ( .A(n2606), .B(n1278), .Y(n2128) );
NAND2X2TS U969 ( .A(n2606), .B(n1320), .Y(n2184) );
NAND2XLTS U970 ( .A(n2156), .B(DMP_EXP_EWSW[2]), .Y(n2027) );
NAND2XLTS U971 ( .A(n2166), .B(n1313), .Y(n2151) );
NAND2XLTS U972 ( .A(n2166), .B(DmP_EXP_EWSW[11]), .Y(n2124) );
NAND2XLTS U973 ( .A(n2601), .B(n989), .Y(n1065) );
NAND2XLTS U974 ( .A(n2539), .B(n1027), .Y(n1026) );
NAND2X2TS U975 ( .A(n2606), .B(intDY_EWSW[17]), .Y(n2193) );
NAND2XLTS U976 ( .A(n2161), .B(DMP_EXP_EWSW[11]), .Y(n2039) );
NAND2XLTS U977 ( .A(n2170), .B(DMP_EXP_EWSW[29]), .Y(n2024) );
NAND2XLTS U978 ( .A(n2170), .B(DMP_EXP_EWSW[8]), .Y(n2042) );
NAND2XLTS U979 ( .A(n2170), .B(n1308), .Y(n2171) );
NAND2XLTS U980 ( .A(n2170), .B(n1305), .Y(n2052) );
NAND2XLTS U981 ( .A(n2161), .B(n1276), .Y(n2142) );
NAND2XLTS U982 ( .A(n2156), .B(DmP_EXP_EWSW[21]), .Y(n2148) );
CLKINVX6TS U983 ( .A(n1856), .Y(n1002) );
CLKINVX1TS U984 ( .A(n1132), .Y(n1152) );
MXI2X2TS U985 ( .A(n2540), .B(n1734), .S0(n2602), .Y(n1735) );
CLKAND2X2TS U986 ( .A(n1660), .B(n2262), .Y(n2263) );
NAND2X2TS U987 ( .A(n2606), .B(n1346), .Y(n2037) );
NAND2XLTS U988 ( .A(n2166), .B(DmP_EXP_EWSW[18]), .Y(n2115) );
NAND2XLTS U989 ( .A(n2166), .B(DmP_EXP_EWSW[10]), .Y(n2136) );
NAND2XLTS U990 ( .A(n2166), .B(DMP_EXP_EWSW[5]), .Y(n2036) );
NAND2XLTS U991 ( .A(n2156), .B(DMP_EXP_EWSW[4]), .Y(n2030) );
NAND2XLTS U992 ( .A(n2166), .B(n1539), .Y(n2121) );
NAND2XLTS U993 ( .A(n2156), .B(n1309), .Y(n2118) );
CLKAND2X2TS U994 ( .A(n973), .B(n2294), .Y(n2295) );
CLKAND2X2TS U995 ( .A(n2280), .B(n2292), .Y(n2281) );
NAND2X2TS U996 ( .A(n2203), .B(n1277), .Y(n2058) );
CLKAND2X2TS U997 ( .A(n2271), .B(n2270), .Y(n2272) );
MXI2X2TS U998 ( .A(n2691), .B(n2632), .S0(n3001), .Y(n766) );
CLKAND2X2TS U999 ( .A(n2277), .B(n2276), .Y(n2278) );
CLKAND2X2TS U1000 ( .A(n991), .B(n2287), .Y(n2289) );
NAND2X4TS U1001 ( .A(n1003), .B(n2546), .Y(n2547) );
NAND2X4TS U1002 ( .A(n1005), .B(n2454), .Y(n1407) );
NAND2X2TS U1003 ( .A(n1916), .B(n1915), .Y(n2308) );
NAND2X2TS U1004 ( .A(n2338), .B(Raw_mant_NRM_SWR[10]), .Y(n1693) );
MXI2X2TS U1005 ( .A(n2694), .B(n2634), .S0(n3000), .Y(n763) );
AOI22X1TS U1006 ( .A0(n2424), .A1(n2602), .B0(n1611), .B1(n2506), .Y(n2425)
);
NAND2BX1TS U1007 ( .AN(n985), .B(final_result_ieee[31]), .Y(n1466) );
NOR2X4TS U1008 ( .A(n1093), .B(n1042), .Y(n1787) );
CLKINVX1TS U1009 ( .A(n772), .Y(n2631) );
NAND2X2TS U1010 ( .A(n2155), .B(n987), .Y(n2153) );
AOI22X1TS U1011 ( .A0(n2545), .A1(DmP_mant_SHT1_SW[5]), .B0(n3080), .B1(
DmP_mant_SHT1_SW[4]), .Y(n2414) );
INVX2TS U1012 ( .A(n3018), .Y(n962) );
INVX2TS U1013 ( .A(n2772), .Y(n959) );
INVX2TS U1014 ( .A(n3017), .Y(n956) );
NOR2X2TS U1015 ( .A(n1652), .B(n1413), .Y(n1513) );
NAND2X1TS U1016 ( .A(n2545), .B(n1612), .Y(n2441) );
NOR2X1TS U1017 ( .A(n2742), .B(n2423), .Y(n2424) );
BUFX16TS U1018 ( .A(n2056), .Y(n2328) );
INVX6TS U1019 ( .A(n1289), .Y(n2442) );
AND2X4TS U1020 ( .A(n2527), .B(n1591), .Y(n2347) );
BUFX6TS U1021 ( .A(n2111), .Y(n2166) );
INVX2TS U1022 ( .A(n2701), .Y(n1020) );
NAND2X2TS U1023 ( .A(n2537), .B(n1592), .Y(n2505) );
CLKBUFX2TS U1024 ( .A(n2665), .Y(n992) );
CLKAND2X2TS U1025 ( .A(n1849), .B(n1791), .Y(n1304) );
CLKAND2X2TS U1026 ( .A(n2492), .B(n2491), .Y(n1256) );
CLKBUFX2TS U1027 ( .A(n3032), .Y(n3017) );
CLKBUFX2TS U1028 ( .A(n3012), .Y(n2772) );
INVX2TS U1029 ( .A(n1012), .Y(n1027) );
INVX4TS U1030 ( .A(n933), .Y(n966) );
MXI2X2TS U1031 ( .A(n2692), .B(n1242), .S0(n2581), .Y(n772) );
AOI22X1TS U1032 ( .A0(n2516), .A1(n844), .B0(n2525), .B1(n2508), .Y(n2397)
);
BUFX3TS U1033 ( .A(n2517), .Y(n1023) );
NAND2X6TS U1034 ( .A(n1315), .B(n1635), .Y(n1634) );
AOI21X2TS U1035 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n2724), .B0(n2545), .Y(
n2447) );
NAND2X6TS U1036 ( .A(n1506), .B(n988), .Y(n1522) );
CLKBUFX3TS U1037 ( .A(n2760), .Y(n3009) );
BUFX4TS U1038 ( .A(n1792), .Y(n1423) );
AOI22X1TS U1039 ( .A0(n2545), .A1(DmP_mant_SHT1_SW[19]), .B0(n3080), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1771) );
AOI22X1TS U1040 ( .A0(n2545), .A1(DmP_mant_SHT1_SW[9]), .B0(n3080), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2544) );
AOI21X2TS U1041 ( .A0(n2274), .A1(n2265), .B0(n2267), .Y(n1444) );
XNOR2X2TS U1042 ( .A(n789), .B(DmP_EXP_EWSW[25]), .Y(n2462) );
NAND2X4TS U1043 ( .A(n1658), .B(n2495), .Y(n1657) );
INVX2TS U1044 ( .A(n944), .Y(n943) );
INVX2TS U1045 ( .A(n2266), .Y(n2287) );
CLKINVX1TS U1046 ( .A(n1385), .Y(n945) );
NOR2X1TS U1047 ( .A(n2327), .B(intDX_EWSW[31]), .Y(n1914) );
NAND2X1TS U1048 ( .A(n2499), .B(n2377), .Y(n2378) );
NOR2X1TS U1049 ( .A(n2718), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2324) );
OR2X6TS U1050 ( .A(n2523), .B(n2671), .Y(n1869) );
NOR2X6TS U1051 ( .A(n1112), .B(n1661), .Y(n1289) );
INVX2TS U1052 ( .A(n1042), .Y(n989) );
AND2X2TS U1053 ( .A(n1441), .B(n2262), .Y(n1392) );
INVX8TS U1054 ( .A(n2576), .Y(n2566) );
NOR2X2TS U1055 ( .A(n1385), .B(n1049), .Y(n944) );
NAND2X4TS U1056 ( .A(n1432), .B(n2496), .Y(n1658) );
INVX3TS U1057 ( .A(n2421), .Y(n1458) );
CLKXOR2X2TS U1058 ( .A(n1390), .B(n2630), .Y(n1790) );
BUFX8TS U1059 ( .A(n1856), .Y(n1465) );
INVX12TS U1060 ( .A(n1505), .Y(n1058) );
NOR2X2TS U1061 ( .A(n1908), .B(n1907), .Y(n1909) );
INVX2TS U1062 ( .A(n3080), .Y(n1817) );
INVX2TS U1063 ( .A(n1582), .Y(n1583) );
INVX4TS U1064 ( .A(n2581), .Y(n1385) );
BUFX16TS U1065 ( .A(n1559), .Y(n1093) );
BUFX8TS U1066 ( .A(n2364), .Y(n2525) );
BUFX6TS U1067 ( .A(n2111), .Y(n2156) );
INVX2TS U1068 ( .A(n1606), .Y(n1025) );
AOI22X2TS U1069 ( .A0(n2902), .A1(n2901), .B0(n986), .B1(n2900), .Y(n1737)
);
INVX2TS U1070 ( .A(n2510), .Y(n3071) );
BUFX6TS U1071 ( .A(n1462), .Y(n1275) );
INVX2TS U1072 ( .A(n2497), .Y(n980) );
CLKBUFX2TS U1073 ( .A(n2946), .Y(n1049) );
AND2X2TS U1074 ( .A(n2984), .B(n1800), .Y(n1808) );
NOR2X4TS U1075 ( .A(n2506), .B(left_right_SHT2), .Y(n2503) );
NAND2X2TS U1076 ( .A(n839), .B(n983), .Y(n1071) );
INVX8TS U1077 ( .A(n1637), .Y(n1314) );
NAND2X2TS U1078 ( .A(n2534), .B(n1074), .Y(n1073) );
NAND2BX2TS U1079 ( .AN(n2411), .B(n983), .Y(n1168) );
CLKINVX6TS U1080 ( .A(n2319), .Y(n1080) );
INVX8TS U1081 ( .A(n1432), .Y(n1637) );
NOR2X6TS U1082 ( .A(Shift_amount_SHT1_EWR[0]), .B(n2437), .Y(n3080) );
CLKINVX6TS U1083 ( .A(n2536), .Y(n983) );
NAND2X2TS U1084 ( .A(n2466), .B(n1351), .Y(n1716) );
XNOR2X1TS U1085 ( .A(n1557), .B(n1294), .Y(n1884) );
XNOR2X1TS U1086 ( .A(n1320), .B(n1253), .Y(n1890) );
XNOR2X1TS U1087 ( .A(n1579), .B(n1357), .Y(n1886) );
NAND2X6TS U1088 ( .A(n2465), .B(n1132), .Y(n1708) );
XNOR2X2TS U1089 ( .A(n1367), .B(n1348), .Y(n1901) );
XNOR2X2TS U1090 ( .A(n1264), .B(n1327), .Y(n1899) );
NAND2X2TS U1091 ( .A(n1604), .B(n2579), .Y(n1709) );
NAND2X2TS U1092 ( .A(n2496), .B(n2495), .Y(n2497) );
INVX8TS U1093 ( .A(n1044), .Y(n2565) );
NOR2X1TS U1094 ( .A(n2102), .B(DMP_exp_NRM2_EW[7]), .Y(n2101) );
INVX3TS U1095 ( .A(n1828), .Y(n1830) );
INVX2TS U1096 ( .A(n1473), .Y(n1108) );
NAND2X4TS U1097 ( .A(n2509), .B(n846), .Y(n1126) );
XNOR2X1TS U1098 ( .A(n1388), .B(n1371), .Y(n1871) );
XNOR2X1TS U1099 ( .A(n1325), .B(n1278), .Y(n1893) );
INVX2TS U1100 ( .A(n1691), .Y(n2334) );
AND2X6TS U1101 ( .A(n1076), .B(n1079), .Y(n979) );
BUFX4TS U1102 ( .A(n1476), .Y(n1356) );
INVX2TS U1103 ( .A(n2494), .Y(n2496) );
NAND2X4TS U1104 ( .A(n2365), .B(n2401), .Y(n1825) );
CLKINVX6TS U1105 ( .A(n852), .Y(n1859) );
NAND2BX1TS U1106 ( .AN(n1582), .B(n1727), .Y(n1483) );
CLKINVX6TS U1107 ( .A(n3103), .Y(n1351) );
INVX8TS U1108 ( .A(n1099), .Y(n1095) );
NAND2X2TS U1109 ( .A(n2261), .B(DMP_SFG[22]), .Y(n2495) );
XOR2X1TS U1110 ( .A(n1282), .B(n1383), .Y(n1353) );
XOR2X1TS U1111 ( .A(n1572), .B(n1252), .Y(n1335) );
INVX2TS U1112 ( .A(n1829), .Y(n1091) );
NAND2X6TS U1113 ( .A(n1488), .B(n1405), .Y(n1094) );
CLKINVX6TS U1114 ( .A(n1008), .Y(n1757) );
INVX8TS U1115 ( .A(n1710), .Y(n2465) );
AND2X4TS U1116 ( .A(n1811), .B(n1810), .Y(n1474) );
INVX2TS U1117 ( .A(n3104), .Y(n1507) );
INVX1TS U1118 ( .A(n2608), .Y(n1068) );
OA22X2TS U1119 ( .A0(n1536), .A1(n1537), .B0(n1862), .B1(n2895), .Y(n1815)
);
NAND2X1TS U1120 ( .A(n2089), .B(n2088), .Y(n2091) );
INVX8TS U1121 ( .A(n1715), .Y(n2509) );
INVX2TS U1122 ( .A(n2519), .Y(n3103) );
INVX12TS U1123 ( .A(n1710), .Y(n2511) );
INVX6TS U1124 ( .A(n1434), .Y(n1433) );
INVX6TS U1125 ( .A(n1700), .Y(n2512) );
BUFX8TS U1126 ( .A(n1521), .Y(n1460) );
NAND2X4TS U1127 ( .A(n2260), .B(n2274), .Y(n1638) );
NAND2X4TS U1128 ( .A(n977), .B(n1605), .Y(n1076) );
INVX4TS U1129 ( .A(Shift_reg_FLAGS_7[0]), .Y(n2079) );
INVX3TS U1130 ( .A(n2483), .Y(n2485) );
NOR2X4TS U1131 ( .A(n1591), .B(n2506), .Y(n2531) );
AOI2BB2X2TS U1132 ( .B0(n1043), .B1(n1194), .A0N(n1603), .A1N(n1214), .Y(
n1739) );
NAND2X6TS U1133 ( .A(n1488), .B(n1405), .Y(n1358) );
INVX4TS U1134 ( .A(n1831), .Y(n2211) );
NOR2X4TS U1135 ( .A(n1477), .B(n1728), .Y(n1811) );
NAND2X2TS U1136 ( .A(n2097), .B(n2096), .Y(n2098) );
NAND3X4TS U1137 ( .A(n1476), .B(n1258), .C(n1756), .Y(n1008) );
NAND2X2TS U1138 ( .A(n1485), .B(n1149), .Y(n2428) );
NOR2X2TS U1139 ( .A(n1044), .B(n1487), .Y(n1485) );
NAND2X4TS U1140 ( .A(n2365), .B(n2671), .Y(n1700) );
INVX4TS U1141 ( .A(n1186), .Y(n1185) );
INVX2TS U1142 ( .A(n1728), .Y(n1541) );
NAND2X4TS U1143 ( .A(n986), .B(n2886), .Y(n1138) );
BUFX16TS U1144 ( .A(n1812), .Y(n1476) );
INVX1TS U1145 ( .A(n2602), .Y(n1098) );
NOR2X4TS U1146 ( .A(n1744), .B(n1487), .Y(n1745) );
INVX4TS U1147 ( .A(n2085), .Y(n2094) );
BUFX3TS U1148 ( .A(n1804), .Y(n1113) );
CLKINVX3TS U1149 ( .A(n1140), .Y(n1137) );
NOR2X6TS U1150 ( .A(n1143), .B(n1147), .Y(n1136) );
CLKXOR2X4TS U1151 ( .A(n3034), .B(n1333), .Y(n2261) );
NAND2X6TS U1152 ( .A(n998), .B(n1501), .Y(n1155) );
INVX2TS U1153 ( .A(n1573), .Y(n1574) );
INVX2TS U1154 ( .A(n1173), .Y(n1172) );
AND3X2TS U1155 ( .A(n2833), .B(n2832), .C(n2831), .Y(n1363) );
AND2X2TS U1156 ( .A(n2966), .B(n2965), .Y(n1178) );
NAND2X6TS U1157 ( .A(n1344), .B(n1547), .Y(n2367) );
NOR2X6TS U1158 ( .A(n1763), .B(n1469), .Y(n1262) );
BUFX3TS U1159 ( .A(n1845), .Y(n1046) );
INVX2TS U1160 ( .A(n2999), .Y(n1746) );
NAND2X2TS U1161 ( .A(n1455), .B(n2560), .Y(n1748) );
NAND2X6TS U1162 ( .A(n1724), .B(n1109), .Y(n1728) );
BUFX3TS U1163 ( .A(DMP_SFG[8]), .Y(n1040) );
INVX12TS U1164 ( .A(n1053), .Y(n984) );
NAND2X6TS U1165 ( .A(n1440), .B(n1439), .Y(n1438) );
NAND2X4TS U1166 ( .A(n2914), .B(n1021), .Y(n1744) );
NOR2X4TS U1167 ( .A(n1862), .B(n1187), .Y(n1143) );
NAND3X6TS U1168 ( .A(n1809), .B(n2437), .C(n2417), .Y(n1742) );
NOR2X4TS U1169 ( .A(n988), .B(n1484), .Y(n1800) );
AND2X6TS U1170 ( .A(n2255), .B(DMP_SFG[20]), .Y(n2266) );
BUFX6TS U1171 ( .A(n2923), .Y(n1484) );
INVX6TS U1172 ( .A(n1384), .Y(n1684) );
BUFX8TS U1173 ( .A(n2209), .Y(n1050) );
BUFX4TS U1174 ( .A(DMP_SFG[5]), .Y(n942) );
INVX2TS U1175 ( .A(n1764), .Y(n2613) );
NAND2X4TS U1176 ( .A(n1498), .B(n1270), .Y(n2088) );
CLKINVX6TS U1177 ( .A(n1840), .Y(n1452) );
OR2X4TS U1178 ( .A(n2256), .B(DMP_SFG[21]), .Y(n2271) );
INVX2TS U1179 ( .A(n1156), .Y(n1032) );
NOR3X4TS U1180 ( .A(n1022), .B(n2602), .C(n2921), .Y(n1021) );
INVX4TS U1181 ( .A(n1301), .Y(n1302) );
NOR2X2TS U1182 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[7]), .Y(n1723)
);
AND3X6TS U1183 ( .A(n1397), .B(n1724), .C(n1725), .Y(n976) );
INVX2TS U1184 ( .A(n1725), .Y(n1110) );
INVX6TS U1185 ( .A(n1343), .Y(n1344) );
INVX2TS U1186 ( .A(n1299), .Y(n1300) );
INVX2TS U1187 ( .A(Raw_mant_NRM_SWR[2]), .Y(n2451) );
INVX2TS U1188 ( .A(n1243), .Y(n1244) );
NOR2X6TS U1189 ( .A(Raw_mant_NRM_SWR[14]), .B(n2923), .Y(n1724) );
NAND2X2TS U1190 ( .A(n2236), .B(DMP_SFG[19]), .Y(n2251) );
INVX12TS U1191 ( .A(n2602), .Y(n2437) );
NAND2X4TS U1192 ( .A(n1115), .B(n1722), .Y(n1114) );
CLKAND2X2TS U1193 ( .A(n1379), .B(n1578), .Y(n1991) );
INVX8TS U1194 ( .A(n1119), .Y(n2914) );
INVX2TS U1195 ( .A(n1967), .Y(n1643) );
NAND2X6TS U1196 ( .A(n1339), .B(n1340), .Y(n1995) );
NAND2X6TS U1197 ( .A(n1975), .B(n1644), .Y(n1978) );
NOR2X4TS U1198 ( .A(DmP_mant_SFG_SWR[2]), .B(n2562), .Y(n1669) );
INVX4TS U1199 ( .A(n2994), .Y(n1022) );
OR2X6TS U1200 ( .A(n2231), .B(DMP_SFG[17]), .Y(n973) );
INVX8TS U1201 ( .A(n1549), .Y(n1550) );
INVX4TS U1202 ( .A(n1542), .Y(n1543) );
CLKINVX6TS U1203 ( .A(n2491), .Y(n1442) );
INVX2TS U1204 ( .A(n1063), .Y(n1157) );
NAND2X2TS U1205 ( .A(n2678), .B(n1330), .Y(n1988) );
INVX4TS U1206 ( .A(n1517), .Y(n2460) );
OAI21X2TS U1207 ( .A0(n1971), .A1(n1970), .B0(n1969), .Y(n1976) );
NOR2X6TS U1208 ( .A(n1647), .B(n1981), .Y(n1646) );
NOR2X2TS U1209 ( .A(n1249), .B(n1573), .Y(n1725) );
NAND2X2TS U1210 ( .A(n1760), .B(n2984), .Y(n1761) );
NAND2X4TS U1211 ( .A(n2670), .B(intDX_EWSW[28]), .Y(n1989) );
BUFX6TS U1212 ( .A(n1575), .Y(n1063) );
NAND2X1TS U1213 ( .A(n1535), .B(n1577), .Y(n1963) );
INVX2TS U1214 ( .A(n1273), .Y(n1274) );
NOR2X4TS U1215 ( .A(n1535), .B(n1577), .Y(n1965) );
NOR2X6TS U1216 ( .A(n1580), .B(n1357), .Y(n1973) );
NOR2X6TS U1217 ( .A(n2673), .B(n1382), .Y(n1984) );
NOR2X6TS U1218 ( .A(n2678), .B(n1330), .Y(n1990) );
BUFX16TS U1219 ( .A(n1525), .Y(n1044) );
NAND2X2TS U1220 ( .A(n1323), .B(n1331), .Y(n1969) );
NOR2X6TS U1221 ( .A(n1936), .B(n972), .Y(n1953) );
INVX4TS U1222 ( .A(n3093), .Y(n988) );
NAND2X2TS U1223 ( .A(n1265), .B(n1327), .Y(n1961) );
OAI21X2TS U1224 ( .A0(n972), .A1(n1951), .B0(n1950), .Y(n1952) );
OAI22X2TS U1225 ( .A0(n1928), .A1(n1528), .B0(n1527), .B1(n1526), .Y(n1932)
);
INVX2TS U1226 ( .A(n1993), .Y(n1338) );
NAND2X4TS U1227 ( .A(n2984), .B(n3093), .Y(n1001) );
NOR2X4TS U1228 ( .A(n1944), .B(n1939), .Y(n1946) );
CLKINVX1TS U1229 ( .A(n1362), .Y(n1069) );
INVX3TS U1230 ( .A(n1571), .Y(n1572) );
INVX4TS U1231 ( .A(n1579), .Y(n1580) );
INVX2TS U1232 ( .A(n1926), .Y(n1271) );
INVX2TS U1233 ( .A(n1347), .Y(n1527) );
NAND2BX2TS U1234 ( .AN(n953), .B(n1560), .Y(n1942) );
OR2X4TS U1235 ( .A(n1379), .B(n1578), .Y(n1993) );
NAND2X2TS U1236 ( .A(n1368), .B(n1348), .Y(n1426) );
NOR2X2TS U1237 ( .A(n1377), .B(n1298), .Y(n1935) );
AND2X4TS U1238 ( .A(n1320), .B(n1254), .Y(n1936) );
NOR2X4TS U1239 ( .A(n952), .B(n1360), .Y(n1929) );
NAND2X2TS U1240 ( .A(n1321), .B(n1253), .Y(n1951) );
INVX2TS U1241 ( .A(n1370), .Y(n1366) );
NAND2X2TS U1242 ( .A(n1372), .B(n1563), .Y(n1529) );
NAND2X2TS U1243 ( .A(n1377), .B(n1298), .Y(n1948) );
NOR2X4TS U1244 ( .A(n1282), .B(n987), .Y(n1281) );
CLKINVX3TS U1245 ( .A(n1341), .Y(n1342) );
INVX3TS U1246 ( .A(n1317), .Y(n1318) );
INVX8TS U1247 ( .A(intDX_EWSW[8]), .Y(n1287) );
NAND2X8TS U1248 ( .A(n1691), .B(DMP_SFG[7]), .Y(n1842) );
NAND2X8TS U1249 ( .A(n1544), .B(n1524), .Y(n1523) );
NAND3X6TS U1250 ( .A(n2192), .B(n2193), .C(n2191), .Y(n797) );
NAND2X6TS U1251 ( .A(n1169), .B(n1168), .Y(n2412) );
NAND2X4TS U1252 ( .A(n1170), .B(n2531), .Y(n1169) );
NAND3X6TS U1253 ( .A(n2190), .B(n2189), .C(n2188), .Y(n794) );
NAND3X6TS U1254 ( .A(n2034), .B(n2035), .C(n2033), .Y(n804) );
NAND2X4TS U1255 ( .A(n2607), .B(n1386), .Y(n2192) );
NAND2X6TS U1256 ( .A(n1552), .B(n2113), .Y(n645) );
NAND3X4TS U1257 ( .A(n2067), .B(n2066), .C(n2065), .Y(n625) );
NAND2X4TS U1258 ( .A(n1595), .B(n1357), .Y(n2066) );
NAND3X6TS U1259 ( .A(n2128), .B(n2129), .C(n2127), .Y(n663) );
NAND2X4TS U1260 ( .A(n2607), .B(n1325), .Y(n2129) );
NOR4X4TS U1261 ( .A(n1878), .B(n1877), .C(n1876), .D(n1875), .Y(n1912) );
AND2X8TS U1262 ( .A(n2393), .B(n2392), .Y(n3138) );
XNOR2X4TS U1263 ( .A(intDY_EWSW[13]), .B(n1362), .Y(n1889) );
NAND2X8TS U1264 ( .A(n1679), .B(n1242), .Y(n1828) );
NAND3X8TS U1265 ( .A(n2469), .B(n2468), .C(n2467), .Y(n2474) );
NAND2X6TS U1266 ( .A(n1082), .B(n1081), .Y(n1415) );
NOR2X8TS U1267 ( .A(n1112), .B(n2542), .Y(n3089) );
MXI2X4TS U1268 ( .A(n2564), .B(n2716), .S0(n2569), .Y(n701) );
NOR2X4TS U1269 ( .A(n2716), .B(DmP_EXP_EWSW[25]), .Y(n2223) );
MXI2X4TS U1270 ( .A(n2457), .B(n2456), .S0(n1592), .Y(n2406) );
NAND3X6TS U1271 ( .A(n1237), .B(n1236), .C(n1235), .Y(n624) );
NAND3X6TS U1272 ( .A(n2153), .B(n2152), .C(n2151), .Y(n653) );
XOR2X4TS U1273 ( .A(n1415), .B(n2211), .Y(n1832) );
INVX6TS U1274 ( .A(n789), .Y(n2716) );
AND2X8TS U1275 ( .A(n2406), .B(n2405), .Y(n3140) );
NAND2X8TS U1276 ( .A(n1131), .B(n1013), .Y(n2518) );
NAND2X6TS U1277 ( .A(n1816), .B(n1130), .Y(n1822) );
NAND3X6TS U1278 ( .A(n2029), .B(n2028), .C(n2027), .Y(n812) );
NAND2X4TS U1279 ( .A(n1590), .B(n1564), .Y(n2028) );
CLKINVX12TS U1280 ( .A(n986), .Y(n1587) );
NAND4X6TS U1281 ( .A(n2344), .B(n2343), .C(n2342), .D(n2341), .Y(n2527) );
CLKINVX12TS U1282 ( .A(n2790), .Y(n1064) );
NAND3X6TS U1283 ( .A(n2107), .B(n2106), .C(n2105), .Y(n641) );
NAND2X4TS U1284 ( .A(n1569), .B(n2165), .Y(n2106) );
NAND3X6TS U1285 ( .A(n2018), .B(n2017), .C(n2016), .Y(n814) );
NAND2X4TS U1286 ( .A(n2365), .B(n851), .Y(n2366) );
INVX16TS U1287 ( .A(n1417), .Y(n1672) );
OAI21X4TS U1288 ( .A0(n2830), .A1(n2829), .B0(n2828), .Y(n1711) );
NAND2X2TS U1289 ( .A(n2527), .B(n1592), .Y(n2528) );
NAND2X6TS U1290 ( .A(n1858), .B(n1857), .Y(n1861) );
NAND3X8TS U1291 ( .A(n1869), .B(n1868), .C(n1867), .Y(n2500) );
XNOR2X4TS U1292 ( .A(DmP_mant_SFG_SWR[2]), .B(n2977), .Y(n2304) );
NAND3X8TS U1293 ( .A(n1689), .B(n1688), .C(n1687), .Y(n2335) );
NAND4X8TS U1294 ( .A(n2376), .B(n2375), .C(n2373), .D(n2374), .Y(n2533) );
INVX4TS U1295 ( .A(n1668), .Y(n1667) );
NAND2X6TS U1296 ( .A(DMP_SFG[4]), .B(n1668), .Y(n2484) );
AND2X8TS U1297 ( .A(n2505), .B(n2504), .Y(n3146) );
INVX12TS U1298 ( .A(n1277), .Y(n1282) );
NAND2X4TS U1299 ( .A(n1277), .B(n1533), .Y(n2152) );
NAND2X4TS U1300 ( .A(n1533), .B(n1296), .Y(n2029) );
NAND2X4TS U1301 ( .A(n1533), .B(n1331), .Y(n2205) );
NAND2X4TS U1302 ( .A(n1533), .B(n1371), .Y(n2172) );
AND2X8TS U1303 ( .A(n2369), .B(n2368), .Y(n3148) );
AND2X6TS U1304 ( .A(n2943), .B(n2942), .Y(n1052) );
NAND3X6TS U1305 ( .A(n2202), .B(n2201), .C(n2200), .Y(n792) );
NAND3X6TS U1306 ( .A(n2183), .B(n2184), .C(n2182), .Y(n800) );
NAND3X2TS U1307 ( .A(n2175), .B(n2327), .C(n2326), .Y(n2333) );
NAND3X4TS U1308 ( .A(n2021), .B(n2020), .C(n2019), .Y(n655) );
NAND3X6TS U1309 ( .A(n2611), .B(n2610), .C(n2609), .Y(n671) );
NAND3X6TS U1310 ( .A(n2074), .B(n2075), .C(n2073), .Y(n639) );
NAND3X8TS U1311 ( .A(n2388), .B(n2387), .C(n2386), .Y(n2470) );
NOR2X8TS U1312 ( .A(n1666), .B(n2412), .Y(n3122) );
CLKINVX12TS U1313 ( .A(n1431), .Y(n1430) );
NAND2X8TS U1314 ( .A(n1134), .B(n1133), .Y(n1431) );
NAND2X4TS U1315 ( .A(n2352), .B(n2509), .Y(n1133) );
AOI21X2TS U1316 ( .A0(n1787), .A1(n1600), .B0(n948), .Y(n3063) );
NAND2X4TS U1317 ( .A(n1741), .B(n1739), .Y(n1072) );
NAND2X6TS U1318 ( .A(n1077), .B(n979), .Y(n2537) );
OAI2BB2X4TS U1319 ( .B0(n2536), .B1(n3074), .A0N(n2531), .A1N(n2530), .Y(
n2532) );
NAND2X4TS U1320 ( .A(n1856), .B(n1006), .Y(n1005) );
NAND2X4TS U1321 ( .A(n1856), .B(n1004), .Y(n1003) );
INVX4TS U1322 ( .A(n1429), .Y(n1428) );
OA22X4TS U1323 ( .A0(n2797), .A1(n1187), .B0(n2796), .B1(n2795), .Y(n1337)
);
NAND3X4TS U1324 ( .A(n2545), .B(n1600), .C(DmP_mant_SHT1_SW[17]), .Y(n3055)
);
BUFX20TS U1325 ( .A(n2227), .Y(n2626) );
NAND2X4TS U1326 ( .A(n2465), .B(n851), .Y(n2399) );
NOR2X8TS U1327 ( .A(n1122), .B(n1014), .Y(n1013) );
NAND3X8TS U1328 ( .A(n1129), .B(n1126), .C(n1123), .Y(n1122) );
INVX12TS U1329 ( .A(n2233), .Y(n1439) );
NAND2X4TS U1330 ( .A(n2607), .B(n953), .Y(n2126) );
NAND2X4TS U1331 ( .A(n1544), .B(Raw_mant_NRM_SWR[1]), .Y(n1490) );
NAND2X4TS U1332 ( .A(n1544), .B(Raw_mant_NRM_SWR[16]), .Y(n2207) );
MXI2X2TS U1333 ( .A(n2642), .B(n2713), .S0(n2563), .Y(n730) );
NAND2X6TS U1334 ( .A(n1540), .B(n2158), .Y(n665) );
MX2X4TS U1335 ( .A(n2336), .B(n2337), .S0(n2335), .Y(n2339) );
NAND2X6TS U1336 ( .A(n2335), .B(n1690), .Y(n1425) );
NAND2X4TS U1337 ( .A(n2559), .B(n2558), .Y(n820) );
NAND2X4TS U1338 ( .A(n2559), .B(n2556), .Y(n821) );
NAND2X4TS U1339 ( .A(n2559), .B(n2554), .Y(n822) );
NAND2X4TS U1340 ( .A(n2559), .B(n2552), .Y(n819) );
NAND2X4TS U1341 ( .A(n2559), .B(n2476), .Y(n816) );
NAND2X4TS U1342 ( .A(n2559), .B(n2478), .Y(n818) );
NAND2X4TS U1343 ( .A(n2559), .B(n2480), .Y(n817) );
NAND4X4TS U1344 ( .A(n1903), .B(n1905), .C(n1904), .D(n1906), .Y(n1907) );
NAND3X4TS U1345 ( .A(n2005), .B(n2004), .C(n2003), .Y(n788) );
NAND2X4TS U1346 ( .A(n2160), .B(n1364), .Y(n2004) );
NOR2X4TS U1347 ( .A(n2542), .B(Raw_mant_NRM_SWR[5]), .Y(n1765) );
INVX12TS U1348 ( .A(n1355), .Y(n950) );
NOR2X4TS U1349 ( .A(n2493), .B(n2494), .Y(n1259) );
NAND4X6TS U1350 ( .A(n1733), .B(n1732), .C(n1102), .D(n2436), .Y(n2540) );
INVX8TS U1351 ( .A(n993), .Y(n1540) );
NAND2X4TS U1352 ( .A(n1533), .B(n1294), .Y(n2034) );
NAND2X8TS U1353 ( .A(n2983), .B(n2982), .Y(n1007) );
NOR2X6TS U1354 ( .A(n1107), .B(n1106), .Y(n1105) );
INVX8TS U1355 ( .A(n1551), .Y(n1552) );
OAI21X4TS U1356 ( .A0(n3126), .A1(n945), .B0(n943), .Y(n583) );
NOR2X8TS U1357 ( .A(n946), .B(n1419), .Y(n3126) );
AND2X8TS U1358 ( .A(n2370), .B(n1591), .Y(n946) );
NAND2X8TS U1359 ( .A(n947), .B(n2460), .Y(n1492) );
NAND2X8TS U1360 ( .A(n1056), .B(n1518), .Y(n947) );
OAI22X4TS U1361 ( .A0(n3065), .A1(n1508), .B0(n1785), .B1(n1608), .Y(n948)
);
AOI22X4TS U1362 ( .A0(n2997), .A1(n1613), .B0(n981), .B1(DmP_mant_SHT1_SW[7]), .Y(n3058) );
INVX12TS U1363 ( .A(n1652), .Y(n981) );
NAND2X4TS U1364 ( .A(n1512), .B(n1510), .Y(n1652) );
OAI21X4TS U1365 ( .A0(n2092), .A1(n2095), .B0(n2096), .Y(n2080) );
MXI2X4TS U1366 ( .A(n3134), .B(n2398), .S0(n2563), .Y(n537) );
OAI2BB1X4TS U1367 ( .A0N(n2352), .A1N(n2365), .B0(n2354), .Y(n2358) );
AOI21X4TS U1368 ( .A0(n2266), .A1(n2271), .B0(n2257), .Y(n2258) );
MXI2X4TS U1369 ( .A(n2395), .B(n2394), .S0(left_right_SHT2), .Y(n2396) );
NAND3X6TS U1370 ( .A(n949), .B(n2072), .C(n2071), .Y(n659) );
NAND2X4TS U1371 ( .A(n2160), .B(n1367), .Y(n949) );
NAND3X6TS U1372 ( .A(n950), .B(n2064), .C(n2063), .Y(n623) );
INVX12TS U1373 ( .A(n951), .Y(n952) );
INVX8TS U1374 ( .A(n953), .Y(n954) );
NAND2X4TS U1375 ( .A(n1533), .B(n1251), .Y(n2189) );
BUFX16TS U1376 ( .A(n2056), .Y(n2155) );
NAND3X4TS U1377 ( .A(n2187), .B(n2186), .C(n2185), .Y(n796) );
NAND2X4TS U1378 ( .A(n2329), .B(n1273), .Y(n2186) );
NAND3X4TS U1379 ( .A(n2196), .B(n2195), .C(n2194), .Y(n799) );
NAND2X4TS U1380 ( .A(n2154), .B(n1317), .Y(n2195) );
OAI21X2TS U1381 ( .A0(n1034), .A1(n2338), .B0(n1033), .Y(n599) );
AND2X4TS U1382 ( .A(n2606), .B(intDY_EWSW[24]), .Y(n1310) );
BUFX20TS U1383 ( .A(n2340), .Y(n2581) );
NAND2X1TS U1384 ( .A(n1282), .B(n987), .Y(n1641) );
NOR2X1TS U1385 ( .A(n1265), .B(n1327), .Y(n1959) );
OAI21X2TS U1386 ( .A0(n1844), .A1(DmP_mant_SFG_SWR[4]), .B0(n1549), .Y(n1681) );
OR2X6TS U1387 ( .A(n1639), .B(n2497), .Y(n1636) );
AND2X2TS U1388 ( .A(n2428), .B(n1412), .Y(n2429) );
XNOR2X1TS U1389 ( .A(n1378), .B(n1578), .Y(n1904) );
XNOR2X1TS U1390 ( .A(n1376), .B(n1298), .Y(n1892) );
NAND2X4TS U1391 ( .A(n1637), .B(n1636), .Y(n1635) );
OR2X4TS U1392 ( .A(n2367), .B(n1586), .Y(n1171) );
NAND2X1TS U1393 ( .A(n2502), .B(n2578), .Y(n2344) );
NAND2X4TS U1394 ( .A(n2579), .B(n2365), .Y(n1774) );
XOR2X1TS U1395 ( .A(n2334), .B(n2633), .Y(n2337) );
OR2X2TS U1396 ( .A(n1300), .B(n3036), .Y(n1662) );
NAND4X1TS U1397 ( .A(n1794), .B(n1040), .C(n1793), .D(n3036), .Y(n1795) );
NAND2X1TS U1398 ( .A(n2338), .B(Raw_mant_NRM_SWR[16]), .Y(n1033) );
INVX4TS U1399 ( .A(n1591), .Y(n1592) );
AOI22X4TS U1400 ( .A0(n1179), .A1(n2887), .B0(n1217), .B1(n1196), .Y(n970)
);
AND2X8TS U1401 ( .A(n1373), .B(n1318), .Y(n972) );
AND2X8TS U1402 ( .A(n1118), .B(n1117), .Y(n974) );
NAND4X8TS U1403 ( .A(n1178), .B(n1177), .C(n1175), .D(n1172), .Y(n977) );
OR2X8TS U1404 ( .A(n1762), .B(n1761), .Y(n978) );
CLKINVX12TS U1405 ( .A(n1505), .Y(n1506) );
NAND2X4TS U1406 ( .A(n1577), .B(n2154), .Y(n2198) );
BUFX8TS U1407 ( .A(n2174), .Y(n1103) );
NOR2X4TS U1408 ( .A(n2174), .B(n2639), .Y(n1463) );
NAND2X6TS U1409 ( .A(n1445), .B(n1446), .Y(n1319) );
NAND2X4TS U1410 ( .A(n1089), .B(n1090), .Y(n1082) );
NAND3X6TS U1411 ( .A(n1105), .B(n1108), .C(n2421), .Y(n1104) );
NOR2X4TS U1412 ( .A(n1084), .B(n984), .Y(n1083) );
INVX2TS U1413 ( .A(n1610), .Y(n1153) );
INVX2TS U1414 ( .A(n1830), .Y(n1088) );
INVX4TS U1415 ( .A(n1087), .Y(n1085) );
CLKMX2X2TS U1416 ( .A(Data_Y[1]), .B(n1388), .S0(n2593), .Y(n888) );
CLKMX2X2TS U1417 ( .A(Data_Y[4]), .B(n1325), .S0(n2595), .Y(n885) );
CLKMX2X2TS U1418 ( .A(Data_Y[15]), .B(n1569), .S0(n2594), .Y(n874) );
INVX2TS U1419 ( .A(n2535), .Y(n1074) );
CLKMX2X2TS U1420 ( .A(Data_Y[14]), .B(n1320), .S0(n2594), .Y(n875) );
CLKMX2X2TS U1421 ( .A(Data_X[20]), .B(n1251), .S0(n2600), .Y(n903) );
CLKMX2X2TS U1422 ( .A(Data_X[10]), .B(n1294), .S0(n2597), .Y(n913) );
CLKMX2X2TS U1423 ( .A(Data_X[12]), .B(n1298), .S0(n2600), .Y(n911) );
CLKMX2X2TS U1424 ( .A(Data_Y[8]), .B(n1341), .S0(n2595), .Y(n881) );
CLKMX2X2TS U1425 ( .A(Data_X[14]), .B(n1253), .S0(n2600), .Y(n909) );
CLKMX2X3TS U1426 ( .A(Data_X[15]), .B(n1317), .S0(n2600), .Y(n908) );
INVX8TS U1427 ( .A(n1608), .Y(n1610) );
CLKMX2X2TS U1428 ( .A(Data_X[18]), .B(n1273), .S0(n2600), .Y(n905) );
BUFX12TS U1429 ( .A(n2548), .Y(n2545) );
OAI21X1TS U1430 ( .A0(n2482), .A1(n1606), .B0(n1746), .Y(n890) );
INVX2TS U1431 ( .A(n1790), .Y(n1794) );
CLKMX2X2TS U1432 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n2591), .Y(n626) );
BUFX8TS U1433 ( .A(n2340), .Y(n2539) );
CLKMX2X3TS U1434 ( .A(DmP_mant_SHT1_SW[21]), .B(DmP_EXP_EWSW[21]), .S0(n2591), .Y(n628) );
CLKMX2X2TS U1435 ( .A(DmP_mant_SHT1_SW[2]), .B(DmP_EXP_EWSW[2]), .S0(n2591),
.Y(n666) );
AND2X2TS U1436 ( .A(n2254), .B(n2251), .Y(n1247) );
CLKMX2X2TS U1437 ( .A(DmP_mant_SHT1_SW[4]), .B(DmP_EXP_EWSW[4]), .S0(n2589),
.Y(n662) );
CLKMX2X2TS U1438 ( .A(DmP_mant_SHT1_SW[10]), .B(DmP_EXP_EWSW[10]), .S0(n2591), .Y(n650) );
INVX2TS U1439 ( .A(n1550), .Y(n1041) );
BUFX12TS U1440 ( .A(n2079), .Y(n3035) );
INVX2TS U1441 ( .A(n1583), .Y(n1006) );
INVX2TS U1442 ( .A(n622), .Y(n2717) );
BUFX16TS U1443 ( .A(n2111), .Y(n2608) );
NOR2X4TS U1444 ( .A(n791), .B(n2721), .Y(n2567) );
INVX3TS U1445 ( .A(n1253), .Y(n1254) );
INVX8TS U1446 ( .A(n1297), .Y(n1383) );
INVX3TS U1447 ( .A(n1325), .Y(n1326) );
BUFX16TS U1448 ( .A(n3162), .Y(n2482) );
INVX3TS U1449 ( .A(n1294), .Y(n1295) );
INVX16TS U1450 ( .A(Shift_reg_FLAGS_7_5), .Y(n2561) );
INVX2TS U1451 ( .A(n1320), .Y(n1321) );
INVX3TS U1452 ( .A(n1328), .Y(n1329) );
BUFX16TS U1453 ( .A(shift_value_SHT2_EWR_4_), .Y(n2506) );
INVX3TS U1454 ( .A(n1557), .Y(n1558) );
INVX2TS U1455 ( .A(DMP_exp_NRM2_EW[7]), .Y(n1017) );
INVX2TS U1456 ( .A(n3060), .Y(n2210) );
BUFX6TS U1457 ( .A(n2663), .Y(n1042) );
INVX2TS U1458 ( .A(n1221), .Y(n1176) );
NAND2X2TS U1459 ( .A(n1002), .B(n1520), .Y(n579) );
NAND2X4TS U1460 ( .A(n1467), .B(n1466), .Y(n604) );
NOR2X4TS U1461 ( .A(n1090), .B(n1085), .Y(n1084) );
INVX3TS U1462 ( .A(n2976), .Y(n1402) );
NAND2X4TS U1463 ( .A(n2534), .B(n2506), .Y(n1131) );
NOR2X4TS U1464 ( .A(n1609), .B(n1817), .Y(n1651) );
NAND2X4TS U1465 ( .A(n1675), .B(n1674), .Y(n1676) );
INVX8TS U1466 ( .A(n1586), .Y(n2517) );
INVX8TS U1467 ( .A(n1609), .Y(n3104) );
INVX8TS U1468 ( .A(n2995), .Y(n2976) );
NAND2X4TS U1469 ( .A(n2524), .B(n2511), .Y(n1134) );
NAND2X4TS U1470 ( .A(n2365), .B(n852), .Y(n1778) );
INVX4TS U1471 ( .A(n2545), .Y(n1511) );
NAND2X4TS U1472 ( .A(n838), .B(n2511), .Y(n1129) );
CLKMX2X2TS U1473 ( .A(Data_X[9]), .B(n987), .S0(n2597), .Y(n914) );
INVX8TS U1474 ( .A(n1608), .Y(n1611) );
INVX2TS U1475 ( .A(n1312), .Y(n1524) );
NAND2X2TS U1476 ( .A(n2566), .B(n1116), .Y(n3041) );
BUFX6TS U1477 ( .A(n2596), .Y(n2593) );
CLKMX2X3TS U1478 ( .A(DmP_mant_SHT1_SW[3]), .B(DmP_EXP_EWSW[3]), .S0(n2591),
.Y(n664) );
BUFX12TS U1479 ( .A(n1591), .Y(n1606) );
BUFX12TS U1480 ( .A(n2340), .Y(n3001) );
CLKMX2X2TS U1481 ( .A(SIGN_FLAG_SHT1), .B(SIGN_FLAG_EXP), .S0(n2569), .Y(
n609) );
CLKMX2X3TS U1482 ( .A(DmP_mant_SHT1_SW[5]), .B(n1309), .S0(n2591), .Y(n660)
);
AND2X4TS U1483 ( .A(n1815), .B(n2963), .Y(n1130) );
INVX4TS U1484 ( .A(n2246), .Y(n2082) );
NOR2X6TS U1485 ( .A(n1700), .B(n1591), .Y(n2364) );
INVX8TS U1486 ( .A(n3035), .Y(n985) );
NOR2X2TS U1487 ( .A(n1914), .B(n2608), .Y(n1915) );
CLKMX2X2TS U1488 ( .A(DmP_mant_SHT1_SW[7]), .B(DmP_EXP_EWSW[7]), .S0(n2590),
.Y(n656) );
INVX6TS U1489 ( .A(n1570), .Y(n1373) );
CLKMX2X2TS U1490 ( .A(DmP_mant_SHT1_SW[16]), .B(DmP_EXP_EWSW[16]), .S0(n2590), .Y(n638) );
CLKMX2X2TS U1491 ( .A(DmP_mant_SHT1_SW[12]), .B(DmP_EXP_EWSW[12]), .S0(n2590), .Y(n646) );
CLKMX2X3TS U1492 ( .A(DmP_mant_SHT1_SW[13]), .B(DmP_EXP_EWSW[13]), .S0(n2588), .Y(n644) );
CLKMX2X2TS U1493 ( .A(DmP_mant_SHT1_SW[14]), .B(DmP_EXP_EWSW[14]), .S0(n2590), .Y(n642) );
INVX12TS U1494 ( .A(n2561), .Y(n2569) );
INVX12TS U1495 ( .A(n2561), .Y(n2589) );
CLKMX2X2TS U1496 ( .A(n1613), .B(DmP_EXP_EWSW[6]), .S0(n2588), .Y(n658) );
INVX4TS U1497 ( .A(n624), .Y(n1664) );
NOR2X4TS U1498 ( .A(n1862), .B(n1183), .Y(n1029) );
CLKMX2X2TS U1499 ( .A(DmP_mant_SHT1_SW[8]), .B(DmP_EXP_EWSW[8]), .S0(n2590),
.Y(n654) );
CLKMX2X3TS U1500 ( .A(DmP_mant_SHT1_SW[17]), .B(n1539), .S0(n2590), .Y(n636)
);
CLKMX2X2TS U1501 ( .A(DmP_mant_SHT1_SW[18]), .B(DmP_EXP_EWSW[18]), .S0(n2590), .Y(n634) );
CLKMX2X2TS U1502 ( .A(DmP_mant_SHT1_SW[11]), .B(DmP_EXP_EWSW[11]), .S0(n2590), .Y(n648) );
NAND2X4TS U1503 ( .A(n1818), .B(n1125), .Y(n1124) );
CLKMX2X3TS U1504 ( .A(DMP_SHT1_EWSW[23]), .B(n791), .S0(n2587), .Y(n711) );
NOR2X4TS U1505 ( .A(n1862), .B(n1213), .Y(n1028) );
INVX8TS U1506 ( .A(n2722), .Y(n2587) );
INVX4TS U1507 ( .A(n1331), .Y(n1332) );
INVX6TS U1508 ( .A(n1564), .Y(n1565) );
INVX2TS U1509 ( .A(n1251), .Y(n1252) );
INVX2TS U1510 ( .A(n2619), .Y(n2573) );
BUFX6TS U1511 ( .A(Shift_reg_FLAGS_7[2]), .Y(n3037) );
INVX6TS U1512 ( .A(n1388), .Y(n1389) );
INVX6TS U1513 ( .A(n1569), .Y(n1570) );
INVX6TS U1514 ( .A(n1346), .Y(n1347) );
INVX2TS U1515 ( .A(n1547), .Y(n1548) );
INVX12TS U1516 ( .A(n1349), .Y(n3093) );
INVX6TS U1517 ( .A(n1534), .Y(n1535) );
INVX2TS U1518 ( .A(n1205), .Y(n1141) );
INVX2TS U1519 ( .A(n1249), .Y(n1250) );
INVX2TS U1520 ( .A(n2627), .Y(n1004) );
AND2X4TS U1521 ( .A(n2956), .B(n2955), .Y(n1125) );
NAND2X4TS U1522 ( .A(n1489), .B(n1299), .Y(n3077) );
INVX8TS U1523 ( .A(n1538), .Y(n1489) );
NAND3X6TS U1524 ( .A(n1491), .B(n1490), .C(n2447), .Y(n1504) );
NAND2X4TS U1525 ( .A(n2461), .B(n1478), .Y(n584) );
NAND4X4TS U1526 ( .A(n1423), .B(n2576), .C(n1791), .D(n1794), .Y(n1796) );
INVX8TS U1527 ( .A(n1070), .Y(n3124) );
INVX12TS U1528 ( .A(n1104), .Y(n1396) );
NAND3X6TS U1529 ( .A(n1075), .B(n1073), .C(n1071), .Y(n1070) );
MX2X2TS U1530 ( .A(Raw_mant_SGF[13]), .B(n1243), .S0(n2566), .Y(n602) );
NAND2X6TS U1531 ( .A(n1180), .B(n2249), .Y(n1468) );
MX2X2TS U1532 ( .A(Raw_mant_SGF[15]), .B(n1249), .S0(n2566), .Y(n600) );
INVX12TS U1533 ( .A(n1080), .Y(n1089) );
AND2X4TS U1534 ( .A(n2429), .B(n1453), .Y(n1408) );
NAND2X4TS U1535 ( .A(n1170), .B(shift_value_SHT2_EWR_4_), .Y(n2467) );
NOR2X4TS U1536 ( .A(n2631), .B(n1402), .Y(n1241) );
NAND2X4TS U1537 ( .A(n2511), .B(n1554), .Y(n1717) );
INVX2TS U1538 ( .A(n1822), .Y(n1316) );
AND2X6TS U1539 ( .A(n1822), .B(n2512), .Y(n1014) );
NAND2X6TS U1540 ( .A(n2517), .B(n2502), .Y(n1079) );
AND2X4TS U1541 ( .A(n1088), .B(n1087), .Y(n1086) );
CLKBUFX3TS U1542 ( .A(n2752), .Y(n982) );
NAND2X6TS U1543 ( .A(n2260), .B(n2275), .Y(n2493) );
INVX2TS U1544 ( .A(n977), .Y(n1785) );
NAND3X4TS U1545 ( .A(n2217), .B(n1685), .C(n2215), .Y(n1686) );
NAND2X6TS U1546 ( .A(n1825), .B(n1826), .Y(n2534) );
MX2X2TS U1547 ( .A(add_subt), .B(intAS), .S0(n2593), .Y(n891) );
CLKMX2X2TS U1548 ( .A(Data_Y[23]), .B(n1579), .S0(n2598), .Y(n866) );
CLKMX2X2TS U1549 ( .A(Data_Y[17]), .B(intDY_EWSW[17]), .S0(n2594), .Y(n872)
);
NAND2X2TS U1550 ( .A(n2301), .B(n2300), .Y(n2302) );
NAND2X6TS U1551 ( .A(n1829), .B(n1828), .Y(n2318) );
MX2X2TS U1552 ( .A(Data_Y[31]), .B(intDY_EWSW[31]), .S0(n2593), .Y(n858) );
MX2X2TS U1553 ( .A(Data_Y[13]), .B(intDY_EWSW[13]), .S0(n2594), .Y(n876) );
NAND2X6TS U1554 ( .A(n844), .B(n2465), .Y(n2348) );
NAND2X6TS U1555 ( .A(n842), .B(n1604), .Y(n1123) );
MX2X2TS U1556 ( .A(Data_Y[22]), .B(n1047), .S0(n2598), .Y(n867) );
MX2X2TS U1557 ( .A(Data_Y[27]), .B(intDY_EWSW[27]), .S0(n2598), .Y(n862) );
MX2X2TS U1558 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n2593), .Y(n892) );
MX2X2TS U1559 ( .A(Data_Y[28]), .B(intDY_EWSW[28]), .S0(n2598), .Y(n861) );
INVX12TS U1560 ( .A(n1608), .Y(n1609) );
CLKMX2X2TS U1561 ( .A(Data_Y[30]), .B(n1378), .S0(n2599), .Y(n859) );
INVX6TS U1562 ( .A(n1441), .Y(n1440) );
BUFX12TS U1563 ( .A(n2596), .Y(n2597) );
INVX8TS U1564 ( .A(n1311), .Y(n1829) );
BUFX12TS U1565 ( .A(n2596), .Y(n2599) );
NAND2X6TS U1566 ( .A(n1442), .B(n1660), .Y(n1441) );
AND2X8TS U1567 ( .A(n1144), .B(n1146), .Y(n1135) );
NAND2X2TS U1568 ( .A(n2581), .B(DmP_mant_SFG_SWR[5]), .Y(n1781) );
BUFX12TS U1569 ( .A(n2596), .Y(n2594) );
BUFX12TS U1570 ( .A(n2596), .Y(n2595) );
INVX2TS U1571 ( .A(n2337), .Y(n2336) );
BUFX12TS U1572 ( .A(n2596), .Y(n2598) );
BUFX12TS U1573 ( .A(n2596), .Y(n2600) );
CLKMX2X2TS U1574 ( .A(DMP_SHT1_EWSW[2]), .B(DMP_EXP_EWSW[2]), .S0(n2591),
.Y(n774) );
NAND2X2TS U1575 ( .A(n2566), .B(n1349), .Y(n2237) );
INVX3TS U1576 ( .A(n1678), .Y(n1679) );
AND2X2TS U1577 ( .A(n2161), .B(n1306), .Y(n2051) );
INVX8TS U1578 ( .A(n2293), .Y(n2280) );
NAND2X2TS U1579 ( .A(n2170), .B(n791), .Y(n2009) );
NAND2X2TS U1580 ( .A(n2170), .B(n789), .Y(n2006) );
NAND2X6TS U1581 ( .A(n1667), .B(n2632), .Y(n2483) );
NAND2X4TS U1582 ( .A(n2717), .B(DMP_EXP_EWSW[26]), .Y(n2310) );
INVX8TS U1583 ( .A(n2923), .Y(n1464) );
INVX8TS U1584 ( .A(n1111), .Y(n1397) );
CLKMX2X2TS U1585 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n2589), .Y(n612)
);
INVX3TS U1586 ( .A(n2292), .Y(n1437) );
INVX6TS U1587 ( .A(n2090), .Y(n1493) );
CLKBUFX3TS U1588 ( .A(n3029), .Y(n3003) );
CLKMX2X2TS U1589 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[24]), .S0(n3037), .Y(
n703) );
NAND2X2TS U1590 ( .A(n2111), .B(DmP_EXP_EWSW[13]), .Y(n2112) );
CLKMX2X2TS U1591 ( .A(DMP_SHT1_EWSW[24]), .B(DMP_EXP_EWSW[24]), .S0(n2587),
.Y(n706) );
CLKMX2X2TS U1592 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[25]), .S0(n3037), .Y(
n698) );
CLKMX2X3TS U1593 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(busy),
.Y(n710) );
NOR2X4TS U1594 ( .A(n2261), .B(DMP_SFG[22]), .Y(n2494) );
CLKMX2X2TS U1595 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[23]), .S0(n3037), .Y(
n708) );
NOR2X4TS U1596 ( .A(n2686), .B(n996), .Y(n1416) );
OA21X4TS U1597 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[2]), .B0(
n1755), .Y(n1756) );
NAND2X2TS U1598 ( .A(n2338), .B(Raw_mant_NRM_SWR[14]), .Y(n1531) );
NAND2X4TS U1599 ( .A(n1329), .B(n1286), .Y(n1919) );
AND2X4TS U1600 ( .A(Raw_mant_NRM_SWR[14]), .B(n3093), .Y(n1760) );
NOR2X4TS U1601 ( .A(n1565), .B(n1296), .Y(n1917) );
CLKMX2X2TS U1602 ( .A(DMP_SHT1_EWSW[29]), .B(DMP_EXP_EWSW[29]), .S0(n2587),
.Y(n681) );
CLKMX2X2TS U1603 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[29]), .S0(n3037), .Y(
n678) );
NAND2X6TS U1604 ( .A(n1342), .B(intDX_EWSW[8]), .Y(n1642) );
NOR2X1TS U1605 ( .A(n985), .B(overflow_flag), .Y(n2489) );
INVX2TS U1606 ( .A(n791), .Y(n2743) );
CLKMX2X3TS U1607 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(n3162), .Y(n611)
);
OR2X4TS U1608 ( .A(n1557), .B(n1295), .Y(n1943) );
CLKMX2X2TS U1609 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n3037), .Y(n606) );
INVX12TS U1610 ( .A(n2561), .Y(n2591) );
CLKMX2X2TS U1611 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[26]), .S0(n3037), .Y(
n693) );
BUFX20TS U1612 ( .A(n1179), .Y(n986) );
CLKMX2X2TS U1613 ( .A(DMP_SHT1_EWSW[0]), .B(DMP_EXP_EWSW[0]), .S0(n2587),
.Y(n780) );
OR2X6TS U1614 ( .A(n2228), .B(DMP_SFG[14]), .Y(n2492) );
CLKMX2X2TS U1615 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(busy),
.Y(n680) );
CLKMX2X2TS U1616 ( .A(DMP_SHT1_EWSW[27]), .B(DMP_EXP_EWSW[27]), .S0(n2587),
.Y(n691) );
CLKMX2X2TS U1617 ( .A(DMP_SHT1_EWSW[26]), .B(DMP_EXP_EWSW[26]), .S0(n2587),
.Y(n696) );
CLKMX2X2TS U1618 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(n3037), .Y(n615) );
CLKMX2X2TS U1619 ( .A(DMP_SHT1_EWSW[1]), .B(n1308), .S0(n2587), .Y(n777) );
CLKMX2X2TS U1620 ( .A(DMP_SHT1_EWSW[28]), .B(n1350), .S0(n2587), .Y(n686) );
NAND2X6TS U1621 ( .A(n2917), .B(n2916), .Y(n1120) );
INVX8TS U1622 ( .A(n1562), .Y(n1563) );
INVX2TS U1623 ( .A(n1602), .Y(n1603) );
NAND2X4TS U1624 ( .A(n1655), .B(n2993), .Y(n1165) );
INVX6TS U1625 ( .A(n1367), .Y(n1368) );
NAND2X4TS U1626 ( .A(n1216), .B(n1202), .Y(n1144) );
INVX12TS U1627 ( .A(n1383), .Y(n987) );
INVX8TS U1628 ( .A(n1369), .Y(n1370) );
NAND3X6TS U1629 ( .A(n1240), .B(n1239), .C(n1238), .Y(n789) );
INVX2TS U1630 ( .A(n1360), .Y(n1361) );
NAND2X6TS U1631 ( .A(n2929), .B(n2928), .Y(n1470) );
INVX6TS U1632 ( .A(n1264), .Y(n1265) );
INVX2TS U1633 ( .A(DMP_SHT2_EWSW[29]), .Y(n2298) );
INVX12TS U1634 ( .A(Shift_reg_FLAGS_7_6), .Y(n2111) );
INVX6TS U1635 ( .A(n1376), .Y(n1377) );
INVX6TS U1636 ( .A(n1378), .Y(n1379) );
INVX2TS U1637 ( .A(n2622), .Y(n2564) );
INVX12TS U1638 ( .A(n1566), .Y(n1420) );
BUFX3TS U1639 ( .A(DmP_mant_SHT1_SW[15]), .Y(n1612) );
BUFX4TS U1640 ( .A(DmP_mant_SHT1_SW[6]), .Y(n1613) );
INVX8TS U1641 ( .A(DMP_SFG[0]), .Y(n2562) );
BUFX8TS U1642 ( .A(n2820), .Y(n1043) );
NAND2X4TS U1643 ( .A(n2681), .B(n1273), .Y(n1964) );
INVX8TS U1644 ( .A(n2722), .Y(n2590) );
INVX3TS U1645 ( .A(n1322), .Y(n1323) );
NOR2X6TS U1646 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2720), .Y(n2592) );
MXI2X2TS U1647 ( .A(n2719), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2325) );
INVX2TS U1648 ( .A(SIGN_FLAG_SHT1SHT2), .Y(n2249) );
AND2X4TS U1649 ( .A(n2913), .B(n2912), .Y(n1128) );
NAND2X8TS U1650 ( .A(n990), .B(n1447), .Y(n1640) );
NAND3X8TS U1651 ( .A(n1838), .B(n1449), .C(n1030), .Y(n990) );
NAND2X4TS U1652 ( .A(n1544), .B(Raw_mant_NRM_SWR[3]), .Y(n2448) );
NAND2X2TS U1653 ( .A(n2111), .B(DmP_EXP_EWSW[6]), .Y(n2071) );
NOR2X8TS U1654 ( .A(n1404), .B(DMP_exp_NRM2_EW[3]), .Y(n2095) );
NOR2X8TS U1655 ( .A(n1403), .B(DMP_exp_NRM2_EW[2]), .Y(n2093) );
NOR2X8TS U1656 ( .A(n2093), .B(n2095), .Y(n2081) );
NAND3X8TS U1657 ( .A(n2409), .B(n2408), .C(n2407), .Y(n3069) );
CLKINVX12TS U1658 ( .A(n2493), .Y(n1639) );
NAND2X8TS U1659 ( .A(n2537), .B(n1606), .Y(n1075) );
NOR2X8TS U1660 ( .A(n1452), .B(n2484), .Y(n1451) );
NOR2X8TS U1661 ( .A(n2259), .B(n2285), .Y(n2260) );
BUFX3TS U1662 ( .A(n2288), .Y(n991) );
BUFX20TS U1663 ( .A(n2165), .Y(n1057) );
NAND2X8TS U1664 ( .A(n2157), .B(n2159), .Y(n993) );
BUFX6TS U1665 ( .A(n2154), .Y(n994) );
NOR2X8TS U1666 ( .A(n2319), .B(n2318), .Y(n2317) );
NAND2X8TS U1667 ( .A(n1677), .B(n1676), .Y(n2319) );
NAND2X8TS U1668 ( .A(n995), .B(n1418), .Y(n1417) );
NAND2X8TS U1669 ( .A(n1064), .B(n2792), .Y(n995) );
OAI21X4TS U1670 ( .A0(n3113), .A1(n1669), .B0(DMP_SFG[1]), .Y(n1670) );
INVX6TS U1671 ( .A(n2276), .Y(n2253) );
AOI21X4TS U1672 ( .A0(n2267), .A1(n991), .B0(n2266), .Y(n2268) );
NAND4X2TS U1673 ( .A(n1874), .B(n1873), .C(n1872), .D(n1871), .Y(n1878) );
NOR2X6TS U1674 ( .A(n1542), .B(n2209), .Y(n1834) );
CLKBUFX2TS U1675 ( .A(DMP_SFG[3]), .Y(n996) );
NOR2X8TS U1676 ( .A(n1163), .B(n1845), .Y(n1162) );
NAND2X8TS U1677 ( .A(n997), .B(n1149), .Y(n1035) );
NAND2X8TS U1678 ( .A(n978), .B(n1150), .Y(n997) );
INVX12TS U1679 ( .A(n1101), .Y(n1525) );
NAND2X8TS U1680 ( .A(n1793), .B(n1040), .Y(n1849) );
NOR2X6TS U1681 ( .A(n2367), .B(n2356), .Y(n2357) );
CLKINVX6TS U1682 ( .A(n998), .Y(n1486) );
NAND3X8TS U1683 ( .A(n1472), .B(n1149), .C(n1406), .Y(n998) );
CLKINVX12TS U1684 ( .A(n999), .Y(n1759) );
NAND2X8TS U1685 ( .A(n1525), .B(n2994), .Y(n999) );
NAND2X4TS U1686 ( .A(n1000), .B(n1151), .Y(n1150) );
NOR2X4TS U1687 ( .A(n1001), .B(n1759), .Y(n1000) );
INVX1TS U1688 ( .A(n1763), .Y(n1312) );
NAND2X8TS U1689 ( .A(n1007), .B(n2981), .Y(n1763) );
OAI22X4TS U1690 ( .A0(n2665), .A1(DMP_SFG[4]), .B0(DMP_SFG[5]), .B1(n1543),
.Y(n1167) );
NAND2X8TS U1691 ( .A(n1476), .B(n1258), .Y(n1454) );
NOR2X8TS U1692 ( .A(n1758), .B(n1757), .Y(n1512) );
NAND4X8TS U1693 ( .A(n1010), .B(n1754), .C(n1009), .D(n1753), .Y(n1758) );
NAND3X8TS U1694 ( .A(n1476), .B(n1541), .C(n1743), .Y(n1009) );
NAND3X8TS U1695 ( .A(n1117), .B(n1149), .C(n1747), .Y(n1010) );
NOR2X8TS U1696 ( .A(n1512), .B(n1611), .Y(n1121) );
NOR2X8TS U1697 ( .A(n1119), .B(n1249), .Y(n1730) );
BUFX6TS U1698 ( .A(n2996), .Y(n1011) );
INVX8TS U1699 ( .A(n1849), .Y(n1852) );
OR3X8TS U1700 ( .A(n1462), .B(n2431), .C(n1461), .Y(n1459) );
BUFX20TS U1701 ( .A(n2055), .Y(n2160) );
BUFX6TS U1702 ( .A(n2813), .Y(n1012) );
AOI22X4TS U1703 ( .A0(n1220), .A1(n2786), .B0(n2785), .B1(n1219), .Y(n1783)
);
NAND2X4TS U1704 ( .A(n2329), .B(n1264), .Y(n2075) );
BUFX6TS U1705 ( .A(n1534), .Y(n1015) );
OAI21X4TS U1706 ( .A0(n1016), .A1(n1978), .B0(n1977), .Y(n1621) );
AOI21X4TS U1707 ( .A0(n1968), .A1(n1967), .B0(n1966), .Y(n1016) );
OAI2BB1X4TS U1708 ( .A0N(n1805), .A1N(n1117), .B0(n2428), .Y(n1106) );
CLKINVX12TS U1709 ( .A(n1045), .Y(n1056) );
OR2X8TS U1710 ( .A(n1112), .B(n2460), .Y(n2444) );
NAND3X8TS U1711 ( .A(n2446), .B(n2445), .C(n2444), .Y(n3092) );
BUFX20TS U1712 ( .A(n1559), .Y(n1112) );
XOR2X4TS U1713 ( .A(n1018), .B(n1017), .Y(n2241) );
OAI21X4TS U1714 ( .A0(n2247), .A1(n2246), .B0(n2103), .Y(n1018) );
XOR2X4TS U1715 ( .A(DmP_mant_SFG_SWR[19]), .B(n3034), .Y(n2231) );
INVX4TS U1716 ( .A(n2274), .Y(n2286) );
OAI21X4TS U1717 ( .A0(n1870), .A1(n3001), .B0(n1019), .Y(n524) );
MXI2X4TS U1718 ( .A(n3152), .B(n2730), .S0(n3000), .Y(n528) );
AOI2BB2X4TS U1719 ( .B0(n2775), .B1(n1221), .A0N(n1222), .A1N(n2774), .Y(
n1705) );
AOI2BB2X4TS U1720 ( .B0(n2512), .B1(n2614), .A0N(n1710), .A1N(n3074), .Y(
n1867) );
CLKINVX12TS U1721 ( .A(LZD_output_NRM2_EW[1]), .Y(n1498) );
OAI2BB1X4TS U1722 ( .A0N(n2503), .A1N(n2530), .B0(n2378), .Y(n2379) );
NOR2X4TS U1723 ( .A(n1515), .B(n2740), .Y(n1514) );
OAI21X4TS U1724 ( .A0(n2470), .A1(n1025), .B0(n1024), .Y(n2473) );
NAND2BX4TS U1725 ( .AN(n2471), .B(n1025), .Y(n1024) );
OAI21X4TS U1726 ( .A0(n3132), .A1(n2571), .B0(n1026), .Y(n589) );
NAND2X4TS U1727 ( .A(n1484), .B(n1262), .Y(n1750) );
NAND2X8TS U1728 ( .A(n1255), .B(n2317), .Y(n1689) );
AOI21X4TS U1729 ( .A0(n2897), .A1(n1201), .B0(n1028), .Y(n1824) );
AOI2BB2X4TS U1730 ( .B0(n1814), .B1(n1484), .A0N(n1316), .A1N(n1153), .Y(
n3094) );
NOR2X8TS U1731 ( .A(n2486), .B(n1831), .Y(n2214) );
AND2X8TS U1732 ( .A(n1599), .B(n2548), .Y(n3096) );
NAND2X4TS U1733 ( .A(n1664), .B(DMP_EXP_EWSW[24]), .Y(n2301) );
XOR2X4TS U1734 ( .A(n2314), .B(n2313), .Y(n2316) );
MXI2X4TS U1735 ( .A(n2316), .B(n2315), .S0(n2561), .Y(n824) );
OAI2BB1X4TS U1736 ( .A0N(n1455), .A1N(n1806), .B0(n2427), .Y(n1107) );
NAND2X6TS U1737 ( .A(n1488), .B(Raw_mant_NRM_SWR[10]), .Y(n2427) );
OR2X8TS U1738 ( .A(n2914), .B(n1505), .Y(n2409) );
AND2X8TS U1739 ( .A(n2160), .B(intDY_EWSW[25]), .Y(n1355) );
AOI21X4TS U1740 ( .A0(n2898), .A1(n1188), .B0(n1029), .Y(n1863) );
MXI2X2TS U1741 ( .A(n2303), .B(n2727), .S0(n2561), .Y(n826) );
NOR2X8TS U1742 ( .A(DMP_EXP_EWSW[24]), .B(n1664), .Y(n2299) );
NAND3X6TS U1743 ( .A(n2199), .B(n2198), .C(n2197), .Y(n795) );
BUFX20TS U1744 ( .A(n1472), .Y(n1117) );
NAND3X8TS U1745 ( .A(n1031), .B(n1158), .C(n1161), .Y(n1030) );
NOR2X8TS U1746 ( .A(n1166), .B(n1032), .Y(n1031) );
NAND2X2TS U1747 ( .A(n2541), .B(n1600), .Y(n3072) );
INVX16TS U1748 ( .A(n1598), .Y(n1600) );
NAND3X6TS U1749 ( .A(n2448), .B(n2450), .C(n2449), .Y(n2541) );
INVX16TS U1750 ( .A(n1559), .Y(n1544) );
NAND2X4TS U1751 ( .A(n2203), .B(n1348), .Y(n2072) );
NAND3X8TS U1752 ( .A(n1622), .B(n1619), .C(n1068), .Y(n1997) );
XNOR2X4TS U1753 ( .A(n1319), .B(n1256), .Y(n1034) );
AOI21X2TS U1754 ( .A0(n1924), .A1(n1923), .B0(n1922), .Y(n1934) );
NAND2X8TS U1755 ( .A(n1409), .B(n1358), .Y(n1503) );
INVX12TS U1756 ( .A(n1035), .Y(n1099) );
NAND2X8TS U1757 ( .A(n1622), .B(n1619), .Y(n1067) );
NOR2X6TS U1758 ( .A(n2996), .B(n3061), .Y(n1845) );
CLKINVX12TS U1759 ( .A(n1519), .Y(n1856) );
NAND2X2TS U1760 ( .A(n1599), .B(n3066), .Y(n3051) );
NAND2X2TS U1761 ( .A(n1599), .B(n2455), .Y(n3044) );
NAND2X6TS U1762 ( .A(n1671), .B(n1670), .Y(n1677) );
NAND3X4TS U1763 ( .A(n1752), .B(n1751), .C(n1750), .Y(n1753) );
NAND2X4TS U1764 ( .A(DMP_SFG[5]), .B(n2209), .Y(n1839) );
INVX6TS U1765 ( .A(n1854), .Y(n2997) );
NOR2X2TS U1766 ( .A(n2312), .B(n2311), .Y(n2313) );
NOR3X4TS U1767 ( .A(n2209), .B(n2946), .C(n1063), .Y(n1160) );
MXI2X4TS U1768 ( .A(n2323), .B(n2677), .S0(n2601), .Y(n569) );
NAND2X2TS U1769 ( .A(n2156), .B(DmP_EXP_EWSW[4]), .Y(n2127) );
NOR2X8TS U1770 ( .A(n1036), .B(n1620), .Y(n1619) );
AND2X8TS U1771 ( .A(n1621), .B(n1625), .Y(n1036) );
NOR2X6TS U1772 ( .A(n1164), .B(n1843), .Y(n1163) );
NAND2X4TS U1773 ( .A(n1544), .B(n2565), .Y(n2407) );
NAND2X8TS U1774 ( .A(n2227), .B(DP_OP_297J37_122_8400_n136), .Y(n1445) );
NAND2X6TS U1775 ( .A(n1853), .B(n1640), .Y(n2227) );
BUFX6TS U1776 ( .A(n2993), .Y(n1037) );
AND2X8TS U1777 ( .A(n1057), .B(n1059), .Y(n1354) );
NAND2X4TS U1778 ( .A(n1841), .B(n984), .Y(n2217) );
NOR2X8TS U1779 ( .A(n1038), .B(n1995), .Y(n1625) );
NAND2X8TS U1780 ( .A(n1646), .B(n1987), .Y(n1038) );
AOI21X4TS U1781 ( .A0(n1448), .A1(n1063), .B0(n1039), .Y(n1447) );
AOI21X4TS U1782 ( .A0(n1847), .A1(n1848), .B0(n1550), .Y(n1039) );
NAND2X6TS U1783 ( .A(n2790), .B(n2791), .Y(n1418) );
AOI21X4TS U1784 ( .A0(n1672), .A1(n1673), .B0(n1041), .Y(n1674) );
NAND2X8TS U1785 ( .A(n1433), .B(n1638), .Y(n1432) );
OAI21X4TS U1786 ( .A0(n2259), .A1(n2284), .B0(n2258), .Y(n1434) );
CLKINVX6TS U1787 ( .A(n1054), .Y(n1847) );
NOR3X8TS U1788 ( .A(n1758), .B(n1757), .C(n1507), .Y(n3110) );
CLKINVX12TS U1789 ( .A(n1521), .Y(n1488) );
NAND2X8TS U1790 ( .A(n976), .B(n1812), .Y(n1521) );
BUFX8TS U1791 ( .A(n1763), .Y(n1045) );
NAND2X8TS U1792 ( .A(n2483), .B(n1053), .Y(n1831) );
BUFX16TS U1793 ( .A(n2056), .Y(n2203) );
OR2X8TS U1794 ( .A(n1050), .B(n942), .Y(n1835) );
XNOR2X4TS U1795 ( .A(n536), .B(n2995), .Y(n2991) );
MXI2X8TS U1796 ( .A(n3136), .B(n1721), .S0(n3000), .Y(n536) );
NAND2X8TS U1797 ( .A(n2160), .B(intDY_EWSW[13]), .Y(n2114) );
NAND2X8TS U1798 ( .A(n2112), .B(n2114), .Y(n1551) );
BUFX6TS U1799 ( .A(intDY_EWSW[22]), .Y(n1047) );
INVX12TS U1800 ( .A(n1804), .Y(n1149) );
BUFX6TS U1801 ( .A(DMP_exp_NRM2_EW[2]), .Y(n1048) );
NAND2X4TS U1802 ( .A(n2490), .B(n2241), .Y(n2104) );
NOR2X2TS U1803 ( .A(n1888), .B(n1887), .Y(n1911) );
MXI2X2TS U1804 ( .A(n2586), .B(n2741), .S0(n2601), .Y(n574) );
AND3X8TS U1805 ( .A(n2214), .B(n2321), .C(n1840), .Y(n1255) );
XOR2X2TS U1806 ( .A(n2583), .B(n3113), .Y(n2585) );
XNOR2X4TS U1807 ( .A(n1047), .B(n1369), .Y(n1885) );
NOR2X6TS U1808 ( .A(n1160), .B(n1159), .Y(n1158) );
CLKXOR2X2TS U1809 ( .A(n3034), .B(DmP_mant_SFG_SWR[25]), .Y(n1414) );
OAI21X4TS U1810 ( .A0(n1934), .A1(n1933), .B0(n1051), .Y(n1628) );
AOI21X4TS U1811 ( .A0(n1931), .A1(n1932), .B0(n1930), .Y(n1051) );
NOR2X8TS U1812 ( .A(n2674), .B(n1386), .Y(n1962) );
NAND2X8TS U1813 ( .A(n2160), .B(n1562), .Y(n2159) );
NAND2X8TS U1814 ( .A(n3059), .B(n3060), .Y(n1840) );
AOI22X4TS U1815 ( .A0(n2998), .A1(DmP_mant_SHT1_SW[2]), .B0(n981), .B1(
DmP_mant_SHT1_SW[3]), .Y(n3042) );
NAND2X8TS U1816 ( .A(n1695), .B(n1052), .Y(n852) );
BUFX12TS U1817 ( .A(n2484), .Y(n1053) );
OAI22X4TS U1818 ( .A0(DMP_SFG[7]), .A1(n2666), .B0(n2813), .B1(DMP_SFG[9]),
.Y(n1054) );
AOI2BB2X4TS U1819 ( .B0(n2015), .B1(n1154), .A0N(n1280), .A1N(n2677), .Y(
n3073) );
NOR2X8TS U1820 ( .A(n1763), .B(n1469), .Y(n1802) );
INVX6TS U1821 ( .A(n1630), .Y(n1629) );
NAND2X8TS U1822 ( .A(n1506), .B(n989), .Y(n2443) );
NAND2X6TS U1823 ( .A(n1352), .B(n1600), .Y(n3106) );
NOR2X8TS U1824 ( .A(n1949), .B(n1935), .Y(n1937) );
AOI22X4TS U1825 ( .A0(n2512), .A1(n835), .B0(n2465), .B1(n839), .Y(n2469) );
AOI22X4TS U1826 ( .A0(n2474), .A1(n1606), .B0(n2580), .B1(n2499), .Y(n3116)
);
NAND2X6TS U1827 ( .A(n1684), .B(n2634), .Y(n1841) );
AND3X6TS U1828 ( .A(n2946), .B(n2662), .C(n1420), .Y(n1159) );
INVX6TS U1829 ( .A(n2377), .Y(n3074) );
NOR2X8TS U1830 ( .A(n1804), .B(n1114), .Y(n1812) );
NAND2X8TS U1831 ( .A(n1802), .B(n1455), .Y(n1804) );
AOI22X4TS U1832 ( .A0(n2500), .A1(n1606), .B0(n2578), .B1(n2499), .Y(n2501)
);
NAND2X4TS U1833 ( .A(n3092), .B(n1599), .Y(n3075) );
BUFX6TS U1834 ( .A(intDX_EWSW[28]), .Y(n1059) );
BUFX6TS U1835 ( .A(intDY_EWSW[18]), .Y(n1060) );
OAI2BB1X4TS U1836 ( .A0N(underflow_flag), .A1N(n3035), .B0(n2559), .Y(n620)
);
AOI22X4TS U1837 ( .A0(DmP_mant_SHT1_SW[13]), .A1(n2998), .B0(n981), .B1(
DmP_mant_SHT1_SW[14]), .Y(n3062) );
NOR2X8TS U1838 ( .A(n1061), .B(n2080), .Y(n2247) );
AND2X8TS U1839 ( .A(n2081), .B(n2085), .Y(n1061) );
OR2X8TS U1840 ( .A(n1694), .B(n1062), .Y(n844) );
OAI2BB1X4TS U1841 ( .A0N(n1219), .A1N(n2809), .B0(n1421), .Y(n1062) );
OAI22X4TS U1842 ( .A0(n2207), .A1(n1508), .B0(n2345), .B1(n3104), .Y(n2208)
);
AOI21X4TS U1843 ( .A0(n1599), .A1(n2543), .B0(n2208), .Y(n3046) );
NAND4X4TS U1844 ( .A(n2218), .B(n2217), .C(n2216), .D(n2215), .Y(n2219) );
OAI21X4TS U1845 ( .A0(n2222), .A1(n2601), .B0(n1065), .Y(n582) );
MXI2X4TS U1846 ( .A(n3128), .B(n2666), .S0(n2571), .Y(n558) );
BUFX12TS U1847 ( .A(n1650), .Y(n1066) );
NAND2X8TS U1848 ( .A(n1067), .B(Shift_reg_FLAGS_7_6), .Y(n1555) );
OAI22X4TS U1849 ( .A0(n1949), .A1(n1948), .B0(intDY_EWSW[13]), .B1(n1069),
.Y(n1954) );
NOR2X8TS U1850 ( .A(n2679), .B(n1362), .Y(n1949) );
NAND2BX4TS U1851 ( .AN(n1072), .B(n1740), .Y(n839) );
AOI22X4TS U1852 ( .A0(n851), .A1(n2509), .B0(n2511), .B1(n2577), .Y(n1077)
);
NAND3X8TS U1853 ( .A(n1078), .B(n2391), .C(n2390), .Y(n2577) );
AND2X8TS U1854 ( .A(n1363), .B(n2389), .Y(n1078) );
NAND4X8TS U1855 ( .A(n1374), .B(n1375), .C(n1185), .D(n970), .Y(n851) );
AOI21X4TS U1856 ( .A0(n1090), .A1(n1830), .B0(n1416), .Y(n1081) );
OAI2BB1X4TS U1857 ( .A0N(n1080), .A1N(n1086), .B0(n1083), .Y(n2487) );
NOR2X8TS U1858 ( .A(n2485), .B(n1416), .Y(n1087) );
NOR2X8TS U1859 ( .A(n1091), .B(n1046), .Y(n1090) );
OAI21X4TS U1860 ( .A0(n1089), .A1(n1830), .B0(n1829), .Y(n2322) );
OAI21X4TS U1861 ( .A0(n2536), .A1(n3071), .B0(n1779), .Y(n1780) );
MXI2X4TS U1862 ( .A(n3118), .B(n1037), .S0(n3001), .Y(n563) );
NAND2X4TS U1863 ( .A(n2381), .B(n2506), .Y(n2376) );
NAND4X8TS U1864 ( .A(n1509), .B(n2986), .C(n1092), .D(n2918), .Y(n1111) );
NAND2X8TS U1865 ( .A(n2920), .B(n2919), .Y(n1092) );
NAND2X8TS U1866 ( .A(n2988), .B(n2987), .Y(n1509) );
NAND2X8TS U1867 ( .A(n1092), .B(n2918), .Y(n1101) );
NAND3X8TS U1868 ( .A(n1096), .B(n1094), .C(n1095), .Y(n1559) );
NOR2X8TS U1869 ( .A(n1486), .B(n1097), .Y(n1096) );
NAND2X8TS U1870 ( .A(n1501), .B(n1098), .Y(n1097) );
NAND2X8TS U1871 ( .A(n1116), .B(n1044), .Y(n1151) );
INVX16TS U1872 ( .A(n1100), .Y(n2984) );
NAND2X8TS U1873 ( .A(n1509), .B(n2986), .Y(n1100) );
BUFX6TS U1874 ( .A(n2427), .Y(n1102) );
NAND2X8TS U1875 ( .A(n1503), .B(n2560), .Y(n1519) );
NAND2X8TS U1876 ( .A(n1396), .B(n1856), .Y(n2174) );
AOI2BB2X4TS U1877 ( .B0(n1356), .B1(n1474), .A0N(n1521), .A1N(n1813), .Y(
n2421) );
NOR2X8TS U1878 ( .A(n1111), .B(n1110), .Y(n1109) );
NAND2X8TS U1879 ( .A(n1456), .B(n2924), .Y(n2923) );
NOR2X8TS U1880 ( .A(n1764), .B(n1299), .Y(n1455) );
NOR2X8TS U1881 ( .A(n988), .B(n1119), .Y(n1115) );
BUFX6TS U1882 ( .A(n1119), .Y(n1116) );
NAND2X8TS U1883 ( .A(n1120), .B(n2915), .Y(n1119) );
NOR2X2TS U1884 ( .A(n1113), .B(Raw_mant_NRM_SWR[14]), .Y(n1118) );
NOR2X8TS U1885 ( .A(n1487), .B(n1762), .Y(n1472) );
INVX12TS U1886 ( .A(n1121), .Y(n1598) );
INVX16TS U1887 ( .A(n1701), .Y(n1179) );
NAND2X8TS U1888 ( .A(n2802), .B(n2801), .Y(n1701) );
AOI22X4TS U1889 ( .A0(n2518), .A1(n1592), .B0(n2516), .B1(n1023), .Y(n3156)
);
OR2X8TS U1890 ( .A(n1819), .B(n1124), .Y(n842) );
NAND2X8TS U1891 ( .A(n1820), .B(n1127), .Y(n846) );
AND2X8TS U1892 ( .A(n1821), .B(n1128), .Y(n1127) );
NAND3X8TS U1893 ( .A(n1783), .B(n1784), .C(n1782), .Y(n838) );
BUFX6TS U1894 ( .A(n2352), .Y(n1132) );
NAND4X8TS U1895 ( .A(n1136), .B(n1135), .C(n1145), .D(n1285), .Y(n2352) );
NAND4X8TS U1896 ( .A(n1139), .B(n1137), .C(n1138), .D(n1776), .Y(n2524) );
AOI22X4TS U1897 ( .A0(n1199), .A1(n2896), .B0(n1196), .B1(n2869), .Y(n1145)
);
AND2X8TS U1898 ( .A(n1142), .B(n2968), .Y(n1139) );
NOR2BX4TS U1899 ( .AN(n2872), .B(n1141), .Y(n1140) );
AOI22X4TS U1900 ( .A0(n1194), .A1(n1217), .B0(n1195), .B1(n1043), .Y(n1142)
);
NAND2X8TS U1901 ( .A(n1179), .B(n2888), .Y(n1146) );
NOR2BX4TS U1902 ( .AN(n2882), .B(n935), .Y(n1147) );
BUFX16TS U1903 ( .A(n3110), .Y(n1154) );
INVX12TS U1904 ( .A(n3110), .Y(n1508) );
NOR2X8TS U1905 ( .A(n1155), .B(n1099), .Y(n1409) );
NAND2BX2TS U1906 ( .AN(n1157), .B(n3091), .Y(n1156) );
OAI21X4TS U1907 ( .A0(n1844), .A1(n1165), .B0(n1162), .Y(n1161) );
NOR2X8TS U1908 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n1843) );
NAND3X4TS U1909 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .C(n1063), .Y(
n1164) );
NOR2X4TS U1910 ( .A(n2667), .B(DMP_SFG[3]), .Y(n1844) );
AND2X8TS U1911 ( .A(n1167), .B(n2977), .Y(n1166) );
AOI22X4TS U1912 ( .A0(n1170), .A1(n2503), .B0(n2499), .B1(n838), .Y(n2368)
);
NAND2X8TS U1913 ( .A(n2366), .B(n1171), .Y(n1170) );
AOI22X4TS U1914 ( .A0(n1179), .A1(n1199), .B0(n1202), .B1(n2869), .Y(n1177)
);
NOR2BX4TS U1915 ( .AN(n936), .B(n2781), .Y(n1173) );
NAND2BX4TS U1916 ( .AN(n1176), .B(n2782), .Y(n1175) );
NAND2X4TS U1917 ( .A(n1599), .B(n2015), .Y(n3048) );
OAI22X4TS U1918 ( .A0(n1929), .A1(n1426), .B0(n951), .B1(n1361), .Y(n1930)
);
AOI22X4TS U1919 ( .A0(n1179), .A1(n2899), .B0(n1195), .B1(n1217), .Y(n2390)
);
NAND2X2TS U1920 ( .A(n2490), .B(n1180), .Y(n1607) );
NAND3X6TS U1921 ( .A(n1495), .B(n1496), .C(n1400), .Y(n1180) );
NOR2X6TS U1922 ( .A(n1481), .B(n1275), .Y(n1480) );
NAND2X2TS U1923 ( .A(n2160), .B(n1278), .Y(n2032) );
NAND3BX2TS U1924 ( .AN(n1319), .B(n1637), .C(n980), .Y(n1632) );
AOI22X1TS U1925 ( .A0(n1220), .A1(n1182), .B0(n2787), .B1(n1218), .Y(n1740)
);
AOI2BB2X4TS U1926 ( .B0(n2778), .B1(n1221), .A0N(n1222), .A1N(n1183), .Y(
n1776) );
AOI2BB2X4TS U1927 ( .B0(n2869), .B1(n1205), .A0N(n1862), .A1N(n2894), .Y(
n1782) );
AOI22X4TS U1928 ( .A0(n1043), .A1(n1198), .B0(n1210), .B1(n2873), .Y(n2389)
);
AOI22X4TS U1929 ( .A0(n1043), .A1(n1207), .B0(n2881), .B1(n2880), .Y(n1697)
);
AOI22X4TS U1930 ( .A0(n2820), .A1(n1197), .B0(n2878), .B1(n2877), .Y(n1703)
);
AO22X4TS U1931 ( .A0(n1204), .A1(n2869), .B0(n1184), .B1(n2883), .Y(n1186)
);
BUFX16TS U1932 ( .A(n2823), .Y(n1862) );
OAI22X1TS U1933 ( .A0(n2816), .A1(n1192), .B0(n2815), .B1(n2814), .Y(n1866)
);
AOI2BB2X4TS U1934 ( .B0(n2843), .B1(n1190), .A0N(n2842), .A1N(n1193), .Y(
n1772) );
OAI22X2TS U1935 ( .A0(n1193), .A1(n2855), .B0(n2854), .B1(n1191), .Y(n1696)
);
OAI22X2TS U1936 ( .A0(n1227), .A1(n2960), .B0(n1223), .B1(n2959), .Y(
final_result_ieee[1]) );
INVX2TS U1937 ( .A(final_result_ieee[1]), .Y(n1211) );
OAI22X1TS U1938 ( .A0(n1226), .A1(n1212), .B0(n1223), .B1(n2948), .Y(
final_result_ieee[20]) );
OAI21X2TS U1939 ( .A0(n2851), .A1(n1214), .B0(n2850), .Y(n1864) );
AOI22X4TS U1940 ( .A0(n2807), .A1(n1182), .B0(n2806), .B1(n1218), .Y(n1818)
);
AOI22X4TS U1941 ( .A0(n2805), .A1(n2804), .B0(n2803), .B1(n1219), .Y(n1821)
);
OAI2BB1X4TS U1942 ( .A0N(n2810), .A1N(n2811), .B0(n2949), .Y(n1422) );
AOI22X1TS U1943 ( .A0(n1220), .A1(n2784), .B0(n2783), .B1(n1218), .Y(n1738)
);
OAI22X2TS U1944 ( .A0(n1222), .A1(n2819), .B0(n2818), .B1(n2817), .Y(n1773)
);
NAND2X4TS U1945 ( .A(n2365), .B(n2481), .Y(n1858) );
NAND2X6TS U1946 ( .A(n2980), .B(n2979), .Y(n1471) );
OAI2BB1X4TS U1947 ( .A0N(n2929), .A1N(n2928), .B0(n2927), .Y(n1517) );
NAND3X4TS U1948 ( .A(n1799), .B(n1397), .C(n1262), .Y(n1751) );
NAND2X8TS U1949 ( .A(n1470), .B(n2927), .Y(n1469) );
NAND2X8TS U1950 ( .A(n1506), .B(n1524), .Y(n2446) );
AOI2BB2X4TS U1951 ( .B0(n2905), .B1(n2904), .A0N(n1587), .A1N(n971), .Y(
n1816) );
AOI22X4TS U1952 ( .A0(n2911), .A1(n2910), .B0(n986), .B1(n2909), .Y(n1741)
);
AOI2BB2X4TS U1953 ( .B0(n2777), .B1(n1221), .A0N(n2776), .A1N(n1181), .Y(
n2391) );
OAI22X4TS U1954 ( .A0(n2507), .A1(n2535), .B0(n2359), .B1(n2536), .Y(n1419)
);
NAND3X6TS U1955 ( .A(n1231), .B(n1230), .C(n1229), .Y(n791) );
NAND2X1TS U1956 ( .A(n2161), .B(n622), .Y(n2068) );
NAND3X2TS U1957 ( .A(n1234), .B(n1233), .C(n1232), .Y(n622) );
NAND2X1TS U1958 ( .A(n2161), .B(n624), .Y(n2012) );
NAND3X2TS U1959 ( .A(n1681), .B(DMP_SFG[2]), .C(n1680), .Y(n1683) );
AND2X4TS U1960 ( .A(n1678), .B(DMP_SFG[2]), .Y(n1311) );
XNOR2X2TS U1961 ( .A(n2210), .B(n1050), .Y(n2220) );
AOI22X4TS U1962 ( .A0(n2789), .A1(n1188), .B0(n2788), .B1(n1219), .Y(n1855)
);
BUFX3TS U1963 ( .A(n1545), .Y(n1245) );
MXI2X4TS U1964 ( .A(n3138), .B(n1546), .S0(n2571), .Y(n535) );
MXI2X4TS U1965 ( .A(n2456), .B(n2457), .S0(n1592), .Y(n2459) );
NAND2X6TS U1966 ( .A(n974), .B(n1483), .Y(n2436) );
NOR2X2TS U1967 ( .A(n2724), .B(Raw_mant_NRM_SWR[4]), .Y(n1755) );
INVX2TS U1968 ( .A(n1335), .Y(n1879) );
NOR2X4TS U1969 ( .A(n2664), .B(n2437), .Y(n2548) );
OAI21X2TS U1970 ( .A0(n1746), .A1(n2627), .B0(n1742), .Y(n1743) );
NAND3X6TS U1971 ( .A(n2436), .B(n1102), .C(n1482), .Y(n1481) );
CLKINVX6TS U1972 ( .A(n1257), .Y(n1713) );
NAND2X2TS U1973 ( .A(n2156), .B(DmP_EXP_EWSW[3]), .Y(n2157) );
NAND2X2TS U1974 ( .A(n2214), .B(n2213), .Y(n2216) );
NAND2X2TS U1975 ( .A(n2557), .B(n2101), .Y(n1500) );
NAND2X2TS U1976 ( .A(n2466), .B(n2517), .Y(n2386) );
NOR2X4TS U1977 ( .A(n1511), .B(n1609), .Y(n1510) );
CLKBUFX2TS U1978 ( .A(n2616), .Y(n1359) );
INVX2TS U1979 ( .A(n1581), .Y(n1526) );
NAND2X2TS U1980 ( .A(n1326), .B(n1278), .Y(n1528) );
NOR2X4TS U1981 ( .A(n1558), .B(n1294), .Y(n1939) );
NAND2X4TS U1982 ( .A(n2668), .B(n1284), .Y(n1980) );
INVX2TS U1983 ( .A(n1386), .Y(n1387) );
NOR3X4TS U1984 ( .A(n1833), .B(DmP_mant_SFG_SWR[8]), .C(n1420), .Y(n1837) );
NOR3X4TS U1985 ( .A(n1834), .B(n2977), .C(n2946), .Y(n1836) );
NOR3X6TS U1986 ( .A(n1978), .B(n1643), .C(n1645), .Y(n1624) );
INVX2TS U1987 ( .A(n1390), .Y(n1850) );
NAND2X2TS U1988 ( .A(n1390), .B(n2630), .Y(n1851) );
NOR2X4TS U1989 ( .A(n2672), .B(n2562), .Y(n1673) );
INVX2TS U1990 ( .A(n1353), .Y(n1883) );
INVX2TS U1991 ( .A(n2430), .Y(n1269) );
INVX2TS U1992 ( .A(n2779), .Y(n1380) );
INVX2TS U1993 ( .A(n2578), .Y(n1775) );
INVX4TS U1994 ( .A(n1639), .Y(n1336) );
NAND2X2TS U1995 ( .A(n1604), .B(n852), .Y(n1718) );
NAND3X6TS U1996 ( .A(n2800), .B(n2799), .C(n2798), .Y(n2578) );
NAND2X4TS U1997 ( .A(n1856), .B(Raw_mant_NRM_SWR[0]), .Y(n1491) );
INVX2TS U1998 ( .A(n1333), .Y(n1334) );
OAI21X2TS U1999 ( .A0(n1608), .A1(n1344), .B0(n1735), .Y(n830) );
NOR2X1TS U2000 ( .A(n2682), .B(n2437), .Y(n2438) );
INVX2TS U2001 ( .A(n1567), .Y(n1568) );
INVX2TS U2002 ( .A(n2617), .Y(n2615) );
NAND2X4TS U2003 ( .A(n1532), .B(n1531), .Y(n601) );
MXI2X4TS U2004 ( .A(n3122), .B(n992), .S0(n2539), .Y(n566) );
INVX2TS U2005 ( .A(n2492), .Y(n1653) );
MXI2X1TS U2006 ( .A(n2477), .B(final_result_ieee[27]), .S0(n2723), .Y(n2478)
);
MX2X1TS U2007 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n985), .Y(n613)
);
OAI2BB1X2TS U2008 ( .A0N(final_result_ieee[30]), .A1N(n2723), .B0(n2104),
.Y(n815) );
CLKBUFX3TS U2009 ( .A(n1589), .Y(n3031) );
NAND2X2TS U2010 ( .A(n1504), .B(n1154), .Y(n3102) );
OR2X4TS U2011 ( .A(n2174), .B(n2460), .Y(n3084) );
CLKINVX3TS U2012 ( .A(rst), .Y(n1588) );
AOI22X1TS U2013 ( .A0(n2548), .A1(DmP_mant_SHT1_SW[2]), .B0(n3080), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2440) );
NAND2X4TS U2014 ( .A(n1058), .B(n2565), .Y(n2413) );
CLKBUFX3TS U2015 ( .A(n3003), .Y(n2749) );
NAND2X2TS U2016 ( .A(n3085), .B(n1154), .Y(n3086) );
CLKBUFX3TS U2017 ( .A(n3011), .Y(n2763) );
INVX2TS U2018 ( .A(rst), .Y(n1601) );
BUFX3TS U2019 ( .A(n1616), .Y(n3004) );
CLKBUFX3TS U2020 ( .A(n1616), .Y(n1596) );
INVX2TS U2021 ( .A(rst), .Y(n1594) );
BUFX3TS U2022 ( .A(n3031), .Y(n3030) );
CLKBUFX3TS U2023 ( .A(n1616), .Y(n1597) );
NAND2X1TS U2024 ( .A(n2715), .B(DMP_EXP_EWSW[15]), .Y(n2194) );
NAND2X2TS U2025 ( .A(n2175), .B(n1557), .Y(n2035) );
OAI21X2TS U2026 ( .A0(n2314), .A1(n2311), .B0(n2310), .Y(n2225) );
XNOR2X4TS U2027 ( .A(n1246), .B(n1247), .Y(n1649) );
AO21X4TS U2028 ( .A0(n1319), .A1(n2235), .B0(n1393), .Y(n1246) );
XOR2X4TS U2029 ( .A(n2248), .B(n1248), .Y(n2479) );
XNOR2X2TS U2030 ( .A(n1341), .B(intDX_EWSW[8]), .Y(n1903) );
NOR2X8TS U2031 ( .A(n1342), .B(n1288), .Y(n1938) );
XOR2X4TS U2032 ( .A(n3061), .B(n1011), .Y(n2321) );
OAI22X4TS U2033 ( .A0(n1268), .A1(n1200), .B0(n1209), .B1(n1206), .Y(n1257)
);
NOR2X8TS U2034 ( .A(n1728), .B(n1477), .Y(n1258) );
NAND2X4TS U2035 ( .A(n2426), .B(n2425), .Y(n828) );
NAND3X4TS U2036 ( .A(n2164), .B(n2163), .C(n2162), .Y(n621) );
NAND3X4TS U2037 ( .A(n2149), .B(n2150), .C(n2148), .Y(n629) );
AND2X8TS U2038 ( .A(n1631), .B(n1259), .Y(n1654) );
NAND4X4TS U2039 ( .A(n1840), .B(n2211), .C(n2212), .D(n2213), .Y(n1688) );
INVX6TS U2040 ( .A(n2486), .Y(n2212) );
NAND2X8TS U2041 ( .A(n1403), .B(n1048), .Y(n2092) );
NOR2X8TS U2042 ( .A(n2347), .B(n2346), .Y(n3128) );
OA21X4TS U2043 ( .A0(n2286), .A1(n2269), .B0(n2268), .Y(n1401) );
NAND3BX2TS U2044 ( .AN(n1336), .B(n1319), .C(n2497), .Y(n1633) );
NAND3X4TS U2045 ( .A(n1632), .B(n1633), .C(n1634), .Y(n2498) );
NAND3X6TS U2046 ( .A(n1480), .B(n2435), .C(n1408), .Y(n1479) );
NAND2X6TS U2047 ( .A(n1650), .B(n1516), .Y(n1280) );
MXI2X8TS U2048 ( .A(n1543), .B(n3124), .S0(n1385), .Y(n547) );
NAND2X8TS U2049 ( .A(n1556), .B(DP_OP_297J37_122_8400_n137), .Y(n1446) );
BUFX16TS U2050 ( .A(n2056), .Y(n1590) );
NOR2X4TS U2051 ( .A(n1929), .B(n1926), .Y(n1931) );
NAND2X6TS U2052 ( .A(n1937), .B(n1953), .Y(n1956) );
INVX6TS U2053 ( .A(n1266), .Y(n1267) );
BUFX12TS U2054 ( .A(n1701), .Y(n1268) );
NOR2X8TS U2055 ( .A(n1654), .B(n1657), .Y(n1656) );
NAND2X2TS U2056 ( .A(n1600), .B(n1504), .Y(n3101) );
XOR2X4TS U2057 ( .A(DmP_mant_SFG_SWR[4]), .B(n1576), .Y(n1678) );
INVX12TS U2058 ( .A(n1575), .Y(n1576) );
NAND2X4TS U2059 ( .A(n1604), .B(n2508), .Y(n1777) );
AOI22X2TS U2060 ( .A0(n2516), .A1(n2508), .B0(n2364), .B1(n844), .Y(n1720)
);
NAND2BX2TS U2061 ( .AN(n1454), .B(n1269), .Y(n1453) );
NOR2X8TS U2062 ( .A(n2680), .B(n1561), .Y(n1981) );
MXI2X1TS U2063 ( .A(n2475), .B(final_result_ieee[29]), .S0(n2723), .Y(n2476)
);
NAND2X4TS U2064 ( .A(n1604), .B(n844), .Y(n2375) );
NAND2X4TS U2065 ( .A(n2511), .B(n842), .Y(n2360) );
AND2X8TS U2066 ( .A(n1927), .B(n1271), .Y(n1272) );
NAND2BX4TS U2067 ( .AN(n1929), .B(n1272), .Y(n1933) );
NAND2X4TS U2068 ( .A(n1940), .B(n1946), .Y(n1941) );
AOI21X4TS U2069 ( .A0(n2859), .A1(n2858), .B0(n1696), .Y(n1699) );
NAND2X2TS U2070 ( .A(n2203), .B(n1296), .Y(n2140) );
INVX8TS U2071 ( .A(n1278), .Y(n1279) );
NAND2X4TS U2072 ( .A(n1404), .B(DMP_exp_NRM2_EW[3]), .Y(n2096) );
NAND2X4TS U2073 ( .A(n1650), .B(n1516), .Y(n1515) );
INVX12TS U2074 ( .A(n1093), .Y(n1516) );
MXI2X1TS U2075 ( .A(n2479), .B(final_result_ieee[28]), .S0(n2723), .Y(n2480)
);
OAI2BB2X4TS U2076 ( .B0(n1972), .B1(n1973), .A0N(n1580), .A1N(n1357), .Y(
n1974) );
INVX12TS U2077 ( .A(Raw_mant_NRM_SWR[4]), .Y(n2542) );
NOR2X8TS U2078 ( .A(n1990), .B(n1338), .Y(n1340) );
NAND2X4TS U2079 ( .A(n1590), .B(n1328), .Y(n2017) );
NAND2X4TS U2080 ( .A(n1286), .B(n1533), .Y(n2018) );
BUFX16TS U2081 ( .A(n2056), .Y(n2175) );
NAND2X2TS U2082 ( .A(n2160), .B(n1288), .Y(n2044) );
NOR2X2TS U2083 ( .A(n1113), .B(n2921), .Y(n1805) );
NAND2X6TS U2084 ( .A(n2490), .B(n1468), .Y(n1467) );
NAND2X4TS U2085 ( .A(n2086), .B(n2092), .Y(n2087) );
OA21X4TS U2086 ( .A0(n1222), .A1(n1208), .B0(n2974), .Y(n1285) );
NOR2X4TS U2087 ( .A(n1514), .B(n1513), .Y(n3049) );
INVX16TS U2088 ( .A(n1287), .Y(n1288) );
MXI2X4TS U2089 ( .A(n3144), .B(n2733), .S0(n3000), .Y(n532) );
NAND2X2TS U2090 ( .A(n2328), .B(n1362), .Y(n2113) );
NAND2X4TS U2091 ( .A(n3093), .B(n2923), .Y(n1518) );
NAND2X6TS U2092 ( .A(n2926), .B(n2925), .Y(n1456) );
BUFX12TS U2093 ( .A(Shift_reg_FLAGS_7[2]), .Y(n2576) );
NAND2X6TS U2094 ( .A(n1628), .B(n1958), .Y(n1627) );
XNOR2X1TS U2095 ( .A(n1286), .B(n1328), .Y(n1906) );
AND2X4TS U2096 ( .A(n2328), .B(intDY_EWSW[13]), .Y(n1290) );
OR3X6TS U2097 ( .A(n1290), .B(n1291), .C(n2051), .Y(n801) );
XOR2X4TS U2098 ( .A(n555), .B(n2995), .Y(n2975) );
AOI2BB2X2TS U2099 ( .B0(n1610), .B1(n2614), .A0N(n1112), .A1N(n2613), .Y(
n3076) );
NAND2X2TS U2100 ( .A(n2607), .B(n1557), .Y(n2138) );
NAND2X4TS U2101 ( .A(n1544), .B(Raw_mant_NRM_SWR[10]), .Y(n3065) );
NAND2X8TS U2102 ( .A(n2675), .B(n2431), .Y(n1482) );
OAI2BB1X2TS U2103 ( .A0N(n1457), .A1N(n2422), .B0(n2437), .Y(n1292) );
NOR2X2TS U2104 ( .A(n2490), .B(n2489), .Y(n619) );
OAI21X4TS U2105 ( .A0(n2400), .A1(n2385), .B0(n2384), .Y(n2471) );
INVX16TS U2106 ( .A(n1631), .Y(n1293) );
NAND2X8TS U2107 ( .A(n1446), .B(n1445), .Y(n1631) );
OAI2BB1X2TS U2108 ( .A0N(n2639), .A1N(n2628), .B0(n2434), .Y(n2422) );
NAND2X6TS U2109 ( .A(n1512), .B(n1651), .Y(n1854) );
AFCSHCINX4TS U2110 ( .CI1N(DP_OP_297J37_122_8400_n142), .B(n1303), .A(n1584),
.CI0N(DP_OP_297J37_122_8400_n143), .CS(n2626), .CO1(
DP_OP_297J37_122_8400_n140), .CO0(DP_OP_297J37_122_8400_n141), .S(
Raw_mant_SGF[13]) );
NAND2X4TS U2111 ( .A(n1533), .B(n1284), .Y(n2002) );
NAND2X4TS U2112 ( .A(n1345), .B(Raw_mant_NRM_SWR[0]), .Y(n3079) );
INVX16TS U2113 ( .A(n1508), .Y(n1650) );
INVX16TS U2114 ( .A(n1598), .Y(n1599) );
NOR2X4TS U2115 ( .A(n1460), .B(n2420), .Y(n1461) );
AOI22X4TS U2116 ( .A0(n2520), .A1(n1606), .B0(n1351), .B1(n2525), .Y(n2521)
);
NAND2X2TS U2117 ( .A(n2155), .B(n1571), .Y(n2190) );
NAND2X2TS U2118 ( .A(n2175), .B(n1047), .Y(n2202) );
NAND3BX4TS U2119 ( .AN(n1310), .B(n2002), .C(n2001), .Y(n790) );
NAND2X2TS U2120 ( .A(n2155), .B(n1388), .Y(n2173) );
NAND2X4TS U2121 ( .A(n2329), .B(intDX_EWSW[31]), .Y(n2332) );
AO22X4TS U2122 ( .A0(n2666), .A1(n2633), .B0(n2813), .B1(n2630), .Y(n1846)
);
AOI2BB2X2TS U2123 ( .B0(n2612), .B1(n1610), .A0N(n1112), .A1N(n1300), .Y(
n3082) );
NAND2X2TS U2124 ( .A(n2154), .B(n987), .Y(n2059) );
INVX16TS U2125 ( .A(n1672), .Y(n3113) );
NAND2X2TS U2126 ( .A(n2175), .B(n1253), .Y(n2146) );
NAND2X2TS U2127 ( .A(n2328), .B(n1579), .Y(n2011) );
NAND2X2TS U2128 ( .A(n2155), .B(n1360), .Y(n2168) );
NAND2X2TS U2129 ( .A(n2155), .B(n1288), .Y(n2020) );
NAND2X2TS U2130 ( .A(n2175), .B(n1367), .Y(n2061) );
NAND2X2TS U2131 ( .A(n2328), .B(n1577), .Y(n2134) );
NAND2X2TS U2132 ( .A(n2175), .B(n1325), .Y(n2031) );
NAND2X4TS U2133 ( .A(n1341), .B(n2165), .Y(n2021) );
NAND2X4TS U2134 ( .A(n1057), .B(n1357), .Y(n2010) );
NAND2X4TS U2135 ( .A(n1057), .B(n1571), .Y(n2143) );
NAND2X4TS U2136 ( .A(n1369), .B(n2607), .Y(n2201) );
NAND2X4TS U2137 ( .A(n986), .B(n2862), .Y(n1820) );
NAND2X2TS U2138 ( .A(n2203), .B(intDY_EWSW[26]), .Y(n2005) );
NAND2X2TS U2139 ( .A(n2175), .B(intDY_EWSW[25]), .Y(n2008) );
AOI22X4TS U2140 ( .A0(n1605), .A1(n2452), .B0(n2466), .B1(n844), .Y(n1868)
);
NAND2X4TS U2141 ( .A(n1595), .B(n1327), .Y(n2074) );
CLKMX2X2TS U2142 ( .A(Data_X[0]), .B(n1286), .S0(n2598), .Y(n923) );
XNOR2X1TS U2143 ( .A(n1564), .B(n1296), .Y(n1894) );
XNOR2X4TS U2144 ( .A(intDY_EWSW[28]), .B(n1059), .Y(n1905) );
MX2X4TS U2145 ( .A(Data_X[28]), .B(n1059), .S0(n2599), .Y(n895) );
NAND2X8TS U2146 ( .A(n1314), .B(n980), .Y(n1315) );
INVX4TS U2147 ( .A(n3069), .Y(n2922) );
NAND2X4TS U2148 ( .A(n2511), .B(n2508), .Y(n2341) );
MXI2X4TS U2149 ( .A(n2660), .B(n2501), .S0(n1385), .Y(n578) );
AOI21X1TS U2150 ( .A0(n1606), .A1(n2383), .B0(n1780), .Y(n1324) );
NOR2X2TS U2151 ( .A(n1898), .B(n1897), .Y(n1910) );
NAND2X4TS U2152 ( .A(n1253), .B(n2154), .Y(n2183) );
MXI2X4TS U2153 ( .A(n2488), .B(n2740), .S0(n2601), .Y(n567) );
XNOR2X4TS U2154 ( .A(n1060), .B(n1273), .Y(n1881) );
NAND4X8TS U2155 ( .A(n1337), .B(n1824), .C(n2958), .D(n2957), .Y(n2401) );
XNOR2X4TS U2156 ( .A(n1792), .B(n1304), .Y(n1424) );
OR2X4TS U2157 ( .A(n2670), .B(intDX_EWSW[28]), .Y(n1339) );
AND2X8TS U2158 ( .A(n1650), .B(n1516), .Y(n1345) );
NAND2X2TS U2159 ( .A(n2165), .B(n1320), .Y(n2147) );
NAND3X6TS U2160 ( .A(n2443), .B(n2442), .C(n2441), .Y(n1352) );
CLKMX2X2TS U2161 ( .A(Data_X[6]), .B(n1348), .S0(n2597), .Y(n917) );
MX2X4TS U2162 ( .A(Data_Y[5]), .B(n1346), .S0(n2595), .Y(n884) );
NAND3BX4TS U2163 ( .AN(n1354), .B(n2023), .C(n2022), .Y(n786) );
NOR2X6TS U2164 ( .A(n954), .B(n1560), .Y(n1944) );
MXI2X4TS U2165 ( .A(n1334), .B(n3158), .S0(n1385), .Y(n525) );
AND3X4TS U2166 ( .A(n1117), .B(n1807), .C(n1149), .Y(n1473) );
NAND2X4TS U2167 ( .A(n2434), .B(n1726), .Y(n1733) );
AND2X8TS U2168 ( .A(n1322), .B(n1332), .Y(n1971) );
XOR2X1TS U2169 ( .A(n951), .B(n1360), .Y(n1876) );
AOI2BB2X4TS U2170 ( .B0(n1745), .B1(n1149), .A0N(n2727), .A1N(n2999), .Y(
n1754) );
NOR2X4TS U2171 ( .A(n2669), .B(n1366), .Y(n1365) );
AND2X8TS U2172 ( .A(n1325), .B(n1279), .Y(n1925) );
NAND2X6TS U2173 ( .A(n1749), .B(n2914), .Y(n1799) );
OA21X4TS U2174 ( .A0(n2879), .A1(n1213), .B0(n1855), .Y(n1374) );
NAND2X2TS U2175 ( .A(n2203), .B(intDY_EWSW[29]), .Y(n2026) );
NAND2X2TS U2176 ( .A(n2155), .B(n1015), .Y(n2199) );
NAND2X2TS U2177 ( .A(n2155), .B(n1372), .Y(n2158) );
AOI21X4TS U2178 ( .A0(n1669), .A1(n3113), .B0(n1420), .Y(n1671) );
NOR2X8TS U2179 ( .A(n1368), .B(n1348), .Y(n1926) );
OA22X4TS U2180 ( .A0(n975), .A1(n1381), .B0(n1380), .B1(n1189), .Y(n1865) );
NOR2X4TS U2181 ( .A(n1928), .B(n1925), .Y(n1927) );
XNOR2X4TS U2182 ( .A(n1542), .B(n1420), .Y(n1384) );
NAND4X2TS U2183 ( .A(n1902), .B(n1901), .C(n1900), .D(n1899), .Y(n1908) );
NOR2X4TS U2184 ( .A(n1347), .B(n1581), .Y(n1928) );
NOR2X8TS U2185 ( .A(n1389), .B(n1371), .Y(n1920) );
NOR2X4TS U2186 ( .A(n1917), .B(n1921), .Y(n1924) );
NOR2X4TS U2187 ( .A(n1959), .B(n1962), .Y(n1960) );
XOR2X4TS U2188 ( .A(n1550), .B(n1391), .Y(n1390) );
NAND2X4TS U2189 ( .A(n1389), .B(n1371), .Y(n1918) );
OAI21X4TS U2190 ( .A0(n1839), .A1(n1684), .B0(n1842), .Y(n1450) );
AO21X2TS U2191 ( .A0(n2274), .A1(n2277), .B0(n2253), .Y(n1393) );
OA21X2TS U2192 ( .A0(n1392), .A1(n2293), .B0(n2292), .Y(n1394) );
OR2X2TS U2193 ( .A(n2283), .B(n2269), .Y(n1395) );
NAND2X6TS U2194 ( .A(n2353), .B(n2671), .Y(n2400) );
NOR2X6TS U2195 ( .A(n1659), .B(n2252), .Y(n2284) );
CLKBUFX3TS U2196 ( .A(n3013), .Y(n2770) );
OR2X2TS U2197 ( .A(n2283), .B(n2285), .Y(n1398) );
OR2X2TS U2198 ( .A(n2291), .B(n2293), .Y(n1399) );
AND3X8TS U2199 ( .A(n2240), .B(n2239), .C(n2238), .Y(n1400) );
AO21X4TS U2200 ( .A0(n1769), .A1(n1768), .B0(Raw_mant_NRM_SWR[10]), .Y(n1405) );
INVX2TS U2201 ( .A(n2367), .Y(n1823) );
INVX8TS U2202 ( .A(n2400), .Y(n1604) );
OA21X4TS U2203 ( .A0(n1770), .A1(n1582), .B0(n1244), .Y(n1406) );
NOR2X4TS U2204 ( .A(n2542), .B(n1454), .Y(n1462) );
AND2X8TS U2205 ( .A(n1523), .B(n2440), .Y(n1410) );
INVX2TS U2206 ( .A(n2262), .Y(n1443) );
OR2X8TS U2207 ( .A(intDY_EWSW[17]), .B(n1387), .Y(n1411) );
NAND2X1TS U2208 ( .A(n1487), .B(n1149), .Y(n1412) );
INVX4TS U2209 ( .A(n2285), .Y(n2265) );
NOR2X4TS U2210 ( .A(n2234), .B(DMP_SFG[18]), .Y(n2250) );
CLKINVX6TS U2211 ( .A(n2250), .Y(n2277) );
CLKBUFX2TS U2212 ( .A(n3010), .Y(n2758) );
INVX2TS U2213 ( .A(rst), .Y(n3161) );
INVX2TS U2214 ( .A(rst), .Y(n1617) );
BUFX3TS U2215 ( .A(n1618), .Y(n3015) );
BUFX3TS U2216 ( .A(n1618), .Y(n3033) );
OAI21X4TS U2217 ( .A0(n1673), .A1(n1672), .B0(DMP_SFG[1]), .Y(n1675) );
XNOR2X4TS U2218 ( .A(n583), .B(n2976), .Y(n2808) );
XOR2X4TS U2219 ( .A(DmP_mant_SFG_SWR[6]), .B(n1566), .Y(n1668) );
INVX2TS U2220 ( .A(n1359), .Y(n2398) );
XOR2X4TS U2221 ( .A(n2616), .B(n1553), .Y(DmP_mant_SFG_SWR_signed[12]) );
NOR2BX4TS U2222 ( .AN(n2950), .B(n1422), .Y(n1421) );
OAI21X4TS U2223 ( .A0(n1424), .A1(n2338), .B0(n1693), .Y(n580) );
NAND2X8TS U2224 ( .A(n1425), .B(n1842), .Y(n1792) );
AOI21X4TS U2225 ( .A0(n1606), .A1(n2383), .B0(n1780), .Y(n3120) );
NAND3X8TS U2226 ( .A(n1427), .B(n1430), .C(n1777), .Y(n2383) );
NAND2X8TS U2227 ( .A(n2530), .B(n2506), .Y(n1427) );
NAND2X8TS U2228 ( .A(n1774), .B(n1428), .Y(n2530) );
NOR2BX4TS U2229 ( .AN(n1823), .B(n1775), .Y(n1429) );
XOR2X4TS U2230 ( .A(DmP_mant_SFG_SWR[16]), .B(n3034), .Y(n2228) );
NAND3X8TS U2231 ( .A(n1438), .B(n1436), .C(n1435), .Y(n2274) );
NAND2X8TS U2232 ( .A(n1439), .B(n1443), .Y(n1435) );
AOI21X4TS U2233 ( .A0(n973), .A1(n1437), .B0(n2232), .Y(n1436) );
NAND2X8TS U2234 ( .A(n2280), .B(n973), .Y(n2233) );
OR2X8TS U2235 ( .A(n2229), .B(DMP_SFG[15]), .Y(n1660) );
OAI21X4TS U2236 ( .A0(n1293), .A1(n1398), .B0(n1444), .Y(n2290) );
INVX12TS U2237 ( .A(n3059), .Y(n2209) );
OR2X8TS U2238 ( .A(n1846), .B(n1848), .Y(n1448) );
AOI21X4TS U2239 ( .A0(n1451), .A1(n1841), .B0(n1450), .Y(n1449) );
NOR2X6TS U2240 ( .A(Raw_mant_NRM_SWR[3]), .B(n1454), .Y(n2434) );
OAI2BB1X4TS U2241 ( .A0N(n1457), .A1N(n2422), .B0(n2437), .Y(n2426) );
NOR2X8TS U2242 ( .A(n1459), .B(n1458), .Y(n1457) );
NOR2X8TS U2243 ( .A(n1460), .B(n2418), .Y(n2431) );
OR2X8TS U2244 ( .A(n1498), .B(n1270), .Y(n2089) );
AOI21X4TS U2245 ( .A0(n2998), .A1(DmP_mant_SHT1_SW[21]), .B0(n1463), .Y(
n3112) );
NAND3X8TS U2246 ( .A(n1464), .B(n2984), .C(n3093), .Y(n1487) );
NAND2X8TS U2247 ( .A(n1759), .B(n1730), .Y(n1762) );
NAND2X8TS U2248 ( .A(n1058), .B(Raw_mant_NRM_SWR[2]), .Y(n2450) );
NAND2X8TS U2249 ( .A(n1471), .B(n2978), .Y(n1764) );
NAND3X8TS U2250 ( .A(n1723), .B(n2675), .C(n1475), .Y(n1477) );
AND2X8TS U2251 ( .A(n2417), .B(n2627), .Y(n1475) );
AOI22X4TS U2252 ( .A0(n981), .A1(DmP_mant_SHT1_SW[4]), .B0(
DmP_mant_SHT1_SW[3]), .B1(n2998), .Y(n3070) );
NAND2X8TS U2253 ( .A(n1479), .B(n2560), .Y(n2461) );
AOI2BB2X4TS U2254 ( .B0(n2998), .B1(DmP_mant_SHT1_SW[17]), .A0N(n1280),
.A1N(n2675), .Y(n3090) );
OA21X4TS U2255 ( .A0(n2628), .A1(Raw_mant_NRM_SWR[1]), .B0(n2451), .Y(n2432)
);
NAND2X8TS U2256 ( .A(n1465), .B(n1396), .Y(n1538) );
NAND2X8TS U2257 ( .A(n1492), .B(n1300), .Y(n1502) );
NAND2X8TS U2258 ( .A(n2089), .B(n1493), .Y(n1497) );
NOR2X8TS U2259 ( .A(n1267), .B(n1283), .Y(n2090) );
INVX16TS U2260 ( .A(n1494), .Y(n2559) );
AND4X8TS U2261 ( .A(n1400), .B(n1495), .C(n1496), .D(n985), .Y(n1494) );
NOR2X8TS U2262 ( .A(n2241), .B(n2479), .Y(n1496) );
NOR2X8TS U2263 ( .A(n2475), .B(n2477), .Y(n1495) );
AOI2BB2X4TS U2264 ( .B0(n1814), .B1(Raw_mant_NRM_SWR[9]), .A0N(n2174), .A1N(
n1574), .Y(n3067) );
NAND2X8TS U2265 ( .A(n1497), .B(n2088), .Y(n2085) );
AND2X8TS U2266 ( .A(n1499), .B(n985), .Y(n2490) );
NAND4BX4TS U2267 ( .AN(n1500), .B(n2100), .C(n2477), .D(n2551), .Y(n1499) );
NAND2X8TS U2268 ( .A(n1502), .B(n2613), .Y(n1501) );
BUFX20TS U2269 ( .A(n1519), .Y(n1505) );
CLKINVX1TS U2270 ( .A(n2984), .Y(n2985) );
NAND2X1TS U2271 ( .A(n2724), .B(n1266), .Y(n1520) );
NAND2X8TS U2272 ( .A(n1522), .B(n1410), .Y(n3095) );
OAI21X4TS U2273 ( .A0(n2921), .A1(n1505), .B0(n2544), .Y(n3085) );
OAI21X4TS U2274 ( .A0(n1921), .A1(n1530), .B0(n1529), .Y(n1922) );
NAND2X4TS U2275 ( .A(n1296), .B(n1565), .Y(n1530) );
NOR2X8TS U2276 ( .A(n1372), .B(n1563), .Y(n1921) );
NAND2BX4TS U2277 ( .AN(n2338), .B(Raw_mant_SGF[14]), .Y(n1532) );
XNOR2X4TS U2278 ( .A(DmP_mant_SFG_SWR[10]), .B(DMP_SFG[8]), .Y(n1848) );
BUFX20TS U2279 ( .A(n2055), .Y(n1533) );
NAND2X4TS U2280 ( .A(n1595), .B(n1286), .Y(n2611) );
NAND2X2TS U2281 ( .A(n2155), .B(n953), .Y(n2040) );
NAND2X2TS U2282 ( .A(n1590), .B(n1331), .Y(n2149) );
NAND2X2TS U2283 ( .A(n2203), .B(n1376), .Y(n2046) );
BUFX20TS U2284 ( .A(n2055), .Y(n2154) );
BUFX20TS U2285 ( .A(n2055), .Y(n2607) );
NAND2X2TS U2286 ( .A(n1590), .B(n1294), .Y(n2137) );
NAND2X2TS U2287 ( .A(n1590), .B(n1341), .Y(n2043) );
INVX4TS U2288 ( .A(n1960), .Y(n1645) );
OAI21X4TS U2289 ( .A0(n1965), .A1(n1964), .B0(n1963), .Y(n1966) );
OAI21X4TS U2290 ( .A0(n1944), .A1(n1943), .B0(n1942), .Y(n1945) );
OAI21X4TS U2291 ( .A0(n2432), .A1(n1767), .B0(n1766), .Y(n1769) );
OR2X4TS U2292 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[5]), .Y(n1767)
);
NAND2X4TS U2293 ( .A(n2165), .B(n1327), .Y(n2180) );
AO21X1TS U2294 ( .A0(n1089), .A1(n2318), .B0(n2317), .Y(n2320) );
NOR2X8TS U2295 ( .A(n1861), .B(n1860), .Y(n2523) );
OAI22X4TS U2296 ( .A0(n566), .A1(n766), .B0(n547), .B1(n763), .Y(n2964) );
NAND2BX1TS U2297 ( .AN(n3037), .B(n2985), .Y(n3039) );
INVX2TS U2298 ( .A(n1245), .Y(n1546) );
MXI2X4TS U2299 ( .A(n1212), .B(n2794), .S0(n2793), .Y(n2297) );
NAND2X4TS U2300 ( .A(n1683), .B(n1682), .Y(n2213) );
OAI21X2TS U2301 ( .A0(n1037), .A1(n1843), .B0(n1063), .Y(n1680) );
INVX6TS U2302 ( .A(n2551), .Y(n2238) );
AOI22X2TS U2303 ( .A0(n1605), .A1(n2577), .B0(n2466), .B1(n977), .Y(n2468)
);
AOI22X1TS U2304 ( .A0(n2516), .A1(n846), .B0(n2525), .B1(n2577), .Y(n2392)
);
AOI22X1TS U2305 ( .A0(n2516), .A1(n2577), .B0(n2499), .B1(n846), .Y(n2472)
);
NAND2X4TS U2306 ( .A(n2228), .B(DMP_SFG[14]), .Y(n2491) );
NAND2X2TS U2307 ( .A(n2566), .B(n2565), .Y(n3040) );
BUFX12TS U2308 ( .A(n2481), .Y(n1554) );
BUFX20TS U2309 ( .A(n2056), .Y(n2606) );
INVX16TS U2310 ( .A(n1555), .Y(n2055) );
NAND2X2TS U2311 ( .A(n1803), .B(n1262), .Y(n1806) );
NAND3X8TS U2312 ( .A(n2515), .B(n2514), .C(n2513), .Y(n2520) );
AOI22X2TS U2313 ( .A0(n2512), .A1(n2612), .B0(n2511), .B1(n2510), .Y(n2513)
);
MXI2X4TS U2314 ( .A(n2471), .B(n2470), .S0(left_right_SHT2), .Y(n2393) );
NAND2X4TS U2315 ( .A(n2461), .B(n2439), .Y(n831) );
AND2X8TS U2316 ( .A(n1640), .B(n1853), .Y(n1556) );
NOR2X4TS U2317 ( .A(n1938), .B(n1281), .Y(n1940) );
NAND2X2TS U2318 ( .A(n1570), .B(n1317), .Y(n1950) );
NAND2X4TS U2319 ( .A(n2229), .B(DMP_SFG[15]), .Y(n2262) );
NOR2X2TS U2320 ( .A(n2283), .B(n2250), .Y(n2235) );
AOI21X4TS U2321 ( .A0(intDY_EWSW[18]), .A1(n1274), .B0(n1965), .Y(n1967) );
OR2X4TS U2322 ( .A(intDY_EWSW[22]), .B(n1370), .Y(n1972) );
NOR2X6TS U2323 ( .A(n1956), .B(n1941), .Y(n1958) );
NAND3BX4TS U2324 ( .AN(n1866), .B(n1865), .C(n2967), .Y(n2377) );
MXI2X1TS U2325 ( .A(n2551), .B(final_result_ieee[26]), .S0(n3035), .Y(n2552)
);
XNOR2X2TS U2326 ( .A(n1550), .B(n2617), .Y(DmP_mant_SFG_SWR_signed[15]) );
NAND2X4TS U2327 ( .A(n1572), .B(n1251), .Y(n1970) );
NAND2X4TS U2328 ( .A(n2676), .B(n1364), .Y(n1983) );
AOI22X4TS U2329 ( .A0(n1179), .A1(n2906), .B0(n934), .B1(n1218), .Y(n1695)
);
INVX2TS U2330 ( .A(n1584), .Y(n1585) );
AND4X8TS U2331 ( .A(n1587), .B(n2990), .C(n1827), .D(n2989), .Y(n1586) );
AFCSHCONX2TS U2332 ( .B(DmP_mant_SFG_SWR_signed[14]), .A(DMP_SFG[12]), .CI0(
DP_OP_297J37_122_8400_n141), .CI1(DP_OP_297J37_122_8400_n140), .CS(
n2626), .S(Raw_mant_SGF[14]), .CO0N(DP_OP_297J37_122_8400_n139),
.CO1N(DP_OP_297J37_122_8400_n138) );
AOI21X4TS U2333 ( .A0(n1953), .A1(n1954), .B0(n1952), .Y(n1955) );
NAND2X4TS U2334 ( .A(n1686), .B(n1840), .Y(n1687) );
NAND2X8TS U2335 ( .A(n2288), .B(n2271), .Y(n2259) );
OAI21X4TS U2336 ( .A0(n1990), .A1(n1989), .B0(n1988), .Y(n1992) );
AOI21X4TS U2337 ( .A0(n1946), .A1(n1947), .B0(n1945), .Y(n1957) );
AOI22X2TS U2338 ( .A0(n1154), .A1(n2455), .B0(n1023), .B1(n1611), .Y(n3111)
);
AOI22X4TS U2339 ( .A0(n2500), .A1(n1592), .B0(n2516), .B1(n2578), .Y(n1870)
);
XOR2X4TS U2340 ( .A(n1576), .B(n1545), .Y(DmP_mant_SFG_SWR_signed[14]) );
AOI22X2TS U2341 ( .A0(n1154), .A1(n2453), .B0(n2452), .B1(n1610), .Y(n3057)
);
MXI2X4TS U2342 ( .A(n2394), .B(n2395), .S0(left_right_SHT2), .Y(n1719) );
NAND3X6TS U2343 ( .A(n1709), .B(n1708), .C(n1707), .Y(n2394) );
NAND2X2TS U2344 ( .A(n994), .B(intDY_EWSW[24]), .Y(n2014) );
NAND2X2TS U2345 ( .A(n2154), .B(n1388), .Y(n2078) );
NAND2X2TS U2346 ( .A(n2165), .B(n1560), .Y(n2041) );
NAND2X2TS U2347 ( .A(n2607), .B(n1298), .Y(n2047) );
NAND2X2TS U2348 ( .A(n2607), .B(n1322), .Y(n2150) );
CLKINVX3TS U2349 ( .A(rst), .Y(n1589) );
INVX3TS U2350 ( .A(rst), .Y(n1618) );
CLKINVX3TS U2351 ( .A(rst), .Y(n1615) );
NOR2X8TS U2352 ( .A(n1396), .B(n1505), .Y(n1814) );
NAND2X2TS U2353 ( .A(n1590), .B(n1562), .Y(n2049) );
NAND2X2TS U2354 ( .A(n1590), .B(n1322), .Y(n2206) );
NAND2X2TS U2355 ( .A(n2203), .B(n1060), .Y(n2187) );
NAND2X2TS U2356 ( .A(n1590), .B(n1264), .Y(n2181) );
NAND2X2TS U2357 ( .A(n2203), .B(n1569), .Y(n2196) );
NAND2X2TS U2358 ( .A(n2329), .B(n1015), .Y(n2135) );
NAND2X4TS U2359 ( .A(n1533), .B(n1328), .Y(n2610) );
NAND2X2TS U2360 ( .A(n2329), .B(n1060), .Y(n2117) );
NAND2X2TS U2361 ( .A(n2165), .B(n1348), .Y(n2062) );
NAND2X2TS U2362 ( .A(n2154), .B(n1564), .Y(n2141) );
NAND2X2TS U2363 ( .A(n2329), .B(n1376), .Y(n2110) );
NAND2X2TS U2364 ( .A(n2154), .B(n951), .Y(n2169) );
CLKBUFX3TS U2365 ( .A(n3031), .Y(n3013) );
NAND2X2TS U2366 ( .A(n2410), .B(left_right_SHT2), .Y(n2369) );
CLKINVX3TS U2367 ( .A(rst), .Y(n1593) );
BUFX20TS U2368 ( .A(n2606), .Y(n1595) );
NAND2X2TS U2369 ( .A(n2328), .B(n1560), .Y(n2125) );
NAND2X2TS U2370 ( .A(n2175), .B(n1273), .Y(n2116) );
NAND2X2TS U2371 ( .A(n2328), .B(n1371), .Y(n2077) );
CLKINVX3TS U2372 ( .A(rst), .Y(n1616) );
AOI22X2TS U2373 ( .A0(n2545), .A1(DmP_mant_SHT1_SW[11]), .B0(n3080), .B1(
DmP_mant_SHT1_SW[10]), .Y(n2454) );
MXI2X2TS U2374 ( .A(n3140), .B(n2615), .S0(n2539), .Y(n534) );
CLKINVX6TS U2375 ( .A(n2400), .Y(n1605) );
AOI22X2TS U2376 ( .A0(n1605), .A1(n2524), .B0(n2509), .B1(n2508), .Y(n2514)
);
NAND2X2TS U2377 ( .A(n994), .B(n1561), .Y(n2007) );
NAND2X2TS U2378 ( .A(n2154), .B(n1581), .Y(n2038) );
NAND2X2TS U2379 ( .A(n2607), .B(n1372), .Y(n2050) );
INVX16TS U2380 ( .A(n3109), .Y(n1608) );
AOI22X1TS U2381 ( .A0(n2548), .A1(n1613), .B0(n3080), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2408) );
OAI21X4TS U2382 ( .A0(n1996), .A1(n1995), .B0(n1994), .Y(n1620) );
NAND2X8TS U2383 ( .A(n1626), .B(n1623), .Y(n1622) );
AND2X8TS U2384 ( .A(n1625), .B(n1624), .Y(n1623) );
NAND2X8TS U2385 ( .A(n1629), .B(n1627), .Y(n1626) );
OAI21X4TS U2386 ( .A0(n1957), .A1(n1956), .B0(n1955), .Y(n1630) );
OAI21X4TS U2387 ( .A0(n1981), .A1(n1980), .B0(n1979), .Y(n1986) );
XOR2X4TS U2388 ( .A(n1656), .B(n1414), .Y(Raw_mant_SGF[25]) );
OAI21X4TS U2389 ( .A0(n1281), .A1(n1642), .B0(n1641), .Y(n1947) );
AOI2BB1X4TS U2390 ( .A0N(n1572), .A1N(n1251), .B0(n1971), .Y(n1644) );
NOR2X8TS U2391 ( .A(n1973), .B(n1365), .Y(n1975) );
NOR2X4TS U2392 ( .A(n2668), .B(n1284), .Y(n1647) );
NOR2X8TS U2393 ( .A(n1984), .B(n1648), .Y(n1987) );
NOR2X4TS U2394 ( .A(n2676), .B(n1364), .Y(n1648) );
NAND2X4TS U2395 ( .A(n2680), .B(n1561), .Y(n1979) );
OAI21X4TS U2396 ( .A0(n1649), .A1(n2338), .B0(n2237), .Y(n3160) );
OAI21X4TS U2397 ( .A0(n1293), .A1(n1653), .B0(n2491), .Y(n2264) );
OAI21X4TS U2398 ( .A0(n1293), .A1(n2283), .B0(n2286), .Y(n2279) );
OAI21X4TS U2399 ( .A0(n1293), .A1(n2291), .B0(n1392), .Y(n2282) );
OAI21X4TS U2400 ( .A0(n1293), .A1(n1395), .B0(n1401), .Y(n2273) );
OAI21X4TS U2401 ( .A0(n1293), .A1(n1399), .B0(n1394), .Y(n2296) );
AND2X8TS U2402 ( .A(n2253), .B(n2254), .Y(n1659) );
NOR2X8TS U2403 ( .A(n2230), .B(DMP_SFG[16]), .Y(n2293) );
XOR2X4TS U2404 ( .A(DmP_mant_SFG_SWR[18]), .B(n3034), .Y(n2230) );
CLKINVX6TS U2405 ( .A(n2579), .Y(n2356) );
NAND2X4TS U2406 ( .A(n1595), .B(intDY_EWSW[27]), .Y(n2000) );
NAND3X6TS U2407 ( .A(n2413), .B(n2414), .C(n2415), .Y(n3088) );
OAI21X4TS U2408 ( .A0(n2400), .A1(n1586), .B0(n2399), .Y(n2457) );
XNOR2X2TS U2409 ( .A(n2322), .B(n2321), .Y(n2323) );
NAND3X8TS U2410 ( .A(n1714), .B(n1713), .C(n1712), .Y(n2481) );
AOI2BB2X4TS U2411 ( .B0(n2893), .B1(n2892), .A0N(n1862), .A1N(n1208), .Y(
n1714) );
XOR2X4TS U2412 ( .A(n2487), .B(n2486), .Y(n2488) );
NOR2X4TS U2413 ( .A(n1093), .B(n2914), .Y(n2453) );
OAI21X4TS U2414 ( .A0(n2367), .A1(n3103), .B0(n1778), .Y(n2381) );
NOR2X4TS U2415 ( .A(n2367), .B(n1859), .Y(n1860) );
MXI2X2TS U2416 ( .A(n2582), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
OAI21X4TS U2417 ( .A0(n2567), .A1(n2299), .B0(n2301), .Y(n2463) );
NAND2X2TS U2418 ( .A(n2165), .B(n1047), .Y(n2131) );
XOR2X4TS U2419 ( .A(n1684), .B(n942), .Y(n2486) );
OAI21X4TS U2420 ( .A0(n1505), .A1(n2542), .B0(n1771), .Y(n2015) );
XOR2X4TS U2421 ( .A(DmP_mant_SFG_SWR[9]), .B(n1549), .Y(n1691) );
AOI21X4TS U2422 ( .A0(n1992), .A1(n1993), .B0(n1991), .Y(n1994) );
AOI21X4TS U2423 ( .A0(n1220), .A1(n2837), .B0(n1711), .Y(n1712) );
OAI21X4TS U2424 ( .A0(n1919), .A1(n1920), .B0(n1918), .Y(n1923) );
NOR2X2TS U2425 ( .A(n2555), .B(n2553), .Y(n2240) );
XOR2X4TS U2426 ( .A(n2091), .B(n2090), .Y(n2555) );
OAI21X4TS U2427 ( .A0(n2094), .A1(n2093), .B0(n2092), .Y(n2099) );
BUFX6TS U2428 ( .A(Shift_reg_FLAGS_7[2]), .Y(n3036) );
AND2X4TS U2429 ( .A(n2410), .B(n1591), .Y(n1666) );
NOR3X2TS U2430 ( .A(Raw_mant_NRM_SWR[9]), .B(n1573), .C(n2663), .Y(n1770) );
XNOR2X1TS U2431 ( .A(intDY_EWSW[27]), .B(n1382), .Y(n1873) );
NAND3X1TS U2432 ( .A(n1809), .B(n2417), .C(n2627), .Y(n1813) );
NAND2X4TS U2433 ( .A(n2256), .B(DMP_SFG[21]), .Y(n2270) );
MXI2X1TS U2434 ( .A(n2553), .B(final_result_ieee[23]), .S0(n3035), .Y(n2554)
);
NAND2X1TS U2435 ( .A(n2329), .B(n1360), .Y(n2053) );
MXI2X2TS U2436 ( .A(n1832), .B(n2675), .S0(n2338), .Y(n568) );
INVX2TS U2442 ( .A(n1046), .Y(n1682) );
NAND2X1TS U2443 ( .A(n2210), .B(n1050), .Y(n1685) );
NAND2X2TS U2444 ( .A(n1384), .B(n942), .Y(n2215) );
NAND2X2TS U2445 ( .A(n2334), .B(n2633), .Y(n1690) );
XOR2X4TS U2446 ( .A(n3034), .B(DmP_mant_SFG_SWR[10]), .Y(n1793) );
INVX2TS U2447 ( .A(n1793), .Y(n1692) );
NAND2X2TS U2448 ( .A(n1692), .B(n2629), .Y(n1791) );
BUFX8TS U2449 ( .A(n2659), .Y(n2338) );
NOR2X2TS U2450 ( .A(n1862), .B(n2876), .Y(n1694) );
NOR2X8TS U2451 ( .A(n1547), .B(n1343), .Y(n2365) );
NAND2X8TS U2452 ( .A(n2512), .B(n1591), .Y(n2536) );
INVX16TS U2453 ( .A(n2536), .Y(n2516) );
AOI22X4TS U2454 ( .A0(n1179), .A1(n2889), .B0(n1216), .B1(n1198), .Y(n1698)
);
NAND4X8TS U2455 ( .A(n1699), .B(n2973), .C(n1698), .D(n1697), .Y(n2508) );
NOR2X8TS U2456 ( .A(n1547), .B(n1344), .Y(n2353) );
OA22X4TS U2457 ( .A0(n1268), .A1(n1665), .B0(n1215), .B1(n1203), .Y(n1706)
);
NAND3X2TS U2458 ( .A(n2836), .B(n2835), .C(n2834), .Y(n1702) );
NOR2BX4TS U2459 ( .AN(n1703), .B(n1702), .Y(n1704) );
NAND3X8TS U2460 ( .A(n1706), .B(n1705), .C(n1704), .Y(n2579) );
OR2X8TS U2461 ( .A(n2367), .B(n2506), .Y(n1710) );
OR3X6TS U2462 ( .A(n2506), .B(n1344), .C(n1548), .Y(n1715) );
NAND2X2TS U2463 ( .A(n2509), .B(n2578), .Y(n1707) );
INVX8TS U2464 ( .A(n1715), .Y(n2466) );
OAI21X4TS U2465 ( .A0(n1191), .A1(n2822), .B0(n2821), .Y(n2519) );
NAND3X4TS U2466 ( .A(n1718), .B(n1717), .C(n1716), .Y(n2395) );
AND2X8TS U2467 ( .A(n1719), .B(n1720), .Y(n3136) );
INVX2TS U2468 ( .A(n2618), .Y(n1721) );
NAND2X8TS U2469 ( .A(n2079), .B(Shift_reg_FLAGS_7[3]), .Y(n2340) );
BUFX20TS U2470 ( .A(n2992), .Y(n2602) );
NOR2X8TS U2471 ( .A(n2437), .B(n2482), .Y(n3109) );
NOR3X4TS U2472 ( .A(n1582), .B(n1243), .C(Raw_mant_NRM_SWR[16]), .Y(n1722)
);
NOR2X8TS U2473 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n2417)
);
NOR3X1TS U2474 ( .A(n2639), .B(Raw_mant_NRM_SWR[4]), .C(Raw_mant_NRM_SWR[2]),
.Y(n1726) );
NOR2X2TS U2475 ( .A(n1243), .B(n1573), .Y(n1727) );
NOR2X1TS U2476 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[14]), .Y(
n1729) );
AOI21X1TS U2477 ( .A0(n1730), .A1(n1729), .B0(n2565), .Y(n1731) );
NAND3X1TS U2478 ( .A(n1808), .B(n1149), .C(n1731), .Y(n1732) );
INVX2TS U2479 ( .A(Shift_amount_SHT1_EWR[3]), .Y(n2315) );
NOR2X1TS U2480 ( .A(n1610), .B(n2315), .Y(n1734) );
AOI2BB2X1TS U2481 ( .B0(n2869), .B1(n2890), .A0N(n1862), .A1N(n1192), .Y(
n1736) );
NAND3X2TS U2482 ( .A(n1738), .B(n1737), .C(n1736), .Y(n835) );
OR2X6TS U2483 ( .A(Raw_mant_NRM_SWR[7]), .B(Raw_mant_NRM_SWR[6]), .Y(n1809)
);
NOR4X2TS U2484 ( .A(n1574), .B(n1746), .C(n1582), .D(n1243), .Y(n1747) );
INVX16TS U2485 ( .A(n2602), .Y(n2560) );
AOI21X2TS U2486 ( .A0(n1349), .A1(n1802), .B0(n1748), .Y(n1752) );
AND2X4TS U2487 ( .A(n1249), .B(n2994), .Y(n1749) );
NOR2X4TS U2488 ( .A(n1765), .B(Raw_mant_NRM_SWR[6]), .Y(n1766) );
INVX4TS U2489 ( .A(n2417), .Y(n2419) );
NOR2X4TS U2490 ( .A(n2419), .B(Raw_mant_NRM_SWR[7]), .Y(n1768) );
NAND3BX4TS U2491 ( .AN(n1773), .B(n1772), .C(n2936), .Y(n2510) );
NAND2X2TS U2492 ( .A(n2381), .B(n2531), .Y(n1779) );
OAI21X4TS U2493 ( .A0(n3120), .A1(n2571), .B0(n1781), .Y(n555) );
AOI2BB2X4TS U2494 ( .B0(n2908), .B1(n2907), .A0N(n1268), .A1N(n1663), .Y(
n1784) );
NAND3X1TS U2495 ( .A(n1790), .B(n3036), .C(n1849), .Y(n1788) );
OR2X4TS U2496 ( .A(n1423), .B(n1788), .Y(n1798) );
NOR3X2TS U2497 ( .A(n1793), .B(n1040), .C(n2566), .Y(n1789) );
AOI22X2TS U2498 ( .A0(n1790), .A1(n1789), .B0(n1573), .B1(n2566), .Y(n1797)
);
NAND4X4TS U2499 ( .A(n1798), .B(n1797), .C(n1796), .D(n1795), .Y(n588) );
NAND2X4TS U2500 ( .A(n1799), .B(n2984), .Y(n1801) );
NAND2X2TS U2501 ( .A(n1801), .B(n1800), .Y(n1803) );
NOR3X1TS U2502 ( .A(n1574), .B(n1582), .C(n1243), .Y(n1807) );
NAND2X4TS U2503 ( .A(n2542), .B(Raw_mant_NRM_SWR[3]), .Y(n2430) );
OAI21X1TS U2504 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2451), .B0(n2430), .Y(n1810) );
NOR2X2TS U2505 ( .A(n1862), .B(n1181), .Y(n1819) );
NAND4X6TS U2506 ( .A(n2841), .B(n2840), .C(n2839), .D(n2838), .Y(n2580) );
NAND2X2TS U2507 ( .A(n1823), .B(n2580), .Y(n1826) );
AOI2BB2X4TS U2508 ( .B0(n1217), .B1(n1197), .A0N(n1862), .A1N(n2891), .Y(
n1827) );
AOI22X4TS U2509 ( .A0(n2518), .A1(n1606), .B0(n1023), .B1(n2525), .Y(n3115)
);
BUFX12TS U2510 ( .A(n2340), .Y(n2571) );
MXI2X4TS U2511 ( .A(n2687), .B(n1550), .S0(n2581), .Y(n610) );
INVX8TS U2512 ( .A(n610), .Y(n2995) );
NOR2X4TS U2513 ( .A(n1543), .B(n2209), .Y(n1833) );
OAI21X4TS U2514 ( .A0(n1837), .A1(n1836), .B0(n1835), .Y(n1838) );
AOI22X4TS U2515 ( .A0(n1852), .A1(n1851), .B0(DMP_SFG[9]), .B1(n1850), .Y(
n1853) );
INVX12TS U2516 ( .A(n1854), .Y(n2998) );
BUFX12TS U2517 ( .A(n2340), .Y(n3000) );
NAND2X1TS U2518 ( .A(n2353), .B(n2519), .Y(n1857) );
NAND3BX4TS U2519 ( .AN(n1864), .B(n1863), .C(n2937), .Y(n2452) );
NAND3X1TS U2520 ( .A(n2846), .B(n2845), .C(n2844), .Y(n2614) );
XNOR2X1TS U2521 ( .A(intDY_EWSW[25]), .B(n1561), .Y(n1874) );
XNOR2X1TS U2522 ( .A(intDY_EWSW[17]), .B(n1386), .Y(n1872) );
XOR2X1TS U2523 ( .A(intDY_EWSW[29]), .B(n1330), .Y(n1877) );
XOR2X1TS U2524 ( .A(intDY_EWSW[26]), .B(n1364), .Y(n1875) );
XNOR2X1TS U2525 ( .A(n1015), .B(n1577), .Y(n1882) );
XNOR2X1TS U2526 ( .A(n1322), .B(n1331), .Y(n1880) );
NAND4X1TS U2527 ( .A(n1882), .B(n1881), .C(n1880), .D(n1879), .Y(n1888) );
NAND4X1TS U2528 ( .A(n1886), .B(n1885), .C(n1884), .D(n1883), .Y(n1887) );
XNOR2X1TS U2529 ( .A(n953), .B(n1560), .Y(n1891) );
NAND4X1TS U2530 ( .A(n1892), .B(n1891), .C(n1890), .D(n1889), .Y(n1898) );
XNOR2X1TS U2531 ( .A(intDY_EWSW[24]), .B(n1284), .Y(n1896) );
XNOR2X1TS U2532 ( .A(n1569), .B(n1317), .Y(n1895) );
NAND4X1TS U2533 ( .A(n1896), .B(n1895), .C(n1894), .D(n1893), .Y(n1897) );
XNOR2X1TS U2534 ( .A(n1562), .B(n1372), .Y(n1902) );
XNOR2X1TS U2535 ( .A(n1346), .B(n1581), .Y(n1900) );
NAND4X4TS U2536 ( .A(n1911), .B(n1912), .C(n1910), .D(n1909), .Y(n2326) );
XOR2X4TS U2537 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n2327) );
INVX2TS U2538 ( .A(n2327), .Y(n1913) );
NOR2X2TS U2539 ( .A(n1913), .B(n2697), .Y(n2330) );
INVX2TS U2540 ( .A(n2330), .Y(n1916) );
OAI21X4TS U2541 ( .A0(n1962), .A1(n1961), .B0(n1411), .Y(n1968) );
AOI21X4TS U2542 ( .A0(n1976), .A1(n1975), .B0(n1974), .Y(n1977) );
NAND2X2TS U2543 ( .A(n2673), .B(n1382), .Y(n1982) );
OAI21X4TS U2544 ( .A0(n1984), .A1(n1983), .B0(n1982), .Y(n1985) );
AOI21X4TS U2545 ( .A0(n1986), .A1(n1987), .B0(n1985), .Y(n1996) );
INVX16TS U2546 ( .A(n1997), .Y(n2056) );
BUFX20TS U2547 ( .A(n2055), .Y(n2165) );
NAND2X4TS U2548 ( .A(n1382), .B(n2329), .Y(n1999) );
BUFX12TS U2549 ( .A(n2111), .Y(n2170) );
NAND2X2TS U2550 ( .A(n2170), .B(DMP_EXP_EWSW[27]), .Y(n1998) );
NAND3X6TS U2551 ( .A(n2000), .B(n1999), .C(n1998), .Y(n787) );
NAND2X2TS U2552 ( .A(n2170), .B(DMP_EXP_EWSW[24]), .Y(n2001) );
NAND2X2TS U2553 ( .A(n2170), .B(DMP_EXP_EWSW[26]), .Y(n2003) );
NAND2X2TS U2554 ( .A(n2203), .B(n1284), .Y(n2013) );
BUFX12TS U2555 ( .A(n2111), .Y(n2161) );
NAND2X1TS U2556 ( .A(n2166), .B(DmP_EXP_EWSW[8]), .Y(n2019) );
NAND2X2TS U2557 ( .A(n1595), .B(intDY_EWSW[28]), .Y(n2023) );
NAND2X2TS U2558 ( .A(n2160), .B(n1330), .Y(n2025) );
NAND3X2TS U2559 ( .A(n2025), .B(n2026), .C(n2024), .Y(n785) );
NAND3X2TS U2560 ( .A(n2032), .B(n2031), .C(n2030), .Y(n810) );
NAND2X1TS U2561 ( .A(n2161), .B(DMP_EXP_EWSW[10]), .Y(n2033) );
NAND3X2TS U2562 ( .A(n2038), .B(n2037), .C(n2036), .Y(n809) );
NAND3X2TS U2563 ( .A(n2041), .B(n2040), .C(n2039), .Y(n803) );
NAND3X2TS U2564 ( .A(n2044), .B(n2043), .C(n2042), .Y(n806) );
NAND2X1TS U2565 ( .A(n2161), .B(DMP_EXP_EWSW[12]), .Y(n2045) );
NAND3X2TS U2566 ( .A(n2047), .B(n2046), .C(n2045), .Y(n802) );
NAND2X1TS U2567 ( .A(n2166), .B(DMP_EXP_EWSW[3]), .Y(n2048) );
NAND3X2TS U2568 ( .A(n2050), .B(n2049), .C(n2048), .Y(n811) );
NAND2X1TS U2569 ( .A(n2175), .B(n951), .Y(n2054) );
BUFX20TS U2570 ( .A(n2055), .Y(n2329) );
NAND3X2TS U2571 ( .A(n2054), .B(n2053), .C(n2052), .Y(n807) );
NAND2X1TS U2572 ( .A(n2608), .B(DMP_EXP_EWSW[9]), .Y(n2057) );
NAND3X2TS U2573 ( .A(n2059), .B(n2058), .C(n2057), .Y(n805) );
NAND2X1TS U2574 ( .A(n2156), .B(DMP_EXP_EWSW[6]), .Y(n2060) );
NAND3X2TS U2575 ( .A(n2062), .B(n2061), .C(n2060), .Y(n808) );
NAND2X2TS U2576 ( .A(n2175), .B(n1561), .Y(n2064) );
NAND2X2TS U2577 ( .A(n2161), .B(DmP_EXP_EWSW[25]), .Y(n2063) );
NAND2X2TS U2578 ( .A(n2160), .B(n1579), .Y(n2067) );
NAND2X2TS U2579 ( .A(n2161), .B(DmP_EXP_EWSW[23]), .Y(n2065) );
NAND2X2TS U2580 ( .A(n2155), .B(n1364), .Y(n2070) );
NAND2X2TS U2581 ( .A(n2329), .B(intDY_EWSW[26]), .Y(n2069) );
NAND2X1TS U2582 ( .A(n2111), .B(DmP_EXP_EWSW[16]), .Y(n2073) );
NAND2X1TS U2583 ( .A(n2608), .B(DmP_EXP_EWSW[1]), .Y(n2076) );
NAND3X2TS U2584 ( .A(n2078), .B(n2077), .C(n2076), .Y(n669) );
NOR2X8TS U2585 ( .A(n1302), .B(DMP_exp_NRM2_EW[4]), .Y(n2246) );
NAND2X6TS U2586 ( .A(n1302), .B(DMP_exp_NRM2_EW[4]), .Y(n2245) );
NAND2X2TS U2587 ( .A(n2082), .B(n2245), .Y(n2083) );
XOR2X4TS U2588 ( .A(n2247), .B(n2083), .Y(n2477) );
NOR2X2TS U2589 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM2_EW[5]), .Y(n2084)
);
NAND2X2TS U2590 ( .A(n2084), .B(n2245), .Y(n2102) );
INVX2TS U2591 ( .A(n2093), .Y(n2086) );
XOR2X4TS U2592 ( .A(n2094), .B(n2087), .Y(n2557) );
XNOR2X2TS U2593 ( .A(n1267), .B(n1283), .Y(n2553) );
AND2X2TS U2594 ( .A(n2555), .B(n2553), .Y(n2100) );
INVX2TS U2595 ( .A(n2095), .Y(n2097) );
XNOR2X4TS U2596 ( .A(n2099), .B(n2098), .Y(n2551) );
INVX2TS U2597 ( .A(n2102), .Y(n2103) );
NAND2X1TS U2598 ( .A(n2111), .B(DmP_EXP_EWSW[15]), .Y(n2105) );
NAND2X2TS U2599 ( .A(n2328), .B(n1298), .Y(n2109) );
NAND2X1TS U2600 ( .A(n2111), .B(DmP_EXP_EWSW[12]), .Y(n2108) );
NAND3X2TS U2601 ( .A(n2110), .B(n2109), .C(n2108), .Y(n647) );
NAND3X2TS U2602 ( .A(n2117), .B(n2116), .C(n2115), .Y(n635) );
NAND2X1TS U2603 ( .A(n2329), .B(n1346), .Y(n2120) );
NAND2X1TS U2604 ( .A(n2328), .B(n1581), .Y(n2119) );
NAND3X2TS U2605 ( .A(n2119), .B(n2120), .C(n2118), .Y(n661) );
NAND2X1TS U2606 ( .A(n2165), .B(intDY_EWSW[17]), .Y(n2123) );
NAND3X2TS U2607 ( .A(n2123), .B(n2122), .C(n2121), .Y(n637) );
NAND2X2TS U2608 ( .A(n1590), .B(n1369), .Y(n2132) );
NAND2X1TS U2609 ( .A(n2156), .B(DmP_EXP_EWSW[22]), .Y(n2130) );
NAND3X2TS U2610 ( .A(n2131), .B(n2132), .C(n2130), .Y(n627) );
NAND2X1TS U2611 ( .A(n2156), .B(DmP_EXP_EWSW[19]), .Y(n2133) );
NAND3X2TS U2612 ( .A(n2135), .B(n2134), .C(n2133), .Y(n633) );
NAND3X2TS U2613 ( .A(n2138), .B(n2137), .C(n2136), .Y(n651) );
NAND2X1TS U2614 ( .A(n2156), .B(DmP_EXP_EWSW[2]), .Y(n2139) );
NAND3X2TS U2615 ( .A(n2141), .B(n2140), .C(n2139), .Y(n667) );
NAND2X1TS U2616 ( .A(n2328), .B(n1251), .Y(n2144) );
NAND3X2TS U2617 ( .A(n2144), .B(n2143), .C(n2142), .Y(n631) );
NAND2X1TS U2618 ( .A(n2166), .B(DmP_EXP_EWSW[14]), .Y(n2145) );
NAND3X2TS U2619 ( .A(n2147), .B(n2146), .C(n2145), .Y(n643) );
NAND2X2TS U2620 ( .A(n2203), .B(n1382), .Y(n2164) );
NAND2X2TS U2621 ( .A(n2154), .B(intDY_EWSW[27]), .Y(n2163) );
NAND2X2TS U2622 ( .A(n2161), .B(DmP_EXP_EWSW[27]), .Y(n2162) );
NAND2X1TS U2623 ( .A(n2166), .B(DmP_EXP_EWSW[7]), .Y(n2167) );
NAND3X2TS U2624 ( .A(n2169), .B(n2168), .C(n2167), .Y(n657) );
NAND3X2TS U2625 ( .A(n2173), .B(n2172), .C(n2171), .Y(n813) );
NAND2X2TS U2626 ( .A(n1590), .B(n1378), .Y(n2178) );
NAND2X2TS U2627 ( .A(n2607), .B(n1578), .Y(n2177) );
NAND2X1TS U2628 ( .A(n2608), .B(DMP_EXP_EWSW[30]), .Y(n2176) );
NAND3X2TS U2629 ( .A(n2178), .B(n2177), .C(n2176), .Y(n784) );
NAND2X2TS U2630 ( .A(n2715), .B(DMP_EXP_EWSW[16]), .Y(n2179) );
NAND2X2TS U2631 ( .A(n2715), .B(DMP_EXP_EWSW[14]), .Y(n2182) );
NAND2X2TS U2632 ( .A(n2715), .B(DMP_EXP_EWSW[18]), .Y(n2185) );
NAND2X2TS U2633 ( .A(n2715), .B(DMP_EXP_EWSW[20]), .Y(n2188) );
NAND2X2TS U2634 ( .A(n2715), .B(DMP_EXP_EWSW[17]), .Y(n2191) );
NAND2X2TS U2635 ( .A(n2715), .B(DMP_EXP_EWSW[19]), .Y(n2197) );
NAND2X1TS U2636 ( .A(n2608), .B(DMP_EXP_EWSW[22]), .Y(n2200) );
NAND2X1TS U2637 ( .A(n2608), .B(n1307), .Y(n2204) );
NAND3X2TS U2638 ( .A(n2206), .B(n2205), .C(n2204), .Y(n793) );
NOR2X4TS U2639 ( .A(n1112), .B(n2921), .Y(n2543) );
INVX2TS U2640 ( .A(n2524), .Y(n2345) );
INVX2TS U2641 ( .A(n2220), .Y(n2221) );
NAND4X4TS U2642 ( .A(n2317), .B(n2212), .C(n2211), .D(n2321), .Y(n2218) );
MXI2X4TS U2643 ( .A(n2221), .B(n2220), .S0(n2219), .Y(n2222) );
BUFX8TS U2644 ( .A(n2659), .Y(n2601) );
OAI22X4TS U2645 ( .A0(n2463), .A1(n2223), .B0(n789), .B1(n2685), .Y(n2314)
);
NOR2X2TS U2646 ( .A(DMP_EXP_EWSW[26]), .B(n2717), .Y(n2311) );
XOR2X1TS U2647 ( .A(DMP_EXP_EWSW[27]), .B(DmP_EXP_EWSW[27]), .Y(n2224) );
XOR2X4TS U2648 ( .A(n2225), .B(n2224), .Y(n2226) );
INVX2TS U2649 ( .A(Shift_amount_SHT1_EWR[4]), .Y(n2423) );
MXI2X4TS U2650 ( .A(n2226), .B(n2423), .S0(n2561), .Y(n823) );
XOR2X4TS U2651 ( .A(n1549), .B(DmP_mant_SFG_SWR[17]), .Y(n2229) );
NAND2X6TS U2652 ( .A(n2492), .B(n1660), .Y(n2291) );
NOR2X8TS U2653 ( .A(n2291), .B(n2233), .Y(n2275) );
INVX4TS U2654 ( .A(n2275), .Y(n2283) );
XOR2X4TS U2655 ( .A(n3034), .B(DmP_mant_SFG_SWR[20]), .Y(n2234) );
NAND2X4TS U2656 ( .A(n2230), .B(DMP_SFG[16]), .Y(n2292) );
NAND2X4TS U2657 ( .A(n2231), .B(DMP_SFG[17]), .Y(n2294) );
INVX2TS U2658 ( .A(n2294), .Y(n2232) );
NAND2X4TS U2659 ( .A(n2234), .B(DMP_SFG[18]), .Y(n2276) );
XOR2X4TS U2660 ( .A(DmP_mant_SFG_SWR[21]), .B(n3034), .Y(n2236) );
OR2X6TS U2661 ( .A(n2236), .B(DMP_SFG[19]), .Y(n2254) );
INVX2TS U2662 ( .A(n2557), .Y(n2239) );
INVX2TS U2663 ( .A(n2245), .Y(n2242) );
NOR2X2TS U2664 ( .A(n2242), .B(DMP_exp_NRM2_EW[5]), .Y(n2243) );
OAI21X4TS U2665 ( .A0(n2247), .A1(n2246), .B0(n2243), .Y(n2244) );
XNOR2X4TS U2666 ( .A(n2244), .B(DMP_exp_NRM2_EW[6]), .Y(n2475) );
OAI21X4TS U2667 ( .A0(n2247), .A1(n2246), .B0(n2245), .Y(n2248) );
NAND2X6TS U2668 ( .A(n2277), .B(n2254), .Y(n2285) );
XOR2X4TS U2669 ( .A(n2297), .B(n3034), .Y(n2255) );
OR2X8TS U2670 ( .A(n2255), .B(DMP_SFG[20]), .Y(n2288) );
XOR2X4TS U2671 ( .A(n3034), .B(DmP_mant_SFG_SWR[23]), .Y(n2256) );
INVX2TS U2672 ( .A(n2251), .Y(n2252) );
INVX2TS U2673 ( .A(n2270), .Y(n2257) );
XOR2X4TS U2674 ( .A(n2264), .B(n2263), .Y(Raw_mant_SGF[17]) );
NAND2X4TS U2675 ( .A(n2265), .B(n2288), .Y(n2269) );
INVX2TS U2676 ( .A(n2284), .Y(n2267) );
XOR2X4TS U2677 ( .A(n2273), .B(n2272), .Y(Raw_mant_SGF[23]) );
XOR2X4TS U2678 ( .A(n2279), .B(n2278), .Y(Raw_mant_SGF[20]) );
XOR2X4TS U2679 ( .A(n2282), .B(n2281), .Y(Raw_mant_SGF[18]) );
XOR2X4TS U2680 ( .A(n2290), .B(n2289), .Y(Raw_mant_SGF[22]) );
XOR2X4TS U2681 ( .A(n2296), .B(n2295), .Y(Raw_mant_SGF[19]) );
CLKBUFX3TS U2682 ( .A(n3030), .Y(n3010) );
CLKBUFX3TS U2683 ( .A(n3010), .Y(n2760) );
CLKBUFX3TS U2684 ( .A(n3009), .Y(n2756) );
INVX2TS U2685 ( .A(n2297), .Y(n3097) );
INVX2TS U2686 ( .A(n2401), .Y(n3047) );
BUFX8TS U2687 ( .A(n2340), .Y(n2563) );
MXI2X1TS U2688 ( .A(n2651), .B(n2709), .S0(n2539), .Y(n709) );
MXI2X1TS U2689 ( .A(n2650), .B(n2708), .S0(n3000), .Y(n704) );
MXI2X1TS U2690 ( .A(n2649), .B(n2707), .S0(n2563), .Y(n694) );
MXI2X1TS U2691 ( .A(n2298), .B(n2704), .S0(n2539), .Y(n679) );
MXI2X1TS U2692 ( .A(n2648), .B(n2706), .S0(n3000), .Y(n689) );
MXI2X1TS U2693 ( .A(n2640), .B(n2703), .S0(n2563), .Y(n674) );
MXI2X1TS U2694 ( .A(n2647), .B(n2705), .S0(n2571), .Y(n684) );
MXI2X2TS U2695 ( .A(n2688), .B(n3059), .S0(n2581), .Y(n760) );
OR2X2TS U2696 ( .A(n2460), .B(n3036), .Y(n2744) );
OR2X2TS U2697 ( .A(n1464), .B(n3036), .Y(n2661) );
OR2X2TS U2698 ( .A(n2613), .B(n3036), .Y(n2745) );
OR2X2TS U2699 ( .A(n1312), .B(n3037), .Y(n2746) );
INVX2TS U2700 ( .A(n2299), .Y(n2300) );
XNOR2X1TS U2701 ( .A(n2302), .B(n2567), .Y(n2303) );
NOR2X2TS U2702 ( .A(n2304), .B(n2562), .Y(n2584) );
INVX2TS U2703 ( .A(n2584), .Y(n2306) );
NAND2X1TS U2704 ( .A(n2304), .B(n2562), .Y(n2305) );
NAND2X1TS U2705 ( .A(n2306), .B(n2305), .Y(n2307) );
MXI2X1TS U2706 ( .A(n2307), .B(n2451), .S0(n2601), .Y(n575) );
OAI2BB1X2TS U2707 ( .A0N(OP_FLAG_EXP), .A1N(n2608), .B0(n2308), .Y(n783) );
INVX2TS U2708 ( .A(n2592), .Y(n2582) );
NOR2X1TS U2709 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2309) );
NAND2X2TS U2710 ( .A(n2309), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2549) );
NAND2X2TS U2711 ( .A(n2582), .B(n2549), .Y(n932) );
INVX2TS U2712 ( .A(n2310), .Y(n2312) );
MXI2X2TS U2713 ( .A(n2320), .B(n2542), .S0(n2601), .Y(n570) );
NOR2X6TS U2714 ( .A(n2325), .B(n2324), .Y(n2604) );
MXI2X2TS U2715 ( .A(n2566), .B(n2602), .S0(n2604), .Y(n925) );
MXI2X1TS U2716 ( .A(n2330), .B(SIGN_FLAG_EXP), .S0(n2715), .Y(n2331) );
NAND3X2TS U2717 ( .A(n2333), .B(n2332), .C(n2331), .Y(n781) );
MXI2X4TS U2718 ( .A(n2339), .B(n1661), .S0(n2338), .Y(n581) );
MXI2X4TS U2719 ( .A(n3115), .B(n2672), .S0(n3001), .Y(n576) );
AND2X4TS U2720 ( .A(n2365), .B(n2506), .Y(n2502) );
NAND2X2TS U2721 ( .A(n1604), .B(n2352), .Y(n2343) );
NAND2X2TS U2722 ( .A(n2509), .B(n2579), .Y(n2342) );
INVX4TS U2723 ( .A(n2531), .Y(n2535) );
OAI22X2TS U2724 ( .A0(n2536), .A1(n2345), .B0(n2523), .B1(n2535), .Y(n2346)
);
NAND2X2TS U2725 ( .A(n2502), .B(n1351), .Y(n2351) );
NAND2X2TS U2726 ( .A(n1605), .B(n1554), .Y(n2350) );
NAND2X2TS U2727 ( .A(n2466), .B(n852), .Y(n2349) );
NAND4X4TS U2728 ( .A(n2351), .B(n2350), .C(n2349), .D(n2348), .Y(n2370) );
INVX2TS U2729 ( .A(n2452), .Y(n2359) );
NAND2X1TS U2730 ( .A(n2353), .B(n2578), .Y(n2354) );
NOR2X8TS U2731 ( .A(n2358), .B(n2357), .Y(n2507) );
NAND2X2TS U2732 ( .A(n2502), .B(n2580), .Y(n2363) );
NAND2X2TS U2733 ( .A(n1604), .B(n846), .Y(n2362) );
NAND2X2TS U2734 ( .A(n2466), .B(n2401), .Y(n2361) );
NAND4X4TS U2735 ( .A(n2361), .B(n2362), .C(n2363), .D(n2360), .Y(n2410) );
BUFX12TS U2736 ( .A(n2364), .Y(n2499) );
MXI2X2TS U2737 ( .A(n3148), .B(n2726), .S0(n2571), .Y(n530) );
INVX2TS U2738 ( .A(n2503), .Y(n2522) );
AOI2BB2X4TS U2739 ( .B0(n2499), .B1(n2452), .A0N(n2507), .A1N(n2522), .Y(
n2372) );
NAND2X2TS U2740 ( .A(n2370), .B(left_right_SHT2), .Y(n2371) );
AND2X8TS U2741 ( .A(n2372), .B(n2371), .Y(n3144) );
NAND2X2TS U2742 ( .A(n2466), .B(n1554), .Y(n2374) );
NAND2X2TS U2743 ( .A(n2465), .B(n2452), .Y(n2373) );
AOI21X4TS U2744 ( .A0(n2533), .A1(n1592), .B0(n2379), .Y(n3152) );
NAND2X2TS U2745 ( .A(n2525), .B(n2510), .Y(n2380) );
OAI2BB1X2TS U2746 ( .A0N(n2503), .A1N(n2381), .B0(n2380), .Y(n2382) );
AOI21X4TS U2747 ( .A0(n2383), .A1(n1592), .B0(n2382), .Y(n3150) );
MXI2X2TS U2748 ( .A(n3150), .B(n2731), .S0(n2563), .Y(n529) );
MXI2X2TS U2749 ( .A(n1396), .B(n2735), .S0(n2602), .Y(n572) );
INVX2TS U2750 ( .A(n2580), .Y(n2385) );
NAND2X2TS U2751 ( .A(n2511), .B(n2401), .Y(n2384) );
NAND2X2TS U2752 ( .A(n1605), .B(n851), .Y(n2388) );
NAND2X2TS U2753 ( .A(n2511), .B(n977), .Y(n2387) );
AND2X4TS U2754 ( .A(n2397), .B(n2396), .Y(n3134) );
NAND2X2TS U2755 ( .A(n1604), .B(n2401), .Y(n2404) );
NAND2X2TS U2756 ( .A(n2465), .B(n846), .Y(n2403) );
NAND2X2TS U2757 ( .A(n2509), .B(n2580), .Y(n2402) );
NAND3X4TS U2758 ( .A(n2404), .B(n2403), .C(n2402), .Y(n2456) );
AOI22X2TS U2759 ( .A0(n2516), .A1(n977), .B0(n2499), .B1(n842), .Y(n2405) );
INVX2TS U2760 ( .A(n838), .Y(n2411) );
NAND2X2TS U2761 ( .A(n1544), .B(n2985), .Y(n2415) );
NOR3X1TS U2762 ( .A(n2677), .B(Raw_mant_NRM_SWR[10]), .C(Raw_mant_NRM_SWR[7]), .Y(n2416) );
NAND2X1TS U2763 ( .A(n2417), .B(n2416), .Y(n2418) );
NAND2X1TS U2764 ( .A(n2419), .B(n2627), .Y(n2420) );
OAI2BB1X2TS U2765 ( .A0N(n1301), .A1N(n2724), .B0(n1292), .Y(n587) );
INVX2TS U2766 ( .A(n2432), .Y(n2433) );
NAND2X2TS U2767 ( .A(n2434), .B(n2433), .Y(n2435) );
MXI2X1TS U2768 ( .A(n2438), .B(n1547), .S0(n1609), .Y(n2439) );
AOI22X2TS U2769 ( .A0(n2545), .A1(DmP_mant_SHT1_SW[1]), .B0(n3080), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2445) );
NAND2X1TS U2770 ( .A(n2548), .B(DmP_mant_SHT1_SW[21]), .Y(n2449) );
NOR2X4TS U2771 ( .A(n2451), .B(n1093), .Y(n2455) );
NOR2X4TS U2772 ( .A(n1112), .B(n1583), .Y(n3066) );
NAND2X2TS U2773 ( .A(n1407), .B(n1600), .Y(n3087) );
NAND2X2TS U2774 ( .A(n981), .B(DmP_mant_SHT1_SW[0]), .Y(n3081) );
OAI22X2TS U2775 ( .A0(n1226), .A1(n2861), .B0(n966), .B1(n2860), .Y(
final_result_ieee[11]) );
OAI22X2TS U2776 ( .A0(n1224), .A1(n2853), .B0(n1225), .B1(n2852), .Y(
final_result_ieee[17]) );
OAI22X2TS U2777 ( .A0(n1226), .A1(n2848), .B0(n1223), .B1(n2847), .Y(
final_result_ieee[4]) );
OAI22X2TS U2778 ( .A0(n1227), .A1(n2945), .B0(n1225), .B1(n2944), .Y(
final_result_ieee[18]) );
OAI22X2TS U2779 ( .A0(n1227), .A1(n2875), .B0(n966), .B1(n2874), .Y(
final_result_ieee[8]) );
OAI22X2TS U2780 ( .A0(n1227), .A1(n2972), .B0(n1225), .B1(n2971), .Y(
final_result_ieee[22]) );
OAI22X2TS U2781 ( .A0(n1224), .A1(n2970), .B0(n1225), .B1(n2969), .Y(
final_result_ieee[21]) );
OAI22X2TS U2782 ( .A0(n1226), .A1(n2962), .B0(n1223), .B1(n2961), .Y(
final_result_ieee[0]) );
OAI22X2TS U2783 ( .A0(n1224), .A1(n2931), .B0(n966), .B1(n2930), .Y(
final_result_ieee[13]) );
OAI22X2TS U2784 ( .A0(n1224), .A1(n2864), .B0(n966), .B1(n2863), .Y(
final_result_ieee[7]) );
OAI22X2TS U2785 ( .A0(n1227), .A1(n2857), .B0(n966), .B1(n2856), .Y(
final_result_ieee[10]) );
OAI22X2TS U2786 ( .A0(n1224), .A1(n2871), .B0(n966), .B1(n2870), .Y(
final_result_ieee[12]) );
OAI22X2TS U2787 ( .A0(n1226), .A1(n2868), .B0(n966), .B1(n2867), .Y(
final_result_ieee[9]) );
OAI22X2TS U2788 ( .A0(n1226), .A1(n2952), .B0(n1225), .B1(n2951), .Y(
final_result_ieee[19]) );
OAI22X2TS U2789 ( .A0(n1227), .A1(n2933), .B0(n1225), .B1(n2932), .Y(
final_result_ieee[15]) );
OAI22X2TS U2790 ( .A0(n1227), .A1(n2866), .B0(n1225), .B1(n2865), .Y(
final_result_ieee[14]) );
OAI22X2TS U2791 ( .A0(n1226), .A1(n2885), .B0(n966), .B1(n2884), .Y(
final_result_ieee[6]) );
OAI22X2TS U2792 ( .A0(n1226), .A1(n2935), .B0(n1223), .B1(n2934), .Y(
final_result_ieee[2]) );
OAI22X2TS U2793 ( .A0(n1224), .A1(n2939), .B0(n1225), .B1(n2938), .Y(
final_result_ieee[16]) );
AOI22X2TS U2794 ( .A0(n2516), .A1(n842), .B0(n2525), .B1(n977), .Y(n2458) );
AND2X8TS U2795 ( .A(n2459), .B(n2458), .Y(n3130) );
MXI2X4TS U2796 ( .A(n3130), .B(n2728), .S0(n2571), .Y(n550) );
XNOR2X1TS U2797 ( .A(n2463), .B(n2462), .Y(n2464) );
MXI2X1TS U2798 ( .A(n2464), .B(n2682), .S0(n2561), .Y(n825) );
AND2X8TS U2799 ( .A(n2473), .B(n2472), .Y(n3132) );
CLKMX2X2TS U2800 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[28]), .S0(n3036), .Y(
n683) );
CLKMX2X2TS U2801 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[27]), .S0(n3036), .Y(
n688) );
AOI22X2TS U2802 ( .A0(n2474), .A1(n1592), .B0(n2580), .B1(n2516), .Y(n3154)
);
CLKBUFX3TS U2803 ( .A(n1615), .Y(n3032) );
CLKBUFX2TS U2804 ( .A(n3032), .Y(n3029) );
CLKBUFX2TS U2805 ( .A(n2767), .Y(n2750) );
CLKBUFX3TS U2806 ( .A(n3029), .Y(n3011) );
CLKBUFX3TS U2807 ( .A(n3011), .Y(n2764) );
CLKBUFX3TS U2808 ( .A(n3031), .Y(n3012) );
CLKBUFX3TS U2809 ( .A(n3013), .Y(n2768) );
CLKBUFX3TS U2810 ( .A(n3012), .Y(n2767) );
BUFX3TS U2811 ( .A(n3032), .Y(n3022) );
BUFX3TS U2812 ( .A(n3033), .Y(n3023) );
BUFX3TS U2813 ( .A(n1597), .Y(n3024) );
BUFX3TS U2814 ( .A(n1596), .Y(n3027) );
BUFX3TS U2815 ( .A(n3006), .Y(n3025) );
BUFX3TS U2816 ( .A(n3033), .Y(n3026) );
CLKBUFX3TS U2817 ( .A(n3032), .Y(n3020) );
BUFX3TS U2818 ( .A(n2753), .Y(n3014) );
BUFX3TS U2819 ( .A(n3032), .Y(n3019) );
CLKBUFX3TS U2820 ( .A(n3011), .Y(n2766) );
CLKBUFX2TS U2821 ( .A(n3011), .Y(n2762) );
BUFX3TS U2822 ( .A(n3032), .Y(n3021) );
BUFX3TS U2823 ( .A(n3032), .Y(n3018) );
CLKBUFX3TS U2824 ( .A(n3009), .Y(n2755) );
CLKBUFX3TS U2825 ( .A(n3011), .Y(n2761) );
CLKBUFX2TS U2826 ( .A(n3003), .Y(n2751) );
CLKBUFX3TS U2827 ( .A(n3013), .Y(n2771) );
BUFX3TS U2828 ( .A(n3011), .Y(n2765) );
BUFX3TS U2829 ( .A(n1597), .Y(n3028) );
BUFX3TS U2830 ( .A(n3009), .Y(n3016) );
BUFX3TS U2831 ( .A(n3012), .Y(n2769) );
CLKBUFX3TS U2832 ( .A(n3003), .Y(n2748) );
OAI22X2TS U2833 ( .A0(n1227), .A1(n2954), .B0(n1223), .B1(n2953), .Y(
final_result_ieee[3]) );
OAI22X2TS U2834 ( .A0(n1224), .A1(n2941), .B0(n966), .B1(n2940), .Y(
final_result_ieee[5]) );
INVX2TS U2835 ( .A(n1554), .Y(n3056) );
INVX6TS U2836 ( .A(n2742), .Y(busy) );
INVX2TS U2837 ( .A(n2508), .Y(n3064) );
OAI2BB1X4TS U2838 ( .A0N(n3036), .A1N(n2498), .B0(n1662), .Y(n3159) );
AOI22X2TS U2839 ( .A0(n2525), .A1(n839), .B0(n2503), .B1(n2534), .Y(n2504)
);
MXI2X4TS U2840 ( .A(n3146), .B(n2732), .S0(n2539), .Y(n531) );
NAND2BX4TS U2841 ( .AN(n2507), .B(shift_value_SHT2_EWR_4_), .Y(n2515) );
NAND4X1TS U2842 ( .A(n2827), .B(n2826), .C(n2825), .D(n2824), .Y(n2612) );
AOI22X4TS U2843 ( .A0(n2520), .A1(n1592), .B0(n1351), .B1(n2516), .Y(n3158)
);
MXI2X4TS U2844 ( .A(n3156), .B(n2729), .S0(n3001), .Y(n526) );
MXI2X4TS U2845 ( .A(n2521), .B(n2573), .S0(n3000), .Y(n586) );
AOI2BB2X2TS U2846 ( .B0(n2525), .B1(n2524), .A0N(n2523), .A1N(n2522), .Y(
n2529) );
AND2X8TS U2847 ( .A(n2529), .B(n2528), .Y(n3142) );
MXI2X4TS U2848 ( .A(n3142), .B(n2734), .S0(n2563), .Y(n533) );
AOI21X4TS U2849 ( .A0(n2533), .A1(n1606), .B0(n2532), .Y(n3118) );
NAND2X2TS U2850 ( .A(n2541), .B(n1154), .Y(n3100) );
NAND2X2TS U2851 ( .A(n1154), .B(n3089), .Y(n3045) );
NAND2X2TS U2852 ( .A(n1066), .B(n2543), .Y(n3052) );
NAND2X2TS U2853 ( .A(n1407), .B(n1154), .Y(n3054) );
AOI22X2TS U2854 ( .A0(n2545), .A1(DmP_mant_SHT1_SW[13]), .B0(n3080), .B1(
DmP_mant_SHT1_SW[12]), .Y(n2546) );
NAND2X2TS U2855 ( .A(n2547), .B(n1154), .Y(n3107) );
NAND2X2TS U2856 ( .A(n2547), .B(n1600), .Y(n3053) );
CLKBUFX2TS U2857 ( .A(n1589), .Y(n2752) );
CLKBUFX2TS U2858 ( .A(n2749), .Y(n2753) );
CLKBUFX3TS U2859 ( .A(n3010), .Y(n2759) );
CLKBUFX3TS U2860 ( .A(n2753), .Y(n2773) );
BUFX3TS U2861 ( .A(n2756), .Y(n3002) );
BUFX3TS U2862 ( .A(n3010), .Y(n2757) );
BUFX3TS U2863 ( .A(n3010), .Y(n3008) );
BUFX3TS U2864 ( .A(n1618), .Y(n3007) );
CLKBUFX3TS U2865 ( .A(n1589), .Y(n3006) );
BUFX3TS U2866 ( .A(n2756), .Y(n3005) );
INVX2TS U2867 ( .A(final_result_ieee[11]), .Y(n3135) );
INVX2TS U2868 ( .A(final_result_ieee[17]), .Y(n3147) );
INVX2TS U2869 ( .A(final_result_ieee[4]), .Y(n3121) );
INVX2TS U2870 ( .A(final_result_ieee[18]), .Y(n3149) );
INVX2TS U2871 ( .A(final_result_ieee[8]), .Y(n3129) );
INVX2TS U2872 ( .A(final_result_ieee[22]), .Y(n3157) );
INVX2TS U2873 ( .A(final_result_ieee[21]), .Y(n3155) );
INVX2TS U2874 ( .A(final_result_ieee[0]), .Y(n3114) );
INVX2TS U2875 ( .A(final_result_ieee[13]), .Y(n3139) );
INVX2TS U2876 ( .A(final_result_ieee[7]), .Y(n3127) );
INVX2TS U2877 ( .A(final_result_ieee[10]), .Y(n3133) );
INVX2TS U2878 ( .A(final_result_ieee[12]), .Y(n3137) );
INVX2TS U2879 ( .A(final_result_ieee[9]), .Y(n3131) );
INVX2TS U2880 ( .A(final_result_ieee[19]), .Y(n3151) );
INVX2TS U2881 ( .A(final_result_ieee[20]), .Y(n3153) );
INVX2TS U2882 ( .A(final_result_ieee[15]), .Y(n3143) );
INVX2TS U2883 ( .A(final_result_ieee[14]), .Y(n3141) );
INVX2TS U2884 ( .A(final_result_ieee[6]), .Y(n3125) );
INVX2TS U2885 ( .A(final_result_ieee[2]), .Y(n3117) );
INVX2TS U2886 ( .A(final_result_ieee[16]), .Y(n3145) );
INVX2TS U2887 ( .A(final_result_ieee[3]), .Y(n3119) );
INVX2TS U2888 ( .A(final_result_ieee[5]), .Y(n3123) );
INVX2TS U2889 ( .A(n760), .Y(n2947) );
MXI2X1TS U2890 ( .A(beg_OP), .B(n2719), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2550) );
OAI21X1TS U2891 ( .A0(n2550), .A1(n2592), .B0(n2549), .Y(n931) );
INVX2TS U2892 ( .A(n925), .Y(n2849) );
MXI2X1TS U2893 ( .A(n2555), .B(final_result_ieee[24]), .S0(n3035), .Y(n2556)
);
MXI2X1TS U2894 ( .A(n2557), .B(final_result_ieee[25]), .S0(n3035), .Y(n2558)
);
MXI2X1TS U2895 ( .A(n2635), .B(n2696), .S0(n2571), .Y(n739) );
MXI2X1TS U2896 ( .A(n2636), .B(n2695), .S0(n3001), .Y(n742) );
MXI2X1TS U2897 ( .A(n2638), .B(n1568), .S0(n2539), .Y(n748) );
CLKMX2X2TS U2898 ( .A(DMP_SHT1_EWSW[7]), .B(n1305), .S0(n2589), .Y(n759) );
CLKMX2X2TS U2899 ( .A(DMP_SHT1_EWSW[13]), .B(n1306), .S0(n2589), .Y(n741) );
CLKMX2X2TS U2900 ( .A(DMP_SHT1_EWSW[4]), .B(DMP_EXP_EWSW[4]), .S0(n2589),
.Y(n768) );
CLKMX2X2TS U2901 ( .A(DMP_SHT1_EWSW[11]), .B(DMP_EXP_EWSW[11]), .S0(n2589),
.Y(n747) );
CLKMX2X2TS U2902 ( .A(DMP_SHT1_EWSW[8]), .B(DMP_EXP_EWSW[8]), .S0(n2589),
.Y(n756) );
CLKMX2X2TS U2903 ( .A(DMP_SHT1_EWSW[12]), .B(DMP_EXP_EWSW[12]), .S0(n2589),
.Y(n744) );
CLKMX2X2TS U2904 ( .A(DMP_SHT1_EWSW[10]), .B(DMP_EXP_EWSW[10]), .S0(n2589),
.Y(n750) );
CLKMX2X2TS U2905 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2560),
.Y(n687) );
CLKMX2X2TS U2906 ( .A(n1048), .B(DMP_exp_NRM_EW[2]), .S0(n2560), .Y(n697) );
CLKMX2X2TS U2907 ( .A(n1270), .B(DMP_exp_NRM_EW[1]), .S0(n2560), .Y(n702) );
CLKMX2X2TS U2908 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2560),
.Y(n692) );
CLKMX2X2TS U2909 ( .A(n1283), .B(DMP_exp_NRM_EW[0]), .S0(n2560), .Y(n707) );
CLKMX2X2TS U2910 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n2560),
.Y(n614) );
CLKMX2X2TS U2911 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n2560),
.Y(n605) );
CLKMX2X2TS U2912 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n2591), .Y(
n618) );
INVX8TS U2913 ( .A(n2722), .Y(n2588) );
CLKMX2X2TS U2914 ( .A(DMP_SHT1_EWSW[21]), .B(n1307), .S0(n2588), .Y(n717) );
CLKMX2X2TS U2915 ( .A(DMP_SHT1_EWSW[20]), .B(DMP_EXP_EWSW[20]), .S0(n2588),
.Y(n720) );
CLKMX2X2TS U2916 ( .A(DMP_SHT1_EWSW[22]), .B(DMP_EXP_EWSW[22]), .S0(n2588),
.Y(n714) );
CLKMX2X2TS U2917 ( .A(DMP_SHT1_EWSW[9]), .B(DMP_EXP_EWSW[9]), .S0(n2588),
.Y(n753) );
CLKMX2X2TS U2918 ( .A(DMP_SHT1_EWSW[3]), .B(DMP_EXP_EWSW[3]), .S0(n2591),
.Y(n771) );
CLKMX2X2TS U2919 ( .A(DMP_SHT1_EWSW[6]), .B(DMP_EXP_EWSW[6]), .S0(n2588),
.Y(n762) );
MXI2X1TS U2920 ( .A(n2637), .B(n1585), .S0(n2563), .Y(n745) );
CLKMX2X2TS U2921 ( .A(DMP_SHT1_EWSW[19]), .B(DMP_EXP_EWSW[19]), .S0(n2569),
.Y(n723) );
CLKMX2X2TS U2922 ( .A(DMP_SHT1_EWSW[15]), .B(DMP_EXP_EWSW[15]), .S0(n2569),
.Y(n735) );
CLKMX2X2TS U2923 ( .A(DMP_SHT1_EWSW[17]), .B(DMP_EXP_EWSW[17]), .S0(n2569),
.Y(n729) );
CLKMX2X2TS U2924 ( .A(DMP_SHT1_EWSW[30]), .B(DMP_EXP_EWSW[30]), .S0(n2569),
.Y(n676) );
CLKMX2X2TS U2925 ( .A(DMP_SHT1_EWSW[16]), .B(DMP_EXP_EWSW[16]), .S0(n2569),
.Y(n732) );
CLKMX2X2TS U2926 ( .A(DMP_SHT1_EWSW[14]), .B(DMP_EXP_EWSW[14]), .S0(n2569),
.Y(n738) );
CLKMX2X2TS U2927 ( .A(DMP_SHT1_EWSW[18]), .B(DMP_EXP_EWSW[18]), .S0(n2569),
.Y(n726) );
CLKMX2X2TS U2928 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n2588),
.Y(n668) );
CLKMX2X2TS U2929 ( .A(DmP_mant_SHT1_SW[0]), .B(DmP_EXP_EWSW[0]), .S0(n2588),
.Y(n670) );
CLKMX2X2TS U2930 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2747),
.Y(n672) );
MXI2X1TS U2931 ( .A(n2693), .B(n1011), .S0(n2571), .Y(n769) );
CLKMX2X2TS U2932 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2747),
.Y(n682) );
CLKMX2X2TS U2933 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2747),
.Y(n677) );
MXI2X1TS U2934 ( .A(n2689), .B(n2629), .S0(n2563), .Y(n754) );
MXI2X1TS U2935 ( .A(n2698), .B(n2562), .S0(n2571), .Y(n778) );
MXI2X1TS U2936 ( .A(n2655), .B(n2700), .S0(n2581), .Y(n718) );
MXI2X1TS U2937 ( .A(n2653), .B(n2702), .S0(n2581), .Y(n712) );
MXI2X1TS U2938 ( .A(n2646), .B(n2711), .S0(n3000), .Y(n616) );
MXI2X1TS U2939 ( .A(n2645), .B(n2710), .S0(n2539), .Y(n607) );
MXI2X1TS U2940 ( .A(n2641), .B(n2738), .S0(n2581), .Y(n727) );
MXI2X1TS U2941 ( .A(n2644), .B(n2739), .S0(n2563), .Y(n736) );
MXI2X1TS U2942 ( .A(n2643), .B(n2714), .S0(n2539), .Y(n733) );
MXI2X1TS U2943 ( .A(n2657), .B(n2712), .S0(n2581), .Y(n724) );
MXI2X1TS U2944 ( .A(n2654), .B(n2736), .S0(n2563), .Y(n715) );
MXI2X1TS U2945 ( .A(n2656), .B(n2737), .S0(n2581), .Y(n721) );
MXI2X1TS U2946 ( .A(n2725), .B(n2658), .S0(n3001), .Y(n699) );
MXI2X1TS U2947 ( .A(n2652), .B(n2812), .S0(n2539), .Y(n775) );
MXI2X1TS U2948 ( .A(n2725), .B(n2564), .S0(n2482), .Y(n700) );
NOR2X1TS U2949 ( .A(n2743), .B(DmP_EXP_EWSW[23]), .Y(n2568) );
NOR2X1TS U2950 ( .A(n2568), .B(n2567), .Y(n2570) );
MXI2X1TS U2951 ( .A(n2664), .B(n2570), .S0(n2569), .Y(n827) );
CLKMX2X2TS U2952 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n2482), .Y(
n608) );
CLKMX2X2TS U2953 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n2482),
.Y(n675) );
CLKMX2X2TS U2954 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n2482),
.Y(n734) );
CLKMX2X2TS U2955 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n2482),
.Y(n731) );
CLKMX2X2TS U2956 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n2482), .Y(
n617) );
CLKMX2X2TS U2957 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2482),
.Y(n737) );
CLKMX2X2TS U2958 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n2482),
.Y(n728) );
MXI2X1TS U2959 ( .A(n2690), .B(n2633), .S0(n3001), .Y(n757) );
XNOR2X1TS U2960 ( .A(n1550), .B(n2660), .Y(n2572) );
MXI2X1TS U2961 ( .A(n2628), .B(n2572), .S0(n2576), .Y(n577) );
XNOR2X1TS U2962 ( .A(n1550), .B(n2573), .Y(n2574) );
MXI2X1TS U2963 ( .A(n2639), .B(n2574), .S0(n2576), .Y(n585) );
CLKMX2X2TS U2964 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(busy),
.Y(n685) );
CLKMX2X2TS U2965 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(busy),
.Y(n705) );
CLKMX2X2TS U2966 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(busy),
.Y(n690) );
CLKMX2X2TS U2967 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(busy),
.Y(n695) );
INVX8TS U2968 ( .A(n2742), .Y(n2575) );
CLKMX2X2TS U2969 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n2575),
.Y(n725) );
CLKMX2X2TS U2970 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n3162),
.Y(n767) );
CLKMX2X2TS U2971 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n2575),
.Y(n719) );
CLKMX2X2TS U2972 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(busy),
.Y(n749) );
CLKMX2X2TS U2973 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(busy),
.Y(n776) );
CLKMX2X2TS U2974 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(busy),
.Y(n755) );
CLKMX2X2TS U2975 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n2575),
.Y(n764) );
CLKMX2X2TS U2976 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n2575),
.Y(n722) );
CLKMX2X2TS U2977 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n2575),
.Y(n773) );
CLKMX2X2TS U2978 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(busy),
.Y(n746) );
CLKMX2X2TS U2979 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n3162),
.Y(n740) );
CLKMX2X2TS U2980 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n3162),
.Y(n758) );
CLKMX2X2TS U2981 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n2575),
.Y(n716) );
CLKMX2X2TS U2982 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n2575),
.Y(n761) );
CLKMX2X2TS U2983 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n2575),
.Y(n770) );
CLKMX2X2TS U2984 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n2575),
.Y(n713) );
CLKMX2X2TS U2985 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n3162),
.Y(n779) );
CLKMX2X2TS U2986 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n3162),
.Y(n743) );
CLKMX2X2TS U2987 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n2575),
.Y(n752) );
CLKMX2X2TS U2988 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[30]), .S0(n2576), .Y(
n673) );
NAND2X2TS U2989 ( .A(n1611), .B(n2577), .Y(n3050) );
NAND2X2TS U2990 ( .A(n1611), .B(n2578), .Y(n3078) );
NAND2X2TS U2991 ( .A(n1611), .B(n2579), .Y(n3043) );
NAND2X1TS U2992 ( .A(n1610), .B(n2580), .Y(n3099) );
MXI2X1TS U2993 ( .A(n2699), .B(n2630), .S0(n3001), .Y(n751) );
CLKMX2X2TS U2994 ( .A(n1612), .B(DmP_EXP_EWSW[15]), .S0(n2588), .Y(n640) );
CLKMX2X2TS U2995 ( .A(DmP_mant_SHT1_SW[19]), .B(DmP_EXP_EWSW[19]), .S0(n2591), .Y(n632) );
XNOR2X1TS U2996 ( .A(n1550), .B(n2812), .Y(n2583) );
XNOR2X1TS U2997 ( .A(n2585), .B(n2584), .Y(n2586) );
CLKMX2X2TS U2998 ( .A(DmP_mant_SHT1_SW[20]), .B(n1276), .S0(n2589), .Y(n630)
);
CLKMX2X2TS U2999 ( .A(DMP_SHT1_EWSW[5]), .B(DMP_EXP_EWSW[5]), .S0(n2590),
.Y(n765) );
MXI2X4TS U3000 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2592), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2603) );
NAND2X8TS U3001 ( .A(n2603), .B(beg_OP), .Y(n2596) );
CLKMX2X2TS U3002 ( .A(Data_Y[0]), .B(n1328), .S0(n2593), .Y(n889) );
CLKMX2X3TS U3003 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n2598), .Y(n860)
);
CLKMX2X2TS U3004 ( .A(Data_Y[19]), .B(n1015), .S0(n2594), .Y(n870) );
CLKMX2X2TS U3005 ( .A(Data_Y[2]), .B(n1564), .S0(n2595), .Y(n887) );
CLKMX2X2TS U3006 ( .A(Data_Y[3]), .B(n1562), .S0(n2595), .Y(n886) );
CLKMX2X3TS U3007 ( .A(Data_Y[26]), .B(intDY_EWSW[26]), .S0(n2598), .Y(n863)
);
CLKMX2X3TS U3008 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n2598), .Y(n865)
);
CLKMX2X2TS U3009 ( .A(Data_Y[10]), .B(n1557), .S0(n2595), .Y(n879) );
CLKMX2X2TS U3010 ( .A(Data_Y[20]), .B(n1571), .S0(n2594), .Y(n869) );
CLKMX2X2TS U3011 ( .A(Data_Y[16]), .B(n1264), .S0(n2594), .Y(n873) );
CLKMX2X2TS U3012 ( .A(Data_Y[11]), .B(n953), .S0(n2595), .Y(n878) );
CLKMX2X3TS U3013 ( .A(Data_Y[25]), .B(intDY_EWSW[25]), .S0(n2598), .Y(n864)
);
CLKMX2X2TS U3014 ( .A(Data_Y[21]), .B(n1322), .S0(n2594), .Y(n868) );
CLKMX2X2TS U3015 ( .A(Data_Y[12]), .B(n1376), .S0(n2594), .Y(n877) );
CLKMX2X2TS U3016 ( .A(Data_Y[6]), .B(n1367), .S0(n2595), .Y(n883) );
CLKMX2X2TS U3017 ( .A(Data_Y[18]), .B(n1060), .S0(n2594), .Y(n871) );
CLKMX2X2TS U3018 ( .A(Data_Y[7]), .B(n951), .S0(n2595), .Y(n882) );
CLKMX2X2TS U3019 ( .A(Data_X[30]), .B(n1578), .S0(n2599), .Y(n893) );
CLKMX2X2TS U3020 ( .A(Data_X[29]), .B(n1330), .S0(n2599), .Y(n894) );
CLKMX2X2TS U3021 ( .A(Data_X[8]), .B(n1288), .S0(n2597), .Y(n915) );
CLKMX2X2TS U3022 ( .A(Data_X[3]), .B(n1372), .S0(n2597), .Y(n920) );
CLKMX2X2TS U3023 ( .A(Data_X[5]), .B(n1581), .S0(n2597), .Y(n918) );
CLKMX2X2TS U3024 ( .A(Data_X[23]), .B(n1357), .S0(n2599), .Y(n900) );
CLKMX2X2TS U3025 ( .A(Data_X[17]), .B(n1386), .S0(n2600), .Y(n906) );
CLKMX2X2TS U3026 ( .A(Data_X[26]), .B(n1364), .S0(n2599), .Y(n897) );
CLKMX2X2TS U3027 ( .A(Data_X[27]), .B(n1382), .S0(n2599), .Y(n896) );
CLKMX2X2TS U3028 ( .A(Data_X[21]), .B(n1331), .S0(n2600), .Y(n902) );
CLKMX2X2TS U3029 ( .A(Data_X[25]), .B(n1561), .S0(n2599), .Y(n898) );
CLKMX2X2TS U3030 ( .A(Data_X[2]), .B(n1296), .S0(n2597), .Y(n921) );
CLKMX2X2TS U3031 ( .A(Data_X[4]), .B(n1278), .S0(n2597), .Y(n919) );
CLKMX2X2TS U3032 ( .A(Data_X[11]), .B(n1560), .S0(n2597), .Y(n912) );
CLKMX2X2TS U3033 ( .A(Data_X[24]), .B(n1284), .S0(n2599), .Y(n899) );
CLKMX2X2TS U3034 ( .A(Data_X[19]), .B(n1577), .S0(n2600), .Y(n904) );
CLKMX2X2TS U3035 ( .A(Data_X[13]), .B(n1362), .S0(n2600), .Y(n910) );
CLKMX2X2TS U3036 ( .A(Data_X[7]), .B(n1360), .S0(n2597), .Y(n916) );
CLKMX2X2TS U3037 ( .A(Data_X[16]), .B(n1327), .S0(n2600), .Y(n907) );
CLKMX2X2TS U3038 ( .A(Data_X[1]), .B(n1371), .S0(n2598), .Y(n922) );
CLKMX2X2TS U3039 ( .A(Data_X[22]), .B(n1369), .S0(n2599), .Y(n901) );
MXI2X1TS U3040 ( .A(n2683), .B(n2601), .S0(n2604), .Y(n926) );
MXI2X1TS U3041 ( .A(n2722), .B(n2742), .S0(n2604), .Y(n928) );
MXI2X1TS U3042 ( .A(n2742), .B(n2683), .S0(n2604), .Y(n927) );
MXI2X1TS U3043 ( .A(n2715), .B(n2722), .S0(n2604), .Y(n929) );
CLKINVX1TS U3044 ( .A(n2603), .Y(n2605) );
MXI2X1TS U3045 ( .A(n2605), .B(n2715), .S0(n2604), .Y(n930) );
NAND2X1TS U3046 ( .A(n2608), .B(DmP_EXP_EWSW[0]), .Y(n2609) );
AFCSHCINX4TS U3047 ( .CI1N(DP_OP_297J37_122_8400_n138), .B(
DmP_mant_SFG_SWR_signed[15]), .A(DMP_SFG[13]), .CI0N(
DP_OP_297J37_122_8400_n139), .CS(n2626), .CO1(
DP_OP_297J37_122_8400_n136), .CO0(DP_OP_297J37_122_8400_n137), .S(
Raw_mant_SGF[15]) );
AFCSIHCONX4TS U3048 ( .A(n1567), .B(DmP_mant_SFG_SWR_signed[12]), .CS(n2626),
.S(Raw_mant_SGF[12]), .CO0N(DP_OP_297J37_122_8400_n143), .CO1N(
DP_OP_297J37_122_8400_n142) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_GDAN16M4P8_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_2_V
`define SKY130_FD_SC_HD__HA_2_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ha_2 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ha_2 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_2_V
|
/*
* Command Processor
*
* Process the received command and then do the action corresponding to the command and present state
*
* Control almost all enable signals of the baseband processor
*
* This module has the greatest immediate power dissipation, because of the huge computing of combinational logic
*
* By Operand Isolation technique save the power dissipation and reduce the max. immediate power
*
* This design of baseband processor is improved by TSMC 0.18 um CMOS standard process
* it does not support EEPROM, so we chose ROM to be the baseband processor's memory
* because we use ROM to be the memory, we are not able to verify the Write command
*/
`timescale 1us / 1ns
module cmd_proc
(
output reg reply_data,
output reg reply_complete,
output reg dr,
output reg [1:0]m,
output reg trext,
output reg en_2nd_clk_cp,
output reg en_tx,
output reg en_prng_idol,
output reg en_prng_act,
output reg en_crc16_for_rpy,
output reg en_if,
output reg [18:0]addr,
input clk_cp,
input clk_frm,
input rst_n,
input rst_for_new_package,
input [7:0]cmd,
input [51:0]param,
input crc_check_pass,
input [15:0]prn,
input pre_p_complete,
input p_complete,
input rd_data,
input rd_complete
);
// --- mandatory commands of EPC Gen2 protocol ---
parameter QueryRep = 8'b0000_1100;
parameter ACK = 8'b0000_1101;
parameter Query = 8'b0011_1000;
parameter QueryAdjust = 8'b0011_1001;
parameter Select = 8'b0011_1010;
parameter NAK = 8'b1100_0000;
parameter Req_RN = 8'b1100_0001;
parameter Read = 8'b1100_0010;
//parameter Write = 8'b1100_0011;
parameter Kill = 8'b1100_0100;
parameter Lock = 8'b1100_0101;
// --- working states ---
parameter Ready = 4'h0;
parameter Sloting = 4'h1;
parameter Arbitrate = 4'h2;
parameter Reply = 4'h3;
parameter Acknowledged = 4'h4;
parameter SlotTran = 4'h5;
parameter Open = 4'h6;
parameter Secured = 4'h7;
parameter Killing = 4'h8;
parameter Killed = 4'h9;
// --- actions ---
parameter do_nothing = 5'h00;
parameter set_sl_or_if = 5'h01;
parameter init_inventory = 5'h02;
parameter adj_q = 5'h03;
parameter dec_slot = 5'h04;
parameter bs_new_rn16 = 5'h05;
parameter reply_ack = 5'h06;
parameter bs_new_rn16_tran_if = 5'h07;
parameter adj_q_tran_if = 5'h08;
parameter dec_slot_tran_if = 5'h09;
parameter tran_if = 5'h0a;
parameter gen_and_bs_new_handle = 5'h0b;
parameter bs_new_rn16_crc16 = 5'h0c;
parameter bs_read_data = 5'h0d;
parameter bs_handle = 5'h0e;
parameter bs_header_kill = 5'h0f;
parameter bs_header_lock = 5'h10;
parameter bs_error_code = 5'h11;
wire clk_cp_n;
reg [7:0]cmd_checked; // checked command
reg [3:0]ps; // present state
reg [3:0]ns; // next state
reg [4:0]act; // action
reg mch; // matching/not-matching
reg [7:0]ptr; // pointer of Select command (bit addressing)
reg trct; // parameter Truncate of Select command
reg [1:0]sl; // SL flag
reg if_s0; // inventoried flag of session 0
reg if_s1; // inventoried flag of session 1
reg if_s2; // inventoried flag of session 2
reg if_s3; // inventoried flag of session 3
//reg dr; // divide ratio
//reg [1:0]m; // cycles per symbol
//reg trext; // pilot tone
reg [1:0]session; // tag's 4 sessions
reg [3:0]q; // # of bits of slot
reg [14:0]slot; // slot counter
reg [9:0]lock_act; // action of Lock command
reg tid_lock;
reg epc_lock;
reg accs_lock;
reg kill_lock;
reg [4:0]act_reg;
reg [15:0]rn16; // 16-bit random number for backscattering new RN16
reg [15:0]handle; // 16-bit random number for backscattering "handle"
reg en_if_d;
reg [4:0]r_cnt; // reply counter
reg [4:0]r_end; // end point of reply counter
// --- check the receieved command ---
always@(*) begin
if(cmd == Query | cmd == Select | cmd == Req_RN | cmd == Read | cmd == Kill | cmd == Lock) begin
if(crc_check_pass) cmd_checked = cmd;
else cmd_checked = 8'h00;
end
else cmd_checked = cmd;
end
// --- state register ---
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) ps <= Ready;
else ps <= ns;
end
// --- next state logic ---
always@(*) begin
case(ps)
Ready : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else ns = Ready;
Sloting : if(slot == 15'b0) ns = Reply;
else ns = Arbitrate;
Arbitrate : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Sloting;
else ns = Arbitrate;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Sloting;
else ns = Arbitrate;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Arbitrate;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Arbitrate;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Arbitrate;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Arbitrate;
else ns = Ready;
end
else ns = Arbitrate;
Reply : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Arbitrate;
else ns = Reply;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Sloting;
else ns = Reply;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) ns = Acknowledged;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Arbitrate;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Reply;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Reply;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Reply;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Reply;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Arbitrate;
else if(cmd_checked == Kill) ns = Arbitrate;
else if(cmd_checked == Lock) ns = Arbitrate;
else ns = Reply;
Acknowledged : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Acknowledged;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Acknowledged;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) ns = Acknowledged;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) begin
if(param[31:16] == rn16) ns = Secured;
else ns = Acknowledged;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Acknowledged;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Acknowledged;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Acknowledged;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Acknowledged;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Arbitrate;
else if(cmd_checked == Kill) ns = Arbitrate;
else if(cmd_checked == Lock) ns = Arbitrate;
else ns = Acknowledged;
SlotTran : if(slot == 15'b0) ns = Reply;
else ns = Arbitrate;
Open : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Open;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Open;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == handle) ns = Open;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Open;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Open;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Open;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Open;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Open;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Open;
else if(cmd_checked == Kill) begin
// the first 16 bits kill password is d357
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) ns = Killing;
else ns = Arbitrate;
end
else if(cmd_checked == Lock) ns = Open;
else ns = Open;
Secured : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Secured;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Secured;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == handle) ns = Secured;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Secured;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Secured;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Secured;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Secured;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Secured;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Secured;
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) ns = Killing;
else ns = Arbitrate;
end
else if(cmd_checked == Lock) ns = Secured;
else ns = Secured;
Killing : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == Req_RN) ns = Killing;
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'h06cc & param[31:16] == handle) ns = Killed;
else ns = Arbitrate;
end
else ns = Arbitrate;
Killed : ns = Killed;
default : ns = Arbitrate;
endcase
end
// --- output logic ---
always@(*) begin
case(ps)
Ready : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Sloting : if(slot == 15'b0) act = bs_new_rn16;
else act = do_nothing;
Arbitrate : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Reply : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Acknowledged : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == rn16) act = gen_and_bs_new_handle;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
SlotTran : if(param[11:10] == session) begin
if(slot == 15'b0) act = bs_new_rn16_tran_if;
else act = tran_if;
end
else act = do_nothing;
Open : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else if(cmd_checked == Read) begin
case(param[49:48])
2'b00 : if(param[39:32] == 8'h0) begin
if(~kill_lock & ~accs_lock & param[47:40] < 8'h3) act = bs_read_data;
else act = bs_error_code;
end
else begin
if((~kill_lock & param[47:40] < 8'h2 & (param[47:40] + param[39:32] < 8'h3)) |
(~accs_lock & param[47:40] < 8'h4 & param[47:40] > 8'h1 & (param[47:40] + param[39:32] < 8'h5)) |
(~kill_lock & ~accs_lock & (param[47:40] + param[39:32] < 8'h5))) act = bs_read_data;
else act = bs_error_code;
end
2'b01 : if(param[39:32] == 8'h0) begin
if(~epc_lock & (param[47:40] < 8'h15)) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~epc_lock & ((param[47:40] + param[39:32]) < 8'hf)) act = bs_read_data;
else act = bs_error_code;
end
2'b10 : if(param[39:32] == 8'h0) begin
if(~tid_lock & param[47:40] < 8'h2) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~tid_lock & ((param[47:40] + param[39:32]) < 8'h3)) act = bs_read_data;
else act = bs_error_code;
end
2'b11 : act = bs_error_code;
endcase
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) act = bs_handle;
else act = do_nothing;
end
else act = do_nothing;
Secured : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else if(cmd_checked == Read) begin
case(param[49:48])
2'b00 : if(param[39:32] == 8'h0) begin
if(~kill_lock & ~accs_lock & param[47:40] < 8'h3) act = bs_read_data;
else act = bs_error_code;
end
else begin
if((~kill_lock & param[47:40] < 8'h2 & (param[47:40] + param[39:32] < 8'h3)) |
(~accs_lock & param[47:40] < 8'h4 & param[47:40] > 8'h1 & (param[47:40] + param[39:32] < 8'h5)) |
(~kill_lock & ~accs_lock & (param[47:40] + param[39:32] < 8'h5))) act = bs_read_data;
else act = bs_error_code;
end
2'b01 : if(param[39:32] == 8'h0) begin
if(~epc_lock & (param[47:40] < 8'h15)) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~epc_lock & ((param[47:40] + param[39:32]) < 8'hf)) act = bs_read_data;
else act = bs_error_code;
end
2'b10 : if(param[39:32] == 8'h0) begin
if(~tid_lock & param[47:40] < 8'h2) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~tid_lock & ((param[47:40] + param[39:32]) < 8'h3)) act = bs_read_data;
else act = bs_error_code;
end
2'b11 : act = bs_error_code;
endcase
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) act = bs_handle;
else act = do_nothing;
end
else if(cmd_checked == Lock) begin
if(param[43:42] != 2'b00 | (({param[50], param[40]} == 2'b10) & lock_act[8]) | (({param[48], param[38]} == 2'b10) & lock_act[6]) | (({param[46], param[36]} == 2'b10) & lock_act[4]) | (({param[44], param[34]} == 2'b10) & lock_act[2])) act = bs_error_code;
else act = bs_header_lock;
end
else act = do_nothing;
Killing : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'h06cc & param[31:16] == handle) act = bs_header_kill;
else act = do_nothing;
end
else act = do_nothing;
Killed : act = do_nothing;
default : act = do_nothing;
endcase
end
// --- define matching/not-matching from Select command ---
always@(*) begin
if(act == set_sl_or_if) begin
if(param[45:44] == 2'b01 & param[43:36] < 8'b1100_0000 & ((param[43:36] - param[35:28]) > 8'b0)) mch = 1'b1;
else if(param[45:44] == 2'b10 & param[43:36] < 8'b0010_0000 & ((param[43:36] - param[35:28]) > 8'b0)) mch = 1'b1;
end
else mch = 1'b0;
end
// --- execute the actions ---
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) ptr <= 8'b0;
else if(act == set_sl_or_if) ptr <= param[43:36] - param[35:28];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) trct <= 1'b0;
else if(act == set_sl_or_if) trct <= param[16];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) sl <= 2'b10;
else if(act == set_sl_or_if & param[51:49] == 3'b100) begin
if(mch) begin
case(param[48:46])
3'b000 : sl <= 2'b11;
3'b001 : sl <= 2'b11;
3'b011 : sl <= ~sl;
3'b100 : sl <= 2'b10;
3'b101 : sl <= 2'b10;
endcase
end
else begin
case(param[48:46])
3'b000 : sl <= 2'b10;
3'b010 : sl <= 2'b10;
3'b100 : sl <= 2'b11;
3'b110 : sl <= 2'b11;
3'b111 : sl <= ~sl;
endcase
end
end
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s0 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b000) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s0 <= 1'b0;
3'b001 : if_s0 <= 1'b0;
3'b011 : if_s0 <= ~if_s0;
3'b100 : if_s0 <= 1'b0;
3'b101 : if_s0 <= 1'b0;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s0 <= 1'b1;
3'b010 : if_s0 <= 1'b1;
3'b100 : if_s0 <= 1'b0;
3'b110 : if_s0 <= 1'b0;
3'b111 : if_s0 <= ~if_s0;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == dec_slot_tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == adj_q_tran_if & session == 2'b00) if_s0 <= ~if_s0;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s1 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b001) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s1 <= 1'b0;
3'b001 : if_s1 <= 1'b0;
3'b011 : if_s1 <= ~if_s1;
3'b100 : if_s1 <= 1'b1;
3'b101 : if_s1 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s1 <= 1'b1;
3'b010 : if_s1 <= 1'b1;
3'b100 : if_s1 <= 1'b0;
3'b110 : if_s1 <= 1'b0;
3'b111 : if_s1 <= ~if_s1;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == dec_slot_tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == adj_q_tran_if & session == 2'b01) if_s1 <= ~if_s1;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s2 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b010) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s2 <= 1'b0;
3'b001 : if_s2 <= 1'b0;
3'b011 : if_s2 <= ~if_s2;
3'b100 : if_s2 <= 1'b1;
3'b101 : if_s2 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s2 <= 1'b1;
3'b010 : if_s2 <= 1'b1;
3'b100 : if_s2 <= 1'b0;
3'b110 : if_s2 <= 1'b0;
3'b111 : if_s2 <= ~if_s2;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == dec_slot_tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == adj_q_tran_if & session == 2'b10) if_s2 <= ~if_s2;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s3 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b011) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s3 <= 1'b0;
3'b001 : if_s3 <= 1'b0;
3'b011 : if_s3 <= ~if_s3;
3'b100 : if_s3 <= 1'b1;
3'b101 : if_s3 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s3 <= 1'b1;
3'b010 : if_s3 <= 1'b1;
3'b100 : if_s3 <= 1'b0;
3'b110 : if_s3 <= 1'b0;
3'b111 : if_s3 <= ~if_s3;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == dec_slot_tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == adj_q_tran_if & session == 2'b11) if_s3 <= ~if_s3;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) dr <= 1'b0;
else if(act == init_inventory) dr <= param[17];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) m <= 2'b00;
else if(act == init_inventory) m <= param[16:15];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) trext <= 1'b0;
else if(act == init_inventory) trext <= param[14];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) session <= 2'b00;
else if(act == init_inventory) session <= param[11:10];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) q <= 4'b0;
else if(act == init_inventory) q <= param[8:5];
else if(act == adj_q | act == adj_q_tran_if) begin
if(param[2:0] == 3'b110) q <= q + 4'b1;
else if(param[2:0] == 3'b011) q <= q - 4'b1;
end
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) slot <= 15'h2ac7;
else if(act == init_inventory) begin
case(param[8:5])
4'h0 : slot <= 15'b0;
4'h1 : slot <= {14'b0, prn[0]};
4'h2 : slot <= {13'b0, prn[1:0]};
4'h3 : slot <= {12'b0, prn[2:0]};
4'h4 : slot <= {11'b0, prn[3:0]};
4'h5 : slot <= {10'b0, prn[4:0]};
4'h6 : slot <= {9'b0, prn[5:0]};
4'h7 : slot <= {8'b0, prn[6:0]};
4'h8 : slot <= {7'b0, prn[7:0]};
4'h9 : slot <= {6'b0, prn[8:0]};
4'ha : slot <= {5'b0, prn[9:0]};
4'hb : slot <= {4'b0, prn[10:0]};
4'hc : slot <= {3'b0, prn[11:0]};
4'hd : slot <= {2'b0, prn[12:0]};
4'he : slot <= {1'b0, prn[13:0]};
4'hf : slot <= prn[14:0];
endcase
end
else if(act == adj_q | act == adj_q_tran_if) begin
if(param[2:0] == 3'b110) begin
case(q)
4'hf : slot <= 15'b0;
4'h0 : slot <= {14'b0, prn[0]};
4'h1 : slot <= {13'b0, prn[1:0]};
4'h2 : slot <= {12'b0, prn[2:0]};
4'h3 : slot <= {11'b0, prn[3:0]};
4'h4 : slot <= {10'b0, prn[4:0]};
4'h5 : slot <= {9'b0, prn[5:0]};
4'h6 : slot <= {8'b0, prn[6:0]};
4'h7 : slot <= {7'b0, prn[7:0]};
4'h8 : slot <= {6'b0, prn[8:0]};
4'h9 : slot <= {5'b0, prn[9:0]};
4'ha : slot <= {4'b0, prn[10:0]};
4'hb : slot <= {3'b0, prn[11:0]};
4'hc : slot <= {2'b0, prn[12:0]};
4'hd : slot <= {1'b0, prn[13:0]};
4'he : slot <= prn[14:0];
endcase
end
else if(param[2:0] == 3'b011) begin
case(q)
4'h1 : slot <= 15'b0;
4'h2 : slot <= {14'b0, prn[0]};
4'h3 : slot <= {13'b0, prn[1:0]};
4'h4 : slot <= {12'b0, prn[2:0]};
4'h5 : slot <= {11'b0, prn[3:0]};
4'h6 : slot <= {10'b0, prn[4:0]};
4'h7 : slot <= {9'b0, prn[5:0]};
4'h8 : slot <= {8'b0, prn[6:0]};
4'h9 : slot <= {7'b0, prn[7:0]};
4'ha : slot <= {6'b0, prn[8:0]};
4'hb : slot <= {5'b0, prn[9:0]};
4'hc : slot <= {4'b0, prn[10:0]};
4'hd : slot <= {3'b0, prn[11:0]};
4'he : slot <= {2'b0, prn[12:0]};
4'hf : slot <= {1'b0, prn[13:0]};
4'h0 : slot <= prn[14:0];
endcase
end
end
else if(act == dec_slot | act == dec_slot_tran_if) slot <= slot - 15'b1;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) lock_act <= 10'b00_0000_0011;
else begin
if(act == bs_header_lock) begin
if(param[43:42] != 2'b00) lock_act <= lock_act;
else if(({param[50], param[40]} == 2'b10) & lock_act[8]) lock_act <= lock_act;
else if(({param[48], param[38]} == 2'b10) & lock_act[6]) lock_act <= lock_act;
else if(({param[46], param[36]} == 2'b10) & lock_act[4]) lock_act <= lock_act;
else if(({param[44], param[34]} == 2'b10) & lock_act[2]) lock_act <= lock_act;
else begin
if(param[51]) lock_act[9] <= param[41];
if(param[50]) lock_act[8] <= param[40];
if(param[49]) lock_act[7] <= param[39];
if(param[48]) lock_act[6] <= param[38];
if(param[47]) lock_act[5] <= param[37];
if(param[46]) lock_act[4] <= param[36];
if(param[45]) lock_act[3] <= param[35];
if(param[44]) lock_act[2] <= param[34];
// if(param[43]) lock_act[1] <= param[33];
// if(param[42]) lock_act[0] <= param[32];
end
end
end
end
// --- Lcok action-field functionality ---
always@(*) begin
case(lock_act[3:2])
2'b00 : if((ps == Open) | (ps == Secured)) tid_lock = 0;
else tid_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) tid_lock = 0;
else tid_lock = 1;
2'b10 : if(ps == Secured) tid_lock = 0;
else tid_lock = 1;
2'b11 : tid_lock = 1;
endcase
end
always@(*) begin
case(lock_act[5:4])
2'b00 : if((ps == Open) | (ps == Secured)) epc_lock = 0;
else epc_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) epc_lock = 0;
else epc_lock = 1;
2'b10 : if(ps == Secured) epc_lock = 0;
else epc_lock = 1;
2'b11 : epc_lock = 1;
endcase
end
always@(*) begin
case(lock_act[7:6])
2'b00 : if((ps == Open) | (ps == Secured)) accs_lock = 0;
else accs_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) accs_lock = 0;
else accs_lock = 1;
2'b10 : if(ps == Secured) accs_lock = 0;
else accs_lock = 1;
2'b11 : accs_lock = 1;
endcase
end
always@(*) begin
case(lock_act[9:8])
2'b00 : if((ps == Open) | (ps == Secured)) kill_lock = 0;
else kill_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) kill_lock = 0;
else kill_lock = 1;
2'b10 : if(ps == Secured) kill_lock = 0;
else kill_lock = 1;
2'b11 : kill_lock = 1;
endcase
end
// --- action register for operand isolation ---
always@(posedge clk_cp or negedge rst_for_new_package) begin
if(~rst_for_new_package) act_reg <= 5'h0;
else act_reg <= act;
end
// --- clk_cp control ---
always@(*) begin
if(act_reg == init_inventory | act_reg == adj_q | act_reg == dec_slot | act_reg == adj_q_tran_if | act_reg == dec_slot_tran_if) en_2nd_clk_cp = 1'b1;
else en_2nd_clk_cp = 1'b0;
end
// --- enable PRNG ---
always@(*) begin
if(ps == Ready) en_prng_idol = 1'b1;
else en_prng_idol = 1'b0;
end
always@(*) begin
if(act_reg == bs_new_rn16 | act_reg == bs_new_rn16_tran_if | act_reg == gen_and_bs_new_handle | act_reg == bs_new_rn16_crc16) en_prng_act = 1'b1;
else en_prng_act = 1'b0;
end
// --- enable TX ---
always@(*) begin
case(act_reg)
bs_new_rn16 : en_tx = 1'b1;
reply_ack : en_tx = 1'b1;
bs_new_rn16_tran_if : en_tx = 1'b1;
gen_and_bs_new_handle : en_tx = 1'b1;
bs_new_rn16_crc16 : en_tx = 1'b1;
bs_read_data : en_tx = 1'b1;
bs_handle : en_tx = 1'b1;
bs_header_kill : en_tx = 1'b1;
bs_header_lock : en_tx = 1'b1;
bs_error_code : en_tx = 1'b1;
default : en_tx = 1'b0;
endcase
end
// --- enable memory interface and ROM ---
always@(*) begin
if(act_reg == reply_ack) begin
if(~trct & pre_p_complete) en_if = 1'b1;
else if(trct & p_complete & (r_cnt < r_end + 5'h02)) en_if = 1'b1;
else en_if = 1'b0;
end
else if(act_reg == bs_read_data) begin
if(p_complete) en_if = 1'b1;
else en_if = 1'b0;
end
else en_if = 1'b0;
end
// --- enable CRC-16 for replying data ---
always@(*) begin
if(p_complete & (act_reg == reply_ack | act_reg == gen_and_bs_new_handle | act_reg == bs_new_rn16_crc16 | act_reg == bs_read_data |
act_reg == bs_handle | act_reg == bs_header_kill | act_reg == bs_header_lock)) en_crc16_for_rpy = 1'b1;
else en_crc16_for_rpy = 1'b0;
end
// --- deliver address to memory interface ---
always@(*) begin
if(act_reg == reply_ack) begin
if(~trct) addr = {1'b0, 2'b01, 8'b0, 8'b0};
else addr = {1'b0, 2'b01, ptr, 8'b0};
end
else if(act_reg == bs_read_data) addr = {1'b1, param[49:32]};
else addr = 19'b0;
end
// --- load a new RN16 or handle ---
assign clk_cp_n = ~clk_cp;
always@(posedge clk_cp_n or negedge rst_n) begin
if(~rst_n) rn16 <= 16'hac70;
else if(act_reg == bs_new_rn16 | act_reg == bs_new_rn16_tran_if | act_reg == bs_new_rn16_crc16) rn16 <= prn[15:0];
end
always@(posedge clk_cp_n or negedge rst_n) begin
if(~rst_n) handle <= 16'hff31;
else if(act_reg == gen_and_bs_new_handle) handle <= prn[15:0];
end
// --- enable/disable reply counter ---
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) en_if_d <= 1'b0;
else en_if_d <= en_if;
end
wire en_r_cnt;
assign en_r_cnt = ~en_if_d | rd_complete;
// --- control reply counter ---
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) r_cnt <= 5'h17;
else if(p_complete & en_r_cnt) begin
if(r_cnt != r_end) r_cnt <= r_cnt - 1;
else r_cnt <= r_cnt;
end
end
// --- determine the end of reply counter ---
always@(*) begin
case(act_reg)
bs_new_rn16 : r_end = 5'h08;
reply_ack : if(~trct) r_end = 5'h17;
else r_end = 5'h12;
bs_new_rn16_tran_if : r_end = 5'h08;
gen_and_bs_new_handle : r_end = 5'h08;
bs_new_rn16_crc16 : r_end = 5'h08;
bs_read_data : r_end = 5'h06;
bs_handle : r_end = 5'h08;
bs_header_kill : r_end = 5'h07;
bs_header_lock : r_end = 5'h07;
bs_error_code : r_end = 5'h00;
default : r_end = 5'h00;
endcase
end
// --- reply data ---
always@(*) begin
case(act_reg)
bs_new_rn16 : reply_data = rn16[r_cnt - 5'h08];
reply_ack : if(~trct) reply_data = rd_data;
else begin
if(r_cnt > 5'h12) reply_data = 1'b0;
else reply_data = rd_data;
end
bs_new_rn16_tran_if : reply_data = rn16[r_cnt - 5'h08];
gen_and_bs_new_handle : reply_data = handle[r_cnt - 5'h08];
bs_new_rn16_crc16 : reply_data = rn16[r_cnt - 5'h08];
bs_read_data : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt == 5'h16) reply_data = rd_data;
else if(r_cnt < 5'h16 & r_cnt > 5'h5) reply_data = handle[r_cnt - 5'h6];
else reply_data = 1'b0;
bs_handle : reply_data = handle[r_cnt - 5'h08];
bs_header_kill : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt < 5'h17 & r_cnt > 5'h6) reply_data = handle[r_cnt - 5'h07];
else reply_data = 1'b0;
bs_header_lock : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt < 5'h17 & r_cnt > 5'h6) reply_data = handle[r_cnt - 5'h07];
else reply_data = 1'b0;
bs_error_code : if(r_cnt > 5'h13) reply_data = 1'b0;
else if(r_cnt < 5'h14 & r_cnt > 5'h0f) reply_data = 1'b1;
else reply_data = handle[r_cnt];
default : reply_data = 1'b0;
endcase
end
// --- determine when does the replying data complete ---
always@(*) begin
if(act_reg == reply_ack) begin
if(rd_complete) reply_complete = 1'b1;
else reply_complete = 1'b0;
end
else begin
if(r_cnt == r_end) reply_complete = 1'b1;
else reply_complete = 1'b0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvgnd2 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V |
module scratch_pad_tb;
//TODO: clean up code, fewer display statements
`include "log2.vh"
`include "abs.vh"
`include "constants.vh"
parameter PORTS = 4;
parameter REORDER_DEPTH=64;
parameter OUT_FILE="simulation.csv";
//TODO: track down why WIDTH=8 does not work
`define WIDTH 64
`define FRAGMENT_DEPTH 512
`define DEPTH PORTS*`FRAGMENT_DEPTH
`define ADDR_WIDTH log2(`DEPTH-1)
`define ADDR_TEST_MAX (`FRAGMENT_DEPTH * 2)
reg rst, clk;
reg [0:PORTS-1] rd_en, wr_en;
reg [PORTS*`WIDTH-1:0] d;
wire [PORTS*`WIDTH-1:0] q;
reg [PORTS*`ADDR_WIDTH-1:0] addr;
reg [0:PORTS-1] stall;
wire [0:PORTS - 1] valid, full;
//TODO: ports and addresses not lining up
scratch_pad #(PORTS, `WIDTH, `FRAGMENT_DEPTH, REORDER_DEPTH, 32) dut(rst, clk, rd_en, wr_en, d, q, addr, stall, valid, full);
initial begin
clk = 0;
forever #5 clk = !clk;
end
wire [PORTS*`WIDTH-1:0] gold_q;
wire [0:PORTS -1] gold_valid;
wire [0:PORTS -1] gold_full;
scratch_pad_gold #(PORTS, `WIDTH) gold_model(rst, clk, rd_en, wr_en, d, gold_q, addr, stall, gold_valid, gold_full);
integer begin_ptr [0:PORTS];
integer end_ptr [0:PORTS];
reg [`WIDTH-1:0] fifo_data [0:PORTS][0:100000];
integer i, j;
initial begin
for(i = 0; i < PORTS; i = i + 1) begin
begin_ptr[i] = 0;
end_ptr[i] = 0;
end
end
integer f;
integer si;
integer tmp;
integer start_time, end_time, latency;
integer data_sent [0:PORTS-1];
integer total_sent;
integer data_to_send [0:PORTS-1];
integer max_data_sent;
integer first_finish, all_finish;
reg [`ADDR_WIDTH-1:0] addr_iterator;
integer ignore_full;
initial begin
//$monitor(valid[0]);
f = $fopen(OUT_FILE, "a");
$display("beginning");
ignore_full = 1;
rst = 1;
rd_en = 0;
wr_en = 0;
d = 0;
addr = 0;
stall = 0;
#1001 rst = 0;
#20000 wr_en[0] = 1;
$display("first write");
ignore_full = 0;
d[PORTS*`WIDTH-1 -: `WIDTH] = 42;
#10 wr_en = 0;
#100 rd_en[0] = 1;
$display("first read");
#10 rd_en = 0;
#1000;
$display("second write");
wr_en[0] = 1;
d[PORTS*`WIDTH-1 -: `WIDTH] = 0;
#10 wr_en = 0;
#100;
rd_en[0] = 1;
$display("second read");
#10 rd_en[0] = 0;
#1000;
//initial random data
$display("writing initial data");
for(addr_iterator = 0; addr_iterator < `ADDR_TEST_MAX; addr_iterator = addr_iterator + 1) begin
wr_en[0] = 0;
while(full[0]) begin
#10;
end
wr_en[0] = 1;
d[PORTS * `WIDTH - 1 -: `WIDTH] = abs($random);
addr[PORTS * `ADDR_WIDTH - 1 -: `ADDR_WIDTH] = addr_iterator;
#10;
end
wr_en[0] = 0;
#1000;
$display("reading initial data. time: %d", $time);
for(si = 0; si < `ADDR_TEST_MAX; si = si + 1) begin
rd_en[0] = 0;
while(full[0]) begin
#10;
end
rd_en[0] = 1;
//d[PORTS * `WIDTH - 1 -: `WIDTH] = si;
addr[PORTS * `ADDR_WIDTH - 1 -: `ADDR_WIDTH] = si;
#10;
end
rd_en[0] = 0;
#1000;
/*
//random data
$display("randrom data");
si = 0;
for(si = 0; si < 10; si = si + 1) begin
for(i = 0; i < PORTS; i = i + 1) begin
tmp = abs($random) % 3;
if(tmp == 0) begin
wr_en[i] = 1;
rd_en[i] = 0;
end else if(tmp == 1) begin
wr_en[i] = 0;
rd_en[i] = 1;
end else if(tmp == 2) begin
wr_en = 0;
rd_en = 0;
end
d[(PORTS-i)*`WIDTH - 1 -: `WIDTH] = abs($random);
addr[(PORTS-i)*`ADDR_WIDTH-1 -: `ADDR_WIDTH] = abs($random) % `ADDR_TEST_MAX;
end
#10;
end
#10 rd_en = 0;
wr_en = 0;
d = 0;
addr = 0;
stall = 0;
#1000;
*/
//stress test write at two ports.
/*
$display("stress testing writing at port 0 and 1");
$display("start time: %d",$time);
start_time=$time;
for(si=0; si<1000; si=si+1) begin
if(!full[0]) begin
wr_en[0]=1;
d[PORTS*`WIDTH-1 -: `WIDTH]=42;
addr[PORTS*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=0;
end else begin
wr_en[0]=0;
end
if(!full[1]) begin
wr_en[1]=1;
d[(PORTS-1)*`WIDTH-1 -: `WIDTH]=42;
addr[(PORTS-1)*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=0;
end else begin
wr_en[1]=0;
end
#10;
end
wr_en=0;
$display("end time: %d",$time);
#1000;
//stress test read at single port.
$display("stress testing reading at port 0 and 1");
$display("start time: %d",$time);
start_time=$time;
for(si=0; si<1000; si=si+1) begin
if(!full[0]) begin
rd_en[0]=1;
d[PORTS*`WIDTH-1 -: `WIDTH]=42;
addr[PORTS*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=0;
end else begin
rd_en[0]=0;
end
if(!full[1]) begin
rd_en[1]=1;
d[(PORTS-1)*`WIDTH-1 -: `WIDTH]=42;
addr[(PORTS-1)*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=0;
end else begin
rd_en[1]=0;
end
#10;
end
rd_en=0;
$display("end time: %d",$time);
//TODO: stress test all ports sequencial write
#1000;
$display("stress testing writing all ports");
$display("start time: %d",$time);
start_time=$time;
for(i=0;i<PORTS;i=i+1)begin
data_sent[i]=0;
data_to_send[i]=1000;
end
for(si=0; si<1000; si=si+1) begin
for(i=0;i<PORTS;i=i+1)begin
if(!full[i]) begin
wr_en[i]=1;
d[(PORTS-i)*`WIDTH-1 -: `WIDTH]=42;
addr[(PORTS-i)*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=data_sent[i];
data_sent[i]=data_sent[i]+1;
end else begin
wr_en[i]=0;
end
end
#10;
end
wr_en=0;
$display("end time: %d",$time);
$display("total time: %d", ($time-start_time));
for(i=0;i<PORTS;i=i+1)begin
$display("data sent from port %d: %d", i, data_sent[i]);
end
*/
//TODO: stress test all ports sequencial read
#10000;
$display("stress testing sequential reading all ports");
$display("start time: %d",$time);
start_time=$time;
for(i=0;i<PORTS;i=i+1)begin
data_sent[i]=0;
data_to_send[i]=1000;
end
$display("starting to send");
for(si=0; si<10000; si=si+1) begin
for(i=0;i<PORTS;i=i+1)begin
if(!full[i]) begin
rd_en[i]=1;
addr[(PORTS-i)*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=data_sent[i] % `ADDR_TEST_MAX;
data_sent[i]=data_sent[i]+1;
end else begin
rd_en[i]=0;
end
end
#10;
end
$display("stopped sending");
rd_en=0;
$display("end time: %d",$time);
end_time=$time;
$display("total time: %d", ($time-start_time));
for(si = 0; si < PORTS; si = si + 1) begin
while(begin_ptr[si] != end_ptr[si]) #10;
end
total_sent = 0;
for(i=0;i<PORTS;i=i+1)begin
$display("data sent from port %d: %d", i, data_sent[i]);
total_sent = total_sent + data_sent[i];
end
$display("latency: %d", ($time-end_time));
$fwrite(f, "%f,%d,", total_sent/PORTS/10000.0,($time-end_time)/10);
/*
//TODO: stress test all ports random write
#1000;
$display("stress testing writing all ports");
$display("start time: %d",$time);
start_time=$time;
for(i=0;i<PORTS;i=i+1)begin
data_sent[i]=0;
data_to_send[i]=1000;
end
for(si=0; si<1000; si=si+1) begin
for(i=0;i<PORTS;i=i+1)begin
if(!full[i]) begin
wr_en[i]=1;
d[(PORTS-i)*`WIDTH-1 -: `WIDTH]=42;
addr[(PORTS-i)*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=data_sent[i];
data_sent[i]=data_sent[i]+1;
end else begin
wr_en[i]=0;
end
end
#10;
end
wr_en=0;
$display("end time: %d",$time);
$display("total time: %d", ($time-start_time));
for(i=0;i<PORTS;i=i+1)begin
$display("data sent from port %d: %d", i, data_sent[i]);
end
*/
//TODO: stress test all ports random read
#10000;
$display("stress testing random reading all ports");
$display("start time: %d",$time);
start_time=$time;
for(i=0;i<PORTS;i=i+1)begin
data_sent[i]=0;
data_to_send[i]=1000;
end
$display("starting to send");
for(si=0; si<10000; si=si+1) begin
for(i=0;i<PORTS;i=i+1)begin
if(!full[i]) begin
rd_en[i]=1;
addr[(PORTS-i)*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=abs($random) % `ADDR_TEST_MAX;
data_sent[i]=data_sent[i]+1;
end else begin
rd_en[i]=0;
end
end
#10;
end
$display("stopped sending");
rd_en=0;
$display("end time: %d",$time);
$display("total time: %d", ($time-start_time));
total_sent = 0;
for(i=0;i<PORTS;i=i+1)begin
$display("data sent from port %d: %d", i, data_sent[i]);
total_sent = total_sent + data_sent[i];
end
$display("average sent: %d", total_sent/PORTS);
end_time=$time;
for(si = 0; si < PORTS; si = si + 1) begin
while(begin_ptr[si] != end_ptr[si]) #10;
end
$display("latency: %d", ($time-end_time));
$fwrite(f, "%f,%d,", total_sent/PORTS/10000.0,($time-end_time)/10);
//TODO: stress test all ports random read
#10000;
$display("stress testing worst case reading, all ports");
$display("start time: %d", $time);
start_time=$time;
j=0;
for(i=0;i<PORTS;i=i+1)begin
data_sent[i]=0;
data_to_send[i]=1000;
end
max_data_sent = 0;
$display("starting to send");
for(si=0; si<10000; si=si+1) begin
for(i=0;i<PORTS;i=i+1)begin
if(!full[i]) begin
rd_en[i]=1;
addr[(PORTS-i)*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=(j*PORTS) % `ADDR_TEST_MAX;
j = j + 1;
data_sent[i]=data_sent[i]+1;
end else begin
rd_en[i]=0;
end
if(data_sent[i] > max_data_sent)
max_data_sent = data_sent[i];
end
#10;
/*
if(max_data_sent > 32) begin
$display("trigger hit:");
end
*/
//for(i=0;i<PORTS;i=i+1)begin
// $display("data sent from port %d: %d", i, data_sent[i]);
//end
//TODO: assert only reads on port 0;
//TODO: look at arbiters
end
$display("stopped sending");
rd_en=0;
$display("end time: %d",$time);
$display("total time: %d", ($time-start_time));
end_time=$time;
for(si = 0; si < PORTS; si = si + 1) begin
while(begin_ptr[si] != end_ptr[si]) #10;
end
$display("latency: %d", ($time-end_time));
total_sent = 0;
for(i=0;i<PORTS;i=i+1)begin
$display("data sent from port %d: %d", i, data_sent[i]);
total_sent = total_sent + data_sent[i];
end
$display("latency: %d", ($time-end_time));
$fwrite(f, "%f,%d,", total_sent/PORTS/10000.0,($time-end_time)/10);
//TODO: stress test all ports random read
#10000;
$display("stress testing segregated reading all ports");
$display("start time: %d",$time);
start_time=$time;
for(i=0;i<PORTS;i=i+1)begin
data_sent[i]=0;
data_to_send[i]=1000;
end
$display("starting to send");
for(si=0; si<10000; si=si+1) begin
for(i=0;i<PORTS;i=i+1)begin
if(!full[i]) begin
rd_en[i]=1;
addr[(PORTS-i)*`ADDR_WIDTH-1 -:`ADDR_WIDTH]=i;
data_sent[i]=data_sent[i]+1;
end else begin
rd_en[i]=0;
end
end
#10;
end
$display("stopped sending");
rd_en=0;
$display("end time: %d",$time);
$display("total time: %d", ($time-start_time));
end_time=$time;
for(si = 0; si < PORTS; si = si + 1) begin
while(begin_ptr[si] != end_ptr[si]) #10;
end
$display("latency: %d", ($time-end_time));
total_sent = 0;
for(i=0;i<PORTS;i=i+1)begin
$display("data sent from port %d: %d", i, data_sent[i]);
total_sent = total_sent + data_sent[i];
end
$display("latency: %d", ($time-end_time));
$fwrite(f, "%f,%d,", total_sent/PORTS/10000.0,($time-end_time)/10);
//TODO: check state with sequential read.
//TODO: stress test all ports random read write
#10000 $display("No ERRORS");
$fclose(f);
$finish;
end
initial begin
#10000000 $display("ERROR: watchdog reached");
$finish;
end
always @(posedge clk) begin
if(`DEBUG) begin
$display("debug on");
for(i = 0; i < PORTS; i = i + 1)
if(valid[i])
$display("i:%d read output: %H", i, q[PORTS*`WIDTH-1 -: `WIDTH ]);
for(i = 0; i < PORTS; i = i + 1) begin
if(rd_en[i] || wr_en[i])
$display("i:%d using address: %H", i, addr[PORTS*`ADDR_WIDTH-1 -: `ADDR_WIDTH ]);
if(wr_en[i])
$display("i:%d writing: %H", i, d[PORTS*`WIDTH - 1 -: `WIDTH]);
end
end
end
always @(posedge clk) begin
for(i=0;i<PORTS;i=i+1) begin
if(full[i]&&!ignore_full)begin
//$display("%d full at port %d",$time, i);
//$finish;
end
end
for(i = 0; i < PORTS; i = i + 1) begin
if(gold_valid[i]) begin
//$display("gold valid: port: %d data: %H time: %d", i, gold_q[(PORTS-i)*`WIDTH-1 -:`WIDTH], $time);
fifo_data[i][begin_ptr[i]] = gold_q[(PORTS-i)*`WIDTH - 1 -: `WIDTH];
begin_ptr[i] = begin_ptr[i] + 1;
end
end
/*
for(i = 0; i< PORTS; i=i+1)begin
if(rd_en[i])begin
$display("Read data: port: %d addr: %H data: %H time: %d", i, addr[(PORTS-i)*`ADDR_WIDTH-1 -:`ADDR_WIDTH], d[(PORTS-i)*`WIDTH-1 -:`WIDTH], $time);
end
if(wr_en[i])begin
$display("Write data: port: %d addr: %H data: %H time: %d", i, addr[(PORTS-i)*`ADDR_WIDTH-1 -:`ADDR_WIDTH], d[(PORTS-i)*`WIDTH-1 -:`WIDTH], $time);
end
end
*/
for(i = 0; i < PORTS; i = i + 1) begin
if(valid[i]) begin
if(fifo_data[i][end_ptr[i]] ==q[(PORTS-i)*`WIDTH - 1 -: `WIDTH] ) begin
//$display("Woot match %d", i);
//$finish;
end else begin
$display("ERROR: no match %d", i);
$display("%d: port %d, fifo %d, q %d", $time, i, fifo_data[i][end_ptr[i]], q[(PORTS-i)*`WIDTH-1 -: `WIDTH]);
$display("%d: port %d, fifo %H, q %H", $time, i, fifo_data[i][end_ptr[i]], q[(PORTS-i)*`WIDTH-1 -: `WIDTH]);
$display("end_ptr: %H", end_ptr[i]);
$display("beg_ptr: %H", begin_ptr[i]);
$finish;
end
end_ptr[i] = end_ptr[i] + 1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:52:15 02/21/2015
// Design Name:
// Module Name: NormaliseProd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NormaliseProd(
input [35:0] cout_Multiply,
input [35:0] zout_Multiply,
input [31:0] sout_Multiply,
input [49:0] productout_Multiply,
input [1:0] modeout_Multiply,
input operationout_Multiply,
input NatLogFlagout_Multiply,
input [7:0] InsTag_Multiply,
input clock,
input [1:0] idle_Multiply,
output reg [1:0] idle_NormaliseProd,
output reg [35:0] cout_NormaliseProd,
output reg [35:0] zout_NormaliseProd,
output reg [31:0] sout_NormaliseProd,
output reg [1:0] modeout_NormaliseProd,
output reg operationout_NormaliseProd,
output reg NatLogFlagout_NormaliseProd,
output reg [49:0] productout_NormaliseProd,
output reg [7:0] InsTag_NormaliseProd
);
parameter mode_circular =2'b01,
mode_linear =2'b00,
mode_hyperbolic=2'b11;
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
assign z_sign = zout_Multiply[35];
assign z_exponent = zout_Multiply[34:27];
assign z_mantissa = {zout_Multiply[26:0]};
always @ (posedge clock) begin
InsTag_NormaliseProd <= InsTag_Multiply;
sout_NormaliseProd <= sout_Multiply;
cout_NormaliseProd <= cout_Multiply;
modeout_NormaliseProd <= modeout_Multiply;
operationout_NormaliseProd <= operationout_Multiply;
idle_NormaliseProd <= idle_Multiply;
NatLogFlagout_NormaliseProd <= NatLogFlagout_Multiply;
if (idle_Multiply == no_idle) begin
// This case will never arise. This is because for input with exponent less than -12 multiply isn't used.
if ($signed(z_exponent) < -126) begin
zout_NormaliseProd[35] <= z_sign;
zout_NormaliseProd[34:27] <= z_exponent + 1;
zout_NormaliseProd[26:0] <= z_mantissa;
productout_NormaliseProd <= productout_Multiply >> 1;
end
// This could be problematic. Will have to test for average number of cycles
// Current solution is to hard code for all cases like normalisation in addition.
else if (productout_Multiply[49] == 0) begin
zout_NormaliseProd[35] <= z_sign;
zout_NormaliseProd[34:27] <= z_exponent - 1;
//zout_NormaliseProd[26:0] <= product[48:25];
zout_NormaliseProd[26:0] <= {productout_Multiply[48:25] , 3'd0};
productout_NormaliseProd <= productout_Multiply << 1;
end
else begin
zout_NormaliseProd[35] <= z_sign;
zout_NormaliseProd[34:27] <= z_exponent;
//z_mantissa <= productout_Multiply[49:26];
zout_NormaliseProd[26:0] <= {productout_Multiply[49:26] , 3'd0};
productout_NormaliseProd <= productout_Multiply;
end
end
else begin
zout_NormaliseProd <= zout_Multiply;
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_6_3,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_6_3,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=32,DIN_FROM=30,DIN_TO=7}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_6_3 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(30),
.DIN_TO(7)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_std.v
// /___/ /\ Date Last Modified : $Date: 2011/06/17 11:11:25 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v1_9_ddr3_7Series, Coregen 14.5" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v1_9,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Foundation_ISE, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=2500, PHY_RATIO=4, CLKIN_PERIOD=5000, VCCAUX_IO=1.8V, MEMORY_TYPE=COMP, MEMORY_PART=mt41j512m8xx-125, DQ_WIDTH=32, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=ROW_BANK_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=NO_BUFFER, REFCLK_TYPE=USE_SYSTEM_CLOCK}" *)
module mig_7series_v1_9_memc_ui_top_std #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter IODELAY_HP_MODE = "ON",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'hF,
parameter [3:0] BYTE_LANES_B1 = 4'hF,
parameter [3:0] BYTE_LANES_B2 = 4'hF,
parameter [3:0] BYTE_LANES_B3 = 4'hF,
parameter [3:0] BYTE_LANES_B4 = 4'hF,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1 // Support ODT output
)
(
// Clock and reset ports
input clk,
input clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
// user interface ports
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input app_hi_pri,
input [APP_DATA_WIDTH-1:0] app_wdf_data,
input app_wdf_end,
input [APP_MASK_WIDTH-1:0] app_wdf_mask,
input app_wdf_wren,
input app_correct_en_i,
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err,
output [APP_DATA_WIDTH-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// temperature monitor ports
input [11:0] device_temp,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data
);
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
(* keep = "true", max_fanout = 10 *) reg reset /* synthesis syn_maxfan = 10 */;
//***************************************************************************
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
mig_7series_v1_9_mem_intfc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT)
)
mem_intfc0
(
.clk (clk),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
.device_temp (device_temp),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)
);
mig_7series_v1_9_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.app_ecc_multiple_err (app_ecc_multiple_err),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (1'b1),
.app_raw_not_ecc (app_raw_not_ecc),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* VC Switch Allocator
* ===================
*
* Technically this is an input first seperable allocator (see Dally/Towles p.367)
*
* Arbitration Stage 1:
* * Arbitrate between requests from VCs at each input port (np x nv:1 arbiters)
* * Select the output port request of the winning flit
*
* Arbitration Stage 2:
* * Arbitrate between requests for each output port (np x np:1 arbiters)
* * Determine which input port requests were successful.
*
*
* ----> req --> grant
* ----> required_output_port
* . .
* . [STAGE 1] [STAGE 2] .
* . Arbitrate between Arbitrate between .
* ----> req requests from same winners of stage 1 --> grant
* ----> required_output_port input port that require the
* same output port
*
* Parameters
* ==========
*
* # np - number of ports (assumes no. input = no. output)
* # nv - number of virtual-channels
*
* (NOT SUPPORTED IN CONFIGURATION FILE)
* Lonely Outputs Optimization [experimentation only, very poor synthesis results]
* ===========================
*
* ** Ignores flit priority if present **
*
* # priority_lonely_outputs = 0 | 1
*
* Prioritises a request if it represents the only request for a
* particular output. See Dally/Towles p.373 for rationale. Note
* this scheme doesn't perform a full count of requests for each
* output. It simply looks for cases where an output is requested
* by a single input.
*
*/
module NW_vc_switch_allocator (req,
req_priority, // for flit prioritisation support
output_port,
grant,
vc_mux_sel, // not used by Lochside
xbar_select, // not used by Lochside
any_request_for_output, // not used by Lochside
taken_by_nonspec, // not used by Lochside
clk, rst_n);
parameter np=5;
parameter nv=4;
parameter priority_lonely_outputs = 0;
parameter speculative_alloc = 0;
parameter dynamic_priority_switch_alloc = 0;
//parameter type flit_priority_t = logic unsigned [3:0];
parameter turn_opt = 1 ; // 0 useful when testing, default 1
input [np-1:0][nv-1:0] req;
input flit_priority_t req_priority [np-1:0][nv-1:0];
input output_port_t output_port [np-1:0][nv-1:0];
output [np-1:0][nv-1:0] grant;
output [np-1:0][nv-1:0] vc_mux_sel;
output [np-1:0][np-1:0] xbar_select;
output [np-1:0] any_request_for_output;
input [np-1:0] taken_by_nonspec; // has a non-spec request been granted at this input port?
input clk, rst_n;
logic [np-1:0] input_port_success;
logic [np-1:0][nv-1:0] stage1_grant;
output_port_t winning_port_req [np-1:0];
logic [np-1:0][np-1:0] output_port_req, all_grants_for_input, output_port_grant,
permitted_output_port_req, permitted_output_port_grant;
logic [np-1:0] uncontested, contested;
logic priority_bit [np-1:0][nv-1:0];
flit_priority_t max_priority[np-1:0];
flit_priority_t req_priority_stage2 [np-1:0][np-1:0];
genvar i,j;
// buffers at each input port arbitrate for access to single port on crossbar
// (winners of stage1 go on to arbitrate for access to actually output port)
assign vc_mux_sel = stage1_grant;
function logic [np-1:0] find_uncontested(input [np-1:0][nv-1:0] req,
input output_port_t output_port [np-1:0][nv-1:0]);
logic [np-1:0] contested, uncontested;
integer o,p,v;
begin
for (o=0; o<np; o++) begin
uncontested[o]=1'b0;
contested[o]=1'b0;
for (p=0; p<np; p++) begin
for (v=0; v<nv; v++) begin
if ((req[p][v])&&(output_port[p][v][o])) begin
// request at input port 'p' at VC 'v' is requesting port 'o'
if (!uncontested[o]&&!contested[o]) begin
uncontested[o]=1'b1;
end else begin
if (uncontested[o]&&!contested[o]) begin
contested[o]=1'b1;
uncontested[o]=1'b0;
end
end
end
end
end
end // for (o=0; o<np; o++)
find_uncontested=uncontested;
end
endfunction
// arbitrate between virtual-channels at each input port
generate
// ************************************************
// look for uncontested requests for an output port
// ************************************************
if (priority_lonely_outputs) begin
assign uncontested=find_uncontested(req, output_port);
// foreach output port
for (i=0; i<np; i++) begin:ips
// set priority bit if request needs uncontested port
for (j=0;j<nv;j++) begin:vcs
assign priority_bit[i][j]=|(output_port[i][j] & uncontested);
end
end
end // if (priority_lonely_outputs)
for (i=0; i<np; i++) begin:inport
// **********************************
// nv:1 arbiter at each input port
// **********************************
if (priority_lonely_outputs) begin
matrix_arb #(.size(nv),
.multistage(1),
//.priority_type(bit),
.priority_support(1)) vc_arb
(.request(req[i]),
.req_priority(priority_bit[i]),
.grant(stage1_grant[i]),
.success(input_port_success[i]),
.clk, .rst_n);
end else begin
matrix_arb #(.size(nv),
.multistage(1),
//.priority_type(flit_priority_t),
.priority_support(dynamic_priority_switch_alloc)) vc_arb
(.request(req[i]),
.req_priority(req_priority[i]),
.max_priority(max_priority[i]),
.grant(stage1_grant[i]),
.success(input_port_success[i]),
.clk, .rst_n);
end
// select output port request of (first-stage) winner
NW_mux_oh_select #( .n(nv)) reqmux
(output_port[i], stage1_grant[i], winning_port_req[i]);
// setup requests for output ports
for (j=0; j<np; j++) begin:outport
//
// request priorities for second stage of arbitration
// - requests from input i will have priority 'max_priority[i]'
//
assign req_priority_stage2[j][i] = max_priority[i];
// if turn is invalid output port request will never be made
if (turn_opt) begin
assign output_port_req[j][i]=(NW_route_valid_turn(i,j)) ? winning_port_req[i][j] : 1'b0;
end else begin
assign output_port_req[j][i] = winning_port_req[i][j];
end
// for cases when both speculative and non-speculative versions of a switch
// allocator are employed together.
if (speculative_alloc) begin
assign permitted_output_port_req[j][i] = output_port_req[j][i] & !taken_by_nonspec[i];
end else begin
assign permitted_output_port_req[j][i] = output_port_req[j][i];
end
end
for (j=0; j<nv; j++) begin:suc
// was request successful at both input and output arbitration?
assign grant[i][j]=stage1_grant[i][j] && input_port_success[i];
end
end // block: inport
for (i=0; i<np; i++) begin:outport
// **********************************
// np:1 arbiter at each output port
// **********************************
if (priority_lonely_outputs) begin
matrix_arb #(.size(np),
.multistage(0)) outport_arb
(.request(output_port_req[i]),
.grant(output_port_grant[i]),
.clk, .rst_n);
end else begin
matrix_arb #(.size(np),
.multistage(0),
//.priority_type(flit_priority_t),
.priority_support(dynamic_priority_switch_alloc)) outport_arb
(.request(output_port_req[i]),
.req_priority(req_priority_stage2[i]),
.grant(output_port_grant[i]),
.clk, .rst_n);
end
for (j=0; j<np; j++) begin:g
// was input port successful?
assign all_grants_for_input[j][i]=output_port_grant[i][j];
if (speculative_alloc) begin
assign permitted_output_port_grant[j][i] = output_port_grant[j][i] && !taken_by_nonspec[i];
end else begin
assign permitted_output_port_grant[j][i] = output_port_grant[j][i];
end
end
assign input_port_success[i]=|all_grants_for_input[i];
assign any_request_for_output[i]=|permitted_output_port_req[i];
end
endgenerate
assign xbar_select = permitted_output_port_grant;
endmodule // NW_vc_switch_allocator
|
`timescale 1ns / 1ps
module state_control(
input CLK, START, RESET, BTN_PLAYER1, BTN_PLAYER2,
input [3:0] iSW,
output [7:0] OLED,
output reg [8:0] occupied,
output reg [8:0] symbol
);
// state parameter
localparam IDLE = 2'd0;
localparam PLAYER1 = 2'd1;
localparam PLAYER2 = 2'd2;
localparam FINISH = 2'd3;
// win parameter
localparam NO_WIN = 2'd0;
localparam PLAYER1_WIN = 2'd1;
localparam PLAYER2_WIN = 2'd2;
localparam DRAW_GAME = 2'd3;
reg [1:0] WIN, state;
reg [1:0] next_win, next_state;
assign OLED = {WIN, 4'b0, state};
always @(posedge CLK)
begin
if (RESET) begin
state <= IDLE;
WIN <= NO_WIN;
end else begin
state <= next_state;
WIN <= next_win;
end
end
// Drawing check.
reg py1_draw, py2_draw;
always @(*)
begin
if (iSW > 0 && iSW <= 9 && ~occupied[iSW-1]) begin
py1_draw = BTN_PLAYER1;
py2_draw = BTN_PLAYER2;
end else begin
py1_draw = 1'b0;
py2_draw = 1'b0;
end
end
// Board drawing.
always @(posedge CLK)
begin
if (RESET) begin
occupied = 9'b0;
symbol = 9'b0;
end else if (iSW > 0 && iSW <= 9) begin
if (state == PLAYER1 && py1_draw) begin
occupied[iSW-1] = 1'b1;
symbol[iSW-1] = 1'b0;
end else if (state == PLAYER2 && py2_draw) begin
occupied[iSW-1] = 1'b1;
symbol[iSW-1] = 1'b1;
end
end
end
reg [8:0] next_occupied, next_symbol;
always @(*)
begin
next_occupied = occupied;
next_symbol = symbol;
if ((state == PLAYER1 && py1_draw) || (state == PLAYER2 && py2_draw))
next_occupied = occupied | (1'b1 << (iSW-1'b1));
if (state == PLAYER2 && py2_draw)
next_symbol = symbol | (1'b1 << (iSW-1'b1));
end
// Wining check.
always @(*)
begin
if (WIN == PLAYER1_WIN)
next_win = PLAYER1_WIN;
else if (WIN == PLAYER2_WIN)
next_win = PLAYER2_WIN;
else if (WIN == DRAW_GAME)
next_win = DRAW_GAME;
else begin
next_win = NO_WIN;
if ((state == PLAYER1 && py1_draw) || (state == PLAYER2 && py2_draw)) begin
if (next_occupied[0] && next_occupied[1] && next_occupied[2])
if (next_symbol[0] == next_symbol[1] && next_symbol[1] == next_symbol[2])
if (next_symbol[0])
next_win = PLAYER2_WIN;
else
next_win = PLAYER1_WIN;
if (next_occupied[3] && next_occupied[4] && next_occupied[5])
if (next_symbol[3] == next_symbol[4] && next_symbol[4] == next_symbol[5])
if (next_symbol[3])
next_win = PLAYER2_WIN;
else
next_win = PLAYER1_WIN;
if (next_occupied[6] && next_occupied[7] && next_occupied[8])
if (next_symbol[6] == next_symbol[7] && next_symbol[7] == next_symbol[8])
if (next_symbol[6])
next_win = PLAYER2_WIN;
else
next_win = PLAYER1_WIN;
if (next_occupied[0] && next_occupied[3] && next_occupied[6])
if (next_symbol[0] == next_symbol[3] && next_symbol[3] == next_symbol[6])
if (next_symbol[0])
next_win = PLAYER2_WIN;
else
next_win = PLAYER1_WIN;
if (next_occupied[1] && next_occupied[4] && next_occupied[7])
if (next_symbol[1] == next_symbol[4] && next_symbol[4] == next_symbol[7])
if (next_symbol[1])
next_win = PLAYER2_WIN;
else
next_win = PLAYER1_WIN;
if (next_occupied[2] && next_occupied[5] && next_occupied[8])
if (next_symbol[2] == next_symbol[5] && next_symbol[5] == next_symbol[8])
if (next_symbol[2])
next_win = PLAYER2_WIN;
else
next_win = PLAYER1_WIN;
if (next_occupied[0] && next_occupied[4] && next_occupied[8])
if (next_symbol[0] == next_symbol[4] && next_symbol[4] == next_symbol[8])
if (next_symbol[0])
next_win = PLAYER2_WIN;
else
next_win = PLAYER1_WIN;
if (next_occupied[2] && next_occupied[4] && next_occupied[6])
if (next_symbol[2] == next_symbol[4] && next_symbol[4] == next_symbol[6])
if (next_symbol[2])
next_win = PLAYER2_WIN;
else
next_win = PLAYER1_WIN;
if (next_win == NO_WIN && next_occupied == 9'b111111111)
next_win = DRAW_GAME;
end
end
end
// State control.
always @(*)
begin
case (state)
IDLE:
if (START)
next_state = PLAYER1;
else
next_state = IDLE;
PLAYER1:
if (py1_draw)
if (next_win)
next_state = FINISH;
else
next_state = PLAYER2;
else
next_state = PLAYER1;
PLAYER2:
if (py2_draw)
if (next_win)
next_state = FINISH;
else
next_state = PLAYER1;
else
next_state = PLAYER2;
default: next_state = FINISH;
endcase
end
endmodule
|
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Josh Sackos
//
// Create Date: 07/26/2012
// Module Name: ssdCtrl
// Project Name: PmodACL_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: This module interfaces the onboard seven segment display (SSD) on
// the Nexys3, and formats the data to be displayed.
//
// The DIN input is a binary number that gets formatted to binary
// coded decimal, and is displayed as a signed 3 digit number on the
// SSD. Bit 9 on the DIN input controls whether or not a minus sign
// will be displayed on the SSD or not. The AN output bus drives the
// SSD's anodes controling the illumination of the 4 digits on the SSD.
// The SEG output bus drives the cathodes on the SSD to display different
// characters.
//
// Revision History:
// Revision 0.01 - File Created (Josh Sackos)
///////////////////////////////////////////////////////////////////////////////////
// ===================================================================================
// Define Module, Inputs and Outputs
// ===================================================================================
module ssdCtrl(
CLK,
RST,
DIN,
AN,
SEG,
DOT,
bcdData
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input CLK;
input RST;
input [9:0] DIN;
output [3:0] AN;
reg [3:0] AN;
output [6:0] SEG;
reg [6:0] SEG;
output DOT;
output wire [15:0] bcdData;
// ====================================================================================
// Parameters, Register, and Wires
// ====================================================================================
// 1 kHz Clock Divider
parameter [15:0] cntEndVal = 16'hC350;
reg [15:0] clkCount;
reg DCLK;
// 2 Bit Counter
reg [1:0] CNT;
// Binary Data to BCD "g" value format x.xx
//wire [15:0] bcdData;
// Output Data Mux
reg [3:0] muxData;
// ====================================================================================
// Implementation
// ====================================================================================
//assign bcdData[15:12] = (DIN[9] == 1'b0) ? (4'hA) : (4'hF);
// Assign DOT when count is 2
assign DOT = (CNT == 2'b11) ? 1'b0 : 1'b1;
//------------------------------
// Format Data
//------------------------------
Format_Data FDATA(
.CLK(CLK),
.DCLK(DCLK),
.RST(RST),
.DIN(DIN),
.BCDOUT(bcdData)
);
//-----------------------------------------------
// Output Data Mux
// Select data to display on SSD
//-----------------------------------------------
always @(CNT[1] or CNT[0] or bcdData or RST)
if (RST == 1'b1)
muxData <= 4'b0000;
else
case (CNT)
2'b00 : muxData <= bcdData[3:0];
2'b01 : muxData <= bcdData[7:4];
2'b10 : muxData <= bcdData[11:8];
2'b11 : muxData <= bcdData[15:12];
default : muxData <= 4'b0000;
endcase
//------------------------------
// Segment Decoder
// Determines cathode pattern
// to display digit on SSD
//------------------------------
always @(posedge DCLK or posedge RST)
if (RST == 1'b1)
SEG <= 7'b1000000;
else
case (muxData)
4'h0 : SEG <= 7'b1000000; // 0
4'h1 : SEG <= 7'b1111001; // 1
4'h2 : SEG <= 7'b0100100; // 2
4'h3 : SEG <= 7'b0110000; // 3
4'h4 : SEG <= 7'b0011001; // 4
4'h5 : SEG <= 7'b0010010; // 5
4'h6 : SEG <= 7'b0000010; // 6
4'h7 : SEG <= 7'b1111000; // 7
4'h8 : SEG <= 7'b0000000; // 8
4'h9 : SEG <= 7'b0010000; // 9
4'hA : SEG <= 7'b0111111; // Minus
4'hF : SEG <= 7'b1111111; // Off
default : SEG <= 7'b1111111;
endcase
//---------------------------------
// Anode Decoder
// Determines digit digit to
// illuminate for clock period
//---------------------------------
always @(posedge DCLK or posedge RST)
if (RST == 1'b1)
AN <= 4'b1111;
else
case (CNT)
2'b00 : AN <= 4'b1110; // 0
2'b01 : AN <= 4'b1101; // 1
2'b10 : AN <= 4'b1011; // 2
2'b11 : AN <= 4'b0111; // 3
default : AN <= 4'b1111; // All off
endcase
//------------------------------
// 2 Bit Counter
// Used to select which digit
// is being illuminated, and
// selects data to be displayed
//------------------------------
always @(posedge DCLK) begin
CNT <= CNT + 1'b1;
end
//------------------------------
// 1khz Clock Divider
// Timing for refreshing the
// SSD, etc.
//------------------------------
always @(posedge CLK) begin
if (clkCount == cntEndVal) begin
DCLK <= 1'b1;
clkCount <= 16'h0000;
end
else begin
DCLK <= 1'b0;
clkCount <= clkCount + 1'b1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A2111OI_PP_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_PP_BLACKBOX_V
|
/* Module from the schematic_gui program written by Andreas Ehliar <andreas.ehliar@liu.se>
This Verilog file is licensed under the CC0 license. */
module mult #(parameter WIREWIDTH = 1) (input wire clk,
input wire [WIREWIDTH:0] x,y,
output reg [WIREWIDTH:0] res); /* FIXME: reswidth! */
initial begin
$schematic_boundingbox(100,120);
$schematic_arc(50,60,40);
$schematic_linestart;
$schematic_coord(20,110);
$schematic_coord(29,94);
$schematic_lineend;
$schematic_linestart;
$schematic_coord(80,110);
$schematic_coord(71,94);
$schematic_lineend;
$schematic_linestart;
$schematic_coord(50,20);
$schematic_coord(50,10);
$schematic_lineend;
$schematic_linestart;
$schematic_coord(50,40);
$schematic_coord(50,80);
$schematic_lineend;
$schematic_linestart;
$schematic_coord(67,70);
$schematic_coord(33,50);
$schematic_lineend;
$schematic_linestart;
$schematic_coord(67,50);
$schematic_coord(33,70);
$schematic_lineend;
$schematic_connector(x,20,110);
$schematic_connector(y,80,110);
$schematic_connector(res,50,10);
end
always @* begin
res = x*y;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_lvt.v: LVT-based Multiported-RAM for register-base and SRAM-based //
// one-hot/binary-coded I-LVT //
// //
// Author: Ameer M.S. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mpram_lvt
#( parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter nRPF = 2 , // number of fixed read ports
parameter nWPF = 2 , // number of fixed write ports
parameter nRPS = 2 , // number of switched read ports
parameter nWPS = 2 , // number of switched write ports
parameter LVTA = "", // LVT architecture type: LVTREG, LVTBIN, LVT1HT
parameter WAWB = 1 , // allow Write-After-Write (need to bypass feedback ram)
parameter RAWB = 1 , // new data for Read-after-Write (need to bypass output ram)
parameter RDWB = 0 , // new data for Read-During-Write
parameter FILE = "" // initialization file, optional
)( input clk , // clock
input rdWr , // switch read/write (write is active low)
input [ (nWPF+nWPS)-1:0] WEnb , // write enablea - packed from nWPF fixed & nWPS switched write ports
input [`log2(MEMD)*(nWPF+nWPS)-1:0] WAddr, // write addresses - packed from nWPF fixed & nWPS switched write ports
input [DATW *(nWPF+nWPS)-1:0] WData, // write data - packed from nWPF fixed & nWPS switched write ports
input [`log2(MEMD)*(nRPF+nRPS)-1:0] RAddr, // read addresses - packed from nRPF fixed & nRPS switched read ports
output reg [DATW *(nRPF+nRPS)-1:0] RData); // read data - packed from nRPF fixed & nRPS switched read ports
// local parameters
localparam nWPT = nWPF+nWPS ; // total number of write ports
localparam nRPT = nRPF+nRPS ; // total number of read ports
localparam ADRW = `log2(MEMD) ; // address width
localparam LVTW = `log2(nWPT) ; // LVT width
localparam SELW = (LVTA=="LVT1HT")?nWPT:LVTW; // data bank selector width
// unpacked/pack addresses/data
reg [ADRW -1:0] WAddr2D [nWPT-1:0] ; // write addresses / 2D
reg [DATW -1:0] WData2D [nWPT-1:0] ; // write data / 2D
wire [DATW*nRPT-1:0] RData2Di [nWPT-1:0] ; // read data / internal / 2D
reg [DATW -1:0] RData3Di [nWPT-1:0][nRPT-1:0]; // read data / internal / 3D
wire [DATW -1:0] RData2D [nRPT-1:0] ; // read data / output / 2D
wire [SELW*nRPT-1:0] RBank ; // read bank selector / 1D
reg [SELW -1:0] RBank2D [nRPT-1:0] ; // read bank selector / 2D
`ARRINIT;
always @* begin
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
`ARR1D2D(nWPT, ADRW,WAddr ,WAddr2D );
`ARR1D2D(nWPT, DATW,WData ,WData2D );
`ARR2D3D(nWPT,nRPT,DATW,RData2Di,RData3Di);
`ARR2D1D(nRPT, DATW,RData2D ,RData );
`ARR1D2D(nRPT, SELW,RBank ,RBank2D );
end
// generate and instantiate LVT with specific implementation
generate
if (LVTA=="LVTREG") begin
// instantiate LVT / REG type
lvt_reg #( .MEMD (MEMD ), // memory depth
.nRP (nRPT ), // number of reading ports
.nWP (nWPT ), // number of writing ports
.RDWB (RDWB ), // new data for Read-During-Write
.ZERO (FILE!=""), // binary / Initial RAM with zeros (has priority over FILE)
.FILE ("" )) // initialization file, optional
lvt_reg_i ( .clk (clk ), // clock - in
.WEnb (WEnb ), // write enable for each writing port - in : [ nWPT-1:0]
.WAddr (WAddr ), // write addresses - packed from nWPT write ports - in : [ADRW*nWPT-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPT read ports - in : [ADRW*nRPT-1:0]
.RBank (RBank )); // read bank selector - packed from nRPT read ports - out: [LVTW*nRPT-1:0]
end
else if (LVTA=="LVTBIN") begin
// instantiate LVT / BIN type
lvt_bin #( .MEMD (MEMD ), // memory depth
.nRP (nRPT ), // number of reading ports
.nWP (nWPT ), // number of writing ports
.WAWB (WAWB ), // allow Write-After-Write (need to bypass feedback ram)
.RAWB (RAWB ), // new data for Read-after-Write (need to bypass output ram)
.RDWB (RDWB ), // new data for Read-During-Write
.ZERO (FILE!=""), // binary / Initial RAM with zeros (has priority over FILE)
.FILE ("" )) // initialization file, optional
lvt_bin_i ( .clk (clk ), // clock - in
.WEnb (WEnb ), // write enable for each writing port - in : [ nWPT-1:0]
.WAddr (WAddr ), // write addresses - packed from nWPT write ports - in : [ADRW*nWPT-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPT read ports - in : [ADRW*nRPT-1:0]
.RBank (RBank )); // read bank selector - packed from nRPT read ports - out: [LVTW*nRPT-1:0]
end
else begin
// instantiate LVT / 1HT TYPE
lvt_1ht #( .MEMD (MEMD ), // memory depth
.nRP (nRPT ), // number of reading ports
.nWP (nWPT ), // number of writing ports
.WAWB (WAWB ), // allow Write-After-Write (need to bypass feedback ram)
.RAWB (RAWB ), // new data for Read-after-Write (need to bypass output ram)
.RDWB (RDWB ), // new data for Read-During-Write
.ZERO (FILE!=""), // binary / Initial RAM with zeros (has priority over FILE)
.FILE ("" )) // initialization file, optional
lvt_1ht_i ( .clk (clk ), // clock - in
.WEnb (WEnb ), // write enable for each writing port - in : [ nWPT-1:0]
.WAddr (WAddr ), // write addresses - packed from nWPT write ports - in : [ADRW*nWPT-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPT read ports - in : [ADRW*nRPT-1:0]
.RBank (RBank )); // 1hot bank selector - packed from nRPT read ports - out: [nWPT*nRPT-1:0]
end
endgenerate
// generate and instantiate mulriread RAM blocks
genvar wpi,rpi;
generate
for (wpi=0 ; wpi<nWPT ; wpi=wpi+1) begin: RPORTwpi
if (wpi<nWPF)
// noraml multi-read ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.nRP (nRPT ), // number of reading ports
.BYPS (RDWB ), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO (0 ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (wpi?"":FILE )) // initialization file, optional
mrram_i ( .clk (clk ), // clock - in
.WEnb (WEnb[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D[wpi] ), // write address (1 port) - in : [ADRW -1:0]
.WData (WData2D[wpi] ), // write data (1 port) - in : [DATW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRPT read ports - in : [ADRW*nRPT-1:0]
.RData (RData2Di[wpi])); // read data - packed from nRPT read ports - out: [DATW*nRPT-1:0]
else
// switched multi-read ram instantiation
mrram_swt #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.nRPF (nRPF ), // number of fixed read ports
.nRPS (nRPS ), // number of switched read ports
.BYPS (RDWB ), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO (0 ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (wpi?"":FILE )) // initialization file, optional
mrram_swt_i ( .clk (clk ), // clock - in
.rdWr (rdWr ), // switch read/write (write is active low) - in
.WEnb (WEnb[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D[wpi] ), // write address (1 port) - in : [ADRW -1:0]
.WData (WData2D[wpi] ), // write data (1 port) - in : [DATW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRPF fixed & nRPS switched read ports - in : [ADRW*(nRPF+nRPS)-1:0]
.RData (RData2Di[wpi])); // read data - packed from nRPF fixed & nRPS switched read ports - out: [DATW*(nRPF+nRPS)-1:0]
end
// infer tri-state buffers and connect busses for LVT1HT and muxes for LVTREG/LVTBIN
for (rpi=0 ; rpi<nRPT ; rpi=rpi+1) begin: PORTrpi
if (LVTA=="LVT1HT") begin
// tri-state buffers and busses connection
for (wpi=0 ; wpi<nWPT ; wpi=wpi+1) begin: PORTwpi
assign RData2D[rpi] = RBank2D[rpi][wpi] ? RData3Di[wpi][rpi] : {DATW{1'bz}};
end
end
else begin
// combinatorial logic for output muxes
assign RData2D[rpi] = RData3Di[RBank2D[rpi]][rpi];
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_TB_V
`define SKY130_FD_SC_HS__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 B2 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 B2 = 1'b0;
#380 C1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 C1 = 1'b1;
#500 B2 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 C1 = 1'bx;
#640 B2 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_TB_V
|
//----------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : fanyibo@fudan.edu.cn
//----------------------------------------------------------------------------
// Filename : dbf_pipeline.v
// Author : Chewein
// Created : 2014-04-18
// Description : the 4-stage pipeline of filter process
//----------------------------------------------------------------------------
module db_pipeline(
//input
clk ,
rst_n ,
tu_edge_i ,
pu_edge_i ,
qp_p_i ,
qp_q_i ,
cbf_p_i ,
cbf_q_i ,
mv_p_i ,
mv_q_i ,
mb_type_i ,
is_ver_i ,
is_luma_i ,
is_tran_i ,
p_i ,
q_i ,
//output
f_p_o ,
f_q_o
);
//---------------------------------------------------------------------------
//
// INPUT/OUTPUT DECLARATION
//
//----------------------------------------------------------------------------
parameter DATA_WIDTH = 128 ;
input clk ;
input rst_n ;
input tu_edge_i ;
input pu_edge_i ;
input [5:0] qp_p_i ;
input [5:0] qp_q_i ;
input cbf_p_i ;
input cbf_q_i ;
input [10*2-1:0] mv_p_i ;
input [10*2-1:0] mv_q_i ;
input mb_type_i ;// 1: I MB , 0: P/B MB
input is_ver_i ;// 1: ver , 0: hor
input is_luma_i ;// 1: luma , 0: chroma
input is_tran_i ;// 1: transposition ,1 : not transpositon
input [DATA_WIDTH-1:0] p_i , q_i ;
output [DATA_WIDTH-1:0] f_p_o , f_q_o ;
reg [DATA_WIDTH-1:0] f_p_o , f_q_o ;
//---------------------------------------------------------------------------
//
// stage0: calcu middle variabls and split p_i/q_i
//
//----------------------------------------------------------------------------
wire [4:0] tc_w ;
wire [6:0] beta_w ;
reg [1:0] bs_w ;
wire [5:0] qpw = ( qp_p_i + qp_q_i + 1 ) >> 1;
wire [5:0] qpwcc = qpw - 6'd30 ;
wire [5:0] qpw2 = qpw - 6'd6 ;
reg [5:0] qpw1 ;
reg [5:0] qpc ;
wire [5:0] qp_lc_w ;
always @* begin
case(qpwcc)
6'd0 :qpw1 = 6'd29;
6'd1 :qpw1 = 6'd30;
6'd2 :qpw1 = 6'd31;
6'd3 :qpw1 = 6'd32;
6'd4 :qpw1 = 6'd33;
6'd5 :qpw1 = 6'd33;
6'd6 :qpw1 = 6'd34;
6'd7 :qpw1 = 6'd34;
6'd8 :qpw1 = 6'd35;
6'd9 :qpw1 = 6'd35;
6'd10:qpw1 = 6'd36;
6'd11:qpw1 = 6'd36;
6'd12:qpw1 = 6'd37;
6'd13:qpw1 = 6'd37;
default:qpw1 = 6'd0 ;
endcase
end
always @* begin
if(qpw>6'd29&&qpw<6'd44)begin
qpc = qpw1;
end
else if(qpw<6'd30)begin
qpc = qpw ;
end
else begin
qpc = qpw2;
end
end
assign qp_lc_w = is_luma_i ? qpw : qpc ;
db_lut_beta ubeta1(
.qp_i(qpw),
.beta_o(beta_w)
);
db_lut_tc utc1(
.qp_i(qp_lc_w),
.mb_type_i(mb_type_i),
.tc_o(tc_w)
);
//bs_l1_r calcu
//intra : tu_edge -->2
//inter tu: tu_edge && (cbf_p || cbf_q) -->1
// pu: pu_edge & abs_l1_r(mv_p.x-mv_q.x)>3 -->1
// pu_edge & abs_l1_r(mv_p.y-mv_q.y)>3 -->1
//other : -->0
//inter chroma donot filter
wire signed [9:0] mv_p_x , mv_q_x ;
wire signed [9:0] mv_p_y , mv_q_y ;
wire [9:0] mv_m_x , mv_m_y ;
wire mv_x_gt_3_w , mv_y_gt_3_w ;
assign mv_p_x = mv_p_i[ 9: 0] ;//? ~mv_p_i[9:0] + 1'b1 : mv_p_i[9:0] ;
assign mv_p_y = mv_p_i[19:10];//? ~mv_p_i[19:10]+ 1'b1 : mv_p_i[19:10];
assign mv_q_x = mv_q_i[ 9: 0] ;//? ~mv_q_i[9:0] + 1'b1 : mv_q_i[9:0] ;
assign mv_q_y = mv_q_i[19:10];//? ~mv_q_i[19:10]+ 1'b1 : mv_q_i[19:10];
assign mv_m_x = mv_p_x > mv_q_x ? (mv_p_x - mv_q_x ):(mv_q_x - mv_p_x);
assign mv_m_y = mv_p_y > mv_q_y ? (mv_p_y - mv_q_y ):(mv_q_y - mv_p_y);
assign mv_x_gt_3_w= mv_m_x > 10'd3 ? 1'b1 : 1'b0 ;
assign mv_y_gt_3_w= mv_m_y > 10'd3 ? 1'b1 : 1'b0 ;
always @* begin
if(mb_type_i)
bs_w = tu_edge_i ;
else
bs_w = is_luma_i&&((tu_edge_i&&(cbf_p_i||cbf_q_i) )|| (pu_edge_i&&(mv_x_gt_3_w||mv_y_gt_3_w)));
end
//----------------------------------------------------------------------------
// pipeline 0:reg delay
reg [6:0] beta_r ;
reg [1:0] bs_r ;
reg [4:0] tc_r ;
reg is_ver_r ;
reg is_luma_r ;
reg is_tran_r ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
beta_r <= 7'b0 ;
tc_r <= 5'b0 ;
bs_r <= 2'b0 ;
is_ver_r <= 1'b0 ;
is_luma_r <= 1'b0 ;
is_tran_r <= 1'b0 ;
end
else begin
beta_r <= beta_w ;
tc_r <= tc_w ;
bs_r <= bs_w ;
is_ver_r <= is_ver_i ;
is_luma_r <= is_luma_i ;
is_tran_r <= is_tran_i ;
end
end
reg [7:0] p0_0_i,p0_1_i,p0_2_i,p0_3_i ,
p1_0_i,p1_1_i,p1_2_i,p1_3_i ,
p2_0_i,p2_1_i,p2_2_i,p2_3_i ,
p3_0_i,p3_1_i,p3_2_i,p3_3_i ;
reg [7:0] q0_0_i,q0_1_i,q0_2_i,q0_3_i ,
q1_0_i,q1_1_i,q1_2_i,q1_3_i ,
q2_0_i,q2_1_i,q2_2_i,q2_3_i ,
q3_0_i,q3_1_i,q3_2_i,q3_3_i ;
// p0_3_i,p0_2_i,p0_1_i,p0_0_i | q0_0_i,q0_1_i,q0_2_i,q0_3_i
// p1_3_i,p1_2_i,p1_1_i,p1_0_i | q1_0_i,q1_1_i,q1_2_i,q1_3_i
// p2_3_i,p2_2_i,p2_1_i,p2_0_i | q2_0_i,q2_1_i,q2_2_i,q2_3_i
// p3_3_i,p3_2_i,p3_1_i,p3_0_i | q3_0_i,q3_1_i,q3_2_i,q3_3_i
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
p0_3_i<=8'b0;p0_2_i<=8'b0;p0_1_i<=8'b0;p0_0_i<=8'b0;q0_0_i<=8'b0;q0_1_i<=8'b0;q0_2_i<=8'b0;q0_3_i<=8'b0;
p1_3_i<=8'b0;p1_2_i<=8'b0;p1_1_i<=8'b0;p1_0_i<=8'b0;q1_0_i<=8'b0;q1_1_i<=8'b0;q1_2_i<=8'b0;q1_3_i<=8'b0;
p2_3_i<=8'b0;p2_2_i<=8'b0;p2_1_i<=8'b0;p2_0_i<=8'b0;q2_0_i<=8'b0;q2_1_i<=8'b0;q2_2_i<=8'b0;q2_3_i<=8'b0;
p3_3_i<=8'b0;p3_2_i<=8'b0;p3_1_i<=8'b0;p3_0_i<=8'b0;q3_0_i<=8'b0;q3_1_i<=8'b0;q3_2_i<=8'b0;q3_3_i<=8'b0;
end
else begin
case({is_ver_i,is_tran_i})
2'b10:begin//ver and not tran
p3_0_i<=p_i[7 :0 ];p3_1_i<=p_i[15 : 8 ];p3_2_i<=p_i[23 :16 ];p3_3_i<=p_i[31 :24 ];
p2_0_i<=p_i[39 :32];p2_1_i<=p_i[47 : 40];p2_2_i<=p_i[55 :48 ];p2_3_i<=p_i[63 :56 ];
p1_0_i<=p_i[71 :64];p1_1_i<=p_i[79 : 72];p1_2_i<=p_i[87 :80 ];p1_3_i<=p_i[95 :88 ];
p0_0_i<=p_i[103:96];p0_1_i<=p_i[111:104];p0_2_i<=p_i[119:112];p0_3_i<=p_i[127:120];
q3_3_i<=q_i[7 :0 ];q3_2_i<=q_i[15 : 8 ];q3_1_i<=q_i[23 :16 ];q3_0_i<=q_i[31 :24 ];
q2_3_i<=q_i[39 :32];q2_2_i<=q_i[47 : 40];q2_1_i<=q_i[55 :48 ];q2_0_i<=q_i[63 :56 ];
q1_3_i<=q_i[71 :64];q1_2_i<=q_i[79 : 72];q1_1_i<=q_i[87 :80 ];q1_0_i<=q_i[95 :88 ];
q0_3_i<=q_i[103:96];q0_2_i<=q_i[111:104];q0_1_i<=q_i[119:112];q0_0_i<=q_i[127:120];
end
2'b11:begin//ver and tran
q3_3_i<=p_i[7 :0 ];q3_2_i<=p_i[15 : 8 ];q3_1_i<=p_i[23 :16 ];q3_0_i<=p_i[31 :24 ];
q2_3_i<=p_i[39 :32];q2_2_i<=p_i[47 : 40];q2_1_i<=p_i[55 :48 ];q2_0_i<=p_i[63 :56 ];
q1_3_i<=p_i[71 :64];q1_2_i<=p_i[79 : 72];q1_1_i<=p_i[87 :80 ];q1_0_i<=p_i[95 :88 ];
q0_3_i<=p_i[103:96];q0_2_i<=p_i[111:104];q0_1_i<=p_i[119:112];q0_0_i<=p_i[127:120];
p3_0_i<=q_i[7 :0 ];p3_1_i<=q_i[15 : 8 ];p3_2_i<=q_i[23 :16 ];p3_3_i<=q_i[31 :24 ];
p2_0_i<=q_i[39 :32];p2_1_i<=q_i[47 : 40];p2_2_i<=q_i[55 :48 ];p2_3_i<=q_i[63 :56 ];
p1_0_i<=q_i[71 :64];p1_1_i<=q_i[79 : 72];p1_2_i<=q_i[87 :80 ];p1_3_i<=q_i[95 :88 ];
p0_0_i<=q_i[103:96];p0_1_i<=q_i[111:104];p0_2_i<=q_i[119:112];p0_3_i<=q_i[127:120];
end
2'b00:begin//hor and not tran
p3_0_i<=p_i[7 :0 ];p2_0_i<=p_i[15 : 8 ];p1_0_i<=p_i[23 :16 ];p0_0_i<=p_i[31 :24 ];
p3_1_i<=p_i[39 :32];p2_1_i<=p_i[47 : 40];p1_1_i<=p_i[55 :48 ];p0_1_i<=p_i[63 :56 ];
p3_2_i<=p_i[71 :64];p2_2_i<=p_i[79 : 72];p1_2_i<=p_i[87 :80 ];p0_2_i<=p_i[95 :88 ];
p3_3_i<=p_i[103:96];p2_3_i<=p_i[111:104];p1_3_i<=p_i[119:112];p0_3_i<=p_i[127:120];
q3_3_i<=q_i[7 :0 ];q2_3_i<=q_i[15 : 8 ];q1_3_i<=q_i[23 :16 ];q0_3_i<=q_i[31 :24 ];
q3_2_i<=q_i[39 :32];q2_2_i<=q_i[47 : 40];q1_2_i<=q_i[55 :48 ];q0_2_i<=q_i[63 :56 ];
q3_1_i<=q_i[71 :64];q2_1_i<=q_i[79 : 72];q1_1_i<=q_i[87 :80 ];q0_1_i<=q_i[95 :88 ];
q3_0_i<=q_i[103:96];q2_0_i<=q_i[111:104];q1_0_i<=q_i[119:112];q0_0_i<=q_i[127:120];
end
2'b01:begin//hor and tran
q3_3_i<=p_i[7 :0 ];q2_3_i<=p_i[15 : 8 ];q1_3_i<=p_i[23 :16 ];q0_3_i<=p_i[31 :24 ];
q3_2_i<=p_i[39 :32];q2_2_i<=p_i[47 : 40];q1_2_i<=p_i[55 :48 ];q0_2_i<=p_i[63 :56 ];
q3_1_i<=p_i[71 :64];q2_1_i<=p_i[79 : 72];q1_1_i<=p_i[87 :80 ];q0_1_i<=p_i[95 :88 ];
q3_0_i<=p_i[103:96];q2_0_i<=p_i[111:104];q1_0_i<=p_i[119:112];q0_0_i<=p_i[127:120];
p3_0_i<=q_i[7 :0 ];p2_0_i<=q_i[15 : 8 ];p1_0_i<=q_i[23 :16 ];p0_0_i<=q_i[31 :24 ];
p3_1_i<=q_i[39 :32];p2_1_i<=q_i[47 : 40];p1_1_i<=q_i[55 :48 ];p0_1_i<=q_i[63 :56 ];
p3_2_i<=q_i[71 :64];p2_2_i<=q_i[79 : 72];p1_2_i<=q_i[87 :80 ];p0_2_i<=q_i[95 :88 ];
p3_3_i<=q_i[103:96];p2_3_i<=q_i[111:104];p1_3_i<=q_i[119:112];p0_3_i<=q_i[127:120];
end
default:begin
p3_0_i<=8'b0 ;p2_0_i<=8'b0 ;p1_0_i<=8'b0 ;p0_0_i<=8'b0;
p3_1_i<=8'b0 ;p2_1_i<=8'b0 ;p1_1_i<=8'b0 ;p0_1_i<=8'b0;
p3_2_i<=8'b0 ;p2_2_i<=8'b0 ;p1_2_i<=8'b0 ;p0_2_i<=8'b0;
p3_3_i<=8'b0 ;p2_3_i<=8'b0 ;p1_3_i<=8'b0 ;p0_3_i<=8'b0;
q3_3_i<=8'b0 ;q2_3_i<=8'b0 ;q1_3_i<=8'b0 ;q0_3_i<=8'b0;
q3_2_i<=8'b0 ;q2_2_i<=8'b0 ;q1_2_i<=8'b0 ;q0_2_i<=8'b0;
q3_1_i<=8'b0 ;q2_1_i<=8'b0 ;q1_1_i<=8'b0 ;q0_1_i<=8'b0;
q3_0_i<=8'b0 ;q2_0_i<=8'b0 ;q1_0_i<=8'b0 ;q0_0_i<=8'b0;
end
endcase
end
end
//---------------------------------------------------------------------------
//
// stage1_a:calcu middle variabls
//
//----------------------------------------------------------------------------
wire signed [8:0] p0_0_s_w , p0_1_s_w ,p0_2_s_w ;
wire signed [8:0] p3_0_s_w , p3_1_s_w ,p3_2_s_w ;
wire signed [8:0] q0_0_s_w , q0_1_s_w ,q0_2_s_w ;
wire signed [8:0] q3_0_s_w , q3_1_s_w ,q3_2_s_w ;
wire signed [9:0] dp0_w , dp3_w ;
wire signed [9:0] dq0_w , dq3_w ;
wire [9:0] dpw , dqw ;
wire [9:0] dqp0_w , dqp3_w ;
wire [10:0] dqp0_m_2_w , dqp3_m_2_w ;
wire [10:0] d_w ;
wire [6:0] tc_mux_3_2_w ;
wire [6:0] beta_m_w ;
wire [9:0] dp0_abs_l1_r_w,dp3_abs_l1_r_w ;
wire [9:0] dq0_abs_l1_r_w,dq3_abs_l1_r_w ;
wire [7:0] dp0_3_0 ,dq0_3_0,dpq0_0_0;
wire [7:0] dp3_3_0 ,dq3_3_0,dpq3_0_0;
wire dsam0 , dsam3 ;
assign p0_0_s_w = {1'b0,p0_0_i} ;
assign p0_1_s_w = {1'b0,p0_1_i} ;
assign p0_2_s_w = {1'b0,p0_2_i} ;
assign p3_0_s_w = {1'b0,p3_0_i} ;
assign p3_1_s_w = {1'b0,p3_1_i} ;
assign p3_2_s_w = {1'b0,p3_2_i} ;
assign q0_0_s_w = {1'b0,q0_0_i} ;
assign q0_1_s_w = {1'b0,q0_1_i} ;
assign q0_2_s_w = {1'b0,q0_2_i} ;
assign q3_0_s_w = {1'b0,q3_0_i} ;
assign q3_1_s_w = {1'b0,q3_1_i} ;
assign q3_2_s_w = {1'b0,q3_2_i} ;
assign beta_m_w = (beta_r + (beta_r>>1)) >>3 ;
assign dp0_w = p0_2_s_w + p0_0_s_w - p0_1_s_w - p0_1_s_w ;
assign dp3_w = p3_2_s_w + p3_0_s_w - p3_1_s_w - p3_1_s_w ;
assign dq0_w = q0_2_s_w + q0_0_s_w - q0_1_s_w - q0_1_s_w ;
assign dq3_w = q3_2_s_w + q3_0_s_w - q3_1_s_w - q3_1_s_w ;
assign dp0_abs_l1_r_w = dp0_w[9] ? (~dp0_w + 1'b1) : dp0_w;
assign dp3_abs_l1_r_w = dp3_w[9] ? (~dp3_w + 1'b1) : dp3_w;
assign dq0_abs_l1_r_w = dq0_w[9] ? (~dq0_w + 1'b1) : dq0_w;
assign dq3_abs_l1_r_w = dq3_w[9] ? (~dq3_w + 1'b1) : dq3_w;
assign dpw = dp0_abs_l1_r_w + dp3_abs_l1_r_w ;
assign dqw = dq0_abs_l1_r_w + dq3_abs_l1_r_w ;
assign dqp0_w = dp0_abs_l1_r_w + dq0_abs_l1_r_w;
assign dqp3_w = dp3_abs_l1_r_w + dq3_abs_l1_r_w;
assign d_w = dpw + dqw ;
assign dp0_3_0 = p0_0_i > p0_3_i ? (p0_0_i - p0_3_i) : (p0_3_i - p0_0_i);
assign dq0_3_0 = q0_0_i > q0_3_i ? (q0_0_i - q0_3_i) : (q0_3_i - q0_0_i);
assign dp3_3_0 = p3_0_i > p3_3_i ? (p3_0_i - p3_3_i) : (p3_3_i - p3_0_i);
assign dq3_3_0 = q3_0_i > q3_3_i ? (q3_0_i - q3_3_i) : (q3_3_i - q3_0_i);
assign dpq0_0_0 = p0_0_i > q0_0_i ? (p0_0_i - q0_0_i) : (q0_0_i - p0_0_i);
assign dpq3_0_0 = p3_0_i > q3_0_i ? (p3_0_i - q3_0_i) : (q3_0_i - p3_0_i);
assign tc_mux_3_2_w = ({tc_r,2'b0}+tc_r+1)>>1 ;
assign dqp0_m_2_w = {dqp0_w,1'b0} ;
assign dqp3_m_2_w = {dqp3_w,1'b0} ;
assign dsam0 = ((dqp0_m_2_w< beta_r[6:2])&&((dp0_3_0 + dq0_3_0)< beta_r[6:3])&&( dpq0_0_0< tc_mux_3_2_w )) ? 1'b1 : 1'b0 ;
assign dsam3 = ((dqp3_m_2_w< beta_r[6:2])&&((dp3_3_0 + dq3_3_0)< beta_r[6:3])&&( dpq3_0_0< tc_mux_3_2_w )) ? 1'b1 : 1'b0 ;
//---------------------------------------------------------------------------
//
// stage1_b:calc conditions and filter dicisons
//
//----------------------------------------------------------------------------
wire d_less_beta_w ; //0:no filter , 1:filter
wire norm_str_w ; //0:normal filter , 1:strong filter
wire filter_cout_pw ; //0:1 pixel filtered, 1:2 pixels filtered
wire filter_cout_qw ;
assign d_less_beta_w = (d_w < beta_r ) ? 1'b1 : 1'b0 ;
assign filter_cout_pw = (dpw < beta_m_w ) ? 1'b1 : 1'b0 ;
assign filter_cout_qw = (dqw < beta_m_w ) ? 1'b1 : 1'b0 ;
assign norm_str_w = (dsam0&&dsam3 ) ? 1'b1 : 1'b0 ;
//---------------------------------------------------------------------------
//
// stage1_c:normal filter and only filter 1 pixels
//
//----------------------------------------------------------------------------
wire signed [8:0] delta0_w ;
wire signed [8:0] delta1_w ;
wire signed [8:0] delta2_w ;
wire signed [8:0] delta3_w ;
wire [3:0] not_nature_edge_w ;
db_normal_filter_1 unormal_1(
//input
.tc_i (tc_r ),
.p0_0_i(p0_0_i ) , .p0_1_i(p0_1_i ) , .p0_2_i(p0_2_i),
.p1_0_i(p1_0_i ) , .p1_1_i(p1_1_i ) , .p1_2_i(p1_2_i),
.p2_0_i(p2_0_i ) , .p2_1_i(p2_1_i ) , .p2_2_i(p2_2_i),
.p3_0_i(p3_0_i ) , .p3_1_i(p3_1_i ) , .p3_2_i(p3_2_i),
.q0_0_i(q0_0_i ) , .q0_1_i(q0_1_i ) , .q0_2_i(q0_2_i),
.q1_0_i(q1_0_i ) , .q1_1_i(q1_1_i ) , .q1_2_i(q1_2_i),
.q2_0_i(q2_0_i ) , .q2_1_i(q2_1_i ) , .q2_2_i(q2_2_i),
.q3_0_i(q3_0_i ) , .q3_1_i(q3_1_i ) , .q3_2_i(q3_2_i),
//output
.delta0_o(delta0_w),
.delta1_o(delta1_w),
.delta2_o(delta2_w),
.delta3_o(delta3_w),
.not_nature_edge_o(not_nature_edge_w)
);
//----------------------------------------------------------------------------------------------
//reg delay 1 cycles
reg [7:0] p0_0_l1_r,p0_1_l1_r,p0_2_l1_r,p0_3_l1_r,
p1_0_l1_r,p1_1_l1_r,p1_2_l1_r,p1_3_l1_r,
p2_0_l1_r,p2_1_l1_r,p2_2_l1_r,p2_3_l1_r,
p3_0_l1_r,p3_1_l1_r,p3_2_l1_r,p3_3_l1_r;
reg [7:0] q0_0_l1_r,q0_1_l1_r,q0_2_l1_r,q0_3_l1_r,
q1_0_l1_r,q1_1_l1_r,q1_2_l1_r,q1_3_l1_r,
q2_0_l1_r,q2_1_l1_r,q2_2_l1_r,q2_3_l1_r,
q3_0_l1_r,q3_1_l1_r,q3_2_l1_r,q3_3_l1_r;
reg signed [8:0] delta0_r ;
reg signed [8:0] delta1_r ;
reg signed [8:0] delta2_r ;
reg signed [8:0] delta3_r ;
reg [3:0] not_nature_edge_r ;
reg [4:0] tc_l1_r ;
reg [1:0] bs_l1_r ;
reg is_ver_d1_r ;
reg is_luma_d1_r ;
reg is_tran_d1_r ;
reg d_less_beta_l1_r ;
reg norm_str_l1_r ;
reg filter_cout_pl1_r ;
reg filter_cout_ql1_r ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
p0_0_l1_r<= 8'b0 ; p0_1_l1_r<= 8'b0 ; p0_2_l1_r<= 8'b0 ; p0_3_l1_r<= 8'b0 ;
p1_0_l1_r<= 8'b0 ; p1_1_l1_r<= 8'b0 ; p1_2_l1_r<= 8'b0 ; p1_3_l1_r<= 8'b0 ;
p2_0_l1_r<= 8'b0 ; p2_1_l1_r<= 8'b0 ; p2_2_l1_r<= 8'b0 ; p2_3_l1_r<= 8'b0 ;
p3_0_l1_r<= 8'b0 ; p3_1_l1_r<= 8'b0 ; p3_2_l1_r<= 8'b0 ; p3_3_l1_r<= 8'b0 ;
q0_0_l1_r<= 8'b0 ; q0_1_l1_r<= 8'b0 ; q0_2_l1_r<= 8'b0 ; q0_3_l1_r<= 8'b0 ;
q1_0_l1_r<= 8'b0 ; q1_1_l1_r<= 8'b0 ; q1_2_l1_r<= 8'b0 ; q1_3_l1_r<= 8'b0 ;
q2_0_l1_r<= 8'b0 ; q2_1_l1_r<= 8'b0 ; q2_2_l1_r<= 8'b0 ; q2_3_l1_r<= 8'b0 ;
q3_0_l1_r<= 8'b0 ; q3_1_l1_r<= 8'b0 ; q3_2_l1_r<= 8'b0 ; q3_3_l1_r<= 8'b0 ;
delta0_r <=9'b0 ; delta1_r <=9'b0; delta2_r <=9'b0 ; delta3_r <=9'b0 ;
not_nature_edge_r <=4'b0;
tc_l1_r <= 5'b0 ;
bs_l1_r <= 2'b0 ;
is_ver_d1_r <= 1'b0 ;
is_luma_d1_r<= 1'b0 ;
is_tran_d1_r<= 1'b0 ;
d_less_beta_l1_r <= 1'b0;
norm_str_l1_r <= 1'b0;
filter_cout_pl1_r <= 1'b0 ;
filter_cout_ql1_r <= 1'b0 ;
end
else begin
p0_0_l1_r<=p0_0_i ; p0_1_l1_r<=p0_1_i ; p0_2_l1_r<=p0_2_i ; p0_3_l1_r<=p0_3_i;
p1_0_l1_r<=p1_0_i ; p1_1_l1_r<=p1_1_i ; p1_2_l1_r<=p1_2_i ; p1_3_l1_r<=p1_3_i;
p2_0_l1_r<=p2_0_i ; p2_1_l1_r<=p2_1_i ; p2_2_l1_r<=p2_2_i ; p2_3_l1_r<=p2_3_i;
p3_0_l1_r<=p3_0_i ; p3_1_l1_r<=p3_1_i ; p3_2_l1_r<=p3_2_i ; p3_3_l1_r<=p3_3_i;
q0_0_l1_r<=q0_0_i ; q0_1_l1_r<=q0_1_i ; q0_2_l1_r<=q0_2_i ; q0_3_l1_r<=q0_3_i;
q1_0_l1_r<=q1_0_i ; q1_1_l1_r<=q1_1_i ; q1_2_l1_r<=q1_2_i ; q1_3_l1_r<=q1_3_i;
q2_0_l1_r<=q2_0_i ; q2_1_l1_r<=q2_1_i ; q2_2_l1_r<=q2_2_i ; q2_3_l1_r<=q2_3_i;
q3_0_l1_r<=q3_0_i ; q3_1_l1_r<=q3_1_i ; q3_2_l1_r<=q3_2_i ; q3_3_l1_r<=q3_3_i;
delta0_r <=delta0_w ; delta1_r <=delta1_w ; delta2_r <=delta2_w ;delta3_r <= delta3_w ;
not_nature_edge_r <=not_nature_edge_w;
tc_l1_r <= tc_r ;
bs_l1_r <= bs_r ;
is_ver_d1_r <=is_ver_r ;
is_luma_d1_r<=is_luma_r ;
is_tran_d1_r<=is_tran_r ;
d_less_beta_l1_r <= d_less_beta_w ;
norm_str_l1_r <= norm_str_w ;
filter_cout_pl1_r <= filter_cout_pw ;
filter_cout_ql1_r <= filter_cout_qw ;
end
end
//---------------------------------------------------------------------------
//
// stage2:filter process
//
//----------------------------------------------------------------------------
//strong filter
wire [7:0] p0_0_str_w,p0_1_str_w,p0_2_str_w,
p1_0_str_w,p1_1_str_w,p1_2_str_w,
p2_0_str_w,p2_1_str_w,p2_2_str_w,
p3_0_str_w,p3_1_str_w,p3_2_str_w;
wire [7:0] q0_0_str_w,q0_1_str_w,q0_2_str_w,
q1_0_str_w,q1_1_str_w,q1_2_str_w,
q2_0_str_w,q2_1_str_w,q2_2_str_w,
q3_0_str_w,q3_1_str_w,q3_2_str_w;
db_strong_filter ustrong_filter(
//input
.tc_i(tc_l1_r),
.p0_0_i(p0_0_l1_r) , .p0_1_i(p0_1_l1_r) , .p0_2_i(p0_2_l1_r) , .p0_3_i(p0_3_l1_r),
.p1_0_i(p1_0_l1_r) , .p1_1_i(p1_1_l1_r) , .p1_2_i(p1_2_l1_r) , .p1_3_i(p1_3_l1_r),
.p2_0_i(p2_0_l1_r) , .p2_1_i(p2_1_l1_r) , .p2_2_i(p2_2_l1_r) , .p2_3_i(p2_3_l1_r),
.p3_0_i(p3_0_l1_r) , .p3_1_i(p3_1_l1_r) , .p3_2_i(p3_2_l1_r) , .p3_3_i(p3_3_l1_r),
.q0_0_i(q0_0_l1_r) , .q0_1_i(q0_1_l1_r) , .q0_2_i(q0_2_l1_r) , .q0_3_i(q0_3_l1_r),
.q1_0_i(q1_0_l1_r) , .q1_1_i(q1_1_l1_r) , .q1_2_i(q1_2_l1_r) , .q1_3_i(q1_3_l1_r),
.q2_0_i(q2_0_l1_r) , .q2_1_i(q2_1_l1_r) , .q2_2_i(q2_2_l1_r) , .q2_3_i(q2_3_l1_r),
.q3_0_i(q3_0_l1_r) , .q3_1_i(q3_1_l1_r) , .q3_2_i(q3_2_l1_r) , .q3_3_i(q3_3_l1_r),
//output
.p0_0_o(p0_0_str_w) , .p0_1_o(p0_1_str_w) , .p0_2_o(p0_2_str_w) ,
.p1_0_o(p1_0_str_w) , .p1_1_o(p1_1_str_w) , .p1_2_o(p1_2_str_w) ,
.p2_0_o(p2_0_str_w) , .p2_1_o(p2_1_str_w) , .p2_2_o(p2_2_str_w) ,
.p3_0_o(p3_0_str_w) , .p3_1_o(p3_1_str_w) , .p3_2_o(p3_2_str_w) ,
.q0_0_o(q0_0_str_w) , .q0_1_o(q0_1_str_w) , .q0_2_o(q0_2_str_w) ,
.q1_0_o(q1_0_str_w) , .q1_1_o(q1_1_str_w) , .q1_2_o(q1_2_str_w) ,
.q2_0_o(q2_0_str_w) , .q2_1_o(q2_1_str_w) , .q2_2_o(q2_2_str_w) ,
.q3_0_o(q3_0_str_w) , .q3_1_o(q3_1_str_w) , .q3_2_o(q3_2_str_w)
);
//----------------------------------------------------------------------------
//normal filter
wire [7:0] p0_0_nor_w , q0_0_nor_w;
wire [7:0] p1_0_nor_w , q1_0_nor_w;
wire [7:0] p2_0_nor_w , q2_0_nor_w;
wire [7:0] p3_0_nor_w , q3_0_nor_w;
wire [7:0] p0_1_nor_w , q0_1_nor_w;
wire [7:0] p1_1_nor_w , q1_1_nor_w;
wire [7:0] p2_1_nor_w , q2_1_nor_w;
wire [7:0] p3_1_nor_w , q3_1_nor_w;
wire [7:0] p0_0_c_w , q0_0_c_w ;//chroma output
wire [7:0] p1_0_c_w , q1_0_c_w ;
wire [7:0] p2_0_c_w , q2_0_c_w ;
wire [7:0] p3_0_c_w , q3_0_c_w ;
db_normal_filter_2 unormal_2(
//input
.tc_i (tc_l1_r ),
.p0_0_i (p0_0_l1_r ),.p0_1_i(p0_1_l1_r),.p0_2_i(p0_2_l1_r),
.p1_0_i (p1_0_l1_r ),.p1_1_i(p1_1_l1_r),.p1_2_i(p1_2_l1_r),
.p2_0_i (p2_0_l1_r ),.p2_1_i(p2_1_l1_r),.p2_2_i(p2_2_l1_r),
.p3_0_i (p3_0_l1_r ),.p3_1_i(p3_1_l1_r),.p3_2_i(p3_2_l1_r),
.q0_0_i (q0_0_l1_r ),.q0_1_i(q0_1_l1_r),.q0_2_i(q0_2_l1_r),
.q1_0_i (q1_0_l1_r ),.q1_1_i(q1_1_l1_r),.q1_2_i(q1_2_l1_r),
.q2_0_i (q2_0_l1_r ),.q2_1_i(q2_1_l1_r),.q2_2_i(q2_2_l1_r),
.q3_0_i (q3_0_l1_r ),.q3_1_i(q3_1_l1_r),.q3_2_i(q3_2_l1_r),
.delta0_i(delta0_r ),
.delta1_i(delta1_r ),
.delta2_i(delta2_r ),
.delta3_i(delta3_r ),
//output
.p0_0_o (p0_0_nor_w),
.p1_0_o (p1_0_nor_w),
.p2_0_o (p2_0_nor_w),
.p3_0_o (p3_0_nor_w),
.q0_0_o (q0_0_nor_w),
.q1_0_o (q1_0_nor_w),
.q2_0_o (q2_0_nor_w),
.q3_0_o (q3_0_nor_w),
.p0_1_o (p0_1_nor_w),
.p1_1_o (p1_1_nor_w),
.p2_1_o (p2_1_nor_w),
.p3_1_o (p3_1_nor_w),
.q0_1_o (q0_1_nor_w),
.q1_1_o (q1_1_nor_w),
.q2_1_o (q2_1_nor_w),
.q3_1_o (q3_1_nor_w),
.p0_0_c_o(p0_0_c_w ),
.p1_0_c_o(p1_0_c_w ),
.p2_0_c_o(p2_0_c_w ),
.p3_0_c_o(p3_0_c_w ),
.q0_0_c_o(q0_0_c_w ),
.q1_0_c_o(q1_0_c_w ),
.q2_0_c_o(q2_0_c_w ),
.q3_0_c_o(q3_0_c_w )
);
//---------------------------------------------------------------------------
//
//stage3:output,select strong/normal filter 2 pixels/normal filter 1 pixels
//
//----------------------------------------------------------------------------
reg [7:0] p0_0_o,p0_1_o,p0_2_o,p0_3_o ,
p1_0_o,p1_1_o,p1_2_o,p1_3_o ,
p2_0_o,p2_1_o,p2_2_o,p2_3_o ,
p3_0_o,p3_1_o,p3_2_o,p3_3_o ;
reg [7:0] q0_0_o,q0_1_o,q0_2_o,q0_3_o ,
q1_0_o,q1_1_o,q1_2_o,q1_3_o ,
q2_0_o,q2_1_o,q2_2_o,q2_3_o ,
q3_0_o,q3_1_o,q3_2_o,q3_3_o ;
// p0_0 p0_1 p0_2 p0_3
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
p0_0_o <= 8'b0 ;
p0_1_o <= 8'b0 ;
p0_2_o <= 8'b0 ;
end
else if(!is_luma_d1_r&&bs_l1_r) begin // chroma
p0_0_o <= p0_0_c_w ;
p0_1_o <= p0_1_l1_r ;
p0_2_o <= p0_2_l1_r ;
end
else if(!(bs_l1_r &&d_less_beta_l1_r&¬_nature_edge_r[0]) ) begin // no filter
p0_0_o <= p0_0_l1_r ;
p0_1_o <= p0_1_l1_r ;
p0_2_o <= p0_2_l1_r ;
end
else begin
if(norm_str_l1_r) begin //strong filter
p0_0_o <= p0_0_str_w ;
p0_1_o <= p0_1_str_w ;
p0_2_o <= p0_2_str_w ;
end
else begin //normal filter
if(filter_cout_pl1_r) begin //p 2 fixels filter
p0_0_o <= p0_0_nor_w ;
p0_1_o <= p0_1_nor_w ;
p0_2_o <= p0_2_l1_r ;
end
else begin //p 1 fixels filter
p0_0_o <= p0_0_nor_w ;
p0_1_o <= p0_1_l1_r ;
p0_2_o <= p0_2_l1_r ;
end
end
end
end
// p1_0 p1_1 p1_2 p1_3
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
p1_0_o <= 8'b0 ;
p1_1_o <= 8'b0 ;
p1_2_o <= 8'b0 ;
end
else if(!is_luma_d1_r&&bs_l1_r)begin
p1_0_o <= p1_0_c_w ;
p1_1_o <= p1_1_l1_r ;
p1_2_o <= p1_2_l1_r ;
end
else if(! (bs_l1_r &&d_less_beta_l1_r&¬_nature_edge_r[1]) ) begin // no filter
p1_0_o <= p1_0_l1_r ;
p1_1_o <= p1_1_l1_r ;
p1_2_o <= p1_2_l1_r ;
end
else begin
if(norm_str_l1_r) begin //strong filter
p1_0_o <= p1_0_str_w ;
p1_1_o <= p1_1_str_w ;
p1_2_o <= p1_2_str_w ;
end
else begin //normal filter
if(filter_cout_pl1_r) begin //p 2 fixels filter
p1_0_o <= p1_0_nor_w ;
p1_1_o <= p1_1_nor_w ;
p1_2_o <= p1_2_l1_r ;
end
else begin //p 1 fixels filter
p1_0_o <= p1_0_nor_w ;
p1_1_o <= p1_1_l1_r ;
p1_2_o <= p1_2_l1_r ;
end
end
end
end
// p2_0 p2_1 p2_2 p2_3
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
p2_0_o <= 8'b0 ;
p2_1_o <= 8'b0 ;
p2_2_o <= 8'b0 ;
end
else if(!is_luma_d1_r&&bs_l1_r)begin
p2_0_o <= p2_0_c_w ;
p2_1_o <= p2_1_l1_r ;
p2_2_o <= p2_2_l1_r ;
end
else if(! (bs_l1_r &&d_less_beta_l1_r&¬_nature_edge_r[2]) ) begin // no filter
p2_0_o <= p2_0_l1_r ;
p2_1_o <= p2_1_l1_r ;
p2_2_o <= p2_2_l1_r ;
end
else begin
if(norm_str_l1_r) begin //strong filter
p2_0_o <= p2_0_str_w ;
p2_1_o <= p2_1_str_w ;
p2_2_o <= p2_2_str_w ;
end
else begin //normal filter
if(filter_cout_pl1_r) begin //p 2 fixels filter
p2_0_o <= p2_0_nor_w ;
p2_1_o <= p2_1_nor_w ;
p2_2_o <= p2_2_l1_r ;
end
else begin //p 1 fixels filter
p2_0_o <= p2_0_nor_w ;
p2_1_o <= p2_1_l1_r ;
p2_2_o <= p2_2_l1_r ;
end
end
end
end
// p3_0 p3_1 p3_2 p3_3
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
p3_0_o <= 8'b0 ;
p3_1_o <= 8'b0 ;
p3_2_o <= 8'b0 ;
end
else if(!is_luma_d1_r&&bs_l1_r)begin
p3_0_o <= p3_0_c_w ;
p3_1_o <= p3_1_l1_r ;
p3_2_o <= p3_2_l1_r ;
end
else if(! (bs_l1_r &&d_less_beta_l1_r&¬_nature_edge_r[3]) ) begin // no filter
p3_0_o <= p3_0_l1_r ;
p3_1_o <= p3_1_l1_r ;
p3_2_o <= p3_2_l1_r ;
end
else begin
if(norm_str_l1_r) begin //strong filter
p3_0_o <= p3_0_str_w ;
p3_1_o <= p3_1_str_w ;
p3_2_o <= p3_2_str_w ;
end
else begin //normal filter
if(filter_cout_pl1_r) begin //p 2 fixels filter
p3_0_o <= p3_0_nor_w ;
p3_1_o <= p3_1_nor_w ;
p3_2_o <= p3_2_l1_r ;
end
else begin //p 1 fixels filter
p3_0_o <= p3_0_nor_w ;
p3_1_o <= p3_1_l1_r ;
p3_2_o <= p3_2_l1_r ;
end
end
end
end
// q0_0 q0_1 q0_2 q0_3
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
q0_0_o <= 8'b0 ;
q0_1_o <= 8'b0 ;
q0_2_o <= 8'b0 ;
end
else if(!is_luma_d1_r&&bs_l1_r)begin
q0_0_o <= q0_0_c_w ;
q0_1_o <= q0_1_l1_r ;
q0_2_o <= q0_2_l1_r ;
end
else if(! (bs_l1_r &&d_less_beta_l1_r&¬_nature_edge_r[0]) ) begin // no filter
q0_0_o <= q0_0_l1_r ;
q0_1_o <= q0_1_l1_r ;
q0_2_o <= q0_2_l1_r ;
end
else begin
if(norm_str_l1_r) begin //strong filter
q0_0_o <= q0_0_str_w ;
q0_1_o <= q0_1_str_w ;
q0_2_o <= q0_2_str_w ;
end
else begin //normal filter
if(filter_cout_ql1_r) begin //q 2 fixels filter
q0_0_o <= q0_0_nor_w ;
q0_1_o <= q0_1_nor_w ;
q0_2_o <= q0_2_l1_r ;
end
else begin //q 1 fixels filter
q0_0_o <= q0_0_nor_w ;
q0_1_o <= q0_1_l1_r ;
q0_2_o <= q0_2_l1_r ;
end
end
end
end
// q1_0 q1_1 q1_2 q1_3
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
q1_0_o <= 8'b0 ;
q1_1_o <= 8'b0 ;
q1_2_o <= 8'b0 ;
end
else if(!is_luma_d1_r&&bs_l1_r)begin
q1_0_o <= q1_0_c_w ;
q1_1_o <= q1_1_l1_r ;
q1_2_o <= q1_2_l1_r ;
end
else if(! (bs_l1_r &&d_less_beta_l1_r&¬_nature_edge_r[1]) ) begin // no filter
q1_0_o <= q1_0_l1_r ;
q1_1_o <= q1_1_l1_r ;
q1_2_o <= q1_2_l1_r ;
end
else begin
if(norm_str_l1_r) begin //strong filter
q1_0_o <= q1_0_str_w ;
q1_1_o <= q1_1_str_w ;
q1_2_o <= q1_2_str_w ;
end
else begin //normal filter
if(filter_cout_ql1_r) begin //q 2 fixels filter
q1_0_o <= q1_0_nor_w ;
q1_1_o <= q1_1_nor_w ;
q1_2_o <= q1_2_l1_r ;
end
else begin //q 1 fixels filter
q1_0_o <= q1_0_nor_w ;
q1_1_o <= q1_1_l1_r ;
q1_2_o <= q1_2_l1_r ;
end
end
end
end
// q2_0 q2_1 q2_2 q2_3
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
q2_0_o <= 8'b0 ;
q2_1_o <= 8'b0 ;
q2_2_o <= 8'b0 ;
end
else if(!is_luma_d1_r&&bs_l1_r)begin
q2_0_o <= q2_0_c_w ;
q2_1_o <= q2_1_l1_r ;
q2_2_o <= q2_2_l1_r ;
end
else if(! (bs_l1_r &&d_less_beta_l1_r&¬_nature_edge_r[2]) ) begin // no filter
q2_0_o <= q2_0_l1_r ;
q2_1_o <= q2_1_l1_r ;
q2_2_o <= q2_2_l1_r ;
end
else begin
if(norm_str_l1_r) begin //strong filter
q2_0_o <= q2_0_str_w ;
q2_1_o <= q2_1_str_w ;
q2_2_o <= q2_2_str_w ;
end
else begin //normal filter
if(filter_cout_ql1_r) begin //q 2 fixels filter
q2_0_o <= q2_0_nor_w ;
q2_1_o <= q2_1_nor_w ;
q2_2_o <= q2_2_l1_r ;
end
else begin //q 1 fixels filter
q2_0_o <= q2_0_nor_w ;
q2_1_o <= q2_1_l1_r ;
q2_2_o <= q2_2_l1_r ;
end
end
end
end
// q3_0 q3_1 q3_2 q3_3
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
q3_0_o <= 8'b0 ;
q3_1_o <= 8'b0 ;
q3_2_o <= 8'b0 ;
end
else if(!is_luma_d1_r&&bs_l1_r)begin
q3_0_o <= q3_0_c_w ;
q3_1_o <= q3_1_l1_r ;
q3_2_o <= q3_2_l1_r ;
end
else if(! (bs_l1_r &&d_less_beta_l1_r&¬_nature_edge_r[3]) ) begin // no filter
q3_0_o <= q3_0_l1_r ;
q3_1_o <= q3_1_l1_r ;
q3_2_o <= q3_2_l1_r ;
end
else begin
if(norm_str_l1_r) begin //strong filter
q3_0_o <= q3_0_str_w ;
q3_1_o <= q3_1_str_w ;
q3_2_o <= q3_2_str_w ;
end
else begin //normal filter
if(filter_cout_ql1_r) begin //q 2 fixels filter
q3_0_o <= q3_0_nor_w ;
q3_1_o <= q3_1_nor_w ;
q3_2_o <= q3_2_l1_r ;
end
else begin //q 1 fixels filter
q3_0_o <= q3_0_nor_w ;
q3_1_o <= q3_1_l1_r ;
q3_2_o <= q3_2_l1_r ;
end
end
end
end
// p0_3_o p1_3_o p2_3_o p3_3_o q0_3_o q1_3_o q2_3_o q3_3_o
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
p0_3_o <= 8'b0 ;
p1_3_o <= 8'b0 ;
p2_3_o <= 8'b0 ;
p3_3_o <= 8'b0 ;
q0_3_o <= 8'b0 ;
q1_3_o <= 8'b0 ;
q2_3_o <= 8'b0 ;
q3_3_o <= 8'b0 ;
end
else begin
p0_3_o <= p0_3_l1_r ;
p1_3_o <= p1_3_l1_r ;
p2_3_o <= p2_3_l1_r ;
p3_3_o <= p3_3_l1_r ;
q0_3_o <= q0_3_l1_r ;
q1_3_o <= q1_3_l1_r ;
q2_3_o <= q2_3_l1_r ;
q3_3_o <= q3_3_l1_r ;
end
end
reg is_tran_d2_r ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
is_tran_d2_r <= 1'b0;
else
is_tran_d2_r <= is_tran_d1_r;
end
always @* begin
case({is_ver_d1_r,is_tran_d2_r})
2'b10:begin//ver and not tran
f_p_o[7 :0 ]=p3_0_o;f_p_o[15 : 8 ]=p3_1_o;f_p_o[23 :16 ]=p3_2_o;f_p_o[31 :24 ]=p3_3_o;
f_p_o[39 :32]=p2_0_o;f_p_o[47 : 40]=p2_1_o;f_p_o[55 :48 ]=p2_2_o;f_p_o[63 :56 ]=p2_3_o;
f_p_o[71 :64]=p1_0_o;f_p_o[79 : 72]=p1_1_o;f_p_o[87 :80 ]=p1_2_o;f_p_o[95 :88 ]=p1_3_o;
f_p_o[103:96]=p0_0_o;f_p_o[111:104]=p0_1_o;f_p_o[119:112]=p0_2_o;f_p_o[127:120]=p0_3_o;
f_q_o[7 :0 ]=q3_3_o;f_q_o[15 : 8 ]=q3_2_o;f_q_o[23 :16 ]=q3_1_o;f_q_o[31 :24 ]=q3_0_o;
f_q_o[39 :32]=q2_3_o;f_q_o[47 : 40]=q2_2_o;f_q_o[55 :48 ]=q2_1_o;f_q_o[63 :56 ]=q2_0_o;
f_q_o[71 :64]=q1_3_o;f_q_o[79 : 72]=q1_2_o;f_q_o[87 :80 ]=q1_1_o;f_q_o[95 :88 ]=q1_0_o;
f_q_o[103:96]=q0_3_o;f_q_o[111:104]=q0_2_o;f_q_o[119:112]=q0_1_o;f_q_o[127:120]=q0_0_o;
end
2'b11:begin//ver and tran
f_q_o[7 :0 ]=p3_0_o;f_q_o[15 : 8 ]=p3_1_o;f_q_o[23 :16 ]=p3_2_o;f_q_o[31 :24 ]=p3_3_o;
f_q_o[39 :32]=p2_0_o;f_q_o[47 : 40]=p2_1_o;f_q_o[55 :48 ]=p2_2_o;f_q_o[63 :56 ]=p2_3_o;
f_q_o[71 :64]=p1_0_o;f_q_o[79 : 72]=p1_1_o;f_q_o[87 :80 ]=p1_2_o;f_q_o[95 :88 ]=p1_3_o;
f_q_o[103:96]=p0_0_o;f_q_o[111:104]=p0_1_o;f_q_o[119:112]=p0_2_o;f_q_o[127:120]=p0_3_o;
f_p_o[7 :0 ]=q3_3_o;f_p_o[15 : 8 ]=q3_2_o;f_p_o[23 :16 ]=q3_1_o;f_p_o[31 :24 ]=q3_0_o;
f_p_o[39 :32]=q2_3_o;f_p_o[47 : 40]=q2_2_o;f_p_o[55 :48 ]=q2_1_o;f_p_o[63 :56 ]=q2_0_o;
f_p_o[71 :64]=q1_3_o;f_p_o[79 : 72]=q1_2_o;f_p_o[87 :80 ]=q1_1_o;f_p_o[95 :88 ]=q1_0_o;
f_p_o[103:96]=q0_3_o;f_p_o[111:104]=q0_2_o;f_p_o[119:112]=q0_1_o;f_p_o[127:120]=q0_0_o;
end
2'b00:begin//hor and not tran
f_p_o[7 :0 ]=p3_0_o;f_p_o[15 : 8 ]=p2_0_o;f_p_o[23 :16 ]=p1_0_o;f_p_o[31 :24 ]=p0_0_o;
f_p_o[39 :32]=p3_1_o;f_p_o[47 : 40]=p2_1_o;f_p_o[55 :48 ]=p1_1_o;f_p_o[63 :56 ]=p0_1_o;
f_p_o[71 :64]=p3_2_o;f_p_o[79 : 72]=p2_2_o;f_p_o[87 :80 ]=p1_2_o;f_p_o[95 :88 ]=p0_2_o;
f_p_o[103:96]=p3_3_o;f_p_o[111:104]=p2_3_o;f_p_o[119:112]=p1_3_o;f_p_o[127:120]=p0_3_o;
f_q_o[7 :0 ]=q3_3_o;f_q_o[15 : 8 ]=q2_3_o;f_q_o[23 :16 ]=q1_3_o;f_q_o[31 :24 ]=q0_3_o;
f_q_o[39 :32]=q3_2_o;f_q_o[47 : 40]=q2_2_o;f_q_o[55 :48 ]=q1_2_o;f_q_o[63 :56 ]=q0_2_o;
f_q_o[71 :64]=q3_1_o;f_q_o[79 : 72]=q2_1_o;f_q_o[87 :80 ]=q1_1_o;f_q_o[95 :88 ]=q0_1_o;
f_q_o[103:96]=q3_0_o;f_q_o[111:104]=q2_0_o;f_q_o[119:112]=q1_0_o;f_q_o[127:120]=q0_0_o;
end
2'b01:begin//hor and tran
f_q_o[7 :0 ]=p3_0_o;f_q_o[15 : 8 ]=p2_0_o;f_q_o[23 :16 ]=p1_0_o;f_q_o[31 :24 ]=p0_0_o;
f_q_o[39 :32]=p3_1_o;f_q_o[47 : 40]=p2_1_o;f_q_o[55 :48 ]=p1_1_o;f_q_o[63 :56 ]=p0_1_o;
f_q_o[71 :64]=p3_2_o;f_q_o[79 : 72]=p2_2_o;f_q_o[87 :80 ]=p1_2_o;f_q_o[95 :88 ]=p0_2_o;
f_q_o[103:96]=p3_3_o;f_q_o[111:104]=p2_3_o;f_q_o[119:112]=p1_3_o;f_q_o[127:120]=p0_3_o;
f_p_o[7 :0 ]=q3_3_o;f_p_o[15 : 8 ]=q2_3_o;f_p_o[23 :16 ]=q1_3_o;f_p_o[31 :24 ]=q0_3_o;
f_p_o[39 :32]=q3_2_o;f_p_o[47 : 40]=q2_2_o;f_p_o[55 :48 ]=q1_2_o;f_p_o[63 :56 ]=q0_2_o;
f_p_o[71 :64]=q3_1_o;f_p_o[79 : 72]=q2_1_o;f_p_o[87 :80 ]=q1_1_o;f_p_o[95 :88 ]=q0_1_o;
f_p_o[103:96]=q3_0_o;f_p_o[111:104]=q2_0_o;f_p_o[119:112]=q1_0_o;f_p_o[127:120]=q0_0_o;
end
default:begin f_q_o = 128'b0 ;f_p_o = 128'b0; end
endcase
end
endmodule
|
/*
* Copyright (c) 2015-2016 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Testbench for system top
*/
`include "common.vh"
`include "ocp_const.vh"
`ifndef TRACE_FILE
`define TRACE_FILE "trace.vcd"
`endif
module tb_sys_top();
localparam HCLK = 5;
localparam PCLK = 2*HCLK; /* Clock period */
reg clk;
reg nrst;
always
#HCLK clk = !clk;
initial
begin
/* Set tracing */
if(!$test$plusargs("NOTRACE"))
begin
$dumpfile(`TRACE_FILE);
$dumpvars(0, tb_sys_top);
end
clk = 1;
nrst = 0;
#(10*PCLK) nrst = 1;
/* #500 $finish; */
end
/* Instantiate system top */
sys_top sys(
.clk(clk),
.nrst(nrst)
);
endmodule /* tb_sys_top */
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 7
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_auto_us_df_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_7_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(1),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_FUNCTIONAL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s6s (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 10:58:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/system_vga_hessian_1_0_stub.v
// Design : system_vga_hessian_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_hessian,Vivado 2016.4" *)
module system_vga_hessian_1_0(clk_x16, active, rst, x_addr, y_addr, g_in,
hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]" */;
input clk_x16;
input active;
input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLRBN_PP_SYMBOL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_PP_SYMBOL_V
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Timing Adapter
// --------------------------------------------------------------------------------
// altera message_level level1
`timescale 1ns / 100ps
module lab3_master_0_timing_adt (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input [ 7: 0] in_data,
// Interface: out
output reg out_valid,
output reg [ 7: 0] out_data,
input out_ready
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 7: 0] in_payload;
reg [ 7: 0] out_payload;
reg [ 0: 0] ready;
reg in_ready;
// synthesis translate_off
always @(negedge in_ready) begin
$display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
end
// synthesis translate_on
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data};
{out_data} = out_payload;
end
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
ready[0] = out_ready;
out_valid = in_valid;
out_payload = in_payload;
in_ready = ready[0];
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:30:37 2016
/////////////////////////////////////////////////////////////
module add_sub_carry_out_W8_DW01_add_0 ( A, B, CI, SUM, CO );
input [8:0] A;
input [8:0] B;
output [8:0] SUM;
input CI;
output CO;
wire n3, n4;
wire [8:1] carry;
CMPR32X2TS U1_6 ( .A(A[6]), .B(B[6]), .C(carry[6]), .CO(carry[7]), .S(SUM[6]) );
CMPR32X2TS U1_5 ( .A(A[5]), .B(B[5]), .C(carry[5]), .CO(carry[6]), .S(SUM[5]) );
CMPR32X2TS U1_7 ( .A(A[7]), .B(B[7]), .C(carry[7]), .CO(SUM[8]), .S(SUM[7])
);
CMPR32X2TS U1_1 ( .A(A[1]), .B(B[1]), .C(carry[1]), .CO(carry[2]), .S(SUM[1]) );
CMPR32X2TS U1_4 ( .A(A[4]), .B(B[4]), .C(carry[4]), .CO(carry[5]), .S(SUM[4]) );
CMPR32X2TS U1_3 ( .A(A[3]), .B(B[3]), .C(carry[3]), .CO(carry[4]), .S(SUM[3]) );
CMPR32X2TS U1_2 ( .A(A[2]), .B(B[2]), .C(carry[2]), .CO(carry[3]), .S(SUM[2]) );
NOR2X1TS U1 ( .A(n3), .B(n4), .Y(carry[1]) );
INVX2TS U2 ( .A(B[0]), .Y(n4) );
INVX2TS U3 ( .A(A[0]), .Y(n3) );
XNOR2X1TS U4 ( .A(B[0]), .B(n3), .Y(SUM[0]) );
endmodule
module add_sub_carry_out_W8_DW01_sub_0 ( A, B, CI, DIFF, CO );
input [8:0] A;
input [8:0] B;
output [8:0] DIFF;
input CI;
output CO;
wire n12, n13, n14, n15, n16, n17, n18, n19, n20;
wire [9:0] carry;
CMPR32X2TS U2_7 ( .A(A[7]), .B(n13), .C(carry[7]), .CO(carry[8]), .S(DIFF[7]) );
CMPR32X2TS U2_6 ( .A(A[6]), .B(n14), .C(carry[6]), .CO(carry[7]), .S(DIFF[6]) );
CMPR32X2TS U2_5 ( .A(A[5]), .B(n15), .C(carry[5]), .CO(carry[6]), .S(DIFF[5]) );
CMPR32X2TS U2_1 ( .A(A[1]), .B(n19), .C(carry[1]), .CO(carry[2]), .S(DIFF[1]) );
CMPR32X2TS U2_4 ( .A(A[4]), .B(n16), .C(carry[4]), .CO(carry[5]), .S(DIFF[4]) );
CMPR32X2TS U2_3 ( .A(A[3]), .B(n17), .C(carry[3]), .CO(carry[4]), .S(DIFF[3]) );
CMPR32X2TS U2_2 ( .A(A[2]), .B(n18), .C(carry[2]), .CO(carry[3]), .S(DIFF[2]) );
INVX2TS U1 ( .A(carry[8]), .Y(DIFF[8]) );
INVX2TS U2 ( .A(B[2]), .Y(n18) );
INVX2TS U3 ( .A(B[3]), .Y(n17) );
INVX2TS U4 ( .A(B[4]), .Y(n16) );
NAND2X1TS U5 ( .A(B[0]), .B(n12), .Y(carry[1]) );
INVX2TS U6 ( .A(B[1]), .Y(n19) );
INVX2TS U7 ( .A(A[0]), .Y(n12) );
INVX2TS U8 ( .A(B[5]), .Y(n15) );
INVX2TS U9 ( .A(B[6]), .Y(n14) );
INVX2TS U10 ( .A(B[7]), .Y(n13) );
XNOR2X1TS U11 ( .A(n20), .B(A[0]), .Y(DIFF[0]) );
INVX2TS U12 ( .A(B[0]), .Y(n20) );
endmodule
module add_sub_carry_out_W8 ( op_mode, Data_A, Data_B, Data_S );
input [7:0] Data_A;
input [7:0] Data_B;
output [8:0] Data_S;
input op_mode;
wire N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17,
N18, N19, N20, n3;
add_sub_carry_out_W8_DW01_add_0 add_36 ( .A({1'b0, Data_A}), .B({1'b0,
Data_B}), .CI(1'b0), .SUM({N20, N19, N18, N17, N16, N15, N14, N13, N12}) );
add_sub_carry_out_W8_DW01_sub_0 sub_34 ( .A({1'b0, Data_A}), .B({1'b0,
Data_B}), .CI(1'b0), .DIFF({N11, N10, N9, N8, N7, N6, N5, N4, N3}) );
AO22X1TS U1 ( .A0(N19), .A1(n3), .B0(N10), .B1(op_mode), .Y(Data_S[7]) );
AO22X1TS U2 ( .A0(N9), .A1(op_mode), .B0(N18), .B1(n3), .Y(Data_S[6]) );
AO22X1TS U5 ( .A0(N8), .A1(op_mode), .B0(N17), .B1(n3), .Y(Data_S[5]) );
AO22X1TS U6 ( .A0(N7), .A1(op_mode), .B0(N16), .B1(n3), .Y(Data_S[4]) );
AO22X1TS U7 ( .A0(N20), .A1(n3), .B0(op_mode), .B1(N11), .Y(Data_S[8]) );
AO22X1TS U8 ( .A0(N5), .A1(op_mode), .B0(N14), .B1(n3), .Y(Data_S[2]) );
AO22X1TS U9 ( .A0(N6), .A1(op_mode), .B0(N15), .B1(n3), .Y(Data_S[3]) );
AO22X1TS U10 ( .A0(N4), .A1(op_mode), .B0(N13), .B1(n3), .Y(Data_S[1]) );
AO22X1TS U11 ( .A0(N3), .A1(op_mode), .B0(N12), .B1(n3), .Y(Data_S[0]) );
INVX2TS U12 ( .A(op_mode), .Y(n3) );
endmodule
module Greater_Comparator_W9 ( Data_A, Data_B, gthan );
input [8:0] Data_A;
input [8:0] Data_B;
output gthan;
wire N0, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35;
assign gthan = N0;
INVX2TS U1 ( .A(n19), .Y(n29) );
INVX2TS U2 ( .A(Data_A[6]), .Y(n32) );
INVX2TS U3 ( .A(Data_A[8]), .Y(n31) );
INVX2TS U4 ( .A(Data_A[4]), .Y(n34) );
INVX2TS U5 ( .A(Data_A[5]), .Y(n33) );
OAI211X1TS U6 ( .A0(n16), .A1(n17), .B0(n18), .C0(n19), .Y(n14) );
AOI22X1TS U7 ( .A0(n22), .A1(n27), .B0(Data_A[3]), .B1(n23), .Y(n16) );
AOI221X1TS U8 ( .A0(n20), .A1(Data_A[0]), .B0(Data_A[1]), .B1(n26), .C0(n21),
.Y(n17) );
OR2X2TS U9 ( .A(n23), .B(Data_A[3]), .Y(n22) );
INVX2TS U10 ( .A(Data_A[2]), .Y(n35) );
NAND2X1TS U11 ( .A(Data_A[7]), .B(n30), .Y(n19) );
OAI22X1TS U12 ( .A0(n11), .A1(n12), .B0(Data_B[8]), .B1(n31), .Y(N0) );
OAI2BB2XLTS U13 ( .B0(Data_A[7]), .B1(n30), .A0N(n31), .A1N(Data_B[8]), .Y(
n12) );
OAI22X1TS U14 ( .A0(n29), .A1(n13), .B0(n14), .B1(n15), .Y(n11) );
AOI21X1TS U15 ( .A0(n28), .A1(n32), .B0(n24), .Y(n13) );
OA21XLTS U16 ( .A0(n28), .A1(n32), .B0(Data_B[6]), .Y(n24) );
INVX2TS U17 ( .A(n25), .Y(n28) );
AOI32X1TS U18 ( .A0(Data_B[4]), .A1(n34), .A2(n18), .B0(n33), .B1(Data_B[5]),
.Y(n25) );
AOI2BB1X1TS U19 ( .A0N(n26), .A1N(Data_A[1]), .B0(Data_B[0]), .Y(n20) );
NAND2X1TS U20 ( .A(Data_B[2]), .B(n35), .Y(n23) );
OAI22X1TS U21 ( .A0(Data_B[6]), .A1(n32), .B0(Data_B[4]), .B1(n34), .Y(n15)
);
OAI2BB2XLTS U22 ( .B0(Data_B[2]), .B1(n35), .A0N(n27), .A1N(Data_A[3]), .Y(
n21) );
NAND2BX1TS U23 ( .AN(Data_B[5]), .B(Data_A[5]), .Y(n18) );
INVX2TS U24 ( .A(Data_B[7]), .Y(n30) );
INVX2TS U25 ( .A(Data_B[3]), .Y(n27) );
INVX2TS U26 ( .A(Data_B[1]), .Y(n26) );
endmodule
module Comparator_Less_W9 ( Data_A, Data_B, less );
input [8:0] Data_A;
input [8:0] Data_B;
output less;
wire N0, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35;
assign less = N0;
AOI22X1TS U1 ( .A0(n24), .A1(n30), .B0(Data_A[6]), .B1(n27), .Y(n13) );
OR2X2TS U2 ( .A(Data_A[6]), .B(n27), .Y(n24) );
INVX2TS U3 ( .A(n25), .Y(n27) );
AOI32X1TS U4 ( .A0(Data_A[4]), .A1(n28), .A2(n18), .B0(n29), .B1(Data_A[5]),
.Y(n25) );
INVX2TS U5 ( .A(Data_A[7]), .Y(n33) );
NAND2X1TS U6 ( .A(Data_A[2]), .B(n26), .Y(n22) );
INVX2TS U7 ( .A(Data_A[3]), .Y(n34) );
INVX2TS U8 ( .A(Data_A[1]), .Y(n35) );
OAI22X1TS U9 ( .A0(Data_A[6]), .A1(n30), .B0(Data_A[4]), .B1(n28), .Y(n15)
);
INVX2TS U10 ( .A(n19), .Y(n31) );
OAI22X1TS U11 ( .A0(n11), .A1(n12), .B0(Data_A[8]), .B1(n32), .Y(N0) );
OAI2BB2XLTS U12 ( .B0(Data_B[7]), .B1(n33), .A0N(n32), .A1N(Data_A[8]), .Y(
n12) );
OAI22X1TS U13 ( .A0(n31), .A1(n13), .B0(n14), .B1(n15), .Y(n11) );
OAI211X1TS U14 ( .A0(n16), .A1(n17), .B0(n18), .C0(n19), .Y(n14) );
AOI21X1TS U15 ( .A0(n22), .A1(n34), .B0(n23), .Y(n16) );
AOI221X1TS U16 ( .A0(n20), .A1(Data_B[0]), .B0(Data_B[1]), .B1(n35), .C0(n21), .Y(n17) );
OA21XLTS U17 ( .A0(n34), .A1(n22), .B0(Data_B[3]), .Y(n23) );
AOI2BB1X1TS U18 ( .A0N(n35), .A1N(Data_B[1]), .B0(Data_A[0]), .Y(n20) );
OAI2BB2XLTS U19 ( .B0(Data_A[2]), .B1(n26), .A0N(n34), .A1N(Data_B[3]), .Y(
n21) );
NAND2X1TS U20 ( .A(Data_B[7]), .B(n33), .Y(n19) );
NAND2BX1TS U21 ( .AN(Data_A[5]), .B(Data_B[5]), .Y(n18) );
INVX2TS U22 ( .A(Data_B[2]), .Y(n26) );
INVX2TS U23 ( .A(Data_B[6]), .Y(n30) );
INVX2TS U24 ( .A(Data_B[8]), .Y(n32) );
INVX2TS U25 ( .A(Data_B[4]), .Y(n28) );
INVX2TS U26 ( .A(Data_B[5]), .Y(n29) );
endmodule
module Comparators_W_Exp9 ( exp, overflow, underflow );
input [8:0] exp;
output overflow, underflow;
Greater_Comparator_W9 GTComparator ( .Data_A(exp), .Data_B({1'b0, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0}), .gthan(overflow) );
Comparator_Less_W9 LTComparator ( .Data_A(exp), .Data_B({1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}), .less(underflow) );
endmodule
module RegisterAdd_W8 ( clk, rst, load, D, Q );
input [7:0] D;
output [7:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n17,
n19, n20;
DFFRX2TS \Q_reg[7] ( .D(n17), .CK(clk), .RN(n20), .Q(Q[7]), .QN(n8) );
DFFRX2TS \Q_reg[6] ( .D(n15), .CK(clk), .RN(n20), .Q(Q[6]), .QN(n7) );
DFFRX2TS \Q_reg[5] ( .D(n14), .CK(clk), .RN(n20), .Q(Q[5]), .QN(n6) );
DFFRX2TS \Q_reg[4] ( .D(n13), .CK(clk), .RN(n20), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[3] ( .D(n12), .CK(clk), .RN(n20), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[2] ( .D(n11), .CK(clk), .RN(n20), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[1] ( .D(n10), .CK(clk), .RN(n20), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n9), .CK(clk), .RN(n20), .Q(Q[0]), .QN(n1) );
CLKBUFX2TS U2 ( .A(load), .Y(n19) );
OAI2BB2XLTS U3 ( .B0(n8), .B1(load), .A0N(D[7]), .A1N(load), .Y(n17) );
OAI2BB2XLTS U4 ( .B0(n5), .B1(n19), .A0N(D[4]), .A1N(load), .Y(n13) );
OAI2BB2XLTS U5 ( .B0(n6), .B1(n19), .A0N(D[5]), .A1N(load), .Y(n14) );
OAI2BB2XLTS U6 ( .B0(n7), .B1(n19), .A0N(D[6]), .A1N(load), .Y(n15) );
OAI2BB2XLTS U7 ( .B0(n1), .B1(n19), .A0N(load), .A1N(D[0]), .Y(n9) );
OAI2BB2XLTS U8 ( .B0(n2), .B1(n19), .A0N(D[1]), .A1N(load), .Y(n10) );
OAI2BB2XLTS U9 ( .B0(n3), .B1(n19), .A0N(D[2]), .A1N(load), .Y(n11) );
OAI2BB2XLTS U10 ( .B0(n4), .B1(n19), .A0N(D[3]), .A1N(load), .Y(n12) );
INVX2TS U11 ( .A(rst), .Y(n20) );
endmodule
module RegisterAdd_W1_3 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4, n6;
DFFRX2TS \Q_reg[0] ( .D(n3), .CK(clk), .RN(n6), .Q(Q[0]), .QN(n4) );
OAI2BB2XLTS U2 ( .B0(n4), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n6) );
endmodule
module RegisterAdd_W1_2 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4, n6;
DFFRX2TS \Q_reg[0] ( .D(n3), .CK(clk), .RN(n6), .Q(Q[0]), .QN(n4) );
OAI2BB2XLTS U2 ( .B0(n4), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n6) );
endmodule
module Exp_Operation ( clk, rst, load_a_i, load_b_i, Data_A_i, Data_B_i,
Add_Subt_i, Data_Result_o, Overflow_flag_o, Underflow_flag_o );
input [7:0] Data_A_i;
input [7:0] Data_B_i;
output [7:0] Data_Result_o;
input clk, rst, load_a_i, load_b_i, Add_Subt_i;
output Overflow_flag_o, Underflow_flag_o;
wire Overflow_flag, Underflow_flag, n1, n2;
wire [8:0] Data_S;
add_sub_carry_out_W8 exp_add_subt ( .op_mode(Add_Subt_i), .Data_A(Data_A_i),
.Data_B(Data_B_i), .Data_S(Data_S) );
Comparators_W_Exp9 array_comparators ( .exp(Data_S), .overflow(Overflow_flag), .underflow(Underflow_flag) );
RegisterAdd_W8 exp_result ( .clk(clk), .rst(rst), .load(n2), .D(Data_S[7:0]),
.Q(Data_Result_o) );
RegisterAdd_W1_3 Overflow ( .clk(clk), .rst(rst), .load(load_a_i), .D(
Overflow_flag), .Q(Overflow_flag_o) );
RegisterAdd_W1_2 Underflow ( .clk(clk), .rst(rst), .load(load_b_i), .D(
Underflow_flag), .Q(Underflow_flag_o) );
INVX2TS U1 ( .A(load_a_i), .Y(n1) );
INVX2TS U2 ( .A(n1), .Y(n2) );
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_65_256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_65_256 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [64:0] data;
input rdreq;
input wrreq;
output empty;
output [64:0] q;
wire sub_wire0;
wire [64:0] sub_wire1;
wire empty = sub_wire0;
wire [64:0] q = sub_wire1[64:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 65,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "65"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "65"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "65"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 65 0 INPUT NODEFVAL "data[64..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 65 0 OUTPUT NODEFVAL "q[64..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 65 0 data 0 0 65 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 65 0 @q 0 0 65 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/***********************************************************
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: byte_lane.v,v 1.9.6.3 2011/05/30 10:45:53 pboya Exp $
// $Author: pboya $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable single 10 or 12 bit byte lane.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module byte_lane #(
// these are used to scale the index into phaser,calib,scan,mc vectors
// to access fields used in this instance
parameter ABCD = "A", // A,B,C, or D
parameter PO_DATA_CTL = "FALSE",
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b0000_0000_0000,
parameter DIFFERENTIAL_DQS = "TRUE",
parameter GENERATE_DDR_CK = "B",
parameter NUM_DDR_CK = 1,
parameter RCLK_SELECT_LANE = "B",
parameter MC_DIVIDE = 4,
//OUT_FIFO
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_ARRAY_MODE = "UNDECLARED",
parameter OF_OUTPUT_DISABLE = "TRUE",
parameter OF_SYNCHRONOUS_MODE = "TRUE",
//IN_FIFO
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_ARRAY_MODE = "UNDECLARED",
parameter IF_SYNCHRONOUS_MODE = "TRUE",
//PHASER_IN
parameter PI_BURST_MODE = "TRUE",
parameter PI_CLKOUT_DIV = 2,
parameter PI_FREQ_REF_DIV = "NONE",
parameter PI_FINE_DELAY = 1,
parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter PI_SYNC_IN_DIV_RST = "FALSE",
//PHASER_OUT
parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2,
parameter PO_FINE_DELAY = 0,
parameter PO_COARSE_BYPASS = "FALSE",
parameter PO_COARSE_DELAY = 0,
parameter PO_OCLK_DELAY = 0,
parameter PO_OCLKDELAY_INV = "TRUE",
parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PO_SYNC_IN_DIV_RST = "FALSE",
// OSERDES
parameter OSERDES_DATA_RATE = "UNDECLARED",
parameter OSERDES_DATA_WIDTH = "UNDECLARED",
//IDELAY
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
parameter real TCK = 0.00,
// local constants, do not pass in from above
parameter BUS_WIDTH = 12,
parameter MSB_BURST_PEND_PO = 3,
parameter MSB_BURST_PEND_PI = 7,
parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI+ 8,
parameter MSB_RANK_SEL_O = MSB_RANK_SEL_I + 8,
parameter MSB_DIV_RST = MSB_RANK_SEL_O + 1,
parameter MSB_PHASE_SELECT = MSB_DIV_RST + 1,
parameter MSB_BURST_PI = MSB_PHASE_SELECT + 4,
parameter PHASER_CTL_BUS_WIDTH = MSB_BURST_PI + 1,
parameter LP_DDR_CK_WIDTH = 2
)(
input rst,
input phy_clk,
input freq_refclk,
input mem_refclk,
input idelayctrl_refclk,
input sync_pulse,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input [9:0] mem_dq_in,
output mem_dqs_out,
output mem_dqs_ts,
input mem_dqs_in,
output [NUM_DDR_CK*LP_DDR_CK_WIDTH-1:0] ddr_ck_out,
output rclk,
output if_a_empty,
output if_empty,
output if_a_full,
output if_full,
output of_a_empty,
output of_empty,
output of_a_full,
output of_full,
output [79:0] phy_din,
input [79:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,
input idelay_inc,
input idelay_ce,
input idelay_ld,
output po_coarse_overflow,
output po_fine_overflow,
output [8:0] po_counter_read_val,
input po_fine_enable,
input po_coarse_enable,
input [1:0] po_en_calib,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input [1:0] pi_en_calib,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output wire pi_iserdes_rst,
output pi_phase_locked,
output pi_fine_overflow,
output [5:0] pi_counter_read_val,
output wire pi_dqs_found,
output dqs_out_of_range
);
localparam PHASER_INDEX =
(ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0));
localparam L_OF_ARRAY_MODE =
(OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE :
((PO_DATA_CTL == "FALSE" ) || (MC_DIVIDE == 2)) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4";
localparam L_IF_ARRAY_MODE =
(IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE :
(MC_DIVIDE == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8" ;
localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" ) && (MC_DIVIDE == 4) ? "SDR" : "DDR") ;
localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4;
localparam real FREQ_REF_PER_NS = TCK > 2500.0 ? TCK/2/1000.0 : TCK/1000.0;
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [3:0] of_q9;
wire [3:0] of_q8;
wire [3:0] of_q7;
wire [7:0] of_q6;
wire [7:0] of_q5;
wire [3:0] of_q4;
wire [3:0] of_q3;
wire [3:0] of_q2;
wire [3:0] of_q1;
wire [3:0] of_q0;
wire [7:0] of_d9;
wire [7:0] of_d8;
wire [7:0] of_d7;
wire [7:0] of_d6;
wire [7:0] of_d5;
wire [7:0] of_d4;
wire [7:0] of_d3;
wire [7:0] of_d2;
wire [7:0] of_d1;
wire [7:0] of_d0;
wire [7:0] if_q9;
wire [7:0] if_q8;
wire [7:0] if_q7;
wire [7:0] if_q6;
wire [7:0] if_q5;
wire [7:0] if_q4;
wire [7:0] if_q3;
wire [7:0] if_q2;
wire [7:0] if_q1;
wire [7:0] if_q0;
wire [3:0] if_d9;
wire [3:0] if_d8;
wire [3:0] if_d7;
wire [3:0] if_d6;
wire [3:0] if_d5;
wire [3:0] if_d4;
wire [3:0] if_d3;
wire [3:0] if_d2;
wire [3:0] if_d1;
wire [3:0] if_d0;
wire [3:0] dummy_i5;
wire [3:0] dummy_i6;
wire [48-1:0] of_dqbus;
wire [10*4-1:0] iserdes_dout;
wire iserdes_clk;
wire iserdes_clkdiv;
wire ififo_wr_enable;
wire phy_rd_en_;
wire dqs_to_phaser;
wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en;
wire if_empty_;
wire if_a_empty_;
wire if_full_;
wire if_a_full_;
wire of_full_;
wire of_a_full_;
wire oserdes_rst;
wire empty_post_fifo;
reg if_empty_r;
wire [79:0] rd_data;
reg [79:0] rd_data_r;
wire reset_dqs_find = rst | pi_rst_dqs_find;
wire ififo_rst = pi_rst_dqs_find | pi_iserdes_rst;
wire ofifo_rst = (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | oserdes_rst;
// IN_FIFO EMPTY->RDEN TIMING FIX:
// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO
// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty
assign #(25) phy_rd_en_ = 1'b1;
generate
if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null
assign if_empty = 0;
assign if_a_empty = 0;
assign if_full = 0;
assign if_a_full = 0;
end
else begin : if_empty_gen
assign if_empty = empty_post_fifo; // Use output of timing fix logic
assign if_a_empty = if_a_empty_;
assign if_full = if_full_;
assign if_a_full = if_a_full_;
end
endgenerate
generate
if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48
assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign phy_din = 80'h0;
end
else begin : dq_gen_40
assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
// IN_FIFO EMPTY->RDEN TIMING FIX:
assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
always @(posedge phy_clk) begin
rd_data_r <= #(025) rd_data;
if_empty_r <= #(025) if_empty_;
end
if_post_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (2), // depth - account for up to 2 cycles of skew
.WIDTH (80) // width
)
if_post_fifo
(
.clk (phy_clk),
.rst (ififo_rst),
.empty_in (if_empty_r),
.rd_en_in (phy_rd_en),
.d_in (rd_data_r),
.empty_out (empty_post_fifo),
.d_out (phy_din)
);
end
endgenerate
assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;
wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);
wire [1:0] rank_sel_o = ((phaser_ctl_bus[MSB_RANK_SEL_O :MSB_RANK_SEL_O -7] >> (PHASER_INDEX << 1)) & 2'b11);
`ifdef FUJI_PHY_BLH
B_PHASER_IN_PHY #(
`else
PHASER_IN_PHY #(
`endif
.BURST_MODE ( PI_BURST_MODE),
.CLKOUT_DIV ( PI_CLKOUT_DIV),
.FINE_DELAY ( PI_FINE_DELAY),
.FREQ_REF_DIV ( PI_FREQ_REF_DIV),
.OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( FREQ_REF_PER_NS)
) phaser_in (
.DQSFOUND (pi_dqs_found),
.DQSOUTOFRANGE (dqs_out_of_range),
.FINEOVERFLOW (pi_fine_overflow),
.PHASELOCKED (pi_phase_locked),
.ISERDESRST (pi_iserdes_rst),
.ICLKDIV (iserdes_clkdiv),
.ICLK (iserdes_clk),
.COUNTERREADVAL (pi_counter_read_val),
.RCLK (rclk),
.WRENABLE (ififo_wr_enable),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
.ENCALIBPHY (pi_en_calib),
.FINEENABLE (pi_fine_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (rank_sel_i),
.PHASEREFCLK (dqs_to_phaser),
.RSTDQSFIND (pi_rst_dqs_find),
.RST (rst),
.FINEINC (pi_fine_inc),
.COUNTERLOADEN (pi_counter_load_en),
.COUNTERREADEN (pi_counter_read_en),
.COUNTERLOADVAL (pi_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
wire #0 phase_ref = freq_refclk;
wire oserdes_clk;
`ifdef FUJI_PHY_BLH
B_PHASER_OUT_PHY #(
`else
PHASER_OUT_PHY #(
`endif
.CLKOUT_DIV ( PO_CLKOUT_DIV),
.DATA_CTL_N ( PO_DATA_CTL ),
.FINE_DELAY ( PO_FINE_DELAY),
.COARSE_BYPASS ( PO_COARSE_BYPASS ),
.COARSE_DELAY ( PO_COARSE_DELAY),
.OCLK_DELAY ( PO_OCLK_DELAY),
.OCLKDELAY_INV ( PO_OCLKDELAY_INV),
.OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( FREQ_REF_PER_NS)
) phaser_out (
.COARSEOVERFLOW (po_coarse_overflow),
.CTSBUS (oserdes_dqs_ts),
.DQSBUS (oserdes_dqs),
.DTSBUS (oserdes_dq_ts),
.FINEOVERFLOW (po_fine_overflow),
.OCLKDIV (oserdes_clkdiv),
.OCLK (oserdes_clk),
.OCLKDELAYED (oserdes_clk_delayed),
.COUNTERREADVAL (po_counter_read_val),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),
.ENCALIBPHY (po_en_calib),
.RDENABLE (po_rd_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.PHASEREFCLK (/*phase_ref*/),
.RST (rst),
.OSERDESRST (oserdes_rst),
.COARSEENABLE (po_coarse_enable),
.FINEENABLE (po_fine_enable),
.COARSEINC (po_coarse_inc),
.FINEINC (po_fine_inc),
.SELFINEOCLKDELAY (po_sel_fine_oclk_delay),
.COUNTERLOADEN (po_counter_load_en),
.COUNTERREADEN (po_counter_read_en),
.COUNTERLOADVAL (po_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
// Model skew going to individual IN_FIFOs - enabled only if
// TEST_MODE is define
reg skewd_ififo_wr_enable;
reg skewd_phy_rd_en_;
reg [3:0] skewd_if_d0;
reg [3:0] skewd_if_d1;
reg [3:0] skewd_if_d2;
reg [3:0] skewd_if_d3;
reg [3:0] skewd_if_d4;
reg [7:0] skewd_if_d5;
reg [7:0] skewd_if_d6;
reg [3:0] skewd_if_d7;
reg [3:0] skewd_if_d8;
reg [3:0] skewd_if_d9;
reg skewd_iserdes_clkdiv;
reg skewd_phy_clk;
`ifdef TEST_MODE
int rd_random_num;
int wr_random_num;
parameter CLK_SKEW_MIN = top.CLK_SKEW_MIN;
parameter CLK_SKEW_MAX = top.CLK_SKEW_MAX;
parameter ENABLE_SKEW = top.ENABLE_SKEW ;
parameter DATA_SKEW = top.DATA_SKEW ;
initial
begin
//$display("VALUE OF CLK_SKEW_MIN = %d",top.CLK_SKEW_MIN);
//$display("VALUE OF CLK_SKEW_MAX = %d",top.CLK_SKEW_MAX);
//$display("VALUE OF ENABLE_SKEW = %d",top.ENABLE_SKEW);
//$display("VALUE OF DATA_SKEW = %d",top.DATA_SKEW);
wr_random_num = CLK_SKEW_MIN + {$random} % (CLK_SKEW_MAX - CLK_SKEW_MIN);
rd_random_num = CLK_SKEW_MIN + {$random} % (CLK_SKEW_MAX - CLK_SKEW_MIN);
$display(" %m value for wr_random_num = %d ::::::: value for rd_random_num",wr_random_num,rd_random_num);
end
always @(skewd_iserdes_clkdiv)
begin
#(ENABLE_SKEW) skewd_ififo_wr_enable = ififo_wr_enable;
end
always @(skewd_iserdes_clkdiv)
begin
#(DATA_SKEW) skewd_if_d0 = if_d0;
skewd_if_d1 = if_d1;
skewd_if_d2 = if_d2;
skewd_if_d3 = if_d3;
skewd_if_d4 = if_d4;
skewd_if_d5 = {dummy_i5,if_d5};
skewd_if_d6 = {dummy_i6,if_d6};
skewd_if_d7 = if_d7;
skewd_if_d8 = if_d8;
skewd_if_d9 = if_d9;
end
always @(skewd_phy_clk)
begin
# (ENABLE_SKEW) skewd_phy_rd_en_ = phy_rd_en_;
end
always @(iserdes_clkdiv)
begin
skewd_iserdes_clkdiv <= #(wr_random_num) iserdes_clkdiv;
end
always @(phy_clk)
begin
skewd_phy_clk <= #(rd_random_num) phy_clk;
end
`else
always @(*)
begin
skewd_iserdes_clkdiv = iserdes_clkdiv;
skewd_phy_clk = phy_clk ;
skewd_phy_rd_en_ = phy_rd_en_ ;
skewd_if_d0 = if_d0;
skewd_if_d1 = if_d1;
skewd_if_d2 = if_d2;
skewd_if_d3 = if_d3;
skewd_if_d4 = if_d4;
skewd_if_d5 = {dummy_i5,if_d5};
skewd_if_d6 = {dummy_i6,if_d6};
skewd_if_d7 = if_d7;
skewd_if_d8 = if_d8;
skewd_if_d9 = if_d9;
skewd_ififo_wr_enable = ififo_wr_enable;
end
`endif
`ifdef FUJI_PHY_BLH
B_IN_FIFO #(
`else
IN_FIFO #(
`endif
.ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
.ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
.ARRAY_MODE ( L_IF_ARRAY_MODE),
.SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
) in_fifo (
.ALMOSTEMPTY (if_a_empty_),
.ALMOSTFULL (if_a_full_),
.EMPTY (if_empty_),
.FULL (if_full_),
.Q0 (if_q0),
.Q1 (if_q1),
.Q2 (if_q2),
.Q3 (if_q3),
.Q4 (if_q4),
.Q5 (if_q5),
.Q6 (if_q6),
.Q7 (if_q7),
.Q8 (if_q8),
.Q9 (if_q9),
//===
.D0 (skewd_if_d0),
.D1 (skewd_if_d1),
.D2 (skewd_if_d2),
.D3 (skewd_if_d3),
.D4 (skewd_if_d4),
.D5 (skewd_if_d5),
.D6 (skewd_if_d6),
.D7 (skewd_if_d7),
.D8 (skewd_if_d8),
.D9 (skewd_if_d9),
.RDCLK (skewd_phy_clk),
.RDEN (skewd_phy_rd_en_),
.RESET (ififo_rst),
.WRCLK (skewd_iserdes_clkdiv),
.WREN (skewd_ififo_wr_enable)
);
//**********************************************************************
// Extend depth of OUT_FIFO to provide additional buffering to avoid
// the OUT_FIFO ever going full or empty due to write-read clock drift
//**********************************************************************
wire of_wren_tmp;
wire [79:0] pre_fifo_dout;
wire pre_fifo_full;
wire pre_fifo_rden;
wire rst_n;
of_pre_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (8), // depth - set to 8 initially, reduce later as appropriate
.WIDTH (80) // width
)
of_pre_fifo
(
.clk (phy_clk),
.rst (rst),
.full_in (of_full),
.wr_en_in (phy_wr_en),
.d_in (phy_dout),
.wr_en_out (of_wren_tmp),
.d_out (pre_fifo_dout)
);
assign {of_d9, of_d8, of_d7, of_d6, of_d5,
of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout;
`ifdef FUJI_PHY_BLH
B_OUT_FIFO #(
`else
OUT_FIFO #(
`endif
.ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.ARRAY_MODE (L_OF_ARRAY_MODE),
.OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
.SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)
) out_fifo (
.ALMOSTEMPTY (of_a_empty),
.ALMOSTFULL (of_a_full),
.EMPTY (of_empty),
.FULL (of_full),
.Q0 (of_q0),
.Q1 (of_q1),
.Q2 (of_q2),
.Q3 (of_q3),
.Q4 (of_q4),
.Q5 (of_q5),
.Q6 (of_q6),
.Q7 (of_q7),
.Q8 (of_q8),
.Q9 (of_q9),
.D0 (of_d0),
.D1 (of_d1),
.D2 (of_d2),
.D3 (of_d3),
.D4 (of_d4),
.D5 (of_d5),
.D6 (of_d6),
.D7 (of_d7),
.D8 (of_d8),
.D9 (of_d9),
.RDCLK (oserdes_clkdiv),
.RDEN (po_rd_enable),
.RESET (ofifo_rst),
.WRCLK (phy_clk),
.WREN (of_wren_tmp)
);
byte_group_io #
(
.PO_DATA_CTL (PO_DATA_CTL),
.BITLANES (BITLANES),
.BITLANES_OUTONLY (BITLANES_OUTONLY),
.OSERDES_DATA_RATE (L_OSERDES_DATA_RATE),
.OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH),
.DIFFERENTIAL_DQS (DIFFERENTIAL_DQS),
.IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
byte_group_io
(
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_in (mem_dqs_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.rst (rst),
.oserdes_rst (oserdes_rst),
.iserdes_rst (pi_iserdes_rst ),
.iserdes_dout (iserdes_dout),
.dqs_to_phaser (dqs_to_phaser),
.phy_clk (phy_clk),
.iserdes_clk (iserdes_clk),
.iserdes_clkb (!iserdes_clk),
.iserdes_clkdiv (iserdes_clkdiv),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.idelayctrl_refclk (idelayctrl_refclk),
.oserdes_clk (oserdes_clk),
.oserdes_clk_delayed (oserdes_clk_delayed),
.oserdes_clkdiv (oserdes_clkdiv),
.oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),
.oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),
.oserdes_dq (of_dqbus),
.oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]})
);
genvar i;
generate
if ( NUM_DDR_CK )
for ( i = 0; i != NUM_DDR_CK; i = i +1)
if ( PO_DATA_CTL== "FALSE" && GENERATE_DDR_CK == ABCD) begin : ddr_ck_gen
wire ddr_ck_out_q;
ODDR ddr_ck (
.C (oserdes_clk),
.R (oserdes_rst),
.S (),
.D1 (1'b0),
.D2 (1'b1),
.CE (1'b1),
.Q (ddr_ck_out_q)
);
OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q), .O(ddr_ck_out[i]), .OB(ddr_ck_out[NUM_DDR_CK+i]));
end // ddr_ck_gen
else begin : ddr_ck_null
assign ddr_ck_out[i] = 1'b0;
assign ddr_ck_out[NUM_DDR_CK + i] = 1'b0;
end
endgenerate
endmodule // byte_lane
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFRTN_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_BLACKBOX_V
|
`timescale 1 ns/100 ps
// Version: 8.5 8.5.0.34
module dmem(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
input [7:0] WD;
output [7:0] RD;
input WEN, REN;
input [9:0] WADDR, RADDR;
input RWCLK, RESET;
wire VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
RAM4K9 dmem_R0C1(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), .ADDRA6(
WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(
WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(
WADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(RADDR[9])
, .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]),
.ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]),
.ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]),
.DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(WD[7]), .DINA2(WD[6]), .DINA1(WD[5]),
.DINA0(WD[4]), .DINB8(GND), .DINB7(GND), .DINB6(GND),
.DINB5(GND), .DINB4(GND), .DINB3(GND), .DINB2(GND),
.DINB1(GND), .DINB0(GND), .WIDTHA0(GND), .WIDTHA1(VCC),
.WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(VCC),
.WMODEA(GND), .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(
GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(
RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(),
.DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(), .DOUTA0(),
.DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(),
.DOUTB3(RD[7]), .DOUTB2(RD[6]), .DOUTB1(RD[5]), .DOUTB0(
RD[4]));
RAM4K9 dmem_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), .ADDRA6(
WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(
WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(
WADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(RADDR[9])
, .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]),
.ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]),
.ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]),
.DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(WD[3]), .DINA2(WD[2]), .DINA1(WD[1]),
.DINA0(WD[0]), .DINB8(GND), .DINB7(GND), .DINB6(GND),
.DINB5(GND), .DINB4(GND), .DINB3(GND), .DINB2(GND),
.DINB1(GND), .DINB0(GND), .WIDTHA0(GND), .WIDTHA1(VCC),
.WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(VCC),
.WMODEA(GND), .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(
GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(
RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(),
.DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(), .DOUTA0(),
.DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(),
.DOUTB3(RD[3]), .DOUTB2(RD[2]), .DOUTB1(RD[1]), .DOUTB0(
RD[0]));
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:05:03 03/23/2016
// Design Name: MAIN
// Module Name: Y:/TEOCOA/EXP2/TEST_MAIN.v
// Project Name: EXP2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MAIN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TEST_MAIN;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg C0;
// Outputs
wire [3:0] F;
wire C4;
// Instantiate the Unit Under Test (UUT)
MAIN uut (
.A(A),
.B(B),
.C0(C0),
.F(F),
.C4(C4)
);
initial begin
// Initialize Inputs
A = 4'b0000;
B = 4'b0000;
C0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 4'b0001;
B = 4'b0000;
C0 = 0;
// Wait 100 ns for global reset to finish
#100;
A = 4'b0001;
B = 4'b0001;
C0 = 0;
// Wait 100 ns for global reset to finish
#100;
A = 4'b0111;
B = 4'b0011;
C0 = 0;
// Wait 100 ns for global reset to finish
#100;
A = 4'b0111;
B = 4'b0011;
C0 = 1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_SYMBOL_V
`define SKY130_FD_SC_LP__A32OI_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_SYMBOL_V
|
//-----------------------------------------------------------------------------
// Title : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper Example Design
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_3_example_design.v
// Version : 1.3
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Description: This is the Example Design wrapper for the Virtex-6
// Embedded Tri-Mode Ethernet MAC. It is intended that this
// example design can be quickly adapted and downloaded onto an
// FPGA to provide a hardware test environment.
//
// The Example Design wrapper:
//
// * instantiates the EMAC LocalLink-level wrapper (the EMAC
// block-level wrapper with the RX and TX FIFOs and a
// LocalLink interface);
//
// * instantiates a simple example design which provides an
// address swap and loopback function at the user interface;
//
// * instantiates the fundamental clocking resources required
// by the core;
//
// Please refer to the Datasheet, Getting Started Guide, and
// the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
// further information.
//
// ---------------------------------------------------------------------
// |EXAMPLE DESIGN WRAPPER |
// | --------------------------------------------------------|
// | |LOCALLINK-LEVEL WRAPPER |
// | | -----------------------------------------|
// | | |BLOCK-LEVEL WRAPPER |
// | | | --------------------- |
// | -------- | ---------- | | INSTANCE-LEVEL | |
// | | | | | | | | WRAPPER | --------- |
// | | |->|->| |->|--->| Tx Tx |->| |--->|
// | | | | | | | | client PHY | | | |
// | | ADDR | | | LOCAL- | | | I/F I/F | | | |
// | | SWAP | | | LINK | | | | | PHY | |
// | | | | | FIFO | | | | | I/F | |
// | | | | | | | | | | | |
// | | | | | | | | Rx Rx | | | |
// | | | | | | | | client PHY | | | |
// | | |<-|<-| |<-|<---| I/F I/F |<-| |<---|
// | | | | | | | | | --------- |
// | -------- | ---------- | --------------------- |
// | | -----------------------------------------|
// | --------------------------------------------------------|
// ---------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Module declaration for the example design
//-----------------------------------------------------------------------------
module v6_emac_v1_3_example_design
(
// Client receiver interface
EMACCLIENTRXDVLD,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client transmitter interface
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC control interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Clock signal
GTX_CLK,
// GMII interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// MDIO interface
MDC,
MDIO_I,
MDIO_O,
MDIO_T,
// Host interface
HOSTCLK,
HOSTOPCODE,
HOSTREQ,
HOSTMIIMSEL,
HOSTADDR,
HOSTWRDATA,
HOSTMIIMRDY,
HOSTRDDATA,
// Reference clock for IODELAYs
REFCLK,
// Asynchronous reset
RESET
);
//-----------------------------------------------------------------------------
// Port declarations
//-----------------------------------------------------------------------------
// Client receiver interface
output EMACCLIENTRXDVLD;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client transmitter interface
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC control interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Clock signal
input GTX_CLK;
// GMII interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// MDIO interface
output MDC;
input MDIO_I;
output MDIO_O;
output MDIO_T;
// Host interface
input HOSTCLK;
input [1:0] HOSTOPCODE;
input HOSTREQ;
input HOSTMIIMSEL;
input [9:0] HOSTADDR;
input [31:0] HOSTWRDATA;
output HOSTMIIMRDY;
output [31:0] HOSTRDDATA;
// Reference clock for IODELAYs
input REFCLK;
// Asynchronous reset
input RESET;
//-----------------------------------------------------------------------------
// Wire and register declarations
//-----------------------------------------------------------------------------
// Global asynchronous reset
wire reset_i;
// LocalLink interface clocking signal
wire ll_clk_i;
// Address swap transmitter connections
wire [7:0] tx_ll_data_i;
wire tx_ll_sof_n_i;
wire tx_ll_eof_n_i;
wire tx_ll_src_rdy_n_i;
wire tx_ll_dst_rdy_n_i;
// Address swap receiver connections
wire [7:0] rx_ll_data_i;
wire rx_ll_sof_n_i;
wire rx_ll_eof_n_i;
wire rx_ll_src_rdy_n_i;
wire rx_ll_dst_rdy_n_i;
// Synchronous reset registers in the LocalLink clock domain
(* ASYNC_REG = "TRUE" *)
reg [5:0] ll_pre_reset_i;
reg ll_reset_i;
// Reference clock for IODELAYs
wire refclk_ibufg_i;
wire refclk_bufg_i;
// Host interface clock
(* BUFFER_TYPE = "NONE" *)
wire host_clk_i;
// GMII input clocks to wrappers
(* KEEP = "TRUE" *)
wire tx_clk;
wire rx_clk_i;
wire gmii_rx_clk_bufio;
wire gmii_rx_clk_delay;
// IDELAY controller
reg [12:0] idelayctrl_reset_r;
wire idelayctrl_reset_i;
// GTX reference clock
wire gtx_clk_i;
//-----------------------------------------------------------------------------
// Main body of code
//-----------------------------------------------------------------------------
// Reset input buffer
IBUF reset_ibuf (
.I (RESET),
.O (reset_i)
);
//------------------------------------------------------------------------
// Clock skew management: use IDELAY on GMII_RX_CLK to move
// the clock into proper alignment with the data
//------------------------------------------------------------------------
// Instantiate IDELAYCTRL for the IDELAY in Fixed Tap Delay Mode
(* SYN_NOPRUNE = "TRUE" *)
IDELAYCTRL dlyctrl (
.RDY (),
.REFCLK (refclk_bufg_i),
.RST (idelayctrl_reset_i)
);
// Assert the proper reset pulse for the IDELAYCTRL
always @(posedge refclk_bufg_i, posedge reset_i)
begin
if (reset_i == 1'b1)
begin
idelayctrl_reset_r[0] <= 1'b0;
idelayctrl_reset_r[12:1] <= 12'b111111111111;
end
else
begin
idelayctrl_reset_r[0] <= 1'b0;
idelayctrl_reset_r[12:1] <= idelayctrl_reset_r[11:0];
end
end
assign idelayctrl_reset_i = idelayctrl_reset_r[12];
// Please modify the IDELAY_VALUE to suit your design.
// The IDELAY_VALUE set here is tuned to this example design.
// For more information on IDELAYCTRL and IODELAY, please
// refer to the Virtex-6 User Guide.
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.DELAY_SRC ("I"),
.SIGNAL_PATTERN ("CLOCK"),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
gmii_rxc_delay (
.IDATAIN (GMII_RX_CLK),
.ODATAIN (1'b0),
.DATAOUT (gmii_rx_clk_delay),
.DATAIN (1'b0),
.C (1'b0),
.T (1'b0),
.CE (1'b0),
.INC (1'b0),
.RST (1'b0)
);
// Globally-buffer the GTX reference clock, used to clock
// the transmit-side functions of the EMAC wrappers
// (tx_clk can be shared between multiple EMAC instances, including
// multiple instantiations of the EMAC wrappers)
BUFG bufg_tx (
.I (gtx_clk_i),
.O (tx_clk)
);
// Use a low-skew BUFIO on the delayed RX_CLK, which will be used in the
// GMII phyical interface block to capture incoming data and control.
BUFIO bufio_rx (
.I (gmii_rx_clk_delay),
.O (gmii_rx_clk_bufio)
);
// Regionally-buffer the receive-side GMII physical interface clock
// for use with receive-side functions of the EMAC
BUFR bufr_rx (
.I (gmii_rx_clk_delay),
.O (rx_clk_i),
.CE (1'b1),
.CLR (1'b0)
);
// Clock the LocalLink interface with the globally-buffered
// GTX reference clock
assign ll_clk_i = tx_clk;
//------------------------------------------------------------------------
// Instantiate the LocalLink-level EMAC wrapper (v6_emac_v1_3_locallink.v)
//------------------------------------------------------------------------
v6_emac_v1_3_locallink v6_emac_v1_3_locallink_inst
(
// TX clock output
.TX_CLK_OUT (),
// TX Clock input from BUFG
.TX_CLK (tx_clk),
// LocalLink receiver interface
.RX_LL_CLOCK (ll_clk_i),
.RX_LL_RESET (ll_reset_i),
.RX_LL_DATA (rx_ll_data_i),
.RX_LL_SOF_N (rx_ll_sof_n_i),
.RX_LL_EOF_N (rx_ll_eof_n_i),
.RX_LL_SRC_RDY_N (rx_ll_src_rdy_n_i),
.RX_LL_DST_RDY_N (rx_ll_dst_rdy_n_i),
.RX_LL_FIFO_STATUS (),
// Client receiver signals
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
// LocalLink transmitter interface
.TX_LL_CLOCK (ll_clk_i),
.TX_LL_RESET (ll_reset_i),
.TX_LL_DATA (tx_ll_data_i),
.TX_LL_SOF_N (tx_ll_sof_n_i),
.TX_LL_EOF_N (tx_ll_eof_n_i),
.TX_LL_SRC_RDY_N (tx_ll_src_rdy_n_i),
.TX_LL_DST_RDY_N (tx_ll_dst_rdy_n_i),
// Client transmitter signals
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
// MAC control interface
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
// Receive-side PHY clock on regional buffer, to EMAC
.PHY_RX_CLK (rx_clk_i),
// Reference clock (unused)
.GTX_CLK (1'b0),
// GMII interface
.GMII_TXD (GMII_TXD),
.GMII_TX_EN (GMII_TX_EN),
.GMII_TX_ER (GMII_TX_ER),
.GMII_TX_CLK (GMII_TX_CLK),
.GMII_RXD (GMII_RXD),
.GMII_RX_DV (GMII_RX_DV),
.GMII_RX_ER (GMII_RX_ER),
.GMII_RX_CLK (gmii_rx_clk_bufio),
// MDIO interface
.MDC (MDC),
.MDIO_I (MDIO_I),
.MDIO_O (MDIO_O),
.MDIO_T (MDIO_T),
// Host interface
.HOSTCLK (host_clk_i),
.HOSTOPCODE (HOSTOPCODE),
.HOSTREQ (HOSTREQ),
.HOSTMIIMSEL (HOSTMIIMSEL),
.HOSTADDR (HOSTADDR),
.HOSTWRDATA (HOSTWRDATA),
.HOSTMIIMRDY (HOSTMIIMRDY),
.HOSTRDDATA (HOSTRDDATA),
// Asynchronous reset
.RESET (reset_i)
);
//-------------------------------------------------------------------
// Instatiate the address swapping module
//-------------------------------------------------------------------
address_swap_module_8 client_side_asm (
.rx_ll_clock (ll_clk_i),
.rx_ll_reset (ll_reset_i),
.rx_ll_data_in (rx_ll_data_i),
.rx_ll_sof_in_n (rx_ll_sof_n_i),
.rx_ll_eof_in_n (rx_ll_eof_n_i),
.rx_ll_src_rdy_in_n (rx_ll_src_rdy_n_i),
.rx_ll_data_out (tx_ll_data_i),
.rx_ll_sof_out_n (tx_ll_sof_n_i),
.rx_ll_eof_out_n (tx_ll_eof_n_i),
.rx_ll_src_rdy_out_n (tx_ll_src_rdy_n_i),
.rx_ll_dst_rdy_in_n (tx_ll_dst_rdy_n_i)
);
assign rx_ll_dst_rdy_n_i = tx_ll_dst_rdy_n_i;
// Create synchronous reset in the transmitter clock domain
always @(posedge ll_clk_i, posedge reset_i)
begin
if (reset_i === 1'b1)
begin
ll_pre_reset_i <= 6'h3F;
ll_reset_i <= 1'b1;
end
else
begin
ll_pre_reset_i[0] <= 1'b0;
ll_pre_reset_i[5:1] <= ll_pre_reset_i[4:0];
ll_reset_i <= ll_pre_reset_i[5];
end
end
// Globally-buffer the reference clock used for
// the IODELAYCTRL primitive
IBUFG refclk_ibufg (
.I (REFCLK),
.O (refclk_ibufg_i)
);
BUFG refclk_bufg (
.I (refclk_ibufg_i),
.O (refclk_bufg_i)
);
// Buffer the input clock used for the generic host management
// interface. This input should be driven from the 125MHz reference
// clock to save clocking resources.
IBUF host_clk (
.I (HOSTCLK),
.O (host_clk_i)
);
// Prepare the GTX_CLK for a BUFG
IBUFG gtx_clk_ibufg (
.I (GTX_CLK),
.O (gtx_clk_i)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V |
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* This file is (C) Copyright 2006-2015 Microsoft Corporation and Inria. *)
(** #<style> .doc { font-family: monospace; white-space: pre; } </style># **)
Require Bool.
Require Import ssreflect ssrfun.
(**
A theory of boolean predicates and operators. A large part of this file is
concerned with boolean reflection.
Definitions and notations:
is_true b == the coercion of b : bool to Prop (:= b = true).
This is just input and displayed as `b''.
reflect P b == the reflection inductive predicate, asserting
that the logical proposition P : prop with the
formula b : bool. Lemmas asserting reflect P b
are often referred to as "views".
iffP, appP, sameP, rwP :: lemmas for direct manipulation of reflection
views: iffP is used to prove reflection from
logical equivalence, appP to compose views, and
sameP and rwP to perform boolean and setoid
rewriting.
elimT :: coercion reflect >-> Funclass, which allows the
direct application of `reflect' views to
boolean assertions.
decidable P <-> P is effectively decidable (:= {P} + {~ P}.
contra, contraL, ... :: contraposition lemmas.
altP my_viewP :: natural alternative for reflection; given
lemma myviewP: reflect my_Prop my_formula,
have #[#myP | not_myP#]# := altP my_viewP.
generates two subgoals, in which my_formula has
been replaced by true and false, resp., with
new assumptions myP : my_Prop and
not_myP: ~~ my_formula.
Caveat: my_formula must be an APPLICATION, not
a variable, constant, let-in, etc. (due to the
poor behaviour of dependent index matching).
boolP my_formula :: boolean disjunction, equivalent to
altP (idP my_formula) but circumventing the
dependent index capture issue; destructing
boolP my_formula generates two subgoals with
assumptions my_formula and ~~ myformula. As
with altP, my_formula must be an application.
\unless C, P <-> we can assume property P when a something that
holds under condition C (such as C itself).
:= forall G : Prop, (C -> G) -> (P -> G) -> G.
This is just C \/ P or rather its impredicative
encoding, whose usage better fits the above
description: given a lemma UCP whose conclusion
is \unless C, P we can assume P by writing:
wlog hP: / P by apply/UCP; (prove C -> goal).
or even apply: UCP id _ => hP if the goal is C.
classically P <-> we can assume P when proving is_true b.
:= forall b : bool, (P -> b) -> b.
This is equivalent to ~ (~ P) when P : Prop.
implies P Q == wrapper variant type that coerces to P -> Q and
can be used as a P -> Q view unambiguously.
Useful to avoid spurious insertion of <-> views
when Q is a conjunction of foralls, as in Lemma
all_and2 below; conversely, avoids confusion in
apply views for impredicative properties, such
as \unless C, P. Also supports contrapositives.
a && b == the boolean conjunction of a and b.
a || b == the boolean disjunction of a and b.
a ==> b == the boolean implication of b by a.
~~ a == the boolean negation of a.
a (+) b == the boolean exclusive or (or sum) of a and b.
#[# /\ P1 , P2 & P3 #]# == multiway logical conjunction, up to 5 terms.
#[# \/ P1 , P2 | P3 #]# == multiway logical disjunction, up to 4 terms.
#[#&& a, b, c & d#]# == iterated, right associative boolean conjunction
with arbitrary arity.
#[#|| a, b, c | d#]# == iterated, right associative boolean disjunction
with arbitrary arity.
#[#==> a, b, c => d#]# == iterated, right associative boolean implication
with arbitrary arity.
and3P, ... == specific reflection lemmas for iterated
connectives.
andTb, orbAC, ... == systematic names for boolean connective
properties (see suffix conventions below).
prop_congr == a tactic to move a boolean equality from
its coerced form in Prop to the equality
in bool.
bool_congr == resolution tactic for blindly weeding out
like terms from boolean equalities (can fail).
This file provides a theory of boolean predicates and relations:
pred T == the type of bool predicates (:= T -> bool).
simpl_pred T == the type of simplifying bool predicates, based on
the simpl_fun type from ssrfun.v.
mem_pred T == a specialized form of simpl_pred for "collective"
predicates (see below).
rel T == the type of bool relations.
:= T -> pred T or T -> T -> bool.
simpl_rel T == type of simplifying relations.
:= T -> simpl_pred T
predType == the generic predicate interface, supported for
for lists and sets.
pred_sort == the predType >-> Type projection; pred_sort is
itself a Coercion target class. Declaring a
coercion to pred_sort is an alternative way of
equiping a type with a predType structure, which
interoperates better with coercion subtyping.
This is used, e.g., for finite sets, so that finite
groups inherit the membership operation by
coercing to sets.
{pred T} == a type convertible to pred T, but whose head
constant is pred_sort. This type should be used
for parameters that can be used as collective
predicates (see below), as this will allow passing
in directly collections that implement predType
by coercion as described above, e.g., finite sets.
:= pred_sort (predPredType T)
If P is a predicate the proposition "x satisfies P" can be written
applicatively as (P x), or using an explicit connective as (x \in P); in
the latter case we say that P is a "collective" predicate. We use A, B
rather than P, Q for collective predicates:
x \in A == x satisfies the (collective) predicate A.
x \notin A == x doesn't satisfy the (collective) predicate A.
The pred T type can be used as a generic predicate type for either kind,
but the two kinds of predicates should not be confused. When a "generic"
pred T value of one type needs to be passed as the other the following
conversions should be used explicitly:
SimplPred P == a (simplifying) applicative equivalent of P.
mem A == an applicative equivalent of collective predicate A:
mem A x simplifies to x \in A, as mem A has in
fact type mem_pred T.
--> In user notation collective predicates _only_ occur as arguments to mem:
A only appears as (mem A). This is hidden by notation, e.g.,
x \in A := in_mem x (mem A) here, enum A := enum_mem (mem A) in fintype.
This makes it possible to unify the various ways in which A can be
interpreted as a predicate, for both pattern matching and display.
Alternatively one can use the syntax for explicit simplifying predicates
and relations (in the following x is bound in E):
#[#pred x | E#]# == simplifying (see ssrfun) predicate x => E.
#[#pred x : T | E#]# == predicate x => E, with a cast on the argument.
#[#pred : T | P#]# == constant predicate P on type T.
#[#pred x | E1 & E2#]# == #[#pred x | E1 && E2#]#; an x : T cast is allowed.
#[#pred x in A#]# == #[#pred x | x in A#]#.
#[#pred x in A | E#]# == #[#pred x | x in A & E#]#.
#[#pred x in A | E1 & E2#]# == #[#pred x in A | E1 && E2#]#.
#[#predU A & B#]# == union of two collective predicates A and B.
#[#predI A & B#]# == intersection of collective predicates A and B.
#[#predD A & B#]# == difference of collective predicates A and B.
#[#predC A#]# == complement of the collective predicate A.
#[#preim f of A#]# == preimage under f of the collective predicate A.
predU P Q, ..., preim f P == union, etc of applicative predicates.
pred0 == the empty predicate.
predT == the total (always true) predicate.
if T : predArgType, then T coerces to predT.
{: T} == T cast to predArgType (e.g., {: bool * nat}).
In the following, x and y are bound in E:
#[#rel x y | E#]# == simplifying relation x, y => E.
#[#rel x y : T | E#]# == simplifying relation with arguments cast.
#[#rel x y in A & B | E#]# == #[#rel x y | #[#&& x \in A, y \in B & E#]# #]#.
#[#rel x y in A & B#]# == #[#rel x y | (x \in A) && (y \in B) #]#.
#[#rel x y in A | E#]# == #[#rel x y in A & A | E#]#.
#[#rel x y in A#]# == #[#rel x y in A & A#]#.
relU R S == union of relations R and S.
relpre f R == preimage of relation R under f.
xpredU, ..., xrelpre == lambda terms implementing predU, ..., etc.
Explicit values of type pred T (i.e., lamdba terms) should always be used
applicatively, while values of collection types implementing the predType
interface, such as sequences or sets should always be used as collective
predicates. Defined constants and functions of type pred T or simpl_pred T
as well as the explicit simpl_pred T values described below, can generally
be used either way. Note however that x \in A will not auto-simplify when
A is an explicit simpl_pred T value; the generic simplification rule inE
must be used (when A : pred T, the unfold_in rule can be used). Constants
of type pred T with an explicit simpl_pred value do not auto-simplify when
used applicatively, but can still be expanded with inE. This behavior can
be controlled as follows:
Let A : collective_pred T := #[#pred x | ... #]#.
The collective_pred T type is just an alias for pred T, but this cast
stops rewrite inE from expanding the definition of A, thus treating A
into an abstract collection (unfold_in or in_collective can be used to
expand manually).
Let A : applicative_pred T := #[#pred x | ... #]#.
This cast causes inE to turn x \in A into the applicative A x form;
A will then have to unfolded explicitly with the /A rule. This will
also apply to any definition that reduces to A (e.g., Let B := A).
Canonical A_app_pred := ApplicativePred A.
This declaration, given after definition of A, similarly causes inE to
turn x \in A into A x, but in addition allows the app_predE rule to
turn A x back into x \in A; it can be used for any definition of type
pred T, which makes it especially useful for ambivalent predicates
as the relational transitive closure connect, that are used in both
applicative and collective styles.
Purely for aesthetics, we provide a subtype of collective predicates:
qualifier q T == a pred T pretty-printing wrapper. An A : qualifier q T
coerces to pred_sort and thus behaves as a collective
predicate, but x \in A and x \notin A are displayed as:
x \is A and x \isn't A when q = 0,
x \is a A and x \isn't a A when q = 1,
x \is an A and x \isn't an A when q = 2, respectively.
#[#qualify x | P#]# := Qualifier 0 (fun x => P), constructor for the above.
#[#qualify x : T | P#]#, #[#qualify a x | P#]#, #[#qualify an X | P#]#, etc.
variants of the above with type constraints and different
values of q.
We provide an internal interface to support attaching properties (such as
being multiplicative) to predicates:
pred_key p == phantom type that will serve as a support for properties
to be attached to p : {pred _}; instances should be
created with Fact/Qed so as to be opaque.
KeyedPred k_p == an instance of the interface structure that attaches
(k_p : pred_key P) to P; the structure projection is a
coercion to pred_sort.
KeyedQualifier k_q == an instance of the interface structure that attaches
(k_q : pred_key q) to (q : qualifier n T).
DefaultPredKey p == a default value for pred_key p; the vernacular command
Import DefaultKeying attaches this key to all predicates
that are not explicitly keyed.
Keys can be used to attach properties to predicates, qualifiers and
generic nouns in a way that allows them to be used transparently. The key
projection of a predicate property structure such as unsignedPred should
be a pred_key, not a pred, and corresponding lemmas will have the form
Lemma rpredN R S (oppS : @opprPred R S) (kS : keyed_pred oppS) :
{mono -%%R: x / x \in kS}.
Because x \in kS will be displayed as x \in S (or x \is S, etc), the
canonical instance of opprPred will not normally be exposed (it will also
be erased by /= simplification). In addition each predicate structure
should have a DefaultPredKey Canonical instance that simply issues the
property as a proof obligation (which can be caught by the Prop-irrelevant
feature of the ssreflect plugin).
Some properties of predicates and relations:
A =i B <-> A and B are extensionally equivalent.
{subset A <= B} <-> A is a (collective) subpredicate of B.
subpred P Q <-> P is an (applicative) subpredicate or Q.
subrel R S <-> R is a subrelation of S.
In the following R is in rel T:
reflexive R <-> R is reflexive.
irreflexive R <-> R is irreflexive.
symmetric R <-> R (in rel T) is symmetric (equation).
pre_symmetric R <-> R is symmetric (implication).
antisymmetric R <-> R is antisymmetric.
total R <-> R is total.
transitive R <-> R is transitive.
left_transitive R <-> R is a congruence on its left hand side.
right_transitive R <-> R is a congruence on its right hand side.
equivalence_rel R <-> R is an equivalence relation.
Localization of (Prop) predicates; if P1 is convertible to forall x, Qx,
P2 to forall x y, Qxy and P3 to forall x y z, Qxyz :
{for y, P1} <-> Qx{y / x}.
{in A, P1} <-> forall x, x \in A -> Qx.
{in A1 & A2, P2} <-> forall x y, x \in A1 -> y \in A2 -> Qxy.
{in A &, P2} <-> forall x y, x \in A -> y \in A -> Qxy.
{in A1 & A2 & A3, Q3} <-> forall x y z,
x \in A1 -> y \in A2 -> z \in A3 -> Qxyz.
{in A1 & A2 &, Q3} := {in A1 & A2 & A2, Q3}.
{in A1 && A3, Q3} := {in A1 & A1 & A3, Q3}.
{in A &&, Q3} := {in A & A & A, Q3}.
{in A, bijective f} <-> f has a right inverse in A.
{on C, P1} <-> forall x, (f x) \in C -> Qx
when P1 is also convertible to Pf f, e.g.,
{on C, involutive f}.
{on C &, P2} == forall x y, f x \in C -> f y \in C -> Qxy
when P2 is also convertible to Pf f, e.g.,
{on C &, injective f}.
{on C, P1' & g} == forall x, (f x) \in cd -> Qx
when P1' is convertible to Pf f
and P1' g is convertible to forall x, Qx, e.g.,
{on C, cancel f & g}.
{on C, bijective f} == f has a right inverse on C.
This file extends the lemma name suffix conventions of ssrfun as follows:
A -- associativity, as in andbA : associative andb.
AC -- right commutativity.
ACA -- self-interchange (inner commutativity), e.g.,
orbACA : (a || b) || (c || d) = (a || c) || (b || d).
b -- a boolean argument, as in andbb : idempotent andb.
C -- commutativity, as in andbC : commutative andb,
or predicate complement, as in predC.
CA -- left commutativity.
D -- predicate difference, as in predD.
E -- elimination, as in negbFE : ~~ b = false -> b.
F or f -- boolean false, as in andbF : b && false = false.
I -- left/right injectivity, as in addbI : right_injective addb,
or predicate intersection, as in predI.
l -- a left-hand operation, as andb_orl : left_distributive andb orb.
N or n -- boolean negation, as in andbN : a && (~~ a) = false.
P -- a characteristic property, often a reflection lemma, as in
andP : reflect (a /\ b) (a && b).
r -- a right-hand operation, as orb_andr : rightt_distributive orb andb.
T or t -- boolean truth, as in andbT: right_id true andb.
U -- predicate union, as in predU.
W -- weakening, as in in1W : (forall x, P) -> {in D, forall x, P}. **)
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Set Warnings "-projection-no-head-constant".
Notation reflect := Bool.reflect.
Notation ReflectT := Bool.ReflectT.
Notation ReflectF := Bool.ReflectF.
Reserved Notation "~~ b" (at level 35, right associativity).
Reserved Notation "b ==> c" (at level 55, right associativity).
Reserved Notation "b1 (+) b2" (at level 50, left associativity).
Reserved Notation "x \in A" (at level 70, no associativity,
format "'[hv' x '/ ' \in A ']'").
Reserved Notation "x \notin A" (at level 70, no associativity,
format "'[hv' x '/ ' \notin A ']'").
Reserved Notation "x \is A" (at level 70, no associativity,
format "'[hv' x '/ ' \is A ']'").
Reserved Notation "x \isn't A" (at level 70, no associativity,
format "'[hv' x '/ ' \isn't A ']'").
Reserved Notation "x \is 'a' A" (at level 70, no associativity,
format "'[hv' x '/ ' \is 'a' A ']'").
Reserved Notation "x \isn't 'a' A" (at level 70, no associativity,
format "'[hv' x '/ ' \isn't 'a' A ']'").
Reserved Notation "x \is 'an' A" (at level 70, no associativity,
format "'[hv' x '/ ' \is 'an' A ']'").
Reserved Notation "x \isn't 'an' A" (at level 70, no associativity,
format "'[hv' x '/ ' \isn't 'an' A ']'").
Reserved Notation "p1 =i p2" (at level 70, no associativity,
format "'[hv' p1 '/ ' =i p2 ']'").
Reserved Notation "{ 'subset' A <= B }" (at level 0, A, B at level 69,
format "'[hv' { 'subset' A '/ ' <= B } ']'").
Reserved Notation "{ : T }" (at level 0, format "{ : T }").
Reserved Notation "{ 'pred' T }" (at level 0, format "{ 'pred' T }").
Reserved Notation "[ 'predType' 'of' T ]" (at level 0,
format "[ 'predType' 'of' T ]").
Reserved Notation "[ 'pred' : T | E ]" (at level 0,
format "'[hv' [ 'pred' : T | '/ ' E ] ']'").
Reserved Notation "[ 'pred' x | E ]" (at level 0, x ident,
format "'[hv' [ 'pred' x | '/ ' E ] ']'").
Reserved Notation "[ 'pred' x : T | E ]" (at level 0, x ident,
format "'[hv' [ 'pred' x : T | '/ ' E ] ']'").
Reserved Notation "[ 'pred' x | E1 & E2 ]" (at level 0, x ident,
format "'[hv' [ 'pred' x | '/ ' E1 & '/ ' E2 ] ']'").
Reserved Notation "[ 'pred' x : T | E1 & E2 ]" (at level 0, x ident,
format "'[hv' [ 'pred' x : T | '/ ' E1 & E2 ] ']'").
Reserved Notation "[ 'pred' x 'in' A ]" (at level 0, x ident,
format "'[hv' [ 'pred' x 'in' A ] ']'").
Reserved Notation "[ 'pred' x 'in' A | E ]" (at level 0, x ident,
format "'[hv' [ 'pred' x 'in' A | '/ ' E ] ']'").
Reserved Notation "[ 'pred' x 'in' A | E1 & E2 ]" (at level 0, x ident,
format "'[hv' [ 'pred' x 'in' A | '/ ' E1 & '/ ' E2 ] ']'").
Reserved Notation "[ 'qualify' x | P ]" (at level 0, x at level 99,
format "'[hv' [ 'qualify' x | '/ ' P ] ']'").
Reserved Notation "[ 'qualify' x : T | P ]" (at level 0, x at level 99,
format "'[hv' [ 'qualify' x : T | '/ ' P ] ']'").
Reserved Notation "[ 'qualify' 'a' x | P ]" (at level 0, x at level 99,
format "'[hv' [ 'qualify' 'a' x | '/ ' P ] ']'").
Reserved Notation "[ 'qualify' 'a' x : T | P ]" (at level 0, x at level 99,
format "'[hv' [ 'qualify' 'a' x : T | '/ ' P ] ']'").
Reserved Notation "[ 'qualify' 'an' x | P ]" (at level 0, x at level 99,
format "'[hv' [ 'qualify' 'an' x | '/ ' P ] ']'").
Reserved Notation "[ 'qualify' 'an' x : T | P ]" (at level 0, x at level 99,
format "'[hv' [ 'qualify' 'an' x : T | '/ ' P ] ']'").
Reserved Notation "[ 'rel' x y | E ]" (at level 0, x ident, y ident,
format "'[hv' [ 'rel' x y | '/ ' E ] ']'").
Reserved Notation "[ 'rel' x y : T | E ]" (at level 0, x ident, y ident,
format "'[hv' [ 'rel' x y : T | '/ ' E ] ']'").
Reserved Notation "[ 'rel' x y 'in' A & B | E ]" (at level 0, x ident, y ident,
format "'[hv' [ 'rel' x y 'in' A & B | '/ ' E ] ']'").
Reserved Notation "[ 'rel' x y 'in' A & B ]" (at level 0, x ident, y ident,
format "'[hv' [ 'rel' x y 'in' A & B ] ']'").
Reserved Notation "[ 'rel' x y 'in' A | E ]" (at level 0, x ident, y ident,
format "'[hv' [ 'rel' x y 'in' A | '/ ' E ] ']'").
Reserved Notation "[ 'rel' x y 'in' A ]" (at level 0, x ident, y ident,
format "'[hv' [ 'rel' x y 'in' A ] ']'").
Reserved Notation "[ 'mem' A ]" (at level 0, format "[ 'mem' A ]").
Reserved Notation "[ 'predI' A & B ]" (at level 0,
format "[ 'predI' A & B ]").
Reserved Notation "[ 'predU' A & B ]" (at level 0,
format "[ 'predU' A & B ]").
Reserved Notation "[ 'predD' A & B ]" (at level 0,
format "[ 'predD' A & B ]").
Reserved Notation "[ 'predC' A ]" (at level 0,
format "[ 'predC' A ]").
Reserved Notation "[ 'preim' f 'of' A ]" (at level 0,
format "[ 'preim' f 'of' A ]").
Reserved Notation "\unless C , P" (at level 200, C at level 100,
format "'[hv' \unless C , '/ ' P ']'").
Reserved Notation "{ 'for' x , P }" (at level 0,
format "'[hv' { 'for' x , '/ ' P } ']'").
Reserved Notation "{ 'in' d , P }" (at level 0,
format "'[hv' { 'in' d , '/ ' P } ']'").
Reserved Notation "{ 'in' d1 & d2 , P }" (at level 0,
format "'[hv' { 'in' d1 & d2 , '/ ' P } ']'").
Reserved Notation "{ 'in' d & , P }" (at level 0,
format "'[hv' { 'in' d & , '/ ' P } ']'").
Reserved Notation "{ 'in' d1 & d2 & d3 , P }" (at level 0,
format "'[hv' { 'in' d1 & d2 & d3 , '/ ' P } ']'").
Reserved Notation "{ 'in' d1 & & d3 , P }" (at level 0,
format "'[hv' { 'in' d1 & & d3 , '/ ' P } ']'").
Reserved Notation "{ 'in' d1 & d2 & , P }" (at level 0,
format "'[hv' { 'in' d1 & d2 & , '/ ' P } ']'").
Reserved Notation "{ 'in' d & & , P }" (at level 0,
format "'[hv' { 'in' d & & , '/ ' P } ']'").
Reserved Notation "{ 'on' cd , P }" (at level 0,
format "'[hv' { 'on' cd , '/ ' P } ']'").
Reserved Notation "{ 'on' cd & , P }" (at level 0,
format "'[hv' { 'on' cd & , '/ ' P } ']'").
Reserved Notation "{ 'on' cd , P & g }" (at level 0, g at level 8,
format "'[hv' { 'on' cd , '/ ' P & g } ']'").
Reserved Notation "{ 'in' d , 'bijective' f }" (at level 0, f at level 8,
format "'[hv' { 'in' d , '/ ' 'bijective' f } ']'").
Reserved Notation "{ 'on' cd , 'bijective' f }" (at level 0, f at level 8,
format "'[hv' { 'on' cd , '/ ' 'bijective' f } ']'").
(**
We introduce a number of n-ary "list-style" notations that share a common
format, namely
#[#op arg1, arg2, ... last_separator last_arg#]#
This usually denotes a right-associative applications of op, e.g.,
#[#&& a, b, c & d#]# denotes a && (b && (c && d))
The last_separator must be a non-operator token. Here we use &, | or =>;
our default is &, but we try to match the intended meaning of op. The
separator is a workaround for limitations of the parsing engine; the same
limitations mean the separator cannot be omitted even when last_arg can.
The Notation declarations are complicated by the separate treatment for
some fixed arities (binary for bool operators, and all arities for Prop
operators).
We also use the square brackets in comprehension-style notations
#[#type var separator expr#]#
where "type" is the type of the comprehension (e.g., pred) and "separator"
is | or => . It is important that in other notations a leading square
bracket #[# is always followed by an operator symbol or a fixed identifier. **)
Reserved Notation "[ /\ P1 & P2 ]" (at level 0, only parsing).
Reserved Notation "[ /\ P1 , P2 & P3 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 ']' '/ ' & P3 ] ']'").
Reserved Notation "[ /\ P1 , P2 , P3 & P4 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 , '/' P3 ']' '/ ' & P4 ] ']'").
Reserved Notation "[ /\ P1 , P2 , P3 , P4 & P5 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 , '/' P3 , '/' P4 ']' '/ ' & P5 ] ']'").
Reserved Notation "[ \/ P1 | P2 ]" (at level 0, only parsing).
Reserved Notation "[ \/ P1 , P2 | P3 ]" (at level 0, format
"'[hv' [ \/ '[' P1 , '/' P2 ']' '/ ' | P3 ] ']'").
Reserved Notation "[ \/ P1 , P2 , P3 | P4 ]" (at level 0, format
"'[hv' [ \/ '[' P1 , '/' P2 , '/' P3 ']' '/ ' | P4 ] ']'").
Reserved Notation "[ && b1 & c ]" (at level 0, only parsing).
Reserved Notation "[ && b1 , b2 , .. , bn & c ]" (at level 0, format
"'[hv' [ && '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/ ' & c ] ']'").
Reserved Notation "[ || b1 | c ]" (at level 0, only parsing).
Reserved Notation "[ || b1 , b2 , .. , bn | c ]" (at level 0, format
"'[hv' [ || '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/ ' | c ] ']'").
Reserved Notation "[ ==> b1 => c ]" (at level 0, only parsing).
Reserved Notation "[ ==> b1 , b2 , .. , bn => c ]" (at level 0, format
"'[hv' [ ==> '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/' => c ] ']'").
(** Shorter delimiter **)
Delimit Scope bool_scope with B.
Open Scope bool_scope.
(** An alternative to xorb that behaves somewhat better wrt simplification. **)
Definition addb b := if b then negb else id.
(** Notation for && and || is declared in Init.Datatypes. **)
Notation "~~ b" := (negb b) : bool_scope.
Notation "b ==> c" := (implb b c) : bool_scope.
Notation "b1 (+) b2" := (addb b1 b2) : bool_scope.
(** Constant is_true b := b = true is defined in Init.Datatypes. **)
Coercion is_true : bool >-> Sortclass. (* Prop *)
Lemma prop_congr : forall b b' : bool, b = b' -> b = b' :> Prop.
Proof. by move=> b b' ->. Qed.
Ltac prop_congr := apply: prop_congr.
(** Lemmas for trivial. **)
Lemma is_true_true : true. Proof. by []. Qed.
Lemma not_false_is_true : ~ false. Proof. by []. Qed.
Lemma is_true_locked_true : locked true. Proof. by unlock. Qed.
Hint Resolve is_true_true not_false_is_true is_true_locked_true : core.
(** Shorter names. **)
Definition isT := is_true_true.
Definition notF := not_false_is_true.
(** Negation lemmas. **)
(**
We generally take NEGATION as the standard form of a false condition:
negative boolean hypotheses should be of the form ~~ b, rather than ~ b or
b = false, as much as possible. **)
Lemma negbT b : b = false -> ~~ b. Proof. by case: b. Qed.
Lemma negbTE b : ~~ b -> b = false. Proof. by case: b. Qed.
Lemma negbF b : (b : bool) -> ~~ b = false. Proof. by case: b. Qed.
Lemma negbFE b : ~~ b = false -> b. Proof. by case: b. Qed.
Lemma negbK : involutive negb. Proof. by case. Qed.
Lemma negbNE b : ~~ ~~ b -> b. Proof. by case: b. Qed.
Lemma negb_inj : injective negb. Proof. exact: can_inj negbK. Qed.
Lemma negbLR b c : b = ~~ c -> ~~ b = c. Proof. exact: canLR negbK. Qed.
Lemma negbRL b c : ~~ b = c -> b = ~~ c. Proof. exact: canRL negbK. Qed.
Lemma contra (c b : bool) : (c -> b) -> ~~ b -> ~~ c.
Proof. by case: b => //; case: c. Qed.
Definition contraNN := contra.
Lemma contraL (c b : bool) : (c -> ~~ b) -> b -> ~~ c.
Proof. by case: b => //; case: c. Qed.
Definition contraTN := contraL.
Lemma contraR (c b : bool) : (~~ c -> b) -> ~~ b -> c.
Proof. by case: b => //; case: c. Qed.
Definition contraNT := contraR.
Lemma contraLR (c b : bool) : (~~ c -> ~~ b) -> b -> c.
Proof. by case: b => //; case: c. Qed.
Definition contraTT := contraLR.
Lemma contraT b : (~~ b -> false) -> b. Proof. by case: b => // ->. Qed.
Lemma wlog_neg b : (~~ b -> b) -> b. Proof. by case: b => // ->. Qed.
Lemma contraFT (c b : bool) : (~~ c -> b) -> b = false -> c.
Proof. by move/contraR=> notb_c /negbT. Qed.
Lemma contraFN (c b : bool) : (c -> b) -> b = false -> ~~ c.
Proof. by move/contra=> notb_notc /negbT. Qed.
Lemma contraTF (c b : bool) : (c -> ~~ b) -> b -> c = false.
Proof. by move/contraL=> b_notc /b_notc/negbTE. Qed.
Lemma contraNF (c b : bool) : (c -> b) -> ~~ b -> c = false.
Proof. by move/contra=> notb_notc /notb_notc/negbTE. Qed.
Lemma contraFF (c b : bool) : (c -> b) -> b = false -> c = false.
Proof. by move/contraFN=> bF_notc /bF_notc/negbTE. Qed.
(**
Coercion of sum-style datatypes into bool, which makes it possible
to use ssr's boolean if rather than Coq's "generic" if. **)
Coercion isSome T (u : option T) := if u is Some _ then true else false.
Coercion is_inl A B (u : A + B) := if u is inl _ then true else false.
Coercion is_left A B (u : {A} + {B}) := if u is left _ then true else false.
Coercion is_inleft A B (u : A + {B}) := if u is inleft _ then true else false.
Prenex Implicits isSome is_inl is_left is_inleft.
Definition decidable P := {P} + {~ P}.
(**
Lemmas for ifs with large conditions, which allow reasoning about the
condition without repeating it inside the proof (the latter IS
preferable when the condition is short).
Usage :
if the goal contains (if cond then ...) = ...
case: ifP => Hcond.
generates two subgoal, with the assumption Hcond : cond = true/false
Rewrite if_same eliminates redundant ifs
Rewrite (fun_if f) moves a function f inside an if
Rewrite if_arg moves an argument inside a function-valued if **)
Section BoolIf.
Variables (A B : Type) (x : A) (f : A -> B) (b : bool) (vT vF : A).
Variant if_spec (not_b : Prop) : bool -> A -> Set :=
| IfSpecTrue of b : if_spec not_b true vT
| IfSpecFalse of not_b : if_spec not_b false vF.
Lemma ifP : if_spec (b = false) b (if b then vT else vF).
Proof. by case def_b: b; constructor. Qed.
Lemma ifPn : if_spec (~~ b) b (if b then vT else vF).
Proof. by case def_b: b; constructor; rewrite ?def_b. Qed.
Lemma ifT : b -> (if b then vT else vF) = vT. Proof. by move->. Qed.
Lemma ifF : b = false -> (if b then vT else vF) = vF. Proof. by move->. Qed.
Lemma ifN : ~~ b -> (if b then vT else vF) = vF. Proof. by move/negbTE->. Qed.
Lemma if_same : (if b then vT else vT) = vT.
Proof. by case b. Qed.
Lemma if_neg : (if ~~ b then vT else vF) = if b then vF else vT.
Proof. by case b. Qed.
Lemma fun_if : f (if b then vT else vF) = if b then f vT else f vF.
Proof. by case b. Qed.
Lemma if_arg (fT fF : A -> B) :
(if b then fT else fF) x = if b then fT x else fF x.
Proof. by case b. Qed.
(** Turning a boolean "if" form into an application. **)
Definition if_expr := if b then vT else vF.
Lemma ifE : (if b then vT else vF) = if_expr. Proof. by []. Qed.
End BoolIf.
(** Core (internal) reflection lemmas, used for the three kinds of views. **)
Section ReflectCore.
Variables (P Q : Prop) (b c : bool).
Hypothesis Hb : reflect P b.
Lemma introNTF : (if c then ~ P else P) -> ~~ b = c.
Proof. by case c; case Hb. Qed.
Lemma introTF : (if c then P else ~ P) -> b = c.
Proof. by case c; case Hb. Qed.
Lemma elimNTF : ~~ b = c -> if c then ~ P else P.
Proof. by move <-; case Hb. Qed.
Lemma elimTF : b = c -> if c then P else ~ P.
Proof. by move <-; case Hb. Qed.
Lemma equivPif : (Q -> P) -> (P -> Q) -> if b then Q else ~ Q.
Proof. by case Hb; auto. Qed.
Lemma xorPif : Q \/ P -> ~ (Q /\ P) -> if b then ~ Q else Q.
Proof. by case Hb => [? _ H ? | ? H _]; case: H. Qed.
End ReflectCore.
(** Internal negated reflection lemmas **)
Section ReflectNegCore.
Variables (P Q : Prop) (b c : bool).
Hypothesis Hb : reflect P (~~ b).
Lemma introTFn : (if c then ~ P else P) -> b = c.
Proof. by move/(introNTF Hb) <-; case b. Qed.
Lemma elimTFn : b = c -> if c then ~ P else P.
Proof. by move <-; apply: (elimNTF Hb); case b. Qed.
Lemma equivPifn : (Q -> P) -> (P -> Q) -> if b then ~ Q else Q.
Proof. by rewrite -if_neg; apply: equivPif. Qed.
Lemma xorPifn : Q \/ P -> ~ (Q /\ P) -> if b then Q else ~ Q.
Proof. by rewrite -if_neg; apply: xorPif. Qed.
End ReflectNegCore.
(** User-oriented reflection lemmas **)
Section Reflect.
Variables (P Q : Prop) (b b' c : bool).
Hypotheses (Pb : reflect P b) (Pb' : reflect P (~~ b')).
Lemma introT : P -> b. Proof. exact: introTF true _. Qed.
Lemma introF : ~ P -> b = false. Proof. exact: introTF false _. Qed.
Lemma introN : ~ P -> ~~ b. Proof. exact: introNTF true _. Qed.
Lemma introNf : P -> ~~ b = false. Proof. exact: introNTF false _. Qed.
Lemma introTn : ~ P -> b'. Proof. exact: introTFn true _. Qed.
Lemma introFn : P -> b' = false. Proof. exact: introTFn false _. Qed.
Lemma elimT : b -> P. Proof. exact: elimTF true _. Qed.
Lemma elimF : b = false -> ~ P. Proof. exact: elimTF false _. Qed.
Lemma elimN : ~~ b -> ~P. Proof. exact: elimNTF true _. Qed.
Lemma elimNf : ~~ b = false -> P. Proof. exact: elimNTF false _. Qed.
Lemma elimTn : b' -> ~ P. Proof. exact: elimTFn true _. Qed.
Lemma elimFn : b' = false -> P. Proof. exact: elimTFn false _. Qed.
Lemma introP : (b -> Q) -> (~~ b -> ~ Q) -> reflect Q b.
Proof. by case b; constructor; auto. Qed.
Lemma iffP : (P -> Q) -> (Q -> P) -> reflect Q b.
Proof. by case: Pb; constructor; auto. Qed.
Lemma equivP : (P <-> Q) -> reflect Q b.
Proof. by case; apply: iffP. Qed.
Lemma sumboolP (decQ : decidable Q) : reflect Q decQ.
Proof. by case: decQ; constructor. Qed.
Lemma appP : reflect Q b -> P -> Q.
Proof. by move=> Qb; move/introT; case: Qb. Qed.
Lemma sameP : reflect P c -> b = c.
Proof. by case; [apply: introT | apply: introF]. Qed.
Lemma decPcases : if b then P else ~ P. Proof. by case Pb. Qed.
Definition decP : decidable P. by case: b decPcases; [left | right]. Defined.
Lemma rwP : P <-> b. Proof. by split; [apply: introT | apply: elimT]. Qed.
Lemma rwP2 : reflect Q b -> (P <-> Q).
Proof. by move=> Qb; split=> ?; [apply: appP | apply: elimT; case: Qb]. Qed.
(** Predicate family to reflect excluded middle in bool. **)
Variant alt_spec : bool -> Type :=
| AltTrue of P : alt_spec true
| AltFalse of ~~ b : alt_spec false.
Lemma altP : alt_spec b.
Proof. by case def_b: b / Pb; constructor; rewrite ?def_b. Qed.
End Reflect.
Hint View for move/ elimTF|3 elimNTF|3 elimTFn|3 introT|2 introTn|2 introN|2.
Hint View for apply/ introTF|3 introNTF|3 introTFn|3 elimT|2 elimTn|2 elimN|2.
Hint View for apply// equivPif|3 xorPif|3 equivPifn|3 xorPifn|3.
(** Allow the direct application of a reflection lemma to a boolean assertion. **)
Coercion elimT : reflect >-> Funclass.
#[universes(template)]
Variant implies P Q := Implies of P -> Q.
Lemma impliesP P Q : implies P Q -> P -> Q. Proof. by case. Qed.
Lemma impliesPn (P Q : Prop) : implies P Q -> ~ Q -> ~ P.
Proof. by case=> iP ? /iP. Qed.
Coercion impliesP : implies >-> Funclass.
Hint View for move/ impliesPn|2 impliesP|2.
Hint View for apply/ impliesPn|2 impliesP|2.
(** Impredicative or, which can emulate a classical not-implies. **)
Definition unless condition property : Prop :=
forall goal : Prop, (condition -> goal) -> (property -> goal) -> goal.
Notation "\unless C , P" := (unless C P) : type_scope.
Lemma unlessL C P : implies C (\unless C, P).
Proof. by split=> hC G /(_ hC). Qed.
Lemma unlessR C P : implies P (\unless C, P).
Proof. by split=> hP G _ /(_ hP). Qed.
Lemma unless_sym C P : implies (\unless C, P) (\unless P, C).
Proof. by split; apply; [apply/unlessR | apply/unlessL]. Qed.
Lemma unlessP (C P : Prop) : (\unless C, P) <-> C \/ P.
Proof. by split=> [|[/unlessL | /unlessR]]; apply; [left | right]. Qed.
Lemma bind_unless C P {Q} : implies (\unless C, P) (\unless (\unless C, Q), P).
Proof. by split; apply=> [hC|hP]; [apply/unlessL/unlessL | apply/unlessR]. Qed.
Lemma unless_contra b C : implies (~~ b -> C) (\unless C, b).
Proof. by split; case: b => [_ | hC]; [apply/unlessR | apply/unlessL/hC]. Qed.
(**
Classical reasoning becomes directly accessible for any bool subgoal.
Note that we cannot use "unless" here for lack of universe polymorphism. **)
Definition classically P : Prop := forall b : bool, (P -> b) -> b.
Lemma classicP (P : Prop) : classically P <-> ~ ~ P.
Proof.
split=> [cP nP | nnP [] // nP]; last by case nnP; move/nP.
by have: P -> false; [move/nP | move/cP].
Qed.
Lemma classicW P : P -> classically P. Proof. by move=> hP _ ->. Qed.
Lemma classic_bind P Q : (P -> classically Q) -> classically P -> classically Q.
Proof. by move=> iPQ cP b /iPQ-/cP. Qed.
Lemma classic_EM P : classically (decidable P).
Proof.
by case=> // undecP; apply/undecP; right=> notP; apply/notF/undecP; left.
Qed.
Lemma classic_pick T P : classically ({x : T | P x} + (forall x, ~ P x)).
Proof.
case=> // undecP; apply/undecP; right=> x Px.
by apply/notF/undecP; left; exists x.
Qed.
Lemma classic_imply P Q : (P -> classically Q) -> classically (P -> Q).
Proof.
move=> iPQ []// notPQ; apply/notPQ=> /iPQ-cQ.
by case: notF; apply: cQ => hQ; apply: notPQ.
Qed.
(**
List notations for wider connectives; the Prop connectives have a fixed
width so as to avoid iterated destruction (we go up to width 5 for /\, and
width 4 for or). The bool connectives have arbitrary widths, but denote
expressions that associate to the RIGHT. This is consistent with the right
associativity of list expressions and thus more convenient in most proofs. **)
Inductive and3 (P1 P2 P3 : Prop) : Prop := And3 of P1 & P2 & P3.
Inductive and4 (P1 P2 P3 P4 : Prop) : Prop := And4 of P1 & P2 & P3 & P4.
Inductive and5 (P1 P2 P3 P4 P5 : Prop) : Prop :=
And5 of P1 & P2 & P3 & P4 & P5.
Inductive or3 (P1 P2 P3 : Prop) : Prop := Or31 of P1 | Or32 of P2 | Or33 of P3.
Inductive or4 (P1 P2 P3 P4 : Prop) : Prop :=
Or41 of P1 | Or42 of P2 | Or43 of P3 | Or44 of P4.
Notation "[ /\ P1 & P2 ]" := (and P1 P2) (only parsing) : type_scope.
Notation "[ /\ P1 , P2 & P3 ]" := (and3 P1 P2 P3) : type_scope.
Notation "[ /\ P1 , P2 , P3 & P4 ]" := (and4 P1 P2 P3 P4) : type_scope.
Notation "[ /\ P1 , P2 , P3 , P4 & P5 ]" := (and5 P1 P2 P3 P4 P5) : type_scope.
Notation "[ \/ P1 | P2 ]" := (or P1 P2) (only parsing) : type_scope.
Notation "[ \/ P1 , P2 | P3 ]" := (or3 P1 P2 P3) : type_scope.
Notation "[ \/ P1 , P2 , P3 | P4 ]" := (or4 P1 P2 P3 P4) : type_scope.
Notation "[ && b1 & c ]" := (b1 && c) (only parsing) : bool_scope.
Notation "[ && b1 , b2 , .. , bn & c ]" := (b1 && (b2 && .. (bn && c) .. ))
: bool_scope.
Notation "[ || b1 | c ]" := (b1 || c) (only parsing) : bool_scope.
Notation "[ || b1 , b2 , .. , bn | c ]" := (b1 || (b2 || .. (bn || c) .. ))
: bool_scope.
Notation "[ ==> b1 , b2 , .. , bn => c ]" :=
(b1 ==> (b2 ==> .. (bn ==> c) .. )) : bool_scope.
Notation "[ ==> b1 => c ]" := (b1 ==> c) (only parsing) : bool_scope.
Section AllAnd.
Variables (T : Type) (P1 P2 P3 P4 P5 : T -> Prop).
Local Notation a P := (forall x, P x).
Lemma all_and2 : implies (forall x, [/\ P1 x & P2 x]) [/\ a P1 & a P2].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and3 : implies (forall x, [/\ P1 x, P2 x & P3 x])
[/\ a P1, a P2 & a P3].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and4 : implies (forall x, [/\ P1 x, P2 x, P3 x & P4 x])
[/\ a P1, a P2, a P3 & a P4].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and5 : implies (forall x, [/\ P1 x, P2 x, P3 x, P4 x & P5 x])
[/\ a P1, a P2, a P3, a P4 & a P5].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
End AllAnd.
Arguments all_and2 {T P1 P2}.
Arguments all_and3 {T P1 P2 P3}.
Arguments all_and4 {T P1 P2 P3 P4}.
Arguments all_and5 {T P1 P2 P3 P4 P5}.
Lemma pair_andP P Q : P /\ Q <-> P * Q. Proof. by split; case. Qed.
Section ReflectConnectives.
Variable b1 b2 b3 b4 b5 : bool.
Lemma idP : reflect b1 b1.
Proof. by case b1; constructor. Qed.
Lemma boolP : alt_spec b1 b1 b1.
Proof. exact: (altP idP). Qed.
Lemma idPn : reflect (~~ b1) (~~ b1).
Proof. by case b1; constructor. Qed.
Lemma negP : reflect (~ b1) (~~ b1).
Proof. by case b1; constructor; auto. Qed.
Lemma negPn : reflect b1 (~~ ~~ b1).
Proof. by case b1; constructor. Qed.
Lemma negPf : reflect (b1 = false) (~~ b1).
Proof. by case b1; constructor. Qed.
Lemma andP : reflect (b1 /\ b2) (b1 && b2).
Proof. by case b1; case b2; constructor=> //; case. Qed.
Lemma and3P : reflect [/\ b1, b2 & b3] [&& b1, b2 & b3].
Proof. by case b1; case b2; case b3; constructor; try by case. Qed.
Lemma and4P : reflect [/\ b1, b2, b3 & b4] [&& b1, b2, b3 & b4].
Proof. by case b1; case b2; case b3; case b4; constructor; try by case. Qed.
Lemma and5P : reflect [/\ b1, b2, b3, b4 & b5] [&& b1, b2, b3, b4 & b5].
Proof.
by case b1; case b2; case b3; case b4; case b5; constructor; try by case.
Qed.
Lemma orP : reflect (b1 \/ b2) (b1 || b2).
Proof. by case b1; case b2; constructor; auto; case. Qed.
Lemma or3P : reflect [\/ b1, b2 | b3] [|| b1, b2 | b3].
Proof.
case b1; first by constructor; constructor 1.
case b2; first by constructor; constructor 2.
case b3; first by constructor; constructor 3.
by constructor; case.
Qed.
Lemma or4P : reflect [\/ b1, b2, b3 | b4] [|| b1, b2, b3 | b4].
Proof.
case b1; first by constructor; constructor 1.
case b2; first by constructor; constructor 2.
case b3; first by constructor; constructor 3.
case b4; first by constructor; constructor 4.
by constructor; case.
Qed.
Lemma nandP : reflect (~~ b1 \/ ~~ b2) (~~ (b1 && b2)).
Proof. by case b1; case b2; constructor; auto; case; auto. Qed.
Lemma norP : reflect (~~ b1 /\ ~~ b2) (~~ (b1 || b2)).
Proof. by case b1; case b2; constructor; auto; case; auto. Qed.
Lemma implyP : reflect (b1 -> b2) (b1 ==> b2).
Proof. by case b1; case b2; constructor; auto. Qed.
End ReflectConnectives.
Arguments idP {b1}.
Arguments idPn {b1}.
Arguments negP {b1}.
Arguments negPn {b1}.
Arguments negPf {b1}.
Arguments andP {b1 b2}.
Arguments and3P {b1 b2 b3}.
Arguments and4P {b1 b2 b3 b4}.
Arguments and5P {b1 b2 b3 b4 b5}.
Arguments orP {b1 b2}.
Arguments or3P {b1 b2 b3}.
Arguments or4P {b1 b2 b3 b4}.
Arguments nandP {b1 b2}.
Arguments norP {b1 b2}.
Arguments implyP {b1 b2}.
Prenex Implicits idP idPn negP negPn negPf.
Prenex Implicits andP and3P and4P and5P orP or3P or4P nandP norP implyP.
(** Shorter, more systematic names for the boolean connectives laws. **)
Lemma andTb : left_id true andb. Proof. by []. Qed.
Lemma andFb : left_zero false andb. Proof. by []. Qed.
Lemma andbT : right_id true andb. Proof. by case. Qed.
Lemma andbF : right_zero false andb. Proof. by case. Qed.
Lemma andbb : idempotent andb. Proof. by case. Qed.
Lemma andbC : commutative andb. Proof. by do 2!case. Qed.
Lemma andbA : associative andb. Proof. by do 3!case. Qed.
Lemma andbCA : left_commutative andb. Proof. by do 3!case. Qed.
Lemma andbAC : right_commutative andb. Proof. by do 3!case. Qed.
Lemma andbACA : interchange andb andb. Proof. by do 4!case. Qed.
Lemma orTb : forall b, true || b. Proof. by []. Qed.
Lemma orFb : left_id false orb. Proof. by []. Qed.
Lemma orbT : forall b, b || true. Proof. by case. Qed.
Lemma orbF : right_id false orb. Proof. by case. Qed.
Lemma orbb : idempotent orb. Proof. by case. Qed.
Lemma orbC : commutative orb. Proof. by do 2!case. Qed.
Lemma orbA : associative orb. Proof. by do 3!case. Qed.
Lemma orbCA : left_commutative orb. Proof. by do 3!case. Qed.
Lemma orbAC : right_commutative orb. Proof. by do 3!case. Qed.
Lemma orbACA : interchange orb orb. Proof. by do 4!case. Qed.
Lemma andbN b : b && ~~ b = false. Proof. by case: b. Qed.
Lemma andNb b : ~~ b && b = false. Proof. by case: b. Qed.
Lemma orbN b : b || ~~ b = true. Proof. by case: b. Qed.
Lemma orNb b : ~~ b || b = true. Proof. by case: b. Qed.
Lemma andb_orl : left_distributive andb orb. Proof. by do 3!case. Qed.
Lemma andb_orr : right_distributive andb orb. Proof. by do 3!case. Qed.
Lemma orb_andl : left_distributive orb andb. Proof. by do 3!case. Qed.
Lemma orb_andr : right_distributive orb andb. Proof. by do 3!case. Qed.
Lemma andb_idl (a b : bool) : (b -> a) -> a && b = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma andb_idr (a b : bool) : (a -> b) -> a && b = a.
Proof. by case: a; case: b => // ->. Qed.
Lemma andb_id2l (a b c : bool) : (a -> b = c) -> a && b = a && c.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma andb_id2r (a b c : bool) : (b -> a = c) -> a && b = c && b.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma orb_idl (a b : bool) : (a -> b) -> a || b = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma orb_idr (a b : bool) : (b -> a) -> a || b = a.
Proof. by case: a; case: b => // ->. Qed.
Lemma orb_id2l (a b c : bool) : (~~ a -> b = c) -> a || b = a || c.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma orb_id2r (a b c : bool) : (~~ b -> a = c) -> a || b = c || b.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma negb_and (a b : bool) : ~~ (a && b) = ~~ a || ~~ b.
Proof. by case: a; case: b. Qed.
Lemma negb_or (a b : bool) : ~~ (a || b) = ~~ a && ~~ b.
Proof. by case: a; case: b. Qed.
(** Pseudo-cancellation -- i.e, absorption **)
Lemma andbK a b : a && b || a = a. Proof. by case: a; case: b. Qed.
Lemma andKb a b : a || b && a = a. Proof. by case: a; case: b. Qed.
Lemma orbK a b : (a || b) && a = a. Proof. by case: a; case: b. Qed.
Lemma orKb a b : a && (b || a) = a. Proof. by case: a; case: b. Qed.
(** Imply **)
Lemma implybT b : b ==> true. Proof. by case: b. Qed.
Lemma implybF b : (b ==> false) = ~~ b. Proof. by case: b. Qed.
Lemma implyFb b : false ==> b. Proof. by []. Qed.
Lemma implyTb b : (true ==> b) = b. Proof. by []. Qed.
Lemma implybb b : b ==> b. Proof. by case: b. Qed.
Lemma negb_imply a b : ~~ (a ==> b) = a && ~~ b.
Proof. by case: a; case: b. Qed.
Lemma implybE a b : (a ==> b) = ~~ a || b.
Proof. by case: a; case: b. Qed.
Lemma implyNb a b : (~~ a ==> b) = a || b.
Proof. by case: a; case: b. Qed.
Lemma implybN a b : (a ==> ~~ b) = (b ==> ~~ a).
Proof. by case: a; case: b. Qed.
Lemma implybNN a b : (~~ a ==> ~~ b) = b ==> a.
Proof. by case: a; case: b. Qed.
Lemma implyb_idl (a b : bool) : (~~ a -> b) -> (a ==> b) = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma implyb_idr (a b : bool) : (b -> ~~ a) -> (a ==> b) = ~~ a.
Proof. by case: a; case: b => // ->. Qed.
Lemma implyb_id2l (a b c : bool) : (a -> b = c) -> (a ==> b) = (a ==> c).
Proof. by case: a; case: b; case: c => // ->. Qed.
(** Addition (xor) **)
Lemma addFb : left_id false addb. Proof. by []. Qed.
Lemma addbF : right_id false addb. Proof. by case. Qed.
Lemma addbb : self_inverse false addb. Proof. by case. Qed.
Lemma addbC : commutative addb. Proof. by do 2!case. Qed.
Lemma addbA : associative addb. Proof. by do 3!case. Qed.
Lemma addbCA : left_commutative addb. Proof. by do 3!case. Qed.
Lemma addbAC : right_commutative addb. Proof. by do 3!case. Qed.
Lemma addbACA : interchange addb addb. Proof. by do 4!case. Qed.
Lemma andb_addl : left_distributive andb addb. Proof. by do 3!case. Qed.
Lemma andb_addr : right_distributive andb addb. Proof. by do 3!case. Qed.
Lemma addKb : left_loop id addb. Proof. by do 2!case. Qed.
Lemma addbK : right_loop id addb. Proof. by do 2!case. Qed.
Lemma addIb : left_injective addb. Proof. by do 3!case. Qed.
Lemma addbI : right_injective addb. Proof. by do 3!case. Qed.
Lemma addTb b : true (+) b = ~~ b. Proof. by []. Qed.
Lemma addbT b : b (+) true = ~~ b. Proof. by case: b. Qed.
Lemma addbN a b : a (+) ~~ b = ~~ (a (+) b).
Proof. by case: a; case: b. Qed.
Lemma addNb a b : ~~ a (+) b = ~~ (a (+) b).
Proof. by case: a; case: b. Qed.
Lemma addbP a b : reflect (~~ a = b) (a (+) b).
Proof. by case: a; case: b; constructor. Qed.
Arguments addbP {a b}.
(**
Resolution tactic for blindly weeding out common terms from boolean
equalities. When faced with a goal of the form (andb/orb/addb b1 b2) = b3
they will try to locate b1 in b3 and remove it. This can fail! **)
Ltac bool_congr :=
match goal with
| |- (?X1 && ?X2 = ?X3) => first
[ symmetry; rewrite -1?(andbC X1) -?(andbCA X1); congr 1 (andb X1); symmetry
| case: (X1); [ rewrite ?andTb ?andbT // | by rewrite ?andbF /= ] ]
| |- (?X1 || ?X2 = ?X3) => first
[ symmetry; rewrite -1?(orbC X1) -?(orbCA X1); congr 1 (orb X1); symmetry
| case: (X1); [ by rewrite ?orbT //= | rewrite ?orFb ?orbF ] ]
| |- (?X1 (+) ?X2 = ?X3) =>
symmetry; rewrite -1?(addbC X1) -?(addbCA X1); congr 1 (addb X1); symmetry
| |- (~~ ?X1 = ?X2) => congr 1 negb
end.
(**
Predicates, i.e., packaged functions to bool.
- pred T, the basic type for predicates over a type T, is simply an alias
for T -> bool.
We actually distinguish two kinds of predicates, which we call applicative
and collective, based on the syntax used to test them at some x in T:
- For an applicative predicate P, one uses prefix syntax:
P x
Also, most operations on applicative predicates use prefix syntax as
well (e.g., predI P Q).
- For a collective predicate A, one uses infix syntax:
x \in A
and all operations on collective predicates use infix syntax as well
(e.g., #[#predI A & B#]#).
There are only two kinds of applicative predicates:
- pred T, the alias for T -> bool mentioned above
- simpl_pred T, an alias for simpl_fun T bool with a coercion to pred T
that auto-simplifies on application (see ssrfun).
On the other hand, the set of collective predicate types is open-ended via
- predType T, a Structure that can be used to put Canonical collective
predicate interpretation on other types, such as lists, tuples,
finite sets, etc.
Indeed, we define such interpretations for applicative predicate types,
which can therefore also be used with the infix syntax, e.g.,
x \in predI P Q
Moreover these infix forms are convertible to their prefix counterpart
(e.g., predI P Q x which in turn simplifies to P x && Q x). The converse
is not true, however; collective predicate types cannot, in general, be
used applicatively, because of restrictions on implicit coercions.
However, we do define an explicit generic coercion
- mem : forall (pT : predType), pT -> mem_pred T
where mem_pred T is a variant of simpl_pred T that preserves the infix
syntax, i.e., mem A x auto-simplifies to x \in A.
Indeed, the infix "collective" operators are notation for a prefix
operator with arguments of type mem_pred T or pred T, applied to coerced
collective predicates, e.g.,
Notation "x \in A" := (in_mem x (mem A)).
This prevents the variability in the predicate type from interfering with
the application of generic lemmas. Moreover this also makes it much easier
to define generic lemmas, because the simplest type -- pred T -- can be
used as the type of generic collective predicates, provided one takes care
not to use it applicatively; this avoids the burden of having to declare a
different predicate type for each predicate parameter of each section or
lemma.
In detail, we ensure that the head normal form of mem A is always of the
eta-long MemPred (fun x => pA x) form, where pA is the pred interpretation of
A following its predType pT, i.e., the _expansion_ of topred A. For a pred T
evar ?P, (mem ?P) converts MemPred (fun x => ?P x), whose argument is a Miller
pattern and therefore always unify: unifying (mem A) with (mem ?P) always
yields ?P = pA, because the rigid constant MemPred aligns the unification.
Furthermore, we ensure pA is always either A or toP .... A where toP ... is
the expansion of @topred T pT, and toP is declared as a Coercion, so pA will
_display_ as A in either case, and the instances of @mem T (predPredType T) pA
appearing in the premises or right-hand side of a generic lemma parametrized
by ?P will be indistinguishable from @mem T pT A.
Users should take care not to inadvertently "strip" (mem A) down to the
coerced A, since this will expose the internal toP coercion: Coq could then
display terms A x that cannot be typed as such. The topredE lemma can be used
to restore the x \in A syntax in this case. While -topredE can conversely be
used to change x \in P into P x for an applicative P, it is safer to use the
inE, unfold_in or and memE lemmas instead, as they do not run the risk of
exposing internal coercions. As a consequence it is better to explicitly
cast a generic applicative predicate to simpl_pred using the SimplPred
constructor when it is used as a collective predicate (see, e.g.,
Lemma eq_big in bigop).
We also sometimes "instantiate" the predType structure by defining a
coercion to the sort of the predPredType structure, conveniently denoted
{pred T}. This works better for types such as {set T} that have subtypes that
coerce to them, since the same coercion will be inserted by the application
of mem, or of any lemma that expects a generic collective predicates with
type {pred T} := pred_sort (predPredType T) = pred T; thus {pred T} should be
the preferred type for generic collective predicate parameters.
This device also lets us turn any Type aT : predArgType into the total
predicate over that type, i.e., fun _: aT => true. This allows us to write,
e.g., ##|'I_n| for the cardinal of the (finite) type of integers less than n.
**)
(** Boolean predicates. *)
Definition pred T := T -> bool.
Identity Coercion fun_of_pred : pred >-> Funclass.
Definition subpred T (p1 p2 : pred T) := forall x : T, p1 x -> p2 x.
(* Notation for some manifest predicates. *)
Notation xpred0 := (fun=> false).
Notation xpredT := (fun=> true).
Notation xpredI := (fun (p1 p2 : pred _) x => p1 x && p2 x).
Notation xpredU := (fun (p1 p2 : pred _) x => p1 x || p2 x).
Notation xpredC := (fun (p : pred _) x => ~~ p x).
Notation xpredD := (fun (p1 p2 : pred _) x => ~~ p2 x && p1 x).
Notation xpreim := (fun f (p : pred _) x => p (f x)).
(** The packed class interface for pred-like types. **)
Structure predType T :=
PredType {pred_sort :> Type; topred : pred_sort -> pred T}.
Definition clone_pred T U :=
fun pT & @pred_sort T pT -> U =>
fun toP (pT' := @PredType T U toP) & phant_id pT' pT => pT'.
Notation "[ 'predType' 'of' T ]" := (@clone_pred _ T _ id _ id) : form_scope.
Canonical predPredType T := PredType (@id (pred T)).
Canonical boolfunPredType T := PredType (@id (T -> bool)).
(** The type of abstract collective predicates.
While {pred T} is contertible to pred T, it presents the pred_sort coercion
class, which crucially does _not_ coerce to Funclass. Term whose type P coerces
to {pred T} cannot be applied to arguments, but they _can_ be used as if P
had a canonical predType instance, as the coercion will be inserted if the
unification P =~= pred_sort ?pT fails, changing the problem into the trivial
{pred T} =~= pred_sort ?pT (solution ?pT := predPredType P).
Additional benefits of this approach are that any type coercing to P will
also inherit this behaviour, and that the coercion will be apparent in the
elaborated expression. The latter may be important if the coercion is also
a canonical structure projector - see mathcomp/fingroup/fingroup.v. The
main drawback of implementing predType by coercion in this way is that the
type of the value must be known when the unification constraint is imposed:
if we only register the constraint and then later discover later that the
expression had type P it will be too late of insert a coercion, whereas a
canonical instance of predType fo P would have solved the deferred constraint.
Finally, definitions, lemmas and sections should use type {pred T} for
their generic collective type parameters, as this will make it possible to
apply such definitions and lemmas directly to values of types that implement
predType by coercion to {pred T} (values of types that implement predType
without coercing to {pred T} will have to be coerced explicitly using topred).
**)
Notation "{ 'pred' T }" := (pred_sort (predPredType T)) : type_scope.
(** The type of self-simplifying collective predicates. **)
Definition simpl_pred T := simpl_fun T bool.
Definition SimplPred {T} (p : pred T) : simpl_pred T := SimplFun p.
(** Some simpl_pred constructors. **)
Definition pred0 {T} := @SimplPred T xpred0.
Definition predT {T} := @SimplPred T xpredT.
Definition predI {T} (p1 p2 : pred T) := SimplPred (xpredI p1 p2).
Definition predU {T} (p1 p2 : pred T) := SimplPred (xpredU p1 p2).
Definition predC {T} (p : pred T) := SimplPred (xpredC p).
Definition predD {T} (p1 p2 : pred T) := SimplPred (xpredD p1 p2).
Definition preim {aT rT} (f : aT -> rT) (d : pred rT) := SimplPred (xpreim f d).
Notation "[ 'pred' : T | E ]" := (SimplPred (fun _ : T => E%B)) : fun_scope.
Notation "[ 'pred' x | E ]" := (SimplPred (fun x => E%B)) : fun_scope.
Notation "[ 'pred' x | E1 & E2 ]" := [pred x | E1 && E2 ] : fun_scope.
Notation "[ 'pred' x : T | E ]" :=
(SimplPred (fun x : T => E%B)) (only parsing) : fun_scope.
Notation "[ 'pred' x : T | E1 & E2 ]" :=
[pred x : T | E1 && E2 ] (only parsing) : fun_scope.
(** Coercions for simpl_pred.
As simpl_pred T values are used both applicatively and collectively we
need simpl_pred to coerce to both pred T _and_ {pred T}. However it is
undesirable to have two distinct constants for what are essentially identical
coercion functions, as this confuses the SSReflect keyed matching algorithm.
While the Coq Coercion declarations appear to disallow such Coercion aliasing,
it is possible to work around this limitation with a combination of modules
and functors, which we do below.
In addition we also give a predType instance for simpl_pred, which will
be preferred to the {pred T} coercion to solve simpl_pred T =~= pred_sort ?pT
constraints; not however that the pred_of_simpl coercion _will_ be used
when a simpl_pred T is passed as a {pred T}, since the simplPredType T
structure for simpl_pred T is _not_ convertible to predPredType T. **)
Module PredOfSimpl.
Definition coerce T (sp : simpl_pred T) : pred T := fun_of_simpl sp.
End PredOfSimpl.
Notation pred_of_simpl := PredOfSimpl.coerce.
Coercion pred_of_simpl : simpl_pred >-> pred.
Canonical simplPredType T := PredType (@pred_of_simpl T).
Module Type PredSortOfSimplSignature.
Parameter coerce : forall T, simpl_pred T -> {pred T}.
End PredSortOfSimplSignature.
Module DeclarePredSortOfSimpl (PredSortOfSimpl : PredSortOfSimplSignature).
Coercion PredSortOfSimpl.coerce : simpl_pred >-> pred_sort.
End DeclarePredSortOfSimpl.
Module Export PredSortOfSimplCoercion := DeclarePredSortOfSimpl PredOfSimpl.
(** Type to pred coercion.
This lets us use types of sort predArgType as a synonym for their universal
predicate. We define this predicate as a simpl_pred T rather than a pred T or
a {pred T} so that /= and inE reduce (T x) and x \in T to true, respectively.
Unfortunately, this can't be used for existing types like bool whose sort
is already fixed (at least, not without redefining bool, true, false and
all bool operations and lemmas); we provide syntax to recast a given type
in predArgType as a workaround. **)
Definition predArgType := Type.
Bind Scope type_scope with predArgType.
Identity Coercion sort_of_predArgType : predArgType >-> Sortclass.
Coercion pred_of_argType (T : predArgType) : simpl_pred T := predT.
Notation "{ : T }" := (T%type : predArgType) : type_scope.
(** Boolean relations.
Simplifying relations follow the coding pattern of 2-argument simplifying
functions: the simplifying type constructor is applied to the _last_
argument. This design choice will let the in_simpl componenent of inE expand
membership in simpl_rel as well. We provide an explicit coercion to rel T
to avoid eta-expansion during coercion; this coercion self-simplifies so it
should be invisible.
**)
Definition rel T := T -> pred T.
Identity Coercion fun_of_rel : rel >-> Funclass.
Definition subrel T (r1 r2 : rel T) := forall x y : T, r1 x y -> r2 x y.
Definition simpl_rel T := T -> simpl_pred T.
Coercion rel_of_simpl T (sr : simpl_rel T) : rel T := fun x : T => sr x.
Arguments rel_of_simpl {T} sr x /.
Notation xrelU := (fun (r1 r2 : rel _) x y => r1 x y || r2 x y).
Notation xrelpre := (fun f (r : rel _) x y => r (f x) (f y)).
Definition SimplRel {T} (r : rel T) : simpl_rel T := fun x => SimplPred (r x).
Definition relU {T} (r1 r2 : rel T) := SimplRel (xrelU r1 r2).
Definition relpre {aT rT} (f : aT -> rT) (r : rel rT) := SimplRel (xrelpre f r).
Notation "[ 'rel' x y | E ]" := (SimplRel (fun x y => E%B)) : fun_scope.
Notation "[ 'rel' x y : T | E ]" :=
(SimplRel (fun x y : T => E%B)) (only parsing) : fun_scope.
Lemma subrelUl T (r1 r2 : rel T) : subrel r1 (relU r1 r2).
Proof. by move=> x y r1xy; apply/orP; left. Qed.
Lemma subrelUr T (r1 r2 : rel T) : subrel r2 (relU r1 r2).
Proof. by move=> x y r2xy; apply/orP; right. Qed.
(** Variant of simpl_pred specialised to the membership operator. **)
Variant mem_pred T := Mem of pred T.
(**
We mainly declare pred_of_mem as a coercion so that it is not displayed.
Similarly to pred_of_simpl, it will usually not be inserted by type
inference, as all mem_pred mp =~= pred_sort ?pT unification problems will
be solve by the memPredType instance below; pred_of_mem will however
be used if a mem_pred T is used as a {pred T}, which is desirable as it
will avoid a redundant mem in a collective, e.g., passing (mem A) to a lemma
exception a generic collective predicate p : {pred T} and premise x \in P
will display a subgoal x \in A rathere than x \in mem A.
Conversely, pred_of_mem will _not_ if it is used id (mem A) is used
applicatively or as a pred T; there the simpl_of_mem coercion defined below
will be used, resulting in a subgoal that displays as mem A x by simplifies
to x \in A.
**)
Coercion pred_of_mem {T} mp : {pred T} := let: Mem p := mp in [eta p].
Canonical memPredType T := PredType (@pred_of_mem T).
Definition in_mem {T} (x : T) mp := pred_of_mem mp x.
Definition eq_mem {T} mp1 mp2 := forall x : T, in_mem x mp1 = in_mem x mp2.
Definition sub_mem {T} mp1 mp2 := forall x : T, in_mem x mp1 -> in_mem x mp2.
Arguments in_mem {T} x mp : simpl never.
Typeclasses Opaque eq_mem.
Typeclasses Opaque sub_mem.
(** The [simpl_of_mem; pred_of_simpl] path provides a new mem_pred >-> pred
coercion, but does _not_ override the pred_of_mem : mem_pred >-> pred_sort
explicit coercion declaration above.
**)
Coercion simpl_of_mem {T} mp := SimplPred (fun x : T => in_mem x mp).
Lemma sub_refl T (mp : mem_pred T) : sub_mem mp mp. Proof. by []. Qed.
Arguments sub_refl {T mp} [x] mp_x.
(**
It is essential to interlock the production of the Mem constructor inside
the branch of the predType match, to ensure that unifying mem A with
Mem [eta ?p] sets ?p := toP A (or ?p := P if toP = id and A = [eta P]),
rather than topred pT A, had we put mem A := Mem (topred A).
**)
Definition mem T (pT : predType T) : pT -> mem_pred T :=
let: PredType toP := pT in fun A => Mem [eta toP A].
Arguments mem {T pT} A : rename, simpl never.
Notation "x \in A" := (in_mem x (mem A)) : bool_scope.
Notation "x \in A" := (in_mem x (mem A)) : bool_scope.
Notation "x \notin A" := (~~ (x \in A)) : bool_scope.
Notation "A =i B" := (eq_mem (mem A) (mem B)) : type_scope.
Notation "{ 'subset' A <= B }" := (sub_mem (mem A) (mem B)) : type_scope.
Notation "[ 'mem' A ]" :=
(pred_of_simpl (simpl_of_mem (mem A))) (only parsing) : fun_scope.
Notation "[ 'predI' A & B ]" := (predI [mem A] [mem B]) : fun_scope.
Notation "[ 'predU' A & B ]" := (predU [mem A] [mem B]) : fun_scope.
Notation "[ 'predD' A & B ]" := (predD [mem A] [mem B]) : fun_scope.
Notation "[ 'predC' A ]" := (predC [mem A]) : fun_scope.
Notation "[ 'preim' f 'of' A ]" := (preim f [mem A]) : fun_scope.
Notation "[ 'pred' x 'in' A ]" := [pred x | x \in A] : fun_scope.
Notation "[ 'pred' x 'in' A | E ]" := [pred x | x \in A & E] : fun_scope.
Notation "[ 'pred' x 'in' A | E1 & E2 ]" :=
[pred x | x \in A & E1 && E2 ] : fun_scope.
Notation "[ 'rel' x y 'in' A & B | E ]" :=
[rel x y | (x \in A) && (y \in B) && E] : fun_scope.
Notation "[ 'rel' x y 'in' A & B ]" :=
[rel x y | (x \in A) && (y \in B)] : fun_scope.
Notation "[ 'rel' x y 'in' A | E ]" := [rel x y in A & A | E] : fun_scope.
Notation "[ 'rel' x y 'in' A ]" := [rel x y in A & A] : fun_scope.
(** Aliases of pred T that let us tag instances of simpl_pred as applicative
or collective, via bespoke coercions. This tagging will give control over
the simplification behaviour of inE and othe rewriting lemmas below.
For this control to work it is crucial that collective_of_simpl _not_
be convertible to either applicative_of_simpl or pred_of_simpl. Indeed
they differ here by a commutattive conversion (of the match and lambda).
**)
Definition applicative_pred T := pred T.
Definition collective_pred T := pred T.
Coercion applicative_pred_of_simpl T (sp : simpl_pred T) : applicative_pred T :=
fun_of_simpl sp.
Coercion collective_pred_of_simpl T (sp : simpl_pred T) : collective_pred T :=
let: SimplFun p := sp in p.
(** Explicit simplification rules for predicate application and membership. **)
Section PredicateSimplification.
Variables T : Type.
Implicit Types (p : pred T) (pT : predType T) (sp : simpl_pred T).
Implicit Types (mp : mem_pred T).
(**
The following four bespoke structures provide fine-grained control over
matching the various predicate forms. While all four follow a common pattern
of using a canonical projection to match a particular form of predicate
(in pred T, simpl_pred, mem_pred and mem_pred, respectively), and display
the matched predicate in the structure type, each is in fact used for a
different, specific purpose:
- registered_applicative_pred: this user-facing structure is used to
declare values of type pred T meant to be used applicatively. The
structure parameter merely displays this same value, and is used to avoid
undesirable, visible occurrence of the structure in the right hand side
of rewrite rules such as app_predE.
There is a canonical instance of registered_applicative_pred for values
of the applicative_of_simpl coercion, which handles the
Definition Apred : applicative_pred T := [pred x | ...] idiom.
This instance is mainly intended for the in_applicative component of inE,
in conjunction with manifest_mem_pred and applicative_mem_pred.
- manifest_simpl_pred: the only instance of this structure matches manifest
simpl_pred values of the form SimplPred p, displaying p in the structure
type. This structure is used in in_simpl to detect and selectively expand
collective predicates of this form. An explicit SimplPred p pattern would
_NOT_ work for this purpose, as then the left-hand side of in_simpl would
reduce to in_mem ?x (Mem [eta ?p]) and would thus match _any_ instance
of \in, not just those arising from a manifest simpl_pred.
- manifest_mem_pred: similar to manifest_simpl_pred, the one instance of this
structure matches manifest mem_pred values of the form Mem [eta ?p]. The
purpose is different however: to match and display in ?p the actual
predicate appearing in an ... \in ... expression matched by the left hand
side of the in_applicative component of inE; then
- applicative_mem_pred is a telescope refinement of manifest_mem_pred p with
a default constructor that checks that the predicate p is the value of a
registered_applicative_pred; any unfolding occurring during this check
does _not_ affect the value of p passed to in_applicative, since that
has been fixed earlier by the manifest_mem_pred match. In particular the
definition of a predicate using the applicative_pred_of_simpl idiom above
will not be expanded - this very case is the reason in_applicative uses
a mem_pred telescope in its left hand side. The more straightforward
?x \in applicative_pred_value ?ap (equivalent to in_mem ?x (Mem ?ap))
with ?ap : registered_applicative_pred ?p would set ?p := [pred x | ...]
rather than ?p := Apred in the example above.
Also note that the in_applicative component of inE must be come before the
in_simpl one, as the latter also matches terms of the form x \in Apred.
Finally, no component of inE matches x \in Acoll, when
Definition Acoll : collective_pred T := [pred x | ...].
as the collective_pred_of_simpl is _not_ convertible to pred_of_simpl. **)
Structure registered_applicative_pred p := RegisteredApplicativePred {
applicative_pred_value :> pred T;
_ : applicative_pred_value = p
}.
Definition ApplicativePred p := RegisteredApplicativePred (erefl p).
Canonical applicative_pred_applicative sp :=
ApplicativePred (applicative_pred_of_simpl sp).
Structure manifest_simpl_pred p := ManifestSimplPred {
simpl_pred_value :> simpl_pred T;
_ : simpl_pred_value = SimplPred p
}.
Canonical expose_simpl_pred p := ManifestSimplPred (erefl (SimplPred p)).
Structure manifest_mem_pred p := ManifestMemPred {
mem_pred_value :> mem_pred T;
_ : mem_pred_value = Mem [eta p]
}.
Canonical expose_mem_pred p := ManifestMemPred (erefl (Mem [eta p])).
Structure applicative_mem_pred p :=
ApplicativeMemPred {applicative_mem_pred_value :> manifest_mem_pred p}.
Canonical check_applicative_mem_pred p (ap : registered_applicative_pred p) :=
[eta @ApplicativeMemPred ap].
Lemma mem_topred pT (pp : pT) : mem (topred pp) = mem pp.
Proof. by case: pT pp. Qed.
Lemma topredE pT x (pp : pT) : topred pp x = (x \in pp).
Proof. by rewrite -mem_topred. Qed.
Lemma app_predE x p (ap : registered_applicative_pred p) : ap x = (x \in p).
Proof. by case: ap => _ /= ->. Qed.
Lemma in_applicative x p (amp : applicative_mem_pred p) : in_mem x amp = p x.
Proof. by case: amp => -[_ /= ->]. Qed.
Lemma in_collective x p (msp : manifest_simpl_pred p) :
(x \in collective_pred_of_simpl msp) = p x.
Proof. by case: msp => _ /= ->. Qed.
Lemma in_simpl x p (msp : manifest_simpl_pred p) :
in_mem x (Mem [eta pred_of_simpl msp]) = p x.
Proof. by case: msp => _ /= ->. Qed.
(**
Because of the explicit eta expansion in the left-hand side, this lemma
should only be used in the left-to-right direction.
**)
Lemma unfold_in x p : (x \in ([eta p] : pred T)) = p x.
Proof. by []. Qed.
Lemma simpl_predE p : SimplPred p =1 p.
Proof. by []. Qed.
Definition inE := (in_applicative, in_simpl, simpl_predE). (* to be extended *)
Lemma mem_simpl sp : mem sp = sp :> pred T.
Proof. by []. Qed.
Definition memE := mem_simpl. (* could be extended *)
Lemma mem_mem mp :
(mem mp = mp) * (mem (mp : simpl_pred T) = mp) * (mem (mp : pred T) = mp).
Proof. by case: mp. Qed.
End PredicateSimplification.
(** Qualifiers and keyed predicates. **)
Variant qualifier (q : nat) T := Qualifier of {pred T}.
Coercion has_quality n T (q : qualifier n T) : {pred T} :=
fun x => let: Qualifier _ p := q in p x.
Arguments has_quality n {T}.
Lemma qualifE n T p x : (x \in @Qualifier n T p) = p x. Proof. by []. Qed.
Notation "x \is A" := (x \in has_quality 0 A) : bool_scope.
Notation "x \is 'a' A" := (x \in has_quality 1 A) : bool_scope.
Notation "x \is 'an' A" := (x \in has_quality 2 A) : bool_scope.
Notation "x \isn't A" := (x \notin has_quality 0 A) : bool_scope.
Notation "x \isn't 'a' A" := (x \notin has_quality 1 A) : bool_scope.
Notation "x \isn't 'an' A" := (x \notin has_quality 2 A) : bool_scope.
Notation "[ 'qualify' x | P ]" := (Qualifier 0 (fun x => P%B)) : form_scope.
Notation "[ 'qualify' x : T | P ]" :=
(Qualifier 0 (fun x : T => P%B)) (only parsing) : form_scope.
Notation "[ 'qualify' 'a' x | P ]" := (Qualifier 1 (fun x => P%B)) : form_scope.
Notation "[ 'qualify' 'a' x : T | P ]" :=
(Qualifier 1 (fun x : T => P%B)) (only parsing) : form_scope.
Notation "[ 'qualify' 'an' x | P ]" :=
(Qualifier 2 (fun x => P%B)) : form_scope.
Notation "[ 'qualify' 'an' x : T | P ]" :=
(Qualifier 2 (fun x : T => P%B)) (only parsing) : form_scope.
(** Keyed predicates: support for property-bearing predicate interfaces. **)
Section KeyPred.
Variable T : Type.
#[universes(template)]
Variant pred_key (p : {pred T}) := DefaultPredKey.
Variable p : {pred T}.
Structure keyed_pred (k : pred_key p) :=
PackKeyedPred {unkey_pred :> {pred T}; _ : unkey_pred =i p}.
Variable k : pred_key p.
Definition KeyedPred := @PackKeyedPred k p (frefl _).
Variable k_p : keyed_pred k.
Lemma keyed_predE : k_p =i p. Proof. by case: k_p. Qed.
(**
Instances that strip the mem cast; the first one has "pred_of_mem" as its
projection head value, while the second has "pred_of_simpl". The latter
has the side benefit of preempting accidental misdeclarations.
Note: pred_of_mem is the registered mem >-> pred_sort coercion, while
[simpl_of_mem; pred_of_simpl] is the mem >-> pred >=> Funclass coercion. We
must write down the coercions explicitly as the Canonical head constant
computation does not strip casts. **)
Canonical keyed_mem :=
@PackKeyedPred k (pred_of_mem (mem k_p)) keyed_predE.
Canonical keyed_mem_simpl :=
@PackKeyedPred k (pred_of_simpl (mem k_p)) keyed_predE.
End KeyPred.
Local Notation in_unkey x S := (x \in @unkey_pred _ S _ _) (only parsing).
Notation "x \in S" := (in_unkey x S) (only printing) : bool_scope.
Section KeyedQualifier.
Variables (T : Type) (n : nat) (q : qualifier n T).
Structure keyed_qualifier (k : pred_key q) :=
PackKeyedQualifier {unkey_qualifier; _ : unkey_qualifier = q}.
Definition KeyedQualifier k := PackKeyedQualifier k (erefl q).
Variables (k : pred_key q) (k_q : keyed_qualifier k).
Fact keyed_qualifier_suproof : unkey_qualifier k_q =i q.
Proof. by case: k_q => /= _ ->. Qed.
Canonical keyed_qualifier_keyed := PackKeyedPred k keyed_qualifier_suproof.
End KeyedQualifier.
Notation "x \is A" :=
(in_unkey x (has_quality 0 A)) (only printing) : bool_scope.
Notation "x \is 'a' A" :=
(in_unkey x (has_quality 1 A)) (only printing) : bool_scope.
Notation "x \is 'an' A" :=
(in_unkey x (has_quality 2 A)) (only printing) : bool_scope.
Module DefaultKeying.
Canonical default_keyed_pred T p := KeyedPred (@DefaultPredKey T p).
Canonical default_keyed_qualifier T n (q : qualifier n T) :=
KeyedQualifier (DefaultPredKey q).
End DefaultKeying.
(** Skolemizing with conditions. **)
Lemma all_tag_cond_dep I T (C : pred I) U :
(forall x, T x) -> (forall x, C x -> {y : T x & U x y}) ->
{f : forall x, T x & forall x, C x -> U x (f x)}.
Proof.
move=> f0 fP; apply: all_tag (fun x y => C x -> U x y) _ => x.
by case Cx: (C x); [case/fP: Cx => y; exists y | exists (f0 x)].
Qed.
Lemma all_tag_cond I T (C : pred I) U :
T -> (forall x, C x -> {y : T & U x y}) ->
{f : I -> T & forall x, C x -> U x (f x)}.
Proof. by move=> y0; apply: all_tag_cond_dep. Qed.
Lemma all_sig_cond_dep I T (C : pred I) P :
(forall x, T x) -> (forall x, C x -> {y : T x | P x y}) ->
{f : forall x, T x | forall x, C x -> P x (f x)}.
Proof. by move=> f0 /(all_tag_cond_dep f0)[f]; exists f. Qed.
Lemma all_sig_cond I T (C : pred I) P :
T -> (forall x, C x -> {y : T | P x y}) ->
{f : I -> T | forall x, C x -> P x (f x)}.
Proof. by move=> y0; apply: all_sig_cond_dep. Qed.
Section RelationProperties.
(**
Caveat: reflexive should not be used to state lemmas, as auto and trivial
will not expand the constant. **)
Variable T : Type.
Variable R : rel T.
Definition total := forall x y, R x y || R y x.
Definition transitive := forall y x z, R x y -> R y z -> R x z.
Definition symmetric := forall x y, R x y = R y x.
Definition antisymmetric := forall x y, R x y && R y x -> x = y.
Definition pre_symmetric := forall x y, R x y -> R y x.
Lemma symmetric_from_pre : pre_symmetric -> symmetric.
Proof. by move=> symR x y; apply/idP/idP; apply: symR. Qed.
Definition reflexive := forall x, R x x.
Definition irreflexive := forall x, R x x = false.
Definition left_transitive := forall x y, R x y -> R x =1 R y.
Definition right_transitive := forall x y, R x y -> R^~ x =1 R^~ y.
Section PER.
Hypotheses (symR : symmetric) (trR : transitive).
Lemma sym_left_transitive : left_transitive.
Proof. by move=> x y Rxy z; apply/idP/idP; apply: trR; rewrite // symR. Qed.
Lemma sym_right_transitive : right_transitive.
Proof. by move=> x y /sym_left_transitive Rxy z; rewrite !(symR z) Rxy. Qed.
End PER.
(**
We define the equivalence property with prenex quantification so that it
can be localized using the {in ..., ..} form defined below. **)
Definition equivalence_rel := forall x y z, R z z * (R x y -> R x z = R y z).
Lemma equivalence_relP : equivalence_rel <-> reflexive /\ left_transitive.
Proof.
split=> [eqiR | [Rxx trR] x y z]; last by split=> [|/trR->].
by split=> [x | x y Rxy z]; [rewrite (eqiR x x x) | rewrite (eqiR x y z)].
Qed.
End RelationProperties.
Lemma rev_trans T (R : rel T) : transitive R -> transitive (fun x y => R y x).
Proof. by move=> trR x y z Ryx Rzy; apply: trR Rzy Ryx. Qed.
(** Property localization **)
Local Notation "{ 'all1' P }" := (forall x, P x : Prop) (at level 0).
Local Notation "{ 'all2' P }" := (forall x y, P x y : Prop) (at level 0).
Local Notation "{ 'all3' P }" := (forall x y z, P x y z: Prop) (at level 0).
Local Notation ph := (phantom _).
Section LocalProperties.
Variables T1 T2 T3 : Type.
Variables (d1 : mem_pred T1) (d2 : mem_pred T2) (d3 : mem_pred T3).
Local Notation ph := (phantom Prop).
Definition prop_for (x : T1) P & ph {all1 P} := P x.
Lemma forE x P phP : @prop_for x P phP = P x. Proof. by []. Qed.
Definition prop_in1 P & ph {all1 P} :=
forall x, in_mem x d1 -> P x.
Definition prop_in11 P & ph {all2 P} :=
forall x y, in_mem x d1 -> in_mem y d2 -> P x y.
Definition prop_in2 P & ph {all2 P} :=
forall x y, in_mem x d1 -> in_mem y d1 -> P x y.
Definition prop_in111 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d2 -> in_mem z d3 -> P x y z.
Definition prop_in12 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d2 -> in_mem z d2 -> P x y z.
Definition prop_in21 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d1 -> in_mem z d2 -> P x y z.
Definition prop_in3 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d1 -> in_mem z d1 -> P x y z.
Variable f : T1 -> T2.
Definition prop_on1 Pf P & phantom T3 (Pf f) & ph {all1 P} :=
forall x, in_mem (f x) d2 -> P x.
Definition prop_on2 Pf P & phantom T3 (Pf f) & ph {all2 P} :=
forall x y, in_mem (f x) d2 -> in_mem (f y) d2 -> P x y.
End LocalProperties.
Definition inPhantom := Phantom Prop.
Definition onPhantom {T} P (x : T) := Phantom Prop (P x).
Definition bijective_in aT rT (d : mem_pred aT) (f : aT -> rT) :=
exists2 g, prop_in1 d (inPhantom (cancel f g))
& prop_on1 d (Phantom _ (cancel g)) (onPhantom (cancel g) f).
Definition bijective_on aT rT (cd : mem_pred rT) (f : aT -> rT) :=
exists2 g, prop_on1 cd (Phantom _ (cancel f)) (onPhantom (cancel f) g)
& prop_in1 cd (inPhantom (cancel g f)).
Notation "{ 'for' x , P }" := (prop_for x (inPhantom P)) : type_scope.
Notation "{ 'in' d , P }" := (prop_in1 (mem d) (inPhantom P)) : type_scope.
Notation "{ 'in' d1 & d2 , P }" :=
(prop_in11 (mem d1) (mem d2) (inPhantom P)) : type_scope.
Notation "{ 'in' d & , P }" := (prop_in2 (mem d) (inPhantom P)) : type_scope.
Notation "{ 'in' d1 & d2 & d3 , P }" :=
(prop_in111 (mem d1) (mem d2) (mem d3) (inPhantom P)) : type_scope.
Notation "{ 'in' d1 & & d3 , P }" :=
(prop_in21 (mem d1) (mem d3) (inPhantom P)) : type_scope.
Notation "{ 'in' d1 & d2 & , P }" :=
(prop_in12 (mem d1) (mem d2) (inPhantom P)) : type_scope.
Notation "{ 'in' d & & , P }" := (prop_in3 (mem d) (inPhantom P)) : type_scope.
Notation "{ 'on' cd , P }" :=
(prop_on1 (mem cd) (inPhantom P) (inPhantom P)) : type_scope.
Notation "{ 'on' cd & , P }" :=
(prop_on2 (mem cd) (inPhantom P) (inPhantom P)) : type_scope.
Local Arguments onPhantom : clear scopes.
Notation "{ 'on' cd , P & g }" :=
(prop_on1 (mem cd) (Phantom (_ -> Prop) P) (onPhantom P g)) : type_scope.
Notation "{ 'in' d , 'bijective' f }" := (bijective_in (mem d) f) : type_scope.
Notation "{ 'on' cd , 'bijective' f }" :=
(bijective_on (mem cd) f) : type_scope.
(**
Weakening and monotonicity lemmas for localized predicates.
Note that using these lemmas in backward reasoning will force expansion of
the predicate definition, as Coq needs to expose the quantifier to apply
these lemmas. We define a few specialized variants to avoid this for some
of the ssrfun predicates. **)
Section LocalGlobal.
Variables T1 T2 T3 : predArgType.
Variables (D1 : {pred T1}) (D2 : {pred T2}) (D3 : {pred T3}).
Variables (d1 d1' : mem_pred T1) (d2 d2' : mem_pred T2) (d3 d3' : mem_pred T3).
Variables (f f' : T1 -> T2) (g : T2 -> T1) (h : T3).
Variables (P1 : T1 -> Prop) (P2 : T1 -> T2 -> Prop).
Variable P3 : T1 -> T2 -> T3 -> Prop.
Variable Q1 : (T1 -> T2) -> T1 -> Prop.
Variable Q1l : (T1 -> T2) -> T3 -> T1 -> Prop.
Variable Q2 : (T1 -> T2) -> T1 -> T1 -> Prop.
Hypothesis sub1 : sub_mem d1 d1'.
Hypothesis sub2 : sub_mem d2 d2'.
Hypothesis sub3 : sub_mem d3 d3'.
Lemma in1W : {all1 P1} -> {in D1, {all1 P1}}.
Proof. by move=> ? ?. Qed.
Lemma in2W : {all2 P2} -> {in D1 & D2, {all2 P2}}.
Proof. by move=> ? ?. Qed.
Lemma in3W : {all3 P3} -> {in D1 & D2 & D3, {all3 P3}}.
Proof. by move=> ? ?. Qed.
Lemma in1T : {in T1, {all1 P1}} -> {all1 P1}.
Proof. by move=> ? ?; auto. Qed.
Lemma in2T : {in T1 & T2, {all2 P2}} -> {all2 P2}.
Proof. by move=> ? ?; auto. Qed.
Lemma in3T : {in T1 & T2 & T3, {all3 P3}} -> {all3 P3}.
Proof. by move=> ? ?; auto. Qed.
Lemma sub_in1 (Ph : ph {all1 P1}) : prop_in1 d1' Ph -> prop_in1 d1 Ph.
Proof. by move=> allP x /sub1; apply: allP. Qed.
Lemma sub_in11 (Ph : ph {all2 P2}) : prop_in11 d1' d2' Ph -> prop_in11 d1 d2 Ph.
Proof. by move=> allP x1 x2 /sub1 d1x1 /sub2; apply: allP. Qed.
Lemma sub_in111 (Ph : ph {all3 P3}) :
prop_in111 d1' d2' d3' Ph -> prop_in111 d1 d2 d3 Ph.
Proof. by move=> allP x1 x2 x3 /sub1 d1x1 /sub2 d2x2 /sub3; apply: allP. Qed.
Let allQ1 f'' := {all1 Q1 f''}.
Let allQ1l f'' h' := {all1 Q1l f'' h'}.
Let allQ2 f'' := {all2 Q2 f''}.
Lemma on1W : allQ1 f -> {on D2, allQ1 f}. Proof. by move=> ? ?. Qed.
Lemma on1lW : allQ1l f h -> {on D2, allQ1l f & h}. Proof. by move=> ? ?. Qed.
Lemma on2W : allQ2 f -> {on D2 &, allQ2 f}. Proof. by move=> ? ?. Qed.
Lemma on1T : {on T2, allQ1 f} -> allQ1 f. Proof. by move=> ? ?; auto. Qed.
Lemma on1lT : {on T2, allQ1l f & h} -> allQ1l f h.
Proof. by move=> ? ?; auto. Qed.
Lemma on2T : {on T2 &, allQ2 f} -> allQ2 f.
Proof. by move=> ? ?; auto. Qed.
Lemma subon1 (Phf : ph (allQ1 f)) (Ph : ph (allQ1 f)) :
prop_on1 d2' Phf Ph -> prop_on1 d2 Phf Ph.
Proof. by move=> allQ x /sub2; apply: allQ. Qed.
Lemma subon1l (Phf : ph (allQ1l f)) (Ph : ph (allQ1l f h)) :
prop_on1 d2' Phf Ph -> prop_on1 d2 Phf Ph.
Proof. by move=> allQ x /sub2; apply: allQ. Qed.
Lemma subon2 (Phf : ph (allQ2 f)) (Ph : ph (allQ2 f)) :
prop_on2 d2' Phf Ph -> prop_on2 d2 Phf Ph.
Proof. by move=> allQ x y /sub2=> d2fx /sub2; apply: allQ. Qed.
Lemma can_in_inj : {in D1, cancel f g} -> {in D1 &, injective f}.
Proof. by move=> fK x y /fK{2}<- /fK{2}<- ->. Qed.
Lemma canLR_in x y : {in D1, cancel f g} -> y \in D1 -> x = f y -> g x = y.
Proof. by move=> fK D1y ->; rewrite fK. Qed.
Lemma canRL_in x y : {in D1, cancel f g} -> x \in D1 -> f x = y -> x = g y.
Proof. by move=> fK D1x <-; rewrite fK. Qed.
Lemma on_can_inj : {on D2, cancel f & g} -> {on D2 &, injective f}.
Proof. by move=> fK x y /fK{2}<- /fK{2}<- ->. Qed.
Lemma canLR_on x y : {on D2, cancel f & g} -> f y \in D2 -> x = f y -> g x = y.
Proof. by move=> fK D2fy ->; rewrite fK. Qed.
Lemma canRL_on x y : {on D2, cancel f & g} -> f x \in D2 -> f x = y -> x = g y.
Proof. by move=> fK D2fx <-; rewrite fK. Qed.
Lemma inW_bij : bijective f -> {in D1, bijective f}.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma onW_bij : bijective f -> {on D2, bijective f}.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma inT_bij : {in T1, bijective f} -> bijective f.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma onT_bij : {on T2, bijective f} -> bijective f.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma sub_in_bij (D1' : pred T1) :
{subset D1 <= D1'} -> {in D1', bijective f} -> {in D1, bijective f}.
Proof.
by move=> subD [g' fK g'K]; exists g' => x; move/subD; [apply: fK | apply: g'K].
Qed.
Lemma subon_bij (D2' : pred T2) :
{subset D2 <= D2'} -> {on D2', bijective f} -> {on D2, bijective f}.
Proof.
by move=> subD [g' fK g'K]; exists g' => x; move/subD; [apply: fK | apply: g'K].
Qed.
End LocalGlobal.
Lemma sub_in2 T d d' (P : T -> T -> Prop) :
sub_mem d d' -> forall Ph : ph {all2 P}, prop_in2 d' Ph -> prop_in2 d Ph.
Proof. by move=> /= sub_dd'; apply: sub_in11. Qed.
Lemma sub_in3 T d d' (P : T -> T -> T -> Prop) :
sub_mem d d' -> forall Ph : ph {all3 P}, prop_in3 d' Ph -> prop_in3 d Ph.
Proof. by move=> /= sub_dd'; apply: sub_in111. Qed.
Lemma sub_in12 T1 T d1 d1' d d' (P : T1 -> T -> T -> Prop) :
sub_mem d1 d1' -> sub_mem d d' ->
forall Ph : ph {all3 P}, prop_in12 d1' d' Ph -> prop_in12 d1 d Ph.
Proof. by move=> /= sub1 sub; apply: sub_in111. Qed.
Lemma sub_in21 T T3 d d' d3 d3' (P : T -> T -> T3 -> Prop) :
sub_mem d d' -> sub_mem d3 d3' ->
forall Ph : ph {all3 P}, prop_in21 d' d3' Ph -> prop_in21 d d3 Ph.
Proof. by move=> /= sub sub3; apply: sub_in111. Qed.
Lemma equivalence_relP_in T (R : rel T) (A : pred T) :
{in A & &, equivalence_rel R}
<-> {in A, reflexive R} /\ {in A &, forall x y, R x y -> {in A, R x =1 R y}}.
Proof.
split=> [eqiR | [Rxx trR] x y z *]; last by split=> [|/trR-> //]; apply: Rxx.
by split=> [x Ax|x y Ax Ay Rxy z Az]; [rewrite (eqiR x x) | rewrite (eqiR x y)].
Qed.
Section MonoHomoMorphismTheory.
Variables (aT rT sT : Type) (f : aT -> rT) (g : rT -> aT).
Variables (aP : pred aT) (rP : pred rT) (aR : rel aT) (rR : rel rT).
Lemma monoW : {mono f : x / aP x >-> rP x} -> {homo f : x / aP x >-> rP x}.
Proof. by move=> hf x ax; rewrite hf. Qed.
Lemma mono2W :
{mono f : x y / aR x y >-> rR x y} -> {homo f : x y / aR x y >-> rR x y}.
Proof. by move=> hf x y axy; rewrite hf. Qed.
Hypothesis fgK : cancel g f.
Lemma homoRL :
{homo f : x y / aR x y >-> rR x y} -> forall x y, aR (g x) y -> rR x (f y).
Proof. by move=> Hf x y /Hf; rewrite fgK. Qed.
Lemma homoLR :
{homo f : x y / aR x y >-> rR x y} -> forall x y, aR x (g y) -> rR (f x) y.
Proof. by move=> Hf x y /Hf; rewrite fgK. Qed.
Lemma homo_mono :
{homo f : x y / aR x y >-> rR x y} -> {homo g : x y / rR x y >-> aR x y} ->
{mono g : x y / rR x y >-> aR x y}.
Proof.
move=> mf mg x y; case: (boolP (rR _ _))=> [/mg //|].
by apply: contraNF=> /mf; rewrite !fgK.
Qed.
Lemma monoLR :
{mono f : x y / aR x y >-> rR x y} -> forall x y, rR (f x) y = aR x (g y).
Proof. by move=> mf x y; rewrite -{1}[y]fgK mf. Qed.
Lemma monoRL :
{mono f : x y / aR x y >-> rR x y} -> forall x y, rR x (f y) = aR (g x) y.
Proof. by move=> mf x y; rewrite -{1}[x]fgK mf. Qed.
Lemma can_mono :
{mono f : x y / aR x y >-> rR x y} -> {mono g : x y / rR x y >-> aR x y}.
Proof. by move=> mf x y /=; rewrite -mf !fgK. Qed.
End MonoHomoMorphismTheory.
Section MonoHomoMorphismTheory_in.
Variables (aT rT sT : predArgType) (f : aT -> rT) (g : rT -> aT).
Variable (aD : {pred aT}).
Variable (aP : pred aT) (rP : pred rT) (aR : rel aT) (rR : rel rT).
Notation rD := [pred x | g x \in aD].
Lemma monoW_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in aD &, {homo f : x y / aR x y >-> rR x y}}.
Proof. by move=> hf x y hx hy axy; rewrite hf. Qed.
Lemma mono2W_in :
{in aD, {mono f : x / aP x >-> rP x}} ->
{in aD, {homo f : x / aP x >-> rP x}}.
Proof. by move=> hf x hx ax; rewrite hf. Qed.
Hypothesis fgK_on : {on aD, cancel g & f}.
Lemma homoRL_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in rD & aD, forall x y, aR (g x) y -> rR x (f y)}.
Proof. by move=> Hf x y hx hy /Hf; rewrite fgK_on //; apply. Qed.
Lemma homoLR_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in aD & rD, forall x y, aR x (g y) -> rR (f x) y}.
Proof. by move=> Hf x y hx hy /Hf; rewrite fgK_on //; apply. Qed.
Lemma homo_mono_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in rD &, {homo g : x y / rR x y >-> aR x y}} ->
{in rD &, {mono g : x y / rR x y >-> aR x y}}.
Proof.
move=> mf mg x y hx hy; case: (boolP (rR _ _))=> [/mg //|]; first exact.
by apply: contraNF=> /mf; rewrite !fgK_on //; apply.
Qed.
Lemma monoLR_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in aD & rD, forall x y, rR (f x) y = aR x (g y)}.
Proof. by move=> mf x y hx hy; rewrite -{1}[y]fgK_on // mf. Qed.
Lemma monoRL_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in rD & aD, forall x y, rR x (f y) = aR (g x) y}.
Proof. by move=> mf x y hx hy; rewrite -{1}[x]fgK_on // mf. Qed.
Lemma can_mono_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in rD &, {mono g : x y / rR x y >-> aR x y}}.
Proof. by move=> mf x y hx hy /=; rewrite -mf // !fgK_on. Qed.
End MonoHomoMorphismTheory_in.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_V |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
usb_system_jtag_uart_sim_scfifo_w the_usb_system_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
usb_system_jtag_uart_sim_scfifo_r the_usb_system_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
usb_system_jtag_uart_scfifo_w the_usb_system_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
usb_system_jtag_uart_scfifo_r the_usb_system_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic usb_system_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam usb_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// usb_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// usb_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// usb_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_TB_V
`define SKY130_FD_SC_MS__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V |
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK,
/* debug */
output p113_out
);
wire CLK2;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [7:0] featurebits;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [7:0] OBC1_SNES_DATA_IN;
wire [7:0] OBC1_SNES_DATA_OUT;
wire [13:0] DBG_msu_address;
wire DBG_msu_reg_oe_rising;
wire DBG_msu_reg_oe_falling;
wire DBG_msu_reg_we_rising;
wire [2:0] SD_DMA_DBG_clkcnt;
wire [10:0] SD_DMA_DBG_cyclecnt;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
reg [7:0] SNES_PARDr;
reg [7:0] SNES_READr;
reg [7:0] SNES_WRITEr;
reg [7:0] SNES_CPU_CLKr;
reg [7:0] SNES_ROMSELr;
reg [23:0] SNES_ADDRr [5:0];
reg [7:0] SNES_PAr [5:0];
reg [7:0] SNES_DATAr [4:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
wire SNES_PARD_start = ((SNES_PARDr[6:1] & SNES_PARDr[7:2]) == 6'b111110);
wire SNES_RD_start = ((SNES_READr[6:1] & SNES_READr[7:2]) == 6'b111110);
wire SNES_RD_end = ((SNES_READr[6:1] & SNES_READr[7:2]) == 6'b000001);
wire SNES_WR_end = ((SNES_WRITEr[6:1] & SNES_WRITEr[7:2]) == 6'b000001);
wire SNES_cycle_start = ((SNES_CPU_CLKr[4:1] & SNES_CPU_CLKr[5:2]) == 4'b0001);
wire SNES_cycle_end = ((SNES_CPU_CLKr[4:1] & SNES_CPU_CLKr[5:2]) == 4'b1110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
wire [7:0] SNES_PA = (SNES_PAr[5] & SNES_PAr[4]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
wire free_slot = SNES_cycle_end | free_strobe;
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= ~ROM_HIT;
end
always @(posedge CLK2) begin
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
end
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
obc1 snes_obc1 (
.clk(CLK2),
.enable(obc1_enable),
.data_in(OBC1_SNES_DATA_IN),
.data_out(OBC1_SNES_DATA_OUT),
.addr_in(SNES_ADDR[12:0]),
.reg_we_rising(SNES_WR_end)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
wire feat_cmd_unlock = featurebits[5];
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.featurebits_out(featurebits),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we)
);
wire [7:0] DCM_STATUS;
// dcm1: dfs 4x
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT),
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
//MSU-1
.msu_enable(msu_enable),
.r213f_enable(r213f_enable),
.obc1_enable(obc1_enable),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable)
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
parameter ST_IDLE = 5'b00001;
parameter ST_MCU_RD_ADDR = 5'b00010;
parameter ST_MCU_RD_END = 5'b00100;
parameter ST_MCU_WR_ADDR = 5'b01000;
parameter ST_MCU_WR_END = 5'b10000;
parameter SNES_DEAD_TIMEOUT = 17'd96000; // 1ms
parameter ROM_CYCLE_LEN = 4'd8;
reg [4:0] STATE;
initial STATE = ST_IDLE;
assign MSU_SNES_DATA_IN = BUS_DATA;
assign OBC1_SNES_DATA_IN = BUS_DATA;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_cycle_start(SNES_cycle_start),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b011;
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
? (msu_enable ? MSU_SNES_DATA_OUT
:obc1_enable ? OBC1_SNES_DATA_OUT
:(cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
:((snescmd_unlock | feat_cmd_unlock) & snescmd_enable) ? snescmd_dout
:(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
wire MCU_WR_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_RD_HIT = |(STATE & ST_MCU_RD_ADDR);
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
endcase
end
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
// r213f_delay <= 3'b000;
// r213f_state <= 2'b10;
// end else if(r213f_state == 2'b10) begin
// r213f_delay <= r213f_delay - 1;
// if(r213f_delay == 3'b000) begin
r213f_forceread <= 1'b0;
r213f_state <= 2'b01;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
// end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) begin
MCU_WRITE_1<= MCU_WRITE;
end
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & IS_WRITABLE & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WR_HIT ? 1'b0
: 1'b1;
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = !ROM_ADDR0;
assign SNES_DATABUS_OE = obc1_enable ? 1'b0 :
msu_enable ? 1'b0 :
snescmd_enable ? (~(snescmd_unlock | feat_cmd_unlock) | (SNES_READ & SNES_WRITE)) :
r213f_enable & !SNES_PARD ? 1'b0 :
snoop_4200_enable ? SNES_WRITE
: ((IS_ROM & SNES_ROMSEL)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
|(SNES_READ & SNES_WRITE)
);
assign SNES_DATABUS_DIR = (~SNES_READ | (~SNES_PARD & (r213f_enable)))
? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
: 1'b0;
assign SNES_IRQ = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[8:0]), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
/*
wire [35:0] CONTROL0;
icon icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
.TRIG3({bsx_data_ovr, r213f_forceread, r213f_enable, SNES_PARD, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(spi_byte_cnt[3:0])
);
*/
/*
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
.TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
.TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
.TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(ST_MEM_DELAYr)
);
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_LP_V
`define SKY130_FD_SC_LP__SDFSTP_LP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_lp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_lp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_2_V
`define SKY130_FD_SC_HS__A21OI_2_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21oi_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_2_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: pulse_synchronizer.v
// Project: UNET-SWITCH4-64bit-wbs
// Description: transforms a pulse from one domain into a pulse in another domain
// note that the arriving pulses should be separated by around 5 cycles
// in each domain.
//
///////////////////////////////////////////////////////////////////////////////
module pulse_synchronizer
( input pulse_in_clkA,
input clkA,
output pulse_out_clkB,
input clkB,
input reset_clkA,
input reset_clkB
);
reg ackA;
reg ackB;
reg ackA_synch;
reg ackA_clkB;
reg ackB_synch;
reg ackB_clkA;
reg pulse_in_clkA_d1;
reg ackA_clkB_d1;
reg ackB_d1;
/* detect rising edges in clkA domain, set the ackA signal
* until the pulse is acked from the other domain */
always @(posedge clkA) begin
if(reset_clkA) begin
ackA <= 0;
end
else if(!pulse_in_clkA_d1 & pulse_in_clkA) begin
ackA <= 1;
end
else if(ackB_clkA) begin
ackA <= 0;
end
end // always @ (posedge clkA)
/* detect the rising edge of ackA and set ackB until ackA falls */
always @(posedge clkB) begin
if(reset_clkB) begin
ackB <= 0;
end
else if(!ackA_clkB_d1 & ackA_clkB) begin
ackB <= 1;
end
else if(!ackA_clkB) begin
ackB <= 0;
end
end // always @ (posedge clkB)
/* detect rising edge of ackB and send pulse */
assign pulse_out_clkB = ackB & !ackB_d1;
/* synchronize the ack signals */
always @(posedge clkA) begin
if(reset_clkA) begin
pulse_in_clkA_d1 <= 0;
ackB_synch <= 0;
ackB_clkA <= 0;
end
else begin
pulse_in_clkA_d1 <= pulse_in_clkA;
ackB_synch <= ackB;
ackB_clkA <= ackB_synch;
end
end
/* synchronize the ack signals */
always @(posedge clkB) begin
if(reset_clkB) begin
ackB_d1 <= 0;
ackA_synch <= 0;
ackA_clkB <= 0;
ackA_clkB_d1 <= 0;
end
else begin
ackB_d1 <= ackB;
ackA_synch <= ackA;
ackA_clkB <= ackA_synch;
ackA_clkB_d1 <= ackA_clkB;
end
end
endmodule // pulse_synchronizer
|
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
// `define DEBUGREGS
// `define DEBUGASM
// `define DEBUG
`ifdef DEBUG
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef FORMAL
`define FORMAL_KEEP (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`endif
// uncomment this for register file in extra module
// `define PICORV32_REGS picorv32_regs
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define PICORV32_V
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] LATCHED_MEM_RDATA = 0,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h0000_0000,
parameter [31:0] LATCHED_IRQ = 32'hffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h0000_0010,
parameter [31:0] STACKADDR = 32'hffff_ffff
) (
input clk, resetn,
output reg trap,
output reg mem_valid,
output reg mem_instr,
input mem_ready,
output reg [31:0] mem_addr,
output reg [31:0] mem_wdata,
output reg [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output reg [31:0] mem_la_wdata,
output reg [ 3:0] mem_la_wstrb,
// Pico Co-Processor Interface (PCPI)
output reg pcpi_valid,
output reg [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ Interface
input [31:0] irq,
output reg [31:0] eoi,
`ifdef RISCV_FORMAL
output reg rvfi_valid,
output reg [63:0] rvfi_order,
output reg [31:0] rvfi_insn,
output reg rvfi_trap,
output reg rvfi_halt,
output reg rvfi_intr,
output reg [ 4:0] rvfi_rs1_addr,
output reg [ 4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [ 4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [ 3:0] rvfi_mem_rmask,
output reg [ 3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output reg trace_valid,
output reg [35:0] trace_data
);
endmodule
|
//
// Copyright (c) 2014 Colin Rothwell
// Copyright (c) 2014 A. Theodore Markettos
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
// intermediary between Bluespec, which outputs an enable signal,
// and Megawizard's verilog, which doesn't have that input
module doubleMulWrapper (
clock,
dataa,
datab,
result,
dummy_enable);
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
input dummy_enable;
doubleMul doubleMul (
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule
|
// tb_rxadc_2.v: top-level testbench for rxadc v2 in Lattice iCE40-Ultra
// 07-17-2016 E. Brombaugh
module tb_rxadc_2;
// SPI slave port
reg SPI_CSL;
reg SPI_MOSI;
wire SPI_MISO;
reg SPI_SCLK;
// rxadc board interface
reg rxadc_clk;
wire rxadc_dfs;
reg rxadc_otr;
reg [9:0] rxadc_dat;
// DAC I2S output
wire dac_mclk;
wire dac_sdout;
wire dac_sclk;
wire dac_lrck;
// MCU I2S output
reg mcu_sdin;
wire mcu_sdout;
wire mcu_sclk;
wire mcu_lrck;
// RGB output
wire o_red;
wire o_green;
wire o_blue;
// ADC NCO source
real rxadc_phs;
// spi shift
reg [39:0] sr;
reg [31:0] read_data;
// spi transaction task
task spi_rxtx
(
input rw,
input [6:0] addr,
input [31:0] wdata
);
begin: spi_task
sr = {rw,addr,wdata};
SPI_CSL = 1'b0;
SPI_SCLK = 1'b0;
SPI_MOSI = sr[39];
repeat(40)
begin
#100
SPI_SCLK = 1'b1;
#100
SPI_SCLK = 1'b0;
sr = {sr[38:0],SPI_MISO};
SPI_MOSI = sr[39];
end
#100
SPI_CSL = 1'b1;
#100
read_data = sr[31:0];
end
endtask
rxadc_2
uut(
// SPI slave port
.SPI_CSL(SPI_CSL),
.SPI_MOSI(SPI_MOSI),
.SPI_MISO(SPI_MISO),
.SPI_SCLK(SPI_SCLK),
// rxadc board interface
.rxadc_clk(rxadc_clk),
.rxadc_dfs(rxadc_dfs),
.rxadc_otr(rxadc_otr),
.rxadc_dat(rxadc_dat),
// I2S DAC output
.dac_mclk(dac_mclk),
.dac_sdout(dac_sdout),
.dac_sclk(dac_sclk),
.dac_lrck(dac_lrck),
// I2S MCU interface
.mcu_sdin(mcu_sdin),
.mcu_sdout(mcu_sdout),
.mcu_sclk(mcu_sclk),
.mcu_lrck(mcu_lrck),
// RGB output
.o_red(o_red),
.o_green(o_green),
.o_blue(o_blue)
);
// test setup
initial
begin
// initial SPI setting
SPI_CSL = 1'b1;
SPI_MOSI = 1'b0;
SPI_SCLK = 1'b0;
// initialize RXADC
rxadc_clk = 1'b0;
rxadc_otr = 1'b0;
// initialize MCU SDIN
mcu_sdin = 1'b0;
// wait for chip to init
#4000
// read ID
spi_rxtx(1'b1, 7'd00, 32'd0);
// write params - assume the defaults are good
spi_rxtx(1'b0, 7'd1, 32'd1000); // cnt_reg
spi_rxtx(1'b0, 7'h10, 32'h00000800); // freq
spi_rxtx(1'b0, 7'h11, 32'd0); // DAC mux
spi_rxtx(1'b0, 7'h12, 32'd1); // noise shaping
spi_rxtx(1'b0, 7'd3, 32'd1); // trig
spi_rxtx(1'b0, 7'd3, 32'd0); // untrig
end
// ADC clock source
always
#12.5 rxadc_clk <= ~rxadc_clk;
// ADC data source
always @(posedge rxadc_clk)
begin
rxadc_phs <= rxadc_phs + 3*3.14159/64;
//rxadc_dat <= 10'd512 + 511*$sin(rxadc_phs);
rxadc_dat <= 10'd1000;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXTP_BLACKBOX_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_l2_buf2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module jbi_l2_buf2(/*AUTOARG*/
// Outputs
jbi_sctag_req_buf, scbuf_jbi_data_buf, jbi_scbuf_ecc_buf,
jbi_sctag_req_vld_buf, scbuf_jbi_ctag_vld_buf,
scbuf_jbi_ue_err_buf, sctag_jbi_iq_dequeue_buf,
sctag_jbi_wib_dequeue_buf, sctag_jbi_por_req_buf,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req
);
output [31:0] jbi_sctag_req_buf;
output [31:0] scbuf_jbi_data_buf;
output [6:0] jbi_scbuf_ecc_buf;
output jbi_sctag_req_vld_buf;
output scbuf_jbi_ctag_vld_buf;
output scbuf_jbi_ue_err_buf;
output sctag_jbi_iq_dequeue_buf;
output sctag_jbi_wib_dequeue_buf;
output sctag_jbi_por_req_buf;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
// This repeater bank is a row of flops
// There are a maximum of 10 flops per row.
assign jbi_sctag_req_buf = jbi_sctag_req ;
assign scbuf_jbi_data_buf = scbuf_jbi_data ;
assign jbi_scbuf_ecc_buf[6:0] = jbi_scbuf_ecc[6:0] ;
assign jbi_sctag_req_vld_buf = jbi_sctag_req_vld ;
assign scbuf_jbi_ctag_vld_buf = scbuf_jbi_ctag_vld ;
assign scbuf_jbi_ue_err_buf = scbuf_jbi_ue_err ;
assign sctag_jbi_iq_dequeue_buf = sctag_jbi_iq_dequeue ;
assign sctag_jbi_wib_dequeue_buf = sctag_jbi_wib_dequeue;
assign sctag_jbi_por_req_buf = sctag_jbi_por_req ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_SYMBOL_V
`define SKY130_FD_SC_MS__BUFBUF_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:30:26 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_buffer_register_1_0 -prefix
// system_buffer_register_1_0_ system_buffer_register_1_0_stub.v
// Design : system_buffer_register_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "buffer_register,Vivado 2016.4" *)
module system_buffer_register_1_0(clk, val_in, val_out)
/* synthesis syn_black_box black_box_pad_pin="clk,val_in[31:0],val_out[31:0]" */;
input clk;
input [31:0]val_in;
output [31:0]val_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_2_V
`define SKY130_FD_SC_HD__O21BAI_2_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_2_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:57:48 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20,
n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90,
n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136,
n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191,
n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202,
n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213,
n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224,
n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235,
n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, n246,
n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268,
n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323,
n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334,
n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345,
n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356,
n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367,
n368, n369, n370;
XOR2X2TS U40 ( .A(n288), .B(n287), .Y(res[22]) );
NAND2X1TS U41 ( .A(n255), .B(n91), .Y(n256) );
NAND2X1TS U42 ( .A(n89), .B(n259), .Y(n260) );
NAND2X1TS U43 ( .A(n286), .B(n285), .Y(n287) );
NAND2X1TS U44 ( .A(n225), .B(n240), .Y(n221) );
NAND2X1TS U45 ( .A(n250), .B(n84), .Y(n251) );
NAND2X1TS U46 ( .A(n87), .B(n242), .Y(n243) );
NAND2XLTS U47 ( .A(n82), .B(n308), .Y(n310) );
NAND2X1TS U48 ( .A(n279), .B(n278), .Y(n280) );
NAND2X1TS U49 ( .A(n272), .B(n271), .Y(n273) );
NAND2XLTS U50 ( .A(n83), .B(n330), .Y(n331) );
NAND2XLTS U51 ( .A(n263), .B(n262), .Y(n264) );
NAND2XLTS U52 ( .A(n290), .B(n289), .Y(n291) );
NAND2XLTS U53 ( .A(n311), .B(n8), .Y(n309) );
NAND2X1TS U54 ( .A(n301), .B(n300), .Y(n302) );
OA21X2TS U55 ( .A0(n239), .A1(n238), .B0(n237), .Y(n93) );
NAND2XLTS U56 ( .A(n296), .B(n295), .Y(n297) );
NOR2X1TS U57 ( .A(n62), .B(n59), .Y(n317) );
NAND3X6TS U58 ( .A(n73), .B(n78), .C(n65), .Y(n235) );
NAND2X1TS U59 ( .A(n232), .B(in1[31]), .Y(n237) );
NAND2X6TS U60 ( .A(n292), .B(n66), .Y(n65) );
NOR2XLTS U61 ( .A(n61), .B(n60), .Y(n59) );
INVX3TS U62 ( .A(n74), .Y(n67) );
CLKMX2X2TS U63 ( .A(in2[31]), .B(n231), .S0(add_sub), .Y(n232) );
NAND2X1TS U64 ( .A(n220), .B(in1[29]), .Y(n240) );
NOR2X1TS U65 ( .A(n229), .B(in2[30]), .Y(n230) );
NAND2X2TS U66 ( .A(n188), .B(in1[22]), .Y(n285) );
NAND2X2TS U67 ( .A(n189), .B(in1[23]), .Y(n278) );
NAND2X1TS U68 ( .A(n169), .B(in1[20]), .Y(n295) );
OR2X4TS U69 ( .A(n211), .B(in1[27]), .Y(n91) );
OR2X4TS U70 ( .A(n226), .B(in1[30]), .Y(n87) );
NAND2X2TS U71 ( .A(n168), .B(in1[19]), .Y(n300) );
NOR2X4TS U72 ( .A(n189), .B(in1[23]), .Y(n277) );
NOR2X2TS U73 ( .A(n169), .B(in1[20]), .Y(n294) );
CLKMX2X3TS U74 ( .A(in2[25]), .B(n195), .S0(n223), .Y(n207) );
CLKMX2X4TS U75 ( .A(in2[29]), .B(n219), .S0(n223), .Y(n220) );
MXI2X2TS U76 ( .A(n167), .B(n166), .S0(add_sub), .Y(n169) );
NOR2X2TS U77 ( .A(n218), .B(n204), .Y(n202) );
NOR2X2TS U78 ( .A(n218), .B(n217), .Y(n205) );
XNOR2X1TS U79 ( .A(n222), .B(in2[29]), .Y(n219) );
XNOR2X1TS U80 ( .A(n183), .B(in2[20]), .Y(n166) );
XNOR2X1TS U81 ( .A(n184), .B(n186), .Y(n185) );
XOR2X1TS U82 ( .A(n196), .B(in2[24]), .Y(n177) );
INVX2TS U83 ( .A(in2[21]), .Y(n186) );
NOR2X2TS U84 ( .A(n183), .B(in2[20]), .Y(n184) );
NOR2X2TS U85 ( .A(n161), .B(in2[18]), .Y(n162) );
CLKINVX3TS U86 ( .A(n218), .Y(n196) );
NOR3X2TS U87 ( .A(n183), .B(in2[22]), .C(n179), .Y(n172) );
OR2X2TS U88 ( .A(n204), .B(in2[27]), .Y(n217) );
NAND2X2TS U89 ( .A(n176), .B(n165), .Y(n161) );
AOI21X2TS U90 ( .A0(n329), .A1(n83), .B0(n139), .Y(n34) );
NOR2X1TS U91 ( .A(in2[25]), .B(in2[24]), .Y(n201) );
CLKXOR2X2TS U92 ( .A(n176), .B(in2[16]), .Y(n154) );
OR2X2TS U93 ( .A(in2[21]), .B(in2[20]), .Y(n179) );
OR2X4TS U94 ( .A(n138), .B(in1[12]), .Y(n83) );
NOR2X1TS U95 ( .A(in2[19]), .B(in2[18]), .Y(n164) );
NOR2X2TS U96 ( .A(in2[17]), .B(in2[16]), .Y(n165) );
NOR2X4TS U97 ( .A(n131), .B(in1[10]), .Y(n36) );
XOR2X1TS U98 ( .A(n151), .B(in2[15]), .Y(n152) );
OR2X4TS U99 ( .A(n122), .B(in1[8]), .Y(n86) );
CLKMX2X4TS U100 ( .A(in2[7]), .B(n118), .S0(n20), .Y(n119) );
AND2X2TS U101 ( .A(n96), .B(n148), .Y(n33) );
INVX2TS U102 ( .A(in2[14]), .Y(n148) );
OR2X4TS U103 ( .A(n129), .B(n128), .Y(n134) );
INVX2TS U104 ( .A(n198), .Y(n19) );
CLKINVX6TS U105 ( .A(n198), .Y(n20) );
XOR2X2TS U106 ( .A(n124), .B(in2[9]), .Y(n125) );
AOI21X2TS U107 ( .A0(n110), .A1(n115), .B0(n369), .Y(n111) );
INVX6TS U108 ( .A(n9), .Y(n108) );
CLKINVX2TS U109 ( .A(n128), .Y(n29) );
INVX8TS U110 ( .A(n223), .Y(n198) );
NOR2X1TS U111 ( .A(in2[11]), .B(in2[10]), .Y(n28) );
INVX12TS U112 ( .A(n369), .Y(n223) );
INVX4TS U113 ( .A(n109), .Y(n30) );
INVX2TS U114 ( .A(in2[5]), .Y(n10) );
INVX4TS U115 ( .A(in2[8]), .Y(n121) );
NOR2X2TS U116 ( .A(in2[7]), .B(in2[6]), .Y(n31) );
OAI2BB1X2TS U117 ( .A0N(in2[2]), .A1N(add_sub), .B0(in2[3]), .Y(n102) );
CLKINVX3TS U118 ( .A(in2[3]), .Y(n114) );
NOR2X1TS U119 ( .A(n19), .B(in2[12]), .Y(n39) );
NOR2XLTS U120 ( .A(n20), .B(in2[18]), .Y(n51) );
XOR2X1TS U121 ( .A(n180), .B(in2[22]), .Y(n181) );
XNOR2X1TS U122 ( .A(n205), .B(in2[28]), .Y(n206) );
INVX4TS U123 ( .A(in2[2]), .Y(n366) );
NAND2X2TS U124 ( .A(n138), .B(in1[12]), .Y(n330) );
NAND2X1TS U125 ( .A(n226), .B(in1[30]), .Y(n242) );
INVX12TS U126 ( .A(add_sub), .Y(n369) );
NAND2X1TS U127 ( .A(n43), .B(n305), .Y(n306) );
AND2X4TS U128 ( .A(n30), .B(n31), .Y(n6) );
NAND2X2TS U129 ( .A(n108), .B(in1[5]), .Y(n355) );
NAND2X2TS U130 ( .A(n70), .B(n69), .Y(n68) );
INVX3TS U131 ( .A(n236), .Y(n75) );
INVX2TS U132 ( .A(n239), .Y(n233) );
NOR2X4TS U133 ( .A(n13), .B(n314), .Y(n58) );
NAND2X1TS U134 ( .A(n7), .B(n315), .Y(n316) );
NAND2X2TS U135 ( .A(n85), .B(n83), .Y(n35) );
INVX2TS U136 ( .A(n330), .Y(n139) );
INVX4TS U137 ( .A(n342), .Y(n123) );
NOR2X4TS U138 ( .A(n53), .B(n228), .Y(n52) );
NAND3X4TS U139 ( .A(n71), .B(n68), .C(n67), .Y(n73) );
NOR2X4TS U140 ( .A(n193), .B(n74), .Y(n66) );
NAND2X4TS U141 ( .A(n216), .B(n75), .Y(n74) );
NAND2X2TS U142 ( .A(n233), .B(n237), .Y(n234) );
NOR2X4TS U143 ( .A(n25), .B(n304), .Y(n24) );
INVX4TS U144 ( .A(n44), .Y(n25) );
NAND2X4TS U145 ( .A(n47), .B(n45), .Y(n44) );
INVX2TS U146 ( .A(n250), .Y(n213) );
INVX2TS U147 ( .A(n262), .Y(n210) );
INVX4TS U148 ( .A(n158), .Y(n45) );
MX2X2TS U149 ( .A(in2[19]), .B(n163), .S0(n20), .Y(n168) );
INVX4TS U150 ( .A(n308), .Y(n158) );
NOR2X4TS U151 ( .A(n58), .B(n63), .Y(n57) );
NAND2X2TS U152 ( .A(n196), .B(n201), .Y(n197) );
NAND2X1TS U153 ( .A(n321), .B(n320), .Y(n322) );
NOR2X6TS U154 ( .A(n324), .B(n319), .Y(n147) );
INVX2TS U155 ( .A(n315), .Y(n63) );
OR2X4TS U156 ( .A(n137), .B(in1[11]), .Y(n85) );
NAND2X4TS U157 ( .A(n131), .B(in1[10]), .Y(n336) );
NAND2X4TS U158 ( .A(n145), .B(in1[13]), .Y(n325) );
NAND2X4TS U159 ( .A(n122), .B(in1[8]), .Y(n342) );
XOR2X2TS U160 ( .A(n141), .B(in2[13]), .Y(n142) );
NOR2X4TS U161 ( .A(n134), .B(in2[10]), .Y(n135) );
NAND2X6TS U162 ( .A(n150), .B(n149), .Y(n143) );
NAND2X4TS U163 ( .A(n29), .B(n28), .Y(n27) );
NAND3X4TS U164 ( .A(n101), .B(n223), .C(in2[3]), .Y(n104) );
NOR2X4TS U165 ( .A(in2[13]), .B(in2[12]), .Y(n149) );
XOR2X1TS U166 ( .A(n307), .B(n306), .Y(res[18]) );
XOR2X1TS U167 ( .A(n317), .B(n316), .Y(res[15]) );
NAND2BX2TS U168 ( .AN(n191), .B(n72), .Y(n71) );
NAND2X4TS U169 ( .A(n87), .B(n225), .Y(n236) );
AOI21X2TS U170 ( .A0(n84), .A1(n246), .B0(n213), .Y(n214) );
OA21X4TS U171 ( .A0(n300), .A1(n294), .B0(n295), .Y(n170) );
NOR2X6TS U172 ( .A(n284), .B(n282), .Y(n276) );
NAND2X4TS U173 ( .A(n91), .B(n84), .Y(n215) );
NOR2X6TS U174 ( .A(n277), .B(n270), .Y(n192) );
NOR2X2TS U175 ( .A(n299), .B(n294), .Y(n171) );
XOR2X1TS U176 ( .A(n332), .B(n331), .Y(res[12]) );
XOR2X1TS U177 ( .A(n327), .B(n61), .Y(res[13]) );
NAND2X2TS U178 ( .A(n190), .B(in1[24]), .Y(n271) );
OR2X4TS U179 ( .A(n212), .B(in1[28]), .Y(n84) );
NAND2X4TS U180 ( .A(n187), .B(in1[21]), .Y(n289) );
MX2X2TS U181 ( .A(in2[30]), .B(n224), .S0(n223), .Y(n226) );
MX2X4TS U182 ( .A(in2[27]), .B(n203), .S0(n223), .Y(n211) );
NAND2X2TS U183 ( .A(n160), .B(in1[18]), .Y(n305) );
MX2X2TS U184 ( .A(in2[28]), .B(n206), .S0(n223), .Y(n212) );
MX2X4TS U185 ( .A(in2[23]), .B(n173), .S0(add_sub), .Y(n189) );
OR2X4TS U186 ( .A(n157), .B(in1[17]), .Y(n82) );
XNOR2X2TS U187 ( .A(n172), .B(in2[23]), .Y(n173) );
XNOR2X2TS U188 ( .A(n162), .B(in2[19]), .Y(n163) );
NAND2X6TS U189 ( .A(n16), .B(n21), .Y(n338) );
NOR3X6TS U190 ( .A(n218), .B(in2[28]), .C(n217), .Y(n222) );
XOR2X1TS U191 ( .A(n341), .B(n340), .Y(res[9]) );
NAND2BX4TS U192 ( .AN(n174), .B(n176), .Y(n183) );
INVX4TS U193 ( .A(n36), .Y(n90) );
NAND2X2TS U194 ( .A(n15), .B(n123), .Y(n38) );
INVX4TS U195 ( .A(n314), .Y(n7) );
MX2X2TS U196 ( .A(in2[11]), .B(n136), .S0(n19), .Y(n137) );
OR2X6TS U197 ( .A(n127), .B(in1[9]), .Y(n15) );
XNOR2X2TS U198 ( .A(n135), .B(in2[11]), .Y(n136) );
OR2X2TS U199 ( .A(n19), .B(in2[10]), .Y(n12) );
OAI21XLTS U200 ( .A0(n370), .A1(n369), .B0(n368), .Y(res[3]) );
OAI21XLTS U201 ( .A0(n369), .A1(n363), .B0(n362), .Y(res[1]) );
OAI21XLTS U202 ( .A0(n365), .A1(n369), .B0(n364), .Y(res[2]) );
NAND4BX2TS U203 ( .AN(in2[5]), .B(n116), .C(n115), .D(n114), .Y(n117) );
NAND2X2TS U204 ( .A(n201), .B(n200), .Y(n204) );
NOR3X4TS U205 ( .A(n109), .B(in2[0]), .C(in2[3]), .Y(n110) );
OR2X1TS U206 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NAND2X1TS U207 ( .A(n313), .B(n18), .Y(n8) );
OR2X4TS U208 ( .A(n156), .B(in1[16]), .Y(n18) );
XNOR2X4TS U209 ( .A(n143), .B(in2[14]), .Y(n144) );
NAND3X6TS U210 ( .A(n88), .B(n359), .C(n361), .Y(n41) );
NAND2BX4TS U211 ( .AN(n198), .B(n105), .Y(n106) );
OR2X6TS U212 ( .A(n42), .B(n358), .Y(n40) );
OR2X6TS U213 ( .A(n107), .B(in1[4]), .Y(n359) );
AND4X6TS U214 ( .A(n104), .B(n105), .C(in1[3]), .D(n103), .Y(n107) );
CLKINVX12TS U215 ( .A(n143), .Y(n97) );
NOR2X4TS U216 ( .A(in2[16]), .B(n98), .Y(n99) );
NAND2X6TS U217 ( .A(n107), .B(in1[4]), .Y(n358) );
OAI21X4TS U218 ( .A0(n270), .A1(n278), .B0(n271), .Y(n191) );
NOR2X4TS U219 ( .A(n190), .B(in1[24]), .Y(n270) );
NOR2X8TS U220 ( .A(n108), .B(in1[5]), .Y(n42) );
XNOR2X2TS U221 ( .A(n197), .B(in2[26]), .Y(n199) );
XNOR2X4TS U222 ( .A(n11), .B(n10), .Y(n9) );
AO21X4TS U223 ( .A0(n56), .A1(n95), .B0(n369), .Y(n11) );
AOI21X4TS U224 ( .A0(n133), .A1(n223), .B0(n39), .Y(n138) );
MXI2X4TS U225 ( .A(n178), .B(n177), .S0(add_sub), .Y(n190) );
MXI2X4TS U226 ( .A(n200), .B(n199), .S0(n20), .Y(n208) );
CLKINVX12TS U227 ( .A(n98), .Y(n176) );
XOR2X2TS U228 ( .A(n274), .B(n273), .Y(res[24]) );
NOR2X6TS U229 ( .A(n153), .B(in1[15]), .Y(n314) );
MX2X4TS U230 ( .A(in2[15]), .B(n152), .S0(n19), .Y(n153) );
XOR2X2TS U231 ( .A(n281), .B(n280), .Y(res[23]) );
NOR2X4TS U232 ( .A(n146), .B(in1[14]), .Y(n319) );
NOR2X4TS U233 ( .A(n145), .B(in1[13]), .Y(n324) );
MX2X4TS U234 ( .A(in2[13]), .B(n142), .S0(n19), .Y(n145) );
INVX8TS U235 ( .A(n244), .Y(n265) );
XNOR2X4TS U236 ( .A(n261), .B(n260), .Y(res[26]) );
NOR3X4TS U237 ( .A(in2[0]), .B(in2[4]), .C(in2[6]), .Y(n116) );
NAND2X8TS U238 ( .A(n176), .B(n175), .Y(n218) );
XNOR2X4TS U239 ( .A(n257), .B(n256), .Y(res[27]) );
OR2X8TS U240 ( .A(in2[4]), .B(in2[5]), .Y(n109) );
XOR2X4TS U241 ( .A(n111), .B(in2[6]), .Y(n112) );
XNOR2X2TS U242 ( .A(n252), .B(n251), .Y(res[28]) );
OAI21X2TS U243 ( .A0(n94), .A1(n54), .B0(n93), .Y(res[32]) );
OA21X4TS U244 ( .A0(n319), .A1(n325), .B0(n320), .Y(n13) );
NAND2X2TS U245 ( .A(n146), .B(in1[14]), .Y(n320) );
NOR2X4TS U246 ( .A(n183), .B(n179), .Y(n180) );
MXI2X4TS U247 ( .A(n182), .B(n181), .S0(n20), .Y(n188) );
NOR2X4TS U248 ( .A(n188), .B(in1[22]), .Y(n284) );
INVX4TS U249 ( .A(n37), .Y(n131) );
MXI2X4TS U250 ( .A(n155), .B(n154), .S0(n20), .Y(n156) );
INVX2TS U251 ( .A(in2[16]), .Y(n155) );
NAND2X2TS U252 ( .A(n112), .B(in1[6]), .Y(n350) );
OR2X2TS U253 ( .A(n112), .B(in1[6]), .Y(n92) );
NAND2X2TS U254 ( .A(n156), .B(in1[16]), .Y(n311) );
OR2X4TS U255 ( .A(n208), .B(in1[26]), .Y(n89) );
NAND2X4TS U256 ( .A(n207), .B(in1[25]), .Y(n262) );
NAND2X2TS U257 ( .A(n208), .B(in1[26]), .Y(n259) );
NAND2X2TS U258 ( .A(n165), .B(n164), .Y(n174) );
NOR3X4TS U259 ( .A(in2[2]), .B(in2[4]), .C(in2[3]), .Y(n56) );
XOR2X1TS U260 ( .A(n117), .B(in2[7]), .Y(n118) );
MXI2X4TS U261 ( .A(n121), .B(n120), .S0(add_sub), .Y(n122) );
MXI2X4TS U262 ( .A(n126), .B(n125), .S0(add_sub), .Y(n127) );
NOR2X4TS U263 ( .A(n129), .B(in2[8]), .Y(n124) );
XOR2X1TS U264 ( .A(n150), .B(in2[12]), .Y(n133) );
AOI21X2TS U265 ( .A0(n159), .A1(n20), .B0(n51), .Y(n160) );
INVX2TS U266 ( .A(in2[22]), .Y(n182) );
NOR2X4TS U267 ( .A(n187), .B(in1[21]), .Y(n282) );
INVX2TS U268 ( .A(in2[24]), .Y(n178) );
INVX2TS U269 ( .A(n255), .Y(n246) );
INVX2TS U270 ( .A(n275), .Y(n72) );
NOR2X4TS U271 ( .A(n119), .B(in1[7]), .Y(n345) );
INVX2TS U272 ( .A(n350), .Y(n113) );
NAND2X2TS U273 ( .A(n119), .B(in1[7]), .Y(n346) );
NAND2X2TS U274 ( .A(n127), .B(in1[9]), .Y(n339) );
AND2X4TS U275 ( .A(n137), .B(in1[11]), .Y(n329) );
NOR2X2TS U276 ( .A(n158), .B(n49), .Y(n48) );
INVX2TS U277 ( .A(n311), .Y(n49) );
INVX2TS U278 ( .A(n82), .Y(n47) );
INVX2TS U279 ( .A(n282), .Y(n290) );
INVX2TS U280 ( .A(n289), .Y(n283) );
INVX8TS U281 ( .A(n266), .Y(n292) );
NOR2X1TS U282 ( .A(n267), .B(n277), .Y(n269) );
INVX2TS U283 ( .A(n276), .Y(n267) );
INVX2TS U284 ( .A(n258), .Y(n263) );
NOR2X2TS U285 ( .A(n207), .B(in1[25]), .Y(n258) );
NAND2X2TS U286 ( .A(n211), .B(in1[27]), .Y(n255) );
NAND2X4TS U287 ( .A(n263), .B(n89), .Y(n254) );
INVX2TS U288 ( .A(n259), .Y(n209) );
NAND2X2TS U289 ( .A(n212), .B(in1[28]), .Y(n250) );
INVX2TS U290 ( .A(n254), .Y(n245) );
INVX2TS U291 ( .A(n241), .Y(n225) );
NOR2X4TS U292 ( .A(n220), .B(in1[29]), .Y(n241) );
INVX4TS U293 ( .A(n95), .Y(n101) );
NOR2X4TS U294 ( .A(in2[1]), .B(in2[2]), .Y(n115) );
NAND2X2TS U295 ( .A(n15), .B(n86), .Y(n22) );
NAND2X1TS U296 ( .A(n150), .B(n140), .Y(n141) );
MXI2X2TS U297 ( .A(n148), .B(n144), .S0(n223), .Y(n146) );
NAND3X1TS U298 ( .A(n150), .B(n149), .C(n148), .Y(n151) );
AND2X2TS U299 ( .A(n147), .B(n7), .Y(n17) );
INVX2TS U300 ( .A(in2[20]), .Y(n167) );
MXI2X4TS U301 ( .A(n186), .B(n185), .S0(add_sub), .Y(n187) );
NOR2X4TS U302 ( .A(n254), .B(n215), .Y(n216) );
INVX2TS U303 ( .A(n191), .Y(n70) );
INVX2TS U304 ( .A(n192), .Y(n69) );
INVX2TS U305 ( .A(n147), .Y(n60) );
INVX2TS U306 ( .A(n318), .Y(n61) );
INVX2TS U307 ( .A(n13), .Y(n62) );
NAND2X2TS U308 ( .A(n153), .B(in1[15]), .Y(n315) );
NOR2X2TS U309 ( .A(n168), .B(in1[19]), .Y(n299) );
INVX2TS U310 ( .A(n293), .Y(n303) );
NOR2X4TS U311 ( .A(n14), .B(n241), .Y(n53) );
INVX2TS U312 ( .A(n242), .Y(n227) );
NOR2X4TS U313 ( .A(n232), .B(in1[31]), .Y(n239) );
AOI21X1TS U314 ( .A0(n369), .A1(in2[2]), .B0(in1[2]), .Y(n364) );
NAND2X1TS U315 ( .A(n359), .B(n358), .Y(n360) );
OAI21XLTS U316 ( .A0(n354), .A1(n353), .B0(n358), .Y(n357) );
NAND2X1TS U317 ( .A(n88), .B(n355), .Y(n356) );
INVX2TS U318 ( .A(n359), .Y(n353) );
NAND2X1TS U319 ( .A(n92), .B(n350), .Y(n351) );
NAND2X1TS U320 ( .A(n347), .B(n346), .Y(n348) );
INVX2TS U321 ( .A(n345), .Y(n347) );
NAND2X1TS U322 ( .A(n86), .B(n342), .Y(n344) );
NAND2X1TS U323 ( .A(n15), .B(n339), .Y(n341) );
NAND2X1TS U324 ( .A(n90), .B(n336), .Y(n337) );
NAND2X1TS U325 ( .A(n85), .B(n333), .Y(n335) );
INVX2TS U326 ( .A(n329), .Y(n333) );
NAND2X1TS U327 ( .A(n326), .B(n325), .Y(n327) );
INVX2TS U328 ( .A(n324), .Y(n326) );
NAND2X1TS U329 ( .A(n18), .B(n311), .Y(n312) );
XNOR2X1TS U330 ( .A(n310), .B(n309), .Y(res[17]) );
NAND2X1TS U331 ( .A(n46), .B(n44), .Y(n307) );
XOR2X1TS U332 ( .A(n303), .B(n302), .Y(res[19]) );
INVX2TS U333 ( .A(n299), .Y(n301) );
XNOR2X1TS U334 ( .A(n298), .B(n297), .Y(res[20]) );
OAI21X1TS U335 ( .A0(n303), .A1(n299), .B0(n300), .Y(n298) );
INVX2TS U336 ( .A(n294), .Y(n296) );
XNOR2X1TS U337 ( .A(n292), .B(n291), .Y(res[21]) );
INVX2TS U338 ( .A(n284), .Y(n286) );
INVX2TS U339 ( .A(n277), .Y(n279) );
INVX2TS U340 ( .A(n270), .Y(n272) );
XOR2X1TS U341 ( .A(n265), .B(n264), .Y(res[25]) );
NAND2X1TS U342 ( .A(n245), .B(n91), .Y(n249) );
OR2X2TS U343 ( .A(n239), .B(n236), .Y(n94) );
INVX3TS U344 ( .A(n77), .Y(n266) );
AND2X4TS U345 ( .A(n38), .B(n339), .Y(n16) );
NAND2X4TS U346 ( .A(n157), .B(in1[17]), .Y(n308) );
MX2X4TS U347 ( .A(in2[17]), .B(n100), .S0(n19), .Y(n157) );
XOR2X2TS U348 ( .A(n129), .B(n121), .Y(n120) );
AOI21X1TS U349 ( .A0(n334), .A1(n85), .B0(n329), .Y(n332) );
XNOR2X2TS U350 ( .A(n194), .B(in2[25]), .Y(n195) );
NOR2X4TS U351 ( .A(n218), .B(in2[24]), .Y(n194) );
INVX8TS U352 ( .A(n42), .Y(n88) );
NAND2X8TS U353 ( .A(n50), .B(n305), .Y(n293) );
AOI21X1TS U354 ( .A0(n343), .A1(n86), .B0(n123), .Y(n340) );
OA21X4TS U355 ( .A0(n253), .A1(n215), .B0(n214), .Y(n14) );
INVX2TS U356 ( .A(n240), .Y(n228) );
INVX2TS U357 ( .A(n361), .Y(n354) );
INVX2TS U358 ( .A(n193), .Y(n76) );
NAND2X4TS U359 ( .A(n192), .B(n276), .Y(n193) );
NOR2X2TS U360 ( .A(n160), .B(in1[18]), .Y(n304) );
INVX2TS U361 ( .A(n304), .Y(n43) );
INVX2TS U362 ( .A(in2[12]), .Y(n140) );
OAI21X1TS U363 ( .A0(n61), .A1(n324), .B0(n325), .Y(n323) );
OAI2BB1X2TS U364 ( .A0N(n130), .A1N(n19), .B0(n12), .Y(n37) );
NAND3X6TS U365 ( .A(n41), .B(n40), .C(n355), .Y(n352) );
NAND2X8TS U366 ( .A(n77), .B(n76), .Y(n80) );
NAND2X8TS U367 ( .A(n26), .B(n170), .Y(n77) );
NAND2BX4TS U368 ( .AN(n22), .B(n343), .Y(n21) );
NAND2X6TS U369 ( .A(n318), .B(n17), .Y(n23) );
CLKINVX12TS U370 ( .A(n105), .Y(n32) );
NAND2X8TS U371 ( .A(n23), .B(n57), .Y(n313) );
NOR4X2TS U372 ( .A(n174), .B(n179), .C(in2[23]), .D(in2[22]), .Y(n175) );
NAND2X8TS U373 ( .A(n46), .B(n24), .Y(n50) );
NAND2X8TS U374 ( .A(n64), .B(n48), .Y(n46) );
NAND2X8TS U375 ( .A(n293), .B(n171), .Y(n26) );
NAND2X8TS U376 ( .A(n32), .B(n6), .Y(n129) );
AND2X8TS U377 ( .A(n79), .B(n14), .Y(n54) );
NOR2X8TS U378 ( .A(n27), .B(n129), .Y(n150) );
NAND3X8TS U379 ( .A(n95), .B(n366), .C(n114), .Y(n105) );
NAND2X8TS U380 ( .A(n97), .B(n33), .Y(n98) );
NAND2X8TS U381 ( .A(n80), .B(n81), .Y(n244) );
OAI21X4TS U382 ( .A0(n328), .A1(n35), .B0(n34), .Y(n318) );
AOI21X4TS U383 ( .A0(n338), .A1(n90), .B0(n132), .Y(n328) );
OAI21X4TS U384 ( .A0(n79), .A1(n241), .B0(n52), .Y(n55) );
XNOR2X2TS U385 ( .A(n55), .B(n243), .Y(res[30]) );
NOR2X8TS U386 ( .A(in2[0]), .B(in2[1]), .Y(n95) );
NAND2X8TS U387 ( .A(n313), .B(n18), .Y(n64) );
AOI21X4TS U388 ( .A0(n192), .A1(n275), .B0(n191), .Y(n81) );
NAND2X8TS U389 ( .A(n244), .B(n216), .Y(n79) );
OA21X4TS U390 ( .A0(n14), .A1(n236), .B0(n238), .Y(n78) );
XNOR2X1TS U391 ( .A(n352), .B(n351), .Y(res[6]) );
XNOR2X1TS U392 ( .A(n337), .B(n338), .Y(res[10]) );
XOR2XLTS U393 ( .A(n349), .B(n348), .Y(res[7]) );
XNOR2X1TS U394 ( .A(n312), .B(n313), .Y(res[16]) );
XNOR2X1TS U395 ( .A(n344), .B(n343), .Y(res[8]) );
CLKINVX1TS U396 ( .A(n328), .Y(n334) );
NAND2X4TS U397 ( .A(n121), .B(n126), .Y(n128) );
OAI21X2TS U398 ( .A0(in2[3]), .A1(n369), .B0(n102), .Y(n103) );
INVX2TS U399 ( .A(n336), .Y(n132) );
OAI21X2TS U400 ( .A0(n72), .A1(n277), .B0(n278), .Y(n268) );
INVX2TS U401 ( .A(in2[9]), .Y(n126) );
INVX2TS U402 ( .A(in2[15]), .Y(n96) );
XNOR2X1TS U403 ( .A(n99), .B(in2[17]), .Y(n100) );
XNOR2X4TS U404 ( .A(n106), .B(in2[4]), .Y(n361) );
AOI21X4TS U405 ( .A0(n352), .A1(n92), .B0(n113), .Y(n349) );
OAI21X4TS U406 ( .A0(n349), .A1(n345), .B0(n346), .Y(n343) );
XNOR2X1TS U407 ( .A(n134), .B(in2[10]), .Y(n130) );
XNOR2X1TS U408 ( .A(n161), .B(in2[18]), .Y(n159) );
OAI21X4TS U409 ( .A0(n284), .A1(n289), .B0(n285), .Y(n275) );
INVX2TS U410 ( .A(in2[26]), .Y(n200) );
XNOR2X1TS U411 ( .A(n202), .B(in2[27]), .Y(n203) );
AOI21X4TS U412 ( .A0(n89), .A1(n210), .B0(n209), .Y(n253) );
XOR2X4TS U413 ( .A(n54), .B(n221), .Y(res[29]) );
NAND2BX4TS U414 ( .AN(in2[29]), .B(n222), .Y(n229) );
XOR2X1TS U415 ( .A(n229), .B(in2[30]), .Y(n224) );
AOI21X4TS U416 ( .A0(n87), .A1(n228), .B0(n227), .Y(n238) );
XNOR2X1TS U417 ( .A(n230), .B(in2[31]), .Y(n231) );
XNOR2X4TS U418 ( .A(n235), .B(n234), .Y(res[31]) );
INVX2TS U419 ( .A(n253), .Y(n247) );
AOI21X4TS U420 ( .A0(n247), .A1(n91), .B0(n246), .Y(n248) );
OAI21X4TS U421 ( .A0(n265), .A1(n249), .B0(n248), .Y(n252) );
OAI21X4TS U422 ( .A0(n265), .A1(n254), .B0(n253), .Y(n257) );
OAI21X4TS U423 ( .A0(n265), .A1(n258), .B0(n262), .Y(n261) );
AOI21X4TS U424 ( .A0(n292), .A1(n269), .B0(n268), .Y(n274) );
AOI21X4TS U425 ( .A0(n292), .A1(n276), .B0(n275), .Y(n281) );
AOI21X4TS U426 ( .A0(n292), .A1(n290), .B0(n283), .Y(n288) );
INVX2TS U427 ( .A(n319), .Y(n321) );
XNOR2X1TS U428 ( .A(n323), .B(n322), .Y(res[14]) );
XNOR2X1TS U429 ( .A(n335), .B(n334), .Y(res[11]) );
XNOR2X1TS U430 ( .A(n357), .B(n356), .Y(res[5]) );
XNOR2X1TS U431 ( .A(n361), .B(n360), .Y(res[4]) );
XNOR2X1TS U432 ( .A(in2[0]), .B(in2[1]), .Y(n363) );
AOI21X1TS U433 ( .A0(n369), .A1(in2[1]), .B0(in1[1]), .Y(n362) );
XNOR2X1TS U434 ( .A(n95), .B(n366), .Y(n365) );
NAND2X1TS U435 ( .A(n95), .B(n366), .Y(n367) );
XNOR2X1TS U436 ( .A(n367), .B(in2[3]), .Y(n370) );
AOI21X1TS U437 ( .A0(n369), .A1(in2[3]), .B0(in1[3]), .Y(n368) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL4_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_1_V
`define SKY130_FD_SC_HD__O32AI_1_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32ai_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_1_V
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=22579 clk0_duty_cycle=50 clk0_multiply_by=116000 clk0_phase_shift="0" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=44288 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:21:18:09:22:SJ cbx_altiobuf_bidir 2015:10:21:18:09:22:SJ cbx_altiobuf_in 2015:10:21:18:09:22:SJ cbx_altiobuf_out 2015:10:21:18:09:22:SJ cbx_altpll 2015:10:21:18:09:23:SJ cbx_altpll_avalon 2015:10:21:18:09:22:SJ cbx_cycloneii 2015:10:21:18:09:23:SJ cbx_lpm_add_sub 2015:10:21:18:09:23:SJ cbx_lpm_compare 2015:10:21:18:09:23:SJ cbx_lpm_counter 2015:10:21:18:09:23:SJ cbx_lpm_decode 2015:10:21:18:09:23:SJ cbx_lpm_mux 2015:10:21:18:09:23:SJ cbx_lpm_shiftreg 2015:10:21:18:09:23:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_nadder 2015:10:21:18:09:23:SJ cbx_stratix 2015:10:21:18:09:23:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_stratixiii 2015:10:21:18:09:23:SJ cbx_stratixv 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:18:12:49:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:18:12:49:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module wasca_altpll_1_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //wasca_altpll_1_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_1_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
wasca_altpll_1_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //wasca_altpll_1_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=22579 clk0_duty_cycle=50 clk0_multiply_by=116000 clk0_phase_shift="0" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=44288 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:21:18:09:22:SJ cbx_altiobuf_bidir 2015:10:21:18:09:22:SJ cbx_altiobuf_in 2015:10:21:18:09:22:SJ cbx_altiobuf_out 2015:10:21:18:09:22:SJ cbx_altpll 2015:10:21:18:09:23:SJ cbx_cycloneii 2015:10:21:18:09:23:SJ cbx_lpm_add_sub 2015:10:21:18:09:23:SJ cbx_lpm_compare 2015:10:21:18:09:23:SJ cbx_lpm_counter 2015:10:21:18:09:23:SJ cbx_lpm_decode 2015:10:21:18:09:23:SJ cbx_lpm_mux 2015:10:21:18:09:23:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_nadder 2015:10:21:18:09:23:SJ cbx_stratix 2015:10:21:18:09:23:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_stratixiii 2015:10:21:18:09:23:SJ cbx_stratixv 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
//synthesis_resources = fiftyfivenm_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module wasca_altpll_1_altpll_8932
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
fiftyfivenm_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 22579,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 116000,
pll7.clk0_phase_shift = "0",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 44288,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "fiftyfivenm_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //wasca_altpll_1_altpll_8932
//synthesis_resources = fiftyfivenm_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_1
(
address,
areset,
c0,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
wasca_altpll_1_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
wasca_altpll_1_altpll_8932 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //wasca_altpll_1
//VALID FILE
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_top.v
// Version : 1.11
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_top # (
// PCIE_2_1 params
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter [11:0] AER_BASE_PTR = 12'h140,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h178,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h128,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1
)
(
// wrapper input
// Common
output user_clk_out,
input user_reset,
input user_lnk_up,
output trn_lnk_up,
output user_rst_n,
// Tx
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
output s_axis_tx_tready,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
input tx_cfg_gnt,
// Rx
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
input wire pl_downstream_deemph_source,
input wire pl_directed_ltssm_new_vld,
input wire [5:0] pl_directed_ltssm_new,
input wire pl_directed_ltssm_stall,
input wire cm_rst_n,
input wire func_lvl_rst_n,
input wire pl_transmit_hot_rst,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en_n,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_rw1c_as_rw_n,
input wire cfg_mgmt_wr_readonly_n,
input wire cfg_mgmt_wr_en_n,
input wire cfg_mgmt_rd_en_n,
input wire cfg_err_malformed_n,
input wire cfg_err_cor_n,
input wire cfg_err_ur_n,
input wire cfg_err_ecrc_n,
input wire cfg_err_cpl_timeout_n,
input wire cfg_err_cpl_abort_n,
input wire cfg_err_cpl_unexpect_n,
input wire cfg_err_poisoned_n,
input wire cfg_err_acs_n,
input wire cfg_err_atomic_egress_blocked_n,
input wire cfg_err_mc_blocked_n,
input wire cfg_err_internal_uncor_n,
input wire cfg_err_internal_cor_n,
input wire cfg_err_posted_n,
input wire cfg_err_locked_n,
input wire cfg_err_norecovery_n,
input wire [127:0] cfg_err_aer_headerlog,
input wire [47:0] cfg_err_tlp_cpl_header,
input wire cfg_interrupt_n,
input wire [7:0] cfg_interrupt_di,
input wire cfg_interrupt_assert_n,
input wire cfg_interrupt_stat_n,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire [7:0] cfg_port_number,
input wire cfg_pm_halt_aspm_l0s_n,
input wire cfg_pm_halt_aspm_l1_n,
input wire cfg_pm_force_state_en_n,
input wire [1:0] cfg_pm_force_state,
input wire cfg_pm_wake_n,
input wire cfg_turnoff_ok,
input wire cfg_pm_send_pme_to_n,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
input wire cfg_trn_pending,
input wire [2:0] cfg_force_mps,
input wire cfg_force_common_clock_off,
input wire cfg_force_extended_sync_on,
input wire [63:0] cfg_dsn,
input wire [4:0] cfg_aer_interrupt_msgnum,
input wire [15:0] cfg_dev_id,
input wire [15:0] cfg_vend_id,
input wire [7:0] cfg_rev_id,
input wire [15:0] cfg_subsys_id,
input wire [15:0] cfg_subsys_vend_id,
input wire drp_clk,
input wire drp_en,
input wire drp_we,
input wire [8:0] drp_addr,
input wire [15:0] drp_di,
output wire drp_rdy,
output wire [15:0] drp_do,
input wire [1:0] dbg_mode,
input wire dbg_sub_mode,
input wire [2:0] pl_dbg_mode ,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
output wire pl_received_hot_rst,
output wire lnk_clk_en,
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire cfg_err_aer_headerlog_set,
output wire cfg_err_cpl_rdy,
output wire cfg_interrupt_rdy,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire [7:0] cfg_interrupt_do,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output wire cfg_received_func_lvl_rst,
output wire cfg_msg_received,
output wire [15:0] cfg_msg_data,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_pme_to,
output wire cfg_msg_received_setslotpowerlimit,
output wire cfg_msg_received_unlock,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_to_turnoff,
output wire [2:0] cfg_pcie_link_state,
output wire cfg_pm_rcv_as_req_l1_n,
output wire cfg_pm_rcv_enter_l1_n,
output wire cfg_pm_rcv_enter_l23_n,
output wire cfg_pm_rcv_req_ack_n,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_en,
output wire cfg_pmcsr_pme_status,
output wire cfg_transaction,
output wire cfg_transaction_type,
output wire [6:0] cfg_transaction_addr,
output wire cfg_command_io_enable,
output wire cfg_command_mem_enable,
output wire cfg_command_bus_master_enable,
output wire cfg_command_interrupt_disable,
output wire cfg_command_serr_en,
output wire cfg_bridge_serr_en,
output wire cfg_dev_status_corr_err_detected,
output wire cfg_dev_status_non_fatal_err_detected,
output wire cfg_dev_status_fatal_err_detected,
output wire cfg_dev_status_ur_detected,
output wire cfg_dev_control_corr_err_reporting_en,
output wire cfg_dev_control_non_fatal_reporting_en,
output wire cfg_dev_control_fatal_err_reporting_en,
output wire cfg_dev_control_ur_err_reporting_en,
output wire cfg_dev_control_enable_ro,
output wire [2:0] cfg_dev_control_max_payload,
output wire cfg_dev_control_ext_tag_en,
output wire cfg_dev_control_phantom_en,
output wire cfg_dev_control_aux_power_en,
output wire cfg_dev_control_no_snoop_en,
output wire [2:0] cfg_dev_control_max_read_req,
output wire [1:0] cfg_link_status_current_speed,
output wire [3:0] cfg_link_status_negotiated_width,
output wire cfg_link_status_link_training,
output wire cfg_link_status_dll_active,
output wire cfg_link_status_bandwidth_status,
output wire cfg_link_status_auto_bandwidth_status,
output wire [1:0] cfg_link_control_aspm_control,
output wire cfg_link_control_rcb,
output wire cfg_link_control_link_disable,
output wire cfg_link_control_retrain_link,
output wire cfg_link_control_common_clock,
output wire cfg_link_control_extended_sync,
output wire cfg_link_control_clock_pm_en,
output wire cfg_link_control_hw_auto_width_dis,
output wire cfg_link_control_bandwidth_int_en,
output wire cfg_link_control_auto_bandwidth_int_en,
output wire [3:0] cfg_dev_control2_cpl_timeout_val,
output wire cfg_dev_control2_cpl_timeout_dis,
output wire cfg_dev_control2_ari_forward_en,
output wire cfg_dev_control2_atomic_requester_en,
output wire cfg_dev_control2_atomic_egress_block,
output wire cfg_dev_control2_ido_req_en,
output wire cfg_dev_control2_ido_cpl_en,
output wire cfg_dev_control2_ltr_en,
output wire cfg_dev_control2_tlp_prefix_block,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire [6:0] cfg_vc_tcvc_map,
output wire [63:0] dbg_vec_a,
output wire [63:0] dbg_vec_b,
output wire [11:0] dbg_vec_c,
output wire dbg_sclr_a,
output wire dbg_sclr_b,
output wire dbg_sclr_c,
output wire dbg_sclr_d,
output wire dbg_sclr_e,
output wire dbg_sclr_f,
output wire dbg_sclr_g,
output wire dbg_sclr_h,
output wire dbg_sclr_i,
output wire dbg_sclr_j,
output wire dbg_sclr_k,
output wire [63:0] trn_rdllp_data,
output wire [1:0] trn_rdllp_src_rdy,
output wire [11:0] pl_dbg_vec,
input phy_rdy_n,
input pipe_clk,
input user_clk,
input user_clk2,
output wire pipe_rx0_polarity_gt,
output wire pipe_rx1_polarity_gt,
output wire pipe_rx2_polarity_gt,
output wire pipe_rx3_polarity_gt,
output wire pipe_rx4_polarity_gt,
output wire pipe_rx5_polarity_gt,
output wire pipe_rx6_polarity_gt,
output wire pipe_rx7_polarity_gt,
output wire pipe_tx_deemph_gt,
output wire [2:0] pipe_tx_margin_gt,
output wire pipe_tx_rate_gt,
output wire pipe_tx_rcvr_det_gt,
output wire [1:0] pipe_tx0_char_is_k_gt,
output wire pipe_tx0_compliance_gt,
output wire [15:0] pipe_tx0_data_gt,
output wire pipe_tx0_elec_idle_gt,
output wire [1:0] pipe_tx0_powerdown_gt,
output wire [1:0] pipe_tx1_char_is_k_gt,
output wire pipe_tx1_compliance_gt,
output wire [15:0] pipe_tx1_data_gt,
output wire pipe_tx1_elec_idle_gt,
output wire [1:0] pipe_tx1_powerdown_gt,
output wire [1:0] pipe_tx2_char_is_k_gt,
output wire pipe_tx2_compliance_gt,
output wire [15:0] pipe_tx2_data_gt,
output wire pipe_tx2_elec_idle_gt,
output wire [1:0] pipe_tx2_powerdown_gt,
output wire [1:0] pipe_tx3_char_is_k_gt,
output wire pipe_tx3_compliance_gt,
output wire [15:0] pipe_tx3_data_gt,
output wire pipe_tx3_elec_idle_gt,
output wire [1:0] pipe_tx3_powerdown_gt,
output wire [1:0] pipe_tx4_char_is_k_gt,
output wire pipe_tx4_compliance_gt,
output wire [15:0] pipe_tx4_data_gt,
output wire pipe_tx4_elec_idle_gt,
output wire [1:0] pipe_tx4_powerdown_gt,
output wire [1:0] pipe_tx5_char_is_k_gt,
output wire pipe_tx5_compliance_gt,
output wire [15:0] pipe_tx5_data_gt,
output wire pipe_tx5_elec_idle_gt,
output wire [1:0] pipe_tx5_powerdown_gt,
output wire [1:0] pipe_tx6_char_is_k_gt,
output wire pipe_tx6_compliance_gt,
output wire [15:0] pipe_tx6_data_gt,
output wire pipe_tx6_elec_idle_gt,
output wire [1:0] pipe_tx6_powerdown_gt,
output wire [1:0] pipe_tx7_char_is_k_gt,
output wire pipe_tx7_compliance_gt,
output wire [15:0] pipe_tx7_data_gt,
output wire pipe_tx7_elec_idle_gt,
output wire [1:0] pipe_tx7_powerdown_gt,
input wire pipe_rx0_chanisaligned_gt,
input wire [1:0] pipe_rx0_char_is_k_gt,
input wire [15:0] pipe_rx0_data_gt,
input wire pipe_rx0_elec_idle_gt,
input wire pipe_rx0_phy_status_gt,
input wire [2:0] pipe_rx0_status_gt,
input wire pipe_rx0_valid_gt,
input wire pipe_rx1_chanisaligned_gt,
input wire [1:0] pipe_rx1_char_is_k_gt,
input wire [15:0] pipe_rx1_data_gt,
input wire pipe_rx1_elec_idle_gt,
input wire pipe_rx1_phy_status_gt,
input wire [2:0] pipe_rx1_status_gt,
input wire pipe_rx1_valid_gt,
input wire pipe_rx2_chanisaligned_gt,
input wire [1:0] pipe_rx2_char_is_k_gt,
input wire [15:0] pipe_rx2_data_gt,
input wire pipe_rx2_elec_idle_gt,
input wire pipe_rx2_phy_status_gt,
input wire [2:0] pipe_rx2_status_gt,
input wire pipe_rx2_valid_gt,
input wire pipe_rx3_chanisaligned_gt,
input wire [1:0] pipe_rx3_char_is_k_gt,
input wire [15:0] pipe_rx3_data_gt,
input wire pipe_rx3_elec_idle_gt,
input wire pipe_rx3_phy_status_gt,
input wire [2:0] pipe_rx3_status_gt,
input wire pipe_rx3_valid_gt,
input wire pipe_rx4_chanisaligned_gt,
input wire [1:0] pipe_rx4_char_is_k_gt,
input wire [15:0] pipe_rx4_data_gt,
input wire pipe_rx4_elec_idle_gt,
input wire pipe_rx4_phy_status_gt,
input wire [2:0] pipe_rx4_status_gt,
input wire pipe_rx4_valid_gt,
input wire pipe_rx5_chanisaligned_gt,
input wire [1:0] pipe_rx5_char_is_k_gt,
input wire [15:0] pipe_rx5_data_gt,
input wire pipe_rx5_elec_idle_gt,
input wire pipe_rx5_phy_status_gt,
input wire [2:0] pipe_rx5_status_gt,
input wire pipe_rx5_valid_gt,
input wire pipe_rx6_chanisaligned_gt,
input wire [1:0] pipe_rx6_char_is_k_gt,
input wire [15:0] pipe_rx6_data_gt,
input wire pipe_rx6_elec_idle_gt,
input wire pipe_rx6_phy_status_gt,
input wire [2:0] pipe_rx6_status_gt,
input wire pipe_rx6_valid_gt,
input wire pipe_rx7_chanisaligned_gt,
input wire [1:0] pipe_rx7_char_is_k_gt,
input wire [15:0] pipe_rx7_data_gt,
input wire pipe_rx7_elec_idle_gt,
input wire pipe_rx7_phy_status_gt,
input wire [2:0] pipe_rx7_status_gt,
input wire pipe_rx7_valid_gt
);
//wire declaration
// TRN Interface
wire [C_DATA_WIDTH-1:0] trn_td;
wire [REM_WIDTH-1:0] trn_trem;
wire trn_tsof;
wire trn_teof;
wire trn_tsrc_rdy;
wire trn_tsrc_dsc;
wire trn_terrfwd;
wire trn_tecrc_gen;
wire trn_tstr;
wire trn_tcfg_gnt;
wire [C_DATA_WIDTH-1:0] trn_rd;
wire [REM_WIDTH-1:0] trn_rrem;
wire trn_rdst_rdy;
wire trn_rsof;
wire trn_reof;
wire trn_rsrc_rdy;
wire trn_rsrc_dsc;
wire trn_rerrfwd;
wire [7:0] trn_rbar_hit;
wire sys_reset_n_d;
wire [1:0] pipe_rx0_char_is_k;
wire [1:0] pipe_rx1_char_is_k;
wire [1:0] pipe_rx2_char_is_k;
wire [1:0] pipe_rx3_char_is_k;
wire [1:0] pipe_rx4_char_is_k;
wire [1:0] pipe_rx5_char_is_k;
wire [1:0] pipe_rx6_char_is_k;
wire [1:0] pipe_rx7_char_is_k;
wire pipe_rx0_valid;
wire pipe_rx1_valid;
wire pipe_rx2_valid;
wire pipe_rx3_valid;
wire pipe_rx4_valid;
wire pipe_rx5_valid;
wire pipe_rx6_valid;
wire pipe_rx7_valid;
wire [15:0] pipe_rx0_data;
wire [15:0] pipe_rx1_data;
wire [15:0] pipe_rx2_data;
wire [15:0] pipe_rx3_data;
wire [15:0] pipe_rx4_data;
wire [15:0] pipe_rx5_data;
wire [15:0] pipe_rx6_data;
wire [15:0] pipe_rx7_data;
wire pipe_rx0_chanisaligned;
wire pipe_rx1_chanisaligned;
wire pipe_rx2_chanisaligned;
wire pipe_rx3_chanisaligned;
wire pipe_rx4_chanisaligned;
wire pipe_rx5_chanisaligned;
wire pipe_rx6_chanisaligned;
wire pipe_rx7_chanisaligned;
wire [2:0] pipe_rx0_status;
wire [2:0] pipe_rx1_status;
wire [2:0] pipe_rx2_status;
wire [2:0] pipe_rx3_status;
wire [2:0] pipe_rx4_status;
wire [2:0] pipe_rx5_status;
wire [2:0] pipe_rx6_status;
wire [2:0] pipe_rx7_status;
wire pipe_rx0_phy_status;
wire pipe_rx1_phy_status;
wire pipe_rx2_phy_status;
wire pipe_rx3_phy_status;
wire pipe_rx4_phy_status;
wire pipe_rx5_phy_status;
wire pipe_rx6_phy_status;
wire pipe_rx7_phy_status;
wire pipe_rx0_elec_idle;
wire pipe_rx1_elec_idle;
wire pipe_rx2_elec_idle;
wire pipe_rx3_elec_idle;
wire pipe_rx4_elec_idle;
wire pipe_rx5_elec_idle;
wire pipe_rx6_elec_idle;
wire pipe_rx7_elec_idle;
wire pipe_tx_reset;
wire pipe_tx_rate;
wire pipe_tx_deemph;
wire [2:0] pipe_tx_margin;
wire pipe_rx0_polarity;
wire pipe_rx1_polarity;
wire pipe_rx2_polarity;
wire pipe_rx3_polarity;
wire pipe_rx4_polarity;
wire pipe_rx5_polarity;
wire pipe_rx6_polarity;
wire pipe_rx7_polarity;
wire pipe_tx0_compliance;
wire pipe_tx1_compliance;
wire pipe_tx2_compliance;
wire pipe_tx3_compliance;
wire pipe_tx4_compliance;
wire pipe_tx5_compliance;
wire pipe_tx6_compliance;
wire pipe_tx7_compliance;
wire [1:0] pipe_tx0_char_is_k;
wire [1:0] pipe_tx1_char_is_k;
wire [1:0] pipe_tx2_char_is_k;
wire [1:0] pipe_tx3_char_is_k;
wire [1:0] pipe_tx4_char_is_k;
wire [1:0] pipe_tx5_char_is_k;
wire [1:0] pipe_tx6_char_is_k;
wire [1:0] pipe_tx7_char_is_k;
wire [15:0] pipe_tx0_data;
wire [15:0] pipe_tx1_data;
wire [15:0] pipe_tx2_data;
wire [15:0] pipe_tx3_data;
wire [15:0] pipe_tx4_data;
wire [15:0] pipe_tx5_data;
wire [15:0] pipe_tx6_data;
wire [15:0] pipe_tx7_data;
wire pipe_tx0_elec_idle;
wire pipe_tx1_elec_idle;
wire pipe_tx2_elec_idle;
wire pipe_tx3_elec_idle;
wire pipe_tx4_elec_idle;
wire pipe_tx5_elec_idle;
wire pipe_tx6_elec_idle;
wire pipe_tx7_elec_idle;
wire [1:0] pipe_tx0_powerdown;
wire [1:0] pipe_tx1_powerdown;
wire [1:0] pipe_tx2_powerdown;
wire [1:0] pipe_tx3_powerdown;
wire [1:0] pipe_tx4_powerdown;
wire [1:0] pipe_tx5_powerdown;
wire [1:0] pipe_tx6_powerdown;
wire [1:0] pipe_tx7_powerdown;
wire cfg_received_func_lvl_rst_n;
wire cfg_err_cpl_rdy_n;
wire cfg_interrupt_rdy_n;
reg [7:0] cfg_bus_number_d;
reg [4:0] cfg_device_number_d;
reg [2:0] cfg_function_number_d;
wire cfg_mgmt_rd_wr_done_n;
wire pl_phy_lnk_up_n;
wire cfg_err_aer_headerlog_set_n;
assign cfg_received_func_lvl_rst = ~cfg_received_func_lvl_rst_n;
assign cfg_err_cpl_rdy = ~cfg_err_cpl_rdy_n;
assign cfg_interrupt_rdy = ~cfg_interrupt_rdy_n;
assign cfg_mgmt_rd_wr_done = ~cfg_mgmt_rd_wr_done_n;
assign pl_phy_lnk_up = ~pl_phy_lnk_up_n;
assign cfg_err_aer_headerlog_set = ~cfg_err_aer_headerlog_set_n;
assign cfg_to_turnoff = cfg_msg_received_pme_to;
assign cfg_status = {16'b0};
assign cfg_command = {5'b0,
cfg_command_interrupt_disable,
1'b0,
cfg_command_serr_en,
5'b0,
cfg_command_bus_master_enable,
cfg_command_mem_enable,
cfg_command_io_enable};
assign cfg_dstatus = {10'h0,
cfg_trn_pending,
1'b0,
cfg_dev_status_ur_detected,
cfg_dev_status_fatal_err_detected,
cfg_dev_status_non_fatal_err_detected,
cfg_dev_status_corr_err_detected};
assign cfg_dcommand = {1'b0,
cfg_dev_control_max_read_req,
cfg_dev_control_no_snoop_en,
cfg_dev_control_aux_power_en,
cfg_dev_control_phantom_en,
cfg_dev_control_ext_tag_en,
cfg_dev_control_max_payload,
cfg_dev_control_enable_ro,
cfg_dev_control_ur_err_reporting_en,
cfg_dev_control_fatal_err_reporting_en,
cfg_dev_control_non_fatal_reporting_en,
cfg_dev_control_corr_err_reporting_en };
assign cfg_lstatus = {cfg_link_status_auto_bandwidth_status,
cfg_link_status_bandwidth_status,
cfg_link_status_dll_active,
(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
cfg_link_status_link_training,
1'b0,
{2'b00, cfg_link_status_negotiated_width},
{2'b00, cfg_link_status_current_speed} };
assign cfg_lcommand = {4'b0,
cfg_link_control_auto_bandwidth_int_en,
cfg_link_control_bandwidth_int_en,
cfg_link_control_hw_auto_width_dis,
cfg_link_control_clock_pm_en,
cfg_link_control_extended_sync,
cfg_link_control_common_clock,
cfg_link_control_retrain_link,
cfg_link_control_link_disable,
cfg_link_control_rcb,
1'b0,
cfg_link_control_aspm_control};
assign cfg_bus_number = cfg_bus_number_d;
assign cfg_device_number = cfg_device_number_d;
assign cfg_function_number = cfg_function_number_d;
assign cfg_dcommand2 = {4'b0,
cfg_dev_control2_tlp_prefix_block,
cfg_dev_control2_ltr_en,
cfg_dev_control2_ido_cpl_en,
cfg_dev_control2_ido_req_en,
cfg_dev_control2_atomic_egress_block,
cfg_dev_control2_atomic_requester_en,
cfg_dev_control2_ari_forward_en,
cfg_dev_control2_cpl_timeout_dis,
cfg_dev_control2_cpl_timeout_val};
// Capture Bus/Device/Function number
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_bus_number_d <= 8'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_bus_number_d <= cfg_msg_data[15:8];
end // if (~cfg_msg_received)
end
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_device_number_d <= 5'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_device_number_d <= cfg_msg_data[7:3];
end // if (~cfg_msg_received)
end
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_function_number_d <= 3'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_function_number_d <= cfg_msg_data[2:0];
end // if (~cfg_msg_received)
end
pcie_7x_v1_11_0_axi_basic_top #(
.C_DATA_WIDTH (C_DATA_WIDTH), // RX/TX interface data width
.C_FAMILY ("X7"), // Targeted FPGA family
.C_ROOT_PORT ("FALSE"), // PCIe block is in root port mode
.C_PM_PRIORITY ("FALSE") // Disable TX packet boundary thrtl
) axi_basic_top (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata), // input
.s_axis_tx_tvalid (s_axis_tx_tvalid), // input
.s_axis_tx_tready (s_axis_tx_tready), // output
.s_axis_tx_tkeep (s_axis_tx_tkeep), // input
.s_axis_tx_tlast (s_axis_tx_tlast), // input
.s_axis_tx_tuser (s_axis_tx_tuser), // input
// AXI RX
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata), // output
.m_axis_rx_tvalid (m_axis_rx_tvalid), // output
.m_axis_rx_tready (m_axis_rx_tready), // input
.m_axis_rx_tkeep (m_axis_rx_tkeep), // output
.m_axis_rx_tlast (m_axis_rx_tlast), // output
.m_axis_rx_tuser (m_axis_rx_tuser), // output
// User Misc.
//-----------
.user_turnoff_ok (cfg_turnoff_ok), // input
.user_tcfg_gnt (tx_cfg_gnt), // input
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
.trn_td (trn_td), // output
.trn_tsof (trn_tsof), // output
.trn_teof (trn_teof), // output
.trn_tsrc_rdy (trn_tsrc_rdy), // output
.trn_tdst_rdy (trn_tdst_rdy), // input
.trn_tsrc_dsc (trn_tsrc_dsc), // output
.trn_trem (trn_trem), // output
.trn_terrfwd (trn_terrfwd), // output
.trn_tstr (trn_tstr), // output
.trn_tbuf_av (tx_buf_av), // input
.trn_tecrc_gen (trn_tecrc_gen), // output
// TRN RX
//-----------
.trn_rd (trn_rd), // input
.trn_rsof (trn_rsof), // input
.trn_reof (trn_reof), // input
.trn_rsrc_rdy (trn_rsrc_rdy), // input
.trn_rdst_rdy (trn_rdst_rdy), // output
.trn_rsrc_dsc (trn_rsrc_dsc), // input
.trn_rrem (trn_rrem), // input
.trn_rerrfwd (trn_rerrfwd), // input
.trn_rbar_hit (trn_rbar_hit[6:0]), // input
.trn_recrc_err (trn_recrc_err), // input
// TRN Misc.
//-----------
.trn_tcfg_req ( tx_cfg_req ), // input
.trn_tcfg_gnt ( trn_tcfg_gnt), // output
.trn_lnk_up ( user_lnk_up), // input
// Fuji3/Virtex6 PM
//-----------
.cfg_pcie_link_state (cfg_pcie_link_state), // input
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to (1'b0), // input NOT USED FOR EP
.cfg_pmcsr_powerstate (cfg_pmcsr_powerstate), // input
.trn_rdllp_data (32'b0), // input - Not used in 7-series
.trn_rdllp_src_rdy (1'b0), // input -- Not used in 7-series
// Power Mgmt for S6/V6
//-----------
.cfg_to_turnoff (cfg_to_turnoff), // input
.cfg_turnoff_ok (cfg_turnoff_ok_w), // output
// System
//-----------
.user_clk (user_clk_out), // input
.user_rst (user_reset), // input
.np_counter () // output
);
//-------------------------------------------------------
// PCI Express Pipe Wrapper
//-------------------------------------------------------
pcie_7x_v1_11_0_pcie_7x # (
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 (ALLOW_X8_GEN2),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR( CAPABILITIES_PTR ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS (CRM_MODULE_RSTS),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP (DISABLE_RX_POISONED_RESP),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED(DEV_CAP2_ARI_FORWARDING_SUPPORTED),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED (DEV_CAP2_CAS128_COMPLETER_SUPPORTED),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED (DEV_CAP2_LTR_MECHANISM_SUPPORTED),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES (DEV_CAP2_MAX_ENDEND_TLP_PREFIXES),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED (DEV_CAP2_TPH_COMPLETER_SUPPORTED),
.DISABLE_ERR_MSG (DISABLE_ERR_MSG),
.DISABLE_LOCKED_FILTER (DISABLE_LOCKED_FILTER),
.DISABLE_PPM_FILTER (DISABLE_PPM_FILTER),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED),
.ENABLE_MSG_ROUTE( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO (INTERRUPT_STAT_AUTO),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE (MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST( PM_CSR_NOSOFTRST ),
.PM_DATA0( PM_DATA0 ),
.PM_DATA1( PM_DATA1 ),
.PM_DATA2( PM_DATA2 ),
.PM_DATA3( PM_DATA3 ),
.PM_DATA4( PM_DATA4 ),
.PM_DATA5( PM_DATA5 ),
.PM_DATA6( PM_DATA6 ),
.PM_DATA7( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF (PM_MF),
.RBAR_BASE_PTR (RBAR_BASE_PTR),
.RBAR_CAP_CONTROL_ENCODEDBAR0 (RBAR_CAP_CONTROL_ENCODEDBAR0),
.RBAR_CAP_CONTROL_ENCODEDBAR1 (RBAR_CAP_CONTROL_ENCODEDBAR1),
.RBAR_CAP_CONTROL_ENCODEDBAR2 (RBAR_CAP_CONTROL_ENCODEDBAR2),
.RBAR_CAP_CONTROL_ENCODEDBAR3 (RBAR_CAP_CONTROL_ENCODEDBAR3),
.RBAR_CAP_CONTROL_ENCODEDBAR4 (RBAR_CAP_CONTROL_ENCODEDBAR4),
.RBAR_CAP_CONTROL_ENCODEDBAR5 (RBAR_CAP_CONTROL_ENCODEDBAR5),
.RBAR_CAP_ID (RBAR_CAP_ID),
.RBAR_CAP_INDEX0 (RBAR_CAP_INDEX0),
.RBAR_CAP_INDEX1 (RBAR_CAP_INDEX1),
.RBAR_CAP_INDEX2 (RBAR_CAP_INDEX2),
.RBAR_CAP_INDEX3 (RBAR_CAP_INDEX3),
.RBAR_CAP_INDEX4 (RBAR_CAP_INDEX4),
.RBAR_CAP_INDEX5 (RBAR_CAP_INDEX5),
.RBAR_CAP_NEXTPTR (RBAR_CAP_NEXTPTR),
.RBAR_CAP_ON (RBAR_CAP_ON),
.RBAR_CAP_SUP0 (RBAR_CAP_SUP0),
.RBAR_CAP_SUP1 (RBAR_CAP_SUP1),
.RBAR_CAP_SUP2 (RBAR_CAP_SUP2),
.RBAR_CAP_SUP3 (RBAR_CAP_SUP3),
.RBAR_CAP_SUP4 (RBAR_CAP_SUP4),
.RBAR_CAP_SUP5 (RBAR_CAP_SUP5),
.RBAR_CAP_VERSION (RBAR_CAP_VERSION),
.RBAR_NUM (RBAR_NUM),
.RECRC_CHK (RECRC_CHK),
.RECRC_CHK_TRIM (RECRC_CHK_TRIM),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO (SSL_MESSAGE_AUTO),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS(TL_RBYPASS),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW (TRN_DW),
.TRN_NP_FC (TRN_NP_FC),
.UPCONFIG_CAPABLE( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC (UR_ATOMIC),
.UR_CFG1 (UR_CFG1),
.UR_INV_REQ(UR_INV_REQ),
.UR_PRS_RESPONSE (UR_PRS_RESPONSE),
.USER_CLK2_DIV2 (USER_CLK2_DIV2),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS (USE_RID_PINS),
.VC0_CPL_INFINITE( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD (VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION( VSEC_CAP_VERSION )
) pcie_7x_i (
.trn_lnk_up ( trn_lnk_up ),
.trn_clk ( user_clk_out ),
.lnk_clk_en ( lnk_clk_en),
.user_rst_n ( user_rst_n ),
.received_func_lvl_rst_n ( cfg_received_func_lvl_rst_n ),
.sys_rst_n (~phy_rdy_n),
.pl_rst_n ( 1'b1 ),
.dl_rst_n ( 1'b1 ),
.tl_rst_n ( 1'b1 ),
.cm_sticky_rst_n ( 1'b1 ),
.func_lvl_rst_n ( func_lvl_rst_n ),
.cm_rst_n ( cm_rst_n ),
.trn_rbar_hit ( trn_rbar_hit ),
.trn_rd ( trn_rd ),
.trn_recrc_err ( trn_recrc_err ),
.trn_reof ( trn_reof ),
.trn_rerrfwd ( trn_rerrfwd ),
.trn_rrem ( trn_rrem ),
.trn_rsof ( trn_rsof ),
.trn_rsrc_dsc ( trn_rsrc_dsc ),
.trn_rsrc_rdy ( trn_rsrc_rdy ),
.trn_rdst_rdy ( trn_rdst_rdy ),
.trn_rnp_ok ( rx_np_ok ),
.trn_rnp_req ( rx_np_req ),
.trn_rfcp_ret ( 1'b1 ),
.trn_tbuf_av ( tx_buf_av ),
.trn_tcfg_req ( tx_cfg_req ),
.trn_tdllp_dst_rdy ( ),
.trn_tdst_rdy ( trn_tdst_rdy ),
.trn_terr_drop ( tx_err_drop ),
.trn_tcfg_gnt ( trn_tcfg_gnt ),
.trn_td ( trn_td ),
.trn_tdllp_data ( 32'b0 ),
.trn_tdllp_src_rdy ( 1'b0 ),
.trn_tecrc_gen ( trn_tecrc_gen ),
.trn_teof ( trn_teof ),
.trn_terrfwd ( trn_terrfwd ),
.trn_trem ( trn_trem),
.trn_tsof ( trn_tsof ),
.trn_tsrc_dsc ( trn_tsrc_dsc ),
.trn_tsrc_rdy ( trn_tsrc_rdy ),
.trn_tstr ( trn_tstr ),
.trn_fc_cpld ( fc_cpld ),
.trn_fc_cplh ( fc_cplh ),
.trn_fc_npd ( fc_npd ),
.trn_fc_nph ( fc_nph ),
.trn_fc_pd ( fc_pd ),
.trn_fc_ph ( fc_ph ),
.trn_fc_sel ( fc_sel ),
.cfg_dev_id (cfg_dev_id),
.cfg_vend_id (cfg_vend_id),
.cfg_rev_id (cfg_rev_id),
.cfg_subsys_id (cfg_subsys_id),
.cfg_subsys_vend_id (cfg_subsys_vend_id),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.cfg_bridge_serr_en (cfg_bridge_serr_en),
.cfg_command_bus_master_enable ( cfg_command_bus_master_enable ),
.cfg_command_interrupt_disable ( cfg_command_interrupt_disable ),
.cfg_command_io_enable ( cfg_command_io_enable ),
.cfg_command_mem_enable ( cfg_command_mem_enable ),
.cfg_command_serr_en ( cfg_command_serr_en ),
.cfg_dev_control_aux_power_en ( cfg_dev_control_aux_power_en ),
.cfg_dev_control_corr_err_reporting_en ( cfg_dev_control_corr_err_reporting_en ),
.cfg_dev_control_enable_ro ( cfg_dev_control_enable_ro ),
.cfg_dev_control_ext_tag_en ( cfg_dev_control_ext_tag_en ),
.cfg_dev_control_fatal_err_reporting_en ( cfg_dev_control_fatal_err_reporting_en ),
.cfg_dev_control_max_payload ( cfg_dev_control_max_payload ),
.cfg_dev_control_max_read_req ( cfg_dev_control_max_read_req ),
.cfg_dev_control_non_fatal_reporting_en ( cfg_dev_control_non_fatal_reporting_en ),
.cfg_dev_control_no_snoop_en ( cfg_dev_control_no_snoop_en ),
.cfg_dev_control_phantom_en ( cfg_dev_control_phantom_en ),
.cfg_dev_control_ur_err_reporting_en ( cfg_dev_control_ur_err_reporting_en ),
.cfg_dev_control2_cpl_timeout_dis ( cfg_dev_control2_cpl_timeout_dis ),
.cfg_dev_control2_cpl_timeout_val ( cfg_dev_control2_cpl_timeout_val ),
.cfg_dev_control2_ari_forward_en ( cfg_dev_control2_ari_forward_en),
.cfg_dev_control2_atomic_requester_en ( cfg_dev_control2_atomic_requester_en),
.cfg_dev_control2_atomic_egress_block ( cfg_dev_control2_atomic_egress_block),
.cfg_dev_control2_ido_req_en ( cfg_dev_control2_ido_req_en),
.cfg_dev_control2_ido_cpl_en ( cfg_dev_control2_ido_cpl_en),
.cfg_dev_control2_ltr_en ( cfg_dev_control2_ltr_en),
.cfg_dev_control2_tlp_prefix_block ( cfg_dev_control2_tlp_prefix_block),
.cfg_dev_status_corr_err_detected ( cfg_dev_status_corr_err_detected ),
.cfg_dev_status_fatal_err_detected ( cfg_dev_status_fatal_err_detected ),
.cfg_dev_status_non_fatal_err_detected ( cfg_dev_status_non_fatal_err_detected ),
.cfg_dev_status_ur_detected ( cfg_dev_status_ur_detected ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set_n ( cfg_err_aer_headerlog_set_n),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog),
.cfg_err_cpl_rdy_n ( cfg_err_cpl_rdy_n ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy_n ( cfg_interrupt_rdy_n ),
.cfg_link_control_rcb ( cfg_link_control_rcb ),
.cfg_link_control_aspm_control ( cfg_link_control_aspm_control ),
.cfg_link_control_auto_bandwidth_int_en ( cfg_link_control_auto_bandwidth_int_en ),
.cfg_link_control_bandwidth_int_en ( cfg_link_control_bandwidth_int_en ),
.cfg_link_control_clock_pm_en ( cfg_link_control_clock_pm_en ),
.cfg_link_control_common_clock ( cfg_link_control_common_clock ),
.cfg_link_control_extended_sync ( cfg_link_control_extended_sync ),
.cfg_link_control_hw_auto_width_dis ( cfg_link_control_hw_auto_width_dis ),
.cfg_link_control_link_disable ( cfg_link_control_link_disable ),
.cfg_link_control_retrain_link ( cfg_link_control_retrain_link ),
.cfg_link_status_auto_bandwidth_status ( cfg_link_status_auto_bandwidth_status ),
.cfg_link_status_bandwidth_status ( cfg_link_status_bandwidth_status ),
.cfg_link_status_current_speed ( cfg_link_status_current_speed ),
.cfg_link_status_dll_active ( cfg_link_status_dll_active ),
.cfg_link_status_link_training ( cfg_link_status_link_training ),
.cfg_link_status_negotiated_width ( cfg_link_status_negotiated_width),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak),
.cfg_msg_received_pme_to ( cfg_msg_received_pme_to ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit),
.cfg_msg_received_unlock ( cfg_msg_received_unlock),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status),
.cfg_pm_rcv_as_req_l1_n ( cfg_pm_rcv_as_req_l1_n),
.cfg_pm_rcv_enter_l1_n ( cfg_pm_rcv_enter_l1_n),
.cfg_pm_rcv_enter_l23_n ( cfg_pm_rcv_enter_l23_n),
.cfg_pm_rcv_req_ack_n ( cfg_pm_rcv_req_ack_n),
.cfg_mgmt_rd_wr_done_n ( cfg_mgmt_rd_wr_done_n ),
.cfg_slot_control_electromech_il_ctl_pulse (cfg_slot_control_electromech_il_ctl_pulse),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en),
.cfg_aer_rooterr_non_fatal_err_reporting_en( cfg_aer_rooterr_non_fatal_err_reporting_en),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( cfg_transaction),
.cfg_transaction_addr ( cfg_transaction_addr),
.cfg_transaction_type ( cfg_transaction_type),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map),
.cfg_mgmt_byte_en_n ( cfg_mgmt_byte_en_n ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( cfg_err_cor_n ),
.cfg_err_cpl_abort_n ( cfg_err_cpl_abort_n ),
.cfg_err_cpl_timeout_n ( cfg_err_cpl_timeout_n ),
.cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n ),
.cfg_err_ecrc_n ( cfg_err_ecrc_n ),
.cfg_err_locked_n ( cfg_err_locked_n ),
.cfg_err_posted_n ( cfg_err_posted_n ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( cfg_err_ur_n ),
.cfg_err_malformed_n ( cfg_err_malformed_n ),
.cfg_err_poisoned_n ( cfg_err_poisoned_n),
.cfg_err_atomic_egress_blocked_n ( cfg_err_atomic_egress_blocked_n ),
.cfg_err_mc_blocked_n ( cfg_err_mc_blocked_n ),
.cfg_err_internal_uncor_n ( cfg_err_internal_uncor_n ),
.cfg_err_internal_cor_n ( cfg_err_internal_cor_n ),
.cfg_err_norecovery_n ( cfg_err_norecovery_n ),
.cfg_interrupt_assert_n ( cfg_interrupt_assert_n ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( cfg_interrupt_n ),
.cfg_interrupt_stat_n ( cfg_interrupt_stat_n),
.cfg_pm_send_pme_to_n ( cfg_pm_send_pme_to_n ),
.cfg_pm_turnoff_ok_n ( cfg_turnoff_ok_w ),
.cfg_pm_wake_n ( cfg_pm_wake_n ),
.cfg_pm_halt_aspm_l0s_n ( cfg_pm_halt_aspm_l0s_n ),
.cfg_pm_halt_aspm_l1_n ( cfg_pm_halt_aspm_l1_n ),
.cfg_pm_force_state_en_n ( cfg_pm_force_state_en_n ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( cfg_force_mps ),
.cfg_force_common_clock_off ( cfg_force_common_clock_off ),
.cfg_force_extended_sync_on ( cfg_force_extended_sync_on ),
.cfg_port_number ( cfg_port_number ),
.cfg_mgmt_rd_en_n ( cfg_mgmt_rd_en_n ),
.cfg_trn_pending_n ( ~cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( cfg_mgmt_wr_en_n ),
.cfg_mgmt_wr_readonly_n ( cfg_mgmt_wr_readonly_n ),
.cfg_mgmt_wr_rw1c_as_rw_n ( cfg_mgmt_wr_rw1c_as_rw_n ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_phy_lnk_up_n ( pl_phy_lnk_up_n ),
.pl_received_hot_rst ( pl_received_hot_rst ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( pl_directed_ltssm_new_vld ),
.pl_directed_ltssm_new ( pl_directed_ltssm_new ),
.pl_directed_ltssm_stall ( pl_directed_ltssm_stall ),
.pl_directed_change_done ( pl_directed_change_done ),
.dbg_sclr_a ( dbg_sclr_a ),
.dbg_sclr_b ( dbg_sclr_b ),
.dbg_sclr_c ( dbg_sclr_c ),
.dbg_sclr_d ( dbg_sclr_d ),
.dbg_sclr_e ( dbg_sclr_e ),
.dbg_sclr_f ( dbg_sclr_f ),
.dbg_sclr_g ( dbg_sclr_g ),
.dbg_sclr_h ( dbg_sclr_h ),
.dbg_sclr_i ( dbg_sclr_i ),
.dbg_sclr_j ( dbg_sclr_j ),
.dbg_sclr_k ( dbg_sclr_k ),
.dbg_vec_a ( dbg_vec_a ),
.dbg_vec_b ( dbg_vec_b ),
.dbg_vec_c ( dbg_vec_c ),
.pl_dbg_vec ( pl_dbg_vec ),
.dbg_mode ( dbg_mode ),
.dbg_sub_mode ( dbg_sub_mode ),
.pl_dbg_mode ( pl_dbg_mode ),
.drp_do ( drp_do ),
.drp_rdy ( drp_rdy ),
.drp_clk ( drp_clk ),
.drp_addr ( drp_addr ),
.drp_en ( drp_en ),
.drp_di ( drp_di ),
.drp_we ( drp_we ),
.ll2_tlp_rcv ( 1'b0 ),
.ll2_send_enter_l1 ( 1'b0 ),
.ll2_send_enter_l23 ( 1'b0 ),
.ll2_send_as_req_l1 ( 1'b0 ),
.ll2_send_pm_ack ( 1'b0 ),
.ll2_suspend_now ( 1'b0 ),
.ll2_tfc_init1_seq ( ),
.ll2_tfc_init2_seq ( ),
.ll2_suspend_ok ( ),
.ll2_tx_idle ( ),
.ll2_link_status ( ),
.ll2_receiver_err ( ),
.ll2_protocol_err ( ),
.ll2_bad_tlp_err ( ),
.ll2_bad_dllp_err ( ),
.ll2_replay_ro_err ( ),
.ll2_replay_to_err ( ),
.tl2_ppm_suspend_req ( 1'b0 ),
.tl2_aspm_suspend_credit_check ( 1'b0 ),
.tl2_ppm_suspend_ok ( ),
.tl2_aspm_suspend_req ( ),
.tl2_aspm_suspend_credit_check_ok ( ),
.tl2_err_hdr ( ),
.tl2_err_malformed ( ),
.tl2_err_rxoverflow ( ),
.tl2_err_fcpe ( ),
.pl2_directed_lstate ( 5'b0 ),
.pl2_suspend_ok ( ),
.pl2_recovery ( ),
.pl2_rx_elec_idle ( ),
.pl2_rx_pm_state ( ),
.pl2_l0_req ( ),
.pl2_link_up ( ),
.pl2_receiver_err ( ),
.trn_rdllp_data (trn_rdllp_data ),
.trn_rdllp_src_rdy (trn_rdllp_src_rdy ),
.pipe_clk ( pipe_clk ),
.user_clk2 ( user_clk2 ),
.user_clk ( user_clk ),
.user_clk_prebuf ( 1'b0 ),
.user_clk_prebuf_en ( 1'b0 ),
.pipe_rx0_polarity ( pipe_rx0_polarity ),
.pipe_rx1_polarity ( pipe_rx1_polarity ),
.pipe_rx2_polarity ( pipe_rx2_polarity ),
.pipe_rx3_polarity ( pipe_rx3_polarity ),
.pipe_rx4_polarity ( pipe_rx4_polarity ),
.pipe_rx5_polarity ( pipe_rx5_polarity ),
.pipe_rx6_polarity ( pipe_rx6_polarity ),
.pipe_rx7_polarity ( pipe_rx7_polarity ),
.pipe_tx0_compliance ( pipe_tx0_compliance ),
.pipe_tx1_compliance ( pipe_tx1_compliance ),
.pipe_tx2_compliance ( pipe_tx2_compliance ),
.pipe_tx3_compliance ( pipe_tx3_compliance ),
.pipe_tx4_compliance ( pipe_tx4_compliance ),
.pipe_tx5_compliance ( pipe_tx5_compliance ),
.pipe_tx6_compliance ( pipe_tx6_compliance ),
.pipe_tx7_compliance ( pipe_tx7_compliance ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k ),
.pipe_tx0_data ( pipe_tx0_data ),
.pipe_tx1_data ( pipe_tx1_data ),
.pipe_tx2_data ( pipe_tx2_data ),
.pipe_tx3_data ( pipe_tx3_data ),
.pipe_tx4_data ( pipe_tx4_data ),
.pipe_tx5_data ( pipe_tx5_data ),
.pipe_tx6_data ( pipe_tx6_data ),
.pipe_tx7_data ( pipe_tx7_data ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown ),
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k ),
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k ),
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k ),
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k ),
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k ),
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k ),
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k ),
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k ),
.pipe_rx0_valid ( pipe_rx0_valid ),
.pipe_rx1_valid ( pipe_rx1_valid ),
.pipe_rx2_valid ( pipe_rx2_valid ),
.pipe_rx3_valid ( pipe_rx3_valid ),
.pipe_rx4_valid ( pipe_rx4_valid ),
.pipe_rx5_valid ( pipe_rx5_valid ),
.pipe_rx6_valid ( pipe_rx6_valid ),
.pipe_rx7_valid ( pipe_rx7_valid ),
.pipe_rx0_data ( pipe_rx0_data ),
.pipe_rx1_data ( pipe_rx1_data ),
.pipe_rx2_data ( pipe_rx2_data ),
.pipe_rx3_data ( pipe_rx3_data ),
.pipe_rx4_data ( pipe_rx4_data ),
.pipe_rx5_data ( pipe_rx5_data ),
.pipe_rx6_data ( pipe_rx6_data ),
.pipe_rx7_data ( pipe_rx7_data ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned ),
.pipe_rx0_status ( pipe_rx0_status ),
.pipe_rx1_status ( pipe_rx1_status ),
.pipe_rx2_status ( pipe_rx2_status ),
.pipe_rx3_status ( pipe_rx3_status ),
.pipe_rx4_status ( pipe_rx4_status ),
.pipe_rx5_status ( pipe_rx5_status ),
.pipe_rx6_status ( pipe_rx6_status ),
.pipe_rx7_status ( pipe_rx7_status ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status ),
.pipe_tx_deemph ( pipe_tx_deemph ),
.pipe_tx_margin ( pipe_tx_margin ),
.pipe_tx_reset ( pipe_tx_reset ),
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det ),
.pipe_tx_rate ( pipe_tx_rate ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle )
);
//------------------------------------------------------------------------------------------------------------------//
// PIPE Interface PIPELINE Module //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_11_0_pcie_pipe_pipeline # (
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES )
)
pcie_pipe_pipeline_i (
// Pipe Per-Link Signals
.pipe_tx_rcvr_det_i (pipe_tx_rcvr_det),
.pipe_tx_reset_i (1'b0), //MV?
.pipe_tx_rate_i (pipe_tx_rate),
.pipe_tx_deemph_i (pipe_tx_deemph),
.pipe_tx_margin_i (pipe_tx_margin),
.pipe_tx_swing_i (1'b0),
.pipe_tx_rcvr_det_o (pipe_tx_rcvr_det_gt),
.pipe_tx_reset_o ( ),
.pipe_tx_rate_o (pipe_tx_rate_gt),
.pipe_tx_deemph_o (pipe_tx_deemph_gt),
.pipe_tx_margin_o (pipe_tx_margin_gt),
.pipe_tx_swing_o ( ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k_o (pipe_rx0_char_is_k ),
.pipe_rx0_data_o (pipe_rx0_data ),
.pipe_rx0_valid_o (pipe_rx0_valid ),
.pipe_rx0_chanisaligned_o (pipe_rx0_chanisaligned ),
.pipe_rx0_status_o (pipe_rx0_status ),
.pipe_rx0_phy_status_o (pipe_rx0_phy_status ),
.pipe_rx0_elec_idle_i (pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity_i (pipe_rx0_polarity ),
.pipe_tx0_compliance_i (pipe_tx0_compliance ),
.pipe_tx0_char_is_k_i (pipe_tx0_char_is_k ),
.pipe_tx0_data_i (pipe_tx0_data ),
.pipe_tx0_elec_idle_i (pipe_tx0_elec_idle ),
.pipe_tx0_powerdown_i (pipe_tx0_powerdown ),
.pipe_rx0_char_is_k_i (pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_i (pipe_rx0_data_gt ),
.pipe_rx0_valid_i (pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned_i (pipe_rx0_chanisaligned_gt),
.pipe_rx0_status_i (pipe_rx0_status_gt ),
.pipe_rx0_phy_status_i (pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle_o (pipe_rx0_elec_idle ),
.pipe_rx0_polarity_o (pipe_rx0_polarity_gt ),
.pipe_tx0_compliance_o (pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k_o (pipe_tx0_char_is_k_gt ),
.pipe_tx0_data_o (pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_o (pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_o (pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k_o (pipe_rx1_char_is_k ),
.pipe_rx1_data_o (pipe_rx1_data ),
.pipe_rx1_valid_o (pipe_rx1_valid ),
.pipe_rx1_chanisaligned_o (pipe_rx1_chanisaligned ),
.pipe_rx1_status_o (pipe_rx1_status ),
.pipe_rx1_phy_status_o (pipe_rx1_phy_status ),
.pipe_rx1_elec_idle_i (pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity_i (pipe_rx1_polarity ),
.pipe_tx1_compliance_i (pipe_tx1_compliance ),
.pipe_tx1_char_is_k_i (pipe_tx1_char_is_k ),
.pipe_tx1_data_i (pipe_tx1_data ),
.pipe_tx1_elec_idle_i (pipe_tx1_elec_idle ),
.pipe_tx1_powerdown_i (pipe_tx1_powerdown ),
.pipe_rx1_char_is_k_i (pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_i (pipe_rx1_data_gt ),
.pipe_rx1_valid_i (pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned_i (pipe_rx1_chanisaligned_gt),
.pipe_rx1_status_i (pipe_rx1_status_gt ),
.pipe_rx1_phy_status_i (pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle_o (pipe_rx1_elec_idle ),
.pipe_rx1_polarity_o (pipe_rx1_polarity_gt ),
.pipe_tx1_compliance_o (pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k_o (pipe_tx1_char_is_k_gt ),
.pipe_tx1_data_o (pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_o (pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_o (pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k_o (pipe_rx2_char_is_k ),
.pipe_rx2_data_o (pipe_rx2_data ),
.pipe_rx2_valid_o (pipe_rx2_valid ),
.pipe_rx2_chanisaligned_o (pipe_rx2_chanisaligned ),
.pipe_rx2_status_o (pipe_rx2_status ),
.pipe_rx2_phy_status_o (pipe_rx2_phy_status ),
.pipe_rx2_elec_idle_i (pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity_i (pipe_rx2_polarity ),
.pipe_tx2_compliance_i (pipe_tx2_compliance ),
.pipe_tx2_char_is_k_i (pipe_tx2_char_is_k ),
.pipe_tx2_data_i (pipe_tx2_data ),
.pipe_tx2_elec_idle_i (pipe_tx2_elec_idle ),
.pipe_tx2_powerdown_i (pipe_tx2_powerdown ),
.pipe_rx2_char_is_k_i (pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_i (pipe_rx2_data_gt ),
.pipe_rx2_valid_i (pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned_i (pipe_rx2_chanisaligned_gt),
.pipe_rx2_status_i (pipe_rx2_status_gt ),
.pipe_rx2_phy_status_i (pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle_o (pipe_rx2_elec_idle ),
.pipe_rx2_polarity_o (pipe_rx2_polarity_gt ),
.pipe_tx2_compliance_o (pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k_o (pipe_tx2_char_is_k_gt ),
.pipe_tx2_data_o (pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_o (pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_o (pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k_o (pipe_rx3_char_is_k ),
.pipe_rx3_data_o (pipe_rx3_data ),
.pipe_rx3_valid_o (pipe_rx3_valid ),
.pipe_rx3_chanisaligned_o (pipe_rx3_chanisaligned ),
.pipe_rx3_status_o (pipe_rx3_status ),
.pipe_rx3_phy_status_o (pipe_rx3_phy_status ),
.pipe_rx3_elec_idle_i (pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity_i (pipe_rx3_polarity ),
.pipe_tx3_compliance_i (pipe_tx3_compliance ),
.pipe_tx3_char_is_k_i (pipe_tx3_char_is_k ),
.pipe_tx3_data_i (pipe_tx3_data ),
.pipe_tx3_elec_idle_i (pipe_tx3_elec_idle ),
.pipe_tx3_powerdown_i (pipe_tx3_powerdown ),
.pipe_rx3_char_is_k_i (pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_i (pipe_rx3_data_gt ),
.pipe_rx3_valid_i (pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned_i (pipe_rx3_chanisaligned_gt),
.pipe_rx3_status_i (pipe_rx3_status_gt ),
.pipe_rx3_phy_status_i (pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle_o (pipe_rx3_elec_idle ),
.pipe_rx3_polarity_o (pipe_rx3_polarity_gt ),
.pipe_tx3_compliance_o (pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k_o (pipe_tx3_char_is_k_gt ),
.pipe_tx3_data_o (pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_o (pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_o (pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k_o (pipe_rx4_char_is_k ),
.pipe_rx4_data_o (pipe_rx4_data ),
.pipe_rx4_valid_o (pipe_rx4_valid ),
.pipe_rx4_chanisaligned_o (pipe_rx4_chanisaligned ),
.pipe_rx4_status_o (pipe_rx4_status ),
.pipe_rx4_phy_status_o (pipe_rx4_phy_status ),
.pipe_rx4_elec_idle_i (pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity_i (pipe_rx4_polarity ),
.pipe_tx4_compliance_i (pipe_tx4_compliance ),
.pipe_tx4_char_is_k_i (pipe_tx4_char_is_k ),
.pipe_tx4_data_i (pipe_tx4_data ),
.pipe_tx4_elec_idle_i (pipe_tx4_elec_idle ),
.pipe_tx4_powerdown_i (pipe_tx4_powerdown ),
.pipe_rx4_char_is_k_i (pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_i (pipe_rx4_data_gt ),
.pipe_rx4_valid_i (pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned_i (pipe_rx4_chanisaligned_gt),
.pipe_rx4_status_i (pipe_rx4_status_gt ),
.pipe_rx4_phy_status_i (pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle_o (pipe_rx4_elec_idle ),
.pipe_rx4_polarity_o (pipe_rx4_polarity_gt ),
.pipe_tx4_compliance_o (pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k_o (pipe_tx4_char_is_k_gt ),
.pipe_tx4_data_o (pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_o (pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_o (pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k_o (pipe_rx5_char_is_k ),
.pipe_rx5_data_o (pipe_rx5_data ),
.pipe_rx5_valid_o (pipe_rx5_valid ),
.pipe_rx5_chanisaligned_o (pipe_rx5_chanisaligned ),
.pipe_rx5_status_o (pipe_rx5_status ),
.pipe_rx5_phy_status_o (pipe_rx5_phy_status ),
.pipe_rx5_elec_idle_i (pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity_i (pipe_rx5_polarity ),
.pipe_tx5_compliance_i (pipe_tx5_compliance ),
.pipe_tx5_char_is_k_i (pipe_tx5_char_is_k ),
.pipe_tx5_data_i (pipe_tx5_data ),
.pipe_tx5_elec_idle_i (pipe_tx5_elec_idle ),
.pipe_tx5_powerdown_i (pipe_tx5_powerdown ),
.pipe_rx5_char_is_k_i (pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_i (pipe_rx5_data_gt ),
.pipe_rx5_valid_i (pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned_i (pipe_rx5_chanisaligned_gt),
.pipe_rx5_status_i (pipe_rx5_status_gt ),
.pipe_rx5_phy_status_i (pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle_o (pipe_rx5_elec_idle ),
.pipe_rx5_polarity_o (pipe_rx5_polarity_gt ),
.pipe_tx5_compliance_o (pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k_o (pipe_tx5_char_is_k_gt ),
.pipe_tx5_data_o (pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_o (pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_o (pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k_o (pipe_rx6_char_is_k ),
.pipe_rx6_data_o (pipe_rx6_data ),
.pipe_rx6_valid_o (pipe_rx6_valid ),
.pipe_rx6_chanisaligned_o (pipe_rx6_chanisaligned ),
.pipe_rx6_status_o (pipe_rx6_status ),
.pipe_rx6_phy_status_o (pipe_rx6_phy_status ),
.pipe_rx6_elec_idle_i (pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity_i (pipe_rx6_polarity ),
.pipe_tx6_compliance_i (pipe_tx6_compliance ),
.pipe_tx6_char_is_k_i (pipe_tx6_char_is_k ),
.pipe_tx6_data_i (pipe_tx6_data ),
.pipe_tx6_elec_idle_i (pipe_tx6_elec_idle ),
.pipe_tx6_powerdown_i (pipe_tx6_powerdown ),
.pipe_rx6_char_is_k_i (pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_i (pipe_rx6_data_gt ),
.pipe_rx6_valid_i (pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned_i (pipe_rx6_chanisaligned_gt),
.pipe_rx6_status_i (pipe_rx6_status_gt ),
.pipe_rx6_phy_status_i (pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle_o (pipe_rx6_elec_idle ),
.pipe_rx6_polarity_o (pipe_rx6_polarity_gt ),
.pipe_tx6_compliance_o (pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k_o (pipe_tx6_char_is_k_gt ),
.pipe_tx6_data_o (pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_o (pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_o (pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k_o (pipe_rx7_char_is_k ),
.pipe_rx7_data_o (pipe_rx7_data ),
.pipe_rx7_valid_o (pipe_rx7_valid ),
.pipe_rx7_chanisaligned_o (pipe_rx7_chanisaligned ),
.pipe_rx7_status_o (pipe_rx7_status ),
.pipe_rx7_phy_status_o (pipe_rx7_phy_status ),
.pipe_rx7_elec_idle_i (pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity_i (pipe_rx7_polarity ),
.pipe_tx7_compliance_i (pipe_tx7_compliance ),
.pipe_tx7_char_is_k_i (pipe_tx7_char_is_k ),
.pipe_tx7_data_i (pipe_tx7_data ),
.pipe_tx7_elec_idle_i (pipe_tx7_elec_idle ),
.pipe_tx7_powerdown_i (pipe_tx7_powerdown ),
.pipe_rx7_char_is_k_i (pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_i (pipe_rx7_data_gt ),
.pipe_rx7_valid_i (pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned_i (pipe_rx7_chanisaligned_gt),
.pipe_rx7_status_i (pipe_rx7_status_gt ),
.pipe_rx7_phy_status_i (pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle_o (pipe_rx7_elec_idle ),
.pipe_rx7_polarity_o (pipe_rx7_polarity_gt ),
.pipe_tx7_compliance_o (pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k_o (pipe_tx7_char_is_k_gt ),
.pipe_tx7_data_o (pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_o (pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_o (pipe_tx7_powerdown_gt ),
// Non PIPE signals
.pipe_clk (pipe_clk ),
.rst_n (phy_rdy_n )
);
endmodule
|
module mac_tb;
parameter INTERMEDIATOR_DEPTH = 1024;
parameter LOG2_INTERMEDIATOR_DEPTH = log2(INTERMEDIATOR_DEPTH - 1);
parameter MATRIX_FILENAME = "../../src/tmp/cant/cant.mtx";
reg clk, rst, wr;
reg [LOG2_INTERMEDIATOR_DEPTH - 1:0] row;
reg [63:0] v0, v1;
wire push_out;
wire [63:0] v_out;
reg eof;
wire stall;
reg stall_out;
mac #(INTERMEDIATOR_DEPTH) dut(clk, rst, wr, row, v0, v1, push_out, v_out, eof, stall, stall_out);
initial begin
clk = 0;
forever #5 clk = !clk;
end
reg [63:0] floats [0:10000000];
reg [63:0] row_index [0:10000000];
reg [63:0] col_index [0:10000000];
integer file;
integer bufferSize = 100;
reg [100 * 8 - 1:0] string;
integer M, N, nnz;
integer r;
integer i = 0;
integer tmp1, tmp2;
real tmp3;
initial begin
$readmemh("floats.hex", floats);
$readmemh("row.hex", row_index);
$readmemh("col.hex", col_index);
file = $fopen(MATRIX_FILENAME, "r");
r = $fgets(string, file);
r = $fscanf(file, "%d%d%d", M, N, nnz);
for(i = 0; i < nnz; i = i + 1) begin
$fscanf(file, "%d%d%f", tmp1, tmp2, tmp3);
//$display("tmp1: %d", tmp1);
row_index[i] = tmp1 - 1;
col_index[i] = tmp2 - 1;
floats[i] = $realtobits(tmp3);
end
$display("finshed reading mtx file");
end
integer stall_count = 0;
initial begin
rst = 1;
wr = 0;
row = 0;
v0 = 0;
v1 = 0;
eof = 0;
stall_out = 0;
#1000 rst = 0;
#100;
for(i = 0; i < nnz; i = i + 1) begin
while(stall) begin
stall_count = stall_count + 1;
wr = 0;
#10;
end
wr = 1;
row = row_index[i];
v0 = floats[i];
v1 = floats[col_index[i]];
//$display("pushing: row: %d, v0: %f, v0: %f", row, $bitstoreal(v0), $bitstoreal(v1));
#10;
end
wr = 0;
//eof = 1;
#10000 eof = 1;
#10 eof = 0;
end
wire multiplier_push_ieee;
wire [63:0] ieee_multiplier_out;
flopoco_to_ieee conv_after_mult(clk, dut.multiplier_push, dut.multiplier_out, multiplier_push_ieee, ieee_multiplier_out);
wire adder_push_ieee;
wire [63:0] ieee_adder_out;
flopoco_to_ieee conv_after_add(clk, dut.adder_push_out, dut.adder_out, adder_push_ieee, ieee_adder_out);
wire [63:0] before_adder_v0, before_adder_v1;
wire push_before_adder;
flopoco_to_ieee conv_before_add0(clk, dut.intermediator_push_to_adder, dut.intermediator_v0_to_adder, push_before_adder, before_adder_v0);
flopoco_to_ieee conv_before_add1(clk, dut.intermediator_push_to_adder, dut.intermediator_v1_to_adder, , before_adder_v1);
integer out_count;
initial begin
#1000000000 $display("watchdog reached");
$display("out_count: %d", out_count);
$display("stall_count: %d", stall_count);
$finish;
end
initial begin
#20000 $display("endgame:");
$display("window end: %d", dut.intermediator_inst.window_end);
end
initial out_count = 0;
always @(posedge clk) begin
if(out_count == M) begin
$display("reached the end");
$display("@verilog:out_count: %d", out_count);
$display("@verilog:stall_count: %d : %d", stall_count, nnz);
$finish;
end
if(push_out) begin
//$display("push_out: %d, %f", v_out, $bitstoreal(v_out));
out_count = out_count + 1;
end
/*
if(dut.flopoco_conv_push)
$display("flopoco_conv_push");
if(dut.multiplier_push)
$display("multiplier_push: row: %d", dut.multiplier_row);
if(dut.intermediator_push_to_adder)
$display("adder push");
if(dut.adder_push_out)
$display("adder output");
if(multiplier_push_ieee)
$display("multiplier_out: %f", $bitstoreal(ieee_multiplier_out));
if(dut.adder_push_out)
$display("flopoco adder out: %H", dut.adder_out);
if(adder_push_ieee)begin
$display("adder_out: %H %f", ieee_adder_out, $bitstoreal(ieee_adder_out));
end
if(push_before_adder) begin
$display("before adder: v0: %f v1: %f", $bitstoreal(before_adder_v0), $bitstoreal(before_adder_v1));
end
*/
/*
if(dut.multiplier_push)
$display("flopoco multiplier_out: %H", dut.multiplier_out);
*/
/*
if(dut.intermediator_inst.p0_stage_0)
$display("intermediator p0_stage_0");
if(dut.intermediator_inst.p0_stage_1)
$display("intermediator p0_stage_1");
if(dut.intermediator_inst.p0_stage_2)
$display("intermediator p0_stage_2");
if(dut.intermediator_inst.p0_stage_3)
$display("intermediator p0_stage_3");
if(dut.intermediator_inst.p0_stage_5)
$display("intermediator p0_stage_5");
if(dut.intermediator_inst.p0_stage_6)
$display("intermediator p0_stage_6");
if(dut.intermediator_inst.to_adder_stage_7)
$display("intermediator to adder stage 7");
if(dut.intermediator_inst.overflow_fifo_pop_stage_5)
$display("intermediator popping overflow fifo");
*/
/*
$display("overflow_fifo_empty: %d", dut.intermediator_inst.overflow_fifo_empty);
$display("p1_stage_5: %d", dut.intermediator_inst.p1_stage_5);
$display("p1_stage_3: %d", dut.intermediator_inst.p1_stage_3);
$display("p1_stage_0: %d", dut.intermediator_inst.p1_stage_0);
*/
end
`include "common.vh"
endmodule
|
`include "Definition.v"
`include "ProcessSelect.v"
`include "ProcessProperty.v"
module ColorImageProcess#
(
parameter[ 2 : 0 ]ReadState = 0, // read raw data operation
parameter[ 2 : 0 ]ALState = 1, // auto level
parameter[ 2 : 0 ]WBState = 2, // white balance
parameter[ 2 : 0 ]RemainderState = 3, // color correction
// forward space
// saturation enhancement
// backward space
// tone reproduction
// gamma correction
parameter[ 2 : 0 ]WriteState = 4
)
(
input Clock,
input Reset,
input[ `size_char - 1 : 0 ]R,
input[ `size_char - 1 : 0 ]G,
input[ `size_char - 1 : 0 ]B,
output reg[ `size_char - 1 : 0 ]R_out,
output reg[ `size_char - 1 : 0 ]G_out,
output reg[ `size_char - 1 : 0 ]B_out
);
reg[ `size_int - 1 : 0 ]ScaleR[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleG[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleB[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleRTemp;
reg[ `size_int - 1 : 0 ]ScaleGTemp;
reg[ `size_int - 1 : 0 ]ScaleBTemp;
reg[ 3 : 0 ]StateNow;
reg[ 3 : 0 ]StateNext;
// counter
integer i;
integer ReadIndex;
integer WriteIndex;
// CTC
reg[ `size_int - 1 : 0 ]RFactor;
reg[ `size_int - 1 : 0 ]BFactor;
// variable declaration
reg[ `size_int + `size_int - 1 : 0 ]RLongTotal;
reg[ `size_int + `size_int - 1 : 0 ]GLongTotal;
reg[ `size_int + `size_int - 1 : 0 ]BLongTotal;
reg[ `size_int - 1 : 0 ]RTotal;
reg[ `size_int - 1 : 0 ]GTotal;
reg[ `size_int - 1 : 0 ]BTotal;
// divider usage
reg[ `size_int - 1 : 0 ]GRIndex;
reg[ `size_int - 1 : 0 ]GBIndex;
// color space
reg[ `size_int - 1 : 0 ]CIEL;
// declaration is signed type, a or b maybe negative value
reg signed[ `size_int - 1 : 0 ]CIEa;
reg signed[ `size_int - 1 : 0 ]CIEb;
reg[ `size_int - 1 : 0 ]X;
reg[ `size_int - 1 : 0 ]Y;
reg[ `size_int - 1 : 0 ]Z;
reg[ `size_int - 1 : 0 ]fX;
reg[ `size_int - 1 : 0 ]fY;
reg[ `size_int - 1 : 0 ]fZ;
always@( posedge Clock )
begin
if( Reset == 1'b1 )
begin
ReadIndex = 0;
WriteIndex = 0;
RLongTotal = 0;
GLongTotal = 0;
BLongTotal = 0;
StateNext = ReadState;
end
end
always@( StateNext )
StateNow = StateNext;
always@( posedge Clock )
begin
if( StateNow == ReadState )
begin
////////////////
// read raw data
ScaleR[ ReadIndex ] = R << `ScaleBit;
ScaleG[ ReadIndex ] = G << `ScaleBit;
ScaleB[ ReadIndex ] = B << `ScaleBit;
ReadIndex = ReadIndex + 1;
if( ReadIndex == `SumPixel )
StateNext = ALState;
end
else if( StateNow == WriteState )
begin
if( WriteIndex < `SumPixel )
begin
R_out = ScaleR[ WriteIndex ] >> `ScaleBit;
G_out = ScaleG[ WriteIndex ] >> `ScaleBit;
B_out = ScaleB[ WriteIndex ] >> `ScaleBit;
WriteIndex = WriteIndex + 1;
end
end
end
always@( StateNow )
begin
case( StateNow )
/////////////
// auto level
ALState:
begin
`ifdef EnableAL
for( i = 0; i < `SumPixel; i = i + 1 )
begin
ScaleRTemp = ScaleR[ i ];
ScaleGTemp = ScaleG[ i ];
ScaleBTemp = ScaleB[ i ];
if( ( ScaleRTemp > `LowThreshold ) && ( ScaleRTemp < `HighThreshold ) )
ScaleR[ i ] = `Scale * ( ScaleRTemp - `LowThreshold );
else if( ScaleRTemp <= `LowThreshold )
ScaleR[ i ] = `MinThreshold;
else // ScaleRTemp >= `HighThreshold
ScaleR[ i ] = `MaxThreshold;
if( ( ScaleGTemp > `LowThreshold ) && ( ScaleGTemp < `HighThreshold ) )
ScaleG[ i ] = `Scale * ( ScaleGTemp - `LowThreshold );
else if( ScaleGTemp <= `LowThreshold )
ScaleG[ i ] = `MinThreshold;
else // ScaleGTemp >= `HighThreshold
ScaleG[ i ] = `MaxThreshold;
if( ( ScaleBTemp > `LowThreshold ) && ( ScaleBTemp < `HighThreshold ) )
ScaleB[ i ] = `Scale * ( ScaleBTemp - `LowThreshold );
else if( ScaleBTemp <= `LowThreshold )
ScaleB[ i ] = `MinThreshold;
else // ScaleBTemp >= `HighThreshold
ScaleB[ i ] = `MaxThreshold;
end
`endif // EnableAL
StateNext = WBState;
end
////////////////
// white balance
WBState:
begin
`ifdef EnableWB
for( i = 0; i < `SumPixel; i = i + 1 )
begin
RLongTotal = RLongTotal + ScaleR[ i ];
GLongTotal = GLongTotal + ScaleG[ i ];
BLongTotal = BLongTotal + ScaleB[ i ];
end
RTotal = RLongTotal >> `ScaleHalfBit;
GTotal = GLongTotal >> `ScaleHalfBit;
BTotal = BLongTotal >> `ScaleHalfBit;
// GR ratio, scale = 16
GRIndex = Divider( GTotal, RTotal >> `ScaleHalfBit );
// GB ratio, scale = 16
GBIndex = Divider( GTotal, BTotal >> `ScaleHalfBit );
if( ( GRIndex >= 16 ) && ( GRIndex <= 40 ) )
GRIndex = GRIndex - 16;
else if( GRIndex < 16 )
GRIndex = 0;
else
GRIndex = 23;
if( ( GBIndex >= 16 ) && ( GBIndex <= 40 ) )
GBIndex = GBIndex - 16;
else if( GBIndex < 16 )
GBIndex = 0;
else
GBIndex = 23;
LUTCTCFactor( GRIndex * 24 + GBIndex, RFactor, BFactor );
// RFactor = ( RFactor * `WBRCorrection ) >> `ScaleBit;
// BFactor = ( BFactor * `WBBCorrection ) >> `ScaleBit;
for( i = 0; i < `SumPixel; i = i + 1 )
begin
ScaleRTemp = ( ScaleR[ i ] * RFactor ) >> `ScaleBit;
ScaleBTemp = ( ScaleB[ i ] * BFactor ) >> `ScaleBit;
ScaleR[ i ] = ( ScaleRTemp[ 17 : 16 ] == 2'b00 ) ? ScaleRTemp : ( ScaleRTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
ScaleB[ i ] = ( ScaleBTemp[ 17 : 16 ] == 2'b00 ) ? ScaleBTemp : ( ScaleBTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
end
`endif // EnableWB
StateNext = RemainderState;
end
/////////////////////////
// color correction
// forward space
// saturation enhancement
// backward space
// tone reproduction
// gamma correction
RemainderState:
begin
for( i = 0; i < `SumPixel; i = i + 1 )
begin
`ifdef EnableCC
///////////////////
// color correction
ScaleRTemp = ( ScaleR[ i ] * `CC1 - ScaleG[ i ] * `CC2 - ScaleB[ i ] * `CC3 ) >> `ScaleBit;
ScaleGTemp = ( -ScaleR[ i ] * `CC4 + ScaleG[ i ] * `CC5 - ScaleB[ i ] * `CC6 ) >> `ScaleBit;
ScaleBTemp = ( ScaleR[ i ] * `CC7 - ScaleG[ i ] * `CC8 + ScaleB[ i ] * `CC9 ) >> `ScaleBit;
ScaleR[ i ] = ( ScaleRTemp[ 17 : 16 ] == 2'b00 ) ? ScaleRTemp : ( ScaleRTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
ScaleG[ i ] = ( ScaleGTemp[ 17 : 16 ] == 2'b00 ) ? ScaleGTemp : ( ScaleGTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
ScaleB[ i ] = ( ScaleBTemp[ 17 : 16 ] == 2'b00 ) ? ScaleBTemp : ( ScaleBTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
`endif // EnableCC
`ifdef EnableSpace
////////////////
// forward space
// 256 * 0.950456 * 256
X = ( ScaleR[ i ] * `RGB2XYZ1 + ScaleG[ i ] * `RGB2XYZ2 + ScaleB[ i ] * `RGB2XYZ3 ) >> ( `ScaleBit + `ScaleBit );
X = ( X * 269 ) >> `ScaleBit; // 256 / 0.950456 = 269.34439
Y = ( ScaleR[ i ] * `RGB2XYZ4 + ScaleG[ i ] * `RGB2XYZ5 + ScaleB[ i ] * `RGB2XYZ6 ) >> ( `ScaleBit + `ScaleBit );
// 256 * 1.088754 * 256
Z = ( ScaleR[ i ] * `RGB2XYZ7 + ScaleG[ i ] * `RGB2XYZ8 + ScaleB[ i ] * `RGB2XYZ9 ) >> ( `ScaleBit + `ScaleBit );
Z = ( Z * 235 ) >> `ScaleBit; // 256 / 1.088754 = 235.13116
// avoid extreme case of Y
if( Y < `RGB2LabLimit )
Y = `RGB2LabLimit;
// avoid extreme case of X
if( X < `RGB2LabLimit )
X = `RGB2LabLimit;
// avoid extreme case of Z
if( Z < `RGB2LabLimit )
Z = `RGB2LabLimit;
fX = LUTPow033( X );
fY = LUTPow033( Y );
fZ = LUTPow033( Z );
CIEL = 116 * fY - `pow_16_256_1_3;
CIEa = 500 * ( fX - fY );
CIEb = 200 * ( fY - fZ );
`endif // EnableSpace
`ifdef EnableSE
/////////////////////////
// saturation enhancement
CIEa = ( CIEa * `SE_a ) >>> `ScaleBit;
CIEb = ( CIEb * `SE_b ) >>> `ScaleBit;
// operator <<<, >>>
// If operand is signed, the right shift fills the vacated bit positions with the MSB.
// If it is unsigned, the vacated bit positions are filled with zeros.
// The left shift fills vacated positions with zeros.
`endif // EnableSE
`ifdef EnableSpace
/////////////////
// backward space
// proto type formulation
// fY = ( CIEL + pow_16_256_1_3 ) / 116;
// fX = CIEa / 500 + fY;
// fZ = fY - CIEb / 200;
// fY = ( ( CIEL + pow_16_256_1_3 ) / 116 ) << ( `ScaleBit + `ScaleBit );
// fX = ( ( CIEa / 500 ) << ( `ScaleBit + `ScaleBit ) ) + fY;
// fZ = fY - ( CIEb / 200 ) << ( `ScaleBit + `ScaleBit );
// avoid usage of the division
fY = ( CIEL + `pow_16_256_1_3 ) * 565;
fX = CIEa * 131 + fY;
fZ = fY - CIEb * 328;
// avoid extreme case of fY
if( fY < `Lab2RGBLimit )
fY = `Lab2RGBLimit;
// avoid extreme case of fX
if( fX < `Lab2RGBLimit )
fX = `Lab2RGBLimit;
// avoid extreme case of fZ
if( fZ < `Lab2RGBLimit )
fZ = `Lab2RGBLimit;
// in case of over-range of power 3 operation later
// fY = fY >> `ScaleHalfBit;
fY = fY >> ( `ScaleHalfBit + `ScaleBit + `ScaleBit );
Y = fY * fY * fY;
Y = ( Y * 256 ) >> `ScaleBit;
// in case of over-range of power 3 operation later
// fX = fX >> `ScaleHalfBit;
fX = fX >> ( `ScaleHalfBit + `ScaleBit + `ScaleBit );
X = fX * fX * fX;
X = ( X * 243 ) >> `ScaleBit; // 256 * 0.950456 = 243.316736
// in case of over-range of power 3 operation later
// fZ = fZ >> `ScaleHalfBit;
fZ = fZ >> ( `ScaleHalfBit + `ScaleBit + `ScaleBit );
Z = fZ * fZ * fZ;
Z = ( Z * 279 ) >> `ScaleBit; // 256 * 1.088754 = 278.721024
ScaleRTemp = ( `XYZ2RGB1 * X - `XYZ2RGB2 * Y - `XYZ2RGB3 * Z )
>> ( `ScaleBit + `ScaleHalfBit );
ScaleGTemp = ( -`XYZ2RGB4 * X + `XYZ2RGB5 * Y + `XYZ2RGB6 * Z )
>> ( `ScaleBit + `ScaleHalfBit );
ScaleBTemp = ( `XYZ2RGB7 * X - `XYZ2RGB8 * Y + `XYZ2RGB9 * Z )
>> ( `ScaleBit + `ScaleHalfBit );
ScaleR[ i ] = ( ScaleRTemp[ 17 : 16 ] == 2'b00 ) ? ScaleRTemp : ( ScaleRTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
ScaleG[ i ] = ( ScaleGTemp[ 17 : 16 ] == 2'b00 ) ? ScaleGTemp : ( ScaleGTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
ScaleB[ i ] = ( ScaleBTemp[ 17 : 16 ] == 2'b00 ) ? ScaleBTemp : ( ScaleBTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
`endif // EnableSpace
`ifdef EnableGC
///////////////////
// gamma correction
ScaleR[ i ] = LUTPow045( ScaleR[ i ] >> `ScaleBit );
ScaleG[ i ] = LUTPow045( ScaleG[ i ] >> `ScaleBit );
ScaleB[ i ] = LUTPow045( ScaleB[ i ] >> `ScaleBit );
`endif // EnableGC
end
StateNext = WriteState;
end
endcase
end
/*
always@( posedge WriteEnable )
begin
R_out = ScaleR[ WriteEnableIndex ] >> `ScaleBit;
G_out = ScaleG[ WriteEnableIndex ] >> `ScaleBit;
B_out = ScaleB[ WriteEnableIndex ] >> `ScaleBit;
WriteEnableIndex = WriteEnableIndex + 1;
end
*/
function[ `size_int - 1 : 0 ]Divider
(
input[ `size_int - 1 : 0 ]Dividend,
input[ `size_int - 1 : 0 ]Divisor
);
reg[ `size_int - 1 : 0 ]Quotient; // Quotient
reg[ `size_int - 1 : 0 ]Remainder; // Remainder
reg[ `size_int : 0 ]Partial;
reg[ `size_int - 1 : 0 ]div;
begin
Quotient = Dividend;
div = Divisor;
Partial = { `size_int'h00, 1'b0 };
for( i = 0; i < `size_int; i = i + 1 )
begin
Partial = { Partial[ `size_int - 1 : 0 ], Quotient[ `size_int - 1 ] };
Quotient = { Quotient[ `size_int - 2 : 0 ], 1'b0 };
Partial = Partial + { ~{ 1'b0, div } + 1'b1 }; // subtraction
if( Partial[ `size_int ] == 1'b0 )
Quotient[ 0 ] = 1'b1;
else
begin
Partial = Partial + div;
Quotient[ 0 ] = 1'b0;
end
end
Remainder = Partial[ `size_int - 1 : 0 ];
//to round up or down
if( Remainder * 10 >= Divisor * 5 )
Divider = Quotient + 1;
else
Divider = Quotient;
end
endfunction
// ratio = 1.0 ~ 2.5
// scale = 16
// ratio * 16 = 16 ~ 40
// every layer size = 40 - 16 = 24
// it needed to be modified
task LUTCTCFactor
(
input[ `size_int - 1 : 0 ]Index,
output[ `size_int - 1 : 0 ]RFactor,
output[ `size_int - 1 : 0 ]BFactor
);
begin
case( Index )
0 : begin RFactor = 417; BFactor = 414; end // GR = 1.00, GB = 1.00
1 : begin RFactor = 405; BFactor = 427; end // GR = 1.00, GB = 1.06
2 : begin RFactor = 394; BFactor = 440; end // GR = 1.00, GB = 1.12
3 : begin RFactor = 383; BFactor = 452; end // GR = 1.00, GB = 1.19
4 : begin RFactor = 373; BFactor = 464; end // GR = 1.00, GB = 1.25
5 : begin RFactor = 364; BFactor = 476; end // GR = 1.00, GB = 1.31
6 : begin RFactor = 356; BFactor = 487; end // GR = 1.00, GB = 1.38
7 : begin RFactor = 348; BFactor = 498; end // GR = 1.00, GB = 1.44
8 : begin RFactor = 341; BFactor = 509; end // GR = 1.00, GB = 1.50
9 : begin RFactor = 334; BFactor = 520; end // GR = 1.00, GB = 1.56
10 : begin RFactor = 327; BFactor = 530; end // GR = 1.00, GB = 1.62
11 : begin RFactor = 321; BFactor = 540; end // GR = 1.00, GB = 1.69
12 : begin RFactor = 315; BFactor = 551; end // GR = 1.00, GB = 1.75
13 : begin RFactor = 310; BFactor = 560; end // GR = 1.00, GB = 1.81
14 : begin RFactor = 305; BFactor = 570; end // GR = 1.00, GB = 1.88
15 : begin RFactor = 300; BFactor = 580; end // GR = 1.00, GB = 1.94
16 : begin RFactor = 295; BFactor = 589; end // GR = 1.00, GB = 2.00
17 : begin RFactor = 291; BFactor = 599; end // GR = 1.00, GB = 2.06
18 : begin RFactor = 286; BFactor = 608; end // GR = 1.00, GB = 2.12
19 : begin RFactor = 282; BFactor = 617; end // GR = 1.00, GB = 2.19
20 : begin RFactor = 278; BFactor = 626; end // GR = 1.00, GB = 2.25
21 : begin RFactor = 274; BFactor = 634; end // GR = 1.00, GB = 2.31
22 : begin RFactor = 271; BFactor = 643; end // GR = 1.00, GB = 2.38
23 : begin RFactor = 267; BFactor = 652; end // GR = 1.00, GB = 2.44
24 : begin RFactor = 430; BFactor = 402; end // GR = 1.06, GB = 1.00
25 : begin RFactor = 417; BFactor = 414; end // GR = 1.06, GB = 1.06
26 : begin RFactor = 405; BFactor = 427; end // GR = 1.06, GB = 1.12
27 : begin RFactor = 395; BFactor = 438; end // GR = 1.06, GB = 1.19
28 : begin RFactor = 385; BFactor = 450; end // GR = 1.06, GB = 1.25
29 : begin RFactor = 375; BFactor = 461; end // GR = 1.06, GB = 1.31
30 : begin RFactor = 367; BFactor = 472; end // GR = 1.06, GB = 1.38
31 : begin RFactor = 359; BFactor = 483; end // GR = 1.06, GB = 1.44
32 : begin RFactor = 351; BFactor = 494; end // GR = 1.06, GB = 1.50
33 : begin RFactor = 344; BFactor = 504; end // GR = 1.06, GB = 1.56
34 : begin RFactor = 337; BFactor = 514; end // GR = 1.06, GB = 1.62
35 : begin RFactor = 331; BFactor = 524; end // GR = 1.06, GB = 1.69
36 : begin RFactor = 325; BFactor = 534; end // GR = 1.06, GB = 1.75
37 : begin RFactor = 319; BFactor = 544; end // GR = 1.06, GB = 1.81
38 : begin RFactor = 314; BFactor = 553; end // GR = 1.06, GB = 1.88
39 : begin RFactor = 309; BFactor = 562; end // GR = 1.06, GB = 1.94
40 : begin RFactor = 304; BFactor = 572; end // GR = 1.06, GB = 2.00
41 : begin RFactor = 299; BFactor = 581; end // GR = 1.06, GB = 2.06
42 : begin RFactor = 295; BFactor = 590; end // GR = 1.06, GB = 2.12
43 : begin RFactor = 291; BFactor = 598; end // GR = 1.06, GB = 2.19
44 : begin RFactor = 287; BFactor = 607; end // GR = 1.06, GB = 2.25
45 : begin RFactor = 283; BFactor = 615; end // GR = 1.06, GB = 2.31
46 : begin RFactor = 279; BFactor = 624; end // GR = 1.06, GB = 2.38
47 : begin RFactor = 275; BFactor = 632; end // GR = 1.06, GB = 2.44
48 : begin RFactor = 442; BFactor = 390; end // GR = 1.12, GB = 1.00
49 : begin RFactor = 429; BFactor = 403; end // GR = 1.12, GB = 1.06
50 : begin RFactor = 417; BFactor = 415; end // GR = 1.12, GB = 1.12
51 : begin RFactor = 406; BFactor = 426; end // GR = 1.12, GB = 1.19
52 : begin RFactor = 396; BFactor = 437; end // GR = 1.12, GB = 1.25
53 : begin RFactor = 386; BFactor = 448; end // GR = 1.12, GB = 1.31
54 : begin RFactor = 377; BFactor = 459; end // GR = 1.12, GB = 1.38
55 : begin RFactor = 369; BFactor = 470; end // GR = 1.12, GB = 1.44
56 : begin RFactor = 361; BFactor = 480; end // GR = 1.12, GB = 1.50
57 : begin RFactor = 354; BFactor = 490; end // GR = 1.12, GB = 1.56
58 : begin RFactor = 347; BFactor = 500; end // GR = 1.12, GB = 1.62
59 : begin RFactor = 340; BFactor = 510; end // GR = 1.12, GB = 1.69
60 : begin RFactor = 334; BFactor = 519; end // GR = 1.12, GB = 1.75
61 : begin RFactor = 328; BFactor = 528; end // GR = 1.12, GB = 1.81
62 : begin RFactor = 323; BFactor = 538; end // GR = 1.12, GB = 1.88
63 : begin RFactor = 318; BFactor = 547; end // GR = 1.12, GB = 1.94
64 : begin RFactor = 313; BFactor = 555; end // GR = 1.12, GB = 2.00
65 : begin RFactor = 308; BFactor = 564; end // GR = 1.12, GB = 2.06
66 : begin RFactor = 303; BFactor = 573; end // GR = 1.12, GB = 2.12
67 : begin RFactor = 299; BFactor = 581; end // GR = 1.12, GB = 2.19
68 : begin RFactor = 295; BFactor = 590; end // GR = 1.12, GB = 2.25
69 : begin RFactor = 291; BFactor = 598; end // GR = 1.12, GB = 2.31
70 : begin RFactor = 287; BFactor = 606; end // GR = 1.12, GB = 2.38
71 : begin RFactor = 283; BFactor = 614; end // GR = 1.12, GB = 2.44
72 : begin RFactor = 454; BFactor = 380; end // GR = 1.19, GB = 1.00
73 : begin RFactor = 441; BFactor = 392; end // GR = 1.19, GB = 1.06
74 : begin RFactor = 428; BFactor = 403; end // GR = 1.19, GB = 1.12
75 : begin RFactor = 417; BFactor = 415; end // GR = 1.19, GB = 1.19
76 : begin RFactor = 406; BFactor = 426; end // GR = 1.19, GB = 1.25
77 : begin RFactor = 396; BFactor = 436; end // GR = 1.19, GB = 1.31
78 : begin RFactor = 387; BFactor = 447; end // GR = 1.19, GB = 1.38
79 : begin RFactor = 379; BFactor = 457; end // GR = 1.19, GB = 1.44
80 : begin RFactor = 371; BFactor = 467; end // GR = 1.19, GB = 1.50
81 : begin RFactor = 363; BFactor = 477; end // GR = 1.19, GB = 1.56
82 : begin RFactor = 356; BFactor = 486; end // GR = 1.19, GB = 1.62
83 : begin RFactor = 350; BFactor = 496; end // GR = 1.19, GB = 1.69
84 : begin RFactor = 343; BFactor = 505; end // GR = 1.19, GB = 1.75
85 : begin RFactor = 337; BFactor = 514; end // GR = 1.19, GB = 1.81
86 : begin RFactor = 332; BFactor = 523; end // GR = 1.19, GB = 1.88
87 : begin RFactor = 326; BFactor = 532; end // GR = 1.19, GB = 1.94
88 : begin RFactor = 321; BFactor = 541; end // GR = 1.19, GB = 2.00
89 : begin RFactor = 316; BFactor = 549; end // GR = 1.19, GB = 2.06
90 : begin RFactor = 312; BFactor = 558; end // GR = 1.19, GB = 2.12
91 : begin RFactor = 307; BFactor = 566; end // GR = 1.19, GB = 2.19
92 : begin RFactor = 303; BFactor = 574; end // GR = 1.19, GB = 2.25
93 : begin RFactor = 299; BFactor = 582; end // GR = 1.19, GB = 2.31
94 : begin RFactor = 295; BFactor = 590; end // GR = 1.19, GB = 2.38
95 : begin RFactor = 291; BFactor = 598; end // GR = 1.19, GB = 2.44
96 : begin RFactor = 466; BFactor = 370; end // GR = 1.25, GB = 1.00
97 : begin RFactor = 452; BFactor = 382; end // GR = 1.25, GB = 1.06
98 : begin RFactor = 439; BFactor = 393; end // GR = 1.25, GB = 1.12
99 : begin RFactor = 428; BFactor = 404; end // GR = 1.25, GB = 1.19
100 : begin RFactor = 417; BFactor = 415; end // GR = 1.25, GB = 1.25
101 : begin RFactor = 407; BFactor = 425; end // GR = 1.25, GB = 1.31
102 : begin RFactor = 397; BFactor = 436; end // GR = 1.25, GB = 1.38
103 : begin RFactor = 389; BFactor = 445; end // GR = 1.25, GB = 1.44
104 : begin RFactor = 380; BFactor = 455; end // GR = 1.25, GB = 1.50
105 : begin RFactor = 373; BFactor = 465; end // GR = 1.25, GB = 1.56
106 : begin RFactor = 365; BFactor = 474; end // GR = 1.25, GB = 1.62
107 : begin RFactor = 359; BFactor = 483; end // GR = 1.25, GB = 1.69
108 : begin RFactor = 352; BFactor = 492; end // GR = 1.25, GB = 1.75
109 : begin RFactor = 346; BFactor = 501; end // GR = 1.25, GB = 1.81
110 : begin RFactor = 340; BFactor = 510; end // GR = 1.25, GB = 1.88
111 : begin RFactor = 335; BFactor = 519; end // GR = 1.25, GB = 1.94
112 : begin RFactor = 329; BFactor = 527; end // GR = 1.25, GB = 2.00
113 : begin RFactor = 324; BFactor = 535; end // GR = 1.25, GB = 2.06
114 : begin RFactor = 319; BFactor = 543; end // GR = 1.25, GB = 2.12
115 : begin RFactor = 315; BFactor = 552; end // GR = 1.25, GB = 2.19
116 : begin RFactor = 310; BFactor = 559; end // GR = 1.25, GB = 2.25
117 : begin RFactor = 306; BFactor = 567; end // GR = 1.25, GB = 2.31
118 : begin RFactor = 302; BFactor = 575; end // GR = 1.25, GB = 2.38
119 : begin RFactor = 298; BFactor = 583; end // GR = 1.25, GB = 2.44
120 : begin RFactor = 477; BFactor = 361; end // GR = 1.31, GB = 1.00
121 : begin RFactor = 463; BFactor = 373; end // GR = 1.31, GB = 1.06
122 : begin RFactor = 450; BFactor = 384; end // GR = 1.31, GB = 1.12
123 : begin RFactor = 438; BFactor = 394; end // GR = 1.31, GB = 1.19
124 : begin RFactor = 427; BFactor = 405; end // GR = 1.31, GB = 1.25
125 : begin RFactor = 417; BFactor = 415; end // GR = 1.31, GB = 1.31
126 : begin RFactor = 407; BFactor = 425; end // GR = 1.31, GB = 1.38
127 : begin RFactor = 398; BFactor = 435; end // GR = 1.31, GB = 1.44
128 : begin RFactor = 390; BFactor = 444; end // GR = 1.31, GB = 1.50
129 : begin RFactor = 382; BFactor = 454; end // GR = 1.31, GB = 1.56
130 : begin RFactor = 374; BFactor = 463; end // GR = 1.31, GB = 1.62
131 : begin RFactor = 367; BFactor = 472; end // GR = 1.31, GB = 1.69
132 : begin RFactor = 361; BFactor = 480; end // GR = 1.31, GB = 1.75
133 : begin RFactor = 354; BFactor = 489; end // GR = 1.31, GB = 1.81
134 : begin RFactor = 348; BFactor = 498; end // GR = 1.31, GB = 1.88
135 : begin RFactor = 343; BFactor = 506; end // GR = 1.31, GB = 1.94
136 : begin RFactor = 337; BFactor = 514; end // GR = 1.31, GB = 2.00
137 : begin RFactor = 332; BFactor = 522; end // GR = 1.31, GB = 2.06
138 : begin RFactor = 327; BFactor = 530; end // GR = 1.31, GB = 2.12
139 : begin RFactor = 323; BFactor = 538; end // GR = 1.31, GB = 2.19
140 : begin RFactor = 318; BFactor = 546; end // GR = 1.31, GB = 2.25
141 : begin RFactor = 314; BFactor = 554; end // GR = 1.31, GB = 2.31
142 : begin RFactor = 310; BFactor = 561; end // GR = 1.31, GB = 2.38
143 : begin RFactor = 306; BFactor = 569; end // GR = 1.31, GB = 2.44
144 : begin RFactor = 488; BFactor = 353; end // GR = 1.38, GB = 1.00
145 : begin RFactor = 474; BFactor = 364; end // GR = 1.38, GB = 1.06
146 : begin RFactor = 460; BFactor = 375; end // GR = 1.38, GB = 1.12
147 : begin RFactor = 448; BFactor = 385; end // GR = 1.38, GB = 1.19
148 : begin RFactor = 437; BFactor = 396; end // GR = 1.38, GB = 1.25
149 : begin RFactor = 426; BFactor = 406; end // GR = 1.38, GB = 1.31
150 : begin RFactor = 416; BFactor = 415; end // GR = 1.38, GB = 1.38
151 : begin RFactor = 407; BFactor = 425; end // GR = 1.38, GB = 1.44
152 : begin RFactor = 399; BFactor = 434; end // GR = 1.38, GB = 1.50
153 : begin RFactor = 391; BFactor = 443; end // GR = 1.38, GB = 1.56
154 : begin RFactor = 383; BFactor = 452; end // GR = 1.38, GB = 1.62
155 : begin RFactor = 376; BFactor = 461; end // GR = 1.38, GB = 1.69
156 : begin RFactor = 369; BFactor = 469; end // GR = 1.38, GB = 1.75
157 : begin RFactor = 363; BFactor = 478; end // GR = 1.38, GB = 1.81
158 : begin RFactor = 356; BFactor = 486; end // GR = 1.38, GB = 1.88
159 : begin RFactor = 351; BFactor = 494; end // GR = 1.38, GB = 1.94
160 : begin RFactor = 345; BFactor = 502; end // GR = 1.38, GB = 2.00
161 : begin RFactor = 340; BFactor = 510; end // GR = 1.38, GB = 2.06
162 : begin RFactor = 335; BFactor = 518; end // GR = 1.38, GB = 2.12
163 : begin RFactor = 330; BFactor = 526; end // GR = 1.38, GB = 2.19
164 : begin RFactor = 325; BFactor = 533; end // GR = 1.38, GB = 2.25
165 : begin RFactor = 321; BFactor = 541; end // GR = 1.38, GB = 2.31
166 : begin RFactor = 317; BFactor = 548; end // GR = 1.38, GB = 2.38
167 : begin RFactor = 313; BFactor = 556; end // GR = 1.38, GB = 2.44
168 : begin RFactor = 499; BFactor = 345; end // GR = 1.44, GB = 1.00
169 : begin RFactor = 484; BFactor = 356; end // GR = 1.44, GB = 1.06
170 : begin RFactor = 471; BFactor = 367; end // GR = 1.44, GB = 1.12
171 : begin RFactor = 458; BFactor = 377; end // GR = 1.44, GB = 1.19
172 : begin RFactor = 446; BFactor = 387; end // GR = 1.44, GB = 1.25
173 : begin RFactor = 436; BFactor = 397; end // GR = 1.44, GB = 1.31
174 : begin RFactor = 426; BFactor = 406; end // GR = 1.44, GB = 1.38
175 : begin RFactor = 416; BFactor = 415; end // GR = 1.44, GB = 1.44
176 : begin RFactor = 407; BFactor = 424; end // GR = 1.44, GB = 1.50
177 : begin RFactor = 399; BFactor = 433; end // GR = 1.44, GB = 1.56
178 : begin RFactor = 391; BFactor = 442; end // GR = 1.44, GB = 1.62
179 : begin RFactor = 384; BFactor = 451; end // GR = 1.44, GB = 1.69
180 : begin RFactor = 377; BFactor = 459; end // GR = 1.44, GB = 1.75
181 : begin RFactor = 371; BFactor = 467; end // GR = 1.44, GB = 1.81
182 : begin RFactor = 364; BFactor = 476; end // GR = 1.44, GB = 1.88
183 : begin RFactor = 358; BFactor = 484; end // GR = 1.44, GB = 1.94
184 : begin RFactor = 353; BFactor = 491; end // GR = 1.44, GB = 2.00
185 : begin RFactor = 347; BFactor = 499; end // GR = 1.44, GB = 2.06
186 : begin RFactor = 342; BFactor = 507; end // GR = 1.44, GB = 2.12
187 : begin RFactor = 337; BFactor = 514; end // GR = 1.44, GB = 2.19
188 : begin RFactor = 333; BFactor = 522; end // GR = 1.44, GB = 2.25
189 : begin RFactor = 328; BFactor = 529; end // GR = 1.44, GB = 2.31
190 : begin RFactor = 324; BFactor = 536; end // GR = 1.44, GB = 2.38
191 : begin RFactor = 320; BFactor = 543; end // GR = 1.44, GB = 2.44
192 : begin RFactor = 510; BFactor = 338; end // GR = 1.50, GB = 1.00
193 : begin RFactor = 494; BFactor = 349; end // GR = 1.50, GB = 1.06
194 : begin RFactor = 481; BFactor = 359; end // GR = 1.50, GB = 1.12
195 : begin RFactor = 468; BFactor = 369; end // GR = 1.50, GB = 1.19
196 : begin RFactor = 456; BFactor = 379; end // GR = 1.50, GB = 1.25
197 : begin RFactor = 445; BFactor = 388; end // GR = 1.50, GB = 1.31
198 : begin RFactor = 435; BFactor = 398; end // GR = 1.50, GB = 1.38
199 : begin RFactor = 425; BFactor = 407; end // GR = 1.50, GB = 1.44
200 : begin RFactor = 416; BFactor = 416; end // GR = 1.50, GB = 1.50
201 : begin RFactor = 408; BFactor = 424; end // GR = 1.50, GB = 1.56
202 : begin RFactor = 400; BFactor = 433; end // GR = 1.50, GB = 1.62
203 : begin RFactor = 392; BFactor = 441; end // GR = 1.50, GB = 1.69
204 : begin RFactor = 385; BFactor = 449; end // GR = 1.50, GB = 1.75
205 : begin RFactor = 378; BFactor = 458; end // GR = 1.50, GB = 1.81
206 : begin RFactor = 372; BFactor = 465; end // GR = 1.50, GB = 1.88
207 : begin RFactor = 366; BFactor = 473; end // GR = 1.50, GB = 1.94
208 : begin RFactor = 360; BFactor = 481; end // GR = 1.50, GB = 2.00
209 : begin RFactor = 355; BFactor = 489; end // GR = 1.50, GB = 2.06
210 : begin RFactor = 350; BFactor = 496; end // GR = 1.50, GB = 2.12
211 : begin RFactor = 344; BFactor = 503; end // GR = 1.50, GB = 2.19
212 : begin RFactor = 340; BFactor = 511; end // GR = 1.50, GB = 2.25
213 : begin RFactor = 335; BFactor = 518; end // GR = 1.50, GB = 2.31
214 : begin RFactor = 331; BFactor = 525; end // GR = 1.50, GB = 2.38
215 : begin RFactor = 326; BFactor = 532; end // GR = 1.50, GB = 2.44
216 : begin RFactor = 520; BFactor = 331; end // GR = 1.56, GB = 1.00
217 : begin RFactor = 505; BFactor = 342; end // GR = 1.56, GB = 1.06
218 : begin RFactor = 490; BFactor = 352; end // GR = 1.56, GB = 1.12
219 : begin RFactor = 477; BFactor = 362; end // GR = 1.56, GB = 1.19
220 : begin RFactor = 465; BFactor = 371; end // GR = 1.56, GB = 1.25
221 : begin RFactor = 454; BFactor = 380; end // GR = 1.56, GB = 1.31
222 : begin RFactor = 443; BFactor = 390; end // GR = 1.56, GB = 1.38
223 : begin RFactor = 434; BFactor = 398; end // GR = 1.56, GB = 1.44
224 : begin RFactor = 425; BFactor = 407; end // GR = 1.56, GB = 1.50
225 : begin RFactor = 416; BFactor = 416; end // GR = 1.56, GB = 1.56
226 : begin RFactor = 408; BFactor = 424; end // GR = 1.56, GB = 1.62
227 : begin RFactor = 400; BFactor = 432; end // GR = 1.56, GB = 1.69
228 : begin RFactor = 393; BFactor = 440; end // GR = 1.56, GB = 1.75
229 : begin RFactor = 386; BFactor = 448; end // GR = 1.56, GB = 1.81
230 : begin RFactor = 380; BFactor = 456; end // GR = 1.56, GB = 1.88
231 : begin RFactor = 373; BFactor = 464; end // GR = 1.56, GB = 1.94
232 : begin RFactor = 368; BFactor = 471; end // GR = 1.56, GB = 2.00
233 : begin RFactor = 362; BFactor = 479; end // GR = 1.56, GB = 2.06
234 : begin RFactor = 357; BFactor = 486; end // GR = 1.56, GB = 2.12
235 : begin RFactor = 351; BFactor = 493; end // GR = 1.56, GB = 2.19
236 : begin RFactor = 347; BFactor = 500; end // GR = 1.56, GB = 2.25
237 : begin RFactor = 342; BFactor = 507; end // GR = 1.56, GB = 2.31
238 : begin RFactor = 337; BFactor = 514; end // GR = 1.56, GB = 2.38
239 : begin RFactor = 333; BFactor = 521; end // GR = 1.56, GB = 2.44
240 : begin RFactor = 530; BFactor = 325; end // GR = 1.62, GB = 1.00
241 : begin RFactor = 514; BFactor = 335; end // GR = 1.62, GB = 1.06
242 : begin RFactor = 500; BFactor = 345; end // GR = 1.62, GB = 1.12
243 : begin RFactor = 486; BFactor = 354; end // GR = 1.62, GB = 1.19
244 : begin RFactor = 474; BFactor = 364; end // GR = 1.62, GB = 1.25
245 : begin RFactor = 463; BFactor = 373; end // GR = 1.62, GB = 1.31
246 : begin RFactor = 452; BFactor = 382; end // GR = 1.62, GB = 1.38
247 : begin RFactor = 442; BFactor = 391; end // GR = 1.62, GB = 1.44
248 : begin RFactor = 433; BFactor = 399; end // GR = 1.62, GB = 1.50
249 : begin RFactor = 424; BFactor = 408; end // GR = 1.62, GB = 1.56
250 : begin RFactor = 416; BFactor = 416; end // GR = 1.62, GB = 1.62
251 : begin RFactor = 408; BFactor = 424; end // GR = 1.62, GB = 1.69
252 : begin RFactor = 401; BFactor = 432; end // GR = 1.62, GB = 1.75
253 : begin RFactor = 394; BFactor = 440; end // GR = 1.62, GB = 1.81
254 : begin RFactor = 387; BFactor = 447; end // GR = 1.62, GB = 1.88
255 : begin RFactor = 381; BFactor = 455; end // GR = 1.62, GB = 1.94
256 : begin RFactor = 375; BFactor = 462; end // GR = 1.62, GB = 2.00
257 : begin RFactor = 369; BFactor = 469; end // GR = 1.62, GB = 2.06
258 : begin RFactor = 364; BFactor = 477; end // GR = 1.62, GB = 2.12
259 : begin RFactor = 358; BFactor = 484; end // GR = 1.62, GB = 2.19
260 : begin RFactor = 353; BFactor = 491; end // GR = 1.62, GB = 2.25
261 : begin RFactor = 348; BFactor = 498; end // GR = 1.62, GB = 2.31
262 : begin RFactor = 344; BFactor = 504; end // GR = 1.62, GB = 2.38
263 : begin RFactor = 339; BFactor = 511; end // GR = 1.62, GB = 2.44
264 : begin RFactor = 540; BFactor = 319; end // GR = 1.69, GB = 1.00
265 : begin RFactor = 524; BFactor = 329; end // GR = 1.69, GB = 1.06
266 : begin RFactor = 509; BFactor = 338; end // GR = 1.69, GB = 1.12
267 : begin RFactor = 496; BFactor = 348; end // GR = 1.69, GB = 1.19
268 : begin RFactor = 483; BFactor = 357; end // GR = 1.69, GB = 1.25
269 : begin RFactor = 471; BFactor = 366; end // GR = 1.69, GB = 1.31
270 : begin RFactor = 461; BFactor = 375; end // GR = 1.69, GB = 1.38
271 : begin RFactor = 450; BFactor = 383; end // GR = 1.69, GB = 1.44
272 : begin RFactor = 441; BFactor = 392; end // GR = 1.69, GB = 1.50
273 : begin RFactor = 432; BFactor = 400; end // GR = 1.69, GB = 1.56
274 : begin RFactor = 424; BFactor = 408; end // GR = 1.69, GB = 1.62
275 : begin RFactor = 416; BFactor = 416; end // GR = 1.69, GB = 1.69
276 : begin RFactor = 408; BFactor = 424; end // GR = 1.69, GB = 1.75
277 : begin RFactor = 401; BFactor = 431; end // GR = 1.69, GB = 1.81
278 : begin RFactor = 394; BFactor = 439; end // GR = 1.69, GB = 1.88
279 : begin RFactor = 388; BFactor = 446; end // GR = 1.69, GB = 1.94
280 : begin RFactor = 382; BFactor = 453; end // GR = 1.69, GB = 2.00
281 : begin RFactor = 376; BFactor = 461; end // GR = 1.69, GB = 2.06
282 : begin RFactor = 370; BFactor = 468; end // GR = 1.69, GB = 2.12
283 : begin RFactor = 365; BFactor = 475; end // GR = 1.69, GB = 2.19
284 : begin RFactor = 360; BFactor = 481; end // GR = 1.69, GB = 2.25
285 : begin RFactor = 355; BFactor = 488; end // GR = 1.69, GB = 2.31
286 : begin RFactor = 350; BFactor = 495; end // GR = 1.69, GB = 2.38
287 : begin RFactor = 346; BFactor = 501; end // GR = 1.69, GB = 2.44
288 : begin RFactor = 550; BFactor = 313; end // GR = 1.75, GB = 1.00
289 : begin RFactor = 533; BFactor = 323; end // GR = 1.75, GB = 1.06
290 : begin RFactor = 518; BFactor = 332; end // GR = 1.75, GB = 1.12
291 : begin RFactor = 505; BFactor = 342; end // GR = 1.75, GB = 1.19
292 : begin RFactor = 492; BFactor = 351; end // GR = 1.75, GB = 1.25
293 : begin RFactor = 480; BFactor = 359; end // GR = 1.75, GB = 1.31
294 : begin RFactor = 469; BFactor = 368; end // GR = 1.75, GB = 1.38
295 : begin RFactor = 459; BFactor = 376; end // GR = 1.75, GB = 1.44
296 : begin RFactor = 449; BFactor = 385; end // GR = 1.75, GB = 1.50
297 : begin RFactor = 440; BFactor = 393; end // GR = 1.75, GB = 1.56
298 : begin RFactor = 431; BFactor = 401; end // GR = 1.75, GB = 1.62
299 : begin RFactor = 423; BFactor = 408; end // GR = 1.75, GB = 1.69
300 : begin RFactor = 416; BFactor = 416; end // GR = 1.75, GB = 1.75
301 : begin RFactor = 408; BFactor = 424; end // GR = 1.75, GB = 1.81
302 : begin RFactor = 401; BFactor = 431; end // GR = 1.75, GB = 1.88
303 : begin RFactor = 395; BFactor = 438; end // GR = 1.75, GB = 1.94
304 : begin RFactor = 389; BFactor = 445; end // GR = 1.75, GB = 2.00
305 : begin RFactor = 383; BFactor = 452; end // GR = 1.75, GB = 2.06
306 : begin RFactor = 377; BFactor = 459; end // GR = 1.75, GB = 2.12
307 : begin RFactor = 372; BFactor = 466; end // GR = 1.75, GB = 2.19
308 : begin RFactor = 366; BFactor = 473; end // GR = 1.75, GB = 2.25
309 : begin RFactor = 361; BFactor = 479; end // GR = 1.75, GB = 2.31
310 : begin RFactor = 357; BFactor = 486; end // GR = 1.75, GB = 2.38
311 : begin RFactor = 352; BFactor = 492; end // GR = 1.75, GB = 2.44
312 : begin RFactor = 559; BFactor = 308; end // GR = 1.81, GB = 1.00
313 : begin RFactor = 543; BFactor = 317; end // GR = 1.81, GB = 1.06
314 : begin RFactor = 527; BFactor = 327; end // GR = 1.81, GB = 1.12
315 : begin RFactor = 513; BFactor = 336; end // GR = 1.81, GB = 1.19
316 : begin RFactor = 500; BFactor = 344; end // GR = 1.81, GB = 1.25
317 : begin RFactor = 488; BFactor = 353; end // GR = 1.81, GB = 1.31
318 : begin RFactor = 477; BFactor = 362; end // GR = 1.81, GB = 1.38
319 : begin RFactor = 467; BFactor = 370; end // GR = 1.81, GB = 1.44
320 : begin RFactor = 457; BFactor = 378; end // GR = 1.81, GB = 1.50
321 : begin RFactor = 447; BFactor = 386; end // GR = 1.81, GB = 1.56
322 : begin RFactor = 439; BFactor = 394; end // GR = 1.81, GB = 1.62
323 : begin RFactor = 431; BFactor = 401; end // GR = 1.81, GB = 1.69
324 : begin RFactor = 423; BFactor = 409; end // GR = 1.81, GB = 1.75
325 : begin RFactor = 415; BFactor = 416; end // GR = 1.81, GB = 1.81
326 : begin RFactor = 408; BFactor = 423; end // GR = 1.81, GB = 1.88
327 : begin RFactor = 402; BFactor = 431; end // GR = 1.81, GB = 1.94
328 : begin RFactor = 395; BFactor = 438; end // GR = 1.81, GB = 2.00
329 : begin RFactor = 389; BFactor = 444; end // GR = 1.81, GB = 2.06
330 : begin RFactor = 384; BFactor = 451; end // GR = 1.81, GB = 2.12
331 : begin RFactor = 378; BFactor = 458; end // GR = 1.81, GB = 2.19
332 : begin RFactor = 373; BFactor = 465; end // GR = 1.81, GB = 2.25
333 : begin RFactor = 368; BFactor = 471; end // GR = 1.81, GB = 2.31
334 : begin RFactor = 363; BFactor = 478; end // GR = 1.81, GB = 2.38
335 : begin RFactor = 358; BFactor = 484; end // GR = 1.81, GB = 2.44
336 : begin RFactor = 569; BFactor = 302; end // GR = 1.88, GB = 1.00
337 : begin RFactor = 552; BFactor = 312; end // GR = 1.88, GB = 1.06
338 : begin RFactor = 536; BFactor = 321; end // GR = 1.88, GB = 1.12
339 : begin RFactor = 522; BFactor = 330; end // GR = 1.88, GB = 1.19
340 : begin RFactor = 509; BFactor = 339; end // GR = 1.88, GB = 1.25
341 : begin RFactor = 497; BFactor = 347; end // GR = 1.88, GB = 1.31
342 : begin RFactor = 485; BFactor = 356; end // GR = 1.88, GB = 1.38
343 : begin RFactor = 474; BFactor = 364; end // GR = 1.88, GB = 1.44
344 : begin RFactor = 464; BFactor = 372; end // GR = 1.88, GB = 1.50
345 : begin RFactor = 455; BFactor = 379; end // GR = 1.88, GB = 1.56
346 : begin RFactor = 446; BFactor = 387; end // GR = 1.88, GB = 1.62
347 : begin RFactor = 438; BFactor = 395; end // GR = 1.88, GB = 1.69
348 : begin RFactor = 430; BFactor = 402; end // GR = 1.88, GB = 1.75
349 : begin RFactor = 422; BFactor = 409; end // GR = 1.88, GB = 1.81
350 : begin RFactor = 415; BFactor = 416; end // GR = 1.88, GB = 1.88
351 : begin RFactor = 409; BFactor = 423; end // GR = 1.88, GB = 1.94
352 : begin RFactor = 402; BFactor = 430; end // GR = 1.88, GB = 2.00
353 : begin RFactor = 396; BFactor = 437; end // GR = 1.88, GB = 2.06
354 : begin RFactor = 390; BFactor = 444; end // GR = 1.88, GB = 2.12
355 : begin RFactor = 384; BFactor = 450; end // GR = 1.88, GB = 2.19
356 : begin RFactor = 379; BFactor = 457; end // GR = 1.88, GB = 2.25
357 : begin RFactor = 374; BFactor = 463; end // GR = 1.88, GB = 2.31
358 : begin RFactor = 369; BFactor = 469; end // GR = 1.88, GB = 2.38
359 : begin RFactor = 364; BFactor = 476; end // GR = 1.88, GB = 2.44
360 : begin RFactor = 578; BFactor = 297; end // GR = 1.94, GB = 1.00
361 : begin RFactor = 561; BFactor = 307; end // GR = 1.94, GB = 1.06
362 : begin RFactor = 545; BFactor = 316; end // GR = 1.94, GB = 1.12
363 : begin RFactor = 531; BFactor = 325; end // GR = 1.94, GB = 1.19
364 : begin RFactor = 517; BFactor = 333; end // GR = 1.94, GB = 1.25
365 : begin RFactor = 505; BFactor = 342; end // GR = 1.94, GB = 1.31
366 : begin RFactor = 493; BFactor = 350; end // GR = 1.94, GB = 1.38
367 : begin RFactor = 482; BFactor = 358; end // GR = 1.94, GB = 1.44
368 : begin RFactor = 472; BFactor = 366; end // GR = 1.94, GB = 1.50
369 : begin RFactor = 462; BFactor = 373; end // GR = 1.94, GB = 1.56
370 : begin RFactor = 453; BFactor = 381; end // GR = 1.94, GB = 1.62
371 : begin RFactor = 445; BFactor = 388; end // GR = 1.94, GB = 1.69
372 : begin RFactor = 437; BFactor = 395; end // GR = 1.94, GB = 1.75
373 : begin RFactor = 429; BFactor = 403; end // GR = 1.94, GB = 1.81
374 : begin RFactor = 422; BFactor = 410; end // GR = 1.94, GB = 1.88
375 : begin RFactor = 415; BFactor = 416; end // GR = 1.94, GB = 1.94
376 : begin RFactor = 409; BFactor = 423; end // GR = 1.94, GB = 2.00
377 : begin RFactor = 402; BFactor = 430; end // GR = 1.94, GB = 2.06
378 : begin RFactor = 396; BFactor = 436; end // GR = 1.94, GB = 2.12
379 : begin RFactor = 391; BFactor = 443; end // GR = 1.94, GB = 2.19
380 : begin RFactor = 385; BFactor = 449; end // GR = 1.94, GB = 2.25
381 : begin RFactor = 380; BFactor = 456; end // GR = 1.94, GB = 2.31
382 : begin RFactor = 375; BFactor = 462; end // GR = 1.94, GB = 2.38
383 : begin RFactor = 370; BFactor = 468; end // GR = 1.94, GB = 2.44
384 : begin RFactor = 587; BFactor = 293; end // GR = 2.00, GB = 1.00
385 : begin RFactor = 570; BFactor = 302; end // GR = 2.00, GB = 1.06
386 : begin RFactor = 554; BFactor = 311; end // GR = 2.00, GB = 1.12
387 : begin RFactor = 539; BFactor = 319; end // GR = 2.00, GB = 1.19
388 : begin RFactor = 525; BFactor = 328; end // GR = 2.00, GB = 1.25
389 : begin RFactor = 513; BFactor = 336; end // GR = 2.00, GB = 1.31
390 : begin RFactor = 501; BFactor = 344; end // GR = 2.00, GB = 1.38
391 : begin RFactor = 490; BFactor = 352; end // GR = 2.00, GB = 1.44
392 : begin RFactor = 479; BFactor = 360; end // GR = 2.00, GB = 1.50
393 : begin RFactor = 470; BFactor = 367; end // GR = 2.00, GB = 1.56
394 : begin RFactor = 461; BFactor = 375; end // GR = 2.00, GB = 1.62
395 : begin RFactor = 452; BFactor = 382; end // GR = 2.00, GB = 1.69
396 : begin RFactor = 444; BFactor = 389; end // GR = 2.00, GB = 1.75
397 : begin RFactor = 436; BFactor = 396; end // GR = 2.00, GB = 1.81
398 : begin RFactor = 429; BFactor = 403; end // GR = 2.00, GB = 1.88
399 : begin RFactor = 422; BFactor = 410; end // GR = 2.00, GB = 1.94
400 : begin RFactor = 415; BFactor = 417; end // GR = 2.00, GB = 2.00
401 : begin RFactor = 409; BFactor = 423; end // GR = 2.00, GB = 2.06
402 : begin RFactor = 403; BFactor = 430; end // GR = 2.00, GB = 2.12
403 : begin RFactor = 397; BFactor = 436; end // GR = 2.00, GB = 2.19
404 : begin RFactor = 391; BFactor = 442; end // GR = 2.00, GB = 2.25
405 : begin RFactor = 386; BFactor = 448; end // GR = 2.00, GB = 2.31
406 : begin RFactor = 381; BFactor = 455; end // GR = 2.00, GB = 2.38
407 : begin RFactor = 376; BFactor = 461; end // GR = 2.00, GB = 2.44
408 : begin RFactor = 596; BFactor = 288; end // GR = 2.06, GB = 1.00
409 : begin RFactor = 578; BFactor = 297; end // GR = 2.06, GB = 1.06
410 : begin RFactor = 562; BFactor = 306; end // GR = 2.06, GB = 1.12
411 : begin RFactor = 547; BFactor = 315; end // GR = 2.06, GB = 1.19
412 : begin RFactor = 533; BFactor = 323; end // GR = 2.06, GB = 1.25
413 : begin RFactor = 520; BFactor = 331; end // GR = 2.06, GB = 1.31
414 : begin RFactor = 508; BFactor = 339; end // GR = 2.06, GB = 1.38
415 : begin RFactor = 497; BFactor = 347; end // GR = 2.06, GB = 1.44
416 : begin RFactor = 487; BFactor = 354; end // GR = 2.06, GB = 1.50
417 : begin RFactor = 477; BFactor = 362; end // GR = 2.06, GB = 1.56
418 : begin RFactor = 468; BFactor = 369; end // GR = 2.06, GB = 1.62
419 : begin RFactor = 459; BFactor = 376; end // GR = 2.06, GB = 1.69
420 : begin RFactor = 451; BFactor = 383; end // GR = 2.06, GB = 1.75
421 : begin RFactor = 443; BFactor = 390; end // GR = 2.06, GB = 1.81
422 : begin RFactor = 435; BFactor = 397; end // GR = 2.06, GB = 1.88
423 : begin RFactor = 428; BFactor = 404; end // GR = 2.06, GB = 1.94
424 : begin RFactor = 421; BFactor = 410; end // GR = 2.06, GB = 2.00
425 : begin RFactor = 415; BFactor = 417; end // GR = 2.06, GB = 2.06
426 : begin RFactor = 409; BFactor = 423; end // GR = 2.06, GB = 2.12
427 : begin RFactor = 403; BFactor = 429; end // GR = 2.06, GB = 2.19
428 : begin RFactor = 397; BFactor = 435; end // GR = 2.06, GB = 2.25
429 : begin RFactor = 392; BFactor = 442; end // GR = 2.06, GB = 2.31
430 : begin RFactor = 387; BFactor = 448; end // GR = 2.06, GB = 2.38
431 : begin RFactor = 382; BFactor = 454; end // GR = 2.06, GB = 2.44
432 : begin RFactor = 605; BFactor = 284; end // GR = 2.12, GB = 1.00
433 : begin RFactor = 587; BFactor = 293; end // GR = 2.12, GB = 1.06
434 : begin RFactor = 570; BFactor = 302; end // GR = 2.12, GB = 1.12
435 : begin RFactor = 555; BFactor = 310; end // GR = 2.12, GB = 1.19
436 : begin RFactor = 541; BFactor = 318; end // GR = 2.12, GB = 1.25
437 : begin RFactor = 528; BFactor = 326; end // GR = 2.12, GB = 1.31
438 : begin RFactor = 516; BFactor = 334; end // GR = 2.12, GB = 1.38
439 : begin RFactor = 505; BFactor = 342; end // GR = 2.12, GB = 1.44
440 : begin RFactor = 494; BFactor = 349; end // GR = 2.12, GB = 1.50
441 : begin RFactor = 484; BFactor = 356; end // GR = 2.12, GB = 1.56
442 : begin RFactor = 475; BFactor = 364; end // GR = 2.12, GB = 1.62
443 : begin RFactor = 466; BFactor = 371; end // GR = 2.12, GB = 1.69
444 : begin RFactor = 457; BFactor = 378; end // GR = 2.12, GB = 1.75
445 : begin RFactor = 449; BFactor = 384; end // GR = 2.12, GB = 1.81
446 : begin RFactor = 442; BFactor = 391; end // GR = 2.12, GB = 1.88
447 : begin RFactor = 435; BFactor = 398; end // GR = 2.12, GB = 1.94
448 : begin RFactor = 428; BFactor = 404; end // GR = 2.12, GB = 2.00
449 : begin RFactor = 421; BFactor = 410; end // GR = 2.12, GB = 2.06
450 : begin RFactor = 415; BFactor = 417; end // GR = 2.12, GB = 2.12
451 : begin RFactor = 409; BFactor = 423; end // GR = 2.12, GB = 2.19
452 : begin RFactor = 403; BFactor = 429; end // GR = 2.12, GB = 2.25
453 : begin RFactor = 398; BFactor = 435; end // GR = 2.12, GB = 2.31
454 : begin RFactor = 392; BFactor = 441; end // GR = 2.12, GB = 2.38
455 : begin RFactor = 387; BFactor = 447; end // GR = 2.12, GB = 2.44
456 : begin RFactor = 614; BFactor = 280; end // GR = 2.19, GB = 1.00
457 : begin RFactor = 595; BFactor = 289; end // GR = 2.19, GB = 1.06
458 : begin RFactor = 579; BFactor = 297; end // GR = 2.19, GB = 1.12
459 : begin RFactor = 563; BFactor = 305; end // GR = 2.19, GB = 1.19
460 : begin RFactor = 549; BFactor = 314; end // GR = 2.19, GB = 1.25
461 : begin RFactor = 536; BFactor = 321; end // GR = 2.19, GB = 1.31
462 : begin RFactor = 523; BFactor = 329; end // GR = 2.19, GB = 1.38
463 : begin RFactor = 512; BFactor = 337; end // GR = 2.19, GB = 1.44
464 : begin RFactor = 501; BFactor = 344; end // GR = 2.19, GB = 1.50
465 : begin RFactor = 491; BFactor = 351; end // GR = 2.19, GB = 1.56
466 : begin RFactor = 481; BFactor = 358; end // GR = 2.19, GB = 1.62
467 : begin RFactor = 472; BFactor = 365; end // GR = 2.19, GB = 1.69
468 : begin RFactor = 464; BFactor = 372; end // GR = 2.19, GB = 1.75
469 : begin RFactor = 456; BFactor = 379; end // GR = 2.19, GB = 1.81
470 : begin RFactor = 448; BFactor = 385; end // GR = 2.19, GB = 1.88
471 : begin RFactor = 441; BFactor = 392; end // GR = 2.19, GB = 1.94
472 : begin RFactor = 434; BFactor = 398; end // GR = 2.19, GB = 2.00
473 : begin RFactor = 427; BFactor = 405; end // GR = 2.19, GB = 2.06
474 : begin RFactor = 421; BFactor = 411; end // GR = 2.19, GB = 2.12
475 : begin RFactor = 415; BFactor = 417; end // GR = 2.19, GB = 2.19
476 : begin RFactor = 409; BFactor = 423; end // GR = 2.19, GB = 2.25
477 : begin RFactor = 403; BFactor = 429; end // GR = 2.19, GB = 2.31
478 : begin RFactor = 398; BFactor = 435; end // GR = 2.19, GB = 2.38
479 : begin RFactor = 393; BFactor = 440; end // GR = 2.19, GB = 2.44
480 : begin RFactor = 622; BFactor = 276; end // GR = 2.25, GB = 1.00
481 : begin RFactor = 604; BFactor = 285; end // GR = 2.25, GB = 1.06
482 : begin RFactor = 587; BFactor = 293; end // GR = 2.25, GB = 1.12
483 : begin RFactor = 571; BFactor = 301; end // GR = 2.25, GB = 1.19
484 : begin RFactor = 557; BFactor = 309; end // GR = 2.25, GB = 1.25
485 : begin RFactor = 543; BFactor = 317; end // GR = 2.25, GB = 1.31
486 : begin RFactor = 531; BFactor = 325; end // GR = 2.25, GB = 1.38
487 : begin RFactor = 519; BFactor = 332; end // GR = 2.25, GB = 1.44
488 : begin RFactor = 508; BFactor = 339; end // GR = 2.25, GB = 1.50
489 : begin RFactor = 498; BFactor = 346; end // GR = 2.25, GB = 1.56
490 : begin RFactor = 488; BFactor = 353; end // GR = 2.25, GB = 1.62
491 : begin RFactor = 479; BFactor = 360; end // GR = 2.25, GB = 1.69
492 : begin RFactor = 470; BFactor = 367; end // GR = 2.25, GB = 1.75
493 : begin RFactor = 462; BFactor = 373; end // GR = 2.25, GB = 1.81
494 : begin RFactor = 454; BFactor = 380; end // GR = 2.25, GB = 1.88
495 : begin RFactor = 447; BFactor = 386; end // GR = 2.25, GB = 1.94
496 : begin RFactor = 440; BFactor = 393; end // GR = 2.25, GB = 2.00
497 : begin RFactor = 433; BFactor = 399; end // GR = 2.25, GB = 2.06
498 : begin RFactor = 427; BFactor = 405; end // GR = 2.25, GB = 2.12
499 : begin RFactor = 421; BFactor = 411; end // GR = 2.25, GB = 2.19
500 : begin RFactor = 415; BFactor = 417; end // GR = 2.25, GB = 2.25
501 : begin RFactor = 409; BFactor = 423; end // GR = 2.25, GB = 2.31
502 : begin RFactor = 404; BFactor = 429; end // GR = 2.25, GB = 2.38
503 : begin RFactor = 398; BFactor = 434; end // GR = 2.25, GB = 2.44
504 : begin RFactor = 631; BFactor = 272; end // GR = 2.31, GB = 1.00
505 : begin RFactor = 612; BFactor = 281; end // GR = 2.31, GB = 1.06
506 : begin RFactor = 595; BFactor = 289; end // GR = 2.31, GB = 1.12
507 : begin RFactor = 579; BFactor = 297; end // GR = 2.31, GB = 1.19
508 : begin RFactor = 564; BFactor = 305; end // GR = 2.31, GB = 1.25
509 : begin RFactor = 551; BFactor = 313; end // GR = 2.31, GB = 1.31
510 : begin RFactor = 538; BFactor = 320; end // GR = 2.31, GB = 1.38
511 : begin RFactor = 526; BFactor = 327; end // GR = 2.31, GB = 1.44
512 : begin RFactor = 515; BFactor = 335; end // GR = 2.31, GB = 1.50
513 : begin RFactor = 505; BFactor = 342; end // GR = 2.31, GB = 1.56
514 : begin RFactor = 495; BFactor = 348; end // GR = 2.31, GB = 1.62
515 : begin RFactor = 485; BFactor = 355; end // GR = 2.31, GB = 1.69
516 : begin RFactor = 477; BFactor = 362; end // GR = 2.31, GB = 1.75
517 : begin RFactor = 468; BFactor = 368; end // GR = 2.31, GB = 1.81
518 : begin RFactor = 461; BFactor = 375; end // GR = 2.31, GB = 1.88
519 : begin RFactor = 453; BFactor = 381; end // GR = 2.31, GB = 1.94
520 : begin RFactor = 446; BFactor = 387; end // GR = 2.31, GB = 2.00
521 : begin RFactor = 439; BFactor = 393; end // GR = 2.31, GB = 2.06
522 : begin RFactor = 433; BFactor = 399; end // GR = 2.31, GB = 2.12
523 : begin RFactor = 426; BFactor = 405; end // GR = 2.31, GB = 2.19
524 : begin RFactor = 420; BFactor = 411; end // GR = 2.31, GB = 2.25
525 : begin RFactor = 415; BFactor = 417; end // GR = 2.31, GB = 2.31
526 : begin RFactor = 409; BFactor = 423; end // GR = 2.31, GB = 2.38
527 : begin RFactor = 404; BFactor = 428; end // GR = 2.31, GB = 2.44
528 : begin RFactor = 639; BFactor = 269; end // GR = 2.38, GB = 1.00
529 : begin RFactor = 620; BFactor = 277; end // GR = 2.38, GB = 1.06
530 : begin RFactor = 603; BFactor = 285; end // GR = 2.38, GB = 1.12
531 : begin RFactor = 586; BFactor = 293; end // GR = 2.38, GB = 1.19
532 : begin RFactor = 572; BFactor = 301; end // GR = 2.38, GB = 1.25
533 : begin RFactor = 558; BFactor = 308; end // GR = 2.38, GB = 1.31
534 : begin RFactor = 545; BFactor = 316; end // GR = 2.38, GB = 1.38
535 : begin RFactor = 533; BFactor = 323; end // GR = 2.38, GB = 1.44
536 : begin RFactor = 522; BFactor = 330; end // GR = 2.38, GB = 1.50
537 : begin RFactor = 511; BFactor = 337; end // GR = 2.38, GB = 1.56
538 : begin RFactor = 501; BFactor = 344; end // GR = 2.38, GB = 1.62
539 : begin RFactor = 492; BFactor = 351; end // GR = 2.38, GB = 1.69
540 : begin RFactor = 483; BFactor = 357; end // GR = 2.38, GB = 1.75
541 : begin RFactor = 475; BFactor = 364; end // GR = 2.38, GB = 1.81
542 : begin RFactor = 467; BFactor = 370; end // GR = 2.38, GB = 1.88
543 : begin RFactor = 459; BFactor = 376; end // GR = 2.38, GB = 1.94
544 : begin RFactor = 452; BFactor = 382; end // GR = 2.38, GB = 2.00
545 : begin RFactor = 445; BFactor = 388; end // GR = 2.38, GB = 2.06
546 : begin RFactor = 438; BFactor = 394; end // GR = 2.38, GB = 2.12
547 : begin RFactor = 432; BFactor = 400; end // GR = 2.38, GB = 2.19
548 : begin RFactor = 426; BFactor = 406; end // GR = 2.38, GB = 2.25
549 : begin RFactor = 420; BFactor = 411; end // GR = 2.38, GB = 2.31
550 : begin RFactor = 415; BFactor = 417; end // GR = 2.38, GB = 2.38
551 : begin RFactor = 409; BFactor = 423; end // GR = 2.38, GB = 2.44
552 : begin RFactor = 647; BFactor = 265; end // GR = 2.44, GB = 1.00
553 : begin RFactor = 628; BFactor = 273; end // GR = 2.44, GB = 1.06
554 : begin RFactor = 610; BFactor = 281; end // GR = 2.44, GB = 1.12
555 : begin RFactor = 594; BFactor = 289; end // GR = 2.44, GB = 1.19
556 : begin RFactor = 579; BFactor = 297; end // GR = 2.44, GB = 1.25
557 : begin RFactor = 565; BFactor = 304; end // GR = 2.44, GB = 1.31
558 : begin RFactor = 552; BFactor = 312; end // GR = 2.44, GB = 1.38
559 : begin RFactor = 540; BFactor = 319; end // GR = 2.44, GB = 1.44
560 : begin RFactor = 528; BFactor = 326; end // GR = 2.44, GB = 1.50
561 : begin RFactor = 518; BFactor = 333; end // GR = 2.44, GB = 1.56
562 : begin RFactor = 508; BFactor = 339; end // GR = 2.44, GB = 1.62
563 : begin RFactor = 498; BFactor = 346; end // GR = 2.44, GB = 1.69
564 : begin RFactor = 489; BFactor = 352; end // GR = 2.44, GB = 1.75
565 : begin RFactor = 481; BFactor = 359; end // GR = 2.44, GB = 1.81
566 : begin RFactor = 473; BFactor = 365; end // GR = 2.44, GB = 1.88
567 : begin RFactor = 465; BFactor = 371; end // GR = 2.44, GB = 1.94
568 : begin RFactor = 458; BFactor = 377; end // GR = 2.44, GB = 2.00
569 : begin RFactor = 451; BFactor = 383; end // GR = 2.44, GB = 2.06
570 : begin RFactor = 444; BFactor = 389; end // GR = 2.44, GB = 2.12
571 : begin RFactor = 438; BFactor = 395; end // GR = 2.44, GB = 2.19
572 : begin RFactor = 431; BFactor = 401; end // GR = 2.44, GB = 2.25
573 : begin RFactor = 426; BFactor = 406; end // GR = 2.44, GB = 2.31
574 : begin RFactor = 420; BFactor = 412; end // GR = 2.44, GB = 2.38
575 : begin RFactor = 414; BFactor = 417; end // GR = 2.44, GB = 2.44
endcase
end
endtask
function[ `size_int - 1 : 0 ]LUTPow033( input[ `size_int - 1 : 0 ]Index );
begin
case( Index )
0 : LUTPow033 = 0;
1 : LUTPow033 = 256;
2 : LUTPow033 = 322;
3 : LUTPow033 = 369;
4 : LUTPow033 = 406;
5 : LUTPow033 = 437;
6 : LUTPow033 = 465;
7 : LUTPow033 = 489;
8 : LUTPow033 = 511;
9 : LUTPow033 = 532;
10 : LUTPow033 = 551;
11 : LUTPow033 = 569;
12 : LUTPow033 = 586;
13 : LUTPow033 = 601;
14 : LUTPow033 = 616;
15 : LUTPow033 = 631;
16 : LUTPow033 = 645;
17 : LUTPow033 = 658;
18 : LUTPow033 = 670;
19 : LUTPow033 = 683;
20 : LUTPow033 = 694;
21 : LUTPow033 = 706;
22 : LUTPow033 = 717;
23 : LUTPow033 = 728;
24 : LUTPow033 = 738;
25 : LUTPow033 = 748;
26 : LUTPow033 = 758;
27 : LUTPow033 = 767;
28 : LUTPow033 = 777;
29 : LUTPow033 = 786;
30 : LUTPow033 = 795;
31 : LUTPow033 = 804;
32 : LUTPow033 = 812;
33 : LUTPow033 = 821;
34 : LUTPow033 = 829;
35 : LUTPow033 = 837;
36 : LUTPow033 = 845;
37 : LUTPow033 = 853;
38 : LUTPow033 = 860;
39 : LUTPow033 = 868;
40 : LUTPow033 = 875;
41 : LUTPow033 = 882;
42 : LUTPow033 = 889;
43 : LUTPow033 = 896;
44 : LUTPow033 = 903;
45 : LUTPow033 = 910;
46 : LUTPow033 = 917;
47 : LUTPow033 = 923;
48 : LUTPow033 = 930;
49 : LUTPow033 = 936;
50 : LUTPow033 = 943;
51 : LUTPow033 = 949;
52 : LUTPow033 = 955;
53 : LUTPow033 = 961;
54 : LUTPow033 = 967;
55 : LUTPow033 = 973;
56 : LUTPow033 = 979;
57 : LUTPow033 = 985;
58 : LUTPow033 = 990;
59 : LUTPow033 = 996;
60 : LUTPow033 = 1002;
61 : LUTPow033 = 1007;
62 : LUTPow033 = 1013;
63 : LUTPow033 = 1018;
64 : LUTPow033 = 1023;
65 : LUTPow033 = 1029;
66 : LUTPow033 = 1034;
67 : LUTPow033 = 1039;
68 : LUTPow033 = 1044;
69 : LUTPow033 = 1050;
70 : LUTPow033 = 1055;
71 : LUTPow033 = 1060;
72 : LUTPow033 = 1065;
73 : LUTPow033 = 1069;
74 : LUTPow033 = 1074;
75 : LUTPow033 = 1079;
76 : LUTPow033 = 1084;
77 : LUTPow033 = 1089;
78 : LUTPow033 = 1093;
79 : LUTPow033 = 1098;
80 : LUTPow033 = 1103;
81 : LUTPow033 = 1107;
82 : LUTPow033 = 1112;
83 : LUTPow033 = 1116;
84 : LUTPow033 = 1121;
85 : LUTPow033 = 1125;
86 : LUTPow033 = 1129;
87 : LUTPow033 = 1134;
88 : LUTPow033 = 1138;
89 : LUTPow033 = 1142;
90 : LUTPow033 = 1147;
91 : LUTPow033 = 1151;
92 : LUTPow033 = 1155;
93 : LUTPow033 = 1159;
94 : LUTPow033 = 1163;
95 : LUTPow033 = 1168;
96 : LUTPow033 = 1172;
97 : LUTPow033 = 1176;
98 : LUTPow033 = 1180;
99 : LUTPow033 = 1184;
100 : LUTPow033 = 1188;
101 : LUTPow033 = 1192;
102 : LUTPow033 = 1196;
103 : LUTPow033 = 1200;
104 : LUTPow033 = 1203;
105 : LUTPow033 = 1207;
106 : LUTPow033 = 1211;
107 : LUTPow033 = 1215;
108 : LUTPow033 = 1219;
109 : LUTPow033 = 1222;
110 : LUTPow033 = 1226;
111 : LUTPow033 = 1230;
112 : LUTPow033 = 1233;
113 : LUTPow033 = 1237;
114 : LUTPow033 = 1241;
115 : LUTPow033 = 1244;
116 : LUTPow033 = 1248;
117 : LUTPow033 = 1252;
118 : LUTPow033 = 1255;
119 : LUTPow033 = 1259;
120 : LUTPow033 = 1262;
121 : LUTPow033 = 1266;
122 : LUTPow033 = 1269;
123 : LUTPow033 = 1273;
124 : LUTPow033 = 1276;
125 : LUTPow033 = 1279;
126 : LUTPow033 = 1283;
127 : LUTPow033 = 1286;
128 : LUTPow033 = 1290;
129 : LUTPow033 = 1293;
130 : LUTPow033 = 1296;
131 : LUTPow033 = 1300;
132 : LUTPow033 = 1303;
133 : LUTPow033 = 1306;
134 : LUTPow033 = 1310;
135 : LUTPow033 = 1313;
136 : LUTPow033 = 1316;
137 : LUTPow033 = 1319;
138 : LUTPow033 = 1322;
139 : LUTPow033 = 1326;
140 : LUTPow033 = 1329;
141 : LUTPow033 = 1332;
142 : LUTPow033 = 1335;
143 : LUTPow033 = 1338;
144 : LUTPow033 = 1341;
145 : LUTPow033 = 1344;
146 : LUTPow033 = 1348;
147 : LUTPow033 = 1351;
148 : LUTPow033 = 1354;
149 : LUTPow033 = 1357;
150 : LUTPow033 = 1360;
151 : LUTPow033 = 1363;
152 : LUTPow033 = 1366;
153 : LUTPow033 = 1369;
154 : LUTPow033 = 1372;
155 : LUTPow033 = 1375;
156 : LUTPow033 = 1378;
157 : LUTPow033 = 1381;
158 : LUTPow033 = 1383;
159 : LUTPow033 = 1386;
160 : LUTPow033 = 1389;
161 : LUTPow033 = 1392;
162 : LUTPow033 = 1395;
163 : LUTPow033 = 1398;
164 : LUTPow033 = 1401;
165 : LUTPow033 = 1404;
166 : LUTPow033 = 1406;
167 : LUTPow033 = 1409;
168 : LUTPow033 = 1412;
169 : LUTPow033 = 1415;
170 : LUTPow033 = 1418;
171 : LUTPow033 = 1420;
172 : LUTPow033 = 1423;
173 : LUTPow033 = 1426;
174 : LUTPow033 = 1429;
175 : LUTPow033 = 1431;
176 : LUTPow033 = 1434;
177 : LUTPow033 = 1437;
178 : LUTPow033 = 1440;
179 : LUTPow033 = 1442;
180 : LUTPow033 = 1445;
181 : LUTPow033 = 1448;
182 : LUTPow033 = 1450;
183 : LUTPow033 = 1453;
184 : LUTPow033 = 1456;
185 : LUTPow033 = 1458;
186 : LUTPow033 = 1461;
187 : LUTPow033 = 1463;
188 : LUTPow033 = 1466;
189 : LUTPow033 = 1469;
190 : LUTPow033 = 1471;
191 : LUTPow033 = 1474;
192 : LUTPow033 = 1476;
193 : LUTPow033 = 1479;
194 : LUTPow033 = 1481;
195 : LUTPow033 = 1484;
196 : LUTPow033 = 1487;
197 : LUTPow033 = 1489;
198 : LUTPow033 = 1492;
199 : LUTPow033 = 1494;
200 : LUTPow033 = 1497;
201 : LUTPow033 = 1499;
202 : LUTPow033 = 1502;
203 : LUTPow033 = 1504;
204 : LUTPow033 = 1507;
205 : LUTPow033 = 1509;
206 : LUTPow033 = 1511;
207 : LUTPow033 = 1514;
208 : LUTPow033 = 1516;
209 : LUTPow033 = 1519;
210 : LUTPow033 = 1521;
211 : LUTPow033 = 1524;
212 : LUTPow033 = 1526;
213 : LUTPow033 = 1528;
214 : LUTPow033 = 1531;
215 : LUTPow033 = 1533;
216 : LUTPow033 = 1535;
217 : LUTPow033 = 1538;
218 : LUTPow033 = 1540;
219 : LUTPow033 = 1543;
220 : LUTPow033 = 1545;
221 : LUTPow033 = 1547;
222 : LUTPow033 = 1550;
223 : LUTPow033 = 1552;
224 : LUTPow033 = 1554;
225 : LUTPow033 = 1557;
226 : LUTPow033 = 1559;
227 : LUTPow033 = 1561;
228 : LUTPow033 = 1563;
229 : LUTPow033 = 1566;
230 : LUTPow033 = 1568;
231 : LUTPow033 = 1570;
232 : LUTPow033 = 1573;
233 : LUTPow033 = 1575;
234 : LUTPow033 = 1577;
235 : LUTPow033 = 1579;
236 : LUTPow033 = 1582;
237 : LUTPow033 = 1584;
238 : LUTPow033 = 1586;
239 : LUTPow033 = 1588;
240 : LUTPow033 = 1590;
241 : LUTPow033 = 1593;
242 : LUTPow033 = 1595;
243 : LUTPow033 = 1597;
244 : LUTPow033 = 1599;
245 : LUTPow033 = 1601;
246 : LUTPow033 = 1604;
247 : LUTPow033 = 1606;
248 : LUTPow033 = 1608;
249 : LUTPow033 = 1610;
250 : LUTPow033 = 1612;
251 : LUTPow033 = 1614;
252 : LUTPow033 = 1616;
253 : LUTPow033 = 1619;
254 : LUTPow033 = 1621;
255 : LUTPow033 = 1623;
256 : LUTPow033 = 1625;
endcase
end
endfunction
function[ `size_int - 1 : 0 ]LUTPow045( input[ `size_int - 1 : 0 ]source );
begin
case( source )
// ( ( RGB / 256 ) ^ 0.45 ) * 256 * 256
0 : LUTPow045 = 0;
1 : LUTPow045 = 5404;
2 : LUTPow045 = 7383;
3 : LUTPow045 = 8860;
4 : LUTPow045 = 10085;
5 : LUTPow045 = 11150;
6 : LUTPow045 = 12104;
7 : LUTPow045 = 12973;
8 : LUTPow045 = 13777;
9 : LUTPow045 = 14527;
10 : LUTPow045 = 15232;
11 : LUTPow045 = 15900;
12 : LUTPow045 = 16534;
13 : LUTPow045 = 17141;
14 : LUTPow045 = 17722;
15 : LUTPow045 = 18281;
16 : LUTPow045 = 18820;
17 : LUTPow045 = 19340;
18 : LUTPow045 = 19844;
19 : LUTPow045 = 20333;
20 : LUTPow045 = 20808;
21 : LUTPow045 = 21270;
22 : LUTPow045 = 21720;
23 : LUTPow045 = 22158;
24 : LUTPow045 = 22587;
25 : LUTPow045 = 23006;
26 : LUTPow045 = 23415;
27 : LUTPow045 = 23816;
28 : LUTPow045 = 24209;
29 : LUTPow045 = 24595;
30 : LUTPow045 = 24973;
31 : LUTPow045 = 25344;
32 : LUTPow045 = 25709;
33 : LUTPow045 = 26067;
34 : LUTPow045 = 26420;
35 : LUTPow045 = 26767;
36 : LUTPow045 = 27108;
37 : LUTPow045 = 27444;
38 : LUTPow045 = 27776;
39 : LUTPow045 = 28102;
40 : LUTPow045 = 28424;
41 : LUTPow045 = 28742;
42 : LUTPow045 = 29055;
43 : LUTPow045 = 29365;
44 : LUTPow045 = 29670;
45 : LUTPow045 = 29972;
46 : LUTPow045 = 30270;
47 : LUTPow045 = 30564;
48 : LUTPow045 = 30855;
49 : LUTPow045 = 31142;
50 : LUTPow045 = 31427;
51 : LUTPow045 = 31708;
52 : LUTPow045 = 31986;
53 : LUTPow045 = 32262;
54 : LUTPow045 = 32534;
55 : LUTPow045 = 32804;
56 : LUTPow045 = 33071;
57 : LUTPow045 = 33336;
58 : LUTPow045 = 33598;
59 : LUTPow045 = 33857;
60 : LUTPow045 = 34114;
61 : LUTPow045 = 34369;
62 : LUTPow045 = 34621;
63 : LUTPow045 = 34871;
64 : LUTPow045 = 35119;
65 : LUTPow045 = 35365;
66 : LUTPow045 = 35609;
67 : LUTPow045 = 35851;
68 : LUTPow045 = 36091;
69 : LUTPow045 = 36329;
70 : LUTPow045 = 36565;
71 : LUTPow045 = 36799;
72 : LUTPow045 = 37031;
73 : LUTPow045 = 37262;
74 : LUTPow045 = 37490;
75 : LUTPow045 = 37718;
76 : LUTPow045 = 37943;
77 : LUTPow045 = 38167;
78 : LUTPow045 = 38389;
79 : LUTPow045 = 38610;
80 : LUTPow045 = 38829;
81 : LUTPow045 = 39047;
82 : LUTPow045 = 39263;
83 : LUTPow045 = 39478;
84 : LUTPow045 = 39691;
85 : LUTPow045 = 39903;
86 : LUTPow045 = 40114;
87 : LUTPow045 = 40323;
88 : LUTPow045 = 40531;
89 : LUTPow045 = 40737;
90 : LUTPow045 = 40943;
91 : LUTPow045 = 41147;
92 : LUTPow045 = 41350;
93 : LUTPow045 = 41551;
94 : LUTPow045 = 41752;
95 : LUTPow045 = 41951;
96 : LUTPow045 = 42149;
97 : LUTPow045 = 42346;
98 : LUTPow045 = 42542;
99 : LUTPow045 = 42737;
100 : LUTPow045 = 42931;
101 : LUTPow045 = 43123;
102 : LUTPow045 = 43315;
103 : LUTPow045 = 43505;
104 : LUTPow045 = 43695;
105 : LUTPow045 = 43884;
106 : LUTPow045 = 44071;
107 : LUTPow045 = 44258;
108 : LUTPow045 = 44443;
109 : LUTPow045 = 44628;
110 : LUTPow045 = 44812;
111 : LUTPow045 = 44995;
112 : LUTPow045 = 45177;
113 : LUTPow045 = 45358;
114 : LUTPow045 = 45538;
115 : LUTPow045 = 45717;
116 : LUTPow045 = 45896;
117 : LUTPow045 = 46073;
118 : LUTPow045 = 46250;
119 : LUTPow045 = 46426;
120 : LUTPow045 = 46601;
121 : LUTPow045 = 46776;
122 : LUTPow045 = 46949;
123 : LUTPow045 = 47122;
124 : LUTPow045 = 47294;
125 : LUTPow045 = 47465;
126 : LUTPow045 = 47636;
127 : LUTPow045 = 47806;
128 : LUTPow045 = 47975;
129 : LUTPow045 = 48143;
130 : LUTPow045 = 48311;
131 : LUTPow045 = 48477;
132 : LUTPow045 = 48644;
133 : LUTPow045 = 48809;
134 : LUTPow045 = 48974;
135 : LUTPow045 = 49138;
136 : LUTPow045 = 49301;
137 : LUTPow045 = 49464;
138 : LUTPow045 = 49626;
139 : LUTPow045 = 49788;
140 : LUTPow045 = 49949;
141 : LUTPow045 = 50109;
142 : LUTPow045 = 50269;
143 : LUTPow045 = 50428;
144 : LUTPow045 = 50586;
145 : LUTPow045 = 50744;
146 : LUTPow045 = 50901;
147 : LUTPow045 = 51058;
148 : LUTPow045 = 51214;
149 : LUTPow045 = 51369;
150 : LUTPow045 = 51524;
151 : LUTPow045 = 51678;
152 : LUTPow045 = 51832;
153 : LUTPow045 = 51985;
154 : LUTPow045 = 52138;
155 : LUTPow045 = 52290;
156 : LUTPow045 = 52441;
157 : LUTPow045 = 52592;
158 : LUTPow045 = 52743;
159 : LUTPow045 = 52893;
160 : LUTPow045 = 53042;
161 : LUTPow045 = 53191;
162 : LUTPow045 = 53340;
163 : LUTPow045 = 53488;
164 : LUTPow045 = 53635;
165 : LUTPow045 = 53782;
166 : LUTPow045 = 53928;
167 : LUTPow045 = 54074;
168 : LUTPow045 = 54220;
169 : LUTPow045 = 54365;
170 : LUTPow045 = 54509;
171 : LUTPow045 = 54653;
172 : LUTPow045 = 54797;
173 : LUTPow045 = 54940;
174 : LUTPow045 = 55083;
175 : LUTPow045 = 55225;
176 : LUTPow045 = 55367;
177 : LUTPow045 = 55508;
178 : LUTPow045 = 55649;
179 : LUTPow045 = 55789;
180 : LUTPow045 = 55929;
181 : LUTPow045 = 56069;
182 : LUTPow045 = 56208;
183 : LUTPow045 = 56347;
184 : LUTPow045 = 56485;
185 : LUTPow045 = 56623;
186 : LUTPow045 = 56761;
187 : LUTPow045 = 56898;
188 : LUTPow045 = 57035;
189 : LUTPow045 = 57171;
190 : LUTPow045 = 57307;
191 : LUTPow045 = 57442;
192 : LUTPow045 = 57578;
193 : LUTPow045 = 57712;
194 : LUTPow045 = 57847;
195 : LUTPow045 = 57981;
196 : LUTPow045 = 58114;
197 : LUTPow045 = 58248;
198 : LUTPow045 = 58380;
199 : LUTPow045 = 58513;
200 : LUTPow045 = 58645;
201 : LUTPow045 = 58777;
202 : LUTPow045 = 58908;
203 : LUTPow045 = 59039;
204 : LUTPow045 = 59170;
205 : LUTPow045 = 59300;
206 : LUTPow045 = 59430;
207 : LUTPow045 = 59560;
208 : LUTPow045 = 59689;
209 : LUTPow045 = 59818;
210 : LUTPow045 = 59947;
211 : LUTPow045 = 60075;
212 : LUTPow045 = 60203;
213 : LUTPow045 = 60331;
214 : LUTPow045 = 60458;
215 : LUTPow045 = 60585;
216 : LUTPow045 = 60712;
217 : LUTPow045 = 60838;
218 : LUTPow045 = 60964;
219 : LUTPow045 = 61090;
220 : LUTPow045 = 61215;
221 : LUTPow045 = 61340;
222 : LUTPow045 = 61465;
223 : LUTPow045 = 61589;
224 : LUTPow045 = 61713;
225 : LUTPow045 = 61837;
226 : LUTPow045 = 61961;
227 : LUTPow045 = 62084;
228 : LUTPow045 = 62207;
229 : LUTPow045 = 62330;
230 : LUTPow045 = 62452;
231 : LUTPow045 = 62574;
232 : LUTPow045 = 62696;
233 : LUTPow045 = 62817;
234 : LUTPow045 = 62938;
235 : LUTPow045 = 63059;
236 : LUTPow045 = 63180;
237 : LUTPow045 = 63300;
238 : LUTPow045 = 63420;
239 : LUTPow045 = 63540;
240 : LUTPow045 = 63660;
241 : LUTPow045 = 63779;
242 : LUTPow045 = 63898;
243 : LUTPow045 = 64016;
244 : LUTPow045 = 64135;
245 : LUTPow045 = 64253;
246 : LUTPow045 = 64371;
247 : LUTPow045 = 64488;
248 : LUTPow045 = 64606;
249 : LUTPow045 = 64723;
250 : LUTPow045 = 64840;
251 : LUTPow045 = 64956;
252 : LUTPow045 = 65073;
253 : LUTPow045 = 65189;
254 : LUTPow045 = 65305;
255 : LUTPow045 = 65420;
endcase
end
endfunction
endmodule
module ColorImageProcess_testbench;
// Signal declaration
reg Clock;
reg Reset;
reg[ `size_char - 1 : 0 ]R;
reg[ `size_char - 1 : 0 ]G;
reg[ `size_char - 1 : 0 ]B;
wire[ `size_char - 1 : 0 ]R_out;
wire[ `size_char - 1 : 0 ]G_out;
wire[ `size_char - 1 : 0 ]B_out;
reg[ `size_char - 1 : 0 ]RBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]GBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]BBlock[ 0 : `SumPixel - 1 ];
integer i;
integer RFile;
integer GFile;
integer BFile;
ColorImageProcess ColorImageProcess_test
(
Clock,
Reset,
R,
G,
B,
R_out,
G_out,
B_out
);
initial
begin
#2
begin
// open test data file
$readmemh( "data/IM000565_RAW_20x15R.dat", RBlock );
$readmemh( "data/IM000565_RAW_20x15G.dat", GBlock );
$readmemh( "data/IM000565_RAW_20x15B.dat", BBlock );
/*
$readmemh( "data/IM000565_RAW_320x240R.dat", RBlock );
$readmemh( "data/IM000565_RAW_320x240G.dat", GBlock );
$readmemh( "data/IM000565_RAW_320x240B.dat", BBlock );
*/
/*
$readmemh( "data/IM000565_RAW_640x480R.dat", RBlock );
$readmemh( "data/IM000565_RAW_640x480G.dat", GBlock );
$readmemh( "data/IM000565_RAW_640x480B.dat", BBlock );
*/
/*
$readmemh( "data/IM000565_RAW_480x360R.dat", RBlock );
$readmemh( "data/IM000565_RAW_480x360G.dat", GBlock );
$readmemh( "data/IM000565_RAW_480x360B.dat", BBlock );
*/
/*
$readmemh( "data/IM000565_RAW_160x120R.dat", RBlock );
$readmemh( "data/IM000565_RAW_160x120G.dat", GBlock );
$readmemh( "data/IM000565_RAW_160x120B.dat", BBlock );
*/
/*
$readmemh( "data/IM000565_RAW_120x90R.dat", RBlock );
$readmemh( "data/IM000565_RAW_120x90G.dat", GBlock );
$readmemh( "data/IM000565_RAW_120x90B.dat", BBlock );
*/
/*
$readmemh( "data/IM000565_RAW_100x75R.dat", RBlock );
$readmemh( "data/IM000565_RAW_100x75G.dat", GBlock );
$readmemh( "data/IM000565_RAW_100x75B.dat", BBlock );
*/
/*
$readmemh( "data/IM000565_RAW_40x30R.dat", RBlock );
$readmemh( "data/IM000565_RAW_40x30G.dat", GBlock );
$readmemh( "data/IM000565_RAW_40x30B.dat", BBlock );
*/
/*
$readmemh( "data/IM000565_RAW_80x60R.dat", RBlock );
$readmemh( "data/IM000565_RAW_80x60G.dat", GBlock );
$readmemh( "data/IM000565_RAW_80x60B.dat", BBlock );
*/
end
#2 Reset = 1'b1;
// Apply Stimulus
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
// initialization, start to read data into buffer
Reset = 1'b0;
R = RBlock[ i ];
G = GBlock[ i ];
B = BBlock[ i ];
end
end
#2
begin
RFile = $fopen( "data/R.dat" );
GFile = $fopen( "data/G.dat" );
BFile = $fopen( "data/B.dat" );
end
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
// display information on the screen
//$display( "R = %d, G = %d, B = %d\t\tR = %d, G = %d, B = %d",
// RBlock[ i ], GBlock[ i ], BBlock[ i ], R_out, G_out, B_out );
if( i % 16 == 0 )
begin
$fwrite( RFile, "\n" );
$fwrite( GFile, "\n" );
$fwrite( BFile, "\n" );
end
$fwrite( RFile, "%X ", R_out );
$fwrite( GFile, "%X ", G_out );
$fwrite( BFile, "%X ", B_out );
end
end
$fclose( RFile );
$fclose( GFile );
$fclose( BFile );
#100000 $stop;
#100000 $finish;
end
initial Clock = 0;
always #1 Clock = ~Clock; //Toggle Clock
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_4_V
`define SKY130_FD_SC_LS__NOR2B_4_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2b_4 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2b_4 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_4_V
|